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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
d8d55ac0 | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
b3a796bc | 4 | Free Software Foundation, Inc. |
cce8749e | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 6 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 8 | |
4f448245 | 9 | This file is part of GCC. |
cce8749e | 10 | |
4f448245 NC |
11 | GCC is free software; you can redistribute it and/or modify it |
12 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 13 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 14 | option) any later version. |
cce8749e | 15 | |
4f448245 NC |
16 | GCC is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
cce8749e | 20 | |
4f448245 | 21 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
f676971a | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
cce8749e CH |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
cce8749e CH |
36 | #include "output.h" |
37 | #include "insn-attr.h" | |
38 | #include "flags.h" | |
af48348a | 39 | #include "reload.h" |
49ad7cfa | 40 | #include "function.h" |
bee06f3d | 41 | #include "expr.h" |
e78d8e51 | 42 | #include "optabs.h" |
718f9c0f | 43 | #include "diagnostic-core.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
390b17c2 | 46 | #include "cgraph.h" |
92a432f4 | 47 | #include "ggc.h" |
d5b7b3ae | 48 | #include "except.h" |
39dabefd | 49 | #include "c-family/c-pragma.h" /* ??? */ |
7b8b8ade | 50 | #include "integrate.h" |
c27ba912 | 51 | #include "tm_p.h" |
672a6f42 NB |
52 | #include "target.h" |
53 | #include "target-def.h" | |
980e61bb | 54 | #include "debug.h" |
6e34d3a3 | 55 | #include "langhooks.h" |
6fb5fa3c | 56 | #include "df.h" |
0fd8c3ad | 57 | #include "intl.h" |
353a58f7 | 58 | #include "libfuncs.h" |
ec3728ad | 59 | #include "params.h" |
cce8749e | 60 | |
d5b7b3ae RE |
61 | /* Forward definitions of types. */ |
62 | typedef struct minipool_node Mnode; | |
63 | typedef struct minipool_fixup Mfix; | |
64 | ||
b76c3c4b PB |
65 | void (*arm_lang_output_object_attributes_hook)(void); |
66 | ||
d5b7b3ae | 67 | /* Forward function declarations. */ |
35596784 | 68 | static int arm_compute_static_chain_stack_bytes (void); |
5848830f | 69 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 70 | static void arm_add_gc_roots (void); |
a406f566 MM |
71 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
72 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
73 | static unsigned bit_count (unsigned long); |
74 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 75 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
5b3e6663 PB |
76 | static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); |
77 | static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); | |
506d7b68 PB |
78 | static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); |
79 | static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); | |
5b3e6663 | 80 | inline static int thumb1_index_register_rtx_p (rtx, int); |
c6c3dba9 | 81 | static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); |
5848830f | 82 | static int thumb_far_jump_used_p (void); |
57934c39 | 83 | static bool thumb_force_lr_save (void); |
e32bac5b | 84 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 85 | static rtx emit_sfm (int, int); |
466e4b7a | 86 | static unsigned arm_size_return_regs (void); |
e32bac5b | 87 | static bool arm_assemble_integer (rtx, unsigned int, int); |
944442bb NF |
88 | static void arm_print_operand (FILE *, rtx, int); |
89 | static void arm_print_operand_address (FILE *, rtx); | |
90 | static bool arm_print_operand_punct_valid_p (unsigned char code); | |
e32bac5b RE |
91 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
92 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
93 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
94 | static rtx is_jump_table (rtx); | |
95 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
96 | int, HOST_WIDE_INT); | |
e32bac5b RE |
97 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
98 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 99 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
100 | static rtx is_jump_table (rtx); |
101 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
102 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
103 | static Mnode *add_minipool_forward_ref (Mfix *); | |
104 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
105 | static Mnode *add_minipool_backward_ref (Mfix *); | |
106 | static void assign_minipool_offsets (Mfix *); | |
107 | static void arm_print_value (FILE *, rtx); | |
108 | static void dump_minipool (rtx); | |
109 | static int arm_barrier_cost (rtx); | |
110 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
111 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
112 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
113 | rtx); | |
114 | static void arm_reorg (void); | |
115 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
e32bac5b RE |
116 | static unsigned long arm_compute_save_reg0_reg12_mask (void); |
117 | static unsigned long arm_compute_save_reg_mask (void); | |
118 | static unsigned long arm_isr_value (tree); | |
119 | static unsigned long arm_compute_func_type (void); | |
120 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
390b17c2 | 121 | static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *); |
e32bac5b | 122 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 123 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 124 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 125 | #endif |
e32bac5b RE |
126 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
127 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
5b3e6663 | 128 | static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT); |
3101faab | 129 | static int arm_comp_type_attributes (const_tree, const_tree); |
e32bac5b RE |
130 | static void arm_set_default_type_attributes (tree); |
131 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
132 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
133 | static int arm_get_strip_length (int); | |
134 | static bool arm_function_ok_for_sibcall (tree, tree); | |
390b17c2 RE |
135 | static enum machine_mode arm_promote_function_mode (const_tree, |
136 | enum machine_mode, int *, | |
137 | const_tree, int); | |
138 | static bool arm_return_in_memory (const_tree, const_tree); | |
139 | static rtx arm_function_value (const_tree, const_tree, bool); | |
7fc6a96b | 140 | static rtx arm_libcall_value (enum machine_mode, const_rtx); |
390b17c2 | 141 | |
e32bac5b RE |
142 | static void arm_internal_label (FILE *, const char *, unsigned long); |
143 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
144 | tree); | |
2929029c | 145 | static bool arm_have_conditional_execution (void); |
d5a0a47b RE |
146 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); |
147 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | |
148 | static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
149 | static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
150 | static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
151 | static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
f40751dd JH |
152 | static bool arm_rtx_costs (rtx, int, int, int *, bool); |
153 | static int arm_address_cost (rtx, bool); | |
e32bac5b RE |
154 | static bool arm_memory_load_p (rtx); |
155 | static bool arm_cirrus_insn_p (rtx); | |
156 | static void cirrus_reorg (rtx); | |
5a9335ef | 157 | static void arm_init_builtins (void); |
5a9335ef NC |
158 | static void arm_init_iwmmxt_builtins (void); |
159 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
160 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
161 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
162 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 163 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 164 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
165 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
166 | tree, bool); | |
390b17c2 RE |
167 | static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree, |
168 | const_tree); | |
169 | static int aapcs_select_return_coproc (const_tree, const_tree); | |
5a9335ef | 170 | |
7abc66b1 | 171 | #ifdef OBJECT_FORMAT_ELF |
9403b7f7 RS |
172 | static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; |
173 | static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; | |
7abc66b1 | 174 | #endif |
fb49053f | 175 | #ifndef ARM_PE |
e32bac5b | 176 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 177 | #endif |
b12a00f1 RE |
178 | |
179 | static void arm_file_end (void); | |
6c6aa1af | 180 | static void arm_file_start (void); |
b12a00f1 | 181 | |
1cc9f5f5 KH |
182 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
183 | tree, int *, int); | |
8cd5a4e0 | 184 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 KG |
185 | enum machine_mode, const_tree, bool); |
186 | static bool arm_promote_prototypes (const_tree); | |
6b045785 | 187 | static bool arm_default_short_enums (void); |
13c1cd82 | 188 | static bool arm_align_anon_bitfield (void); |
586de218 KG |
189 | static bool arm_return_in_msb (const_tree); |
190 | static bool arm_must_pass_in_stack (enum machine_mode, const_tree); | |
23668cf7 | 191 | static bool arm_return_in_memory (const_tree, const_tree); |
617a1b71 PB |
192 | #ifdef TARGET_UNWIND_INFO |
193 | static void arm_unwind_emit (FILE *, rtx); | |
194 | static bool arm_output_ttype (rtx); | |
195 | #endif | |
5b3e6663 | 196 | static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); |
854b8a40 | 197 | static rtx arm_dwarf_register_span (rtx); |
c237e94a | 198 | |
4185ae53 PB |
199 | static tree arm_cxx_guard_type (void); |
200 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
201 | static tree arm_get_cookie_size (tree); |
202 | static bool arm_cookie_has_size (void); | |
44d10c10 | 203 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 204 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
205 | static void arm_cxx_determine_class_data_visibility (tree); |
206 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 207 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 208 | static void arm_init_libfuncs (void); |
07d8efe3 MM |
209 | static tree arm_build_builtin_va_list (void); |
210 | static void arm_expand_builtin_va_start (tree, rtx); | |
ae46a823 | 211 | static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
c54c7322 | 212 | static bool arm_handle_option (size_t, const char *, int); |
67e6ba46 | 213 | static void arm_target_help (void); |
273a2526 | 214 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
215 | static bool arm_cannot_copy_insn_p (rtx); |
216 | static bool arm_tls_symbol_p (rtx x); | |
bd4dc3cd | 217 | static int arm_issue_rate (void); |
afcc986d | 218 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
007e61c2 | 219 | static bool arm_allocate_stack_slots_for_args (void); |
0fd8c3ad SL |
220 | static const char *arm_invalid_parameter_type (const_tree t); |
221 | static const char *arm_invalid_return_type (const_tree t); | |
222 | static tree arm_promoted_type (const_tree t); | |
223 | static tree arm_convert_to_type (tree type, tree expr); | |
bdc4827b | 224 | static bool arm_scalar_mode_supported_p (enum machine_mode); |
b52b1749 | 225 | static bool arm_frame_pointer_required (void); |
7b5cbb57 | 226 | static bool arm_can_eliminate (const int, const int); |
0ef9304b RH |
227 | static void arm_asm_trampoline_template (FILE *); |
228 | static void arm_trampoline_init (rtx, tree, rtx); | |
229 | static rtx arm_trampoline_adjust_address (rtx); | |
85c9bcd4 | 230 | static rtx arm_pic_static_addr (rtx orig, rtx reg); |
b0c13111 RR |
231 | static bool cortex_a9_sched_adjust_cost (rtx, rtx, rtx, int *); |
232 | static bool xscale_sched_adjust_cost (rtx, rtx, rtx, int *); | |
b52b1749 | 233 | |
5a82ecd9 ILT |
234 | \f |
235 | /* Table of machine attributes. */ | |
236 | static const struct attribute_spec arm_attribute_table[] = | |
237 | { | |
238 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ | |
239 | /* Function calls made to this symbol must be done indirectly, because | |
240 | it may lie outside of the 26 bit addressing range of a normal function | |
241 | call. */ | |
242 | { "long_call", 0, 0, false, true, true, NULL }, | |
243 | /* Whereas these functions are always known to reside within the 26 bit | |
244 | addressing range. */ | |
245 | { "short_call", 0, 0, false, true, true, NULL }, | |
390b17c2 RE |
246 | /* Specify the procedure call conventions for a function. */ |
247 | { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute }, | |
5a82ecd9 ILT |
248 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
249 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
250 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
251 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
252 | #ifdef ARM_PE | |
253 | /* ARM/PE has three new attributes: | |
254 | interfacearm - ? | |
255 | dllexport - for exporting a function/variable that will live in a dll | |
256 | dllimport - for importing a function/variable from a dll | |
d3585b76 | 257 | |
5a82ecd9 ILT |
258 | Microsoft allows multiple declspecs in one __declspec, separating |
259 | them with spaces. We do NOT support this. Instead, use __declspec | |
260 | multiple times. | |
261 | */ | |
262 | { "dllimport", 0, 0, true, false, false, NULL }, | |
263 | { "dllexport", 0, 0, true, false, false, NULL }, | |
264 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
265 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
266 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, | |
267 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, | |
268 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, | |
269 | #endif | |
270 | { NULL, 0, 0, false, false, false, NULL } | |
271 | }; | |
672a6f42 NB |
272 | \f |
273 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 274 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 275 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
276 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
277 | #endif | |
f3bb6135 | 278 | |
506d7b68 PB |
279 | #undef TARGET_LEGITIMIZE_ADDRESS |
280 | #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address | |
281 | ||
1d6e90ac | 282 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 283 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 284 | |
6c6aa1af PB |
285 | #undef TARGET_ASM_FILE_START |
286 | #define TARGET_ASM_FILE_START arm_file_start | |
b12a00f1 RE |
287 | #undef TARGET_ASM_FILE_END |
288 | #define TARGET_ASM_FILE_END arm_file_end | |
289 | ||
1d6e90ac | 290 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 291 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 292 | #undef TARGET_ASM_INTEGER |
301d03af | 293 | #define TARGET_ASM_INTEGER arm_assemble_integer |
301d03af | 294 | |
944442bb NF |
295 | #undef TARGET_PRINT_OPERAND |
296 | #define TARGET_PRINT_OPERAND arm_print_operand | |
297 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
298 | #define TARGET_PRINT_OPERAND_ADDRESS arm_print_operand_address | |
299 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
300 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P arm_print_operand_punct_valid_p | |
301 | ||
1d6e90ac | 302 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
303 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
304 | ||
1d6e90ac | 305 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
306 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
307 | ||
c54c7322 RS |
308 | #undef TARGET_DEFAULT_TARGET_FLAGS |
309 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
310 | #undef TARGET_HANDLE_OPTION | |
311 | #define TARGET_HANDLE_OPTION arm_handle_option | |
67e6ba46 NC |
312 | #undef TARGET_HELP |
313 | #define TARGET_HELP arm_target_help | |
c54c7322 | 314 | |
1d6e90ac | 315 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
316 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
317 | ||
1d6e90ac | 318 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
319 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
320 | ||
1d6e90ac | 321 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
322 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
323 | ||
fb49053f RH |
324 | #undef TARGET_ENCODE_SECTION_INFO |
325 | #ifdef ARM_PE | |
326 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
327 | #else | |
328 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
329 | #endif | |
330 | ||
5a9335ef | 331 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
332 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
333 | ||
5a9335ef | 334 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
335 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
336 | ||
5a9335ef | 337 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
338 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
339 | ||
390b17c2 RE |
340 | #undef TARGET_FUNCTION_VALUE |
341 | #define TARGET_FUNCTION_VALUE arm_function_value | |
342 | ||
343 | #undef TARGET_LIBCALL_VALUE | |
344 | #define TARGET_LIBCALL_VALUE arm_libcall_value | |
345 | ||
5a9335ef | 346 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 347 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 348 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 349 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 350 | |
5a9335ef | 351 | #undef TARGET_RTX_COSTS |
f40751dd | 352 | #define TARGET_RTX_COSTS arm_rtx_costs |
5a9335ef | 353 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 354 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 355 | |
273a2526 RS |
356 | #undef TARGET_SHIFT_TRUNCATION_MASK |
357 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
358 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
359 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
360 | ||
5a9335ef | 361 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
362 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
363 | ||
5a9335ef NC |
364 | #undef TARGET_INIT_BUILTINS |
365 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
366 | #undef TARGET_EXPAND_BUILTIN | |
367 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
368 | ||
b3f8d95d MM |
369 | #undef TARGET_INIT_LIBFUNCS |
370 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
371 | ||
cde0f3fd PB |
372 | #undef TARGET_PROMOTE_FUNCTION_MODE |
373 | #define TARGET_PROMOTE_FUNCTION_MODE arm_promote_function_mode | |
f9ba5949 | 374 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 375 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
376 | #undef TARGET_PASS_BY_REFERENCE |
377 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
378 | #undef TARGET_ARG_PARTIAL_BYTES |
379 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
f9ba5949 | 380 | |
1cc9f5f5 KH |
381 | #undef TARGET_SETUP_INCOMING_VARARGS |
382 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
383 | ||
007e61c2 PB |
384 | #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS |
385 | #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args | |
386 | ||
0ef9304b RH |
387 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
388 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE arm_asm_trampoline_template | |
389 | #undef TARGET_TRAMPOLINE_INIT | |
390 | #define TARGET_TRAMPOLINE_INIT arm_trampoline_init | |
391 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
392 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address | |
393 | ||
6b045785 PB |
394 | #undef TARGET_DEFAULT_SHORT_ENUMS |
395 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
396 | ||
13c1cd82 PB |
397 | #undef TARGET_ALIGN_ANON_BITFIELD |
398 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
399 | ||
c2a64439 PB |
400 | #undef TARGET_NARROW_VOLATILE_BITFIELD |
401 | #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false | |
402 | ||
4185ae53 PB |
403 | #undef TARGET_CXX_GUARD_TYPE |
404 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
405 | ||
406 | #undef TARGET_CXX_GUARD_MASK_BIT | |
407 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
408 | ||
46e995e0 PB |
409 | #undef TARGET_CXX_GET_COOKIE_SIZE |
410 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
411 | ||
412 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
413 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
414 | ||
44d10c10 PB |
415 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
416 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
417 | ||
505970fc MM |
418 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
419 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
420 | ||
9f62c3e3 PB |
421 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
422 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
423 | ||
1e731102 MM |
424 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
425 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
426 | arm_cxx_determine_class_data_visibility | |
427 | ||
428 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
429 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 430 | |
866af8a9 JB |
431 | #undef TARGET_RETURN_IN_MSB |
432 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
433 | ||
23668cf7 CLT |
434 | #undef TARGET_RETURN_IN_MEMORY |
435 | #define TARGET_RETURN_IN_MEMORY arm_return_in_memory | |
436 | ||
866af8a9 JB |
437 | #undef TARGET_MUST_PASS_IN_STACK |
438 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
439 | ||
617a1b71 | 440 | #ifdef TARGET_UNWIND_INFO |
38f8b050 JR |
441 | #undef TARGET_ASM_UNWIND_EMIT |
442 | #define TARGET_ASM_UNWIND_EMIT arm_unwind_emit | |
617a1b71 PB |
443 | |
444 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
445 | #undef TARGET_ASM_TTYPE | |
446 | #define TARGET_ASM_TTYPE arm_output_ttype | |
447 | ||
448 | #undef TARGET_ARM_EABI_UNWINDER | |
449 | #define TARGET_ARM_EABI_UNWINDER true | |
450 | #endif /* TARGET_UNWIND_INFO */ | |
451 | ||
5b3e6663 PB |
452 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
453 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec | |
454 | ||
854b8a40 JB |
455 | #undef TARGET_DWARF_REGISTER_SPAN |
456 | #define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span | |
457 | ||
d3585b76 DJ |
458 | #undef TARGET_CANNOT_COPY_INSN_P |
459 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
460 | ||
461 | #ifdef HAVE_AS_TLS | |
462 | #undef TARGET_HAVE_TLS | |
463 | #define TARGET_HAVE_TLS true | |
464 | #endif | |
465 | ||
2929029c WG |
466 | #undef TARGET_HAVE_CONDITIONAL_EXECUTION |
467 | #define TARGET_HAVE_CONDITIONAL_EXECUTION arm_have_conditional_execution | |
468 | ||
d3585b76 | 469 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
8426b956 | 470 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem |
d3585b76 | 471 | |
f67358da PB |
472 | #undef TARGET_MAX_ANCHOR_OFFSET |
473 | #define TARGET_MAX_ANCHOR_OFFSET 4095 | |
474 | ||
475 | /* The minimum is set such that the total size of the block | |
476 | for a particular anchor is -4088 + 1 + 4095 bytes, which is | |
477 | divisible by eight, ensuring natural spacing of anchors. */ | |
478 | #undef TARGET_MIN_ANCHOR_OFFSET | |
479 | #define TARGET_MIN_ANCHOR_OFFSET -4088 | |
480 | ||
bd4dc3cd PB |
481 | #undef TARGET_SCHED_ISSUE_RATE |
482 | #define TARGET_SCHED_ISSUE_RATE arm_issue_rate | |
483 | ||
608063c3 JB |
484 | #undef TARGET_MANGLE_TYPE |
485 | #define TARGET_MANGLE_TYPE arm_mangle_type | |
486 | ||
07d8efe3 MM |
487 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
488 | #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list | |
489 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
490 | #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start | |
491 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
492 | #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr | |
493 | ||
afcc986d JM |
494 | #ifdef HAVE_AS_TLS |
495 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
496 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel | |
497 | #endif | |
498 | ||
c6c3dba9 PB |
499 | #undef TARGET_LEGITIMATE_ADDRESS_P |
500 | #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p | |
501 | ||
0fd8c3ad SL |
502 | #undef TARGET_INVALID_PARAMETER_TYPE |
503 | #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type | |
504 | ||
505 | #undef TARGET_INVALID_RETURN_TYPE | |
506 | #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type | |
507 | ||
508 | #undef TARGET_PROMOTED_TYPE | |
509 | #define TARGET_PROMOTED_TYPE arm_promoted_type | |
510 | ||
511 | #undef TARGET_CONVERT_TO_TYPE | |
512 | #define TARGET_CONVERT_TO_TYPE arm_convert_to_type | |
513 | ||
bdc4827b SL |
514 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
515 | #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p | |
516 | ||
b52b1749 AS |
517 | #undef TARGET_FRAME_POINTER_REQUIRED |
518 | #define TARGET_FRAME_POINTER_REQUIRED arm_frame_pointer_required | |
519 | ||
7b5cbb57 AS |
520 | #undef TARGET_CAN_ELIMINATE |
521 | #define TARGET_CAN_ELIMINATE arm_can_eliminate | |
522 | ||
f6897b10 | 523 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 524 | \f |
c7319d87 RE |
525 | /* Obstack for minipool constant handling. */ |
526 | static struct obstack minipool_obstack; | |
1d6e90ac | 527 | static char * minipool_startobj; |
c7319d87 | 528 | |
1d6e90ac NC |
529 | /* The maximum number of insns skipped which |
530 | will be conditionalised if possible. */ | |
c27ba912 DM |
531 | static int max_insns_skipped = 5; |
532 | ||
533 | extern FILE * asm_out_file; | |
534 | ||
6354dc9b | 535 | /* True if we are currently building a constant table. */ |
13bd191d PB |
536 | int making_const_table; |
537 | ||
9b66ebb1 PB |
538 | /* The processor for which instructions should be scheduled. */ |
539 | enum processor_type arm_tune = arm_none; | |
540 | ||
1b78f575 RE |
541 | /* The current tuning set. */ |
542 | const struct tune_params *current_tune; | |
543 | ||
9b66ebb1 | 544 | /* Which floating point hardware to schedule for. */ |
d79f3032 PB |
545 | int arm_fpu_attr; |
546 | ||
547 | /* Which floating popint hardware to use. */ | |
548 | const struct arm_fpu_desc *arm_fpu_desc; | |
9b66ebb1 PB |
549 | |
550 | /* Whether to use floating point hardware. */ | |
551 | enum float_abi_type arm_float_abi; | |
552 | ||
0fd8c3ad SL |
553 | /* Which __fp16 format to use. */ |
554 | enum arm_fp16_format_type arm_fp16_format; | |
555 | ||
5848830f PB |
556 | /* Which ABI to use. */ |
557 | enum arm_abi_type arm_abi; | |
558 | ||
d3585b76 DJ |
559 | /* Which thread pointer model to use. */ |
560 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
561 | ||
b355a481 | 562 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 563 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 564 | |
b12a00f1 | 565 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 566 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
567 | static int thumb_call_reg_needed; |
568 | ||
aec3cfba | 569 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 570 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 571 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
572 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
573 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
574 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
575 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
576 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
577 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
578 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 579 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 580 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 581 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 582 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
583 | media instructions. */ |
584 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
585 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
586 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 587 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
5b3e6663 PB |
588 | #define FL_THUMB2 (1 << 16) /* Thumb-2. */ |
589 | #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' | |
590 | profile. */ | |
7a085dce | 591 | #define FL_DIV (1 << 18) /* Hardware divide. */ |
f1adb0a9 | 592 | #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ |
88f77cba | 593 | #define FL_NEON (1 << 20) /* Neon instructions. */ |
60bd3528 PB |
594 | #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M |
595 | architecture. */ | |
aec3cfba | 596 | |
9b66ebb1 PB |
597 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
598 | ||
12a0a4d4 PB |
599 | /* Flags that only effect tuning, not available instructions. */ |
600 | #define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \ | |
601 | | FL_CO_PROC) | |
602 | ||
5b3e6663 PB |
603 | #define FL_FOR_ARCH2 FL_NOTM |
604 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | |
78011587 PB |
605 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) |
606 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
607 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
608 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
609 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
610 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
611 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
612 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
613 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
614 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 615 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 616 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 617 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
5b3e6663 | 618 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) |
bf98ec6c | 619 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) |
5b3e6663 | 620 | #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) |
87d05b44 | 621 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) |
5b3e6663 PB |
622 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) |
623 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | |
60bd3528 | 624 | #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) |
78011587 | 625 | |
1d6e90ac NC |
626 | /* The bits in this mask specify which |
627 | instructions we are allowed to generate. */ | |
0977774b | 628 | static unsigned long insn_flags = 0; |
d5b7b3ae | 629 | |
aec3cfba | 630 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 631 | be used. */ |
0977774b | 632 | static unsigned long tune_flags = 0; |
aec3cfba NC |
633 | |
634 | /* The following are used in the arm.md file as equivalents to bits | |
635 | in the above two flag variables. */ | |
636 | ||
9b66ebb1 PB |
637 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
638 | int arm_arch3m = 0; | |
2b835d68 | 639 | |
6354dc9b | 640 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
641 | int arm_arch4 = 0; |
642 | ||
68d560d4 RE |
643 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
644 | int arm_arch4t = 0; | |
645 | ||
6354dc9b | 646 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
647 | int arm_arch5 = 0; |
648 | ||
b15bca31 RE |
649 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
650 | int arm_arch5e = 0; | |
651 | ||
9b66ebb1 PB |
652 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
653 | int arm_arch6 = 0; | |
654 | ||
d3585b76 DJ |
655 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
656 | int arm_arch6k = 0; | |
657 | ||
5b3e6663 PB |
658 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
659 | int arm_arch_notm = 0; | |
660 | ||
60bd3528 PB |
661 | /* Nonzero if instructions present in ARMv7E-M can be used. */ |
662 | int arm_arch7em = 0; | |
663 | ||
aec3cfba | 664 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
665 | int arm_ld_sched = 0; |
666 | ||
667 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 668 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 669 | |
78011587 PB |
670 | /* Nonzero if this chip is a Cirrus variant. */ |
671 | int arm_arch_cirrus = 0; | |
672 | ||
5a9335ef NC |
673 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
674 | int arm_arch_iwmmxt = 0; | |
675 | ||
d19fb8e3 | 676 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
677 | int arm_arch_xscale = 0; |
678 | ||
679 | /* Nonzero if tuning for XScale */ | |
680 | int arm_tune_xscale = 0; | |
d19fb8e3 | 681 | |
e0b92319 | 682 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 683 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 684 | int arm_tune_wbuf = 0; |
b111229a | 685 | |
7612f14d PB |
686 | /* Nonzero if tuning for Cortex-A9. */ |
687 | int arm_tune_cortex_a9 = 0; | |
688 | ||
0616531f RE |
689 | /* Nonzero if generating Thumb instructions. */ |
690 | int thumb_code = 0; | |
691 | ||
906668bb BS |
692 | /* Nonzero if generating Thumb-1 instructions. */ |
693 | int thumb1_code = 0; | |
694 | ||
2ad4dcf9 | 695 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 696 | preprocessor. |
2ad4dcf9 RE |
697 | XXX This is a bit of a hack, it's intended to help work around |
698 | problems in GLD which doesn't understand that armv5t code is | |
699 | interworking clean. */ | |
700 | int arm_cpp_interwork = 0; | |
701 | ||
5b3e6663 PB |
702 | /* Nonzero if chip supports Thumb 2. */ |
703 | int arm_arch_thumb2; | |
704 | ||
705 | /* Nonzero if chip supports integer division instruction. */ | |
706 | int arm_arch_hwdiv; | |
707 | ||
944442bb NF |
708 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, |
709 | we must report the mode of the memory reference from | |
710 | TARGET_PRINT_OPERAND to TARGET_PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 711 | enum machine_mode output_memory_reference_mode; |
cce8749e | 712 | |
32de079a | 713 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 714 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 715 | |
aec3cfba NC |
716 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
717 | the next function. */ | |
4b632bf1 RE |
718 | static int after_arm_reorg = 0; |
719 | ||
12ffc7d5 | 720 | enum arm_pcs arm_pcs_default; |
390b17c2 | 721 | |
cce8749e CH |
722 | /* For an explanation of these variables, see final_prescan_insn below. */ |
723 | int arm_ccfsm_state; | |
5b3e6663 | 724 | /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ |
84ed5e79 | 725 | enum arm_cond_code arm_current_cc; |
906668bb | 726 | |
cce8749e CH |
727 | rtx arm_target_insn; |
728 | int arm_target_label; | |
5b3e6663 PB |
729 | /* The number of conditionally executed insns, including the current insn. */ |
730 | int arm_condexec_count = 0; | |
731 | /* A bitmask specifying the patterns for the IT block. | |
732 | Zero means do not output an IT block before this insn. */ | |
733 | int arm_condexec_mask = 0; | |
734 | /* The number of bits used in arm_condexec_mask. */ | |
735 | int arm_condexec_masklen = 0; | |
9997d19d RE |
736 | |
737 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 738 | static const char * const arm_condition_codes[] = |
9997d19d RE |
739 | { |
740 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
741 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
742 | }; | |
743 | ||
37119410 BS |
744 | /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ |
745 | int arm_regs_in_sequence[] = | |
746 | { | |
747 | 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 | |
748 | }; | |
749 | ||
5b3e6663 | 750 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") |
f5a1b0d2 | 751 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
5b3e6663 PB |
752 | |
753 | #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \ | |
754 | | (1 << SP_REGNUM) | (1 << PC_REGNUM) \ | |
755 | | (1 << PIC_OFFSET_TABLE_REGNUM))) | |
2b835d68 | 756 | \f |
6354dc9b | 757 | /* Initialization code. */ |
2b835d68 | 758 | |
2b835d68 RE |
759 | struct processors |
760 | { | |
8b60264b | 761 | const char *const name; |
9b66ebb1 | 762 | enum processor_type core; |
78011587 | 763 | const char *arch; |
0977774b | 764 | const unsigned long flags; |
1b78f575 RE |
765 | const struct tune_params *const tune; |
766 | }; | |
767 | ||
768 | const struct tune_params arm_slowmul_tune = | |
769 | { | |
770 | arm_slowmul_rtx_costs, | |
b0c13111 | 771 | NULL, |
1b78f575 RE |
772 | 3 |
773 | }; | |
774 | ||
775 | const struct tune_params arm_fastmul_tune = | |
776 | { | |
777 | arm_fastmul_rtx_costs, | |
b0c13111 | 778 | NULL, |
1b78f575 RE |
779 | 1 |
780 | }; | |
781 | ||
782 | const struct tune_params arm_xscale_tune = | |
783 | { | |
784 | arm_xscale_rtx_costs, | |
b0c13111 | 785 | xscale_sched_adjust_cost, |
1b78f575 RE |
786 | 2 |
787 | }; | |
788 | ||
789 | const struct tune_params arm_9e_tune = | |
790 | { | |
791 | arm_9e_rtx_costs, | |
b0c13111 | 792 | NULL, |
1b78f575 | 793 | 1 |
2b835d68 RE |
794 | }; |
795 | ||
b0c13111 RR |
796 | const struct tune_params arm_cortex_a9_tune = |
797 | { | |
798 | arm_9e_rtx_costs, | |
799 | cortex_a9_sched_adjust_cost, | |
800 | 1 | |
801 | }; | |
802 | ||
803 | ||
2b835d68 RE |
804 | /* Not all of these give usefully different compilation alternatives, |
805 | but there is no simple way of generalizing them. */ | |
8b60264b | 806 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
807 | { |
808 | /* ARM Cores */ | |
d98a72fd | 809 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
12a0a4d4 | 810 | {NAME, IDENT, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, &arm_##COSTS##_tune}, |
9b66ebb1 PB |
811 | #include "arm-cores.def" |
812 | #undef ARM_CORE | |
78011587 | 813 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
814 | }; |
815 | ||
8b60264b | 816 | static const struct processors all_architectures[] = |
2b835d68 | 817 | { |
f5a1b0d2 | 818 | /* ARM Architectures */ |
1b78f575 | 819 | /* We don't specify tuning costs here as it will be figured out |
9b66ebb1 | 820 | from the core. */ |
f676971a | 821 | |
78011587 PB |
822 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
823 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
824 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
825 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
826 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
827 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
828 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
829 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
830 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
831 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
832 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
833 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
834 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
835 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
836 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
837 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
838 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
5b3e6663 | 839 | {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL}, |
bf98ec6c | 840 | {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL}, |
5b3e6663 PB |
841 | {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL}, |
842 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | |
843 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | |
844 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | |
f6e47b26 | 845 | {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL}, |
78011587 PB |
846 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
847 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
442dc742 | 848 | {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, |
78011587 | 849 | {NULL, arm_none, NULL, 0 , NULL} |
f5a1b0d2 NC |
850 | }; |
851 | ||
f5a1b0d2 | 852 | |
12a0a4d4 PB |
853 | /* These are populated as commandline arguments are processed, or NULL |
854 | if not specified. */ | |
855 | static const struct processors *arm_selected_arch; | |
856 | static const struct processors *arm_selected_cpu; | |
857 | static const struct processors *arm_selected_tune; | |
78011587 | 858 | |
afc0a4ba | 859 | /* The name of the preprocessor macro to define for this architecture. */ |
78011587 PB |
860 | |
861 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
862 | ||
56f42830 | 863 | /* Available values for -mfpu=. */ |
9b66ebb1 | 864 | |
d79f3032 PB |
865 | static const struct arm_fpu_desc all_fpus[] = |
866 | { | |
70dd156a RN |
867 | {"fpa", ARM_FP_MODEL_FPA, 0, VFP_NONE, false, false}, |
868 | {"fpe2", ARM_FP_MODEL_FPA, 2, VFP_NONE, false, false}, | |
869 | {"fpe3", ARM_FP_MODEL_FPA, 3, VFP_NONE, false, false}, | |
870 | {"maverick", ARM_FP_MODEL_MAVERICK, 0, VFP_NONE, false, false}, | |
d79f3032 PB |
871 | {"vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false}, |
872 | {"vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false}, | |
e0dc3601 | 873 | {"vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true}, |
d79f3032 | 874 | {"vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false}, |
e0dc3601 PB |
875 | {"vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true}, |
876 | {"vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false}, | |
877 | {"vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true}, | |
d79f3032 PB |
878 | {"neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false}, |
879 | {"neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , true }, | |
6ed126e6 PB |
880 | {"vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true}, |
881 | {"vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true}, | |
1abed66b | 882 | {"fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true}, |
6ed126e6 | 883 | {"neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true}, |
d79f3032 PB |
884 | /* Compatibility aliases. */ |
885 | {"vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false}, | |
9b66ebb1 PB |
886 | }; |
887 | ||
888 | ||
889 | struct float_abi | |
890 | { | |
891 | const char * name; | |
892 | enum float_abi_type abi_type; | |
893 | }; | |
894 | ||
895 | ||
896 | /* Available values for -mfloat-abi=. */ | |
897 | ||
898 | static const struct float_abi all_float_abis[] = | |
899 | { | |
900 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
901 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
902 | {"hard", ARM_FLOAT_ABI_HARD} | |
903 | }; | |
904 | ||
905 | ||
0fd8c3ad SL |
906 | struct fp16_format |
907 | { | |
908 | const char *name; | |
909 | enum arm_fp16_format_type fp16_format_type; | |
910 | }; | |
911 | ||
912 | ||
913 | /* Available values for -mfp16-format=. */ | |
914 | ||
915 | static const struct fp16_format all_fp16_formats[] = | |
916 | { | |
917 | {"none", ARM_FP16_FORMAT_NONE}, | |
918 | {"ieee", ARM_FP16_FORMAT_IEEE}, | |
919 | {"alternative", ARM_FP16_FORMAT_ALTERNATIVE} | |
920 | }; | |
921 | ||
922 | ||
5848830f PB |
923 | struct abi_name |
924 | { | |
925 | const char *name; | |
926 | enum arm_abi_type abi_type; | |
927 | }; | |
928 | ||
929 | ||
930 | /* Available values for -mabi=. */ | |
931 | ||
932 | static const struct abi_name arm_all_abis[] = | |
933 | { | |
934 | {"apcs-gnu", ARM_ABI_APCS}, | |
935 | {"atpcs", ARM_ABI_ATPCS}, | |
936 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
937 | {"iwmmxt", ARM_ABI_IWMMXT}, |
938 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
939 | }; |
940 | ||
d3585b76 DJ |
941 | /* Supported TLS relocations. */ |
942 | ||
943 | enum tls_reloc { | |
944 | TLS_GD32, | |
945 | TLS_LDM32, | |
946 | TLS_LDO32, | |
947 | TLS_IE32, | |
948 | TLS_LE32 | |
949 | }; | |
950 | ||
1b78f575 RE |
951 | /* The maximum number of insns to be used when loading a constant. */ |
952 | inline static int | |
953 | arm_constant_limit (bool size_p) | |
954 | { | |
955 | return size_p ? 1 : current_tune->constant_limit; | |
956 | } | |
957 | ||
d66437c5 RE |
958 | /* Emit an insn that's a simple single-set. Both the operands must be known |
959 | to be valid. */ | |
960 | inline static rtx | |
961 | emit_set_insn (rtx x, rtx y) | |
962 | { | |
963 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
964 | } | |
965 | ||
0977774b JT |
966 | /* Return the number of bits set in VALUE. */ |
967 | static unsigned | |
e32bac5b | 968 | bit_count (unsigned long value) |
aec3cfba | 969 | { |
d5b7b3ae | 970 | unsigned long count = 0; |
f676971a | 971 | |
aec3cfba NC |
972 | while (value) |
973 | { | |
0977774b JT |
974 | count++; |
975 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
976 | } |
977 | ||
978 | return count; | |
979 | } | |
980 | ||
c112cf2b | 981 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
982 | |
983 | static void | |
984 | arm_init_libfuncs (void) | |
985 | { | |
986 | /* There are no special library functions unless we are using the | |
987 | ARM BPABI. */ | |
988 | if (!TARGET_BPABI) | |
989 | return; | |
990 | ||
991 | /* The functions below are described in Section 4 of the "Run-Time | |
992 | ABI for the ARM architecture", Version 1.0. */ | |
993 | ||
994 | /* Double-precision floating-point arithmetic. Table 2. */ | |
995 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
996 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
997 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
998 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
999 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
1000 | ||
c112cf2b | 1001 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
1002 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
1003 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
1004 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
1005 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
1006 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
1007 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
1008 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
1009 | ||
1010 | /* Single-precision floating-point arithmetic. Table 4. */ | |
1011 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
1012 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
1013 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
1014 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
1015 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 1016 | |
c112cf2b | 1017 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
1018 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
1019 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
1020 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
1021 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
1022 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
1023 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
1024 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
1025 | ||
1026 | /* Floating-point to integer conversions. Table 6. */ | |
1027 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
1028 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
1029 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
1030 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
1031 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
1032 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
1033 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
1034 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
1035 | ||
1036 | /* Conversions between floating types. Table 7. */ | |
1037 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
1038 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
1039 | ||
c112cf2b | 1040 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
1041 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
1042 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
1043 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
1044 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
1045 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
1046 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
1047 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
1048 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
1049 | ||
1050 | /* Long long. Table 9. */ | |
1051 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
1052 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
1053 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
1054 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
1055 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
1056 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
1057 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
1058 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
1059 | ||
1060 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
1061 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
1062 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
1063 | ||
1064 | /* The divmod functions are designed so that they can be used for | |
1065 | plain division, even though they return both the quotient and the | |
1066 | remainder. The quotient is returned in the usual location (i.e., | |
1067 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
1068 | for an ordinary division routine. Because the AAPCS calling | |
1069 | conventions specify that all of { r0, r1, r2, r3 } are | |
1070 | callee-saved registers, there is no need to tell the compiler | |
1071 | explicitly that those registers are clobbered by these | |
1072 | routines. */ | |
1073 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
1074 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
1075 | |
1076 | /* For SImode division the ABI provides div-without-mod routines, | |
1077 | which are faster. */ | |
1078 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
1079 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
1080 | |
1081 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
1082 | divmod libcalls instead. */ | |
1083 | set_optab_libfunc (smod_optab, DImode, NULL); | |
1084 | set_optab_libfunc (umod_optab, DImode, NULL); | |
1085 | set_optab_libfunc (smod_optab, SImode, NULL); | |
1086 | set_optab_libfunc (umod_optab, SImode, NULL); | |
0fd8c3ad SL |
1087 | |
1088 | /* Half-precision float operations. The compiler handles all operations | |
1089 | with NULL libfuncs by converting the SFmode. */ | |
1090 | switch (arm_fp16_format) | |
1091 | { | |
1092 | case ARM_FP16_FORMAT_IEEE: | |
1093 | case ARM_FP16_FORMAT_ALTERNATIVE: | |
1094 | ||
1095 | /* Conversions. */ | |
1096 | set_conv_libfunc (trunc_optab, HFmode, SFmode, | |
1097 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
1098 | ? "__gnu_f2h_ieee" | |
1099 | : "__gnu_f2h_alternative")); | |
1100 | set_conv_libfunc (sext_optab, SFmode, HFmode, | |
1101 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
1102 | ? "__gnu_h2f_ieee" | |
1103 | : "__gnu_h2f_alternative")); | |
1104 | ||
1105 | /* Arithmetic. */ | |
1106 | set_optab_libfunc (add_optab, HFmode, NULL); | |
1107 | set_optab_libfunc (sdiv_optab, HFmode, NULL); | |
1108 | set_optab_libfunc (smul_optab, HFmode, NULL); | |
1109 | set_optab_libfunc (neg_optab, HFmode, NULL); | |
1110 | set_optab_libfunc (sub_optab, HFmode, NULL); | |
1111 | ||
1112 | /* Comparisons. */ | |
1113 | set_optab_libfunc (eq_optab, HFmode, NULL); | |
1114 | set_optab_libfunc (ne_optab, HFmode, NULL); | |
1115 | set_optab_libfunc (lt_optab, HFmode, NULL); | |
1116 | set_optab_libfunc (le_optab, HFmode, NULL); | |
1117 | set_optab_libfunc (ge_optab, HFmode, NULL); | |
1118 | set_optab_libfunc (gt_optab, HFmode, NULL); | |
1119 | set_optab_libfunc (unord_optab, HFmode, NULL); | |
1120 | break; | |
1121 | ||
1122 | default: | |
1123 | break; | |
1124 | } | |
353a58f7 AH |
1125 | |
1126 | if (TARGET_AAPCS_BASED) | |
1127 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
b3f8d95d MM |
1128 | } |
1129 | ||
07d8efe3 MM |
1130 | /* On AAPCS systems, this is the "struct __va_list". */ |
1131 | static GTY(()) tree va_list_type; | |
1132 | ||
1133 | /* Return the type to use as __builtin_va_list. */ | |
1134 | static tree | |
1135 | arm_build_builtin_va_list (void) | |
1136 | { | |
1137 | tree va_list_name; | |
1138 | tree ap_field; | |
1139 | ||
1140 | if (!TARGET_AAPCS_BASED) | |
1141 | return std_build_builtin_va_list (); | |
1142 | ||
1143 | /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type | |
1144 | defined as: | |
1145 | ||
1146 | struct __va_list | |
1147 | { | |
1148 | void *__ap; | |
1149 | }; | |
1150 | ||
1151 | The C Library ABI further reinforces this definition in \S | |
1152 | 4.1. | |
1153 | ||
1154 | We must follow this definition exactly. The structure tag | |
1155 | name is visible in C++ mangled names, and thus forms a part | |
1156 | of the ABI. The field name may be used by people who | |
1157 | #include <stdarg.h>. */ | |
1158 | /* Create the type. */ | |
1159 | va_list_type = lang_hooks.types.make_type (RECORD_TYPE); | |
1160 | /* Give it the required name. */ | |
4c4bde29 AH |
1161 | va_list_name = build_decl (BUILTINS_LOCATION, |
1162 | TYPE_DECL, | |
07d8efe3 MM |
1163 | get_identifier ("__va_list"), |
1164 | va_list_type); | |
1165 | DECL_ARTIFICIAL (va_list_name) = 1; | |
1166 | TYPE_NAME (va_list_type) = va_list_name; | |
1167 | /* Create the __ap field. */ | |
4c4bde29 AH |
1168 | ap_field = build_decl (BUILTINS_LOCATION, |
1169 | FIELD_DECL, | |
07d8efe3 MM |
1170 | get_identifier ("__ap"), |
1171 | ptr_type_node); | |
1172 | DECL_ARTIFICIAL (ap_field) = 1; | |
1173 | DECL_FIELD_CONTEXT (ap_field) = va_list_type; | |
1174 | TYPE_FIELDS (va_list_type) = ap_field; | |
1175 | /* Compute its layout. */ | |
1176 | layout_type (va_list_type); | |
1177 | ||
1178 | return va_list_type; | |
1179 | } | |
1180 | ||
1181 | /* Return an expression of type "void *" pointing to the next | |
1182 | available argument in a variable-argument list. VALIST is the | |
1183 | user-level va_list object, of type __builtin_va_list. */ | |
1184 | static tree | |
1185 | arm_extract_valist_ptr (tree valist) | |
1186 | { | |
1187 | if (TREE_TYPE (valist) == error_mark_node) | |
1188 | return error_mark_node; | |
1189 | ||
1190 | /* On an AAPCS target, the pointer is stored within "struct | |
1191 | va_list". */ | |
1192 | if (TARGET_AAPCS_BASED) | |
1193 | { | |
1194 | tree ap_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
1195 | valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field), | |
1196 | valist, ap_field, NULL_TREE); | |
1197 | } | |
1198 | ||
1199 | return valist; | |
1200 | } | |
1201 | ||
1202 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ | |
1203 | static void | |
1204 | arm_expand_builtin_va_start (tree valist, rtx nextarg) | |
1205 | { | |
1206 | valist = arm_extract_valist_ptr (valist); | |
1207 | std_expand_builtin_va_start (valist, nextarg); | |
1208 | } | |
1209 | ||
1210 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
1211 | static tree | |
ae46a823 JM |
1212 | arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1213 | gimple_seq *post_p) | |
07d8efe3 MM |
1214 | { |
1215 | valist = arm_extract_valist_ptr (valist); | |
1216 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); | |
1217 | } | |
1218 | ||
12a0a4d4 PB |
1219 | /* Lookup NAME in SEL. */ |
1220 | ||
1221 | static const struct processors * | |
1222 | arm_find_cpu (const char *name, const struct processors *sel, const char *desc) | |
1223 | { | |
1224 | if (!(name && *name)) | |
1225 | return NULL; | |
1226 | ||
1227 | for (; sel->name != NULL; sel++) | |
1228 | { | |
1229 | if (streq (name, sel->name)) | |
1230 | return sel; | |
1231 | } | |
1232 | ||
1233 | error ("bad value (%s) for %s switch", name, desc); | |
1234 | return NULL; | |
1235 | } | |
1236 | ||
c54c7322 RS |
1237 | /* Implement TARGET_HANDLE_OPTION. */ |
1238 | ||
1239 | static bool | |
1240 | arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
1241 | { | |
1242 | switch (code) | |
1243 | { | |
c54c7322 | 1244 | case OPT_march_: |
12a0a4d4 | 1245 | arm_selected_arch = arm_find_cpu(arg, all_architectures, "-march"); |
c54c7322 RS |
1246 | return true; |
1247 | ||
1248 | case OPT_mcpu_: | |
12a0a4d4 | 1249 | arm_selected_cpu = arm_find_cpu(arg, all_cores, "-mcpu"); |
c54c7322 RS |
1250 | return true; |
1251 | ||
c54c7322 RS |
1252 | case OPT_mhard_float: |
1253 | target_float_abi_name = "hard"; | |
1254 | return true; | |
1255 | ||
c54c7322 RS |
1256 | case OPT_msoft_float: |
1257 | target_float_abi_name = "soft"; | |
1258 | return true; | |
1259 | ||
c54c7322 | 1260 | case OPT_mtune_: |
12a0a4d4 | 1261 | arm_selected_tune = arm_find_cpu(arg, all_cores, "-mtune"); |
c54c7322 RS |
1262 | return true; |
1263 | ||
1264 | default: | |
1265 | return true; | |
1266 | } | |
1267 | } | |
1268 | ||
67e6ba46 NC |
1269 | static void |
1270 | arm_target_help (void) | |
1271 | { | |
1272 | int i; | |
1273 | static int columns = 0; | |
1274 | int remaining; | |
1275 | ||
1276 | /* If we have not done so already, obtain the desired maximum width of | |
1277 | the output. Note - this is a duplication of the code at the start of | |
1278 | gcc/opts.c:print_specific_help() - the two copies should probably be | |
1279 | replaced by a single function. */ | |
1280 | if (columns == 0) | |
1281 | { | |
1282 | const char *p; | |
1283 | ||
1284 | GET_ENVIRONMENT (p, "COLUMNS"); | |
1285 | if (p != NULL) | |
1286 | { | |
1287 | int value = atoi (p); | |
1288 | ||
1289 | if (value > 0) | |
1290 | columns = value; | |
1291 | } | |
1292 | ||
1293 | if (columns == 0) | |
1294 | /* Use a reasonable default. */ | |
1295 | columns = 80; | |
1296 | } | |
1297 | ||
1298 | printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"); | |
1299 | ||
1300 | /* The - 2 is because we know that the last entry in the array is NULL. */ | |
1301 | i = ARRAY_SIZE (all_cores) - 2; | |
1302 | gcc_assert (i > 0); | |
1303 | printf (" %s", all_cores[i].name); | |
1304 | remaining = columns - (strlen (all_cores[i].name) + 4); | |
1305 | gcc_assert (remaining >= 0); | |
1306 | ||
1307 | while (i--) | |
1308 | { | |
1309 | int len = strlen (all_cores[i].name); | |
1310 | ||
1311 | if (remaining > len + 2) | |
1312 | { | |
1313 | printf (", %s", all_cores[i].name); | |
1314 | remaining -= len + 2; | |
1315 | } | |
1316 | else | |
1317 | { | |
1318 | if (remaining > 0) | |
1319 | printf (","); | |
1320 | printf ("\n %s", all_cores[i].name); | |
1321 | remaining = columns - (len + 4); | |
1322 | } | |
1323 | } | |
1324 | ||
1325 | printf ("\n\n Known ARM architectures (for use with the -march= option):\n"); | |
1326 | ||
1327 | i = ARRAY_SIZE (all_architectures) - 2; | |
1328 | gcc_assert (i > 0); | |
1329 | ||
1330 | printf (" %s", all_architectures[i].name); | |
1331 | remaining = columns - (strlen (all_architectures[i].name) + 4); | |
1332 | gcc_assert (remaining >= 0); | |
1333 | ||
1334 | while (i--) | |
1335 | { | |
1336 | int len = strlen (all_architectures[i].name); | |
1337 | ||
1338 | if (remaining > len + 2) | |
1339 | { | |
1340 | printf (", %s", all_architectures[i].name); | |
1341 | remaining -= len + 2; | |
1342 | } | |
1343 | else | |
1344 | { | |
1345 | if (remaining > 0) | |
1346 | printf (","); | |
1347 | printf ("\n %s", all_architectures[i].name); | |
1348 | remaining = columns - (len + 4); | |
1349 | } | |
1350 | } | |
1351 | printf ("\n"); | |
1352 | ||
1353 | } | |
1354 | ||
2b835d68 RE |
1355 | /* Fix up any incompatible options that the user has specified. |
1356 | This has now turned into a maze. */ | |
1357 | void | |
e32bac5b | 1358 | arm_override_options (void) |
2b835d68 | 1359 | { |
ed4c4348 | 1360 | unsigned i; |
9b66ebb1 | 1361 | |
12a0a4d4 | 1362 | if (arm_selected_arch) |
bd9c7e23 | 1363 | { |
12a0a4d4 PB |
1364 | if (arm_selected_cpu) |
1365 | { | |
1366 | /* Check for conflict between mcpu and march. */ | |
1367 | if ((arm_selected_cpu->flags ^ arm_selected_arch->flags) & ~FL_TUNE) | |
1368 | { | |
1369 | warning (0, "switch -mcpu=%s conflicts with -march=%s switch", | |
1370 | arm_selected_cpu->name, arm_selected_arch->name); | |
1371 | /* -march wins for code generation. | |
1372 | -mcpu wins for default tuning. */ | |
1373 | if (!arm_selected_tune) | |
1374 | arm_selected_tune = arm_selected_cpu; | |
1375 | ||
1376 | arm_selected_cpu = arm_selected_arch; | |
1377 | } | |
1378 | else | |
1379 | /* -mcpu wins. */ | |
1380 | arm_selected_arch = NULL; | |
1381 | } | |
1382 | else | |
1383 | /* Pick a CPU based on the architecture. */ | |
1384 | arm_selected_cpu = arm_selected_arch; | |
bd9c7e23 | 1385 | } |
f676971a | 1386 | |
f5a1b0d2 | 1387 | /* If the user did not specify a processor, choose one for them. */ |
12a0a4d4 | 1388 | if (!arm_selected_cpu) |
f5a1b0d2 | 1389 | { |
8b60264b | 1390 | const struct processors * sel; |
aec3cfba | 1391 | unsigned int sought; |
aec3cfba | 1392 | |
12a0a4d4 PB |
1393 | arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT]; |
1394 | if (!arm_selected_cpu->name) | |
78011587 PB |
1395 | { |
1396 | #ifdef SUBTARGET_CPU_DEFAULT | |
1397 | /* Use the subtarget default CPU if none was specified by | |
1398 | configure. */ | |
12a0a4d4 | 1399 | arm_selected_cpu = &all_cores[SUBTARGET_CPU_DEFAULT]; |
78011587 PB |
1400 | #endif |
1401 | /* Default to ARM6. */ | |
12a0a4d4 PB |
1402 | if (arm_selected_cpu->name) |
1403 | arm_selected_cpu = &all_cores[arm6]; | |
78011587 | 1404 | } |
aec3cfba | 1405 | |
12a0a4d4 | 1406 | sel = arm_selected_cpu; |
aec3cfba | 1407 | insn_flags = sel->flags; |
9b66ebb1 | 1408 | |
aec3cfba NC |
1409 | /* Now check to see if the user has specified some command line |
1410 | switch that require certain abilities from the cpu. */ | |
1411 | sought = 0; | |
f676971a | 1412 | |
d5b7b3ae | 1413 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 1414 | { |
aec3cfba | 1415 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 1416 | |
d5b7b3ae | 1417 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
1418 | interworking. Therefore we force FL_MODE26 to be removed |
1419 | from insn_flags here (if it was set), so that the search | |
1420 | below will always be able to find a compatible processor. */ | |
5895f793 | 1421 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 1422 | } |
f676971a | 1423 | |
aec3cfba | 1424 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 1425 | { |
aec3cfba NC |
1426 | /* Try to locate a CPU type that supports all of the abilities |
1427 | of the default CPU, plus the extra abilities requested by | |
1428 | the user. */ | |
5895f793 | 1429 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 1430 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
1431 | break; |
1432 | ||
1433 | if (sel->name == NULL) | |
aec3cfba | 1434 | { |
0977774b | 1435 | unsigned current_bit_count = 0; |
8b60264b | 1436 | const struct processors * best_fit = NULL; |
f676971a | 1437 | |
aec3cfba NC |
1438 | /* Ideally we would like to issue an error message here |
1439 | saying that it was not possible to find a CPU compatible | |
1440 | with the default CPU, but which also supports the command | |
1441 | line options specified by the programmer, and so they | |
1442 | ought to use the -mcpu=<name> command line option to | |
1443 | override the default CPU type. | |
1444 | ||
61f0ccff RE |
1445 | If we cannot find a cpu that has both the |
1446 | characteristics of the default cpu and the given | |
1447 | command line options we scan the array again looking | |
1448 | for a best match. */ | |
5895f793 | 1449 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1450 | if ((sel->flags & sought) == sought) |
1451 | { | |
0977774b | 1452 | unsigned count; |
aec3cfba NC |
1453 | |
1454 | count = bit_count (sel->flags & insn_flags); | |
1455 | ||
1456 | if (count >= current_bit_count) | |
1457 | { | |
1458 | best_fit = sel; | |
1459 | current_bit_count = count; | |
1460 | } | |
1461 | } | |
f5a1b0d2 | 1462 | |
e6d29d15 NS |
1463 | gcc_assert (best_fit); |
1464 | sel = best_fit; | |
aec3cfba NC |
1465 | } |
1466 | ||
12a0a4d4 | 1467 | arm_selected_cpu = sel; |
f5a1b0d2 NC |
1468 | } |
1469 | } | |
f676971a | 1470 | |
12a0a4d4 PB |
1471 | gcc_assert (arm_selected_cpu); |
1472 | /* The selected cpu may be an architecture, so lookup tuning by core ID. */ | |
1473 | if (!arm_selected_tune) | |
1474 | arm_selected_tune = &all_cores[arm_selected_cpu->core]; | |
1475 | ||
1476 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch); | |
1477 | insn_flags = arm_selected_cpu->flags; | |
f676971a | 1478 | |
12a0a4d4 PB |
1479 | arm_tune = arm_selected_tune->core; |
1480 | tune_flags = arm_selected_tune->flags; | |
1481 | current_tune = arm_selected_tune->tune; | |
e26053d1 | 1482 | |
0fd8c3ad SL |
1483 | if (target_fp16_format_name) |
1484 | { | |
1485 | for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++) | |
1486 | { | |
1487 | if (streq (all_fp16_formats[i].name, target_fp16_format_name)) | |
1488 | { | |
1489 | arm_fp16_format = all_fp16_formats[i].fp16_format_type; | |
1490 | break; | |
1491 | } | |
1492 | } | |
1493 | if (i == ARRAY_SIZE (all_fp16_formats)) | |
1494 | error ("invalid __fp16 format option: -mfp16-format=%s", | |
1495 | target_fp16_format_name); | |
1496 | } | |
1497 | else | |
1498 | arm_fp16_format = ARM_FP16_FORMAT_NONE; | |
1499 | ||
26272ba2 PB |
1500 | if (target_abi_name) |
1501 | { | |
1502 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1503 | { | |
1504 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1505 | { | |
1506 | arm_abi = arm_all_abis[i].abi_type; | |
1507 | break; | |
1508 | } | |
1509 | } | |
1510 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1511 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1512 | } | |
1513 | else | |
1514 | arm_abi = ARM_DEFAULT_ABI; | |
1515 | ||
f5a1b0d2 NC |
1516 | /* Make sure that the processor choice does not conflict with any of the |
1517 | other command line choices. */ | |
5b3e6663 PB |
1518 | if (TARGET_ARM && !(insn_flags & FL_NOTM)) |
1519 | error ("target CPU does not support ARM mode"); | |
1520 | ||
26272ba2 PB |
1521 | /* BPABI targets use linker tricks to allow interworking on cores |
1522 | without thumb support. */ | |
1523 | if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI)) | |
f5a1b0d2 | 1524 | { |
d4ee4d25 | 1525 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1526 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1527 | } |
f676971a | 1528 | |
d5b7b3ae RE |
1529 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1530 | { | |
d4ee4d25 | 1531 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1532 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1533 | } |
1534 | ||
1535 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1536 | { | |
d4ee4d25 | 1537 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1538 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1539 | } |
d19fb8e3 | 1540 | |
da8ce8be RE |
1541 | /* Callee super interworking implies thumb interworking. Adding |
1542 | this to the flags here simplifies the logic elsewhere. */ | |
1543 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
1544 | target_flags |= MASK_INTERWORK; | |
1545 | ||
d5b7b3ae RE |
1546 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1547 | from here where no function is being compiled currently. */ | |
c54c7322 | 1548 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1549 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1550 | |
1551 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1552 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1553 | |
1554 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
d4ee4d25 | 1555 | warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1556 | |
5895f793 | 1557 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1558 | { |
d4ee4d25 | 1559 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1560 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1561 | } |
f676971a | 1562 | |
2b835d68 | 1563 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1564 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1565 | |
2b835d68 | 1566 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1567 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1568 | |
2b835d68 | 1569 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1570 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1571 | |
d5b7b3ae RE |
1572 | /* If this target is normally configured to use APCS frames, warn if they |
1573 | are turned off and debugging is turned on. */ | |
1574 | if (TARGET_ARM | |
1575 | && write_symbols != NO_DEBUG | |
5895f793 | 1576 | && !TARGET_APCS_FRAME |
c54c7322 | 1577 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1578 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1579 | |
2b835d68 | 1580 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1581 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1582 | |
4912a07c | 1583 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1584 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1585 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1586 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1587 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1588 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1589 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1590 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
5b3e6663 | 1591 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; |
60bd3528 | 1592 | arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; |
5b3e6663 | 1593 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; |
9b66ebb1 | 1594 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1595 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1596 | |
1597 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1598 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
906668bb BS |
1599 | thumb_code = TARGET_ARM == 0; |
1600 | thumb1_code = TARGET_THUMB1 != 0; | |
abac3b49 | 1601 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1602 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1603 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5b3e6663 | 1604 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; |
7612f14d | 1605 | arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; |
5a9335ef | 1606 | |
f67358da PB |
1607 | /* If we are not using the default (ARM mode) section anchor offset |
1608 | ranges, then set the correct ranges now. */ | |
1609 | if (TARGET_THUMB1) | |
1610 | { | |
1611 | /* Thumb-1 LDR instructions cannot have negative offsets. | |
1612 | Permissible positive offset ranges are 5-bit (for byte loads), | |
1613 | 6-bit (for halfword loads), or 7-bit (for word loads). | |
1614 | Empirical results suggest a 7-bit anchor range gives the best | |
1615 | overall code size. */ | |
1616 | targetm.min_anchor_offset = 0; | |
1617 | targetm.max_anchor_offset = 127; | |
1618 | } | |
1619 | else if (TARGET_THUMB2) | |
1620 | { | |
1621 | /* The minimum is set such that the total size of the block | |
1622 | for a particular anchor is 248 + 1 + 4095 bytes, which is | |
1623 | divisible by eight, ensuring natural spacing of anchors. */ | |
1624 | targetm.min_anchor_offset = -248; | |
1625 | targetm.max_anchor_offset = 4095; | |
1626 | } | |
1627 | ||
68d560d4 RE |
1628 | /* V5 code we generate is completely interworking capable, so we turn off |
1629 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1630 | |
1631 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1632 | or GLD can get confused. This is a hack. */ | |
1633 | if (TARGET_INTERWORK) | |
1634 | arm_cpp_interwork = 1; | |
1635 | ||
68d560d4 | 1636 | if (arm_arch5) |
c54c7322 | 1637 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1638 | |
5848830f PB |
1639 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) |
1640 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1641 | ||
1642 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1643 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1644 | |
9b66ebb1 | 1645 | if (target_fpu_name == NULL && target_fpe_name != NULL) |
9b6b54e2 | 1646 | { |
9b66ebb1 PB |
1647 | if (streq (target_fpe_name, "2")) |
1648 | target_fpu_name = "fpe2"; | |
1649 | else if (streq (target_fpe_name, "3")) | |
1650 | target_fpu_name = "fpe3"; | |
1651 | else | |
1652 | error ("invalid floating point emulation option: -mfpe=%s", | |
1653 | target_fpe_name); | |
1654 | } | |
d79f3032 PB |
1655 | |
1656 | if (target_fpu_name == NULL) | |
2b835d68 | 1657 | { |
9b66ebb1 | 1658 | #ifdef FPUTYPE_DEFAULT |
d79f3032 | 1659 | target_fpu_name = FPUTYPE_DEFAULT; |
9b66ebb1 | 1660 | #else |
78011587 | 1661 | if (arm_arch_cirrus) |
d79f3032 | 1662 | target_fpu_name = "maverick"; |
9b66ebb1 | 1663 | else |
d79f3032 | 1664 | target_fpu_name = "fpe2"; |
9b66ebb1 | 1665 | #endif |
d79f3032 PB |
1666 | } |
1667 | ||
1668 | arm_fpu_desc = NULL; | |
1669 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1670 | { | |
1671 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1672 | { | |
1673 | arm_fpu_desc = &all_fpus[i]; | |
1674 | break; | |
1675 | } | |
1676 | } | |
b761dbe6 | 1677 | |
d79f3032 | 1678 | if (!arm_fpu_desc) |
b761dbe6 RE |
1679 | { |
1680 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
1681 | return; | |
1682 | } | |
d79f3032 PB |
1683 | |
1684 | switch (arm_fpu_desc->model) | |
1685 | { | |
1686 | case ARM_FP_MODEL_FPA: | |
1687 | if (arm_fpu_desc->rev == 2) | |
1688 | arm_fpu_attr = FPU_FPE2; | |
1689 | else if (arm_fpu_desc->rev == 3) | |
1690 | arm_fpu_attr = FPU_FPE3; | |
2b835d68 | 1691 | else |
d79f3032 PB |
1692 | arm_fpu_attr = FPU_FPA; |
1693 | break; | |
1694 | ||
1695 | case ARM_FP_MODEL_MAVERICK: | |
1696 | arm_fpu_attr = FPU_MAVERICK; | |
1697 | break; | |
1698 | ||
1699 | case ARM_FP_MODEL_VFP: | |
1700 | arm_fpu_attr = FPU_VFP; | |
1701 | break; | |
1702 | ||
1703 | default: | |
1704 | gcc_unreachable(); | |
9b66ebb1 PB |
1705 | } |
1706 | ||
1707 | if (target_float_abi_name != NULL) | |
1708 | { | |
1709 | /* The user specified a FP ABI. */ | |
1710 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1711 | { | |
1712 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1713 | { | |
1714 | arm_float_abi = all_float_abis[i].abi_type; | |
1715 | break; | |
1716 | } | |
1717 | } | |
1718 | if (i == ARRAY_SIZE (all_float_abis)) | |
1719 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1720 | target_float_abi_name); | |
2b835d68 | 1721 | } |
3d8532aa PB |
1722 | else |
1723 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1724 | |
0c48a567 | 1725 | if (TARGET_AAPCS_BASED |
d79f3032 | 1726 | && (arm_fpu_desc->model == ARM_FP_MODEL_FPA)) |
0c48a567 RR |
1727 | error ("FPA is unsupported in the AAPCS"); |
1728 | ||
3ce14752 | 1729 | if (TARGET_AAPCS_BASED) |
9df5bfe4 RR |
1730 | { |
1731 | if (TARGET_CALLER_INTERWORKING) | |
1732 | error ("AAPCS does not support -mcaller-super-interworking"); | |
1733 | else | |
1734 | if (TARGET_CALLEE_INTERWORKING) | |
1735 | error ("AAPCS does not support -mcallee-super-interworking"); | |
1736 | } | |
3ce14752 | 1737 | |
87b24aaf PB |
1738 | /* FPA and iWMMXt are incompatible because the insn encodings overlap. |
1739 | VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon | |
1740 | will ever exist. GCC makes no attempt to support this combination. */ | |
1741 | if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) | |
1742 | sorry ("iWMMXt and hardware floating point"); | |
1743 | ||
5b3e6663 PB |
1744 | /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ |
1745 | if (TARGET_THUMB2 && TARGET_IWMMXT) | |
1746 | sorry ("Thumb-2 iWMMXt"); | |
1747 | ||
0fd8c3ad SL |
1748 | /* __fp16 support currently assumes the core has ldrh. */ |
1749 | if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) | |
1750 | sorry ("__fp16 and no ldrh"); | |
1751 | ||
9b66ebb1 PB |
1752 | /* If soft-float is specified then don't use FPU. */ |
1753 | if (TARGET_SOFT_FLOAT) | |
d79f3032 | 1754 | arm_fpu_attr = FPU_NONE; |
f676971a | 1755 | |
390b17c2 RE |
1756 | if (TARGET_AAPCS_BASED) |
1757 | { | |
1758 | if (arm_abi == ARM_ABI_IWMMXT) | |
1759 | arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; | |
1760 | else if (arm_float_abi == ARM_FLOAT_ABI_HARD | |
1761 | && TARGET_HARD_FLOAT | |
1762 | && TARGET_VFP) | |
1763 | arm_pcs_default = ARM_PCS_AAPCS_VFP; | |
1764 | else | |
1765 | arm_pcs_default = ARM_PCS_AAPCS; | |
1766 | } | |
1767 | else | |
1768 | { | |
1769 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) | |
1770 | sorry ("-mfloat-abi=hard and VFP"); | |
1771 | ||
1772 | if (arm_abi == ARM_ABI_APCS) | |
1773 | arm_pcs_default = ARM_PCS_APCS; | |
1774 | else | |
1775 | arm_pcs_default = ARM_PCS_ATPCS; | |
1776 | } | |
1777 | ||
f5a1b0d2 NC |
1778 | /* For arm2/3 there is no need to do any scheduling if there is only |
1779 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 | 1780 | if ((TARGET_SOFT_FLOAT |
d79f3032 | 1781 | || (TARGET_FPA && arm_fpu_desc->rev)) |
ed0e6530 | 1782 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1783 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1784 | |
d3585b76 DJ |
1785 | if (target_thread_switch) |
1786 | { | |
1787 | if (strcmp (target_thread_switch, "soft") == 0) | |
1788 | target_thread_pointer = TP_SOFT; | |
1789 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1790 | target_thread_pointer = TP_AUTO; | |
1791 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1792 | target_thread_pointer = TP_CP15; | |
1793 | else | |
1794 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1795 | } | |
1796 | ||
1797 | /* Use the cp15 method if it is available. */ | |
1798 | if (target_thread_pointer == TP_AUTO) | |
1799 | { | |
87d05b44 | 1800 | if (arm_arch6k && !TARGET_THUMB1) |
d3585b76 DJ |
1801 | target_thread_pointer = TP_CP15; |
1802 | else | |
1803 | target_thread_pointer = TP_SOFT; | |
1804 | } | |
1805 | ||
5b3e6663 PB |
1806 | if (TARGET_HARD_TP && TARGET_THUMB1) |
1807 | error ("can not use -mtp=cp15 with 16-bit Thumb"); | |
d3585b76 | 1808 | |
5848830f | 1809 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1810 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1811 | arm_structure_size_boundary = 8; |
1812 | ||
b355a481 NC |
1813 | if (structure_size_string != NULL) |
1814 | { | |
1815 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1816 | |
1817 | if (size == 8 || size == 32 | |
1818 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1819 | arm_structure_size_boundary = size; |
1820 | else | |
d4ee4d25 | 1821 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1822 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1823 | } |
ed0e6530 | 1824 | |
9403b7f7 RS |
1825 | if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic) |
1826 | { | |
1827 | error ("RTP PIC is incompatible with Thumb"); | |
1828 | flag_pic = 0; | |
1829 | } | |
1830 | ||
c147eacb PB |
1831 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1832 | which keeps r9 available. The EABI specifies r9 as the PIC register. */ | |
1833 | if (flag_pic && TARGET_SINGLE_PIC_BASE) | |
9403b7f7 RS |
1834 | { |
1835 | if (TARGET_VXWORKS_RTP) | |
1836 | warning (0, "RTP PIC is incompatible with -msingle-pic-base"); | |
1837 | arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10; | |
1838 | } | |
1839 | ||
1840 | if (flag_pic && TARGET_VXWORKS_RTP) | |
1841 | arm_pic_register = 9; | |
c147eacb | 1842 | |
ed0e6530 PB |
1843 | if (arm_pic_register_string != NULL) |
1844 | { | |
5b43fed1 | 1845 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1846 | |
5895f793 | 1847 | if (!flag_pic) |
d4ee4d25 | 1848 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1849 | |
ed0e6530 | 1850 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1851 | else if (pic_register < 0 || call_used_regs[pic_register] |
1852 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1853 | || pic_register == STACK_POINTER_REGNUM | |
9403b7f7 RS |
1854 | || pic_register >= PC_REGNUM |
1855 | || (TARGET_VXWORKS_RTP | |
1856 | && (unsigned int) pic_register != arm_pic_register)) | |
c725bd79 | 1857 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1858 | else |
1859 | arm_pic_register = pic_register; | |
1860 | } | |
d5b7b3ae | 1861 | |
5fd42423 PB |
1862 | /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ |
1863 | if (fix_cm3_ldrd == 2) | |
1864 | { | |
12a0a4d4 | 1865 | if (arm_selected_cpu->core == cortexm3) |
5fd42423 PB |
1866 | fix_cm3_ldrd = 1; |
1867 | else | |
1868 | fix_cm3_ldrd = 0; | |
1869 | } | |
1870 | ||
4aef21c8 | 1871 | if (TARGET_THUMB1 && flag_schedule_insns) |
d5b7b3ae RE |
1872 | { |
1873 | /* Don't warn since it's on by default in -O2. */ | |
1874 | flag_schedule_insns = 0; | |
1875 | } | |
1876 | ||
f5a1b0d2 | 1877 | if (optimize_size) |
be03ccc9 | 1878 | { |
be03ccc9 | 1879 | /* If optimizing for size, bump the number of instructions that we |
d6b4baa4 | 1880 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1881 | max_insns_skipped = 6; |
1882 | } | |
1883 | else | |
1884 | { | |
be03ccc9 NP |
1885 | /* StrongARM has early execution of branches, so a sequence |
1886 | that is worth skipping is shorter. */ | |
abac3b49 | 1887 | if (arm_tune_strongarm) |
be03ccc9 NP |
1888 | max_insns_skipped = 3; |
1889 | } | |
92a432f4 | 1890 | |
70041f8a RE |
1891 | /* Hot/Cold partitioning is not currently supported, since we can't |
1892 | handle literal pool placement in that case. */ | |
1893 | if (flag_reorder_blocks_and_partition) | |
1894 | { | |
1895 | inform (input_location, | |
1896 | "-freorder-blocks-and-partition not supported on this architecture"); | |
1897 | flag_reorder_blocks_and_partition = 0; | |
1898 | flag_reorder_blocks = 1; | |
1899 | } | |
1900 | ||
ec3728ad MK |
1901 | if (!PARAM_SET_P (PARAM_GCSE_UNRESTRICTED_COST) |
1902 | && flag_pic) | |
1903 | /* Hoisting PIC address calculations more aggressively provides a small, | |
1904 | but measurable, size reduction for PIC code. Therefore, we decrease | |
1905 | the bar for unrestricted expression hoisting to the cost of PIC address | |
1906 | calculation, which is 2 instructions. */ | |
1907 | set_param_value ("gcse-unrestricted-cost", 2); | |
1908 | ||
92a432f4 RE |
1909 | /* Register global variables with the garbage collector. */ |
1910 | arm_add_gc_roots (); | |
1911 | } | |
1912 | ||
1913 | static void | |
e32bac5b | 1914 | arm_add_gc_roots (void) |
92a432f4 | 1915 | { |
c7319d87 RE |
1916 | gcc_obstack_init(&minipool_obstack); |
1917 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1918 | } |
cce8749e | 1919 | \f |
6d3d9133 NC |
1920 | /* A table of known ARM exception types. |
1921 | For use with the interrupt function attribute. */ | |
1922 | ||
1923 | typedef struct | |
1924 | { | |
8b60264b KG |
1925 | const char *const arg; |
1926 | const unsigned long return_value; | |
6d3d9133 NC |
1927 | } |
1928 | isr_attribute_arg; | |
1929 | ||
8b60264b | 1930 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1931 | { |
1932 | { "IRQ", ARM_FT_ISR }, | |
1933 | { "irq", ARM_FT_ISR }, | |
1934 | { "FIQ", ARM_FT_FIQ }, | |
1935 | { "fiq", ARM_FT_FIQ }, | |
1936 | { "ABORT", ARM_FT_ISR }, | |
1937 | { "abort", ARM_FT_ISR }, | |
1938 | { "ABORT", ARM_FT_ISR }, | |
1939 | { "abort", ARM_FT_ISR }, | |
1940 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1941 | { "undef", ARM_FT_EXCEPTION }, | |
1942 | { "SWI", ARM_FT_EXCEPTION }, | |
1943 | { "swi", ARM_FT_EXCEPTION }, | |
1944 | { NULL, ARM_FT_NORMAL } | |
1945 | }; | |
1946 | ||
1947 | /* Returns the (interrupt) function type of the current | |
1948 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1949 | ||
1950 | static unsigned long | |
e32bac5b | 1951 | arm_isr_value (tree argument) |
6d3d9133 | 1952 | { |
8b60264b | 1953 | const isr_attribute_arg * ptr; |
1d6e90ac | 1954 | const char * arg; |
6d3d9133 | 1955 | |
5b3e6663 PB |
1956 | if (!arm_arch_notm) |
1957 | return ARM_FT_NORMAL | ARM_FT_STACKALIGN; | |
1958 | ||
6d3d9133 NC |
1959 | /* No argument - default to IRQ. */ |
1960 | if (argument == NULL_TREE) | |
1961 | return ARM_FT_ISR; | |
1962 | ||
1963 | /* Get the value of the argument. */ | |
1964 | if (TREE_VALUE (argument) == NULL_TREE | |
1965 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1966 | return ARM_FT_UNKNOWN; | |
1967 | ||
1968 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1969 | ||
1970 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1971 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1972 | if (streq (arg, ptr->arg)) |
1973 | return ptr->return_value; | |
6d3d9133 | 1974 | |
05713b80 | 1975 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1976 | return ARM_FT_UNKNOWN; |
1977 | } | |
1978 | ||
1979 | /* Computes the type of the current function. */ | |
1980 | ||
1981 | static unsigned long | |
e32bac5b | 1982 | arm_compute_func_type (void) |
6d3d9133 NC |
1983 | { |
1984 | unsigned long type = ARM_FT_UNKNOWN; | |
1985 | tree a; | |
1986 | tree attr; | |
f676971a | 1987 | |
e6d29d15 | 1988 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
1989 | |
1990 | /* Decide if the current function is volatile. Such functions | |
1991 | never return, and many memory cycles can be saved by not storing | |
1992 | register values that will never be needed again. This optimization | |
1993 | was added to speed up context switching in a kernel application. */ | |
1994 | if (optimize > 0 | |
cf1955dc PB |
1995 | && (TREE_NOTHROW (current_function_decl) |
1996 | || !(flag_unwind_tables | |
1997 | || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) | |
6d3d9133 NC |
1998 | && TREE_THIS_VOLATILE (current_function_decl)) |
1999 | type |= ARM_FT_VOLATILE; | |
f676971a | 2000 | |
6de9cd9a | 2001 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
2002 | type |= ARM_FT_NESTED; |
2003 | ||
91d231cb | 2004 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 2005 | |
6d3d9133 NC |
2006 | a = lookup_attribute ("naked", attr); |
2007 | if (a != NULL_TREE) | |
2008 | type |= ARM_FT_NAKED; | |
2009 | ||
c9ca9b88 PB |
2010 | a = lookup_attribute ("isr", attr); |
2011 | if (a == NULL_TREE) | |
2012 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 2013 | |
c9ca9b88 PB |
2014 | if (a == NULL_TREE) |
2015 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 2016 | else |
c9ca9b88 | 2017 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 2018 | |
6d3d9133 NC |
2019 | return type; |
2020 | } | |
2021 | ||
2022 | /* Returns the type of the current function. */ | |
2023 | ||
2024 | unsigned long | |
e32bac5b | 2025 | arm_current_func_type (void) |
6d3d9133 NC |
2026 | { |
2027 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
2028 | cfun->machine->func_type = arm_compute_func_type (); | |
2029 | ||
2030 | return cfun->machine->func_type; | |
2031 | } | |
007e61c2 PB |
2032 | |
2033 | bool | |
2034 | arm_allocate_stack_slots_for_args (void) | |
2035 | { | |
2036 | /* Naked functions should not allocate stack slots for arguments. */ | |
2037 | return !IS_NAKED (arm_current_func_type ()); | |
2038 | } | |
2039 | ||
0ef9304b RH |
2040 | \f |
2041 | /* Output assembler code for a block containing the constant parts | |
2042 | of a trampoline, leaving space for the variable parts. | |
2043 | ||
2044 | On the ARM, (if r8 is the static chain regnum, and remembering that | |
2045 | referencing pc adds an offset of 8) the trampoline looks like: | |
2046 | ldr r8, [pc, #0] | |
2047 | ldr pc, [pc] | |
2048 | .word static chain value | |
2049 | .word function's address | |
2050 | XXX FIXME: When the trampoline returns, r8 will be clobbered. */ | |
2051 | ||
2052 | static void | |
2053 | arm_asm_trampoline_template (FILE *f) | |
2054 | { | |
2055 | if (TARGET_ARM) | |
2056 | { | |
2057 | asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", STATIC_CHAIN_REGNUM, PC_REGNUM); | |
2058 | asm_fprintf (f, "\tldr\t%r, [%r, #0]\n", PC_REGNUM, PC_REGNUM); | |
2059 | } | |
2060 | else if (TARGET_THUMB2) | |
2061 | { | |
2062 | /* The Thumb-2 trampoline is similar to the arm implementation. | |
2063 | Unlike 16-bit Thumb, we enter the stub in thumb mode. */ | |
2064 | asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", | |
2065 | STATIC_CHAIN_REGNUM, PC_REGNUM); | |
2066 | asm_fprintf (f, "\tldr.w\t%r, [%r, #4]\n", PC_REGNUM, PC_REGNUM); | |
2067 | } | |
2068 | else | |
2069 | { | |
2070 | ASM_OUTPUT_ALIGN (f, 2); | |
2071 | fprintf (f, "\t.code\t16\n"); | |
2072 | fprintf (f, ".Ltrampoline_start:\n"); | |
2073 | asm_fprintf (f, "\tpush\t{r0, r1}\n"); | |
2074 | asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM); | |
2075 | asm_fprintf (f, "\tmov\t%r, r0\n", STATIC_CHAIN_REGNUM); | |
2076 | asm_fprintf (f, "\tldr\tr0, [%r, #8]\n", PC_REGNUM); | |
2077 | asm_fprintf (f, "\tstr\tr0, [%r, #4]\n", SP_REGNUM); | |
2078 | asm_fprintf (f, "\tpop\t{r0, %r}\n", PC_REGNUM); | |
2079 | } | |
2080 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2081 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2082 | } | |
2083 | ||
2084 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
2085 | ||
2086 | static void | |
2087 | arm_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2088 | { | |
2089 | rtx fnaddr, mem, a_tramp; | |
2090 | ||
2091 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2092 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2093 | ||
2094 | mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 8 : 12); | |
2095 | emit_move_insn (mem, chain_value); | |
2096 | ||
2097 | mem = adjust_address (m_tramp, SImode, TARGET_32BIT ? 12 : 16); | |
2098 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2099 | emit_move_insn (mem, fnaddr); | |
2100 | ||
2101 | a_tramp = XEXP (m_tramp, 0); | |
2102 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), | |
2103 | LCT_NORMAL, VOIDmode, 2, a_tramp, Pmode, | |
2104 | plus_constant (a_tramp, TRAMPOLINE_SIZE), Pmode); | |
2105 | } | |
2106 | ||
2107 | /* Thumb trampolines should be entered in thumb mode, so set | |
2108 | the bottom bit of the address. */ | |
2109 | ||
2110 | static rtx | |
2111 | arm_trampoline_adjust_address (rtx addr) | |
2112 | { | |
2113 | if (TARGET_THUMB) | |
2114 | addr = expand_simple_binop (Pmode, IOR, addr, const1_rtx, | |
2115 | NULL, 0, OPTAB_LIB_WIDEN); | |
2116 | return addr; | |
2117 | } | |
6d3d9133 | 2118 | \f |
f676971a | 2119 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
2120 | If SIBLING is non-null, this is a test for a return before a sibling |
2121 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 2122 | |
ff9940b0 | 2123 | int |
a72d4945 | 2124 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
2125 | { |
2126 | int regno; | |
9b598fa0 | 2127 | unsigned int func_type; |
d5db54a1 | 2128 | unsigned long saved_int_regs; |
a72d4945 | 2129 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 2130 | arm_stack_offsets *offsets; |
ff9940b0 | 2131 | |
d5b7b3ae | 2132 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
2133 | if (!reload_completed) |
2134 | return 0; | |
efc2515b | 2135 | |
9b598fa0 RE |
2136 | func_type = arm_current_func_type (); |
2137 | ||
5b3e6663 | 2138 | /* Naked, volatile and stack alignment functions need special |
3a7731fd | 2139 | consideration. */ |
5b3e6663 | 2140 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN)) |
6d3d9133 | 2141 | return 0; |
06bea5aa | 2142 | |
a15908a4 PB |
2143 | /* So do interrupt functions that use the frame pointer and Thumb |
2144 | interrupt functions. */ | |
2145 | if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) | |
06bea5aa | 2146 | return 0; |
a72d4945 | 2147 | |
5848830f PB |
2148 | offsets = arm_get_frame_offsets (); |
2149 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 2150 | |
6d3d9133 | 2151 | /* As do variadic functions. */ |
38173d38 | 2152 | if (crtl->args.pretend_args_size |
3cb66fd7 | 2153 | || cfun->machine->uses_anonymous_args |
699a4925 | 2154 | /* Or if the function calls __builtin_eh_return () */ |
e3b5732b | 2155 | || crtl->calls_eh_return |
699a4925 | 2156 | /* Or if the function calls alloca */ |
e3b5732b | 2157 | || cfun->calls_alloca |
a72d4945 RE |
2158 | /* Or if there is a stack adjustment. However, if the stack pointer |
2159 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
ec6237e4 PB |
2160 | || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed |
2161 | && stack_adjust == 4))) | |
ff9940b0 RE |
2162 | return 0; |
2163 | ||
954954d1 | 2164 | saved_int_regs = offsets->saved_regs_mask; |
d5db54a1 | 2165 | |
a72d4945 RE |
2166 | /* Unfortunately, the insn |
2167 | ||
2168 | ldmib sp, {..., sp, ...} | |
2169 | ||
2170 | triggers a bug on most SA-110 based devices, such that the stack | |
2171 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 2172 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 2173 | the other registers, since that is never slower than executing |
f676971a | 2174 | another instruction. |
a72d4945 RE |
2175 | |
2176 | We test for !arm_arch5 here, because code for any architecture | |
2177 | less than this could potentially be run on one of the buggy | |
2178 | chips. */ | |
5b3e6663 | 2179 | if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) |
a72d4945 RE |
2180 | { |
2181 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 2182 | the default abi) ... */ |
a72d4945 RE |
2183 | if (!call_used_regs[3]) |
2184 | return 0; | |
2185 | ||
4f5dfed0 JC |
2186 | /* ... that it isn't being used for a return value ... */ |
2187 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
2188 | return 0; | |
2189 | ||
2190 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
2191 | if (sibling) |
2192 | { | |
e6d29d15 | 2193 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
2194 | |
2195 | if (find_regno_fusage (sibling, USE, 3)) | |
2196 | return 0; | |
2197 | } | |
2198 | ||
2199 | /* ... and that there are no call-saved registers in r0-r2 | |
2200 | (always true in the default ABI). */ | |
2201 | if (saved_int_regs & 0x7) | |
2202 | return 0; | |
2203 | } | |
2204 | ||
b111229a | 2205 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 | 2206 | stacked. */ |
a15908a4 | 2207 | if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type)) |
b36ba79f | 2208 | return 0; |
d5db54a1 RE |
2209 | |
2210 | /* On StrongARM, conditional returns are expensive if they aren't | |
2211 | taken and multiple registers have been stacked. */ | |
abac3b49 | 2212 | if (iscond && arm_tune_strongarm) |
6ed30148 | 2213 | { |
f676971a | 2214 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
2215 | conditional-load instruction, that's not expensive. */ |
2216 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
2217 | return 0; | |
6ed30148 | 2218 | |
020a4035 RE |
2219 | if (flag_pic |
2220 | && arm_pic_register != INVALID_REGNUM | |
6fb5fa3c | 2221 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b111229a | 2222 | return 0; |
6ed30148 | 2223 | } |
d5db54a1 RE |
2224 | |
2225 | /* If there are saved registers but the LR isn't saved, then we need | |
2226 | two instructions for the return. */ | |
2227 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
2228 | return 0; | |
2229 | ||
3b684012 | 2230 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 2231 | since this also requires an insn. */ |
9b66ebb1 PB |
2232 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
2233 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 2234 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
9b66ebb1 PB |
2235 | return 0; |
2236 | ||
2237 | /* Likewise VFP regs. */ | |
2238 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
2239 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
6fb5fa3c | 2240 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
d5b7b3ae | 2241 | return 0; |
ff9940b0 | 2242 | |
5a9335ef NC |
2243 | if (TARGET_REALLY_IWMMXT) |
2244 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
6fb5fa3c | 2245 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5a9335ef NC |
2246 | return 0; |
2247 | ||
ff9940b0 RE |
2248 | return 1; |
2249 | } | |
2250 | ||
cce8749e CH |
2251 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
2252 | ||
2253 | int | |
e32bac5b | 2254 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 2255 | { |
4642ccb1 | 2256 | int lowbit; |
e0b92319 | 2257 | |
f676971a | 2258 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 2259 | be all zero, or all one. */ |
30cf4896 KG |
2260 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
2261 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
2262 | != ((~(unsigned HOST_WIDE_INT) 0) | |
2263 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 2264 | return FALSE; |
f676971a | 2265 | |
4642ccb1 | 2266 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 2267 | |
4642ccb1 RE |
2268 | /* Fast return for 0 and small values. We must do this for zero, since |
2269 | the code below can't handle that one case. */ | |
2270 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
2271 | return TRUE; |
2272 | ||
5b3e6663 PB |
2273 | /* Get the number of trailing zeros. */ |
2274 | lowbit = ffs((int) i) - 1; | |
2275 | ||
2276 | /* Only even shifts are allowed in ARM mode so round down to the | |
2277 | nearest even number. */ | |
2278 | if (TARGET_ARM) | |
2279 | lowbit &= ~1; | |
4642ccb1 RE |
2280 | |
2281 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
2282 | return TRUE; | |
5b3e6663 PB |
2283 | |
2284 | if (TARGET_ARM) | |
2285 | { | |
2286 | /* Allow rotated constants in ARM mode. */ | |
2287 | if (lowbit <= 4 | |
4642ccb1 RE |
2288 | && ((i & ~0xc000003f) == 0 |
2289 | || (i & ~0xf000000f) == 0 | |
2290 | || (i & ~0xfc000003) == 0)) | |
5b3e6663 PB |
2291 | return TRUE; |
2292 | } | |
2293 | else | |
2294 | { | |
2295 | HOST_WIDE_INT v; | |
2296 | ||
2297 | /* Allow repeated pattern. */ | |
2298 | v = i & 0xff; | |
2299 | v |= v << 16; | |
2300 | if (i == v || i == (v | (v << 8))) | |
2301 | return TRUE; | |
2302 | } | |
cce8749e | 2303 | |
f3bb6135 RE |
2304 | return FALSE; |
2305 | } | |
cce8749e | 2306 | |
6354dc9b | 2307 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 2308 | static int |
e32bac5b | 2309 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
2310 | { |
2311 | if (const_ok_for_arm (i)) | |
2312 | return 1; | |
2313 | ||
2314 | switch (code) | |
2315 | { | |
2316 | case PLUS: | |
d5a0a47b RE |
2317 | case COMPARE: |
2318 | case EQ: | |
2319 | case NE: | |
2320 | case GT: | |
2321 | case LE: | |
2322 | case LT: | |
2323 | case GE: | |
2324 | case GEU: | |
2325 | case LTU: | |
2326 | case GTU: | |
2327 | case LEU: | |
2328 | case UNORDERED: | |
2329 | case ORDERED: | |
2330 | case UNEQ: | |
2331 | case UNGE: | |
2332 | case UNLT: | |
2333 | case UNGT: | |
2334 | case UNLE: | |
e2c671ba RE |
2335 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); |
2336 | ||
2337 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
2338 | case XOR: | |
a7994a57 RR |
2339 | return 0; |
2340 | ||
e2c671ba | 2341 | case IOR: |
a7994a57 RR |
2342 | if (TARGET_THUMB2) |
2343 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
e2c671ba RE |
2344 | return 0; |
2345 | ||
2346 | case AND: | |
2347 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
2348 | ||
2349 | default: | |
e6d29d15 | 2350 | gcc_unreachable (); |
e2c671ba RE |
2351 | } |
2352 | } | |
2353 | ||
2354 | /* Emit a sequence of insns to handle a large constant. | |
2355 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
2356 | IOR, AND, XOR, MINUS; | |
2357 | MODE is the mode in which the operation is being performed; | |
2358 | VAL is the integer to operate on; | |
2359 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
2360 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
2361 | either produce a simpler sequence, or we will want to cse the values. |
2362 | Return value is the number of insns emitted. */ | |
e2c671ba | 2363 | |
5b3e6663 | 2364 | /* ??? Tweak this for thumb2. */ |
e2c671ba | 2365 | int |
a406f566 | 2366 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 2367 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 2368 | { |
a406f566 MM |
2369 | rtx cond; |
2370 | ||
2371 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2372 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
2373 | else | |
2374 | cond = NULL_RTX; | |
2375 | ||
2b835d68 RE |
2376 | if (subtargets || code == SET |
2377 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
2378 | && REGNO (target) != REGNO (source))) | |
2379 | { | |
4b632bf1 | 2380 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 2381 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
2382 | them in-line, regardless of the cost. This is only likely to |
2383 | be more costly on chips that have load delay slots and we are | |
2384 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
2385 | occurred before the final instruction emission). |
2386 | ||
2387 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 2388 | */ |
5895f793 | 2389 | if (!after_arm_reorg |
a406f566 | 2390 | && !cond |
f676971a | 2391 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 2392 | 1, 0) |
1b78f575 RE |
2393 | > (arm_constant_limit (optimize_function_for_size_p (cfun)) |
2394 | + (code != SET)))) | |
2b835d68 RE |
2395 | { |
2396 | if (code == SET) | |
2397 | { | |
2398 | /* Currently SET is the only monadic value for CODE, all | |
2399 | the rest are diadic. */ | |
571191af PB |
2400 | if (TARGET_USE_MOVT) |
2401 | arm_emit_movpair (target, GEN_INT (val)); | |
2402 | else | |
2403 | emit_set_insn (target, GEN_INT (val)); | |
2404 | ||
2b835d68 RE |
2405 | return 1; |
2406 | } | |
2407 | else | |
2408 | { | |
2409 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
2410 | ||
571191af PB |
2411 | if (TARGET_USE_MOVT) |
2412 | arm_emit_movpair (temp, GEN_INT (val)); | |
2413 | else | |
2414 | emit_set_insn (temp, GEN_INT (val)); | |
2415 | ||
2b835d68 RE |
2416 | /* For MINUS, the value is subtracted from, since we never |
2417 | have subtraction of a constant. */ | |
2418 | if (code == MINUS) | |
d66437c5 | 2419 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 2420 | else |
d66437c5 RE |
2421 | emit_set_insn (target, |
2422 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
2423 | return 2; |
2424 | } | |
2425 | } | |
2426 | } | |
2427 | ||
f676971a | 2428 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 2429 | 1); |
2b835d68 RE |
2430 | } |
2431 | ||
162e4591 RE |
2432 | /* Return the number of instructions required to synthesize the given |
2433 | constant, if we start emitting them from bit-position I. */ | |
ceebdb09 | 2434 | static int |
e32bac5b | 2435 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
2436 | { |
2437 | HOST_WIDE_INT temp1; | |
162e4591 | 2438 | int step_size = TARGET_ARM ? 2 : 1; |
ceebdb09 | 2439 | int num_insns = 0; |
162e4591 RE |
2440 | |
2441 | gcc_assert (TARGET_ARM || i == 0); | |
2442 | ||
ceebdb09 PB |
2443 | do |
2444 | { | |
2445 | int end; | |
f676971a | 2446 | |
ceebdb09 PB |
2447 | if (i <= 0) |
2448 | i += 32; | |
162e4591 | 2449 | if (remainder & (((1 << step_size) - 1) << (i - step_size))) |
ceebdb09 PB |
2450 | { |
2451 | end = i - 8; | |
2452 | if (end < 0) | |
2453 | end += 32; | |
2454 | temp1 = remainder & ((0x0ff << end) | |
2455 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2456 | remainder &= ~temp1; | |
2457 | num_insns++; | |
162e4591 | 2458 | i -= 8 - step_size; |
ceebdb09 | 2459 | } |
162e4591 | 2460 | i -= step_size; |
ceebdb09 PB |
2461 | } while (remainder); |
2462 | return num_insns; | |
2463 | } | |
2464 | ||
162e4591 | 2465 | static int |
90e77553 | 2466 | find_best_start (unsigned HOST_WIDE_INT remainder) |
162e4591 RE |
2467 | { |
2468 | int best_consecutive_zeros = 0; | |
2469 | int i; | |
2470 | int best_start = 0; | |
2471 | ||
2472 | /* If we aren't targetting ARM, the best place to start is always at | |
2473 | the bottom. */ | |
2474 | if (! TARGET_ARM) | |
2475 | return 0; | |
2476 | ||
2477 | for (i = 0; i < 32; i += 2) | |
2478 | { | |
2479 | int consecutive_zeros = 0; | |
2480 | ||
2481 | if (!(remainder & (3 << i))) | |
2482 | { | |
2483 | while ((i < 32) && !(remainder & (3 << i))) | |
2484 | { | |
2485 | consecutive_zeros += 2; | |
2486 | i += 2; | |
2487 | } | |
2488 | if (consecutive_zeros > best_consecutive_zeros) | |
2489 | { | |
2490 | best_consecutive_zeros = consecutive_zeros; | |
2491 | best_start = i - consecutive_zeros; | |
2492 | } | |
2493 | i -= 2; | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | /* So long as it won't require any more insns to do so, it's | |
2498 | desirable to emit a small constant (in bits 0...9) in the last | |
2499 | insn. This way there is more chance that it can be combined with | |
2500 | a later addressing insn to form a pre-indexed load or store | |
2501 | operation. Consider: | |
2502 | ||
2503 | *((volatile int *)0xe0000100) = 1; | |
2504 | *((volatile int *)0xe0000110) = 2; | |
2505 | ||
2506 | We want this to wind up as: | |
2507 | ||
2508 | mov rA, #0xe0000000 | |
2509 | mov rB, #1 | |
2510 | str rB, [rA, #0x100] | |
2511 | mov rB, #2 | |
2512 | str rB, [rA, #0x110] | |
2513 | ||
2514 | rather than having to synthesize both large constants from scratch. | |
2515 | ||
2516 | Therefore, we calculate how many insns would be required to emit | |
2517 | the constant starting from `best_start', and also starting from | |
2518 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't | |
2519 | yield a shorter sequence, we may as well use zero. */ | |
2520 | if (best_start != 0 | |
2521 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
2522 | && (count_insns_for_constant (remainder, 0) <= | |
2523 | count_insns_for_constant (remainder, best_start))) | |
2524 | best_start = 0; | |
2525 | ||
2526 | return best_start; | |
2527 | } | |
2528 | ||
a406f566 MM |
2529 | /* Emit an instruction with the indicated PATTERN. If COND is |
2530 | non-NULL, conditionalize the execution of the instruction on COND | |
2531 | being true. */ | |
2532 | ||
2533 | static void | |
2534 | emit_constant_insn (rtx cond, rtx pattern) | |
2535 | { | |
2536 | if (cond) | |
2537 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
2538 | emit_insn (pattern); | |
2539 | } | |
2540 | ||
2b835d68 RE |
2541 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
2542 | RTL generation. */ | |
5b3e6663 | 2543 | /* ??? This needs more work for thumb2. */ |
1d6e90ac | 2544 | |
d5b7b3ae | 2545 | static int |
a406f566 | 2546 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
2547 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
2548 | int generate) | |
e2c671ba | 2549 | { |
e2c671ba RE |
2550 | int can_invert = 0; |
2551 | int can_negate = 0; | |
162e4591 | 2552 | int final_invert = 0; |
e2c671ba | 2553 | int can_negate_initial = 0; |
e2c671ba RE |
2554 | int i; |
2555 | int num_bits_set = 0; | |
2556 | int set_sign_bit_copies = 0; | |
2557 | int clear_sign_bit_copies = 0; | |
2558 | int clear_zero_bit_copies = 0; | |
2559 | int set_zero_bit_copies = 0; | |
2560 | int insns = 0; | |
e2c671ba | 2561 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 2562 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
162e4591 | 2563 | int step_size = TARGET_ARM ? 2 : 1; |
e2c671ba | 2564 | |
d5b7b3ae | 2565 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
2566 | check for degenerate cases; these can occur when DImode operations |
2567 | are split. */ | |
2568 | switch (code) | |
2569 | { | |
2570 | case SET: | |
2571 | can_invert = 1; | |
e2c671ba RE |
2572 | can_negate = 1; |
2573 | break; | |
2574 | ||
2575 | case PLUS: | |
2576 | can_negate = 1; | |
2577 | can_negate_initial = 1; | |
2578 | break; | |
2579 | ||
2580 | case IOR: | |
30cf4896 | 2581 | if (remainder == 0xffffffff) |
e2c671ba | 2582 | { |
2b835d68 | 2583 | if (generate) |
a406f566 MM |
2584 | emit_constant_insn (cond, |
2585 | gen_rtx_SET (VOIDmode, target, | |
2586 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
2587 | return 1; |
2588 | } | |
a7994a57 | 2589 | |
e2c671ba RE |
2590 | if (remainder == 0) |
2591 | { | |
2592 | if (reload_completed && rtx_equal_p (target, source)) | |
2593 | return 0; | |
a7994a57 | 2594 | |
2b835d68 | 2595 | if (generate) |
a406f566 MM |
2596 | emit_constant_insn (cond, |
2597 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2598 | return 1; |
2599 | } | |
a7994a57 RR |
2600 | |
2601 | if (TARGET_THUMB2) | |
2602 | can_invert = 1; | |
e2c671ba RE |
2603 | break; |
2604 | ||
2605 | case AND: | |
2606 | if (remainder == 0) | |
2607 | { | |
2b835d68 | 2608 | if (generate) |
a406f566 MM |
2609 | emit_constant_insn (cond, |
2610 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
2611 | return 1; |
2612 | } | |
30cf4896 | 2613 | if (remainder == 0xffffffff) |
e2c671ba RE |
2614 | { |
2615 | if (reload_completed && rtx_equal_p (target, source)) | |
2616 | return 0; | |
2b835d68 | 2617 | if (generate) |
a406f566 MM |
2618 | emit_constant_insn (cond, |
2619 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2620 | return 1; |
2621 | } | |
2622 | can_invert = 1; | |
2623 | break; | |
2624 | ||
2625 | case XOR: | |
2626 | if (remainder == 0) | |
2627 | { | |
2628 | if (reload_completed && rtx_equal_p (target, source)) | |
2629 | return 0; | |
2b835d68 | 2630 | if (generate) |
a406f566 MM |
2631 | emit_constant_insn (cond, |
2632 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2633 | return 1; |
2634 | } | |
e0b92319 | 2635 | |
162e4591 RE |
2636 | if (remainder == 0xffffffff) |
2637 | { | |
2638 | if (generate) | |
2639 | emit_constant_insn (cond, | |
2640 | gen_rtx_SET (VOIDmode, target, | |
2641 | gen_rtx_NOT (mode, source))); | |
2642 | return 1; | |
2643 | } | |
2644 | break; | |
e2c671ba RE |
2645 | |
2646 | case MINUS: | |
2647 | /* We treat MINUS as (val - source), since (source - val) is always | |
2648 | passed as (source + (-val)). */ | |
2649 | if (remainder == 0) | |
2650 | { | |
2b835d68 | 2651 | if (generate) |
a406f566 MM |
2652 | emit_constant_insn (cond, |
2653 | gen_rtx_SET (VOIDmode, target, | |
2654 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
2655 | return 1; |
2656 | } | |
2657 | if (const_ok_for_arm (val)) | |
2658 | { | |
2b835d68 | 2659 | if (generate) |
a406f566 | 2660 | emit_constant_insn (cond, |
f676971a | 2661 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2662 | gen_rtx_MINUS (mode, GEN_INT (val), |
2663 | source))); | |
e2c671ba RE |
2664 | return 1; |
2665 | } | |
2666 | can_negate = 1; | |
2667 | ||
2668 | break; | |
2669 | ||
2670 | default: | |
e6d29d15 | 2671 | gcc_unreachable (); |
e2c671ba RE |
2672 | } |
2673 | ||
6354dc9b | 2674 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
2675 | if (const_ok_for_arm (val) |
2676 | || (can_negate_initial && const_ok_for_arm (-val)) | |
2677 | || (can_invert && const_ok_for_arm (~val))) | |
2678 | { | |
2b835d68 | 2679 | if (generate) |
a406f566 MM |
2680 | emit_constant_insn (cond, |
2681 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 2682 | (source |
a406f566 MM |
2683 | ? gen_rtx_fmt_ee (code, mode, source, |
2684 | GEN_INT (val)) | |
2685 | : GEN_INT (val)))); | |
e2c671ba RE |
2686 | return 1; |
2687 | } | |
2688 | ||
e2c671ba | 2689 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 2690 | optimizations. */ |
a7994a57 | 2691 | /* Count number of leading zeros. */ |
e2c671ba RE |
2692 | for (i = 31; i >= 0; i--) |
2693 | { | |
2694 | if ((remainder & (1 << i)) == 0) | |
2695 | clear_sign_bit_copies++; | |
2696 | else | |
2697 | break; | |
2698 | } | |
2699 | ||
a7994a57 | 2700 | /* Count number of leading 1's. */ |
e2c671ba RE |
2701 | for (i = 31; i >= 0; i--) |
2702 | { | |
2703 | if ((remainder & (1 << i)) != 0) | |
2704 | set_sign_bit_copies++; | |
2705 | else | |
2706 | break; | |
2707 | } | |
2708 | ||
a7994a57 | 2709 | /* Count number of trailing zero's. */ |
e2c671ba RE |
2710 | for (i = 0; i <= 31; i++) |
2711 | { | |
2712 | if ((remainder & (1 << i)) == 0) | |
2713 | clear_zero_bit_copies++; | |
2714 | else | |
2715 | break; | |
2716 | } | |
2717 | ||
a7994a57 | 2718 | /* Count number of trailing 1's. */ |
e2c671ba RE |
2719 | for (i = 0; i <= 31; i++) |
2720 | { | |
2721 | if ((remainder & (1 << i)) != 0) | |
2722 | set_zero_bit_copies++; | |
2723 | else | |
2724 | break; | |
2725 | } | |
2726 | ||
2727 | switch (code) | |
2728 | { | |
2729 | case SET: | |
5b3e6663 PB |
2730 | /* See if we can use movw. */ |
2731 | if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0) | |
2732 | { | |
2733 | if (generate) | |
2734 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
2735 | GEN_INT (val))); | |
2736 | return 1; | |
2737 | } | |
2738 | ||
e2c671ba RE |
2739 | /* See if we can do this by sign_extending a constant that is known |
2740 | to be negative. This is a good, way of doing it, since the shift | |
2741 | may well merge into a subsequent insn. */ | |
2742 | if (set_sign_bit_copies > 1) | |
2743 | { | |
2744 | if (const_ok_for_arm | |
f676971a | 2745 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
2746 | << (set_sign_bit_copies - 1)))) |
2747 | { | |
2b835d68 RE |
2748 | if (generate) |
2749 | { | |
d499463f | 2750 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 2751 | emit_constant_insn (cond, |
f676971a | 2752 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
2753 | GEN_INT (temp1))); |
2754 | emit_constant_insn (cond, | |
f676971a | 2755 | gen_ashrsi3 (target, new_src, |
a406f566 | 2756 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2757 | } |
e2c671ba RE |
2758 | return 2; |
2759 | } | |
2760 | /* For an inverted constant, we will need to set the low bits, | |
2761 | these will be shifted out of harm's way. */ | |
2762 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
2763 | if (const_ok_for_arm (~temp1)) | |
2764 | { | |
2b835d68 RE |
2765 | if (generate) |
2766 | { | |
d499463f | 2767 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
2768 | emit_constant_insn (cond, |
2769 | gen_rtx_SET (VOIDmode, new_src, | |
2770 | GEN_INT (temp1))); | |
2771 | emit_constant_insn (cond, | |
f676971a | 2772 | gen_ashrsi3 (target, new_src, |
a406f566 | 2773 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2774 | } |
e2c671ba RE |
2775 | return 2; |
2776 | } | |
2777 | } | |
2778 | ||
c87e6352 RE |
2779 | /* See if we can calculate the value as the difference between two |
2780 | valid immediates. */ | |
2781 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
2782 | { | |
2783 | int topshift = clear_sign_bit_copies & ~1; | |
2784 | ||
fa2c88a0 RE |
2785 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
2786 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
2787 | |
2788 | /* If temp1 is zero, then that means the 9 most significant | |
2789 | bits of remainder were 1 and we've caused it to overflow. | |
2790 | When topshift is 0 we don't need to do anything since we | |
2791 | can borrow from 'bit 32'. */ | |
2792 | if (temp1 == 0 && topshift != 0) | |
2793 | temp1 = 0x80000000 >> (topshift - 1); | |
2794 | ||
fa2c88a0 | 2795 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 2796 | |
c87e6352 RE |
2797 | if (const_ok_for_arm (temp2)) |
2798 | { | |
2799 | if (generate) | |
2800 | { | |
2801 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
2802 | emit_constant_insn (cond, | |
2803 | gen_rtx_SET (VOIDmode, new_src, | |
2804 | GEN_INT (temp1))); | |
2805 | emit_constant_insn (cond, | |
2806 | gen_addsi3 (target, new_src, | |
2807 | GEN_INT (-temp2))); | |
2808 | } | |
2809 | ||
2810 | return 2; | |
2811 | } | |
2812 | } | |
2813 | ||
e2c671ba RE |
2814 | /* See if we can generate this by setting the bottom (or the top) |
2815 | 16 bits, and then shifting these into the other half of the | |
2816 | word. We only look for the simplest cases, to do more would cost | |
2817 | too much. Be careful, however, not to generate this when the | |
2818 | alternative would take fewer insns. */ | |
30cf4896 | 2819 | if (val & 0xffff0000) |
e2c671ba | 2820 | { |
30cf4896 | 2821 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2822 | temp2 = remainder & 0x0000ffff; |
2823 | ||
6354dc9b | 2824 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2825 | for (i = 9; i < 24; i++) |
2826 | { | |
30cf4896 | 2827 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2828 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2829 | { |
d499463f RE |
2830 | rtx new_src = (subtargets |
2831 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2832 | : target); | |
a406f566 | 2833 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2834 | source, subtargets, generate); |
e2c671ba | 2835 | source = new_src; |
2b835d68 | 2836 | if (generate) |
f676971a | 2837 | emit_constant_insn |
a406f566 MM |
2838 | (cond, |
2839 | gen_rtx_SET | |
2840 | (VOIDmode, target, | |
2841 | gen_rtx_IOR (mode, | |
2842 | gen_rtx_ASHIFT (mode, source, | |
2843 | GEN_INT (i)), | |
2844 | source))); | |
e2c671ba RE |
2845 | return insns + 1; |
2846 | } | |
2847 | } | |
2848 | ||
6354dc9b | 2849 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
2850 | for (i = 17; i < 24; i++) |
2851 | { | |
2852 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 2853 | && !const_ok_for_arm (temp1)) |
e2c671ba | 2854 | { |
d499463f RE |
2855 | rtx new_src = (subtargets |
2856 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2857 | : target); | |
a406f566 | 2858 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 2859 | source, subtargets, generate); |
e2c671ba | 2860 | source = new_src; |
2b835d68 | 2861 | if (generate) |
a406f566 MM |
2862 | emit_constant_insn |
2863 | (cond, | |
2864 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
2865 | gen_rtx_IOR |
2866 | (mode, | |
2867 | gen_rtx_LSHIFTRT (mode, source, | |
2868 | GEN_INT (i)), | |
2869 | source))); | |
e2c671ba RE |
2870 | return insns + 1; |
2871 | } | |
2872 | } | |
2873 | } | |
2874 | break; | |
2875 | ||
2876 | case IOR: | |
2877 | case XOR: | |
7b64da89 RE |
2878 | /* If we have IOR or XOR, and the constant can be loaded in a |
2879 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
2880 | then this can be done in two instructions instead of 3-4. */ |
2881 | if (subtargets | |
d499463f | 2882 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 2883 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 2884 | { |
5895f793 | 2885 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2886 | { |
2b835d68 RE |
2887 | if (generate) |
2888 | { | |
2889 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 2890 | |
a406f566 | 2891 | emit_constant_insn (cond, |
f676971a | 2892 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
2893 | GEN_INT (val))); |
2894 | emit_constant_insn (cond, | |
f676971a | 2895 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2896 | gen_rtx_fmt_ee (code, mode, |
2897 | source, sub))); | |
2b835d68 | 2898 | } |
e2c671ba RE |
2899 | return 2; |
2900 | } | |
2901 | } | |
2902 | ||
2903 | if (code == XOR) | |
2904 | break; | |
2905 | ||
a7994a57 RR |
2906 | /* Convert. |
2907 | x = y | constant ( which is composed of set_sign_bit_copies of leading 1s | |
2908 | and the remainder 0s for e.g. 0xfff00000) | |
2909 | x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies) | |
2910 | ||
2911 | This can be done in 2 instructions by using shifts with mov or mvn. | |
2912 | e.g. for | |
2913 | x = x | 0xfff00000; | |
2914 | we generate. | |
2915 | mvn r0, r0, asl #12 | |
2916 | mvn r0, r0, lsr #12 */ | |
e2c671ba RE |
2917 | if (set_sign_bit_copies > 8 |
2918 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
2919 | { | |
2b835d68 RE |
2920 | if (generate) |
2921 | { | |
2922 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2923 | rtx shift = GEN_INT (set_sign_bit_copies); | |
2924 | ||
f676971a | 2925 | emit_constant_insn |
a406f566 MM |
2926 | (cond, |
2927 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2928 | gen_rtx_NOT (mode, |
a406f566 | 2929 | gen_rtx_ASHIFT (mode, |
f676971a | 2930 | source, |
a406f566 | 2931 | shift)))); |
f676971a | 2932 | emit_constant_insn |
a406f566 MM |
2933 | (cond, |
2934 | gen_rtx_SET (VOIDmode, target, | |
2935 | gen_rtx_NOT (mode, | |
2936 | gen_rtx_LSHIFTRT (mode, sub, | |
2937 | shift)))); | |
2b835d68 | 2938 | } |
e2c671ba RE |
2939 | return 2; |
2940 | } | |
2941 | ||
a7994a57 RR |
2942 | /* Convert |
2943 | x = y | constant (which has set_zero_bit_copies number of trailing ones). | |
2944 | to | |
2945 | x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies). | |
2946 | ||
2947 | For eg. r0 = r0 | 0xfff | |
2948 | mvn r0, r0, lsr #12 | |
2949 | mvn r0, r0, asl #12 | |
2950 | ||
2951 | */ | |
e2c671ba RE |
2952 | if (set_zero_bit_copies > 8 |
2953 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
2954 | { | |
2b835d68 RE |
2955 | if (generate) |
2956 | { | |
2957 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2958 | rtx shift = GEN_INT (set_zero_bit_copies); | |
2959 | ||
a406f566 MM |
2960 | emit_constant_insn |
2961 | (cond, | |
2962 | gen_rtx_SET (VOIDmode, sub, | |
2963 | gen_rtx_NOT (mode, | |
2964 | gen_rtx_LSHIFTRT (mode, | |
2965 | source, | |
2966 | shift)))); | |
f676971a | 2967 | emit_constant_insn |
a406f566 MM |
2968 | (cond, |
2969 | gen_rtx_SET (VOIDmode, target, | |
2970 | gen_rtx_NOT (mode, | |
2971 | gen_rtx_ASHIFT (mode, sub, | |
2972 | shift)))); | |
2b835d68 | 2973 | } |
e2c671ba RE |
2974 | return 2; |
2975 | } | |
2976 | ||
a7994a57 RR |
2977 | /* This will never be reached for Thumb2 because orn is a valid |
2978 | instruction. This is for Thumb1 and the ARM 32 bit cases. | |
2979 | ||
2980 | x = y | constant (such that ~constant is a valid constant) | |
2981 | Transform this to | |
2982 | x = ~(~y & ~constant). | |
2983 | */ | |
5895f793 | 2984 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2985 | { |
2b835d68 RE |
2986 | if (generate) |
2987 | { | |
2988 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
2989 | emit_constant_insn (cond, |
2990 | gen_rtx_SET (VOIDmode, sub, | |
2991 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
2992 | source = sub; |
2993 | if (subtargets) | |
2994 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
2995 | emit_constant_insn (cond, |
2996 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2997 | gen_rtx_AND (mode, source, |
a406f566 MM |
2998 | GEN_INT (temp1)))); |
2999 | emit_constant_insn (cond, | |
3000 | gen_rtx_SET (VOIDmode, target, | |
3001 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 3002 | } |
e2c671ba RE |
3003 | return 3; |
3004 | } | |
3005 | break; | |
3006 | ||
3007 | case AND: | |
3008 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
3009 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
3010 | { | |
30cf4896 | 3011 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 3012 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 3013 | & 0xffffffff); |
e2c671ba | 3014 | |
30cf4896 | 3015 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 3016 | { |
2b835d68 RE |
3017 | if (generate) |
3018 | { | |
d499463f | 3019 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 3020 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 3021 | remainder | shift_mask, |
d499463f RE |
3022 | new_src, source, subtargets, 1); |
3023 | source = new_src; | |
2b835d68 RE |
3024 | } |
3025 | else | |
d499463f RE |
3026 | { |
3027 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
3028 | insns = arm_gen_constant (AND, mode, cond, |
3029 | remainder | shift_mask, | |
d499463f RE |
3030 | targ, source, subtargets, 0); |
3031 | } | |
2b835d68 RE |
3032 | } |
3033 | ||
3034 | if (generate) | |
3035 | { | |
d499463f RE |
3036 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3037 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
3038 | ||
3039 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
3040 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
3041 | } |
3042 | ||
e2c671ba RE |
3043 | return insns + 2; |
3044 | } | |
3045 | ||
3046 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
3047 | { | |
3048 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 3049 | |
30cf4896 | 3050 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 3051 | { |
2b835d68 RE |
3052 | if (generate) |
3053 | { | |
d499463f RE |
3054 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3055 | ||
a406f566 MM |
3056 | insns = arm_gen_constant (AND, mode, cond, |
3057 | remainder | shift_mask, | |
d499463f RE |
3058 | new_src, source, subtargets, 1); |
3059 | source = new_src; | |
2b835d68 RE |
3060 | } |
3061 | else | |
d499463f RE |
3062 | { |
3063 | rtx targ = subtargets ? NULL_RTX : target; | |
3064 | ||
a406f566 MM |
3065 | insns = arm_gen_constant (AND, mode, cond, |
3066 | remainder | shift_mask, | |
d499463f RE |
3067 | targ, source, subtargets, 0); |
3068 | } | |
2b835d68 RE |
3069 | } |
3070 | ||
3071 | if (generate) | |
3072 | { | |
d499463f RE |
3073 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
3074 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
3075 | ||
3076 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
3077 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
3078 | } |
3079 | ||
e2c671ba RE |
3080 | return insns + 2; |
3081 | } | |
3082 | ||
3083 | break; | |
3084 | ||
3085 | default: | |
3086 | break; | |
3087 | } | |
3088 | ||
3089 | for (i = 0; i < 32; i++) | |
3090 | if (remainder & (1 << i)) | |
3091 | num_bits_set++; | |
3092 | ||
a7994a57 RR |
3093 | if ((code == AND) |
3094 | || (code != IOR && can_invert && num_bits_set > 16)) | |
162e4591 | 3095 | remainder ^= 0xffffffff; |
e2c671ba | 3096 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 3097 | remainder = (-remainder) & 0xffffffff; |
162e4591 RE |
3098 | |
3099 | /* For XOR, if more than half the bits are set and there's a sequence | |
3100 | of more than 8 consecutive ones in the pattern then we can XOR by the | |
3101 | inverted constant and then invert the final result; this may save an | |
3102 | instruction and might also lead to the final mvn being merged with | |
3103 | some other operation. */ | |
3104 | else if (code == XOR && num_bits_set > 16 | |
3105 | && (count_insns_for_constant (remainder ^ 0xffffffff, | |
3106 | find_best_start | |
3107 | (remainder ^ 0xffffffff)) | |
3108 | < count_insns_for_constant (remainder, | |
3109 | find_best_start (remainder)))) | |
3110 | { | |
3111 | remainder ^= 0xffffffff; | |
3112 | final_invert = 1; | |
3113 | } | |
e2c671ba RE |
3114 | else |
3115 | { | |
3116 | can_invert = 0; | |
3117 | can_negate = 0; | |
3118 | } | |
3119 | ||
3120 | /* Now try and find a way of doing the job in either two or three | |
3121 | instructions. | |
3122 | We start by looking for the largest block of zeros that are aligned on | |
3123 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
3124 | top of the word when we drop off the bottom. | |
5b3e6663 PB |
3125 | In the worst case this code should produce no more than four insns. |
3126 | Thumb-2 constants are shifted, not rotated, so the MSB is always the | |
3127 | best place to start. */ | |
3128 | ||
3129 | /* ??? Use thumb2 replicated constants when the high and low halfwords are | |
3130 | the same. */ | |
e2c671ba | 3131 | { |
ceebdb09 | 3132 | /* Now start emitting the insns. */ |
162e4591 | 3133 | i = find_best_start (remainder); |
e2c671ba RE |
3134 | do |
3135 | { | |
3136 | int end; | |
3137 | ||
3138 | if (i <= 0) | |
3139 | i += 32; | |
3140 | if (remainder & (3 << (i - 2))) | |
3141 | { | |
3142 | end = i - 8; | |
3143 | if (end < 0) | |
3144 | end += 32; | |
3145 | temp1 = remainder & ((0x0ff << end) | |
3146 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
3147 | remainder &= ~temp1; | |
3148 | ||
d499463f | 3149 | if (generate) |
e2c671ba | 3150 | { |
9503f3d1 RH |
3151 | rtx new_src, temp1_rtx; |
3152 | ||
3153 | if (code == SET || code == MINUS) | |
3154 | { | |
3155 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 3156 | if (can_invert && code != MINUS) |
9503f3d1 RH |
3157 | temp1 = ~temp1; |
3158 | } | |
3159 | else | |
3160 | { | |
162e4591 | 3161 | if ((final_invert || remainder) && subtargets) |
9503f3d1 | 3162 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
3163 | else |
3164 | new_src = target; | |
9503f3d1 RH |
3165 | if (can_invert) |
3166 | temp1 = ~temp1; | |
3167 | else if (can_negate) | |
3168 | temp1 = -temp1; | |
3169 | } | |
3170 | ||
3171 | temp1 = trunc_int_for_mode (temp1, mode); | |
3172 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
3173 | |
3174 | if (code == SET) | |
9503f3d1 | 3175 | ; |
d499463f | 3176 | else if (code == MINUS) |
9503f3d1 | 3177 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 3178 | else |
9503f3d1 RH |
3179 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
3180 | ||
a406f566 | 3181 | emit_constant_insn (cond, |
f676971a | 3182 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 3183 | temp1_rtx)); |
d499463f | 3184 | source = new_src; |
e2c671ba RE |
3185 | } |
3186 | ||
d499463f RE |
3187 | if (code == SET) |
3188 | { | |
3189 | can_invert = 0; | |
3190 | code = PLUS; | |
3191 | } | |
3192 | else if (code == MINUS) | |
3193 | code = PLUS; | |
3194 | ||
e2c671ba | 3195 | insns++; |
162e4591 | 3196 | i -= 8 - step_size; |
e2c671ba | 3197 | } |
7a085dce | 3198 | /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary |
5b3e6663 | 3199 | shifts. */ |
162e4591 | 3200 | i -= step_size; |
1d6e90ac NC |
3201 | } |
3202 | while (remainder); | |
e2c671ba | 3203 | } |
1d6e90ac | 3204 | |
162e4591 RE |
3205 | if (final_invert) |
3206 | { | |
3207 | if (generate) | |
3208 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
3209 | gen_rtx_NOT (mode, source))); | |
3210 | insns++; | |
3211 | } | |
3212 | ||
e2c671ba RE |
3213 | return insns; |
3214 | } | |
3215 | ||
bd9c7e23 RE |
3216 | /* Canonicalize a comparison so that we are more likely to recognize it. |
3217 | This can be done for a few constant compares, where we can make the | |
3218 | immediate value easier to load. */ | |
1d6e90ac | 3219 | |
bd9c7e23 | 3220 | enum rtx_code |
73160ba9 | 3221 | arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1) |
bd9c7e23 | 3222 | { |
73160ba9 DJ |
3223 | enum machine_mode mode; |
3224 | unsigned HOST_WIDE_INT i, maxval; | |
3225 | ||
3226 | mode = GET_MODE (*op0); | |
3227 | if (mode == VOIDmode) | |
3228 | mode = GET_MODE (*op1); | |
3229 | ||
a14b88bb | 3230 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; |
bd9c7e23 | 3231 | |
73160ba9 DJ |
3232 | /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode |
3233 | we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either | |
3234 | reversed or (for constant OP1) adjusted to GE/LT. Similarly | |
3235 | for GTU/LEU in Thumb mode. */ | |
3236 | if (mode == DImode) | |
3237 | { | |
3238 | rtx tem; | |
3239 | ||
3240 | /* To keep things simple, always use the Cirrus cfcmp64 if it is | |
3241 | available. */ | |
3242 | if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
3243 | return code; | |
3244 | ||
3245 | if (code == GT || code == LE | |
3246 | || (!TARGET_ARM && (code == GTU || code == LEU))) | |
3247 | { | |
3248 | /* Missing comparison. First try to use an available | |
3249 | comparison. */ | |
3250 | if (GET_CODE (*op1) == CONST_INT) | |
3251 | { | |
3252 | i = INTVAL (*op1); | |
3253 | switch (code) | |
3254 | { | |
3255 | case GT: | |
3256 | case LE: | |
3257 | if (i != maxval | |
3258 | && arm_const_double_by_immediates (GEN_INT (i + 1))) | |
3259 | { | |
3260 | *op1 = GEN_INT (i + 1); | |
3261 | return code == GT ? GE : LT; | |
3262 | } | |
3263 | break; | |
3264 | case GTU: | |
3265 | case LEU: | |
3266 | if (i != ~((unsigned HOST_WIDE_INT) 0) | |
3267 | && arm_const_double_by_immediates (GEN_INT (i + 1))) | |
3268 | { | |
3269 | *op1 = GEN_INT (i + 1); | |
3270 | return code == GTU ? GEU : LTU; | |
3271 | } | |
3272 | break; | |
3273 | default: | |
3274 | gcc_unreachable (); | |
3275 | } | |
3276 | } | |
3277 | ||
3278 | /* If that did not work, reverse the condition. */ | |
3279 | tem = *op0; | |
3280 | *op0 = *op1; | |
3281 | *op1 = tem; | |
3282 | return swap_condition (code); | |
3283 | } | |
3284 | ||
3285 | return code; | |
3286 | } | |
3287 | ||
3288 | /* Comparisons smaller than DImode. Only adjust comparisons against | |
3289 | an out-of-range constant. */ | |
3290 | if (GET_CODE (*op1) != CONST_INT | |
3291 | || const_ok_for_arm (INTVAL (*op1)) | |
3292 | || const_ok_for_arm (- INTVAL (*op1))) | |
3293 | return code; | |
3294 | ||
3295 | i = INTVAL (*op1); | |
3296 | ||
bd9c7e23 RE |
3297 | switch (code) |
3298 | { | |
3299 | case EQ: | |
3300 | case NE: | |
3301 | return code; | |
3302 | ||
3303 | case GT: | |
3304 | case LE: | |
a14b88bb | 3305 | if (i != maxval |
5895f793 | 3306 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 3307 | { |
5895f793 | 3308 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
3309 | return code == GT ? GE : LT; |
3310 | } | |
3311 | break; | |
3312 | ||
3313 | case GE: | |
3314 | case LT: | |
a14b88bb | 3315 | if (i != ~maxval |
5895f793 | 3316 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 3317 | { |
5895f793 | 3318 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
3319 | return code == GE ? GT : LE; |
3320 | } | |
3321 | break; | |
3322 | ||
3323 | case GTU: | |
3324 | case LEU: | |
30cf4896 | 3325 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 3326 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
3327 | { |
3328 | *op1 = GEN_INT (i + 1); | |
3329 | return code == GTU ? GEU : LTU; | |
3330 | } | |
3331 | break; | |
3332 | ||
3333 | case GEU: | |
3334 | case LTU: | |
3335 | if (i != 0 | |
5895f793 | 3336 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
3337 | { |
3338 | *op1 = GEN_INT (i - 1); | |
3339 | return code == GEU ? GTU : LEU; | |
3340 | } | |
3341 | break; | |
3342 | ||
3343 | default: | |
e6d29d15 | 3344 | gcc_unreachable (); |
bd9c7e23 RE |
3345 | } |
3346 | ||
3347 | return code; | |
3348 | } | |
bd9c7e23 | 3349 | |
d4453b7a PB |
3350 | |
3351 | /* Define how to find the value returned by a function. */ | |
3352 | ||
390b17c2 RE |
3353 | static rtx |
3354 | arm_function_value(const_tree type, const_tree func, | |
3355 | bool outgoing ATTRIBUTE_UNUSED) | |
d4453b7a PB |
3356 | { |
3357 | enum machine_mode mode; | |
3358 | int unsignedp ATTRIBUTE_UNUSED; | |
3359 | rtx r ATTRIBUTE_UNUSED; | |
3360 | ||
d4453b7a | 3361 | mode = TYPE_MODE (type); |
390b17c2 RE |
3362 | |
3363 | if (TARGET_AAPCS_BASED) | |
3364 | return aapcs_allocate_return_reg (mode, type, func); | |
3365 | ||
d4453b7a PB |
3366 | /* Promote integer types. */ |
3367 | if (INTEGRAL_TYPE_P (type)) | |
cde0f3fd | 3368 | mode = arm_promote_function_mode (type, mode, &unsignedp, func, 1); |
866af8a9 JB |
3369 | |
3370 | /* Promotes small structs returned in a register to full-word size | |
3371 | for big-endian AAPCS. */ | |
3372 | if (arm_return_in_msb (type)) | |
3373 | { | |
3374 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
3375 | if (size % UNITS_PER_WORD != 0) | |
3376 | { | |
3377 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
3378 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
3379 | } | |
3380 | } | |
e0b92319 | 3381 | |
390b17c2 RE |
3382 | return LIBCALL_VALUE (mode); |
3383 | } | |
3384 | ||
3385 | static int | |
3386 | libcall_eq (const void *p1, const void *p2) | |
3387 | { | |
3388 | return rtx_equal_p ((const_rtx) p1, (const_rtx) p2); | |
3389 | } | |
3390 | ||
3391 | static hashval_t | |
3392 | libcall_hash (const void *p1) | |
3393 | { | |
3394 | return hash_rtx ((const_rtx) p1, VOIDmode, NULL, NULL, FALSE); | |
3395 | } | |
3396 | ||
3397 | static void | |
3398 | add_libcall (htab_t htab, rtx libcall) | |
3399 | { | |
3400 | *htab_find_slot (htab, libcall, INSERT) = libcall; | |
3401 | } | |
3402 | ||
3403 | static bool | |
7fc6a96b | 3404 | arm_libcall_uses_aapcs_base (const_rtx libcall) |
390b17c2 RE |
3405 | { |
3406 | static bool init_done = false; | |
3407 | static htab_t libcall_htab; | |
3408 | ||
3409 | if (!init_done) | |
3410 | { | |
3411 | init_done = true; | |
3412 | ||
3413 | libcall_htab = htab_create (31, libcall_hash, libcall_eq, | |
3414 | NULL); | |
3415 | add_libcall (libcall_htab, | |
3416 | convert_optab_libfunc (sfloat_optab, SFmode, SImode)); | |
3417 | add_libcall (libcall_htab, | |
3418 | convert_optab_libfunc (sfloat_optab, DFmode, SImode)); | |
3419 | add_libcall (libcall_htab, | |
3420 | convert_optab_libfunc (sfloat_optab, SFmode, DImode)); | |
3421 | add_libcall (libcall_htab, | |
3422 | convert_optab_libfunc (sfloat_optab, DFmode, DImode)); | |
3423 | ||
3424 | add_libcall (libcall_htab, | |
3425 | convert_optab_libfunc (ufloat_optab, SFmode, SImode)); | |
3426 | add_libcall (libcall_htab, | |
3427 | convert_optab_libfunc (ufloat_optab, DFmode, SImode)); | |
3428 | add_libcall (libcall_htab, | |
3429 | convert_optab_libfunc (ufloat_optab, SFmode, DImode)); | |
3430 | add_libcall (libcall_htab, | |
3431 | convert_optab_libfunc (ufloat_optab, DFmode, DImode)); | |
3432 | ||
3433 | add_libcall (libcall_htab, | |
3434 | convert_optab_libfunc (sext_optab, SFmode, HFmode)); | |
3435 | add_libcall (libcall_htab, | |
3436 | convert_optab_libfunc (trunc_optab, HFmode, SFmode)); | |
3437 | add_libcall (libcall_htab, | |
3438 | convert_optab_libfunc (sfix_optab, DImode, DFmode)); | |
3439 | add_libcall (libcall_htab, | |
3440 | convert_optab_libfunc (ufix_optab, DImode, DFmode)); | |
3441 | add_libcall (libcall_htab, | |
3442 | convert_optab_libfunc (sfix_optab, DImode, SFmode)); | |
3443 | add_libcall (libcall_htab, | |
3444 | convert_optab_libfunc (ufix_optab, DImode, SFmode)); | |
3445 | } | |
3446 | ||
3447 | return libcall && htab_find (libcall_htab, libcall) != NULL; | |
3448 | } | |
3449 | ||
3450 | rtx | |
7fc6a96b | 3451 | arm_libcall_value (enum machine_mode mode, const_rtx libcall) |
390b17c2 RE |
3452 | { |
3453 | if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS | |
3454 | && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3455 | { | |
3456 | /* The following libcalls return their result in integer registers, | |
3457 | even though they return a floating point value. */ | |
3458 | if (arm_libcall_uses_aapcs_base (libcall)) | |
3459 | return gen_rtx_REG (mode, ARG_REGISTER(1)); | |
3460 | ||
3461 | } | |
3462 | ||
3463 | return LIBCALL_VALUE (mode); | |
d4453b7a PB |
3464 | } |
3465 | ||
e0b92319 | 3466 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
3467 | registers of an untyped call. */ |
3468 | int | |
3469 | arm_apply_result_size (void) | |
3470 | { | |
3471 | int size = 16; | |
3472 | ||
390b17c2 | 3473 | if (TARGET_32BIT) |
9f7bf991 RE |
3474 | { |
3475 | if (TARGET_HARD_FLOAT_ABI) | |
3476 | { | |
390b17c2 RE |
3477 | if (TARGET_VFP) |
3478 | size += 32; | |
9f7bf991 RE |
3479 | if (TARGET_FPA) |
3480 | size += 12; | |
3481 | if (TARGET_MAVERICK) | |
3482 | size += 8; | |
3483 | } | |
3484 | if (TARGET_IWMMXT_ABI) | |
3485 | size += 8; | |
3486 | } | |
3487 | ||
3488 | return size; | |
3489 | } | |
d4453b7a | 3490 | |
390b17c2 RE |
3491 | /* Decide whether TYPE should be returned in memory (true) |
3492 | or in a register (false). FNTYPE is the type of the function making | |
3493 | the call. */ | |
23668cf7 | 3494 | static bool |
390b17c2 | 3495 | arm_return_in_memory (const_tree type, const_tree fntype) |
2b835d68 | 3496 | { |
dc0ba55a JT |
3497 | HOST_WIDE_INT size; |
3498 | ||
390b17c2 RE |
3499 | size = int_size_in_bytes (type); /* Negative if not fixed size. */ |
3500 | ||
3501 | if (TARGET_AAPCS_BASED) | |
3502 | { | |
3503 | /* Simple, non-aggregate types (ie not including vectors and | |
3504 | complex) are always returned in a register (or registers). | |
3505 | We don't care about which register here, so we can short-cut | |
3506 | some of the detail. */ | |
3507 | if (!AGGREGATE_TYPE_P (type) | |
3508 | && TREE_CODE (type) != VECTOR_TYPE | |
3509 | && TREE_CODE (type) != COMPLEX_TYPE) | |
3510 | return false; | |
3511 | ||
3512 | /* Any return value that is no larger than one word can be | |
3513 | returned in r0. */ | |
3514 | if (((unsigned HOST_WIDE_INT) size) <= UNITS_PER_WORD) | |
3515 | return false; | |
3516 | ||
3517 | /* Check any available co-processors to see if they accept the | |
3518 | type as a register candidate (VFP, for example, can return | |
3519 | some aggregates in consecutive registers). These aren't | |
3520 | available if the call is variadic. */ | |
3521 | if (aapcs_select_return_coproc (type, fntype) >= 0) | |
3522 | return false; | |
3523 | ||
3524 | /* Vector values should be returned using ARM registers, not | |
3525 | memory (unless they're over 16 bytes, which will break since | |
3526 | we only have four call-clobbered registers to play with). */ | |
3527 | if (TREE_CODE (type) == VECTOR_TYPE) | |
3528 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
3529 | ||
3530 | /* The rest go in memory. */ | |
3531 | return true; | |
3532 | } | |
88f77cba | 3533 | |
88f77cba JB |
3534 | if (TREE_CODE (type) == VECTOR_TYPE) |
3535 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
3536 | ||
3dd7ab65 | 3537 | if (!AGGREGATE_TYPE_P (type) && |
390b17c2 RE |
3538 | (TREE_CODE (type) != VECTOR_TYPE)) |
3539 | /* All simple types are returned in registers. */ | |
3540 | return false; | |
dc0ba55a | 3541 | |
5848830f | 3542 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 3543 | { |
5848830f | 3544 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
3545 | larger than a word (or are variable size). */ |
3546 | return (size < 0 || size > UNITS_PER_WORD); | |
3547 | } | |
f676971a | 3548 | |
6bc82793 | 3549 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
3550 | ARM and Thumb compilers, which always return aggregates in memory. */ |
3551 | #ifndef ARM_WINCE | |
e529bd42 NC |
3552 | /* All structures/unions bigger than one word are returned in memory. |
3553 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 3554 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 3555 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 3556 | if (size < 0 || size > UNITS_PER_WORD) |
390b17c2 | 3557 | return true; |
f676971a | 3558 | |
d7d01975 | 3559 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
3560 | { |
3561 | tree field; | |
3562 | ||
3a2ea258 RE |
3563 | /* For a struct the APCS says that we only return in a register |
3564 | if the type is 'integer like' and every addressable element | |
3565 | has an offset of zero. For practical purposes this means | |
3566 | that the structure can have at most one non bit-field element | |
3567 | and that this element must be the first one in the structure. */ | |
f676971a | 3568 | |
f5a1b0d2 NC |
3569 | /* Find the first field, ignoring non FIELD_DECL things which will |
3570 | have been created by C++. */ | |
3571 | for (field = TYPE_FIELDS (type); | |
3572 | field && TREE_CODE (field) != FIELD_DECL; | |
910ad8de | 3573 | field = DECL_CHAIN (field)) |
f5a1b0d2 | 3574 | continue; |
f676971a | 3575 | |
f5a1b0d2 | 3576 | if (field == NULL) |
390b17c2 | 3577 | return false; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 3578 | |
d5b7b3ae RE |
3579 | /* Check that the first field is valid for returning in a register. */ |
3580 | ||
3581 | /* ... Floats are not allowed */ | |
9e291dbe | 3582 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
390b17c2 | 3583 | return true; |
3a2ea258 | 3584 | |
d5b7b3ae RE |
3585 | /* ... Aggregates that are not themselves valid for returning in |
3586 | a register are not allowed. */ | |
81464b2c | 3587 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
390b17c2 | 3588 | return true; |
6f7ebcbb | 3589 | |
3a2ea258 RE |
3590 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
3591 | since they are not addressable. */ | |
910ad8de | 3592 | for (field = DECL_CHAIN (field); |
f5a1b0d2 | 3593 | field; |
910ad8de | 3594 | field = DECL_CHAIN (field)) |
f5a1b0d2 NC |
3595 | { |
3596 | if (TREE_CODE (field) != FIELD_DECL) | |
3597 | continue; | |
f676971a | 3598 | |
5895f793 | 3599 | if (!DECL_BIT_FIELD_TYPE (field)) |
390b17c2 | 3600 | return true; |
f5a1b0d2 | 3601 | } |
2b835d68 | 3602 | |
390b17c2 | 3603 | return false; |
2b835d68 | 3604 | } |
f676971a | 3605 | |
d7d01975 | 3606 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
3607 | { |
3608 | tree field; | |
3609 | ||
3610 | /* Unions can be returned in registers if every element is | |
3611 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
3612 | for (field = TYPE_FIELDS (type); |
3613 | field; | |
910ad8de | 3614 | field = DECL_CHAIN (field)) |
2b835d68 | 3615 | { |
f5a1b0d2 NC |
3616 | if (TREE_CODE (field) != FIELD_DECL) |
3617 | continue; | |
3618 | ||
6cc8c0b3 | 3619 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
390b17c2 | 3620 | return true; |
f676971a | 3621 | |
81464b2c | 3622 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
390b17c2 | 3623 | return true; |
2b835d68 | 3624 | } |
f676971a | 3625 | |
390b17c2 | 3626 | return false; |
2b835d68 | 3627 | } |
f676971a EC |
3628 | #endif /* not ARM_WINCE */ |
3629 | ||
d5b7b3ae | 3630 | /* Return all other types in memory. */ |
390b17c2 | 3631 | return true; |
2b835d68 RE |
3632 | } |
3633 | ||
d6b4baa4 | 3634 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
3635 | |
3636 | int | |
e32bac5b | 3637 | arm_float_words_big_endian (void) |
3717da94 | 3638 | { |
9b66ebb1 | 3639 | if (TARGET_MAVERICK) |
9b6b54e2 | 3640 | return 0; |
3717da94 JT |
3641 | |
3642 | /* For FPA, float words are always big-endian. For VFP, floats words | |
3643 | follow the memory system mode. */ | |
3644 | ||
9b66ebb1 | 3645 | if (TARGET_FPA) |
3717da94 | 3646 | { |
3717da94 JT |
3647 | return 1; |
3648 | } | |
3649 | ||
3650 | if (TARGET_VFP) | |
3651 | return (TARGET_BIG_END ? 1 : 0); | |
3652 | ||
3653 | return 1; | |
3654 | } | |
3655 | ||
390b17c2 RE |
3656 | const struct pcs_attribute_arg |
3657 | { | |
3658 | const char *arg; | |
3659 | enum arm_pcs value; | |
3660 | } pcs_attribute_args[] = | |
3661 | { | |
3662 | {"aapcs", ARM_PCS_AAPCS}, | |
3663 | {"aapcs-vfp", ARM_PCS_AAPCS_VFP}, | |
0f1a24df RE |
3664 | #if 0 |
3665 | /* We could recognize these, but changes would be needed elsewhere | |
3666 | * to implement them. */ | |
390b17c2 RE |
3667 | {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT}, |
3668 | {"atpcs", ARM_PCS_ATPCS}, | |
3669 | {"apcs", ARM_PCS_APCS}, | |
0f1a24df | 3670 | #endif |
390b17c2 RE |
3671 | {NULL, ARM_PCS_UNKNOWN} |
3672 | }; | |
3673 | ||
3674 | static enum arm_pcs | |
3675 | arm_pcs_from_attribute (tree attr) | |
3676 | { | |
3677 | const struct pcs_attribute_arg *ptr; | |
3678 | const char *arg; | |
3679 | ||
3680 | /* Get the value of the argument. */ | |
3681 | if (TREE_VALUE (attr) == NULL_TREE | |
3682 | || TREE_CODE (TREE_VALUE (attr)) != STRING_CST) | |
3683 | return ARM_PCS_UNKNOWN; | |
3684 | ||
3685 | arg = TREE_STRING_POINTER (TREE_VALUE (attr)); | |
3686 | ||
3687 | /* Check it against the list of known arguments. */ | |
3688 | for (ptr = pcs_attribute_args; ptr->arg != NULL; ptr++) | |
3689 | if (streq (arg, ptr->arg)) | |
3690 | return ptr->value; | |
3691 | ||
3692 | /* An unrecognized interrupt type. */ | |
3693 | return ARM_PCS_UNKNOWN; | |
3694 | } | |
3695 | ||
3696 | /* Get the PCS variant to use for this call. TYPE is the function's type | |
3697 | specification, DECL is the specific declartion. DECL may be null if | |
3698 | the call could be indirect or if this is a library call. */ | |
3699 | static enum arm_pcs | |
3700 | arm_get_pcs_model (const_tree type, const_tree decl) | |
3701 | { | |
3702 | bool user_convention = false; | |
3703 | enum arm_pcs user_pcs = arm_pcs_default; | |
3704 | tree attr; | |
3705 | ||
3706 | gcc_assert (type); | |
3707 | ||
3708 | attr = lookup_attribute ("pcs", TYPE_ATTRIBUTES (type)); | |
3709 | if (attr) | |
3710 | { | |
3711 | user_pcs = arm_pcs_from_attribute (TREE_VALUE (attr)); | |
3712 | user_convention = true; | |
3713 | } | |
3714 | ||
3715 | if (TARGET_AAPCS_BASED) | |
3716 | { | |
3717 | /* Detect varargs functions. These always use the base rules | |
3718 | (no argument is ever a candidate for a co-processor | |
3719 | register). */ | |
f38958e8 | 3720 | bool base_rules = stdarg_p (type); |
390b17c2 RE |
3721 | |
3722 | if (user_convention) | |
3723 | { | |
3724 | if (user_pcs > ARM_PCS_AAPCS_LOCAL) | |
3725 | sorry ("Non-AAPCS derived PCS variant"); | |
3726 | else if (base_rules && user_pcs != ARM_PCS_AAPCS) | |
3727 | error ("Variadic functions must use the base AAPCS variant"); | |
3728 | } | |
3729 | ||
3730 | if (base_rules) | |
3731 | return ARM_PCS_AAPCS; | |
3732 | else if (user_convention) | |
3733 | return user_pcs; | |
3734 | else if (decl && flag_unit_at_a_time) | |
3735 | { | |
3736 | /* Local functions never leak outside this compilation unit, | |
3737 | so we are free to use whatever conventions are | |
3738 | appropriate. */ | |
3739 | /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */ | |
3740 | struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl)); | |
3741 | if (i && i->local) | |
3742 | return ARM_PCS_AAPCS_LOCAL; | |
3743 | } | |
3744 | } | |
3745 | else if (user_convention && user_pcs != arm_pcs_default) | |
3746 | sorry ("PCS variant"); | |
3747 | ||
3748 | /* For everything else we use the target's default. */ | |
3749 | return arm_pcs_default; | |
3750 | } | |
3751 | ||
3752 | ||
3753 | static void | |
3754 | aapcs_vfp_cum_init (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED, | |
3755 | const_tree fntype ATTRIBUTE_UNUSED, | |
3756 | rtx libcall ATTRIBUTE_UNUSED, | |
3757 | const_tree fndecl ATTRIBUTE_UNUSED) | |
3758 | { | |
3759 | /* Record the unallocated VFP registers. */ | |
3760 | pcum->aapcs_vfp_regs_free = (1 << NUM_VFP_ARG_REGS) - 1; | |
3761 | pcum->aapcs_vfp_reg_alloc = 0; | |
3762 | } | |
3763 | ||
3764 | /* Walk down the type tree of TYPE counting consecutive base elements. | |
3765 | If *MODEP is VOIDmode, then set it to the first valid floating point | |
3766 | type. If a non-floating point type is found, or if a floating point | |
3767 | type that doesn't match a non-VOIDmode *MODEP is found, then return -1, | |
3768 | otherwise return the count in the sub-tree. */ | |
3769 | static int | |
3770 | aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep) | |
3771 | { | |
3772 | enum machine_mode mode; | |
3773 | HOST_WIDE_INT size; | |
3774 | ||
3775 | switch (TREE_CODE (type)) | |
3776 | { | |
3777 | case REAL_TYPE: | |
3778 | mode = TYPE_MODE (type); | |
3779 | if (mode != DFmode && mode != SFmode) | |
3780 | return -1; | |
3781 | ||
3782 | if (*modep == VOIDmode) | |
3783 | *modep = mode; | |
3784 | ||
3785 | if (*modep == mode) | |
3786 | return 1; | |
3787 | ||
3788 | break; | |
3789 | ||
3790 | case COMPLEX_TYPE: | |
3791 | mode = TYPE_MODE (TREE_TYPE (type)); | |
3792 | if (mode != DFmode && mode != SFmode) | |
3793 | return -1; | |
3794 | ||
3795 | if (*modep == VOIDmode) | |
3796 | *modep = mode; | |
3797 | ||
3798 | if (*modep == mode) | |
3799 | return 2; | |
3800 | ||
3801 | break; | |
3802 | ||
3803 | case VECTOR_TYPE: | |
3804 | /* Use V2SImode and V4SImode as representatives of all 64-bit | |
3805 | and 128-bit vector types, whether or not those modes are | |
3806 | supported with the present options. */ | |
3807 | size = int_size_in_bytes (type); | |
3808 | switch (size) | |
3809 | { | |
3810 | case 8: | |
3811 | mode = V2SImode; | |
3812 | break; | |
3813 | case 16: | |
3814 | mode = V4SImode; | |
3815 | break; | |
3816 | default: | |
3817 | return -1; | |
3818 | } | |
3819 | ||
3820 | if (*modep == VOIDmode) | |
3821 | *modep = mode; | |
3822 | ||
3823 | /* Vector modes are considered to be opaque: two vectors are | |
3824 | equivalent for the purposes of being homogeneous aggregates | |
3825 | if they are the same size. */ | |
3826 | if (*modep == mode) | |
3827 | return 1; | |
3828 | ||
3829 | break; | |
3830 | ||
3831 | case ARRAY_TYPE: | |
3832 | { | |
3833 | int count; | |
3834 | tree index = TYPE_DOMAIN (type); | |
3835 | ||
3836 | /* Can't handle incomplete types. */ | |
3837 | if (!COMPLETE_TYPE_P(type)) | |
3838 | return -1; | |
3839 | ||
3840 | count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep); | |
3841 | if (count == -1 | |
3842 | || !index | |
3843 | || !TYPE_MAX_VALUE (index) | |
3844 | || !host_integerp (TYPE_MAX_VALUE (index), 1) | |
3845 | || !TYPE_MIN_VALUE (index) | |
3846 | || !host_integerp (TYPE_MIN_VALUE (index), 1) | |
3847 | || count < 0) | |
3848 | return -1; | |
3849 | ||
3850 | count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1) | |
3851 | - tree_low_cst (TYPE_MIN_VALUE (index), 1)); | |
3852 | ||
3853 | /* There must be no padding. */ | |
3854 | if (!host_integerp (TYPE_SIZE (type), 1) | |
3855 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
3856 | != count * GET_MODE_BITSIZE (*modep))) | |
3857 | return -1; | |
3858 | ||
3859 | return count; | |
3860 | } | |
3861 | ||
3862 | case RECORD_TYPE: | |
3863 | { | |
3864 | int count = 0; | |
3865 | int sub_count; | |
3866 | tree field; | |
3867 | ||
3868 | /* Can't handle incomplete types. */ | |
3869 | if (!COMPLETE_TYPE_P(type)) | |
3870 | return -1; | |
3871 | ||
910ad8de | 3872 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
390b17c2 RE |
3873 | { |
3874 | if (TREE_CODE (field) != FIELD_DECL) | |
3875 | continue; | |
3876 | ||
3877 | sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); | |
3878 | if (sub_count < 0) | |
3879 | return -1; | |
3880 | count += sub_count; | |
3881 | } | |
3882 | ||
3883 | /* There must be no padding. */ | |
3884 | if (!host_integerp (TYPE_SIZE (type), 1) | |
3885 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
3886 | != count * GET_MODE_BITSIZE (*modep))) | |
3887 | return -1; | |
3888 | ||
3889 | return count; | |
3890 | } | |
3891 | ||
3892 | case UNION_TYPE: | |
3893 | case QUAL_UNION_TYPE: | |
3894 | { | |
3895 | /* These aren't very interesting except in a degenerate case. */ | |
3896 | int count = 0; | |
3897 | int sub_count; | |
3898 | tree field; | |
3899 | ||
3900 | /* Can't handle incomplete types. */ | |
3901 | if (!COMPLETE_TYPE_P(type)) | |
3902 | return -1; | |
3903 | ||
910ad8de | 3904 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
390b17c2 RE |
3905 | { |
3906 | if (TREE_CODE (field) != FIELD_DECL) | |
3907 | continue; | |
3908 | ||
3909 | sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep); | |
3910 | if (sub_count < 0) | |
3911 | return -1; | |
3912 | count = count > sub_count ? count : sub_count; | |
3913 | } | |
3914 | ||
3915 | /* There must be no padding. */ | |
3916 | if (!host_integerp (TYPE_SIZE (type), 1) | |
3917 | || (tree_low_cst (TYPE_SIZE (type), 1) | |
3918 | != count * GET_MODE_BITSIZE (*modep))) | |
3919 | return -1; | |
3920 | ||
3921 | return count; | |
3922 | } | |
3923 | ||
3924 | default: | |
3925 | break; | |
3926 | } | |
3927 | ||
3928 | return -1; | |
3929 | } | |
3930 | ||
e0dc3601 | 3931 | /* Return true if PCS_VARIANT should use VFP registers. */ |
390b17c2 | 3932 | static bool |
e0dc3601 | 3933 | use_vfp_abi (enum arm_pcs pcs_variant, bool is_double) |
390b17c2 | 3934 | { |
e0dc3601 | 3935 | if (pcs_variant == ARM_PCS_AAPCS_VFP) |
50416c61 PB |
3936 | { |
3937 | static bool seen_thumb1_vfp = false; | |
3938 | ||
3939 | if (TARGET_THUMB1 && !seen_thumb1_vfp) | |
3940 | { | |
3941 | sorry ("Thumb-1 hard-float VFP ABI"); | |
3942 | /* sorry() is not immediately fatal, so only display this once. */ | |
3943 | seen_thumb1_vfp = true; | |
3944 | } | |
3945 | ||
3946 | return true; | |
3947 | } | |
e0dc3601 PB |
3948 | |
3949 | if (pcs_variant != ARM_PCS_AAPCS_LOCAL) | |
3950 | return false; | |
3951 | ||
3952 | return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT && | |
3953 | (TARGET_VFP_DOUBLE || !is_double)); | |
3954 | } | |
3955 | ||
3956 | static bool | |
3957 | aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant, | |
3958 | enum machine_mode mode, const_tree type, | |
70dd156a | 3959 | enum machine_mode *base_mode, int *count) |
e0dc3601 PB |
3960 | { |
3961 | enum machine_mode new_mode = VOIDmode; | |
3962 | ||
390b17c2 RE |
3963 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
3964 | || GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
3965 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
3966 | { | |
3967 | *count = 1; | |
e0dc3601 | 3968 | new_mode = mode; |
390b17c2 RE |
3969 | } |
3970 | else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
3971 | { | |
3972 | *count = 2; | |
e0dc3601 | 3973 | new_mode = (mode == DCmode ? DFmode : SFmode); |
390b17c2 RE |
3974 | } |
3975 | else if (type && (mode == BLKmode || TREE_CODE (type) == VECTOR_TYPE)) | |
3976 | { | |
e0dc3601 | 3977 | int ag_count = aapcs_vfp_sub_candidate (type, &new_mode); |
390b17c2 RE |
3978 | |
3979 | if (ag_count > 0 && ag_count <= 4) | |
e0dc3601 PB |
3980 | *count = ag_count; |
3981 | else | |
3982 | return false; | |
390b17c2 | 3983 | } |
e0dc3601 PB |
3984 | else |
3985 | return false; | |
3986 | ||
3987 | ||
3988 | if (!use_vfp_abi (pcs_variant, ARM_NUM_REGS (new_mode) > 1)) | |
3989 | return false; | |
3990 | ||
3991 | *base_mode = new_mode; | |
3992 | return true; | |
390b17c2 RE |
3993 | } |
3994 | ||
3995 | static bool | |
3996 | aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant, | |
3997 | enum machine_mode mode, const_tree type) | |
3998 | { | |
3999 | int count ATTRIBUTE_UNUSED; | |
46107b99 | 4000 | enum machine_mode ag_mode ATTRIBUTE_UNUSED; |
390b17c2 | 4001 | |
e0dc3601 | 4002 | if (!use_vfp_abi (pcs_variant, false)) |
390b17c2 | 4003 | return false; |
e0dc3601 PB |
4004 | return aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type, |
4005 | &ag_mode, &count); | |
390b17c2 RE |
4006 | } |
4007 | ||
4008 | static bool | |
4009 | aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4010 | const_tree type) | |
4011 | { | |
e0dc3601 | 4012 | if (!use_vfp_abi (pcum->pcs_variant, false)) |
390b17c2 | 4013 | return false; |
e0dc3601 PB |
4014 | |
4015 | return aapcs_vfp_is_call_or_return_candidate (pcum->pcs_variant, mode, type, | |
390b17c2 RE |
4016 | &pcum->aapcs_vfp_rmode, |
4017 | &pcum->aapcs_vfp_rcount); | |
4018 | } | |
4019 | ||
4020 | static bool | |
4021 | aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4022 | const_tree type ATTRIBUTE_UNUSED) | |
4023 | { | |
4024 | int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode); | |
4025 | unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1; | |
4026 | int regno; | |
4027 | ||
4028 | for (regno = 0; regno < NUM_VFP_ARG_REGS; regno += shift) | |
4029 | if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask) | |
4030 | { | |
4031 | pcum->aapcs_vfp_reg_alloc = mask << regno; | |
4032 | if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) | |
4033 | { | |
4034 | int i; | |
4035 | int rcount = pcum->aapcs_vfp_rcount; | |
4036 | int rshift = shift; | |
4037 | enum machine_mode rmode = pcum->aapcs_vfp_rmode; | |
4038 | rtx par; | |
4039 | if (!TARGET_NEON) | |
4040 | { | |
4041 | /* Avoid using unsupported vector modes. */ | |
4042 | if (rmode == V2SImode) | |
4043 | rmode = DImode; | |
4044 | else if (rmode == V4SImode) | |
4045 | { | |
4046 | rmode = DImode; | |
4047 | rcount *= 2; | |
4048 | rshift /= 2; | |
4049 | } | |
4050 | } | |
4051 | par = gen_rtx_PARALLEL (mode, rtvec_alloc (rcount)); | |
4052 | for (i = 0; i < rcount; i++) | |
4053 | { | |
4054 | rtx tmp = gen_rtx_REG (rmode, | |
4055 | FIRST_VFP_REGNUM + regno + i * rshift); | |
4056 | tmp = gen_rtx_EXPR_LIST | |
4057 | (VOIDmode, tmp, | |
4058 | GEN_INT (i * GET_MODE_SIZE (rmode))); | |
4059 | XVECEXP (par, 0, i) = tmp; | |
4060 | } | |
4061 | ||
4062 | pcum->aapcs_reg = par; | |
4063 | } | |
4064 | else | |
4065 | pcum->aapcs_reg = gen_rtx_REG (mode, FIRST_VFP_REGNUM + regno); | |
4066 | return true; | |
4067 | } | |
4068 | return false; | |
4069 | } | |
4070 | ||
4071 | static rtx | |
4072 | aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, | |
4073 | enum machine_mode mode, | |
4074 | const_tree type ATTRIBUTE_UNUSED) | |
4075 | { | |
e0dc3601 | 4076 | if (!use_vfp_abi (pcs_variant, false)) |
390b17c2 | 4077 | return false; |
e0dc3601 | 4078 | |
390b17c2 RE |
4079 | if (mode == BLKmode || (mode == TImode && !TARGET_NEON)) |
4080 | { | |
4081 | int count; | |
46107b99 | 4082 | enum machine_mode ag_mode; |
390b17c2 RE |
4083 | int i; |
4084 | rtx par; | |
4085 | int shift; | |
4086 | ||
e0dc3601 PB |
4087 | aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type, |
4088 | &ag_mode, &count); | |
390b17c2 RE |
4089 | |
4090 | if (!TARGET_NEON) | |
4091 | { | |
4092 | if (ag_mode == V2SImode) | |
4093 | ag_mode = DImode; | |
4094 | else if (ag_mode == V4SImode) | |
4095 | { | |
4096 | ag_mode = DImode; | |
4097 | count *= 2; | |
4098 | } | |
4099 | } | |
4100 | shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode); | |
4101 | par = gen_rtx_PARALLEL (mode, rtvec_alloc (count)); | |
4102 | for (i = 0; i < count; i++) | |
4103 | { | |
4104 | rtx tmp = gen_rtx_REG (ag_mode, FIRST_VFP_REGNUM + i * shift); | |
4105 | tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, | |
4106 | GEN_INT (i * GET_MODE_SIZE (ag_mode))); | |
4107 | XVECEXP (par, 0, i) = tmp; | |
4108 | } | |
4109 | ||
4110 | return par; | |
4111 | } | |
4112 | ||
4113 | return gen_rtx_REG (mode, FIRST_VFP_REGNUM); | |
4114 | } | |
4115 | ||
4116 | static void | |
4117 | aapcs_vfp_advance (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED, | |
4118 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
4119 | const_tree type ATTRIBUTE_UNUSED) | |
4120 | { | |
4121 | pcum->aapcs_vfp_regs_free &= ~pcum->aapcs_vfp_reg_alloc; | |
4122 | pcum->aapcs_vfp_reg_alloc = 0; | |
4123 | return; | |
4124 | } | |
4125 | ||
4126 | #define AAPCS_CP(X) \ | |
4127 | { \ | |
4128 | aapcs_ ## X ## _cum_init, \ | |
4129 | aapcs_ ## X ## _is_call_candidate, \ | |
4130 | aapcs_ ## X ## _allocate, \ | |
4131 | aapcs_ ## X ## _is_return_candidate, \ | |
4132 | aapcs_ ## X ## _allocate_return_reg, \ | |
4133 | aapcs_ ## X ## _advance \ | |
4134 | } | |
4135 | ||
4136 | /* Table of co-processors that can be used to pass arguments in | |
4137 | registers. Idealy no arugment should be a candidate for more than | |
4138 | one co-processor table entry, but the table is processed in order | |
4139 | and stops after the first match. If that entry then fails to put | |
4140 | the argument into a co-processor register, the argument will go on | |
4141 | the stack. */ | |
4142 | static struct | |
4143 | { | |
4144 | /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */ | |
4145 | void (*cum_init) (CUMULATIVE_ARGS *, const_tree, rtx, const_tree); | |
4146 | ||
4147 | /* Return true if an argument of mode MODE (or type TYPE if MODE is | |
4148 | BLKmode) is a candidate for this co-processor's registers; this | |
4149 | function should ignore any position-dependent state in | |
4150 | CUMULATIVE_ARGS and only use call-type dependent information. */ | |
4151 | bool (*is_call_candidate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4152 | ||
4153 | /* Return true if the argument does get a co-processor register; it | |
4154 | should set aapcs_reg to an RTX of the register allocated as is | |
4155 | required for a return from FUNCTION_ARG. */ | |
4156 | bool (*allocate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4157 | ||
4158 | /* Return true if a result of mode MODE (or type TYPE if MODE is | |
4159 | BLKmode) is can be returned in this co-processor's registers. */ | |
4160 | bool (*is_return_candidate) (enum arm_pcs, enum machine_mode, const_tree); | |
4161 | ||
4162 | /* Allocate and return an RTX element to hold the return type of a | |
4163 | call, this routine must not fail and will only be called if | |
4164 | is_return_candidate returned true with the same parameters. */ | |
4165 | rtx (*allocate_return_reg) (enum arm_pcs, enum machine_mode, const_tree); | |
4166 | ||
4167 | /* Finish processing this argument and prepare to start processing | |
4168 | the next one. */ | |
4169 | void (*advance) (CUMULATIVE_ARGS *, enum machine_mode, const_tree); | |
4170 | } aapcs_cp_arg_layout[ARM_NUM_COPROC_SLOTS] = | |
4171 | { | |
4172 | AAPCS_CP(vfp) | |
4173 | }; | |
4174 | ||
4175 | #undef AAPCS_CP | |
4176 | ||
4177 | static int | |
4178 | aapcs_select_call_coproc (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4179 | tree type) | |
4180 | { | |
4181 | int i; | |
4182 | ||
4183 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4184 | if (aapcs_cp_arg_layout[i].is_call_candidate (pcum, mode, type)) | |
4185 | return i; | |
4186 | ||
4187 | return -1; | |
4188 | } | |
4189 | ||
4190 | static int | |
4191 | aapcs_select_return_coproc (const_tree type, const_tree fntype) | |
4192 | { | |
4193 | /* We aren't passed a decl, so we can't check that a call is local. | |
4194 | However, it isn't clear that that would be a win anyway, since it | |
4195 | might limit some tail-calling opportunities. */ | |
4196 | enum arm_pcs pcs_variant; | |
4197 | ||
4198 | if (fntype) | |
4199 | { | |
4200 | const_tree fndecl = NULL_TREE; | |
4201 | ||
4202 | if (TREE_CODE (fntype) == FUNCTION_DECL) | |
4203 | { | |
4204 | fndecl = fntype; | |
4205 | fntype = TREE_TYPE (fntype); | |
4206 | } | |
4207 | ||
4208 | pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4209 | } | |
4210 | else | |
4211 | pcs_variant = arm_pcs_default; | |
4212 | ||
4213 | if (pcs_variant != ARM_PCS_AAPCS) | |
4214 | { | |
4215 | int i; | |
4216 | ||
4217 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4218 | if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, | |
4219 | TYPE_MODE (type), | |
4220 | type)) | |
4221 | return i; | |
4222 | } | |
4223 | return -1; | |
4224 | } | |
4225 | ||
4226 | static rtx | |
4227 | aapcs_allocate_return_reg (enum machine_mode mode, const_tree type, | |
4228 | const_tree fntype) | |
4229 | { | |
4230 | /* We aren't passed a decl, so we can't check that a call is local. | |
4231 | However, it isn't clear that that would be a win anyway, since it | |
4232 | might limit some tail-calling opportunities. */ | |
4233 | enum arm_pcs pcs_variant; | |
4234 | int unsignedp ATTRIBUTE_UNUSED; | |
4235 | ||
4236 | if (fntype) | |
4237 | { | |
4238 | const_tree fndecl = NULL_TREE; | |
4239 | ||
4240 | if (TREE_CODE (fntype) == FUNCTION_DECL) | |
4241 | { | |
4242 | fndecl = fntype; | |
4243 | fntype = TREE_TYPE (fntype); | |
4244 | } | |
4245 | ||
4246 | pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4247 | } | |
4248 | else | |
4249 | pcs_variant = arm_pcs_default; | |
4250 | ||
4251 | /* Promote integer types. */ | |
4252 | if (type && INTEGRAL_TYPE_P (type)) | |
4253 | mode = arm_promote_function_mode (type, mode, &unsignedp, fntype, 1); | |
4254 | ||
4255 | if (pcs_variant != ARM_PCS_AAPCS) | |
4256 | { | |
4257 | int i; | |
4258 | ||
4259 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4260 | if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, mode, | |
4261 | type)) | |
4262 | return aapcs_cp_arg_layout[i].allocate_return_reg (pcs_variant, | |
4263 | mode, type); | |
4264 | } | |
4265 | ||
4266 | /* Promotes small structs returned in a register to full-word size | |
4267 | for big-endian AAPCS. */ | |
4268 | if (type && arm_return_in_msb (type)) | |
4269 | { | |
4270 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
4271 | if (size % UNITS_PER_WORD != 0) | |
4272 | { | |
4273 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
4274 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4275 | } | |
4276 | } | |
4277 | ||
4278 | return gen_rtx_REG (mode, R0_REGNUM); | |
4279 | } | |
4280 | ||
4281 | rtx | |
4282 | aapcs_libcall_value (enum machine_mode mode) | |
4283 | { | |
4284 | return aapcs_allocate_return_reg (mode, NULL_TREE, NULL_TREE); | |
4285 | } | |
4286 | ||
4287 | /* Lay out a function argument using the AAPCS rules. The rule | |
4288 | numbers referred to here are those in the AAPCS. */ | |
4289 | static void | |
4290 | aapcs_layout_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4291 | tree type, int named) | |
4292 | { | |
4293 | int nregs, nregs2; | |
4294 | int ncrn; | |
4295 | ||
4296 | /* We only need to do this once per argument. */ | |
4297 | if (pcum->aapcs_arg_processed) | |
4298 | return; | |
4299 | ||
4300 | pcum->aapcs_arg_processed = true; | |
4301 | ||
4302 | /* Special case: if named is false then we are handling an incoming | |
4303 | anonymous argument which is on the stack. */ | |
4304 | if (!named) | |
4305 | return; | |
4306 | ||
4307 | /* Is this a potential co-processor register candidate? */ | |
4308 | if (pcum->pcs_variant != ARM_PCS_AAPCS) | |
4309 | { | |
4310 | int slot = aapcs_select_call_coproc (pcum, mode, type); | |
4311 | pcum->aapcs_cprc_slot = slot; | |
4312 | ||
4313 | /* We don't have to apply any of the rules from part B of the | |
4314 | preparation phase, these are handled elsewhere in the | |
4315 | compiler. */ | |
4316 | ||
4317 | if (slot >= 0) | |
4318 | { | |
4319 | /* A Co-processor register candidate goes either in its own | |
4320 | class of registers or on the stack. */ | |
4321 | if (!pcum->aapcs_cprc_failed[slot]) | |
4322 | { | |
4323 | /* C1.cp - Try to allocate the argument to co-processor | |
4324 | registers. */ | |
4325 | if (aapcs_cp_arg_layout[slot].allocate (pcum, mode, type)) | |
4326 | return; | |
4327 | ||
4328 | /* C2.cp - Put the argument on the stack and note that we | |
4329 | can't assign any more candidates in this slot. We also | |
4330 | need to note that we have allocated stack space, so that | |
4331 | we won't later try to split a non-cprc candidate between | |
4332 | core registers and the stack. */ | |
4333 | pcum->aapcs_cprc_failed[slot] = true; | |
4334 | pcum->can_split = false; | |
4335 | } | |
4336 | ||
4337 | /* We didn't get a register, so this argument goes on the | |
4338 | stack. */ | |
4339 | gcc_assert (pcum->can_split == false); | |
4340 | return; | |
4341 | } | |
4342 | } | |
4343 | ||
4344 | /* C3 - For double-word aligned arguments, round the NCRN up to the | |
4345 | next even number. */ | |
4346 | ncrn = pcum->aapcs_ncrn; | |
4347 | if ((ncrn & 1) && arm_needs_doubleword_align (mode, type)) | |
4348 | ncrn++; | |
4349 | ||
4350 | nregs = ARM_NUM_REGS2(mode, type); | |
4351 | ||
4352 | /* Sigh, this test should really assert that nregs > 0, but a GCC | |
4353 | extension allows empty structs and then gives them empty size; it | |
4354 | then allows such a structure to be passed by value. For some of | |
4355 | the code below we have to pretend that such an argument has | |
4356 | non-zero size so that we 'locate' it correctly either in | |
4357 | registers or on the stack. */ | |
4358 | gcc_assert (nregs >= 0); | |
4359 | ||
4360 | nregs2 = nregs ? nregs : 1; | |
4361 | ||
4362 | /* C4 - Argument fits entirely in core registers. */ | |
4363 | if (ncrn + nregs2 <= NUM_ARG_REGS) | |
4364 | { | |
4365 | pcum->aapcs_reg = gen_rtx_REG (mode, ncrn); | |
4366 | pcum->aapcs_next_ncrn = ncrn + nregs; | |
4367 | return; | |
4368 | } | |
4369 | ||
4370 | /* C5 - Some core registers left and there are no arguments already | |
4371 | on the stack: split this argument between the remaining core | |
4372 | registers and the stack. */ | |
4373 | if (ncrn < NUM_ARG_REGS && pcum->can_split) | |
4374 | { | |
4375 | pcum->aapcs_reg = gen_rtx_REG (mode, ncrn); | |
4376 | pcum->aapcs_next_ncrn = NUM_ARG_REGS; | |
4377 | pcum->aapcs_partial = (NUM_ARG_REGS - ncrn) * UNITS_PER_WORD; | |
4378 | return; | |
4379 | } | |
4380 | ||
4381 | /* C6 - NCRN is set to 4. */ | |
4382 | pcum->aapcs_next_ncrn = NUM_ARG_REGS; | |
4383 | ||
4384 | /* C7,C8 - arugment goes on the stack. We have nothing to do here. */ | |
4385 | return; | |
4386 | } | |
4387 | ||
82e9d970 PB |
4388 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
4389 | for a call to a function whose data type is FNTYPE. | |
4390 | For a library call, FNTYPE is NULL. */ | |
4391 | void | |
f676971a | 4392 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
390b17c2 | 4393 | rtx libname, |
e32bac5b | 4394 | tree fndecl ATTRIBUTE_UNUSED) |
82e9d970 | 4395 | { |
390b17c2 RE |
4396 | /* Long call handling. */ |
4397 | if (fntype) | |
4398 | pcum->pcs_variant = arm_get_pcs_model (fntype, fndecl); | |
4399 | else | |
4400 | pcum->pcs_variant = arm_pcs_default; | |
4401 | ||
4402 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4403 | { | |
4404 | if (arm_libcall_uses_aapcs_base (libname)) | |
4405 | pcum->pcs_variant = ARM_PCS_AAPCS; | |
4406 | ||
4407 | pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0; | |
4408 | pcum->aapcs_reg = NULL_RTX; | |
4409 | pcum->aapcs_partial = 0; | |
4410 | pcum->aapcs_arg_processed = false; | |
4411 | pcum->aapcs_cprc_slot = -1; | |
4412 | pcum->can_split = true; | |
4413 | ||
4414 | if (pcum->pcs_variant != ARM_PCS_AAPCS) | |
4415 | { | |
4416 | int i; | |
4417 | ||
4418 | for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++) | |
4419 | { | |
4420 | pcum->aapcs_cprc_failed[i] = false; | |
4421 | aapcs_cp_arg_layout[i].cum_init (pcum, fntype, libname, fndecl); | |
4422 | } | |
4423 | } | |
4424 | return; | |
4425 | } | |
4426 | ||
4427 | /* Legacy ABIs */ | |
4428 | ||
82e9d970 | 4429 | /* On the ARM, the offset starts at 0. */ |
29e339b9 | 4430 | pcum->nregs = 0; |
5a9335ef | 4431 | pcum->iwmmxt_nregs = 0; |
5848830f | 4432 | pcum->can_split = true; |
f676971a | 4433 | |
5a9335ef NC |
4434 | /* Varargs vectors are treated the same as long long. |
4435 | named_count avoids having to change the way arm handles 'named' */ | |
4436 | pcum->named_count = 0; | |
4437 | pcum->nargs = 0; | |
4438 | ||
4439 | if (TARGET_REALLY_IWMMXT && fntype) | |
4440 | { | |
4441 | tree fn_arg; | |
4442 | ||
4443 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
4444 | fn_arg; | |
4445 | fn_arg = TREE_CHAIN (fn_arg)) | |
4446 | pcum->named_count += 1; | |
4447 | ||
4448 | if (! pcum->named_count) | |
4449 | pcum->named_count = INT_MAX; | |
4450 | } | |
82e9d970 PB |
4451 | } |
4452 | ||
5848830f PB |
4453 | |
4454 | /* Return true if mode/type need doubleword alignment. */ | |
4455 | bool | |
4456 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
4457 | { | |
65a939f7 PB |
4458 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
4459 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
4460 | } |
4461 | ||
4462 | ||
82e9d970 PB |
4463 | /* Determine where to put an argument to a function. |
4464 | Value is zero to push the argument on the stack, | |
4465 | or a hard register in which to store the argument. | |
4466 | ||
4467 | MODE is the argument's machine mode. | |
4468 | TYPE is the data type of the argument (as a tree). | |
4469 | This is null for libcalls where that information may | |
4470 | not be available. | |
4471 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
4472 | the preceding args and about the function being called. | |
4473 | NAMED is nonzero if this argument is a named parameter | |
4474 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 4475 | |
82e9d970 | 4476 | rtx |
e32bac5b | 4477 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 4478 | tree type, int named) |
82e9d970 | 4479 | { |
5848830f PB |
4480 | int nregs; |
4481 | ||
390b17c2 RE |
4482 | /* Handle the special case quickly. Pick an arbitrary value for op2 of |
4483 | a call insn (op3 of a call_value insn). */ | |
4484 | if (mode == VOIDmode) | |
4485 | return const0_rtx; | |
4486 | ||
4487 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4488 | { | |
4489 | aapcs_layout_arg (pcum, mode, type, named); | |
4490 | return pcum->aapcs_reg; | |
4491 | } | |
4492 | ||
5848830f PB |
4493 | /* Varargs vectors are treated the same as long long. |
4494 | named_count avoids having to change the way arm handles 'named' */ | |
4495 | if (TARGET_IWMMXT_ABI | |
f676971a | 4496 | && arm_vector_mode_supported_p (mode) |
5848830f | 4497 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 4498 | { |
5848830f PB |
4499 | if (pcum->iwmmxt_nregs <= 9) |
4500 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
4501 | else | |
5a9335ef | 4502 | { |
5848830f PB |
4503 | pcum->can_split = false; |
4504 | return NULL_RTX; | |
5a9335ef | 4505 | } |
5a9335ef NC |
4506 | } |
4507 | ||
5848830f PB |
4508 | /* Put doubleword aligned quantities in even register pairs. */ |
4509 | if (pcum->nregs & 1 | |
4510 | && ARM_DOUBLEWORD_ALIGN | |
4511 | && arm_needs_doubleword_align (mode, type)) | |
4512 | pcum->nregs++; | |
4513 | ||
666c27b9 | 4514 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
4515 | args were allocated to regs. For args passed by reference we only count |
4516 | the reference pointer. */ | |
4517 | if (pcum->can_split) | |
4518 | nregs = 1; | |
4519 | else | |
4520 | nregs = ARM_NUM_REGS2 (mode, type); | |
4521 | ||
4522 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 4523 | return NULL_RTX; |
f676971a | 4524 | |
82e9d970 PB |
4525 | return gen_rtx_REG (mode, pcum->nregs); |
4526 | } | |
1741620c | 4527 | |
78a52f11 RH |
4528 | static int |
4529 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
390b17c2 | 4530 | tree type, bool named) |
78a52f11 RH |
4531 | { |
4532 | int nregs = pcum->nregs; | |
4533 | ||
390b17c2 RE |
4534 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) |
4535 | { | |
4536 | aapcs_layout_arg (pcum, mode, type, named); | |
4537 | return pcum->aapcs_partial; | |
4538 | } | |
4539 | ||
88f77cba | 4540 | if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) |
78a52f11 RH |
4541 | return 0; |
4542 | ||
4543 | if (NUM_ARG_REGS > nregs | |
4544 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
4545 | && pcum->can_split) | |
4546 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
4547 | ||
4548 | return 0; | |
4549 | } | |
4550 | ||
390b17c2 RE |
4551 | void |
4552 | arm_function_arg_advance (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
4553 | tree type, bool named) | |
4554 | { | |
4555 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) | |
4556 | { | |
4557 | aapcs_layout_arg (pcum, mode, type, named); | |
4558 | ||
4559 | if (pcum->aapcs_cprc_slot >= 0) | |
4560 | { | |
4561 | aapcs_cp_arg_layout[pcum->aapcs_cprc_slot].advance (pcum, mode, | |
4562 | type); | |
4563 | pcum->aapcs_cprc_slot = -1; | |
4564 | } | |
4565 | ||
4566 | /* Generic stuff. */ | |
4567 | pcum->aapcs_arg_processed = false; | |
4568 | pcum->aapcs_ncrn = pcum->aapcs_next_ncrn; | |
4569 | pcum->aapcs_reg = NULL_RTX; | |
4570 | pcum->aapcs_partial = 0; | |
4571 | } | |
4572 | else | |
4573 | { | |
4574 | pcum->nargs += 1; | |
4575 | if (arm_vector_mode_supported_p (mode) | |
4576 | && pcum->named_count > pcum->nargs | |
4577 | && TARGET_IWMMXT_ABI) | |
4578 | pcum->iwmmxt_nregs += 1; | |
4579 | else | |
4580 | pcum->nregs += ARM_NUM_REGS2 (mode, type); | |
4581 | } | |
4582 | } | |
4583 | ||
1741620c JD |
4584 | /* Variable sized types are passed by reference. This is a GCC |
4585 | extension to the ARM ABI. */ | |
4586 | ||
8cd5a4e0 RH |
4587 | static bool |
4588 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
4589 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
586de218 | 4590 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1741620c JD |
4591 | { |
4592 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
4593 | } | |
82e9d970 | 4594 | \f |
c27ba912 DM |
4595 | /* Encode the current state of the #pragma [no_]long_calls. */ |
4596 | typedef enum | |
82e9d970 | 4597 | { |
6fc0bb99 | 4598 | OFF, /* No #pragma [no_]long_calls is in effect. */ |
c27ba912 DM |
4599 | LONG, /* #pragma long_calls is in effect. */ |
4600 | SHORT /* #pragma no_long_calls is in effect. */ | |
4601 | } arm_pragma_enum; | |
82e9d970 | 4602 | |
c27ba912 | 4603 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 4604 | |
8b97c5f8 | 4605 | void |
e32bac5b | 4606 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 4607 | { |
8b97c5f8 ZW |
4608 | arm_pragma_long_calls = LONG; |
4609 | } | |
4610 | ||
4611 | void | |
e32bac5b | 4612 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
4613 | { |
4614 | arm_pragma_long_calls = SHORT; | |
4615 | } | |
4616 | ||
4617 | void | |
e32bac5b | 4618 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
4619 | { |
4620 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
4621 | } |
4622 | \f | |
91d231cb JM |
4623 | /* Handle an attribute requiring a FUNCTION_DECL; |
4624 | arguments as in struct attribute_spec.handler. */ | |
4625 | static tree | |
e32bac5b RE |
4626 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
4627 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
4628 | { |
4629 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4630 | { | |
29d08eba JM |
4631 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
4632 | name); | |
91d231cb JM |
4633 | *no_add_attrs = true; |
4634 | } | |
4635 | ||
4636 | return NULL_TREE; | |
4637 | } | |
4638 | ||
4639 | /* Handle an "interrupt" or "isr" attribute; | |
4640 | arguments as in struct attribute_spec.handler. */ | |
4641 | static tree | |
e32bac5b RE |
4642 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
4643 | bool *no_add_attrs) | |
91d231cb JM |
4644 | { |
4645 | if (DECL_P (*node)) | |
4646 | { | |
4647 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
4648 | { | |
29d08eba JM |
4649 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
4650 | name); | |
91d231cb JM |
4651 | *no_add_attrs = true; |
4652 | } | |
4653 | /* FIXME: the argument if any is checked for type attributes; | |
4654 | should it be checked for decl ones? */ | |
4655 | } | |
4656 | else | |
4657 | { | |
4658 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
4659 | || TREE_CODE (*node) == METHOD_TYPE) | |
4660 | { | |
4661 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
4662 | { | |
29d08eba JM |
4663 | warning (OPT_Wattributes, "%qE attribute ignored", |
4664 | name); | |
91d231cb JM |
4665 | *no_add_attrs = true; |
4666 | } | |
4667 | } | |
4668 | else if (TREE_CODE (*node) == POINTER_TYPE | |
4669 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
4670 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
4671 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
4672 | { | |
8dd16ecc | 4673 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
4674 | TREE_TYPE (*node) = build_type_attribute_variant |
4675 | (TREE_TYPE (*node), | |
4676 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
4677 | *no_add_attrs = true; |
4678 | } | |
4679 | else | |
4680 | { | |
4681 | /* Possibly pass this attribute on from the type to a decl. */ | |
4682 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
4683 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
4684 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
4685 | { | |
4686 | *no_add_attrs = true; | |
4687 | return tree_cons (name, args, NULL_TREE); | |
4688 | } | |
4689 | else | |
4690 | { | |
29d08eba JM |
4691 | warning (OPT_Wattributes, "%qE attribute ignored", |
4692 | name); | |
91d231cb JM |
4693 | } |
4694 | } | |
4695 | } | |
4696 | ||
4697 | return NULL_TREE; | |
82e9d970 PB |
4698 | } |
4699 | ||
390b17c2 RE |
4700 | /* Handle a "pcs" attribute; arguments as in struct |
4701 | attribute_spec.handler. */ | |
4702 | static tree | |
4703 | arm_handle_pcs_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, | |
4704 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
4705 | { | |
4706 | if (arm_pcs_from_attribute (args) == ARM_PCS_UNKNOWN) | |
4707 | { | |
a9717079 | 4708 | warning (OPT_Wattributes, "%qE attribute ignored", name); |
390b17c2 RE |
4709 | *no_add_attrs = true; |
4710 | } | |
4711 | return NULL_TREE; | |
4712 | } | |
4713 | ||
7bff66a7 | 4714 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
4715 | /* Handle the "notshared" attribute. This attribute is another way of |
4716 | requesting hidden visibility. ARM's compiler supports | |
4717 | "__declspec(notshared)"; we support the same thing via an | |
4718 | attribute. */ | |
4719 | ||
4720 | static tree | |
e0b92319 NC |
4721 | arm_handle_notshared_attribute (tree *node, |
4722 | tree name ATTRIBUTE_UNUSED, | |
4723 | tree args ATTRIBUTE_UNUSED, | |
4724 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
4725 | bool *no_add_attrs) |
4726 | { | |
4727 | tree decl = TYPE_NAME (*node); | |
4728 | ||
4729 | if (decl) | |
4730 | { | |
4731 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
4732 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
4733 | *no_add_attrs = false; | |
4734 | } | |
4735 | return NULL_TREE; | |
4736 | } | |
7bff66a7 | 4737 | #endif |
04fb56d5 | 4738 | |
82e9d970 PB |
4739 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
4740 | are compatible, and 2 if they are nearly compatible (which causes a | |
4741 | warning to be generated). */ | |
8d8e52be | 4742 | static int |
3101faab | 4743 | arm_comp_type_attributes (const_tree type1, const_tree type2) |
82e9d970 | 4744 | { |
1cb8d58a | 4745 | int l1, l2, s1, s2; |
f676971a | 4746 | |
82e9d970 PB |
4747 | /* Check for mismatch of non-default calling convention. */ |
4748 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
4749 | return 1; | |
4750 | ||
4751 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
4752 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
4753 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
4754 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
4755 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
4756 | |
4757 | /* Only bother to check if an attribute is defined. */ | |
4758 | if (l1 | l2 | s1 | s2) | |
4759 | { | |
4760 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 4761 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 4762 | return 0; |
82e9d970 | 4763 | |
bd7fc26f NC |
4764 | /* Disallow mixed attributes. */ |
4765 | if ((l1 & s2) || (l2 & s1)) | |
4766 | return 0; | |
4767 | } | |
f676971a | 4768 | |
6d3d9133 NC |
4769 | /* Check for mismatched ISR attribute. */ |
4770 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
4771 | if (! l1) | |
4772 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
4773 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
4774 | if (! l2) | |
4775 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
4776 | if (l1 != l2) | |
4777 | return 0; | |
4778 | ||
bd7fc26f | 4779 | return 1; |
82e9d970 PB |
4780 | } |
4781 | ||
c27ba912 DM |
4782 | /* Assigns default attributes to newly defined type. This is used to |
4783 | set short_call/long_call attributes for function types of | |
4784 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 4785 | static void |
e32bac5b | 4786 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
4787 | { |
4788 | /* Add __attribute__ ((long_call)) to all functions, when | |
4789 | inside #pragma long_calls or __attribute__ ((short_call)), | |
4790 | when inside #pragma no_long_calls. */ | |
4791 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
4792 | { | |
4793 | tree type_attr_list, attr_name; | |
4794 | type_attr_list = TYPE_ATTRIBUTES (type); | |
4795 | ||
4796 | if (arm_pragma_long_calls == LONG) | |
4797 | attr_name = get_identifier ("long_call"); | |
4798 | else if (arm_pragma_long_calls == SHORT) | |
4799 | attr_name = get_identifier ("short_call"); | |
4800 | else | |
4801 | return; | |
4802 | ||
4803 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
4804 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
4805 | } | |
4806 | } | |
4807 | \f | |
25a65198 RS |
4808 | /* Return true if DECL is known to be linked into section SECTION. */ |
4809 | ||
4810 | static bool | |
4811 | arm_function_in_section_p (tree decl, section *section) | |
c27ba912 | 4812 | { |
25a65198 RS |
4813 | /* We can only be certain about functions defined in the same |
4814 | compilation unit. */ | |
4815 | if (!TREE_STATIC (decl)) | |
4816 | return false; | |
c27ba912 | 4817 | |
25a65198 RS |
4818 | /* Make sure that SYMBOL always binds to the definition in this |
4819 | compilation unit. */ | |
4820 | if (!targetm.binds_local_p (decl)) | |
4821 | return false; | |
c27ba912 | 4822 | |
25a65198 RS |
4823 | /* If DECL_SECTION_NAME is set, assume it is trustworthy. */ |
4824 | if (!DECL_SECTION_NAME (decl)) | |
4825 | { | |
25a65198 RS |
4826 | /* Make sure that we will not create a unique section for DECL. */ |
4827 | if (flag_function_sections || DECL_ONE_ONLY (decl)) | |
4828 | return false; | |
4829 | } | |
4830 | ||
4831 | return function_section (decl) == section; | |
c27ba912 DM |
4832 | } |
4833 | ||
a50aa827 | 4834 | /* Return nonzero if a 32-bit "long_call" should be generated for |
25a65198 RS |
4835 | a call from the current function to DECL. We generate a long_call |
4836 | if the function: | |
c27ba912 DM |
4837 | |
4838 | a. has an __attribute__((long call)) | |
4839 | or b. is within the scope of a #pragma long_calls | |
4840 | or c. the -mlong-calls command line switch has been specified | |
4841 | ||
4842 | However we do not generate a long call if the function: | |
f676971a | 4843 | |
c27ba912 DM |
4844 | d. has an __attribute__ ((short_call)) |
4845 | or e. is inside the scope of a #pragma no_long_calls | |
25a65198 | 4846 | or f. is defined in the same section as the current function. */ |
c27ba912 | 4847 | |
25a65198 RS |
4848 | bool |
4849 | arm_is_long_call_p (tree decl) | |
4850 | { | |
4851 | tree attrs; | |
c27ba912 | 4852 | |
25a65198 RS |
4853 | if (!decl) |
4854 | return TARGET_LONG_CALLS; | |
c27ba912 | 4855 | |
25a65198 RS |
4856 | attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
4857 | if (lookup_attribute ("short_call", attrs)) | |
4858 | return false; | |
c27ba912 | 4859 | |
25a65198 RS |
4860 | /* For "f", be conservative, and only cater for cases in which the |
4861 | whole of the current function is placed in the same section. */ | |
4862 | if (!flag_reorder_blocks_and_partition | |
b3a796bc | 4863 | && TREE_CODE (decl) == FUNCTION_DECL |
25a65198 RS |
4864 | && arm_function_in_section_p (decl, current_function_section ())) |
4865 | return false; | |
a77655b1 | 4866 | |
25a65198 RS |
4867 | if (lookup_attribute ("long_call", attrs)) |
4868 | return true; | |
f676971a | 4869 | |
25a65198 | 4870 | return TARGET_LONG_CALLS; |
c27ba912 | 4871 | } |
f99fce0c | 4872 | |
825dda42 | 4873 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 4874 | static bool |
390b17c2 | 4875 | arm_function_ok_for_sibcall (tree decl, tree exp) |
f99fce0c | 4876 | { |
5b3e6663 | 4877 | unsigned long func_type; |
f99fce0c | 4878 | |
5a9335ef NC |
4879 | if (cfun->machine->sibcall_blocked) |
4880 | return false; | |
4881 | ||
f99fce0c | 4882 | /* Never tailcall something for which we have no decl, or if we |
7c19c715 JB |
4883 | are generating code for Thumb-1. */ |
4884 | if (decl == NULL || TARGET_THUMB1) | |
4977bab6 | 4885 | return false; |
f99fce0c | 4886 | |
9403b7f7 RS |
4887 | /* The PIC register is live on entry to VxWorks PLT entries, so we |
4888 | must make the call before restoring the PIC register. */ | |
4889 | if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) | |
4890 | return false; | |
4891 | ||
f99fce0c | 4892 | /* Cannot tail-call to long calls, since these are out of range of |
25a65198 RS |
4893 | a branch instruction. */ |
4894 | if (arm_is_long_call_p (decl)) | |
4977bab6 | 4895 | return false; |
f99fce0c RE |
4896 | |
4897 | /* If we are interworking and the function is not declared static | |
f676971a | 4898 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 4899 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 4900 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 4901 | return false; |
f99fce0c | 4902 | |
5b3e6663 | 4903 | func_type = arm_current_func_type (); |
6d3d9133 | 4904 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
5b3e6663 PB |
4905 | if (IS_INTERRUPT (func_type)) |
4906 | return false; | |
4907 | ||
390b17c2 RE |
4908 | if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) |
4909 | { | |
4910 | /* Check that the return value locations are the same. For | |
4911 | example that we aren't returning a value from the sibling in | |
4912 | a VFP register but then need to transfer it to a core | |
4913 | register. */ | |
4914 | rtx a, b; | |
4915 | ||
4916 | a = arm_function_value (TREE_TYPE (exp), decl, false); | |
4917 | b = arm_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)), | |
4918 | cfun->decl, false); | |
4919 | if (!rtx_equal_p (a, b)) | |
4920 | return false; | |
4921 | } | |
4922 | ||
5b3e6663 PB |
4923 | /* Never tailcall if function may be called with a misaligned SP. */ |
4924 | if (IS_STACKALIGN (func_type)) | |
4977bab6 | 4925 | return false; |
6d3d9133 | 4926 | |
f99fce0c | 4927 | /* Everything else is ok. */ |
4977bab6 | 4928 | return true; |
f99fce0c RE |
4929 | } |
4930 | ||
82e9d970 | 4931 | \f |
6b990f6b RE |
4932 | /* Addressing mode support functions. */ |
4933 | ||
0b4be7de | 4934 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 4935 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 4936 | int |
e32bac5b | 4937 | legitimate_pic_operand_p (rtx x) |
32de079a | 4938 | { |
020a4035 RE |
4939 | if (GET_CODE (x) == SYMBOL_REF |
4940 | || (GET_CODE (x) == CONST | |
4941 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4942 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
4943 | return 0; |
4944 | ||
4945 | return 1; | |
4946 | } | |
4947 | ||
9403b7f7 RS |
4948 | /* Record that the current function needs a PIC register. Initialize |
4949 | cfun->machine->pic_reg if we have not already done so. */ | |
4950 | ||
4951 | static void | |
4952 | require_pic_register (void) | |
4953 | { | |
4954 | /* A lot of the logic here is made obscure by the fact that this | |
4955 | routine gets called as part of the rtx cost estimation process. | |
4956 | We don't want those calls to affect any assumptions about the real | |
4957 | function; and further, we can't call entry_of_function() until we | |
4958 | start the real expansion process. */ | |
e3b5732b | 4959 | if (!crtl->uses_pic_offset_table) |
9403b7f7 | 4960 | { |
b3a13419 | 4961 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
4962 | if (arm_pic_register != INVALID_REGNUM) |
4963 | { | |
6d2538f5 JB |
4964 | if (!cfun->machine->pic_reg) |
4965 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
9403b7f7 RS |
4966 | |
4967 | /* Play games to avoid marking the function as needing pic | |
4968 | if we are being called as part of the cost-estimation | |
4969 | process. */ | |
04ef80ce | 4970 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
e3b5732b | 4971 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
4972 | } |
4973 | else | |
4974 | { | |
4975 | rtx seq; | |
4976 | ||
6d2538f5 JB |
4977 | if (!cfun->machine->pic_reg) |
4978 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
9403b7f7 RS |
4979 | |
4980 | /* Play games to avoid marking the function as needing pic | |
4981 | if we are being called as part of the cost-estimation | |
4982 | process. */ | |
04ef80ce | 4983 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
9403b7f7 | 4984 | { |
e3b5732b | 4985 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
4986 | start_sequence (); |
4987 | ||
4988 | arm_load_pic_register (0UL); | |
4989 | ||
4990 | seq = get_insns (); | |
4991 | end_sequence (); | |
af618949 MM |
4992 | /* We can be called during expansion of PHI nodes, where |
4993 | we can't yet emit instructions directly in the final | |
4994 | insn stream. Queue the insns on the entry edge, they will | |
4995 | be committed after everything else is expanded. */ | |
4996 | insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | |
9403b7f7 RS |
4997 | } |
4998 | } | |
4999 | } | |
5000 | } | |
5001 | ||
32de079a | 5002 | rtx |
e32bac5b | 5003 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 5004 | { |
a3c48721 RE |
5005 | if (GET_CODE (orig) == SYMBOL_REF |
5006 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 5007 | { |
32de079a | 5008 | rtx insn; |
020a4035 | 5009 | |
32de079a RE |
5010 | if (reg == 0) |
5011 | { | |
b3a13419 | 5012 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5013 | reg = gen_reg_rtx (Pmode); |
32de079a | 5014 | } |
32de079a | 5015 | |
9403b7f7 RS |
5016 | /* VxWorks does not impose a fixed gap between segments; the run-time |
5017 | gap can be different from the object-file gap. We therefore can't | |
5018 | use GOTOFF unless we are absolutely sure that the symbol is in the | |
5019 | same segment as the GOT. Unfortunately, the flexibility of linker | |
5020 | scripts means that we can't be sure of that in general, so assume | |
5021 | that GOTOFF is never valid on VxWorks. */ | |
14f583b8 | 5022 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 5023 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 5024 | SYMBOL_REF_LOCAL_P (orig))) |
9403b7f7 RS |
5025 | && NEED_GOT_RELOC |
5026 | && !TARGET_VXWORKS_RTP) | |
85c9bcd4 | 5027 | insn = arm_pic_static_addr (orig, reg); |
a3c48721 RE |
5028 | else |
5029 | { | |
d37c3c62 MK |
5030 | rtx pat; |
5031 | rtx mem; | |
5032 | ||
85c9bcd4 WG |
5033 | /* If this function doesn't have a pic register, create one now. */ |
5034 | require_pic_register (); | |
5035 | ||
d37c3c62 | 5036 | pat = gen_calculate_pic_address (reg, cfun->machine->pic_reg, orig); |
85c9bcd4 | 5037 | |
d37c3c62 MK |
5038 | /* Make the MEM as close to a constant as possible. */ |
5039 | mem = SET_SRC (pat); | |
5040 | gcc_assert (MEM_P (mem) && !MEM_VOLATILE_P (mem)); | |
5041 | MEM_READONLY_P (mem) = 1; | |
5042 | MEM_NOTRAP_P (mem) = 1; | |
5043 | ||
5044 | insn = emit_insn (pat); | |
a3c48721 RE |
5045 | } |
5046 | ||
32de079a RE |
5047 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
5048 | by loop. */ | |
bd94cb6e SB |
5049 | set_unique_reg_note (insn, REG_EQUAL, orig); |
5050 | ||
32de079a RE |
5051 | return reg; |
5052 | } | |
5053 | else if (GET_CODE (orig) == CONST) | |
5054 | { | |
5055 | rtx base, offset; | |
5056 | ||
5057 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 5058 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
5059 | return orig; |
5060 | ||
f67358da | 5061 | /* Handle the case where we have: const (UNSPEC_TLS). */ |
d3585b76 DJ |
5062 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
5063 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
5064 | return orig; | |
5065 | ||
f67358da PB |
5066 | /* Handle the case where we have: |
5067 | const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a | |
5068 | CONST_INT. */ | |
5069 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
5070 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC | |
5071 | && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) | |
5072 | { | |
5073 | gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); | |
5074 | return orig; | |
5075 | } | |
5076 | ||
32de079a RE |
5077 | if (reg == 0) |
5078 | { | |
b3a13419 | 5079 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5080 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
5081 | } |
5082 | ||
e6d29d15 | 5083 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 5084 | |
e6d29d15 NS |
5085 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
5086 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
5087 | base == reg ? 0 : reg); | |
32de079a RE |
5088 | |
5089 | if (GET_CODE (offset) == CONST_INT) | |
5090 | { | |
5091 | /* The base register doesn't really matter, we only want to | |
5092 | test the index for the appropriate mode. */ | |
1e1ab407 | 5093 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 5094 | { |
b3a13419 | 5095 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 5096 | offset = force_reg (Pmode, offset); |
6b990f6b | 5097 | } |
32de079a | 5098 | |
32de079a | 5099 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 5100 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
5101 | } |
5102 | ||
5103 | if (GET_MODE_SIZE (mode) > 4 | |
5104 | && (GET_MODE_CLASS (mode) == MODE_INT | |
5105 | || TARGET_SOFT_FLOAT)) | |
5106 | { | |
5107 | emit_insn (gen_addsi3 (reg, base, offset)); | |
5108 | return reg; | |
5109 | } | |
5110 | ||
43cffd11 | 5111 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 5112 | } |
32de079a RE |
5113 | |
5114 | return orig; | |
5115 | } | |
5116 | ||
57934c39 | 5117 | |
5b3e6663 | 5118 | /* Find a spare register to use during the prolog of a function. */ |
57934c39 PB |
5119 | |
5120 | static int | |
b279b20a | 5121 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
5122 | { |
5123 | int reg; | |
5124 | ||
b279b20a NC |
5125 | /* Check the argument registers first as these are call-used. The |
5126 | register allocation order means that sometimes r3 might be used | |
5127 | but earlier argument registers might not, so check them all. */ | |
5128 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
6fb5fa3c | 5129 | if (!df_regs_ever_live_p (reg)) |
b279b20a NC |
5130 | return reg; |
5131 | ||
5132 | /* Before going on to check the call-saved registers we can try a couple | |
5133 | more ways of deducing that r3 is available. The first is when we are | |
5134 | pushing anonymous arguments onto the stack and we have less than 4 | |
5135 | registers worth of fixed arguments(*). In this case r3 will be part of | |
5136 | the variable argument list and so we can be sure that it will be | |
5137 | pushed right at the start of the function. Hence it will be available | |
5138 | for the rest of the prologue. | |
38173d38 | 5139 | (*): ie crtl->args.pretend_args_size is greater than 0. */ |
b279b20a | 5140 | if (cfun->machine->uses_anonymous_args |
38173d38 | 5141 | && crtl->args.pretend_args_size > 0) |
57934c39 PB |
5142 | return LAST_ARG_REGNUM; |
5143 | ||
b279b20a NC |
5144 | /* The other case is when we have fixed arguments but less than 4 registers |
5145 | worth. In this case r3 might be used in the body of the function, but | |
5146 | it is not being used to convey an argument into the function. In theory | |
38173d38 | 5147 | we could just check crtl->args.size to see how many bytes are |
b279b20a NC |
5148 | being passed in argument registers, but it seems that it is unreliable. |
5149 | Sometimes it will have the value 0 when in fact arguments are being | |
5150 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
5151 | check the args_info.nregs field as well. The problem with this field is | |
5152 | that it makes no allowances for arguments that are passed to the | |
5153 | function but which are not used. Hence we could miss an opportunity | |
5154 | when a function has an unused argument in r3. But it is better to be | |
5155 | safe than to be sorry. */ | |
5156 | if (! cfun->machine->uses_anonymous_args | |
38173d38 JH |
5157 | && crtl->args.size >= 0 |
5158 | && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
f6d2671e | 5159 | && crtl->args.info.nregs < 4) |
b279b20a | 5160 | return LAST_ARG_REGNUM; |
e0b92319 | 5161 | |
b279b20a NC |
5162 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
5163 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
5164 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
5165 | return reg; |
5166 | ||
5b3e6663 PB |
5167 | if (TARGET_THUMB2) |
5168 | { | |
5169 | /* Thumb-2 can use high regs. */ | |
5170 | for (reg = FIRST_HI_REGNUM; reg < 15; reg ++) | |
5171 | if (pushed_regs_mask & (1 << reg)) | |
5172 | return reg; | |
5173 | } | |
b279b20a NC |
5174 | /* Something went wrong - thumb_compute_save_reg_mask() |
5175 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 5176 | gcc_unreachable (); |
57934c39 PB |
5177 | } |
5178 | ||
f16fe45f | 5179 | static GTY(()) int pic_labelno; |
876f13b0 | 5180 | |
fe013435 PB |
5181 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
5182 | low register. */ | |
876f13b0 | 5183 | |
32de079a | 5184 | void |
e55ef7f4 | 5185 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a | 5186 | { |
f9bd1a89 | 5187 | rtx l1, labelno, pic_tmp, pic_rtx, pic_reg; |
32de079a | 5188 | |
e3b5732b | 5189 | if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
5190 | return; |
5191 | ||
e6d29d15 | 5192 | gcc_assert (flag_pic); |
32de079a | 5193 | |
9403b7f7 RS |
5194 | pic_reg = cfun->machine->pic_reg; |
5195 | if (TARGET_VXWORKS_RTP) | |
5196 | { | |
5197 | pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); | |
5198 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
87d05b44 | 5199 | emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx)); |
43cffd11 | 5200 | |
9403b7f7 | 5201 | emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg))); |
f676971a | 5202 | |
9403b7f7 RS |
5203 | pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); |
5204 | emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp)); | |
4bec9f7d | 5205 | } |
9403b7f7 | 5206 | else |
5b3e6663 | 5207 | { |
9403b7f7 RS |
5208 | /* We use an UNSPEC rather than a LABEL_REF because this label |
5209 | never appears in the code stream. */ | |
5210 | ||
5211 | labelno = GEN_INT (pic_labelno++); | |
5212 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5213 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
5214 | ||
9403b7f7 RS |
5215 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
5216 | addition, on the Thumb it is 'dot + 4'. */ | |
f9bd1a89 RS |
5217 | pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); |
5218 | pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx), | |
5219 | UNSPEC_GOTSYM_OFF); | |
9403b7f7 RS |
5220 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); |
5221 | ||
87d05b44 | 5222 | if (TARGET_32BIT) |
9403b7f7 | 5223 | { |
87d05b44 RE |
5224 | emit_insn (gen_pic_load_addr_32bit (pic_reg, pic_rtx)); |
5225 | if (TARGET_ARM) | |
5226 | emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); | |
9403b7f7 | 5227 | else |
87d05b44 | 5228 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); |
9403b7f7 RS |
5229 | } |
5230 | else /* TARGET_THUMB1 */ | |
876f13b0 | 5231 | { |
9403b7f7 RS |
5232 | if (arm_pic_register != INVALID_REGNUM |
5233 | && REGNO (pic_reg) > LAST_LO_REGNUM) | |
5234 | { | |
5235 | /* We will have pushed the pic register, so we should always be | |
5236 | able to find a work register. */ | |
5237 | pic_tmp = gen_rtx_REG (SImode, | |
5238 | thumb_find_work_register (saved_regs)); | |
5239 | emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); | |
5240 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
5241 | } | |
5242 | else | |
5243 | emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); | |
5244 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); | |
876f13b0 | 5245 | } |
4bec9f7d | 5246 | } |
32de079a | 5247 | |
32de079a RE |
5248 | /* Need to emit this whether or not we obey regdecls, |
5249 | since setjmp/longjmp can cause life info to screw up. */ | |
c41c1387 | 5250 | emit_use (pic_reg); |
32de079a RE |
5251 | } |
5252 | ||
85c9bcd4 WG |
5253 | /* Generate code to load the address of a static var when flag_pic is set. */ |
5254 | static rtx | |
5255 | arm_pic_static_addr (rtx orig, rtx reg) | |
5256 | { | |
5257 | rtx l1, labelno, offset_rtx, insn; | |
5258 | ||
5259 | gcc_assert (flag_pic); | |
5260 | ||
5261 | /* We use an UNSPEC rather than a LABEL_REF because this label | |
5262 | never appears in the code stream. */ | |
5263 | labelno = GEN_INT (pic_labelno++); | |
5264 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5265 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
5266 | ||
5267 | /* On the ARM the PC register contains 'dot + 8' at the time of the | |
5268 | addition, on the Thumb it is 'dot + 4'. */ | |
5269 | offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); | |
5270 | offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx), | |
5271 | UNSPEC_SYMBOL_OFFSET); | |
5272 | offset_rtx = gen_rtx_CONST (Pmode, offset_rtx); | |
5273 | ||
5274 | if (TARGET_32BIT) | |
5275 | { | |
5276 | emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx)); | |
5277 | if (TARGET_ARM) | |
5278 | insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); | |
5279 | else | |
5280 | insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | |
5281 | } | |
5282 | else /* TARGET_THUMB1 */ | |
5283 | { | |
5284 | emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx)); | |
5285 | insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); | |
5286 | } | |
5287 | ||
5288 | return insn; | |
5289 | } | |
876f13b0 | 5290 | |
6b990f6b RE |
5291 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
5292 | static int | |
e32bac5b | 5293 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
5294 | { |
5295 | int regno; | |
5296 | ||
5297 | if (GET_CODE (x) != REG) | |
5298 | return 0; | |
5299 | ||
5300 | regno = REGNO (x); | |
5301 | ||
5302 | if (strict_p) | |
5303 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
5304 | ||
5305 | return (regno <= LAST_ARM_REGNUM | |
5306 | || regno >= FIRST_PSEUDO_REGISTER | |
5307 | || regno == FRAME_POINTER_REGNUM | |
5308 | || regno == ARG_POINTER_REGNUM); | |
5309 | } | |
5310 | ||
d3585b76 DJ |
5311 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
5312 | and will reduce to a PC-relative relocation in the object file. | |
5313 | Expressions like this can be left alone when generating PIC, rather | |
5314 | than forced through the GOT. */ | |
5315 | static int | |
5316 | pcrel_constant_p (rtx x) | |
5317 | { | |
5318 | if (GET_CODE (x) == MINUS) | |
5319 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
5320 | ||
5321 | return FALSE; | |
5322 | } | |
5323 | ||
d37c3c62 MK |
5324 | /* Return true if X will surely end up in an index register after next |
5325 | splitting pass. */ | |
5326 | static bool | |
5327 | will_be_in_index_register (const_rtx x) | |
5328 | { | |
5329 | /* arm.md: calculate_pic_address will split this into a register. */ | |
5330 | return GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_SYM; | |
5331 | } | |
5332 | ||
6b990f6b RE |
5333 | /* Return nonzero if X is a valid ARM state address operand. */ |
5334 | int | |
c6c3dba9 PB |
5335 | arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
5336 | int strict_p) | |
6b990f6b | 5337 | { |
fdd695fd PB |
5338 | bool use_ldrd; |
5339 | enum rtx_code code = GET_CODE (x); | |
f676971a | 5340 | |
6b990f6b RE |
5341 | if (arm_address_register_rtx_p (x, strict_p)) |
5342 | return 1; | |
5343 | ||
fdd695fd PB |
5344 | use_ldrd = (TARGET_LDRD |
5345 | && (mode == DImode | |
5346 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
5347 | ||
5348 | if (code == POST_INC || code == PRE_DEC | |
5349 | || ((code == PRE_INC || code == POST_DEC) | |
5350 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
5351 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
5352 | ||
fdd695fd | 5353 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
5354 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
5355 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 5356 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
5357 | { |
5358 | rtx addend = XEXP (XEXP (x, 1), 1); | |
5359 | ||
112cdef5 | 5360 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
5361 | to fixup invalid register choices. */ |
5362 | if (use_ldrd | |
5363 | && GET_CODE (x) == POST_MODIFY | |
5364 | && GET_CODE (addend) == REG) | |
5365 | return 0; | |
5366 | ||
5367 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
5368 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
5369 | } | |
6b990f6b RE |
5370 | |
5371 | /* After reload constants split into minipools will have addresses | |
5372 | from a LABEL_REF. */ | |
0bfb39ef | 5373 | else if (reload_completed |
fdd695fd PB |
5374 | && (code == LABEL_REF |
5375 | || (code == CONST | |
6b990f6b RE |
5376 | && GET_CODE (XEXP (x, 0)) == PLUS |
5377 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5378 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5379 | return 1; | |
5380 | ||
88f77cba | 5381 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
6b990f6b RE |
5382 | return 0; |
5383 | ||
fdd695fd | 5384 | else if (code == PLUS) |
6b990f6b RE |
5385 | { |
5386 | rtx xop0 = XEXP (x, 0); | |
5387 | rtx xop1 = XEXP (x, 1); | |
5388 | ||
5389 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
d37c3c62 MK |
5390 | && ((GET_CODE(xop1) == CONST_INT |
5391 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) | |
5392 | || (!strict_p && will_be_in_index_register (xop1)))) | |
6b990f6b | 5393 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 5394 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
5395 | } |
5396 | ||
5397 | #if 0 | |
5398 | /* Reload currently can't handle MINUS, so disable this for now */ | |
5399 | else if (GET_CODE (x) == MINUS) | |
5400 | { | |
5401 | rtx xop0 = XEXP (x, 0); | |
5402 | rtx xop1 = XEXP (x, 1); | |
5403 | ||
5404 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 5405 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
5406 | } |
5407 | #endif | |
5408 | ||
5409 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 5410 | && code == SYMBOL_REF |
6b990f6b RE |
5411 | && CONSTANT_POOL_ADDRESS_P (x) |
5412 | && ! (flag_pic | |
d3585b76 DJ |
5413 | && symbol_mentioned_p (get_pool_constant (x)) |
5414 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
5415 | return 1; |
5416 | ||
6b990f6b RE |
5417 | return 0; |
5418 | } | |
5419 | ||
5b3e6663 | 5420 | /* Return nonzero if X is a valid Thumb-2 address operand. */ |
c6c3dba9 | 5421 | static int |
5b3e6663 PB |
5422 | thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
5423 | { | |
5424 | bool use_ldrd; | |
5425 | enum rtx_code code = GET_CODE (x); | |
5426 | ||
5427 | if (arm_address_register_rtx_p (x, strict_p)) | |
5428 | return 1; | |
5429 | ||
5430 | use_ldrd = (TARGET_LDRD | |
5431 | && (mode == DImode | |
5432 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
5433 | ||
5434 | if (code == POST_INC || code == PRE_DEC | |
5435 | || ((code == PRE_INC || code == POST_DEC) | |
5436 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
5437 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
5438 | ||
5439 | else if ((code == POST_MODIFY || code == PRE_MODIFY) | |
5440 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
5441 | && GET_CODE (XEXP (x, 1)) == PLUS | |
5442 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
5443 | { | |
5444 | /* Thumb-2 only has autoincrement by constant. */ | |
5445 | rtx addend = XEXP (XEXP (x, 1), 1); | |
5446 | HOST_WIDE_INT offset; | |
5447 | ||
5448 | if (GET_CODE (addend) != CONST_INT) | |
5449 | return 0; | |
5450 | ||
5451 | offset = INTVAL(addend); | |
5452 | if (GET_MODE_SIZE (mode) <= 4) | |
5453 | return (offset > -256 && offset < 256); | |
5454 | ||
5455 | return (use_ldrd && offset > -1024 && offset < 1024 | |
5456 | && (offset & 3) == 0); | |
5457 | } | |
5458 | ||
5459 | /* After reload constants split into minipools will have addresses | |
5460 | from a LABEL_REF. */ | |
5461 | else if (reload_completed | |
5462 | && (code == LABEL_REF | |
5463 | || (code == CONST | |
5464 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5465 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5466 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5467 | return 1; | |
5468 | ||
88f77cba | 5469 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
5b3e6663 PB |
5470 | return 0; |
5471 | ||
5472 | else if (code == PLUS) | |
5473 | { | |
5474 | rtx xop0 = XEXP (x, 0); | |
5475 | rtx xop1 = XEXP (x, 1); | |
5476 | ||
5477 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
d37c3c62 MK |
5478 | && (thumb2_legitimate_index_p (mode, xop1, strict_p) |
5479 | || (!strict_p && will_be_in_index_register (xop1)))) | |
5b3e6663 PB |
5480 | || (arm_address_register_rtx_p (xop1, strict_p) |
5481 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | |
5482 | } | |
5483 | ||
5484 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
5485 | && code == SYMBOL_REF | |
5486 | && CONSTANT_POOL_ADDRESS_P (x) | |
5487 | && ! (flag_pic | |
5488 | && symbol_mentioned_p (get_pool_constant (x)) | |
5489 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
5490 | return 1; | |
5491 | ||
5492 | return 0; | |
5493 | } | |
5494 | ||
6b990f6b RE |
5495 | /* Return nonzero if INDEX is valid for an address index operand in |
5496 | ARM state. */ | |
5497 | static int | |
1e1ab407 RE |
5498 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
5499 | int strict_p) | |
6b990f6b RE |
5500 | { |
5501 | HOST_WIDE_INT range; | |
5502 | enum rtx_code code = GET_CODE (index); | |
5503 | ||
778ebdd9 PB |
5504 | /* Standard coprocessor addressing modes. */ |
5505 | if (TARGET_HARD_FLOAT | |
5506 | && (TARGET_FPA || TARGET_MAVERICK) | |
5507 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5508 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
5509 | return (code == CONST_INT && INTVAL (index) < 1024 |
5510 | && INTVAL (index) > -1024 | |
5511 | && (INTVAL (index) & 3) == 0); | |
5512 | ||
88f77cba JB |
5513 | if (TARGET_NEON |
5514 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
5515 | return (code == CONST_INT | |
5516 | && INTVAL (index) < 1016 | |
5517 | && INTVAL (index) > -1024 | |
5518 | && (INTVAL (index) & 3) == 0); | |
5519 | ||
5a9335ef NC |
5520 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
5521 | return (code == CONST_INT | |
3657dc3e PB |
5522 | && INTVAL (index) < 1024 |
5523 | && INTVAL (index) > -1024 | |
5524 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 5525 | |
fdd695fd PB |
5526 | if (arm_address_register_rtx_p (index, strict_p) |
5527 | && (GET_MODE_SIZE (mode) <= 4)) | |
5528 | return 1; | |
5529 | ||
5530 | if (mode == DImode || mode == DFmode) | |
5531 | { | |
5532 | if (code == CONST_INT) | |
5533 | { | |
5534 | HOST_WIDE_INT val = INTVAL (index); | |
5535 | ||
5536 | if (TARGET_LDRD) | |
5537 | return val > -256 && val < 256; | |
5538 | else | |
f372c932 | 5539 | return val > -4096 && val < 4092; |
fdd695fd PB |
5540 | } |
5541 | ||
5542 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
5543 | } | |
5544 | ||
6b990f6b | 5545 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
5546 | && ! (arm_arch4 |
5547 | && (mode == HImode | |
0fd8c3ad | 5548 | || mode == HFmode |
1e1ab407 | 5549 | || (mode == QImode && outer == SIGN_EXTEND)))) |
6b990f6b | 5550 | { |
1e1ab407 RE |
5551 | if (code == MULT) |
5552 | { | |
5553 | rtx xiop0 = XEXP (index, 0); | |
5554 | rtx xiop1 = XEXP (index, 1); | |
5555 | ||
5556 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
5557 | && power_of_two_operand (xiop1, SImode)) | |
5558 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
5559 | && power_of_two_operand (xiop0, SImode))); | |
5560 | } | |
5561 | else if (code == LSHIFTRT || code == ASHIFTRT | |
5562 | || code == ASHIFT || code == ROTATERT) | |
5563 | { | |
5564 | rtx op = XEXP (index, 1); | |
6b990f6b | 5565 | |
1e1ab407 RE |
5566 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
5567 | && GET_CODE (op) == CONST_INT | |
5568 | && INTVAL (op) > 0 | |
5569 | && INTVAL (op) <= 31); | |
5570 | } | |
6b990f6b RE |
5571 | } |
5572 | ||
1e1ab407 RE |
5573 | /* For ARM v4 we may be doing a sign-extend operation during the |
5574 | load. */ | |
e1471c91 | 5575 | if (arm_arch4) |
1e1ab407 | 5576 | { |
0fd8c3ad SL |
5577 | if (mode == HImode |
5578 | || mode == HFmode | |
5579 | || (outer == SIGN_EXTEND && mode == QImode)) | |
1e1ab407 RE |
5580 | range = 256; |
5581 | else | |
5582 | range = 4096; | |
5583 | } | |
e1471c91 | 5584 | else |
0fd8c3ad | 5585 | range = (mode == HImode || mode == HFmode) ? 4095 : 4096; |
6b990f6b RE |
5586 | |
5587 | return (code == CONST_INT | |
5588 | && INTVAL (index) < range | |
5589 | && INTVAL (index) > -range); | |
76a318e9 RE |
5590 | } |
5591 | ||
5b3e6663 PB |
5592 | /* Return true if OP is a valid index scaling factor for Thumb-2 address |
5593 | index operand. i.e. 1, 2, 4 or 8. */ | |
5594 | static bool | |
5595 | thumb2_index_mul_operand (rtx op) | |
5596 | { | |
5597 | HOST_WIDE_INT val; | |
5598 | ||
5599 | if (GET_CODE(op) != CONST_INT) | |
5600 | return false; | |
5601 | ||
5602 | val = INTVAL(op); | |
5603 | return (val == 1 || val == 2 || val == 4 || val == 8); | |
5604 | } | |
5605 | ||
5606 | /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ | |
5607 | static int | |
5608 | thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) | |
5609 | { | |
5610 | enum rtx_code code = GET_CODE (index); | |
5611 | ||
5612 | /* ??? Combine arm and thumb2 coprocessor addressing modes. */ | |
5613 | /* Standard coprocessor addressing modes. */ | |
5614 | if (TARGET_HARD_FLOAT | |
5615 | && (TARGET_FPA || TARGET_MAVERICK) | |
5616 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
5617 | || (TARGET_MAVERICK && mode == DImode))) | |
5618 | return (code == CONST_INT && INTVAL (index) < 1024 | |
5619 | && INTVAL (index) > -1024 | |
5620 | && (INTVAL (index) & 3) == 0); | |
5621 | ||
5622 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | |
fe2d934b PB |
5623 | { |
5624 | /* For DImode assume values will usually live in core regs | |
5625 | and only allow LDRD addressing modes. */ | |
5626 | if (!TARGET_LDRD || mode != DImode) | |
5627 | return (code == CONST_INT | |
5628 | && INTVAL (index) < 1024 | |
5629 | && INTVAL (index) > -1024 | |
5630 | && (INTVAL (index) & 3) == 0); | |
5631 | } | |
5b3e6663 | 5632 | |
88f77cba JB |
5633 | if (TARGET_NEON |
5634 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
5635 | return (code == CONST_INT | |
5636 | && INTVAL (index) < 1016 | |
5637 | && INTVAL (index) > -1024 | |
5638 | && (INTVAL (index) & 3) == 0); | |
5639 | ||
5b3e6663 PB |
5640 | if (arm_address_register_rtx_p (index, strict_p) |
5641 | && (GET_MODE_SIZE (mode) <= 4)) | |
5642 | return 1; | |
5643 | ||
5644 | if (mode == DImode || mode == DFmode) | |
5645 | { | |
e07e020b RR |
5646 | if (code == CONST_INT) |
5647 | { | |
5648 | HOST_WIDE_INT val = INTVAL (index); | |
5649 | /* ??? Can we assume ldrd for thumb2? */ | |
5650 | /* Thumb-2 ldrd only has reg+const addressing modes. */ | |
5651 | /* ldrd supports offsets of +-1020. | |
5652 | However the ldr fallback does not. */ | |
5653 | return val > -256 && val < 256 && (val & 3) == 0; | |
5654 | } | |
5655 | else | |
5b3e6663 | 5656 | return 0; |
5b3e6663 PB |
5657 | } |
5658 | ||
5659 | if (code == MULT) | |
5660 | { | |
5661 | rtx xiop0 = XEXP (index, 0); | |
5662 | rtx xiop1 = XEXP (index, 1); | |
5663 | ||
5664 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
5665 | && thumb2_index_mul_operand (xiop1)) | |
5666 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
5667 | && thumb2_index_mul_operand (xiop0))); | |
5668 | } | |
5669 | else if (code == ASHIFT) | |
5670 | { | |
5671 | rtx op = XEXP (index, 1); | |
5672 | ||
5673 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
5674 | && GET_CODE (op) == CONST_INT | |
5675 | && INTVAL (op) > 0 | |
5676 | && INTVAL (op) <= 3); | |
5677 | } | |
5678 | ||
5679 | return (code == CONST_INT | |
5680 | && INTVAL (index) < 4096 | |
5681 | && INTVAL (index) > -256); | |
5682 | } | |
5683 | ||
5684 | /* Return nonzero if X is valid as a 16-bit Thumb state base register. */ | |
76a318e9 | 5685 | static int |
5b3e6663 | 5686 | thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
5687 | { |
5688 | int regno; | |
5689 | ||
5690 | if (GET_CODE (x) != REG) | |
5691 | return 0; | |
5692 | ||
5693 | regno = REGNO (x); | |
5694 | ||
5695 | if (strict_p) | |
5b3e6663 | 5696 | return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode); |
76a318e9 RE |
5697 | |
5698 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 5699 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
5700 | || regno == FRAME_POINTER_REGNUM |
5701 | || (GET_MODE_SIZE (mode) >= 4 | |
5702 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 5703 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
5704 | || x == hard_frame_pointer_rtx |
5705 | || x == arg_pointer_rtx))); | |
5706 | } | |
5707 | ||
5708 | /* Return nonzero if x is a legitimate index register. This is the case | |
5709 | for any base register that can access a QImode object. */ | |
5710 | inline static int | |
5b3e6663 | 5711 | thumb1_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 | 5712 | { |
5b3e6663 | 5713 | return thumb1_base_register_rtx_p (x, QImode, strict_p); |
76a318e9 RE |
5714 | } |
5715 | ||
5b3e6663 | 5716 | /* Return nonzero if x is a legitimate 16-bit Thumb-state address. |
f676971a | 5717 | |
76a318e9 RE |
5718 | The AP may be eliminated to either the SP or the FP, so we use the |
5719 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
5720 | ||
5721 | ??? Verify whether the above is the right approach. | |
5722 | ||
5723 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
5724 | needs special handling also. | |
5725 | ||
5726 | ??? Look at how the mips16 port solves this problem. It probably uses | |
5727 | better ways to solve some of these problems. | |
5728 | ||
5729 | Although it is not incorrect, we don't accept QImode and HImode | |
5730 | addresses based on the frame pointer or arg pointer until the | |
5731 | reload pass starts. This is so that eliminating such addresses | |
5732 | into stack based ones won't produce impossible code. */ | |
c6c3dba9 | 5733 | static int |
5b3e6663 | 5734 | thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
5735 | { |
5736 | /* ??? Not clear if this is right. Experiment. */ | |
5737 | if (GET_MODE_SIZE (mode) < 4 | |
5738 | && !(reload_in_progress || reload_completed) | |
5739 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
5740 | || reg_mentioned_p (arg_pointer_rtx, x) | |
5741 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
5742 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
5743 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
5744 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
5745 | return 0; | |
5746 | ||
5747 | /* Accept any base register. SP only in SImode or larger. */ | |
5b3e6663 | 5748 | else if (thumb1_base_register_rtx_p (x, mode, strict_p)) |
76a318e9 RE |
5749 | return 1; |
5750 | ||
18dbd950 | 5751 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
5752 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
5753 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 5754 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
5755 | return 1; |
5756 | ||
18dbd950 | 5757 | /* This is PC relative data after arm_reorg runs. */ |
0fd8c3ad SL |
5758 | else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode) |
5759 | && reload_completed | |
76a318e9 RE |
5760 | && (GET_CODE (x) == LABEL_REF |
5761 | || (GET_CODE (x) == CONST | |
5762 | && GET_CODE (XEXP (x, 0)) == PLUS | |
5763 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
5764 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
5765 | return 1; | |
5766 | ||
5767 | /* Post-inc indexing only supported for SImode and larger. */ | |
5768 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
5b3e6663 | 5769 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)) |
76a318e9 RE |
5770 | return 1; |
5771 | ||
5772 | else if (GET_CODE (x) == PLUS) | |
5773 | { | |
5774 | /* REG+REG address can be any two index registers. */ | |
5775 | /* We disallow FRAME+REG addressing since we know that FRAME | |
5776 | will be replaced with STACK, and SP relative addressing only | |
5777 | permits SP+OFFSET. */ | |
5778 | if (GET_MODE_SIZE (mode) <= 4 | |
5779 | && XEXP (x, 0) != frame_pointer_rtx | |
5780 | && XEXP (x, 1) != frame_pointer_rtx | |
5b3e6663 | 5781 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
d37c3c62 MK |
5782 | && (thumb1_index_register_rtx_p (XEXP (x, 1), strict_p) |
5783 | || (!strict_p && will_be_in_index_register (XEXP (x, 1))))) | |
76a318e9 RE |
5784 | return 1; |
5785 | ||
5786 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
5b3e6663 | 5787 | else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
76a318e9 RE |
5788 | || XEXP (x, 0) == arg_pointer_rtx) |
5789 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5790 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
5791 | return 1; | |
5792 | ||
a50aa827 | 5793 | /* REG+const has 10-bit offset for SP, but only SImode and |
76a318e9 RE |
5794 | larger is supported. */ |
5795 | /* ??? Should probably check for DI/DFmode overflow here | |
5796 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
5797 | else if (GET_CODE (XEXP (x, 0)) == REG | |
5798 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
5799 | && GET_MODE_SIZE (mode) >= 4 | |
5800 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5801 | && INTVAL (XEXP (x, 1)) >= 0 | |
5802 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
5803 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
5804 | return 1; | |
5805 | ||
5806 | else if (GET_CODE (XEXP (x, 0)) == REG | |
c5289e45 RE |
5807 | && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM |
5808 | || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM | |
5809 | || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER | |
5810 | && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER)) | |
76a318e9 RE |
5811 | && GET_MODE_SIZE (mode) >= 4 |
5812 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5813 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
5814 | return 1; | |
5815 | } | |
5816 | ||
5817 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 5818 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
5819 | && GET_CODE (x) == SYMBOL_REF |
5820 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
5821 | && ! (flag_pic |
5822 | && symbol_mentioned_p (get_pool_constant (x)) | |
5823 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
5824 | return 1; |
5825 | ||
5826 | return 0; | |
5827 | } | |
5828 | ||
5829 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
5830 | instruction of mode MODE. */ | |
5831 | int | |
e32bac5b | 5832 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
5833 | { |
5834 | switch (GET_MODE_SIZE (mode)) | |
5835 | { | |
5836 | case 1: | |
5837 | return val >= 0 && val < 32; | |
5838 | ||
5839 | case 2: | |
5840 | return val >= 0 && val < 64 && (val & 1) == 0; | |
5841 | ||
5842 | default: | |
5843 | return (val >= 0 | |
5844 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
5845 | && (val & 3) == 0); | |
5846 | } | |
5847 | } | |
5848 | ||
c6c3dba9 PB |
5849 | bool |
5850 | arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
5851 | { | |
5852 | if (TARGET_ARM) | |
5853 | return arm_legitimate_address_outer_p (mode, x, SET, strict_p); | |
5854 | else if (TARGET_THUMB2) | |
5855 | return thumb2_legitimate_address_p (mode, x, strict_p); | |
5856 | else /* if (TARGET_THUMB1) */ | |
5857 | return thumb1_legitimate_address_p (mode, x, strict_p); | |
5858 | } | |
5859 | ||
d3585b76 DJ |
5860 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
5861 | ||
5862 | static GTY(()) rtx tls_get_addr_libfunc; | |
5863 | ||
5864 | static rtx | |
5865 | get_tls_get_addr (void) | |
5866 | { | |
5867 | if (!tls_get_addr_libfunc) | |
5868 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
5869 | return tls_get_addr_libfunc; | |
5870 | } | |
5871 | ||
5872 | static rtx | |
5873 | arm_load_tp (rtx target) | |
5874 | { | |
5875 | if (!target) | |
5876 | target = gen_reg_rtx (SImode); | |
5877 | ||
5878 | if (TARGET_HARD_TP) | |
5879 | { | |
5880 | /* Can return in any reg. */ | |
5881 | emit_insn (gen_load_tp_hard (target)); | |
5882 | } | |
5883 | else | |
5884 | { | |
5885 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
5886 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
5887 | clobber the value. */ | |
5888 | ||
5889 | rtx tmp; | |
5890 | ||
5891 | emit_insn (gen_load_tp_soft ()); | |
5892 | ||
5893 | tmp = gen_rtx_REG (SImode, 0); | |
5894 | emit_move_insn (target, tmp); | |
5895 | } | |
5896 | return target; | |
5897 | } | |
5898 | ||
5899 | static rtx | |
5900 | load_tls_operand (rtx x, rtx reg) | |
5901 | { | |
5902 | rtx tmp; | |
5903 | ||
5904 | if (reg == NULL_RTX) | |
5905 | reg = gen_reg_rtx (SImode); | |
5906 | ||
5907 | tmp = gen_rtx_CONST (SImode, x); | |
5908 | ||
5909 | emit_move_insn (reg, tmp); | |
5910 | ||
5911 | return reg; | |
5912 | } | |
5913 | ||
5914 | static rtx | |
5915 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
5916 | { | |
f16fe45f | 5917 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
5918 | |
5919 | start_sequence (); | |
5920 | ||
f16fe45f DJ |
5921 | labelno = GEN_INT (pic_labelno++); |
5922 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5923 | label = gen_rtx_CONST (VOIDmode, label); | |
5924 | ||
d3585b76 | 5925 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 5926 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
5927 | GEN_INT (TARGET_ARM ? 8 : 4)), |
5928 | UNSPEC_TLS); | |
5929 | reg = load_tls_operand (sum, reg); | |
5930 | ||
5931 | if (TARGET_ARM) | |
f16fe45f | 5932 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 | 5933 | else if (TARGET_THUMB2) |
87d05b44 | 5934 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
5b3e6663 | 5935 | else /* TARGET_THUMB1 */ |
f16fe45f | 5936 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
5937 | |
5938 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
5939 | Pmode, 1, reg, Pmode); | |
5940 | ||
5941 | insns = get_insns (); | |
5942 | end_sequence (); | |
5943 | ||
5944 | return insns; | |
5945 | } | |
5946 | ||
5947 | rtx | |
5948 | legitimize_tls_address (rtx x, rtx reg) | |
5949 | { | |
f16fe45f | 5950 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
5951 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
5952 | ||
5953 | switch (model) | |
5954 | { | |
5955 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
5956 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
5957 | dest = gen_reg_rtx (Pmode); | |
5958 | emit_libcall_block (insns, dest, ret, x); | |
5959 | return dest; | |
5960 | ||
5961 | case TLS_MODEL_LOCAL_DYNAMIC: | |
5962 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
5963 | ||
5964 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
5965 | share the LDM result with other LD model accesses. */ | |
5966 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
5967 | UNSPEC_TLS); | |
5968 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 5969 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
5970 | |
5971 | /* Load the addend. */ | |
5972 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
5973 | UNSPEC_TLS); | |
5974 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
5975 | return gen_rtx_PLUS (Pmode, dest, addend); | |
5976 | ||
5977 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
5978 | labelno = GEN_INT (pic_labelno++); |
5979 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
5980 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 5981 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 5982 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
5983 | GEN_INT (TARGET_ARM ? 8 : 4)), |
5984 | UNSPEC_TLS); | |
5985 | reg = load_tls_operand (sum, reg); | |
5986 | ||
5987 | if (TARGET_ARM) | |
f16fe45f | 5988 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 | 5989 | else if (TARGET_THUMB2) |
2e5505a4 | 5990 | emit_insn (gen_tls_load_dot_plus_four (reg, NULL, reg, labelno)); |
d3585b76 DJ |
5991 | else |
5992 | { | |
f16fe45f | 5993 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
5994 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
5995 | } | |
5996 | ||
5997 | tp = arm_load_tp (NULL_RTX); | |
5998 | ||
5999 | return gen_rtx_PLUS (Pmode, tp, reg); | |
6000 | ||
6001 | case TLS_MODEL_LOCAL_EXEC: | |
6002 | tp = arm_load_tp (NULL_RTX); | |
6003 | ||
6004 | reg = gen_rtx_UNSPEC (Pmode, | |
6005 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
6006 | UNSPEC_TLS); | |
6007 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
6008 | ||
6009 | return gen_rtx_PLUS (Pmode, tp, reg); | |
6010 | ||
6011 | default: | |
6012 | abort (); | |
6013 | } | |
6014 | } | |
6015 | ||
ccf4d512 RE |
6016 | /* Try machine-dependent ways of modifying an illegitimate address |
6017 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 6018 | rtx |
e32bac5b | 6019 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 6020 | { |
506d7b68 PB |
6021 | if (!TARGET_ARM) |
6022 | { | |
6023 | /* TODO: legitimize_address for Thumb2. */ | |
6024 | if (TARGET_THUMB2) | |
6025 | return x; | |
6026 | return thumb_legitimize_address (x, orig_x, mode); | |
6027 | } | |
6028 | ||
d3585b76 DJ |
6029 | if (arm_tls_symbol_p (x)) |
6030 | return legitimize_tls_address (x, NULL_RTX); | |
6031 | ||
ccf4d512 RE |
6032 | if (GET_CODE (x) == PLUS) |
6033 | { | |
6034 | rtx xop0 = XEXP (x, 0); | |
6035 | rtx xop1 = XEXP (x, 1); | |
6036 | ||
6037 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
6038 | xop0 = force_reg (SImode, xop0); | |
6039 | ||
6040 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
6041 | xop1 = force_reg (SImode, xop1); | |
6042 | ||
6043 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
6044 | && GET_CODE (xop1) == CONST_INT) | |
6045 | { | |
6046 | HOST_WIDE_INT n, low_n; | |
6047 | rtx base_reg, val; | |
6048 | n = INTVAL (xop1); | |
6049 | ||
9b66ebb1 PB |
6050 | /* VFP addressing modes actually allow greater offsets, but for |
6051 | now we just stick with the lowest common denominator. */ | |
6052 | if (mode == DImode | |
6053 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
6054 | { |
6055 | low_n = n & 0x0f; | |
6056 | n &= ~0x0f; | |
6057 | if (low_n > 4) | |
6058 | { | |
6059 | n += 16; | |
6060 | low_n -= 16; | |
6061 | } | |
6062 | } | |
6063 | else | |
6064 | { | |
6065 | low_n = ((mode) == TImode ? 0 | |
6066 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
6067 | n -= low_n; | |
6068 | } | |
6069 | ||
6070 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 6071 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 6072 | emit_move_insn (base_reg, val); |
d66437c5 | 6073 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
6074 | } |
6075 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
6076 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
6077 | } | |
6078 | ||
6079 | /* XXX We don't allow MINUS any more -- see comment in | |
c6c3dba9 | 6080 | arm_legitimate_address_outer_p (). */ |
ccf4d512 RE |
6081 | else if (GET_CODE (x) == MINUS) |
6082 | { | |
6083 | rtx xop0 = XEXP (x, 0); | |
6084 | rtx xop1 = XEXP (x, 1); | |
6085 | ||
6086 | if (CONSTANT_P (xop0)) | |
6087 | xop0 = force_reg (SImode, xop0); | |
6088 | ||
6089 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
6090 | xop1 = force_reg (SImode, xop1); | |
6091 | ||
6092 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
6093 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
6094 | } | |
6095 | ||
86805759 NP |
6096 | /* Make sure to take full advantage of the pre-indexed addressing mode |
6097 | with absolute addresses which often allows for the base register to | |
6098 | be factorized for multiple adjacent memory references, and it might | |
6099 | even allows for the mini pool to be avoided entirely. */ | |
6100 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
6101 | { | |
6102 | unsigned int bits; | |
6103 | HOST_WIDE_INT mask, base, index; | |
6104 | rtx base_reg; | |
6105 | ||
a50aa827 KH |
6106 | /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only |
6107 | use a 8-bit index. So let's use a 12-bit index for SImode only and | |
86805759 NP |
6108 | hope that arm_gen_constant will enable ldrb to use more bits. */ |
6109 | bits = (mode == SImode) ? 12 : 8; | |
6110 | mask = (1 << bits) - 1; | |
6111 | base = INTVAL (x) & ~mask; | |
6112 | index = INTVAL (x) & mask; | |
b107d743 | 6113 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
6114 | { |
6115 | /* It'll most probably be more efficient to generate the base | |
6116 | with more bits set and use a negative index instead. */ | |
6117 | base |= mask; | |
6118 | index -= mask; | |
6119 | } | |
6120 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 6121 | x = plus_constant (base_reg, index); |
86805759 NP |
6122 | } |
6123 | ||
ccf4d512 RE |
6124 | if (flag_pic) |
6125 | { | |
6126 | /* We need to find and carefully transform any SYMBOL and LABEL | |
6127 | references; so go back to the original address expression. */ | |
6128 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
6129 | ||
6130 | if (new_x != orig_x) | |
6131 | x = new_x; | |
6132 | } | |
6133 | ||
6134 | return x; | |
6135 | } | |
6136 | ||
6f5b4f3e RE |
6137 | |
6138 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
6139 | to be legitimate. If we find one, return the new, valid address. */ | |
6140 | rtx | |
6141 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
6142 | { | |
d3585b76 DJ |
6143 | if (arm_tls_symbol_p (x)) |
6144 | return legitimize_tls_address (x, NULL_RTX); | |
6145 | ||
6f5b4f3e RE |
6146 | if (GET_CODE (x) == PLUS |
6147 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6148 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
6149 | || INTVAL (XEXP (x, 1)) < 0)) | |
6150 | { | |
6151 | rtx xop0 = XEXP (x, 0); | |
6152 | rtx xop1 = XEXP (x, 1); | |
6153 | HOST_WIDE_INT offset = INTVAL (xop1); | |
6154 | ||
6155 | /* Try and fold the offset into a biasing of the base register and | |
6156 | then offsetting that. Don't do this when optimizing for space | |
6157 | since it can cause too many CSEs. */ | |
6158 | if (optimize_size && offset >= 0 | |
6159 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
6160 | { | |
6161 | HOST_WIDE_INT delta; | |
6162 | ||
6163 | if (offset >= 256) | |
6164 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
6165 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
6166 | delta = 31 * GET_MODE_SIZE (mode); | |
6167 | else | |
6168 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
6169 | ||
6170 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
6171 | NULL_RTX); | |
6172 | x = plus_constant (xop0, delta); | |
6173 | } | |
6174 | else if (offset < 0 && offset > -256) | |
6175 | /* Small negative offsets are best done with a subtract before the | |
6176 | dereference, forcing these into a register normally takes two | |
6177 | instructions. */ | |
6178 | x = force_operand (x, NULL_RTX); | |
6179 | else | |
6180 | { | |
6181 | /* For the remaining cases, force the constant into a register. */ | |
6182 | xop1 = force_reg (SImode, xop1); | |
6183 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
6184 | } | |
6185 | } | |
6186 | else if (GET_CODE (x) == PLUS | |
6187 | && s_register_operand (XEXP (x, 1), SImode) | |
6188 | && !s_register_operand (XEXP (x, 0), SImode)) | |
6189 | { | |
6190 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
6191 | ||
6192 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
6193 | } | |
6194 | ||
6195 | if (flag_pic) | |
6196 | { | |
6197 | /* We need to find and carefully transform any SYMBOL and LABEL | |
6198 | references; so go back to the original address expression. */ | |
6199 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
6200 | ||
6201 | if (new_x != orig_x) | |
6202 | x = new_x; | |
6203 | } | |
6204 | ||
6205 | return x; | |
6206 | } | |
6207 | ||
a132dad6 | 6208 | rtx |
e0b92319 NC |
6209 | thumb_legitimize_reload_address (rtx *x_p, |
6210 | enum machine_mode mode, | |
6211 | int opnum, int type, | |
6212 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
6213 | { |
6214 | rtx x = *x_p; | |
e0b92319 | 6215 | |
a132dad6 RE |
6216 | if (GET_CODE (x) == PLUS |
6217 | && GET_MODE_SIZE (mode) < 4 | |
6218 | && REG_P (XEXP (x, 0)) | |
6219 | && XEXP (x, 0) == stack_pointer_rtx | |
6220 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6221 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
6222 | { | |
6223 | rtx orig_x = x; | |
6224 | ||
6225 | x = copy_rtx (x); | |
6226 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 6227 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
6228 | return x; |
6229 | } | |
6230 | ||
6231 | /* If both registers are hi-regs, then it's better to reload the | |
6232 | entire expression rather than each register individually. That | |
6233 | only requires one reload register rather than two. */ | |
6234 | if (GET_CODE (x) == PLUS | |
6235 | && REG_P (XEXP (x, 0)) | |
6236 | && REG_P (XEXP (x, 1)) | |
6237 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
6238 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
6239 | { | |
6240 | rtx orig_x = x; | |
6241 | ||
6242 | x = copy_rtx (x); | |
6243 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 6244 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
6245 | return x; |
6246 | } | |
6247 | ||
6248 | return NULL; | |
6249 | } | |
d3585b76 DJ |
6250 | |
6251 | /* Test for various thread-local symbols. */ | |
6252 | ||
6253 | /* Return TRUE if X is a thread-local symbol. */ | |
6254 | ||
6255 | static bool | |
6256 | arm_tls_symbol_p (rtx x) | |
6257 | { | |
6258 | if (! TARGET_HAVE_TLS) | |
6259 | return false; | |
6260 | ||
6261 | if (GET_CODE (x) != SYMBOL_REF) | |
6262 | return false; | |
6263 | ||
6264 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
6265 | } | |
6266 | ||
6267 | /* Helper for arm_tls_referenced_p. */ | |
6268 | ||
6269 | static int | |
6270 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
6271 | { | |
6272 | if (GET_CODE (*x) == SYMBOL_REF) | |
6273 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
6274 | ||
6275 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
6276 | TLS offsets, not real symbol references. */ | |
6277 | if (GET_CODE (*x) == UNSPEC | |
6278 | && XINT (*x, 1) == UNSPEC_TLS) | |
6279 | return -1; | |
6280 | ||
6281 | return 0; | |
6282 | } | |
6283 | ||
6284 | /* Return TRUE if X contains any TLS symbol references. */ | |
6285 | ||
6286 | bool | |
6287 | arm_tls_referenced_p (rtx x) | |
6288 | { | |
6289 | if (! TARGET_HAVE_TLS) | |
6290 | return false; | |
6291 | ||
6292 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
6293 | } | |
8426b956 RS |
6294 | |
6295 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
6296 | ||
6297 | bool | |
6298 | arm_cannot_force_const_mem (rtx x) | |
6299 | { | |
6300 | rtx base, offset; | |
6301 | ||
6302 | if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
6303 | { | |
6304 | split_const (x, &base, &offset); | |
6305 | if (GET_CODE (base) == SYMBOL_REF | |
6306 | && !offset_within_block_p (base, INTVAL (offset))) | |
6307 | return true; | |
6308 | } | |
6309 | return arm_tls_referenced_p (x); | |
6310 | } | |
6b990f6b | 6311 | \f |
e2c671ba RE |
6312 | #define REG_OR_SUBREG_REG(X) \ |
6313 | (GET_CODE (X) == REG \ | |
6314 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
6315 | ||
6316 | #define REG_OR_SUBREG_RTX(X) \ | |
6317 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
6318 | ||
3c50106f | 6319 | static inline int |
5b3e6663 | 6320 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
6321 | { |
6322 | enum machine_mode mode = GET_MODE (x); | |
e4c6a07a | 6323 | int total; |
e2c671ba | 6324 | |
9b66ebb1 | 6325 | switch (code) |
d5b7b3ae | 6326 | { |
9b66ebb1 PB |
6327 | case ASHIFT: |
6328 | case ASHIFTRT: | |
6329 | case LSHIFTRT: | |
f676971a | 6330 | case ROTATERT: |
9b66ebb1 PB |
6331 | case PLUS: |
6332 | case MINUS: | |
6333 | case COMPARE: | |
6334 | case NEG: | |
f676971a | 6335 | case NOT: |
9b66ebb1 | 6336 | return COSTS_N_INSNS (1); |
f676971a EC |
6337 | |
6338 | case MULT: | |
6339 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6340 | { | |
6341 | int cycles = 0; | |
9b66ebb1 | 6342 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
6343 | |
6344 | while (i) | |
6345 | { | |
6346 | i >>= 2; | |
6347 | cycles++; | |
6348 | } | |
6349 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
6350 | } |
6351 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
6352 | |
6353 | case SET: | |
6354 | return (COSTS_N_INSNS (1) | |
6355 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 6356 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
6357 | |
6358 | case CONST_INT: | |
6359 | if (outer == SET) | |
6360 | { | |
6361 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
6362 | return 0; | |
6363 | if (thumb_shiftable_const (INTVAL (x))) | |
6364 | return COSTS_N_INSNS (2); | |
6365 | return COSTS_N_INSNS (3); | |
6366 | } | |
9b66ebb1 | 6367 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 6368 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 | 6369 | return 0; |
582021ba | 6370 | else if ((outer == IOR || outer == XOR || outer == AND) |
9b66ebb1 PB |
6371 | && INTVAL (x) < 256 && INTVAL (x) >= -256) |
6372 | return COSTS_N_INSNS (1); | |
c99102b8 BS |
6373 | else if (outer == AND) |
6374 | { | |
6375 | int i; | |
6376 | /* This duplicates the tests in the andsi3 expander. */ | |
6377 | for (i = 9; i <= 31; i++) | |
6378 | if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x) | |
6379 | || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x)) | |
6380 | return COSTS_N_INSNS (2); | |
6381 | } | |
f676971a EC |
6382 | else if (outer == ASHIFT || outer == ASHIFTRT |
6383 | || outer == LSHIFTRT) | |
6384 | return 0; | |
9b66ebb1 | 6385 | return COSTS_N_INSNS (2); |
f676971a EC |
6386 | |
6387 | case CONST: | |
6388 | case CONST_DOUBLE: | |
6389 | case LABEL_REF: | |
6390 | case SYMBOL_REF: | |
9b66ebb1 | 6391 | return COSTS_N_INSNS (3); |
f676971a | 6392 | |
9b66ebb1 PB |
6393 | case UDIV: |
6394 | case UMOD: | |
6395 | case DIV: | |
6396 | case MOD: | |
6397 | return 100; | |
d5b7b3ae | 6398 | |
9b66ebb1 PB |
6399 | case TRUNCATE: |
6400 | return 99; | |
d5b7b3ae | 6401 | |
9b66ebb1 PB |
6402 | case AND: |
6403 | case XOR: | |
f676971a | 6404 | case IOR: |
ff482c8d | 6405 | /* XXX guess. */ |
9b66ebb1 | 6406 | return 8; |
d5b7b3ae | 6407 | |
9b66ebb1 PB |
6408 | case MEM: |
6409 | /* XXX another guess. */ | |
6410 | /* Memory costs quite a lot for the first word, but subsequent words | |
6411 | load at the equivalent of a single insn each. */ | |
6412 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
6413 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
6414 | ? 4 : 0)); | |
6415 | ||
6416 | case IF_THEN_ELSE: | |
ff482c8d | 6417 | /* XXX a guess. */ |
9b66ebb1 PB |
6418 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
6419 | return 14; | |
6420 | return 2; | |
6421 | ||
e4c6a07a | 6422 | case SIGN_EXTEND: |
9b66ebb1 | 6423 | case ZERO_EXTEND: |
e4c6a07a BS |
6424 | total = mode == DImode ? COSTS_N_INSNS (1) : 0; |
6425 | total += thumb1_rtx_costs (XEXP (x, 0), GET_CODE (XEXP (x, 0)), code); | |
f676971a | 6426 | |
e4c6a07a BS |
6427 | if (mode == SImode) |
6428 | return total; | |
f676971a | 6429 | |
e4c6a07a BS |
6430 | if (arm_arch6) |
6431 | return total + COSTS_N_INSNS (1); | |
f676971a | 6432 | |
e4c6a07a BS |
6433 | /* Assume a two-shift sequence. Increase the cost slightly so |
6434 | we prefer actual shifts over an extend operation. */ | |
6435 | return total + 1 + COSTS_N_INSNS (2); | |
f676971a | 6436 | |
9b66ebb1 PB |
6437 | default: |
6438 | return 99; | |
d5b7b3ae | 6439 | } |
9b66ebb1 PB |
6440 | } |
6441 | ||
d5a0a47b RE |
6442 | static inline bool |
6443 | arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) | |
9b66ebb1 PB |
6444 | { |
6445 | enum machine_mode mode = GET_MODE (x); | |
6446 | enum rtx_code subcode; | |
d5a0a47b RE |
6447 | rtx operand; |
6448 | enum rtx_code code = GET_CODE (x); | |
d5a0a47b | 6449 | *total = 0; |
9b66ebb1 | 6450 | |
e2c671ba RE |
6451 | switch (code) |
6452 | { | |
6453 | case MEM: | |
6454 | /* Memory costs quite a lot for the first word, but subsequent words | |
6455 | load at the equivalent of a single insn each. */ | |
d5a0a47b RE |
6456 | *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); |
6457 | return true; | |
e2c671ba RE |
6458 | |
6459 | case DIV: | |
6460 | case MOD: | |
b9c53150 RS |
6461 | case UDIV: |
6462 | case UMOD: | |
d5a0a47b RE |
6463 | if (TARGET_HARD_FLOAT && mode == SFmode) |
6464 | *total = COSTS_N_INSNS (2); | |
e0dc3601 | 6465 | else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE) |
d5a0a47b RE |
6466 | *total = COSTS_N_INSNS (4); |
6467 | else | |
6468 | *total = COSTS_N_INSNS (20); | |
6469 | return false; | |
e2c671ba RE |
6470 | |
6471 | case ROTATE: | |
d5a0a47b RE |
6472 | if (GET_CODE (XEXP (x, 1)) == REG) |
6473 | *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ | |
6474 | else if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6475 | *total = rtx_cost (XEXP (x, 1), code, speed); | |
6476 | ||
e2c671ba RE |
6477 | /* Fall through */ |
6478 | case ROTATERT: | |
6479 | if (mode != SImode) | |
d5a0a47b RE |
6480 | { |
6481 | *total += COSTS_N_INSNS (4); | |
6482 | return true; | |
6483 | } | |
6484 | ||
e2c671ba RE |
6485 | /* Fall through */ |
6486 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
d5a0a47b | 6487 | *total += rtx_cost (XEXP (x, 0), code, speed); |
e2c671ba | 6488 | if (mode == DImode) |
d5a0a47b RE |
6489 | { |
6490 | *total += COSTS_N_INSNS (3); | |
6491 | return true; | |
6492 | } | |
7612f14d | 6493 | |
d5a0a47b | 6494 | *total += COSTS_N_INSNS (1); |
7612f14d PB |
6495 | /* Increase the cost of complex shifts because they aren't any faster, |
6496 | and reduce dual issue opportunities. */ | |
6497 | if (arm_tune_cortex_a9 | |
6498 | && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
d5a0a47b RE |
6499 | ++*total; |
6500 | ||
6501 | return true; | |
e2c671ba RE |
6502 | |
6503 | case MINUS: | |
6504 | if (mode == DImode) | |
d5a0a47b RE |
6505 | { |
6506 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
6507 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
6508 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
6509 | { | |
6510 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6511 | return true; | |
6512 | } | |
6513 | ||
6514 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6515 | && const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
6516 | { | |
6517 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6518 | return true; | |
6519 | } | |
6520 | ||
6521 | return false; | |
6522 | } | |
e2c671ba RE |
6523 | |
6524 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b | 6525 | { |
e0dc3601 PB |
6526 | if (TARGET_HARD_FLOAT |
6527 | && (mode == SFmode | |
6528 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6529 | { |
6530 | *total = COSTS_N_INSNS (1); | |
6531 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
6532 | && arm_const_double_rtx (XEXP (x, 0))) | |
6533 | { | |
6534 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6535 | return true; | |
6536 | } | |
6537 | ||
6538 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
6539 | && arm_const_double_rtx (XEXP (x, 1))) | |
6540 | { | |
6541 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6542 | return true; | |
6543 | } | |
6544 | ||
6545 | return false; | |
6546 | } | |
6547 | *total = COSTS_N_INSNS (20); | |
6548 | return false; | |
6549 | } | |
6550 | ||
6551 | *total = COSTS_N_INSNS (1); | |
6552 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
6553 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
6554 | { | |
6555 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6556 | return true; | |
6557 | } | |
6558 | ||
6559 | subcode = GET_CODE (XEXP (x, 1)); | |
6560 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6561 | || subcode == LSHIFTRT | |
6562 | || subcode == ROTATE || subcode == ROTATERT) | |
6563 | { | |
6564 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6565 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
6566 | return true; | |
6567 | } | |
6568 | ||
b32f6fff KH |
6569 | /* A shift as a part of RSB costs no more than RSB itself. */ |
6570 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 6571 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
b32f6fff KH |
6572 | { |
6573 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, speed); | |
6574 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6575 | return true; | |
6576 | } | |
6577 | ||
d5a0a47b | 6578 | if (subcode == MULT |
4c7c486a | 6579 | && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode)) |
d5a0a47b RE |
6580 | { |
6581 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6582 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
6583 | return true; | |
6584 | } | |
6585 | ||
6586 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE | |
6587 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) | |
6588 | { | |
6589 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
6590 | if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
6591 | && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) | |
6592 | *total += COSTS_N_INSNS (1); | |
6593 | ||
6594 | return true; | |
6595 | } | |
6596 | ||
e2c671ba RE |
6597 | /* Fall through */ |
6598 | ||
f676971a | 6599 | case PLUS: |
d5a0a47b | 6600 | if (code == PLUS && arm_arch6 && mode == SImode |
ff069900 PB |
6601 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND |
6602 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
6603 | { |
6604 | *total = COSTS_N_INSNS (1); | |
6605 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)), | |
6606 | speed); | |
6607 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6608 | return true; | |
6609 | } | |
ff069900 | 6610 | |
d5a0a47b RE |
6611 | /* MLA: All arguments must be registers. We filter out |
6612 | multiplication by a power of two, so that we fall down into | |
6613 | the code below. */ | |
6614 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 6615 | && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
26da58dd | 6616 | { |
d5a0a47b RE |
6617 | /* The cost comes from the cost of the multiply. */ |
6618 | return false; | |
26da58dd PB |
6619 | } |
6620 | ||
e2c671ba | 6621 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b | 6622 | { |
e0dc3601 PB |
6623 | if (TARGET_HARD_FLOAT |
6624 | && (mode == SFmode | |
6625 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6626 | { |
6627 | *total = COSTS_N_INSNS (1); | |
6628 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
6629 | && arm_const_double_rtx (XEXP (x, 1))) | |
6630 | { | |
6631 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6632 | return true; | |
6633 | } | |
6634 | ||
6635 | return false; | |
6636 | } | |
6637 | ||
6638 | *total = COSTS_N_INSNS (20); | |
6639 | return false; | |
6640 | } | |
6641 | ||
6642 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE | |
6643 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) | |
6644 | { | |
6645 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, speed); | |
6646 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
6647 | && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) | |
6648 | *total += COSTS_N_INSNS (1); | |
6649 | return true; | |
6650 | } | |
e2c671ba RE |
6651 | |
6652 | /* Fall through */ | |
d5a0a47b | 6653 | |
f676971a | 6654 | case AND: case XOR: case IOR: |
e2c671ba RE |
6655 | |
6656 | /* Normally the frame registers will be spilt into reg+const during | |
6657 | reload, so it is a bad idea to combine them with other instructions, | |
6658 | since then they might not be moved outside of loops. As a compromise | |
6659 | we allow integration with ops that have a constant as their second | |
6660 | operand. */ | |
13cc4787 BS |
6661 | if (REG_OR_SUBREG_REG (XEXP (x, 0)) |
6662 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
6663 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6664 | *total = COSTS_N_INSNS (1); | |
e2c671ba RE |
6665 | |
6666 | if (mode == DImode) | |
d5a0a47b RE |
6667 | { |
6668 | *total += COSTS_N_INSNS (2); | |
6669 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6670 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
6671 | { | |
6672 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6673 | return true; | |
6674 | } | |
e2c671ba | 6675 | |
d5a0a47b RE |
6676 | return false; |
6677 | } | |
6678 | ||
6679 | *total += COSTS_N_INSNS (1); | |
6680 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6681 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
6682 | { | |
6683 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6684 | return true; | |
6685 | } | |
6686 | subcode = GET_CODE (XEXP (x, 0)); | |
6687 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6688 | || subcode == LSHIFTRT | |
6689 | || subcode == ROTATE || subcode == ROTATERT) | |
6690 | { | |
6691 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6692 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6693 | return true; | |
6694 | } | |
6695 | ||
6696 | if (subcode == MULT | |
4c7c486a | 6697 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
6698 | { |
6699 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6700 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6701 | return true; | |
6702 | } | |
6703 | ||
6704 | if (subcode == UMIN || subcode == UMAX | |
6705 | || subcode == SMIN || subcode == SMAX) | |
6706 | { | |
6707 | *total = COSTS_N_INSNS (3); | |
6708 | return true; | |
6709 | } | |
6710 | ||
6711 | return false; | |
e2c671ba RE |
6712 | |
6713 | case MULT: | |
9b66ebb1 | 6714 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 6715 | gcc_unreachable (); |
e2c671ba | 6716 | |
56636818 | 6717 | case TRUNCATE: |
9b66ebb1 | 6718 | if (arm_arch3m && mode == SImode |
56636818 JL |
6719 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
6720 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
6721 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
6722 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
6723 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
6724 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
6725 | { |
6726 | *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, speed); | |
6727 | return true; | |
6728 | } | |
6729 | *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */ | |
6730 | return false; | |
56636818 | 6731 | |
e2c671ba RE |
6732 | case NEG: |
6733 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b | 6734 | { |
e0dc3601 PB |
6735 | if (TARGET_HARD_FLOAT |
6736 | && (mode == SFmode | |
6737 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6738 | { |
6739 | *total = COSTS_N_INSNS (1); | |
6740 | return false; | |
6741 | } | |
6742 | *total = COSTS_N_INSNS (2); | |
6743 | return false; | |
6744 | } | |
6745 | ||
e2c671ba RE |
6746 | /* Fall through */ |
6747 | case NOT: | |
d5a0a47b RE |
6748 | *total = COSTS_N_INSNS (ARM_NUM_REGS(mode)); |
6749 | if (mode == SImode && code == NOT) | |
6750 | { | |
6751 | subcode = GET_CODE (XEXP (x, 0)); | |
6752 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6753 | || subcode == LSHIFTRT | |
6754 | || subcode == ROTATE || subcode == ROTATERT | |
6755 | || (subcode == MULT | |
4c7c486a | 6756 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))) |
d5a0a47b RE |
6757 | { |
6758 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6759 | /* Register shifts cost an extra cycle. */ | |
6760 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
6761 | *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), | |
6762 | subcode, speed); | |
6763 | return true; | |
6764 | } | |
6765 | } | |
e2c671ba | 6766 | |
d5a0a47b | 6767 | return false; |
e2c671ba RE |
6768 | |
6769 | case IF_THEN_ELSE: | |
6770 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
d5a0a47b RE |
6771 | { |
6772 | *total = COSTS_N_INSNS (4); | |
6773 | return true; | |
6774 | } | |
6775 | ||
6776 | operand = XEXP (x, 0); | |
6777 | ||
6778 | if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE | |
6779 | || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) | |
6780 | && GET_CODE (XEXP (operand, 0)) == REG | |
6781 | && REGNO (XEXP (operand, 0)) == CC_REGNUM)) | |
6782 | *total += COSTS_N_INSNS (1); | |
6783 | *total += (rtx_cost (XEXP (x, 1), code, speed) | |
6784 | + rtx_cost (XEXP (x, 2), code, speed)); | |
6785 | return true; | |
6786 | ||
6787 | case NE: | |
6788 | if (mode == SImode && XEXP (x, 1) == const0_rtx) | |
6789 | { | |
6790 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
6791 | return true; | |
6792 | } | |
6793 | goto scc_insn; | |
6794 | ||
6795 | case GE: | |
6796 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
6797 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
6798 | { | |
6799 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
6800 | return true; | |
6801 | } | |
6802 | goto scc_insn; | |
6803 | ||
6804 | case LT: | |
6805 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
6806 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
6807 | { | |
6808 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
6809 | return true; | |
6810 | } | |
6811 | goto scc_insn; | |
6812 | ||
6813 | case EQ: | |
6814 | case GT: | |
6815 | case LE: | |
6816 | case GEU: | |
6817 | case LTU: | |
6818 | case GTU: | |
6819 | case LEU: | |
6820 | case UNORDERED: | |
6821 | case ORDERED: | |
6822 | case UNEQ: | |
6823 | case UNGE: | |
6824 | case UNLT: | |
6825 | case UNGT: | |
6826 | case UNLE: | |
6827 | scc_insn: | |
6828 | /* SCC insns. In the case where the comparison has already been | |
6829 | performed, then they cost 2 instructions. Otherwise they need | |
6830 | an additional comparison before them. */ | |
6831 | *total = COSTS_N_INSNS (2); | |
6832 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) | |
6833 | { | |
6834 | return true; | |
6835 | } | |
e2c671ba | 6836 | |
d5a0a47b | 6837 | /* Fall through */ |
e2c671ba | 6838 | case COMPARE: |
d5a0a47b RE |
6839 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) |
6840 | { | |
6841 | *total = 0; | |
6842 | return true; | |
6843 | } | |
6844 | ||
6845 | *total += COSTS_N_INSNS (1); | |
6846 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6847 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
6848 | { | |
6849 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6850 | return true; | |
6851 | } | |
6852 | ||
6853 | subcode = GET_CODE (XEXP (x, 0)); | |
6854 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
6855 | || subcode == LSHIFTRT | |
6856 | || subcode == ROTATE || subcode == ROTATERT) | |
6857 | { | |
6858 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6859 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6860 | return true; | |
6861 | } | |
6862 | ||
6863 | if (subcode == MULT | |
4c7c486a | 6864 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
6865 | { |
6866 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6867 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
6868 | return true; | |
6869 | } | |
6870 | ||
6871 | return false; | |
6872 | ||
6873 | case UMIN: | |
6874 | case UMAX: | |
6875 | case SMIN: | |
6876 | case SMAX: | |
6877 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
6878 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
6879 | || !const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
6880 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
6881 | return true; | |
e2c671ba RE |
6882 | |
6883 | case ABS: | |
bbbbb16a | 6884 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b | 6885 | { |
e0dc3601 PB |
6886 | if (TARGET_HARD_FLOAT |
6887 | && (mode == SFmode | |
6888 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
6889 | { |
6890 | *total = COSTS_N_INSNS (1); | |
6891 | return false; | |
6892 | } | |
6893 | *total = COSTS_N_INSNS (20); | |
6894 | return false; | |
6895 | } | |
6896 | *total = COSTS_N_INSNS (1); | |
6897 | if (mode == DImode) | |
6898 | *total += COSTS_N_INSNS (3); | |
6899 | return false; | |
e2c671ba RE |
6900 | |
6901 | case SIGN_EXTEND: | |
e2c671ba | 6902 | case ZERO_EXTEND: |
d5a0a47b RE |
6903 | *total = 0; |
6904 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
e2c671ba | 6905 | { |
e4c6a07a BS |
6906 | rtx op = XEXP (x, 0); |
6907 | enum machine_mode opmode = GET_MODE (op); | |
6908 | ||
d5a0a47b RE |
6909 | if (mode == DImode) |
6910 | *total += COSTS_N_INSNS (1); | |
e2c671ba | 6911 | |
e4c6a07a | 6912 | if (opmode != SImode) |
d5a0a47b | 6913 | { |
e4c6a07a | 6914 | if (MEM_P (op)) |
d5a0a47b | 6915 | { |
e4c6a07a BS |
6916 | /* If !arm_arch4, we use one of the extendhisi2_mem |
6917 | or movhi_bytes patterns for HImode. For a QImode | |
6918 | sign extension, we first zero-extend from memory | |
6919 | and then perform a shift sequence. */ | |
6920 | if (!arm_arch4 && (opmode != QImode || code == SIGN_EXTEND)) | |
6921 | *total += COSTS_N_INSNS (2); | |
d5a0a47b | 6922 | } |
e4c6a07a BS |
6923 | else if (arm_arch6) |
6924 | *total += COSTS_N_INSNS (1); | |
6925 | ||
6926 | /* We don't have the necessary insn, so we need to perform some | |
6927 | other operation. */ | |
6928 | else if (TARGET_ARM && code == ZERO_EXTEND && mode == QImode) | |
6929 | /* An and with constant 255. */ | |
6930 | *total += COSTS_N_INSNS (1); | |
6931 | else | |
6932 | /* A shift sequence. Increase costs slightly to avoid | |
6933 | combining two shifts into an extend operation. */ | |
6934 | *total += COSTS_N_INSNS (2) + 1; | |
d5a0a47b | 6935 | } |
e2c671ba | 6936 | |
d5a0a47b RE |
6937 | return false; |
6938 | } | |
ad076f4e | 6939 | |
d5a0a47b RE |
6940 | switch (GET_MODE (XEXP (x, 0))) |
6941 | { | |
5a9335ef NC |
6942 | case V8QImode: |
6943 | case V4HImode: | |
6944 | case V2SImode: | |
6945 | case V4QImode: | |
6946 | case V2HImode: | |
d5a0a47b RE |
6947 | *total = COSTS_N_INSNS (1); |
6948 | return false; | |
5a9335ef | 6949 | |
ad076f4e | 6950 | default: |
e6d29d15 | 6951 | gcc_unreachable (); |
e2c671ba | 6952 | } |
e6d29d15 | 6953 | gcc_unreachable (); |
e2c671ba | 6954 | |
d5a0a47b RE |
6955 | case ZERO_EXTRACT: |
6956 | case SIGN_EXTRACT: | |
6957 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
6958 | return true; | |
6959 | ||
f676971a | 6960 | case CONST_INT: |
d5a0a47b RE |
6961 | if (const_ok_for_arm (INTVAL (x)) |
6962 | || const_ok_for_arm (~INTVAL (x))) | |
6963 | *total = COSTS_N_INSNS (1); | |
f676971a | 6964 | else |
d5a0a47b RE |
6965 | *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX, |
6966 | INTVAL (x), NULL_RTX, | |
6967 | NULL_RTX, 0, 0)); | |
6968 | return true; | |
f676971a EC |
6969 | |
6970 | case CONST: | |
6971 | case LABEL_REF: | |
6972 | case SYMBOL_REF: | |
d5a0a47b RE |
6973 | *total = COSTS_N_INSNS (3); |
6974 | return true; | |
f676971a | 6975 | |
571191af | 6976 | case HIGH: |
d5a0a47b RE |
6977 | *total = COSTS_N_INSNS (1); |
6978 | return true; | |
6979 | ||
571191af | 6980 | case LO_SUM: |
d5a0a47b RE |
6981 | *total = COSTS_N_INSNS (1); |
6982 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
6983 | return true; | |
571191af | 6984 | |
f676971a | 6985 | case CONST_DOUBLE: |
e0dc3601 PB |
6986 | if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x) |
6987 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
d5a0a47b RE |
6988 | *total = COSTS_N_INSNS (1); |
6989 | else | |
6990 | *total = COSTS_N_INSNS (4); | |
6991 | return true; | |
f676971a | 6992 | |
e2c671ba | 6993 | default: |
d5a0a47b RE |
6994 | *total = COSTS_N_INSNS (4); |
6995 | return false; | |
e2c671ba RE |
6996 | } |
6997 | } | |
32de079a | 6998 | |
7548c1be WG |
6999 | /* Estimates the size cost of thumb1 instructions. |
7000 | For now most of the code is copied from thumb1_rtx_costs. We need more | |
7001 | fine grain tuning when we have more related test cases. */ | |
7002 | static inline int | |
7003 | thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) | |
7004 | { | |
7005 | enum machine_mode mode = GET_MODE (x); | |
7006 | ||
7007 | switch (code) | |
7008 | { | |
7009 | case ASHIFT: | |
7010 | case ASHIFTRT: | |
7011 | case LSHIFTRT: | |
7012 | case ROTATERT: | |
7013 | case PLUS: | |
7014 | case MINUS: | |
7015 | case COMPARE: | |
7016 | case NEG: | |
7017 | case NOT: | |
7018 | return COSTS_N_INSNS (1); | |
7019 | ||
7020 | case MULT: | |
7021 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7022 | { | |
7023 | /* Thumb1 mul instruction can't operate on const. We must Load it | |
7024 | into a register first. */ | |
7025 | int const_size = thumb1_size_rtx_costs (XEXP (x, 1), CONST_INT, SET); | |
7026 | return COSTS_N_INSNS (1) + const_size; | |
7027 | } | |
7028 | return COSTS_N_INSNS (1); | |
7029 | ||
7030 | case SET: | |
7031 | return (COSTS_N_INSNS (1) | |
7032 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
7033 | + GET_CODE (SET_DEST (x)) == MEM)); | |
7034 | ||
7035 | case CONST_INT: | |
7036 | if (outer == SET) | |
7037 | { | |
7038 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
9b9ee6d3 | 7039 | return COSTS_N_INSNS (1); |
3393e880 MK |
7040 | /* See split "TARGET_THUMB1 && satisfies_constraint_J". */ |
7041 | if (INTVAL (x) >= -255 && INTVAL (x) <= -1) | |
7042 | return COSTS_N_INSNS (2); | |
7043 | /* See split "TARGET_THUMB1 && satisfies_constraint_K". */ | |
7548c1be WG |
7044 | if (thumb_shiftable_const (INTVAL (x))) |
7045 | return COSTS_N_INSNS (2); | |
7046 | return COSTS_N_INSNS (3); | |
7047 | } | |
7048 | else if ((outer == PLUS || outer == COMPARE) | |
7049 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
7050 | return 0; | |
7051 | else if ((outer == IOR || outer == XOR || outer == AND) | |
7052 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
7053 | return COSTS_N_INSNS (1); | |
7054 | else if (outer == AND) | |
7055 | { | |
7056 | int i; | |
7057 | /* This duplicates the tests in the andsi3 expander. */ | |
7058 | for (i = 9; i <= 31; i++) | |
7059 | if ((((HOST_WIDE_INT) 1) << i) - 1 == INTVAL (x) | |
7060 | || (((HOST_WIDE_INT) 1) << i) - 1 == ~INTVAL (x)) | |
7061 | return COSTS_N_INSNS (2); | |
7062 | } | |
7063 | else if (outer == ASHIFT || outer == ASHIFTRT | |
7064 | || outer == LSHIFTRT) | |
7065 | return 0; | |
7066 | return COSTS_N_INSNS (2); | |
7067 | ||
7068 | case CONST: | |
7069 | case CONST_DOUBLE: | |
7070 | case LABEL_REF: | |
7071 | case SYMBOL_REF: | |
7072 | return COSTS_N_INSNS (3); | |
7073 | ||
7074 | case UDIV: | |
7075 | case UMOD: | |
7076 | case DIV: | |
7077 | case MOD: | |
7078 | return 100; | |
7079 | ||
7080 | case TRUNCATE: | |
7081 | return 99; | |
7082 | ||
7083 | case AND: | |
7084 | case XOR: | |
7085 | case IOR: | |
7086 | /* XXX guess. */ | |
7087 | return 8; | |
7088 | ||
7089 | case MEM: | |
7090 | /* XXX another guess. */ | |
7091 | /* Memory costs quite a lot for the first word, but subsequent words | |
7092 | load at the equivalent of a single insn each. */ | |
7093 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
7094 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
7095 | ? 4 : 0)); | |
7096 | ||
7097 | case IF_THEN_ELSE: | |
7098 | /* XXX a guess. */ | |
7099 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
7100 | return 14; | |
7101 | return 2; | |
7102 | ||
7103 | case ZERO_EXTEND: | |
7104 | /* XXX still guessing. */ | |
7105 | switch (GET_MODE (XEXP (x, 0))) | |
7106 | { | |
7107 | case QImode: | |
7108 | return (1 + (mode == DImode ? 4 : 0) | |
7109 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7110 | ||
7111 | case HImode: | |
7112 | return (4 + (mode == DImode ? 4 : 0) | |
7113 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7114 | ||
7115 | case SImode: | |
7116 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
7117 | ||
7118 | default: | |
7119 | return 99; | |
7120 | } | |
7121 | ||
7122 | default: | |
7123 | return 99; | |
7124 | } | |
7125 | } | |
7126 | ||
21b5653c RE |
7127 | /* RTX costs when optimizing for size. */ |
7128 | static bool | |
d5a0a47b RE |
7129 | arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7130 | int *total) | |
21b5653c RE |
7131 | { |
7132 | enum machine_mode mode = GET_MODE (x); | |
09754904 | 7133 | if (TARGET_THUMB1) |
21b5653c | 7134 | { |
7548c1be | 7135 | *total = thumb1_size_rtx_costs (x, code, outer_code); |
21b5653c RE |
7136 | return true; |
7137 | } | |
7138 | ||
09754904 | 7139 | /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */ |
21b5653c RE |
7140 | switch (code) |
7141 | { | |
7142 | case MEM: | |
f676971a | 7143 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
7144 | a single register, otherwise it costs one insn per word. */ |
7145 | if (REG_P (XEXP (x, 0))) | |
7146 | *total = COSTS_N_INSNS (1); | |
d37c3c62 MK |
7147 | else if (flag_pic |
7148 | && GET_CODE (XEXP (x, 0)) == PLUS | |
7149 | && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) | |
7150 | /* This will be split into two instructions. | |
7151 | See arm.md:calculate_pic_address. */ | |
7152 | *total = COSTS_N_INSNS (2); | |
21b5653c RE |
7153 | else |
7154 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7155 | return true; | |
7156 | ||
7157 | case DIV: | |
7158 | case MOD: | |
7159 | case UDIV: | |
7160 | case UMOD: | |
7161 | /* Needs a libcall, so it costs about this. */ | |
7162 | *total = COSTS_N_INSNS (2); | |
7163 | return false; | |
7164 | ||
7165 | case ROTATE: | |
7166 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
7167 | { | |
f40751dd | 7168 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7169 | return true; |
7170 | } | |
7171 | /* Fall through */ | |
7172 | case ROTATERT: | |
7173 | case ASHIFT: | |
7174 | case LSHIFTRT: | |
7175 | case ASHIFTRT: | |
7176 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7177 | { | |
f40751dd | 7178 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7179 | return true; |
7180 | } | |
7181 | else if (mode == SImode) | |
7182 | { | |
f40751dd | 7183 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
7184 | /* Slightly disparage register shifts, but not by much. */ |
7185 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
f40751dd | 7186 | *total += 1 + rtx_cost (XEXP (x, 1), code, false); |
21b5653c RE |
7187 | return true; |
7188 | } | |
7189 | ||
7190 | /* Needs a libcall. */ | |
7191 | *total = COSTS_N_INSNS (2); | |
7192 | return false; | |
7193 | ||
7194 | case MINUS: | |
e0dc3601 PB |
7195 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7196 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7197 | { |
7198 | *total = COSTS_N_INSNS (1); | |
7199 | return false; | |
7200 | } | |
7201 | ||
7202 | if (mode == SImode) | |
7203 | { | |
7204 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
7205 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
7206 | ||
7207 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
7208 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
7209 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
7210 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
7211 | || subcode1 == ASHIFTRT) | |
7212 | { | |
7213 | /* It's just the cost of the two operands. */ | |
7214 | *total = 0; | |
7215 | return false; | |
7216 | } | |
7217 | ||
7218 | *total = COSTS_N_INSNS (1); | |
7219 | return false; | |
7220 | } | |
7221 | ||
7222 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7223 | return false; | |
7224 | ||
f676971a | 7225 | case PLUS: |
e0dc3601 PB |
7226 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7227 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7228 | { |
7229 | *total = COSTS_N_INSNS (1); | |
7230 | return false; | |
7231 | } | |
7232 | ||
6e782a29 KH |
7233 | /* A shift as a part of ADD costs nothing. */ |
7234 | if (GET_CODE (XEXP (x, 0)) == MULT | |
7235 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) | |
7236 | { | |
7237 | *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1); | |
7238 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, false); | |
7239 | *total += rtx_cost (XEXP (x, 1), code, false); | |
7240 | return true; | |
7241 | } | |
7242 | ||
21b5653c RE |
7243 | /* Fall through */ |
7244 | case AND: case XOR: case IOR: | |
7245 | if (mode == SImode) | |
7246 | { | |
7247 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
7248 | ||
7249 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
7250 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
7251 | || (code == AND && subcode == NOT)) | |
7252 | { | |
7253 | /* It's just the cost of the two operands. */ | |
7254 | *total = 0; | |
7255 | return false; | |
7256 | } | |
7257 | } | |
7258 | ||
7259 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7260 | return false; | |
7261 | ||
7262 | case MULT: | |
7263 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7264 | return false; | |
7265 | ||
7266 | case NEG: | |
e0dc3601 PB |
7267 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7268 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
7ce8451d MG |
7269 | { |
7270 | *total = COSTS_N_INSNS (1); | |
7271 | return false; | |
7272 | } | |
7273 | ||
21b5653c RE |
7274 | /* Fall through */ |
7275 | case NOT: | |
7276 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7277 | ||
7278 | return false; | |
7279 | ||
7280 | case IF_THEN_ELSE: | |
7281 | *total = 0; | |
7282 | return false; | |
7283 | ||
7284 | case COMPARE: | |
7285 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
7286 | * total = 0; | |
7287 | else | |
7288 | *total = COSTS_N_INSNS (1); | |
7289 | return false; | |
7290 | ||
7291 | case ABS: | |
e0dc3601 PB |
7292 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT |
7293 | && (mode == SFmode || !TARGET_VFP_SINGLE)) | |
21b5653c RE |
7294 | *total = COSTS_N_INSNS (1); |
7295 | else | |
7296 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
7297 | return false; | |
7298 | ||
7299 | case SIGN_EXTEND: | |
21b5653c | 7300 | case ZERO_EXTEND: |
e4c6a07a | 7301 | return arm_rtx_costs_1 (x, outer_code, total, 0); |
21b5653c | 7302 | |
f676971a EC |
7303 | case CONST_INT: |
7304 | if (const_ok_for_arm (INTVAL (x))) | |
6e782a29 KH |
7305 | /* A multiplication by a constant requires another instruction |
7306 | to load the constant to a register. */ | |
7307 | *total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT) | |
7308 | ? 1 : 0); | |
21b5653c RE |
7309 | else if (const_ok_for_arm (~INTVAL (x))) |
7310 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
7311 | else if (const_ok_for_arm (-INTVAL (x))) | |
7312 | { | |
7313 | if (outer_code == COMPARE || outer_code == PLUS | |
7314 | || outer_code == MINUS) | |
7315 | *total = 0; | |
7316 | else | |
7317 | *total = COSTS_N_INSNS (1); | |
7318 | } | |
7319 | else | |
7320 | *total = COSTS_N_INSNS (2); | |
7321 | return true; | |
f676971a EC |
7322 | |
7323 | case CONST: | |
7324 | case LABEL_REF: | |
7325 | case SYMBOL_REF: | |
21b5653c RE |
7326 | *total = COSTS_N_INSNS (2); |
7327 | return true; | |
f676971a | 7328 | |
21b5653c RE |
7329 | case CONST_DOUBLE: |
7330 | *total = COSTS_N_INSNS (4); | |
7331 | return true; | |
7332 | ||
571191af PB |
7333 | case HIGH: |
7334 | case LO_SUM: | |
7335 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | |
7336 | cost of these slightly. */ | |
7337 | *total = COSTS_N_INSNS (1) + 1; | |
7338 | return true; | |
7339 | ||
21b5653c RE |
7340 | default: |
7341 | if (mode != VOIDmode) | |
7342 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
7343 | else | |
7344 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
7345 | return false; | |
7346 | } | |
7347 | } | |
7348 | ||
f40751dd JH |
7349 | /* RTX costs when optimizing for size. */ |
7350 | static bool | |
d5a0a47b RE |
7351 | arm_rtx_costs (rtx x, int code, int outer_code, int *total, |
7352 | bool speed) | |
f40751dd JH |
7353 | { |
7354 | if (!speed) | |
bbbbb16a ILT |
7355 | return arm_size_rtx_costs (x, (enum rtx_code) code, |
7356 | (enum rtx_code) outer_code, total); | |
f40751dd | 7357 | else |
1b78f575 RE |
7358 | return current_tune->rtx_costs (x, (enum rtx_code) code, |
7359 | (enum rtx_code) outer_code, | |
7360 | total, speed); | |
f40751dd JH |
7361 | } |
7362 | ||
5b3e6663 PB |
7363 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not |
7364 | supported on any "slowmul" cores, so it can be ignored. */ | |
9b66ebb1 | 7365 | |
3c50106f | 7366 | static bool |
d5a0a47b RE |
7367 | arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7368 | int *total, bool speed) | |
3c50106f | 7369 | { |
9b66ebb1 PB |
7370 | enum machine_mode mode = GET_MODE (x); |
7371 | ||
7372 | if (TARGET_THUMB) | |
7373 | { | |
5b3e6663 | 7374 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7375 | return true; |
7376 | } | |
f676971a | 7377 | |
9b66ebb1 PB |
7378 | switch (code) |
7379 | { | |
7380 | case MULT: | |
7381 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
7382 | || mode == DImode) | |
7383 | { | |
d5a0a47b RE |
7384 | *total = COSTS_N_INSNS (20); |
7385 | return false; | |
9b66ebb1 PB |
7386 | } |
7387 | ||
7388 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7389 | { | |
7390 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
7391 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
7392 | int cost, const_ok = const_ok_for_arm (i); | |
7393 | int j, booth_unit_size; | |
7394 | ||
f676971a | 7395 | /* Tune as appropriate. */ |
9b66ebb1 PB |
7396 | cost = const_ok ? 4 : 8; |
7397 | booth_unit_size = 2; | |
7398 | for (j = 0; i && j < 32; j += booth_unit_size) | |
7399 | { | |
7400 | i >>= booth_unit_size; | |
d5a0a47b | 7401 | cost++; |
9b66ebb1 PB |
7402 | } |
7403 | ||
d5a0a47b RE |
7404 | *total = COSTS_N_INSNS (cost); |
7405 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
9b66ebb1 PB |
7406 | return true; |
7407 | } | |
7408 | ||
d5a0a47b RE |
7409 | *total = COSTS_N_INSNS (20); |
7410 | return false; | |
f676971a | 7411 | |
9b66ebb1 | 7412 | default: |
d5a0a47b | 7413 | return arm_rtx_costs_1 (x, outer_code, total, speed);; |
9b66ebb1 | 7414 | } |
3c50106f RH |
7415 | } |
7416 | ||
9b66ebb1 PB |
7417 | |
7418 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
7419 | ||
7420 | static bool | |
d5a0a47b RE |
7421 | arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7422 | int *total, bool speed) | |
9b66ebb1 PB |
7423 | { |
7424 | enum machine_mode mode = GET_MODE (x); | |
7425 | ||
5b3e6663 | 7426 | if (TARGET_THUMB1) |
9b66ebb1 | 7427 | { |
5b3e6663 | 7428 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7429 | return true; |
7430 | } | |
f676971a | 7431 | |
5b3e6663 | 7432 | /* ??? should thumb2 use different costs? */ |
9b66ebb1 PB |
7433 | switch (code) |
7434 | { | |
7435 | case MULT: | |
7436 | /* There is no point basing this on the tuning, since it is always the | |
7437 | fast variant if it exists at all. */ | |
7438 | if (mode == DImode | |
7439 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7440 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7441 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7442 | { | |
d5a0a47b RE |
7443 | *total = COSTS_N_INSNS(2); |
7444 | return false; | |
9b66ebb1 | 7445 | } |
f676971a | 7446 | |
9b66ebb1 | 7447 | |
d5a0a47b | 7448 | if (mode == DImode) |
9b66ebb1 | 7449 | { |
d5a0a47b RE |
7450 | *total = COSTS_N_INSNS (5); |
7451 | return false; | |
9b66ebb1 PB |
7452 | } |
7453 | ||
7454 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7455 | { | |
7456 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
7457 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
7458 | int cost, const_ok = const_ok_for_arm (i); | |
7459 | int j, booth_unit_size; | |
7460 | ||
f676971a | 7461 | /* Tune as appropriate. */ |
9b66ebb1 PB |
7462 | cost = const_ok ? 4 : 8; |
7463 | booth_unit_size = 8; | |
7464 | for (j = 0; i && j < 32; j += booth_unit_size) | |
7465 | { | |
7466 | i >>= booth_unit_size; | |
d5a0a47b | 7467 | cost++; |
9b66ebb1 PB |
7468 | } |
7469 | ||
d5a0a47b RE |
7470 | *total = COSTS_N_INSNS(cost); |
7471 | return false; | |
9b66ebb1 PB |
7472 | } |
7473 | ||
d5a0a47b RE |
7474 | if (mode == SImode) |
7475 | { | |
7476 | *total = COSTS_N_INSNS (4); | |
7477 | return false; | |
7478 | } | |
7479 | ||
7480 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
7481 | { | |
e0dc3601 PB |
7482 | if (TARGET_HARD_FLOAT |
7483 | && (mode == SFmode | |
7484 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
7485 | { |
7486 | *total = COSTS_N_INSNS (1); | |
7487 | return false; | |
7488 | } | |
7489 | } | |
7490 | ||
7491 | /* Requires a lib call */ | |
7492 | *total = COSTS_N_INSNS (20); | |
7493 | return false; | |
f676971a | 7494 | |
9b66ebb1 | 7495 | default: |
d5a0a47b | 7496 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7497 | } |
7498 | } | |
7499 | ||
7500 | ||
5b3e6663 PB |
7501 | /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores, |
7502 | so it can be ignored. */ | |
9b66ebb1 PB |
7503 | |
7504 | static bool | |
1b78f575 RE |
7505 | arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7506 | int *total, bool speed) | |
9b66ebb1 PB |
7507 | { |
7508 | enum machine_mode mode = GET_MODE (x); | |
7509 | ||
7510 | if (TARGET_THUMB) | |
7511 | { | |
5b3e6663 | 7512 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7513 | return true; |
7514 | } | |
f676971a | 7515 | |
9b66ebb1 PB |
7516 | switch (code) |
7517 | { | |
d5a0a47b RE |
7518 | case COMPARE: |
7519 | if (GET_CODE (XEXP (x, 0)) != MULT) | |
7520 | return arm_rtx_costs_1 (x, outer_code, total, speed); | |
7521 | ||
7522 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
7523 | will stall until the multiplication is complete. */ | |
7524 | *total = COSTS_N_INSNS (3); | |
7525 | return false; | |
7526 | ||
9b66ebb1 PB |
7527 | case MULT: |
7528 | /* There is no point basing this on the tuning, since it is always the | |
7529 | fast variant if it exists at all. */ | |
7530 | if (mode == DImode | |
7531 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7532 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7533 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7534 | { | |
d5a0a47b RE |
7535 | *total = COSTS_N_INSNS (2); |
7536 | return false; | |
9b66ebb1 | 7537 | } |
f676971a | 7538 | |
9b66ebb1 | 7539 | |
d5a0a47b | 7540 | if (mode == DImode) |
9b66ebb1 | 7541 | { |
d5a0a47b RE |
7542 | *total = COSTS_N_INSNS (5); |
7543 | return false; | |
9b66ebb1 PB |
7544 | } |
7545 | ||
7546 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7547 | { | |
d5a0a47b RE |
7548 | /* If operand 1 is a constant we can more accurately |
7549 | calculate the cost of the multiply. The multiplier can | |
7550 | retire 15 bits on the first cycle and a further 12 on the | |
7551 | second. We do, of course, have to load the constant into | |
7552 | a register first. */ | |
7553 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
7554 | /* There's a general overhead of one cycle. */ | |
7555 | int cost = 1; | |
9b66ebb1 PB |
7556 | unsigned HOST_WIDE_INT masked_const; |
7557 | ||
d5a0a47b RE |
7558 | if (i & 0x80000000) |
7559 | i = ~i; | |
7560 | ||
7561 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; | |
7562 | ||
9b66ebb1 | 7563 | masked_const = i & 0xffff8000; |
d5a0a47b | 7564 | if (masked_const != 0) |
9b66ebb1 | 7565 | { |
d5a0a47b | 7566 | cost++; |
9b66ebb1 | 7567 | masked_const = i & 0xf8000000; |
d5a0a47b RE |
7568 | if (masked_const != 0) |
7569 | cost++; | |
9b66ebb1 | 7570 | } |
d5a0a47b RE |
7571 | *total = COSTS_N_INSNS (cost); |
7572 | return false; | |
9b66ebb1 PB |
7573 | } |
7574 | ||
d5a0a47b RE |
7575 | if (mode == SImode) |
7576 | { | |
7577 | *total = COSTS_N_INSNS (3); | |
7578 | return false; | |
7579 | } | |
f676971a | 7580 | |
d5a0a47b RE |
7581 | /* Requires a lib call */ |
7582 | *total = COSTS_N_INSNS (20); | |
7583 | return false; | |
06d5588c | 7584 | |
9b66ebb1 | 7585 | default: |
d5a0a47b | 7586 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7587 | } |
7588 | } | |
7589 | ||
7590 | ||
7591 | /* RTX costs for 9e (and later) cores. */ | |
7592 | ||
7593 | static bool | |
d5a0a47b RE |
7594 | arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
7595 | int *total, bool speed) | |
9b66ebb1 PB |
7596 | { |
7597 | enum machine_mode mode = GET_MODE (x); | |
f676971a | 7598 | |
5b3e6663 | 7599 | if (TARGET_THUMB1) |
9b66ebb1 PB |
7600 | { |
7601 | switch (code) | |
7602 | { | |
7603 | case MULT: | |
7604 | *total = COSTS_N_INSNS (3); | |
7605 | return true; | |
f676971a | 7606 | |
9b66ebb1 | 7607 | default: |
5b3e6663 | 7608 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
7609 | return true; |
7610 | } | |
7611 | } | |
f676971a | 7612 | |
9b66ebb1 PB |
7613 | switch (code) |
7614 | { | |
7615 | case MULT: | |
7616 | /* There is no point basing this on the tuning, since it is always the | |
7617 | fast variant if it exists at all. */ | |
7618 | if (mode == DImode | |
7619 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
7620 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
7621 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
7622 | { | |
d5a0a47b RE |
7623 | *total = COSTS_N_INSNS (2); |
7624 | return false; | |
9b66ebb1 | 7625 | } |
f676971a | 7626 | |
9b66ebb1 | 7627 | |
9b66ebb1 PB |
7628 | if (mode == DImode) |
7629 | { | |
d5a0a47b RE |
7630 | *total = COSTS_N_INSNS (5); |
7631 | return false; | |
9b66ebb1 | 7632 | } |
d5a0a47b RE |
7633 | |
7634 | if (mode == SImode) | |
9b66ebb1 | 7635 | { |
d5a0a47b RE |
7636 | *total = COSTS_N_INSNS (2); |
7637 | return false; | |
9b66ebb1 PB |
7638 | } |
7639 | ||
d5a0a47b RE |
7640 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
7641 | { | |
e0dc3601 PB |
7642 | if (TARGET_HARD_FLOAT |
7643 | && (mode == SFmode | |
7644 | || (mode == DFmode && !TARGET_VFP_SINGLE))) | |
d5a0a47b RE |
7645 | { |
7646 | *total = COSTS_N_INSNS (1); | |
7647 | return false; | |
7648 | } | |
7649 | } | |
9b66ebb1 | 7650 | |
d5a0a47b RE |
7651 | *total = COSTS_N_INSNS (20); |
7652 | return false; | |
f676971a | 7653 | |
9b66ebb1 | 7654 | default: |
d5a0a47b | 7655 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
7656 | } |
7657 | } | |
dcefdf67 RH |
7658 | /* All address computations that can be done are free, but rtx cost returns |
7659 | the same for practically all of them. So we weight the different types | |
7660 | of address here in the order (most pref first): | |
d6b4baa4 | 7661 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
7662 | static inline int |
7663 | arm_arm_address_cost (rtx x) | |
7664 | { | |
7665 | enum rtx_code c = GET_CODE (x); | |
7666 | ||
7667 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
7668 | return 0; | |
7669 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
7670 | return 10; | |
7671 | ||
17eb4921 | 7672 | if (c == PLUS) |
d2b6eb76 | 7673 | { |
17eb4921 | 7674 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
d2b6eb76 ZW |
7675 | return 2; |
7676 | ||
ec8e098d | 7677 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
7678 | return 3; |
7679 | ||
7680 | return 4; | |
7681 | } | |
7682 | ||
7683 | return 6; | |
7684 | } | |
7685 | ||
7686 | static inline int | |
7687 | arm_thumb_address_cost (rtx x) | |
7688 | { | |
7689 | enum rtx_code c = GET_CODE (x); | |
7690 | ||
7691 | if (c == REG) | |
7692 | return 1; | |
7693 | if (c == PLUS | |
7694 | && GET_CODE (XEXP (x, 0)) == REG | |
7695 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
7696 | return 1; | |
7697 | ||
7698 | return 2; | |
7699 | } | |
7700 | ||
dcefdf67 | 7701 | static int |
f40751dd | 7702 | arm_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
dcefdf67 | 7703 | { |
5b3e6663 | 7704 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 | 7705 | } |
906668bb | 7706 | |
b0c13111 RR |
7707 | /* Adjust cost hook for XScale. */ |
7708 | static bool | |
7709 | xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | |
7710 | { | |
d19fb8e3 NC |
7711 | /* Some true dependencies can have a higher cost depending |
7712 | on precisely how certain input operands are used. */ | |
b0c13111 | 7713 | if (REG_NOTE_KIND(link) == 0 |
eda833e3 BE |
7714 | && recog_memoized (insn) >= 0 |
7715 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
7716 | { |
7717 | int shift_opnum = get_attr_shift (insn); | |
7718 | enum attr_type attr_type = get_attr_type (dep); | |
7719 | ||
7720 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
7721 | operand for INSN. If we have a shifted input operand and the | |
7722 | instruction we depend on is another ALU instruction, then we may | |
7723 | have to account for an additional stall. */ | |
9b66ebb1 PB |
7724 | if (shift_opnum != 0 |
7725 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
7726 | { |
7727 | rtx shifted_operand; | |
7728 | int opno; | |
f676971a | 7729 | |
d19fb8e3 NC |
7730 | /* Get the shifted operand. */ |
7731 | extract_insn (insn); | |
7732 | shifted_operand = recog_data.operand[shift_opnum]; | |
7733 | ||
7734 | /* Iterate over all the operands in DEP. If we write an operand | |
7735 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
7736 | cost of this dependency. */ | |
7737 | extract_insn (dep); | |
7738 | preprocess_constraints (); | |
7739 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
7740 | { | |
7741 | /* We can ignore strict inputs. */ | |
7742 | if (recog_data.operand_type[opno] == OP_IN) | |
7743 | continue; | |
7744 | ||
7745 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
7746 | shifted_operand)) | |
b0c13111 RR |
7747 | { |
7748 | *cost = 2; | |
7749 | return false; | |
7750 | } | |
d19fb8e3 NC |
7751 | } |
7752 | } | |
7753 | } | |
b0c13111 RR |
7754 | return true; |
7755 | } | |
7756 | ||
7757 | /* Adjust cost hook for Cortex A9. */ | |
7758 | static bool | |
7759 | cortex_a9_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) | |
7760 | { | |
7761 | switch (REG_NOTE_KIND (link)) | |
7762 | { | |
7763 | case REG_DEP_ANTI: | |
7764 | *cost = 0; | |
7765 | return false; | |
7766 | ||
7767 | case REG_DEP_TRUE: | |
7768 | case REG_DEP_OUTPUT: | |
7769 | if (recog_memoized (insn) >= 0 | |
7770 | && recog_memoized (dep) >= 0) | |
7771 | { | |
7772 | if (GET_CODE (PATTERN (insn)) == SET) | |
7773 | { | |
7774 | if (GET_MODE_CLASS | |
7775 | (GET_MODE (SET_DEST (PATTERN (insn)))) == MODE_FLOAT | |
7776 | || GET_MODE_CLASS | |
7777 | (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
7778 | { | |
7779 | enum attr_type attr_type_insn = get_attr_type (insn); | |
7780 | enum attr_type attr_type_dep = get_attr_type (dep); | |
7781 | ||
7782 | /* By default all dependencies of the form | |
7783 | s0 = s0 <op> s1 | |
7784 | s0 = s0 <op> s2 | |
7785 | have an extra latency of 1 cycle because | |
7786 | of the input and output dependency in this | |
7787 | case. However this gets modeled as an true | |
7788 | dependency and hence all these checks. */ | |
7789 | if (REG_P (SET_DEST (PATTERN (insn))) | |
7790 | && REG_P (SET_DEST (PATTERN (dep))) | |
7791 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (insn)), | |
7792 | SET_DEST (PATTERN (dep)))) | |
7793 | { | |
7794 | /* FMACS is a special case where the dependant | |
7795 | instruction can be issued 3 cycles before | |
7796 | the normal latency in case of an output | |
7797 | dependency. */ | |
7798 | if ((attr_type_insn == TYPE_FMACS | |
7799 | || attr_type_insn == TYPE_FMACD) | |
7800 | && (attr_type_dep == TYPE_FMACS | |
7801 | || attr_type_dep == TYPE_FMACD)) | |
7802 | { | |
7803 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
7804 | *cost = insn_default_latency (dep) - 3; | |
7805 | else | |
7806 | *cost = insn_default_latency (dep); | |
7807 | return false; | |
7808 | } | |
7809 | else | |
7810 | { | |
7811 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
7812 | *cost = insn_default_latency (dep) + 1; | |
7813 | else | |
7814 | *cost = insn_default_latency (dep); | |
7815 | } | |
7816 | return false; | |
7817 | } | |
7818 | } | |
7819 | } | |
7820 | } | |
7821 | break; | |
7822 | ||
7823 | default: | |
7824 | gcc_unreachable (); | |
7825 | } | |
7826 | ||
7827 | return true; | |
7828 | } | |
7829 | ||
7830 | /* This function implements the target macro TARGET_SCHED_ADJUST_COST. | |
7831 | It corrects the value of COST based on the relationship between | |
7832 | INSN and DEP through the dependence LINK. It returns the new | |
7833 | value. There is a per-core adjust_cost hook to adjust scheduler costs | |
7834 | and the per-core hook can choose to completely override the generic | |
7835 | adjust_cost function. Only put bits of code into arm_adjust_cost that | |
7836 | are common across all cores. */ | |
7837 | static int | |
7838 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) | |
7839 | { | |
7840 | rtx i_pat, d_pat; | |
7841 | ||
7842 | /* When generating Thumb-1 code, we want to place flag-setting operations | |
7843 | close to a conditional branch which depends on them, so that we can | |
7844 | omit the comparison. */ | |
7845 | if (TARGET_THUMB1 | |
7846 | && REG_NOTE_KIND (link) == 0 | |
7847 | && recog_memoized (insn) == CODE_FOR_cbranchsi4_insn | |
7848 | && recog_memoized (dep) >= 0 | |
7849 | && get_attr_conds (dep) == CONDS_SET) | |
7850 | return 0; | |
7851 | ||
7852 | if (current_tune->sched_adjust_cost != NULL) | |
7853 | { | |
7854 | if (!current_tune->sched_adjust_cost (insn, link, dep, &cost)) | |
7855 | return cost; | |
7856 | } | |
d19fb8e3 | 7857 | |
6354dc9b | 7858 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
7859 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
7860 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
7861 | return 0; |
7862 | ||
d5b7b3ae RE |
7863 | /* Call insns don't incur a stall, even if they follow a load. */ |
7864 | if (REG_NOTE_KIND (link) == 0 | |
7865 | && GET_CODE (insn) == CALL_INSN) | |
7866 | return 1; | |
7867 | ||
32de079a RE |
7868 | if ((i_pat = single_set (insn)) != NULL |
7869 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
7870 | && (d_pat = single_set (dep)) != NULL | |
7871 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
7872 | { | |
48f6efae | 7873 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
7874 | /* This is a load after a store, there is no conflict if the load reads |
7875 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 7876 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 7877 | hack. */ |
f676971a | 7878 | |
b0c13111 RR |
7879 | if ((GET_CODE (src_mem) == SYMBOL_REF |
7880 | && CONSTANT_POOL_ADDRESS_P (src_mem)) | |
48f6efae NC |
7881 | || reg_mentioned_p (stack_pointer_rtx, src_mem) |
7882 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
7883 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 7884 | return 1; |
32de079a RE |
7885 | } |
7886 | ||
7887 | return cost; | |
7888 | } | |
7889 | ||
9b66ebb1 | 7890 | static int fp_consts_inited = 0; |
ff9940b0 | 7891 | |
9b66ebb1 PB |
7892 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
7893 | static const char * const strings_fp[8] = | |
62b10bbc | 7894 | { |
2b835d68 RE |
7895 | "0", "1", "2", "3", |
7896 | "4", "5", "0.5", "10" | |
7897 | }; | |
ff9940b0 | 7898 | |
9b66ebb1 | 7899 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
7900 | |
7901 | static void | |
9b66ebb1 | 7902 | init_fp_table (void) |
ff9940b0 RE |
7903 | { |
7904 | int i; | |
7905 | REAL_VALUE_TYPE r; | |
7906 | ||
9b66ebb1 PB |
7907 | if (TARGET_VFP) |
7908 | fp_consts_inited = 1; | |
7909 | else | |
7910 | fp_consts_inited = 8; | |
7911 | ||
7912 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 7913 | { |
9b66ebb1 PB |
7914 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
7915 | values_fp[i] = r; | |
ff9940b0 | 7916 | } |
ff9940b0 RE |
7917 | } |
7918 | ||
9b66ebb1 | 7919 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 7920 | int |
9b66ebb1 | 7921 | arm_const_double_rtx (rtx x) |
cce8749e | 7922 | { |
ff9940b0 RE |
7923 | REAL_VALUE_TYPE r; |
7924 | int i; | |
f676971a | 7925 | |
9b66ebb1 PB |
7926 | if (!fp_consts_inited) |
7927 | init_fp_table (); | |
f676971a | 7928 | |
ff9940b0 RE |
7929 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
7930 | if (REAL_VALUE_MINUS_ZERO (r)) | |
7931 | return 0; | |
f3bb6135 | 7932 | |
9b66ebb1 PB |
7933 | for (i = 0; i < fp_consts_inited; i++) |
7934 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 7935 | return 1; |
f3bb6135 | 7936 | |
ff9940b0 | 7937 | return 0; |
f3bb6135 | 7938 | } |
ff9940b0 | 7939 | |
3b684012 | 7940 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 7941 | int |
e32bac5b | 7942 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
7943 | { |
7944 | REAL_VALUE_TYPE r; | |
7945 | int i; | |
f676971a | 7946 | |
9b66ebb1 PB |
7947 | if (!fp_consts_inited) |
7948 | init_fp_table (); | |
f676971a | 7949 | |
ff9940b0 | 7950 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
d49b6e1e | 7951 | r = real_value_negate (&r); |
ff9940b0 RE |
7952 | if (REAL_VALUE_MINUS_ZERO (r)) |
7953 | return 0; | |
f3bb6135 | 7954 | |
ff9940b0 | 7955 | for (i = 0; i < 8; i++) |
9b66ebb1 | 7956 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 7957 | return 1; |
f3bb6135 | 7958 | |
ff9940b0 | 7959 | return 0; |
f3bb6135 | 7960 | } |
f1adb0a9 JB |
7961 | |
7962 | ||
7963 | /* VFPv3 has a fairly wide range of representable immediates, formed from | |
7964 | "quarter-precision" floating-point values. These can be evaluated using this | |
7965 | formula (with ^ for exponentiation): | |
7966 | ||
7967 | -1^s * n * 2^-r | |
7968 | ||
7969 | Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that | |
7970 | 16 <= n <= 31 and 0 <= r <= 7. | |
7971 | ||
7972 | These values are mapped onto an 8-bit integer ABCDEFGH s.t. | |
7973 | ||
7974 | - A (most-significant) is the sign bit. | |
7975 | - BCD are the exponent (encoded as r XOR 3). | |
7976 | - EFGH are the mantissa (encoded as n - 16). | |
7977 | */ | |
7978 | ||
7979 | /* Return an integer index for a VFPv3 immediate operand X suitable for the | |
7980 | fconst[sd] instruction, or -1 if X isn't suitable. */ | |
7981 | static int | |
7982 | vfp3_const_double_index (rtx x) | |
7983 | { | |
7984 | REAL_VALUE_TYPE r, m; | |
7985 | int sign, exponent; | |
7986 | unsigned HOST_WIDE_INT mantissa, mant_hi; | |
7987 | unsigned HOST_WIDE_INT mask; | |
8e39e9af | 7988 | HOST_WIDE_INT m1, m2; |
f1adb0a9 JB |
7989 | int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; |
7990 | ||
7991 | if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) | |
7992 | return -1; | |
7993 | ||
7994 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
7995 | ||
7996 | /* We can't represent these things, so detect them first. */ | |
7997 | if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r)) | |
7998 | return -1; | |
7999 | ||
8000 | /* Extract sign, exponent and mantissa. */ | |
8001 | sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0; | |
d49b6e1e | 8002 | r = real_value_abs (&r); |
f1adb0a9 JB |
8003 | exponent = REAL_EXP (&r); |
8004 | /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the | |
8005 | highest (sign) bit, with a fixed binary point at bit point_pos. | |
8006 | WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1 | |
8007 | bits for the mantissa, this may fail (low bits would be lost). */ | |
8008 | real_ldexp (&m, &r, point_pos - exponent); | |
8e39e9af RE |
8009 | REAL_VALUE_TO_INT (&m1, &m2, m); |
8010 | mantissa = m1; | |
8011 | mant_hi = m2; | |
f1adb0a9 JB |
8012 | |
8013 | /* If there are bits set in the low part of the mantissa, we can't | |
8014 | represent this value. */ | |
8015 | if (mantissa != 0) | |
8016 | return -1; | |
8017 | ||
8018 | /* Now make it so that mantissa contains the most-significant bits, and move | |
8019 | the point_pos to indicate that the least-significant bits have been | |
8020 | discarded. */ | |
8021 | point_pos -= HOST_BITS_PER_WIDE_INT; | |
8022 | mantissa = mant_hi; | |
8023 | ||
8024 | /* We can permit four significant bits of mantissa only, plus a high bit | |
8025 | which is always 1. */ | |
8026 | mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; | |
8027 | if ((mantissa & mask) != 0) | |
8028 | return -1; | |
8029 | ||
8030 | /* Now we know the mantissa is in range, chop off the unneeded bits. */ | |
8031 | mantissa >>= point_pos - 5; | |
8032 | ||
8033 | /* The mantissa may be zero. Disallow that case. (It's possible to load the | |
8034 | floating-point immediate zero with Neon using an integer-zero load, but | |
8035 | that case is handled elsewhere.) */ | |
8036 | if (mantissa == 0) | |
8037 | return -1; | |
8038 | ||
8039 | gcc_assert (mantissa >= 16 && mantissa <= 31); | |
8040 | ||
8041 | /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where | |
6ed3da00 KH |
8042 | normalized significands are in the range [1, 2). (Our mantissa is shifted |
8043 | left 4 places at this point relative to normalized IEEE754 values). GCC | |
f1adb0a9 JB |
8044 | internally uses [0.5, 1) (see real.c), so the exponent returned from |
8045 | REAL_EXP must be altered. */ | |
8046 | exponent = 5 - exponent; | |
8047 | ||
8048 | if (exponent < 0 || exponent > 7) | |
8049 | return -1; | |
8050 | ||
8051 | /* Sign, mantissa and exponent are now in the correct form to plug into the | |
15dc95cb | 8052 | formula described in the comment above. */ |
f1adb0a9 JB |
8053 | return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16); |
8054 | } | |
8055 | ||
8056 | /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */ | |
8057 | int | |
8058 | vfp3_const_double_rtx (rtx x) | |
8059 | { | |
8060 | if (!TARGET_VFP3) | |
8061 | return 0; | |
8062 | ||
8063 | return vfp3_const_double_index (x) != -1; | |
8064 | } | |
8065 | ||
88f77cba JB |
8066 | /* Recognize immediates which can be used in various Neon instructions. Legal |
8067 | immediates are described by the following table (for VMVN variants, the | |
8068 | bitwise inverse of the constant shown is recognized. In either case, VMOV | |
8069 | is output and the correct instruction to use for a given constant is chosen | |
8070 | by the assembler). The constant shown is replicated across all elements of | |
8071 | the destination vector. | |
8072 | ||
8073 | insn elems variant constant (binary) | |
8074 | ---- ----- ------- ----------------- | |
8075 | vmov i32 0 00000000 00000000 00000000 abcdefgh | |
8076 | vmov i32 1 00000000 00000000 abcdefgh 00000000 | |
8077 | vmov i32 2 00000000 abcdefgh 00000000 00000000 | |
8078 | vmov i32 3 abcdefgh 00000000 00000000 00000000 | |
8079 | vmov i16 4 00000000 abcdefgh | |
8080 | vmov i16 5 abcdefgh 00000000 | |
8081 | vmvn i32 6 00000000 00000000 00000000 abcdefgh | |
8082 | vmvn i32 7 00000000 00000000 abcdefgh 00000000 | |
8083 | vmvn i32 8 00000000 abcdefgh 00000000 00000000 | |
8084 | vmvn i32 9 abcdefgh 00000000 00000000 00000000 | |
8085 | vmvn i16 10 00000000 abcdefgh | |
8086 | vmvn i16 11 abcdefgh 00000000 | |
8087 | vmov i32 12 00000000 00000000 abcdefgh 11111111 | |
8088 | vmvn i32 13 00000000 00000000 abcdefgh 11111111 | |
8089 | vmov i32 14 00000000 abcdefgh 11111111 11111111 | |
8090 | vmvn i32 15 00000000 abcdefgh 11111111 11111111 | |
8091 | vmov i8 16 abcdefgh | |
8092 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | |
8093 | eeeeeeee ffffffff gggggggg hhhhhhhh | |
8094 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | |
8095 | ||
8096 | For case 18, B = !b. Representable values are exactly those accepted by | |
8097 | vfp3_const_double_index, but are output as floating-point numbers rather | |
8098 | than indices. | |
8099 | ||
8100 | Variants 0-5 (inclusive) may also be used as immediates for the second | |
8101 | operand of VORR/VBIC instructions. | |
8102 | ||
8103 | The INVERSE argument causes the bitwise inverse of the given operand to be | |
8104 | recognized instead (used for recognizing legal immediates for the VAND/VORN | |
8105 | pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is | |
8106 | *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be | |
8107 | output, rather than the real insns vbic/vorr). | |
8108 | ||
8109 | INVERSE makes no difference to the recognition of float vectors. | |
8110 | ||
8111 | The return value is the variant of immediate as shown in the above table, or | |
8112 | -1 if the given value doesn't match any of the listed patterns. | |
8113 | */ | |
8114 | static int | |
8115 | neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, | |
8116 | rtx *modconst, int *elementwidth) | |
8117 | { | |
8118 | #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ | |
8119 | matches = 1; \ | |
8120 | for (i = 0; i < idx; i += (STRIDE)) \ | |
8121 | if (!(TEST)) \ | |
8122 | matches = 0; \ | |
8123 | if (matches) \ | |
8124 | { \ | |
8125 | immtype = (CLASS); \ | |
8126 | elsize = (ELSIZE); \ | |
8127 | break; \ | |
8128 | } | |
8129 | ||
ff128632 | 8130 | unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); |
88f77cba JB |
8131 | unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
8132 | unsigned char bytes[16]; | |
8133 | int immtype = -1, matches; | |
8134 | unsigned int invmask = inverse ? 0xff : 0; | |
8135 | ||
8136 | /* Vectors of float constants. */ | |
8137 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
8138 | { | |
8139 | rtx el0 = CONST_VECTOR_ELT (op, 0); | |
8140 | REAL_VALUE_TYPE r0; | |
8141 | ||
8142 | if (!vfp3_const_double_rtx (el0)) | |
8143 | return -1; | |
8144 | ||
8145 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | |
8146 | ||
8147 | for (i = 1; i < n_elts; i++) | |
8148 | { | |
8149 | rtx elt = CONST_VECTOR_ELT (op, i); | |
8150 | REAL_VALUE_TYPE re; | |
8151 | ||
8152 | REAL_VALUE_FROM_CONST_DOUBLE (re, elt); | |
8153 | ||
8154 | if (!REAL_VALUES_EQUAL (r0, re)) | |
8155 | return -1; | |
8156 | } | |
8157 | ||
8158 | if (modconst) | |
8159 | *modconst = CONST_VECTOR_ELT (op, 0); | |
8160 | ||
8161 | if (elementwidth) | |
8162 | *elementwidth = 0; | |
8163 | ||
8164 | return 18; | |
8165 | } | |
8166 | ||
8167 | /* Splat vector constant out into a byte vector. */ | |
8168 | for (i = 0; i < n_elts; i++) | |
8169 | { | |
8170 | rtx el = CONST_VECTOR_ELT (op, i); | |
8171 | unsigned HOST_WIDE_INT elpart; | |
8172 | unsigned int part, parts; | |
8173 | ||
8174 | if (GET_CODE (el) == CONST_INT) | |
8175 | { | |
8176 | elpart = INTVAL (el); | |
8177 | parts = 1; | |
8178 | } | |
8179 | else if (GET_CODE (el) == CONST_DOUBLE) | |
8180 | { | |
8181 | elpart = CONST_DOUBLE_LOW (el); | |
8182 | parts = 2; | |
8183 | } | |
8184 | else | |
8185 | gcc_unreachable (); | |
8186 | ||
8187 | for (part = 0; part < parts; part++) | |
8188 | { | |
8189 | unsigned int byte; | |
8190 | for (byte = 0; byte < innersize; byte++) | |
8191 | { | |
8192 | bytes[idx++] = (elpart & 0xff) ^ invmask; | |
8193 | elpart >>= BITS_PER_UNIT; | |
8194 | } | |
8195 | if (GET_CODE (el) == CONST_DOUBLE) | |
8196 | elpart = CONST_DOUBLE_HIGH (el); | |
8197 | } | |
8198 | } | |
8199 | ||
8200 | /* Sanity check. */ | |
8201 | gcc_assert (idx == GET_MODE_SIZE (mode)); | |
8202 | ||
8203 | do | |
8204 | { | |
8205 | CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 | |
8206 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8207 | ||
8208 | CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
8209 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8210 | ||
8211 | CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 | |
8212 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
8213 | ||
8214 | CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 | |
8215 | && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); | |
8216 | ||
8217 | CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); | |
8218 | ||
8219 | CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); | |
8220 | ||
8221 | CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff | |
8222 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8223 | ||
8224 | CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
8225 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8226 | ||
8227 | CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8228 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
8229 | ||
8230 | CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8231 | && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); | |
8232 | ||
8233 | CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); | |
8234 | ||
8235 | CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); | |
8236 | ||
8237 | CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
8238 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
8239 | ||
8240 | CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
8241 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
8242 | ||
8243 | CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
8244 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
8245 | ||
8246 | CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 | |
8247 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
8248 | ||
8249 | CHECK (1, 8, 16, bytes[i] == bytes[0]); | |
8250 | ||
8251 | CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) | |
8252 | && bytes[i] == bytes[(i + 8) % idx]); | |
8253 | } | |
8254 | while (0); | |
8255 | ||
8256 | if (immtype == -1) | |
8257 | return -1; | |
8258 | ||
8259 | if (elementwidth) | |
8260 | *elementwidth = elsize; | |
8261 | ||
8262 | if (modconst) | |
8263 | { | |
8264 | unsigned HOST_WIDE_INT imm = 0; | |
8265 | ||
cea618ac | 8266 | /* Un-invert bytes of recognized vector, if necessary. */ |
88f77cba JB |
8267 | if (invmask != 0) |
8268 | for (i = 0; i < idx; i++) | |
8269 | bytes[i] ^= invmask; | |
8270 | ||
8271 | if (immtype == 17) | |
8272 | { | |
8273 | /* FIXME: Broken on 32-bit H_W_I hosts. */ | |
8274 | gcc_assert (sizeof (HOST_WIDE_INT) == 8); | |
8275 | ||
8276 | for (i = 0; i < 8; i++) | |
8277 | imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) | |
8278 | << (i * BITS_PER_UNIT); | |
8279 | ||
8280 | *modconst = GEN_INT (imm); | |
8281 | } | |
8282 | else | |
8283 | { | |
8284 | unsigned HOST_WIDE_INT imm = 0; | |
8285 | ||
8286 | for (i = 0; i < elsize / BITS_PER_UNIT; i++) | |
8287 | imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); | |
8288 | ||
8289 | *modconst = GEN_INT (imm); | |
8290 | } | |
8291 | } | |
8292 | ||
8293 | return immtype; | |
8294 | #undef CHECK | |
8295 | } | |
8296 | ||
8297 | /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, | |
8298 | VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for | |
8299 | float elements), and a modified constant (whatever should be output for a | |
8300 | VMOV) in *MODCONST. */ | |
8301 | ||
8302 | int | |
8303 | neon_immediate_valid_for_move (rtx op, enum machine_mode mode, | |
8304 | rtx *modconst, int *elementwidth) | |
8305 | { | |
8306 | rtx tmpconst; | |
8307 | int tmpwidth; | |
8308 | int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); | |
8309 | ||
8310 | if (retval == -1) | |
8311 | return 0; | |
8312 | ||
8313 | if (modconst) | |
8314 | *modconst = tmpconst; | |
8315 | ||
8316 | if (elementwidth) | |
8317 | *elementwidth = tmpwidth; | |
8318 | ||
8319 | return 1; | |
8320 | } | |
8321 | ||
8322 | /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If | |
8323 | the immediate is valid, write a constant suitable for using as an operand | |
8324 | to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to | |
8325 | *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ | |
8326 | ||
8327 | int | |
8328 | neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, | |
8329 | rtx *modconst, int *elementwidth) | |
8330 | { | |
8331 | rtx tmpconst; | |
8332 | int tmpwidth; | |
8333 | int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); | |
8334 | ||
8335 | if (retval < 0 || retval > 5) | |
8336 | return 0; | |
8337 | ||
8338 | if (modconst) | |
8339 | *modconst = tmpconst; | |
8340 | ||
8341 | if (elementwidth) | |
8342 | *elementwidth = tmpwidth; | |
8343 | ||
8344 | return 1; | |
8345 | } | |
8346 | ||
8347 | /* Return a string suitable for output of Neon immediate logic operation | |
8348 | MNEM. */ | |
8349 | ||
8350 | char * | |
8351 | neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, | |
8352 | int inverse, int quad) | |
8353 | { | |
8354 | int width, is_valid; | |
8355 | static char templ[40]; | |
8356 | ||
8357 | is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); | |
8358 | ||
8359 | gcc_assert (is_valid != 0); | |
8360 | ||
8361 | if (quad) | |
8362 | sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); | |
8363 | else | |
8364 | sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); | |
8365 | ||
8366 | return templ; | |
8367 | } | |
8368 | ||
8369 | /* Output a sequence of pairwise operations to implement a reduction. | |
8370 | NOTE: We do "too much work" here, because pairwise operations work on two | |
8371 | registers-worth of operands in one go. Unfortunately we can't exploit those | |
8372 | extra calculations to do the full operation in fewer steps, I don't think. | |
8373 | Although all vector elements of the result but the first are ignored, we | |
8374 | actually calculate the same result in each of the elements. An alternative | |
8375 | such as initially loading a vector with zero to use as each of the second | |
8376 | operands would use up an additional register and take an extra instruction, | |
8377 | for no particular gain. */ | |
8378 | ||
8379 | void | |
8380 | neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, | |
8381 | rtx (*reduc) (rtx, rtx, rtx)) | |
8382 | { | |
8383 | enum machine_mode inner = GET_MODE_INNER (mode); | |
8384 | unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); | |
8385 | rtx tmpsum = op1; | |
8386 | ||
8387 | for (i = parts / 2; i >= 1; i /= 2) | |
8388 | { | |
8389 | rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); | |
8390 | emit_insn (reduc (dest, tmpsum, tmpsum)); | |
8391 | tmpsum = dest; | |
8392 | } | |
8393 | } | |
8394 | ||
814a4c3b DJ |
8395 | /* If VALS is a vector constant that can be loaded into a register |
8396 | using VDUP, generate instructions to do so and return an RTX to | |
8397 | assign to the register. Otherwise return NULL_RTX. */ | |
8398 | ||
8399 | static rtx | |
8400 | neon_vdup_constant (rtx vals) | |
8401 | { | |
8402 | enum machine_mode mode = GET_MODE (vals); | |
8403 | enum machine_mode inner_mode = GET_MODE_INNER (mode); | |
8404 | int n_elts = GET_MODE_NUNITS (mode); | |
8405 | bool all_same = true; | |
8406 | rtx x; | |
8407 | int i; | |
8408 | ||
8409 | if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4) | |
8410 | return NULL_RTX; | |
8411 | ||
8412 | for (i = 0; i < n_elts; ++i) | |
8413 | { | |
8414 | x = XVECEXP (vals, 0, i); | |
8415 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
8416 | all_same = false; | |
8417 | } | |
8418 | ||
8419 | if (!all_same) | |
8420 | /* The elements are not all the same. We could handle repeating | |
8421 | patterns of a mode larger than INNER_MODE here (e.g. int8x8_t | |
8422 | {0, C, 0, C, 0, C, 0, C} which can be loaded using | |
8423 | vdup.i16). */ | |
8424 | return NULL_RTX; | |
8425 | ||
8426 | /* We can load this constant by using VDUP and a constant in a | |
8427 | single ARM register. This will be cheaper than a vector | |
8428 | load. */ | |
8429 | ||
8430 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | |
a277dd9b | 8431 | return gen_rtx_VEC_DUPLICATE (mode, x); |
814a4c3b DJ |
8432 | } |
8433 | ||
8434 | /* Generate code to load VALS, which is a PARALLEL containing only | |
8435 | constants (for vec_init) or CONST_VECTOR, efficiently into a | |
8436 | register. Returns an RTX to copy into the register, or NULL_RTX | |
8437 | for a PARALLEL that can not be converted into a CONST_VECTOR. */ | |
8438 | ||
8439 | rtx | |
8440 | neon_make_constant (rtx vals) | |
8441 | { | |
8442 | enum machine_mode mode = GET_MODE (vals); | |
8443 | rtx target; | |
8444 | rtx const_vec = NULL_RTX; | |
8445 | int n_elts = GET_MODE_NUNITS (mode); | |
8446 | int n_const = 0; | |
8447 | int i; | |
8448 | ||
8449 | if (GET_CODE (vals) == CONST_VECTOR) | |
8450 | const_vec = vals; | |
8451 | else if (GET_CODE (vals) == PARALLEL) | |
8452 | { | |
8453 | /* A CONST_VECTOR must contain only CONST_INTs and | |
8454 | CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF). | |
8455 | Only store valid constants in a CONST_VECTOR. */ | |
8456 | for (i = 0; i < n_elts; ++i) | |
8457 | { | |
8458 | rtx x = XVECEXP (vals, 0, i); | |
8459 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) | |
8460 | n_const++; | |
8461 | } | |
8462 | if (n_const == n_elts) | |
8463 | const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)); | |
8464 | } | |
8465 | else | |
8466 | gcc_unreachable (); | |
8467 | ||
8468 | if (const_vec != NULL | |
8469 | && neon_immediate_valid_for_move (const_vec, mode, NULL, NULL)) | |
8470 | /* Load using VMOV. On Cortex-A8 this takes one cycle. */ | |
8471 | return const_vec; | |
8472 | else if ((target = neon_vdup_constant (vals)) != NULL_RTX) | |
8473 | /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON | |
8474 | pipeline cycle; creating the constant takes one or two ARM | |
8475 | pipeline cycles. */ | |
8476 | return target; | |
8477 | else if (const_vec != NULL_RTX) | |
8478 | /* Load from constant pool. On Cortex-A8 this takes two cycles | |
8479 | (for either double or quad vectors). We can not take advantage | |
8480 | of single-cycle VLD1 because we need a PC-relative addressing | |
8481 | mode. */ | |
8482 | return const_vec; | |
8483 | else | |
8484 | /* A PARALLEL containing something not valid inside CONST_VECTOR. | |
8485 | We can not construct an initializer. */ | |
8486 | return NULL_RTX; | |
8487 | } | |
8488 | ||
8489 | /* Initialize vector TARGET to VALS. */ | |
88f77cba JB |
8490 | |
8491 | void | |
8492 | neon_expand_vector_init (rtx target, rtx vals) | |
8493 | { | |
8494 | enum machine_mode mode = GET_MODE (target); | |
814a4c3b DJ |
8495 | enum machine_mode inner_mode = GET_MODE_INNER (mode); |
8496 | int n_elts = GET_MODE_NUNITS (mode); | |
8497 | int n_var = 0, one_var = -1; | |
8498 | bool all_same = true; | |
8499 | rtx x, mem; | |
8500 | int i; | |
88f77cba | 8501 | |
814a4c3b DJ |
8502 | for (i = 0; i < n_elts; ++i) |
8503 | { | |
8504 | x = XVECEXP (vals, 0, i); | |
8505 | if (!CONSTANT_P (x)) | |
8506 | ++n_var, one_var = i; | |
8507 | ||
8508 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
8509 | all_same = false; | |
8510 | } | |
88f77cba | 8511 | |
814a4c3b DJ |
8512 | if (n_var == 0) |
8513 | { | |
8514 | rtx constant = neon_make_constant (vals); | |
8515 | if (constant != NULL_RTX) | |
8516 | { | |
8517 | emit_move_insn (target, constant); | |
8518 | return; | |
8519 | } | |
8520 | } | |
8521 | ||
8522 | /* Splat a single non-constant element if we can. */ | |
8523 | if (all_same && GET_MODE_SIZE (inner_mode) <= 4) | |
8524 | { | |
8525 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0)); | |
8526 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
a277dd9b | 8527 | gen_rtx_VEC_DUPLICATE (mode, x))); |
814a4c3b DJ |
8528 | return; |
8529 | } | |
8530 | ||
8531 | /* One field is non-constant. Load constant then overwrite varying | |
8532 | field. This is more efficient than using the stack. */ | |
8533 | if (n_var == 1) | |
8534 | { | |
8535 | rtx copy = copy_rtx (vals); | |
a277dd9b | 8536 | rtx index = GEN_INT (one_var); |
814a4c3b DJ |
8537 | |
8538 | /* Load constant part of vector, substitute neighboring value for | |
8539 | varying element. */ | |
8540 | XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts); | |
8541 | neon_expand_vector_init (target, copy); | |
8542 | ||
8543 | /* Insert variable. */ | |
8544 | x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var)); | |
a277dd9b SL |
8545 | switch (mode) |
8546 | { | |
8547 | case V8QImode: | |
8548 | emit_insn (gen_neon_vset_lanev8qi (target, x, target, index)); | |
8549 | break; | |
8550 | case V16QImode: | |
8551 | emit_insn (gen_neon_vset_lanev16qi (target, x, target, index)); | |
8552 | break; | |
8553 | case V4HImode: | |
8554 | emit_insn (gen_neon_vset_lanev4hi (target, x, target, index)); | |
8555 | break; | |
8556 | case V8HImode: | |
8557 | emit_insn (gen_neon_vset_lanev8hi (target, x, target, index)); | |
8558 | break; | |
8559 | case V2SImode: | |
8560 | emit_insn (gen_neon_vset_lanev2si (target, x, target, index)); | |
8561 | break; | |
8562 | case V4SImode: | |
8563 | emit_insn (gen_neon_vset_lanev4si (target, x, target, index)); | |
8564 | break; | |
8565 | case V2SFmode: | |
8566 | emit_insn (gen_neon_vset_lanev2sf (target, x, target, index)); | |
8567 | break; | |
8568 | case V4SFmode: | |
8569 | emit_insn (gen_neon_vset_lanev4sf (target, x, target, index)); | |
8570 | break; | |
8571 | case V2DImode: | |
8572 | emit_insn (gen_neon_vset_lanev2di (target, x, target, index)); | |
8573 | break; | |
8574 | default: | |
8575 | gcc_unreachable (); | |
8576 | } | |
814a4c3b DJ |
8577 | return; |
8578 | } | |
8579 | ||
8580 | /* Construct the vector in memory one field at a time | |
8581 | and load the whole vector. */ | |
88f77cba JB |
8582 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); |
8583 | for (i = 0; i < n_elts; i++) | |
814a4c3b DJ |
8584 | emit_move_insn (adjust_address_nv (mem, inner_mode, |
8585 | i * GET_MODE_SIZE (inner_mode)), | |
8586 | XVECEXP (vals, 0, i)); | |
88f77cba JB |
8587 | emit_move_insn (target, mem); |
8588 | } | |
8589 | ||
b617fc71 JB |
8590 | /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise |
8591 | ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so | |
8592 | reported source locations are bogus. */ | |
8593 | ||
8594 | static void | |
8595 | bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, | |
8596 | const char *err) | |
8597 | { | |
8598 | HOST_WIDE_INT lane; | |
8599 | ||
8600 | gcc_assert (GET_CODE (operand) == CONST_INT); | |
8601 | ||
8602 | lane = INTVAL (operand); | |
8603 | ||
8604 | if (lane < low || lane >= high) | |
8605 | error (err); | |
8606 | } | |
8607 | ||
8608 | /* Bounds-check lanes. */ | |
8609 | ||
8610 | void | |
8611 | neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
8612 | { | |
8613 | bounds_check (operand, low, high, "lane out of range"); | |
8614 | } | |
8615 | ||
8616 | /* Bounds-check constants. */ | |
8617 | ||
8618 | void | |
8619 | neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
8620 | { | |
8621 | bounds_check (operand, low, high, "constant out of range"); | |
8622 | } | |
8623 | ||
8624 | HOST_WIDE_INT | |
8625 | neon_element_bits (enum machine_mode mode) | |
8626 | { | |
8627 | if (mode == DImode) | |
8628 | return GET_MODE_BITSIZE (mode); | |
8629 | else | |
8630 | return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); | |
8631 | } | |
8632 | ||
cce8749e CH |
8633 | \f |
8634 | /* Predicates for `match_operand' and `match_operator'. */ | |
8635 | ||
9b6b54e2 | 8636 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 8637 | int |
e32bac5b | 8638 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
8639 | { |
8640 | /* Reject eliminable registers. */ | |
8641 | if (! (reload_in_progress || reload_completed) | |
8642 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8643 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8644 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8645 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8646 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8647 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8648 | return 0; | |
8649 | ||
8650 | if (GET_CODE (op) == MEM) | |
8651 | { | |
8652 | rtx ind; | |
8653 | ||
8654 | ind = XEXP (op, 0); | |
8655 | ||
8656 | /* Match: (mem (reg)). */ | |
8657 | if (GET_CODE (ind) == REG) | |
8658 | return 1; | |
8659 | ||
8660 | /* Match: | |
8661 | (mem (plus (reg) | |
8662 | (const))). */ | |
8663 | if (GET_CODE (ind) == PLUS | |
8664 | && GET_CODE (XEXP (ind, 0)) == REG | |
8665 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
8666 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
8667 | return 1; | |
8668 | } | |
8669 | ||
8670 | return 0; | |
8671 | } | |
8672 | ||
f26b8ec9 | 8673 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
5b3e6663 PB |
8674 | WB is true if full writeback address modes are allowed and is false |
8675 | if limited writeback address modes (POST_INC and PRE_DEC) are | |
8676 | allowed. */ | |
9b66ebb1 PB |
8677 | |
8678 | int | |
fdd695fd | 8679 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 8680 | { |
fdd695fd | 8681 | rtx ind; |
9b66ebb1 | 8682 | |
fdd695fd | 8683 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
8684 | if (! (reload_in_progress || reload_completed) |
8685 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8686 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8687 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8688 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8689 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8690 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8691 | return FALSE; | |
8692 | ||
59b9a953 | 8693 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
8694 | if (GET_CODE (op) != MEM) |
8695 | return FALSE; | |
9b66ebb1 | 8696 | |
fdd695fd | 8697 | ind = XEXP (op, 0); |
9b66ebb1 | 8698 | |
fdd695fd PB |
8699 | if (reload_completed |
8700 | && (GET_CODE (ind) == LABEL_REF | |
8701 | || (GET_CODE (ind) == CONST | |
8702 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
8703 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
8704 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
8705 | return TRUE; | |
9b66ebb1 | 8706 | |
fdd695fd PB |
8707 | /* Match: (mem (reg)). */ |
8708 | if (GET_CODE (ind) == REG) | |
8709 | return arm_address_register_rtx_p (ind, 0); | |
8710 | ||
5b3e6663 PB |
8711 | /* Autoincremment addressing modes. POST_INC and PRE_DEC are |
8712 | acceptable in any case (subject to verification by | |
8713 | arm_address_register_rtx_p). We need WB to be true to accept | |
8714 | PRE_INC and POST_DEC. */ | |
8715 | if (GET_CODE (ind) == POST_INC | |
8716 | || GET_CODE (ind) == PRE_DEC | |
8717 | || (wb | |
8718 | && (GET_CODE (ind) == PRE_INC | |
8719 | || GET_CODE (ind) == POST_DEC))) | |
fdd695fd PB |
8720 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
8721 | ||
8722 | if (wb | |
8723 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
8724 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
8725 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
8726 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
8727 | ind = XEXP (ind, 1); | |
8728 | ||
8729 | /* Match: | |
8730 | (plus (reg) | |
8731 | (const)). */ | |
8732 | if (GET_CODE (ind) == PLUS | |
8733 | && GET_CODE (XEXP (ind, 0)) == REG | |
8734 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
8735 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
8736 | && INTVAL (XEXP (ind, 1)) > -1024 | |
8737 | && INTVAL (XEXP (ind, 1)) < 1024 | |
8738 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
8739 | return TRUE; | |
9b66ebb1 PB |
8740 | |
8741 | return FALSE; | |
8742 | } | |
8743 | ||
88f77cba | 8744 | /* Return TRUE if OP is a memory operand which we can load or store a vector |
dc34db56 PB |
8745 | to/from. TYPE is one of the following values: |
8746 | 0 - Vector load/stor (vldr) | |
8747 | 1 - Core registers (ldm) | |
8748 | 2 - Element/structure loads (vld1) | |
8749 | */ | |
88f77cba | 8750 | int |
dc34db56 | 8751 | neon_vector_mem_operand (rtx op, int type) |
88f77cba JB |
8752 | { |
8753 | rtx ind; | |
8754 | ||
8755 | /* Reject eliminable registers. */ | |
8756 | if (! (reload_in_progress || reload_completed) | |
8757 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8758 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8759 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8760 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8761 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8762 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8763 | return FALSE; | |
8764 | ||
8765 | /* Constants are converted into offsets from labels. */ | |
8766 | if (GET_CODE (op) != MEM) | |
8767 | return FALSE; | |
8768 | ||
8769 | ind = XEXP (op, 0); | |
8770 | ||
8771 | if (reload_completed | |
8772 | && (GET_CODE (ind) == LABEL_REF | |
8773 | || (GET_CODE (ind) == CONST | |
8774 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
8775 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
8776 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
8777 | return TRUE; | |
8778 | ||
8779 | /* Match: (mem (reg)). */ | |
8780 | if (GET_CODE (ind) == REG) | |
8781 | return arm_address_register_rtx_p (ind, 0); | |
8782 | ||
8783 | /* Allow post-increment with Neon registers. */ | |
dc34db56 | 8784 | if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) |
88f77cba JB |
8785 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
8786 | ||
dc34db56 | 8787 | /* FIXME: vld1 allows register post-modify. */ |
88f77cba JB |
8788 | |
8789 | /* Match: | |
8790 | (plus (reg) | |
8791 | (const)). */ | |
dc34db56 | 8792 | if (type == 0 |
88f77cba JB |
8793 | && GET_CODE (ind) == PLUS |
8794 | && GET_CODE (XEXP (ind, 0)) == REG | |
8795 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
8796 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
8797 | && INTVAL (XEXP (ind, 1)) > -1024 | |
8798 | && INTVAL (XEXP (ind, 1)) < 1016 | |
8799 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
8800 | return TRUE; | |
8801 | ||
8802 | return FALSE; | |
8803 | } | |
8804 | ||
8805 | /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct | |
8806 | type. */ | |
8807 | int | |
8808 | neon_struct_mem_operand (rtx op) | |
8809 | { | |
8810 | rtx ind; | |
8811 | ||
8812 | /* Reject eliminable registers. */ | |
8813 | if (! (reload_in_progress || reload_completed) | |
8814 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
8815 | || reg_mentioned_p (arg_pointer_rtx, op) | |
8816 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
8817 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
8818 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
8819 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
8820 | return FALSE; | |
8821 | ||
8822 | /* Constants are converted into offsets from labels. */ | |
8823 | if (GET_CODE (op) != MEM) | |
8824 | return FALSE; | |
8825 | ||
8826 | ind = XEXP (op, 0); | |
8827 | ||
8828 | if (reload_completed | |
8829 | && (GET_CODE (ind) == LABEL_REF | |
8830 | || (GET_CODE (ind) == CONST | |
8831 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
8832 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
8833 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
8834 | return TRUE; | |
8835 | ||
8836 | /* Match: (mem (reg)). */ | |
8837 | if (GET_CODE (ind) == REG) | |
8838 | return arm_address_register_rtx_p (ind, 0); | |
8839 | ||
8840 | return FALSE; | |
8841 | } | |
8842 | ||
6555b6bd RE |
8843 | /* Return true if X is a register that will be eliminated later on. */ |
8844 | int | |
8845 | arm_eliminable_register (rtx x) | |
8846 | { | |
8847 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
8848 | || REGNO (x) == ARG_POINTER_REGNUM | |
8849 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
8850 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
8851 | } | |
9b66ebb1 | 8852 | |
9b66ebb1 | 8853 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
fe2d934b | 8854 | coprocessor registers. Otherwise return NO_REGS. */ |
9b66ebb1 PB |
8855 | |
8856 | enum reg_class | |
fe2d934b | 8857 | coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) |
9b66ebb1 | 8858 | { |
0fd8c3ad SL |
8859 | if (mode == HFmode) |
8860 | { | |
e0dc3601 PB |
8861 | if (!TARGET_NEON_FP16) |
8862 | return GENERAL_REGS; | |
0fd8c3ad SL |
8863 | if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2)) |
8864 | return NO_REGS; | |
8865 | return GENERAL_REGS; | |
8866 | } | |
8867 | ||
88f77cba JB |
8868 | if (TARGET_NEON |
8869 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
8870 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
dc34db56 | 8871 | && neon_vector_mem_operand (x, 0)) |
88f77cba JB |
8872 | return NO_REGS; |
8873 | ||
fe2d934b | 8874 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) |
9b66ebb1 PB |
8875 | return NO_REGS; |
8876 | ||
8877 | return GENERAL_REGS; | |
8878 | } | |
8879 | ||
866af8a9 JB |
8880 | /* Values which must be returned in the most-significant end of the return |
8881 | register. */ | |
8882 | ||
8883 | static bool | |
586de218 | 8884 | arm_return_in_msb (const_tree valtype) |
866af8a9 JB |
8885 | { |
8886 | return (TARGET_AAPCS_BASED | |
8887 | && BYTES_BIG_ENDIAN | |
8888 | && (AGGREGATE_TYPE_P (valtype) | |
8889 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
8890 | } | |
9b66ebb1 | 8891 | |
f0375c66 NC |
8892 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
8893 | Use by the Cirrus Maverick code which has to workaround | |
8894 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 8895 | static bool |
e32bac5b | 8896 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
8897 | { |
8898 | rtx body, lhs, rhs;; | |
8899 | ||
f0375c66 NC |
8900 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
8901 | return false; | |
9b6b54e2 NC |
8902 | |
8903 | body = PATTERN (insn); | |
8904 | ||
8905 | if (GET_CODE (body) != SET) | |
f0375c66 | 8906 | return false; |
9b6b54e2 NC |
8907 | |
8908 | lhs = XEXP (body, 0); | |
8909 | rhs = XEXP (body, 1); | |
8910 | ||
f0375c66 NC |
8911 | lhs = REG_OR_SUBREG_RTX (lhs); |
8912 | ||
8913 | /* If the destination is not a general purpose | |
8914 | register we do not have to worry. */ | |
8915 | if (GET_CODE (lhs) != REG | |
8916 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
8917 | return false; | |
8918 | ||
8919 | /* As well as loads from memory we also have to react | |
8920 | to loads of invalid constants which will be turned | |
8921 | into loads from the minipool. */ | |
8922 | return (GET_CODE (rhs) == MEM | |
8923 | || GET_CODE (rhs) == SYMBOL_REF | |
8924 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
8925 | } |
8926 | ||
f0375c66 | 8927 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 8928 | static bool |
e32bac5b | 8929 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
8930 | { |
8931 | enum attr_cirrus attr; | |
8932 | ||
e6d29d15 | 8933 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
8934 | if (!insn |
8935 | || GET_CODE (insn) != INSN | |
8936 | || GET_CODE (PATTERN (insn)) == USE | |
8937 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
8938 | return 0; | |
8939 | ||
8940 | attr = get_attr_cirrus (insn); | |
8941 | ||
f0375c66 | 8942 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
8943 | } |
8944 | ||
8945 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 8946 | static void |
e32bac5b | 8947 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
8948 | { |
8949 | enum attr_cirrus attr; | |
8950 | rtx body = PATTERN (first); | |
8951 | rtx t; | |
8952 | int nops; | |
8953 | ||
8954 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
8955 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
8956 | { | |
8957 | nops = 0; | |
8958 | t = next_nonnote_insn (first); | |
8959 | ||
f0375c66 | 8960 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
8961 | ++ nops; |
8962 | ||
f0375c66 | 8963 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
8964 | ++ nops; |
8965 | ||
8966 | while (nops --) | |
8967 | emit_insn_after (gen_nop (), first); | |
8968 | ||
8969 | return; | |
8970 | } | |
8971 | ||
8972 | /* (float (blah)) is in parallel with a clobber. */ | |
8973 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
8974 | body = XVECEXP (body, 0, 0); | |
8975 | ||
8976 | if (GET_CODE (body) == SET) | |
8977 | { | |
8978 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
8979 | ||
8980 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
8981 | be followed by a non Cirrus insn. */ | |
8982 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
8983 | { | |
f0375c66 | 8984 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
8985 | emit_insn_after (gen_nop (), first); |
8986 | ||
8987 | return; | |
8988 | } | |
f0375c66 | 8989 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
8990 | { |
8991 | unsigned int arm_regno; | |
8992 | ||
8993 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
8994 | ldr/cfmv64hr combination where the Rd field is the same | |
8995 | in both instructions must be split with a non Cirrus | |
8996 | insn. Example: | |
8997 | ||
8998 | ldr r0, blah | |
8999 | nop | |
9000 | cfmvsr mvf0, r0. */ | |
9001 | ||
9002 | /* Get Arm register number for ldr insn. */ | |
9003 | if (GET_CODE (lhs) == REG) | |
9004 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 9005 | else |
e6d29d15 NS |
9006 | { |
9007 | gcc_assert (GET_CODE (rhs) == REG); | |
9008 | arm_regno = REGNO (rhs); | |
9009 | } | |
9b6b54e2 NC |
9010 | |
9011 | /* Next insn. */ | |
9012 | first = next_nonnote_insn (first); | |
9013 | ||
f0375c66 | 9014 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
9015 | return; |
9016 | ||
9017 | body = PATTERN (first); | |
9018 | ||
9019 | /* (float (blah)) is in parallel with a clobber. */ | |
9020 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
9021 | body = XVECEXP (body, 0, 0); | |
9022 | ||
9023 | if (GET_CODE (body) == FLOAT) | |
9024 | body = XEXP (body, 0); | |
9025 | ||
9026 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
9027 | && GET_CODE (XEXP (body, 1)) == REG | |
9028 | && arm_regno == REGNO (XEXP (body, 1))) | |
9029 | emit_insn_after (gen_nop (), first); | |
9030 | ||
9031 | return; | |
9032 | } | |
9033 | } | |
9034 | ||
e6d29d15 | 9035 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
9036 | if (!first |
9037 | || GET_CODE (first) != INSN | |
9038 | || GET_CODE (PATTERN (first)) == USE | |
9039 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
9040 | return; | |
9041 | ||
9042 | attr = get_attr_cirrus (first); | |
9043 | ||
9044 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
9045 | must be followed by a non-coprocessor instruction. */ | |
9046 | if (attr == CIRRUS_COMPARE) | |
9047 | { | |
9048 | nops = 0; | |
9049 | ||
9050 | t = next_nonnote_insn (first); | |
9051 | ||
f0375c66 | 9052 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
9053 | ++ nops; |
9054 | ||
f0375c66 | 9055 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
9056 | ++ nops; |
9057 | ||
9058 | while (nops --) | |
9059 | emit_insn_after (gen_nop (), first); | |
9060 | ||
9061 | return; | |
9062 | } | |
9063 | } | |
9064 | ||
2b835d68 RE |
9065 | /* Return TRUE if X references a SYMBOL_REF. */ |
9066 | int | |
e32bac5b | 9067 | symbol_mentioned_p (rtx x) |
2b835d68 | 9068 | { |
1d6e90ac NC |
9069 | const char * fmt; |
9070 | int i; | |
2b835d68 RE |
9071 | |
9072 | if (GET_CODE (x) == SYMBOL_REF) | |
9073 | return 1; | |
9074 | ||
d3585b76 DJ |
9075 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
9076 | are constant offsets, not symbols. */ | |
9077 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
9078 | return 0; | |
9079 | ||
2b835d68 | 9080 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 9081 | |
2b835d68 RE |
9082 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
9083 | { | |
9084 | if (fmt[i] == 'E') | |
9085 | { | |
1d6e90ac | 9086 | int j; |
2b835d68 RE |
9087 | |
9088 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9089 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
9090 | return 1; | |
9091 | } | |
9092 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
9093 | return 1; | |
9094 | } | |
9095 | ||
9096 | return 0; | |
9097 | } | |
9098 | ||
9099 | /* Return TRUE if X references a LABEL_REF. */ | |
9100 | int | |
e32bac5b | 9101 | label_mentioned_p (rtx x) |
2b835d68 | 9102 | { |
1d6e90ac NC |
9103 | const char * fmt; |
9104 | int i; | |
2b835d68 RE |
9105 | |
9106 | if (GET_CODE (x) == LABEL_REF) | |
9107 | return 1; | |
9108 | ||
d3585b76 DJ |
9109 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
9110 | instruction, but they are constant offsets, not symbols. */ | |
9111 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
9112 | return 0; | |
9113 | ||
2b835d68 RE |
9114 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
9115 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
9116 | { | |
9117 | if (fmt[i] == 'E') | |
9118 | { | |
1d6e90ac | 9119 | int j; |
2b835d68 RE |
9120 | |
9121 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
9122 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
9123 | return 1; | |
9124 | } | |
9125 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
9126 | return 1; | |
9127 | } | |
9128 | ||
9129 | return 0; | |
9130 | } | |
9131 | ||
d3585b76 DJ |
9132 | int |
9133 | tls_mentioned_p (rtx x) | |
9134 | { | |
9135 | switch (GET_CODE (x)) | |
9136 | { | |
9137 | case CONST: | |
9138 | return tls_mentioned_p (XEXP (x, 0)); | |
9139 | ||
9140 | case UNSPEC: | |
9141 | if (XINT (x, 1) == UNSPEC_TLS) | |
9142 | return 1; | |
9143 | ||
9144 | default: | |
9145 | return 0; | |
9146 | } | |
9147 | } | |
9148 | ||
2e5505a4 RE |
9149 | /* Must not copy any rtx that uses a pc-relative address. */ |
9150 | ||
9151 | static int | |
9152 | arm_note_pic_base (rtx *x, void *date ATTRIBUTE_UNUSED) | |
9153 | { | |
9154 | if (GET_CODE (*x) == UNSPEC | |
9155 | && XINT (*x, 1) == UNSPEC_PIC_BASE) | |
9156 | return 1; | |
9157 | return 0; | |
9158 | } | |
d3585b76 DJ |
9159 | |
9160 | static bool | |
9161 | arm_cannot_copy_insn_p (rtx insn) | |
9162 | { | |
2e5505a4 | 9163 | return for_each_rtx (&PATTERN (insn), arm_note_pic_base, NULL); |
d3585b76 DJ |
9164 | } |
9165 | ||
ff9940b0 | 9166 | enum rtx_code |
e32bac5b | 9167 | minmax_code (rtx x) |
ff9940b0 RE |
9168 | { |
9169 | enum rtx_code code = GET_CODE (x); | |
9170 | ||
e6d29d15 NS |
9171 | switch (code) |
9172 | { | |
9173 | case SMAX: | |
9174 | return GE; | |
9175 | case SMIN: | |
9176 | return LE; | |
9177 | case UMIN: | |
9178 | return LEU; | |
9179 | case UMAX: | |
9180 | return GEU; | |
9181 | default: | |
9182 | gcc_unreachable (); | |
9183 | } | |
ff9940b0 RE |
9184 | } |
9185 | ||
6354dc9b | 9186 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 9187 | int |
e32bac5b | 9188 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 9189 | { |
15b5c4c1 RE |
9190 | /* We don't guarantee to preserve the order of these memory refs. */ |
9191 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
9192 | return 0; | |
9193 | ||
ff9940b0 RE |
9194 | if ((GET_CODE (XEXP (a, 0)) == REG |
9195 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
9196 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
9197 | && (GET_CODE (XEXP (b, 0)) == REG | |
9198 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
9199 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
9200 | { | |
6555b6bd RE |
9201 | HOST_WIDE_INT val0 = 0, val1 = 0; |
9202 | rtx reg0, reg1; | |
9203 | int val_diff; | |
f676971a | 9204 | |
ff9940b0 RE |
9205 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
9206 | { | |
6555b6bd | 9207 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
9208 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
9209 | } | |
9210 | else | |
6555b6bd | 9211 | reg0 = XEXP (a, 0); |
1d6e90ac | 9212 | |
ff9940b0 RE |
9213 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
9214 | { | |
6555b6bd | 9215 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
9216 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
9217 | } | |
9218 | else | |
6555b6bd | 9219 | reg1 = XEXP (b, 0); |
1d6e90ac | 9220 | |
e32bac5b RE |
9221 | /* Don't accept any offset that will require multiple |
9222 | instructions to handle, since this would cause the | |
9223 | arith_adjacentmem pattern to output an overlong sequence. */ | |
bbbbb16a | 9224 | if (!const_ok_for_op (val0, PLUS) || !const_ok_for_op (val1, PLUS)) |
c75a3ddc | 9225 | return 0; |
f676971a | 9226 | |
6555b6bd RE |
9227 | /* Don't allow an eliminable register: register elimination can make |
9228 | the offset too large. */ | |
9229 | if (arm_eliminable_register (reg0)) | |
9230 | return 0; | |
9231 | ||
9232 | val_diff = val1 - val0; | |
15b5c4c1 RE |
9233 | |
9234 | if (arm_ld_sched) | |
9235 | { | |
9236 | /* If the target has load delay slots, then there's no benefit | |
9237 | to using an ldm instruction unless the offset is zero and | |
9238 | we are optimizing for size. */ | |
9239 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
9240 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
9241 | && (val_diff == 4 || val_diff == -4)); | |
9242 | } | |
9243 | ||
6555b6bd RE |
9244 | return ((REGNO (reg0) == REGNO (reg1)) |
9245 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 9246 | } |
6555b6bd | 9247 | |
ff9940b0 RE |
9248 | return 0; |
9249 | } | |
9250 | ||
93b338c3 BS |
9251 | /* Return true iff it would be profitable to turn a sequence of NOPS loads |
9252 | or stores (depending on IS_STORE) into a load-multiple or store-multiple | |
9253 | instruction. ADD_OFFSET is nonzero if the base address register needs | |
9254 | to be modified with an add instruction before we can use it. */ | |
9255 | ||
9256 | static bool | |
9257 | multiple_operation_profitable_p (bool is_store ATTRIBUTE_UNUSED, | |
9258 | int nops, HOST_WIDE_INT add_offset) | |
9259 | { | |
9260 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm | |
9261 | if the offset isn't small enough. The reason 2 ldrs are faster | |
9262 | is because these ARMs are able to do more than one cache access | |
9263 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
9264 | whilst the ARM8 has a double bandwidth cache. This means that | |
9265 | these cores can do both an instruction fetch and a data fetch in | |
9266 | a single cycle, so the trick of calculating the address into a | |
9267 | scratch register (one of the result regs) and then doing a load | |
9268 | multiple actually becomes slower (and no smaller in code size). | |
9269 | That is the transformation | |
9270 | ||
9271 | ldr rd1, [rbase + offset] | |
9272 | ldr rd2, [rbase + offset + 4] | |
9273 | ||
9274 | to | |
9275 | ||
9276 | add rd1, rbase, offset | |
9277 | ldmia rd1, {rd1, rd2} | |
9278 | ||
9279 | produces worse code -- '3 cycles + any stalls on rd2' instead of | |
9280 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
9281 | access per cycle, the first sequence could never complete in less | |
9282 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
9283 | would make better use of sequential accesses if not hitting the | |
9284 | cache. | |
9285 | ||
9286 | We cheat here and test 'arm_ld_sched' which we currently know to | |
9287 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
9288 | changes, then the test below needs to be reworked. */ | |
9289 | if (nops == 2 && arm_ld_sched && add_offset != 0) | |
9290 | return false; | |
9291 | ||
9292 | return true; | |
9293 | } | |
9294 | ||
9295 | /* Subroutine of load_multiple_sequence and store_multiple_sequence. | |
9296 | Given an array of UNSORTED_OFFSETS, of which there are NOPS, compute | |
9297 | an array ORDER which describes the sequence to use when accessing the | |
9298 | offsets that produces an ascending order. In this sequence, each | |
9299 | offset must be larger by exactly 4 than the previous one. ORDER[0] | |
9300 | must have been filled in with the lowest offset by the caller. | |
9301 | If UNSORTED_REGS is nonnull, it is an array of register numbers that | |
9302 | we use to verify that ORDER produces an ascending order of registers. | |
9303 | Return true if it was possible to construct such an order, false if | |
9304 | not. */ | |
9305 | ||
9306 | static bool | |
9307 | compute_offset_order (int nops, HOST_WIDE_INT *unsorted_offsets, int *order, | |
9308 | int *unsorted_regs) | |
9309 | { | |
9310 | int i; | |
9311 | for (i = 1; i < nops; i++) | |
9312 | { | |
9313 | int j; | |
9314 | ||
9315 | order[i] = order[i - 1]; | |
9316 | for (j = 0; j < nops; j++) | |
9317 | if (unsorted_offsets[j] == unsorted_offsets[order[i - 1]] + 4) | |
9318 | { | |
9319 | /* We must find exactly one offset that is higher than the | |
9320 | previous one by 4. */ | |
9321 | if (order[i] != order[i - 1]) | |
9322 | return false; | |
9323 | order[i] = j; | |
9324 | } | |
9325 | if (order[i] == order[i - 1]) | |
9326 | return false; | |
9327 | /* The register numbers must be ascending. */ | |
9328 | if (unsorted_regs != NULL | |
9329 | && unsorted_regs[order[i]] <= unsorted_regs[order[i - 1]]) | |
9330 | return false; | |
9331 | } | |
9332 | return true; | |
9333 | } | |
9334 | ||
37119410 BS |
9335 | /* Used to determine in a peephole whether a sequence of load |
9336 | instructions can be changed into a load-multiple instruction. | |
9337 | NOPS is the number of separate load instructions we are examining. The | |
9338 | first NOPS entries in OPERANDS are the destination registers, the | |
9339 | next NOPS entries are memory operands. If this function is | |
9340 | successful, *BASE is set to the common base register of the memory | |
9341 | accesses; *LOAD_OFFSET is set to the first memory location's offset | |
9342 | from that base register. | |
9343 | REGS is an array filled in with the destination register numbers. | |
9344 | SAVED_ORDER (if nonnull), is an array filled in with an order that maps | |
9345 | insn numbers to to an ascending order of stores. If CHECK_REGS is true, | |
9346 | the sequence of registers in REGS matches the loads from ascending memory | |
9347 | locations, and the function verifies that the register numbers are | |
9348 | themselves ascending. If CHECK_REGS is false, the register numbers | |
9349 | are stored in the order they are found in the operands. */ | |
9350 | static int | |
9351 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order, | |
9352 | int *base, HOST_WIDE_INT *load_offset, bool check_regs) | |
84ed5e79 | 9353 | { |
93b338c3 BS |
9354 | int unsorted_regs[MAX_LDM_STM_OPS]; |
9355 | HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; | |
9356 | int order[MAX_LDM_STM_OPS]; | |
37119410 | 9357 | rtx base_reg_rtx = NULL; |
ad076f4e | 9358 | int base_reg = -1; |
93b338c3 | 9359 | int i, ldm_case; |
84ed5e79 | 9360 | |
93b338c3 BS |
9361 | /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be |
9362 | easily extended if required. */ | |
9363 | gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | |
84ed5e79 | 9364 | |
93b338c3 | 9365 | memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); |
f0b4bdd5 | 9366 | |
84ed5e79 | 9367 | /* Loop over the operands and check that the memory references are |
112cdef5 | 9368 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
9369 | the same time, extract the target register, and the memory |
9370 | offsets. */ | |
9371 | for (i = 0; i < nops; i++) | |
9372 | { | |
9373 | rtx reg; | |
9374 | rtx offset; | |
9375 | ||
56636818 JL |
9376 | /* Convert a subreg of a mem into the mem itself. */ |
9377 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 9378 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 9379 | |
e6d29d15 | 9380 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
9381 | |
9382 | /* Don't reorder volatile memory references; it doesn't seem worth | |
9383 | looking for the case where the order is ok anyway. */ | |
9384 | if (MEM_VOLATILE_P (operands[nops + i])) | |
9385 | return 0; | |
9386 | ||
9387 | offset = const0_rtx; | |
9388 | ||
9389 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
9390 | || (GET_CODE (reg) == SUBREG | |
9391 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9392 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
9393 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
9394 | == REG) | |
9395 | || (GET_CODE (reg) == SUBREG | |
9396 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9397 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
9398 | == CONST_INT))) | |
9399 | { | |
9400 | if (i == 0) | |
84ed5e79 | 9401 | { |
37119410 BS |
9402 | base_reg = REGNO (reg); |
9403 | base_reg_rtx = reg; | |
9404 | if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | |
84ed5e79 | 9405 | return 0; |
84ed5e79 | 9406 | } |
37119410 BS |
9407 | else if (base_reg != (int) REGNO (reg)) |
9408 | /* Not addressed from the same base register. */ | |
9409 | return 0; | |
9410 | ||
93b338c3 BS |
9411 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG |
9412 | ? REGNO (operands[i]) | |
9413 | : REGNO (SUBREG_REG (operands[i]))); | |
84ed5e79 RE |
9414 | |
9415 | /* If it isn't an integer register, or if it overwrites the | |
9416 | base register but isn't the last insn in the list, then | |
9417 | we can't do this. */ | |
37119410 BS |
9418 | if (unsorted_regs[i] < 0 |
9419 | || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | |
9420 | || unsorted_regs[i] > 14 | |
84ed5e79 RE |
9421 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) |
9422 | return 0; | |
9423 | ||
9424 | unsorted_offsets[i] = INTVAL (offset); | |
93b338c3 BS |
9425 | if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) |
9426 | order[0] = i; | |
84ed5e79 RE |
9427 | } |
9428 | else | |
9429 | /* Not a suitable memory address. */ | |
9430 | return 0; | |
9431 | } | |
9432 | ||
9433 | /* All the useful information has now been extracted from the | |
9434 | operands into unsorted_regs and unsorted_offsets; additionally, | |
93b338c3 BS |
9435 | order[0] has been set to the lowest offset in the list. Sort |
9436 | the offsets into order, verifying that they are adjacent, and | |
9437 | check that the register numbers are ascending. */ | |
37119410 BS |
9438 | if (!compute_offset_order (nops, unsorted_offsets, order, |
9439 | check_regs ? unsorted_regs : NULL)) | |
93b338c3 | 9440 | return 0; |
84ed5e79 | 9441 | |
37119410 BS |
9442 | if (saved_order) |
9443 | memcpy (saved_order, order, sizeof order); | |
9444 | ||
84ed5e79 RE |
9445 | if (base) |
9446 | { | |
9447 | *base = base_reg; | |
9448 | ||
9449 | for (i = 0; i < nops; i++) | |
37119410 | 9450 | regs[i] = unsorted_regs[check_regs ? order[i] : i]; |
84ed5e79 RE |
9451 | |
9452 | *load_offset = unsorted_offsets[order[0]]; | |
9453 | } | |
9454 | ||
37119410 BS |
9455 | if (TARGET_THUMB1 |
9456 | && !peep2_reg_dead_p (nops, base_reg_rtx)) | |
9457 | return 0; | |
9458 | ||
84ed5e79 | 9459 | if (unsorted_offsets[order[0]] == 0) |
93b338c3 BS |
9460 | ldm_case = 1; /* ldmia */ |
9461 | else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | |
9462 | ldm_case = 2; /* ldmib */ | |
9463 | else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | |
9464 | ldm_case = 3; /* ldmda */ | |
37119410 | 9465 | else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) |
93b338c3 BS |
9466 | ldm_case = 4; /* ldmdb */ |
9467 | else if (const_ok_for_arm (unsorted_offsets[order[0]]) | |
9468 | || const_ok_for_arm (-unsorted_offsets[order[0]])) | |
9469 | ldm_case = 5; | |
9470 | else | |
9471 | return 0; | |
949d79eb | 9472 | |
93b338c3 BS |
9473 | if (!multiple_operation_profitable_p (false, nops, |
9474 | ldm_case == 5 | |
9475 | ? unsorted_offsets[order[0]] : 0)) | |
b36ba79f RE |
9476 | return 0; |
9477 | ||
93b338c3 | 9478 | return ldm_case; |
84ed5e79 RE |
9479 | } |
9480 | ||
37119410 BS |
9481 | /* Used to determine in a peephole whether a sequence of store instructions can |
9482 | be changed into a store-multiple instruction. | |
9483 | NOPS is the number of separate store instructions we are examining. | |
9484 | NOPS_TOTAL is the total number of instructions recognized by the peephole | |
9485 | pattern. | |
9486 | The first NOPS entries in OPERANDS are the source registers, the next | |
9487 | NOPS entries are memory operands. If this function is successful, *BASE is | |
9488 | set to the common base register of the memory accesses; *LOAD_OFFSET is set | |
9489 | to the first memory location's offset from that base register. REGS is an | |
9490 | array filled in with the source register numbers, REG_RTXS (if nonnull) is | |
9491 | likewise filled with the corresponding rtx's. | |
9492 | SAVED_ORDER (if nonnull), is an array filled in with an order that maps insn | |
9493 | numbers to to an ascending order of stores. | |
9494 | If CHECK_REGS is true, the sequence of registers in *REGS matches the stores | |
9495 | from ascending memory locations, and the function verifies that the register | |
9496 | numbers are themselves ascending. If CHECK_REGS is false, the register | |
9497 | numbers are stored in the order they are found in the operands. */ | |
9498 | static int | |
9499 | store_multiple_sequence (rtx *operands, int nops, int nops_total, | |
9500 | int *regs, rtx *reg_rtxs, int *saved_order, int *base, | |
9501 | HOST_WIDE_INT *load_offset, bool check_regs) | |
84ed5e79 | 9502 | { |
93b338c3 | 9503 | int unsorted_regs[MAX_LDM_STM_OPS]; |
37119410 | 9504 | rtx unsorted_reg_rtxs[MAX_LDM_STM_OPS]; |
93b338c3 BS |
9505 | HOST_WIDE_INT unsorted_offsets[MAX_LDM_STM_OPS]; |
9506 | int order[MAX_LDM_STM_OPS]; | |
ad076f4e | 9507 | int base_reg = -1; |
37119410 | 9508 | rtx base_reg_rtx = NULL; |
93b338c3 | 9509 | int i, stm_case; |
84ed5e79 | 9510 | |
93b338c3 BS |
9511 | /* Can only handle up to MAX_LDM_STM_OPS insns at present, though could be |
9512 | easily extended if required. */ | |
9513 | gcc_assert (nops >= 2 && nops <= MAX_LDM_STM_OPS); | |
84ed5e79 | 9514 | |
93b338c3 | 9515 | memset (order, 0, MAX_LDM_STM_OPS * sizeof (int)); |
f0b4bdd5 | 9516 | |
84ed5e79 | 9517 | /* Loop over the operands and check that the memory references are |
112cdef5 | 9518 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
9519 | the same time, extract the target register, and the memory |
9520 | offsets. */ | |
9521 | for (i = 0; i < nops; i++) | |
9522 | { | |
9523 | rtx reg; | |
9524 | rtx offset; | |
9525 | ||
56636818 JL |
9526 | /* Convert a subreg of a mem into the mem itself. */ |
9527 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 9528 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 9529 | |
e6d29d15 | 9530 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
9531 | |
9532 | /* Don't reorder volatile memory references; it doesn't seem worth | |
9533 | looking for the case where the order is ok anyway. */ | |
9534 | if (MEM_VOLATILE_P (operands[nops + i])) | |
9535 | return 0; | |
9536 | ||
9537 | offset = const0_rtx; | |
9538 | ||
9539 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
9540 | || (GET_CODE (reg) == SUBREG | |
9541 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9542 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
9543 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
9544 | == REG) | |
9545 | || (GET_CODE (reg) == SUBREG | |
9546 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
9547 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
9548 | == CONST_INT))) | |
9549 | { | |
37119410 BS |
9550 | unsorted_reg_rtxs[i] = (GET_CODE (operands[i]) == REG |
9551 | ? operands[i] : SUBREG_REG (operands[i])); | |
9552 | unsorted_regs[i] = REGNO (unsorted_reg_rtxs[i]); | |
9553 | ||
84ed5e79 | 9554 | if (i == 0) |
37119410 BS |
9555 | { |
9556 | base_reg = REGNO (reg); | |
9557 | base_reg_rtx = reg; | |
9558 | if (TARGET_THUMB1 && base_reg > LAST_LO_REGNUM) | |
9559 | return 0; | |
9560 | } | |
93b338c3 BS |
9561 | else if (base_reg != (int) REGNO (reg)) |
9562 | /* Not addressed from the same base register. */ | |
9563 | return 0; | |
84ed5e79 RE |
9564 | |
9565 | /* If it isn't an integer register, then we can't do this. */ | |
37119410 BS |
9566 | if (unsorted_regs[i] < 0 |
9567 | || (TARGET_THUMB1 && unsorted_regs[i] > LAST_LO_REGNUM) | |
9568 | || (TARGET_THUMB2 && unsorted_regs[i] == base_reg) | |
9569 | || (TARGET_THUMB2 && unsorted_regs[i] == SP_REGNUM) | |
9570 | || unsorted_regs[i] > 14) | |
84ed5e79 RE |
9571 | return 0; |
9572 | ||
9573 | unsorted_offsets[i] = INTVAL (offset); | |
93b338c3 BS |
9574 | if (i == 0 || unsorted_offsets[i] < unsorted_offsets[order[0]]) |
9575 | order[0] = i; | |
84ed5e79 RE |
9576 | } |
9577 | else | |
9578 | /* Not a suitable memory address. */ | |
9579 | return 0; | |
9580 | } | |
9581 | ||
9582 | /* All the useful information has now been extracted from the | |
9583 | operands into unsorted_regs and unsorted_offsets; additionally, | |
93b338c3 BS |
9584 | order[0] has been set to the lowest offset in the list. Sort |
9585 | the offsets into order, verifying that they are adjacent, and | |
9586 | check that the register numbers are ascending. */ | |
37119410 BS |
9587 | if (!compute_offset_order (nops, unsorted_offsets, order, |
9588 | check_regs ? unsorted_regs : NULL)) | |
93b338c3 | 9589 | return 0; |
84ed5e79 | 9590 | |
37119410 BS |
9591 | if (saved_order) |
9592 | memcpy (saved_order, order, sizeof order); | |
9593 | ||
84ed5e79 RE |
9594 | if (base) |
9595 | { | |
9596 | *base = base_reg; | |
9597 | ||
9598 | for (i = 0; i < nops; i++) | |
37119410 BS |
9599 | { |
9600 | regs[i] = unsorted_regs[check_regs ? order[i] : i]; | |
9601 | if (reg_rtxs) | |
9602 | reg_rtxs[i] = unsorted_reg_rtxs[check_regs ? order[i] : i]; | |
9603 | } | |
84ed5e79 RE |
9604 | |
9605 | *load_offset = unsorted_offsets[order[0]]; | |
9606 | } | |
9607 | ||
37119410 BS |
9608 | if (TARGET_THUMB1 |
9609 | && !peep2_reg_dead_p (nops_total, base_reg_rtx)) | |
9610 | return 0; | |
9611 | ||
84ed5e79 | 9612 | if (unsorted_offsets[order[0]] == 0) |
93b338c3 BS |
9613 | stm_case = 1; /* stmia */ |
9614 | else if (TARGET_ARM && unsorted_offsets[order[0]] == 4) | |
9615 | stm_case = 2; /* stmib */ | |
9616 | else if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) | |
9617 | stm_case = 3; /* stmda */ | |
37119410 | 9618 | else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4) |
93b338c3 BS |
9619 | stm_case = 4; /* stmdb */ |
9620 | else | |
9621 | return 0; | |
84ed5e79 | 9622 | |
93b338c3 BS |
9623 | if (!multiple_operation_profitable_p (false, nops, 0)) |
9624 | return 0; | |
84ed5e79 | 9625 | |
93b338c3 | 9626 | return stm_case; |
84ed5e79 | 9627 | } |
ff9940b0 | 9628 | \f |
6354dc9b | 9629 | /* Routines for use in generating RTL. */ |
1d6e90ac | 9630 | |
37119410 BS |
9631 | /* Generate a load-multiple instruction. COUNT is the number of loads in |
9632 | the instruction; REGS and MEMS are arrays containing the operands. | |
9633 | BASEREG is the base register to be used in addressing the memory operands. | |
9634 | WBACK_OFFSET is nonzero if the instruction should update the base | |
9635 | register. */ | |
9636 | ||
9637 | static rtx | |
9638 | arm_gen_load_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | |
9639 | HOST_WIDE_INT wback_offset) | |
ff9940b0 RE |
9640 | { |
9641 | int i = 0, j; | |
9642 | rtx result; | |
ff9940b0 | 9643 | |
d19fb8e3 | 9644 | /* XScale has load-store double instructions, but they have stricter |
1e5f1716 | 9645 | alignment requirements than load-store multiple, so we cannot |
d19fb8e3 NC |
9646 | use them. |
9647 | ||
9648 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
9649 | the pipeline until completion. | |
9650 | ||
9651 | NREGS CYCLES | |
9652 | 1 3 | |
9653 | 2 4 | |
9654 | 3 5 | |
9655 | 4 6 | |
9656 | ||
9657 | An ldr instruction takes 1-3 cycles, but does not block the | |
9658 | pipeline. | |
9659 | ||
9660 | NREGS CYCLES | |
9661 | 1 1-3 | |
9662 | 2 2-6 | |
9663 | 3 3-9 | |
9664 | 4 4-12 | |
9665 | ||
9666 | Best case ldr will always win. However, the more ldr instructions | |
9667 | we issue, the less likely we are to be able to schedule them well. | |
9668 | Using ldr instructions also increases code size. | |
9669 | ||
9670 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
9671 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 9672 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
9673 | { |
9674 | rtx seq; | |
f676971a | 9675 | |
d19fb8e3 | 9676 | start_sequence (); |
f676971a | 9677 | |
d19fb8e3 | 9678 | for (i = 0; i < count; i++) |
37119410 | 9679 | emit_move_insn (gen_rtx_REG (SImode, regs[i]), mems[i]); |
d19fb8e3 | 9680 | |
37119410 BS |
9681 | if (wback_offset != 0) |
9682 | emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | |
d19fb8e3 | 9683 | |
2f937369 | 9684 | seq = get_insns (); |
d19fb8e3 | 9685 | end_sequence (); |
f676971a | 9686 | |
d19fb8e3 NC |
9687 | return seq; |
9688 | } | |
9689 | ||
43cffd11 | 9690 | result = gen_rtx_PARALLEL (VOIDmode, |
37119410 BS |
9691 | rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); |
9692 | if (wback_offset != 0) | |
f3bb6135 | 9693 | { |
ff9940b0 | 9694 | XVECEXP (result, 0, 0) |
37119410 BS |
9695 | = gen_rtx_SET (VOIDmode, basereg, |
9696 | plus_constant (basereg, wback_offset)); | |
ff9940b0 RE |
9697 | i = 1; |
9698 | count++; | |
f3bb6135 RE |
9699 | } |
9700 | ||
ff9940b0 | 9701 | for (j = 0; i < count; i++, j++) |
37119410 BS |
9702 | XVECEXP (result, 0, i) |
9703 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regs[j]), mems[j]); | |
50ed9cea | 9704 | |
ff9940b0 RE |
9705 | return result; |
9706 | } | |
9707 | ||
37119410 BS |
9708 | /* Generate a store-multiple instruction. COUNT is the number of stores in |
9709 | the instruction; REGS and MEMS are arrays containing the operands. | |
9710 | BASEREG is the base register to be used in addressing the memory operands. | |
9711 | WBACK_OFFSET is nonzero if the instruction should update the base | |
9712 | register. */ | |
9713 | ||
9714 | static rtx | |
9715 | arm_gen_store_multiple_1 (int count, int *regs, rtx *mems, rtx basereg, | |
9716 | HOST_WIDE_INT wback_offset) | |
ff9940b0 RE |
9717 | { |
9718 | int i = 0, j; | |
9719 | rtx result; | |
ff9940b0 | 9720 | |
37119410 BS |
9721 | if (GET_CODE (basereg) == PLUS) |
9722 | basereg = XEXP (basereg, 0); | |
9723 | ||
9724 | /* See arm_gen_load_multiple_1 for discussion of | |
d19fb8e3 | 9725 | the pros/cons of ldm/stm usage for XScale. */ |
4b3c2e48 | 9726 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
9727 | { |
9728 | rtx seq; | |
f676971a | 9729 | |
d19fb8e3 | 9730 | start_sequence (); |
f676971a | 9731 | |
d19fb8e3 | 9732 | for (i = 0; i < count; i++) |
37119410 | 9733 | emit_move_insn (mems[i], gen_rtx_REG (SImode, regs[i])); |
d19fb8e3 | 9734 | |
37119410 BS |
9735 | if (wback_offset != 0) |
9736 | emit_move_insn (basereg, plus_constant (basereg, wback_offset)); | |
d19fb8e3 | 9737 | |
2f937369 | 9738 | seq = get_insns (); |
d19fb8e3 | 9739 | end_sequence (); |
f676971a | 9740 | |
d19fb8e3 NC |
9741 | return seq; |
9742 | } | |
9743 | ||
43cffd11 | 9744 | result = gen_rtx_PARALLEL (VOIDmode, |
37119410 BS |
9745 | rtvec_alloc (count + (wback_offset != 0 ? 1 : 0))); |
9746 | if (wback_offset != 0) | |
f3bb6135 | 9747 | { |
ff9940b0 | 9748 | XVECEXP (result, 0, 0) |
37119410 BS |
9749 | = gen_rtx_SET (VOIDmode, basereg, |
9750 | plus_constant (basereg, wback_offset)); | |
ff9940b0 RE |
9751 | i = 1; |
9752 | count++; | |
f3bb6135 RE |
9753 | } |
9754 | ||
ff9940b0 | 9755 | for (j = 0; i < count; i++, j++) |
37119410 BS |
9756 | XVECEXP (result, 0, i) |
9757 | = gen_rtx_SET (VOIDmode, mems[j], gen_rtx_REG (SImode, regs[j])); | |
9758 | ||
9759 | return result; | |
9760 | } | |
9761 | ||
9762 | /* Generate either a load-multiple or a store-multiple instruction. This | |
9763 | function can be used in situations where we can start with a single MEM | |
9764 | rtx and adjust its address upwards. | |
9765 | COUNT is the number of operations in the instruction, not counting a | |
9766 | possible update of the base register. REGS is an array containing the | |
9767 | register operands. | |
9768 | BASEREG is the base register to be used in addressing the memory operands, | |
9769 | which are constructed from BASEMEM. | |
9770 | WRITE_BACK specifies whether the generated instruction should include an | |
9771 | update of the base register. | |
9772 | OFFSETP is used to pass an offset to and from this function; this offset | |
9773 | is not used when constructing the address (instead BASEMEM should have an | |
9774 | appropriate offset in its address), it is used only for setting | |
9775 | MEM_OFFSET. It is updated only if WRITE_BACK is true.*/ | |
9776 | ||
9777 | static rtx | |
9778 | arm_gen_multiple_op (bool is_load, int *regs, int count, rtx basereg, | |
9779 | bool write_back, rtx basemem, HOST_WIDE_INT *offsetp) | |
9780 | { | |
9781 | rtx mems[MAX_LDM_STM_OPS]; | |
9782 | HOST_WIDE_INT offset = *offsetp; | |
9783 | int i; | |
9784 | ||
9785 | gcc_assert (count <= MAX_LDM_STM_OPS); | |
9786 | ||
9787 | if (GET_CODE (basereg) == PLUS) | |
9788 | basereg = XEXP (basereg, 0); | |
9789 | ||
9790 | for (i = 0; i < count; i++) | |
f3bb6135 | 9791 | { |
37119410 BS |
9792 | rtx addr = plus_constant (basereg, i * 4); |
9793 | mems[i] = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
9794 | offset += 4; | |
f3bb6135 RE |
9795 | } |
9796 | ||
50ed9cea RH |
9797 | if (write_back) |
9798 | *offsetp = offset; | |
9799 | ||
37119410 BS |
9800 | if (is_load) |
9801 | return arm_gen_load_multiple_1 (count, regs, mems, basereg, | |
9802 | write_back ? 4 * count : 0); | |
9803 | else | |
9804 | return arm_gen_store_multiple_1 (count, regs, mems, basereg, | |
9805 | write_back ? 4 * count : 0); | |
9806 | } | |
9807 | ||
9808 | rtx | |
9809 | arm_gen_load_multiple (int *regs, int count, rtx basereg, int write_back, | |
9810 | rtx basemem, HOST_WIDE_INT *offsetp) | |
9811 | { | |
9812 | return arm_gen_multiple_op (TRUE, regs, count, basereg, write_back, basemem, | |
9813 | offsetp); | |
9814 | } | |
9815 | ||
9816 | rtx | |
9817 | arm_gen_store_multiple (int *regs, int count, rtx basereg, int write_back, | |
9818 | rtx basemem, HOST_WIDE_INT *offsetp) | |
9819 | { | |
9820 | return arm_gen_multiple_op (FALSE, regs, count, basereg, write_back, basemem, | |
9821 | offsetp); | |
9822 | } | |
9823 | ||
9824 | /* Called from a peephole2 expander to turn a sequence of loads into an | |
9825 | LDM instruction. OPERANDS are the operands found by the peephole matcher; | |
9826 | NOPS indicates how many separate loads we are trying to combine. SORT_REGS | |
9827 | is true if we can reorder the registers because they are used commutatively | |
9828 | subsequently. | |
9829 | Returns true iff we could generate a new instruction. */ | |
9830 | ||
9831 | bool | |
9832 | gen_ldm_seq (rtx *operands, int nops, bool sort_regs) | |
9833 | { | |
9834 | int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
9835 | rtx mems[MAX_LDM_STM_OPS]; | |
9836 | int i, j, base_reg; | |
9837 | rtx base_reg_rtx; | |
9838 | HOST_WIDE_INT offset; | |
9839 | int write_back = FALSE; | |
9840 | int ldm_case; | |
9841 | rtx addr; | |
9842 | ||
9843 | ldm_case = load_multiple_sequence (operands, nops, regs, mem_order, | |
9844 | &base_reg, &offset, !sort_regs); | |
9845 | ||
9846 | if (ldm_case == 0) | |
9847 | return false; | |
9848 | ||
9849 | if (sort_regs) | |
9850 | for (i = 0; i < nops - 1; i++) | |
9851 | for (j = i + 1; j < nops; j++) | |
9852 | if (regs[i] > regs[j]) | |
9853 | { | |
9854 | int t = regs[i]; | |
9855 | regs[i] = regs[j]; | |
9856 | regs[j] = t; | |
9857 | } | |
9858 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
9859 | ||
9860 | if (TARGET_THUMB1) | |
9861 | { | |
9862 | gcc_assert (peep2_reg_dead_p (nops, base_reg_rtx)); | |
9863 | gcc_assert (ldm_case == 1 || ldm_case == 5); | |
9864 | write_back = TRUE; | |
9865 | } | |
9866 | ||
9867 | if (ldm_case == 5) | |
9868 | { | |
9869 | rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG (SImode, regs[0]); | |
9870 | emit_insn (gen_addsi3 (newbase, base_reg_rtx, GEN_INT (offset))); | |
9871 | offset = 0; | |
9872 | if (!TARGET_THUMB1) | |
9873 | { | |
9874 | base_reg = regs[0]; | |
9875 | base_reg_rtx = newbase; | |
9876 | } | |
9877 | } | |
9878 | ||
9879 | for (i = 0; i < nops; i++) | |
9880 | { | |
9881 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
9882 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
9883 | SImode, addr, 0); | |
9884 | } | |
9885 | emit_insn (arm_gen_load_multiple_1 (nops, regs, mems, base_reg_rtx, | |
9886 | write_back ? offset + i * 4 : 0)); | |
9887 | return true; | |
9888 | } | |
9889 | ||
9890 | /* Called from a peephole2 expander to turn a sequence of stores into an | |
9891 | STM instruction. OPERANDS are the operands found by the peephole matcher; | |
9892 | NOPS indicates how many separate stores we are trying to combine. | |
9893 | Returns true iff we could generate a new instruction. */ | |
9894 | ||
9895 | bool | |
9896 | gen_stm_seq (rtx *operands, int nops) | |
9897 | { | |
9898 | int i; | |
9899 | int regs[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
9900 | rtx mems[MAX_LDM_STM_OPS]; | |
9901 | int base_reg; | |
9902 | rtx base_reg_rtx; | |
9903 | HOST_WIDE_INT offset; | |
9904 | int write_back = FALSE; | |
9905 | int stm_case; | |
9906 | rtx addr; | |
9907 | bool base_reg_dies; | |
9908 | ||
9909 | stm_case = store_multiple_sequence (operands, nops, nops, regs, NULL, | |
9910 | mem_order, &base_reg, &offset, true); | |
9911 | ||
9912 | if (stm_case == 0) | |
9913 | return false; | |
9914 | ||
9915 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
9916 | ||
9917 | base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx); | |
9918 | if (TARGET_THUMB1) | |
9919 | { | |
9920 | gcc_assert (base_reg_dies); | |
9921 | write_back = TRUE; | |
9922 | } | |
9923 | ||
9924 | if (stm_case == 5) | |
9925 | { | |
9926 | gcc_assert (base_reg_dies); | |
9927 | emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | |
9928 | offset = 0; | |
9929 | } | |
9930 | ||
9931 | addr = plus_constant (base_reg_rtx, offset); | |
9932 | ||
9933 | for (i = 0; i < nops; i++) | |
9934 | { | |
9935 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
9936 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
9937 | SImode, addr, 0); | |
9938 | } | |
9939 | emit_insn (arm_gen_store_multiple_1 (nops, regs, mems, base_reg_rtx, | |
9940 | write_back ? offset + i * 4 : 0)); | |
9941 | return true; | |
9942 | } | |
9943 | ||
9944 | /* Called from a peephole2 expander to turn a sequence of stores that are | |
9945 | preceded by constant loads into an STM instruction. OPERANDS are the | |
9946 | operands found by the peephole matcher; NOPS indicates how many | |
9947 | separate stores we are trying to combine; there are 2 * NOPS | |
9948 | instructions in the peephole. | |
9949 | Returns true iff we could generate a new instruction. */ | |
9950 | ||
9951 | bool | |
9952 | gen_const_stm_seq (rtx *operands, int nops) | |
9953 | { | |
9954 | int regs[MAX_LDM_STM_OPS], sorted_regs[MAX_LDM_STM_OPS]; | |
9955 | int reg_order[MAX_LDM_STM_OPS], mem_order[MAX_LDM_STM_OPS]; | |
9956 | rtx reg_rtxs[MAX_LDM_STM_OPS], orig_reg_rtxs[MAX_LDM_STM_OPS]; | |
9957 | rtx mems[MAX_LDM_STM_OPS]; | |
9958 | int base_reg; | |
9959 | rtx base_reg_rtx; | |
9960 | HOST_WIDE_INT offset; | |
9961 | int write_back = FALSE; | |
9962 | int stm_case; | |
9963 | rtx addr; | |
9964 | bool base_reg_dies; | |
9965 | int i, j; | |
9966 | HARD_REG_SET allocated; | |
9967 | ||
9968 | stm_case = store_multiple_sequence (operands, nops, 2 * nops, regs, reg_rtxs, | |
9969 | mem_order, &base_reg, &offset, false); | |
9970 | ||
9971 | if (stm_case == 0) | |
9972 | return false; | |
9973 | ||
9974 | memcpy (orig_reg_rtxs, reg_rtxs, sizeof orig_reg_rtxs); | |
9975 | ||
9976 | /* If the same register is used more than once, try to find a free | |
9977 | register. */ | |
9978 | CLEAR_HARD_REG_SET (allocated); | |
9979 | for (i = 0; i < nops; i++) | |
9980 | { | |
9981 | for (j = i + 1; j < nops; j++) | |
9982 | if (regs[i] == regs[j]) | |
9983 | { | |
9984 | rtx t = peep2_find_free_register (0, nops * 2, | |
9985 | TARGET_THUMB1 ? "l" : "r", | |
9986 | SImode, &allocated); | |
9987 | if (t == NULL_RTX) | |
9988 | return false; | |
9989 | reg_rtxs[i] = t; | |
9990 | regs[i] = REGNO (t); | |
9991 | } | |
9992 | } | |
9993 | ||
9994 | /* Compute an ordering that maps the register numbers to an ascending | |
9995 | sequence. */ | |
9996 | reg_order[0] = 0; | |
9997 | for (i = 0; i < nops; i++) | |
9998 | if (regs[i] < regs[reg_order[0]]) | |
9999 | reg_order[0] = i; | |
10000 | ||
10001 | for (i = 1; i < nops; i++) | |
10002 | { | |
10003 | int this_order = reg_order[i - 1]; | |
10004 | for (j = 0; j < nops; j++) | |
10005 | if (regs[j] > regs[reg_order[i - 1]] | |
10006 | && (this_order == reg_order[i - 1] | |
10007 | || regs[j] < regs[this_order])) | |
10008 | this_order = j; | |
10009 | reg_order[i] = this_order; | |
10010 | } | |
10011 | ||
10012 | /* Ensure that registers that must be live after the instruction end | |
10013 | up with the correct value. */ | |
10014 | for (i = 0; i < nops; i++) | |
10015 | { | |
10016 | int this_order = reg_order[i]; | |
10017 | if ((this_order != mem_order[i] | |
10018 | || orig_reg_rtxs[this_order] != reg_rtxs[this_order]) | |
10019 | && !peep2_reg_dead_p (nops * 2, orig_reg_rtxs[this_order])) | |
10020 | return false; | |
10021 | } | |
10022 | ||
10023 | /* Load the constants. */ | |
10024 | for (i = 0; i < nops; i++) | |
10025 | { | |
10026 | rtx op = operands[2 * nops + mem_order[i]]; | |
10027 | sorted_regs[i] = regs[reg_order[i]]; | |
10028 | emit_move_insn (reg_rtxs[reg_order[i]], op); | |
10029 | } | |
10030 | ||
10031 | base_reg_rtx = gen_rtx_REG (Pmode, base_reg); | |
10032 | ||
10033 | base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx); | |
10034 | if (TARGET_THUMB1) | |
10035 | { | |
10036 | gcc_assert (base_reg_dies); | |
10037 | write_back = TRUE; | |
10038 | } | |
10039 | ||
10040 | if (stm_case == 5) | |
10041 | { | |
10042 | gcc_assert (base_reg_dies); | |
10043 | emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset))); | |
10044 | offset = 0; | |
10045 | } | |
10046 | ||
10047 | addr = plus_constant (base_reg_rtx, offset); | |
10048 | ||
10049 | for (i = 0; i < nops; i++) | |
10050 | { | |
10051 | addr = plus_constant (base_reg_rtx, offset + i * 4); | |
10052 | mems[i] = adjust_automodify_address_nv (operands[nops + mem_order[i]], | |
10053 | SImode, addr, 0); | |
10054 | } | |
10055 | emit_insn (arm_gen_store_multiple_1 (nops, sorted_regs, mems, base_reg_rtx, | |
10056 | write_back ? offset + i * 4 : 0)); | |
10057 | return true; | |
ff9940b0 RE |
10058 | } |
10059 | ||
880e2516 | 10060 | int |
70128ad9 | 10061 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
10062 | { |
10063 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 10064 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 10065 | int i; |
50ed9cea | 10066 | rtx src, dst, srcbase, dstbase; |
880e2516 | 10067 | rtx part_bytes_reg = NULL; |
56636818 | 10068 | rtx mem; |
880e2516 RE |
10069 | |
10070 | if (GET_CODE (operands[2]) != CONST_INT | |
10071 | || GET_CODE (operands[3]) != CONST_INT | |
10072 | || INTVAL (operands[2]) > 64 | |
10073 | || INTVAL (operands[3]) & 3) | |
10074 | return 0; | |
10075 | ||
50ed9cea RH |
10076 | dstbase = operands[0]; |
10077 | srcbase = operands[1]; | |
56636818 | 10078 | |
50ed9cea RH |
10079 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
10080 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 10081 | |
e9d7b180 | 10082 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
10083 | out_words_to_go = INTVAL (operands[2]) / 4; |
10084 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 10085 | dstoffset = srcoffset = 0; |
880e2516 RE |
10086 | |
10087 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 10088 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
10089 | |
10090 | for (i = 0; in_words_to_go >= 2; i+=4) | |
10091 | { | |
bd9c7e23 | 10092 | if (in_words_to_go > 4) |
37119410 BS |
10093 | emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, 4, src, |
10094 | TRUE, srcbase, &srcoffset)); | |
bd9c7e23 | 10095 | else |
37119410 BS |
10096 | emit_insn (arm_gen_load_multiple (arm_regs_in_sequence, in_words_to_go, |
10097 | src, FALSE, srcbase, | |
10098 | &srcoffset)); | |
bd9c7e23 | 10099 | |
880e2516 RE |
10100 | if (out_words_to_go) |
10101 | { | |
bd9c7e23 | 10102 | if (out_words_to_go > 4) |
37119410 BS |
10103 | emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, 4, dst, |
10104 | TRUE, dstbase, &dstoffset)); | |
bd9c7e23 | 10105 | else if (out_words_to_go != 1) |
37119410 BS |
10106 | emit_insn (arm_gen_store_multiple (arm_regs_in_sequence, |
10107 | out_words_to_go, dst, | |
bd9c7e23 | 10108 | (last_bytes == 0 |
56636818 | 10109 | ? FALSE : TRUE), |
50ed9cea | 10110 | dstbase, &dstoffset)); |
880e2516 RE |
10111 | else |
10112 | { | |
50ed9cea | 10113 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 10114 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 10115 | if (last_bytes != 0) |
50ed9cea RH |
10116 | { |
10117 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
10118 | dstoffset += 4; | |
10119 | } | |
880e2516 RE |
10120 | } |
10121 | } | |
10122 | ||
10123 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
10124 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
10125 | } | |
10126 | ||
10127 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
10128 | if (out_words_to_go) | |
62b10bbc NC |
10129 | { |
10130 | rtx sreg; | |
f676971a | 10131 | |
50ed9cea RH |
10132 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
10133 | sreg = copy_to_reg (mem); | |
10134 | ||
10135 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 10136 | emit_move_insn (mem, sreg); |
62b10bbc | 10137 | in_words_to_go--; |
f676971a | 10138 | |
e6d29d15 | 10139 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 10140 | } |
880e2516 RE |
10141 | |
10142 | if (in_words_to_go) | |
10143 | { | |
e6d29d15 | 10144 | gcc_assert (in_words_to_go > 0); |
880e2516 | 10145 | |
50ed9cea | 10146 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 10147 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
10148 | } |
10149 | ||
e6d29d15 | 10150 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 10151 | |
880e2516 RE |
10152 | if (BYTES_BIG_ENDIAN && last_bytes) |
10153 | { | |
10154 | rtx tmp = gen_reg_rtx (SImode); | |
10155 | ||
6354dc9b | 10156 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
10157 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
10158 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 10159 | part_bytes_reg = tmp; |
f676971a | 10160 | |
880e2516 RE |
10161 | while (last_bytes) |
10162 | { | |
50ed9cea RH |
10163 | mem = adjust_automodify_address (dstbase, QImode, |
10164 | plus_constant (dst, last_bytes - 1), | |
10165 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
10166 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
10167 | ||
880e2516 RE |
10168 | if (--last_bytes) |
10169 | { | |
10170 | tmp = gen_reg_rtx (SImode); | |
10171 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
10172 | part_bytes_reg = tmp; | |
10173 | } | |
10174 | } | |
f676971a | 10175 | |
880e2516 RE |
10176 | } |
10177 | else | |
10178 | { | |
d5b7b3ae | 10179 | if (last_bytes > 1) |
880e2516 | 10180 | { |
50ed9cea | 10181 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 10182 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
10183 | last_bytes -= 2; |
10184 | if (last_bytes) | |
880e2516 RE |
10185 | { |
10186 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 10187 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 10188 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 10189 | part_bytes_reg = tmp; |
50ed9cea | 10190 | dstoffset += 2; |
880e2516 RE |
10191 | } |
10192 | } | |
f676971a | 10193 | |
d5b7b3ae RE |
10194 | if (last_bytes) |
10195 | { | |
50ed9cea | 10196 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 10197 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 10198 | } |
880e2516 RE |
10199 | } |
10200 | ||
10201 | return 1; | |
10202 | } | |
10203 | ||
03f1640c RE |
10204 | /* Select a dominance comparison mode if possible for a test of the general |
10205 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 10206 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 10207 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 10208 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 10209 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 10210 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
10211 | CC mode. This will then fail to match for the RTL expressions that |
10212 | generate this call. */ | |
03f1640c | 10213 | enum machine_mode |
e32bac5b | 10214 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
10215 | { |
10216 | enum rtx_code cond1, cond2; | |
10217 | int swapped = 0; | |
10218 | ||
10219 | /* Currently we will probably get the wrong result if the individual | |
10220 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 10221 | reverse a comparison if necessary. */ |
84ed5e79 RE |
10222 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
10223 | != CCmode) | |
10224 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
10225 | != CCmode)) | |
10226 | return CCmode; | |
10227 | ||
1646cf41 RE |
10228 | /* The if_then_else variant of this tests the second condition if the |
10229 | first passes, but is true if the first fails. Reverse the first | |
10230 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 10231 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
10232 | cond1 = reverse_condition (cond1); |
10233 | ||
10234 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
10235 | then we can't do this. */ | |
f676971a | 10236 | if (cond1 != cond2 |
5895f793 RE |
10237 | && !comparison_dominates_p (cond1, cond2) |
10238 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
10239 | return CCmode; |
10240 | ||
10241 | if (swapped) | |
10242 | { | |
10243 | enum rtx_code temp = cond1; | |
10244 | cond1 = cond2; | |
10245 | cond2 = temp; | |
10246 | } | |
10247 | ||
10248 | switch (cond1) | |
10249 | { | |
10250 | case EQ: | |
e6d29d15 | 10251 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
10252 | return CC_DEQmode; |
10253 | ||
10254 | switch (cond2) | |
10255 | { | |
e6d29d15 | 10256 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
10257 | case LE: return CC_DLEmode; |
10258 | case LEU: return CC_DLEUmode; | |
10259 | case GE: return CC_DGEmode; | |
10260 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 10261 | default: gcc_unreachable (); |
84ed5e79 RE |
10262 | } |
10263 | ||
84ed5e79 | 10264 | case LT: |
e6d29d15 | 10265 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10266 | return CC_DLTmode; |
e0b92319 | 10267 | |
e6d29d15 NS |
10268 | switch (cond2) |
10269 | { | |
10270 | case LT: | |
10271 | return CC_DLTmode; | |
10272 | case LE: | |
10273 | return CC_DLEmode; | |
10274 | case NE: | |
10275 | return CC_DNEmode; | |
10276 | default: | |
10277 | gcc_unreachable (); | |
10278 | } | |
84ed5e79 RE |
10279 | |
10280 | case GT: | |
e6d29d15 | 10281 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10282 | return CC_DGTmode; |
e6d29d15 NS |
10283 | |
10284 | switch (cond2) | |
10285 | { | |
10286 | case GT: | |
10287 | return CC_DGTmode; | |
10288 | case GE: | |
10289 | return CC_DGEmode; | |
10290 | case NE: | |
10291 | return CC_DNEmode; | |
10292 | default: | |
10293 | gcc_unreachable (); | |
10294 | } | |
f676971a | 10295 | |
84ed5e79 | 10296 | case LTU: |
e6d29d15 | 10297 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10298 | return CC_DLTUmode; |
e6d29d15 NS |
10299 | |
10300 | switch (cond2) | |
10301 | { | |
10302 | case LTU: | |
10303 | return CC_DLTUmode; | |
10304 | case LEU: | |
10305 | return CC_DLEUmode; | |
10306 | case NE: | |
10307 | return CC_DNEmode; | |
10308 | default: | |
10309 | gcc_unreachable (); | |
10310 | } | |
84ed5e79 RE |
10311 | |
10312 | case GTU: | |
e6d29d15 | 10313 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 10314 | return CC_DGTUmode; |
e0b92319 | 10315 | |
e6d29d15 NS |
10316 | switch (cond2) |
10317 | { | |
10318 | case GTU: | |
10319 | return CC_DGTUmode; | |
10320 | case GEU: | |
10321 | return CC_DGEUmode; | |
10322 | case NE: | |
10323 | return CC_DNEmode; | |
10324 | default: | |
10325 | gcc_unreachable (); | |
10326 | } | |
84ed5e79 RE |
10327 | |
10328 | /* The remaining cases only occur when both comparisons are the | |
10329 | same. */ | |
10330 | case NE: | |
e6d29d15 | 10331 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10332 | return CC_DNEmode; |
10333 | ||
10334 | case LE: | |
e6d29d15 | 10335 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10336 | return CC_DLEmode; |
10337 | ||
10338 | case GE: | |
e6d29d15 | 10339 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10340 | return CC_DGEmode; |
10341 | ||
10342 | case LEU: | |
e6d29d15 | 10343 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
10344 | return CC_DLEUmode; |
10345 | ||
10346 | case GEU: | |
e6d29d15 | 10347 | gcc_assert (cond1 == cond2); |
84ed5e79 | 10348 | return CC_DGEUmode; |
ad076f4e RE |
10349 | |
10350 | default: | |
e6d29d15 | 10351 | gcc_unreachable (); |
84ed5e79 | 10352 | } |
84ed5e79 RE |
10353 | } |
10354 | ||
10355 | enum machine_mode | |
e32bac5b | 10356 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
10357 | { |
10358 | /* All floating point compares return CCFP if it is an equality | |
10359 | comparison, and CCFPE otherwise. */ | |
10360 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
10361 | { |
10362 | switch (op) | |
10363 | { | |
10364 | case EQ: | |
10365 | case NE: | |
10366 | case UNORDERED: | |
10367 | case ORDERED: | |
10368 | case UNLT: | |
10369 | case UNLE: | |
10370 | case UNGT: | |
10371 | case UNGE: | |
10372 | case UNEQ: | |
10373 | case LTGT: | |
10374 | return CCFPmode; | |
10375 | ||
10376 | case LT: | |
10377 | case LE: | |
10378 | case GT: | |
10379 | case GE: | |
9b66ebb1 | 10380 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 10381 | return CCFPmode; |
e45b72c4 RE |
10382 | return CCFPEmode; |
10383 | ||
10384 | default: | |
e6d29d15 | 10385 | gcc_unreachable (); |
e45b72c4 RE |
10386 | } |
10387 | } | |
f676971a | 10388 | |
84ed5e79 RE |
10389 | /* A compare with a shifted operand. Because of canonicalization, the |
10390 | comparison will have to be swapped when we emit the assembler. */ | |
3e2d9dcf RR |
10391 | if (GET_MODE (y) == SImode |
10392 | && (REG_P (y) || (GET_CODE (y) == SUBREG)) | |
84ed5e79 RE |
10393 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT |
10394 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
10395 | || GET_CODE (x) == ROTATERT)) | |
10396 | return CC_SWPmode; | |
10397 | ||
04d8b819 RE |
10398 | /* This operation is performed swapped, but since we only rely on the Z |
10399 | flag we don't need an additional mode. */ | |
3e2d9dcf RR |
10400 | if (GET_MODE (y) == SImode |
10401 | && (REG_P (y) || (GET_CODE (y) == SUBREG)) | |
04d8b819 RE |
10402 | && GET_CODE (x) == NEG |
10403 | && (op == EQ || op == NE)) | |
10404 | return CC_Zmode; | |
10405 | ||
f676971a | 10406 | /* This is a special case that is used by combine to allow a |
956d6950 | 10407 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 10408 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 10409 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
10410 | if (GET_MODE (x) == SImode |
10411 | && GET_CODE (x) == ASHIFT | |
10412 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
10413 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
10414 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
10415 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
10416 | && (op == EQ || op == NE | |
10417 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
10418 | && GET_CODE (y) == CONST_INT) | |
10419 | return CC_Zmode; | |
10420 | ||
1646cf41 RE |
10421 | /* A construct for a conditional compare, if the false arm contains |
10422 | 0, then both conditions must be true, otherwise either condition | |
10423 | must be true. Not all conditions are possible, so CCmode is | |
10424 | returned if it can't be done. */ | |
10425 | if (GET_CODE (x) == IF_THEN_ELSE | |
10426 | && (XEXP (x, 2) == const0_rtx | |
10427 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
10428 | && COMPARISON_P (XEXP (x, 0)) |
10429 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 10430 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 10431 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
10432 | |
10433 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
10434 | if (GET_CODE (x) == AND | |
ec8e098d PB |
10435 | && COMPARISON_P (XEXP (x, 0)) |
10436 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
10437 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
10438 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
10439 | |
10440 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
10441 | && COMPARISON_P (XEXP (x, 0)) |
10442 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
10443 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
10444 | DOM_CC_X_OR_Y); | |
1646cf41 | 10445 | |
defc0463 RE |
10446 | /* An operation (on Thumb) where we want to test for a single bit. |
10447 | This is done by shifting that bit up into the top bit of a | |
10448 | scratch register; we can then branch on the sign bit. */ | |
5b3e6663 | 10449 | if (TARGET_THUMB1 |
defc0463 RE |
10450 | && GET_MODE (x) == SImode |
10451 | && (op == EQ || op == NE) | |
f9fa4363 RE |
10452 | && GET_CODE (x) == ZERO_EXTRACT |
10453 | && XEXP (x, 1) == const1_rtx) | |
defc0463 RE |
10454 | return CC_Nmode; |
10455 | ||
84ed5e79 RE |
10456 | /* An operation that sets the condition codes as a side-effect, the |
10457 | V flag is not set correctly, so we can only use comparisons where | |
10458 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 10459 | instead.) */ |
5b3e6663 | 10460 | /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */ |
84ed5e79 RE |
10461 | if (GET_MODE (x) == SImode |
10462 | && y == const0_rtx | |
10463 | && (op == EQ || op == NE || op == LT || op == GE) | |
10464 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
10465 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
10466 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
10467 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
10468 | || GET_CODE (x) == LSHIFTRT | |
10469 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 | 10470 | || GET_CODE (x) == ROTATERT |
5b3e6663 | 10471 | || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) |
84ed5e79 RE |
10472 | return CC_NOOVmode; |
10473 | ||
84ed5e79 RE |
10474 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
10475 | return CC_Zmode; | |
10476 | ||
bd9c7e23 RE |
10477 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
10478 | && GET_CODE (x) == PLUS | |
10479 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
10480 | return CC_Cmode; | |
10481 | ||
73160ba9 DJ |
10482 | if (GET_MODE (x) == DImode || GET_MODE (y) == DImode) |
10483 | { | |
10484 | /* To keep things simple, always use the Cirrus cfcmp64 if it is | |
10485 | available. */ | |
10486 | if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
10487 | return CCmode; | |
10488 | ||
10489 | switch (op) | |
10490 | { | |
10491 | case EQ: | |
10492 | case NE: | |
10493 | /* A DImode comparison against zero can be implemented by | |
10494 | or'ing the two halves together. */ | |
10495 | if (y == const0_rtx) | |
10496 | return CC_Zmode; | |
10497 | ||
10498 | /* We can do an equality test in three Thumb instructions. */ | |
10499 | if (!TARGET_ARM) | |
10500 | return CC_Zmode; | |
10501 | ||
10502 | /* FALLTHROUGH */ | |
10503 | ||
10504 | case LTU: | |
10505 | case LEU: | |
10506 | case GTU: | |
10507 | case GEU: | |
10508 | /* DImode unsigned comparisons can be implemented by cmp + | |
10509 | cmpeq without a scratch register. Not worth doing in | |
10510 | Thumb-2. */ | |
10511 | if (TARGET_ARM) | |
10512 | return CC_CZmode; | |
10513 | ||
10514 | /* FALLTHROUGH */ | |
10515 | ||
10516 | case LT: | |
10517 | case LE: | |
10518 | case GT: | |
10519 | case GE: | |
10520 | /* DImode signed and unsigned comparisons can be implemented | |
10521 | by cmp + sbcs with a scratch register, but that does not | |
10522 | set the Z flag - we must reverse GT/LE/GTU/LEU. */ | |
10523 | gcc_assert (op != EQ && op != NE); | |
10524 | return CC_NCVmode; | |
10525 | ||
10526 | default: | |
10527 | gcc_unreachable (); | |
10528 | } | |
10529 | } | |
10530 | ||
84ed5e79 RE |
10531 | return CCmode; |
10532 | } | |
10533 | ||
ff9940b0 RE |
10534 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
10535 | return the rtx for register 0 in the proper mode. FP means this is a | |
10536 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 10537 | rtx |
e32bac5b | 10538 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 | 10539 | { |
73160ba9 DJ |
10540 | enum machine_mode mode; |
10541 | rtx cc_reg; | |
10542 | int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode; | |
ff9940b0 | 10543 | |
73160ba9 DJ |
10544 | /* We might have X as a constant, Y as a register because of the predicates |
10545 | used for cmpdi. If so, force X to a register here. */ | |
10546 | if (dimode_comparison && !REG_P (x)) | |
10547 | x = force_reg (DImode, x); | |
10548 | ||
10549 | mode = SELECT_CC_MODE (code, x, y); | |
10550 | cc_reg = gen_rtx_REG (mode, CC_REGNUM); | |
10551 | ||
10552 | if (dimode_comparison | |
10553 | && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) | |
10554 | && mode != CC_CZmode) | |
10555 | { | |
10556 | rtx clobber, set; | |
10557 | ||
10558 | /* To compare two non-zero values for equality, XOR them and | |
10559 | then compare against zero. Not used for ARM mode; there | |
10560 | CC_CZmode is cheaper. */ | |
10561 | if (mode == CC_Zmode && y != const0_rtx) | |
10562 | { | |
10563 | x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN); | |
10564 | y = const0_rtx; | |
10565 | } | |
10566 | /* A scratch register is required. */ | |
10567 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); | |
10568 | set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y)); | |
10569 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber))); | |
10570 | } | |
10571 | else | |
10572 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); | |
ff9940b0 RE |
10573 | |
10574 | return cc_reg; | |
10575 | } | |
10576 | ||
fcd53748 JT |
10577 | /* Generate a sequence of insns that will generate the correct return |
10578 | address mask depending on the physical architecture that the program | |
10579 | is running on. */ | |
fcd53748 | 10580 | rtx |
e32bac5b | 10581 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
10582 | { |
10583 | rtx reg = gen_reg_rtx (Pmode); | |
10584 | ||
10585 | emit_insn (gen_return_addr_mask (reg)); | |
10586 | return reg; | |
10587 | } | |
10588 | ||
0a81f500 | 10589 | void |
e32bac5b | 10590 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 10591 | { |
f9cc092a RE |
10592 | rtx ref = operands[1]; |
10593 | rtx base, scratch; | |
10594 | HOST_WIDE_INT offset = 0; | |
10595 | ||
10596 | if (GET_CODE (ref) == SUBREG) | |
10597 | { | |
ddef6bc7 | 10598 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
10599 | ref = SUBREG_REG (ref); |
10600 | } | |
10601 | ||
10602 | if (GET_CODE (ref) == REG) | |
10603 | { | |
10604 | /* We have a pseudo which has been spilt onto the stack; there | |
10605 | are two cases here: the first where there is a simple | |
10606 | stack-slot replacement and a second where the stack-slot is | |
10607 | out of range, or is used as a subreg. */ | |
10608 | if (reg_equiv_mem[REGNO (ref)]) | |
10609 | { | |
10610 | ref = reg_equiv_mem[REGNO (ref)]; | |
10611 | base = find_replacement (&XEXP (ref, 0)); | |
10612 | } | |
10613 | else | |
6354dc9b | 10614 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
10615 | base = reg_equiv_address[REGNO (ref)]; |
10616 | } | |
10617 | else | |
10618 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 10619 | |
e5e809f4 JL |
10620 | /* Handle the case where the address is too complex to be offset by 1. */ |
10621 | if (GET_CODE (base) == MINUS | |
10622 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
10623 | { | |
f9cc092a | 10624 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 10625 | |
d66437c5 | 10626 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
10627 | base = base_plus; |
10628 | } | |
f9cc092a RE |
10629 | else if (GET_CODE (base) == PLUS) |
10630 | { | |
6354dc9b | 10631 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
10632 | HOST_WIDE_INT hi, lo; |
10633 | ||
10634 | offset += INTVAL (XEXP (base, 1)); | |
10635 | base = XEXP (base, 0); | |
10636 | ||
6354dc9b | 10637 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
10638 | /* Valid range for lo is -4095 -> 4095 */ |
10639 | lo = (offset >= 0 | |
10640 | ? (offset & 0xfff) | |
10641 | : -((-offset) & 0xfff)); | |
10642 | ||
10643 | /* Corner case, if lo is the max offset then we would be out of range | |
10644 | once we have added the additional 1 below, so bump the msb into the | |
10645 | pre-loading insn(s). */ | |
10646 | if (lo == 4095) | |
10647 | lo &= 0x7ff; | |
10648 | ||
30cf4896 KG |
10649 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
10650 | ^ (HOST_WIDE_INT) 0x80000000) | |
10651 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 10652 | |
e6d29d15 | 10653 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
10654 | |
10655 | if (hi != 0) | |
10656 | { | |
10657 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10658 | ||
10659 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 10660 | that require more than one insn. */ |
f9cc092a RE |
10661 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
10662 | base = base_plus; | |
10663 | offset = lo; | |
10664 | } | |
10665 | } | |
e5e809f4 | 10666 | |
3a1944a6 RE |
10667 | /* Operands[2] may overlap operands[0] (though it won't overlap |
10668 | operands[1]), that's why we asked for a DImode reg -- so we can | |
10669 | use the bit that does not overlap. */ | |
10670 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
10671 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10672 | else | |
10673 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
10674 | ||
f9cc092a RE |
10675 | emit_insn (gen_zero_extendqisi2 (scratch, |
10676 | gen_rtx_MEM (QImode, | |
10677 | plus_constant (base, | |
10678 | offset)))); | |
43cffd11 | 10679 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 10680 | gen_rtx_MEM (QImode, |
f9cc092a RE |
10681 | plus_constant (base, |
10682 | offset + 1)))); | |
5895f793 | 10683 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
10684 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
10685 | gen_rtx_IOR (SImode, | |
10686 | gen_rtx_ASHIFT | |
10687 | (SImode, | |
10688 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
10689 | GEN_INT (8)), | |
10690 | scratch)); | |
0a81f500 | 10691 | else |
d66437c5 RE |
10692 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
10693 | gen_rtx_IOR (SImode, | |
10694 | gen_rtx_ASHIFT (SImode, scratch, | |
10695 | GEN_INT (8)), | |
10696 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
10697 | } |
10698 | ||
72ac76be | 10699 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
10700 | byte stores. Take care not to clobber the input values until after we |
10701 | have moved them somewhere safe. This code assumes that if the DImode | |
10702 | scratch in operands[2] overlaps either the input value or output address | |
10703 | in some way, then that value must die in this insn (we absolutely need | |
10704 | two scratch registers for some corner cases). */ | |
f3bb6135 | 10705 | void |
e32bac5b | 10706 | arm_reload_out_hi (rtx *operands) |
af48348a | 10707 | { |
f9cc092a RE |
10708 | rtx ref = operands[0]; |
10709 | rtx outval = operands[1]; | |
10710 | rtx base, scratch; | |
10711 | HOST_WIDE_INT offset = 0; | |
10712 | ||
10713 | if (GET_CODE (ref) == SUBREG) | |
10714 | { | |
ddef6bc7 | 10715 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
10716 | ref = SUBREG_REG (ref); |
10717 | } | |
10718 | ||
f9cc092a RE |
10719 | if (GET_CODE (ref) == REG) |
10720 | { | |
10721 | /* We have a pseudo which has been spilt onto the stack; there | |
10722 | are two cases here: the first where there is a simple | |
10723 | stack-slot replacement and a second where the stack-slot is | |
10724 | out of range, or is used as a subreg. */ | |
10725 | if (reg_equiv_mem[REGNO (ref)]) | |
10726 | { | |
10727 | ref = reg_equiv_mem[REGNO (ref)]; | |
10728 | base = find_replacement (&XEXP (ref, 0)); | |
10729 | } | |
10730 | else | |
6354dc9b | 10731 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
10732 | base = reg_equiv_address[REGNO (ref)]; |
10733 | } | |
10734 | else | |
10735 | base = find_replacement (&XEXP (ref, 0)); | |
10736 | ||
10737 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
10738 | ||
10739 | /* Handle the case where the address is too complex to be offset by 1. */ | |
10740 | if (GET_CODE (base) == MINUS | |
10741 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
10742 | { | |
10743 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10744 | ||
10745 | /* Be careful not to destroy OUTVAL. */ | |
10746 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
10747 | { | |
10748 | /* Updating base_plus might destroy outval, see if we can | |
10749 | swap the scratch and base_plus. */ | |
5895f793 | 10750 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
10751 | { |
10752 | rtx tmp = scratch; | |
10753 | scratch = base_plus; | |
10754 | base_plus = tmp; | |
10755 | } | |
10756 | else | |
10757 | { | |
10758 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
10759 | ||
10760 | /* Be conservative and copy OUTVAL into the scratch now, | |
10761 | this should only be necessary if outval is a subreg | |
10762 | of something larger than a word. */ | |
10763 | /* XXX Might this clobber base? I can't see how it can, | |
10764 | since scratch is known to overlap with OUTVAL, and | |
10765 | must be wider than a word. */ | |
10766 | emit_insn (gen_movhi (scratch_hi, outval)); | |
10767 | outval = scratch_hi; | |
10768 | } | |
10769 | } | |
10770 | ||
d66437c5 | 10771 | emit_set_insn (base_plus, base); |
f9cc092a RE |
10772 | base = base_plus; |
10773 | } | |
10774 | else if (GET_CODE (base) == PLUS) | |
10775 | { | |
6354dc9b | 10776 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
10777 | HOST_WIDE_INT hi, lo; |
10778 | ||
10779 | offset += INTVAL (XEXP (base, 1)); | |
10780 | base = XEXP (base, 0); | |
10781 | ||
6354dc9b | 10782 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
10783 | /* Valid range for lo is -4095 -> 4095 */ |
10784 | lo = (offset >= 0 | |
10785 | ? (offset & 0xfff) | |
10786 | : -((-offset) & 0xfff)); | |
10787 | ||
10788 | /* Corner case, if lo is the max offset then we would be out of range | |
10789 | once we have added the additional 1 below, so bump the msb into the | |
10790 | pre-loading insn(s). */ | |
10791 | if (lo == 4095) | |
10792 | lo &= 0x7ff; | |
10793 | ||
30cf4896 KG |
10794 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
10795 | ^ (HOST_WIDE_INT) 0x80000000) | |
10796 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 10797 | |
e6d29d15 | 10798 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
10799 | |
10800 | if (hi != 0) | |
10801 | { | |
10802 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
10803 | ||
10804 | /* Be careful not to destroy OUTVAL. */ | |
10805 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
10806 | { | |
10807 | /* Updating base_plus might destroy outval, see if we | |
10808 | can swap the scratch and base_plus. */ | |
5895f793 | 10809 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
10810 | { |
10811 | rtx tmp = scratch; | |
10812 | scratch = base_plus; | |
10813 | base_plus = tmp; | |
10814 | } | |
10815 | else | |
10816 | { | |
10817 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
10818 | ||
10819 | /* Be conservative and copy outval into scratch now, | |
10820 | this should only be necessary if outval is a | |
10821 | subreg of something larger than a word. */ | |
10822 | /* XXX Might this clobber base? I can't see how it | |
10823 | can, since scratch is known to overlap with | |
10824 | outval. */ | |
10825 | emit_insn (gen_movhi (scratch_hi, outval)); | |
10826 | outval = scratch_hi; | |
10827 | } | |
10828 | } | |
10829 | ||
10830 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 10831 | that require more than one insn. */ |
f9cc092a RE |
10832 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
10833 | base = base_plus; | |
10834 | offset = lo; | |
10835 | } | |
10836 | } | |
af48348a | 10837 | |
b5cc037f RE |
10838 | if (BYTES_BIG_ENDIAN) |
10839 | { | |
f676971a | 10840 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 10841 | plus_constant (base, offset + 1)), |
5d5603e2 | 10842 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
10843 | emit_insn (gen_lshrsi3 (scratch, |
10844 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 10845 | GEN_INT (8))); |
f9cc092a | 10846 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 10847 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
10848 | } |
10849 | else | |
10850 | { | |
f9cc092a | 10851 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 10852 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
10853 | emit_insn (gen_lshrsi3 (scratch, |
10854 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 10855 | GEN_INT (8))); |
f9cc092a RE |
10856 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
10857 | plus_constant (base, offset + 1)), | |
5d5603e2 | 10858 | gen_lowpart (QImode, scratch))); |
b5cc037f | 10859 | } |
af48348a | 10860 | } |
866af8a9 JB |
10861 | |
10862 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
10863 | (padded to the size of a word) should be passed in a register. */ | |
10864 | ||
10865 | static bool | |
586de218 | 10866 | arm_must_pass_in_stack (enum machine_mode mode, const_tree type) |
866af8a9 JB |
10867 | { |
10868 | if (TARGET_AAPCS_BASED) | |
10869 | return must_pass_in_stack_var_size (mode, type); | |
10870 | else | |
10871 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
10872 | } | |
10873 | ||
10874 | ||
10875 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
10876 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
10877 | i.e. if the least-significant byte has useful data. |
10878 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
10879 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
10880 | |
10881 | bool | |
586de218 | 10882 | arm_pad_arg_upward (enum machine_mode mode, const_tree type) |
866af8a9 JB |
10883 | { |
10884 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 10885 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
10886 | |
10887 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
10888 | return false; | |
10889 | ||
10890 | return true; | |
10891 | } | |
10892 | ||
10893 | ||
10894 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
10895 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
10896 | byte of the register has useful data, and return the opposite if the | |
10897 | most significant byte does. | |
10898 | For AAPCS, small aggregates and small complex types are always padded | |
10899 | upwards. */ | |
10900 | ||
10901 | bool | |
10902 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
10903 | tree type, int first ATTRIBUTE_UNUSED) | |
10904 | { | |
10905 | if (TARGET_AAPCS_BASED | |
10906 | && BYTES_BIG_ENDIAN | |
10907 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
10908 | && int_size_in_bytes (type) <= 4) | |
10909 | return true; | |
10910 | ||
10911 | /* Otherwise, use default padding. */ | |
10912 | return !BYTES_BIG_ENDIAN; | |
10913 | } | |
10914 | ||
2b835d68 | 10915 | \f |
d5b7b3ae RE |
10916 | /* Print a symbolic form of X to the debug file, F. */ |
10917 | static void | |
e32bac5b | 10918 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
10919 | { |
10920 | switch (GET_CODE (x)) | |
10921 | { | |
10922 | case CONST_INT: | |
10923 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
10924 | return; | |
10925 | ||
10926 | case CONST_DOUBLE: | |
10927 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
10928 | return; | |
10929 | ||
5a9335ef NC |
10930 | case CONST_VECTOR: |
10931 | { | |
10932 | int i; | |
10933 | ||
10934 | fprintf (f, "<"); | |
10935 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
10936 | { | |
10937 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
10938 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
10939 | fputc (',', f); | |
10940 | } | |
10941 | fprintf (f, ">"); | |
10942 | } | |
10943 | return; | |
10944 | ||
d5b7b3ae RE |
10945 | case CONST_STRING: |
10946 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
10947 | return; | |
10948 | ||
10949 | case SYMBOL_REF: | |
10950 | fprintf (f, "`%s'", XSTR (x, 0)); | |
10951 | return; | |
10952 | ||
10953 | case LABEL_REF: | |
10954 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
10955 | return; | |
10956 | ||
10957 | case CONST: | |
10958 | arm_print_value (f, XEXP (x, 0)); | |
10959 | return; | |
10960 | ||
10961 | case PLUS: | |
10962 | arm_print_value (f, XEXP (x, 0)); | |
10963 | fprintf (f, "+"); | |
10964 | arm_print_value (f, XEXP (x, 1)); | |
10965 | return; | |
10966 | ||
10967 | case PC: | |
10968 | fprintf (f, "pc"); | |
10969 | return; | |
10970 | ||
10971 | default: | |
10972 | fprintf (f, "????"); | |
10973 | return; | |
10974 | } | |
10975 | } | |
10976 | \f | |
2b835d68 | 10977 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 10978 | |
949d79eb RE |
10979 | /* Arm instructions cannot load a large constant directly into a |
10980 | register; they have to come from a pc relative load. The constant | |
10981 | must therefore be placed in the addressable range of the pc | |
10982 | relative load. Depending on the precise pc relative load | |
10983 | instruction the range is somewhere between 256 bytes and 4k. This | |
10984 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
10985 | generate code to branch around it. |
10986 | ||
949d79eb RE |
10987 | It is important to minimize this, since the branches will slow |
10988 | things down and make the code larger. | |
2b835d68 | 10989 | |
949d79eb RE |
10990 | Normally we can hide the table after an existing unconditional |
10991 | branch so that there is no interruption of the flow, but in the | |
10992 | worst case the code looks like this: | |
2b835d68 RE |
10993 | |
10994 | ldr rn, L1 | |
949d79eb | 10995 | ... |
2b835d68 RE |
10996 | b L2 |
10997 | align | |
10998 | L1: .long value | |
10999 | L2: | |
949d79eb | 11000 | ... |
2b835d68 | 11001 | |
2b835d68 | 11002 | ldr rn, L3 |
949d79eb | 11003 | ... |
2b835d68 RE |
11004 | b L4 |
11005 | align | |
2b835d68 RE |
11006 | L3: .long value |
11007 | L4: | |
949d79eb RE |
11008 | ... |
11009 | ||
11010 | We fix this by performing a scan after scheduling, which notices | |
11011 | which instructions need to have their operands fetched from the | |
11012 | constant table and builds the table. | |
11013 | ||
11014 | The algorithm starts by building a table of all the constants that | |
11015 | need fixing up and all the natural barriers in the function (places | |
11016 | where a constant table can be dropped without breaking the flow). | |
11017 | For each fixup we note how far the pc-relative replacement will be | |
11018 | able to reach and the offset of the instruction into the function. | |
11019 | ||
11020 | Having built the table we then group the fixes together to form | |
11021 | tables that are as large as possible (subject to addressing | |
11022 | constraints) and emit each table of constants after the last | |
11023 | barrier that is within range of all the instructions in the group. | |
11024 | If a group does not contain a barrier, then we forcibly create one | |
11025 | by inserting a jump instruction into the flow. Once the table has | |
11026 | been inserted, the insns are then modified to reference the | |
11027 | relevant entry in the pool. | |
11028 | ||
6354dc9b | 11029 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 11030 | |
d5b7b3ae | 11031 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
11032 | aligning the pools to the start of cache lines; this alignment |
11033 | would need to be taken into account when calculating addressability | |
6354dc9b | 11034 | of a pool. */ |
2b835d68 | 11035 | |
d5b7b3ae RE |
11036 | /* These typedefs are located at the start of this file, so that |
11037 | they can be used in the prototypes there. This comment is to | |
11038 | remind readers of that fact so that the following structures | |
11039 | can be understood more easily. | |
11040 | ||
11041 | typedef struct minipool_node Mnode; | |
11042 | typedef struct minipool_fixup Mfix; */ | |
11043 | ||
11044 | struct minipool_node | |
11045 | { | |
11046 | /* Doubly linked chain of entries. */ | |
11047 | Mnode * next; | |
11048 | Mnode * prev; | |
11049 | /* The maximum offset into the code that this entry can be placed. While | |
11050 | pushing fixes for forward references, all entries are sorted in order | |
11051 | of increasing max_address. */ | |
11052 | HOST_WIDE_INT max_address; | |
5519a4f9 | 11053 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
11054 | HOST_WIDE_INT min_address; |
11055 | /* The number of fixes referencing this entry. This can become zero | |
11056 | if we "unpush" an entry. In this case we ignore the entry when we | |
11057 | come to emit the code. */ | |
11058 | int refcount; | |
11059 | /* The offset from the start of the minipool. */ | |
11060 | HOST_WIDE_INT offset; | |
11061 | /* The value in table. */ | |
11062 | rtx value; | |
11063 | /* The mode of value. */ | |
11064 | enum machine_mode mode; | |
5a9335ef NC |
11065 | /* The size of the value. With iWMMXt enabled |
11066 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
11067 | int fix_size; |
11068 | }; | |
11069 | ||
11070 | struct minipool_fixup | |
2b835d68 | 11071 | { |
d5b7b3ae RE |
11072 | Mfix * next; |
11073 | rtx insn; | |
11074 | HOST_WIDE_INT address; | |
11075 | rtx * loc; | |
11076 | enum machine_mode mode; | |
11077 | int fix_size; | |
11078 | rtx value; | |
11079 | Mnode * minipool; | |
11080 | HOST_WIDE_INT forwards; | |
11081 | HOST_WIDE_INT backwards; | |
11082 | }; | |
2b835d68 | 11083 | |
d5b7b3ae RE |
11084 | /* Fixes less than a word need padding out to a word boundary. */ |
11085 | #define MINIPOOL_FIX_SIZE(mode) \ | |
11086 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 11087 | |
d5b7b3ae RE |
11088 | static Mnode * minipool_vector_head; |
11089 | static Mnode * minipool_vector_tail; | |
11090 | static rtx minipool_vector_label; | |
34a9f549 | 11091 | static int minipool_pad; |
332072db | 11092 | |
d5b7b3ae RE |
11093 | /* The linked list of all minipool fixes required for this function. */ |
11094 | Mfix * minipool_fix_head; | |
11095 | Mfix * minipool_fix_tail; | |
11096 | /* The fix entry for the current minipool, once it has been placed. */ | |
11097 | Mfix * minipool_barrier; | |
11098 | ||
11099 | /* Determines if INSN is the start of a jump table. Returns the end | |
11100 | of the TABLE or NULL_RTX. */ | |
11101 | static rtx | |
e32bac5b | 11102 | is_jump_table (rtx insn) |
2b835d68 | 11103 | { |
d5b7b3ae | 11104 | rtx table; |
f676971a | 11105 | |
d5b7b3ae RE |
11106 | if (GET_CODE (insn) == JUMP_INSN |
11107 | && JUMP_LABEL (insn) != NULL | |
11108 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
11109 | == next_real_insn (insn)) | |
11110 | && table != NULL | |
11111 | && GET_CODE (table) == JUMP_INSN | |
11112 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
11113 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
11114 | return table; | |
11115 | ||
11116 | return NULL_RTX; | |
2b835d68 RE |
11117 | } |
11118 | ||
657d9449 RE |
11119 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
11120 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
11121 | #endif | |
11122 | ||
d5b7b3ae | 11123 | static HOST_WIDE_INT |
e32bac5b | 11124 | get_jump_table_size (rtx insn) |
2b835d68 | 11125 | { |
657d9449 RE |
11126 | /* ADDR_VECs only take room if read-only data does into the text |
11127 | section. */ | |
d6b5193b | 11128 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
11129 | { |
11130 | rtx body = PATTERN (insn); | |
11131 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
5b3e6663 PB |
11132 | HOST_WIDE_INT size; |
11133 | HOST_WIDE_INT modesize; | |
2b835d68 | 11134 | |
5b3e6663 PB |
11135 | modesize = GET_MODE_SIZE (GET_MODE (body)); |
11136 | size = modesize * XVECLEN (body, elt); | |
11137 | switch (modesize) | |
11138 | { | |
11139 | case 1: | |
88512ba0 | 11140 | /* Round up size of TBB table to a halfword boundary. */ |
5b3e6663 PB |
11141 | size = (size + 1) & ~(HOST_WIDE_INT)1; |
11142 | break; | |
11143 | case 2: | |
7a085dce | 11144 | /* No padding necessary for TBH. */ |
5b3e6663 PB |
11145 | break; |
11146 | case 4: | |
11147 | /* Add two bytes for alignment on Thumb. */ | |
11148 | if (TARGET_THUMB) | |
11149 | size += 2; | |
11150 | break; | |
11151 | default: | |
11152 | gcc_unreachable (); | |
11153 | } | |
11154 | return size; | |
657d9449 RE |
11155 | } |
11156 | ||
11157 | return 0; | |
d5b7b3ae | 11158 | } |
2b835d68 | 11159 | |
d5b7b3ae RE |
11160 | /* Move a minipool fix MP from its current location to before MAX_MP. |
11161 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 11162 | constraints may need updating. */ |
d5b7b3ae | 11163 | static Mnode * |
e32bac5b RE |
11164 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
11165 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 11166 | { |
e6d29d15 NS |
11167 | /* The code below assumes these are different. */ |
11168 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
11169 | |
11170 | if (max_mp == NULL) | |
11171 | { | |
11172 | if (max_address < mp->max_address) | |
11173 | mp->max_address = max_address; | |
11174 | } | |
11175 | else | |
2b835d68 | 11176 | { |
d5b7b3ae RE |
11177 | if (max_address > max_mp->max_address - mp->fix_size) |
11178 | mp->max_address = max_mp->max_address - mp->fix_size; | |
11179 | else | |
11180 | mp->max_address = max_address; | |
2b835d68 | 11181 | |
d5b7b3ae RE |
11182 | /* Unlink MP from its current position. Since max_mp is non-null, |
11183 | mp->prev must be non-null. */ | |
11184 | mp->prev->next = mp->next; | |
11185 | if (mp->next != NULL) | |
11186 | mp->next->prev = mp->prev; | |
11187 | else | |
11188 | minipool_vector_tail = mp->prev; | |
2b835d68 | 11189 | |
d5b7b3ae RE |
11190 | /* Re-insert it before MAX_MP. */ |
11191 | mp->next = max_mp; | |
11192 | mp->prev = max_mp->prev; | |
11193 | max_mp->prev = mp; | |
f676971a | 11194 | |
d5b7b3ae RE |
11195 | if (mp->prev != NULL) |
11196 | mp->prev->next = mp; | |
11197 | else | |
11198 | minipool_vector_head = mp; | |
11199 | } | |
2b835d68 | 11200 | |
d5b7b3ae RE |
11201 | /* Save the new entry. */ |
11202 | max_mp = mp; | |
11203 | ||
d6a7951f | 11204 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
11205 | required. */ |
11206 | while (mp->prev != NULL | |
11207 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
11208 | { | |
11209 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
11210 | mp = mp->prev; | |
2b835d68 RE |
11211 | } |
11212 | ||
d5b7b3ae | 11213 | return max_mp; |
2b835d68 RE |
11214 | } |
11215 | ||
d5b7b3ae RE |
11216 | /* Add a constant to the minipool for a forward reference. Returns the |
11217 | node added or NULL if the constant will not fit in this pool. */ | |
11218 | static Mnode * | |
e32bac5b | 11219 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
11220 | { |
11221 | /* If set, max_mp is the first pool_entry that has a lower | |
11222 | constraint than the one we are trying to add. */ | |
11223 | Mnode * max_mp = NULL; | |
34a9f549 | 11224 | HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; |
d5b7b3ae | 11225 | Mnode * mp; |
f676971a | 11226 | |
7a7017bc PB |
11227 | /* If the minipool starts before the end of FIX->INSN then this FIX |
11228 | can not be placed into the current pool. Furthermore, adding the | |
11229 | new constant pool entry may cause the pool to start FIX_SIZE bytes | |
11230 | earlier. */ | |
d5b7b3ae | 11231 | if (minipool_vector_head && |
7a7017bc PB |
11232 | (fix->address + get_attr_length (fix->insn) |
11233 | >= minipool_vector_head->max_address - fix->fix_size)) | |
d5b7b3ae | 11234 | return NULL; |
2b835d68 | 11235 | |
d5b7b3ae RE |
11236 | /* Scan the pool to see if a constant with the same value has |
11237 | already been added. While we are doing this, also note the | |
11238 | location where we must insert the constant if it doesn't already | |
11239 | exist. */ | |
11240 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11241 | { | |
11242 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
11243 | && fix->mode == mp->mode | |
11244 | && (GET_CODE (fix->value) != CODE_LABEL | |
11245 | || (CODE_LABEL_NUMBER (fix->value) | |
11246 | == CODE_LABEL_NUMBER (mp->value))) | |
11247 | && rtx_equal_p (fix->value, mp->value)) | |
11248 | { | |
11249 | /* More than one fix references this entry. */ | |
11250 | mp->refcount++; | |
11251 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
11252 | } | |
11253 | ||
11254 | /* Note the insertion point if necessary. */ | |
11255 | if (max_mp == NULL | |
11256 | && mp->max_address > max_address) | |
11257 | max_mp = mp; | |
5a9335ef NC |
11258 | |
11259 | /* If we are inserting an 8-bytes aligned quantity and | |
11260 | we have not already found an insertion point, then | |
11261 | make sure that all such 8-byte aligned quantities are | |
11262 | placed at the start of the pool. */ | |
5848830f | 11263 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 11264 | && max_mp == NULL |
88f77cba JB |
11265 | && fix->fix_size >= 8 |
11266 | && mp->fix_size < 8) | |
5a9335ef NC |
11267 | { |
11268 | max_mp = mp; | |
11269 | max_address = mp->max_address; | |
11270 | } | |
d5b7b3ae RE |
11271 | } |
11272 | ||
11273 | /* The value is not currently in the minipool, so we need to create | |
11274 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
11275 | the end of the list since the placement is less constrained than | |
11276 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 11277 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae | 11278 | entries. */ |
5ed6ace5 | 11279 | mp = XNEW (Mnode); |
d5b7b3ae RE |
11280 | mp->fix_size = fix->fix_size; |
11281 | mp->mode = fix->mode; | |
11282 | mp->value = fix->value; | |
11283 | mp->refcount = 1; | |
11284 | /* Not yet required for a backwards ref. */ | |
11285 | mp->min_address = -65536; | |
11286 | ||
11287 | if (max_mp == NULL) | |
11288 | { | |
11289 | mp->max_address = max_address; | |
11290 | mp->next = NULL; | |
11291 | mp->prev = minipool_vector_tail; | |
11292 | ||
11293 | if (mp->prev == NULL) | |
11294 | { | |
11295 | minipool_vector_head = mp; | |
11296 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 11297 | } |
2b835d68 | 11298 | else |
d5b7b3ae | 11299 | mp->prev->next = mp; |
2b835d68 | 11300 | |
d5b7b3ae RE |
11301 | minipool_vector_tail = mp; |
11302 | } | |
11303 | else | |
11304 | { | |
11305 | if (max_address > max_mp->max_address - mp->fix_size) | |
11306 | mp->max_address = max_mp->max_address - mp->fix_size; | |
11307 | else | |
11308 | mp->max_address = max_address; | |
11309 | ||
11310 | mp->next = max_mp; | |
11311 | mp->prev = max_mp->prev; | |
11312 | max_mp->prev = mp; | |
11313 | if (mp->prev != NULL) | |
11314 | mp->prev->next = mp; | |
11315 | else | |
11316 | minipool_vector_head = mp; | |
11317 | } | |
11318 | ||
11319 | /* Save the new entry. */ | |
11320 | max_mp = mp; | |
11321 | ||
d6a7951f | 11322 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
11323 | required. */ |
11324 | while (mp->prev != NULL | |
11325 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
11326 | { | |
11327 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
11328 | mp = mp->prev; | |
2b835d68 RE |
11329 | } |
11330 | ||
d5b7b3ae RE |
11331 | return max_mp; |
11332 | } | |
11333 | ||
11334 | static Mnode * | |
e32bac5b RE |
11335 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
11336 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
11337 | { |
11338 | HOST_WIDE_INT offset; | |
11339 | ||
e6d29d15 NS |
11340 | /* The code below assumes these are different. */ |
11341 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
11342 | |
11343 | if (min_mp == NULL) | |
2b835d68 | 11344 | { |
d5b7b3ae RE |
11345 | if (min_address > mp->min_address) |
11346 | mp->min_address = min_address; | |
11347 | } | |
11348 | else | |
11349 | { | |
11350 | /* We will adjust this below if it is too loose. */ | |
11351 | mp->min_address = min_address; | |
11352 | ||
11353 | /* Unlink MP from its current position. Since min_mp is non-null, | |
11354 | mp->next must be non-null. */ | |
11355 | mp->next->prev = mp->prev; | |
11356 | if (mp->prev != NULL) | |
11357 | mp->prev->next = mp->next; | |
11358 | else | |
11359 | minipool_vector_head = mp->next; | |
11360 | ||
11361 | /* Reinsert it after MIN_MP. */ | |
11362 | mp->prev = min_mp; | |
11363 | mp->next = min_mp->next; | |
11364 | min_mp->next = mp; | |
11365 | if (mp->next != NULL) | |
11366 | mp->next->prev = mp; | |
2b835d68 | 11367 | else |
d5b7b3ae RE |
11368 | minipool_vector_tail = mp; |
11369 | } | |
11370 | ||
11371 | min_mp = mp; | |
11372 | ||
11373 | offset = 0; | |
11374 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11375 | { | |
11376 | mp->offset = offset; | |
11377 | if (mp->refcount > 0) | |
11378 | offset += mp->fix_size; | |
11379 | ||
11380 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
11381 | mp->next->min_address = mp->min_address + mp->fix_size; | |
11382 | } | |
11383 | ||
11384 | return min_mp; | |
f676971a | 11385 | } |
d5b7b3ae RE |
11386 | |
11387 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 11388 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
11389 | |
11390 | Note that the code for insertion for a backwards reference can be | |
11391 | somewhat confusing because the calculated offsets for each fix do | |
11392 | not take into account the size of the pool (which is still under | |
11393 | construction. */ | |
11394 | static Mnode * | |
e32bac5b | 11395 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
11396 | { |
11397 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
11398 | than the one we are trying to add. */ | |
e32bac5b | 11399 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
11400 | /* This can be negative, since it is only a constraint. */ |
11401 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 11402 | Mnode *mp; |
d5b7b3ae RE |
11403 | |
11404 | /* If we can't reach the current pool from this insn, or if we can't | |
11405 | insert this entry at the end of the pool without pushing other | |
11406 | fixes out of range, then we don't try. This ensures that we | |
11407 | can't fail later on. */ | |
11408 | if (min_address >= minipool_barrier->address | |
11409 | || (minipool_vector_tail->min_address + fix->fix_size | |
11410 | >= minipool_barrier->address)) | |
11411 | return NULL; | |
11412 | ||
11413 | /* Scan the pool to see if a constant with the same value has | |
11414 | already been added. While we are doing this, also note the | |
11415 | location where we must insert the constant if it doesn't already | |
11416 | exist. */ | |
11417 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
11418 | { | |
11419 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
11420 | && fix->mode == mp->mode | |
11421 | && (GET_CODE (fix->value) != CODE_LABEL | |
11422 | || (CODE_LABEL_NUMBER (fix->value) | |
11423 | == CODE_LABEL_NUMBER (mp->value))) | |
11424 | && rtx_equal_p (fix->value, mp->value) | |
11425 | /* Check that there is enough slack to move this entry to the | |
11426 | end of the table (this is conservative). */ | |
f676971a EC |
11427 | && (mp->max_address |
11428 | > (minipool_barrier->address | |
d5b7b3ae RE |
11429 | + minipool_vector_tail->offset |
11430 | + minipool_vector_tail->fix_size))) | |
11431 | { | |
11432 | mp->refcount++; | |
11433 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
11434 | } | |
11435 | ||
11436 | if (min_mp != NULL) | |
11437 | mp->min_address += fix->fix_size; | |
11438 | else | |
11439 | { | |
11440 | /* Note the insertion point if necessary. */ | |
11441 | if (mp->min_address < min_address) | |
5a9335ef NC |
11442 | { |
11443 | /* For now, we do not allow the insertion of 8-byte alignment | |
11444 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f | 11445 | if (ARM_DOUBLEWORD_ALIGN |
88f77cba | 11446 | && fix->fix_size >= 8 && mp->fix_size < 8) |
5a9335ef NC |
11447 | return NULL; |
11448 | else | |
11449 | min_mp = mp; | |
11450 | } | |
d5b7b3ae RE |
11451 | else if (mp->max_address |
11452 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
11453 | { | |
11454 | /* Inserting before this entry would push the fix beyond | |
11455 | its maximum address (which can happen if we have | |
11456 | re-located a forwards fix); force the new fix to come | |
11457 | after it. */ | |
853ff9e2 JM |
11458 | if (ARM_DOUBLEWORD_ALIGN |
11459 | && fix->fix_size >= 8 && mp->fix_size < 8) | |
11460 | return NULL; | |
11461 | else | |
11462 | { | |
11463 | min_mp = mp; | |
11464 | min_address = mp->min_address + fix->fix_size; | |
11465 | } | |
d5b7b3ae | 11466 | } |
853ff9e2 JM |
11467 | /* Do not insert a non-8-byte aligned quantity before 8-byte |
11468 | aligned quantities. */ | |
5848830f | 11469 | else if (ARM_DOUBLEWORD_ALIGN |
853ff9e2 JM |
11470 | && fix->fix_size < 8 |
11471 | && mp->fix_size >= 8) | |
5a9335ef NC |
11472 | { |
11473 | min_mp = mp; | |
11474 | min_address = mp->min_address + fix->fix_size; | |
11475 | } | |
d5b7b3ae RE |
11476 | } |
11477 | } | |
11478 | ||
11479 | /* We need to create a new entry. */ | |
5ed6ace5 | 11480 | mp = XNEW (Mnode); |
d5b7b3ae RE |
11481 | mp->fix_size = fix->fix_size; |
11482 | mp->mode = fix->mode; | |
11483 | mp->value = fix->value; | |
11484 | mp->refcount = 1; | |
11485 | mp->max_address = minipool_barrier->address + 65536; | |
11486 | ||
11487 | mp->min_address = min_address; | |
11488 | ||
11489 | if (min_mp == NULL) | |
11490 | { | |
11491 | mp->prev = NULL; | |
11492 | mp->next = minipool_vector_head; | |
11493 | ||
11494 | if (mp->next == NULL) | |
11495 | { | |
11496 | minipool_vector_tail = mp; | |
11497 | minipool_vector_label = gen_label_rtx (); | |
11498 | } | |
11499 | else | |
11500 | mp->next->prev = mp; | |
11501 | ||
11502 | minipool_vector_head = mp; | |
11503 | } | |
11504 | else | |
11505 | { | |
11506 | mp->next = min_mp->next; | |
11507 | mp->prev = min_mp; | |
11508 | min_mp->next = mp; | |
f676971a | 11509 | |
d5b7b3ae RE |
11510 | if (mp->next != NULL) |
11511 | mp->next->prev = mp; | |
11512 | else | |
11513 | minipool_vector_tail = mp; | |
11514 | } | |
11515 | ||
11516 | /* Save the new entry. */ | |
11517 | min_mp = mp; | |
11518 | ||
11519 | if (mp->prev) | |
11520 | mp = mp->prev; | |
11521 | else | |
11522 | mp->offset = 0; | |
11523 | ||
11524 | /* Scan over the following entries and adjust their offsets. */ | |
11525 | while (mp->next != NULL) | |
11526 | { | |
11527 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
11528 | mp->next->min_address = mp->min_address + mp->fix_size; | |
11529 | ||
11530 | if (mp->refcount) | |
11531 | mp->next->offset = mp->offset + mp->fix_size; | |
11532 | else | |
11533 | mp->next->offset = mp->offset; | |
11534 | ||
11535 | mp = mp->next; | |
11536 | } | |
11537 | ||
11538 | return min_mp; | |
11539 | } | |
11540 | ||
11541 | static void | |
e32bac5b | 11542 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
11543 | { |
11544 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 11545 | Mnode *mp; |
d5b7b3ae RE |
11546 | |
11547 | minipool_barrier = barrier; | |
11548 | ||
11549 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
11550 | { | |
11551 | mp->offset = offset; | |
f676971a | 11552 | |
d5b7b3ae RE |
11553 | if (mp->refcount > 0) |
11554 | offset += mp->fix_size; | |
11555 | } | |
11556 | } | |
11557 | ||
11558 | /* Output the literal table */ | |
11559 | static void | |
e32bac5b | 11560 | dump_minipool (rtx scan) |
d5b7b3ae | 11561 | { |
5a9335ef NC |
11562 | Mnode * mp; |
11563 | Mnode * nmp; | |
11564 | int align64 = 0; | |
11565 | ||
5848830f | 11566 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef | 11567 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
88f77cba | 11568 | if (mp->refcount > 0 && mp->fix_size >= 8) |
5a9335ef NC |
11569 | { |
11570 | align64 = 1; | |
11571 | break; | |
11572 | } | |
d5b7b3ae | 11573 | |
c263766c RH |
11574 | if (dump_file) |
11575 | fprintf (dump_file, | |
5a9335ef NC |
11576 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
11577 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
11578 | |
11579 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 11580 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
11581 | scan = emit_label_after (minipool_vector_label, scan); |
11582 | ||
11583 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
11584 | { | |
11585 | if (mp->refcount > 0) | |
11586 | { | |
c263766c | 11587 | if (dump_file) |
d5b7b3ae | 11588 | { |
f676971a | 11589 | fprintf (dump_file, |
d5b7b3ae RE |
11590 | ";; Offset %u, min %ld, max %ld ", |
11591 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
11592 | (unsigned long) mp->max_address); | |
c263766c RH |
11593 | arm_print_value (dump_file, mp->value); |
11594 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
11595 | } |
11596 | ||
11597 | switch (mp->fix_size) | |
11598 | { | |
11599 | #ifdef HAVE_consttable_1 | |
11600 | case 1: | |
11601 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
11602 | break; | |
11603 | ||
11604 | #endif | |
11605 | #ifdef HAVE_consttable_2 | |
11606 | case 2: | |
11607 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
11608 | break; | |
11609 | ||
11610 | #endif | |
11611 | #ifdef HAVE_consttable_4 | |
11612 | case 4: | |
11613 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
11614 | break; | |
11615 | ||
11616 | #endif | |
11617 | #ifdef HAVE_consttable_8 | |
11618 | case 8: | |
11619 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
11620 | break; | |
11621 | ||
88f77cba JB |
11622 | #endif |
11623 | #ifdef HAVE_consttable_16 | |
11624 | case 16: | |
11625 | scan = emit_insn_after (gen_consttable_16 (mp->value), scan); | |
11626 | break; | |
11627 | ||
d5b7b3ae RE |
11628 | #endif |
11629 | default: | |
e6d29d15 | 11630 | gcc_unreachable (); |
d5b7b3ae RE |
11631 | } |
11632 | } | |
11633 | ||
11634 | nmp = mp->next; | |
11635 | free (mp); | |
2b835d68 RE |
11636 | } |
11637 | ||
d5b7b3ae RE |
11638 | minipool_vector_head = minipool_vector_tail = NULL; |
11639 | scan = emit_insn_after (gen_consttable_end (), scan); | |
11640 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
11641 | } |
11642 | ||
d5b7b3ae RE |
11643 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
11644 | static int | |
e32bac5b | 11645 | arm_barrier_cost (rtx insn) |
949d79eb | 11646 | { |
d5b7b3ae RE |
11647 | /* Basing the location of the pool on the loop depth is preferable, |
11648 | but at the moment, the basic block information seems to be | |
11649 | corrupt by this stage of the compilation. */ | |
11650 | int base_cost = 50; | |
11651 | rtx next = next_nonnote_insn (insn); | |
11652 | ||
11653 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
11654 | base_cost -= 20; | |
11655 | ||
11656 | switch (GET_CODE (insn)) | |
11657 | { | |
11658 | case CODE_LABEL: | |
11659 | /* It will always be better to place the table before the label, rather | |
11660 | than after it. */ | |
f676971a | 11661 | return 50; |
949d79eb | 11662 | |
d5b7b3ae RE |
11663 | case INSN: |
11664 | case CALL_INSN: | |
11665 | return base_cost; | |
11666 | ||
11667 | case JUMP_INSN: | |
11668 | return base_cost - 10; | |
11669 | ||
11670 | default: | |
11671 | return base_cost + 10; | |
11672 | } | |
11673 | } | |
11674 | ||
11675 | /* Find the best place in the insn stream in the range | |
11676 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
11677 | Create the barrier by inserting a jump and add a new fix entry for | |
11678 | it. */ | |
11679 | static Mfix * | |
e32bac5b | 11680 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
11681 | { |
11682 | HOST_WIDE_INT count = 0; | |
11683 | rtx barrier; | |
11684 | rtx from = fix->insn; | |
7a7017bc PB |
11685 | /* The instruction after which we will insert the jump. */ |
11686 | rtx selected = NULL; | |
d5b7b3ae | 11687 | int selected_cost; |
7a7017bc | 11688 | /* The address at which the jump instruction will be placed. */ |
d5b7b3ae RE |
11689 | HOST_WIDE_INT selected_address; |
11690 | Mfix * new_fix; | |
11691 | HOST_WIDE_INT max_count = max_address - fix->address; | |
11692 | rtx label = gen_label_rtx (); | |
11693 | ||
11694 | selected_cost = arm_barrier_cost (from); | |
11695 | selected_address = fix->address; | |
11696 | ||
11697 | while (from && count < max_count) | |
11698 | { | |
11699 | rtx tmp; | |
11700 | int new_cost; | |
11701 | ||
11702 | /* This code shouldn't have been called if there was a natural barrier | |
11703 | within range. */ | |
e6d29d15 | 11704 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
11705 | |
11706 | /* Count the length of this insn. */ | |
11707 | count += get_attr_length (from); | |
11708 | ||
11709 | /* If there is a jump table, add its length. */ | |
11710 | tmp = is_jump_table (from); | |
11711 | if (tmp != NULL) | |
11712 | { | |
11713 | count += get_jump_table_size (tmp); | |
11714 | ||
11715 | /* Jump tables aren't in a basic block, so base the cost on | |
11716 | the dispatch insn. If we select this location, we will | |
11717 | still put the pool after the table. */ | |
11718 | new_cost = arm_barrier_cost (from); | |
11719 | ||
7a7017bc PB |
11720 | if (count < max_count |
11721 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
11722 | { |
11723 | selected = tmp; | |
11724 | selected_cost = new_cost; | |
11725 | selected_address = fix->address + count; | |
11726 | } | |
11727 | ||
11728 | /* Continue after the dispatch table. */ | |
11729 | from = NEXT_INSN (tmp); | |
11730 | continue; | |
11731 | } | |
11732 | ||
11733 | new_cost = arm_barrier_cost (from); | |
f676971a | 11734 | |
7a7017bc PB |
11735 | if (count < max_count |
11736 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
11737 | { |
11738 | selected = from; | |
11739 | selected_cost = new_cost; | |
11740 | selected_address = fix->address + count; | |
11741 | } | |
11742 | ||
11743 | from = NEXT_INSN (from); | |
11744 | } | |
11745 | ||
7a7017bc PB |
11746 | /* Make sure that we found a place to insert the jump. */ |
11747 | gcc_assert (selected); | |
11748 | ||
d5b7b3ae RE |
11749 | /* Create a new JUMP_INSN that branches around a barrier. */ |
11750 | from = emit_jump_insn_after (gen_jump (label), selected); | |
11751 | JUMP_LABEL (from) = label; | |
11752 | barrier = emit_barrier_after (from); | |
11753 | emit_label_after (label, barrier); | |
11754 | ||
11755 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 11756 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
11757 | new_fix->insn = barrier; |
11758 | new_fix->address = selected_address; | |
11759 | new_fix->next = fix->next; | |
11760 | fix->next = new_fix; | |
11761 | ||
11762 | return new_fix; | |
11763 | } | |
11764 | ||
11765 | /* Record that there is a natural barrier in the insn stream at | |
11766 | ADDRESS. */ | |
949d79eb | 11767 | static void |
e32bac5b | 11768 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 11769 | { |
c7319d87 | 11770 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 11771 | |
949d79eb RE |
11772 | fix->insn = insn; |
11773 | fix->address = address; | |
2b835d68 | 11774 | |
949d79eb RE |
11775 | fix->next = NULL; |
11776 | if (minipool_fix_head != NULL) | |
11777 | minipool_fix_tail->next = fix; | |
11778 | else | |
11779 | minipool_fix_head = fix; | |
11780 | ||
11781 | minipool_fix_tail = fix; | |
11782 | } | |
2b835d68 | 11783 | |
d5b7b3ae RE |
11784 | /* Record INSN, which will need fixing up to load a value from the |
11785 | minipool. ADDRESS is the offset of the insn since the start of the | |
11786 | function; LOC is a pointer to the part of the insn which requires | |
11787 | fixing; VALUE is the constant that must be loaded, which is of type | |
11788 | MODE. */ | |
949d79eb | 11789 | static void |
e32bac5b RE |
11790 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
11791 | enum machine_mode mode, rtx value) | |
949d79eb | 11792 | { |
c7319d87 | 11793 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb | 11794 | |
949d79eb RE |
11795 | fix->insn = insn; |
11796 | fix->address = address; | |
11797 | fix->loc = loc; | |
11798 | fix->mode = mode; | |
d5b7b3ae | 11799 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 11800 | fix->value = value; |
d5b7b3ae RE |
11801 | fix->forwards = get_attr_pool_range (insn); |
11802 | fix->backwards = get_attr_neg_pool_range (insn); | |
11803 | fix->minipool = NULL; | |
949d79eb RE |
11804 | |
11805 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 11806 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 11807 | to generate duff assembly code. */ |
e6d29d15 | 11808 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 11809 | |
34a9f549 PB |
11810 | /* If an entry requires 8-byte alignment then assume all constant pools |
11811 | require 4 bytes of padding. Trying to do this later on a per-pool | |
917f1b7e | 11812 | basis is awkward because existing pool entries have to be modified. */ |
88f77cba | 11813 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) |
34a9f549 | 11814 | minipool_pad = 4; |
5a9335ef | 11815 | |
c263766c | 11816 | if (dump_file) |
d5b7b3ae | 11817 | { |
c263766c | 11818 | fprintf (dump_file, |
d5b7b3ae RE |
11819 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
11820 | GET_MODE_NAME (mode), | |
f676971a | 11821 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 11822 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
11823 | arm_print_value (dump_file, fix->value); |
11824 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
11825 | } |
11826 | ||
6354dc9b | 11827 | /* Add it to the chain of fixes. */ |
949d79eb | 11828 | fix->next = NULL; |
f676971a | 11829 | |
949d79eb RE |
11830 | if (minipool_fix_head != NULL) |
11831 | minipool_fix_tail->next = fix; | |
11832 | else | |
11833 | minipool_fix_head = fix; | |
11834 | ||
11835 | minipool_fix_tail = fix; | |
11836 | } | |
11837 | ||
9b901d50 | 11838 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
11839 | Returns the number of insns needed, or 99 if we don't know how to |
11840 | do it. */ | |
11841 | int | |
11842 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 11843 | { |
9b901d50 RE |
11844 | rtx lowpart, highpart; |
11845 | enum machine_mode mode; | |
e0b92319 | 11846 | |
9b901d50 | 11847 | mode = GET_MODE (val); |
b9e8bfda | 11848 | |
9b901d50 RE |
11849 | if (mode == VOIDmode) |
11850 | mode = DImode; | |
11851 | ||
11852 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 11853 | |
9b901d50 RE |
11854 | lowpart = gen_lowpart (SImode, val); |
11855 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 11856 | |
9b901d50 RE |
11857 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
11858 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
11859 | ||
11860 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 11861 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 11862 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
11863 | NULL_RTX, NULL_RTX, 0, 0)); |
11864 | } | |
11865 | ||
f3b569ca | 11866 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
11867 | 32-bit operations. This is the case if optimizing for size, or |
11868 | if we have load delay slots, or if one 32-bit part can be done with | |
11869 | a single data operation. */ | |
11870 | bool | |
11871 | arm_const_double_by_parts (rtx val) | |
11872 | { | |
11873 | enum machine_mode mode = GET_MODE (val); | |
11874 | rtx part; | |
11875 | ||
11876 | if (optimize_size || arm_ld_sched) | |
11877 | return true; | |
11878 | ||
11879 | if (mode == VOIDmode) | |
11880 | mode = DImode; | |
e0b92319 | 11881 | |
b4a58f80 | 11882 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 11883 | |
b4a58f80 | 11884 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 11885 | |
b4a58f80 RE |
11886 | if (const_ok_for_arm (INTVAL (part)) |
11887 | || const_ok_for_arm (~INTVAL (part))) | |
11888 | return true; | |
e0b92319 | 11889 | |
b4a58f80 | 11890 | part = gen_lowpart (SImode, val); |
e0b92319 | 11891 | |
b4a58f80 | 11892 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 11893 | |
b4a58f80 RE |
11894 | if (const_ok_for_arm (INTVAL (part)) |
11895 | || const_ok_for_arm (~INTVAL (part))) | |
11896 | return true; | |
e0b92319 | 11897 | |
b4a58f80 RE |
11898 | return false; |
11899 | } | |
11900 | ||
73160ba9 DJ |
11901 | /* Return true if it is possible to inline both the high and low parts |
11902 | of a 64-bit constant into 32-bit data processing instructions. */ | |
11903 | bool | |
11904 | arm_const_double_by_immediates (rtx val) | |
11905 | { | |
11906 | enum machine_mode mode = GET_MODE (val); | |
11907 | rtx part; | |
11908 | ||
11909 | if (mode == VOIDmode) | |
11910 | mode = DImode; | |
11911 | ||
11912 | part = gen_highpart_mode (SImode, mode, val); | |
11913 | ||
11914 | gcc_assert (GET_CODE (part) == CONST_INT); | |
11915 | ||
11916 | if (!const_ok_for_arm (INTVAL (part))) | |
11917 | return false; | |
11918 | ||
11919 | part = gen_lowpart (SImode, val); | |
11920 | ||
11921 | gcc_assert (GET_CODE (part) == CONST_INT); | |
11922 | ||
11923 | if (!const_ok_for_arm (INTVAL (part))) | |
11924 | return false; | |
11925 | ||
11926 | return true; | |
11927 | } | |
11928 | ||
f0375c66 NC |
11929 | /* Scan INSN and note any of its operands that need fixing. |
11930 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 11931 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
11932 | This is used by arm_memory_load_p() which needs to know about loads |
11933 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 11934 | static bool |
e32bac5b | 11935 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 11936 | { |
f0375c66 | 11937 | bool result = false; |
949d79eb RE |
11938 | int opno; |
11939 | ||
d5b7b3ae | 11940 | extract_insn (insn); |
949d79eb | 11941 | |
5895f793 | 11942 | if (!constrain_operands (1)) |
949d79eb RE |
11943 | fatal_insn_not_found (insn); |
11944 | ||
8c2a5582 RE |
11945 | if (recog_data.n_alternatives == 0) |
11946 | return false; | |
11947 | ||
9b901d50 RE |
11948 | /* Fill in recog_op_alt with information about the constraints of |
11949 | this insn. */ | |
949d79eb RE |
11950 | preprocess_constraints (); |
11951 | ||
1ccbefce | 11952 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 11953 | { |
6354dc9b | 11954 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 11955 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
11956 | continue; |
11957 | ||
11958 | /* If this alternative is a memory reference, then any mention | |
11959 | of constants in this alternative is really to fool reload | |
11960 | into allowing us to accept one there. We need to fix them up | |
11961 | now so that we output the right code. */ | |
11962 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
11963 | { | |
1ccbefce | 11964 | rtx op = recog_data.operand[opno]; |
949d79eb | 11965 | |
9b901d50 | 11966 | if (CONSTANT_P (op)) |
f0375c66 NC |
11967 | { |
11968 | if (do_pushes) | |
11969 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
11970 | recog_data.operand_mode[opno], op); | |
11971 | result = true; | |
11972 | } | |
d5b7b3ae | 11973 | else if (GET_CODE (op) == MEM |
949d79eb RE |
11974 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
11975 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
11976 | { |
11977 | if (do_pushes) | |
244b1afb RE |
11978 | { |
11979 | rtx cop = avoid_constant_pool_reference (op); | |
11980 | ||
11981 | /* Casting the address of something to a mode narrower | |
11982 | than a word can cause avoid_constant_pool_reference() | |
11983 | to return the pool reference itself. That's no good to | |
f676971a | 11984 | us here. Lets just hope that we can use the |
244b1afb RE |
11985 | constant pool value directly. */ |
11986 | if (op == cop) | |
c769a35d | 11987 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
11988 | |
11989 | push_minipool_fix (insn, address, | |
11990 | recog_data.operand_loc[opno], | |
c769a35d | 11991 | recog_data.operand_mode[opno], cop); |
244b1afb | 11992 | } |
f0375c66 NC |
11993 | |
11994 | result = true; | |
11995 | } | |
949d79eb | 11996 | } |
2b835d68 | 11997 | } |
f0375c66 NC |
11998 | |
11999 | return result; | |
2b835d68 RE |
12000 | } |
12001 | ||
eef5973d BS |
12002 | /* Convert instructions to their cc-clobbering variant if possible, since |
12003 | that allows us to use smaller encodings. */ | |
12004 | ||
12005 | static void | |
12006 | thumb2_reorg (void) | |
12007 | { | |
12008 | basic_block bb; | |
12009 | regset_head live; | |
12010 | ||
12011 | INIT_REG_SET (&live); | |
12012 | ||
12013 | /* We are freeing block_for_insn in the toplev to keep compatibility | |
12014 | with old MDEP_REORGS that are not CFG based. Recompute it now. */ | |
12015 | compute_bb_for_insn (); | |
12016 | df_analyze (); | |
12017 | ||
12018 | FOR_EACH_BB (bb) | |
12019 | { | |
12020 | rtx insn; | |
12021 | COPY_REG_SET (&live, DF_LR_OUT (bb)); | |
12022 | df_simulate_initialize_backwards (bb, &live); | |
12023 | FOR_BB_INSNS_REVERSE (bb, insn) | |
12024 | { | |
12025 | if (NONJUMP_INSN_P (insn) | |
12026 | && !REGNO_REG_SET_P (&live, CC_REGNUM)) | |
12027 | { | |
12028 | rtx pat = PATTERN (insn); | |
12029 | if (GET_CODE (pat) == SET | |
12030 | && low_register_operand (XEXP (pat, 0), SImode) | |
12031 | && thumb_16bit_operator (XEXP (pat, 1), SImode) | |
12032 | && low_register_operand (XEXP (XEXP (pat, 1), 0), SImode) | |
12033 | && low_register_operand (XEXP (XEXP (pat, 1), 1), SImode)) | |
12034 | { | |
12035 | rtx dst = XEXP (pat, 0); | |
12036 | rtx src = XEXP (pat, 1); | |
12037 | rtx op0 = XEXP (src, 0); | |
eef5973d BS |
12038 | if (rtx_equal_p (dst, op0) |
12039 | || GET_CODE (src) == PLUS || GET_CODE (src) == MINUS) | |
12040 | { | |
12041 | rtx ccreg = gen_rtx_REG (CCmode, CC_REGNUM); | |
12042 | rtx clobber = gen_rtx_CLOBBER (VOIDmode, ccreg); | |
f63a6726 | 12043 | rtvec vec = gen_rtvec (2, pat, clobber); |
eef5973d BS |
12044 | PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); |
12045 | INSN_CODE (insn) = -1; | |
12046 | } | |
12047 | } | |
12048 | } | |
12049 | if (NONDEBUG_INSN_P (insn)) | |
12050 | df_simulate_one_insn_backwards (bb, insn, &live); | |
12051 | } | |
12052 | } | |
12053 | CLEAR_REG_SET (&live); | |
12054 | } | |
12055 | ||
18dbd950 RS |
12056 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
12057 | load addresses a limited distance around the pc. We do some | |
12058 | special munging to move the constant pool values to the correct | |
12059 | point in the code. */ | |
18dbd950 | 12060 | static void |
e32bac5b | 12061 | arm_reorg (void) |
2b835d68 RE |
12062 | { |
12063 | rtx insn; | |
d5b7b3ae RE |
12064 | HOST_WIDE_INT address = 0; |
12065 | Mfix * fix; | |
ad076f4e | 12066 | |
eef5973d BS |
12067 | if (TARGET_THUMB2) |
12068 | thumb2_reorg (); | |
12069 | ||
949d79eb | 12070 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 12071 | |
949d79eb RE |
12072 | /* The first insn must always be a note, or the code below won't |
12073 | scan it properly. */ | |
18dbd950 | 12074 | insn = get_insns (); |
e6d29d15 | 12075 | gcc_assert (GET_CODE (insn) == NOTE); |
34a9f549 | 12076 | minipool_pad = 0; |
949d79eb RE |
12077 | |
12078 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 12079 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 12080 | { |
9b6b54e2 | 12081 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 12082 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 12083 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 12084 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
12085 | cirrus_reorg (insn); |
12086 | ||
949d79eb | 12087 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 12088 | push_minipool_barrier (insn, address); |
f0375c66 | 12089 | else if (INSN_P (insn)) |
949d79eb RE |
12090 | { |
12091 | rtx table; | |
12092 | ||
f0375c66 | 12093 | note_invalid_constants (insn, address, true); |
949d79eb | 12094 | address += get_attr_length (insn); |
d5b7b3ae | 12095 | |
949d79eb RE |
12096 | /* If the insn is a vector jump, add the size of the table |
12097 | and skip the table. */ | |
d5b7b3ae | 12098 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 12099 | { |
d5b7b3ae | 12100 | address += get_jump_table_size (table); |
949d79eb RE |
12101 | insn = table; |
12102 | } | |
12103 | } | |
12104 | } | |
332072db | 12105 | |
d5b7b3ae | 12106 | fix = minipool_fix_head; |
f676971a | 12107 | |
949d79eb | 12108 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 12109 | while (fix) |
949d79eb | 12110 | { |
d5b7b3ae RE |
12111 | Mfix * ftmp; |
12112 | Mfix * fdel; | |
12113 | Mfix * last_added_fix; | |
12114 | Mfix * last_barrier = NULL; | |
12115 | Mfix * this_fix; | |
949d79eb RE |
12116 | |
12117 | /* Skip any further barriers before the next fix. */ | |
12118 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
12119 | fix = fix->next; | |
12120 | ||
d5b7b3ae | 12121 | /* No more fixes. */ |
949d79eb RE |
12122 | if (fix == NULL) |
12123 | break; | |
332072db | 12124 | |
d5b7b3ae | 12125 | last_added_fix = NULL; |
2b835d68 | 12126 | |
d5b7b3ae | 12127 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 12128 | { |
949d79eb | 12129 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 12130 | { |
d5b7b3ae RE |
12131 | if (ftmp->address >= minipool_vector_head->max_address) |
12132 | break; | |
2b835d68 | 12133 | |
d5b7b3ae | 12134 | last_barrier = ftmp; |
2b835d68 | 12135 | } |
d5b7b3ae RE |
12136 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
12137 | break; | |
12138 | ||
12139 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 12140 | } |
949d79eb | 12141 | |
d5b7b3ae RE |
12142 | /* If we found a barrier, drop back to that; any fixes that we |
12143 | could have reached but come after the barrier will now go in | |
12144 | the next mini-pool. */ | |
949d79eb RE |
12145 | if (last_barrier != NULL) |
12146 | { | |
f676971a | 12147 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
12148 | pool after all. */ |
12149 | for (fdel = last_barrier->next; | |
12150 | fdel && fdel != ftmp; | |
12151 | fdel = fdel->next) | |
12152 | { | |
12153 | fdel->minipool->refcount--; | |
12154 | fdel->minipool = NULL; | |
12155 | } | |
12156 | ||
949d79eb RE |
12157 | ftmp = last_barrier; |
12158 | } | |
12159 | else | |
2bfa88dc | 12160 | { |
d5b7b3ae RE |
12161 | /* ftmp is first fix that we can't fit into this pool and |
12162 | there no natural barriers that we could use. Insert a | |
12163 | new barrier in the code somewhere between the previous | |
12164 | fix and this one, and arrange to jump around it. */ | |
12165 | HOST_WIDE_INT max_address; | |
12166 | ||
12167 | /* The last item on the list of fixes must be a barrier, so | |
12168 | we can never run off the end of the list of fixes without | |
12169 | last_barrier being set. */ | |
e6d29d15 | 12170 | gcc_assert (ftmp); |
d5b7b3ae RE |
12171 | |
12172 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
12173 | /* Check that there isn't another fix that is in range that |
12174 | we couldn't fit into this pool because the pool was | |
12175 | already too large: we need to put the pool before such an | |
7a7017bc PB |
12176 | instruction. The pool itself may come just after the |
12177 | fix because create_fix_barrier also allows space for a | |
12178 | jump instruction. */ | |
d5b7b3ae | 12179 | if (ftmp->address < max_address) |
7a7017bc | 12180 | max_address = ftmp->address + 1; |
d5b7b3ae RE |
12181 | |
12182 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
12183 | } | |
12184 | ||
12185 | assign_minipool_offsets (last_barrier); | |
12186 | ||
12187 | while (ftmp) | |
12188 | { | |
12189 | if (GET_CODE (ftmp->insn) != BARRIER | |
12190 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
12191 | == NULL)) | |
12192 | break; | |
2bfa88dc | 12193 | |
d5b7b3ae | 12194 | ftmp = ftmp->next; |
2bfa88dc | 12195 | } |
949d79eb RE |
12196 | |
12197 | /* Scan over the fixes we have identified for this pool, fixing them | |
12198 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 12199 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
12200 | this_fix = this_fix->next) |
12201 | if (GET_CODE (this_fix->insn) != BARRIER) | |
12202 | { | |
949d79eb | 12203 | rtx addr |
f676971a | 12204 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 12205 | minipool_vector_label), |
d5b7b3ae | 12206 | this_fix->minipool->offset); |
949d79eb RE |
12207 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
12208 | } | |
12209 | ||
d5b7b3ae | 12210 | dump_minipool (last_barrier->insn); |
949d79eb | 12211 | fix = ftmp; |
2b835d68 | 12212 | } |
4b632bf1 | 12213 | |
949d79eb RE |
12214 | /* From now on we must synthesize any constants that we can't handle |
12215 | directly. This can happen if the RTL gets split during final | |
12216 | instruction generation. */ | |
4b632bf1 | 12217 | after_arm_reorg = 1; |
c7319d87 RE |
12218 | |
12219 | /* Free the minipool memory. */ | |
12220 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 12221 | } |
cce8749e CH |
12222 | \f |
12223 | /* Routines to output assembly language. */ | |
12224 | ||
f3bb6135 | 12225 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 12226 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 12227 | when cross compiling. */ |
cd2b33d0 | 12228 | const char * |
e32bac5b | 12229 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
12230 | { |
12231 | REAL_VALUE_TYPE r; | |
12232 | int i; | |
f676971a | 12233 | |
9b66ebb1 PB |
12234 | if (!fp_consts_inited) |
12235 | init_fp_table (); | |
f676971a | 12236 | |
ff9940b0 RE |
12237 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
12238 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
12239 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
12240 | return strings_fp[i]; | |
f3bb6135 | 12241 | |
e6d29d15 | 12242 | gcc_unreachable (); |
ff9940b0 RE |
12243 | } |
12244 | ||
9997d19d | 12245 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 12246 | static const char * |
e32bac5b | 12247 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
12248 | { |
12249 | int i; | |
12250 | ||
9b66ebb1 PB |
12251 | if (!fp_consts_inited) |
12252 | init_fp_table (); | |
9997d19d RE |
12253 | |
12254 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
12255 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
12256 | return strings_fp[i]; | |
9997d19d | 12257 | |
e6d29d15 | 12258 | gcc_unreachable (); |
9997d19d | 12259 | } |
ff9940b0 | 12260 | |
cce8749e CH |
12261 | /* Output the operands of a LDM/STM instruction to STREAM. |
12262 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 | 12263 | REG is the base register, either the frame pointer or the stack pointer, |
a15908a4 PB |
12264 | INSTR is the possibly suffixed load or store instruction. |
12265 | RFE is nonzero if the instruction should also copy spsr to cpsr. */ | |
b279b20a | 12266 | |
d5b7b3ae | 12267 | static void |
b279b20a | 12268 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
a15908a4 | 12269 | unsigned long mask, int rfe) |
cce8749e | 12270 | { |
b279b20a NC |
12271 | unsigned i; |
12272 | bool not_first = FALSE; | |
cce8749e | 12273 | |
a15908a4 | 12274 | gcc_assert (!rfe || (mask & (1 << PC_REGNUM))); |
1d5473cb | 12275 | fputc ('\t', stream); |
dd18ae56 | 12276 | asm_fprintf (stream, instr, reg); |
5b3e6663 | 12277 | fputc ('{', stream); |
f676971a | 12278 | |
d5b7b3ae | 12279 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
12280 | if (mask & (1 << i)) |
12281 | { | |
12282 | if (not_first) | |
12283 | fprintf (stream, ", "); | |
f676971a | 12284 | |
dd18ae56 | 12285 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
12286 | not_first = TRUE; |
12287 | } | |
f3bb6135 | 12288 | |
a15908a4 PB |
12289 | if (rfe) |
12290 | fprintf (stream, "}^\n"); | |
12291 | else | |
12292 | fprintf (stream, "}\n"); | |
f3bb6135 | 12293 | } |
cce8749e | 12294 | |
9b66ebb1 | 12295 | |
8edfc4cc | 12296 | /* Output a FLDMD instruction to STREAM. |
9728c9d1 PB |
12297 | BASE if the register containing the address. |
12298 | REG and COUNT specify the register range. | |
8edfc4cc MS |
12299 | Extra registers may be added to avoid hardware bugs. |
12300 | ||
12301 | We output FLDMD even for ARMv5 VFP implementations. Although | |
12302 | FLDMD is technically not supported until ARMv6, it is believed | |
12303 | that all VFP implementations support its use in this context. */ | |
9b66ebb1 PB |
12304 | |
12305 | static void | |
8edfc4cc | 12306 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
12307 | { |
12308 | int i; | |
12309 | ||
9728c9d1 PB |
12310 | /* Workaround ARM10 VFPr1 bug. */ |
12311 | if (count == 2 && !arm_arch6) | |
12312 | { | |
12313 | if (reg == 15) | |
12314 | reg--; | |
12315 | count++; | |
12316 | } | |
12317 | ||
f1adb0a9 JB |
12318 | /* FLDMD may not load more than 16 doubleword registers at a time. Split the |
12319 | load into multiple parts if we have to handle more than 16 registers. */ | |
12320 | if (count > 16) | |
12321 | { | |
12322 | vfp_output_fldmd (stream, base, reg, 16); | |
12323 | vfp_output_fldmd (stream, base, reg + 16, count - 16); | |
12324 | return; | |
12325 | } | |
12326 | ||
9b66ebb1 | 12327 | fputc ('\t', stream); |
8edfc4cc | 12328 | asm_fprintf (stream, "fldmfdd\t%r!, {", base); |
9b66ebb1 | 12329 | |
9728c9d1 | 12330 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 12331 | { |
9728c9d1 | 12332 | if (i > reg) |
9b66ebb1 | 12333 | fputs (", ", stream); |
9728c9d1 | 12334 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
12335 | } |
12336 | fputs ("}\n", stream); | |
9728c9d1 | 12337 | |
9b66ebb1 PB |
12338 | } |
12339 | ||
12340 | ||
12341 | /* Output the assembly for a store multiple. */ | |
12342 | ||
12343 | const char * | |
8edfc4cc | 12344 | vfp_output_fstmd (rtx * operands) |
9b66ebb1 PB |
12345 | { |
12346 | char pattern[100]; | |
12347 | int p; | |
12348 | int base; | |
12349 | int i; | |
12350 | ||
8edfc4cc | 12351 | strcpy (pattern, "fstmfdd\t%m0!, {%P1"); |
9b66ebb1 PB |
12352 | p = strlen (pattern); |
12353 | ||
e6d29d15 | 12354 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
12355 | |
12356 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
12357 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
12358 | { | |
12359 | p += sprintf (&pattern[p], ", d%d", base + i); | |
12360 | } | |
12361 | strcpy (&pattern[p], "}"); | |
12362 | ||
12363 | output_asm_insn (pattern, operands); | |
12364 | return ""; | |
12365 | } | |
12366 | ||
12367 | ||
9728c9d1 PB |
12368 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
12369 | number of bytes pushed. */ | |
9b66ebb1 | 12370 | |
9728c9d1 | 12371 | static int |
8edfc4cc | 12372 | vfp_emit_fstmd (int base_reg, int count) |
9b66ebb1 PB |
12373 | { |
12374 | rtx par; | |
12375 | rtx dwarf; | |
12376 | rtx tmp, reg; | |
12377 | int i; | |
12378 | ||
9728c9d1 PB |
12379 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
12380 | register pairs are stored by a store multiple insn. We avoid this | |
12381 | by pushing an extra pair. */ | |
12382 | if (count == 2 && !arm_arch6) | |
12383 | { | |
12384 | if (base_reg == LAST_VFP_REGNUM - 3) | |
12385 | base_reg -= 2; | |
12386 | count++; | |
12387 | } | |
12388 | ||
f1adb0a9 JB |
12389 | /* FSTMD may not store more than 16 doubleword registers at once. Split |
12390 | larger stores into multiple parts (up to a maximum of two, in | |
12391 | practice). */ | |
12392 | if (count > 16) | |
12393 | { | |
12394 | int saved; | |
12395 | /* NOTE: base_reg is an internal register number, so each D register | |
12396 | counts as 2. */ | |
12397 | saved = vfp_emit_fstmd (base_reg + 32, count - 16); | |
12398 | saved += vfp_emit_fstmd (base_reg, 16); | |
12399 | return saved; | |
12400 | } | |
12401 | ||
9b66ebb1 PB |
12402 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
12403 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
12404 | ||
12405 | reg = gen_rtx_REG (DFmode, base_reg); | |
12406 | base_reg += 2; | |
12407 | ||
12408 | XVECEXP (par, 0, 0) | |
12409 | = gen_rtx_SET (VOIDmode, | |
9abf5d7b RR |
12410 | gen_frame_mem |
12411 | (BLKmode, | |
12412 | gen_rtx_PRE_MODIFY (Pmode, | |
12413 | stack_pointer_rtx, | |
12414 | plus_constant | |
12415 | (stack_pointer_rtx, | |
12416 | - (count * 8))) | |
12417 | ), | |
9b66ebb1 PB |
12418 | gen_rtx_UNSPEC (BLKmode, |
12419 | gen_rtvec (1, reg), | |
12420 | UNSPEC_PUSH_MULT)); | |
12421 | ||
12422 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8edfc4cc | 12423 | plus_constant (stack_pointer_rtx, -(count * 8))); |
9b66ebb1 PB |
12424 | RTX_FRAME_RELATED_P (tmp) = 1; |
12425 | XVECEXP (dwarf, 0, 0) = tmp; | |
12426 | ||
12427 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12428 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
12429 | reg); |
12430 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12431 | XVECEXP (dwarf, 0, 1) = tmp; | |
12432 | ||
12433 | for (i = 1; i < count; i++) | |
12434 | { | |
12435 | reg = gen_rtx_REG (DFmode, base_reg); | |
12436 | base_reg += 2; | |
12437 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
12438 | ||
12439 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12440 | gen_frame_mem (DFmode, |
d66437c5 RE |
12441 | plus_constant (stack_pointer_rtx, |
12442 | i * 8)), | |
9b66ebb1 PB |
12443 | reg); |
12444 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12445 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
12446 | } | |
12447 | ||
12448 | par = emit_insn (par); | |
bbbbb16a | 12449 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
9728c9d1 PB |
12450 | RTX_FRAME_RELATED_P (par) = 1; |
12451 | ||
8edfc4cc | 12452 | return count * 8; |
9b66ebb1 PB |
12453 | } |
12454 | ||
9403b7f7 RS |
12455 | /* Emit a call instruction with pattern PAT. ADDR is the address of |
12456 | the call target. */ | |
12457 | ||
12458 | void | |
12459 | arm_emit_call_insn (rtx pat, rtx addr) | |
12460 | { | |
12461 | rtx insn; | |
12462 | ||
12463 | insn = emit_call_insn (pat); | |
12464 | ||
12465 | /* The PIC register is live on entry to VxWorks PIC PLT entries. | |
12466 | If the call might use such an entry, add a use of the PIC register | |
12467 | to the instruction's CALL_INSN_FUNCTION_USAGE. */ | |
12468 | if (TARGET_VXWORKS_RTP | |
12469 | && flag_pic | |
12470 | && GET_CODE (addr) == SYMBOL_REF | |
12471 | && (SYMBOL_REF_DECL (addr) | |
12472 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
12473 | : !SYMBOL_REF_LOCAL_P (addr))) | |
12474 | { | |
12475 | require_pic_register (); | |
12476 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); | |
12477 | } | |
12478 | } | |
9b66ebb1 | 12479 | |
6354dc9b | 12480 | /* Output a 'call' insn. */ |
cd2b33d0 | 12481 | const char * |
e32bac5b | 12482 | output_call (rtx *operands) |
cce8749e | 12483 | { |
e6d29d15 | 12484 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 12485 | |
68d560d4 | 12486 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 12487 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 12488 | { |
62b10bbc | 12489 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 12490 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 12491 | } |
f676971a | 12492 | |
1d5473cb | 12493 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 12494 | |
68d560d4 | 12495 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
12496 | output_asm_insn ("bx%?\t%0", operands); |
12497 | else | |
12498 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 12499 | |
f3bb6135 RE |
12500 | return ""; |
12501 | } | |
cce8749e | 12502 | |
0986ef45 JB |
12503 | /* Output a 'call' insn that is a reference in memory. This is |
12504 | disabled for ARMv5 and we prefer a blx instead because otherwise | |
12505 | there's a significant performance overhead. */ | |
cd2b33d0 | 12506 | const char * |
e32bac5b | 12507 | output_call_mem (rtx *operands) |
ff9940b0 | 12508 | { |
0986ef45 JB |
12509 | gcc_assert (!arm_arch5); |
12510 | if (TARGET_INTERWORK) | |
da6558fd NC |
12511 | { |
12512 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
12513 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
12514 | output_asm_insn ("bx%?\t%|ip", operands); | |
12515 | } | |
6ab5da80 RE |
12516 | else if (regno_use_in (LR_REGNUM, operands[0])) |
12517 | { | |
12518 | /* LR is used in the memory address. We load the address in the | |
12519 | first instruction. It's safe to use IP as the target of the | |
12520 | load since the call will kill it anyway. */ | |
12521 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
0986ef45 JB |
12522 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
12523 | if (arm_arch4t) | |
12524 | output_asm_insn ("bx%?\t%|ip", operands); | |
68d560d4 | 12525 | else |
0986ef45 | 12526 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); |
6ab5da80 | 12527 | } |
da6558fd NC |
12528 | else |
12529 | { | |
12530 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
12531 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
12532 | } | |
12533 | ||
f3bb6135 RE |
12534 | return ""; |
12535 | } | |
ff9940b0 RE |
12536 | |
12537 | ||
3b684012 RE |
12538 | /* Output a move from arm registers to an fpa registers. |
12539 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 12540 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 12541 | const char * |
e32bac5b | 12542 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
12543 | { |
12544 | int arm_reg0 = REGNO (operands[1]); | |
12545 | rtx ops[3]; | |
12546 | ||
e6d29d15 | 12547 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12548 | |
43cffd11 RE |
12549 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12550 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
12551 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 12552 | |
5b3e6663 | 12553 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
1d5473cb | 12554 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); |
f676971a | 12555 | |
f3bb6135 RE |
12556 | return ""; |
12557 | } | |
ff9940b0 | 12558 | |
3b684012 | 12559 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 12560 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 12561 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 12562 | const char * |
e32bac5b | 12563 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
12564 | { |
12565 | int arm_reg0 = REGNO (operands[0]); | |
12566 | rtx ops[3]; | |
12567 | ||
e6d29d15 | 12568 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12569 | |
43cffd11 RE |
12570 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12571 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
12572 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 12573 | |
1d5473cb | 12574 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
5b3e6663 | 12575 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
f3bb6135 RE |
12576 | return ""; |
12577 | } | |
ff9940b0 RE |
12578 | |
12579 | /* Output a move from arm registers to arm registers of a long double | |
12580 | OPERANDS[0] is the destination. | |
12581 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 12582 | const char * |
e32bac5b | 12583 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 12584 | { |
6354dc9b | 12585 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
12586 | int dest_start = REGNO (operands[0]); |
12587 | int src_start = REGNO (operands[1]); | |
12588 | rtx ops[2]; | |
12589 | int i; | |
12590 | ||
12591 | if (dest_start < src_start) | |
12592 | { | |
12593 | for (i = 0; i < 3; i++) | |
12594 | { | |
43cffd11 RE |
12595 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
12596 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 12597 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
12598 | } |
12599 | } | |
12600 | else | |
12601 | { | |
12602 | for (i = 2; i >= 0; i--) | |
12603 | { | |
43cffd11 RE |
12604 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
12605 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 12606 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
12607 | } |
12608 | } | |
f3bb6135 | 12609 | |
ff9940b0 RE |
12610 | return ""; |
12611 | } | |
12612 | ||
a552b644 RR |
12613 | void |
12614 | arm_emit_movpair (rtx dest, rtx src) | |
12615 | { | |
12616 | /* If the src is an immediate, simplify it. */ | |
12617 | if (CONST_INT_P (src)) | |
12618 | { | |
12619 | HOST_WIDE_INT val = INTVAL (src); | |
12620 | emit_set_insn (dest, GEN_INT (val & 0x0000ffff)); | |
12621 | if ((val >> 16) & 0x0000ffff) | |
12622 | emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16), | |
12623 | GEN_INT (16)), | |
12624 | GEN_INT ((val >> 16) & 0x0000ffff)); | |
12625 | return; | |
12626 | } | |
12627 | emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); | |
12628 | emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); | |
12629 | } | |
571191af | 12630 | |
3b684012 RE |
12631 | /* Output a move from arm registers to an fpa registers. |
12632 | OPERANDS[0] is an fpa register. | |
cce8749e | 12633 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 12634 | const char * |
e32bac5b | 12635 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
12636 | { |
12637 | int arm_reg0 = REGNO (operands[1]); | |
12638 | rtx ops[2]; | |
12639 | ||
e6d29d15 | 12640 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 12641 | |
43cffd11 RE |
12642 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12643 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
5b3e6663 | 12644 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops); |
1d5473cb | 12645 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); |
f3bb6135 RE |
12646 | return ""; |
12647 | } | |
cce8749e | 12648 | |
3b684012 | 12649 | /* Output a move from an fpa register to arm registers. |
cce8749e | 12650 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 12651 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 12652 | const char * |
e32bac5b | 12653 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
12654 | { |
12655 | int arm_reg0 = REGNO (operands[0]); | |
12656 | rtx ops[2]; | |
12657 | ||
e6d29d15 | 12658 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 12659 | |
43cffd11 RE |
12660 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
12661 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb | 12662 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
5b3e6663 | 12663 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops); |
f3bb6135 RE |
12664 | return ""; |
12665 | } | |
cce8749e CH |
12666 | |
12667 | /* Output a move between double words. | |
12668 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
12669 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 12670 | const char * |
e32bac5b | 12671 | output_move_double (rtx *operands) |
cce8749e CH |
12672 | { |
12673 | enum rtx_code code0 = GET_CODE (operands[0]); | |
12674 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 12675 | rtx otherops[3]; |
cce8749e CH |
12676 | |
12677 | if (code0 == REG) | |
12678 | { | |
f0b4bdd5 | 12679 | unsigned int reg0 = REGNO (operands[0]); |
cce8749e | 12680 | |
43cffd11 | 12681 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 12682 | |
e6d29d15 NS |
12683 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
12684 | ||
12685 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 12686 | { |
e6d29d15 | 12687 | case REG: |
5fd42423 PB |
12688 | if (TARGET_LDRD |
12689 | && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0)))) | |
5dea0c19 PB |
12690 | output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands); |
12691 | else | |
12692 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
e6d29d15 | 12693 | break; |
e0b92319 | 12694 | |
e6d29d15 NS |
12695 | case PRE_INC: |
12696 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 12697 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands); |
e6d29d15 | 12698 | break; |
e0b92319 | 12699 | |
e6d29d15 | 12700 | case PRE_DEC: |
5b3e6663 PB |
12701 | if (TARGET_LDRD) |
12702 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands); | |
12703 | else | |
12704 | output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands); | |
e6d29d15 | 12705 | break; |
e0b92319 | 12706 | |
e6d29d15 | 12707 | case POST_INC: |
5dea0c19 PB |
12708 | if (TARGET_LDRD) |
12709 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands); | |
12710 | else | |
12711 | output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands); | |
e6d29d15 | 12712 | break; |
e0b92319 | 12713 | |
e6d29d15 NS |
12714 | case POST_DEC: |
12715 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 12716 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands); |
e6d29d15 | 12717 | break; |
e0b92319 | 12718 | |
e6d29d15 NS |
12719 | case PRE_MODIFY: |
12720 | case POST_MODIFY: | |
5fd42423 PB |
12721 | /* Autoicrement addressing modes should never have overlapping |
12722 | base and destination registers, and overlapping index registers | |
12723 | are already prohibited, so this doesn't need to worry about | |
12724 | fix_cm3_ldrd. */ | |
e6d29d15 NS |
12725 | otherops[0] = operands[0]; |
12726 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
12727 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 12728 | |
e6d29d15 | 12729 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 12730 | { |
e6d29d15 | 12731 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 12732 | { |
e6d29d15 NS |
12733 | /* Registers overlap so split out the increment. */ |
12734 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
5b3e6663 | 12735 | output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops); |
fdd695fd PB |
12736 | } |
12737 | else | |
fe2d934b | 12738 | { |
ff128632 RE |
12739 | /* Use a single insn if we can. |
12740 | FIXME: IWMMXT allows offsets larger than ldrd can | |
12741 | handle, fix these up with a pair of ldr. */ | |
12742 | if (TARGET_THUMB2 | |
12743 | || GET_CODE (otherops[2]) != CONST_INT | |
12744 | || (INTVAL (otherops[2]) > -256 | |
12745 | && INTVAL (otherops[2]) < 256)) | |
12746 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops); | |
12747 | else | |
fe2d934b PB |
12748 | { |
12749 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 12750 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b | 12751 | } |
fe2d934b | 12752 | } |
e6d29d15 NS |
12753 | } |
12754 | else | |
12755 | { | |
ff128632 RE |
12756 | /* Use a single insn if we can. |
12757 | FIXME: IWMMXT allows offsets larger than ldrd can handle, | |
fe2d934b | 12758 | fix these up with a pair of ldr. */ |
ff128632 RE |
12759 | if (TARGET_THUMB2 |
12760 | || GET_CODE (otherops[2]) != CONST_INT | |
12761 | || (INTVAL (otherops[2]) > -256 | |
12762 | && INTVAL (otherops[2]) < 256)) | |
12763 | output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops); | |
12764 | else | |
fe2d934b | 12765 | { |
ff128632 | 12766 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
12767 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
12768 | } | |
e6d29d15 NS |
12769 | } |
12770 | break; | |
e0b92319 | 12771 | |
e6d29d15 NS |
12772 | case LABEL_REF: |
12773 | case CONST: | |
5dea0c19 PB |
12774 | /* We might be able to use ldrd %0, %1 here. However the range is |
12775 | different to ldr/adr, and it is broken on some ARMv7-M | |
12776 | implementations. */ | |
5fd42423 PB |
12777 | /* Use the second register of the pair to avoid problematic |
12778 | overlap. */ | |
12779 | otherops[1] = operands[1]; | |
12780 | output_asm_insn ("adr%?\t%0, %1", otherops); | |
12781 | operands[1] = otherops[0]; | |
5dea0c19 | 12782 | if (TARGET_LDRD) |
5fd42423 | 12783 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); |
5dea0c19 | 12784 | else |
5fd42423 | 12785 | output_asm_insn ("ldm%(ia%)\t%1, %M0", operands); |
e6d29d15 | 12786 | break; |
e0b92319 | 12787 | |
5b3e6663 | 12788 | /* ??? This needs checking for thumb2. */ |
e6d29d15 NS |
12789 | default: |
12790 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
12791 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
12792 | { | |
12793 | otherops[0] = operands[0]; | |
12794 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
12795 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 12796 | |
e6d29d15 | 12797 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 12798 | { |
5dea0c19 | 12799 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 12800 | { |
e6d29d15 | 12801 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 12802 | { |
e6d29d15 | 12803 | case -8: |
5b3e6663 | 12804 | output_asm_insn ("ldm%(db%)\t%1, %M0", otherops); |
e6d29d15 NS |
12805 | return ""; |
12806 | case -4: | |
5b3e6663 PB |
12807 | if (TARGET_THUMB2) |
12808 | break; | |
12809 | output_asm_insn ("ldm%(da%)\t%1, %M0", otherops); | |
e6d29d15 NS |
12810 | return ""; |
12811 | case 4: | |
5b3e6663 PB |
12812 | if (TARGET_THUMB2) |
12813 | break; | |
12814 | output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops); | |
e6d29d15 | 12815 | return ""; |
fdd695fd | 12816 | } |
e6d29d15 | 12817 | } |
5fd42423 PB |
12818 | otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); |
12819 | operands[1] = otherops[0]; | |
e6d29d15 NS |
12820 | if (TARGET_LDRD |
12821 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 12822 | || TARGET_THUMB2 |
e6d29d15 NS |
12823 | || (GET_CODE (otherops[2]) == CONST_INT |
12824 | && INTVAL (otherops[2]) > -256 | |
12825 | && INTVAL (otherops[2]) < 256))) | |
12826 | { | |
5fd42423 | 12827 | if (reg_overlap_mentioned_p (operands[0], |
e6d29d15 | 12828 | otherops[2])) |
fdd695fd | 12829 | { |
5fd42423 | 12830 | rtx tmp; |
e6d29d15 NS |
12831 | /* Swap base and index registers over to |
12832 | avoid a conflict. */ | |
5fd42423 PB |
12833 | tmp = otherops[1]; |
12834 | otherops[1] = otherops[2]; | |
12835 | otherops[2] = tmp; | |
fdd695fd | 12836 | } |
e6d29d15 NS |
12837 | /* If both registers conflict, it will usually |
12838 | have been fixed by a splitter. */ | |
5fd42423 PB |
12839 | if (reg_overlap_mentioned_p (operands[0], otherops[2]) |
12840 | || (fix_cm3_ldrd && reg0 == REGNO (otherops[1]))) | |
fdd695fd | 12841 | { |
5fd42423 PB |
12842 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
12843 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); | |
2b835d68 RE |
12844 | } |
12845 | else | |
5fd42423 PB |
12846 | { |
12847 | otherops[0] = operands[0]; | |
12848 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops); | |
12849 | } | |
e6d29d15 | 12850 | return ""; |
2b835d68 | 12851 | } |
e0b92319 | 12852 | |
e6d29d15 | 12853 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 12854 | { |
e6d29d15 NS |
12855 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
12856 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
12857 | else | |
12858 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
12859 | } |
12860 | else | |
e6d29d15 NS |
12861 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
12862 | } | |
12863 | else | |
12864 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
12865 | ||
5dea0c19 | 12866 | if (TARGET_LDRD) |
5fd42423 | 12867 | return "ldr%(d%)\t%0, [%1]"; |
5dea0c19 | 12868 | |
5fd42423 | 12869 | return "ldm%(ia%)\t%1, %M0"; |
e6d29d15 NS |
12870 | } |
12871 | else | |
12872 | { | |
12873 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
12874 | /* Take care of overlapping base/data reg. */ | |
12875 | if (reg_mentioned_p (operands[0], operands[1])) | |
12876 | { | |
12877 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
12878 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
12879 | } | |
12880 | else | |
12881 | { | |
12882 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
12883 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
12884 | } |
12885 | } | |
12886 | } | |
cce8749e | 12887 | } |
e6d29d15 | 12888 | else |
cce8749e | 12889 | { |
e6d29d15 NS |
12890 | /* Constraints should ensure this. */ |
12891 | gcc_assert (code0 == MEM && code1 == REG); | |
12892 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 12893 | |
ff9940b0 RE |
12894 | switch (GET_CODE (XEXP (operands[0], 0))) |
12895 | { | |
12896 | case REG: | |
5dea0c19 PB |
12897 | if (TARGET_LDRD) |
12898 | output_asm_insn ("str%(d%)\t%1, [%m0]", operands); | |
12899 | else | |
12900 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
ff9940b0 | 12901 | break; |
2b835d68 | 12902 | |
ff9940b0 | 12903 | case PRE_INC: |
e6d29d15 | 12904 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 12905 | output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands); |
ff9940b0 | 12906 | break; |
2b835d68 | 12907 | |
ff9940b0 | 12908 | case PRE_DEC: |
5b3e6663 PB |
12909 | if (TARGET_LDRD) |
12910 | output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands); | |
12911 | else | |
12912 | output_asm_insn ("stm%(db%)\t%m0!, %M1", operands); | |
ff9940b0 | 12913 | break; |
2b835d68 | 12914 | |
ff9940b0 | 12915 | case POST_INC: |
5dea0c19 PB |
12916 | if (TARGET_LDRD) |
12917 | output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands); | |
12918 | else | |
12919 | output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands); | |
ff9940b0 | 12920 | break; |
2b835d68 | 12921 | |
ff9940b0 | 12922 | case POST_DEC: |
e6d29d15 | 12923 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 12924 | output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands); |
fdd695fd PB |
12925 | break; |
12926 | ||
12927 | case PRE_MODIFY: | |
12928 | case POST_MODIFY: | |
12929 | otherops[0] = operands[1]; | |
12930 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
12931 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
12932 | ||
fe2d934b PB |
12933 | /* IWMMXT allows offsets larger than ldrd can handle, |
12934 | fix these up with a pair of ldr. */ | |
ff128632 RE |
12935 | if (!TARGET_THUMB2 |
12936 | && GET_CODE (otherops[2]) == CONST_INT | |
fe2d934b PB |
12937 | && (INTVAL(otherops[2]) <= -256 |
12938 | || INTVAL(otherops[2]) >= 256)) | |
12939 | { | |
fe2d934b PB |
12940 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) |
12941 | { | |
12942 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 12943 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
12944 | } |
12945 | else | |
12946 | { | |
ff128632 | 12947 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
12948 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
12949 | } | |
12950 | } | |
12951 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
5b3e6663 | 12952 | output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops); |
fdd695fd | 12953 | else |
5b3e6663 | 12954 | output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops); |
ff9940b0 | 12955 | break; |
2b835d68 RE |
12956 | |
12957 | case PLUS: | |
fdd695fd | 12958 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
5dea0c19 | 12959 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 12960 | { |
06bea5aa | 12961 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
12962 | { |
12963 | case -8: | |
5b3e6663 | 12964 | output_asm_insn ("stm%(db%)\t%m0, %M1", operands); |
2b835d68 RE |
12965 | return ""; |
12966 | ||
12967 | case -4: | |
5b3e6663 PB |
12968 | if (TARGET_THUMB2) |
12969 | break; | |
12970 | output_asm_insn ("stm%(da%)\t%m0, %M1", operands); | |
2b835d68 RE |
12971 | return ""; |
12972 | ||
12973 | case 4: | |
5b3e6663 PB |
12974 | if (TARGET_THUMB2) |
12975 | break; | |
12976 | output_asm_insn ("stm%(ib%)\t%m0, %M1", operands); | |
2b835d68 RE |
12977 | return ""; |
12978 | } | |
12979 | } | |
fdd695fd PB |
12980 | if (TARGET_LDRD |
12981 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 12982 | || TARGET_THUMB2 |
fdd695fd PB |
12983 | || (GET_CODE (otherops[2]) == CONST_INT |
12984 | && INTVAL (otherops[2]) > -256 | |
12985 | && INTVAL (otherops[2]) < 256))) | |
12986 | { | |
12987 | otherops[0] = operands[1]; | |
12988 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
5b3e6663 | 12989 | output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops); |
fdd695fd PB |
12990 | return ""; |
12991 | } | |
2b835d68 RE |
12992 | /* Fall through */ |
12993 | ||
ff9940b0 | 12994 | default: |
a4a37b30 | 12995 | otherops[0] = adjust_address (operands[0], SImode, 4); |
ff128632 | 12996 | otherops[1] = operands[1]; |
9997d19d | 12997 | output_asm_insn ("str%?\t%1, %0", operands); |
ff128632 | 12998 | output_asm_insn ("str%?\t%H1, %0", otherops); |
cce8749e CH |
12999 | } |
13000 | } | |
cce8749e | 13001 | |
9997d19d RE |
13002 | return ""; |
13003 | } | |
cce8749e | 13004 | |
88f77cba | 13005 | /* Output a move, load or store for quad-word vectors in ARM registers. Only |
dc34db56 | 13006 | handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */ |
5b3e6663 PB |
13007 | |
13008 | const char * | |
88f77cba | 13009 | output_move_quad (rtx *operands) |
5b3e6663 | 13010 | { |
88f77cba JB |
13011 | if (REG_P (operands[0])) |
13012 | { | |
13013 | /* Load, or reg->reg move. */ | |
5b3e6663 | 13014 | |
88f77cba JB |
13015 | if (MEM_P (operands[1])) |
13016 | { | |
13017 | switch (GET_CODE (XEXP (operands[1], 0))) | |
13018 | { | |
13019 | case REG: | |
13020 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
13021 | break; | |
13022 | ||
13023 | case LABEL_REF: | |
13024 | case CONST: | |
13025 | output_asm_insn ("adr%?\t%0, %1", operands); | |
13026 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
13027 | break; | |
13028 | ||
13029 | default: | |
13030 | gcc_unreachable (); | |
13031 | } | |
13032 | } | |
13033 | else | |
13034 | { | |
13035 | rtx ops[2]; | |
13036 | int dest, src, i; | |
5b3e6663 | 13037 | |
88f77cba | 13038 | gcc_assert (REG_P (operands[1])); |
5b3e6663 | 13039 | |
88f77cba JB |
13040 | dest = REGNO (operands[0]); |
13041 | src = REGNO (operands[1]); | |
5b3e6663 | 13042 | |
88f77cba JB |
13043 | /* This seems pretty dumb, but hopefully GCC won't try to do it |
13044 | very often. */ | |
13045 | if (dest < src) | |
13046 | for (i = 0; i < 4; i++) | |
13047 | { | |
13048 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
13049 | ops[1] = gen_rtx_REG (SImode, src + i); | |
13050 | output_asm_insn ("mov%?\t%0, %1", ops); | |
13051 | } | |
13052 | else | |
13053 | for (i = 3; i >= 0; i--) | |
13054 | { | |
13055 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
13056 | ops[1] = gen_rtx_REG (SImode, src + i); | |
13057 | output_asm_insn ("mov%?\t%0, %1", ops); | |
13058 | } | |
13059 | } | |
13060 | } | |
13061 | else | |
13062 | { | |
13063 | gcc_assert (MEM_P (operands[0])); | |
13064 | gcc_assert (REG_P (operands[1])); | |
13065 | gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); | |
13066 | ||
13067 | switch (GET_CODE (XEXP (operands[0], 0))) | |
13068 | { | |
13069 | case REG: | |
13070 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
13071 | break; | |
13072 | ||
13073 | default: | |
13074 | gcc_unreachable (); | |
13075 | } | |
13076 | } | |
13077 | ||
13078 | return ""; | |
13079 | } | |
13080 | ||
13081 | /* Output a VFP load or store instruction. */ | |
13082 | ||
13083 | const char * | |
13084 | output_move_vfp (rtx *operands) | |
13085 | { | |
13086 | rtx reg, mem, addr, ops[2]; | |
13087 | int load = REG_P (operands[0]); | |
13088 | int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; | |
13089 | int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; | |
0a2aaacc | 13090 | const char *templ; |
88f77cba JB |
13091 | char buff[50]; |
13092 | enum machine_mode mode; | |
13093 | ||
13094 | reg = operands[!load]; | |
13095 | mem = operands[load]; | |
13096 | ||
13097 | mode = GET_MODE (reg); | |
13098 | ||
13099 | gcc_assert (REG_P (reg)); | |
13100 | gcc_assert (IS_VFP_REGNUM (REGNO (reg))); | |
13101 | gcc_assert (mode == SFmode | |
13102 | || mode == DFmode | |
13103 | || mode == SImode | |
13104 | || mode == DImode | |
13105 | || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); | |
13106 | gcc_assert (MEM_P (mem)); | |
13107 | ||
13108 | addr = XEXP (mem, 0); | |
13109 | ||
13110 | switch (GET_CODE (addr)) | |
13111 | { | |
13112 | case PRE_DEC: | |
0a2aaacc | 13113 | templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; |
88f77cba JB |
13114 | ops[0] = XEXP (addr, 0); |
13115 | ops[1] = reg; | |
5b3e6663 PB |
13116 | break; |
13117 | ||
13118 | case POST_INC: | |
0a2aaacc | 13119 | templ = "f%smia%c%%?\t%%0!, {%%%s1}%s"; |
5b3e6663 PB |
13120 | ops[0] = XEXP (addr, 0); |
13121 | ops[1] = reg; | |
13122 | break; | |
13123 | ||
13124 | default: | |
0a2aaacc | 13125 | templ = "f%s%c%%?\t%%%s0, %%1%s"; |
5b3e6663 PB |
13126 | ops[0] = reg; |
13127 | ops[1] = mem; | |
13128 | break; | |
13129 | } | |
13130 | ||
0a2aaacc | 13131 | sprintf (buff, templ, |
5b3e6663 PB |
13132 | load ? "ld" : "st", |
13133 | dp ? 'd' : 's', | |
13134 | dp ? "P" : "", | |
13135 | integer_p ? "\t%@ int" : ""); | |
13136 | output_asm_insn (buff, ops); | |
13137 | ||
13138 | return ""; | |
13139 | } | |
13140 | ||
88f77cba | 13141 | /* Output a Neon quad-word load or store, or a load or store for |
874d42b9 | 13142 | larger structure modes. |
88f77cba | 13143 | |
874d42b9 JM |
13144 | WARNING: The ordering of elements is weird in big-endian mode, |
13145 | because we use VSTM, as required by the EABI. GCC RTL defines | |
13146 | element ordering based on in-memory order. This can be differ | |
13147 | from the architectural ordering of elements within a NEON register. | |
13148 | The intrinsics defined in arm_neon.h use the NEON register element | |
13149 | ordering, not the GCC RTL element ordering. | |
88f77cba | 13150 | |
874d42b9 JM |
13151 | For example, the in-memory ordering of a big-endian a quadword |
13152 | vector with 16-bit elements when stored from register pair {d0,d1} | |
13153 | will be (lowest address first, d0[N] is NEON register element N): | |
88f77cba | 13154 | |
874d42b9 | 13155 | [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]] |
88f77cba | 13156 | |
874d42b9 JM |
13157 | When necessary, quadword registers (dN, dN+1) are moved to ARM |
13158 | registers from rN in the order: | |
88f77cba JB |
13159 | |
13160 | dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) | |
13161 | ||
874d42b9 JM |
13162 | So that STM/LDM can be used on vectors in ARM registers, and the |
13163 | same memory layout will result as if VSTM/VLDM were used. */ | |
88f77cba JB |
13164 | |
13165 | const char * | |
13166 | output_move_neon (rtx *operands) | |
13167 | { | |
13168 | rtx reg, mem, addr, ops[2]; | |
13169 | int regno, load = REG_P (operands[0]); | |
0a2aaacc | 13170 | const char *templ; |
88f77cba JB |
13171 | char buff[50]; |
13172 | enum machine_mode mode; | |
13173 | ||
13174 | reg = operands[!load]; | |
13175 | mem = operands[load]; | |
13176 | ||
13177 | mode = GET_MODE (reg); | |
13178 | ||
13179 | gcc_assert (REG_P (reg)); | |
13180 | regno = REGNO (reg); | |
13181 | gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) | |
13182 | || NEON_REGNO_OK_FOR_QUAD (regno)); | |
13183 | gcc_assert (VALID_NEON_DREG_MODE (mode) | |
13184 | || VALID_NEON_QREG_MODE (mode) | |
13185 | || VALID_NEON_STRUCT_MODE (mode)); | |
13186 | gcc_assert (MEM_P (mem)); | |
13187 | ||
13188 | addr = XEXP (mem, 0); | |
13189 | ||
13190 | /* Strip off const from addresses like (const (plus (...))). */ | |
13191 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
13192 | addr = XEXP (addr, 0); | |
13193 | ||
13194 | switch (GET_CODE (addr)) | |
13195 | { | |
13196 | case POST_INC: | |
0a2aaacc | 13197 | templ = "v%smia%%?\t%%0!, %%h1"; |
88f77cba JB |
13198 | ops[0] = XEXP (addr, 0); |
13199 | ops[1] = reg; | |
13200 | break; | |
13201 | ||
dc34db56 PB |
13202 | case PRE_DEC: |
13203 | /* FIXME: We should be using vld1/vst1 here in BE mode? */ | |
13204 | templ = "v%smdb%%?\t%%0!, %%h1"; | |
13205 | ops[0] = XEXP (addr, 0); | |
13206 | ops[1] = reg; | |
13207 | break; | |
13208 | ||
88f77cba JB |
13209 | case POST_MODIFY: |
13210 | /* FIXME: Not currently enabled in neon_vector_mem_operand. */ | |
13211 | gcc_unreachable (); | |
13212 | ||
13213 | case LABEL_REF: | |
13214 | case PLUS: | |
13215 | { | |
13216 | int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
13217 | int i; | |
13218 | int overlap = -1; | |
13219 | for (i = 0; i < nregs; i++) | |
13220 | { | |
13221 | /* We're only using DImode here because it's a convenient size. */ | |
13222 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); | |
5728868b | 13223 | ops[1] = adjust_address (mem, DImode, 8 * i); |
88f77cba JB |
13224 | if (reg_overlap_mentioned_p (ops[0], mem)) |
13225 | { | |
13226 | gcc_assert (overlap == -1); | |
13227 | overlap = i; | |
13228 | } | |
13229 | else | |
13230 | { | |
13231 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
13232 | output_asm_insn (buff, ops); | |
13233 | } | |
13234 | } | |
13235 | if (overlap != -1) | |
13236 | { | |
13237 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); | |
13238 | ops[1] = adjust_address (mem, SImode, 8 * overlap); | |
13239 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
13240 | output_asm_insn (buff, ops); | |
13241 | } | |
13242 | ||
13243 | return ""; | |
13244 | } | |
13245 | ||
13246 | default: | |
0a2aaacc | 13247 | templ = "v%smia%%?\t%%m0, %%h1"; |
88f77cba JB |
13248 | ops[0] = mem; |
13249 | ops[1] = reg; | |
13250 | } | |
13251 | ||
0a2aaacc | 13252 | sprintf (buff, templ, load ? "ld" : "st"); |
88f77cba JB |
13253 | output_asm_insn (buff, ops); |
13254 | ||
13255 | return ""; | |
13256 | } | |
13257 | ||
7c4f0041 JZ |
13258 | /* Compute and return the length of neon_mov<mode>, where <mode> is |
13259 | one of VSTRUCT modes: EI, OI, CI or XI. */ | |
13260 | int | |
13261 | arm_attr_length_move_neon (rtx insn) | |
13262 | { | |
13263 | rtx reg, mem, addr; | |
e4dde839 | 13264 | int load; |
7c4f0041 JZ |
13265 | enum machine_mode mode; |
13266 | ||
13267 | extract_insn_cached (insn); | |
13268 | ||
13269 | if (REG_P (recog_data.operand[0]) && REG_P (recog_data.operand[1])) | |
13270 | { | |
13271 | mode = GET_MODE (recog_data.operand[0]); | |
13272 | switch (mode) | |
13273 | { | |
13274 | case EImode: | |
13275 | case OImode: | |
13276 | return 8; | |
13277 | case CImode: | |
13278 | return 12; | |
13279 | case XImode: | |
13280 | return 16; | |
13281 | default: | |
13282 | gcc_unreachable (); | |
13283 | } | |
13284 | } | |
13285 | ||
13286 | load = REG_P (recog_data.operand[0]); | |
13287 | reg = recog_data.operand[!load]; | |
13288 | mem = recog_data.operand[load]; | |
13289 | ||
13290 | gcc_assert (MEM_P (mem)); | |
13291 | ||
13292 | mode = GET_MODE (reg); | |
7c4f0041 JZ |
13293 | addr = XEXP (mem, 0); |
13294 | ||
13295 | /* Strip off const from addresses like (const (plus (...))). */ | |
13296 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
13297 | addr = XEXP (addr, 0); | |
13298 | ||
13299 | if (GET_CODE (addr) == LABEL_REF || GET_CODE (addr) == PLUS) | |
13300 | { | |
13301 | int insns = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
13302 | return insns * 4; | |
13303 | } | |
13304 | else | |
13305 | return 4; | |
13306 | } | |
13307 | ||
1d6e90ac NC |
13308 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
13309 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 13310 | const char * |
e32bac5b | 13311 | output_add_immediate (rtx *operands) |
cce8749e | 13312 | { |
f3bb6135 | 13313 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
13314 | |
13315 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
13316 | { | |
13317 | if (n < 0) | |
13318 | output_multi_immediate (operands, | |
9997d19d RE |
13319 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
13320 | -n); | |
cce8749e CH |
13321 | else |
13322 | output_multi_immediate (operands, | |
9997d19d RE |
13323 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
13324 | n); | |
cce8749e | 13325 | } |
f3bb6135 RE |
13326 | |
13327 | return ""; | |
13328 | } | |
cce8749e | 13329 | |
cce8749e CH |
13330 | /* Output a multiple immediate operation. |
13331 | OPERANDS is the vector of operands referred to in the output patterns. | |
13332 | INSTR1 is the output pattern to use for the first constant. | |
13333 | INSTR2 is the output pattern to use for subsequent constants. | |
13334 | IMMED_OP is the index of the constant slot in OPERANDS. | |
13335 | N is the constant value. */ | |
cd2b33d0 | 13336 | static const char * |
e32bac5b RE |
13337 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
13338 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 13339 | { |
f3bb6135 | 13340 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 13341 | n &= 0xffffffff; |
f3bb6135 RE |
13342 | #endif |
13343 | ||
cce8749e CH |
13344 | if (n == 0) |
13345 | { | |
1d6e90ac | 13346 | /* Quick and easy output. */ |
cce8749e | 13347 | operands[immed_op] = const0_rtx; |
1d6e90ac | 13348 | output_asm_insn (instr1, operands); |
cce8749e CH |
13349 | } |
13350 | else | |
13351 | { | |
13352 | int i; | |
cd2b33d0 | 13353 | const char * instr = instr1; |
cce8749e | 13354 | |
6354dc9b | 13355 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
13356 | for (i = 0; i < 32; i += 2) |
13357 | { | |
13358 | if (n & (3 << i)) | |
13359 | { | |
f3bb6135 RE |
13360 | operands[immed_op] = GEN_INT (n & (255 << i)); |
13361 | output_asm_insn (instr, operands); | |
cce8749e CH |
13362 | instr = instr2; |
13363 | i += 6; | |
13364 | } | |
13365 | } | |
13366 | } | |
f676971a | 13367 | |
f3bb6135 | 13368 | return ""; |
9997d19d | 13369 | } |
cce8749e | 13370 | |
5b3e6663 PB |
13371 | /* Return the name of a shifter operation. */ |
13372 | static const char * | |
13373 | arm_shift_nmem(enum rtx_code code) | |
13374 | { | |
13375 | switch (code) | |
13376 | { | |
13377 | case ASHIFT: | |
13378 | return ARM_LSL_NAME; | |
13379 | ||
13380 | case ASHIFTRT: | |
13381 | return "asr"; | |
13382 | ||
13383 | case LSHIFTRT: | |
13384 | return "lsr"; | |
13385 | ||
13386 | case ROTATERT: | |
13387 | return "ror"; | |
13388 | ||
13389 | default: | |
13390 | abort(); | |
13391 | } | |
13392 | } | |
13393 | ||
cce8749e CH |
13394 | /* Return the appropriate ARM instruction for the operation code. |
13395 | The returned result should not be overwritten. OP is the rtx of the | |
13396 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
13397 | was shifted. */ | |
cd2b33d0 | 13398 | const char * |
e32bac5b | 13399 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 13400 | { |
9997d19d | 13401 | switch (GET_CODE (op)) |
cce8749e CH |
13402 | { |
13403 | case PLUS: | |
f3bb6135 RE |
13404 | return "add"; |
13405 | ||
cce8749e | 13406 | case MINUS: |
f3bb6135 RE |
13407 | return shift_first_arg ? "rsb" : "sub"; |
13408 | ||
cce8749e | 13409 | case IOR: |
f3bb6135 RE |
13410 | return "orr"; |
13411 | ||
cce8749e | 13412 | case XOR: |
f3bb6135 RE |
13413 | return "eor"; |
13414 | ||
cce8749e | 13415 | case AND: |
f3bb6135 RE |
13416 | return "and"; |
13417 | ||
5b3e6663 PB |
13418 | case ASHIFT: |
13419 | case ASHIFTRT: | |
13420 | case LSHIFTRT: | |
13421 | case ROTATERT: | |
13422 | return arm_shift_nmem(GET_CODE(op)); | |
13423 | ||
cce8749e | 13424 | default: |
e6d29d15 | 13425 | gcc_unreachable (); |
cce8749e | 13426 | } |
f3bb6135 | 13427 | } |
cce8749e | 13428 | |
cce8749e CH |
13429 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
13430 | for the operation code. The returned result should not be overwritten. | |
13431 | OP is the rtx code of the shift. | |
9997d19d | 13432 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 13433 | shift. */ |
cd2b33d0 | 13434 | static const char * |
e32bac5b | 13435 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 13436 | { |
cd2b33d0 | 13437 | const char * mnem; |
e2c671ba | 13438 | enum rtx_code code = GET_CODE (op); |
cce8749e | 13439 | |
e6d29d15 NS |
13440 | switch (GET_CODE (XEXP (op, 1))) |
13441 | { | |
13442 | case REG: | |
13443 | case SUBREG: | |
13444 | *amountp = -1; | |
13445 | break; | |
13446 | ||
13447 | case CONST_INT: | |
13448 | *amountp = INTVAL (XEXP (op, 1)); | |
13449 | break; | |
13450 | ||
13451 | default: | |
13452 | gcc_unreachable (); | |
13453 | } | |
9997d19d | 13454 | |
e2c671ba | 13455 | switch (code) |
cce8749e | 13456 | { |
a657c98a | 13457 | case ROTATE: |
e6d29d15 | 13458 | gcc_assert (*amountp != -1); |
a657c98a | 13459 | *amountp = 32 - *amountp; |
5b3e6663 | 13460 | code = ROTATERT; |
a657c98a RE |
13461 | |
13462 | /* Fall through. */ | |
13463 | ||
5b3e6663 PB |
13464 | case ASHIFT: |
13465 | case ASHIFTRT: | |
13466 | case LSHIFTRT: | |
9997d19d | 13467 | case ROTATERT: |
5b3e6663 | 13468 | mnem = arm_shift_nmem(code); |
9997d19d RE |
13469 | break; |
13470 | ||
ff9940b0 | 13471 | case MULT: |
e2c671ba RE |
13472 | /* We never have to worry about the amount being other than a |
13473 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
13474 | gcc_assert (*amountp != -1); |
13475 | *amountp = int_log2 (*amountp); | |
5b3e6663 | 13476 | return ARM_LSL_NAME; |
f3bb6135 | 13477 | |
cce8749e | 13478 | default: |
e6d29d15 | 13479 | gcc_unreachable (); |
cce8749e CH |
13480 | } |
13481 | ||
e2c671ba RE |
13482 | if (*amountp != -1) |
13483 | { | |
13484 | /* This is not 100% correct, but follows from the desire to merge | |
13485 | multiplication by a power of 2 with the recognizer for a | |
5b3e6663 | 13486 | shift. >=32 is not a valid shift for "lsl", so we must try and |
e2c671ba | 13487 | output a shift that produces the correct arithmetical result. |
ddd5a7c1 | 13488 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 13489 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
13490 | carry bit from such an operation, so we can ignore that. */ |
13491 | if (code == ROTATERT) | |
1d6e90ac NC |
13492 | /* Rotate is just modulo 32. */ |
13493 | *amountp &= 31; | |
e2c671ba RE |
13494 | else if (*amountp != (*amountp & 31)) |
13495 | { | |
13496 | if (code == ASHIFT) | |
13497 | mnem = "lsr"; | |
13498 | *amountp = 32; | |
13499 | } | |
13500 | ||
13501 | /* Shifts of 0 are no-ops. */ | |
13502 | if (*amountp == 0) | |
13503 | return NULL; | |
f676971a | 13504 | } |
e2c671ba | 13505 | |
9997d19d RE |
13506 | return mnem; |
13507 | } | |
cce8749e | 13508 | |
6354dc9b | 13509 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 13510 | |
18af7313 | 13511 | static HOST_WIDE_INT |
e32bac5b | 13512 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 13513 | { |
f3bb6135 | 13514 | HOST_WIDE_INT shift = 0; |
cce8749e | 13515 | |
30cf4896 | 13516 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 13517 | { |
e6d29d15 | 13518 | gcc_assert (shift <= 31); |
e32bac5b | 13519 | shift++; |
cce8749e | 13520 | } |
f3bb6135 RE |
13521 | |
13522 | return shift; | |
13523 | } | |
cce8749e | 13524 | |
c5ff069d ZW |
13525 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
13526 | because /bin/as is horribly restrictive. The judgement about | |
13527 | whether or not each character is 'printable' (and can be output as | |
13528 | is) or not (and must be printed with an octal escape) must be made | |
13529 | with reference to the *host* character set -- the situation is | |
13530 | similar to that discussed in the comments above pp_c_char in | |
13531 | c-pretty-print.c. */ | |
13532 | ||
6cfc7210 | 13533 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
13534 | |
13535 | void | |
e32bac5b | 13536 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
13537 | { |
13538 | int i; | |
6cfc7210 | 13539 | int len_so_far = 0; |
cce8749e | 13540 | |
6cfc7210 | 13541 | fputs ("\t.ascii\t\"", stream); |
f676971a | 13542 | |
cce8749e CH |
13543 | for (i = 0; i < len; i++) |
13544 | { | |
1d6e90ac | 13545 | int c = p[i]; |
cce8749e | 13546 | |
6cfc7210 | 13547 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 13548 | { |
6cfc7210 | 13549 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 13550 | len_so_far = 0; |
cce8749e CH |
13551 | } |
13552 | ||
c5ff069d | 13553 | if (ISPRINT (c)) |
cce8749e | 13554 | { |
c5ff069d | 13555 | if (c == '\\' || c == '\"') |
6cfc7210 | 13556 | { |
c5ff069d | 13557 | putc ('\\', stream); |
5895f793 | 13558 | len_so_far++; |
6cfc7210 | 13559 | } |
c5ff069d ZW |
13560 | putc (c, stream); |
13561 | len_so_far++; | |
13562 | } | |
13563 | else | |
13564 | { | |
13565 | fprintf (stream, "\\%03o", c); | |
13566 | len_so_far += 4; | |
cce8749e | 13567 | } |
cce8749e | 13568 | } |
f3bb6135 | 13569 | |
cce8749e | 13570 | fputs ("\"\n", stream); |
f3bb6135 | 13571 | } |
cce8749e | 13572 | \f |
c9ca9b88 | 13573 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 13574 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 13575 | |
6d3d9133 | 13576 | static unsigned long |
e32bac5b | 13577 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 13578 | { |
121308d4 | 13579 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 13580 | unsigned long save_reg_mask = 0; |
6d3d9133 | 13581 | unsigned int reg; |
6d3d9133 | 13582 | |
7b8b8ade | 13583 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 13584 | { |
7b8b8ade | 13585 | unsigned int max_reg; |
7b8b8ade NC |
13586 | /* Interrupt functions must not corrupt any registers, |
13587 | even call clobbered ones. If this is a leaf function | |
13588 | we can just examine the registers used by the RTL, but | |
13589 | otherwise we have to assume that whatever function is | |
13590 | called might clobber anything, and so we have to save | |
13591 | all the call-clobbered registers as well. */ | |
13592 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
13593 | /* FIQ handlers have registers r8 - r12 banked, so | |
13594 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 13595 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
13596 | r13 is the stack pointer which is always preserved, |
13597 | so we do not need to consider it here. */ | |
13598 | max_reg = 7; | |
13599 | else | |
13600 | max_reg = 12; | |
f676971a | 13601 | |
7b8b8ade | 13602 | for (reg = 0; reg <= max_reg; reg++) |
6fb5fa3c DB |
13603 | if (df_regs_ever_live_p (reg) |
13604 | || (! current_function_is_leaf && call_used_regs[reg])) | |
6d3d9133 | 13605 | save_reg_mask |= (1 << reg); |
cfa01aab | 13606 | |
286d28c3 | 13607 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
13608 | if (flag_pic |
13609 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 13610 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 13611 | && crtl->uses_pic_offset_table) |
cfa01aab | 13612 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
6d3d9133 | 13613 | } |
1586899e PB |
13614 | else if (IS_VOLATILE(func_type)) |
13615 | { | |
13616 | /* For noreturn functions we historically omitted register saves | |
13617 | altogether. However this really messes up debugging. As a | |
3ed04dbd | 13618 | compromise save just the frame pointers. Combined with the link |
1586899e PB |
13619 | register saved elsewhere this should be sufficient to get |
13620 | a backtrace. */ | |
13621 | if (frame_pointer_needed) | |
13622 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
13623 | if (df_regs_ever_live_p (ARM_HARD_FRAME_POINTER_REGNUM)) | |
13624 | save_reg_mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
13625 | if (df_regs_ever_live_p (THUMB_HARD_FRAME_POINTER_REGNUM)) | |
13626 | save_reg_mask |= 1 << THUMB_HARD_FRAME_POINTER_REGNUM; | |
13627 | } | |
6d3d9133 NC |
13628 | else |
13629 | { | |
13630 | /* In the normal case we only need to save those registers | |
13631 | which are call saved and which are used by this function. */ | |
ec6237e4 | 13632 | for (reg = 0; reg <= 11; reg++) |
6fb5fa3c | 13633 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
6d3d9133 NC |
13634 | save_reg_mask |= (1 << reg); |
13635 | ||
13636 | /* Handle the frame pointer as a special case. */ | |
ec6237e4 | 13637 | if (frame_pointer_needed) |
6d3d9133 NC |
13638 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; |
13639 | ||
13640 | /* If we aren't loading the PIC register, | |
13641 | don't stack it even though it may be live. */ | |
13642 | if (flag_pic | |
e0b92319 | 13643 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 13644 | && arm_pic_register != INVALID_REGNUM |
6fb5fa3c | 13645 | && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) |
e3b5732b | 13646 | || crtl->uses_pic_offset_table)) |
6d3d9133 | 13647 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
5b3e6663 PB |
13648 | |
13649 | /* The prologue will copy SP into R0, so save it. */ | |
13650 | if (IS_STACKALIGN (func_type)) | |
13651 | save_reg_mask |= 1; | |
6d3d9133 NC |
13652 | } |
13653 | ||
c9ca9b88 | 13654 | /* Save registers so the exception handler can modify them. */ |
e3b5732b | 13655 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
13656 | { |
13657 | unsigned int i; | |
f676971a | 13658 | |
c9ca9b88 PB |
13659 | for (i = 0; ; i++) |
13660 | { | |
13661 | reg = EH_RETURN_DATA_REGNO (i); | |
13662 | if (reg == INVALID_REGNUM) | |
13663 | break; | |
13664 | save_reg_mask |= 1 << reg; | |
13665 | } | |
13666 | } | |
13667 | ||
121308d4 NC |
13668 | return save_reg_mask; |
13669 | } | |
13670 | ||
5b3e6663 | 13671 | |
35596784 AJ |
13672 | /* Compute the number of bytes used to store the static chain register on the |
13673 | stack, above the stack frame. We need to know this accurately to get the | |
13674 | alignment of the rest of the stack frame correct. */ | |
13675 | ||
13676 | static int arm_compute_static_chain_stack_bytes (void) | |
13677 | { | |
13678 | unsigned long func_type = arm_current_func_type (); | |
13679 | int static_chain_stack_bytes = 0; | |
13680 | ||
13681 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && | |
13682 | IS_NESTED (func_type) && | |
13683 | df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0) | |
13684 | static_chain_stack_bytes = 4; | |
13685 | ||
13686 | return static_chain_stack_bytes; | |
13687 | } | |
13688 | ||
13689 | ||
121308d4 | 13690 | /* Compute a bit mask of which registers need to be |
954954d1 PB |
13691 | saved on the stack for the current function. |
13692 | This is used by arm_get_frame_offsets, which may add extra registers. */ | |
121308d4 NC |
13693 | |
13694 | static unsigned long | |
e32bac5b | 13695 | arm_compute_save_reg_mask (void) |
121308d4 NC |
13696 | { |
13697 | unsigned int save_reg_mask = 0; | |
13698 | unsigned long func_type = arm_current_func_type (); | |
5b3e6663 | 13699 | unsigned int reg; |
121308d4 NC |
13700 | |
13701 | if (IS_NAKED (func_type)) | |
13702 | /* This should never really happen. */ | |
13703 | return 0; | |
13704 | ||
13705 | /* If we are creating a stack frame, then we must save the frame pointer, | |
13706 | IP (which will hold the old stack pointer), LR and the PC. */ | |
ec6237e4 | 13707 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
121308d4 NC |
13708 | save_reg_mask |= |
13709 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
13710 | | (1 << IP_REGNUM) | |
13711 | | (1 << LR_REGNUM) | |
13712 | | (1 << PC_REGNUM); | |
13713 | ||
121308d4 NC |
13714 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); |
13715 | ||
6d3d9133 NC |
13716 | /* Decide if we need to save the link register. |
13717 | Interrupt routines have their own banked link register, | |
13718 | so they never need to save it. | |
1768c26f | 13719 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
13720 | it. If we are pushing other registers onto the stack however, we |
13721 | can save an instruction in the epilogue by pushing the link register | |
13722 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 13723 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 13724 | if we know that we will not need a fancy return sequence. */ |
6fb5fa3c DB |
13725 | if (df_regs_ever_live_p (LR_REGNUM) |
13726 | || (save_reg_mask | |
13727 | && optimize_size | |
13728 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 13729 | && !crtl->calls_eh_return)) |
6d3d9133 NC |
13730 | save_reg_mask |= 1 << LR_REGNUM; |
13731 | ||
6f7ebcbb NC |
13732 | if (cfun->machine->lr_save_eliminated) |
13733 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
13734 | ||
5a9335ef NC |
13735 | if (TARGET_REALLY_IWMMXT |
13736 | && ((bit_count (save_reg_mask) | |
35596784 AJ |
13737 | + ARM_NUM_INTS (crtl->args.pretend_args_size + |
13738 | arm_compute_static_chain_stack_bytes()) | |
13739 | ) % 2) != 0) | |
5a9335ef | 13740 | { |
5a9335ef NC |
13741 | /* The total number of registers that are going to be pushed |
13742 | onto the stack is odd. We need to ensure that the stack | |
13743 | is 64-bit aligned before we start to save iWMMXt registers, | |
13744 | and also before we start to create locals. (A local variable | |
13745 | might be a double or long long which we will load/store using | |
13746 | an iWMMXt instruction). Therefore we need to push another | |
13747 | ARM register, so that the stack will be 64-bit aligned. We | |
13748 | try to avoid using the arg registers (r0 -r3) as they might be | |
13749 | used to pass values in a tail call. */ | |
13750 | for (reg = 4; reg <= 12; reg++) | |
13751 | if ((save_reg_mask & (1 << reg)) == 0) | |
13752 | break; | |
13753 | ||
13754 | if (reg <= 12) | |
13755 | save_reg_mask |= (1 << reg); | |
13756 | else | |
13757 | { | |
13758 | cfun->machine->sibcall_blocked = 1; | |
13759 | save_reg_mask |= (1 << 3); | |
13760 | } | |
13761 | } | |
13762 | ||
5b3e6663 PB |
13763 | /* We may need to push an additional register for use initializing the |
13764 | PIC base register. */ | |
13765 | if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic | |
13766 | && (save_reg_mask & THUMB2_WORK_REGS) == 0) | |
13767 | { | |
13768 | reg = thumb_find_work_register (1 << 4); | |
13769 | if (!call_used_regs[reg]) | |
13770 | save_reg_mask |= (1 << reg); | |
13771 | } | |
13772 | ||
6d3d9133 NC |
13773 | return save_reg_mask; |
13774 | } | |
13775 | ||
9728c9d1 | 13776 | |
57934c39 PB |
13777 | /* Compute a bit mask of which registers need to be |
13778 | saved on the stack for the current function. */ | |
13779 | static unsigned long | |
5b3e6663 | 13780 | thumb1_compute_save_reg_mask (void) |
57934c39 PB |
13781 | { |
13782 | unsigned long mask; | |
b279b20a | 13783 | unsigned reg; |
57934c39 PB |
13784 | |
13785 | mask = 0; | |
13786 | for (reg = 0; reg < 12; reg ++) | |
6fb5fa3c | 13787 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b279b20a | 13788 | mask |= 1 << reg; |
57934c39 | 13789 | |
39c39be0 RE |
13790 | if (flag_pic |
13791 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 13792 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 13793 | && crtl->uses_pic_offset_table) |
39c39be0 | 13794 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
b279b20a | 13795 | |
a2503645 RS |
13796 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
13797 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
13798 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 13799 | |
b279b20a | 13800 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
13801 | if (mask & 0xff || thumb_force_lr_save ()) |
13802 | mask |= (1 << LR_REGNUM); | |
13803 | ||
b279b20a NC |
13804 | /* Make sure we have a low work register if we need one. |
13805 | We will need one if we are going to push a high register, | |
13806 | but we are not currently intending to push a low register. */ | |
13807 | if ((mask & 0xff) == 0 | |
57934c39 | 13808 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
13809 | { |
13810 | /* Use thumb_find_work_register to choose which register | |
13811 | we will use. If the register is live then we will | |
13812 | have to push it. Use LAST_LO_REGNUM as our fallback | |
13813 | choice for the register to select. */ | |
13814 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
19e723f4 PB |
13815 | /* Make sure the register returned by thumb_find_work_register is |
13816 | not part of the return value. */ | |
954954d1 | 13817 | if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) |
19e723f4 | 13818 | reg = LAST_LO_REGNUM; |
b279b20a NC |
13819 | |
13820 | if (! call_used_regs[reg]) | |
13821 | mask |= 1 << reg; | |
13822 | } | |
57934c39 | 13823 | |
35596784 AJ |
13824 | /* The 504 below is 8 bytes less than 512 because there are two possible |
13825 | alignment words. We can't tell here if they will be present or not so we | |
13826 | have to play it safe and assume that they are. */ | |
13827 | if ((CALLER_INTERWORKING_SLOT_SIZE + | |
13828 | ROUND_UP_WORD (get_frame_size ()) + | |
13829 | crtl->outgoing_args_size) >= 504) | |
13830 | { | |
13831 | /* This is the same as the code in thumb1_expand_prologue() which | |
13832 | determines which register to use for stack decrement. */ | |
13833 | for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++) | |
13834 | if (mask & (1 << reg)) | |
13835 | break; | |
13836 | ||
13837 | if (reg > LAST_LO_REGNUM) | |
13838 | { | |
13839 | /* Make sure we have a register available for stack decrement. */ | |
13840 | mask |= 1 << LAST_LO_REGNUM; | |
13841 | } | |
13842 | } | |
13843 | ||
57934c39 PB |
13844 | return mask; |
13845 | } | |
13846 | ||
13847 | ||
9728c9d1 PB |
13848 | /* Return the number of bytes required to save VFP registers. */ |
13849 | static int | |
13850 | arm_get_vfp_saved_size (void) | |
13851 | { | |
13852 | unsigned int regno; | |
13853 | int count; | |
13854 | int saved; | |
13855 | ||
13856 | saved = 0; | |
13857 | /* Space for saved VFP registers. */ | |
13858 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
13859 | { | |
13860 | count = 0; | |
13861 | for (regno = FIRST_VFP_REGNUM; | |
13862 | regno < LAST_VFP_REGNUM; | |
13863 | regno += 2) | |
13864 | { | |
6fb5fa3c DB |
13865 | if ((!df_regs_ever_live_p (regno) || call_used_regs[regno]) |
13866 | && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1])) | |
9728c9d1 PB |
13867 | { |
13868 | if (count > 0) | |
13869 | { | |
13870 | /* Workaround ARM10 VFPr1 bug. */ | |
13871 | if (count == 2 && !arm_arch6) | |
13872 | count++; | |
8edfc4cc | 13873 | saved += count * 8; |
9728c9d1 PB |
13874 | } |
13875 | count = 0; | |
13876 | } | |
13877 | else | |
13878 | count++; | |
13879 | } | |
13880 | if (count > 0) | |
13881 | { | |
13882 | if (count == 2 && !arm_arch6) | |
13883 | count++; | |
8edfc4cc | 13884 | saved += count * 8; |
9728c9d1 PB |
13885 | } |
13886 | } | |
13887 | return saved; | |
13888 | } | |
13889 | ||
13890 | ||
699a4925 | 13891 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 13892 | everything bar the final return instruction. */ |
cd2b33d0 | 13893 | const char * |
e32bac5b | 13894 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 13895 | { |
6d3d9133 | 13896 | char conditional[10]; |
ff9940b0 | 13897 | char instr[100]; |
b279b20a | 13898 | unsigned reg; |
6d3d9133 NC |
13899 | unsigned long live_regs_mask; |
13900 | unsigned long func_type; | |
5848830f | 13901 | arm_stack_offsets *offsets; |
e26053d1 | 13902 | |
6d3d9133 | 13903 | func_type = arm_current_func_type (); |
e2c671ba | 13904 | |
6d3d9133 | 13905 | if (IS_NAKED (func_type)) |
d5b7b3ae | 13906 | return ""; |
6d3d9133 NC |
13907 | |
13908 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 13909 | { |
699a4925 RE |
13910 | /* If this function was declared non-returning, and we have |
13911 | found a tail call, then we have to trust that the called | |
13912 | function won't return. */ | |
3a5a4282 PB |
13913 | if (really_return) |
13914 | { | |
13915 | rtx ops[2]; | |
f676971a | 13916 | |
3a5a4282 PB |
13917 | /* Otherwise, trap an attempted return by aborting. */ |
13918 | ops[0] = operand; | |
f676971a | 13919 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
13920 | : "abort"); |
13921 | assemble_external_libcall (ops[1]); | |
13922 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
13923 | } | |
f676971a | 13924 | |
e2c671ba RE |
13925 | return ""; |
13926 | } | |
6d3d9133 | 13927 | |
e3b5732b | 13928 | gcc_assert (!cfun->calls_alloca || really_return); |
ff9940b0 | 13929 | |
c414f8a9 | 13930 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 13931 | |
934c2060 | 13932 | cfun->machine->return_used_this_function = 1; |
ff9940b0 | 13933 | |
954954d1 PB |
13934 | offsets = arm_get_frame_offsets (); |
13935 | live_regs_mask = offsets->saved_regs_mask; | |
ff9940b0 | 13936 | |
1768c26f | 13937 | if (live_regs_mask) |
6d3d9133 | 13938 | { |
1768c26f PB |
13939 | const char * return_reg; |
13940 | ||
f676971a | 13941 | /* If we do not have any special requirements for function exit |
a15908a4 | 13942 | (e.g. interworking) then we can load the return address |
1768c26f PB |
13943 | directly into the PC. Otherwise we must load it into LR. */ |
13944 | if (really_return | |
a15908a4 | 13945 | && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK)) |
1768c26f | 13946 | return_reg = reg_names[PC_REGNUM]; |
6d3d9133 | 13947 | else |
1768c26f PB |
13948 | return_reg = reg_names[LR_REGNUM]; |
13949 | ||
6d3d9133 | 13950 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
13951 | { |
13952 | /* There are three possible reasons for the IP register | |
13953 | being saved. 1) a stack frame was created, in which case | |
13954 | IP contains the old stack pointer, or 2) an ISR routine | |
13955 | corrupted it, or 3) it was saved to align the stack on | |
13956 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
13957 | restore IP. */ | |
13958 | if (frame_pointer_needed) | |
13959 | { | |
13960 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
13961 | live_regs_mask |= (1 << SP_REGNUM); | |
13962 | } | |
13963 | else | |
e6d29d15 | 13964 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 13965 | } |
f3bb6135 | 13966 | |
3a7731fd PB |
13967 | /* On some ARM architectures it is faster to use LDR rather than |
13968 | LDM to load a single register. On other architectures, the | |
13969 | cost is the same. In 26 bit mode, or for exception handlers, | |
13970 | we have to use LDM to load the PC so that the CPSR is also | |
13971 | restored. */ | |
13972 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
13973 | if (live_regs_mask == (1U << reg)) |
13974 | break; | |
13975 | ||
3a7731fd PB |
13976 | if (reg <= LAST_ARM_REGNUM |
13977 | && (reg != LR_REGNUM | |
f676971a | 13978 | || ! really_return |
61f0ccff | 13979 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 13980 | { |
f676971a | 13981 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 13982 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 13983 | } |
ff9940b0 | 13984 | else |
1d5473cb | 13985 | { |
1768c26f PB |
13986 | char *p; |
13987 | int first = 1; | |
6d3d9133 | 13988 | |
699a4925 RE |
13989 | /* Generate the load multiple instruction to restore the |
13990 | registers. Note we can get here, even if | |
13991 | frame_pointer_needed is true, but only if sp already | |
13992 | points to the base of the saved core registers. */ | |
13993 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 13994 | { |
5848830f PB |
13995 | unsigned HOST_WIDE_INT stack_adjust; |
13996 | ||
5848830f | 13997 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; |
e6d29d15 | 13998 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 | 13999 | |
5b3e6663 | 14000 | if (stack_adjust && arm_arch5 && TARGET_ARM) |
c7e9ab97 RR |
14001 | if (TARGET_UNIFIED_ASM) |
14002 | sprintf (instr, "ldmib%s\t%%|sp, {", conditional); | |
14003 | else | |
14004 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); | |
a72d4945 RE |
14005 | else |
14006 | { | |
b279b20a NC |
14007 | /* If we can't use ldmib (SA110 bug), |
14008 | then try to pop r3 instead. */ | |
a72d4945 RE |
14009 | if (stack_adjust) |
14010 | live_regs_mask |= 1 << 3; | |
c7e9ab97 RR |
14011 | |
14012 | if (TARGET_UNIFIED_ASM) | |
14013 | sprintf (instr, "ldmfd%s\t%%|sp, {", conditional); | |
14014 | else | |
14015 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
a72d4945 RE |
14016 | } |
14017 | } | |
da6558fd | 14018 | else |
c7e9ab97 RR |
14019 | if (TARGET_UNIFIED_ASM) |
14020 | sprintf (instr, "pop%s\t{", conditional); | |
14021 | else | |
14022 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); | |
1768c26f PB |
14023 | |
14024 | p = instr + strlen (instr); | |
6d3d9133 | 14025 | |
1768c26f PB |
14026 | for (reg = 0; reg <= SP_REGNUM; reg++) |
14027 | if (live_regs_mask & (1 << reg)) | |
14028 | { | |
14029 | int l = strlen (reg_names[reg]); | |
14030 | ||
14031 | if (first) | |
14032 | first = 0; | |
14033 | else | |
14034 | { | |
14035 | memcpy (p, ", ", 2); | |
14036 | p += 2; | |
14037 | } | |
14038 | ||
14039 | memcpy (p, "%|", 2); | |
14040 | memcpy (p + 2, reg_names[reg], l); | |
14041 | p += l + 2; | |
14042 | } | |
f676971a | 14043 | |
1768c26f PB |
14044 | if (live_regs_mask & (1 << LR_REGNUM)) |
14045 | { | |
b17fe233 | 14046 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
14047 | /* If returning from an interrupt, restore the CPSR. */ |
14048 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 14049 | strcat (p, "^"); |
1768c26f PB |
14050 | } |
14051 | else | |
14052 | strcpy (p, "}"); | |
1d5473cb | 14053 | } |
da6558fd | 14054 | |
1768c26f PB |
14055 | output_asm_insn (instr, & operand); |
14056 | ||
3a7731fd PB |
14057 | /* See if we need to generate an extra instruction to |
14058 | perform the actual function return. */ | |
14059 | if (really_return | |
14060 | && func_type != ARM_FT_INTERWORKED | |
14061 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 14062 | { |
3a7731fd PB |
14063 | /* The return has already been handled |
14064 | by loading the LR into the PC. */ | |
14065 | really_return = 0; | |
da6558fd | 14066 | } |
ff9940b0 | 14067 | } |
e26053d1 | 14068 | |
1768c26f | 14069 | if (really_return) |
ff9940b0 | 14070 | { |
6d3d9133 NC |
14071 | switch ((int) ARM_FUNC_TYPE (func_type)) |
14072 | { | |
14073 | case ARM_FT_ISR: | |
14074 | case ARM_FT_FIQ: | |
5b3e6663 | 14075 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
14076 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); |
14077 | break; | |
14078 | ||
14079 | case ARM_FT_INTERWORKED: | |
14080 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
14081 | break; | |
14082 | ||
14083 | case ARM_FT_EXCEPTION: | |
5b3e6663 | 14084 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
14085 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); |
14086 | break; | |
14087 | ||
14088 | default: | |
68d560d4 RE |
14089 | /* Use bx if it's available. */ |
14090 | if (arm_arch5 || arm_arch4t) | |
f676971a | 14091 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 14092 | else |
61f0ccff | 14093 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
14094 | break; |
14095 | } | |
1768c26f PB |
14096 | |
14097 | output_asm_insn (instr, & operand); | |
ff9940b0 | 14098 | } |
f3bb6135 | 14099 | |
ff9940b0 RE |
14100 | return ""; |
14101 | } | |
14102 | ||
ef179a26 NC |
14103 | /* Write the function name into the code section, directly preceding |
14104 | the function prologue. | |
14105 | ||
14106 | Code will be output similar to this: | |
14107 | t0 | |
14108 | .ascii "arm_poke_function_name", 0 | |
14109 | .align | |
14110 | t1 | |
14111 | .word 0xff000000 + (t1 - t0) | |
14112 | arm_poke_function_name | |
14113 | mov ip, sp | |
14114 | stmfd sp!, {fp, ip, lr, pc} | |
14115 | sub fp, ip, #4 | |
14116 | ||
14117 | When performing a stack backtrace, code can inspect the value | |
14118 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
14119 | at location pc - 12 and the top 8 bits are set, then we know | |
14120 | that there is a function name embedded immediately preceding this | |
14121 | location and has length ((pc[-3]) & 0xff000000). | |
14122 | ||
14123 | We assume that pc is declared as a pointer to an unsigned long. | |
14124 | ||
14125 | It is of no benefit to output the function name if we are assembling | |
14126 | a leaf function. These function types will not contain a stack | |
14127 | backtrace structure, therefore it is not possible to determine the | |
14128 | function name. */ | |
ef179a26 | 14129 | void |
e32bac5b | 14130 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
14131 | { |
14132 | unsigned long alignlength; | |
14133 | unsigned long length; | |
14134 | rtx x; | |
14135 | ||
d5b7b3ae | 14136 | length = strlen (name) + 1; |
0c2ca901 | 14137 | alignlength = ROUND_UP_WORD (length); |
f676971a | 14138 | |
949d79eb | 14139 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 14140 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 14141 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 14142 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
14143 | } |
14144 | ||
6d3d9133 NC |
14145 | /* Place some comments into the assembler stream |
14146 | describing the current function. */ | |
08c148a8 | 14147 | static void |
e32bac5b | 14148 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 14149 | { |
6d3d9133 | 14150 | unsigned long func_type; |
08c148a8 | 14151 | |
5b3e6663 | 14152 | if (TARGET_THUMB1) |
08c148a8 | 14153 | { |
5b3e6663 | 14154 | thumb1_output_function_prologue (f, frame_size); |
08c148a8 NB |
14155 | return; |
14156 | } | |
f676971a | 14157 | |
6d3d9133 | 14158 | /* Sanity check. */ |
e6d29d15 | 14159 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 14160 | |
6d3d9133 | 14161 | func_type = arm_current_func_type (); |
f676971a | 14162 | |
6d3d9133 NC |
14163 | switch ((int) ARM_FUNC_TYPE (func_type)) |
14164 | { | |
14165 | default: | |
14166 | case ARM_FT_NORMAL: | |
14167 | break; | |
14168 | case ARM_FT_INTERWORKED: | |
14169 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
14170 | break; | |
6d3d9133 NC |
14171 | case ARM_FT_ISR: |
14172 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
14173 | break; | |
14174 | case ARM_FT_FIQ: | |
14175 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
14176 | break; | |
14177 | case ARM_FT_EXCEPTION: | |
14178 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
14179 | break; | |
14180 | } | |
f676971a | 14181 | |
6d3d9133 NC |
14182 | if (IS_NAKED (func_type)) |
14183 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
14184 | ||
14185 | if (IS_VOLATILE (func_type)) | |
14186 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
14187 | ||
14188 | if (IS_NESTED (func_type)) | |
14189 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
5b3e6663 PB |
14190 | if (IS_STACKALIGN (func_type)) |
14191 | asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n"); | |
f676971a | 14192 | |
c53dddc2 | 14193 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
38173d38 JH |
14194 | crtl->args.size, |
14195 | crtl->args.pretend_args_size, frame_size); | |
6d3d9133 | 14196 | |
3cb66fd7 | 14197 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 14198 | frame_pointer_needed, |
3cb66fd7 | 14199 | cfun->machine->uses_anonymous_args); |
cce8749e | 14200 | |
6f7ebcbb NC |
14201 | if (cfun->machine->lr_save_eliminated) |
14202 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
14203 | ||
e3b5732b | 14204 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
14205 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); |
14206 | ||
f3bb6135 | 14207 | } |
cce8749e | 14208 | |
cd2b33d0 | 14209 | const char * |
a72d4945 | 14210 | arm_output_epilogue (rtx sibling) |
cce8749e | 14211 | { |
949d79eb | 14212 | int reg; |
6f7ebcbb | 14213 | unsigned long saved_regs_mask; |
6d3d9133 | 14214 | unsigned long func_type; |
f676971a | 14215 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
14216 | frame that is $fp + 4 for a non-variadic function. */ |
14217 | int floats_offset = 0; | |
cce8749e | 14218 | rtx operands[3]; |
d5b7b3ae | 14219 | FILE * f = asm_out_file; |
5a9335ef | 14220 | unsigned int lrm_count = 0; |
a72d4945 | 14221 | int really_return = (sibling == NULL); |
9b66ebb1 | 14222 | int start_reg; |
5848830f | 14223 | arm_stack_offsets *offsets; |
cce8749e | 14224 | |
6d3d9133 NC |
14225 | /* If we have already generated the return instruction |
14226 | then it is futile to generate anything else. */ | |
934c2060 RR |
14227 | if (use_return_insn (FALSE, sibling) && |
14228 | (cfun->machine->return_used_this_function != 0)) | |
949d79eb | 14229 | return ""; |
cce8749e | 14230 | |
6d3d9133 | 14231 | func_type = arm_current_func_type (); |
d5b7b3ae | 14232 | |
6d3d9133 NC |
14233 | if (IS_NAKED (func_type)) |
14234 | /* Naked functions don't have epilogues. */ | |
14235 | return ""; | |
0616531f | 14236 | |
6d3d9133 | 14237 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 14238 | { |
86efdc8e | 14239 | rtx op; |
f676971a | 14240 | |
6d3d9133 | 14241 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 14242 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 14243 | assemble_external_libcall (op); |
e2c671ba | 14244 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 14245 | |
949d79eb | 14246 | return ""; |
e2c671ba RE |
14247 | } |
14248 | ||
e6d29d15 NS |
14249 | /* If we are throwing an exception, then we really must be doing a |
14250 | return, so we can't tail-call. */ | |
e3b5732b | 14251 | gcc_assert (!crtl->calls_eh_return || really_return); |
f676971a | 14252 | |
5848830f | 14253 | offsets = arm_get_frame_offsets (); |
954954d1 | 14254 | saved_regs_mask = offsets->saved_regs_mask; |
5a9335ef NC |
14255 | |
14256 | if (TARGET_IWMMXT) | |
14257 | lrm_count = bit_count (saved_regs_mask); | |
14258 | ||
5848830f | 14259 | floats_offset = offsets->saved_args; |
6d3d9133 | 14260 | /* Compute how far away the floats will be. */ |
5a9335ef | 14261 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 14262 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 14263 | floats_offset += 4; |
f676971a | 14264 | |
ec6237e4 | 14265 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
cce8749e | 14266 | { |
9b66ebb1 | 14267 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 14268 | int vfp_offset = offsets->frame; |
c882c7ac | 14269 | |
d79f3032 | 14270 | if (TARGET_FPA_EMU2) |
b111229a | 14271 | { |
9b66ebb1 | 14272 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
6fb5fa3c | 14273 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14274 | { |
14275 | floats_offset += 12; | |
f676971a | 14276 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 14277 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14278 | } |
14279 | } | |
14280 | else | |
14281 | { | |
9b66ebb1 | 14282 | start_reg = LAST_FPA_REGNUM; |
b111229a | 14283 | |
9b66ebb1 | 14284 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 14285 | { |
6fb5fa3c | 14286 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14287 | { |
14288 | floats_offset += 12; | |
f676971a | 14289 | |
6354dc9b | 14290 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
14291 | if (start_reg - reg == 3) |
14292 | { | |
dd18ae56 | 14293 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 14294 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14295 | start_reg = reg - 1; |
14296 | } | |
14297 | } | |
14298 | else | |
14299 | { | |
14300 | if (reg != start_reg) | |
dd18ae56 NC |
14301 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
14302 | reg + 1, start_reg - reg, | |
c882c7ac | 14303 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
14304 | start_reg = reg - 1; |
14305 | } | |
14306 | } | |
14307 | ||
14308 | /* Just in case the last register checked also needs unstacking. */ | |
14309 | if (reg != start_reg) | |
dd18ae56 NC |
14310 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
14311 | reg + 1, start_reg - reg, | |
c882c7ac | 14312 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 14313 | } |
6d3d9133 | 14314 | |
9b66ebb1 PB |
14315 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
14316 | { | |
9728c9d1 | 14317 | int saved_size; |
9b66ebb1 | 14318 | |
8edfc4cc MS |
14319 | /* The fldmd insns do not have base+offset addressing |
14320 | modes, so we use IP to hold the address. */ | |
9728c9d1 | 14321 | saved_size = arm_get_vfp_saved_size (); |
9b66ebb1 | 14322 | |
9728c9d1 | 14323 | if (saved_size > 0) |
9b66ebb1 | 14324 | { |
9728c9d1 | 14325 | floats_offset += saved_size; |
9b66ebb1 PB |
14326 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
14327 | FP_REGNUM, floats_offset - vfp_offset); | |
14328 | } | |
14329 | start_reg = FIRST_VFP_REGNUM; | |
14330 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
14331 | { | |
6fb5fa3c DB |
14332 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
14333 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
14334 | { |
14335 | if (start_reg != reg) | |
8edfc4cc | 14336 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
14337 | (start_reg - FIRST_VFP_REGNUM) / 2, |
14338 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
14339 | start_reg = reg + 2; |
14340 | } | |
14341 | } | |
14342 | if (start_reg != reg) | |
8edfc4cc | 14343 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
14344 | (start_reg - FIRST_VFP_REGNUM) / 2, |
14345 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
14346 | } |
14347 | ||
5a9335ef NC |
14348 | if (TARGET_IWMMXT) |
14349 | { | |
14350 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
14351 | This is because it is set to (old_stack_pointer - 4) and the | |
14352 | old_stack_pointer was double word aligned. Thus the offset to | |
14353 | the iWMMXt registers to be loaded must also be non-double-word | |
14354 | sized, so that the resultant address *is* double-word aligned. | |
14355 | We can ignore floats_offset since that was already included in | |
14356 | the live_regs_mask. */ | |
14357 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 14358 | |
01d4c813 | 14359 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
6fb5fa3c | 14360 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5a9335ef | 14361 | { |
f676971a | 14362 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 14363 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 14364 | lrm_count += 2; |
5a9335ef NC |
14365 | } |
14366 | } | |
14367 | ||
6f7ebcbb | 14368 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
14369 | frame generation actually contains the old stack pointer. So a |
14370 | quick way to unwind the stack is just pop the IP register directly | |
14371 | into the stack pointer. */ | |
e6d29d15 | 14372 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
14373 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
14374 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 14375 | |
6f7ebcbb | 14376 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
14377 | only need to restore the LR register (the return address), but to |
14378 | save time we can load it directly into the PC, unless we need a | |
14379 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
14380 | if (really_return |
14381 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 14382 | && !crtl->calls_eh_return) |
6d3d9133 NC |
14383 | /* Delete the LR from the register mask, so that the LR on |
14384 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 14385 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 14386 | else |
6f7ebcbb | 14387 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
14388 | |
14389 | /* We must use SP as the base register, because SP is one of the | |
14390 | registers being restored. If an interrupt or page fault | |
14391 | happens in the ldm instruction, the SP might or might not | |
14392 | have been restored. That would be bad, as then SP will no | |
14393 | longer indicate the safe area of stack, and we can get stack | |
14394 | corruption. Using SP as the base register means that it will | |
14395 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
14396 | occur. If the stack pointer already points at the right |
14397 | place, then omit the subtraction. */ | |
5848830f | 14398 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
e3b5732b | 14399 | || cfun->calls_alloca) |
699a4925 RE |
14400 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, |
14401 | 4 * bit_count (saved_regs_mask)); | |
a15908a4 | 14402 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0); |
7b8b8ade NC |
14403 | |
14404 | if (IS_INTERRUPT (func_type)) | |
14405 | /* Interrupt handlers will have pushed the | |
14406 | IP onto the stack, so restore it now. */ | |
a15908a4 | 14407 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0); |
cce8749e CH |
14408 | } |
14409 | else | |
14410 | { | |
ec6237e4 PB |
14411 | /* This branch is executed for ARM mode (non-apcs frames) and |
14412 | Thumb-2 mode. Frame layout is essentially the same for those | |
14413 | cases, except that in ARM mode frame pointer points to the | |
14414 | first saved register, while in Thumb-2 mode the frame pointer points | |
14415 | to the last saved register. | |
14416 | ||
14417 | It is possible to make frame pointer point to last saved | |
14418 | register in both cases, and remove some conditionals below. | |
14419 | That means that fp setup in prologue would be just "mov fp, sp" | |
14420 | and sp restore in epilogue would be just "mov sp, fp", whereas | |
14421 | now we have to use add/sub in those cases. However, the value | |
14422 | of that would be marginal, as both mov and add/sub are 32-bit | |
14423 | in ARM mode, and it would require extra conditionals | |
14424 | in arm_expand_prologue to distingish ARM-apcs-frame case | |
14425 | (where frame pointer is required to point at first register) | |
14426 | and ARM-non-apcs-frame. Therefore, such change is postponed | |
14427 | until real need arise. */ | |
f0b4bdd5 | 14428 | unsigned HOST_WIDE_INT amount; |
a15908a4 | 14429 | int rfe; |
d2288d8d | 14430 | /* Restore stack pointer if necessary. */ |
ec6237e4 | 14431 | if (TARGET_ARM && frame_pointer_needed) |
5b3e6663 PB |
14432 | { |
14433 | operands[0] = stack_pointer_rtx; | |
ec6237e4 PB |
14434 | operands[1] = hard_frame_pointer_rtx; |
14435 | ||
14436 | operands[2] = GEN_INT (offsets->frame - offsets->saved_regs); | |
14437 | output_add_immediate (operands); | |
5b3e6663 | 14438 | } |
ec6237e4 | 14439 | else |
5b3e6663 | 14440 | { |
ec6237e4 PB |
14441 | if (frame_pointer_needed) |
14442 | { | |
14443 | /* For Thumb-2 restore sp from the frame pointer. | |
14444 | Operand restrictions mean we have to incrememnt FP, then copy | |
14445 | to SP. */ | |
14446 | amount = offsets->locals_base - offsets->saved_regs; | |
14447 | operands[0] = hard_frame_pointer_rtx; | |
14448 | } | |
14449 | else | |
14450 | { | |
954954d1 | 14451 | unsigned long count; |
ec6237e4 PB |
14452 | operands[0] = stack_pointer_rtx; |
14453 | amount = offsets->outgoing_args - offsets->saved_regs; | |
954954d1 PB |
14454 | /* pop call clobbered registers if it avoids a |
14455 | separate stack adjustment. */ | |
14456 | count = offsets->saved_regs - offsets->saved_args; | |
14457 | if (optimize_size | |
14458 | && count != 0 | |
e3b5732b | 14459 | && !crtl->calls_eh_return |
954954d1 PB |
14460 | && bit_count(saved_regs_mask) * 4 == count |
14461 | && !IS_INTERRUPT (func_type) | |
e3b5732b | 14462 | && !crtl->tail_call_emit) |
954954d1 PB |
14463 | { |
14464 | unsigned long mask; | |
14465 | mask = (1 << (arm_size_return_regs() / 4)) - 1; | |
14466 | mask ^= 0xf; | |
14467 | mask &= ~saved_regs_mask; | |
14468 | reg = 0; | |
14469 | while (bit_count (mask) * 4 > amount) | |
14470 | { | |
14471 | while ((mask & (1 << reg)) == 0) | |
14472 | reg++; | |
14473 | mask &= ~(1 << reg); | |
14474 | } | |
14475 | if (bit_count (mask) * 4 == amount) { | |
14476 | amount = 0; | |
14477 | saved_regs_mask |= mask; | |
14478 | } | |
14479 | } | |
ec6237e4 PB |
14480 | } |
14481 | ||
14482 | if (amount) | |
14483 | { | |
14484 | operands[1] = operands[0]; | |
14485 | operands[2] = GEN_INT (amount); | |
14486 | output_add_immediate (operands); | |
14487 | } | |
14488 | if (frame_pointer_needed) | |
14489 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
14490 | SP_REGNUM, HARD_FRAME_POINTER_REGNUM); | |
d2288d8d TG |
14491 | } |
14492 | ||
d79f3032 | 14493 | if (TARGET_FPA_EMU2) |
b111229a | 14494 | { |
9b66ebb1 | 14495 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
6fb5fa3c | 14496 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
dd18ae56 NC |
14497 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
14498 | reg, SP_REGNUM); | |
b111229a RE |
14499 | } |
14500 | else | |
14501 | { | |
9b66ebb1 | 14502 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 14503 | |
9b66ebb1 | 14504 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 14505 | { |
6fb5fa3c | 14506 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
14507 | { |
14508 | if (reg - start_reg == 3) | |
14509 | { | |
dd18ae56 NC |
14510 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
14511 | start_reg, SP_REGNUM); | |
b111229a RE |
14512 | start_reg = reg + 1; |
14513 | } | |
14514 | } | |
14515 | else | |
14516 | { | |
14517 | if (reg != start_reg) | |
dd18ae56 NC |
14518 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
14519 | start_reg, reg - start_reg, | |
14520 | SP_REGNUM); | |
f676971a | 14521 | |
b111229a RE |
14522 | start_reg = reg + 1; |
14523 | } | |
14524 | } | |
14525 | ||
14526 | /* Just in case the last register checked also needs unstacking. */ | |
14527 | if (reg != start_reg) | |
dd18ae56 NC |
14528 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
14529 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
14530 | } |
14531 | ||
9b66ebb1 PB |
14532 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
14533 | { | |
f8b68ed3 RE |
14534 | int end_reg = LAST_VFP_REGNUM + 1; |
14535 | ||
14536 | /* Scan the registers in reverse order. We need to match | |
14537 | any groupings made in the prologue and generate matching | |
14538 | pop operations. */ | |
14539 | for (reg = LAST_VFP_REGNUM - 1; reg >= FIRST_VFP_REGNUM; reg -= 2) | |
9b66ebb1 | 14540 | { |
6fb5fa3c | 14541 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
f8b68ed3 RE |
14542 | && (!df_regs_ever_live_p (reg + 1) |
14543 | || call_used_regs[reg + 1])) | |
9b66ebb1 | 14544 | { |
f8b68ed3 | 14545 | if (end_reg > reg + 2) |
8edfc4cc | 14546 | vfp_output_fldmd (f, SP_REGNUM, |
f8b68ed3 RE |
14547 | (reg + 2 - FIRST_VFP_REGNUM) / 2, |
14548 | (end_reg - (reg + 2)) / 2); | |
14549 | end_reg = reg; | |
9b66ebb1 PB |
14550 | } |
14551 | } | |
f8b68ed3 RE |
14552 | if (end_reg > reg + 2) |
14553 | vfp_output_fldmd (f, SP_REGNUM, 0, | |
14554 | (end_reg - (reg + 2)) / 2); | |
9b66ebb1 | 14555 | } |
f8b68ed3 | 14556 | |
5a9335ef NC |
14557 | if (TARGET_IWMMXT) |
14558 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
6fb5fa3c | 14559 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
01d4c813 | 14560 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 14561 | |
6d3d9133 | 14562 | /* If we can, restore the LR into the PC. */ |
a15908a4 PB |
14563 | if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED |
14564 | && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
5b3e6663 | 14565 | && !IS_STACKALIGN (func_type) |
6d3d9133 | 14566 | && really_return |
38173d38 | 14567 | && crtl->args.pretend_args_size == 0 |
c9ca9b88 | 14568 | && saved_regs_mask & (1 << LR_REGNUM) |
e3b5732b | 14569 | && !crtl->calls_eh_return) |
cce8749e | 14570 | { |
6f7ebcbb NC |
14571 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
14572 | saved_regs_mask |= (1 << PC_REGNUM); | |
a15908a4 | 14573 | rfe = IS_INTERRUPT (func_type); |
6d3d9133 | 14574 | } |
a15908a4 PB |
14575 | else |
14576 | rfe = 0; | |
d5b7b3ae | 14577 | |
6d3d9133 | 14578 | /* Load the registers off the stack. If we only have one register |
5b3e6663 PB |
14579 | to load use the LDR instruction - it is faster. For Thumb-2 |
14580 | always use pop and the assembler will pick the best instruction.*/ | |
a15908a4 PB |
14581 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) |
14582 | && !IS_INTERRUPT(func_type)) | |
6d3d9133 | 14583 | { |
c9ca9b88 | 14584 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 14585 | } |
6f7ebcbb | 14586 | else if (saved_regs_mask) |
f1acdf8b NC |
14587 | { |
14588 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
14589 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 14590 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
14591 | in the list of registers and if we add writeback the |
14592 | instruction becomes UNPREDICTABLE. */ | |
a15908a4 PB |
14593 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, |
14594 | rfe); | |
5b3e6663 | 14595 | else if (TARGET_ARM) |
a15908a4 PB |
14596 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, |
14597 | rfe); | |
f1acdf8b | 14598 | else |
a15908a4 | 14599 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); |
f1acdf8b | 14600 | } |
6d3d9133 | 14601 | |
38173d38 | 14602 | if (crtl->args.pretend_args_size) |
cce8749e | 14603 | { |
6d3d9133 NC |
14604 | /* Unwind the pre-pushed regs. */ |
14605 | operands[0] = operands[1] = stack_pointer_rtx; | |
38173d38 | 14606 | operands[2] = GEN_INT (crtl->args.pretend_args_size); |
6d3d9133 NC |
14607 | output_add_immediate (operands); |
14608 | } | |
14609 | } | |
32de079a | 14610 | |
2966b00e | 14611 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 14612 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 14613 | return ""; |
d5b7b3ae | 14614 | |
c9ca9b88 | 14615 | /* Stack adjustment for exception handler. */ |
e3b5732b | 14616 | if (crtl->calls_eh_return) |
f676971a | 14617 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
14618 | ARM_EH_STACKADJ_REGNUM); |
14619 | ||
6d3d9133 NC |
14620 | /* Generate the return instruction. */ |
14621 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
14622 | { | |
6d3d9133 NC |
14623 | case ARM_FT_ISR: |
14624 | case ARM_FT_FIQ: | |
14625 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
14626 | break; | |
14627 | ||
14628 | case ARM_FT_EXCEPTION: | |
14629 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
14630 | break; | |
14631 | ||
14632 | case ARM_FT_INTERWORKED: | |
14633 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
14634 | break; | |
14635 | ||
14636 | default: | |
5b3e6663 PB |
14637 | if (IS_STACKALIGN (func_type)) |
14638 | { | |
14639 | /* See comment in arm_expand_prologue. */ | |
14640 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0); | |
14641 | } | |
68d560d4 RE |
14642 | if (arm_arch5 || arm_arch4t) |
14643 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
14644 | else | |
14645 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 14646 | break; |
cce8749e | 14647 | } |
f3bb6135 | 14648 | |
949d79eb RE |
14649 | return ""; |
14650 | } | |
14651 | ||
08c148a8 | 14652 | static void |
e32bac5b | 14653 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 14654 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 14655 | { |
5848830f PB |
14656 | arm_stack_offsets *offsets; |
14657 | ||
5b3e6663 | 14658 | if (TARGET_THUMB1) |
d5b7b3ae | 14659 | { |
b12a00f1 RE |
14660 | int regno; |
14661 | ||
14662 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
14663 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 14664 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
14665 | { |
14666 | rtx label = cfun->machine->call_via[regno]; | |
14667 | ||
14668 | if (label != NULL) | |
14669 | { | |
d6b5193b | 14670 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
14671 | targetm.asm_out.internal_label (asm_out_file, "L", |
14672 | CODE_LABEL_NUMBER (label)); | |
14673 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
14674 | } | |
14675 | } | |
14676 | ||
d5b7b3ae RE |
14677 | /* ??? Probably not safe to set this here, since it assumes that a |
14678 | function will be emitted as assembly immediately after we generate | |
14679 | RTL for it. This does not happen for inline functions. */ | |
934c2060 | 14680 | cfun->machine->return_used_this_function = 0; |
d5b7b3ae | 14681 | } |
5b3e6663 | 14682 | else /* TARGET_32BIT */ |
d5b7b3ae | 14683 | { |
0977774b | 14684 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 14685 | offsets = arm_get_frame_offsets (); |
0977774b | 14686 | |
e6d29d15 | 14687 | gcc_assert (!use_return_insn (FALSE, NULL) |
934c2060 | 14688 | || (cfun->machine->return_used_this_function != 0) |
e6d29d15 NS |
14689 | || offsets->saved_regs == offsets->outgoing_args |
14690 | || frame_pointer_needed); | |
f3bb6135 | 14691 | |
d5b7b3ae | 14692 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
14693 | after_arm_reorg = 0; |
14694 | } | |
f3bb6135 | 14695 | } |
e2c671ba | 14696 | |
2c849145 JM |
14697 | /* Generate and emit an insn that we will recognize as a push_multi. |
14698 | Unfortunately, since this insn does not reflect very well the actual | |
14699 | semantics of the operation, we need to annotate the insn for the benefit | |
14700 | of DWARF2 frame unwind information. */ | |
2c849145 | 14701 | static rtx |
b279b20a | 14702 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
14703 | { |
14704 | int num_regs = 0; | |
9b598fa0 | 14705 | int num_dwarf_regs; |
e2c671ba RE |
14706 | int i, j; |
14707 | rtx par; | |
2c849145 | 14708 | rtx dwarf; |
87e27392 | 14709 | int dwarf_par_index; |
2c849145 | 14710 | rtx tmp, reg; |
e2c671ba | 14711 | |
d5b7b3ae | 14712 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 14713 | if (mask & (1 << i)) |
5895f793 | 14714 | num_regs++; |
e2c671ba | 14715 | |
e6d29d15 | 14716 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 14717 | |
9b598fa0 RE |
14718 | /* We don't record the PC in the dwarf frame information. */ |
14719 | num_dwarf_regs = num_regs; | |
14720 | if (mask & (1 << PC_REGNUM)) | |
14721 | num_dwarf_regs--; | |
14722 | ||
87e27392 | 14723 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 14724 | parallel with several USEs. This allows the insn to be recognized |
9abf5d7b RR |
14725 | by the push_multi pattern in the arm.md file. |
14726 | ||
14727 | The body of the insn looks something like this: | |
87e27392 | 14728 | |
f676971a | 14729 | (parallel [ |
9abf5d7b RR |
14730 | (set (mem:BLK (pre_modify:SI (reg:SI sp) |
14731 | (const_int:SI <num>))) | |
b15bca31 | 14732 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) |
9abf5d7b RR |
14733 | (use (reg:SI XX)) |
14734 | (use (reg:SI YY)) | |
14735 | ... | |
87e27392 NC |
14736 | ]) |
14737 | ||
14738 | For the frame note however, we try to be more explicit and actually | |
14739 | show each register being stored into the stack frame, plus a (single) | |
14740 | decrement of the stack pointer. We do it this way in order to be | |
14741 | friendly to the stack unwinding code, which only wants to see a single | |
14742 | stack decrement per instruction. The RTL we generate for the note looks | |
14743 | something like this: | |
14744 | ||
f676971a | 14745 | (sequence [ |
87e27392 NC |
14746 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
14747 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
9abf5d7b RR |
14748 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI XX)) |
14749 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI YY)) | |
14750 | ... | |
87e27392 NC |
14751 | ]) |
14752 | ||
9abf5d7b RR |
14753 | FIXME:: In an ideal world the PRE_MODIFY would not exist and |
14754 | instead we'd have a parallel expression detailing all | |
14755 | the stores to the various memory addresses so that debug | |
14756 | information is more up-to-date. Remember however while writing | |
14757 | this to take care of the constraints with the push instruction. | |
14758 | ||
14759 | Note also that this has to be taken care of for the VFP registers. | |
14760 | ||
14761 | For more see PR43399. */ | |
f676971a | 14762 | |
43cffd11 | 14763 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 14764 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 14765 | dwarf_par_index = 1; |
e2c671ba | 14766 | |
d5b7b3ae | 14767 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
14768 | { |
14769 | if (mask & (1 << i)) | |
14770 | { | |
2c849145 JM |
14771 | reg = gen_rtx_REG (SImode, i); |
14772 | ||
e2c671ba | 14773 | XVECEXP (par, 0, 0) |
43cffd11 | 14774 | = gen_rtx_SET (VOIDmode, |
9abf5d7b RR |
14775 | gen_frame_mem |
14776 | (BLKmode, | |
14777 | gen_rtx_PRE_MODIFY (Pmode, | |
14778 | stack_pointer_rtx, | |
14779 | plus_constant | |
14780 | (stack_pointer_rtx, | |
14781 | -4 * num_regs)) | |
14782 | ), | |
43cffd11 | 14783 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 14784 | gen_rtvec (1, reg), |
9b598fa0 | 14785 | UNSPEC_PUSH_MULT)); |
2c849145 | 14786 | |
9b598fa0 RE |
14787 | if (i != PC_REGNUM) |
14788 | { | |
14789 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 14790 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
14791 | reg); |
14792 | RTX_FRAME_RELATED_P (tmp) = 1; | |
14793 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
14794 | dwarf_par_index++; | |
14795 | } | |
2c849145 | 14796 | |
e2c671ba RE |
14797 | break; |
14798 | } | |
14799 | } | |
14800 | ||
14801 | for (j = 1, i++; j < num_regs; i++) | |
14802 | { | |
14803 | if (mask & (1 << i)) | |
14804 | { | |
2c849145 JM |
14805 | reg = gen_rtx_REG (SImode, i); |
14806 | ||
14807 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
14808 | ||
9b598fa0 RE |
14809 | if (i != PC_REGNUM) |
14810 | { | |
31fa16b6 RE |
14811 | tmp |
14812 | = gen_rtx_SET (VOIDmode, | |
9abf5d7b RR |
14813 | gen_frame_mem |
14814 | (SImode, | |
14815 | plus_constant (stack_pointer_rtx, | |
14816 | 4 * j)), | |
31fa16b6 | 14817 | reg); |
9b598fa0 RE |
14818 | RTX_FRAME_RELATED_P (tmp) = 1; |
14819 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
14820 | } | |
14821 | ||
e2c671ba RE |
14822 | j++; |
14823 | } | |
14824 | } | |
b111229a | 14825 | |
2c849145 | 14826 | par = emit_insn (par); |
f676971a | 14827 | |
d66437c5 | 14828 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 14829 | stack_pointer_rtx, |
d66437c5 | 14830 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
14831 | RTX_FRAME_RELATED_P (tmp) = 1; |
14832 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 14833 | |
bbbbb16a ILT |
14834 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
14835 | ||
2c849145 | 14836 | return par; |
b111229a RE |
14837 | } |
14838 | ||
4f5dfed0 | 14839 | /* Calculate the size of the return value that is passed in registers. */ |
466e4b7a | 14840 | static unsigned |
4f5dfed0 JC |
14841 | arm_size_return_regs (void) |
14842 | { | |
14843 | enum machine_mode mode; | |
14844 | ||
38173d38 JH |
14845 | if (crtl->return_rtx != 0) |
14846 | mode = GET_MODE (crtl->return_rtx); | |
4f5dfed0 JC |
14847 | else |
14848 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
14849 | ||
14850 | return GET_MODE_SIZE (mode); | |
14851 | } | |
14852 | ||
2c849145 | 14853 | static rtx |
e32bac5b | 14854 | emit_sfm (int base_reg, int count) |
b111229a RE |
14855 | { |
14856 | rtx par; | |
2c849145 JM |
14857 | rtx dwarf; |
14858 | rtx tmp, reg; | |
b111229a RE |
14859 | int i; |
14860 | ||
43cffd11 | 14861 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 14862 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
14863 | |
14864 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
14865 | |
14866 | XVECEXP (par, 0, 0) | |
f676971a | 14867 | = gen_rtx_SET (VOIDmode, |
9abf5d7b RR |
14868 | gen_frame_mem |
14869 | (BLKmode, | |
14870 | gen_rtx_PRE_MODIFY (Pmode, | |
14871 | stack_pointer_rtx, | |
14872 | plus_constant | |
14873 | (stack_pointer_rtx, | |
14874 | -12 * count)) | |
14875 | ), | |
43cffd11 | 14876 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 14877 | gen_rtvec (1, reg), |
b15bca31 | 14878 | UNSPEC_PUSH_MULT)); |
f676971a | 14879 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 14880 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 14881 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
14882 | XVECEXP (dwarf, 0, 1) = tmp; |
14883 | ||
b111229a | 14884 | for (i = 1; i < count; i++) |
2c849145 JM |
14885 | { |
14886 | reg = gen_rtx_REG (XFmode, base_reg++); | |
14887 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
14888 | ||
f676971a | 14889 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
14890 | gen_frame_mem (XFmode, |
14891 | plus_constant (stack_pointer_rtx, | |
14892 | i * 12)), | |
2c849145 JM |
14893 | reg); |
14894 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 14895 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 14896 | } |
b111229a | 14897 | |
8ee6eb4e PB |
14898 | tmp = gen_rtx_SET (VOIDmode, |
14899 | stack_pointer_rtx, | |
d66437c5 RE |
14900 | plus_constant (stack_pointer_rtx, -12 * count)); |
14901 | ||
8ee6eb4e PB |
14902 | RTX_FRAME_RELATED_P (tmp) = 1; |
14903 | XVECEXP (dwarf, 0, 0) = tmp; | |
14904 | ||
2c849145 | 14905 | par = emit_insn (par); |
bbbbb16a ILT |
14906 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
14907 | ||
2c849145 | 14908 | return par; |
e2c671ba RE |
14909 | } |
14910 | ||
9b66ebb1 | 14911 | |
3c7ad43e PB |
14912 | /* Return true if the current function needs to save/restore LR. */ |
14913 | ||
14914 | static bool | |
14915 | thumb_force_lr_save (void) | |
14916 | { | |
14917 | return !cfun->machine->lr_save_eliminated | |
14918 | && (!leaf_function_p () | |
14919 | || thumb_far_jump_used_p () | |
6fb5fa3c | 14920 | || df_regs_ever_live_p (LR_REGNUM)); |
3c7ad43e PB |
14921 | } |
14922 | ||
14923 | ||
095bb276 NC |
14924 | /* Compute the distance from register FROM to register TO. |
14925 | These can be the arg pointer (26), the soft frame pointer (25), | |
14926 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 14927 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
14928 | Typical stack layout looks like this: |
14929 | ||
14930 | old stack pointer -> | | | |
14931 | ---- | |
14932 | | | \ | |
14933 | | | saved arguments for | |
14934 | | | vararg functions | |
14935 | | | / | |
14936 | -- | |
14937 | hard FP & arg pointer -> | | \ | |
14938 | | | stack | |
14939 | | | frame | |
14940 | | | / | |
14941 | -- | |
14942 | | | \ | |
14943 | | | call saved | |
14944 | | | registers | |
14945 | soft frame pointer -> | | / | |
14946 | -- | |
14947 | | | \ | |
14948 | | | local | |
14949 | | | variables | |
2591db65 | 14950 | locals base pointer -> | | / |
095bb276 NC |
14951 | -- |
14952 | | | \ | |
14953 | | | outgoing | |
14954 | | | arguments | |
14955 | current stack pointer -> | | / | |
14956 | -- | |
14957 | ||
43aa4e05 | 14958 | For a given function some or all of these stack components |
095bb276 NC |
14959 | may not be needed, giving rise to the possibility of |
14960 | eliminating some of the registers. | |
14961 | ||
825dda42 | 14962 | The values returned by this function must reflect the behavior |
095bb276 NC |
14963 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
14964 | ||
14965 | The sign of the number returned reflects the direction of stack | |
14966 | growth, so the values are positive for all eliminations except | |
5848830f PB |
14967 | from the soft frame pointer to the hard frame pointer. |
14968 | ||
14969 | SFP may point just inside the local variables block to ensure correct | |
14970 | alignment. */ | |
14971 | ||
14972 | ||
14973 | /* Calculate stack offsets. These are used to calculate register elimination | |
954954d1 PB |
14974 | offsets and in prologue/epilogue code. Also calculates which registers |
14975 | should be saved. */ | |
5848830f PB |
14976 | |
14977 | static arm_stack_offsets * | |
14978 | arm_get_frame_offsets (void) | |
095bb276 | 14979 | { |
5848830f | 14980 | struct arm_stack_offsets *offsets; |
095bb276 | 14981 | unsigned long func_type; |
5848830f | 14982 | int leaf; |
5848830f | 14983 | int saved; |
954954d1 | 14984 | int core_saved; |
5848830f | 14985 | HOST_WIDE_INT frame_size; |
954954d1 | 14986 | int i; |
5848830f PB |
14987 | |
14988 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 14989 | |
5848830f PB |
14990 | /* We need to know if we are a leaf function. Unfortunately, it |
14991 | is possible to be called after start_sequence has been called, | |
14992 | which causes get_insns to return the insns for the sequence, | |
14993 | not the function, which will cause leaf_function_p to return | |
14994 | the incorrect result. | |
095bb276 | 14995 | |
5848830f PB |
14996 | to know about leaf functions once reload has completed, and the |
14997 | frame size cannot be changed after that time, so we can safely | |
14998 | use the cached value. */ | |
14999 | ||
15000 | if (reload_completed) | |
15001 | return offsets; | |
15002 | ||
666c27b9 KH |
15003 | /* Initially this is the size of the local variables. It will translated |
15004 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
15005 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
15006 | ||
15007 | leaf = leaf_function_p (); | |
15008 | ||
15009 | /* Space for variadic functions. */ | |
38173d38 | 15010 | offsets->saved_args = crtl->args.pretend_args_size; |
5848830f | 15011 | |
5b3e6663 | 15012 | /* In Thumb mode this is incorrect, but never used. */ |
35596784 AJ |
15013 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) + |
15014 | arm_compute_static_chain_stack_bytes(); | |
5848830f | 15015 | |
5b3e6663 | 15016 | if (TARGET_32BIT) |
095bb276 | 15017 | { |
5848830f | 15018 | unsigned int regno; |
ef7112de | 15019 | |
954954d1 PB |
15020 | offsets->saved_regs_mask = arm_compute_save_reg_mask (); |
15021 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
15022 | saved = core_saved; | |
5a9335ef | 15023 | |
5848830f PB |
15024 | /* We know that SP will be doubleword aligned on entry, and we must |
15025 | preserve that condition at any subroutine call. We also require the | |
15026 | soft frame pointer to be doubleword aligned. */ | |
15027 | ||
15028 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 15029 | { |
5848830f PB |
15030 | /* Check for the call-saved iWMMXt registers. */ |
15031 | for (regno = FIRST_IWMMXT_REGNUM; | |
15032 | regno <= LAST_IWMMXT_REGNUM; | |
15033 | regno++) | |
6fb5fa3c | 15034 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
15035 | saved += 8; |
15036 | } | |
15037 | ||
15038 | func_type = arm_current_func_type (); | |
15039 | if (! IS_VOLATILE (func_type)) | |
15040 | { | |
15041 | /* Space for saved FPA registers. */ | |
15042 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 15043 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
15044 | saved += 12; |
15045 | ||
15046 | /* Space for saved VFP registers. */ | |
15047 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 15048 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 15049 | } |
5848830f | 15050 | } |
5b3e6663 | 15051 | else /* TARGET_THUMB1 */ |
5848830f | 15052 | { |
954954d1 PB |
15053 | offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); |
15054 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
15055 | saved = core_saved; | |
5848830f | 15056 | if (TARGET_BACKTRACE) |
57934c39 | 15057 | saved += 16; |
5848830f | 15058 | } |
9b66ebb1 | 15059 | |
5848830f | 15060 | /* Saved registers include the stack frame. */ |
35596784 AJ |
15061 | offsets->saved_regs = offsets->saved_args + saved + |
15062 | arm_compute_static_chain_stack_bytes(); | |
a2503645 | 15063 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
15064 | /* A leaf function does not need any stack alignment if it has nothing |
15065 | on the stack. */ | |
15066 | if (leaf && frame_size == 0) | |
15067 | { | |
15068 | offsets->outgoing_args = offsets->soft_frame; | |
a3a531ec | 15069 | offsets->locals_base = offsets->soft_frame; |
5848830f PB |
15070 | return offsets; |
15071 | } | |
15072 | ||
15073 | /* Ensure SFP has the correct alignment. */ | |
15074 | if (ARM_DOUBLEWORD_ALIGN | |
15075 | && (offsets->soft_frame & 7)) | |
954954d1 PB |
15076 | { |
15077 | offsets->soft_frame += 4; | |
15078 | /* Try to align stack by pushing an extra reg. Don't bother doing this | |
15079 | when there is a stack frame as the alignment will be rolled into | |
15080 | the normal stack adjustment. */ | |
38173d38 | 15081 | if (frame_size + crtl->outgoing_args_size == 0) |
954954d1 PB |
15082 | { |
15083 | int reg = -1; | |
15084 | ||
55b2829b RE |
15085 | /* If it is safe to use r3, then do so. This sometimes |
15086 | generates better code on Thumb-2 by avoiding the need to | |
15087 | use 32-bit push/pop instructions. */ | |
15088 | if (!crtl->tail_call_emit | |
fb2f8cf8 JZ |
15089 | && arm_size_return_regs () <= 12 |
15090 | && (offsets->saved_regs_mask & (1 << 3)) == 0) | |
954954d1 | 15091 | { |
954954d1 PB |
15092 | reg = 3; |
15093 | } | |
55b2829b RE |
15094 | else |
15095 | for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) | |
15096 | { | |
15097 | if ((offsets->saved_regs_mask & (1 << i)) == 0) | |
15098 | { | |
15099 | reg = i; | |
15100 | break; | |
15101 | } | |
15102 | } | |
954954d1 PB |
15103 | |
15104 | if (reg != -1) | |
15105 | { | |
15106 | offsets->saved_regs += 4; | |
15107 | offsets->saved_regs_mask |= (1 << reg); | |
15108 | } | |
15109 | } | |
15110 | } | |
5848830f | 15111 | |
2591db65 RE |
15112 | offsets->locals_base = offsets->soft_frame + frame_size; |
15113 | offsets->outgoing_args = (offsets->locals_base | |
38173d38 | 15114 | + crtl->outgoing_args_size); |
5848830f PB |
15115 | |
15116 | if (ARM_DOUBLEWORD_ALIGN) | |
15117 | { | |
15118 | /* Ensure SP remains doubleword aligned. */ | |
15119 | if (offsets->outgoing_args & 7) | |
15120 | offsets->outgoing_args += 4; | |
e6d29d15 | 15121 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
15122 | } |
15123 | ||
5848830f PB |
15124 | return offsets; |
15125 | } | |
15126 | ||
15127 | ||
666c27b9 | 15128 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
15129 | offsets are in the direction of stack growth. */ |
15130 | ||
b3f8d95d | 15131 | HOST_WIDE_INT |
5848830f PB |
15132 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
15133 | { | |
15134 | arm_stack_offsets *offsets; | |
15135 | ||
15136 | offsets = arm_get_frame_offsets (); | |
095bb276 | 15137 | |
095bb276 NC |
15138 | /* OK, now we have enough information to compute the distances. |
15139 | There must be an entry in these switch tables for each pair | |
15140 | of registers in ELIMINABLE_REGS, even if some of the entries | |
15141 | seem to be redundant or useless. */ | |
15142 | switch (from) | |
15143 | { | |
15144 | case ARG_POINTER_REGNUM: | |
15145 | switch (to) | |
15146 | { | |
15147 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
15148 | return 0; | |
15149 | ||
15150 | case FRAME_POINTER_REGNUM: | |
15151 | /* This is the reverse of the soft frame pointer | |
15152 | to hard frame pointer elimination below. */ | |
5848830f | 15153 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
15154 | |
15155 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
35596784 AJ |
15156 | /* This is only non-zero in the case where the static chain register |
15157 | is stored above the frame. */ | |
15158 | return offsets->frame - offsets->saved_args - 4; | |
095bb276 NC |
15159 | |
15160 | case STACK_POINTER_REGNUM: | |
15161 | /* If nothing has been pushed on the stack at all | |
15162 | then this will return -4. This *is* correct! */ | |
5848830f | 15163 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
15164 | |
15165 | default: | |
e6d29d15 | 15166 | gcc_unreachable (); |
095bb276 | 15167 | } |
e6d29d15 | 15168 | gcc_unreachable (); |
095bb276 NC |
15169 | |
15170 | case FRAME_POINTER_REGNUM: | |
15171 | switch (to) | |
15172 | { | |
15173 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
15174 | return 0; | |
15175 | ||
15176 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
15177 | /* The hard frame pointer points to the top entry in the | |
15178 | stack frame. The soft frame pointer to the bottom entry | |
15179 | in the stack frame. If there is no stack frame at all, | |
15180 | then they are identical. */ | |
5848830f PB |
15181 | |
15182 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
15183 | |
15184 | case STACK_POINTER_REGNUM: | |
5848830f | 15185 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
15186 | |
15187 | default: | |
e6d29d15 | 15188 | gcc_unreachable (); |
095bb276 | 15189 | } |
e6d29d15 | 15190 | gcc_unreachable (); |
095bb276 NC |
15191 | |
15192 | default: | |
15193 | /* You cannot eliminate from the stack pointer. | |
15194 | In theory you could eliminate from the hard frame | |
15195 | pointer to the stack pointer, but this will never | |
15196 | happen, since if a stack frame is not needed the | |
15197 | hard frame pointer will never be used. */ | |
e6d29d15 | 15198 | gcc_unreachable (); |
095bb276 NC |
15199 | } |
15200 | } | |
15201 | ||
7b5cbb57 AS |
15202 | /* Given FROM and TO register numbers, say whether this elimination is |
15203 | allowed. Frame pointer elimination is automatically handled. | |
15204 | ||
15205 | All eliminations are permissible. Note that ARG_POINTER_REGNUM and | |
15206 | HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame | |
15207 | pointer, we must eliminate FRAME_POINTER_REGNUM into | |
15208 | HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or | |
15209 | ARG_POINTER_REGNUM. */ | |
15210 | ||
15211 | bool | |
15212 | arm_can_eliminate (const int from, const int to) | |
15213 | { | |
15214 | return ((to == FRAME_POINTER_REGNUM && from == ARG_POINTER_REGNUM) ? false : | |
15215 | (to == STACK_POINTER_REGNUM && frame_pointer_needed) ? false : | |
15216 | (to == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? false : | |
15217 | (to == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? false : | |
15218 | true); | |
15219 | } | |
0977774b | 15220 | |
7a085dce | 15221 | /* Emit RTL to save coprocessor registers on function entry. Returns the |
5b3e6663 PB |
15222 | number of bytes pushed. */ |
15223 | ||
15224 | static int | |
15225 | arm_save_coproc_regs(void) | |
15226 | { | |
15227 | int saved_size = 0; | |
15228 | unsigned reg; | |
15229 | unsigned start_reg; | |
15230 | rtx insn; | |
15231 | ||
15232 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) | |
6fb5fa3c | 15233 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
5b3e6663 | 15234 | { |
d8d55ac0 | 15235 | insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
5b3e6663 PB |
15236 | insn = gen_rtx_MEM (V2SImode, insn); |
15237 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); | |
15238 | RTX_FRAME_RELATED_P (insn) = 1; | |
15239 | saved_size += 8; | |
15240 | } | |
15241 | ||
15242 | /* Save any floating point call-saved registers used by this | |
15243 | function. */ | |
d79f3032 | 15244 | if (TARGET_FPA_EMU2) |
5b3e6663 PB |
15245 | { |
15246 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
6fb5fa3c | 15247 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 | 15248 | { |
d8d55ac0 | 15249 | insn = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); |
5b3e6663 PB |
15250 | insn = gen_rtx_MEM (XFmode, insn); |
15251 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); | |
15252 | RTX_FRAME_RELATED_P (insn) = 1; | |
15253 | saved_size += 12; | |
15254 | } | |
15255 | } | |
15256 | else | |
15257 | { | |
15258 | start_reg = LAST_FPA_REGNUM; | |
15259 | ||
15260 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
15261 | { | |
6fb5fa3c | 15262 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
15263 | { |
15264 | if (start_reg - reg == 3) | |
15265 | { | |
15266 | insn = emit_sfm (reg, 4); | |
15267 | RTX_FRAME_RELATED_P (insn) = 1; | |
15268 | saved_size += 48; | |
15269 | start_reg = reg - 1; | |
15270 | } | |
15271 | } | |
15272 | else | |
15273 | { | |
15274 | if (start_reg != reg) | |
15275 | { | |
15276 | insn = emit_sfm (reg + 1, start_reg - reg); | |
15277 | RTX_FRAME_RELATED_P (insn) = 1; | |
15278 | saved_size += (start_reg - reg) * 12; | |
15279 | } | |
15280 | start_reg = reg - 1; | |
15281 | } | |
15282 | } | |
15283 | ||
15284 | if (start_reg != reg) | |
15285 | { | |
15286 | insn = emit_sfm (reg + 1, start_reg - reg); | |
15287 | saved_size += (start_reg - reg) * 12; | |
15288 | RTX_FRAME_RELATED_P (insn) = 1; | |
15289 | } | |
15290 | } | |
15291 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
15292 | { | |
15293 | start_reg = FIRST_VFP_REGNUM; | |
15294 | ||
15295 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
15296 | { | |
6fb5fa3c DB |
15297 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
15298 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
5b3e6663 PB |
15299 | { |
15300 | if (start_reg != reg) | |
15301 | saved_size += vfp_emit_fstmd (start_reg, | |
15302 | (reg - start_reg) / 2); | |
15303 | start_reg = reg + 2; | |
15304 | } | |
15305 | } | |
15306 | if (start_reg != reg) | |
15307 | saved_size += vfp_emit_fstmd (start_reg, | |
15308 | (reg - start_reg) / 2); | |
15309 | } | |
15310 | return saved_size; | |
15311 | } | |
15312 | ||
15313 | ||
15314 | /* Set the Thumb frame pointer from the stack pointer. */ | |
15315 | ||
15316 | static void | |
15317 | thumb_set_frame_pointer (arm_stack_offsets *offsets) | |
15318 | { | |
15319 | HOST_WIDE_INT amount; | |
15320 | rtx insn, dwarf; | |
15321 | ||
15322 | amount = offsets->outgoing_args - offsets->locals_base; | |
15323 | if (amount < 1024) | |
15324 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15325 | stack_pointer_rtx, GEN_INT (amount))); | |
15326 | else | |
15327 | { | |
15328 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
f5c630c3 PB |
15329 | /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1 |
15330 | expects the first two operands to be the same. */ | |
15331 | if (TARGET_THUMB2) | |
15332 | { | |
15333 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15334 | stack_pointer_rtx, | |
15335 | hard_frame_pointer_rtx)); | |
15336 | } | |
15337 | else | |
15338 | { | |
15339 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15340 | hard_frame_pointer_rtx, | |
15341 | stack_pointer_rtx)); | |
15342 | } | |
5b3e6663 PB |
15343 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
15344 | plus_constant (stack_pointer_rtx, amount)); | |
15345 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 15346 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
15347 | } |
15348 | ||
15349 | RTX_FRAME_RELATED_P (insn) = 1; | |
15350 | } | |
15351 | ||
15352 | /* Generate the prologue instructions for entry into an ARM or Thumb-2 | |
15353 | function. */ | |
e2c671ba | 15354 | void |
e32bac5b | 15355 | arm_expand_prologue (void) |
e2c671ba | 15356 | { |
6d3d9133 | 15357 | rtx amount; |
2c849145 | 15358 | rtx insn; |
68dfd979 | 15359 | rtx ip_rtx; |
6d3d9133 NC |
15360 | unsigned long live_regs_mask; |
15361 | unsigned long func_type; | |
68dfd979 | 15362 | int fp_offset = 0; |
095bb276 | 15363 | int saved_pretend_args = 0; |
5848830f | 15364 | int saved_regs = 0; |
b9705a21 | 15365 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 15366 | arm_stack_offsets *offsets; |
d3236b4d | 15367 | |
6d3d9133 | 15368 | func_type = arm_current_func_type (); |
e2c671ba | 15369 | |
31fdb4d5 | 15370 | /* Naked functions don't have prologues. */ |
6d3d9133 | 15371 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
15372 | return; |
15373 | ||
095bb276 | 15374 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
38173d38 | 15375 | args_to_push = crtl->args.pretend_args_size; |
f676971a | 15376 | |
6d3d9133 | 15377 | /* Compute which register we will have to save onto the stack. */ |
954954d1 PB |
15378 | offsets = arm_get_frame_offsets (); |
15379 | live_regs_mask = offsets->saved_regs_mask; | |
e2c671ba | 15380 | |
68dfd979 | 15381 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 15382 | |
5b3e6663 PB |
15383 | if (IS_STACKALIGN (func_type)) |
15384 | { | |
15385 | rtx dwarf; | |
15386 | rtx r0; | |
15387 | rtx r1; | |
15388 | /* Handle a word-aligned stack pointer. We generate the following: | |
15389 | ||
15390 | mov r0, sp | |
15391 | bic r1, r0, #7 | |
15392 | mov sp, r1 | |
15393 | <save and restore r0 in normal prologue/epilogue> | |
15394 | mov sp, r0 | |
15395 | bx lr | |
15396 | ||
15397 | The unwinder doesn't need to know about the stack realignment. | |
15398 | Just tell it we saved SP in r0. */ | |
15399 | gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0); | |
15400 | ||
15401 | r0 = gen_rtx_REG (SImode, 0); | |
15402 | r1 = gen_rtx_REG (SImode, 1); | |
44bfa35b NF |
15403 | /* Use a real rtvec rather than NULL_RTVEC so the rest of the |
15404 | compiler won't choke. */ | |
15405 | dwarf = gen_rtx_UNSPEC (SImode, rtvec_alloc (0), UNSPEC_STACK_ALIGN); | |
5b3e6663 PB |
15406 | dwarf = gen_rtx_SET (VOIDmode, r0, dwarf); |
15407 | insn = gen_movsi (r0, stack_pointer_rtx); | |
15408 | RTX_FRAME_RELATED_P (insn) = 1; | |
bbbbb16a | 15409 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
15410 | emit_insn (insn); |
15411 | emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7))); | |
15412 | emit_insn (gen_movsi (stack_pointer_rtx, r1)); | |
15413 | } | |
15414 | ||
ec6237e4 PB |
15415 | /* For APCS frames, if IP register is clobbered |
15416 | when creating frame, save that register in a special | |
15417 | way. */ | |
15418 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) | |
e2c671ba | 15419 | { |
7b8b8ade NC |
15420 | if (IS_INTERRUPT (func_type)) |
15421 | { | |
15422 | /* Interrupt functions must not corrupt any registers. | |
15423 | Creating a frame pointer however, corrupts the IP | |
15424 | register, so we must push it first. */ | |
15425 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
15426 | |
15427 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
15428 | The dwarf stack unwinding code only wants to see one | |
15429 | stack decrement per function, and this is not it. If | |
15430 | this instruction is labeled as being part of the frame | |
15431 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 15432 | die when it encounters the assignment of IP to FP |
121308d4 NC |
15433 | later on, since the use of SP here establishes SP as |
15434 | the CFA register and not IP. | |
15435 | ||
15436 | Anyway this instruction is not really part of the stack | |
15437 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
15438 | } |
15439 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
15440 | { |
15441 | /* The Static chain register is the same as the IP register | |
15442 | used as a scratch register during stack frame creation. | |
15443 | To get around this need to find somewhere to store IP | |
15444 | whilst the frame is being created. We try the following | |
15445 | places in order: | |
f676971a | 15446 | |
6d3d9133 | 15447 | 1. The last argument register. |
68dfd979 NC |
15448 | 2. A slot on the stack above the frame. (This only |
15449 | works if the function is not a varargs function). | |
095bb276 NC |
15450 | 3. Register r3, after pushing the argument registers |
15451 | onto the stack. | |
6d3d9133 | 15452 | |
34ce3d7b JM |
15453 | Note - we only need to tell the dwarf2 backend about the SP |
15454 | adjustment in the second variant; the static chain register | |
15455 | doesn't need to be unwound, as it doesn't contain a value | |
15456 | inherited from the caller. */ | |
d3236b4d | 15457 | |
6fb5fa3c | 15458 | if (df_regs_ever_live_p (3) == false) |
d66437c5 | 15459 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 15460 | else if (args_to_push == 0) |
68dfd979 | 15461 | { |
f0b4bdd5 RE |
15462 | rtx dwarf; |
15463 | ||
35596784 AJ |
15464 | gcc_assert(arm_compute_static_chain_stack_bytes() == 4); |
15465 | saved_regs += 4; | |
15466 | ||
d66437c5 RE |
15467 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
15468 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 15469 | fp_offset = 4; |
34ce3d7b JM |
15470 | |
15471 | /* Just tell the dwarf backend that we adjusted SP. */ | |
15472 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
15473 | plus_constant (stack_pointer_rtx, |
15474 | -fp_offset)); | |
34ce3d7b | 15475 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 15476 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
68dfd979 NC |
15477 | } |
15478 | else | |
095bb276 NC |
15479 | { |
15480 | /* Store the args on the stack. */ | |
3cb66fd7 | 15481 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
15482 | insn = emit_multi_reg_push |
15483 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
15484 | else | |
15485 | insn = emit_insn | |
f676971a | 15486 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
15487 | GEN_INT (- args_to_push))); |
15488 | ||
15489 | RTX_FRAME_RELATED_P (insn) = 1; | |
15490 | ||
15491 | saved_pretend_args = 1; | |
15492 | fp_offset = args_to_push; | |
15493 | args_to_push = 0; | |
15494 | ||
15495 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 15496 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 15497 | } |
68dfd979 NC |
15498 | } |
15499 | ||
d66437c5 RE |
15500 | insn = emit_set_insn (ip_rtx, |
15501 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 15502 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
15503 | } |
15504 | ||
095bb276 | 15505 | if (args_to_push) |
e2c671ba | 15506 | { |
6d3d9133 | 15507 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 15508 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 15509 | insn = emit_multi_reg_push |
095bb276 | 15510 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 15511 | else |
2c849145 | 15512 | insn = emit_insn |
f676971a | 15513 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 15514 | GEN_INT (- args_to_push))); |
2c849145 | 15515 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
15516 | } |
15517 | ||
06bea5aa | 15518 | /* If this is an interrupt service routine, and the link register |
ec6237e4 PB |
15519 | is going to be pushed, and we're not generating extra |
15520 | push of IP (needed when frame is needed and frame layout if apcs), | |
06bea5aa NC |
15521 | subtracting four from LR now will mean that the function return |
15522 | can be done with a single instruction. */ | |
3a7731fd | 15523 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa | 15524 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
ec6237e4 | 15525 | && !(frame_pointer_needed && TARGET_APCS_FRAME) |
a15908a4 | 15526 | && TARGET_ARM) |
d66437c5 RE |
15527 | { |
15528 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
15529 | ||
15530 | emit_set_insn (lr, plus_constant (lr, -4)); | |
15531 | } | |
3a7731fd | 15532 | |
e2c671ba RE |
15533 | if (live_regs_mask) |
15534 | { | |
5848830f | 15535 | saved_regs += bit_count (live_regs_mask) * 4; |
954954d1 PB |
15536 | if (optimize_size && !frame_pointer_needed |
15537 | && saved_regs == offsets->saved_regs - offsets->saved_args) | |
15538 | { | |
15539 | /* If no coprocessor registers are being pushed and we don't have | |
15540 | to worry about a frame pointer then push extra registers to | |
15541 | create the stack frame. This is done is a way that does not | |
15542 | alter the frame layout, so is independent of the epilogue. */ | |
15543 | int n; | |
15544 | int frame; | |
15545 | n = 0; | |
15546 | while (n < 8 && (live_regs_mask & (1 << n)) == 0) | |
15547 | n++; | |
15548 | frame = offsets->outgoing_args - (offsets->saved_args + saved_regs); | |
15549 | if (frame && n * 4 >= frame) | |
15550 | { | |
15551 | n = frame / 4; | |
15552 | live_regs_mask |= (1 << n) - 1; | |
15553 | saved_regs += frame; | |
15554 | } | |
15555 | } | |
15556 | insn = emit_multi_reg_push (live_regs_mask); | |
2c849145 | 15557 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 15558 | } |
d5b7b3ae | 15559 | |
6d3d9133 | 15560 | if (! IS_VOLATILE (func_type)) |
5b3e6663 | 15561 | saved_regs += arm_save_coproc_regs (); |
b111229a | 15562 | |
5b3e6663 PB |
15563 | if (frame_pointer_needed && TARGET_ARM) |
15564 | { | |
15565 | /* Create the new frame pointer. */ | |
ec6237e4 | 15566 | if (TARGET_APCS_FRAME) |
9b66ebb1 | 15567 | { |
5b3e6663 PB |
15568 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
15569 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
15570 | RTX_FRAME_RELATED_P (insn) = 1; | |
9b66ebb1 | 15571 | |
5b3e6663 | 15572 | if (IS_NESTED (func_type)) |
9b66ebb1 | 15573 | { |
5b3e6663 | 15574 | /* Recover the static chain register. */ |
6fb5fa3c | 15575 | if (!df_regs_ever_live_p (3) |
5b3e6663 PB |
15576 | || saved_pretend_args) |
15577 | insn = gen_rtx_REG (SImode, 3); | |
38173d38 | 15578 | else /* if (crtl->args.pretend_args_size == 0) */ |
9b66ebb1 | 15579 | { |
5b3e6663 PB |
15580 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
15581 | insn = gen_frame_mem (SImode, insn); | |
9b66ebb1 | 15582 | } |
5b3e6663 PB |
15583 | emit_set_insn (ip_rtx, insn); |
15584 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
15585 | emit_insn (gen_prologue_use (ip_rtx)); | |
9b66ebb1 | 15586 | } |
68dfd979 | 15587 | } |
ec6237e4 PB |
15588 | else |
15589 | { | |
15590 | insn = GEN_INT (saved_regs - 4); | |
15591 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
15592 | stack_pointer_rtx, insn)); | |
15593 | RTX_FRAME_RELATED_P (insn) = 1; | |
15594 | } | |
2c849145 | 15595 | } |
e2c671ba | 15596 | |
5848830f | 15597 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) |
e2c671ba | 15598 | { |
745b9093 JM |
15599 | /* This add can produce multiple insns for a large constant, so we |
15600 | need to get tricky. */ | |
15601 | rtx last = get_last_insn (); | |
5848830f PB |
15602 | |
15603 | amount = GEN_INT (offsets->saved_args + saved_regs | |
15604 | - offsets->outgoing_args); | |
15605 | ||
2c849145 JM |
15606 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
15607 | amount)); | |
745b9093 JM |
15608 | do |
15609 | { | |
15610 | last = last ? NEXT_INSN (last) : get_insns (); | |
15611 | RTX_FRAME_RELATED_P (last) = 1; | |
15612 | } | |
15613 | while (last != insn); | |
e04c2d6c RE |
15614 | |
15615 | /* If the frame pointer is needed, emit a special barrier that | |
15616 | will prevent the scheduler from moving stores to the frame | |
15617 | before the stack adjustment. */ | |
15618 | if (frame_pointer_needed) | |
3894f59e RE |
15619 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
15620 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
15621 | } |
15622 | ||
876f13b0 | 15623 | |
5b3e6663 PB |
15624 | if (frame_pointer_needed && TARGET_THUMB2) |
15625 | thumb_set_frame_pointer (offsets); | |
15626 | ||
020a4035 | 15627 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
5b3e6663 PB |
15628 | { |
15629 | unsigned long mask; | |
15630 | ||
15631 | mask = live_regs_mask; | |
15632 | mask &= THUMB2_WORK_REGS; | |
15633 | if (!IS_NESTED (func_type)) | |
15634 | mask |= (1 << IP_REGNUM); | |
15635 | arm_load_pic_register (mask); | |
15636 | } | |
876f13b0 | 15637 | |
e2c671ba | 15638 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 15639 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
15640 | scheduling in the prolog. Similarly if we want non-call exceptions |
15641 | using the EABI unwinder, to prevent faulting instructions from being | |
15642 | swapped with a stack adjustment. */ | |
e3b5732b | 15643 | if (crtl->profile || !TARGET_SCHED_PROLOG |
8f4f502f | 15644 | || (ARM_EABI_UNWIND_TABLES && cfun->can_throw_non_call_exceptions)) |
e2c671ba | 15645 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
15646 | |
15647 | /* If the link register is being kept alive, with the return address in it, | |
15648 | then make sure that it does not get reused by the ce2 pass. */ | |
15649 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
6fb5fa3c | 15650 | cfun->machine->lr_save_eliminated = 1; |
e2c671ba | 15651 | } |
cce8749e | 15652 | \f |
5b3e6663 PB |
15653 | /* Print condition code to STREAM. Helper function for arm_print_operand. */ |
15654 | static void | |
15655 | arm_print_condition (FILE *stream) | |
15656 | { | |
15657 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
15658 | { | |
15659 | /* Branch conversion is not implemented for Thumb-2. */ | |
15660 | if (TARGET_THUMB) | |
15661 | { | |
15662 | output_operand_lossage ("predicated Thumb instruction"); | |
15663 | return; | |
15664 | } | |
15665 | if (current_insn_predicate != NULL) | |
15666 | { | |
15667 | output_operand_lossage | |
15668 | ("predicated instruction in conditional sequence"); | |
15669 | return; | |
15670 | } | |
15671 | ||
15672 | fputs (arm_condition_codes[arm_current_cc], stream); | |
15673 | } | |
15674 | else if (current_insn_predicate) | |
15675 | { | |
15676 | enum arm_cond_code code; | |
15677 | ||
15678 | if (TARGET_THUMB1) | |
15679 | { | |
15680 | output_operand_lossage ("predicated Thumb instruction"); | |
15681 | return; | |
15682 | } | |
15683 | ||
15684 | code = get_arm_condition_code (current_insn_predicate); | |
15685 | fputs (arm_condition_codes[code], stream); | |
15686 | } | |
15687 | } | |
15688 | ||
15689 | ||
9997d19d RE |
15690 | /* If CODE is 'd', then the X is a condition operand and the instruction |
15691 | should only be executed if the condition is true. | |
ddd5a7c1 | 15692 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
15693 | should only be executed if the condition is false: however, if the mode |
15694 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
15695 | do this because in these circumstances !GE does not necessarily imply LT; | |
15696 | in these cases the instruction pattern will take care to make sure that | |
15697 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 15698 | doing this instruction unconditionally. |
9997d19d RE |
15699 | If CODE is 'N' then X is a floating point operand that must be negated |
15700 | before output. | |
15701 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
15702 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
944442bb | 15703 | static void |
e32bac5b | 15704 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
15705 | { |
15706 | switch (code) | |
15707 | { | |
15708 | case '@': | |
f3139301 | 15709 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
15710 | return; |
15711 | ||
d5b7b3ae RE |
15712 | case '_': |
15713 | fputs (user_label_prefix, stream); | |
15714 | return; | |
f676971a | 15715 | |
9997d19d | 15716 | case '|': |
f3139301 | 15717 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
15718 | return; |
15719 | ||
15720 | case '?': | |
5b3e6663 PB |
15721 | arm_print_condition (stream); |
15722 | return; | |
cca0a211 | 15723 | |
5b3e6663 PB |
15724 | case '(': |
15725 | /* Nothing in unified syntax, otherwise the current condition code. */ | |
15726 | if (!TARGET_UNIFIED_ASM) | |
15727 | arm_print_condition (stream); | |
15728 | break; | |
15729 | ||
15730 | case ')': | |
15731 | /* The current condition code in unified syntax, otherwise nothing. */ | |
15732 | if (TARGET_UNIFIED_ASM) | |
15733 | arm_print_condition (stream); | |
15734 | break; | |
15735 | ||
15736 | case '.': | |
15737 | /* The current condition code for a condition code setting instruction. | |
7a085dce | 15738 | Preceded by 's' in unified syntax, otherwise followed by 's'. */ |
5b3e6663 PB |
15739 | if (TARGET_UNIFIED_ASM) |
15740 | { | |
15741 | fputc('s', stream); | |
15742 | arm_print_condition (stream); | |
cca0a211 | 15743 | } |
5b3e6663 | 15744 | else |
cca0a211 | 15745 | { |
5b3e6663 PB |
15746 | arm_print_condition (stream); |
15747 | fputc('s', stream); | |
cca0a211 | 15748 | } |
9997d19d RE |
15749 | return; |
15750 | ||
5b3e6663 PB |
15751 | case '!': |
15752 | /* If the instruction is conditionally executed then print | |
15753 | the current condition code, otherwise print 's'. */ | |
15754 | gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM); | |
15755 | if (current_insn_predicate) | |
15756 | arm_print_condition (stream); | |
15757 | else | |
15758 | fputc('s', stream); | |
15759 | break; | |
15760 | ||
88f77cba | 15761 | /* %# is a "break" sequence. It doesn't output anything, but is used to |
cea618ac | 15762 | separate e.g. operand numbers from following text, if that text consists |
88f77cba JB |
15763 | of further digits which we don't want to be part of the operand |
15764 | number. */ | |
15765 | case '#': | |
15766 | return; | |
15767 | ||
9997d19d RE |
15768 | case 'N': |
15769 | { | |
15770 | REAL_VALUE_TYPE r; | |
15771 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
d49b6e1e | 15772 | r = real_value_negate (&r); |
9997d19d RE |
15773 | fprintf (stream, "%s", fp_const_from_val (&r)); |
15774 | } | |
15775 | return; | |
15776 | ||
571191af | 15777 | /* An integer or symbol address without a preceding # sign. */ |
88f77cba | 15778 | case 'c': |
571191af PB |
15779 | switch (GET_CODE (x)) |
15780 | { | |
15781 | case CONST_INT: | |
15782 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
15783 | break; | |
15784 | ||
15785 | case SYMBOL_REF: | |
15786 | output_addr_const (stream, x); | |
15787 | break; | |
15788 | ||
15789 | default: | |
15790 | gcc_unreachable (); | |
15791 | } | |
88f77cba JB |
15792 | return; |
15793 | ||
9997d19d RE |
15794 | case 'B': |
15795 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
15796 | { |
15797 | HOST_WIDE_INT val; | |
5895f793 | 15798 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 15799 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 15800 | } |
9997d19d RE |
15801 | else |
15802 | { | |
15803 | putc ('~', stream); | |
15804 | output_addr_const (stream, x); | |
15805 | } | |
15806 | return; | |
15807 | ||
5b3e6663 PB |
15808 | case 'L': |
15809 | /* The low 16 bits of an immediate constant. */ | |
15810 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); | |
15811 | return; | |
15812 | ||
9997d19d RE |
15813 | case 'i': |
15814 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
15815 | return; | |
15816 | ||
9b6b54e2 NC |
15817 | /* Truncate Cirrus shift counts. */ |
15818 | case 's': | |
15819 | if (GET_CODE (x) == CONST_INT) | |
15820 | { | |
15821 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
15822 | return; | |
15823 | } | |
15824 | arm_print_operand (stream, x, 0); | |
15825 | return; | |
15826 | ||
9997d19d RE |
15827 | case 'I': |
15828 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
15829 | return; | |
15830 | ||
15831 | case 'S': | |
15832 | { | |
15833 | HOST_WIDE_INT val; | |
beed32b8 RE |
15834 | const char *shift; |
15835 | ||
15836 | if (!shift_operator (x, SImode)) | |
15837 | { | |
15838 | output_operand_lossage ("invalid shift operand"); | |
15839 | break; | |
15840 | } | |
15841 | ||
15842 | shift = shift_op (x, &val); | |
9997d19d | 15843 | |
e2c671ba RE |
15844 | if (shift) |
15845 | { | |
beed32b8 | 15846 | fprintf (stream, ", %s ", shift); |
e2c671ba RE |
15847 | if (val == -1) |
15848 | arm_print_operand (stream, XEXP (x, 1), 0); | |
15849 | else | |
4a0a75dd | 15850 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 15851 | } |
9997d19d RE |
15852 | } |
15853 | return; | |
15854 | ||
d5b7b3ae | 15855 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 15856 | |
d5b7b3ae RE |
15857 | In a pair of registers containing a DI or DF value the 'Q' |
15858 | operand returns the register number of the register containing | |
093354e0 | 15859 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
15860 | the register number of the register containing the most |
15861 | significant part of the value. | |
f676971a | 15862 | |
d5b7b3ae RE |
15863 | The 'H' operand returns the higher of the two register numbers. |
15864 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 15865 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
15866 | value is held in the lower number register. The reverse is true |
15867 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 15868 | |
d5b7b3ae RE |
15869 | The purpose of these operands is to distinguish between cases |
15870 | where the endian-ness of the values is important (for example | |
15871 | when they are added together), and cases where the endian-ness | |
15872 | is irrelevant, but the order of register operations is important. | |
15873 | For example when loading a value from memory into a register | |
15874 | pair, the endian-ness does not matter. Provided that the value | |
15875 | from the lower memory address is put into the lower numbered | |
15876 | register, and the value from the higher address is put into the | |
15877 | higher numbered register, the load will work regardless of whether | |
15878 | the value being loaded is big-wordian or little-wordian. The | |
15879 | order of the two register loads can matter however, if the address | |
15880 | of the memory location is actually held in one of the registers | |
73160ba9 DJ |
15881 | being overwritten by the load. |
15882 | ||
15883 | The 'Q' and 'R' constraints are also available for 64-bit | |
15884 | constants. */ | |
c1c2bc04 | 15885 | case 'Q': |
73160ba9 DJ |
15886 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
15887 | { | |
15888 | rtx part = gen_lowpart (SImode, x); | |
15889 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | |
15890 | return; | |
15891 | } | |
15892 | ||
22de4c3d RE |
15893 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
15894 | { | |
15895 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15896 | return; | |
15897 | } | |
15898 | ||
d5b7b3ae | 15899 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
15900 | return; |
15901 | ||
9997d19d | 15902 | case 'R': |
73160ba9 DJ |
15903 | if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) |
15904 | { | |
15905 | enum machine_mode mode = GET_MODE (x); | |
15906 | rtx part; | |
15907 | ||
15908 | if (mode == VOIDmode) | |
15909 | mode = DImode; | |
15910 | part = gen_highpart_mode (SImode, mode, x); | |
15911 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part)); | |
15912 | return; | |
15913 | } | |
15914 | ||
22de4c3d RE |
15915 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
15916 | { | |
15917 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15918 | return; | |
15919 | } | |
15920 | ||
d5b7b3ae RE |
15921 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
15922 | return; | |
15923 | ||
15924 | case 'H': | |
22de4c3d RE |
15925 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
15926 | { | |
15927 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15928 | return; | |
15929 | } | |
15930 | ||
d5b7b3ae | 15931 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
15932 | return; |
15933 | ||
88f77cba JB |
15934 | case 'J': |
15935 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
15936 | { | |
15937 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15938 | return; | |
15939 | } | |
15940 | ||
15941 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); | |
15942 | return; | |
15943 | ||
15944 | case 'K': | |
15945 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
15946 | { | |
15947 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15948 | return; | |
15949 | } | |
15950 | ||
15951 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); | |
15952 | return; | |
15953 | ||
9997d19d | 15954 | case 'm': |
f676971a | 15955 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
15956 | GET_CODE (XEXP (x, 0)) == REG |
15957 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
15958 | return; |
15959 | ||
15960 | case 'M': | |
dd18ae56 | 15961 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 15962 | REGNO (x), |
e9d7b180 | 15963 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
15964 | return; |
15965 | ||
88f77cba JB |
15966 | /* Like 'M', but writing doubleword vector registers, for use by Neon |
15967 | insns. */ | |
15968 | case 'h': | |
15969 | { | |
15970 | int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; | |
15971 | int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; | |
15972 | if (numregs == 1) | |
15973 | asm_fprintf (stream, "{d%d}", regno); | |
15974 | else | |
15975 | asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); | |
15976 | } | |
15977 | return; | |
15978 | ||
9997d19d | 15979 | case 'd': |
64e92a26 RE |
15980 | /* CONST_TRUE_RTX means always -- that's the default. */ |
15981 | if (x == const_true_rtx) | |
d5b7b3ae | 15982 | return; |
f676971a | 15983 | |
22de4c3d RE |
15984 | if (!COMPARISON_P (x)) |
15985 | { | |
15986 | output_operand_lossage ("invalid operand for code '%c'", code); | |
15987 | return; | |
15988 | } | |
15989 | ||
defc0463 RE |
15990 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
15991 | stream); | |
9997d19d RE |
15992 | return; |
15993 | ||
15994 | case 'D': | |
112cdef5 | 15995 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
15996 | want to do that. */ |
15997 | if (x == const_true_rtx) | |
22de4c3d | 15998 | { |
4dad0aca | 15999 | output_operand_lossage ("instruction never executed"); |
22de4c3d RE |
16000 | return; |
16001 | } | |
16002 | if (!COMPARISON_P (x)) | |
16003 | { | |
16004 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16005 | return; | |
16006 | } | |
d5b7b3ae | 16007 | |
defc0463 RE |
16008 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
16009 | (get_arm_condition_code (x))], | |
16010 | stream); | |
9997d19d RE |
16011 | return; |
16012 | ||
9b6b54e2 NC |
16013 | /* Cirrus registers can be accessed in a variety of ways: |
16014 | single floating point (f) | |
16015 | double floating point (d) | |
16016 | 32bit integer (fx) | |
16017 | 64bit integer (dx). */ | |
16018 | case 'W': /* Cirrus register in F mode. */ | |
16019 | case 'X': /* Cirrus register in D mode. */ | |
16020 | case 'Y': /* Cirrus register in FX mode. */ | |
16021 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
16022 | gcc_assert (GET_CODE (x) == REG |
16023 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
16024 | |
16025 | fprintf (stream, "mv%s%s", | |
16026 | code == 'W' ? "f" | |
16027 | : code == 'X' ? "d" | |
16028 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
16029 | ||
16030 | return; | |
16031 | ||
16032 | /* Print cirrus register in the mode specified by the register's mode. */ | |
16033 | case 'V': | |
16034 | { | |
16035 | int mode = GET_MODE (x); | |
16036 | ||
16037 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
16038 | { |
16039 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16040 | return; | |
16041 | } | |
9b6b54e2 NC |
16042 | |
16043 | fprintf (stream, "mv%s%s", | |
16044 | mode == DFmode ? "d" | |
16045 | : mode == SImode ? "fx" | |
16046 | : mode == DImode ? "dx" | |
16047 | : "f", reg_names[REGNO (x)] + 2); | |
16048 | ||
16049 | return; | |
16050 | } | |
16051 | ||
5a9335ef NC |
16052 | case 'U': |
16053 | if (GET_CODE (x) != REG | |
16054 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
16055 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
16056 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
16057 | { |
16058 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16059 | return; | |
16060 | } | |
16061 | ||
5a9335ef NC |
16062 | else |
16063 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
16064 | return; | |
16065 | ||
16066 | /* Print an iWMMXt control register name. */ | |
16067 | case 'w': | |
16068 | if (GET_CODE (x) != CONST_INT | |
16069 | || INTVAL (x) < 0 | |
16070 | || INTVAL (x) >= 16) | |
16071 | /* Bad value for wC register number. */ | |
22de4c3d RE |
16072 | { |
16073 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16074 | return; | |
16075 | } | |
16076 | ||
5a9335ef NC |
16077 | else |
16078 | { | |
16079 | static const char * wc_reg_names [16] = | |
16080 | { | |
16081 | "wCID", "wCon", "wCSSF", "wCASF", | |
16082 | "wC4", "wC5", "wC6", "wC7", | |
16083 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
16084 | "wC12", "wC13", "wC14", "wC15" | |
16085 | }; | |
f676971a | 16086 | |
5a9335ef NC |
16087 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
16088 | } | |
16089 | return; | |
16090 | ||
e0dc3601 PB |
16091 | /* Print the high single-precision register of a VFP double-precision |
16092 | register. */ | |
16093 | case 'p': | |
16094 | { | |
16095 | int mode = GET_MODE (x); | |
16096 | int regno; | |
16097 | ||
16098 | if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG) | |
16099 | { | |
16100 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16101 | return; | |
16102 | } | |
16103 | ||
16104 | regno = REGNO (x); | |
16105 | if (!VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
16106 | { | |
16107 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16108 | return; | |
16109 | } | |
16110 | ||
16111 | fprintf (stream, "s%d", regno - FIRST_VFP_REGNUM + 1); | |
16112 | } | |
16113 | return; | |
16114 | ||
88f77cba | 16115 | /* Print a VFP/Neon double precision or quad precision register name. */ |
9b66ebb1 | 16116 | case 'P': |
88f77cba | 16117 | case 'q': |
9b66ebb1 PB |
16118 | { |
16119 | int mode = GET_MODE (x); | |
88f77cba JB |
16120 | int is_quad = (code == 'q'); |
16121 | int regno; | |
9b66ebb1 | 16122 | |
88f77cba | 16123 | if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) |
22de4c3d RE |
16124 | { |
16125 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16126 | return; | |
16127 | } | |
9b66ebb1 PB |
16128 | |
16129 | if (GET_CODE (x) != REG | |
16130 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
16131 | { |
16132 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16133 | return; | |
16134 | } | |
9b66ebb1 | 16135 | |
88f77cba JB |
16136 | regno = REGNO (x); |
16137 | if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) | |
16138 | || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) | |
22de4c3d RE |
16139 | { |
16140 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16141 | return; | |
16142 | } | |
9b66ebb1 | 16143 | |
88f77cba JB |
16144 | fprintf (stream, "%c%d", is_quad ? 'q' : 'd', |
16145 | (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); | |
16146 | } | |
16147 | return; | |
16148 | ||
16149 | /* These two codes print the low/high doubleword register of a Neon quad | |
16150 | register, respectively. For pair-structure types, can also print | |
16151 | low/high quadword registers. */ | |
16152 | case 'e': | |
16153 | case 'f': | |
16154 | { | |
16155 | int mode = GET_MODE (x); | |
16156 | int regno; | |
16157 | ||
16158 | if ((GET_MODE_SIZE (mode) != 16 | |
16159 | && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) | |
16160 | { | |
16161 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16162 | return; | |
16163 | } | |
16164 | ||
16165 | regno = REGNO (x); | |
16166 | if (!NEON_REGNO_OK_FOR_QUAD (regno)) | |
16167 | { | |
16168 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16169 | return; | |
16170 | } | |
16171 | ||
16172 | if (GET_MODE_SIZE (mode) == 16) | |
16173 | fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) | |
16174 | + (code == 'f' ? 1 : 0)); | |
16175 | else | |
16176 | fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) | |
16177 | + (code == 'f' ? 1 : 0)); | |
9b66ebb1 PB |
16178 | } |
16179 | return; | |
16180 | ||
f1adb0a9 JB |
16181 | /* Print a VFPv3 floating-point constant, represented as an integer |
16182 | index. */ | |
16183 | case 'G': | |
16184 | { | |
16185 | int index = vfp3_const_double_index (x); | |
16186 | gcc_assert (index != -1); | |
16187 | fprintf (stream, "%d", index); | |
16188 | } | |
16189 | return; | |
16190 | ||
88f77cba JB |
16191 | /* Print bits representing opcode features for Neon. |
16192 | ||
16193 | Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed | |
16194 | and polynomials as unsigned. | |
16195 | ||
16196 | Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. | |
16197 | ||
16198 | Bit 2 is 1 for rounding functions, 0 otherwise. */ | |
16199 | ||
16200 | /* Identify the type as 's', 'u', 'p' or 'f'. */ | |
16201 | case 'T': | |
16202 | { | |
16203 | HOST_WIDE_INT bits = INTVAL (x); | |
16204 | fputc ("uspf"[bits & 3], stream); | |
16205 | } | |
16206 | return; | |
16207 | ||
16208 | /* Likewise, but signed and unsigned integers are both 'i'. */ | |
16209 | case 'F': | |
16210 | { | |
16211 | HOST_WIDE_INT bits = INTVAL (x); | |
16212 | fputc ("iipf"[bits & 3], stream); | |
16213 | } | |
16214 | return; | |
16215 | ||
16216 | /* As for 'T', but emit 'u' instead of 'p'. */ | |
16217 | case 't': | |
16218 | { | |
16219 | HOST_WIDE_INT bits = INTVAL (x); | |
16220 | fputc ("usuf"[bits & 3], stream); | |
16221 | } | |
16222 | return; | |
16223 | ||
16224 | /* Bit 2: rounding (vs none). */ | |
16225 | case 'O': | |
16226 | { | |
16227 | HOST_WIDE_INT bits = INTVAL (x); | |
16228 | fputs ((bits & 4) != 0 ? "r" : "", stream); | |
16229 | } | |
16230 | return; | |
16231 | ||
dc34db56 PB |
16232 | /* Memory operand for vld1/vst1 instruction. */ |
16233 | case 'A': | |
16234 | { | |
16235 | rtx addr; | |
16236 | bool postinc = FALSE; | |
16237 | gcc_assert (GET_CODE (x) == MEM); | |
16238 | addr = XEXP (x, 0); | |
16239 | if (GET_CODE (addr) == POST_INC) | |
16240 | { | |
16241 | postinc = 1; | |
16242 | addr = XEXP (addr, 0); | |
16243 | } | |
16244 | asm_fprintf (stream, "[%r]", REGNO (addr)); | |
16245 | if (postinc) | |
16246 | fputs("!", stream); | |
16247 | } | |
16248 | return; | |
16249 | ||
814a4c3b DJ |
16250 | /* Translate an S register number into a D register number and element index. */ |
16251 | case 'y': | |
16252 | { | |
16253 | int mode = GET_MODE (x); | |
16254 | int regno; | |
16255 | ||
16256 | if (GET_MODE_SIZE (mode) != 4 || GET_CODE (x) != REG) | |
16257 | { | |
16258 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16259 | return; | |
16260 | } | |
16261 | ||
16262 | regno = REGNO (x); | |
16263 | if (!VFP_REGNO_OK_FOR_SINGLE (regno)) | |
16264 | { | |
16265 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16266 | return; | |
16267 | } | |
16268 | ||
16269 | regno = regno - FIRST_VFP_REGNUM; | |
16270 | fprintf (stream, "d%d[%d]", regno / 2, regno % 2); | |
16271 | } | |
16272 | return; | |
16273 | ||
0fd8c3ad SL |
16274 | /* Register specifier for vld1.16/vst1.16. Translate the S register |
16275 | number into a D register number and element index. */ | |
16276 | case 'z': | |
16277 | { | |
16278 | int mode = GET_MODE (x); | |
16279 | int regno; | |
16280 | ||
16281 | if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG) | |
16282 | { | |
16283 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16284 | return; | |
16285 | } | |
16286 | ||
16287 | regno = REGNO (x); | |
16288 | if (!VFP_REGNO_OK_FOR_SINGLE (regno)) | |
16289 | { | |
16290 | output_operand_lossage ("invalid operand for code '%c'", code); | |
16291 | return; | |
16292 | } | |
16293 | ||
16294 | regno = regno - FIRST_VFP_REGNUM; | |
16295 | fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0)); | |
16296 | } | |
16297 | return; | |
16298 | ||
9997d19d RE |
16299 | default: |
16300 | if (x == 0) | |
22de4c3d RE |
16301 | { |
16302 | output_operand_lossage ("missing operand"); | |
16303 | return; | |
16304 | } | |
9997d19d | 16305 | |
e6d29d15 | 16306 | switch (GET_CODE (x)) |
9997d19d | 16307 | { |
e6d29d15 NS |
16308 | case REG: |
16309 | asm_fprintf (stream, "%r", REGNO (x)); | |
16310 | break; | |
16311 | ||
16312 | case MEM: | |
9997d19d RE |
16313 | output_memory_reference_mode = GET_MODE (x); |
16314 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
16315 | break; |
16316 | ||
16317 | case CONST_DOUBLE: | |
88f77cba JB |
16318 | if (TARGET_NEON) |
16319 | { | |
16320 | char fpstr[20]; | |
16321 | real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), | |
16322 | sizeof (fpstr), 0, 1); | |
16323 | fprintf (stream, "#%s", fpstr); | |
16324 | } | |
16325 | else | |
16326 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
e6d29d15 NS |
16327 | break; |
16328 | ||
16329 | default: | |
16330 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d | 16331 | fputc ('#', stream); |
d58bc084 NS |
16332 | if (GET_CODE (x) == HIGH) |
16333 | { | |
16334 | fputs (":lower16:", stream); | |
16335 | x = XEXP (x, 0); | |
16336 | } | |
16337 | ||
9997d19d | 16338 | output_addr_const (stream, x); |
e6d29d15 | 16339 | break; |
9997d19d RE |
16340 | } |
16341 | } | |
16342 | } | |
cce8749e | 16343 | \f |
944442bb NF |
16344 | /* Target hook for printing a memory address. */ |
16345 | static void | |
16346 | arm_print_operand_address (FILE *stream, rtx x) | |
16347 | { | |
16348 | if (TARGET_32BIT) | |
16349 | { | |
16350 | int is_minus = GET_CODE (x) == MINUS; | |
16351 | ||
16352 | if (GET_CODE (x) == REG) | |
16353 | asm_fprintf (stream, "[%r, #0]", REGNO (x)); | |
16354 | else if (GET_CODE (x) == PLUS || is_minus) | |
16355 | { | |
16356 | rtx base = XEXP (x, 0); | |
16357 | rtx index = XEXP (x, 1); | |
16358 | HOST_WIDE_INT offset = 0; | |
16359 | if (GET_CODE (base) != REG | |
16360 | || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) | |
16361 | { | |
16362 | /* Ensure that BASE is a register. */ | |
16363 | /* (one of them must be). */ | |
16364 | /* Also ensure the SP is not used as in index register. */ | |
16365 | rtx temp = base; | |
16366 | base = index; | |
16367 | index = temp; | |
16368 | } | |
16369 | switch (GET_CODE (index)) | |
16370 | { | |
16371 | case CONST_INT: | |
16372 | offset = INTVAL (index); | |
16373 | if (is_minus) | |
16374 | offset = -offset; | |
16375 | asm_fprintf (stream, "[%r, #%wd]", | |
16376 | REGNO (base), offset); | |
16377 | break; | |
16378 | ||
16379 | case REG: | |
16380 | asm_fprintf (stream, "[%r, %s%r]", | |
16381 | REGNO (base), is_minus ? "-" : "", | |
16382 | REGNO (index)); | |
16383 | break; | |
16384 | ||
16385 | case MULT: | |
16386 | case ASHIFTRT: | |
16387 | case LSHIFTRT: | |
16388 | case ASHIFT: | |
16389 | case ROTATERT: | |
16390 | { | |
16391 | asm_fprintf (stream, "[%r, %s%r", | |
16392 | REGNO (base), is_minus ? "-" : "", | |
16393 | REGNO (XEXP (index, 0))); | |
16394 | arm_print_operand (stream, index, 'S'); | |
16395 | fputs ("]", stream); | |
16396 | break; | |
16397 | } | |
16398 | ||
16399 | default: | |
16400 | gcc_unreachable (); | |
16401 | } | |
16402 | } | |
16403 | else if (GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_INC | |
16404 | || GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_DEC) | |
16405 | { | |
16406 | extern enum machine_mode output_memory_reference_mode; | |
16407 | ||
16408 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); | |
16409 | ||
16410 | if (GET_CODE (x) == PRE_DEC || GET_CODE (x) == PRE_INC) | |
16411 | asm_fprintf (stream, "[%r, #%s%d]!", | |
16412 | REGNO (XEXP (x, 0)), | |
16413 | GET_CODE (x) == PRE_DEC ? "-" : "", | |
16414 | GET_MODE_SIZE (output_memory_reference_mode)); | |
16415 | else | |
16416 | asm_fprintf (stream, "[%r], #%s%d", | |
16417 | REGNO (XEXP (x, 0)), | |
16418 | GET_CODE (x) == POST_DEC ? "-" : "", | |
16419 | GET_MODE_SIZE (output_memory_reference_mode)); | |
16420 | } | |
16421 | else if (GET_CODE (x) == PRE_MODIFY) | |
16422 | { | |
16423 | asm_fprintf (stream, "[%r, ", REGNO (XEXP (x, 0))); | |
16424 | if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
16425 | asm_fprintf (stream, "#%wd]!", | |
16426 | INTVAL (XEXP (XEXP (x, 1), 1))); | |
16427 | else | |
16428 | asm_fprintf (stream, "%r]!", | |
16429 | REGNO (XEXP (XEXP (x, 1), 1))); | |
16430 | } | |
16431 | else if (GET_CODE (x) == POST_MODIFY) | |
16432 | { | |
16433 | asm_fprintf (stream, "[%r], ", REGNO (XEXP (x, 0))); | |
16434 | if (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
16435 | asm_fprintf (stream, "#%wd", | |
16436 | INTVAL (XEXP (XEXP (x, 1), 1))); | |
16437 | else | |
16438 | asm_fprintf (stream, "%r", | |
16439 | REGNO (XEXP (XEXP (x, 1), 1))); | |
16440 | } | |
16441 | else output_addr_const (stream, x); | |
16442 | } | |
16443 | else | |
16444 | { | |
16445 | if (GET_CODE (x) == REG) | |
16446 | asm_fprintf (stream, "[%r]", REGNO (x)); | |
16447 | else if (GET_CODE (x) == POST_INC) | |
16448 | asm_fprintf (stream, "%r!", REGNO (XEXP (x, 0))); | |
16449 | else if (GET_CODE (x) == PLUS) | |
16450 | { | |
16451 | gcc_assert (GET_CODE (XEXP (x, 0)) == REG); | |
16452 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
16453 | asm_fprintf (stream, "[%r, #%wd]", | |
16454 | REGNO (XEXP (x, 0)), | |
16455 | INTVAL (XEXP (x, 1))); | |
16456 | else | |
16457 | asm_fprintf (stream, "[%r, %r]", | |
16458 | REGNO (XEXP (x, 0)), | |
16459 | REGNO (XEXP (x, 1))); | |
16460 | } | |
16461 | else | |
16462 | output_addr_const (stream, x); | |
16463 | } | |
16464 | } | |
16465 | \f | |
16466 | /* Target hook for indicating whether a punctuation character for | |
16467 | TARGET_PRINT_OPERAND is valid. */ | |
16468 | static bool | |
16469 | arm_print_operand_punct_valid_p (unsigned char code) | |
16470 | { | |
16471 | return (code == '@' || code == '|' || code == '.' | |
16472 | || code == '(' || code == ')' || code == '#' | |
16473 | || (TARGET_32BIT && (code == '?')) | |
16474 | || (TARGET_THUMB2 && (code == '!')) | |
16475 | || (TARGET_THUMB && (code == '_'))); | |
16476 | } | |
16477 | \f | |
301d03af RS |
16478 | /* Target hook for assembling integer objects. The ARM version needs to |
16479 | handle word-sized values specially. */ | |
301d03af | 16480 | static bool |
e32bac5b | 16481 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 16482 | { |
88f77cba JB |
16483 | enum machine_mode mode; |
16484 | ||
301d03af RS |
16485 | if (size == UNITS_PER_WORD && aligned_p) |
16486 | { | |
16487 | fputs ("\t.word\t", asm_out_file); | |
16488 | output_addr_const (asm_out_file, x); | |
16489 | ||
16490 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 16491 | .text segment, not in the .data segment. */ |
301d03af RS |
16492 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
16493 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
16494 | { | |
9403b7f7 RS |
16495 | /* See legitimize_pic_address for an explanation of the |
16496 | TARGET_VXWORKS_RTP check. */ | |
16497 | if (TARGET_VXWORKS_RTP | |
16498 | || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) | |
301d03af | 16499 | fputs ("(GOT)", asm_out_file); |
9403b7f7 RS |
16500 | else |
16501 | fputs ("(GOTOFF)", asm_out_file); | |
301d03af RS |
16502 | } |
16503 | fputc ('\n', asm_out_file); | |
16504 | return true; | |
16505 | } | |
1d6e90ac | 16506 | |
88f77cba JB |
16507 | mode = GET_MODE (x); |
16508 | ||
16509 | if (arm_vector_mode_supported_p (mode)) | |
5a9335ef NC |
16510 | { |
16511 | int i, units; | |
16512 | ||
e6d29d15 | 16513 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
16514 | |
16515 | units = CONST_VECTOR_NUNITS (x); | |
88f77cba | 16516 | size = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
5a9335ef | 16517 | |
88f77cba JB |
16518 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) |
16519 | for (i = 0; i < units; i++) | |
16520 | { | |
874d42b9 | 16521 | rtx elt = CONST_VECTOR_ELT (x, i); |
88f77cba JB |
16522 | assemble_integer |
16523 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
16524 | } | |
16525 | else | |
16526 | for (i = 0; i < units; i++) | |
16527 | { | |
16528 | rtx elt = CONST_VECTOR_ELT (x, i); | |
16529 | REAL_VALUE_TYPE rval; | |
5a9335ef | 16530 | |
88f77cba JB |
16531 | REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); |
16532 | ||
16533 | assemble_real | |
16534 | (rval, GET_MODE_INNER (mode), | |
16535 | i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); | |
16536 | } | |
5a9335ef NC |
16537 | |
16538 | return true; | |
16539 | } | |
16540 | ||
301d03af RS |
16541 | return default_assemble_integer (x, size, aligned_p); |
16542 | } | |
7abc66b1 | 16543 | |
7abc66b1 | 16544 | static void |
9f296620 | 16545 | arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
7abc66b1 | 16546 | { |
50603eed PB |
16547 | section *s; |
16548 | ||
7abc66b1 JB |
16549 | if (!TARGET_AAPCS_BASED) |
16550 | { | |
9f296620 MM |
16551 | (is_ctor ? |
16552 | default_named_section_asm_out_constructor | |
16553 | : default_named_section_asm_out_destructor) (symbol, priority); | |
7abc66b1 JB |
16554 | return; |
16555 | } | |
16556 | ||
16557 | /* Put these in the .init_array section, using a special relocation. */ | |
50603eed PB |
16558 | if (priority != DEFAULT_INIT_PRIORITY) |
16559 | { | |
16560 | char buf[18]; | |
9f296620 MM |
16561 | sprintf (buf, "%s.%.5u", |
16562 | is_ctor ? ".init_array" : ".fini_array", | |
16563 | priority); | |
50603eed PB |
16564 | s = get_section (buf, SECTION_WRITE, NULL_TREE); |
16565 | } | |
9f296620 | 16566 | else if (is_ctor) |
50603eed | 16567 | s = ctors_section; |
9f296620 MM |
16568 | else |
16569 | s = dtors_section; | |
50603eed PB |
16570 | |
16571 | switch_to_section (s); | |
7abc66b1 JB |
16572 | assemble_align (POINTER_SIZE); |
16573 | fputs ("\t.word\t", asm_out_file); | |
16574 | output_addr_const (asm_out_file, symbol); | |
16575 | fputs ("(target1)\n", asm_out_file); | |
16576 | } | |
9f296620 MM |
16577 | |
16578 | /* Add a function to the list of static constructors. */ | |
16579 | ||
16580 | static void | |
16581 | arm_elf_asm_constructor (rtx symbol, int priority) | |
16582 | { | |
16583 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true); | |
16584 | } | |
16585 | ||
16586 | /* Add a function to the list of static destructors. */ | |
16587 | ||
16588 | static void | |
16589 | arm_elf_asm_destructor (rtx symbol, int priority) | |
16590 | { | |
16591 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false); | |
16592 | } | |
301d03af | 16593 | \f |
cce8749e CH |
16594 | /* A finite state machine takes care of noticing whether or not instructions |
16595 | can be conditionally executed, and thus decrease execution time and code | |
16596 | size by deleting branch instructions. The fsm is controlled by | |
16597 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
16598 | ||
16599 | /* The state of the fsm controlling condition codes are: | |
16600 | 0: normal, do nothing special | |
16601 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
16602 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
16603 | 3: make instructions conditional | |
16604 | 4: make instructions conditional | |
16605 | ||
16606 | State transitions (state->state by whom under condition): | |
16607 | 0 -> 1 final_prescan_insn if the `target' is a label | |
16608 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
16609 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
16610 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 16611 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
16612 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
16613 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
16614 | (the target insn is arm_target_insn). | |
16615 | ||
ff9940b0 RE |
16616 | If the jump clobbers the conditions then we use states 2 and 4. |
16617 | ||
16618 | A similar thing can be done with conditional return insns. | |
16619 | ||
cce8749e CH |
16620 | XXX In case the `target' is an unconditional branch, this conditionalising |
16621 | of the instructions always reduces code size, but not always execution | |
16622 | time. But then, I want to reduce the code size to somewhere near what | |
16623 | /bin/cc produces. */ | |
16624 | ||
5b3e6663 PB |
16625 | /* In addition to this, state is maintained for Thumb-2 COND_EXEC |
16626 | instructions. When a COND_EXEC instruction is seen the subsequent | |
16627 | instructions are scanned so that multiple conditional instructions can be | |
16628 | combined into a single IT block. arm_condexec_count and arm_condexec_mask | |
16629 | specify the length and true/false mask for the IT block. These will be | |
16630 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | |
16631 | ||
cce8749e CH |
16632 | /* Returns the index of the ARM condition code string in |
16633 | `arm_condition_codes'. COMPARISON should be an rtx like | |
16634 | `(eq (...) (...))'. */ | |
84ed5e79 | 16635 | static enum arm_cond_code |
e32bac5b | 16636 | get_arm_condition_code (rtx comparison) |
cce8749e | 16637 | { |
5165176d | 16638 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
81f40b79 | 16639 | enum arm_cond_code code; |
1d6e90ac | 16640 | enum rtx_code comp_code = GET_CODE (comparison); |
5165176d RE |
16641 | |
16642 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 16643 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
16644 | XEXP (comparison, 1)); |
16645 | ||
16646 | switch (mode) | |
cce8749e | 16647 | { |
84ed5e79 RE |
16648 | case CC_DNEmode: code = ARM_NE; goto dominance; |
16649 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
16650 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
16651 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
16652 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
16653 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
16654 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
16655 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
16656 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
16657 | case CC_DLTUmode: code = ARM_CC; | |
16658 | ||
16659 | dominance: | |
e6d29d15 | 16660 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
16661 | |
16662 | if (comp_code == EQ) | |
16663 | return ARM_INVERSE_CONDITION_CODE (code); | |
16664 | return code; | |
16665 | ||
5165176d | 16666 | case CC_NOOVmode: |
84ed5e79 | 16667 | switch (comp_code) |
5165176d | 16668 | { |
84ed5e79 RE |
16669 | case NE: return ARM_NE; |
16670 | case EQ: return ARM_EQ; | |
16671 | case GE: return ARM_PL; | |
16672 | case LT: return ARM_MI; | |
e6d29d15 | 16673 | default: gcc_unreachable (); |
5165176d RE |
16674 | } |
16675 | ||
16676 | case CC_Zmode: | |
84ed5e79 | 16677 | switch (comp_code) |
5165176d | 16678 | { |
84ed5e79 RE |
16679 | case NE: return ARM_NE; |
16680 | case EQ: return ARM_EQ; | |
e6d29d15 | 16681 | default: gcc_unreachable (); |
5165176d RE |
16682 | } |
16683 | ||
defc0463 RE |
16684 | case CC_Nmode: |
16685 | switch (comp_code) | |
16686 | { | |
16687 | case NE: return ARM_MI; | |
16688 | case EQ: return ARM_PL; | |
e6d29d15 | 16689 | default: gcc_unreachable (); |
defc0463 RE |
16690 | } |
16691 | ||
5165176d | 16692 | case CCFPEmode: |
e45b72c4 RE |
16693 | case CCFPmode: |
16694 | /* These encodings assume that AC=1 in the FPA system control | |
16695 | byte. This allows us to handle all cases except UNEQ and | |
16696 | LTGT. */ | |
84ed5e79 RE |
16697 | switch (comp_code) |
16698 | { | |
16699 | case GE: return ARM_GE; | |
16700 | case GT: return ARM_GT; | |
16701 | case LE: return ARM_LS; | |
16702 | case LT: return ARM_MI; | |
e45b72c4 RE |
16703 | case NE: return ARM_NE; |
16704 | case EQ: return ARM_EQ; | |
16705 | case ORDERED: return ARM_VC; | |
16706 | case UNORDERED: return ARM_VS; | |
16707 | case UNLT: return ARM_LT; | |
16708 | case UNLE: return ARM_LE; | |
16709 | case UNGT: return ARM_HI; | |
16710 | case UNGE: return ARM_PL; | |
16711 | /* UNEQ and LTGT do not have a representation. */ | |
16712 | case UNEQ: /* Fall through. */ | |
16713 | case LTGT: /* Fall through. */ | |
e6d29d15 | 16714 | default: gcc_unreachable (); |
84ed5e79 RE |
16715 | } |
16716 | ||
16717 | case CC_SWPmode: | |
16718 | switch (comp_code) | |
16719 | { | |
16720 | case NE: return ARM_NE; | |
16721 | case EQ: return ARM_EQ; | |
16722 | case GE: return ARM_LE; | |
16723 | case GT: return ARM_LT; | |
16724 | case LE: return ARM_GE; | |
16725 | case LT: return ARM_GT; | |
16726 | case GEU: return ARM_LS; | |
16727 | case GTU: return ARM_CC; | |
16728 | case LEU: return ARM_CS; | |
16729 | case LTU: return ARM_HI; | |
e6d29d15 | 16730 | default: gcc_unreachable (); |
84ed5e79 RE |
16731 | } |
16732 | ||
bd9c7e23 RE |
16733 | case CC_Cmode: |
16734 | switch (comp_code) | |
18e8200f BS |
16735 | { |
16736 | case LTU: return ARM_CS; | |
16737 | case GEU: return ARM_CC; | |
16738 | default: gcc_unreachable (); | |
16739 | } | |
16740 | ||
73160ba9 DJ |
16741 | case CC_CZmode: |
16742 | switch (comp_code) | |
16743 | { | |
16744 | case NE: return ARM_NE; | |
16745 | case EQ: return ARM_EQ; | |
16746 | case GEU: return ARM_CS; | |
16747 | case GTU: return ARM_HI; | |
16748 | case LEU: return ARM_LS; | |
16749 | case LTU: return ARM_CC; | |
16750 | default: gcc_unreachable (); | |
16751 | } | |
16752 | ||
16753 | case CC_NCVmode: | |
16754 | switch (comp_code) | |
16755 | { | |
16756 | case GE: return ARM_GE; | |
16757 | case LT: return ARM_LT; | |
16758 | case GEU: return ARM_CS; | |
16759 | case LTU: return ARM_CC; | |
16760 | default: gcc_unreachable (); | |
16761 | } | |
16762 | ||
5165176d | 16763 | case CCmode: |
84ed5e79 | 16764 | switch (comp_code) |
5165176d | 16765 | { |
84ed5e79 RE |
16766 | case NE: return ARM_NE; |
16767 | case EQ: return ARM_EQ; | |
16768 | case GE: return ARM_GE; | |
16769 | case GT: return ARM_GT; | |
16770 | case LE: return ARM_LE; | |
16771 | case LT: return ARM_LT; | |
16772 | case GEU: return ARM_CS; | |
16773 | case GTU: return ARM_HI; | |
16774 | case LEU: return ARM_LS; | |
16775 | case LTU: return ARM_CC; | |
e6d29d15 | 16776 | default: gcc_unreachable (); |
5165176d RE |
16777 | } |
16778 | ||
e6d29d15 | 16779 | default: gcc_unreachable (); |
cce8749e | 16780 | } |
f3bb6135 | 16781 | } |
cce8749e | 16782 | |
44c7bd63 | 16783 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed |
5b3e6663 PB |
16784 | instructions. */ |
16785 | void | |
16786 | thumb2_final_prescan_insn (rtx insn) | |
16787 | { | |
16788 | rtx first_insn = insn; | |
16789 | rtx body = PATTERN (insn); | |
16790 | rtx predicate; | |
16791 | enum arm_cond_code code; | |
16792 | int n; | |
16793 | int mask; | |
16794 | ||
16795 | /* Remove the previous insn from the count of insns to be output. */ | |
16796 | if (arm_condexec_count) | |
16797 | arm_condexec_count--; | |
16798 | ||
16799 | /* Nothing to do if we are already inside a conditional block. */ | |
16800 | if (arm_condexec_count) | |
16801 | return; | |
16802 | ||
16803 | if (GET_CODE (body) != COND_EXEC) | |
16804 | return; | |
16805 | ||
16806 | /* Conditional jumps are implemented directly. */ | |
16807 | if (GET_CODE (insn) == JUMP_INSN) | |
16808 | return; | |
16809 | ||
16810 | predicate = COND_EXEC_TEST (body); | |
16811 | arm_current_cc = get_arm_condition_code (predicate); | |
16812 | ||
16813 | n = get_attr_ce_count (insn); | |
16814 | arm_condexec_count = 1; | |
16815 | arm_condexec_mask = (1 << n) - 1; | |
16816 | arm_condexec_masklen = n; | |
16817 | /* See if subsequent instructions can be combined into the same block. */ | |
16818 | for (;;) | |
16819 | { | |
16820 | insn = next_nonnote_insn (insn); | |
16821 | ||
16822 | /* Jumping into the middle of an IT block is illegal, so a label or | |
16823 | barrier terminates the block. */ | |
16824 | if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) | |
16825 | break; | |
16826 | ||
16827 | body = PATTERN (insn); | |
16828 | /* USE and CLOBBER aren't really insns, so just skip them. */ | |
16829 | if (GET_CODE (body) == USE | |
16830 | || GET_CODE (body) == CLOBBER) | |
5b0202af | 16831 | continue; |
5b3e6663 | 16832 | |
7a085dce | 16833 | /* ??? Recognize conditional jumps, and combine them with IT blocks. */ |
5b3e6663 PB |
16834 | if (GET_CODE (body) != COND_EXEC) |
16835 | break; | |
16836 | /* Allow up to 4 conditionally executed instructions in a block. */ | |
16837 | n = get_attr_ce_count (insn); | |
16838 | if (arm_condexec_masklen + n > 4) | |
16839 | break; | |
16840 | ||
16841 | predicate = COND_EXEC_TEST (body); | |
16842 | code = get_arm_condition_code (predicate); | |
16843 | mask = (1 << n) - 1; | |
16844 | if (arm_current_cc == code) | |
16845 | arm_condexec_mask |= (mask << arm_condexec_masklen); | |
16846 | else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code)) | |
16847 | break; | |
16848 | ||
16849 | arm_condexec_count++; | |
16850 | arm_condexec_masklen += n; | |
16851 | ||
16852 | /* A jump must be the last instruction in a conditional block. */ | |
16853 | if (GET_CODE(insn) == JUMP_INSN) | |
16854 | break; | |
16855 | } | |
16856 | /* Restore recog_data (getting the attributes of other insns can | |
16857 | destroy this array, but final.c assumes that it remains intact | |
16858 | across this call). */ | |
16859 | extract_constrain_insn_cached (first_insn); | |
16860 | } | |
16861 | ||
cce8749e | 16862 | void |
e32bac5b | 16863 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
16864 | { |
16865 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 16866 | rtx body = PATTERN (insn); |
cce8749e CH |
16867 | |
16868 | /* This will be 1 if trying to repeat the trick, and things need to be | |
16869 | reversed if it appears to fail. */ | |
16870 | int reverse = 0; | |
16871 | ||
6354dc9b | 16872 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 16873 | int seeking_return = 0; |
f676971a | 16874 | |
cce8749e CH |
16875 | /* START_INSN will hold the insn from where we start looking. This is the |
16876 | first insn after the following code_label if REVERSE is true. */ | |
16877 | rtx start_insn = insn; | |
16878 | ||
16879 | /* If in state 4, check if the target branch is reached, in order to | |
16880 | change back to state 0. */ | |
16881 | if (arm_ccfsm_state == 4) | |
16882 | { | |
16883 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
16884 | { |
16885 | arm_target_insn = NULL; | |
16886 | arm_ccfsm_state = 0; | |
16887 | } | |
cce8749e CH |
16888 | return; |
16889 | } | |
16890 | ||
16891 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
16892 | unconditional branch to a label, and immediately following this branch | |
16893 | is the previous target label which is only used once, and the label this | |
16894 | branch jumps to is not too far off. */ | |
16895 | if (arm_ccfsm_state == 3) | |
16896 | { | |
16897 | if (simplejump_p (insn)) | |
16898 | { | |
16899 | start_insn = next_nonnote_insn (start_insn); | |
16900 | if (GET_CODE (start_insn) == BARRIER) | |
16901 | { | |
16902 | /* XXX Isn't this always a barrier? */ | |
16903 | start_insn = next_nonnote_insn (start_insn); | |
16904 | } | |
16905 | if (GET_CODE (start_insn) == CODE_LABEL | |
16906 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
16907 | && LABEL_NUSES (start_insn) == 1) | |
16908 | reverse = TRUE; | |
16909 | else | |
16910 | return; | |
16911 | } | |
ff9940b0 RE |
16912 | else if (GET_CODE (body) == RETURN) |
16913 | { | |
16914 | start_insn = next_nonnote_insn (start_insn); | |
16915 | if (GET_CODE (start_insn) == BARRIER) | |
16916 | start_insn = next_nonnote_insn (start_insn); | |
16917 | if (GET_CODE (start_insn) == CODE_LABEL | |
16918 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
16919 | && LABEL_NUSES (start_insn) == 1) | |
16920 | { | |
16921 | reverse = TRUE; | |
16922 | seeking_return = 1; | |
16923 | } | |
16924 | else | |
16925 | return; | |
16926 | } | |
cce8749e CH |
16927 | else |
16928 | return; | |
16929 | } | |
16930 | ||
e6d29d15 | 16931 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
16932 | if (GET_CODE (insn) != JUMP_INSN) |
16933 | return; | |
16934 | ||
f676971a | 16935 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
16936 | the jump should always come first */ |
16937 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
16938 | body = XVECEXP (body, 0, 0); | |
16939 | ||
cce8749e CH |
16940 | if (reverse |
16941 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
16942 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
16943 | { | |
bd9c7e23 RE |
16944 | int insns_skipped; |
16945 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
16946 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
16947 | int then_not_else = TRUE; | |
ff9940b0 | 16948 | rtx this_insn = start_insn, label = 0; |
cce8749e CH |
16949 | |
16950 | /* Register the insn jumped to. */ | |
16951 | if (reverse) | |
ff9940b0 RE |
16952 | { |
16953 | if (!seeking_return) | |
16954 | label = XEXP (SET_SRC (body), 0); | |
16955 | } | |
cce8749e CH |
16956 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
16957 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
16958 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
16959 | { | |
16960 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
16961 | then_not_else = FALSE; | |
16962 | } | |
ff9940b0 RE |
16963 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
16964 | seeking_return = 1; | |
16965 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
16966 | { | |
16967 | seeking_return = 1; | |
16968 | then_not_else = FALSE; | |
16969 | } | |
cce8749e | 16970 | else |
e6d29d15 | 16971 | gcc_unreachable (); |
cce8749e CH |
16972 | |
16973 | /* See how many insns this branch skips, and what kind of insns. If all | |
16974 | insns are okay, and the label or unconditional branch to the same | |
16975 | label is not too far away, succeed. */ | |
16976 | for (insns_skipped = 0; | |
b36ba79f | 16977 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
16978 | { |
16979 | rtx scanbody; | |
16980 | ||
16981 | this_insn = next_nonnote_insn (this_insn); | |
16982 | if (!this_insn) | |
16983 | break; | |
16984 | ||
cce8749e CH |
16985 | switch (GET_CODE (this_insn)) |
16986 | { | |
16987 | case CODE_LABEL: | |
16988 | /* Succeed if it is the target label, otherwise fail since | |
16989 | control falls in from somewhere else. */ | |
16990 | if (this_insn == label) | |
16991 | { | |
accbd151 | 16992 | arm_ccfsm_state = 1; |
cce8749e CH |
16993 | succeed = TRUE; |
16994 | } | |
16995 | else | |
16996 | fail = TRUE; | |
16997 | break; | |
16998 | ||
ff9940b0 | 16999 | case BARRIER: |
cce8749e | 17000 | /* Succeed if the following insn is the target label. |
f676971a EC |
17001 | Otherwise fail. |
17002 | If return insns are used then the last insn in a function | |
6354dc9b | 17003 | will be a barrier. */ |
cce8749e | 17004 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 17005 | if (this_insn && this_insn == label) |
cce8749e | 17006 | { |
accbd151 | 17007 | arm_ccfsm_state = 1; |
cce8749e CH |
17008 | succeed = TRUE; |
17009 | } | |
17010 | else | |
17011 | fail = TRUE; | |
17012 | break; | |
17013 | ||
ff9940b0 | 17014 | case CALL_INSN: |
68d560d4 RE |
17015 | /* The AAPCS says that conditional calls should not be |
17016 | used since they make interworking inefficient (the | |
17017 | linker can't transform BL<cond> into BLX). That's | |
17018 | only a problem if the machine has BLX. */ | |
17019 | if (arm_arch5) | |
17020 | { | |
17021 | fail = TRUE; | |
17022 | break; | |
17023 | } | |
17024 | ||
61f0ccff RE |
17025 | /* Succeed if the following insn is the target label, or |
17026 | if the following two insns are a barrier and the | |
17027 | target label. */ | |
17028 | this_insn = next_nonnote_insn (this_insn); | |
17029 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
17030 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 17031 | |
61f0ccff RE |
17032 | if (this_insn && this_insn == label |
17033 | && insns_skipped < max_insns_skipped) | |
17034 | { | |
accbd151 | 17035 | arm_ccfsm_state = 1; |
61f0ccff | 17036 | succeed = TRUE; |
bd9c7e23 | 17037 | } |
61f0ccff RE |
17038 | else |
17039 | fail = TRUE; | |
ff9940b0 | 17040 | break; |
2b835d68 | 17041 | |
cce8749e CH |
17042 | case JUMP_INSN: |
17043 | /* If this is an unconditional branch to the same label, succeed. | |
17044 | If it is to another label, do nothing. If it is conditional, | |
17045 | fail. */ | |
e32bac5b RE |
17046 | /* XXX Probably, the tests for SET and the PC are |
17047 | unnecessary. */ | |
cce8749e | 17048 | |
ed4c4348 | 17049 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
17050 | if (GET_CODE (scanbody) == SET |
17051 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
17052 | { |
17053 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
17054 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
17055 | { | |
17056 | arm_ccfsm_state = 2; | |
17057 | succeed = TRUE; | |
17058 | } | |
17059 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
17060 | fail = TRUE; | |
17061 | } | |
112cdef5 | 17062 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
17063 | StrongARM), but still allow this if optimizing for size. */ |
17064 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 17065 | && !use_return_insn (TRUE, NULL) |
5895f793 | 17066 | && !optimize_size) |
b36ba79f | 17067 | fail = TRUE; |
ff9940b0 RE |
17068 | else if (GET_CODE (scanbody) == RETURN |
17069 | && seeking_return) | |
17070 | { | |
17071 | arm_ccfsm_state = 2; | |
17072 | succeed = TRUE; | |
17073 | } | |
17074 | else if (GET_CODE (scanbody) == PARALLEL) | |
17075 | { | |
17076 | switch (get_attr_conds (this_insn)) | |
17077 | { | |
17078 | case CONDS_NOCOND: | |
17079 | break; | |
17080 | default: | |
17081 | fail = TRUE; | |
17082 | break; | |
17083 | } | |
17084 | } | |
4e67550b | 17085 | else |
112cdef5 | 17086 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 17087 | |
cce8749e CH |
17088 | break; |
17089 | ||
17090 | case INSN: | |
ff9940b0 RE |
17091 | /* Instructions using or affecting the condition codes make it |
17092 | fail. */ | |
ed4c4348 | 17093 | scanbody = PATTERN (this_insn); |
5895f793 RE |
17094 | if (!(GET_CODE (scanbody) == SET |
17095 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 17096 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 17097 | fail = TRUE; |
9b6b54e2 NC |
17098 | |
17099 | /* A conditional cirrus instruction must be followed by | |
17100 | a non Cirrus instruction. However, since we | |
17101 | conditionalize instructions in this function and by | |
17102 | the time we get here we can't add instructions | |
17103 | (nops), because shorten_branches() has already been | |
17104 | called, we will disable conditionalizing Cirrus | |
17105 | instructions to be safe. */ | |
17106 | if (GET_CODE (scanbody) != USE | |
17107 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 17108 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 17109 | fail = TRUE; |
cce8749e CH |
17110 | break; |
17111 | ||
17112 | default: | |
17113 | break; | |
17114 | } | |
17115 | } | |
17116 | if (succeed) | |
17117 | { | |
ff9940b0 | 17118 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 17119 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 17120 | else |
ff9940b0 | 17121 | { |
e6d29d15 | 17122 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 17123 | |
ff9940b0 RE |
17124 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
17125 | { | |
17126 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
17127 | gcc_assert (!this_insn |
17128 | || (GET_CODE (this_insn) != BARRIER | |
17129 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
17130 | } |
17131 | if (!this_insn) | |
17132 | { | |
d6b4baa4 | 17133 | /* Oh, dear! we ran off the end.. give up. */ |
5b3e6663 | 17134 | extract_constrain_insn_cached (insn); |
ff9940b0 | 17135 | arm_ccfsm_state = 0; |
abaa26e5 | 17136 | arm_target_insn = NULL; |
ff9940b0 RE |
17137 | return; |
17138 | } | |
17139 | arm_target_insn = this_insn; | |
17140 | } | |
accbd151 PB |
17141 | |
17142 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
17143 | what it was. */ | |
17144 | if (!reverse) | |
17145 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 0)); | |
cce8749e | 17146 | |
cce8749e CH |
17147 | if (reverse || then_not_else) |
17148 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
17149 | } | |
f676971a | 17150 | |
1ccbefce | 17151 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 17152 | destroy this array, but final.c assumes that it remains intact |
5b3e6663 PB |
17153 | across this call. */ |
17154 | extract_constrain_insn_cached (insn); | |
17155 | } | |
17156 | } | |
17157 | ||
17158 | /* Output IT instructions. */ | |
17159 | void | |
17160 | thumb2_asm_output_opcode (FILE * stream) | |
17161 | { | |
17162 | char buff[5]; | |
17163 | int n; | |
17164 | ||
17165 | if (arm_condexec_mask) | |
17166 | { | |
17167 | for (n = 0; n < arm_condexec_masklen; n++) | |
17168 | buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e'; | |
17169 | buff[n] = 0; | |
17170 | asm_fprintf(stream, "i%s\t%s\n\t", buff, | |
17171 | arm_condition_codes[arm_current_cc]); | |
17172 | arm_condexec_mask = 0; | |
cce8749e | 17173 | } |
f3bb6135 | 17174 | } |
cce8749e | 17175 | |
4b02997f | 17176 | /* Returns true if REGNO is a valid register |
21b5653c | 17177 | for holding a quantity of type MODE. */ |
4b02997f | 17178 | int |
e32bac5b | 17179 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
17180 | { |
17181 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
17182 | return (regno == CC_REGNUM |
17183 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
17184 | && regno == VFPCC_REGNUM)); | |
f676971a | 17185 | |
5b3e6663 | 17186 | if (TARGET_THUMB1) |
4b02997f NC |
17187 | /* For the Thumb we only allow values bigger than SImode in |
17188 | registers 0 - 6, so that there is always a second low | |
17189 | register available to hold the upper part of the value. | |
17190 | We probably we ought to ensure that the register is the | |
17191 | start of an even numbered register pair. */ | |
e9d7b180 | 17192 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 17193 | |
a6a5de04 RE |
17194 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
17195 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
17196 | /* We have outlawed SI values in Cirrus registers because they |
17197 | reside in the lower 32 bits, but SF values reside in the | |
17198 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
17199 | even split the registers into pairs because Cirrus SI values | |
17200 | get sign extended to 64bits-- aldyh. */ | |
17201 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
17202 | ||
a6a5de04 RE |
17203 | if (TARGET_HARD_FLOAT && TARGET_VFP |
17204 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
17205 | { |
17206 | if (mode == SFmode || mode == SImode) | |
f1adb0a9 | 17207 | return VFP_REGNO_OK_FOR_SINGLE (regno); |
9b66ebb1 | 17208 | |
9b66ebb1 | 17209 | if (mode == DFmode) |
f1adb0a9 | 17210 | return VFP_REGNO_OK_FOR_DOUBLE (regno); |
88f77cba | 17211 | |
0fd8c3ad | 17212 | /* VFP registers can hold HFmode values, but there is no point in |
e0dc3601 | 17213 | putting them there unless we have hardware conversion insns. */ |
0fd8c3ad | 17214 | if (mode == HFmode) |
e0dc3601 | 17215 | return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno); |
0fd8c3ad | 17216 | |
88f77cba JB |
17217 | if (TARGET_NEON) |
17218 | return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
17219 | || (VALID_NEON_QREG_MODE (mode) | |
17220 | && NEON_REGNO_OK_FOR_QUAD (regno)) | |
17221 | || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) | |
17222 | || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) | |
17223 | || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) | |
17224 | || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) | |
17225 | || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); | |
17226 | ||
9b66ebb1 PB |
17227 | return FALSE; |
17228 | } | |
17229 | ||
a6a5de04 RE |
17230 | if (TARGET_REALLY_IWMMXT) |
17231 | { | |
17232 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
17233 | return mode == SImode; | |
5a9335ef | 17234 | |
a6a5de04 RE |
17235 | if (IS_IWMMXT_REGNUM (regno)) |
17236 | return VALID_IWMMXT_REG_MODE (mode); | |
17237 | } | |
17238 | ||
2e94c12d | 17239 | /* We allow almost any value to be stored in the general registers. |
fdd695fd | 17240 | Restrict doubleword quantities to even register pairs so that we can |
2e94c12d JB |
17241 | use ldrd. Do not allow very large Neon structure opaque modes in |
17242 | general registers; they would use too many. */ | |
4b02997f | 17243 | if (regno <= LAST_ARM_REGNUM) |
88f77cba | 17244 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) |
2e94c12d | 17245 | && ARM_NUM_REGS (mode) <= 4; |
4b02997f | 17246 | |
a6a5de04 | 17247 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
17248 | || regno == ARG_POINTER_REGNUM) |
17249 | /* We only allow integers in the fake hard registers. */ | |
17250 | return GET_MODE_CLASS (mode) == MODE_INT; | |
17251 | ||
3b684012 | 17252 | /* The only registers left are the FPA registers |
4b02997f | 17253 | which we only allow to hold FP values. */ |
a6a5de04 RE |
17254 | return (TARGET_HARD_FLOAT && TARGET_FPA |
17255 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
17256 | && regno >= FIRST_FPA_REGNUM | |
17257 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
17258 | } |
17259 | ||
5b3e6663 PB |
17260 | /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are |
17261 | not used in arm mode. */ | |
bbbbb16a ILT |
17262 | |
17263 | enum reg_class | |
e32bac5b | 17264 | arm_regno_class (int regno) |
d5b7b3ae | 17265 | { |
5b3e6663 | 17266 | if (TARGET_THUMB1) |
d5b7b3ae RE |
17267 | { |
17268 | if (regno == STACK_POINTER_REGNUM) | |
17269 | return STACK_REG; | |
17270 | if (regno == CC_REGNUM) | |
17271 | return CC_REG; | |
17272 | if (regno < 8) | |
17273 | return LO_REGS; | |
17274 | return HI_REGS; | |
17275 | } | |
17276 | ||
5b3e6663 PB |
17277 | if (TARGET_THUMB2 && regno < 8) |
17278 | return LO_REGS; | |
17279 | ||
d5b7b3ae RE |
17280 | if ( regno <= LAST_ARM_REGNUM |
17281 | || regno == FRAME_POINTER_REGNUM | |
17282 | || regno == ARG_POINTER_REGNUM) | |
5b3e6663 | 17283 | return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS; |
f676971a | 17284 | |
9b66ebb1 | 17285 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
5b3e6663 | 17286 | return TARGET_THUMB2 ? CC_REG : NO_REGS; |
d5b7b3ae | 17287 | |
9b6b54e2 NC |
17288 | if (IS_CIRRUS_REGNUM (regno)) |
17289 | return CIRRUS_REGS; | |
17290 | ||
9b66ebb1 | 17291 | if (IS_VFP_REGNUM (regno)) |
f1adb0a9 JB |
17292 | { |
17293 | if (regno <= D7_VFP_REGNUM) | |
17294 | return VFP_D0_D7_REGS; | |
17295 | else if (regno <= LAST_LO_VFP_REGNUM) | |
17296 | return VFP_LO_REGS; | |
17297 | else | |
17298 | return VFP_HI_REGS; | |
17299 | } | |
9b66ebb1 | 17300 | |
5a9335ef NC |
17301 | if (IS_IWMMXT_REGNUM (regno)) |
17302 | return IWMMXT_REGS; | |
17303 | ||
e99faaaa ILT |
17304 | if (IS_IWMMXT_GR_REGNUM (regno)) |
17305 | return IWMMXT_GR_REGS; | |
17306 | ||
3b684012 | 17307 | return FPA_REGS; |
d5b7b3ae RE |
17308 | } |
17309 | ||
17310 | /* Handle a special case when computing the offset | |
17311 | of an argument from the frame pointer. */ | |
17312 | int | |
e32bac5b | 17313 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
17314 | { |
17315 | rtx insn; | |
17316 | ||
17317 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
17318 | if (value != 0) | |
17319 | return 0; | |
17320 | ||
17321 | /* We can only cope with the case where the address is held in a register. */ | |
17322 | if (GET_CODE (addr) != REG) | |
17323 | return 0; | |
17324 | ||
17325 | /* If we are using the frame pointer to point at the argument, then | |
17326 | an offset of 0 is correct. */ | |
cd2b33d0 | 17327 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 17328 | return 0; |
f676971a | 17329 | |
d5b7b3ae RE |
17330 | /* If we are using the stack pointer to point at the |
17331 | argument, then an offset of 0 is correct. */ | |
5b3e6663 | 17332 | /* ??? Check this is consistent with thumb2 frame layout. */ |
5895f793 | 17333 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
17334 | && REGNO (addr) == SP_REGNUM) |
17335 | return 0; | |
f676971a | 17336 | |
d5b7b3ae RE |
17337 | /* Oh dear. The argument is pointed to by a register rather |
17338 | than being held in a register, or being stored at a known | |
17339 | offset from the frame pointer. Since GDB only understands | |
17340 | those two kinds of argument we must translate the address | |
17341 | held in the register into an offset from the frame pointer. | |
17342 | We do this by searching through the insns for the function | |
17343 | looking to see where this register gets its value. If the | |
4912a07c | 17344 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 17345 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 17346 | |
d5b7b3ae RE |
17347 | This code is exercised by producing debugging information |
17348 | for a function with arguments like this: | |
f676971a | 17349 | |
d5b7b3ae | 17350 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 17351 | |
d5b7b3ae RE |
17352 | Without this code the stab for parameter 'd' will be set to |
17353 | an offset of 0 from the frame pointer, rather than 8. */ | |
17354 | ||
17355 | /* The if() statement says: | |
17356 | ||
17357 | If the insn is a normal instruction | |
17358 | and if the insn is setting the value in a register | |
17359 | and if the register being set is the register holding the address of the argument | |
17360 | and if the address is computing by an addition | |
17361 | that involves adding to a register | |
17362 | which is the frame pointer | |
17363 | a constant integer | |
17364 | ||
d6b4baa4 | 17365 | then... */ |
f676971a | 17366 | |
d5b7b3ae RE |
17367 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
17368 | { | |
f676971a | 17369 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
17370 | && GET_CODE (PATTERN (insn)) == SET |
17371 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
17372 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
17373 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 17374 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
17375 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
17376 | ) | |
17377 | { | |
17378 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 17379 | |
d5b7b3ae RE |
17380 | break; |
17381 | } | |
17382 | } | |
f676971a | 17383 | |
d5b7b3ae RE |
17384 | if (value == 0) |
17385 | { | |
17386 | debug_rtx (addr); | |
d4ee4d25 | 17387 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
17388 | value = 8; /* XXX magic hack */ |
17389 | } | |
17390 | ||
17391 | return value; | |
17392 | } | |
d5b7b3ae | 17393 | \f |
5a9335ef NC |
17394 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
17395 | do \ | |
17396 | { \ | |
17397 | if ((MASK) & insn_flags) \ | |
c79efc4d RÁE |
17398 | add_builtin_function ((NAME), (TYPE), (CODE), \ |
17399 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
17400 | } \ |
17401 | while (0) | |
17402 | ||
17403 | struct builtin_description | |
17404 | { | |
17405 | const unsigned int mask; | |
17406 | const enum insn_code icode; | |
17407 | const char * const name; | |
17408 | const enum arm_builtins code; | |
17409 | const enum rtx_code comparison; | |
17410 | const unsigned int flag; | |
17411 | }; | |
17412 | ||
17413 | static const struct builtin_description bdesc_2arg[] = | |
17414 | { | |
17415 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
17416 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
81f40b79 | 17417 | ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
5a9335ef NC |
17418 | |
17419 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
17420 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
17421 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
17422 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
17423 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
17424 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
17425 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
17426 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
17427 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
17428 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
17429 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
17430 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
17431 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
17432 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
17433 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
17434 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
17435 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
17436 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
17437 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
17438 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
17439 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
17440 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
17441 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
17442 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
17443 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
17444 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
17445 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
17446 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
17447 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
17448 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
17449 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
17450 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
17451 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
17452 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
17453 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
17454 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
17455 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
17456 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
17457 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
17458 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
17459 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
17460 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
17461 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
17462 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
17463 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
17464 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
17465 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
17466 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
17467 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
17468 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
17469 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
17470 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
17471 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
17472 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
17473 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
17474 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
17475 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
17476 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
17477 | ||
17478 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
81f40b79 | 17479 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
f676971a | 17480 | |
5a9335ef NC |
17481 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
17482 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
17483 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
17484 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
17485 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
17486 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
17487 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
88f77cba | 17488 | IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) |
5a9335ef | 17489 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) |
88f77cba | 17490 | IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) |
5a9335ef NC |
17491 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) |
17492 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
17493 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
88f77cba | 17494 | IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) |
5a9335ef | 17495 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) |
88f77cba | 17496 | IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) |
5a9335ef | 17497 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) |
9b66ebb1 | 17498 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef | 17499 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
88f77cba | 17500 | IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) |
5a9335ef | 17501 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) |
88f77cba | 17502 | IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) |
5a9335ef | 17503 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) |
9b66ebb1 | 17504 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
17505 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
17506 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
17507 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
17508 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
17509 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
17510 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
17511 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
17512 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
17513 | }; | |
17514 | ||
17515 | static const struct builtin_description bdesc_1arg[] = | |
17516 | { | |
17517 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
17518 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
17519 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
17520 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
17521 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
17522 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
17523 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
17524 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
17525 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
17526 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
17527 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
17528 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
17529 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
17530 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
17531 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
17532 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
17533 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
17534 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
17535 | }; | |
17536 | ||
17537 | /* Set up all the iWMMXt builtins. This is | |
17538 | not called if TARGET_IWMMXT is zero. */ | |
17539 | ||
17540 | static void | |
17541 | arm_init_iwmmxt_builtins (void) | |
17542 | { | |
17543 | const struct builtin_description * d; | |
17544 | size_t i; | |
17545 | tree endlink = void_list_node; | |
17546 | ||
4a5eab38 PB |
17547 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
17548 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
17549 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
17550 | ||
5a9335ef NC |
17551 | tree int_ftype_int |
17552 | = build_function_type (integer_type_node, | |
17553 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
17554 | tree v8qi_ftype_v8qi_v8qi_int | |
17555 | = build_function_type (V8QI_type_node, | |
17556 | tree_cons (NULL_TREE, V8QI_type_node, | |
17557 | tree_cons (NULL_TREE, V8QI_type_node, | |
17558 | tree_cons (NULL_TREE, | |
17559 | integer_type_node, | |
17560 | endlink)))); | |
17561 | tree v4hi_ftype_v4hi_int | |
17562 | = build_function_type (V4HI_type_node, | |
17563 | tree_cons (NULL_TREE, V4HI_type_node, | |
17564 | tree_cons (NULL_TREE, integer_type_node, | |
17565 | endlink))); | |
17566 | tree v2si_ftype_v2si_int | |
17567 | = build_function_type (V2SI_type_node, | |
17568 | tree_cons (NULL_TREE, V2SI_type_node, | |
17569 | tree_cons (NULL_TREE, integer_type_node, | |
17570 | endlink))); | |
17571 | tree v2si_ftype_di_di | |
17572 | = build_function_type (V2SI_type_node, | |
17573 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17574 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17575 | endlink))); | |
17576 | tree di_ftype_di_int | |
17577 | = build_function_type (long_long_integer_type_node, | |
17578 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17579 | tree_cons (NULL_TREE, integer_type_node, | |
17580 | endlink))); | |
17581 | tree di_ftype_di_int_int | |
17582 | = build_function_type (long_long_integer_type_node, | |
17583 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
17584 | tree_cons (NULL_TREE, integer_type_node, | |
17585 | tree_cons (NULL_TREE, | |
17586 | integer_type_node, | |
17587 | endlink)))); | |
17588 | tree int_ftype_v8qi | |
17589 | = build_function_type (integer_type_node, | |
17590 | tree_cons (NULL_TREE, V8QI_type_node, | |
17591 | endlink)); | |
17592 | tree int_ftype_v4hi | |
17593 | = build_function_type (integer_type_node, | |
17594 | tree_cons (NULL_TREE, V4HI_type_node, | |
17595 | endlink)); | |
17596 | tree int_ftype_v2si | |
17597 | = build_function_type (integer_type_node, | |
17598 | tree_cons (NULL_TREE, V2SI_type_node, | |
17599 | endlink)); | |
17600 | tree int_ftype_v8qi_int | |
17601 | = build_function_type (integer_type_node, | |
17602 | tree_cons (NULL_TREE, V8QI_type_node, | |
17603 | tree_cons (NULL_TREE, integer_type_node, | |
17604 | endlink))); | |
17605 | tree int_ftype_v4hi_int | |
17606 | = build_function_type (integer_type_node, | |
17607 | tree_cons (NULL_TREE, V4HI_type_node, | |
17608 | tree_cons (NULL_TREE, integer_type_node, | |
17609 | endlink))); | |
17610 | tree int_ftype_v2si_int | |
17611 | = build_function_type (integer_type_node, | |
17612 | tree_cons (NULL_TREE, V2SI_type_node, | |
17613 | tree_cons (NULL_TREE, integer_type_node, | |
17614 | endlink))); | |
17615 | tree v8qi_ftype_v8qi_int_int | |
17616 | = build_function_type (V8QI_type_node, | |
17617 | tree_cons (NULL_TREE, V8QI_type_node, | |
17618 | tree_cons (NULL_TREE, integer_type_node, | |
17619 | tree_cons (NULL_TREE, | |
17620 | integer_type_node, | |
17621 | endlink)))); | |
17622 | tree v4hi_ftype_v4hi_int_int | |
17623 | = build_function_type (V4HI_type_node, | |
17624 | tree_cons (NULL_TREE, V4HI_type_node, | |
17625 | tree_cons (NULL_TREE, integer_type_node, | |
17626 | tree_cons (NULL_TREE, | |
17627 | integer_type_node, | |
17628 | endlink)))); | |
17629 | tree v2si_ftype_v2si_int_int | |
17630 | = build_function_type (V2SI_type_node, | |
17631 | tree_cons (NULL_TREE, V2SI_type_node, | |
17632 | tree_cons (NULL_TREE, integer_type_node, | |
17633 | tree_cons (NULL_TREE, | |
17634 | integer_type_node, | |
17635 | endlink)))); | |
17636 | /* Miscellaneous. */ | |
17637 | tree v8qi_ftype_v4hi_v4hi | |
17638 | = build_function_type (V8QI_type_node, | |
17639 | tree_cons (NULL_TREE, V4HI_type_node, | |
17640 | tree_cons (NULL_TREE, V4HI_type_node, | |
17641 | endlink))); | |
17642 | tree v4hi_ftype_v2si_v2si | |
17643 | = build_function_type (V4HI_type_node, | |
17644 | tree_cons (NULL_TREE, V2SI_type_node, | |
17645 | tree_cons (NULL_TREE, V2SI_type_node, | |
17646 | endlink))); | |
17647 | tree v2si_ftype_v4hi_v4hi | |
17648 | = build_function_type (V2SI_type_node, | |
17649 | tree_cons (NULL_TREE, V4HI_type_node, | |
17650 | tree_cons (NULL_TREE, V4HI_type_node, | |
17651 | endlink))); | |
17652 | tree v2si_ftype_v8qi_v8qi | |
17653 | = build_function_type (V2SI_type_node, | |
17654 | tree_cons (NULL_TREE, V8QI_type_node, | |
17655 | tree_cons (NULL_TREE, V8QI_type_node, | |
17656 | endlink))); | |
17657 | tree v4hi_ftype_v4hi_di | |
17658 | = build_function_type (V4HI_type_node, | |
17659 | tree_cons (NULL_TREE, V4HI_type_node, | |
17660 | tree_cons (NULL_TREE, | |
17661 | long_long_integer_type_node, | |
17662 | endlink))); | |
17663 | tree v2si_ftype_v2si_di | |
17664 | = build_function_type (V2SI_type_node, | |
17665 | tree_cons (NULL_TREE, V2SI_type_node, | |
17666 | tree_cons (NULL_TREE, | |
17667 | long_long_integer_type_node, | |
17668 | endlink))); | |
17669 | tree void_ftype_int_int | |
17670 | = build_function_type (void_type_node, | |
17671 | tree_cons (NULL_TREE, integer_type_node, | |
17672 | tree_cons (NULL_TREE, integer_type_node, | |
17673 | endlink))); | |
17674 | tree di_ftype_void | |
17675 | = build_function_type (long_long_unsigned_type_node, endlink); | |
17676 | tree di_ftype_v8qi | |
17677 | = build_function_type (long_long_integer_type_node, | |
17678 | tree_cons (NULL_TREE, V8QI_type_node, | |
17679 | endlink)); | |
17680 | tree di_ftype_v4hi | |
17681 | = build_function_type (long_long_integer_type_node, | |
17682 | tree_cons (NULL_TREE, V4HI_type_node, | |
17683 | endlink)); | |
17684 | tree di_ftype_v2si | |
17685 | = build_function_type (long_long_integer_type_node, | |
17686 | tree_cons (NULL_TREE, V2SI_type_node, | |
17687 | endlink)); | |
17688 | tree v2si_ftype_v4hi | |
17689 | = build_function_type (V2SI_type_node, | |
17690 | tree_cons (NULL_TREE, V4HI_type_node, | |
17691 | endlink)); | |
17692 | tree v4hi_ftype_v8qi | |
17693 | = build_function_type (V4HI_type_node, | |
17694 | tree_cons (NULL_TREE, V8QI_type_node, | |
17695 | endlink)); | |
17696 | ||
17697 | tree di_ftype_di_v4hi_v4hi | |
17698 | = build_function_type (long_long_unsigned_type_node, | |
17699 | tree_cons (NULL_TREE, | |
17700 | long_long_unsigned_type_node, | |
17701 | tree_cons (NULL_TREE, V4HI_type_node, | |
17702 | tree_cons (NULL_TREE, | |
17703 | V4HI_type_node, | |
17704 | endlink)))); | |
17705 | ||
17706 | tree di_ftype_v4hi_v4hi | |
17707 | = build_function_type (long_long_unsigned_type_node, | |
17708 | tree_cons (NULL_TREE, V4HI_type_node, | |
17709 | tree_cons (NULL_TREE, V4HI_type_node, | |
17710 | endlink))); | |
17711 | ||
17712 | /* Normal vector binops. */ | |
17713 | tree v8qi_ftype_v8qi_v8qi | |
17714 | = build_function_type (V8QI_type_node, | |
17715 | tree_cons (NULL_TREE, V8QI_type_node, | |
17716 | tree_cons (NULL_TREE, V8QI_type_node, | |
17717 | endlink))); | |
17718 | tree v4hi_ftype_v4hi_v4hi | |
17719 | = build_function_type (V4HI_type_node, | |
17720 | tree_cons (NULL_TREE, V4HI_type_node, | |
17721 | tree_cons (NULL_TREE, V4HI_type_node, | |
17722 | endlink))); | |
17723 | tree v2si_ftype_v2si_v2si | |
17724 | = build_function_type (V2SI_type_node, | |
17725 | tree_cons (NULL_TREE, V2SI_type_node, | |
17726 | tree_cons (NULL_TREE, V2SI_type_node, | |
17727 | endlink))); | |
17728 | tree di_ftype_di_di | |
17729 | = build_function_type (long_long_unsigned_type_node, | |
17730 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
17731 | tree_cons (NULL_TREE, | |
17732 | long_long_unsigned_type_node, | |
17733 | endlink))); | |
17734 | ||
17735 | /* Add all builtins that are more or less simple operations on two | |
17736 | operands. */ | |
e97a46ce | 17737 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
17738 | { |
17739 | /* Use one of the operands; the target can have a different mode for | |
17740 | mask-generating compares. */ | |
17741 | enum machine_mode mode; | |
17742 | tree type; | |
17743 | ||
17744 | if (d->name == 0) | |
17745 | continue; | |
17746 | ||
17747 | mode = insn_data[d->icode].operand[1].mode; | |
17748 | ||
17749 | switch (mode) | |
17750 | { | |
17751 | case V8QImode: | |
17752 | type = v8qi_ftype_v8qi_v8qi; | |
17753 | break; | |
17754 | case V4HImode: | |
17755 | type = v4hi_ftype_v4hi_v4hi; | |
17756 | break; | |
17757 | case V2SImode: | |
17758 | type = v2si_ftype_v2si_v2si; | |
17759 | break; | |
17760 | case DImode: | |
17761 | type = di_ftype_di_di; | |
17762 | break; | |
17763 | ||
17764 | default: | |
e6d29d15 | 17765 | gcc_unreachable (); |
5a9335ef NC |
17766 | } |
17767 | ||
17768 | def_mbuiltin (d->mask, d->name, type, d->code); | |
17769 | } | |
17770 | ||
17771 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
17772 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
17773 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
17774 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
17775 | ||
17776 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
17777 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
17778 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
17779 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
17780 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
17781 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
17782 | ||
17783 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
17784 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
17785 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
17786 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
17787 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
17788 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
17789 | ||
17790 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
17791 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
17792 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
17793 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
17794 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
17795 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
17796 | ||
17797 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
17798 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
17799 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
17800 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
17801 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
17802 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
17803 | ||
17804 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
17805 | ||
17806 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
17807 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
17808 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
17809 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
17810 | ||
17811 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
17812 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
17813 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
17814 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
17815 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
17816 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
17817 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
17818 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
17819 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
17820 | ||
17821 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
17822 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
17823 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
17824 | ||
17825 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
17826 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
17827 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
17828 | ||
17829 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
17830 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
17831 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
17832 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
17833 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
17834 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
17835 | ||
17836 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
17837 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
17838 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
17839 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
17840 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
17841 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
17842 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
17843 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
17844 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
17845 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
17846 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
17847 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
17848 | ||
17849 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
17850 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
17851 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
17852 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
17853 | ||
17854 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
17855 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
17856 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
17857 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
17858 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
17859 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
17860 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
17861 | } | |
17862 | ||
d3585b76 DJ |
17863 | static void |
17864 | arm_init_tls_builtins (void) | |
17865 | { | |
ebfe65a3 | 17866 | tree ftype, decl; |
d3585b76 DJ |
17867 | |
17868 | ftype = build_function_type (ptr_type_node, void_list_node); | |
ebfe65a3 JJ |
17869 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
17870 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
17871 | NULL, NULL_TREE); | |
17872 | TREE_NOTHROW (decl) = 1; | |
17873 | TREE_READONLY (decl) = 1; | |
d3585b76 DJ |
17874 | } |
17875 | ||
81f40b79 | 17876 | enum neon_builtin_type_bits { |
88f77cba JB |
17877 | T_V8QI = 0x0001, |
17878 | T_V4HI = 0x0002, | |
17879 | T_V2SI = 0x0004, | |
17880 | T_V2SF = 0x0008, | |
17881 | T_DI = 0x0010, | |
17882 | T_V16QI = 0x0020, | |
17883 | T_V8HI = 0x0040, | |
17884 | T_V4SI = 0x0080, | |
17885 | T_V4SF = 0x0100, | |
17886 | T_V2DI = 0x0200, | |
17887 | T_TI = 0x0400, | |
17888 | T_EI = 0x0800, | |
17889 | T_OI = 0x1000 | |
81f40b79 | 17890 | }; |
88f77cba JB |
17891 | |
17892 | #define v8qi_UP T_V8QI | |
17893 | #define v4hi_UP T_V4HI | |
17894 | #define v2si_UP T_V2SI | |
17895 | #define v2sf_UP T_V2SF | |
17896 | #define di_UP T_DI | |
17897 | #define v16qi_UP T_V16QI | |
17898 | #define v8hi_UP T_V8HI | |
17899 | #define v4si_UP T_V4SI | |
17900 | #define v4sf_UP T_V4SF | |
17901 | #define v2di_UP T_V2DI | |
17902 | #define ti_UP T_TI | |
17903 | #define ei_UP T_EI | |
17904 | #define oi_UP T_OI | |
17905 | ||
17906 | #define UP(X) X##_UP | |
17907 | ||
17908 | #define T_MAX 13 | |
17909 | ||
17910 | typedef enum { | |
17911 | NEON_BINOP, | |
17912 | NEON_TERNOP, | |
17913 | NEON_UNOP, | |
17914 | NEON_GETLANE, | |
17915 | NEON_SETLANE, | |
17916 | NEON_CREATE, | |
17917 | NEON_DUP, | |
17918 | NEON_DUPLANE, | |
17919 | NEON_COMBINE, | |
17920 | NEON_SPLIT, | |
17921 | NEON_LANEMUL, | |
17922 | NEON_LANEMULL, | |
17923 | NEON_LANEMULH, | |
17924 | NEON_LANEMAC, | |
17925 | NEON_SCALARMUL, | |
17926 | NEON_SCALARMULL, | |
17927 | NEON_SCALARMULH, | |
17928 | NEON_SCALARMAC, | |
17929 | NEON_CONVERT, | |
17930 | NEON_FIXCONV, | |
17931 | NEON_SELECT, | |
17932 | NEON_RESULTPAIR, | |
17933 | NEON_REINTERP, | |
17934 | NEON_VTBL, | |
17935 | NEON_VTBX, | |
17936 | NEON_LOAD1, | |
17937 | NEON_LOAD1LANE, | |
17938 | NEON_STORE1, | |
17939 | NEON_STORE1LANE, | |
17940 | NEON_LOADSTRUCT, | |
17941 | NEON_LOADSTRUCTLANE, | |
17942 | NEON_STORESTRUCT, | |
17943 | NEON_STORESTRUCTLANE, | |
17944 | NEON_LOGICBINOP, | |
17945 | NEON_SHIFTINSERT, | |
17946 | NEON_SHIFTIMM, | |
17947 | NEON_SHIFTACC | |
17948 | } neon_itype; | |
17949 | ||
17950 | typedef struct { | |
17951 | const char *name; | |
17952 | const neon_itype itype; | |
81f40b79 | 17953 | const int bits; |
88f77cba JB |
17954 | const enum insn_code codes[T_MAX]; |
17955 | const unsigned int num_vars; | |
17956 | unsigned int base_fcode; | |
17957 | } neon_builtin_datum; | |
17958 | ||
17959 | #define CF(N,X) CODE_FOR_neon_##N##X | |
17960 | ||
17961 | #define VAR1(T, N, A) \ | |
17962 | #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 | |
17963 | #define VAR2(T, N, A, B) \ | |
17964 | #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 | |
17965 | #define VAR3(T, N, A, B, C) \ | |
17966 | #N, NEON_##T, UP (A) | UP (B) | UP (C), \ | |
17967 | { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 | |
17968 | #define VAR4(T, N, A, B, C, D) \ | |
17969 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ | |
17970 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 | |
17971 | #define VAR5(T, N, A, B, C, D, E) \ | |
17972 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ | |
17973 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 | |
17974 | #define VAR6(T, N, A, B, C, D, E, F) \ | |
17975 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ | |
17976 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 | |
17977 | #define VAR7(T, N, A, B, C, D, E, F, G) \ | |
17978 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ | |
17979 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
17980 | CF (N, G) }, 7, 0 | |
17981 | #define VAR8(T, N, A, B, C, D, E, F, G, H) \ | |
17982 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
17983 | | UP (H), \ | |
17984 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
17985 | CF (N, G), CF (N, H) }, 8, 0 | |
17986 | #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ | |
17987 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
17988 | | UP (H) | UP (I), \ | |
17989 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
17990 | CF (N, G), CF (N, H), CF (N, I) }, 9, 0 | |
17991 | #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ | |
17992 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
17993 | | UP (H) | UP (I) | UP (J), \ | |
17994 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
17995 | CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 | |
17996 | ||
17997 | /* The mode entries in the following table correspond to the "key" type of the | |
17998 | instruction variant, i.e. equivalent to that which would be specified after | |
17999 | the assembler mnemonic, which usually refers to the last vector operand. | |
18000 | (Signed/unsigned/polynomial types are not differentiated between though, and | |
18001 | are all mapped onto the same mode for a given element size.) The modes | |
18002 | listed per instruction should be the same as those defined for that | |
18003 | instruction's pattern in neon.md. | |
18004 | WARNING: Variants should be listed in the same increasing order as | |
18005 | neon_builtin_type_bits. */ | |
18006 | ||
18007 | static neon_builtin_datum neon_builtin_data[] = | |
18008 | { | |
18009 | { VAR10 (BINOP, vadd, | |
18010 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18011 | { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, | |
18012 | { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, | |
18013 | { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18014 | { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18015 | { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, | |
18016 | { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18017 | { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18018 | { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, | |
18019 | { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18020 | { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, | |
18021 | { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, | |
18022 | { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, | |
18023 | { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, | |
18024 | { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, | |
18025 | { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, | |
18026 | { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, | |
18027 | { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, | |
18028 | { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, | |
18029 | { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, | |
18030 | { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, | |
18031 | { VAR2 (BINOP, vqdmull, v4hi, v2si) }, | |
18032 | { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18033 | { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18034 | { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18035 | { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, | |
18036 | { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, | |
18037 | { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, | |
18038 | { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18039 | { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18040 | { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18041 | { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, | |
18042 | { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18043 | { VAR10 (BINOP, vsub, | |
18044 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18045 | { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, | |
18046 | { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, | |
18047 | { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18048 | { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18049 | { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, | |
18050 | { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18051 | { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18052 | { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18053 | { VAR2 (BINOP, vcage, v2sf, v4sf) }, | |
18054 | { VAR2 (BINOP, vcagt, v2sf, v4sf) }, | |
18055 | { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18056 | { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18057 | { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, | |
18058 | { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18059 | { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, | |
18060 | { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18061 | { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18062 | { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, | |
18063 | { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18064 | { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18065 | { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, | |
18066 | { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, | |
18067 | { VAR2 (BINOP, vrecps, v2sf, v4sf) }, | |
18068 | { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, | |
18069 | { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18070 | { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
18071 | { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18072 | { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18073 | { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18074 | { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18075 | { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18076 | { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18077 | { VAR2 (UNOP, vcnt, v8qi, v16qi) }, | |
18078 | { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, | |
18079 | { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, | |
18080 | { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
18081 | /* FIXME: vget_lane supports more variants than this! */ | |
18082 | { VAR10 (GETLANE, vget_lane, | |
18083 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18084 | { VAR10 (SETLANE, vset_lane, | |
18085 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18086 | { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, | |
18087 | { VAR10 (DUP, vdup_n, | |
18088 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18089 | { VAR10 (DUPLANE, vdup_lane, | |
18090 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18091 | { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, | |
18092 | { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18093 | { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18094 | { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, | |
18095 | { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, | |
18096 | { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, | |
18097 | { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, | |
18098 | { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18099 | { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18100 | { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, | |
18101 | { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, | |
18102 | { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18103 | { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, | |
18104 | { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, | |
18105 | { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18106 | { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18107 | { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, | |
18108 | { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, | |
18109 | { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18110 | { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, | |
18111 | { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, | |
18112 | { VAR10 (BINOP, vext, | |
18113 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18114 | { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18115 | { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, | |
18116 | { VAR2 (UNOP, vrev16, v8qi, v16qi) }, | |
18117 | { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, | |
18118 | { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, | |
18119 | { VAR10 (SELECT, vbsl, | |
18120 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18121 | { VAR1 (VTBL, vtbl1, v8qi) }, | |
18122 | { VAR1 (VTBL, vtbl2, v8qi) }, | |
18123 | { VAR1 (VTBL, vtbl3, v8qi) }, | |
18124 | { VAR1 (VTBL, vtbl4, v8qi) }, | |
18125 | { VAR1 (VTBX, vtbx1, v8qi) }, | |
18126 | { VAR1 (VTBX, vtbx2, v8qi) }, | |
18127 | { VAR1 (VTBX, vtbx3, v8qi) }, | |
18128 | { VAR1 (VTBX, vtbx4, v8qi) }, | |
18129 | { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18130 | { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18131 | { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
18132 | { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, | |
18133 | { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, | |
18134 | { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, | |
18135 | { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, | |
18136 | { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, | |
18137 | { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18138 | { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18139 | { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18140 | { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18141 | { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18142 | { VAR10 (LOAD1, vld1, | |
18143 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18144 | { VAR10 (LOAD1LANE, vld1_lane, | |
18145 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18146 | { VAR10 (LOAD1, vld1_dup, | |
18147 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18148 | { VAR10 (STORE1, vst1, | |
18149 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18150 | { VAR10 (STORE1LANE, vst1_lane, | |
18151 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18152 | { VAR9 (LOADSTRUCT, | |
18153 | vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18154 | { VAR7 (LOADSTRUCTLANE, vld2_lane, | |
18155 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18156 | { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18157 | { VAR9 (STORESTRUCT, vst2, | |
18158 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18159 | { VAR7 (STORESTRUCTLANE, vst2_lane, | |
18160 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18161 | { VAR9 (LOADSTRUCT, | |
18162 | vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18163 | { VAR7 (LOADSTRUCTLANE, vld3_lane, | |
18164 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18165 | { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18166 | { VAR9 (STORESTRUCT, vst3, | |
18167 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18168 | { VAR7 (STORESTRUCTLANE, vst3_lane, | |
18169 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18170 | { VAR9 (LOADSTRUCT, vld4, | |
18171 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18172 | { VAR7 (LOADSTRUCTLANE, vld4_lane, | |
18173 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18174 | { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
18175 | { VAR9 (STORESTRUCT, vst4, | |
18176 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
18177 | { VAR7 (STORESTRUCTLANE, vst4_lane, | |
18178 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
18179 | { VAR10 (LOGICBINOP, vand, | |
18180 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18181 | { VAR10 (LOGICBINOP, vorr, | |
18182 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18183 | { VAR10 (BINOP, veor, | |
18184 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18185 | { VAR10 (LOGICBINOP, vbic, | |
18186 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
18187 | { VAR10 (LOGICBINOP, vorn, | |
18188 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } | |
18189 | }; | |
18190 | ||
18191 | #undef CF | |
18192 | #undef VAR1 | |
18193 | #undef VAR2 | |
18194 | #undef VAR3 | |
18195 | #undef VAR4 | |
18196 | #undef VAR5 | |
18197 | #undef VAR6 | |
18198 | #undef VAR7 | |
18199 | #undef VAR8 | |
18200 | #undef VAR9 | |
18201 | #undef VAR10 | |
18202 | ||
18203 | static void | |
18204 | arm_init_neon_builtins (void) | |
18205 | { | |
18206 | unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; | |
18207 | ||
af06585a JM |
18208 | tree neon_intQI_type_node; |
18209 | tree neon_intHI_type_node; | |
18210 | tree neon_polyQI_type_node; | |
18211 | tree neon_polyHI_type_node; | |
18212 | tree neon_intSI_type_node; | |
18213 | tree neon_intDI_type_node; | |
18214 | tree neon_float_type_node; | |
18215 | ||
18216 | tree intQI_pointer_node; | |
18217 | tree intHI_pointer_node; | |
18218 | tree intSI_pointer_node; | |
18219 | tree intDI_pointer_node; | |
18220 | tree float_pointer_node; | |
18221 | ||
18222 | tree const_intQI_node; | |
18223 | tree const_intHI_node; | |
18224 | tree const_intSI_node; | |
18225 | tree const_intDI_node; | |
18226 | tree const_float_node; | |
18227 | ||
18228 | tree const_intQI_pointer_node; | |
18229 | tree const_intHI_pointer_node; | |
18230 | tree const_intSI_pointer_node; | |
18231 | tree const_intDI_pointer_node; | |
18232 | tree const_float_pointer_node; | |
18233 | ||
18234 | tree V8QI_type_node; | |
18235 | tree V4HI_type_node; | |
18236 | tree V2SI_type_node; | |
18237 | tree V2SF_type_node; | |
18238 | tree V16QI_type_node; | |
18239 | tree V8HI_type_node; | |
18240 | tree V4SI_type_node; | |
18241 | tree V4SF_type_node; | |
18242 | tree V2DI_type_node; | |
18243 | ||
18244 | tree intUQI_type_node; | |
18245 | tree intUHI_type_node; | |
18246 | tree intUSI_type_node; | |
18247 | tree intUDI_type_node; | |
18248 | ||
18249 | tree intEI_type_node; | |
18250 | tree intOI_type_node; | |
18251 | tree intCI_type_node; | |
18252 | tree intXI_type_node; | |
18253 | ||
18254 | tree V8QI_pointer_node; | |
18255 | tree V4HI_pointer_node; | |
18256 | tree V2SI_pointer_node; | |
18257 | tree V2SF_pointer_node; | |
18258 | tree V16QI_pointer_node; | |
18259 | tree V8HI_pointer_node; | |
18260 | tree V4SI_pointer_node; | |
18261 | tree V4SF_pointer_node; | |
18262 | tree V2DI_pointer_node; | |
18263 | ||
18264 | tree void_ftype_pv8qi_v8qi_v8qi; | |
18265 | tree void_ftype_pv4hi_v4hi_v4hi; | |
18266 | tree void_ftype_pv2si_v2si_v2si; | |
18267 | tree void_ftype_pv2sf_v2sf_v2sf; | |
18268 | tree void_ftype_pdi_di_di; | |
18269 | tree void_ftype_pv16qi_v16qi_v16qi; | |
18270 | tree void_ftype_pv8hi_v8hi_v8hi; | |
18271 | tree void_ftype_pv4si_v4si_v4si; | |
18272 | tree void_ftype_pv4sf_v4sf_v4sf; | |
18273 | tree void_ftype_pv2di_v2di_v2di; | |
18274 | ||
18275 | tree reinterp_ftype_dreg[5][5]; | |
18276 | tree reinterp_ftype_qreg[5][5]; | |
18277 | tree dreg_types[5], qreg_types[5]; | |
18278 | ||
88f77cba JB |
18279 | /* Create distinguished type nodes for NEON vector element types, |
18280 | and pointers to values of such types, so we can detect them later. */ | |
af06585a JM |
18281 | neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); |
18282 | neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
18283 | neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); | |
18284 | neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
18285 | neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); | |
18286 | neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); | |
18287 | neon_float_type_node = make_node (REAL_TYPE); | |
18288 | TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; | |
18289 | layout_type (neon_float_type_node); | |
18290 | ||
bcbdbbb0 JM |
18291 | /* Define typedefs which exactly correspond to the modes we are basing vector |
18292 | types on. If you change these names you'll need to change | |
18293 | the table used by arm_mangle_type too. */ | |
18294 | (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, | |
18295 | "__builtin_neon_qi"); | |
18296 | (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, | |
18297 | "__builtin_neon_hi"); | |
18298 | (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, | |
18299 | "__builtin_neon_si"); | |
18300 | (*lang_hooks.types.register_builtin_type) (neon_float_type_node, | |
18301 | "__builtin_neon_sf"); | |
18302 | (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, | |
18303 | "__builtin_neon_di"); | |
18304 | (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, | |
18305 | "__builtin_neon_poly8"); | |
18306 | (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, | |
18307 | "__builtin_neon_poly16"); | |
18308 | ||
af06585a JM |
18309 | intQI_pointer_node = build_pointer_type (neon_intQI_type_node); |
18310 | intHI_pointer_node = build_pointer_type (neon_intHI_type_node); | |
18311 | intSI_pointer_node = build_pointer_type (neon_intSI_type_node); | |
18312 | intDI_pointer_node = build_pointer_type (neon_intDI_type_node); | |
18313 | float_pointer_node = build_pointer_type (neon_float_type_node); | |
88f77cba JB |
18314 | |
18315 | /* Next create constant-qualified versions of the above types. */ | |
af06585a JM |
18316 | const_intQI_node = build_qualified_type (neon_intQI_type_node, |
18317 | TYPE_QUAL_CONST); | |
18318 | const_intHI_node = build_qualified_type (neon_intHI_type_node, | |
18319 | TYPE_QUAL_CONST); | |
18320 | const_intSI_node = build_qualified_type (neon_intSI_type_node, | |
18321 | TYPE_QUAL_CONST); | |
18322 | const_intDI_node = build_qualified_type (neon_intDI_type_node, | |
18323 | TYPE_QUAL_CONST); | |
18324 | const_float_node = build_qualified_type (neon_float_type_node, | |
18325 | TYPE_QUAL_CONST); | |
18326 | ||
18327 | const_intQI_pointer_node = build_pointer_type (const_intQI_node); | |
18328 | const_intHI_pointer_node = build_pointer_type (const_intHI_node); | |
18329 | const_intSI_pointer_node = build_pointer_type (const_intSI_node); | |
18330 | const_intDI_pointer_node = build_pointer_type (const_intDI_node); | |
18331 | const_float_pointer_node = build_pointer_type (const_float_node); | |
88f77cba JB |
18332 | |
18333 | /* Now create vector types based on our NEON element types. */ | |
18334 | /* 64-bit vectors. */ | |
af06585a | 18335 | V8QI_type_node = |
88f77cba | 18336 | build_vector_type_for_mode (neon_intQI_type_node, V8QImode); |
af06585a | 18337 | V4HI_type_node = |
88f77cba | 18338 | build_vector_type_for_mode (neon_intHI_type_node, V4HImode); |
af06585a | 18339 | V2SI_type_node = |
88f77cba | 18340 | build_vector_type_for_mode (neon_intSI_type_node, V2SImode); |
af06585a | 18341 | V2SF_type_node = |
88f77cba JB |
18342 | build_vector_type_for_mode (neon_float_type_node, V2SFmode); |
18343 | /* 128-bit vectors. */ | |
af06585a | 18344 | V16QI_type_node = |
88f77cba | 18345 | build_vector_type_for_mode (neon_intQI_type_node, V16QImode); |
af06585a | 18346 | V8HI_type_node = |
88f77cba | 18347 | build_vector_type_for_mode (neon_intHI_type_node, V8HImode); |
af06585a | 18348 | V4SI_type_node = |
88f77cba | 18349 | build_vector_type_for_mode (neon_intSI_type_node, V4SImode); |
af06585a | 18350 | V4SF_type_node = |
88f77cba | 18351 | build_vector_type_for_mode (neon_float_type_node, V4SFmode); |
af06585a | 18352 | V2DI_type_node = |
88f77cba JB |
18353 | build_vector_type_for_mode (neon_intDI_type_node, V2DImode); |
18354 | ||
18355 | /* Unsigned integer types for various mode sizes. */ | |
af06585a JM |
18356 | intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); |
18357 | intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); | |
18358 | intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); | |
18359 | intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); | |
88f77cba | 18360 | |
bcbdbbb0 JM |
18361 | (*lang_hooks.types.register_builtin_type) (intUQI_type_node, |
18362 | "__builtin_neon_uqi"); | |
18363 | (*lang_hooks.types.register_builtin_type) (intUHI_type_node, | |
18364 | "__builtin_neon_uhi"); | |
18365 | (*lang_hooks.types.register_builtin_type) (intUSI_type_node, | |
18366 | "__builtin_neon_usi"); | |
18367 | (*lang_hooks.types.register_builtin_type) (intUDI_type_node, | |
18368 | "__builtin_neon_udi"); | |
18369 | ||
88f77cba | 18370 | /* Opaque integer types for structures of vectors. */ |
af06585a JM |
18371 | intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); |
18372 | intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); | |
18373 | intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); | |
18374 | intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); | |
88f77cba | 18375 | |
bcbdbbb0 JM |
18376 | (*lang_hooks.types.register_builtin_type) (intTI_type_node, |
18377 | "__builtin_neon_ti"); | |
18378 | (*lang_hooks.types.register_builtin_type) (intEI_type_node, | |
18379 | "__builtin_neon_ei"); | |
18380 | (*lang_hooks.types.register_builtin_type) (intOI_type_node, | |
18381 | "__builtin_neon_oi"); | |
18382 | (*lang_hooks.types.register_builtin_type) (intCI_type_node, | |
18383 | "__builtin_neon_ci"); | |
18384 | (*lang_hooks.types.register_builtin_type) (intXI_type_node, | |
18385 | "__builtin_neon_xi"); | |
18386 | ||
88f77cba | 18387 | /* Pointers to vector types. */ |
af06585a JM |
18388 | V8QI_pointer_node = build_pointer_type (V8QI_type_node); |
18389 | V4HI_pointer_node = build_pointer_type (V4HI_type_node); | |
18390 | V2SI_pointer_node = build_pointer_type (V2SI_type_node); | |
18391 | V2SF_pointer_node = build_pointer_type (V2SF_type_node); | |
18392 | V16QI_pointer_node = build_pointer_type (V16QI_type_node); | |
18393 | V8HI_pointer_node = build_pointer_type (V8HI_type_node); | |
18394 | V4SI_pointer_node = build_pointer_type (V4SI_type_node); | |
18395 | V4SF_pointer_node = build_pointer_type (V4SF_type_node); | |
18396 | V2DI_pointer_node = build_pointer_type (V2DI_type_node); | |
88f77cba JB |
18397 | |
18398 | /* Operations which return results as pairs. */ | |
af06585a | 18399 | void_ftype_pv8qi_v8qi_v8qi = |
88f77cba JB |
18400 | build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, |
18401 | V8QI_type_node, NULL); | |
af06585a | 18402 | void_ftype_pv4hi_v4hi_v4hi = |
88f77cba JB |
18403 | build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, |
18404 | V4HI_type_node, NULL); | |
af06585a | 18405 | void_ftype_pv2si_v2si_v2si = |
88f77cba JB |
18406 | build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, |
18407 | V2SI_type_node, NULL); | |
af06585a | 18408 | void_ftype_pv2sf_v2sf_v2sf = |
88f77cba JB |
18409 | build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, |
18410 | V2SF_type_node, NULL); | |
af06585a | 18411 | void_ftype_pdi_di_di = |
88f77cba JB |
18412 | build_function_type_list (void_type_node, intDI_pointer_node, |
18413 | neon_intDI_type_node, neon_intDI_type_node, NULL); | |
af06585a | 18414 | void_ftype_pv16qi_v16qi_v16qi = |
88f77cba JB |
18415 | build_function_type_list (void_type_node, V16QI_pointer_node, |
18416 | V16QI_type_node, V16QI_type_node, NULL); | |
af06585a | 18417 | void_ftype_pv8hi_v8hi_v8hi = |
88f77cba JB |
18418 | build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, |
18419 | V8HI_type_node, NULL); | |
af06585a | 18420 | void_ftype_pv4si_v4si_v4si = |
88f77cba JB |
18421 | build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, |
18422 | V4SI_type_node, NULL); | |
af06585a | 18423 | void_ftype_pv4sf_v4sf_v4sf = |
88f77cba JB |
18424 | build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, |
18425 | V4SF_type_node, NULL); | |
af06585a | 18426 | void_ftype_pv2di_v2di_v2di = |
88f77cba JB |
18427 | build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, |
18428 | V2DI_type_node, NULL); | |
18429 | ||
88f77cba JB |
18430 | dreg_types[0] = V8QI_type_node; |
18431 | dreg_types[1] = V4HI_type_node; | |
18432 | dreg_types[2] = V2SI_type_node; | |
18433 | dreg_types[3] = V2SF_type_node; | |
18434 | dreg_types[4] = neon_intDI_type_node; | |
18435 | ||
18436 | qreg_types[0] = V16QI_type_node; | |
18437 | qreg_types[1] = V8HI_type_node; | |
18438 | qreg_types[2] = V4SI_type_node; | |
18439 | qreg_types[3] = V4SF_type_node; | |
18440 | qreg_types[4] = V2DI_type_node; | |
18441 | ||
18442 | for (i = 0; i < 5; i++) | |
18443 | { | |
18444 | int j; | |
18445 | for (j = 0; j < 5; j++) | |
18446 | { | |
18447 | reinterp_ftype_dreg[i][j] | |
18448 | = build_function_type_list (dreg_types[i], dreg_types[j], NULL); | |
18449 | reinterp_ftype_qreg[i][j] | |
18450 | = build_function_type_list (qreg_types[i], qreg_types[j], NULL); | |
18451 | } | |
18452 | } | |
18453 | ||
18454 | for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) | |
18455 | { | |
18456 | neon_builtin_datum *d = &neon_builtin_data[i]; | |
18457 | unsigned int j, codeidx = 0; | |
18458 | ||
18459 | d->base_fcode = fcode; | |
18460 | ||
18461 | for (j = 0; j < T_MAX; j++) | |
18462 | { | |
18463 | const char* const modenames[] = { | |
18464 | "v8qi", "v4hi", "v2si", "v2sf", "di", | |
18465 | "v16qi", "v8hi", "v4si", "v4sf", "v2di" | |
18466 | }; | |
18467 | char namebuf[60]; | |
18468 | tree ftype = NULL; | |
18469 | enum insn_code icode; | |
18470 | int is_load = 0, is_store = 0; | |
18471 | ||
18472 | if ((d->bits & (1 << j)) == 0) | |
18473 | continue; | |
18474 | ||
18475 | icode = d->codes[codeidx++]; | |
18476 | ||
18477 | switch (d->itype) | |
18478 | { | |
18479 | case NEON_LOAD1: | |
18480 | case NEON_LOAD1LANE: | |
18481 | case NEON_LOADSTRUCT: | |
18482 | case NEON_LOADSTRUCTLANE: | |
18483 | is_load = 1; | |
18484 | /* Fall through. */ | |
18485 | case NEON_STORE1: | |
18486 | case NEON_STORE1LANE: | |
18487 | case NEON_STORESTRUCT: | |
18488 | case NEON_STORESTRUCTLANE: | |
18489 | if (!is_load) | |
18490 | is_store = 1; | |
18491 | /* Fall through. */ | |
18492 | case NEON_UNOP: | |
18493 | case NEON_BINOP: | |
18494 | case NEON_LOGICBINOP: | |
18495 | case NEON_SHIFTINSERT: | |
18496 | case NEON_TERNOP: | |
18497 | case NEON_GETLANE: | |
18498 | case NEON_SETLANE: | |
18499 | case NEON_CREATE: | |
18500 | case NEON_DUP: | |
18501 | case NEON_DUPLANE: | |
18502 | case NEON_SHIFTIMM: | |
18503 | case NEON_SHIFTACC: | |
18504 | case NEON_COMBINE: | |
18505 | case NEON_SPLIT: | |
18506 | case NEON_CONVERT: | |
18507 | case NEON_FIXCONV: | |
18508 | case NEON_LANEMUL: | |
18509 | case NEON_LANEMULL: | |
18510 | case NEON_LANEMULH: | |
18511 | case NEON_LANEMAC: | |
18512 | case NEON_SCALARMUL: | |
18513 | case NEON_SCALARMULL: | |
18514 | case NEON_SCALARMULH: | |
18515 | case NEON_SCALARMAC: | |
18516 | case NEON_SELECT: | |
18517 | case NEON_VTBL: | |
18518 | case NEON_VTBX: | |
18519 | { | |
18520 | int k; | |
18521 | tree return_type = void_type_node, args = void_list_node; | |
18522 | ||
18523 | /* Build a function type directly from the insn_data for this | |
18524 | builtin. The build_function_type() function takes care of | |
18525 | removing duplicates for us. */ | |
18526 | for (k = insn_data[icode].n_operands - 1; k >= 0; k--) | |
18527 | { | |
18528 | tree eltype; | |
18529 | ||
18530 | if (is_load && k == 1) | |
18531 | { | |
18532 | /* Neon load patterns always have the memory operand | |
18533 | (a SImode pointer) in the operand 1 position. We | |
18534 | want a const pointer to the element type in that | |
18535 | position. */ | |
18536 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
18537 | ||
18538 | switch (1 << j) | |
18539 | { | |
18540 | case T_V8QI: | |
18541 | case T_V16QI: | |
18542 | eltype = const_intQI_pointer_node; | |
18543 | break; | |
18544 | ||
18545 | case T_V4HI: | |
18546 | case T_V8HI: | |
18547 | eltype = const_intHI_pointer_node; | |
18548 | break; | |
18549 | ||
18550 | case T_V2SI: | |
18551 | case T_V4SI: | |
18552 | eltype = const_intSI_pointer_node; | |
18553 | break; | |
18554 | ||
18555 | case T_V2SF: | |
18556 | case T_V4SF: | |
18557 | eltype = const_float_pointer_node; | |
18558 | break; | |
18559 | ||
18560 | case T_DI: | |
18561 | case T_V2DI: | |
18562 | eltype = const_intDI_pointer_node; | |
18563 | break; | |
18564 | ||
18565 | default: gcc_unreachable (); | |
18566 | } | |
18567 | } | |
18568 | else if (is_store && k == 0) | |
18569 | { | |
18570 | /* Similarly, Neon store patterns use operand 0 as | |
18571 | the memory location to store to (a SImode pointer). | |
18572 | Use a pointer to the element type of the store in | |
18573 | that position. */ | |
18574 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
18575 | ||
18576 | switch (1 << j) | |
18577 | { | |
18578 | case T_V8QI: | |
18579 | case T_V16QI: | |
18580 | eltype = intQI_pointer_node; | |
18581 | break; | |
18582 | ||
18583 | case T_V4HI: | |
18584 | case T_V8HI: | |
18585 | eltype = intHI_pointer_node; | |
18586 | break; | |
18587 | ||
18588 | case T_V2SI: | |
18589 | case T_V4SI: | |
18590 | eltype = intSI_pointer_node; | |
18591 | break; | |
18592 | ||
18593 | case T_V2SF: | |
18594 | case T_V4SF: | |
18595 | eltype = float_pointer_node; | |
18596 | break; | |
18597 | ||
18598 | case T_DI: | |
18599 | case T_V2DI: | |
18600 | eltype = intDI_pointer_node; | |
18601 | break; | |
18602 | ||
18603 | default: gcc_unreachable (); | |
18604 | } | |
18605 | } | |
18606 | else | |
18607 | { | |
18608 | switch (insn_data[icode].operand[k].mode) | |
18609 | { | |
18610 | case VOIDmode: eltype = void_type_node; break; | |
18611 | /* Scalars. */ | |
18612 | case QImode: eltype = neon_intQI_type_node; break; | |
18613 | case HImode: eltype = neon_intHI_type_node; break; | |
18614 | case SImode: eltype = neon_intSI_type_node; break; | |
18615 | case SFmode: eltype = neon_float_type_node; break; | |
18616 | case DImode: eltype = neon_intDI_type_node; break; | |
18617 | case TImode: eltype = intTI_type_node; break; | |
18618 | case EImode: eltype = intEI_type_node; break; | |
18619 | case OImode: eltype = intOI_type_node; break; | |
18620 | case CImode: eltype = intCI_type_node; break; | |
18621 | case XImode: eltype = intXI_type_node; break; | |
18622 | /* 64-bit vectors. */ | |
18623 | case V8QImode: eltype = V8QI_type_node; break; | |
18624 | case V4HImode: eltype = V4HI_type_node; break; | |
18625 | case V2SImode: eltype = V2SI_type_node; break; | |
18626 | case V2SFmode: eltype = V2SF_type_node; break; | |
18627 | /* 128-bit vectors. */ | |
18628 | case V16QImode: eltype = V16QI_type_node; break; | |
18629 | case V8HImode: eltype = V8HI_type_node; break; | |
18630 | case V4SImode: eltype = V4SI_type_node; break; | |
18631 | case V4SFmode: eltype = V4SF_type_node; break; | |
18632 | case V2DImode: eltype = V2DI_type_node; break; | |
18633 | default: gcc_unreachable (); | |
18634 | } | |
18635 | } | |
18636 | ||
18637 | if (k == 0 && !is_store) | |
18638 | return_type = eltype; | |
18639 | else | |
18640 | args = tree_cons (NULL_TREE, eltype, args); | |
18641 | } | |
18642 | ||
18643 | ftype = build_function_type (return_type, args); | |
18644 | } | |
18645 | break; | |
18646 | ||
18647 | case NEON_RESULTPAIR: | |
18648 | { | |
18649 | switch (insn_data[icode].operand[1].mode) | |
18650 | { | |
18651 | case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; | |
18652 | case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; | |
18653 | case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; | |
18654 | case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; | |
18655 | case DImode: ftype = void_ftype_pdi_di_di; break; | |
18656 | case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; | |
18657 | case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; | |
18658 | case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; | |
18659 | case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; | |
18660 | case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; | |
18661 | default: gcc_unreachable (); | |
18662 | } | |
18663 | } | |
18664 | break; | |
18665 | ||
18666 | case NEON_REINTERP: | |
18667 | { | |
18668 | /* We iterate over 5 doubleword types, then 5 quadword | |
18669 | types. */ | |
18670 | int rhs = j % 5; | |
18671 | switch (insn_data[icode].operand[0].mode) | |
18672 | { | |
18673 | case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; | |
18674 | case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; | |
18675 | case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; | |
18676 | case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; | |
18677 | case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; | |
18678 | case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; | |
18679 | case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; | |
18680 | case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; | |
18681 | case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; | |
18682 | case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; | |
18683 | default: gcc_unreachable (); | |
18684 | } | |
18685 | } | |
18686 | break; | |
18687 | ||
18688 | default: | |
18689 | gcc_unreachable (); | |
18690 | } | |
18691 | ||
18692 | gcc_assert (ftype != NULL); | |
18693 | ||
18694 | sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); | |
18695 | ||
18696 | add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, | |
18697 | NULL_TREE); | |
18698 | } | |
18699 | } | |
18700 | } | |
18701 | ||
0fd8c3ad SL |
18702 | static void |
18703 | arm_init_fp16_builtins (void) | |
18704 | { | |
18705 | tree fp16_type = make_node (REAL_TYPE); | |
18706 | TYPE_PRECISION (fp16_type) = 16; | |
18707 | layout_type (fp16_type); | |
18708 | (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16"); | |
18709 | } | |
18710 | ||
5a9335ef NC |
18711 | static void |
18712 | arm_init_builtins (void) | |
18713 | { | |
d3585b76 DJ |
18714 | arm_init_tls_builtins (); |
18715 | ||
5a9335ef NC |
18716 | if (TARGET_REALLY_IWMMXT) |
18717 | arm_init_iwmmxt_builtins (); | |
88f77cba JB |
18718 | |
18719 | if (TARGET_NEON) | |
18720 | arm_init_neon_builtins (); | |
0fd8c3ad SL |
18721 | |
18722 | if (arm_fp16_format) | |
18723 | arm_init_fp16_builtins (); | |
18724 | } | |
18725 | ||
18726 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
18727 | ||
18728 | static const char * | |
18729 | arm_invalid_parameter_type (const_tree t) | |
18730 | { | |
18731 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
18732 | return N_("function parameters cannot have __fp16 type"); | |
18733 | return NULL; | |
18734 | } | |
18735 | ||
18736 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
18737 | ||
18738 | static const char * | |
18739 | arm_invalid_return_type (const_tree t) | |
18740 | { | |
18741 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
18742 | return N_("functions cannot return __fp16 type"); | |
18743 | return NULL; | |
18744 | } | |
18745 | ||
18746 | /* Implement TARGET_PROMOTED_TYPE. */ | |
18747 | ||
18748 | static tree | |
18749 | arm_promoted_type (const_tree t) | |
18750 | { | |
18751 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
18752 | return float_type_node; | |
18753 | return NULL_TREE; | |
18754 | } | |
18755 | ||
18756 | /* Implement TARGET_CONVERT_TO_TYPE. | |
18757 | Specifically, this hook implements the peculiarity of the ARM | |
18758 | half-precision floating-point C semantics that requires conversions between | |
18759 | __fp16 to or from double to do an intermediate conversion to float. */ | |
18760 | ||
18761 | static tree | |
18762 | arm_convert_to_type (tree type, tree expr) | |
18763 | { | |
18764 | tree fromtype = TREE_TYPE (expr); | |
18765 | if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type)) | |
18766 | return NULL_TREE; | |
18767 | if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32) | |
18768 | || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32)) | |
18769 | return convert (type, convert (float_type_node, expr)); | |
18770 | return NULL_TREE; | |
5a9335ef NC |
18771 | } |
18772 | ||
bdc4827b SL |
18773 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. |
18774 | This simply adds HFmode as a supported mode; even though we don't | |
18775 | implement arithmetic on this type directly, it's supported by | |
18776 | optabs conversions, much the way the double-word arithmetic is | |
18777 | special-cased in the default hook. */ | |
18778 | ||
18779 | static bool | |
18780 | arm_scalar_mode_supported_p (enum machine_mode mode) | |
18781 | { | |
18782 | if (mode == HFmode) | |
18783 | return (arm_fp16_format != ARM_FP16_FORMAT_NONE); | |
18784 | else | |
18785 | return default_scalar_mode_supported_p (mode); | |
18786 | } | |
18787 | ||
5a9335ef NC |
18788 | /* Errors in the source file can cause expand_expr to return const0_rtx |
18789 | where we expect a vector. To avoid crashing, use one of the vector | |
18790 | clear instructions. */ | |
18791 | ||
18792 | static rtx | |
18793 | safe_vector_operand (rtx x, enum machine_mode mode) | |
18794 | { | |
18795 | if (x != const0_rtx) | |
18796 | return x; | |
18797 | x = gen_reg_rtx (mode); | |
18798 | ||
18799 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
18800 | : gen_rtx_SUBREG (DImode, x, 0))); | |
18801 | return x; | |
18802 | } | |
18803 | ||
18804 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
18805 | ||
18806 | static rtx | |
18807 | arm_expand_binop_builtin (enum insn_code icode, | |
5039610b | 18808 | tree exp, rtx target) |
5a9335ef NC |
18809 | { |
18810 | rtx pat; | |
5039610b SL |
18811 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
18812 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
18813 | rtx op0 = expand_normal (arg0); |
18814 | rtx op1 = expand_normal (arg1); | |
5a9335ef NC |
18815 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
18816 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
18817 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
18818 | ||
18819 | if (VECTOR_MODE_P (mode0)) | |
18820 | op0 = safe_vector_operand (op0, mode0); | |
18821 | if (VECTOR_MODE_P (mode1)) | |
18822 | op1 = safe_vector_operand (op1, mode1); | |
18823 | ||
18824 | if (! target | |
18825 | || GET_MODE (target) != tmode | |
18826 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
18827 | target = gen_reg_rtx (tmode); | |
18828 | ||
e6d29d15 | 18829 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
18830 | |
18831 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
18832 | op0 = copy_to_mode_reg (mode0, op0); | |
18833 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
18834 | op1 = copy_to_mode_reg (mode1, op1); | |
18835 | ||
18836 | pat = GEN_FCN (icode) (target, op0, op1); | |
18837 | if (! pat) | |
18838 | return 0; | |
18839 | emit_insn (pat); | |
18840 | return target; | |
18841 | } | |
18842 | ||
18843 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
18844 | ||
18845 | static rtx | |
18846 | arm_expand_unop_builtin (enum insn_code icode, | |
5039610b | 18847 | tree exp, rtx target, int do_load) |
5a9335ef NC |
18848 | { |
18849 | rtx pat; | |
5039610b | 18850 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 18851 | rtx op0 = expand_normal (arg0); |
5a9335ef NC |
18852 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
18853 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
18854 | ||
18855 | if (! target | |
18856 | || GET_MODE (target) != tmode | |
18857 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
18858 | target = gen_reg_rtx (tmode); | |
18859 | if (do_load) | |
18860 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
18861 | else | |
18862 | { | |
18863 | if (VECTOR_MODE_P (mode0)) | |
18864 | op0 = safe_vector_operand (op0, mode0); | |
18865 | ||
18866 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
18867 | op0 = copy_to_mode_reg (mode0, op0); | |
18868 | } | |
18869 | ||
18870 | pat = GEN_FCN (icode) (target, op0); | |
18871 | if (! pat) | |
18872 | return 0; | |
18873 | emit_insn (pat); | |
18874 | return target; | |
18875 | } | |
18876 | ||
88f77cba JB |
18877 | static int |
18878 | neon_builtin_compare (const void *a, const void *b) | |
18879 | { | |
5ead67f6 KG |
18880 | const neon_builtin_datum *const key = (const neon_builtin_datum *) a; |
18881 | const neon_builtin_datum *const memb = (const neon_builtin_datum *) b; | |
88f77cba JB |
18882 | unsigned int soughtcode = key->base_fcode; |
18883 | ||
18884 | if (soughtcode >= memb->base_fcode | |
18885 | && soughtcode < memb->base_fcode + memb->num_vars) | |
18886 | return 0; | |
18887 | else if (soughtcode < memb->base_fcode) | |
18888 | return -1; | |
18889 | else | |
18890 | return 1; | |
18891 | } | |
18892 | ||
18893 | static enum insn_code | |
18894 | locate_neon_builtin_icode (int fcode, neon_itype *itype) | |
18895 | { | |
18896 | neon_builtin_datum key, *found; | |
18897 | int idx; | |
18898 | ||
18899 | key.base_fcode = fcode; | |
5ead67f6 KG |
18900 | found = (neon_builtin_datum *) |
18901 | bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), | |
88f77cba JB |
18902 | sizeof (neon_builtin_data[0]), neon_builtin_compare); |
18903 | gcc_assert (found); | |
18904 | idx = fcode - (int) found->base_fcode; | |
18905 | gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); | |
18906 | ||
18907 | if (itype) | |
18908 | *itype = found->itype; | |
18909 | ||
18910 | return found->codes[idx]; | |
18911 | } | |
18912 | ||
18913 | typedef enum { | |
18914 | NEON_ARG_COPY_TO_REG, | |
18915 | NEON_ARG_CONSTANT, | |
18916 | NEON_ARG_STOP | |
18917 | } builtin_arg; | |
18918 | ||
18919 | #define NEON_MAX_BUILTIN_ARGS 5 | |
18920 | ||
18921 | /* Expand a Neon builtin. */ | |
18922 | static rtx | |
18923 | arm_expand_neon_args (rtx target, int icode, int have_retval, | |
18924 | tree exp, ...) | |
18925 | { | |
18926 | va_list ap; | |
18927 | rtx pat; | |
18928 | tree arg[NEON_MAX_BUILTIN_ARGS]; | |
18929 | rtx op[NEON_MAX_BUILTIN_ARGS]; | |
18930 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
18931 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | |
18932 | int argc = 0; | |
18933 | ||
18934 | if (have_retval | |
18935 | && (!target | |
18936 | || GET_MODE (target) != tmode | |
18937 | || !(*insn_data[icode].operand[0].predicate) (target, tmode))) | |
18938 | target = gen_reg_rtx (tmode); | |
18939 | ||
18940 | va_start (ap, exp); | |
18941 | ||
18942 | for (;;) | |
18943 | { | |
81f40b79 | 18944 | builtin_arg thisarg = (builtin_arg) va_arg (ap, int); |
88f77cba JB |
18945 | |
18946 | if (thisarg == NEON_ARG_STOP) | |
18947 | break; | |
18948 | else | |
18949 | { | |
18950 | arg[argc] = CALL_EXPR_ARG (exp, argc); | |
18951 | op[argc] = expand_normal (arg[argc]); | |
18952 | mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | |
18953 | ||
18954 | switch (thisarg) | |
18955 | { | |
18956 | case NEON_ARG_COPY_TO_REG: | |
18957 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | |
18958 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
18959 | (op[argc], mode[argc])) | |
18960 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | |
18961 | break; | |
18962 | ||
18963 | case NEON_ARG_CONSTANT: | |
18964 | /* FIXME: This error message is somewhat unhelpful. */ | |
18965 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
18966 | (op[argc], mode[argc])) | |
18967 | error ("argument must be a constant"); | |
18968 | break; | |
18969 | ||
18970 | case NEON_ARG_STOP: | |
18971 | gcc_unreachable (); | |
18972 | } | |
18973 | ||
18974 | argc++; | |
18975 | } | |
18976 | } | |
18977 | ||
18978 | va_end (ap); | |
18979 | ||
18980 | if (have_retval) | |
18981 | switch (argc) | |
18982 | { | |
18983 | case 1: | |
18984 | pat = GEN_FCN (icode) (target, op[0]); | |
18985 | break; | |
18986 | ||
18987 | case 2: | |
18988 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
18989 | break; | |
18990 | ||
18991 | case 3: | |
18992 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
18993 | break; | |
18994 | ||
18995 | case 4: | |
18996 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
18997 | break; | |
18998 | ||
18999 | case 5: | |
19000 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
19001 | break; | |
19002 | ||
19003 | default: | |
19004 | gcc_unreachable (); | |
19005 | } | |
19006 | else | |
19007 | switch (argc) | |
19008 | { | |
19009 | case 1: | |
19010 | pat = GEN_FCN (icode) (op[0]); | |
19011 | break; | |
19012 | ||
19013 | case 2: | |
19014 | pat = GEN_FCN (icode) (op[0], op[1]); | |
19015 | break; | |
19016 | ||
19017 | case 3: | |
19018 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
19019 | break; | |
19020 | ||
19021 | case 4: | |
19022 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
19023 | break; | |
19024 | ||
19025 | case 5: | |
19026 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
19027 | break; | |
19028 | ||
19029 | default: | |
19030 | gcc_unreachable (); | |
19031 | } | |
19032 | ||
19033 | if (!pat) | |
19034 | return 0; | |
19035 | ||
19036 | emit_insn (pat); | |
19037 | ||
19038 | return target; | |
19039 | } | |
19040 | ||
19041 | /* Expand a Neon builtin. These are "special" because they don't have symbolic | |
19042 | constants defined per-instruction or per instruction-variant. Instead, the | |
19043 | required info is looked up in the table neon_builtin_data. */ | |
19044 | static rtx | |
19045 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | |
19046 | { | |
19047 | neon_itype itype; | |
19048 | enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | |
19049 | ||
19050 | switch (itype) | |
19051 | { | |
19052 | case NEON_UNOP: | |
19053 | case NEON_CONVERT: | |
19054 | case NEON_DUPLANE: | |
19055 | return arm_expand_neon_args (target, icode, 1, exp, | |
19056 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19057 | ||
19058 | case NEON_BINOP: | |
19059 | case NEON_SETLANE: | |
19060 | case NEON_SCALARMUL: | |
19061 | case NEON_SCALARMULL: | |
19062 | case NEON_SCALARMULH: | |
19063 | case NEON_SHIFTINSERT: | |
19064 | case NEON_LOGICBINOP: | |
19065 | return arm_expand_neon_args (target, icode, 1, exp, | |
19066 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19067 | NEON_ARG_STOP); | |
19068 | ||
19069 | case NEON_TERNOP: | |
19070 | return arm_expand_neon_args (target, icode, 1, exp, | |
19071 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19072 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19073 | ||
19074 | case NEON_GETLANE: | |
19075 | case NEON_FIXCONV: | |
19076 | case NEON_SHIFTIMM: | |
19077 | return arm_expand_neon_args (target, icode, 1, exp, | |
19078 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | |
19079 | NEON_ARG_STOP); | |
19080 | ||
19081 | case NEON_CREATE: | |
19082 | return arm_expand_neon_args (target, icode, 1, exp, | |
19083 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19084 | ||
19085 | case NEON_DUP: | |
19086 | case NEON_SPLIT: | |
19087 | case NEON_REINTERP: | |
19088 | return arm_expand_neon_args (target, icode, 1, exp, | |
19089 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19090 | ||
19091 | case NEON_COMBINE: | |
19092 | case NEON_VTBL: | |
19093 | return arm_expand_neon_args (target, icode, 1, exp, | |
19094 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19095 | ||
19096 | case NEON_RESULTPAIR: | |
19097 | return arm_expand_neon_args (target, icode, 0, exp, | |
19098 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19099 | NEON_ARG_STOP); | |
19100 | ||
19101 | case NEON_LANEMUL: | |
19102 | case NEON_LANEMULL: | |
19103 | case NEON_LANEMULH: | |
19104 | return arm_expand_neon_args (target, icode, 1, exp, | |
19105 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19106 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19107 | ||
19108 | case NEON_LANEMAC: | |
19109 | return arm_expand_neon_args (target, icode, 1, exp, | |
19110 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19111 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19112 | ||
19113 | case NEON_SHIFTACC: | |
19114 | return arm_expand_neon_args (target, icode, 1, exp, | |
19115 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19116 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19117 | ||
19118 | case NEON_SCALARMAC: | |
19119 | return arm_expand_neon_args (target, icode, 1, exp, | |
19120 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19121 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
19122 | ||
19123 | case NEON_SELECT: | |
19124 | case NEON_VTBX: | |
19125 | return arm_expand_neon_args (target, icode, 1, exp, | |
19126 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
19127 | NEON_ARG_STOP); | |
19128 | ||
19129 | case NEON_LOAD1: | |
19130 | case NEON_LOADSTRUCT: | |
19131 | return arm_expand_neon_args (target, icode, 1, exp, | |
19132 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19133 | ||
19134 | case NEON_LOAD1LANE: | |
19135 | case NEON_LOADSTRUCTLANE: | |
19136 | return arm_expand_neon_args (target, icode, 1, exp, | |
19137 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19138 | NEON_ARG_STOP); | |
19139 | ||
19140 | case NEON_STORE1: | |
19141 | case NEON_STORESTRUCT: | |
19142 | return arm_expand_neon_args (target, icode, 0, exp, | |
19143 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
19144 | ||
19145 | case NEON_STORE1LANE: | |
19146 | case NEON_STORESTRUCTLANE: | |
19147 | return arm_expand_neon_args (target, icode, 0, exp, | |
19148 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
19149 | NEON_ARG_STOP); | |
19150 | } | |
19151 | ||
19152 | gcc_unreachable (); | |
19153 | } | |
19154 | ||
19155 | /* Emit code to reinterpret one Neon type as another, without altering bits. */ | |
19156 | void | |
19157 | neon_reinterpret (rtx dest, rtx src) | |
19158 | { | |
19159 | emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); | |
19160 | } | |
19161 | ||
19162 | /* Emit code to place a Neon pair result in memory locations (with equal | |
19163 | registers). */ | |
19164 | void | |
19165 | neon_emit_pair_result_insn (enum machine_mode mode, | |
19166 | rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, | |
19167 | rtx op1, rtx op2) | |
19168 | { | |
19169 | rtx mem = gen_rtx_MEM (mode, destaddr); | |
19170 | rtx tmp1 = gen_reg_rtx (mode); | |
19171 | rtx tmp2 = gen_reg_rtx (mode); | |
19172 | ||
19173 | emit_insn (intfn (tmp1, op1, tmp2, op2)); | |
19174 | ||
19175 | emit_move_insn (mem, tmp1); | |
19176 | mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); | |
19177 | emit_move_insn (mem, tmp2); | |
19178 | } | |
19179 | ||
19180 | /* Set up operands for a register copy from src to dest, taking care not to | |
19181 | clobber registers in the process. | |
19182 | FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't | |
19183 | be called with a large N, so that should be OK. */ | |
19184 | ||
19185 | void | |
19186 | neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) | |
19187 | { | |
19188 | unsigned int copied = 0, opctr = 0; | |
19189 | unsigned int done = (1 << count) - 1; | |
19190 | unsigned int i, j; | |
19191 | ||
19192 | while (copied != done) | |
19193 | { | |
19194 | for (i = 0; i < count; i++) | |
19195 | { | |
19196 | int good = 1; | |
19197 | ||
19198 | for (j = 0; good && j < count; j++) | |
19199 | if (i != j && (copied & (1 << j)) == 0 | |
19200 | && reg_overlap_mentioned_p (src[j], dest[i])) | |
19201 | good = 0; | |
19202 | ||
19203 | if (good) | |
19204 | { | |
19205 | operands[opctr++] = dest[i]; | |
19206 | operands[opctr++] = src[i]; | |
19207 | copied |= 1 << i; | |
19208 | } | |
19209 | } | |
19210 | } | |
19211 | ||
19212 | gcc_assert (opctr == count * 2); | |
19213 | } | |
19214 | ||
5a9335ef NC |
19215 | /* Expand an expression EXP that calls a built-in function, |
19216 | with result going to TARGET if that's convenient | |
19217 | (and in mode MODE if that's convenient). | |
19218 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
19219 | IGNORE is nonzero if the value is to be ignored. */ | |
19220 | ||
19221 | static rtx | |
19222 | arm_expand_builtin (tree exp, | |
19223 | rtx target, | |
19224 | rtx subtarget ATTRIBUTE_UNUSED, | |
19225 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
19226 | int ignore ATTRIBUTE_UNUSED) | |
19227 | { | |
19228 | const struct builtin_description * d; | |
19229 | enum insn_code icode; | |
5039610b | 19230 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
5a9335ef NC |
19231 | tree arg0; |
19232 | tree arg1; | |
19233 | tree arg2; | |
19234 | rtx op0; | |
19235 | rtx op1; | |
19236 | rtx op2; | |
19237 | rtx pat; | |
19238 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
19239 | size_t i; | |
19240 | enum machine_mode tmode; | |
19241 | enum machine_mode mode0; | |
19242 | enum machine_mode mode1; | |
19243 | enum machine_mode mode2; | |
19244 | ||
88f77cba JB |
19245 | if (fcode >= ARM_BUILTIN_NEON_BASE) |
19246 | return arm_expand_neon_builtin (fcode, exp, target); | |
19247 | ||
5a9335ef NC |
19248 | switch (fcode) |
19249 | { | |
19250 | case ARM_BUILTIN_TEXTRMSB: | |
19251 | case ARM_BUILTIN_TEXTRMUB: | |
19252 | case ARM_BUILTIN_TEXTRMSH: | |
19253 | case ARM_BUILTIN_TEXTRMUH: | |
19254 | case ARM_BUILTIN_TEXTRMSW: | |
19255 | case ARM_BUILTIN_TEXTRMUW: | |
19256 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
19257 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
19258 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
19259 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
19260 | : CODE_FOR_iwmmxt_textrmw); | |
19261 | ||
5039610b SL |
19262 | arg0 = CALL_EXPR_ARG (exp, 0); |
19263 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19264 | op0 = expand_normal (arg0); |
19265 | op1 = expand_normal (arg1); | |
5a9335ef NC |
19266 | tmode = insn_data[icode].operand[0].mode; |
19267 | mode0 = insn_data[icode].operand[1].mode; | |
19268 | mode1 = insn_data[icode].operand[2].mode; | |
19269 | ||
19270 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19271 | op0 = copy_to_mode_reg (mode0, op0); | |
19272 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19273 | { | |
19274 | /* @@@ better error message */ | |
19275 | error ("selector must be an immediate"); | |
19276 | return gen_reg_rtx (tmode); | |
19277 | } | |
19278 | if (target == 0 | |
19279 | || GET_MODE (target) != tmode | |
19280 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19281 | target = gen_reg_rtx (tmode); | |
19282 | pat = GEN_FCN (icode) (target, op0, op1); | |
19283 | if (! pat) | |
19284 | return 0; | |
19285 | emit_insn (pat); | |
19286 | return target; | |
19287 | ||
19288 | case ARM_BUILTIN_TINSRB: | |
19289 | case ARM_BUILTIN_TINSRH: | |
19290 | case ARM_BUILTIN_TINSRW: | |
19291 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
19292 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
19293 | : CODE_FOR_iwmmxt_tinsrw); | |
5039610b SL |
19294 | arg0 = CALL_EXPR_ARG (exp, 0); |
19295 | arg1 = CALL_EXPR_ARG (exp, 1); | |
19296 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
19297 | op0 = expand_normal (arg0); |
19298 | op1 = expand_normal (arg1); | |
19299 | op2 = expand_normal (arg2); | |
5a9335ef NC |
19300 | tmode = insn_data[icode].operand[0].mode; |
19301 | mode0 = insn_data[icode].operand[1].mode; | |
19302 | mode1 = insn_data[icode].operand[2].mode; | |
19303 | mode2 = insn_data[icode].operand[3].mode; | |
19304 | ||
19305 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19306 | op0 = copy_to_mode_reg (mode0, op0); | |
19307 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19308 | op1 = copy_to_mode_reg (mode1, op1); | |
19309 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
19310 | { | |
19311 | /* @@@ better error message */ | |
19312 | error ("selector must be an immediate"); | |
19313 | return const0_rtx; | |
19314 | } | |
19315 | if (target == 0 | |
19316 | || GET_MODE (target) != tmode | |
19317 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19318 | target = gen_reg_rtx (tmode); | |
19319 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
19320 | if (! pat) | |
19321 | return 0; | |
19322 | emit_insn (pat); | |
19323 | return target; | |
19324 | ||
19325 | case ARM_BUILTIN_SETWCX: | |
5039610b SL |
19326 | arg0 = CALL_EXPR_ARG (exp, 0); |
19327 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19328 | op0 = force_reg (SImode, expand_normal (arg0)); |
19329 | op1 = expand_normal (arg1); | |
f07a6b21 | 19330 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); |
5a9335ef NC |
19331 | return 0; |
19332 | ||
19333 | case ARM_BUILTIN_GETWCX: | |
5039610b | 19334 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 19335 | op0 = expand_normal (arg0); |
5a9335ef NC |
19336 | target = gen_reg_rtx (SImode); |
19337 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
19338 | return target; | |
19339 | ||
19340 | case ARM_BUILTIN_WSHUFH: | |
19341 | icode = CODE_FOR_iwmmxt_wshufh; | |
5039610b SL |
19342 | arg0 = CALL_EXPR_ARG (exp, 0); |
19343 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
19344 | op0 = expand_normal (arg0); |
19345 | op1 = expand_normal (arg1); | |
5a9335ef NC |
19346 | tmode = insn_data[icode].operand[0].mode; |
19347 | mode1 = insn_data[icode].operand[1].mode; | |
19348 | mode2 = insn_data[icode].operand[2].mode; | |
19349 | ||
19350 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
19351 | op0 = copy_to_mode_reg (mode1, op0); | |
19352 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
19353 | { | |
19354 | /* @@@ better error message */ | |
19355 | error ("mask must be an immediate"); | |
19356 | return const0_rtx; | |
19357 | } | |
19358 | if (target == 0 | |
19359 | || GET_MODE (target) != tmode | |
19360 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19361 | target = gen_reg_rtx (tmode); | |
19362 | pat = GEN_FCN (icode) (target, op0, op1); | |
19363 | if (! pat) | |
19364 | return 0; | |
19365 | emit_insn (pat); | |
19366 | return target; | |
19367 | ||
19368 | case ARM_BUILTIN_WSADB: | |
5039610b | 19369 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target); |
5a9335ef | 19370 | case ARM_BUILTIN_WSADH: |
5039610b | 19371 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target); |
5a9335ef | 19372 | case ARM_BUILTIN_WSADBZ: |
5039610b | 19373 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); |
5a9335ef | 19374 | case ARM_BUILTIN_WSADHZ: |
5039610b | 19375 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); |
5a9335ef NC |
19376 | |
19377 | /* Several three-argument builtins. */ | |
19378 | case ARM_BUILTIN_WMACS: | |
19379 | case ARM_BUILTIN_WMACU: | |
19380 | case ARM_BUILTIN_WALIGN: | |
19381 | case ARM_BUILTIN_TMIA: | |
19382 | case ARM_BUILTIN_TMIAPH: | |
19383 | case ARM_BUILTIN_TMIATT: | |
19384 | case ARM_BUILTIN_TMIATB: | |
19385 | case ARM_BUILTIN_TMIABT: | |
19386 | case ARM_BUILTIN_TMIABB: | |
19387 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
19388 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
19389 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
19390 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
19391 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
19392 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
19393 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
19394 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
19395 | : CODE_FOR_iwmmxt_walign); | |
5039610b SL |
19396 | arg0 = CALL_EXPR_ARG (exp, 0); |
19397 | arg1 = CALL_EXPR_ARG (exp, 1); | |
19398 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
19399 | op0 = expand_normal (arg0); |
19400 | op1 = expand_normal (arg1); | |
19401 | op2 = expand_normal (arg2); | |
5a9335ef NC |
19402 | tmode = insn_data[icode].operand[0].mode; |
19403 | mode0 = insn_data[icode].operand[1].mode; | |
19404 | mode1 = insn_data[icode].operand[2].mode; | |
19405 | mode2 = insn_data[icode].operand[3].mode; | |
19406 | ||
19407 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
19408 | op0 = copy_to_mode_reg (mode0, op0); | |
19409 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
19410 | op1 = copy_to_mode_reg (mode1, op1); | |
19411 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
19412 | op2 = copy_to_mode_reg (mode2, op2); | |
19413 | if (target == 0 | |
19414 | || GET_MODE (target) != tmode | |
19415 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
19416 | target = gen_reg_rtx (tmode); | |
19417 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
19418 | if (! pat) | |
19419 | return 0; | |
19420 | emit_insn (pat); | |
19421 | return target; | |
f676971a | 19422 | |
5a9335ef NC |
19423 | case ARM_BUILTIN_WZERO: |
19424 | target = gen_reg_rtx (DImode); | |
19425 | emit_insn (gen_iwmmxt_clrdi (target)); | |
19426 | return target; | |
19427 | ||
d3585b76 DJ |
19428 | case ARM_BUILTIN_THREAD_POINTER: |
19429 | return arm_load_tp (target); | |
19430 | ||
5a9335ef NC |
19431 | default: |
19432 | break; | |
19433 | } | |
19434 | ||
e97a46ce | 19435 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef | 19436 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 19437 | return arm_expand_binop_builtin (d->icode, exp, target); |
5a9335ef | 19438 | |
e97a46ce | 19439 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef | 19440 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 19441 | return arm_expand_unop_builtin (d->icode, exp, target, 0); |
5a9335ef NC |
19442 | |
19443 | /* @@@ Should really do something sensible here. */ | |
19444 | return NULL_RTX; | |
19445 | } | |
19446 | \f | |
1d6e90ac NC |
19447 | /* Return the number (counting from 0) of |
19448 | the least significant set bit in MASK. */ | |
19449 | ||
e32bac5b | 19450 | inline static int |
b279b20a | 19451 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
19452 | { |
19453 | int bit; | |
19454 | ||
19455 | for (bit = 0; | |
19456 | (mask & (1 << bit)) == 0; | |
5895f793 | 19457 | ++bit) |
d5b7b3ae RE |
19458 | continue; |
19459 | ||
19460 | return bit; | |
19461 | } | |
19462 | ||
b279b20a NC |
19463 | /* Emit code to push or pop registers to or from the stack. F is the |
19464 | assembly file. MASK is the registers to push or pop. PUSH is | |
19465 | nonzero if we should push, and zero if we should pop. For debugging | |
19466 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
19467 | to the stack. REAL_REGS should have the same number of bits set as | |
19468 | MASK, and will be used instead (in the same order) to describe which | |
19469 | registers were saved - this is used to mark the save slots when we | |
19470 | push high registers after moving them to low registers. */ | |
19471 | static void | |
19472 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
19473 | unsigned long real_regs) | |
19474 | { | |
19475 | int regno; | |
19476 | int lo_mask = mask & 0xFF; | |
19477 | int pushed_words = 0; | |
19478 | ||
e6d29d15 | 19479 | gcc_assert (mask); |
b279b20a NC |
19480 | |
19481 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
19482 | { | |
19483 | /* Special case. Do not generate a POP PC statement here, do it in | |
19484 | thumb_exit() */ | |
19485 | thumb_exit (f, -1); | |
19486 | return; | |
19487 | } | |
19488 | ||
617a1b71 PB |
19489 | if (ARM_EABI_UNWIND_TABLES && push) |
19490 | { | |
19491 | fprintf (f, "\t.save\t{"); | |
19492 | for (regno = 0; regno < 15; regno++) | |
19493 | { | |
19494 | if (real_regs & (1 << regno)) | |
19495 | { | |
19496 | if (real_regs & ((1 << regno) -1)) | |
19497 | fprintf (f, ", "); | |
19498 | asm_fprintf (f, "%r", regno); | |
19499 | } | |
19500 | } | |
19501 | fprintf (f, "}\n"); | |
19502 | } | |
19503 | ||
b279b20a NC |
19504 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
19505 | ||
19506 | /* Look at the low registers first. */ | |
19507 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
19508 | { | |
19509 | if (lo_mask & 1) | |
19510 | { | |
19511 | asm_fprintf (f, "%r", regno); | |
19512 | ||
19513 | if ((lo_mask & ~1) != 0) | |
19514 | fprintf (f, ", "); | |
19515 | ||
19516 | pushed_words++; | |
19517 | } | |
19518 | } | |
19519 | ||
19520 | if (push && (mask & (1 << LR_REGNUM))) | |
19521 | { | |
19522 | /* Catch pushing the LR. */ | |
19523 | if (mask & 0xFF) | |
19524 | fprintf (f, ", "); | |
19525 | ||
19526 | asm_fprintf (f, "%r", LR_REGNUM); | |
19527 | ||
19528 | pushed_words++; | |
19529 | } | |
19530 | else if (!push && (mask & (1 << PC_REGNUM))) | |
19531 | { | |
19532 | /* Catch popping the PC. */ | |
19533 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
e3b5732b | 19534 | || crtl->calls_eh_return) |
b279b20a NC |
19535 | { |
19536 | /* The PC is never poped directly, instead | |
19537 | it is popped into r3 and then BX is used. */ | |
19538 | fprintf (f, "}\n"); | |
19539 | ||
19540 | thumb_exit (f, -1); | |
19541 | ||
19542 | return; | |
19543 | } | |
19544 | else | |
19545 | { | |
19546 | if (mask & 0xFF) | |
19547 | fprintf (f, ", "); | |
19548 | ||
19549 | asm_fprintf (f, "%r", PC_REGNUM); | |
19550 | } | |
19551 | } | |
19552 | ||
19553 | fprintf (f, "}\n"); | |
19554 | ||
19555 | if (push && pushed_words && dwarf2out_do_frame ()) | |
19556 | { | |
d342c045 | 19557 | char *l = dwarf2out_cfi_label (false); |
b279b20a NC |
19558 | int pushed_mask = real_regs; |
19559 | ||
19560 | *cfa_offset += pushed_words * 4; | |
19561 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
19562 | ||
19563 | pushed_words = 0; | |
19564 | pushed_mask = real_regs; | |
19565 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
19566 | { | |
19567 | if (pushed_mask & 1) | |
19568 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
19569 | } | |
19570 | } | |
19571 | } | |
19572 | ||
d5b7b3ae RE |
19573 | /* Generate code to return from a thumb function. |
19574 | If 'reg_containing_return_addr' is -1, then the return address is | |
19575 | actually on the stack, at the stack pointer. */ | |
19576 | static void | |
c9ca9b88 | 19577 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
19578 | { |
19579 | unsigned regs_available_for_popping; | |
19580 | unsigned regs_to_pop; | |
19581 | int pops_needed; | |
19582 | unsigned available; | |
19583 | unsigned required; | |
19584 | int mode; | |
19585 | int size; | |
19586 | int restore_a4 = FALSE; | |
19587 | ||
19588 | /* Compute the registers we need to pop. */ | |
19589 | regs_to_pop = 0; | |
19590 | pops_needed = 0; | |
19591 | ||
c9ca9b88 | 19592 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 19593 | { |
d5b7b3ae | 19594 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 19595 | ++pops_needed; |
d5b7b3ae RE |
19596 | } |
19597 | ||
19598 | if (TARGET_BACKTRACE) | |
19599 | { | |
19600 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
19601 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
19602 | pops_needed += 2; | |
19603 | } | |
19604 | ||
19605 | /* If there is nothing to pop then just emit the BX instruction and | |
19606 | return. */ | |
19607 | if (pops_needed == 0) | |
19608 | { | |
e3b5732b | 19609 | if (crtl->calls_eh_return) |
c9ca9b88 | 19610 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
19611 | |
19612 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
19613 | return; | |
19614 | } | |
19615 | /* Otherwise if we are not supporting interworking and we have not created | |
19616 | a backtrace structure and the function was not entered in ARM mode then | |
19617 | just pop the return address straight into the PC. */ | |
5895f793 RE |
19618 | else if (!TARGET_INTERWORK |
19619 | && !TARGET_BACKTRACE | |
c9ca9b88 | 19620 | && !is_called_in_ARM_mode (current_function_decl) |
e3b5732b | 19621 | && !crtl->calls_eh_return) |
d5b7b3ae | 19622 | { |
c9ca9b88 | 19623 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
19624 | return; |
19625 | } | |
19626 | ||
19627 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
19628 | regs_available_for_popping = 0; | |
19629 | ||
19630 | /* If returning via __builtin_eh_return, the bottom three registers | |
19631 | all contain information needed for the return. */ | |
e3b5732b | 19632 | if (crtl->calls_eh_return) |
d5b7b3ae RE |
19633 | size = 12; |
19634 | else | |
19635 | { | |
d5b7b3ae RE |
19636 | /* If we can deduce the registers used from the function's |
19637 | return value. This is more reliable that examining | |
6fb5fa3c | 19638 | df_regs_ever_live_p () because that will be set if the register is |
d5b7b3ae RE |
19639 | ever used in the function, not just if the register is used |
19640 | to hold a return value. */ | |
19641 | ||
38173d38 JH |
19642 | if (crtl->return_rtx != 0) |
19643 | mode = GET_MODE (crtl->return_rtx); | |
d5b7b3ae | 19644 | else |
d5b7b3ae RE |
19645 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
19646 | ||
19647 | size = GET_MODE_SIZE (mode); | |
19648 | ||
19649 | if (size == 0) | |
19650 | { | |
19651 | /* In a void function we can use any argument register. | |
19652 | In a function that returns a structure on the stack | |
19653 | we can use the second and third argument registers. */ | |
19654 | if (mode == VOIDmode) | |
19655 | regs_available_for_popping = | |
19656 | (1 << ARG_REGISTER (1)) | |
19657 | | (1 << ARG_REGISTER (2)) | |
19658 | | (1 << ARG_REGISTER (3)); | |
19659 | else | |
19660 | regs_available_for_popping = | |
19661 | (1 << ARG_REGISTER (2)) | |
19662 | | (1 << ARG_REGISTER (3)); | |
19663 | } | |
19664 | else if (size <= 4) | |
19665 | regs_available_for_popping = | |
19666 | (1 << ARG_REGISTER (2)) | |
19667 | | (1 << ARG_REGISTER (3)); | |
19668 | else if (size <= 8) | |
19669 | regs_available_for_popping = | |
19670 | (1 << ARG_REGISTER (3)); | |
19671 | } | |
19672 | ||
19673 | /* Match registers to be popped with registers into which we pop them. */ | |
19674 | for (available = regs_available_for_popping, | |
19675 | required = regs_to_pop; | |
19676 | required != 0 && available != 0; | |
19677 | available &= ~(available & - available), | |
19678 | required &= ~(required & - required)) | |
19679 | -- pops_needed; | |
19680 | ||
19681 | /* If we have any popping registers left over, remove them. */ | |
19682 | if (available > 0) | |
5895f793 | 19683 | regs_available_for_popping &= ~available; |
f676971a | 19684 | |
d5b7b3ae RE |
19685 | /* Otherwise if we need another popping register we can use |
19686 | the fourth argument register. */ | |
19687 | else if (pops_needed) | |
19688 | { | |
19689 | /* If we have not found any free argument registers and | |
19690 | reg a4 contains the return address, we must move it. */ | |
19691 | if (regs_available_for_popping == 0 | |
19692 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
19693 | { | |
19694 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
19695 | reg_containing_return_addr = LR_REGNUM; | |
19696 | } | |
19697 | else if (size > 12) | |
19698 | { | |
19699 | /* Register a4 is being used to hold part of the return value, | |
19700 | but we have dire need of a free, low register. */ | |
19701 | restore_a4 = TRUE; | |
f676971a | 19702 | |
d5b7b3ae RE |
19703 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
19704 | } | |
f676971a | 19705 | |
d5b7b3ae RE |
19706 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
19707 | { | |
19708 | /* The fourth argument register is available. */ | |
19709 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 19710 | |
5895f793 | 19711 | --pops_needed; |
d5b7b3ae RE |
19712 | } |
19713 | } | |
19714 | ||
19715 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
19716 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
19717 | regs_available_for_popping); | |
d5b7b3ae RE |
19718 | |
19719 | /* Process the registers we popped. */ | |
19720 | if (reg_containing_return_addr == -1) | |
19721 | { | |
19722 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 19723 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 19724 | |
d5b7b3ae RE |
19725 | reg_containing_return_addr = |
19726 | number_of_first_bit_set (regs_available_for_popping); | |
19727 | ||
19728 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 19729 | the return address will not be corrupted by further pops. */ |
5895f793 | 19730 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
19731 | } |
19732 | ||
19733 | /* If we popped other registers then handle them here. */ | |
19734 | if (regs_available_for_popping) | |
19735 | { | |
19736 | int frame_pointer; | |
f676971a | 19737 | |
d5b7b3ae RE |
19738 | /* Work out which register currently contains the frame pointer. */ |
19739 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
19740 | ||
19741 | /* Move it into the correct place. */ | |
19742 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
19743 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
19744 | ||
19745 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
19746 | regs_available_for_popping &= ~(1 << frame_pointer); |
19747 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 19748 | |
d5b7b3ae RE |
19749 | if (regs_available_for_popping) |
19750 | { | |
19751 | int stack_pointer; | |
f676971a | 19752 | |
d5b7b3ae RE |
19753 | /* We popped the stack pointer as well, |
19754 | find the register that contains it. */ | |
19755 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
19756 | ||
19757 | /* Move it into the stack register. */ | |
19758 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 19759 | |
d5b7b3ae RE |
19760 | /* At this point we have popped all necessary registers, so |
19761 | do not worry about restoring regs_available_for_popping | |
19762 | to its correct value: | |
19763 | ||
19764 | assert (pops_needed == 0) | |
19765 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
19766 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
19767 | } | |
19768 | else | |
19769 | { | |
19770 | /* Since we have just move the popped value into the frame | |
19771 | pointer, the popping register is available for reuse, and | |
19772 | we know that we still have the stack pointer left to pop. */ | |
19773 | regs_available_for_popping |= (1 << frame_pointer); | |
19774 | } | |
19775 | } | |
f676971a | 19776 | |
d5b7b3ae RE |
19777 | /* If we still have registers left on the stack, but we no longer have |
19778 | any registers into which we can pop them, then we must move the return | |
19779 | address into the link register and make available the register that | |
19780 | contained it. */ | |
19781 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
19782 | { | |
19783 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 19784 | |
d5b7b3ae RE |
19785 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
19786 | reg_containing_return_addr); | |
f676971a | 19787 | |
d5b7b3ae RE |
19788 | reg_containing_return_addr = LR_REGNUM; |
19789 | } | |
19790 | ||
19791 | /* If we have registers left on the stack then pop some more. | |
19792 | We know that at most we will want to pop FP and SP. */ | |
19793 | if (pops_needed > 0) | |
19794 | { | |
19795 | int popped_into; | |
19796 | int move_to; | |
f676971a | 19797 | |
980e61bb DJ |
19798 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
19799 | regs_available_for_popping); | |
d5b7b3ae RE |
19800 | |
19801 | /* We have popped either FP or SP. | |
19802 | Move whichever one it is into the correct register. */ | |
19803 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
19804 | move_to = number_of_first_bit_set (regs_to_pop); | |
19805 | ||
19806 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
19807 | ||
5895f793 | 19808 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 19809 | |
5895f793 | 19810 | --pops_needed; |
d5b7b3ae | 19811 | } |
f676971a | 19812 | |
d5b7b3ae RE |
19813 | /* If we still have not popped everything then we must have only |
19814 | had one register available to us and we are now popping the SP. */ | |
19815 | if (pops_needed > 0) | |
19816 | { | |
19817 | int popped_into; | |
f676971a | 19818 | |
980e61bb DJ |
19819 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
19820 | regs_available_for_popping); | |
d5b7b3ae RE |
19821 | |
19822 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
19823 | ||
19824 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
19825 | /* | |
19826 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
19827 | assert (pops_needed == 1) | |
19828 | */ | |
19829 | } | |
19830 | ||
19831 | /* If necessary restore the a4 register. */ | |
19832 | if (restore_a4) | |
19833 | { | |
19834 | if (reg_containing_return_addr != LR_REGNUM) | |
19835 | { | |
19836 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
19837 | reg_containing_return_addr = LR_REGNUM; | |
19838 | } | |
f676971a | 19839 | |
d5b7b3ae RE |
19840 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
19841 | } | |
19842 | ||
e3b5732b | 19843 | if (crtl->calls_eh_return) |
c9ca9b88 | 19844 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
19845 | |
19846 | /* Return to caller. */ | |
19847 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
19848 | } | |
d5b7b3ae | 19849 | \f |
906668bb BS |
19850 | /* Scan INSN just before assembler is output for it. |
19851 | For Thumb-1, we track the status of the condition codes; this | |
19852 | information is used in the cbranchsi4_insn pattern. */ | |
d5b7b3ae | 19853 | void |
5b3e6663 | 19854 | thumb1_final_prescan_insn (rtx insn) |
d5b7b3ae | 19855 | { |
d5b7b3ae | 19856 | if (flag_print_asm_name) |
9d98a694 AO |
19857 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
19858 | INSN_ADDRESSES (INSN_UID (insn))); | |
906668bb BS |
19859 | /* Don't overwrite the previous setter when we get to a cbranch. */ |
19860 | if (INSN_CODE (insn) != CODE_FOR_cbranchsi4_insn) | |
19861 | { | |
19862 | enum attr_conds conds; | |
19863 | ||
19864 | if (cfun->machine->thumb1_cc_insn) | |
19865 | { | |
19866 | if (modified_in_p (cfun->machine->thumb1_cc_op0, insn) | |
19867 | || modified_in_p (cfun->machine->thumb1_cc_op1, insn)) | |
19868 | CC_STATUS_INIT; | |
19869 | } | |
19870 | conds = get_attr_conds (insn); | |
19871 | if (conds == CONDS_SET) | |
19872 | { | |
19873 | rtx set = single_set (insn); | |
19874 | cfun->machine->thumb1_cc_insn = insn; | |
19875 | cfun->machine->thumb1_cc_op0 = SET_DEST (set); | |
19876 | cfun->machine->thumb1_cc_op1 = const0_rtx; | |
19877 | cfun->machine->thumb1_cc_mode = CC_NOOVmode; | |
19878 | if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn) | |
19879 | { | |
19880 | rtx src1 = XEXP (SET_SRC (set), 1); | |
19881 | if (src1 == const0_rtx) | |
19882 | cfun->machine->thumb1_cc_mode = CCmode; | |
19883 | } | |
19884 | } | |
19885 | else if (conds != CONDS_NOCOND) | |
19886 | cfun->machine->thumb1_cc_insn = NULL_RTX; | |
19887 | } | |
d5b7b3ae RE |
19888 | } |
19889 | ||
19890 | int | |
e32bac5b | 19891 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
19892 | { |
19893 | unsigned HOST_WIDE_INT mask = 0xff; | |
19894 | int i; | |
19895 | ||
ce41c38b | 19896 | val = val & (unsigned HOST_WIDE_INT)0xffffffffu; |
d5b7b3ae RE |
19897 | if (val == 0) /* XXX */ |
19898 | return 0; | |
f676971a | 19899 | |
d5b7b3ae RE |
19900 | for (i = 0; i < 25; i++) |
19901 | if ((val & (mask << i)) == val) | |
19902 | return 1; | |
19903 | ||
19904 | return 0; | |
19905 | } | |
19906 | ||
825dda42 | 19907 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 19908 | or might contain a far jump. */ |
5848830f PB |
19909 | static int |
19910 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
19911 | { |
19912 | rtx insn; | |
19913 | ||
19914 | /* This test is only important for leaf functions. */ | |
5895f793 | 19915 | /* assert (!leaf_function_p ()); */ |
f676971a | 19916 | |
d5b7b3ae RE |
19917 | /* If we have already decided that far jumps may be used, |
19918 | do not bother checking again, and always return true even if | |
19919 | it turns out that they are not being used. Once we have made | |
19920 | the decision that far jumps are present (and that hence the link | |
19921 | register will be pushed onto the stack) we cannot go back on it. */ | |
19922 | if (cfun->machine->far_jump_used) | |
19923 | return 1; | |
19924 | ||
19925 | /* If this function is not being called from the prologue/epilogue | |
19926 | generation code then it must be being called from the | |
19927 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 19928 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
19929 | { |
19930 | /* In this case we know that we are being asked about the elimination | |
19931 | of the arg pointer register. If that register is not being used, | |
19932 | then there are no arguments on the stack, and we do not have to | |
19933 | worry that a far jump might force the prologue to push the link | |
19934 | register, changing the stack offsets. In this case we can just | |
19935 | return false, since the presence of far jumps in the function will | |
19936 | not affect stack offsets. | |
19937 | ||
19938 | If the arg pointer is live (or if it was live, but has now been | |
19939 | eliminated and so set to dead) then we do have to test to see if | |
19940 | the function might contain a far jump. This test can lead to some | |
19941 | false negatives, since before reload is completed, then length of | |
19942 | branch instructions is not known, so gcc defaults to returning their | |
19943 | longest length, which in turn sets the far jump attribute to true. | |
19944 | ||
19945 | A false negative will not result in bad code being generated, but it | |
19946 | will result in a needless push and pop of the link register. We | |
5848830f PB |
19947 | hope that this does not occur too often. |
19948 | ||
19949 | If we need doubleword stack alignment this could affect the other | |
19950 | elimination offsets so we can't risk getting it wrong. */ | |
6fb5fa3c | 19951 | if (df_regs_ever_live_p (ARG_POINTER_REGNUM)) |
d5b7b3ae | 19952 | cfun->machine->arg_pointer_live = 1; |
5895f793 | 19953 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
19954 | return 0; |
19955 | } | |
19956 | ||
19957 | /* Check to see if the function contains a branch | |
19958 | insn with the far jump attribute set. */ | |
19959 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
19960 | { | |
19961 | if (GET_CODE (insn) == JUMP_INSN | |
19962 | /* Ignore tablejump patterns. */ | |
19963 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
19964 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
19965 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
19966 | ) | |
19967 | { | |
9a9f7594 | 19968 | /* Record the fact that we have decided that |
d5b7b3ae RE |
19969 | the function does use far jumps. */ |
19970 | cfun->machine->far_jump_used = 1; | |
19971 | return 1; | |
19972 | } | |
19973 | } | |
f676971a | 19974 | |
d5b7b3ae RE |
19975 | return 0; |
19976 | } | |
19977 | ||
825dda42 | 19978 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 19979 | int |
e32bac5b | 19980 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 19981 | { |
e6d29d15 | 19982 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 19983 | |
696e78bf | 19984 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
19985 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
19986 | return TRUE; | |
19987 | ||
f676971a | 19988 | #ifdef ARM_PE |
91d231cb | 19989 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
19990 | #else |
19991 | return FALSE; | |
19992 | #endif | |
19993 | } | |
19994 | ||
e784c52c BS |
19995 | /* Given the stack offsets and register mask in OFFSETS, decide how |
19996 | many additional registers to push instead of subtracting a constant | |
19997 | from SP. For epilogues the principle is the same except we use pop. | |
19998 | FOR_PROLOGUE indicates which we're generating. */ | |
19999 | static int | |
20000 | thumb1_extra_regs_pushed (arm_stack_offsets *offsets, bool for_prologue) | |
20001 | { | |
20002 | HOST_WIDE_INT amount; | |
20003 | unsigned long live_regs_mask = offsets->saved_regs_mask; | |
20004 | /* Extract a mask of the ones we can give to the Thumb's push/pop | |
20005 | instruction. */ | |
20006 | unsigned long l_mask = live_regs_mask & (for_prologue ? 0x40ff : 0xff); | |
20007 | /* Then count how many other high registers will need to be pushed. */ | |
20008 | unsigned long high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
20009 | int n_free, reg_base; | |
20010 | ||
20011 | if (!for_prologue && frame_pointer_needed) | |
20012 | amount = offsets->locals_base - offsets->saved_regs; | |
20013 | else | |
20014 | amount = offsets->outgoing_args - offsets->saved_regs; | |
20015 | ||
20016 | /* If the stack frame size is 512 exactly, we can save one load | |
20017 | instruction, which should make this a win even when optimizing | |
20018 | for speed. */ | |
20019 | if (!optimize_size && amount != 512) | |
20020 | return 0; | |
20021 | ||
20022 | /* Can't do this if there are high registers to push. */ | |
20023 | if (high_regs_pushed != 0) | |
20024 | return 0; | |
20025 | ||
20026 | /* Shouldn't do it in the prologue if no registers would normally | |
20027 | be pushed at all. In the epilogue, also allow it if we'll have | |
20028 | a pop insn for the PC. */ | |
20029 | if (l_mask == 0 | |
20030 | && (for_prologue | |
20031 | || TARGET_BACKTRACE | |
20032 | || (live_regs_mask & 1 << LR_REGNUM) == 0 | |
20033 | || TARGET_INTERWORK | |
20034 | || crtl->args.pretend_args_size != 0)) | |
20035 | return 0; | |
20036 | ||
20037 | /* Don't do this if thumb_expand_prologue wants to emit instructions | |
20038 | between the push and the stack frame allocation. */ | |
20039 | if (for_prologue | |
20040 | && ((flag_pic && arm_pic_register != INVALID_REGNUM) | |
20041 | || (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0))) | |
20042 | return 0; | |
20043 | ||
20044 | reg_base = 0; | |
20045 | n_free = 0; | |
20046 | if (!for_prologue) | |
20047 | { | |
20048 | reg_base = arm_size_return_regs () / UNITS_PER_WORD; | |
20049 | live_regs_mask >>= reg_base; | |
20050 | } | |
20051 | ||
20052 | while (reg_base + n_free < 8 && !(live_regs_mask & 1) | |
20053 | && (for_prologue || call_used_regs[reg_base + n_free])) | |
20054 | { | |
20055 | live_regs_mask >>= 1; | |
20056 | n_free++; | |
20057 | } | |
20058 | ||
20059 | if (n_free == 0) | |
20060 | return 0; | |
20061 | gcc_assert (amount / 4 * 4 == amount); | |
20062 | ||
20063 | if (amount >= 512 && (amount - n_free * 4) < 512) | |
20064 | return (amount - 508) / 4; | |
20065 | if (amount <= n_free * 4) | |
20066 | return amount / 4; | |
20067 | return 0; | |
20068 | } | |
20069 | ||
d6b4baa4 | 20070 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 20071 | const char * |
e32bac5b | 20072 | thumb_unexpanded_epilogue (void) |
d5b7b3ae | 20073 | { |
954954d1 | 20074 | arm_stack_offsets *offsets; |
d5b7b3ae | 20075 | int regno; |
b279b20a | 20076 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 20077 | int high_regs_pushed = 0; |
e784c52c | 20078 | int extra_pop; |
d5b7b3ae | 20079 | int had_to_push_lr; |
57934c39 | 20080 | int size; |
d5b7b3ae | 20081 | |
934c2060 | 20082 | if (cfun->machine->return_used_this_function != 0) |
d5b7b3ae RE |
20083 | return ""; |
20084 | ||
58e60158 AN |
20085 | if (IS_NAKED (arm_current_func_type ())) |
20086 | return ""; | |
20087 | ||
954954d1 PB |
20088 | offsets = arm_get_frame_offsets (); |
20089 | live_regs_mask = offsets->saved_regs_mask; | |
57934c39 PB |
20090 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); |
20091 | ||
20092 | /* If we can deduce the registers used from the function's return value. | |
6fb5fa3c | 20093 | This is more reliable that examining df_regs_ever_live_p () because that |
57934c39 PB |
20094 | will be set if the register is ever used in the function, not just if |
20095 | the register is used to hold a return value. */ | |
4f5dfed0 | 20096 | size = arm_size_return_regs (); |
d5b7b3ae | 20097 | |
e784c52c BS |
20098 | extra_pop = thumb1_extra_regs_pushed (offsets, false); |
20099 | if (extra_pop > 0) | |
20100 | { | |
20101 | unsigned long extra_mask = (1 << extra_pop) - 1; | |
20102 | live_regs_mask |= extra_mask << (size / UNITS_PER_WORD); | |
20103 | } | |
20104 | ||
d5b7b3ae | 20105 | /* The prolog may have pushed some high registers to use as |
112cdef5 | 20106 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
20107 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
20108 | compiles to produce: | |
20109 | push {r4, r5, r6, r7, lr} | |
20110 | mov r7, r9 | |
20111 | mov r6, r8 | |
20112 | push {r6, r7} | |
20113 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 20114 | |
d5b7b3ae RE |
20115 | if (high_regs_pushed) |
20116 | { | |
b279b20a | 20117 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 20118 | int next_hi_reg; |
d5b7b3ae | 20119 | |
57934c39 PB |
20120 | /* The available low registers depend on the size of the value we are |
20121 | returning. */ | |
20122 | if (size <= 12) | |
d5b7b3ae | 20123 | mask |= 1 << 3; |
57934c39 PB |
20124 | if (size <= 8) |
20125 | mask |= 1 << 2; | |
d5b7b3ae RE |
20126 | |
20127 | if (mask == 0) | |
20128 | /* Oh dear! We have no low registers into which we can pop | |
20129 | high registers! */ | |
400500c4 RK |
20130 | internal_error |
20131 | ("no low registers available for popping high registers"); | |
f676971a | 20132 | |
d5b7b3ae | 20133 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 20134 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
20135 | break; |
20136 | ||
20137 | while (high_regs_pushed) | |
20138 | { | |
20139 | /* Find lo register(s) into which the high register(s) can | |
20140 | be popped. */ | |
20141 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
20142 | { | |
20143 | if (mask & (1 << regno)) | |
20144 | high_regs_pushed--; | |
20145 | if (high_regs_pushed == 0) | |
20146 | break; | |
20147 | } | |
20148 | ||
20149 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
20150 | ||
d6b4baa4 | 20151 | /* Pop the values into the low register(s). */ |
980e61bb | 20152 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
20153 | |
20154 | /* Move the value(s) into the high registers. */ | |
20155 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
20156 | { | |
20157 | if (mask & (1 << regno)) | |
20158 | { | |
20159 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
20160 | regno); | |
f676971a | 20161 | |
d5b7b3ae | 20162 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 20163 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
20164 | break; |
20165 | } | |
20166 | } | |
20167 | } | |
57934c39 | 20168 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
20169 | } |
20170 | ||
57934c39 PB |
20171 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
20172 | live_regs_mask &= 0xff; | |
20173 | ||
38173d38 | 20174 | if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE) |
d5b7b3ae | 20175 | { |
f676971a | 20176 | /* Pop the return address into the PC. */ |
57934c39 | 20177 | if (had_to_push_lr) |
d5b7b3ae RE |
20178 | live_regs_mask |= 1 << PC_REGNUM; |
20179 | ||
20180 | /* Either no argument registers were pushed or a backtrace | |
20181 | structure was created which includes an adjusted stack | |
20182 | pointer, so just pop everything. */ | |
20183 | if (live_regs_mask) | |
980e61bb DJ |
20184 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
20185 | live_regs_mask); | |
57934c39 | 20186 | |
d5b7b3ae | 20187 | /* We have either just popped the return address into the |
e784c52c BS |
20188 | PC or it is was kept in LR for the entire function. |
20189 | Note that thumb_pushpop has already called thumb_exit if the | |
20190 | PC was in the list. */ | |
57934c39 PB |
20191 | if (!had_to_push_lr) |
20192 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
20193 | } |
20194 | else | |
20195 | { | |
20196 | /* Pop everything but the return address. */ | |
d5b7b3ae | 20197 | if (live_regs_mask) |
980e61bb DJ |
20198 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
20199 | live_regs_mask); | |
d5b7b3ae RE |
20200 | |
20201 | if (had_to_push_lr) | |
57934c39 PB |
20202 | { |
20203 | if (size > 12) | |
20204 | { | |
20205 | /* We have no free low regs, so save one. */ | |
20206 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
20207 | LAST_ARG_REGNUM); | |
20208 | } | |
20209 | ||
20210 | /* Get the return address into a temporary register. */ | |
20211 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
20212 | 1 << LAST_ARG_REGNUM); | |
20213 | ||
20214 | if (size > 12) | |
20215 | { | |
20216 | /* Move the return address to lr. */ | |
20217 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
20218 | LAST_ARG_REGNUM); | |
20219 | /* Restore the low register. */ | |
20220 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
20221 | IP_REGNUM); | |
20222 | regno = LR_REGNUM; | |
20223 | } | |
20224 | else | |
20225 | regno = LAST_ARG_REGNUM; | |
20226 | } | |
20227 | else | |
20228 | regno = LR_REGNUM; | |
f676971a | 20229 | |
d5b7b3ae RE |
20230 | /* Remove the argument registers that were pushed onto the stack. */ |
20231 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
20232 | SP_REGNUM, SP_REGNUM, | |
38173d38 | 20233 | crtl->args.pretend_args_size); |
f676971a | 20234 | |
57934c39 | 20235 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
20236 | } |
20237 | ||
20238 | return ""; | |
20239 | } | |
20240 | ||
20241 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 20242 | static struct machine_function * |
e32bac5b | 20243 | arm_init_machine_status (void) |
d5b7b3ae | 20244 | { |
e2500fed | 20245 | struct machine_function *machine; |
a9429e29 | 20246 | machine = ggc_alloc_cleared_machine_function (); |
6d3d9133 | 20247 | |
f676971a | 20248 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 20249 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 20250 | #endif |
e2500fed | 20251 | return machine; |
f7a80099 NC |
20252 | } |
20253 | ||
d5b7b3ae RE |
20254 | /* Return an RTX indicating where the return address to the |
20255 | calling function can be found. */ | |
20256 | rtx | |
e32bac5b | 20257 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 20258 | { |
d5b7b3ae RE |
20259 | if (count != 0) |
20260 | return NULL_RTX; | |
20261 | ||
61f0ccff | 20262 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
20263 | } |
20264 | ||
20265 | /* Do anything needed before RTL is emitted for each function. */ | |
20266 | void | |
e32bac5b | 20267 | arm_init_expanders (void) |
d5b7b3ae RE |
20268 | { |
20269 | /* Arrange to initialize and mark the machine per-function status. */ | |
20270 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
20271 | |
20272 | /* This is to stop the combine pass optimizing away the alignment | |
20273 | adjustment of va_arg. */ | |
20274 | /* ??? It is claimed that this should not be necessary. */ | |
20275 | if (cfun) | |
20276 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
20277 | } |
20278 | ||
0977774b | 20279 | |
2591db65 RE |
20280 | /* Like arm_compute_initial_elimination offset. Simpler because there |
20281 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
20282 | to point at the base of the local variables after static stack | |
20283 | space for a function has been allocated. */ | |
0977774b | 20284 | |
5848830f PB |
20285 | HOST_WIDE_INT |
20286 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
20287 | { | |
20288 | arm_stack_offsets *offsets; | |
0977774b | 20289 | |
5848830f | 20290 | offsets = arm_get_frame_offsets (); |
0977774b | 20291 | |
5848830f | 20292 | switch (from) |
0977774b | 20293 | { |
5848830f PB |
20294 | case ARG_POINTER_REGNUM: |
20295 | switch (to) | |
20296 | { | |
20297 | case STACK_POINTER_REGNUM: | |
20298 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 20299 | |
5848830f PB |
20300 | case FRAME_POINTER_REGNUM: |
20301 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 20302 | |
5848830f PB |
20303 | case ARM_HARD_FRAME_POINTER_REGNUM: |
20304 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 20305 | |
2591db65 RE |
20306 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
20307 | return offsets->locals_base - offsets->saved_args; | |
20308 | ||
5848830f | 20309 | default: |
e6d29d15 | 20310 | gcc_unreachable (); |
5848830f PB |
20311 | } |
20312 | break; | |
0977774b | 20313 | |
5848830f PB |
20314 | case FRAME_POINTER_REGNUM: |
20315 | switch (to) | |
20316 | { | |
20317 | case STACK_POINTER_REGNUM: | |
20318 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 20319 | |
5848830f PB |
20320 | case ARM_HARD_FRAME_POINTER_REGNUM: |
20321 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 20322 | |
2591db65 RE |
20323 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
20324 | return offsets->locals_base - offsets->soft_frame; | |
20325 | ||
5848830f | 20326 | default: |
e6d29d15 | 20327 | gcc_unreachable (); |
5848830f PB |
20328 | } |
20329 | break; | |
0977774b | 20330 | |
5848830f | 20331 | default: |
e6d29d15 | 20332 | gcc_unreachable (); |
5848830f | 20333 | } |
0977774b JT |
20334 | } |
20335 | ||
d5b7b3ae RE |
20336 | /* Generate the rest of a function's prologue. */ |
20337 | void | |
5b3e6663 | 20338 | thumb1_expand_prologue (void) |
d5b7b3ae | 20339 | { |
980e61bb DJ |
20340 | rtx insn, dwarf; |
20341 | ||
5848830f PB |
20342 | HOST_WIDE_INT amount; |
20343 | arm_stack_offsets *offsets; | |
6d3d9133 | 20344 | unsigned long func_type; |
3c7ad43e | 20345 | int regno; |
57934c39 | 20346 | unsigned long live_regs_mask; |
6d3d9133 NC |
20347 | |
20348 | func_type = arm_current_func_type (); | |
f676971a | 20349 | |
d5b7b3ae | 20350 | /* Naked functions don't have prologues. */ |
6d3d9133 | 20351 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
20352 | return; |
20353 | ||
6d3d9133 NC |
20354 | if (IS_INTERRUPT (func_type)) |
20355 | { | |
c725bd79 | 20356 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
20357 | return; |
20358 | } | |
20359 | ||
954954d1 PB |
20360 | offsets = arm_get_frame_offsets (); |
20361 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a NC |
20362 | /* Load the pic register before setting the frame pointer, |
20363 | so we can use r7 as a temporary work register. */ | |
020a4035 | 20364 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 20365 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 20366 | |
2591db65 | 20367 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
20368 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
20369 | stack_pointer_rtx); | |
d5b7b3ae | 20370 | |
5848830f | 20371 | amount = offsets->outgoing_args - offsets->saved_regs; |
e784c52c | 20372 | amount -= 4 * thumb1_extra_regs_pushed (offsets, true); |
d5b7b3ae RE |
20373 | if (amount) |
20374 | { | |
d5b7b3ae | 20375 | if (amount < 512) |
980e61bb DJ |
20376 | { |
20377 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
20378 | GEN_INT (- amount))); | |
20379 | RTX_FRAME_RELATED_P (insn) = 1; | |
20380 | } | |
d5b7b3ae RE |
20381 | else |
20382 | { | |
d5b7b3ae RE |
20383 | rtx reg; |
20384 | ||
20385 | /* The stack decrement is too big for an immediate value in a single | |
20386 | insn. In theory we could issue multiple subtracts, but after | |
20387 | three of them it becomes more space efficient to place the full | |
20388 | value in the constant pool and load into a register. (Also the | |
20389 | ARM debugger really likes to see only one stack decrement per | |
20390 | function). So instead we look for a scratch register into which | |
20391 | we can load the decrement, and then we subtract this from the | |
20392 | stack pointer. Unfortunately on the thumb the only available | |
20393 | scratch registers are the argument registers, and we cannot use | |
20394 | these as they may hold arguments to the function. Instead we | |
20395 | attempt to locate a call preserved register which is used by this | |
20396 | function. If we can find one, then we know that it will have | |
20397 | been pushed at the start of the prologue and so we can corrupt | |
20398 | it now. */ | |
20399 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
35596784 | 20400 | if (live_regs_mask & (1 << regno)) |
d5b7b3ae RE |
20401 | break; |
20402 | ||
35596784 | 20403 | gcc_assert(regno <= LAST_LO_REGNUM); |
d5b7b3ae | 20404 | |
35596784 | 20405 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 20406 | |
35596784 | 20407 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb | 20408 | |
35596784 AJ |
20409 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
20410 | stack_pointer_rtx, reg)); | |
20411 | RTX_FRAME_RELATED_P (insn) = 1; | |
20412 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
20413 | plus_constant (stack_pointer_rtx, | |
20414 | -amount)); | |
20415 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 20416 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
d5b7b3ae | 20417 | } |
2591db65 RE |
20418 | } |
20419 | ||
20420 | if (frame_pointer_needed) | |
5b3e6663 | 20421 | thumb_set_frame_pointer (offsets); |
f676971a | 20422 | |
74d9c39f DJ |
20423 | /* If we are profiling, make sure no instructions are scheduled before |
20424 | the call to mcount. Similarly if the user has requested no | |
20425 | scheduling in the prolog. Similarly if we want non-call exceptions | |
20426 | using the EABI unwinder, to prevent faulting instructions from being | |
20427 | swapped with a stack adjustment. */ | |
e3b5732b | 20428 | if (crtl->profile || !TARGET_SCHED_PROLOG |
8f4f502f | 20429 | || (ARM_EABI_UNWIND_TABLES && cfun->can_throw_non_call_exceptions)) |
d5b7b3ae | 20430 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
20431 | |
20432 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
20433 | if (live_regs_mask & 0xff) |
20434 | cfun->machine->lr_save_eliminated = 0; | |
d5b7b3ae RE |
20435 | } |
20436 | ||
57934c39 | 20437 | |
d5b7b3ae | 20438 | void |
5b3e6663 | 20439 | thumb1_expand_epilogue (void) |
d5b7b3ae | 20440 | { |
5848830f PB |
20441 | HOST_WIDE_INT amount; |
20442 | arm_stack_offsets *offsets; | |
defc0463 RE |
20443 | int regno; |
20444 | ||
6d3d9133 NC |
20445 | /* Naked functions don't have prologues. */ |
20446 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
20447 | return; |
20448 | ||
5848830f PB |
20449 | offsets = arm_get_frame_offsets (); |
20450 | amount = offsets->outgoing_args - offsets->saved_regs; | |
20451 | ||
d5b7b3ae | 20452 | if (frame_pointer_needed) |
2591db65 RE |
20453 | { |
20454 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
20455 | amount = offsets->locals_base - offsets->saved_regs; | |
20456 | } | |
e784c52c | 20457 | amount -= 4 * thumb1_extra_regs_pushed (offsets, false); |
e0b92319 | 20458 | |
a3a531ec | 20459 | gcc_assert (amount >= 0); |
2591db65 | 20460 | if (amount) |
d5b7b3ae | 20461 | { |
d5b7b3ae RE |
20462 | if (amount < 512) |
20463 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
20464 | GEN_INT (amount))); | |
20465 | else | |
20466 | { | |
20467 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 20468 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
20469 | |
20470 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
20471 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
20472 | } | |
20473 | } | |
f676971a | 20474 | |
d5b7b3ae RE |
20475 | /* Emit a USE (stack_pointer_rtx), so that |
20476 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 20477 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 20478 | |
e3b5732b | 20479 | if (crtl->profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 20480 | emit_insn (gen_blockage ()); |
defc0463 RE |
20481 | |
20482 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
20483 | so that flow2 will get register lifetimes correct. */ | |
20484 | for (regno = 0; regno < 13; regno++) | |
6fb5fa3c | 20485 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
c41c1387 | 20486 | emit_clobber (gen_rtx_REG (SImode, regno)); |
defc0463 | 20487 | |
6fb5fa3c | 20488 | if (! df_regs_ever_live_p (LR_REGNUM)) |
c41c1387 | 20489 | emit_use (gen_rtx_REG (SImode, LR_REGNUM)); |
d5b7b3ae RE |
20490 | } |
20491 | ||
08c148a8 | 20492 | static void |
5b3e6663 | 20493 | thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 20494 | { |
954954d1 | 20495 | arm_stack_offsets *offsets; |
b279b20a NC |
20496 | unsigned long live_regs_mask = 0; |
20497 | unsigned long l_mask; | |
20498 | unsigned high_regs_pushed = 0; | |
980e61bb | 20499 | int cfa_offset = 0; |
d5b7b3ae RE |
20500 | int regno; |
20501 | ||
6d3d9133 | 20502 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
20503 | return; |
20504 | ||
20505 | if (is_called_in_ARM_mode (current_function_decl)) | |
20506 | { | |
20507 | const char * name; | |
20508 | ||
e6d29d15 NS |
20509 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
20510 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
20511 | == SYMBOL_REF); | |
d5b7b3ae | 20512 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 20513 | |
d5b7b3ae RE |
20514 | /* Generate code sequence to switch us into Thumb mode. */ |
20515 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 20516 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
20517 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
20518 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
20519 | ||
20520 | /* Generate a label, so that the debugger will notice the | |
20521 | change in instruction sets. This label is also used by | |
20522 | the assembler to bypass the ARM code when this function | |
20523 | is called from a Thumb encoded function elsewhere in the | |
20524 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 20525 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 20526 | |
d5b7b3ae | 20527 | #define STUB_NAME ".real_start_of" |
f676971a | 20528 | |
761c70aa | 20529 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
20530 | #ifdef ARM_PE |
20531 | if (arm_dllexport_name_p (name)) | |
e5951263 | 20532 | name = arm_strip_name_encoding (name); |
f676971a | 20533 | #endif |
d5b7b3ae | 20534 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 20535 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
20536 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
20537 | } | |
f676971a | 20538 | |
38173d38 | 20539 | if (crtl->args.pretend_args_size) |
d5b7b3ae | 20540 | { |
617a1b71 PB |
20541 | /* Output unwind directive for the stack adjustment. */ |
20542 | if (ARM_EABI_UNWIND_TABLES) | |
20543 | fprintf (f, "\t.pad #%d\n", | |
38173d38 | 20544 | crtl->args.pretend_args_size); |
617a1b71 | 20545 | |
3cb66fd7 | 20546 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
20547 | { |
20548 | int num_pushes; | |
f676971a | 20549 | |
761c70aa | 20550 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 20551 | |
38173d38 | 20552 | num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size); |
f676971a | 20553 | |
d5b7b3ae RE |
20554 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
20555 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 20556 | regno++) |
d5b7b3ae RE |
20557 | asm_fprintf (f, "%r%s", regno, |
20558 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
20559 | ||
761c70aa | 20560 | fprintf (f, "}\n"); |
d5b7b3ae RE |
20561 | } |
20562 | else | |
f676971a | 20563 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae | 20564 | SP_REGNUM, SP_REGNUM, |
38173d38 | 20565 | crtl->args.pretend_args_size); |
980e61bb DJ |
20566 | |
20567 | /* We don't need to record the stores for unwinding (would it | |
20568 | help the debugger any if we did?), but record the change in | |
20569 | the stack pointer. */ | |
20570 | if (dwarf2out_do_frame ()) | |
20571 | { | |
d342c045 | 20572 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 20573 | |
38173d38 | 20574 | cfa_offset = cfa_offset + crtl->args.pretend_args_size; |
980e61bb DJ |
20575 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); |
20576 | } | |
d5b7b3ae RE |
20577 | } |
20578 | ||
b279b20a | 20579 | /* Get the registers we are going to push. */ |
954954d1 PB |
20580 | offsets = arm_get_frame_offsets (); |
20581 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a | 20582 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 20583 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
20584 | /* Then count how many other high registers will need to be pushed. */ |
20585 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
20586 | |
20587 | if (TARGET_BACKTRACE) | |
20588 | { | |
b279b20a NC |
20589 | unsigned offset; |
20590 | unsigned work_register; | |
f676971a | 20591 | |
d5b7b3ae RE |
20592 | /* We have been asked to create a stack backtrace structure. |
20593 | The code looks like this: | |
f676971a | 20594 | |
d5b7b3ae RE |
20595 | 0 .align 2 |
20596 | 0 func: | |
20597 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 20598 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
20599 | 4 add R7, SP, #20 Get the stack pointer before the push. |
20600 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
20601 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
20602 | 10 str R7, [SP, #16] Store it. | |
20603 | 12 mov R7, FP Get hold of the current frame pointer. | |
20604 | 14 str R7, [SP, #4] Store it. | |
20605 | 16 mov R7, LR Get hold of the current return address. | |
20606 | 18 str R7, [SP, #12] Store it. | |
20607 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
20608 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
20609 | ||
57934c39 | 20610 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 20611 | |
617a1b71 PB |
20612 | if (ARM_EABI_UNWIND_TABLES) |
20613 | asm_fprintf (f, "\t.pad #16\n"); | |
20614 | ||
d5b7b3ae RE |
20615 | asm_fprintf |
20616 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
20617 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
20618 | |
20619 | if (dwarf2out_do_frame ()) | |
20620 | { | |
d342c045 | 20621 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 20622 | |
980e61bb DJ |
20623 | cfa_offset = cfa_offset + 16; |
20624 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
20625 | } | |
20626 | ||
57934c39 PB |
20627 | if (l_mask) |
20628 | { | |
20629 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 20630 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
20631 | } |
20632 | else | |
20633 | offset = 0; | |
f676971a | 20634 | |
d5b7b3ae | 20635 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
38173d38 | 20636 | offset + 16 + crtl->args.pretend_args_size); |
f676971a | 20637 | |
d5b7b3ae RE |
20638 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
20639 | offset + 4); | |
20640 | ||
20641 | /* Make sure that the instruction fetching the PC is in the right place | |
20642 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 20643 | if (l_mask) |
d5b7b3ae RE |
20644 | { |
20645 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
20646 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
20647 | offset + 12); | |
20648 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
20649 | ARM_HARD_FRAME_POINTER_REGNUM); | |
20650 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
20651 | offset); | |
20652 | } | |
20653 | else | |
20654 | { | |
20655 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
20656 | ARM_HARD_FRAME_POINTER_REGNUM); | |
20657 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
20658 | offset); | |
20659 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
20660 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
20661 | offset + 12); | |
20662 | } | |
f676971a | 20663 | |
d5b7b3ae RE |
20664 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
20665 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
20666 | offset + 8); | |
20667 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
20668 | offset + 12); | |
20669 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
20670 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
20671 | } | |
0fa2e4df | 20672 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
20673 | to push some high registers then delay our first push. This will just |
20674 | be a push of LR and we can combine it with the push of the first high | |
20675 | register. */ | |
20676 | else if ((l_mask & 0xff) != 0 | |
20677 | || (high_regs_pushed == 0 && l_mask)) | |
cb751cbd BS |
20678 | { |
20679 | unsigned long mask = l_mask; | |
e784c52c | 20680 | mask |= (1 << thumb1_extra_regs_pushed (offsets, true)) - 1; |
cb751cbd BS |
20681 | thumb_pushpop (f, mask, 1, &cfa_offset, mask); |
20682 | } | |
d5b7b3ae | 20683 | |
d5b7b3ae RE |
20684 | if (high_regs_pushed) |
20685 | { | |
b279b20a NC |
20686 | unsigned pushable_regs; |
20687 | unsigned next_hi_reg; | |
d5b7b3ae RE |
20688 | |
20689 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 20690 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 20691 | break; |
d5b7b3ae | 20692 | |
57934c39 | 20693 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
20694 | |
20695 | if (pushable_regs == 0) | |
57934c39 | 20696 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
20697 | |
20698 | while (high_regs_pushed > 0) | |
20699 | { | |
b279b20a | 20700 | unsigned long real_regs_mask = 0; |
980e61bb | 20701 | |
b279b20a | 20702 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 20703 | { |
57934c39 | 20704 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
20705 | { |
20706 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 20707 | |
b279b20a | 20708 | high_regs_pushed --; |
980e61bb | 20709 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 20710 | |
d5b7b3ae | 20711 | if (high_regs_pushed) |
aeaf4d25 | 20712 | { |
b279b20a NC |
20713 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
20714 | next_hi_reg --) | |
57934c39 | 20715 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 20716 | break; |
aeaf4d25 | 20717 | } |
d5b7b3ae RE |
20718 | else |
20719 | { | |
57934c39 | 20720 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
20721 | break; |
20722 | } | |
20723 | } | |
20724 | } | |
980e61bb | 20725 | |
b279b20a NC |
20726 | /* If we had to find a work register and we have not yet |
20727 | saved the LR then add it to the list of regs to push. */ | |
20728 | if (l_mask == (1 << LR_REGNUM)) | |
20729 | { | |
20730 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
20731 | 1, &cfa_offset, | |
20732 | real_regs_mask | (1 << LR_REGNUM)); | |
20733 | l_mask = 0; | |
20734 | } | |
20735 | else | |
20736 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 20737 | } |
d5b7b3ae RE |
20738 | } |
20739 | } | |
20740 | ||
20741 | /* Handle the case of a double word load into a low register from | |
20742 | a computed memory address. The computed address may involve a | |
20743 | register which is overwritten by the load. */ | |
cd2b33d0 | 20744 | const char * |
e32bac5b | 20745 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
20746 | { |
20747 | rtx addr; | |
20748 | rtx base; | |
20749 | rtx offset; | |
20750 | rtx arg1; | |
20751 | rtx arg2; | |
f676971a | 20752 | |
e6d29d15 NS |
20753 | gcc_assert (GET_CODE (operands[0]) == REG); |
20754 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
20755 | |
20756 | /* Get the memory address. */ | |
20757 | addr = XEXP (operands[1], 0); | |
f676971a | 20758 | |
d5b7b3ae RE |
20759 | /* Work out how the memory address is computed. */ |
20760 | switch (GET_CODE (addr)) | |
20761 | { | |
20762 | case REG: | |
31fa16b6 | 20763 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 20764 | |
d5b7b3ae RE |
20765 | if (REGNO (operands[0]) == REGNO (addr)) |
20766 | { | |
20767 | output_asm_insn ("ldr\t%H0, %2", operands); | |
20768 | output_asm_insn ("ldr\t%0, %1", operands); | |
20769 | } | |
20770 | else | |
20771 | { | |
20772 | output_asm_insn ("ldr\t%0, %1", operands); | |
20773 | output_asm_insn ("ldr\t%H0, %2", operands); | |
20774 | } | |
20775 | break; | |
f676971a | 20776 | |
d5b7b3ae RE |
20777 | case CONST: |
20778 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 20779 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 20780 | |
d5b7b3ae RE |
20781 | output_asm_insn ("ldr\t%0, %1", operands); |
20782 | output_asm_insn ("ldr\t%H0, %2", operands); | |
20783 | break; | |
f676971a | 20784 | |
d5b7b3ae RE |
20785 | case PLUS: |
20786 | arg1 = XEXP (addr, 0); | |
20787 | arg2 = XEXP (addr, 1); | |
f676971a | 20788 | |
d5b7b3ae RE |
20789 | if (CONSTANT_P (arg1)) |
20790 | base = arg2, offset = arg1; | |
20791 | else | |
20792 | base = arg1, offset = arg2; | |
f676971a | 20793 | |
e6d29d15 | 20794 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
20795 | |
20796 | /* Catch the case of <address> = <reg> + <reg> */ | |
20797 | if (GET_CODE (offset) == REG) | |
20798 | { | |
20799 | int reg_offset = REGNO (offset); | |
20800 | int reg_base = REGNO (base); | |
20801 | int reg_dest = REGNO (operands[0]); | |
f676971a | 20802 | |
d5b7b3ae RE |
20803 | /* Add the base and offset registers together into the |
20804 | higher destination register. */ | |
20805 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
20806 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 20807 | |
d5b7b3ae RE |
20808 | /* Load the lower destination register from the address in |
20809 | the higher destination register. */ | |
20810 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
20811 | reg_dest, reg_dest + 1); | |
f676971a | 20812 | |
d5b7b3ae RE |
20813 | /* Load the higher destination register from its own address |
20814 | plus 4. */ | |
20815 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
20816 | reg_dest + 1, reg_dest + 1); | |
20817 | } | |
20818 | else | |
20819 | { | |
20820 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 20821 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 20822 | |
d5b7b3ae RE |
20823 | /* If the computed address is held in the low order register |
20824 | then load the high order register first, otherwise always | |
20825 | load the low order register first. */ | |
20826 | if (REGNO (operands[0]) == REGNO (base)) | |
20827 | { | |
20828 | output_asm_insn ("ldr\t%H0, %2", operands); | |
20829 | output_asm_insn ("ldr\t%0, %1", operands); | |
20830 | } | |
20831 | else | |
20832 | { | |
20833 | output_asm_insn ("ldr\t%0, %1", operands); | |
20834 | output_asm_insn ("ldr\t%H0, %2", operands); | |
20835 | } | |
20836 | } | |
20837 | break; | |
20838 | ||
20839 | case LABEL_REF: | |
20840 | /* With no registers to worry about we can just load the value | |
20841 | directly. */ | |
31fa16b6 | 20842 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 20843 | |
d5b7b3ae RE |
20844 | output_asm_insn ("ldr\t%H0, %2", operands); |
20845 | output_asm_insn ("ldr\t%0, %1", operands); | |
20846 | break; | |
f676971a | 20847 | |
d5b7b3ae | 20848 | default: |
e6d29d15 | 20849 | gcc_unreachable (); |
d5b7b3ae | 20850 | } |
f676971a | 20851 | |
d5b7b3ae RE |
20852 | return ""; |
20853 | } | |
20854 | ||
cd2b33d0 | 20855 | const char * |
e32bac5b | 20856 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
20857 | { |
20858 | rtx tmp; | |
20859 | ||
20860 | switch (n) | |
20861 | { | |
20862 | case 2: | |
ca356f3a | 20863 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 20864 | { |
ca356f3a RE |
20865 | tmp = operands[4]; |
20866 | operands[4] = operands[5]; | |
20867 | operands[5] = tmp; | |
d5b7b3ae | 20868 | } |
ca356f3a RE |
20869 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
20870 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
20871 | break; |
20872 | ||
20873 | case 3: | |
ca356f3a | 20874 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 20875 | { |
ca356f3a RE |
20876 | tmp = operands[4]; |
20877 | operands[4] = operands[5]; | |
20878 | operands[5] = tmp; | |
d5b7b3ae | 20879 | } |
ca356f3a | 20880 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 20881 | { |
ca356f3a RE |
20882 | tmp = operands[5]; |
20883 | operands[5] = operands[6]; | |
20884 | operands[6] = tmp; | |
d5b7b3ae | 20885 | } |
ca356f3a | 20886 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 20887 | { |
ca356f3a RE |
20888 | tmp = operands[4]; |
20889 | operands[4] = operands[5]; | |
20890 | operands[5] = tmp; | |
d5b7b3ae | 20891 | } |
f676971a | 20892 | |
ca356f3a RE |
20893 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
20894 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
20895 | break; |
20896 | ||
20897 | default: | |
e6d29d15 | 20898 | gcc_unreachable (); |
d5b7b3ae RE |
20899 | } |
20900 | ||
20901 | return ""; | |
20902 | } | |
20903 | ||
b12a00f1 RE |
20904 | /* Output a call-via instruction for thumb state. */ |
20905 | const char * | |
20906 | thumb_call_via_reg (rtx reg) | |
20907 | { | |
20908 | int regno = REGNO (reg); | |
20909 | rtx *labelp; | |
20910 | ||
57ecec57 | 20911 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
20912 | |
20913 | /* If we are in the normal text section we can use a single instance | |
20914 | per compilation unit. If we are doing function sections, then we need | |
20915 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 20916 | if (in_section == text_section) |
b12a00f1 RE |
20917 | { |
20918 | thumb_call_reg_needed = 1; | |
20919 | ||
20920 | if (thumb_call_via_label[regno] == NULL) | |
20921 | thumb_call_via_label[regno] = gen_label_rtx (); | |
20922 | labelp = thumb_call_via_label + regno; | |
20923 | } | |
20924 | else | |
20925 | { | |
20926 | if (cfun->machine->call_via[regno] == NULL) | |
20927 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
20928 | labelp = cfun->machine->call_via + regno; | |
20929 | } | |
20930 | ||
20931 | output_asm_insn ("bl\t%a0", labelp); | |
20932 | return ""; | |
20933 | } | |
20934 | ||
1d6e90ac | 20935 | /* Routines for generating rtl. */ |
d5b7b3ae | 20936 | void |
70128ad9 | 20937 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
20938 | { |
20939 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
20940 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
20941 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
20942 | HOST_WIDE_INT offset = 0; | |
20943 | ||
20944 | while (len >= 12) | |
20945 | { | |
ca356f3a | 20946 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
20947 | len -= 12; |
20948 | } | |
f676971a | 20949 | |
d5b7b3ae RE |
20950 | if (len >= 8) |
20951 | { | |
ca356f3a | 20952 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
20953 | len -= 8; |
20954 | } | |
f676971a | 20955 | |
d5b7b3ae RE |
20956 | if (len >= 4) |
20957 | { | |
20958 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
20959 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
20960 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
20961 | len -= 4; |
20962 | offset += 4; | |
20963 | } | |
f676971a | 20964 | |
d5b7b3ae RE |
20965 | if (len >= 2) |
20966 | { | |
20967 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 20968 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
20969 | plus_constant (in, offset)))); |
20970 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
20971 | reg)); |
20972 | len -= 2; | |
20973 | offset += 2; | |
20974 | } | |
f676971a | 20975 | |
d5b7b3ae RE |
20976 | if (len) |
20977 | { | |
20978 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
20979 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
20980 | plus_constant (in, offset)))); | |
20981 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
20982 | reg)); |
20983 | } | |
20984 | } | |
20985 | ||
d5b7b3ae | 20986 | void |
e32bac5b | 20987 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
20988 | { |
20989 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
20990 | } | |
20991 | ||
f676971a | 20992 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 20993 | void |
e32bac5b | 20994 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 20995 | { |
e6d29d15 | 20996 | gcc_unreachable (); |
d5b7b3ae RE |
20997 | } |
20998 | ||
c27ba912 DM |
20999 | /* Return the length of a function name prefix |
21000 | that starts with the character 'c'. */ | |
21001 | static int | |
e32bac5b | 21002 | arm_get_strip_length (int c) |
c27ba912 DM |
21003 | { |
21004 | switch (c) | |
21005 | { | |
21006 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 21007 | default: return 0; |
c27ba912 DM |
21008 | } |
21009 | } | |
21010 | ||
21011 | /* Return a pointer to a function's name with any | |
21012 | and all prefix encodings stripped from it. */ | |
21013 | const char * | |
e32bac5b | 21014 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
21015 | { |
21016 | int skip; | |
f676971a | 21017 | |
c27ba912 DM |
21018 | while ((skip = arm_get_strip_length (* name))) |
21019 | name += skip; | |
21020 | ||
21021 | return name; | |
21022 | } | |
21023 | ||
e1944073 KW |
21024 | /* If there is a '*' anywhere in the name's prefix, then |
21025 | emit the stripped name verbatim, otherwise prepend an | |
21026 | underscore if leading underscores are being used. */ | |
e1944073 | 21027 | void |
e32bac5b | 21028 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
21029 | { |
21030 | int skip; | |
21031 | int verbatim = 0; | |
21032 | ||
21033 | while ((skip = arm_get_strip_length (* name))) | |
21034 | { | |
21035 | verbatim |= (*name == '*'); | |
21036 | name += skip; | |
21037 | } | |
21038 | ||
21039 | if (verbatim) | |
21040 | fputs (name, stream); | |
21041 | else | |
21042 | asm_fprintf (stream, "%U%s", name); | |
21043 | } | |
21044 | ||
6c6aa1af PB |
21045 | static void |
21046 | arm_file_start (void) | |
21047 | { | |
21048 | int val; | |
21049 | ||
5b3e6663 PB |
21050 | if (TARGET_UNIFIED_ASM) |
21051 | asm_fprintf (asm_out_file, "\t.syntax unified\n"); | |
21052 | ||
6c6aa1af PB |
21053 | if (TARGET_BPABI) |
21054 | { | |
21055 | const char *fpu_name; | |
12a0a4d4 PB |
21056 | if (arm_selected_arch) |
21057 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); | |
6c6aa1af | 21058 | else |
12a0a4d4 | 21059 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); |
6c6aa1af PB |
21060 | |
21061 | if (TARGET_SOFT_FLOAT) | |
21062 | { | |
21063 | if (TARGET_VFP) | |
21064 | fpu_name = "softvfp"; | |
21065 | else | |
21066 | fpu_name = "softfpa"; | |
21067 | } | |
21068 | else | |
21069 | { | |
d79f3032 PB |
21070 | fpu_name = arm_fpu_desc->name; |
21071 | if (arm_fpu_desc->model == ARM_FP_MODEL_VFP) | |
f1adb0a9 JB |
21072 | { |
21073 | if (TARGET_HARD_FLOAT) | |
21074 | asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); | |
21075 | if (TARGET_HARD_FLOAT_ABI) | |
21076 | asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n"); | |
21077 | } | |
6c6aa1af PB |
21078 | } |
21079 | asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name); | |
21080 | ||
21081 | /* Some of these attributes only apply when the corresponding features | |
21082 | are used. However we don't have any easy way of figuring this out. | |
21083 | Conservatively record the setting that would have been used. */ | |
21084 | ||
6c6aa1af PB |
21085 | /* Tag_ABI_FP_rounding. */ |
21086 | if (flag_rounding_math) | |
21087 | asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n"); | |
21088 | if (!flag_unsafe_math_optimizations) | |
21089 | { | |
21090 | /* Tag_ABI_FP_denomal. */ | |
21091 | asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n"); | |
21092 | /* Tag_ABI_FP_exceptions. */ | |
21093 | asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n"); | |
21094 | } | |
21095 | /* Tag_ABI_FP_user_exceptions. */ | |
21096 | if (flag_signaling_nans) | |
21097 | asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); | |
21098 | /* Tag_ABI_FP_number_model. */ | |
21099 | asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", | |
21100 | flag_finite_math_only ? 1 : 3); | |
21101 | ||
21102 | /* Tag_ABI_align8_needed. */ | |
21103 | asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n"); | |
21104 | /* Tag_ABI_align8_preserved. */ | |
21105 | asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n"); | |
21106 | /* Tag_ABI_enum_size. */ | |
21107 | asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n", | |
21108 | flag_short_enums ? 1 : 2); | |
21109 | ||
21110 | /* Tag_ABI_optimization_goals. */ | |
21111 | if (optimize_size) | |
21112 | val = 4; | |
21113 | else if (optimize >= 2) | |
21114 | val = 2; | |
21115 | else if (optimize) | |
21116 | val = 1; | |
21117 | else | |
21118 | val = 6; | |
21119 | asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); | |
b76c3c4b | 21120 | |
0fd8c3ad SL |
21121 | /* Tag_ABI_FP_16bit_format. */ |
21122 | if (arm_fp16_format) | |
21123 | asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n", | |
21124 | (int)arm_fp16_format); | |
21125 | ||
b76c3c4b PB |
21126 | if (arm_lang_output_object_attributes_hook) |
21127 | arm_lang_output_object_attributes_hook(); | |
6c6aa1af PB |
21128 | } |
21129 | default_file_start(); | |
21130 | } | |
21131 | ||
b12a00f1 RE |
21132 | static void |
21133 | arm_file_end (void) | |
21134 | { | |
21135 | int regno; | |
21136 | ||
978e411f CD |
21137 | if (NEED_INDICATE_EXEC_STACK) |
21138 | /* Add .note.GNU-stack. */ | |
21139 | file_end_indicate_exec_stack (); | |
21140 | ||
b12a00f1 RE |
21141 | if (! thumb_call_reg_needed) |
21142 | return; | |
21143 | ||
d6b5193b | 21144 | switch_to_section (text_section); |
b12a00f1 RE |
21145 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
21146 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
21147 | ||
57ecec57 | 21148 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
21149 | { |
21150 | rtx label = thumb_call_via_label[regno]; | |
21151 | ||
21152 | if (label != 0) | |
21153 | { | |
21154 | targetm.asm_out.internal_label (asm_out_file, "L", | |
21155 | CODE_LABEL_NUMBER (label)); | |
21156 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
21157 | } | |
21158 | } | |
21159 | } | |
21160 | ||
fb49053f RH |
21161 | #ifndef ARM_PE |
21162 | /* Symbols in the text segment can be accessed without indirecting via the | |
21163 | constant pool; it may take an extra binary operation, but this is still | |
21164 | faster than indirecting via memory. Don't do this when not optimizing, | |
21165 | since we won't be calculating al of the offsets necessary to do this | |
21166 | simplification. */ | |
21167 | ||
21168 | static void | |
e32bac5b | 21169 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 21170 | { |
3521b33c | 21171 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 21172 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f | 21173 | |
d3585b76 | 21174 | default_encode_section_info (decl, rtl, first); |
fb49053f RH |
21175 | } |
21176 | #endif /* !ARM_PE */ | |
483ab821 | 21177 | |
4977bab6 | 21178 | static void |
e32bac5b | 21179 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
21180 | { |
21181 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
21182 | && !strcmp (prefix, "L")) | |
21183 | { | |
21184 | arm_ccfsm_state = 0; | |
21185 | arm_target_insn = NULL; | |
21186 | } | |
21187 | default_internal_label (stream, prefix, labelno); | |
21188 | } | |
21189 | ||
c590b625 RH |
21190 | /* Output code to add DELTA to the first argument, and then jump |
21191 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 21192 | static void |
e32bac5b RE |
21193 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
21194 | HOST_WIDE_INT delta, | |
21195 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
21196 | tree function) | |
483ab821 | 21197 | { |
9b66ebb1 PB |
21198 | static int thunk_label = 0; |
21199 | char label[256]; | |
54b9e939 | 21200 | char labelpc[256]; |
483ab821 MM |
21201 | int mi_delta = delta; |
21202 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
21203 | int shift = 0; | |
61f71b34 | 21204 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
21205 | ? 1 : 0); |
21206 | if (mi_delta < 0) | |
21207 | mi_delta = - mi_delta; | |
bf98ec6c | 21208 | |
5b3e6663 | 21209 | if (TARGET_THUMB1) |
9b66ebb1 PB |
21210 | { |
21211 | int labelno = thunk_label++; | |
21212 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
bf98ec6c PB |
21213 | /* Thunks are entered in arm mode when avaiable. */ |
21214 | if (TARGET_THUMB1_ONLY) | |
21215 | { | |
21216 | /* push r3 so we can use it as a temporary. */ | |
21217 | /* TODO: Omit this save if r3 is not used. */ | |
21218 | fputs ("\tpush {r3}\n", file); | |
21219 | fputs ("\tldr\tr3, ", file); | |
21220 | } | |
21221 | else | |
21222 | { | |
21223 | fputs ("\tldr\tr12, ", file); | |
21224 | } | |
9b66ebb1 PB |
21225 | assemble_name (file, label); |
21226 | fputc ('\n', file); | |
54b9e939 KH |
21227 | if (flag_pic) |
21228 | { | |
21229 | /* If we are generating PIC, the ldr instruction below loads | |
21230 | "(target - 7) - .LTHUNKPCn" into r12. The pc reads as | |
21231 | the address of the add + 8, so we have: | |
21232 | ||
21233 | r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) | |
21234 | = target + 1. | |
21235 | ||
21236 | Note that we have "+ 1" because some versions of GNU ld | |
21237 | don't set the low bit of the result for R_ARM_REL32 | |
bf98ec6c PB |
21238 | relocations against thumb function symbols. |
21239 | On ARMv6M this is +4, not +8. */ | |
54b9e939 KH |
21240 | ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); |
21241 | assemble_name (file, labelpc); | |
21242 | fputs (":\n", file); | |
bf98ec6c PB |
21243 | if (TARGET_THUMB1_ONLY) |
21244 | { | |
21245 | /* This is 2 insns after the start of the thunk, so we know it | |
21246 | is 4-byte aligned. */ | |
21247 | fputs ("\tadd\tr3, pc, r3\n", file); | |
21248 | fputs ("\tmov r12, r3\n", file); | |
21249 | } | |
21250 | else | |
21251 | fputs ("\tadd\tr12, pc, r12\n", file); | |
54b9e939 | 21252 | } |
bf98ec6c PB |
21253 | else if (TARGET_THUMB1_ONLY) |
21254 | fputs ("\tmov r12, r3\n", file); | |
9b66ebb1 | 21255 | } |
bf98ec6c | 21256 | if (TARGET_THUMB1_ONLY) |
483ab821 | 21257 | { |
bf98ec6c PB |
21258 | if (mi_delta > 255) |
21259 | { | |
21260 | fputs ("\tldr\tr3, ", file); | |
21261 | assemble_name (file, label); | |
21262 | fputs ("+4\n", file); | |
21263 | asm_fprintf (file, "\t%s\t%r, %r, r3\n", | |
21264 | mi_op, this_regno, this_regno); | |
21265 | } | |
21266 | else if (mi_delta != 0) | |
21267 | { | |
21268 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
21269 | mi_op, this_regno, this_regno, | |
21270 | mi_delta); | |
21271 | } | |
21272 | } | |
21273 | else | |
21274 | { | |
21275 | /* TODO: Use movw/movt for large constants when available. */ | |
21276 | while (mi_delta != 0) | |
21277 | { | |
21278 | if ((mi_delta & (3 << shift)) == 0) | |
21279 | shift += 2; | |
21280 | else | |
21281 | { | |
21282 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
21283 | mi_op, this_regno, this_regno, | |
21284 | mi_delta & (0xff << shift)); | |
21285 | mi_delta &= ~(0xff << shift); | |
21286 | shift += 8; | |
21287 | } | |
21288 | } | |
483ab821 | 21289 | } |
5b3e6663 | 21290 | if (TARGET_THUMB1) |
9b66ebb1 | 21291 | { |
bf98ec6c PB |
21292 | if (TARGET_THUMB1_ONLY) |
21293 | fputs ("\tpop\t{r3}\n", file); | |
21294 | ||
9b66ebb1 PB |
21295 | fprintf (file, "\tbx\tr12\n"); |
21296 | ASM_OUTPUT_ALIGN (file, 2); | |
21297 | assemble_name (file, label); | |
21298 | fputs (":\n", file); | |
54b9e939 KH |
21299 | if (flag_pic) |
21300 | { | |
21301 | /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ | |
21302 | rtx tem = XEXP (DECL_RTL (function), 0); | |
21303 | tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); | |
21304 | tem = gen_rtx_MINUS (GET_MODE (tem), | |
21305 | tem, | |
21306 | gen_rtx_SYMBOL_REF (Pmode, | |
21307 | ggc_strdup (labelpc))); | |
21308 | assemble_integer (tem, 4, BITS_PER_WORD, 1); | |
21309 | } | |
21310 | else | |
21311 | /* Output ".word .LTHUNKn". */ | |
21312 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
bf98ec6c PB |
21313 | |
21314 | if (TARGET_THUMB1_ONLY && mi_delta > 255) | |
21315 | assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1); | |
9b66ebb1 PB |
21316 | } |
21317 | else | |
21318 | { | |
21319 | fputs ("\tb\t", file); | |
21320 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
21321 | if (NEED_PLT_RELOC) | |
21322 | fputs ("(PLT)", file); | |
21323 | fputc ('\n', file); | |
21324 | } | |
483ab821 | 21325 | } |
5a9335ef NC |
21326 | |
21327 | int | |
6f5f2481 | 21328 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
21329 | { |
21330 | int i; | |
21331 | const char * pattern; | |
21332 | ||
e6d29d15 | 21333 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
21334 | |
21335 | switch (GET_MODE (x)) | |
21336 | { | |
21337 | case V2SImode: pattern = "%08x"; break; | |
21338 | case V4HImode: pattern = "%04x"; break; | |
21339 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 21340 | default: gcc_unreachable (); |
5a9335ef NC |
21341 | } |
21342 | ||
21343 | fprintf (file, "0x"); | |
21344 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
21345 | { | |
21346 | rtx element; | |
21347 | ||
21348 | element = CONST_VECTOR_ELT (x, i); | |
21349 | fprintf (file, pattern, INTVAL (element)); | |
21350 | } | |
21351 | ||
21352 | return 1; | |
21353 | } | |
21354 | ||
0fd8c3ad SL |
21355 | /* Emit a fp16 constant appropriately padded to occupy a 4-byte word. |
21356 | HFmode constant pool entries are actually loaded with ldr. */ | |
21357 | void | |
21358 | arm_emit_fp16_const (rtx c) | |
21359 | { | |
21360 | REAL_VALUE_TYPE r; | |
21361 | long bits; | |
21362 | ||
21363 | REAL_VALUE_FROM_CONST_DOUBLE (r, c); | |
21364 | bits = real_to_target (NULL, &r, HFmode); | |
21365 | if (WORDS_BIG_ENDIAN) | |
21366 | assemble_zeros (2); | |
21367 | assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1); | |
21368 | if (!WORDS_BIG_ENDIAN) | |
21369 | assemble_zeros (2); | |
21370 | } | |
21371 | ||
5a9335ef | 21372 | const char * |
6f5f2481 | 21373 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
21374 | { |
21375 | rtx reg; | |
21376 | rtx offset; | |
21377 | rtx wcgr; | |
21378 | rtx sum; | |
f676971a | 21379 | |
5a9335ef NC |
21380 | if (GET_CODE (operands [1]) != MEM |
21381 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
21382 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
21383 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
21384 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
21385 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
21386 | |
21387 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
21388 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
21389 | wcgr = operands[0]; | |
21390 | operands[0] = reg; | |
21391 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
21392 | ||
21393 | operands[0] = wcgr; | |
21394 | operands[1] = reg; | |
21395 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
21396 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
21397 | ||
21398 | return ""; | |
21399 | } | |
f9ba5949 | 21400 | |
1cc9f5f5 KH |
21401 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. |
21402 | ||
21403 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
21404 | named arg and all anonymous args onto the stack. | |
21405 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
21406 | that way. */ | |
21407 | ||
21408 | static void | |
390b17c2 | 21409 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, |
22ccaaee JJ |
21410 | enum machine_mode mode, |
21411 | tree type, | |
1cc9f5f5 KH |
21412 | int *pretend_size, |
21413 | int second_time ATTRIBUTE_UNUSED) | |
21414 | { | |
390b17c2 RE |
21415 | int nregs; |
21416 | ||
1cc9f5f5 | 21417 | cfun->machine->uses_anonymous_args = 1; |
390b17c2 RE |
21418 | if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL) |
21419 | { | |
21420 | nregs = pcum->aapcs_ncrn; | |
21421 | if ((nregs & 1) && arm_needs_doubleword_align (mode, type)) | |
21422 | nregs++; | |
21423 | } | |
21424 | else | |
21425 | nregs = pcum->nregs; | |
21426 | ||
22ccaaee JJ |
21427 | if (nregs < NUM_ARG_REGS) |
21428 | *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
1cc9f5f5 | 21429 | } |
9b66ebb1 | 21430 | |
59b9a953 | 21431 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
21432 | PRODUCER's value to calculate the address. */ |
21433 | ||
21434 | int | |
21435 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
21436 | { | |
21437 | rtx value = PATTERN (producer); | |
21438 | rtx addr = PATTERN (consumer); | |
21439 | ||
21440 | if (GET_CODE (value) == COND_EXEC) | |
21441 | value = COND_EXEC_CODE (value); | |
21442 | if (GET_CODE (value) == PARALLEL) | |
21443 | value = XVECEXP (value, 0, 0); | |
21444 | value = XEXP (value, 0); | |
21445 | if (GET_CODE (addr) == COND_EXEC) | |
21446 | addr = COND_EXEC_CODE (addr); | |
21447 | if (GET_CODE (addr) == PARALLEL) | |
21448 | addr = XVECEXP (addr, 0, 0); | |
21449 | addr = XEXP (addr, 0); | |
f676971a | 21450 | |
9b66ebb1 PB |
21451 | return !reg_overlap_mentioned_p (value, addr); |
21452 | } | |
21453 | ||
59b9a953 | 21454 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
21455 | have an early register shift value or amount dependency on the |
21456 | result of PRODUCER. */ | |
21457 | ||
21458 | int | |
21459 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
21460 | { | |
21461 | rtx value = PATTERN (producer); | |
21462 | rtx op = PATTERN (consumer); | |
21463 | rtx early_op; | |
21464 | ||
21465 | if (GET_CODE (value) == COND_EXEC) | |
21466 | value = COND_EXEC_CODE (value); | |
21467 | if (GET_CODE (value) == PARALLEL) | |
21468 | value = XVECEXP (value, 0, 0); | |
21469 | value = XEXP (value, 0); | |
21470 | if (GET_CODE (op) == COND_EXEC) | |
21471 | op = COND_EXEC_CODE (op); | |
21472 | if (GET_CODE (op) == PARALLEL) | |
21473 | op = XVECEXP (op, 0, 0); | |
21474 | op = XEXP (op, 1); | |
f676971a | 21475 | |
9b66ebb1 PB |
21476 | early_op = XEXP (op, 0); |
21477 | /* This is either an actual independent shift, or a shift applied to | |
21478 | the first operand of another operation. We want the whole shift | |
21479 | operation. */ | |
21480 | if (GET_CODE (early_op) == REG) | |
21481 | early_op = op; | |
21482 | ||
21483 | return !reg_overlap_mentioned_p (value, early_op); | |
21484 | } | |
21485 | ||
59b9a953 | 21486 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
21487 | have an early register shift value dependency on the result of |
21488 | PRODUCER. */ | |
21489 | ||
21490 | int | |
21491 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
21492 | { | |
21493 | rtx value = PATTERN (producer); | |
21494 | rtx op = PATTERN (consumer); | |
21495 | rtx early_op; | |
21496 | ||
21497 | if (GET_CODE (value) == COND_EXEC) | |
21498 | value = COND_EXEC_CODE (value); | |
21499 | if (GET_CODE (value) == PARALLEL) | |
21500 | value = XVECEXP (value, 0, 0); | |
21501 | value = XEXP (value, 0); | |
21502 | if (GET_CODE (op) == COND_EXEC) | |
21503 | op = COND_EXEC_CODE (op); | |
21504 | if (GET_CODE (op) == PARALLEL) | |
21505 | op = XVECEXP (op, 0, 0); | |
21506 | op = XEXP (op, 1); | |
f676971a | 21507 | |
9b66ebb1 PB |
21508 | early_op = XEXP (op, 0); |
21509 | ||
21510 | /* This is either an actual independent shift, or a shift applied to | |
21511 | the first operand of another operation. We want the value being | |
21512 | shifted, in either case. */ | |
21513 | if (GET_CODE (early_op) != REG) | |
21514 | early_op = XEXP (early_op, 0); | |
f676971a | 21515 | |
9b66ebb1 PB |
21516 | return !reg_overlap_mentioned_p (value, early_op); |
21517 | } | |
21518 | ||
59b9a953 | 21519 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
21520 | have an early register mult dependency on the result of |
21521 | PRODUCER. */ | |
21522 | ||
21523 | int | |
21524 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
21525 | { | |
21526 | rtx value = PATTERN (producer); | |
21527 | rtx op = PATTERN (consumer); | |
21528 | ||
21529 | if (GET_CODE (value) == COND_EXEC) | |
21530 | value = COND_EXEC_CODE (value); | |
21531 | if (GET_CODE (value) == PARALLEL) | |
21532 | value = XVECEXP (value, 0, 0); | |
21533 | value = XEXP (value, 0); | |
21534 | if (GET_CODE (op) == COND_EXEC) | |
21535 | op = COND_EXEC_CODE (op); | |
21536 | if (GET_CODE (op) == PARALLEL) | |
21537 | op = XVECEXP (op, 0, 0); | |
21538 | op = XEXP (op, 1); | |
f676971a | 21539 | |
756f763b PB |
21540 | if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
21541 | { | |
21542 | if (GET_CODE (XEXP (op, 0)) == MULT) | |
21543 | return !reg_overlap_mentioned_p (value, XEXP (op, 0)); | |
21544 | else | |
21545 | return !reg_overlap_mentioned_p (value, XEXP (op, 1)); | |
21546 | } | |
21547 | ||
21548 | return 0; | |
9b66ebb1 PB |
21549 | } |
21550 | ||
70301b45 PB |
21551 | /* We can't rely on the caller doing the proper promotion when |
21552 | using APCS or ATPCS. */ | |
21553 | ||
21554 | static bool | |
586de218 | 21555 | arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED) |
70301b45 | 21556 | { |
b6685939 | 21557 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
21558 | } |
21559 | ||
cde0f3fd PB |
21560 | static enum machine_mode |
21561 | arm_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, | |
21562 | enum machine_mode mode, | |
21563 | int *punsignedp ATTRIBUTE_UNUSED, | |
21564 | const_tree fntype ATTRIBUTE_UNUSED, | |
21565 | int for_return ATTRIBUTE_UNUSED) | |
21566 | { | |
21567 | if (GET_MODE_CLASS (mode) == MODE_INT | |
21568 | && GET_MODE_SIZE (mode) < 4) | |
21569 | return SImode; | |
21570 | ||
21571 | return mode; | |
21572 | } | |
6b045785 PB |
21573 | |
21574 | /* AAPCS based ABIs use short enums by default. */ | |
21575 | ||
21576 | static bool | |
21577 | arm_default_short_enums (void) | |
21578 | { | |
077fc835 | 21579 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 21580 | } |
13c1cd82 PB |
21581 | |
21582 | ||
21583 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
21584 | ||
21585 | static bool | |
21586 | arm_align_anon_bitfield (void) | |
21587 | { | |
21588 | return TARGET_AAPCS_BASED; | |
21589 | } | |
4185ae53 PB |
21590 | |
21591 | ||
21592 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
21593 | ||
21594 | static tree | |
21595 | arm_cxx_guard_type (void) | |
21596 | { | |
21597 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
21598 | } | |
21599 | ||
c956e102 MS |
21600 | /* Return non-zero if the consumer (a multiply-accumulate instruction) |
21601 | has an accumulator dependency on the result of the producer (a | |
21602 | multiplication instruction) and no other dependency on that result. */ | |
21603 | int | |
21604 | arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) | |
21605 | { | |
21606 | rtx mul = PATTERN (producer); | |
21607 | rtx mac = PATTERN (consumer); | |
21608 | rtx mul_result; | |
21609 | rtx mac_op0, mac_op1, mac_acc; | |
21610 | ||
21611 | if (GET_CODE (mul) == COND_EXEC) | |
21612 | mul = COND_EXEC_CODE (mul); | |
21613 | if (GET_CODE (mac) == COND_EXEC) | |
21614 | mac = COND_EXEC_CODE (mac); | |
21615 | ||
21616 | /* Check that mul is of the form (set (...) (mult ...)) | |
21617 | and mla is of the form (set (...) (plus (mult ...) (...))). */ | |
21618 | if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT) | |
21619 | || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS | |
21620 | || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT)) | |
21621 | return 0; | |
21622 | ||
21623 | mul_result = XEXP (mul, 0); | |
21624 | mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0); | |
21625 | mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1); | |
21626 | mac_acc = XEXP (XEXP (mac, 1), 1); | |
21627 | ||
21628 | return (reg_overlap_mentioned_p (mul_result, mac_acc) | |
21629 | && !reg_overlap_mentioned_p (mul_result, mac_op0) | |
21630 | && !reg_overlap_mentioned_p (mul_result, mac_op1)); | |
21631 | } | |
21632 | ||
4185ae53 | 21633 | |
0fa2e4df | 21634 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
21635 | |
21636 | static bool | |
21637 | arm_cxx_guard_mask_bit (void) | |
21638 | { | |
21639 | return TARGET_AAPCS_BASED; | |
21640 | } | |
46e995e0 PB |
21641 | |
21642 | ||
21643 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
21644 | ||
21645 | static tree | |
21646 | arm_get_cookie_size (tree type) | |
21647 | { | |
21648 | tree size; | |
21649 | ||
21650 | if (!TARGET_AAPCS_BASED) | |
21651 | return default_cxx_get_cookie_size (type); | |
21652 | ||
7d60be94 | 21653 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
21654 | return size; |
21655 | } | |
21656 | ||
21657 | ||
21658 | /* The EABI says that array cookies should also contain the element size. */ | |
21659 | ||
21660 | static bool | |
21661 | arm_cookie_has_size (void) | |
21662 | { | |
21663 | return TARGET_AAPCS_BASED; | |
21664 | } | |
44d10c10 PB |
21665 | |
21666 | ||
21667 | /* The EABI says constructors and destructors should return a pointer to | |
21668 | the object constructed/destroyed. */ | |
21669 | ||
21670 | static bool | |
21671 | arm_cxx_cdtor_returns_this (void) | |
21672 | { | |
21673 | return TARGET_AAPCS_BASED; | |
21674 | } | |
c9ca9b88 | 21675 | |
505970fc MM |
21676 | /* The EABI says that an inline function may never be the key |
21677 | method. */ | |
21678 | ||
21679 | static bool | |
21680 | arm_cxx_key_method_may_be_inline (void) | |
21681 | { | |
21682 | return !TARGET_AAPCS_BASED; | |
21683 | } | |
21684 | ||
1e731102 MM |
21685 | static void |
21686 | arm_cxx_determine_class_data_visibility (tree decl) | |
21687 | { | |
711b2998 JB |
21688 | if (!TARGET_AAPCS_BASED |
21689 | || !TARGET_DLLIMPORT_DECL_ATTRIBUTES) | |
1e731102 | 21690 | return; |
505970fc | 21691 | |
1e731102 MM |
21692 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
21693 | is exported. However, on systems without dynamic vague linkage, | |
21694 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
21695 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
21696 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
21697 | else | |
21698 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
21699 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
21700 | } | |
e0b92319 | 21701 | |
505970fc | 21702 | static bool |
1e731102 | 21703 | arm_cxx_class_data_always_comdat (void) |
505970fc | 21704 | { |
1e731102 MM |
21705 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
21706 | vague linkage if the class has no key function. */ | |
21707 | return !TARGET_AAPCS_BASED; | |
505970fc | 21708 | } |
c9ca9b88 | 21709 | |
9f62c3e3 PB |
21710 | |
21711 | /* The EABI says __aeabi_atexit should be used to register static | |
21712 | destructors. */ | |
21713 | ||
21714 | static bool | |
21715 | arm_cxx_use_aeabi_atexit (void) | |
21716 | { | |
21717 | return TARGET_AAPCS_BASED; | |
21718 | } | |
21719 | ||
21720 | ||
c9ca9b88 PB |
21721 | void |
21722 | arm_set_return_address (rtx source, rtx scratch) | |
21723 | { | |
21724 | arm_stack_offsets *offsets; | |
21725 | HOST_WIDE_INT delta; | |
21726 | rtx addr; | |
21727 | unsigned long saved_regs; | |
21728 | ||
954954d1 PB |
21729 | offsets = arm_get_frame_offsets (); |
21730 | saved_regs = offsets->saved_regs_mask; | |
c9ca9b88 PB |
21731 | |
21732 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
21733 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
21734 | else | |
21735 | { | |
21736 | if (frame_pointer_needed) | |
21737 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
21738 | else | |
21739 | { | |
21740 | /* LR will be the first saved register. */ | |
c9ca9b88 PB |
21741 | delta = offsets->outgoing_args - (offsets->frame + 4); |
21742 | ||
f676971a | 21743 | |
c9ca9b88 PB |
21744 | if (delta >= 4096) |
21745 | { | |
21746 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
21747 | GEN_INT (delta & ~4095))); | |
21748 | addr = scratch; | |
21749 | delta &= 4095; | |
21750 | } | |
21751 | else | |
21752 | addr = stack_pointer_rtx; | |
21753 | ||
21754 | addr = plus_constant (addr, delta); | |
21755 | } | |
31fa16b6 | 21756 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
21757 | } |
21758 | } | |
21759 | ||
21760 | ||
21761 | void | |
21762 | thumb_set_return_address (rtx source, rtx scratch) | |
21763 | { | |
21764 | arm_stack_offsets *offsets; | |
c9ca9b88 | 21765 | HOST_WIDE_INT delta; |
5b3e6663 | 21766 | HOST_WIDE_INT limit; |
c9ca9b88 PB |
21767 | int reg; |
21768 | rtx addr; | |
57934c39 | 21769 | unsigned long mask; |
c9ca9b88 | 21770 | |
c41c1387 | 21771 | emit_use (source); |
c9ca9b88 | 21772 | |
954954d1 PB |
21773 | offsets = arm_get_frame_offsets (); |
21774 | mask = offsets->saved_regs_mask; | |
57934c39 | 21775 | if (mask & (1 << LR_REGNUM)) |
c9ca9b88 | 21776 | { |
5b3e6663 | 21777 | limit = 1024; |
c9ca9b88 PB |
21778 | /* Find the saved regs. */ |
21779 | if (frame_pointer_needed) | |
21780 | { | |
21781 | delta = offsets->soft_frame - offsets->saved_args; | |
21782 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
5b3e6663 PB |
21783 | if (TARGET_THUMB1) |
21784 | limit = 128; | |
c9ca9b88 PB |
21785 | } |
21786 | else | |
21787 | { | |
21788 | delta = offsets->outgoing_args - offsets->saved_args; | |
21789 | reg = SP_REGNUM; | |
21790 | } | |
21791 | /* Allow for the stack frame. */ | |
5b3e6663 | 21792 | if (TARGET_THUMB1 && TARGET_BACKTRACE) |
c9ca9b88 PB |
21793 | delta -= 16; |
21794 | /* The link register is always the first saved register. */ | |
21795 | delta -= 4; | |
f676971a | 21796 | |
c9ca9b88 PB |
21797 | /* Construct the address. */ |
21798 | addr = gen_rtx_REG (SImode, reg); | |
5b3e6663 | 21799 | if (delta > limit) |
c9ca9b88 PB |
21800 | { |
21801 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
21802 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
21803 | addr = scratch; | |
21804 | } | |
21805 | else | |
21806 | addr = plus_constant (addr, delta); | |
21807 | ||
31fa16b6 | 21808 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
21809 | } |
21810 | else | |
21811 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
21812 | } | |
21813 | ||
f676971a EC |
21814 | /* Implements target hook vector_mode_supported_p. */ |
21815 | bool | |
21816 | arm_vector_mode_supported_p (enum machine_mode mode) | |
21817 | { | |
88f77cba JB |
21818 | /* Neon also supports V2SImode, etc. listed in the clause below. */ |
21819 | if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode | |
21820 | || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) | |
21821 | return true; | |
21822 | ||
390b17c2 RE |
21823 | if ((TARGET_NEON || TARGET_IWMMXT) |
21824 | && ((mode == V2SImode) | |
21825 | || (mode == V4HImode) | |
21826 | || (mode == V8QImode))) | |
f676971a EC |
21827 | return true; |
21828 | ||
21829 | return false; | |
21830 | } | |
273a2526 | 21831 | |
42db504c SB |
21832 | /* Implements target hook small_register_classes_for_mode_p. */ |
21833 | bool | |
21834 | arm_small_register_classes_for_mode_p (enum machine_mode mode ATTRIBUTE_UNUSED) | |
21835 | { | |
21836 | return TARGET_THUMB1; | |
21837 | } | |
21838 | ||
273a2526 RS |
21839 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal |
21840 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
21841 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
21842 | guarantee no particular behavior for out-of-range counts. */ | |
21843 | ||
21844 | static unsigned HOST_WIDE_INT | |
21845 | arm_shift_truncation_mask (enum machine_mode mode) | |
21846 | { | |
21847 | return mode == SImode ? 255 : 0; | |
21848 | } | |
2fa330b2 PB |
21849 | |
21850 | ||
21851 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
21852 | ||
21853 | unsigned int | |
21854 | arm_dbx_register_number (unsigned int regno) | |
21855 | { | |
21856 | if (regno < 16) | |
21857 | return regno; | |
21858 | ||
21859 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
21860 | compatibility. The EABI defines them as registers 96-103. */ | |
21861 | if (IS_FPA_REGNUM (regno)) | |
21862 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
21863 | ||
21864 | if (IS_VFP_REGNUM (regno)) | |
854b8a40 JB |
21865 | { |
21866 | /* See comment in arm_dwarf_register_span. */ | |
21867 | if (VFP_REGNO_OK_FOR_SINGLE (regno)) | |
21868 | return 64 + regno - FIRST_VFP_REGNUM; | |
21869 | else | |
21870 | return 256 + (regno - FIRST_VFP_REGNUM) / 2; | |
21871 | } | |
2fa330b2 PB |
21872 | |
21873 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
21874 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
21875 | ||
21876 | if (IS_IWMMXT_REGNUM (regno)) | |
21877 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
21878 | ||
e6d29d15 | 21879 | gcc_unreachable (); |
2fa330b2 PB |
21880 | } |
21881 | ||
854b8a40 JB |
21882 | /* Dwarf models VFPv3 registers as 32 64-bit registers. |
21883 | GCC models tham as 64 32-bit registers, so we need to describe this to | |
21884 | the DWARF generation code. Other registers can use the default. */ | |
21885 | static rtx | |
21886 | arm_dwarf_register_span (rtx rtl) | |
21887 | { | |
21888 | unsigned regno; | |
21889 | int nregs; | |
21890 | int i; | |
21891 | rtx p; | |
21892 | ||
21893 | regno = REGNO (rtl); | |
21894 | if (!IS_VFP_REGNUM (regno)) | |
21895 | return NULL_RTX; | |
21896 | ||
21897 | /* XXX FIXME: The EABI defines two VFP register ranges: | |
21898 | 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent) | |
21899 | 256-287: D0-D31 | |
21900 | The recommended encoding for S0-S31 is a DW_OP_bit_piece of the | |
21901 | corresponding D register. Until GDB supports this, we shall use the | |
21902 | legacy encodings. We also use these encodings for D0-D15 for | |
21903 | compatibility with older debuggers. */ | |
21904 | if (VFP_REGNO_OK_FOR_SINGLE (regno)) | |
21905 | return NULL_RTX; | |
21906 | ||
21907 | nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8; | |
21908 | p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs)); | |
21909 | regno = (regno - FIRST_VFP_REGNUM) / 2; | |
21910 | for (i = 0; i < nregs; i++) | |
21911 | XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i); | |
21912 | ||
21913 | return p; | |
21914 | } | |
617a1b71 PB |
21915 | |
21916 | #ifdef TARGET_UNWIND_INFO | |
5b3e6663 PB |
21917 | /* Emit unwind directives for a store-multiple instruction or stack pointer |
21918 | push during alignment. | |
21919 | These should only ever be generated by the function prologue code, so | |
21920 | expect them to have a particular form. */ | |
617a1b71 PB |
21921 | |
21922 | static void | |
5b3e6663 | 21923 | arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) |
617a1b71 PB |
21924 | { |
21925 | int i; | |
21926 | HOST_WIDE_INT offset; | |
21927 | HOST_WIDE_INT nregs; | |
21928 | int reg_size; | |
21929 | unsigned reg; | |
21930 | unsigned lastreg; | |
21931 | rtx e; | |
21932 | ||
617a1b71 | 21933 | e = XVECEXP (p, 0, 0); |
5b3e6663 PB |
21934 | if (GET_CODE (e) != SET) |
21935 | abort (); | |
21936 | ||
21937 | /* First insn will adjust the stack pointer. */ | |
617a1b71 PB |
21938 | if (GET_CODE (e) != SET |
21939 | || GET_CODE (XEXP (e, 0)) != REG | |
21940 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
21941 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
21942 | abort (); | |
21943 | ||
21944 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
21945 | nregs = XVECLEN (p, 0) - 1; | |
21946 | ||
21947 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
21948 | if (reg < 16) | |
21949 | { | |
21950 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 21951 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
21952 | if (nregs * 4 == offset - 4) |
21953 | { | |
21954 | fprintf (asm_out_file, "\t.pad #4\n"); | |
21955 | offset -= 4; | |
21956 | } | |
21957 | reg_size = 4; | |
8edfc4cc | 21958 | fprintf (asm_out_file, "\t.save {"); |
617a1b71 PB |
21959 | } |
21960 | else if (IS_VFP_REGNUM (reg)) | |
21961 | { | |
617a1b71 | 21962 | reg_size = 8; |
8edfc4cc | 21963 | fprintf (asm_out_file, "\t.vsave {"); |
617a1b71 PB |
21964 | } |
21965 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
21966 | { | |
21967 | /* FPA registers are done differently. */ | |
ea40ba9c | 21968 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
21969 | return; |
21970 | } | |
21971 | else | |
21972 | /* Unknown register type. */ | |
21973 | abort (); | |
21974 | ||
21975 | /* If the stack increment doesn't match the size of the saved registers, | |
21976 | something has gone horribly wrong. */ | |
21977 | if (offset != nregs * reg_size) | |
21978 | abort (); | |
21979 | ||
617a1b71 PB |
21980 | offset = 0; |
21981 | lastreg = 0; | |
21982 | /* The remaining insns will describe the stores. */ | |
21983 | for (i = 1; i <= nregs; i++) | |
21984 | { | |
21985 | /* Expect (set (mem <addr>) (reg)). | |
21986 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
21987 | e = XVECEXP (p, 0, i); | |
21988 | if (GET_CODE (e) != SET | |
21989 | || GET_CODE (XEXP (e, 0)) != MEM | |
21990 | || GET_CODE (XEXP (e, 1)) != REG) | |
21991 | abort (); | |
e0b92319 | 21992 | |
617a1b71 PB |
21993 | reg = REGNO (XEXP (e, 1)); |
21994 | if (reg < lastreg) | |
21995 | abort (); | |
e0b92319 | 21996 | |
617a1b71 PB |
21997 | if (i != 1) |
21998 | fprintf (asm_out_file, ", "); | |
21999 | /* We can't use %r for vfp because we need to use the | |
22000 | double precision register names. */ | |
22001 | if (IS_VFP_REGNUM (reg)) | |
22002 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
22003 | else | |
22004 | asm_fprintf (asm_out_file, "%r", reg); | |
22005 | ||
22006 | #ifdef ENABLE_CHECKING | |
22007 | /* Check that the addresses are consecutive. */ | |
22008 | e = XEXP (XEXP (e, 0), 0); | |
22009 | if (GET_CODE (e) == PLUS) | |
22010 | { | |
22011 | offset += reg_size; | |
22012 | if (GET_CODE (XEXP (e, 0)) != REG | |
22013 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
22014 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
22015 | || offset != INTVAL (XEXP (e, 1))) | |
22016 | abort (); | |
22017 | } | |
22018 | else if (i != 1 | |
22019 | || GET_CODE (e) != REG | |
22020 | || REGNO (e) != SP_REGNUM) | |
22021 | abort (); | |
22022 | #endif | |
22023 | } | |
22024 | fprintf (asm_out_file, "}\n"); | |
22025 | } | |
22026 | ||
22027 | /* Emit unwind directives for a SET. */ | |
22028 | ||
22029 | static void | |
22030 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
22031 | { | |
22032 | rtx e0; | |
22033 | rtx e1; | |
5b3e6663 | 22034 | unsigned reg; |
617a1b71 PB |
22035 | |
22036 | e0 = XEXP (p, 0); | |
22037 | e1 = XEXP (p, 1); | |
22038 | switch (GET_CODE (e0)) | |
22039 | { | |
22040 | case MEM: | |
22041 | /* Pushing a single register. */ | |
22042 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
22043 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
22044 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
22045 | abort (); | |
22046 | ||
22047 | asm_fprintf (asm_out_file, "\t.save "); | |
22048 | if (IS_VFP_REGNUM (REGNO (e1))) | |
22049 | asm_fprintf(asm_out_file, "{d%d}\n", | |
22050 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
22051 | else | |
22052 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
22053 | break; | |
22054 | ||
22055 | case REG: | |
22056 | if (REGNO (e0) == SP_REGNUM) | |
22057 | { | |
22058 | /* A stack increment. */ | |
22059 | if (GET_CODE (e1) != PLUS | |
22060 | || GET_CODE (XEXP (e1, 0)) != REG | |
22061 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
22062 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
22063 | abort (); | |
22064 | ||
ea40ba9c | 22065 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
22066 | -INTVAL (XEXP (e1, 1))); |
22067 | } | |
22068 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
22069 | { | |
22070 | HOST_WIDE_INT offset; | |
e0b92319 | 22071 | |
617a1b71 PB |
22072 | if (GET_CODE (e1) == PLUS) |
22073 | { | |
22074 | if (GET_CODE (XEXP (e1, 0)) != REG | |
22075 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
22076 | abort (); | |
22077 | reg = REGNO (XEXP (e1, 0)); | |
22078 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 22079 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 | 22080 | HARD_FRAME_POINTER_REGNUM, reg, |
80d56d04 | 22081 | offset); |
617a1b71 PB |
22082 | } |
22083 | else if (GET_CODE (e1) == REG) | |
22084 | { | |
22085 | reg = REGNO (e1); | |
22086 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
22087 | HARD_FRAME_POINTER_REGNUM, reg); | |
22088 | } | |
22089 | else | |
22090 | abort (); | |
22091 | } | |
22092 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
22093 | { | |
22094 | /* Move from sp to reg. */ | |
22095 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
22096 | } | |
758ed9b2 PB |
22097 | else if (GET_CODE (e1) == PLUS |
22098 | && GET_CODE (XEXP (e1, 0)) == REG | |
22099 | && REGNO (XEXP (e1, 0)) == SP_REGNUM | |
22100 | && GET_CODE (XEXP (e1, 1)) == CONST_INT) | |
22101 | { | |
22102 | /* Set reg to offset from sp. */ | |
22103 | asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", | |
22104 | REGNO (e0), (int)INTVAL(XEXP (e1, 1))); | |
22105 | } | |
5b3e6663 PB |
22106 | else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN) |
22107 | { | |
22108 | /* Stack pointer save before alignment. */ | |
22109 | reg = REGNO (e0); | |
22110 | asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n", | |
22111 | reg + 0x90, reg); | |
22112 | } | |
617a1b71 PB |
22113 | else |
22114 | abort (); | |
22115 | break; | |
22116 | ||
22117 | default: | |
22118 | abort (); | |
22119 | } | |
22120 | } | |
22121 | ||
22122 | ||
22123 | /* Emit unwind directives for the given insn. */ | |
22124 | ||
22125 | static void | |
22126 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
22127 | { | |
22128 | rtx pat; | |
22129 | ||
22130 | if (!ARM_EABI_UNWIND_TABLES) | |
22131 | return; | |
22132 | ||
e3b5732b | 22133 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 22134 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 22135 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
22136 | return; |
22137 | ||
617a1b71 PB |
22138 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) |
22139 | return; | |
22140 | ||
22141 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
22142 | if (pat) | |
22143 | pat = XEXP (pat, 0); | |
22144 | else | |
22145 | pat = PATTERN (insn); | |
22146 | ||
22147 | switch (GET_CODE (pat)) | |
22148 | { | |
22149 | case SET: | |
22150 | arm_unwind_emit_set (asm_out_file, pat); | |
22151 | break; | |
22152 | ||
22153 | case SEQUENCE: | |
22154 | /* Store multiple. */ | |
5b3e6663 | 22155 | arm_unwind_emit_sequence (asm_out_file, pat); |
617a1b71 PB |
22156 | break; |
22157 | ||
22158 | default: | |
22159 | abort(); | |
22160 | } | |
22161 | } | |
22162 | ||
22163 | ||
22164 | /* Output a reference from a function exception table to the type_info | |
22165 | object X. The EABI specifies that the symbol should be relocated by | |
22166 | an R_ARM_TARGET2 relocation. */ | |
22167 | ||
22168 | static bool | |
22169 | arm_output_ttype (rtx x) | |
22170 | { | |
22171 | fputs ("\t.word\t", asm_out_file); | |
22172 | output_addr_const (asm_out_file, x); | |
22173 | /* Use special relocations for symbol references. */ | |
22174 | if (GET_CODE (x) != CONST_INT) | |
22175 | fputs ("(TARGET2)", asm_out_file); | |
22176 | fputc ('\n', asm_out_file); | |
22177 | ||
22178 | return TRUE; | |
22179 | } | |
22180 | #endif /* TARGET_UNWIND_INFO */ | |
22181 | ||
22182 | ||
5b3e6663 PB |
22183 | /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic |
22184 | stack alignment. */ | |
22185 | ||
22186 | static void | |
22187 | arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) | |
22188 | { | |
22189 | rtx unspec = SET_SRC (pattern); | |
22190 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
22191 | ||
22192 | switch (index) | |
22193 | { | |
22194 | case UNSPEC_STACK_ALIGN: | |
22195 | /* ??? We should set the CFA = (SP & ~7). At this point we haven't | |
22196 | put anything on the stack, so hopefully it won't matter. | |
22197 | CFA = SP will be correct after alignment. */ | |
22198 | dwarf2out_reg_save_reg (label, stack_pointer_rtx, | |
22199 | SET_DEST (pattern)); | |
22200 | break; | |
22201 | default: | |
22202 | gcc_unreachable (); | |
22203 | } | |
22204 | } | |
22205 | ||
22206 | ||
617a1b71 PB |
22207 | /* Output unwind directives for the start/end of a function. */ |
22208 | ||
22209 | void | |
22210 | arm_output_fn_unwind (FILE * f, bool prologue) | |
22211 | { | |
22212 | if (!ARM_EABI_UNWIND_TABLES) | |
22213 | return; | |
22214 | ||
22215 | if (prologue) | |
22216 | fputs ("\t.fnstart\n", f); | |
22217 | else | |
80efdb6a PB |
22218 | { |
22219 | /* If this function will never be unwound, then mark it as such. | |
22220 | The came condition is used in arm_unwind_emit to suppress | |
22221 | the frame annotations. */ | |
e3b5732b | 22222 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 22223 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 22224 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
22225 | fputs("\t.cantunwind\n", f); |
22226 | ||
22227 | fputs ("\t.fnend\n", f); | |
22228 | } | |
617a1b71 | 22229 | } |
d3585b76 DJ |
22230 | |
22231 | static bool | |
22232 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
22233 | { | |
22234 | enum tls_reloc reloc; | |
22235 | rtx val; | |
22236 | ||
22237 | val = XVECEXP (x, 0, 0); | |
32e8bb8e | 22238 | reloc = (enum tls_reloc) INTVAL (XVECEXP (x, 0, 1)); |
d3585b76 DJ |
22239 | |
22240 | output_addr_const (fp, val); | |
22241 | ||
22242 | switch (reloc) | |
22243 | { | |
22244 | case TLS_GD32: | |
22245 | fputs ("(tlsgd)", fp); | |
22246 | break; | |
22247 | case TLS_LDM32: | |
22248 | fputs ("(tlsldm)", fp); | |
22249 | break; | |
22250 | case TLS_LDO32: | |
22251 | fputs ("(tlsldo)", fp); | |
22252 | break; | |
22253 | case TLS_IE32: | |
22254 | fputs ("(gottpoff)", fp); | |
22255 | break; | |
22256 | case TLS_LE32: | |
22257 | fputs ("(tpoff)", fp); | |
22258 | break; | |
22259 | default: | |
22260 | gcc_unreachable (); | |
22261 | } | |
22262 | ||
22263 | switch (reloc) | |
22264 | { | |
22265 | case TLS_GD32: | |
22266 | case TLS_LDM32: | |
22267 | case TLS_IE32: | |
22268 | fputs (" + (. - ", fp); | |
22269 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
22270 | fputs (" - ", fp); | |
22271 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
22272 | fputc (')', fp); | |
22273 | break; | |
22274 | default: | |
22275 | break; | |
22276 | } | |
22277 | ||
22278 | return TRUE; | |
22279 | } | |
22280 | ||
afcc986d JM |
22281 | /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
22282 | ||
22283 | static void | |
22284 | arm_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
22285 | { | |
22286 | gcc_assert (size == 4); | |
22287 | fputs ("\t.word\t", file); | |
22288 | output_addr_const (file, x); | |
22289 | fputs ("(tlsldo)", file); | |
22290 | } | |
22291 | ||
d3585b76 DJ |
22292 | bool |
22293 | arm_output_addr_const_extra (FILE *fp, rtx x) | |
22294 | { | |
22295 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
22296 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
22297 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
22298 | { | |
22299 | char label[256]; | |
22300 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
22301 | ||
22302 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
22303 | assemble_name_raw (fp, label); | |
22304 | ||
f9bd1a89 RS |
22305 | return TRUE; |
22306 | } | |
22307 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF) | |
22308 | { | |
22309 | assemble_name (fp, "_GLOBAL_OFFSET_TABLE_"); | |
22310 | if (GOT_PCREL) | |
22311 | fputs ("+.", fp); | |
22312 | fputs ("-(", fp); | |
22313 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
22314 | fputc (')', fp); | |
f16fe45f DJ |
22315 | return TRUE; |
22316 | } | |
85c9bcd4 WG |
22317 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET) |
22318 | { | |
22319 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
22320 | if (GOT_PCREL) | |
22321 | fputs ("+.", fp); | |
22322 | fputs ("-(", fp); | |
22323 | output_addr_const (fp, XVECEXP (x, 0, 1)); | |
22324 | fputc (')', fp); | |
22325 | return TRUE; | |
22326 | } | |
d3585b76 DJ |
22327 | else if (GET_CODE (x) == CONST_VECTOR) |
22328 | return arm_emit_vector_const (fp, x); | |
22329 | ||
22330 | return FALSE; | |
22331 | } | |
22332 | ||
5b3e6663 PB |
22333 | /* Output assembly for a shift instruction. |
22334 | SET_FLAGS determines how the instruction modifies the condition codes. | |
7a085dce | 22335 | 0 - Do not set condition codes. |
5b3e6663 PB |
22336 | 1 - Set condition codes. |
22337 | 2 - Use smallest instruction. */ | |
22338 | const char * | |
22339 | arm_output_shift(rtx * operands, int set_flags) | |
22340 | { | |
22341 | char pattern[100]; | |
22342 | static const char flag_chars[3] = {'?', '.', '!'}; | |
22343 | const char *shift; | |
22344 | HOST_WIDE_INT val; | |
22345 | char c; | |
22346 | ||
22347 | c = flag_chars[set_flags]; | |
22348 | if (TARGET_UNIFIED_ASM) | |
22349 | { | |
22350 | shift = shift_op(operands[3], &val); | |
22351 | if (shift) | |
22352 | { | |
22353 | if (val != -1) | |
22354 | operands[2] = GEN_INT(val); | |
22355 | sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c); | |
22356 | } | |
22357 | else | |
22358 | sprintf (pattern, "mov%%%c\t%%0, %%1", c); | |
22359 | } | |
22360 | else | |
22361 | sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c); | |
22362 | output_asm_insn (pattern, operands); | |
22363 | return ""; | |
22364 | } | |
22365 | ||
907dd0c7 RE |
22366 | /* Output a Thumb-1 casesi dispatch sequence. */ |
22367 | const char * | |
22368 | thumb1_output_casesi (rtx *operands) | |
22369 | { | |
22370 | rtx diff_vec = PATTERN (next_real_insn (operands[0])); | |
907dd0c7 RE |
22371 | |
22372 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
22373 | ||
907dd0c7 RE |
22374 | switch (GET_MODE(diff_vec)) |
22375 | { | |
22376 | case QImode: | |
22377 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
22378 | "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi"); | |
22379 | case HImode: | |
22380 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
22381 | "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi"); | |
22382 | case SImode: | |
22383 | return "bl\t%___gnu_thumb1_case_si"; | |
22384 | default: | |
22385 | gcc_unreachable (); | |
22386 | } | |
22387 | } | |
22388 | ||
5b3e6663 PB |
22389 | /* Output a Thumb-2 casesi instruction. */ |
22390 | const char * | |
22391 | thumb2_output_casesi (rtx *operands) | |
22392 | { | |
22393 | rtx diff_vec = PATTERN (next_real_insn (operands[2])); | |
22394 | ||
22395 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
22396 | ||
22397 | output_asm_insn ("cmp\t%0, %1", operands); | |
22398 | output_asm_insn ("bhi\t%l3", operands); | |
22399 | switch (GET_MODE(diff_vec)) | |
22400 | { | |
22401 | case QImode: | |
22402 | return "tbb\t[%|pc, %0]"; | |
22403 | case HImode: | |
22404 | return "tbh\t[%|pc, %0, lsl #1]"; | |
22405 | case SImode: | |
22406 | if (flag_pic) | |
22407 | { | |
22408 | output_asm_insn ("adr\t%4, %l2", operands); | |
22409 | output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands); | |
22410 | output_asm_insn ("add\t%4, %4, %5", operands); | |
22411 | return "bx\t%4"; | |
22412 | } | |
22413 | else | |
22414 | { | |
22415 | output_asm_insn ("adr\t%4, %l2", operands); | |
22416 | return "ldr\t%|pc, [%4, %0, lsl #2]"; | |
22417 | } | |
22418 | default: | |
22419 | gcc_unreachable (); | |
22420 | } | |
22421 | } | |
22422 | ||
bd4dc3cd PB |
22423 | /* Most ARM cores are single issue, but some newer ones can dual issue. |
22424 | The scheduler descriptions rely on this being correct. */ | |
22425 | static int | |
22426 | arm_issue_rate (void) | |
22427 | { | |
22428 | switch (arm_tune) | |
22429 | { | |
22430 | case cortexr4: | |
51c69ddb | 22431 | case cortexr4f: |
bd4dc3cd | 22432 | case cortexa8: |
7612f14d | 22433 | case cortexa9: |
bd4dc3cd PB |
22434 | return 2; |
22435 | ||
22436 | default: | |
22437 | return 1; | |
22438 | } | |
22439 | } | |
22440 | ||
608063c3 JB |
22441 | /* A table and a function to perform ARM-specific name mangling for |
22442 | NEON vector types in order to conform to the AAPCS (see "Procedure | |
22443 | Call Standard for the ARM Architecture", Appendix A). To qualify | |
22444 | for emission with the mangled names defined in that document, a | |
22445 | vector type must not only be of the correct mode but also be | |
22446 | composed of NEON vector element types (e.g. __builtin_neon_qi). */ | |
22447 | typedef struct | |
22448 | { | |
22449 | enum machine_mode mode; | |
22450 | const char *element_type_name; | |
22451 | const char *aapcs_name; | |
22452 | } arm_mangle_map_entry; | |
22453 | ||
22454 | static arm_mangle_map_entry arm_mangle_map[] = { | |
22455 | /* 64-bit containerized types. */ | |
22456 | { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" }, | |
22457 | { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, | |
22458 | { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, | |
22459 | { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, | |
22460 | { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, | |
22461 | { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, | |
22462 | { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, | |
22463 | { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" }, | |
22464 | { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" }, | |
22465 | /* 128-bit containerized types. */ | |
22466 | { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" }, | |
22467 | { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" }, | |
22468 | { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" }, | |
22469 | { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" }, | |
22470 | { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" }, | |
22471 | { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" }, | |
22472 | { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" }, | |
22473 | { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" }, | |
22474 | { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" }, | |
22475 | { VOIDmode, NULL, NULL } | |
22476 | }; | |
22477 | ||
22478 | const char * | |
3101faab | 22479 | arm_mangle_type (const_tree type) |
608063c3 JB |
22480 | { |
22481 | arm_mangle_map_entry *pos = arm_mangle_map; | |
22482 | ||
07d8efe3 MM |
22483 | /* The ARM ABI documents (10th October 2008) say that "__va_list" |
22484 | has to be managled as if it is in the "std" namespace. */ | |
22485 | if (TARGET_AAPCS_BASED | |
ae46a823 | 22486 | && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) |
07d8efe3 MM |
22487 | { |
22488 | static bool warned; | |
d147cbd9 | 22489 | if (!warned && warn_psabi && !in_system_header) |
07d8efe3 MM |
22490 | { |
22491 | warned = true; | |
22492 | inform (input_location, | |
22493 | "the mangling of %<va_list%> has changed in GCC 4.4"); | |
22494 | } | |
22495 | return "St9__va_list"; | |
22496 | } | |
22497 | ||
0fd8c3ad SL |
22498 | /* Half-precision float. */ |
22499 | if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16) | |
22500 | return "Dh"; | |
22501 | ||
608063c3 JB |
22502 | if (TREE_CODE (type) != VECTOR_TYPE) |
22503 | return NULL; | |
22504 | ||
22505 | /* Check the mode of the vector type, and the name of the vector | |
22506 | element type, against the table. */ | |
22507 | while (pos->mode != VOIDmode) | |
22508 | { | |
22509 | tree elt_type = TREE_TYPE (type); | |
22510 | ||
22511 | if (pos->mode == TYPE_MODE (type) | |
22512 | && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL | |
22513 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), | |
22514 | pos->element_type_name)) | |
22515 | return pos->aapcs_name; | |
22516 | ||
22517 | pos++; | |
22518 | } | |
22519 | ||
22520 | /* Use the default mangling for unrecognized (possibly user-defined) | |
22521 | vector types. */ | |
22522 | return NULL; | |
22523 | } | |
22524 | ||
795dc4fc PB |
22525 | /* Order of allocation of core registers for Thumb: this allocation is |
22526 | written over the corresponding initial entries of the array | |
22527 | initialized with REG_ALLOC_ORDER. We allocate all low registers | |
22528 | first. Saving and restoring a low register is usually cheaper than | |
22529 | using a call-clobbered high register. */ | |
22530 | ||
22531 | static const int thumb_core_reg_alloc_order[] = | |
22532 | { | |
22533 | 3, 2, 1, 0, 4, 5, 6, 7, | |
22534 | 14, 12, 8, 9, 10, 11, 13, 15 | |
22535 | }; | |
22536 | ||
22537 | /* Adjust register allocation order when compiling for Thumb. */ | |
22538 | ||
22539 | void | |
22540 | arm_order_regs_for_local_alloc (void) | |
22541 | { | |
22542 | const int arm_reg_alloc_order[] = REG_ALLOC_ORDER; | |
22543 | memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order)); | |
22544 | if (TARGET_THUMB) | |
22545 | memcpy (reg_alloc_order, thumb_core_reg_alloc_order, | |
22546 | sizeof (thumb_core_reg_alloc_order)); | |
22547 | } | |
22548 | ||
f67358da PB |
22549 | /* Set default optimization options. */ |
22550 | void | |
22551 | arm_optimization_options (int level, int size ATTRIBUTE_UNUSED) | |
22552 | { | |
b1bdaf40 ST |
22553 | /* Enable section anchors by default at -O1 or higher. |
22554 | Use 2 to distinguish from an explicit -fsection-anchors | |
22555 | given on the command line. */ | |
22556 | if (level > 0) | |
22557 | flag_section_anchors = 2; | |
f67358da PB |
22558 | } |
22559 | ||
b52b1749 AS |
22560 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
22561 | ||
22562 | bool | |
22563 | arm_frame_pointer_required (void) | |
22564 | { | |
22565 | return (cfun->has_nonlocal_label | |
22566 | || SUBTARGET_FRAME_POINTER_REQUIRED | |
22567 | || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())); | |
22568 | } | |
22569 | ||
2929029c WG |
22570 | /* Only thumb1 can't support conditional execution, so return true if |
22571 | the target is not thumb1. */ | |
22572 | static bool | |
22573 | arm_have_conditional_execution (void) | |
22574 | { | |
22575 | return !TARGET_THUMB1; | |
22576 | } | |
22577 | ||
d3585b76 | 22578 | #include "gt-arm.h" |