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b36ba79f | 1 | /* Output routines for GCC for ARM. |
b0888988 | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
2398fb2a | 3 | Free Software Foundation, Inc. |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e CH |
7 | |
8 | This file is part of GNU CC. | |
9 | ||
10 | GNU CC is free software; you can redistribute it and/or modify | |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 2, or (at your option) | |
13 | any later version. | |
14 | ||
15 | GNU CC is distributed in the hope that it will be useful, | |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with GNU CC; see the file COPYING. If not, write to | |
8fb289e7 RK |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, |
23 | Boston, MA 02111-1307, USA. */ | |
ff9940b0 | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
cce8749e | 27 | #include "rtl.h" |
d5b7b3ae | 28 | #include "tree.h" |
c7319d87 | 29 | #include "obstack.h" |
cce8749e CH |
30 | #include "regs.h" |
31 | #include "hard-reg-set.h" | |
32 | #include "real.h" | |
33 | #include "insn-config.h" | |
34 | #include "conditions.h" | |
cce8749e CH |
35 | #include "output.h" |
36 | #include "insn-attr.h" | |
37 | #include "flags.h" | |
af48348a | 38 | #include "reload.h" |
49ad7cfa | 39 | #include "function.h" |
bee06f3d | 40 | #include "expr.h" |
ad076f4e | 41 | #include "toplev.h" |
aec3cfba | 42 | #include "recog.h" |
92a432f4 | 43 | #include "ggc.h" |
d5b7b3ae | 44 | #include "except.h" |
8b97c5f8 | 45 | #include "c-pragma.h" |
7b8b8ade | 46 | #include "integrate.h" |
c27ba912 | 47 | #include "tm_p.h" |
672a6f42 NB |
48 | #include "target.h" |
49 | #include "target-def.h" | |
cce8749e | 50 | |
d5b7b3ae RE |
51 | /* Forward definitions of types. */ |
52 | typedef struct minipool_node Mnode; | |
53 | typedef struct minipool_fixup Mfix; | |
54 | ||
55 | /* In order to improve the layout of the prototypes below | |
56 | some short type abbreviations are defined here. */ | |
57 | #define Hint HOST_WIDE_INT | |
58 | #define Mmode enum machine_mode | |
59 | #define Ulong unsigned long | |
6d3d9133 | 60 | #define Ccstar const char * |
d5b7b3ae RE |
61 | |
62 | /* Forward function declarations. */ | |
63 | static void arm_add_gc_roots PARAMS ((void)); | |
64 | static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int)); | |
d5b7b3ae RE |
65 | static Ulong bit_count PARAMS ((signed int)); |
66 | static int const_ok_for_op PARAMS ((Hint, enum rtx_code)); | |
67 | static int eliminate_lr2ip PARAMS ((rtx *)); | |
68 | static rtx emit_multi_reg_push PARAMS ((int)); | |
69 | static rtx emit_sfm PARAMS ((int, int)); | |
6d3d9133 | 70 | static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *)); |
d5b7b3ae RE |
71 | static arm_cc get_arm_condition_code PARAMS ((rtx)); |
72 | static void init_fpa_table PARAMS ((void)); | |
73 | static Hint int_log2 PARAMS ((Hint)); | |
74 | static rtx is_jump_table PARAMS ((rtx)); | |
6d3d9133 NC |
75 | static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint)); |
76 | static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int)); | |
d5b7b3ae | 77 | static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint)); |
6d3d9133 | 78 | static Ccstar shift_op PARAMS ((rtx, Hint *)); |
d5b7b3ae RE |
79 | static void arm_init_machine_status PARAMS ((struct function *)); |
80 | static void arm_mark_machine_status PARAMS ((struct function *)); | |
f7a80099 | 81 | static void arm_free_machine_status PARAMS ((struct function *)); |
d5b7b3ae RE |
82 | static int number_of_first_bit_set PARAMS ((int)); |
83 | static void replace_symbols_in_block PARAMS ((tree, rtx, rtx)); | |
84 | static void thumb_exit PARAMS ((FILE *, int, rtx)); | |
85 | static void thumb_pushpop PARAMS ((FILE *, int, int)); | |
6d3d9133 | 86 | static Ccstar thumb_condition_code PARAMS ((rtx, int)); |
d5b7b3ae RE |
87 | static rtx is_jump_table PARAMS ((rtx)); |
88 | static Hint get_jump_table_size PARAMS ((rtx)); | |
89 | static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint)); | |
90 | static Mnode * add_minipool_forward_ref PARAMS ((Mfix *)); | |
91 | static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint)); | |
92 | static Mnode * add_minipool_backward_ref PARAMS ((Mfix *)); | |
93 | static void assign_minipool_offsets PARAMS ((Mfix *)); | |
94 | static void arm_print_value PARAMS ((FILE *, rtx)); | |
95 | static void dump_minipool PARAMS ((rtx)); | |
96 | static int arm_barrier_cost PARAMS ((rtx)); | |
97 | static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint)); | |
98 | static void push_minipool_barrier PARAMS ((rtx, Hint)); | |
99 | static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx)); | |
100 | static void note_invalid_constants PARAMS ((rtx, Hint)); | |
87e27392 | 101 | static int current_file_function_operand PARAMS ((rtx)); |
6d3d9133 NC |
102 | static Ulong arm_compute_save_reg_mask PARAMS ((void)); |
103 | static Ulong arm_isr_value PARAMS ((tree)); | |
104 | static Ulong arm_compute_func_type PARAMS ((void)); | |
672a6f42 NB |
105 | static int arm_valid_type_attribute_p PARAMS ((tree, tree, |
106 | tree, tree)); | |
107 | static int arm_valid_decl_attribute_p PARAMS ((tree, tree, | |
108 | tree, tree)); | |
8d8e52be JM |
109 | static int arm_comp_type_attributes PARAMS ((tree, tree)); |
110 | static void arm_set_default_type_attributes PARAMS ((tree)); | |
d5b7b3ae RE |
111 | #undef Hint |
112 | #undef Mmode | |
113 | #undef Ulong | |
6d3d9133 | 114 | #undef Ccstar |
672a6f42 NB |
115 | \f |
116 | /* Initialize the GCC target structure. */ | |
117 | #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
118 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
119 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes | |
120 | #endif | |
f3bb6135 | 121 | |
672a6f42 NB |
122 | #undef TARGET_VALID_TYPE_ATTRIBUTE |
123 | #define TARGET_VALID_TYPE_ATTRIBUTE arm_valid_type_attribute_p | |
124 | ||
125 | #undef TARGET_VALID_DECL_ATTRIBUTE | |
126 | #ifdef ARM_PE | |
127 | static int arm_pe_valid_decl_attribute_p PARAMS ((tree, tree, tree, tree)); | |
128 | # define TARGET_VALID_DECL_ATTRIBUTE arm_pe_valid_decl_attribute_p | |
129 | #else | |
130 | # define TARGET_VALID_DECL_ATTRIBUTE arm_valid_decl_attribute_p | |
131 | #endif | |
132 | ||
8d8e52be JM |
133 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
134 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes | |
135 | ||
136 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES | |
137 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes | |
138 | ||
672a6f42 NB |
139 | struct gcc_target target = TARGET_INITIALIZER; |
140 | \f | |
c7319d87 RE |
141 | /* Obstack for minipool constant handling. */ |
142 | static struct obstack minipool_obstack; | |
143 | static char *minipool_startobj; | |
144 | ||
145 | #define obstack_chunk_alloc xmalloc | |
146 | #define obstack_chunk_free free | |
147 | ||
c27ba912 DM |
148 | /* The maximum number of insns skipped which will be conditionalised if |
149 | possible. */ | |
150 | static int max_insns_skipped = 5; | |
151 | ||
152 | extern FILE * asm_out_file; | |
153 | ||
6354dc9b | 154 | /* True if we are currently building a constant table. */ |
13bd191d PB |
155 | int making_const_table; |
156 | ||
60d0536b | 157 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 158 | stored from the compare operation. */ |
ff9940b0 | 159 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 160 | |
6354dc9b | 161 | /* What type of floating point are we tuning for? */ |
bee06f3d RE |
162 | enum floating_point_type arm_fpu; |
163 | ||
6354dc9b | 164 | /* What type of floating point instructions are available? */ |
b111229a RE |
165 | enum floating_point_type arm_fpu_arch; |
166 | ||
6354dc9b | 167 | /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ |
2b835d68 RE |
168 | enum prog_mode_type arm_prgmode; |
169 | ||
6354dc9b | 170 | /* Set by the -mfp=... option. */ |
f9cc092a | 171 | const char * target_fp_name = NULL; |
2b835d68 | 172 | |
b355a481 | 173 | /* Used to parse -mstructure_size_boundary command line option. */ |
f9cc092a | 174 | const char * structure_size_string = NULL; |
723ae7c1 | 175 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 176 | |
aec3cfba | 177 | /* Bit values used to identify processor capabilities. */ |
62b10bbc NC |
178 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
179 | #define FL_FAST_MULT (1 << 1) /* Fast multiply */ | |
180 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ | |
181 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
182 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
183 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
184 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
185 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
186 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
b15bca31 | 187 | #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */ |
d19fb8e3 | 188 | #define FL_XSCALE (1 << 10) /* XScale */ |
aec3cfba | 189 | |
d5b7b3ae RE |
190 | /* The bits in this mask specify which instructions we are |
191 | allowed to generate. */ | |
aec3cfba | 192 | static int insn_flags = 0; |
d5b7b3ae | 193 | |
aec3cfba NC |
194 | /* The bits in this mask specify which instruction scheduling options should |
195 | be used. Note - there is an overlap with the FL_FAST_MULT. For some | |
196 | hardware we want to be able to generate the multiply instructions, but to | |
197 | tune as if they were not present in the architecture. */ | |
198 | static int tune_flags = 0; | |
199 | ||
200 | /* The following are used in the arm.md file as equivalents to bits | |
201 | in the above two flag variables. */ | |
202 | ||
2b835d68 RE |
203 | /* Nonzero if this is an "M" variant of the processor. */ |
204 | int arm_fast_multiply = 0; | |
205 | ||
6354dc9b | 206 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
207 | int arm_arch4 = 0; |
208 | ||
6354dc9b | 209 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
210 | int arm_arch5 = 0; |
211 | ||
b15bca31 RE |
212 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
213 | int arm_arch5e = 0; | |
214 | ||
aec3cfba | 215 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
216 | int arm_ld_sched = 0; |
217 | ||
218 | /* Nonzero if this chip is a StrongARM. */ | |
219 | int arm_is_strong = 0; | |
220 | ||
d19fb8e3 NC |
221 | /* Nonzero if this chip is an XScale. */ |
222 | int arm_is_xscale = 0; | |
223 | ||
f5a1b0d2 NC |
224 | /* Nonzero if this chip is a an ARM6 or an ARM7. */ |
225 | int arm_is_6_or_7 = 0; | |
b111229a | 226 | |
0616531f RE |
227 | /* Nonzero if generating Thumb instructions. */ |
228 | int thumb_code = 0; | |
229 | ||
cce8749e CH |
230 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
231 | must report the mode of the memory reference from PRINT_OPERAND to | |
232 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 233 | enum machine_mode output_memory_reference_mode; |
cce8749e CH |
234 | |
235 | /* Nonzero if the prologue must setup `fp'. */ | |
236 | int current_function_anonymous_args; | |
237 | ||
32de079a | 238 | /* The register number to be used for the PIC offset register. */ |
ed0e6530 | 239 | const char * arm_pic_register_string = NULL; |
32de079a RE |
240 | int arm_pic_register = 9; |
241 | ||
ff9940b0 | 242 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 243 | is not needed. */ |
d5b7b3ae | 244 | int return_used_this_function; |
ff9940b0 | 245 | |
aec3cfba NC |
246 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
247 | the next function. */ | |
4b632bf1 RE |
248 | static int after_arm_reorg = 0; |
249 | ||
aec3cfba | 250 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
251 | static int arm_constant_limit = 3; |
252 | ||
cce8749e CH |
253 | /* For an explanation of these variables, see final_prescan_insn below. */ |
254 | int arm_ccfsm_state; | |
84ed5e79 | 255 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
256 | rtx arm_target_insn; |
257 | int arm_target_label; | |
9997d19d RE |
258 | |
259 | /* The condition codes of the ARM, and the inverse function. */ | |
cd2b33d0 | 260 | const char * arm_condition_codes[] = |
9997d19d RE |
261 | { |
262 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
263 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
264 | }; | |
265 | ||
f5a1b0d2 | 266 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
2b835d68 | 267 | \f |
6354dc9b | 268 | /* Initialization code. */ |
2b835d68 | 269 | |
2b835d68 RE |
270 | struct processors |
271 | { | |
cd2b33d0 | 272 | const char * name; |
2b835d68 RE |
273 | unsigned int flags; |
274 | }; | |
275 | ||
276 | /* Not all of these give usefully different compilation alternatives, | |
277 | but there is no simple way of generalizing them. */ | |
f5a1b0d2 NC |
278 | static struct processors all_cores[] = |
279 | { | |
280 | /* ARM Cores */ | |
281 | ||
282 | {"arm2", FL_CO_PROC | FL_MODE26 }, | |
283 | {"arm250", FL_CO_PROC | FL_MODE26 }, | |
284 | {"arm3", FL_CO_PROC | FL_MODE26 }, | |
285 | {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
286 | {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
287 | {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
288 | {"arm610", FL_MODE26 | FL_MODE32 }, | |
289 | {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
949d79eb RE |
290 | {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, |
291 | /* arm7m doesn't exist on its own, but only with D, (and I), but | |
d5b7b3ae | 292 | those don't alter the code, so arm7m is sometimes used. */ |
949d79eb RE |
293 | {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
294 | {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
295 | {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
296 | {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
f5a1b0d2 NC |
297 | {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, |
298 | {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
299 | {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
300 | {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
301 | {"arm710", FL_MODE26 | FL_MODE32 }, | |
eab4abeb | 302 | {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
a120a3bd | 303 | {"arm720", FL_MODE26 | FL_MODE32 }, |
eab4abeb NC |
304 | {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB }, |
305 | {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB }, | |
f5a1b0d2 NC |
306 | {"arm710c", FL_MODE26 | FL_MODE32 }, |
307 | {"arm7100", FL_MODE26 | FL_MODE32 }, | |
308 | {"arm7500", FL_MODE26 | FL_MODE32 }, | |
949d79eb RE |
309 | /* Doesn't have an external co-proc, but does have embedded fpu. */ |
310 | {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
f5a1b0d2 NC |
311 | {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
312 | {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
313 | {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, | |
314 | {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
6cf32035 NC |
315 | {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
316 | {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, | |
eab4abeb | 317 | {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
f5a1b0d2 | 318 | {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, |
eab4abeb | 319 | {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, |
f5a1b0d2 NC |
320 | {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
321 | {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
322 | {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, | |
eab4abeb NC |
323 | {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, |
324 | {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
325 | {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, | |
326 | {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, | |
f5a1b0d2 NC |
327 | |
328 | {NULL, 0} | |
329 | }; | |
330 | ||
331 | static struct processors all_architectures[] = | |
2b835d68 | 332 | { |
f5a1b0d2 NC |
333 | /* ARM Architectures */ |
334 | ||
62b10bbc NC |
335 | { "armv2", FL_CO_PROC | FL_MODE26 }, |
336 | { "armv2a", FL_CO_PROC | FL_MODE26 }, | |
337 | { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, | |
338 | { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, | |
949d79eb | 339 | { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, |
b111229a RE |
340 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
341 | implementations that support it, so we will leave it out for now. */ | |
62b10bbc NC |
342 | { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, |
343 | { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, | |
d19fb8e3 NC |
344 | { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, |
345 | { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, | |
62b10bbc | 346 | { NULL, 0 } |
f5a1b0d2 NC |
347 | }; |
348 | ||
349 | /* This is a magic stucture. The 'string' field is magically filled in | |
350 | with a pointer to the value specified by the user on the command line | |
351 | assuming that the user has specified such a value. */ | |
352 | ||
353 | struct arm_cpu_select arm_select[] = | |
354 | { | |
355 | /* string name processors */ | |
356 | { NULL, "-mcpu=", all_cores }, | |
357 | { NULL, "-march=", all_architectures }, | |
358 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
359 | }; |
360 | ||
aec3cfba | 361 | /* Return the number of bits set in value' */ |
d5b7b3ae | 362 | static unsigned long |
aec3cfba NC |
363 | bit_count (value) |
364 | signed int value; | |
365 | { | |
d5b7b3ae | 366 | unsigned long count = 0; |
aec3cfba NC |
367 | |
368 | while (value) | |
369 | { | |
5895f793 RE |
370 | value &= ~(value & -value); |
371 | ++count; | |
aec3cfba NC |
372 | } |
373 | ||
374 | return count; | |
375 | } | |
376 | ||
2b835d68 RE |
377 | /* Fix up any incompatible options that the user has specified. |
378 | This has now turned into a maze. */ | |
379 | void | |
380 | arm_override_options () | |
381 | { | |
ed4c4348 | 382 | unsigned i; |
f5a1b0d2 NC |
383 | |
384 | /* Set up the flags based on the cpu/architecture selected by the user. */ | |
b6a1cbae | 385 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 386 | { |
f5a1b0d2 NC |
387 | struct arm_cpu_select * ptr = arm_select + i; |
388 | ||
389 | if (ptr->string != NULL && ptr->string[0] != '\0') | |
bd9c7e23 | 390 | { |
13bd191d | 391 | const struct processors * sel; |
bd9c7e23 | 392 | |
5895f793 | 393 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 394 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 395 | { |
aec3cfba NC |
396 | if (i == 2) |
397 | tune_flags = sel->flags; | |
398 | else | |
b111229a | 399 | { |
aec3cfba NC |
400 | /* If we have been given an architecture and a processor |
401 | make sure that they are compatible. We only generate | |
402 | a warning though, and we prefer the CPU over the | |
6354dc9b | 403 | architecture. */ |
aec3cfba | 404 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
6cf32035 | 405 | warning ("switch -mcpu=%s conflicts with -march= switch", |
aec3cfba NC |
406 | ptr->string); |
407 | ||
408 | insn_flags = sel->flags; | |
b111229a | 409 | } |
f5a1b0d2 | 410 | |
bd9c7e23 RE |
411 | break; |
412 | } | |
413 | ||
414 | if (sel->name == NULL) | |
415 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
416 | } | |
417 | } | |
aec3cfba | 418 | |
f5a1b0d2 | 419 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 420 | if (insn_flags == 0) |
f5a1b0d2 NC |
421 | { |
422 | struct processors * sel; | |
aec3cfba NC |
423 | unsigned int sought; |
424 | static struct cpu_default | |
425 | { | |
cd2b33d0 NC |
426 | int cpu; |
427 | const char * name; | |
aec3cfba NC |
428 | } |
429 | cpu_defaults[] = | |
430 | { | |
431 | { TARGET_CPU_arm2, "arm2" }, | |
432 | { TARGET_CPU_arm6, "arm6" }, | |
433 | { TARGET_CPU_arm610, "arm610" }, | |
2aa0c933 | 434 | { TARGET_CPU_arm710, "arm710" }, |
aec3cfba NC |
435 | { TARGET_CPU_arm7m, "arm7m" }, |
436 | { TARGET_CPU_arm7500fe, "arm7500fe" }, | |
437 | { TARGET_CPU_arm7tdmi, "arm7tdmi" }, | |
438 | { TARGET_CPU_arm8, "arm8" }, | |
439 | { TARGET_CPU_arm810, "arm810" }, | |
440 | { TARGET_CPU_arm9, "arm9" }, | |
441 | { TARGET_CPU_strongarm, "strongarm" }, | |
d19fb8e3 | 442 | { TARGET_CPU_xscale, "xscale" }, |
aec3cfba NC |
443 | { TARGET_CPU_generic, "arm" }, |
444 | { 0, 0 } | |
445 | }; | |
446 | struct cpu_default * def; | |
447 | ||
448 | /* Find the default. */ | |
5895f793 | 449 | for (def = cpu_defaults; def->name; def++) |
aec3cfba NC |
450 | if (def->cpu == TARGET_CPU_DEFAULT) |
451 | break; | |
452 | ||
453 | /* Make sure we found the default CPU. */ | |
454 | if (def->name == NULL) | |
455 | abort (); | |
456 | ||
457 | /* Find the default CPU's flags. */ | |
5895f793 | 458 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
459 | if (streq (def->name, sel->name)) |
460 | break; | |
461 | ||
462 | if (sel->name == NULL) | |
463 | abort (); | |
464 | ||
465 | insn_flags = sel->flags; | |
466 | ||
467 | /* Now check to see if the user has specified some command line | |
468 | switch that require certain abilities from the cpu. */ | |
469 | sought = 0; | |
f5a1b0d2 | 470 | |
d5b7b3ae | 471 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 472 | { |
aec3cfba NC |
473 | sought |= (FL_THUMB | FL_MODE32); |
474 | ||
475 | /* Force apcs-32 to be used for interworking. */ | |
f5a1b0d2 | 476 | target_flags |= ARM_FLAG_APCS_32; |
aec3cfba | 477 | |
d5b7b3ae | 478 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
479 | interworking. Therefore we force FL_MODE26 to be removed |
480 | from insn_flags here (if it was set), so that the search | |
481 | below will always be able to find a compatible processor. */ | |
5895f793 | 482 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 483 | } |
5895f793 | 484 | else if (!TARGET_APCS_32) |
f5a1b0d2 | 485 | sought |= FL_MODE26; |
d5b7b3ae | 486 | |
aec3cfba | 487 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 488 | { |
aec3cfba NC |
489 | /* Try to locate a CPU type that supports all of the abilities |
490 | of the default CPU, plus the extra abilities requested by | |
491 | the user. */ | |
5895f793 | 492 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 493 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
494 | break; |
495 | ||
496 | if (sel->name == NULL) | |
aec3cfba NC |
497 | { |
498 | unsigned int current_bit_count = 0; | |
499 | struct processors * best_fit = NULL; | |
500 | ||
501 | /* Ideally we would like to issue an error message here | |
502 | saying that it was not possible to find a CPU compatible | |
503 | with the default CPU, but which also supports the command | |
504 | line options specified by the programmer, and so they | |
505 | ought to use the -mcpu=<name> command line option to | |
506 | override the default CPU type. | |
507 | ||
508 | Unfortunately this does not work with multilibing. We | |
509 | need to be able to support multilibs for -mapcs-26 and for | |
510 | -mthumb-interwork and there is no CPU that can support both | |
511 | options. Instead if we cannot find a cpu that has both the | |
512 | characteristics of the default cpu and the given command line | |
513 | options we scan the array again looking for a best match. */ | |
5895f793 | 514 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
515 | if ((sel->flags & sought) == sought) |
516 | { | |
517 | unsigned int count; | |
518 | ||
519 | count = bit_count (sel->flags & insn_flags); | |
520 | ||
521 | if (count >= current_bit_count) | |
522 | { | |
523 | best_fit = sel; | |
524 | current_bit_count = count; | |
525 | } | |
526 | } | |
f5a1b0d2 | 527 | |
aec3cfba NC |
528 | if (best_fit == NULL) |
529 | abort (); | |
530 | else | |
531 | sel = best_fit; | |
532 | } | |
533 | ||
534 | insn_flags = sel->flags; | |
f5a1b0d2 NC |
535 | } |
536 | } | |
aec3cfba NC |
537 | |
538 | /* If tuning has not been specified, tune for whichever processor or | |
539 | architecture has been selected. */ | |
540 | if (tune_flags == 0) | |
541 | tune_flags = insn_flags; | |
542 | ||
f5a1b0d2 NC |
543 | /* Make sure that the processor choice does not conflict with any of the |
544 | other command line choices. */ | |
aec3cfba | 545 | if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) |
f5a1b0d2 | 546 | { |
aec3cfba NC |
547 | /* If APCS-32 was not the default then it must have been set by the |
548 | user, so issue a warning message. If the user has specified | |
549 | "-mapcs-32 -mcpu=arm2" then we loose here. */ | |
550 | if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) | |
551 | warning ("target CPU does not support APCS-32" ); | |
5895f793 | 552 | target_flags &= ~ARM_FLAG_APCS_32; |
f5a1b0d2 | 553 | } |
5895f793 | 554 | else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) |
f5a1b0d2 NC |
555 | { |
556 | warning ("target CPU does not support APCS-26" ); | |
557 | target_flags |= ARM_FLAG_APCS_32; | |
558 | } | |
559 | ||
6cfc7210 | 560 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 NC |
561 | { |
562 | warning ("target CPU does not support interworking" ); | |
6cfc7210 | 563 | target_flags &= ~ARM_FLAG_INTERWORK; |
f5a1b0d2 NC |
564 | } |
565 | ||
d5b7b3ae RE |
566 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
567 | { | |
5184f7c5 | 568 | warning ("target CPU does not support THUMB instructions."); |
d5b7b3ae RE |
569 | target_flags &= ~ARM_FLAG_THUMB; |
570 | } | |
571 | ||
572 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
573 | { | |
574 | /* warning ("ignoring -mapcs-frame because -mthumb was used."); */ | |
575 | target_flags &= ~ARM_FLAG_APCS_FRAME; | |
576 | } | |
d19fb8e3 | 577 | |
d5b7b3ae RE |
578 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
579 | from here where no function is being compiled currently. */ | |
580 | if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) | |
581 | && TARGET_ARM) | |
582 | warning ("enabling backtrace support is only meaningful when compiling for the Thumb."); | |
583 | ||
584 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
585 | warning ("enabling callee interworking support is only meaningful when compiling for the Thumb."); | |
586 | ||
587 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
588 | warning ("enabling caller interworking support is only meaningful when compiling for the Thumb."); | |
589 | ||
f5a1b0d2 | 590 | /* If interworking is enabled then APCS-32 must be selected as well. */ |
6cfc7210 | 591 | if (TARGET_INTERWORK) |
f5a1b0d2 | 592 | { |
5895f793 | 593 | if (!TARGET_APCS_32) |
f5a1b0d2 NC |
594 | warning ("interworking forces APCS-32 to be used" ); |
595 | target_flags |= ARM_FLAG_APCS_32; | |
596 | } | |
597 | ||
5895f793 | 598 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 NC |
599 | { |
600 | warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); | |
601 | target_flags |= ARM_FLAG_APCS_FRAME; | |
602 | } | |
aec3cfba | 603 | |
2b835d68 RE |
604 | if (TARGET_POKE_FUNCTION_NAME) |
605 | target_flags |= ARM_FLAG_APCS_FRAME; | |
aec3cfba | 606 | |
2b835d68 | 607 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 608 | error ("-fpic and -mapcs-reent are incompatible"); |
aec3cfba | 609 | |
2b835d68 | 610 | if (TARGET_APCS_REENT) |
f5a1b0d2 | 611 | warning ("APCS reentrant code not supported. Ignored"); |
aec3cfba | 612 | |
d5b7b3ae RE |
613 | /* If this target is normally configured to use APCS frames, warn if they |
614 | are turned off and debugging is turned on. */ | |
615 | if (TARGET_ARM | |
616 | && write_symbols != NO_DEBUG | |
5895f793 | 617 | && !TARGET_APCS_FRAME |
d5b7b3ae RE |
618 | && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) |
619 | warning ("-g with -mno-apcs-frame may not give sensible debugging"); | |
6cfc7210 | 620 | |
32de079a RE |
621 | /* If stack checking is disabled, we can use r10 as the PIC register, |
622 | which keeps r9 available. */ | |
5895f793 | 623 | if (flag_pic && !TARGET_APCS_STACK) |
32de079a | 624 | arm_pic_register = 10; |
aec3cfba | 625 | |
2b835d68 RE |
626 | if (TARGET_APCS_FLOAT) |
627 | warning ("Passing floating point arguments in fp regs not yet supported"); | |
f5a1b0d2 | 628 | |
aec3cfba | 629 | /* Initialise boolean versions of the flags, for use in the arm.md file. */ |
2ca12935 JL |
630 | arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; |
631 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
632 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; | |
b15bca31 | 633 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; |
a67ded0f | 634 | arm_is_xscale = (insn_flags & FL_XSCALE) != 0; |
6f7ebcbb | 635 | |
2ca12935 JL |
636 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; |
637 | arm_is_strong = (tune_flags & FL_STRONG) != 0; | |
0616531f | 638 | thumb_code = (TARGET_ARM == 0); |
d5b7b3ae RE |
639 | arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) |
640 | && !(tune_flags & FL_ARCH4))) != 0; | |
6f7ebcbb | 641 | |
bd9c7e23 RE |
642 | /* Default value for floating point code... if no co-processor |
643 | bus, then schedule for emulated floating point. Otherwise, | |
b111229a RE |
644 | assume the user has an FPA. |
645 | Note: this does not prevent use of floating point instructions, | |
646 | -msoft-float does that. */ | |
aec3cfba | 647 | arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3; |
f5a1b0d2 | 648 | |
b111229a | 649 | if (target_fp_name) |
2b835d68 | 650 | { |
f5a1b0d2 | 651 | if (streq (target_fp_name, "2")) |
b111229a | 652 | arm_fpu_arch = FP_SOFT2; |
f5a1b0d2 NC |
653 | else if (streq (target_fp_name, "3")) |
654 | arm_fpu_arch = FP_SOFT3; | |
2b835d68 | 655 | else |
400500c4 | 656 | error ("Invalid floating point emulation option: -mfpe-%s", |
b111229a | 657 | target_fp_name); |
2b835d68 | 658 | } |
b111229a RE |
659 | else |
660 | arm_fpu_arch = FP_DEFAULT; | |
f5a1b0d2 NC |
661 | |
662 | if (TARGET_FPE && arm_fpu != FP_HARD) | |
663 | arm_fpu = FP_SOFT2; | |
aec3cfba | 664 | |
f5a1b0d2 NC |
665 | /* For arm2/3 there is no need to do any scheduling if there is only |
666 | a floating point emulator, or we are doing software floating-point. */ | |
ed0e6530 PB |
667 | if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) |
668 | && (tune_flags & FL_MODE32) == 0) | |
f5a1b0d2 | 669 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
aec3cfba | 670 | |
cd2b33d0 | 671 | arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; |
b355a481 NC |
672 | |
673 | if (structure_size_string != NULL) | |
674 | { | |
675 | int size = strtol (structure_size_string, NULL, 0); | |
676 | ||
677 | if (size == 8 || size == 32) | |
678 | arm_structure_size_boundary = size; | |
679 | else | |
680 | warning ("Structure size boundary can only be set to 8 or 32"); | |
681 | } | |
ed0e6530 PB |
682 | |
683 | if (arm_pic_register_string != NULL) | |
684 | { | |
685 | int pic_register; | |
686 | ||
5895f793 | 687 | if (!flag_pic) |
ed0e6530 PB |
688 | warning ("-mpic-register= is useless without -fpic"); |
689 | ||
690 | pic_register = decode_reg_name (arm_pic_register_string); | |
691 | ||
692 | /* Prevent the user from choosing an obviously stupid PIC register. */ | |
693 | if (pic_register < 0 || call_used_regs[pic_register] | |
694 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
695 | || pic_register == STACK_POINTER_REGNUM | |
696 | || pic_register >= PC_REGNUM) | |
697 | error ("Unable to use '%s' for PIC register", arm_pic_register_string); | |
698 | else | |
699 | arm_pic_register = pic_register; | |
700 | } | |
d5b7b3ae RE |
701 | |
702 | if (TARGET_THUMB && flag_schedule_insns) | |
703 | { | |
704 | /* Don't warn since it's on by default in -O2. */ | |
705 | flag_schedule_insns = 0; | |
706 | } | |
707 | ||
f5a1b0d2 NC |
708 | /* If optimizing for space, don't synthesize constants. |
709 | For processors with load scheduling, it never costs more than 2 cycles | |
710 | to load a constant, and the load scheduler may well reduce that to 1. */ | |
aec3cfba | 711 | if (optimize_size || (tune_flags & FL_LDSCHED)) |
f5a1b0d2 | 712 | arm_constant_limit = 1; |
aec3cfba | 713 | |
d19fb8e3 NC |
714 | if (arm_is_xscale) |
715 | arm_constant_limit = 2; | |
716 | ||
f5a1b0d2 NC |
717 | /* If optimizing for size, bump the number of instructions that we |
718 | are prepared to conditionally execute (even on a StrongARM). | |
719 | Otherwise for the StrongARM, which has early execution of branches, | |
720 | a sequence that is worth skipping is shorter. */ | |
721 | if (optimize_size) | |
722 | max_insns_skipped = 6; | |
723 | else if (arm_is_strong) | |
724 | max_insns_skipped = 3; | |
92a432f4 RE |
725 | |
726 | /* Register global variables with the garbage collector. */ | |
727 | arm_add_gc_roots (); | |
728 | } | |
729 | ||
730 | static void | |
731 | arm_add_gc_roots () | |
732 | { | |
733 | ggc_add_rtx_root (&arm_compare_op0, 1); | |
734 | ggc_add_rtx_root (&arm_compare_op1, 1); | |
6d3d9133 | 735 | ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */ |
c7319d87 RE |
736 | |
737 | gcc_obstack_init(&minipool_obstack); | |
738 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 739 | } |
cce8749e | 740 | \f |
6d3d9133 NC |
741 | /* A table of known ARM exception types. |
742 | For use with the interrupt function attribute. */ | |
743 | ||
744 | typedef struct | |
745 | { | |
746 | const char * arg; | |
747 | unsigned long return_value; | |
748 | } | |
749 | isr_attribute_arg; | |
750 | ||
751 | static isr_attribute_arg isr_attribute_args [] = | |
752 | { | |
753 | { "IRQ", ARM_FT_ISR }, | |
754 | { "irq", ARM_FT_ISR }, | |
755 | { "FIQ", ARM_FT_FIQ }, | |
756 | { "fiq", ARM_FT_FIQ }, | |
757 | { "ABORT", ARM_FT_ISR }, | |
758 | { "abort", ARM_FT_ISR }, | |
759 | { "ABORT", ARM_FT_ISR }, | |
760 | { "abort", ARM_FT_ISR }, | |
761 | { "UNDEF", ARM_FT_EXCEPTION }, | |
762 | { "undef", ARM_FT_EXCEPTION }, | |
763 | { "SWI", ARM_FT_EXCEPTION }, | |
764 | { "swi", ARM_FT_EXCEPTION }, | |
765 | { NULL, ARM_FT_NORMAL } | |
766 | }; | |
767 | ||
768 | /* Returns the (interrupt) function type of the current | |
769 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
770 | ||
771 | static unsigned long | |
772 | arm_isr_value (argument) | |
773 | tree argument; | |
774 | { | |
775 | isr_attribute_arg * ptr; | |
776 | const char * arg; | |
777 | ||
778 | /* No argument - default to IRQ. */ | |
779 | if (argument == NULL_TREE) | |
780 | return ARM_FT_ISR; | |
781 | ||
782 | /* Get the value of the argument. */ | |
783 | if (TREE_VALUE (argument) == NULL_TREE | |
784 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
785 | return ARM_FT_UNKNOWN; | |
786 | ||
787 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
788 | ||
789 | /* Check it against the list of known arguments. */ | |
790 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++) | |
791 | if (strcmp (arg, ptr->arg) == 0) | |
792 | return ptr->return_value; | |
793 | ||
794 | /* An unrecognised interrupt type. */ | |
795 | return ARM_FT_UNKNOWN; | |
796 | } | |
797 | ||
798 | /* Computes the type of the current function. */ | |
799 | ||
800 | static unsigned long | |
801 | arm_compute_func_type () | |
802 | { | |
803 | unsigned long type = ARM_FT_UNKNOWN; | |
804 | tree a; | |
805 | tree attr; | |
806 | ||
807 | if (TREE_CODE (current_function_decl) != FUNCTION_DECL) | |
808 | abort (); | |
809 | ||
810 | /* Decide if the current function is volatile. Such functions | |
811 | never return, and many memory cycles can be saved by not storing | |
812 | register values that will never be needed again. This optimization | |
813 | was added to speed up context switching in a kernel application. */ | |
814 | if (optimize > 0 | |
815 | && current_function_nothrow | |
816 | && TREE_THIS_VOLATILE (current_function_decl)) | |
817 | type |= ARM_FT_VOLATILE; | |
818 | ||
819 | if (current_function_needs_context) | |
820 | type |= ARM_FT_NESTED; | |
821 | ||
822 | attr = DECL_MACHINE_ATTRIBUTES (current_function_decl); | |
823 | ||
824 | a = lookup_attribute ("naked", attr); | |
825 | if (a != NULL_TREE) | |
826 | type |= ARM_FT_NAKED; | |
827 | ||
828 | if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) | |
829 | type |= ARM_FT_EXCEPTION_HANDLER; | |
830 | else | |
831 | { | |
832 | a = lookup_attribute ("isr", attr); | |
833 | if (a == NULL_TREE) | |
834 | a = lookup_attribute ("interrupt", attr); | |
835 | ||
836 | if (a == NULL_TREE) | |
837 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
838 | else | |
839 | type |= arm_isr_value (TREE_VALUE (a)); | |
840 | } | |
841 | ||
842 | return type; | |
843 | } | |
844 | ||
845 | /* Returns the type of the current function. */ | |
846 | ||
847 | unsigned long | |
848 | arm_current_func_type () | |
849 | { | |
850 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
851 | cfun->machine->func_type = arm_compute_func_type (); | |
852 | ||
853 | return cfun->machine->func_type; | |
854 | } | |
855 | \f | |
6354dc9b | 856 | /* Return 1 if it is possible to return using a single instruction. */ |
6d3d9133 | 857 | |
ff9940b0 | 858 | int |
b36ba79f RE |
859 | use_return_insn (iscond) |
860 | int iscond; | |
ff9940b0 RE |
861 | { |
862 | int regno; | |
9b598fa0 | 863 | unsigned int func_type; |
ff9940b0 | 864 | |
d5b7b3ae | 865 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
866 | if (!reload_completed) |
867 | return 0; | |
868 | ||
9b598fa0 RE |
869 | func_type = arm_current_func_type (); |
870 | ||
6d3d9133 NC |
871 | /* Naked functions, volatile functiond and interrupt |
872 | functions all need special consideration. */ | |
873 | if (func_type & (ARM_FT_INTERRUPT | ARM_FT_VOLATILE | ARM_FT_NAKED)) | |
874 | return 0; | |
875 | ||
876 | /* As do variadic functions. */ | |
877 | if (current_function_pretend_args_size | |
ff9940b0 | 878 | || current_function_anonymous_args |
d5b7b3ae | 879 | /* Of if the function calls __builtin_eh_return () */ |
6d3d9133 | 880 | || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
d5b7b3ae | 881 | /* Or if there is no frame pointer and there is a stack adjustment. */ |
56636818 | 882 | || ((get_frame_size () + current_function_outgoing_args_size != 0) |
5895f793 | 883 | && !frame_pointer_needed)) |
ff9940b0 RE |
884 | return 0; |
885 | ||
b111229a | 886 | /* Can't be done if interworking with Thumb, and any registers have been |
b36ba79f RE |
887 | stacked. Similarly, on StrongARM, conditional returns are expensive |
888 | if they aren't taken and registers have been stacked. */ | |
f5a1b0d2 | 889 | if (iscond && arm_is_strong && frame_pointer_needed) |
b36ba79f | 890 | return 0; |
d5b7b3ae | 891 | |
f5a1b0d2 | 892 | if ((iscond && arm_is_strong) |
6cfc7210 | 893 | || TARGET_INTERWORK) |
6ed30148 | 894 | { |
d5b7b3ae | 895 | for (regno = 0; regno <= LAST_ARM_REGNUM; regno++) |
5895f793 | 896 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
6ed30148 RE |
897 | return 0; |
898 | ||
899 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
b111229a | 900 | return 0; |
6ed30148 | 901 | } |
b111229a | 902 | |
6d3d9133 NC |
903 | /* Can't be done if any of the FPU regs are pushed, |
904 | since this also requires an insn. */ | |
d5b7b3ae RE |
905 | if (TARGET_HARD_FLOAT) |
906 | for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) | |
5895f793 | 907 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
d5b7b3ae | 908 | return 0; |
ff9940b0 RE |
909 | |
910 | return 1; | |
911 | } | |
912 | ||
cce8749e CH |
913 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
914 | ||
915 | int | |
916 | const_ok_for_arm (i) | |
ff9940b0 | 917 | HOST_WIDE_INT i; |
cce8749e | 918 | { |
5895f793 | 919 | unsigned HOST_WIDE_INT mask = ~HOST_UINT (0xFF); |
cce8749e | 920 | |
56636818 JL |
921 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
922 | be all zero, or all one. */ | |
5895f793 RE |
923 | if ((i & ~HOST_UINT (0xffffffff)) != 0 |
924 | && ((i & ~HOST_UINT (0xffffffff)) | |
925 | != ((~HOST_UINT (0)) | |
926 | & ~HOST_UINT (0xffffffff)))) | |
56636818 JL |
927 | return FALSE; |
928 | ||
e2c671ba RE |
929 | /* Fast return for 0 and powers of 2 */ |
930 | if ((i & (i - 1)) == 0) | |
931 | return TRUE; | |
932 | ||
cce8749e CH |
933 | do |
934 | { | |
e5951263 | 935 | if ((i & mask & HOST_UINT (0xffffffff)) == 0) |
f3bb6135 | 936 | return TRUE; |
abaa26e5 | 937 | mask = |
e5951263 NC |
938 | (mask << 2) | ((mask & HOST_UINT (0xffffffff)) |
939 | >> (32 - 2)) | ~(HOST_UINT (0xffffffff)); | |
5895f793 | 940 | } while (mask != ~HOST_UINT (0xFF)); |
cce8749e | 941 | |
f3bb6135 RE |
942 | return FALSE; |
943 | } | |
cce8749e | 944 | |
6354dc9b | 945 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 NC |
946 | static int |
947 | const_ok_for_op (i, code) | |
e2c671ba RE |
948 | HOST_WIDE_INT i; |
949 | enum rtx_code code; | |
e2c671ba RE |
950 | { |
951 | if (const_ok_for_arm (i)) | |
952 | return 1; | |
953 | ||
954 | switch (code) | |
955 | { | |
956 | case PLUS: | |
957 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
958 | ||
959 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
960 | case XOR: | |
961 | case IOR: | |
962 | return 0; | |
963 | ||
964 | case AND: | |
965 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
966 | ||
967 | default: | |
968 | abort (); | |
969 | } | |
970 | } | |
971 | ||
972 | /* Emit a sequence of insns to handle a large constant. | |
973 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
974 | IOR, AND, XOR, MINUS; | |
975 | MODE is the mode in which the operation is being performed; | |
976 | VAL is the integer to operate on; | |
977 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
978 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
979 | either produce a simpler sequence, or we will want to cse the values. |
980 | Return value is the number of insns emitted. */ | |
e2c671ba RE |
981 | |
982 | int | |
983 | arm_split_constant (code, mode, val, target, source, subtargets) | |
984 | enum rtx_code code; | |
985 | enum machine_mode mode; | |
986 | HOST_WIDE_INT val; | |
987 | rtx target; | |
988 | rtx source; | |
989 | int subtargets; | |
2b835d68 RE |
990 | { |
991 | if (subtargets || code == SET | |
992 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
993 | && REGNO (target) != REGNO (source))) | |
994 | { | |
4b632bf1 RE |
995 | /* After arm_reorg has been called, we can't fix up expensive |
996 | constants by pushing them into memory so we must synthesise | |
997 | them in-line, regardless of the cost. This is only likely to | |
998 | be more costly on chips that have load delay slots and we are | |
999 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1000 | occurred before the final instruction emission). |
1001 | ||
1002 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1003 | */ |
5895f793 | 1004 | if (!after_arm_reorg |
4b632bf1 RE |
1005 | && (arm_gen_constant (code, mode, val, target, source, 1, 0) |
1006 | > arm_constant_limit + (code != SET))) | |
2b835d68 RE |
1007 | { |
1008 | if (code == SET) | |
1009 | { | |
1010 | /* Currently SET is the only monadic value for CODE, all | |
1011 | the rest are diadic. */ | |
43cffd11 | 1012 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); |
2b835d68 RE |
1013 | return 1; |
1014 | } | |
1015 | else | |
1016 | { | |
1017 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1018 | ||
43cffd11 | 1019 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); |
2b835d68 RE |
1020 | /* For MINUS, the value is subtracted from, since we never |
1021 | have subtraction of a constant. */ | |
1022 | if (code == MINUS) | |
43cffd11 | 1023 | emit_insn (gen_rtx_SET (VOIDmode, target, |
d5b7b3ae | 1024 | gen_rtx_MINUS (mode, temp, source))); |
2b835d68 | 1025 | else |
43cffd11 RE |
1026 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1027 | gen_rtx (code, mode, source, temp))); | |
2b835d68 RE |
1028 | return 2; |
1029 | } | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | return arm_gen_constant (code, mode, val, target, source, subtargets, 1); | |
1034 | } | |
1035 | ||
ceebdb09 PB |
1036 | static int |
1037 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) | |
1038 | { | |
1039 | HOST_WIDE_INT temp1; | |
1040 | int num_insns = 0; | |
1041 | do | |
1042 | { | |
1043 | int end; | |
1044 | ||
1045 | if (i <= 0) | |
1046 | i += 32; | |
1047 | if (remainder & (3 << (i - 2))) | |
1048 | { | |
1049 | end = i - 8; | |
1050 | if (end < 0) | |
1051 | end += 32; | |
1052 | temp1 = remainder & ((0x0ff << end) | |
1053 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1054 | remainder &= ~temp1; | |
1055 | num_insns++; | |
1056 | i -= 6; | |
1057 | } | |
1058 | i -= 2; | |
1059 | } while (remainder); | |
1060 | return num_insns; | |
1061 | } | |
1062 | ||
2b835d68 RE |
1063 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1064 | RTL generation. */ | |
d5b7b3ae | 1065 | static int |
2b835d68 RE |
1066 | arm_gen_constant (code, mode, val, target, source, subtargets, generate) |
1067 | enum rtx_code code; | |
1068 | enum machine_mode mode; | |
1069 | HOST_WIDE_INT val; | |
1070 | rtx target; | |
1071 | rtx source; | |
1072 | int subtargets; | |
1073 | int generate; | |
e2c671ba | 1074 | { |
e2c671ba RE |
1075 | int can_invert = 0; |
1076 | int can_negate = 0; | |
1077 | int can_negate_initial = 0; | |
1078 | int can_shift = 0; | |
1079 | int i; | |
1080 | int num_bits_set = 0; | |
1081 | int set_sign_bit_copies = 0; | |
1082 | int clear_sign_bit_copies = 0; | |
1083 | int clear_zero_bit_copies = 0; | |
1084 | int set_zero_bit_copies = 0; | |
1085 | int insns = 0; | |
e2c671ba | 1086 | unsigned HOST_WIDE_INT temp1, temp2; |
e5951263 | 1087 | unsigned HOST_WIDE_INT remainder = val & HOST_UINT (0xffffffff); |
e2c671ba | 1088 | |
d5b7b3ae | 1089 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1090 | check for degenerate cases; these can occur when DImode operations |
1091 | are split. */ | |
1092 | switch (code) | |
1093 | { | |
1094 | case SET: | |
1095 | can_invert = 1; | |
1096 | can_shift = 1; | |
1097 | can_negate = 1; | |
1098 | break; | |
1099 | ||
1100 | case PLUS: | |
1101 | can_negate = 1; | |
1102 | can_negate_initial = 1; | |
1103 | break; | |
1104 | ||
1105 | case IOR: | |
e5951263 | 1106 | if (remainder == HOST_UINT (0xffffffff)) |
e2c671ba | 1107 | { |
2b835d68 | 1108 | if (generate) |
43cffd11 RE |
1109 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1110 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
1111 | return 1; |
1112 | } | |
1113 | if (remainder == 0) | |
1114 | { | |
1115 | if (reload_completed && rtx_equal_p (target, source)) | |
1116 | return 0; | |
2b835d68 | 1117 | if (generate) |
43cffd11 | 1118 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1119 | return 1; |
1120 | } | |
1121 | break; | |
1122 | ||
1123 | case AND: | |
1124 | if (remainder == 0) | |
1125 | { | |
2b835d68 | 1126 | if (generate) |
43cffd11 | 1127 | emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); |
e2c671ba RE |
1128 | return 1; |
1129 | } | |
e5951263 | 1130 | if (remainder == HOST_UINT (0xffffffff)) |
e2c671ba RE |
1131 | { |
1132 | if (reload_completed && rtx_equal_p (target, source)) | |
1133 | return 0; | |
2b835d68 | 1134 | if (generate) |
43cffd11 | 1135 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1136 | return 1; |
1137 | } | |
1138 | can_invert = 1; | |
1139 | break; | |
1140 | ||
1141 | case XOR: | |
1142 | if (remainder == 0) | |
1143 | { | |
1144 | if (reload_completed && rtx_equal_p (target, source)) | |
1145 | return 0; | |
2b835d68 | 1146 | if (generate) |
43cffd11 | 1147 | emit_insn (gen_rtx_SET (VOIDmode, target, source)); |
e2c671ba RE |
1148 | return 1; |
1149 | } | |
e5951263 | 1150 | if (remainder == HOST_UINT (0xffffffff)) |
e2c671ba | 1151 | { |
2b835d68 | 1152 | if (generate) |
43cffd11 RE |
1153 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1154 | gen_rtx_NOT (mode, source))); | |
e2c671ba RE |
1155 | return 1; |
1156 | } | |
1157 | ||
1158 | /* We don't know how to handle this yet below. */ | |
1159 | abort (); | |
1160 | ||
1161 | case MINUS: | |
1162 | /* We treat MINUS as (val - source), since (source - val) is always | |
1163 | passed as (source + (-val)). */ | |
1164 | if (remainder == 0) | |
1165 | { | |
2b835d68 | 1166 | if (generate) |
43cffd11 RE |
1167 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1168 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
1169 | return 1; |
1170 | } | |
1171 | if (const_ok_for_arm (val)) | |
1172 | { | |
2b835d68 | 1173 | if (generate) |
43cffd11 RE |
1174 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1175 | gen_rtx_MINUS (mode, GEN_INT (val), | |
1176 | source))); | |
e2c671ba RE |
1177 | return 1; |
1178 | } | |
1179 | can_negate = 1; | |
1180 | ||
1181 | break; | |
1182 | ||
1183 | default: | |
1184 | abort (); | |
1185 | } | |
1186 | ||
6354dc9b | 1187 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
1188 | if (const_ok_for_arm (val) |
1189 | || (can_negate_initial && const_ok_for_arm (-val)) | |
1190 | || (can_invert && const_ok_for_arm (~val))) | |
1191 | { | |
2b835d68 | 1192 | if (generate) |
43cffd11 RE |
1193 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1194 | (source ? gen_rtx (code, mode, source, | |
1195 | GEN_INT (val)) | |
1196 | : GEN_INT (val)))); | |
e2c671ba RE |
1197 | return 1; |
1198 | } | |
1199 | ||
e2c671ba | 1200 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 1201 | optimizations. */ |
e2c671ba RE |
1202 | for (i = 31; i >= 0; i--) |
1203 | { | |
1204 | if ((remainder & (1 << i)) == 0) | |
1205 | clear_sign_bit_copies++; | |
1206 | else | |
1207 | break; | |
1208 | } | |
1209 | ||
1210 | for (i = 31; i >= 0; i--) | |
1211 | { | |
1212 | if ((remainder & (1 << i)) != 0) | |
1213 | set_sign_bit_copies++; | |
1214 | else | |
1215 | break; | |
1216 | } | |
1217 | ||
1218 | for (i = 0; i <= 31; i++) | |
1219 | { | |
1220 | if ((remainder & (1 << i)) == 0) | |
1221 | clear_zero_bit_copies++; | |
1222 | else | |
1223 | break; | |
1224 | } | |
1225 | ||
1226 | for (i = 0; i <= 31; i++) | |
1227 | { | |
1228 | if ((remainder & (1 << i)) != 0) | |
1229 | set_zero_bit_copies++; | |
1230 | else | |
1231 | break; | |
1232 | } | |
1233 | ||
1234 | switch (code) | |
1235 | { | |
1236 | case SET: | |
1237 | /* See if we can do this by sign_extending a constant that is known | |
1238 | to be negative. This is a good, way of doing it, since the shift | |
1239 | may well merge into a subsequent insn. */ | |
1240 | if (set_sign_bit_copies > 1) | |
1241 | { | |
1242 | if (const_ok_for_arm | |
1243 | (temp1 = ARM_SIGN_EXTEND (remainder | |
1244 | << (set_sign_bit_copies - 1)))) | |
1245 | { | |
2b835d68 RE |
1246 | if (generate) |
1247 | { | |
d499463f | 1248 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1249 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1250 | GEN_INT (temp1))); | |
2b835d68 RE |
1251 | emit_insn (gen_ashrsi3 (target, new_src, |
1252 | GEN_INT (set_sign_bit_copies - 1))); | |
1253 | } | |
e2c671ba RE |
1254 | return 2; |
1255 | } | |
1256 | /* For an inverted constant, we will need to set the low bits, | |
1257 | these will be shifted out of harm's way. */ | |
1258 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
1259 | if (const_ok_for_arm (~temp1)) | |
1260 | { | |
2b835d68 RE |
1261 | if (generate) |
1262 | { | |
d499463f | 1263 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
43cffd11 RE |
1264 | emit_insn (gen_rtx_SET (VOIDmode, new_src, |
1265 | GEN_INT (temp1))); | |
2b835d68 RE |
1266 | emit_insn (gen_ashrsi3 (target, new_src, |
1267 | GEN_INT (set_sign_bit_copies - 1))); | |
1268 | } | |
e2c671ba RE |
1269 | return 2; |
1270 | } | |
1271 | } | |
1272 | ||
1273 | /* See if we can generate this by setting the bottom (or the top) | |
1274 | 16 bits, and then shifting these into the other half of the | |
1275 | word. We only look for the simplest cases, to do more would cost | |
1276 | too much. Be careful, however, not to generate this when the | |
1277 | alternative would take fewer insns. */ | |
e5951263 | 1278 | if (val & HOST_UINT (0xffff0000)) |
e2c671ba | 1279 | { |
e5951263 | 1280 | temp1 = remainder & HOST_UINT (0xffff0000); |
e2c671ba RE |
1281 | temp2 = remainder & 0x0000ffff; |
1282 | ||
6354dc9b | 1283 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
1284 | for (i = 9; i < 24; i++) |
1285 | { | |
d5b7b3ae | 1286 | if ((((temp2 | (temp2 << i)) |
e5951263 | 1287 | & HOST_UINT (0xffffffff)) == remainder) |
5895f793 | 1288 | && !const_ok_for_arm (temp2)) |
e2c671ba | 1289 | { |
d499463f RE |
1290 | rtx new_src = (subtargets |
1291 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1292 | : target); | |
1293 | insns = arm_gen_constant (code, mode, temp2, new_src, | |
2b835d68 | 1294 | source, subtargets, generate); |
e2c671ba | 1295 | source = new_src; |
2b835d68 | 1296 | if (generate) |
43cffd11 RE |
1297 | emit_insn (gen_rtx_SET |
1298 | (VOIDmode, target, | |
1299 | gen_rtx_IOR (mode, | |
1300 | gen_rtx_ASHIFT (mode, source, | |
1301 | GEN_INT (i)), | |
1302 | source))); | |
e2c671ba RE |
1303 | return insns + 1; |
1304 | } | |
1305 | } | |
1306 | ||
6354dc9b | 1307 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
1308 | for (i = 17; i < 24; i++) |
1309 | { | |
1310 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 1311 | && !const_ok_for_arm (temp1)) |
e2c671ba | 1312 | { |
d499463f RE |
1313 | rtx new_src = (subtargets |
1314 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1315 | : target); | |
1316 | insns = arm_gen_constant (code, mode, temp1, new_src, | |
2b835d68 | 1317 | source, subtargets, generate); |
e2c671ba | 1318 | source = new_src; |
2b835d68 | 1319 | if (generate) |
43cffd11 RE |
1320 | emit_insn |
1321 | (gen_rtx_SET (VOIDmode, target, | |
1322 | gen_rtx_IOR | |
1323 | (mode, | |
1324 | gen_rtx_LSHIFTRT (mode, source, | |
1325 | GEN_INT (i)), | |
1326 | source))); | |
e2c671ba RE |
1327 | return insns + 1; |
1328 | } | |
1329 | } | |
1330 | } | |
1331 | break; | |
1332 | ||
1333 | case IOR: | |
1334 | case XOR: | |
7b64da89 RE |
1335 | /* If we have IOR or XOR, and the constant can be loaded in a |
1336 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
1337 | then this can be done in two instructions instead of 3-4. */ |
1338 | if (subtargets | |
d499463f | 1339 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 1340 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 1341 | { |
5895f793 | 1342 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1343 | { |
2b835d68 RE |
1344 | if (generate) |
1345 | { | |
1346 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 1347 | |
43cffd11 RE |
1348 | emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); |
1349 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1350 | gen_rtx (code, mode, source, sub))); | |
2b835d68 | 1351 | } |
e2c671ba RE |
1352 | return 2; |
1353 | } | |
1354 | } | |
1355 | ||
1356 | if (code == XOR) | |
1357 | break; | |
1358 | ||
1359 | if (set_sign_bit_copies > 8 | |
1360 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
1361 | { | |
2b835d68 RE |
1362 | if (generate) |
1363 | { | |
1364 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1365 | rtx shift = GEN_INT (set_sign_bit_copies); | |
1366 | ||
43cffd11 RE |
1367 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1368 | gen_rtx_NOT (mode, | |
1369 | gen_rtx_ASHIFT (mode, | |
1370 | source, | |
f5a1b0d2 | 1371 | shift)))); |
43cffd11 RE |
1372 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1373 | gen_rtx_NOT (mode, | |
1374 | gen_rtx_LSHIFTRT (mode, sub, | |
1375 | shift)))); | |
2b835d68 | 1376 | } |
e2c671ba RE |
1377 | return 2; |
1378 | } | |
1379 | ||
1380 | if (set_zero_bit_copies > 8 | |
1381 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
1382 | { | |
2b835d68 RE |
1383 | if (generate) |
1384 | { | |
1385 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1386 | rtx shift = GEN_INT (set_zero_bit_copies); | |
1387 | ||
43cffd11 RE |
1388 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1389 | gen_rtx_NOT (mode, | |
1390 | gen_rtx_LSHIFTRT (mode, | |
1391 | source, | |
f5a1b0d2 | 1392 | shift)))); |
43cffd11 RE |
1393 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1394 | gen_rtx_NOT (mode, | |
1395 | gen_rtx_ASHIFT (mode, sub, | |
f5a1b0d2 | 1396 | shift)))); |
2b835d68 | 1397 | } |
e2c671ba RE |
1398 | return 2; |
1399 | } | |
1400 | ||
5895f793 | 1401 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1402 | { |
2b835d68 RE |
1403 | if (generate) |
1404 | { | |
1405 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
43cffd11 RE |
1406 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1407 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
1408 | source = sub; |
1409 | if (subtargets) | |
1410 | sub = gen_reg_rtx (mode); | |
43cffd11 RE |
1411 | emit_insn (gen_rtx_SET (VOIDmode, sub, |
1412 | gen_rtx_AND (mode, source, | |
1413 | GEN_INT (temp1)))); | |
1414 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
1415 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 1416 | } |
e2c671ba RE |
1417 | return 3; |
1418 | } | |
1419 | break; | |
1420 | ||
1421 | case AND: | |
1422 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
1423 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
1424 | { | |
e5951263 | 1425 | HOST_WIDE_INT shift_mask = (((HOST_UINT (0xffffffff)) |
e2c671ba | 1426 | << (32 - clear_sign_bit_copies)) |
e5951263 | 1427 | & HOST_UINT (0xffffffff)); |
e2c671ba | 1428 | |
e5951263 | 1429 | if ((remainder | shift_mask) != HOST_UINT (0xffffffff)) |
e2c671ba | 1430 | { |
2b835d68 RE |
1431 | if (generate) |
1432 | { | |
d499463f | 1433 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2b835d68 | 1434 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1435 | new_src, source, subtargets, 1); |
1436 | source = new_src; | |
2b835d68 RE |
1437 | } |
1438 | else | |
d499463f RE |
1439 | { |
1440 | rtx targ = subtargets ? NULL_RTX : target; | |
1441 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1442 | targ, source, subtargets, 0); | |
1443 | } | |
2b835d68 RE |
1444 | } |
1445 | ||
1446 | if (generate) | |
1447 | { | |
d499463f RE |
1448 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1449 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
1450 | ||
1451 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
1452 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
1453 | } |
1454 | ||
e2c671ba RE |
1455 | return insns + 2; |
1456 | } | |
1457 | ||
1458 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
1459 | { | |
1460 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
e2c671ba | 1461 | |
e5951263 | 1462 | if ((remainder | shift_mask) != HOST_UINT (0xffffffff)) |
e2c671ba | 1463 | { |
2b835d68 RE |
1464 | if (generate) |
1465 | { | |
d499463f RE |
1466 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1467 | ||
2b835d68 | 1468 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, |
d499463f RE |
1469 | new_src, source, subtargets, 1); |
1470 | source = new_src; | |
2b835d68 RE |
1471 | } |
1472 | else | |
d499463f RE |
1473 | { |
1474 | rtx targ = subtargets ? NULL_RTX : target; | |
1475 | ||
1476 | insns = arm_gen_constant (AND, mode, remainder | shift_mask, | |
1477 | targ, source, subtargets, 0); | |
1478 | } | |
2b835d68 RE |
1479 | } |
1480 | ||
1481 | if (generate) | |
1482 | { | |
d499463f RE |
1483 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1484 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
1485 | ||
1486 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
1487 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
1488 | } |
1489 | ||
e2c671ba RE |
1490 | return insns + 2; |
1491 | } | |
1492 | ||
1493 | break; | |
1494 | ||
1495 | default: | |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | for (i = 0; i < 32; i++) | |
1500 | if (remainder & (1 << i)) | |
1501 | num_bits_set++; | |
1502 | ||
1503 | if (code == AND || (can_invert && num_bits_set > 16)) | |
e5951263 | 1504 | remainder = (~remainder) & HOST_UINT (0xffffffff); |
e2c671ba | 1505 | else if (code == PLUS && num_bits_set > 16) |
e5951263 | 1506 | remainder = (-remainder) & HOST_UINT (0xffffffff); |
e2c671ba RE |
1507 | else |
1508 | { | |
1509 | can_invert = 0; | |
1510 | can_negate = 0; | |
1511 | } | |
1512 | ||
1513 | /* Now try and find a way of doing the job in either two or three | |
1514 | instructions. | |
1515 | We start by looking for the largest block of zeros that are aligned on | |
1516 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
1517 | top of the word when we drop off the bottom. | |
6354dc9b | 1518 | In the worst case this code should produce no more than four insns. */ |
e2c671ba RE |
1519 | { |
1520 | int best_start = 0; | |
1521 | int best_consecutive_zeros = 0; | |
1522 | ||
1523 | for (i = 0; i < 32; i += 2) | |
1524 | { | |
1525 | int consecutive_zeros = 0; | |
1526 | ||
5895f793 | 1527 | if (!(remainder & (3 << i))) |
e2c671ba | 1528 | { |
5895f793 | 1529 | while ((i < 32) && !(remainder & (3 << i))) |
e2c671ba RE |
1530 | { |
1531 | consecutive_zeros += 2; | |
1532 | i += 2; | |
1533 | } | |
1534 | if (consecutive_zeros > best_consecutive_zeros) | |
1535 | { | |
1536 | best_consecutive_zeros = consecutive_zeros; | |
1537 | best_start = i - consecutive_zeros; | |
1538 | } | |
1539 | i -= 2; | |
1540 | } | |
1541 | } | |
1542 | ||
ceebdb09 PB |
1543 | /* So long as it won't require any more insns to do so, it's |
1544 | desirable to emit a small constant (in bits 0...9) in the last | |
1545 | insn. This way there is more chance that it can be combined with | |
1546 | a later addressing insn to form a pre-indexed load or store | |
1547 | operation. Consider: | |
1548 | ||
1549 | *((volatile int *)0xe0000100) = 1; | |
1550 | *((volatile int *)0xe0000110) = 2; | |
1551 | ||
1552 | We want this to wind up as: | |
1553 | ||
1554 | mov rA, #0xe0000000 | |
1555 | mov rB, #1 | |
1556 | str rB, [rA, #0x100] | |
1557 | mov rB, #2 | |
1558 | str rB, [rA, #0x110] | |
1559 | ||
1560 | rather than having to synthesize both large constants from scratch. | |
1561 | ||
1562 | Therefore, we calculate how many insns would be required to emit | |
1563 | the constant starting from `best_start', and also starting from | |
1564 | zero (ie with bit 31 first to be output). If `best_start' doesn't | |
1565 | yield a shorter sequence, we may as well use zero. */ | |
1566 | if (best_start != 0 | |
1567 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
1568 | && (count_insns_for_constant (remainder, 0) <= | |
1569 | count_insns_for_constant (remainder, best_start))) | |
1570 | best_start = 0; | |
1571 | ||
1572 | /* Now start emitting the insns. */ | |
e2c671ba RE |
1573 | i = best_start; |
1574 | do | |
1575 | { | |
1576 | int end; | |
1577 | ||
1578 | if (i <= 0) | |
1579 | i += 32; | |
1580 | if (remainder & (3 << (i - 2))) | |
1581 | { | |
1582 | end = i - 8; | |
1583 | if (end < 0) | |
1584 | end += 32; | |
1585 | temp1 = remainder & ((0x0ff << end) | |
1586 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1587 | remainder &= ~temp1; | |
1588 | ||
d499463f | 1589 | if (generate) |
e2c671ba | 1590 | { |
d499463f RE |
1591 | rtx new_src; |
1592 | ||
1593 | if (code == SET) | |
43cffd11 RE |
1594 | emit_insn (gen_rtx_SET (VOIDmode, |
1595 | new_src = (subtargets | |
1596 | ? gen_reg_rtx (mode) | |
1597 | : target), | |
1598 | GEN_INT (can_invert | |
1599 | ? ~temp1 : temp1))); | |
d499463f | 1600 | else if (code == MINUS) |
43cffd11 RE |
1601 | emit_insn (gen_rtx_SET (VOIDmode, |
1602 | new_src = (subtargets | |
1603 | ? gen_reg_rtx (mode) | |
1604 | : target), | |
1605 | gen_rtx (code, mode, GEN_INT (temp1), | |
1606 | source))); | |
d499463f | 1607 | else |
43cffd11 RE |
1608 | emit_insn (gen_rtx_SET (VOIDmode, |
1609 | new_src = (remainder | |
1610 | ? (subtargets | |
1611 | ? gen_reg_rtx (mode) | |
1612 | : target) | |
1613 | : target), | |
1614 | gen_rtx (code, mode, source, | |
1615 | GEN_INT (can_invert ? ~temp1 | |
1616 | : (can_negate | |
1617 | ? -temp1 | |
1618 | : temp1))))); | |
d499463f | 1619 | source = new_src; |
e2c671ba RE |
1620 | } |
1621 | ||
d499463f RE |
1622 | if (code == SET) |
1623 | { | |
1624 | can_invert = 0; | |
1625 | code = PLUS; | |
1626 | } | |
1627 | else if (code == MINUS) | |
1628 | code = PLUS; | |
1629 | ||
e2c671ba | 1630 | insns++; |
e2c671ba RE |
1631 | i -= 6; |
1632 | } | |
1633 | i -= 2; | |
1634 | } while (remainder); | |
1635 | } | |
1636 | return insns; | |
1637 | } | |
1638 | ||
bd9c7e23 RE |
1639 | /* Canonicalize a comparison so that we are more likely to recognize it. |
1640 | This can be done for a few constant compares, where we can make the | |
1641 | immediate value easier to load. */ | |
1642 | enum rtx_code | |
1643 | arm_canonicalize_comparison (code, op1) | |
1644 | enum rtx_code code; | |
62b10bbc | 1645 | rtx * op1; |
bd9c7e23 | 1646 | { |
ad076f4e | 1647 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
bd9c7e23 RE |
1648 | |
1649 | switch (code) | |
1650 | { | |
1651 | case EQ: | |
1652 | case NE: | |
1653 | return code; | |
1654 | ||
1655 | case GT: | |
1656 | case LE: | |
5895f793 RE |
1657 | if (i != (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) |
1658 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) | |
bd9c7e23 | 1659 | { |
5895f793 | 1660 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
1661 | return code == GT ? GE : LT; |
1662 | } | |
1663 | break; | |
1664 | ||
1665 | case GE: | |
1666 | case LT: | |
e5951263 | 1667 | if (i != ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) |
5895f793 | 1668 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 1669 | { |
5895f793 | 1670 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
1671 | return code == GE ? GT : LE; |
1672 | } | |
1673 | break; | |
1674 | ||
1675 | case GTU: | |
1676 | case LEU: | |
5895f793 RE |
1677 | if (i != ~(HOST_UINT (0)) |
1678 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) | |
bd9c7e23 RE |
1679 | { |
1680 | *op1 = GEN_INT (i + 1); | |
1681 | return code == GTU ? GEU : LTU; | |
1682 | } | |
1683 | break; | |
1684 | ||
1685 | case GEU: | |
1686 | case LTU: | |
1687 | if (i != 0 | |
5895f793 | 1688 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
1689 | { |
1690 | *op1 = GEN_INT (i - 1); | |
1691 | return code == GEU ? GTU : LEU; | |
1692 | } | |
1693 | break; | |
1694 | ||
1695 | default: | |
1696 | abort (); | |
1697 | } | |
1698 | ||
1699 | return code; | |
1700 | } | |
bd9c7e23 | 1701 | |
f5a1b0d2 NC |
1702 | /* Decide whether a type should be returned in memory (true) |
1703 | or in a register (false). This is called by the macro | |
1704 | RETURN_IN_MEMORY. */ | |
2b835d68 RE |
1705 | int |
1706 | arm_return_in_memory (type) | |
1707 | tree type; | |
1708 | { | |
5895f793 | 1709 | if (!AGGREGATE_TYPE_P (type)) |
9e291dbe | 1710 | /* All simple types are returned in registers. */ |
d7d01975 | 1711 | return 0; |
d5b7b3ae RE |
1712 | |
1713 | /* For the arm-wince targets we choose to be compitable with Microsoft's | |
1714 | ARM and Thumb compilers, which always return aggregates in memory. */ | |
1715 | #ifndef ARM_WINCE | |
1716 | ||
d7d01975 | 1717 | if (int_size_in_bytes (type) > 4) |
9e291dbe | 1718 | /* All structures/unions bigger than one word are returned in memory. */ |
d7d01975 | 1719 | return 1; |
d5b7b3ae | 1720 | |
d7d01975 | 1721 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
1722 | { |
1723 | tree field; | |
1724 | ||
3a2ea258 RE |
1725 | /* For a struct the APCS says that we only return in a register |
1726 | if the type is 'integer like' and every addressable element | |
1727 | has an offset of zero. For practical purposes this means | |
1728 | that the structure can have at most one non bit-field element | |
1729 | and that this element must be the first one in the structure. */ | |
1730 | ||
f5a1b0d2 NC |
1731 | /* Find the first field, ignoring non FIELD_DECL things which will |
1732 | have been created by C++. */ | |
1733 | for (field = TYPE_FIELDS (type); | |
1734 | field && TREE_CODE (field) != FIELD_DECL; | |
1735 | field = TREE_CHAIN (field)) | |
1736 | continue; | |
1737 | ||
1738 | if (field == NULL) | |
9e291dbe | 1739 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 1740 | |
d5b7b3ae RE |
1741 | /* Check that the first field is valid for returning in a register. */ |
1742 | ||
1743 | /* ... Floats are not allowed */ | |
9e291dbe | 1744 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
1745 | return 1; |
1746 | ||
d5b7b3ae RE |
1747 | /* ... Aggregates that are not themselves valid for returning in |
1748 | a register are not allowed. */ | |
9e291dbe | 1749 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
3a2ea258 | 1750 | return 1; |
6f7ebcbb | 1751 | |
3a2ea258 RE |
1752 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
1753 | since they are not addressable. */ | |
f5a1b0d2 NC |
1754 | for (field = TREE_CHAIN (field); |
1755 | field; | |
1756 | field = TREE_CHAIN (field)) | |
1757 | { | |
1758 | if (TREE_CODE (field) != FIELD_DECL) | |
1759 | continue; | |
1760 | ||
5895f793 | 1761 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
1762 | return 1; |
1763 | } | |
2b835d68 RE |
1764 | |
1765 | return 0; | |
1766 | } | |
d7d01975 NC |
1767 | |
1768 | if (TREE_CODE (type) == UNION_TYPE) | |
2b835d68 RE |
1769 | { |
1770 | tree field; | |
1771 | ||
1772 | /* Unions can be returned in registers if every element is | |
1773 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
1774 | for (field = TYPE_FIELDS (type); |
1775 | field; | |
1776 | field = TREE_CHAIN (field)) | |
2b835d68 | 1777 | { |
f5a1b0d2 NC |
1778 | if (TREE_CODE (field) != FIELD_DECL) |
1779 | continue; | |
1780 | ||
6cc8c0b3 NC |
1781 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
1782 | return 1; | |
1783 | ||
f5a1b0d2 | 1784 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
2b835d68 RE |
1785 | return 1; |
1786 | } | |
f5a1b0d2 | 1787 | |
2b835d68 RE |
1788 | return 0; |
1789 | } | |
d5b7b3ae | 1790 | #endif /* not ARM_WINCE */ |
f5a1b0d2 | 1791 | |
d5b7b3ae | 1792 | /* Return all other types in memory. */ |
2b835d68 RE |
1793 | return 1; |
1794 | } | |
1795 | ||
82e9d970 PB |
1796 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1797 | for a call to a function whose data type is FNTYPE. | |
1798 | For a library call, FNTYPE is NULL. */ | |
1799 | void | |
1800 | arm_init_cumulative_args (pcum, fntype, libname, indirect) | |
1801 | CUMULATIVE_ARGS * pcum; | |
1802 | tree fntype; | |
1803 | rtx libname ATTRIBUTE_UNUSED; | |
1804 | int indirect ATTRIBUTE_UNUSED; | |
1805 | { | |
1806 | /* On the ARM, the offset starts at 0. */ | |
c27ba912 DM |
1807 | pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0); |
1808 | ||
82e9d970 PB |
1809 | pcum->call_cookie = CALL_NORMAL; |
1810 | ||
1811 | if (TARGET_LONG_CALLS) | |
1812 | pcum->call_cookie = CALL_LONG; | |
1813 | ||
1814 | /* Check for long call/short call attributes. The attributes | |
1815 | override any command line option. */ | |
1816 | if (fntype) | |
1817 | { | |
1818 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) | |
1819 | pcum->call_cookie = CALL_SHORT; | |
1820 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) | |
1821 | pcum->call_cookie = CALL_LONG; | |
1822 | } | |
1823 | } | |
1824 | ||
1825 | /* Determine where to put an argument to a function. | |
1826 | Value is zero to push the argument on the stack, | |
1827 | or a hard register in which to store the argument. | |
1828 | ||
1829 | MODE is the argument's machine mode. | |
1830 | TYPE is the data type of the argument (as a tree). | |
1831 | This is null for libcalls where that information may | |
1832 | not be available. | |
1833 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1834 | the preceding args and about the function being called. | |
1835 | NAMED is nonzero if this argument is a named parameter | |
1836 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1837 | rtx | |
1838 | arm_function_arg (pcum, mode, type, named) | |
1839 | CUMULATIVE_ARGS * pcum; | |
1840 | enum machine_mode mode; | |
1841 | tree type ATTRIBUTE_UNUSED; | |
1842 | int named; | |
1843 | { | |
1844 | if (mode == VOIDmode) | |
1845 | /* Compute operand 2 of the call insn. */ | |
1846 | return GEN_INT (pcum->call_cookie); | |
1847 | ||
5895f793 | 1848 | if (!named || pcum->nregs >= NUM_ARG_REGS) |
82e9d970 PB |
1849 | return NULL_RTX; |
1850 | ||
1851 | return gen_rtx_REG (mode, pcum->nregs); | |
1852 | } | |
82e9d970 | 1853 | \f |
c27ba912 DM |
1854 | /* Encode the current state of the #pragma [no_]long_calls. */ |
1855 | typedef enum | |
82e9d970 | 1856 | { |
c27ba912 DM |
1857 | OFF, /* No #pramgma [no_]long_calls is in effect. */ |
1858 | LONG, /* #pragma long_calls is in effect. */ | |
1859 | SHORT /* #pragma no_long_calls is in effect. */ | |
1860 | } arm_pragma_enum; | |
82e9d970 | 1861 | |
c27ba912 | 1862 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 1863 | |
8b97c5f8 ZW |
1864 | void |
1865 | arm_pr_long_calls (pfile) | |
1866 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
82e9d970 | 1867 | { |
8b97c5f8 ZW |
1868 | arm_pragma_long_calls = LONG; |
1869 | } | |
1870 | ||
1871 | void | |
1872 | arm_pr_no_long_calls (pfile) | |
1873 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
1874 | { | |
1875 | arm_pragma_long_calls = SHORT; | |
1876 | } | |
1877 | ||
1878 | void | |
1879 | arm_pr_long_calls_off (pfile) | |
1880 | cpp_reader *pfile ATTRIBUTE_UNUSED; | |
1881 | { | |
1882 | arm_pragma_long_calls = OFF; | |
82e9d970 | 1883 | } |
8b97c5f8 | 1884 | |
82e9d970 | 1885 | \f |
672a6f42 NB |
1886 | /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine |
1887 | specific attribute for TYPE. The attributes in ATTRIBUTES have | |
1888 | previously been assigned to TYPE. */ | |
1889 | static int | |
82e9d970 PB |
1890 | arm_valid_type_attribute_p (type, attributes, identifier, args) |
1891 | tree type; | |
1892 | tree attributes ATTRIBUTE_UNUSED; | |
1893 | tree identifier; | |
1894 | tree args; | |
1895 | { | |
1896 | if ( TREE_CODE (type) != FUNCTION_TYPE | |
1897 | && TREE_CODE (type) != METHOD_TYPE | |
1898 | && TREE_CODE (type) != FIELD_DECL | |
1899 | && TREE_CODE (type) != TYPE_DECL) | |
1900 | return 0; | |
1901 | ||
1902 | /* Function calls made to this symbol must be done indirectly, because | |
1903 | it may lie outside of the 26 bit addressing range of a normal function | |
1904 | call. */ | |
1905 | if (is_attribute_p ("long_call", identifier)) | |
1906 | return (args == NULL_TREE); | |
c27ba912 | 1907 | |
82e9d970 PB |
1908 | /* Whereas these functions are always known to reside within the 26 bit |
1909 | addressing range. */ | |
1910 | if (is_attribute_p ("short_call", identifier)) | |
1911 | return (args == NULL_TREE); | |
1912 | ||
6d3d9133 NC |
1913 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
1914 | if (is_attribute_p ("isr", identifier) | |
1915 | || is_attribute_p ("interrupt", identifier)) | |
1916 | return arm_isr_value (args); | |
1917 | ||
82e9d970 PB |
1918 | return 0; |
1919 | } | |
1920 | ||
1921 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
1922 | are compatible, and 2 if they are nearly compatible (which causes a | |
1923 | warning to be generated). */ | |
8d8e52be | 1924 | static int |
82e9d970 PB |
1925 | arm_comp_type_attributes (type1, type2) |
1926 | tree type1; | |
1927 | tree type2; | |
1928 | { | |
1cb8d58a | 1929 | int l1, l2, s1, s2; |
bd7fc26f | 1930 | |
82e9d970 PB |
1931 | /* Check for mismatch of non-default calling convention. */ |
1932 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
1933 | return 1; | |
1934 | ||
1935 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
1936 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
1937 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
1938 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
1939 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
1940 | |
1941 | /* Only bother to check if an attribute is defined. */ | |
1942 | if (l1 | l2 | s1 | s2) | |
1943 | { | |
1944 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 1945 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 1946 | return 0; |
82e9d970 | 1947 | |
bd7fc26f NC |
1948 | /* Disallow mixed attributes. */ |
1949 | if ((l1 & s2) || (l2 & s1)) | |
1950 | return 0; | |
1951 | } | |
1952 | ||
6d3d9133 NC |
1953 | /* Check for mismatched ISR attribute. */ |
1954 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
1955 | if (! l1) | |
1956 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
1957 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
1958 | if (! l2) | |
1959 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
1960 | if (l1 != l2) | |
1961 | return 0; | |
1962 | ||
bd7fc26f | 1963 | return 1; |
82e9d970 PB |
1964 | } |
1965 | ||
c27ba912 DM |
1966 | /* Encode long_call or short_call attribute by prefixing |
1967 | symbol name in DECL with a special character FLAG. */ | |
1968 | void | |
1969 | arm_encode_call_attribute (decl, flag) | |
1970 | tree decl; | |
cd2b33d0 | 1971 | int flag; |
c27ba912 | 1972 | { |
3cce094d | 1973 | const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
6354dc9b | 1974 | int len = strlen (str); |
d19fb8e3 | 1975 | char * newstr; |
c27ba912 DM |
1976 | |
1977 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
1978 | return; | |
1979 | ||
1980 | /* Do not allow weak functions to be treated as short call. */ | |
1981 | if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) | |
1982 | return; | |
c27ba912 | 1983 | |
520a57c8 ZW |
1984 | newstr = alloca (len + 2); |
1985 | newstr[0] = flag; | |
1986 | strcpy (newstr + 1, str); | |
c27ba912 | 1987 | |
6d3d9133 | 1988 | newstr = (char *) ggc_alloc_string (newstr, len + 1); |
c27ba912 DM |
1989 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
1990 | } | |
1991 | ||
1992 | /* Assigns default attributes to newly defined type. This is used to | |
1993 | set short_call/long_call attributes for function types of | |
1994 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 1995 | static void |
c27ba912 DM |
1996 | arm_set_default_type_attributes (type) |
1997 | tree type; | |
1998 | { | |
1999 | /* Add __attribute__ ((long_call)) to all functions, when | |
2000 | inside #pragma long_calls or __attribute__ ((short_call)), | |
2001 | when inside #pragma no_long_calls. */ | |
2002 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
2003 | { | |
2004 | tree type_attr_list, attr_name; | |
2005 | type_attr_list = TYPE_ATTRIBUTES (type); | |
2006 | ||
2007 | if (arm_pragma_long_calls == LONG) | |
2008 | attr_name = get_identifier ("long_call"); | |
2009 | else if (arm_pragma_long_calls == SHORT) | |
2010 | attr_name = get_identifier ("short_call"); | |
2011 | else | |
2012 | return; | |
2013 | ||
2014 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
2015 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
2016 | } | |
2017 | } | |
2018 | \f | |
2019 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be | |
2020 | defined within the current compilation unit. If this caanot be | |
2021 | determined, then 0 is returned. */ | |
2022 | static int | |
2023 | current_file_function_operand (sym_ref) | |
2024 | rtx sym_ref; | |
2025 | { | |
2026 | /* This is a bit of a fib. A function will have a short call flag | |
2027 | applied to its name if it has the short call attribute, or it has | |
2028 | already been defined within the current compilation unit. */ | |
2029 | if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) | |
2030 | return 1; | |
2031 | ||
6d77b53e | 2032 | /* The current function is always defined within the current compilation |
c27ba912 DM |
2033 | unit. if it s a weak defintion however, then this may not be the real |
2034 | defintion of the function, and so we have to say no. */ | |
2035 | if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) | |
5895f793 | 2036 | && !DECL_WEAK (current_function_decl)) |
c27ba912 DM |
2037 | return 1; |
2038 | ||
2039 | /* We cannot make the determination - default to returning 0. */ | |
2040 | return 0; | |
2041 | } | |
2042 | ||
2043 | /* Return non-zero if a 32 bit "long_call" should be generated for | |
2044 | this call. We generate a long_call if the function: | |
2045 | ||
2046 | a. has an __attribute__((long call)) | |
2047 | or b. is within the scope of a #pragma long_calls | |
2048 | or c. the -mlong-calls command line switch has been specified | |
2049 | ||
2050 | However we do not generate a long call if the function: | |
2051 | ||
2052 | d. has an __attribute__ ((short_call)) | |
2053 | or e. is inside the scope of a #pragma no_long_calls | |
2054 | or f. has an __attribute__ ((section)) | |
2055 | or g. is defined within the current compilation unit. | |
2056 | ||
2057 | This function will be called by C fragments contained in the machine | |
2058 | description file. CALL_REF and CALL_COOKIE correspond to the matched | |
2059 | rtl operands. CALL_SYMBOL is used to distinguish between | |
2060 | two different callers of the function. It is set to 1 in the | |
2061 | "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" | |
2062 | and "call_value" patterns. This is because of the difference in the | |
2063 | SYM_REFs passed by these patterns. */ | |
2064 | int | |
2065 | arm_is_longcall_p (sym_ref, call_cookie, call_symbol) | |
2066 | rtx sym_ref; | |
2067 | int call_cookie; | |
2068 | int call_symbol; | |
2069 | { | |
5895f793 | 2070 | if (!call_symbol) |
c27ba912 DM |
2071 | { |
2072 | if (GET_CODE (sym_ref) != MEM) | |
2073 | return 0; | |
2074 | ||
2075 | sym_ref = XEXP (sym_ref, 0); | |
2076 | } | |
2077 | ||
2078 | if (GET_CODE (sym_ref) != SYMBOL_REF) | |
2079 | return 0; | |
2080 | ||
2081 | if (call_cookie & CALL_SHORT) | |
2082 | return 0; | |
2083 | ||
2084 | if (TARGET_LONG_CALLS && flag_function_sections) | |
2085 | return 1; | |
2086 | ||
87e27392 | 2087 | if (current_file_function_operand (sym_ref)) |
c27ba912 DM |
2088 | return 0; |
2089 | ||
2090 | return (call_cookie & CALL_LONG) | |
2091 | || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) | |
2092 | || TARGET_LONG_CALLS; | |
2093 | } | |
f99fce0c RE |
2094 | |
2095 | /* Return non-zero if it is ok to make a tail-call to DECL. */ | |
2096 | int | |
2097 | arm_function_ok_for_sibcall (decl) | |
2098 | tree decl; | |
2099 | { | |
2100 | int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; | |
2101 | ||
2102 | /* Never tailcall something for which we have no decl, or if we | |
2103 | are in Thumb mode. */ | |
2104 | if (decl == NULL || TARGET_THUMB) | |
2105 | return 0; | |
2106 | ||
2107 | /* Get the calling method. */ | |
2108 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2109 | call_type = CALL_SHORT; | |
2110 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2111 | call_type = CALL_LONG; | |
2112 | ||
2113 | /* Cannot tail-call to long calls, since these are out of range of | |
2114 | a branch instruction. However, if not compiling PIC, we know | |
2115 | we can reach the symbol if it is in this compilation unit. */ | |
5895f793 | 2116 | if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) |
f99fce0c RE |
2117 | return 0; |
2118 | ||
2119 | /* If we are interworking and the function is not declared static | |
2120 | then we can't tail-call it unless we know that it exists in this | |
2121 | compilation unit (since it might be a Thumb routine). */ | |
5895f793 | 2122 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
f99fce0c RE |
2123 | return 0; |
2124 | ||
6d3d9133 NC |
2125 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
2126 | if (IS_INTERRUPT (arm_current_func_type ())) | |
2127 | return 0; | |
2128 | ||
f99fce0c RE |
2129 | /* Everything else is ok. */ |
2130 | return 1; | |
2131 | } | |
2132 | ||
82e9d970 | 2133 | \f |
32de079a RE |
2134 | int |
2135 | legitimate_pic_operand_p (x) | |
2136 | rtx x; | |
2137 | { | |
d5b7b3ae RE |
2138 | if (CONSTANT_P (x) |
2139 | && flag_pic | |
32de079a RE |
2140 | && (GET_CODE (x) == SYMBOL_REF |
2141 | || (GET_CODE (x) == CONST | |
2142 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2143 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) | |
2144 | return 0; | |
2145 | ||
2146 | return 1; | |
2147 | } | |
2148 | ||
2149 | rtx | |
2150 | legitimize_pic_address (orig, mode, reg) | |
2151 | rtx orig; | |
2152 | enum machine_mode mode; | |
2153 | rtx reg; | |
2154 | { | |
2155 | if (GET_CODE (orig) == SYMBOL_REF) | |
2156 | { | |
2157 | rtx pic_ref, address; | |
2158 | rtx insn; | |
2159 | int subregs = 0; | |
2160 | ||
2161 | if (reg == 0) | |
2162 | { | |
893f3d5b | 2163 | if (no_new_pseudos) |
32de079a RE |
2164 | abort (); |
2165 | else | |
2166 | reg = gen_reg_rtx (Pmode); | |
2167 | ||
2168 | subregs = 1; | |
2169 | } | |
2170 | ||
2171 | #ifdef AOF_ASSEMBLER | |
2172 | /* The AOF assembler can generate relocations for these directly, and | |
6354dc9b | 2173 | understands that the PIC register has to be added into the offset. */ |
32de079a RE |
2174 | insn = emit_insn (gen_pic_load_addr_based (reg, orig)); |
2175 | #else | |
2176 | if (subregs) | |
2177 | address = gen_reg_rtx (Pmode); | |
2178 | else | |
2179 | address = reg; | |
2180 | ||
4bec9f7d NC |
2181 | if (TARGET_ARM) |
2182 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
2183 | else | |
2184 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
32de079a | 2185 | |
43cffd11 RE |
2186 | pic_ref = gen_rtx_MEM (Pmode, |
2187 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
2188 | address)); | |
32de079a RE |
2189 | RTX_UNCHANGING_P (pic_ref) = 1; |
2190 | insn = emit_move_insn (reg, pic_ref); | |
2191 | #endif | |
2192 | current_function_uses_pic_offset_table = 1; | |
2193 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2194 | by loop. */ | |
43cffd11 RE |
2195 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, |
2196 | REG_NOTES (insn)); | |
32de079a RE |
2197 | return reg; |
2198 | } | |
2199 | else if (GET_CODE (orig) == CONST) | |
2200 | { | |
2201 | rtx base, offset; | |
2202 | ||
2203 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
2204 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2205 | return orig; | |
2206 | ||
2207 | if (reg == 0) | |
2208 | { | |
893f3d5b | 2209 | if (no_new_pseudos) |
32de079a RE |
2210 | abort (); |
2211 | else | |
2212 | reg = gen_reg_rtx (Pmode); | |
2213 | } | |
2214 | ||
2215 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
2216 | { | |
2217 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2218 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2219 | base == reg ? 0 : reg); | |
2220 | } | |
2221 | else | |
2222 | abort (); | |
2223 | ||
2224 | if (GET_CODE (offset) == CONST_INT) | |
2225 | { | |
2226 | /* The base register doesn't really matter, we only want to | |
2227 | test the index for the appropriate mode. */ | |
f1008e52 | 2228 | ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win); |
32de079a | 2229 | |
5895f793 | 2230 | if (!no_new_pseudos) |
32de079a RE |
2231 | offset = force_reg (Pmode, offset); |
2232 | else | |
2233 | abort (); | |
2234 | ||
2235 | win: | |
2236 | if (GET_CODE (offset) == CONST_INT) | |
ed8908e7 | 2237 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
2238 | } |
2239 | ||
2240 | if (GET_MODE_SIZE (mode) > 4 | |
2241 | && (GET_MODE_CLASS (mode) == MODE_INT | |
2242 | || TARGET_SOFT_FLOAT)) | |
2243 | { | |
2244 | emit_insn (gen_addsi3 (reg, base, offset)); | |
2245 | return reg; | |
2246 | } | |
2247 | ||
43cffd11 | 2248 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a RE |
2249 | } |
2250 | else if (GET_CODE (orig) == LABEL_REF) | |
82e9d970 PB |
2251 | { |
2252 | current_function_uses_pic_offset_table = 1; | |
2253 | ||
2254 | if (NEED_GOT_RELOC) | |
d5b7b3ae RE |
2255 | { |
2256 | rtx pic_ref, address = gen_reg_rtx (Pmode); | |
4bec9f7d NC |
2257 | |
2258 | if (TARGET_ARM) | |
2259 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
2260 | else | |
2261 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
d19fb8e3 | 2262 | |
d5b7b3ae RE |
2263 | pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); |
2264 | ||
2265 | emit_move_insn (address, pic_ref); | |
2266 | return address; | |
2267 | } | |
82e9d970 | 2268 | } |
32de079a RE |
2269 | |
2270 | return orig; | |
2271 | } | |
2272 | ||
c1163e75 PB |
2273 | /* Generate code to load the PIC register. PROLOGUE is true if |
2274 | called from arm_expand_prologue (in which case we want the | |
2275 | generated insns at the start of the function); false if called | |
2276 | by an exception receiver that needs the PIC register reloaded | |
2277 | (in which case the insns are just dumped at the current location). */ | |
eab4abeb | 2278 | |
32de079a | 2279 | void |
eab4abeb NC |
2280 | arm_finalize_pic (prologue) |
2281 | int prologue; | |
32de079a RE |
2282 | { |
2283 | #ifndef AOF_ASSEMBLER | |
c1163e75 | 2284 | rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; |
32de079a RE |
2285 | rtx global_offset_table; |
2286 | ||
ed0e6530 | 2287 | if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
2288 | return; |
2289 | ||
5895f793 | 2290 | if (!flag_pic) |
32de079a RE |
2291 | abort (); |
2292 | ||
2293 | start_sequence (); | |
2294 | l1 = gen_label_rtx (); | |
2295 | ||
43cffd11 | 2296 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
dfa08768 | 2297 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
d5b7b3ae RE |
2298 | addition, on the Thumb it is 'dot + 4'. */ |
2299 | pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); | |
84306176 PB |
2300 | if (GOT_PCREL) |
2301 | pic_tmp2 = gen_rtx_CONST (VOIDmode, | |
43cffd11 | 2302 | gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); |
84306176 PB |
2303 | else |
2304 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); | |
43cffd11 RE |
2305 | |
2306 | pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); | |
f5a1b0d2 | 2307 | |
d5b7b3ae | 2308 | if (TARGET_ARM) |
4bec9f7d NC |
2309 | { |
2310 | emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); | |
2311 | emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); | |
2312 | } | |
d5b7b3ae | 2313 | else |
4bec9f7d NC |
2314 | { |
2315 | emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); | |
2316 | emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); | |
2317 | } | |
32de079a RE |
2318 | |
2319 | seq = gen_sequence (); | |
2320 | end_sequence (); | |
c1163e75 PB |
2321 | if (prologue) |
2322 | emit_insn_after (seq, get_insns ()); | |
2323 | else | |
2324 | emit_insn (seq); | |
32de079a RE |
2325 | |
2326 | /* Need to emit this whether or not we obey regdecls, | |
2327 | since setjmp/longjmp can cause life info to screw up. */ | |
43cffd11 | 2328 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
32de079a RE |
2329 | #endif /* AOF_ASSEMBLER */ |
2330 | } | |
2331 | ||
e2c671ba RE |
2332 | #define REG_OR_SUBREG_REG(X) \ |
2333 | (GET_CODE (X) == REG \ | |
2334 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
2335 | ||
2336 | #define REG_OR_SUBREG_RTX(X) \ | |
2337 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
2338 | ||
d5b7b3ae RE |
2339 | #ifndef COSTS_N_INSNS |
2340 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
2341 | #endif | |
e2c671ba RE |
2342 | |
2343 | int | |
d5b7b3ae | 2344 | arm_rtx_costs (x, code, outer) |
e2c671ba | 2345 | rtx x; |
74bbc178 | 2346 | enum rtx_code code; |
d5b7b3ae | 2347 | enum rtx_code outer; |
e2c671ba RE |
2348 | { |
2349 | enum machine_mode mode = GET_MODE (x); | |
2350 | enum rtx_code subcode; | |
2351 | int extra_cost; | |
2352 | ||
d5b7b3ae RE |
2353 | if (TARGET_THUMB) |
2354 | { | |
2355 | switch (code) | |
2356 | { | |
2357 | case ASHIFT: | |
2358 | case ASHIFTRT: | |
2359 | case LSHIFTRT: | |
2360 | case ROTATERT: | |
2361 | case PLUS: | |
2362 | case MINUS: | |
2363 | case COMPARE: | |
2364 | case NEG: | |
2365 | case NOT: | |
2366 | return COSTS_N_INSNS (1); | |
2367 | ||
2368 | case MULT: | |
2369 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2370 | { | |
2371 | int cycles = 0; | |
2372 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
2373 | ||
2374 | while (i) | |
2375 | { | |
2376 | i >>= 2; | |
5895f793 | 2377 | cycles++; |
d5b7b3ae RE |
2378 | } |
2379 | return COSTS_N_INSNS (2) + cycles; | |
2380 | } | |
2381 | return COSTS_N_INSNS (1) + 16; | |
2382 | ||
2383 | case SET: | |
2384 | return (COSTS_N_INSNS (1) | |
2385 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
2386 | + GET_CODE (SET_DEST (x)) == MEM)); | |
2387 | ||
2388 | case CONST_INT: | |
2389 | if (outer == SET) | |
2390 | { | |
2391 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
2392 | return 0; | |
2393 | if (thumb_shiftable_const (INTVAL (x))) | |
2394 | return COSTS_N_INSNS (2); | |
2395 | return COSTS_N_INSNS (3); | |
2396 | } | |
2397 | else if (outer == PLUS | |
2398 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
2399 | return 0; | |
2400 | else if (outer == COMPARE | |
2401 | && (unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
2402 | return 0; | |
2403 | else if (outer == ASHIFT || outer == ASHIFTRT | |
2404 | || outer == LSHIFTRT) | |
2405 | return 0; | |
2406 | return COSTS_N_INSNS (2); | |
2407 | ||
2408 | case CONST: | |
2409 | case CONST_DOUBLE: | |
2410 | case LABEL_REF: | |
2411 | case SYMBOL_REF: | |
2412 | return COSTS_N_INSNS (3); | |
2413 | ||
2414 | case UDIV: | |
2415 | case UMOD: | |
2416 | case DIV: | |
2417 | case MOD: | |
2418 | return 100; | |
2419 | ||
2420 | case TRUNCATE: | |
2421 | return 99; | |
2422 | ||
2423 | case AND: | |
2424 | case XOR: | |
2425 | case IOR: | |
2426 | /* XXX guess. */ | |
2427 | return 8; | |
2428 | ||
2429 | case ADDRESSOF: | |
2430 | case MEM: | |
2431 | /* XXX another guess. */ | |
2432 | /* Memory costs quite a lot for the first word, but subsequent words | |
2433 | load at the equivalent of a single insn each. */ | |
2434 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
2435 | + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
2436 | ||
2437 | case IF_THEN_ELSE: | |
2438 | /* XXX a guess. */ | |
2439 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
2440 | return 14; | |
2441 | return 2; | |
2442 | ||
2443 | case ZERO_EXTEND: | |
2444 | /* XXX still guessing. */ | |
2445 | switch (GET_MODE (XEXP (x, 0))) | |
2446 | { | |
2447 | case QImode: | |
2448 | return (1 + (mode == DImode ? 4 : 0) | |
2449 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2450 | ||
2451 | case HImode: | |
2452 | return (4 + (mode == DImode ? 4 : 0) | |
2453 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2454 | ||
2455 | case SImode: | |
2456 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2457 | ||
2458 | default: | |
2459 | return 99; | |
2460 | } | |
2461 | ||
2462 | default: | |
2463 | return 99; | |
2464 | #if 0 | |
2465 | case FFS: | |
2466 | case FLOAT: | |
2467 | case FIX: | |
2468 | case UNSIGNED_FIX: | |
2469 | /* XXX guess */ | |
2470 | fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n", | |
2471 | rtx_name[code]); | |
2472 | abort (); | |
2473 | #endif | |
2474 | } | |
2475 | } | |
2476 | ||
e2c671ba RE |
2477 | switch (code) |
2478 | { | |
2479 | case MEM: | |
2480 | /* Memory costs quite a lot for the first word, but subsequent words | |
2481 | load at the equivalent of a single insn each. */ | |
2482 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
2483 | + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
2484 | ||
2485 | case DIV: | |
2486 | case MOD: | |
2487 | return 100; | |
2488 | ||
2489 | case ROTATE: | |
2490 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
2491 | return 4; | |
2492 | /* Fall through */ | |
2493 | case ROTATERT: | |
2494 | if (mode != SImode) | |
2495 | return 8; | |
2496 | /* Fall through */ | |
2497 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
2498 | if (mode == DImode) | |
2499 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
2500 | + ((GET_CODE (XEXP (x, 0)) == REG | |
2501 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
2502 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
2503 | ? 0 : 8)); | |
2504 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
2505 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
2506 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
2507 | ? 0 : 4) | |
2508 | + ((GET_CODE (XEXP (x, 1)) == REG | |
2509 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
2510 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
2511 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
2512 | ? 0 : 4)); | |
2513 | ||
2514 | case MINUS: | |
2515 | if (mode == DImode) | |
2516 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
2517 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
2518 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
2519 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
2520 | ? 0 : 8)); | |
2521 | ||
2522 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2523 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
2524 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
2525 | && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) | |
2526 | ? 0 : 8) | |
2527 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
2528 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
2529 | && const_double_rtx_ok_for_fpu (XEXP (x, 0)))) | |
2530 | ? 0 : 8)); | |
2531 | ||
2532 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
2533 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
2534 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
2535 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
2536 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
2537 | || subcode == ROTATE || subcode == ROTATERT | |
2538 | || (subcode == MULT | |
2539 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
2540 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
2541 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
2542 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
2543 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
2544 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
2545 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
2546 | return 1; | |
2547 | /* Fall through */ | |
2548 | ||
2549 | case PLUS: | |
2550 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2551 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
2552 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
2553 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
2554 | && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) | |
2555 | ? 0 : 8)); | |
2556 | ||
2557 | /* Fall through */ | |
2558 | case AND: case XOR: case IOR: | |
2559 | extra_cost = 0; | |
2560 | ||
2561 | /* Normally the frame registers will be spilt into reg+const during | |
2562 | reload, so it is a bad idea to combine them with other instructions, | |
2563 | since then they might not be moved outside of loops. As a compromise | |
2564 | we allow integration with ops that have a constant as their second | |
2565 | operand. */ | |
2566 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
2567 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
2568 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
2569 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
2570 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
2571 | extra_cost = 4; | |
2572 | ||
2573 | if (mode == DImode) | |
2574 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
2575 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
2576 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 2577 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
2578 | ? 0 : 8)); |
2579 | ||
2580 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
2581 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
2582 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
2583 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 2584 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
2585 | ? 0 : 4)); |
2586 | ||
2587 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
2588 | return (1 + extra_cost | |
2589 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
2590 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
2591 | || subcode == ROTATE || subcode == ROTATERT | |
2592 | || (subcode == MULT | |
2593 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2594 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 2595 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
2596 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
2597 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 2598 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
2599 | ? 0 : 4)); |
2600 | ||
2601 | return 8; | |
2602 | ||
2603 | case MULT: | |
b111229a | 2604 | /* There is no point basing this on the tuning, since it is always the |
6354dc9b | 2605 | fast variant if it exists at all. */ |
2b835d68 RE |
2606 | if (arm_fast_multiply && mode == DImode |
2607 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
2608 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
2609 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
2610 | return 8; | |
2611 | ||
e2c671ba RE |
2612 | if (GET_MODE_CLASS (mode) == MODE_FLOAT |
2613 | || mode == DImode) | |
2614 | return 30; | |
2615 | ||
2616 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
2617 | { | |
2b835d68 | 2618 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) |
e5951263 | 2619 | & HOST_UINT (0xffffffff)); |
e2c671ba RE |
2620 | int add_cost = const_ok_for_arm (i) ? 4 : 8; |
2621 | int j; | |
6354dc9b NC |
2622 | |
2623 | /* Tune as appropriate. */ | |
aec3cfba | 2624 | int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); |
2a5307b1 | 2625 | |
2b835d68 | 2626 | for (j = 0; i && j < 32; j += booth_unit_size) |
e2c671ba | 2627 | { |
2b835d68 | 2628 | i >>= booth_unit_size; |
e2c671ba RE |
2629 | add_cost += 2; |
2630 | } | |
2631 | ||
2632 | return add_cost; | |
2633 | } | |
2634 | ||
aec3cfba | 2635 | return (((tune_flags & FL_FAST_MULT) ? 8 : 30) |
2b835d68 | 2636 | + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) |
e2c671ba RE |
2637 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); |
2638 | ||
56636818 JL |
2639 | case TRUNCATE: |
2640 | if (arm_fast_multiply && mode == SImode | |
2641 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
2642 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
2643 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
2644 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
2645 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
2646 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
2647 | return 8; | |
2648 | return 99; | |
2649 | ||
e2c671ba RE |
2650 | case NEG: |
2651 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
2652 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
2653 | /* Fall through */ | |
2654 | case NOT: | |
2655 | if (mode == DImode) | |
2656 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
2657 | ||
2658 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
2659 | ||
2660 | case IF_THEN_ELSE: | |
2661 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
2662 | return 14; | |
2663 | return 2; | |
2664 | ||
2665 | case COMPARE: | |
2666 | return 1; | |
2667 | ||
2668 | case ABS: | |
2669 | return 4 + (mode == DImode ? 4 : 0); | |
2670 | ||
2671 | case SIGN_EXTEND: | |
2672 | if (GET_MODE (XEXP (x, 0)) == QImode) | |
2673 | return (4 + (mode == DImode ? 4 : 0) | |
2674 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2675 | /* Fall through */ | |
2676 | case ZERO_EXTEND: | |
2677 | switch (GET_MODE (XEXP (x, 0))) | |
2678 | { | |
2679 | case QImode: | |
2680 | return (1 + (mode == DImode ? 4 : 0) | |
2681 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2682 | ||
2683 | case HImode: | |
2684 | return (4 + (mode == DImode ? 4 : 0) | |
2685 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
2686 | ||
2687 | case SImode: | |
2688 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e RE |
2689 | |
2690 | default: | |
2691 | break; | |
e2c671ba RE |
2692 | } |
2693 | abort (); | |
2694 | ||
d5b7b3ae RE |
2695 | case CONST_INT: |
2696 | if (const_ok_for_arm (INTVAL (x))) | |
2697 | return outer == SET ? 2 : -1; | |
2698 | else if (outer == AND | |
5895f793 | 2699 | && const_ok_for_arm (~INTVAL (x))) |
d5b7b3ae RE |
2700 | return -1; |
2701 | else if ((outer == COMPARE | |
2702 | || outer == PLUS || outer == MINUS) | |
5895f793 | 2703 | && const_ok_for_arm (-INTVAL (x))) |
d5b7b3ae RE |
2704 | return -1; |
2705 | else | |
2706 | return 5; | |
2707 | ||
2708 | case CONST: | |
2709 | case LABEL_REF: | |
2710 | case SYMBOL_REF: | |
2711 | return 6; | |
2712 | ||
2713 | case CONST_DOUBLE: | |
2714 | if (const_double_rtx_ok_for_fpu (x)) | |
2715 | return outer == SET ? 2 : -1; | |
2716 | else if ((outer == COMPARE || outer == PLUS) | |
2717 | && neg_const_double_rtx_ok_for_fpu (x)) | |
2718 | return -1; | |
2719 | return 7; | |
2720 | ||
e2c671ba RE |
2721 | default: |
2722 | return 99; | |
2723 | } | |
2724 | } | |
32de079a RE |
2725 | |
2726 | int | |
2727 | arm_adjust_cost (insn, link, dep, cost) | |
2728 | rtx insn; | |
2729 | rtx link; | |
2730 | rtx dep; | |
2731 | int cost; | |
2732 | { | |
2733 | rtx i_pat, d_pat; | |
2734 | ||
d19fb8e3 NC |
2735 | /* Some true dependencies can have a higher cost depending |
2736 | on precisely how certain input operands are used. */ | |
2737 | if (arm_is_xscale | |
2738 | && REG_NOTE_KIND (link) == 0 | |
2739 | && recog_memoized (insn) < 0 | |
2740 | && recog_memoized (dep) < 0) | |
2741 | { | |
2742 | int shift_opnum = get_attr_shift (insn); | |
2743 | enum attr_type attr_type = get_attr_type (dep); | |
2744 | ||
2745 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
2746 | operand for INSN. If we have a shifted input operand and the | |
2747 | instruction we depend on is another ALU instruction, then we may | |
2748 | have to account for an additional stall. */ | |
2749 | if (shift_opnum != 0 && attr_type == TYPE_NORMAL) | |
2750 | { | |
2751 | rtx shifted_operand; | |
2752 | int opno; | |
2753 | ||
2754 | /* Get the shifted operand. */ | |
2755 | extract_insn (insn); | |
2756 | shifted_operand = recog_data.operand[shift_opnum]; | |
2757 | ||
2758 | /* Iterate over all the operands in DEP. If we write an operand | |
2759 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
2760 | cost of this dependency. */ | |
2761 | extract_insn (dep); | |
2762 | preprocess_constraints (); | |
2763 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
2764 | { | |
2765 | /* We can ignore strict inputs. */ | |
2766 | if (recog_data.operand_type[opno] == OP_IN) | |
2767 | continue; | |
2768 | ||
2769 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
2770 | shifted_operand)) | |
2771 | return 2; | |
2772 | } | |
2773 | } | |
2774 | } | |
2775 | ||
6354dc9b | 2776 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
2777 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
2778 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
2779 | return 0; |
2780 | ||
d5b7b3ae RE |
2781 | /* Call insns don't incur a stall, even if they follow a load. */ |
2782 | if (REG_NOTE_KIND (link) == 0 | |
2783 | && GET_CODE (insn) == CALL_INSN) | |
2784 | return 1; | |
2785 | ||
32de079a RE |
2786 | if ((i_pat = single_set (insn)) != NULL |
2787 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
2788 | && (d_pat = single_set (dep)) != NULL | |
2789 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
2790 | { | |
2791 | /* This is a load after a store, there is no conflict if the load reads | |
2792 | from a cached area. Assume that loads from the stack, and from the | |
2793 | constant pool are cached, and that others will miss. This is a | |
6354dc9b | 2794 | hack. */ |
32de079a | 2795 | |
32de079a RE |
2796 | if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0)) |
2797 | || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) | |
2798 | || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) | |
2799 | || reg_mentioned_p (hard_frame_pointer_rtx, | |
2800 | XEXP (SET_SRC (i_pat), 0))) | |
949d79eb | 2801 | return 1; |
32de079a RE |
2802 | } |
2803 | ||
2804 | return cost; | |
2805 | } | |
2806 | ||
6354dc9b | 2807 | /* This code has been fixed for cross compilation. */ |
ff9940b0 RE |
2808 | |
2809 | static int fpa_consts_inited = 0; | |
2810 | ||
cd2b33d0 | 2811 | static const char * strings_fpa[8] = |
62b10bbc | 2812 | { |
2b835d68 RE |
2813 | "0", "1", "2", "3", |
2814 | "4", "5", "0.5", "10" | |
2815 | }; | |
ff9940b0 RE |
2816 | |
2817 | static REAL_VALUE_TYPE values_fpa[8]; | |
2818 | ||
2819 | static void | |
2820 | init_fpa_table () | |
2821 | { | |
2822 | int i; | |
2823 | REAL_VALUE_TYPE r; | |
2824 | ||
2825 | for (i = 0; i < 8; i++) | |
2826 | { | |
2827 | r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); | |
2828 | values_fpa[i] = r; | |
2829 | } | |
f3bb6135 | 2830 | |
ff9940b0 RE |
2831 | fpa_consts_inited = 1; |
2832 | } | |
2833 | ||
6354dc9b | 2834 | /* Return TRUE if rtx X is a valid immediate FPU constant. */ |
cce8749e CH |
2835 | |
2836 | int | |
2837 | const_double_rtx_ok_for_fpu (x) | |
2838 | rtx x; | |
2839 | { | |
ff9940b0 RE |
2840 | REAL_VALUE_TYPE r; |
2841 | int i; | |
2842 | ||
2843 | if (!fpa_consts_inited) | |
2844 | init_fpa_table (); | |
2845 | ||
2846 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2847 | if (REAL_VALUE_MINUS_ZERO (r)) | |
2848 | return 0; | |
f3bb6135 | 2849 | |
ff9940b0 RE |
2850 | for (i = 0; i < 8; i++) |
2851 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
2852 | return 1; | |
f3bb6135 | 2853 | |
ff9940b0 | 2854 | return 0; |
f3bb6135 | 2855 | } |
ff9940b0 | 2856 | |
6354dc9b | 2857 | /* Return TRUE if rtx X is a valid immediate FPU constant. */ |
ff9940b0 RE |
2858 | |
2859 | int | |
2860 | neg_const_double_rtx_ok_for_fpu (x) | |
2861 | rtx x; | |
2862 | { | |
2863 | REAL_VALUE_TYPE r; | |
2864 | int i; | |
2865 | ||
2866 | if (!fpa_consts_inited) | |
2867 | init_fpa_table (); | |
2868 | ||
2869 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
2870 | r = REAL_VALUE_NEGATE (r); | |
2871 | if (REAL_VALUE_MINUS_ZERO (r)) | |
2872 | return 0; | |
f3bb6135 | 2873 | |
ff9940b0 RE |
2874 | for (i = 0; i < 8; i++) |
2875 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
2876 | return 1; | |
f3bb6135 | 2877 | |
ff9940b0 | 2878 | return 0; |
f3bb6135 | 2879 | } |
cce8749e CH |
2880 | \f |
2881 | /* Predicates for `match_operand' and `match_operator'. */ | |
2882 | ||
ff9940b0 | 2883 | /* s_register_operand is the same as register_operand, but it doesn't accept |
56a38cec DE |
2884 | (SUBREG (MEM)...). |
2885 | ||
2886 | This function exists because at the time it was put in it led to better | |
2887 | code. SUBREG(MEM) always needs a reload in the places where | |
2888 | s_register_operand is used, and this seemed to lead to excessive | |
2889 | reloading. */ | |
ff9940b0 RE |
2890 | |
2891 | int | |
2892 | s_register_operand (op, mode) | |
2893 | register rtx op; | |
2894 | enum machine_mode mode; | |
2895 | { | |
2896 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
2897 | return 0; | |
2898 | ||
2899 | if (GET_CODE (op) == SUBREG) | |
f3bb6135 | 2900 | op = SUBREG_REG (op); |
ff9940b0 RE |
2901 | |
2902 | /* We don't consider registers whose class is NO_REGS | |
2903 | to be a register operand. */ | |
d5b7b3ae | 2904 | /* XXX might have to check for lo regs only for thumb ??? */ |
ff9940b0 RE |
2905 | return (GET_CODE (op) == REG |
2906 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
2907 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
2908 | } | |
2909 | ||
b0888988 RE |
2910 | /* A hard register operand (even before reload. */ |
2911 | int | |
2912 | arm_hard_register_operand (op, mode) | |
2913 | register rtx op; | |
2914 | enum machine_mode mode; | |
2915 | { | |
2916 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
2917 | return 0; | |
2918 | ||
2919 | return (GET_CODE (op) == REG | |
2920 | && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
2921 | } | |
2922 | ||
e2c671ba RE |
2923 | /* Only accept reg, subreg(reg), const_int. */ |
2924 | ||
2925 | int | |
2926 | reg_or_int_operand (op, mode) | |
2927 | register rtx op; | |
2928 | enum machine_mode mode; | |
2929 | { | |
2930 | if (GET_CODE (op) == CONST_INT) | |
2931 | return 1; | |
2932 | ||
2933 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
2934 | return 0; | |
2935 | ||
2936 | if (GET_CODE (op) == SUBREG) | |
2937 | op = SUBREG_REG (op); | |
2938 | ||
2939 | /* We don't consider registers whose class is NO_REGS | |
2940 | to be a register operand. */ | |
2941 | return (GET_CODE (op) == REG | |
2942 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
2943 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
2944 | } | |
2945 | ||
ff9940b0 RE |
2946 | /* Return 1 if OP is an item in memory, given that we are in reload. */ |
2947 | ||
2948 | int | |
d5b7b3ae | 2949 | arm_reload_memory_operand (op, mode) |
ff9940b0 | 2950 | rtx op; |
74bbc178 | 2951 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 RE |
2952 | { |
2953 | int regno = true_regnum (op); | |
2954 | ||
5895f793 | 2955 | return (!CONSTANT_P (op) |
ff9940b0 RE |
2956 | && (regno == -1 |
2957 | || (GET_CODE (op) == REG | |
2958 | && REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
2959 | } | |
2960 | ||
4d818c85 | 2961 | /* Return 1 if OP is a valid memory address, but not valid for a signed byte |
d5b7b3ae RE |
2962 | memory access (architecture V4). |
2963 | MODE is QImode if called when computing contraints, or VOIDmode when | |
2964 | emitting patterns. In this latter case we cannot use memory_operand() | |
2965 | because it will fail on badly formed MEMs, which is precisly what we are | |
2966 | trying to catch. */ | |
4d818c85 RE |
2967 | int |
2968 | bad_signed_byte_operand (op, mode) | |
2969 | rtx op; | |
d5b7b3ae | 2970 | enum machine_mode mode ATTRIBUTE_UNUSED; |
4d818c85 | 2971 | { |
d5b7b3ae | 2972 | #if 0 |
5895f793 | 2973 | if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM) |
d5b7b3ae RE |
2974 | return 0; |
2975 | #endif | |
2976 | if (GET_CODE (op) != MEM) | |
4d818c85 RE |
2977 | return 0; |
2978 | ||
2979 | op = XEXP (op, 0); | |
2980 | ||
6354dc9b | 2981 | /* A sum of anything more complex than reg + reg or reg + const is bad. */ |
4d818c85 | 2982 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
5895f793 RE |
2983 | && (!s_register_operand (XEXP (op, 0), VOIDmode) |
2984 | || (!s_register_operand (XEXP (op, 1), VOIDmode) | |
9c8cc54f | 2985 | && GET_CODE (XEXP (op, 1)) != CONST_INT))) |
4d818c85 RE |
2986 | return 1; |
2987 | ||
6354dc9b | 2988 | /* Big constants are also bad. */ |
4d818c85 RE |
2989 | if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT |
2990 | && (INTVAL (XEXP (op, 1)) > 0xff | |
2991 | || -INTVAL (XEXP (op, 1)) > 0xff)) | |
2992 | return 1; | |
2993 | ||
6354dc9b | 2994 | /* Everything else is good, or can will automatically be made so. */ |
4d818c85 RE |
2995 | return 0; |
2996 | } | |
2997 | ||
cce8749e CH |
2998 | /* Return TRUE for valid operands for the rhs of an ARM instruction. */ |
2999 | ||
3000 | int | |
3001 | arm_rhs_operand (op, mode) | |
3002 | rtx op; | |
3003 | enum machine_mode mode; | |
3004 | { | |
ff9940b0 | 3005 | return (s_register_operand (op, mode) |
cce8749e | 3006 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); |
f3bb6135 | 3007 | } |
cce8749e | 3008 | |
ff9940b0 RE |
3009 | /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load. |
3010 | */ | |
3011 | ||
3012 | int | |
3013 | arm_rhsm_operand (op, mode) | |
3014 | rtx op; | |
3015 | enum machine_mode mode; | |
3016 | { | |
3017 | return (s_register_operand (op, mode) | |
3018 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) | |
3019 | || memory_operand (op, mode)); | |
f3bb6135 | 3020 | } |
ff9940b0 RE |
3021 | |
3022 | /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a | |
3023 | constant that is valid when negated. */ | |
3024 | ||
3025 | int | |
3026 | arm_add_operand (op, mode) | |
3027 | rtx op; | |
3028 | enum machine_mode mode; | |
3029 | { | |
d5b7b3ae RE |
3030 | if (TARGET_THUMB) |
3031 | return thumb_cmp_operand (op, mode); | |
3032 | ||
ff9940b0 RE |
3033 | return (s_register_operand (op, mode) |
3034 | || (GET_CODE (op) == CONST_INT | |
3035 | && (const_ok_for_arm (INTVAL (op)) | |
3036 | || const_ok_for_arm (-INTVAL (op))))); | |
f3bb6135 | 3037 | } |
ff9940b0 RE |
3038 | |
3039 | int | |
3040 | arm_not_operand (op, mode) | |
3041 | rtx op; | |
3042 | enum machine_mode mode; | |
3043 | { | |
3044 | return (s_register_operand (op, mode) | |
3045 | || (GET_CODE (op) == CONST_INT | |
3046 | && (const_ok_for_arm (INTVAL (op)) | |
3047 | || const_ok_for_arm (~INTVAL (op))))); | |
f3bb6135 | 3048 | } |
ff9940b0 | 3049 | |
5165176d RE |
3050 | /* Return TRUE if the operand is a memory reference which contains an |
3051 | offsettable address. */ | |
3052 | int | |
3053 | offsettable_memory_operand (op, mode) | |
3054 | register rtx op; | |
3055 | enum machine_mode mode; | |
3056 | { | |
3057 | if (mode == VOIDmode) | |
3058 | mode = GET_MODE (op); | |
3059 | ||
3060 | return (mode == GET_MODE (op) | |
3061 | && GET_CODE (op) == MEM | |
3062 | && offsettable_address_p (reload_completed | reload_in_progress, | |
3063 | mode, XEXP (op, 0))); | |
3064 | } | |
3065 | ||
3066 | /* Return TRUE if the operand is a memory reference which is, or can be | |
3067 | made word aligned by adjusting the offset. */ | |
3068 | int | |
3069 | alignable_memory_operand (op, mode) | |
3070 | register rtx op; | |
3071 | enum machine_mode mode; | |
3072 | { | |
3073 | rtx reg; | |
3074 | ||
3075 | if (mode == VOIDmode) | |
3076 | mode = GET_MODE (op); | |
3077 | ||
3078 | if (mode != GET_MODE (op) || GET_CODE (op) != MEM) | |
3079 | return 0; | |
3080 | ||
3081 | op = XEXP (op, 0); | |
3082 | ||
3083 | return ((GET_CODE (reg = op) == REG | |
3084 | || (GET_CODE (op) == SUBREG | |
3085 | && GET_CODE (reg = SUBREG_REG (op)) == REG) | |
3086 | || (GET_CODE (op) == PLUS | |
3087 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
3088 | && (GET_CODE (reg = XEXP (op, 0)) == REG | |
3089 | || (GET_CODE (XEXP (op, 0)) == SUBREG | |
3090 | && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) | |
bdb429a5 | 3091 | && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); |
5165176d RE |
3092 | } |
3093 | ||
b111229a RE |
3094 | /* Similar to s_register_operand, but does not allow hard integer |
3095 | registers. */ | |
3096 | int | |
3097 | f_register_operand (op, mode) | |
3098 | register rtx op; | |
3099 | enum machine_mode mode; | |
3100 | { | |
3101 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3102 | return 0; | |
3103 | ||
3104 | if (GET_CODE (op) == SUBREG) | |
3105 | op = SUBREG_REG (op); | |
3106 | ||
3107 | /* We don't consider registers whose class is NO_REGS | |
3108 | to be a register operand. */ | |
3109 | return (GET_CODE (op) == REG | |
3110 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3111 | || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS)); | |
3112 | } | |
3113 | ||
cce8749e CH |
3114 | /* Return TRUE for valid operands for the rhs of an FPU instruction. */ |
3115 | ||
3116 | int | |
3117 | fpu_rhs_operand (op, mode) | |
3118 | rtx op; | |
3119 | enum machine_mode mode; | |
3120 | { | |
ff9940b0 | 3121 | if (s_register_operand (op, mode)) |
f3bb6135 | 3122 | return TRUE; |
9ce71c6f BS |
3123 | |
3124 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3125 | return FALSE; | |
3126 | ||
3127 | if (GET_CODE (op) == CONST_DOUBLE) | |
3128 | return const_double_rtx_ok_for_fpu (op); | |
f3bb6135 RE |
3129 | |
3130 | return FALSE; | |
3131 | } | |
cce8749e | 3132 | |
ff9940b0 RE |
3133 | int |
3134 | fpu_add_operand (op, mode) | |
3135 | rtx op; | |
3136 | enum machine_mode mode; | |
3137 | { | |
3138 | if (s_register_operand (op, mode)) | |
f3bb6135 | 3139 | return TRUE; |
9ce71c6f BS |
3140 | |
3141 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
3142 | return FALSE; | |
3143 | ||
3144 | if (GET_CODE (op) == CONST_DOUBLE) | |
f3bb6135 RE |
3145 | return (const_double_rtx_ok_for_fpu (op) |
3146 | || neg_const_double_rtx_ok_for_fpu (op)); | |
3147 | ||
3148 | return FALSE; | |
ff9940b0 RE |
3149 | } |
3150 | ||
cce8749e CH |
3151 | /* Return nonzero if OP is a constant power of two. */ |
3152 | ||
3153 | int | |
3154 | power_of_two_operand (op, mode) | |
3155 | rtx op; | |
74bbc178 | 3156 | enum machine_mode mode ATTRIBUTE_UNUSED; |
cce8749e CH |
3157 | { |
3158 | if (GET_CODE (op) == CONST_INT) | |
3159 | { | |
d5b7b3ae | 3160 | HOST_WIDE_INT value = INTVAL (op); |
f3bb6135 | 3161 | return value != 0 && (value & (value - 1)) == 0; |
cce8749e | 3162 | } |
f3bb6135 RE |
3163 | return FALSE; |
3164 | } | |
cce8749e CH |
3165 | |
3166 | /* Return TRUE for a valid operand of a DImode operation. | |
e9c6b69b | 3167 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
ff9940b0 RE |
3168 | Note that this disallows MEM(REG+REG), but allows |
3169 | MEM(PRE/POST_INC/DEC(REG)). */ | |
cce8749e CH |
3170 | |
3171 | int | |
3172 | di_operand (op, mode) | |
3173 | rtx op; | |
3174 | enum machine_mode mode; | |
3175 | { | |
ff9940b0 | 3176 | if (s_register_operand (op, mode)) |
f3bb6135 | 3177 | return TRUE; |
cce8749e | 3178 | |
9ce71c6f BS |
3179 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) |
3180 | return FALSE; | |
3181 | ||
e9c6b69b NC |
3182 | if (GET_CODE (op) == SUBREG) |
3183 | op = SUBREG_REG (op); | |
3184 | ||
cce8749e CH |
3185 | switch (GET_CODE (op)) |
3186 | { | |
3187 | case CONST_DOUBLE: | |
3188 | case CONST_INT: | |
f3bb6135 RE |
3189 | return TRUE; |
3190 | ||
cce8749e | 3191 | case MEM: |
f3bb6135 RE |
3192 | return memory_address_p (DImode, XEXP (op, 0)); |
3193 | ||
cce8749e | 3194 | default: |
f3bb6135 | 3195 | return FALSE; |
cce8749e | 3196 | } |
f3bb6135 | 3197 | } |
cce8749e | 3198 | |
d5b7b3ae RE |
3199 | /* Like di_operand, but don't accept constants. */ |
3200 | int | |
3201 | nonimmediate_di_operand (op, mode) | |
3202 | rtx op; | |
3203 | enum machine_mode mode; | |
3204 | { | |
3205 | if (s_register_operand (op, mode)) | |
3206 | return TRUE; | |
3207 | ||
3208 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) | |
3209 | return FALSE; | |
3210 | ||
3211 | if (GET_CODE (op) == SUBREG) | |
3212 | op = SUBREG_REG (op); | |
3213 | ||
3214 | if (GET_CODE (op) == MEM) | |
3215 | return memory_address_p (DImode, XEXP (op, 0)); | |
3216 | ||
3217 | return FALSE; | |
3218 | } | |
3219 | ||
f3139301 | 3220 | /* Return TRUE for a valid operand of a DFmode operation when -msoft-float. |
e9c6b69b | 3221 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
f3139301 DE |
3222 | Note that this disallows MEM(REG+REG), but allows |
3223 | MEM(PRE/POST_INC/DEC(REG)). */ | |
3224 | ||
3225 | int | |
3226 | soft_df_operand (op, mode) | |
3227 | rtx op; | |
3228 | enum machine_mode mode; | |
3229 | { | |
3230 | if (s_register_operand (op, mode)) | |
3231 | return TRUE; | |
3232 | ||
9ce71c6f BS |
3233 | if (mode != VOIDmode && GET_MODE (op) != mode) |
3234 | return FALSE; | |
3235 | ||
37b80d2e BS |
3236 | if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) |
3237 | return FALSE; | |
3238 | ||
e9c6b69b NC |
3239 | if (GET_CODE (op) == SUBREG) |
3240 | op = SUBREG_REG (op); | |
9ce71c6f | 3241 | |
f3139301 DE |
3242 | switch (GET_CODE (op)) |
3243 | { | |
3244 | case CONST_DOUBLE: | |
3245 | return TRUE; | |
3246 | ||
3247 | case MEM: | |
3248 | return memory_address_p (DFmode, XEXP (op, 0)); | |
3249 | ||
3250 | default: | |
3251 | return FALSE; | |
3252 | } | |
3253 | } | |
3254 | ||
d5b7b3ae RE |
3255 | /* Like soft_df_operand, but don't accept constants. */ |
3256 | int | |
3257 | nonimmediate_soft_df_operand (op, mode) | |
3258 | rtx op; | |
3259 | enum machine_mode mode; | |
3260 | { | |
3261 | if (s_register_operand (op, mode)) | |
3262 | return TRUE; | |
3263 | ||
3264 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
3265 | return FALSE; | |
3266 | ||
3267 | if (GET_CODE (op) == SUBREG) | |
3268 | op = SUBREG_REG (op); | |
3269 | ||
3270 | if (GET_CODE (op) == MEM) | |
3271 | return memory_address_p (DFmode, XEXP (op, 0)); | |
3272 | return FALSE; | |
3273 | } | |
cce8749e | 3274 | |
d5b7b3ae | 3275 | /* Return TRUE for valid index operands. */ |
cce8749e CH |
3276 | int |
3277 | index_operand (op, mode) | |
3278 | rtx op; | |
3279 | enum machine_mode mode; | |
3280 | { | |
d5b7b3ae | 3281 | return (s_register_operand (op, mode) |
ff9940b0 | 3282 | || (immediate_operand (op, mode) |
d5b7b3ae RE |
3283 | && (GET_CODE (op) != CONST_INT |
3284 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); | |
f3bb6135 | 3285 | } |
cce8749e | 3286 | |
ff9940b0 RE |
3287 | /* Return TRUE for valid shifts by a constant. This also accepts any |
3288 | power of two on the (somewhat overly relaxed) assumption that the | |
6354dc9b | 3289 | shift operator in this case was a mult. */ |
ff9940b0 RE |
3290 | |
3291 | int | |
3292 | const_shift_operand (op, mode) | |
3293 | rtx op; | |
3294 | enum machine_mode mode; | |
3295 | { | |
3296 | return (power_of_two_operand (op, mode) | |
3297 | || (immediate_operand (op, mode) | |
d5b7b3ae RE |
3298 | && (GET_CODE (op) != CONST_INT |
3299 | || (INTVAL (op) < 32 && INTVAL (op) > 0)))); | |
f3bb6135 | 3300 | } |
ff9940b0 | 3301 | |
cce8749e CH |
3302 | /* Return TRUE for arithmetic operators which can be combined with a multiply |
3303 | (shift). */ | |
3304 | ||
3305 | int | |
3306 | shiftable_operator (x, mode) | |
3307 | rtx x; | |
3308 | enum machine_mode mode; | |
3309 | { | |
3310 | if (GET_MODE (x) != mode) | |
3311 | return FALSE; | |
3312 | else | |
3313 | { | |
3314 | enum rtx_code code = GET_CODE (x); | |
3315 | ||
3316 | return (code == PLUS || code == MINUS | |
3317 | || code == IOR || code == XOR || code == AND); | |
3318 | } | |
f3bb6135 | 3319 | } |
cce8749e | 3320 | |
6ab589e0 JL |
3321 | /* Return TRUE for binary logical operators. */ |
3322 | ||
3323 | int | |
3324 | logical_binary_operator (x, mode) | |
3325 | rtx x; | |
3326 | enum machine_mode mode; | |
3327 | { | |
3328 | if (GET_MODE (x) != mode) | |
3329 | return FALSE; | |
3330 | else | |
3331 | { | |
3332 | enum rtx_code code = GET_CODE (x); | |
3333 | ||
3334 | return (code == IOR || code == XOR || code == AND); | |
3335 | } | |
3336 | } | |
3337 | ||
6354dc9b | 3338 | /* Return TRUE for shift operators. */ |
cce8749e CH |
3339 | |
3340 | int | |
3341 | shift_operator (x, mode) | |
3342 | rtx x; | |
3343 | enum machine_mode mode; | |
3344 | { | |
3345 | if (GET_MODE (x) != mode) | |
3346 | return FALSE; | |
3347 | else | |
3348 | { | |
3349 | enum rtx_code code = GET_CODE (x); | |
3350 | ||
ff9940b0 | 3351 | if (code == MULT) |
aec3cfba | 3352 | return power_of_two_operand (XEXP (x, 1), mode); |
f3bb6135 | 3353 | |
e2c671ba RE |
3354 | return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT |
3355 | || code == ROTATERT); | |
cce8749e | 3356 | } |
f3bb6135 | 3357 | } |
ff9940b0 | 3358 | |
6354dc9b NC |
3359 | /* Return TRUE if x is EQ or NE. */ |
3360 | int | |
3361 | equality_operator (x, mode) | |
f3bb6135 | 3362 | rtx x; |
74bbc178 | 3363 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 3364 | { |
f3bb6135 | 3365 | return GET_CODE (x) == EQ || GET_CODE (x) == NE; |
ff9940b0 RE |
3366 | } |
3367 | ||
e45b72c4 RE |
3368 | /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ |
3369 | int | |
3370 | arm_comparison_operator (x, mode) | |
3371 | rtx x; | |
3372 | enum machine_mode mode; | |
3373 | { | |
3374 | return (comparison_operator (x, mode) | |
3375 | && GET_CODE (x) != LTGT | |
3376 | && GET_CODE (x) != UNEQ); | |
3377 | } | |
3378 | ||
6354dc9b | 3379 | /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ |
ff9940b0 RE |
3380 | int |
3381 | minmax_operator (x, mode) | |
3382 | rtx x; | |
3383 | enum machine_mode mode; | |
3384 | { | |
3385 | enum rtx_code code = GET_CODE (x); | |
3386 | ||
3387 | if (GET_MODE (x) != mode) | |
3388 | return FALSE; | |
f3bb6135 | 3389 | |
ff9940b0 | 3390 | return code == SMIN || code == SMAX || code == UMIN || code == UMAX; |
f3bb6135 | 3391 | } |
ff9940b0 | 3392 | |
ff9940b0 | 3393 | /* Return TRUE if this is the condition code register, if we aren't given |
6354dc9b | 3394 | a mode, accept any class CCmode register. */ |
ff9940b0 RE |
3395 | int |
3396 | cc_register (x, mode) | |
f3bb6135 RE |
3397 | rtx x; |
3398 | enum machine_mode mode; | |
ff9940b0 RE |
3399 | { |
3400 | if (mode == VOIDmode) | |
3401 | { | |
3402 | mode = GET_MODE (x); | |
d5b7b3ae | 3403 | |
ff9940b0 RE |
3404 | if (GET_MODE_CLASS (mode) != MODE_CC) |
3405 | return FALSE; | |
3406 | } | |
f3bb6135 | 3407 | |
d5b7b3ae RE |
3408 | if ( GET_MODE (x) == mode |
3409 | && GET_CODE (x) == REG | |
3410 | && REGNO (x) == CC_REGNUM) | |
ff9940b0 | 3411 | return TRUE; |
f3bb6135 | 3412 | |
ff9940b0 RE |
3413 | return FALSE; |
3414 | } | |
5bbe2d40 RE |
3415 | |
3416 | /* Return TRUE if this is the condition code register, if we aren't given | |
84ed5e79 RE |
3417 | a mode, accept any class CCmode register which indicates a dominance |
3418 | expression. */ | |
5bbe2d40 | 3419 | int |
84ed5e79 | 3420 | dominant_cc_register (x, mode) |
5bbe2d40 RE |
3421 | rtx x; |
3422 | enum machine_mode mode; | |
3423 | { | |
3424 | if (mode == VOIDmode) | |
3425 | { | |
3426 | mode = GET_MODE (x); | |
d5b7b3ae | 3427 | |
84ed5e79 | 3428 | if (GET_MODE_CLASS (mode) != MODE_CC) |
5bbe2d40 RE |
3429 | return FALSE; |
3430 | } | |
3431 | ||
d5b7b3ae | 3432 | if ( mode != CC_DNEmode && mode != CC_DEQmode |
84ed5e79 RE |
3433 | && mode != CC_DLEmode && mode != CC_DLTmode |
3434 | && mode != CC_DGEmode && mode != CC_DGTmode | |
3435 | && mode != CC_DLEUmode && mode != CC_DLTUmode | |
3436 | && mode != CC_DGEUmode && mode != CC_DGTUmode) | |
3437 | return FALSE; | |
3438 | ||
d5b7b3ae | 3439 | return cc_register (x, mode); |
5bbe2d40 RE |
3440 | } |
3441 | ||
2b835d68 RE |
3442 | /* Return TRUE if X references a SYMBOL_REF. */ |
3443 | int | |
3444 | symbol_mentioned_p (x) | |
3445 | rtx x; | |
3446 | { | |
6f7d635c | 3447 | register const char * fmt; |
2b835d68 RE |
3448 | register int i; |
3449 | ||
3450 | if (GET_CODE (x) == SYMBOL_REF) | |
3451 | return 1; | |
3452 | ||
3453 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
d5b7b3ae | 3454 | |
2b835d68 RE |
3455 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
3456 | { | |
3457 | if (fmt[i] == 'E') | |
3458 | { | |
3459 | register int j; | |
3460 | ||
3461 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3462 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
3463 | return 1; | |
3464 | } | |
3465 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
3466 | return 1; | |
3467 | } | |
3468 | ||
3469 | return 0; | |
3470 | } | |
3471 | ||
3472 | /* Return TRUE if X references a LABEL_REF. */ | |
3473 | int | |
3474 | label_mentioned_p (x) | |
3475 | rtx x; | |
3476 | { | |
6f7d635c | 3477 | register const char * fmt; |
2b835d68 RE |
3478 | register int i; |
3479 | ||
3480 | if (GET_CODE (x) == LABEL_REF) | |
3481 | return 1; | |
3482 | ||
3483 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
3484 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
3485 | { | |
3486 | if (fmt[i] == 'E') | |
3487 | { | |
3488 | register int j; | |
3489 | ||
3490 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3491 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
3492 | return 1; | |
3493 | } | |
3494 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
3495 | return 1; | |
3496 | } | |
3497 | ||
3498 | return 0; | |
3499 | } | |
3500 | ||
ff9940b0 RE |
3501 | enum rtx_code |
3502 | minmax_code (x) | |
f3bb6135 | 3503 | rtx x; |
ff9940b0 RE |
3504 | { |
3505 | enum rtx_code code = GET_CODE (x); | |
3506 | ||
3507 | if (code == SMAX) | |
3508 | return GE; | |
f3bb6135 | 3509 | else if (code == SMIN) |
ff9940b0 | 3510 | return LE; |
f3bb6135 | 3511 | else if (code == UMIN) |
ff9940b0 | 3512 | return LEU; |
f3bb6135 | 3513 | else if (code == UMAX) |
ff9940b0 | 3514 | return GEU; |
f3bb6135 | 3515 | |
ff9940b0 RE |
3516 | abort (); |
3517 | } | |
3518 | ||
6354dc9b | 3519 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 3520 | int |
ff9940b0 RE |
3521 | adjacent_mem_locations (a, b) |
3522 | rtx a, b; | |
3523 | { | |
3524 | int val0 = 0, val1 = 0; | |
3525 | int reg0, reg1; | |
3526 | ||
3527 | if ((GET_CODE (XEXP (a, 0)) == REG | |
3528 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
3529 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
3530 | && (GET_CODE (XEXP (b, 0)) == REG | |
3531 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
3532 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
3533 | { | |
3534 | if (GET_CODE (XEXP (a, 0)) == PLUS) | |
3535 | { | |
3536 | reg0 = REGNO (XEXP (XEXP (a, 0), 0)); | |
3537 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); | |
3538 | } | |
3539 | else | |
3540 | reg0 = REGNO (XEXP (a, 0)); | |
3541 | if (GET_CODE (XEXP (b, 0)) == PLUS) | |
3542 | { | |
3543 | reg1 = REGNO (XEXP (XEXP (b, 0), 0)); | |
3544 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); | |
3545 | } | |
3546 | else | |
3547 | reg1 = REGNO (XEXP (b, 0)); | |
3548 | return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); | |
3549 | } | |
3550 | return 0; | |
3551 | } | |
3552 | ||
3553 | /* Return 1 if OP is a load multiple operation. It is known to be | |
6354dc9b | 3554 | parallel and the first section will be tested. */ |
f3bb6135 | 3555 | int |
ff9940b0 RE |
3556 | load_multiple_operation (op, mode) |
3557 | rtx op; | |
74bbc178 | 3558 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 3559 | { |
f3bb6135 | 3560 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
3561 | int dest_regno; |
3562 | rtx src_addr; | |
f3bb6135 | 3563 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
3564 | rtx elt; |
3565 | ||
3566 | if (count <= 1 | |
3567 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
3568 | return 0; | |
3569 | ||
6354dc9b | 3570 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
3571 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
3572 | { | |
3573 | i++; | |
3574 | base = 1; | |
3575 | ||
6354dc9b | 3576 | /* Now check it more carefully. */ |
ff9940b0 RE |
3577 | if (GET_CODE (SET_DEST (elt)) != REG |
3578 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
3579 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
3580 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 3581 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 3582 | return 0; |
ff9940b0 RE |
3583 | } |
3584 | ||
3585 | /* Perform a quick check so we don't blow up below. */ | |
3586 | if (count <= i | |
3587 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
3588 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
3589 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
3590 | return 0; | |
3591 | ||
3592 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
3593 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
3594 | ||
3595 | for (; i < count; i++) | |
3596 | { | |
ed4c4348 | 3597 | elt = XVECEXP (op, 0, i); |
ff9940b0 RE |
3598 | |
3599 | if (GET_CODE (elt) != SET | |
3600 | || GET_CODE (SET_DEST (elt)) != REG | |
3601 | || GET_MODE (SET_DEST (elt)) != SImode | |
6354dc9b | 3602 | || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) |
ff9940b0 RE |
3603 | || GET_CODE (SET_SRC (elt)) != MEM |
3604 | || GET_MODE (SET_SRC (elt)) != SImode | |
3605 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5895f793 | 3606 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) |
ff9940b0 RE |
3607 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT |
3608 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | |
3609 | return 0; | |
3610 | } | |
3611 | ||
3612 | return 1; | |
3613 | } | |
3614 | ||
3615 | /* Return 1 if OP is a store multiple operation. It is known to be | |
6354dc9b | 3616 | parallel and the first section will be tested. */ |
f3bb6135 | 3617 | int |
ff9940b0 RE |
3618 | store_multiple_operation (op, mode) |
3619 | rtx op; | |
74bbc178 | 3620 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ff9940b0 | 3621 | { |
f3bb6135 | 3622 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
3623 | int src_regno; |
3624 | rtx dest_addr; | |
f3bb6135 | 3625 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
3626 | rtx elt; |
3627 | ||
3628 | if (count <= 1 | |
3629 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
3630 | return 0; | |
3631 | ||
6354dc9b | 3632 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
3633 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
3634 | { | |
3635 | i++; | |
3636 | base = 1; | |
3637 | ||
6354dc9b | 3638 | /* Now check it more carefully. */ |
ff9940b0 RE |
3639 | if (GET_CODE (SET_DEST (elt)) != REG |
3640 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
3641 | || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) | |
3642 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT | |
41e3f998 | 3643 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 3644 | return 0; |
ff9940b0 RE |
3645 | } |
3646 | ||
3647 | /* Perform a quick check so we don't blow up below. */ | |
3648 | if (count <= i | |
3649 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
3650 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
3651 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
3652 | return 0; | |
3653 | ||
3654 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
3655 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
3656 | ||
3657 | for (; i < count; i++) | |
3658 | { | |
3659 | elt = XVECEXP (op, 0, i); | |
3660 | ||
3661 | if (GET_CODE (elt) != SET | |
3662 | || GET_CODE (SET_SRC (elt)) != REG | |
3663 | || GET_MODE (SET_SRC (elt)) != SImode | |
6354dc9b | 3664 | || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) |
ff9940b0 RE |
3665 | || GET_CODE (SET_DEST (elt)) != MEM |
3666 | || GET_MODE (SET_DEST (elt)) != SImode | |
3667 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5895f793 | 3668 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) |
ff9940b0 RE |
3669 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT |
3670 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | |
3671 | return 0; | |
3672 | } | |
3673 | ||
3674 | return 1; | |
3675 | } | |
e2c671ba | 3676 | |
84ed5e79 RE |
3677 | int |
3678 | load_multiple_sequence (operands, nops, regs, base, load_offset) | |
62b10bbc | 3679 | rtx * operands; |
84ed5e79 | 3680 | int nops; |
62b10bbc NC |
3681 | int * regs; |
3682 | int * base; | |
3683 | HOST_WIDE_INT * load_offset; | |
84ed5e79 RE |
3684 | { |
3685 | int unsorted_regs[4]; | |
3686 | HOST_WIDE_INT unsorted_offsets[4]; | |
3687 | int order[4]; | |
ad076f4e | 3688 | int base_reg = -1; |
84ed5e79 RE |
3689 | int i; |
3690 | ||
3691 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
3692 | extended if required. */ | |
3693 | if (nops < 2 || nops > 4) | |
3694 | abort (); | |
3695 | ||
3696 | /* Loop over the operands and check that the memory references are | |
3697 | suitable (ie immediate offsets from the same base register). At | |
3698 | the same time, extract the target register, and the memory | |
3699 | offsets. */ | |
3700 | for (i = 0; i < nops; i++) | |
3701 | { | |
3702 | rtx reg; | |
3703 | rtx offset; | |
3704 | ||
56636818 JL |
3705 | /* Convert a subreg of a mem into the mem itself. */ |
3706 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
d5b7b3ae | 3707 | operands[nops + i] = alter_subreg (operands[nops + i]); |
56636818 | 3708 | |
84ed5e79 RE |
3709 | if (GET_CODE (operands[nops + i]) != MEM) |
3710 | abort (); | |
3711 | ||
3712 | /* Don't reorder volatile memory references; it doesn't seem worth | |
3713 | looking for the case where the order is ok anyway. */ | |
3714 | if (MEM_VOLATILE_P (operands[nops + i])) | |
3715 | return 0; | |
3716 | ||
3717 | offset = const0_rtx; | |
3718 | ||
3719 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
3720 | || (GET_CODE (reg) == SUBREG | |
3721 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
3722 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
3723 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
3724 | == REG) | |
3725 | || (GET_CODE (reg) == SUBREG | |
3726 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
3727 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
3728 | == CONST_INT))) | |
3729 | { | |
3730 | if (i == 0) | |
3731 | { | |
d5b7b3ae | 3732 | base_reg = REGNO (reg); |
84ed5e79 RE |
3733 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
3734 | ? REGNO (operands[i]) | |
3735 | : REGNO (SUBREG_REG (operands[i]))); | |
3736 | order[0] = 0; | |
3737 | } | |
3738 | else | |
3739 | { | |
6354dc9b | 3740 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
3741 | /* Not addressed from the same base register. */ |
3742 | return 0; | |
3743 | ||
3744 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
3745 | ? REGNO (operands[i]) | |
3746 | : REGNO (SUBREG_REG (operands[i]))); | |
3747 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
3748 | order[0] = i; | |
3749 | } | |
3750 | ||
3751 | /* If it isn't an integer register, or if it overwrites the | |
3752 | base register but isn't the last insn in the list, then | |
3753 | we can't do this. */ | |
3754 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
3755 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
3756 | return 0; | |
3757 | ||
3758 | unsorted_offsets[i] = INTVAL (offset); | |
3759 | } | |
3760 | else | |
3761 | /* Not a suitable memory address. */ | |
3762 | return 0; | |
3763 | } | |
3764 | ||
3765 | /* All the useful information has now been extracted from the | |
3766 | operands into unsorted_regs and unsorted_offsets; additionally, | |
3767 | order[0] has been set to the lowest numbered register in the | |
3768 | list. Sort the registers into order, and check that the memory | |
3769 | offsets are ascending and adjacent. */ | |
3770 | ||
3771 | for (i = 1; i < nops; i++) | |
3772 | { | |
3773 | int j; | |
3774 | ||
3775 | order[i] = order[i - 1]; | |
3776 | for (j = 0; j < nops; j++) | |
3777 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
3778 | && (order[i] == order[i - 1] | |
3779 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
3780 | order[i] = j; | |
3781 | ||
3782 | /* Have we found a suitable register? if not, one must be used more | |
3783 | than once. */ | |
3784 | if (order[i] == order[i - 1]) | |
3785 | return 0; | |
3786 | ||
3787 | /* Is the memory address adjacent and ascending? */ | |
3788 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
3789 | return 0; | |
3790 | } | |
3791 | ||
3792 | if (base) | |
3793 | { | |
3794 | *base = base_reg; | |
3795 | ||
3796 | for (i = 0; i < nops; i++) | |
3797 | regs[i] = unsorted_regs[order[i]]; | |
3798 | ||
3799 | *load_offset = unsorted_offsets[order[0]]; | |
3800 | } | |
3801 | ||
3802 | if (unsorted_offsets[order[0]] == 0) | |
3803 | return 1; /* ldmia */ | |
3804 | ||
3805 | if (unsorted_offsets[order[0]] == 4) | |
3806 | return 2; /* ldmib */ | |
3807 | ||
3808 | if (unsorted_offsets[order[nops - 1]] == 0) | |
3809 | return 3; /* ldmda */ | |
3810 | ||
3811 | if (unsorted_offsets[order[nops - 1]] == -4) | |
3812 | return 4; /* ldmdb */ | |
3813 | ||
949d79eb RE |
3814 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
3815 | if the offset isn't small enough. The reason 2 ldrs are faster | |
3816 | is because these ARMs are able to do more than one cache access | |
3817 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
3818 | whilst the ARM8 has a double bandwidth cache. This means that | |
3819 | these cores can do both an instruction fetch and a data fetch in | |
3820 | a single cycle, so the trick of calculating the address into a | |
3821 | scratch register (one of the result regs) and then doing a load | |
3822 | multiple actually becomes slower (and no smaller in code size). | |
3823 | That is the transformation | |
6cc8c0b3 NC |
3824 | |
3825 | ldr rd1, [rbase + offset] | |
3826 | ldr rd2, [rbase + offset + 4] | |
3827 | ||
3828 | to | |
3829 | ||
3830 | add rd1, rbase, offset | |
3831 | ldmia rd1, {rd1, rd2} | |
3832 | ||
949d79eb RE |
3833 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
3834 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
3835 | access per cycle, the first sequence could never complete in less | |
3836 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
3837 | would make better use of sequential accesses if not hitting the | |
3838 | cache. | |
3839 | ||
3840 | We cheat here and test 'arm_ld_sched' which we currently know to | |
3841 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
3842 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 3843 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
3844 | return 0; |
3845 | ||
84ed5e79 RE |
3846 | /* Can't do it without setting up the offset, only do this if it takes |
3847 | no more than one insn. */ | |
3848 | return (const_ok_for_arm (unsorted_offsets[order[0]]) | |
3849 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | |
3850 | } | |
3851 | ||
cd2b33d0 | 3852 | const char * |
84ed5e79 | 3853 | emit_ldm_seq (operands, nops) |
62b10bbc | 3854 | rtx * operands; |
84ed5e79 RE |
3855 | int nops; |
3856 | { | |
3857 | int regs[4]; | |
3858 | int base_reg; | |
3859 | HOST_WIDE_INT offset; | |
3860 | char buf[100]; | |
3861 | int i; | |
3862 | ||
3863 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
3864 | { | |
3865 | case 1: | |
3866 | strcpy (buf, "ldm%?ia\t"); | |
3867 | break; | |
3868 | ||
3869 | case 2: | |
3870 | strcpy (buf, "ldm%?ib\t"); | |
3871 | break; | |
3872 | ||
3873 | case 3: | |
3874 | strcpy (buf, "ldm%?da\t"); | |
3875 | break; | |
3876 | ||
3877 | case 4: | |
3878 | strcpy (buf, "ldm%?db\t"); | |
3879 | break; | |
3880 | ||
3881 | case 5: | |
3882 | if (offset >= 0) | |
3883 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
3884 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
3885 | (long) offset); | |
3886 | else | |
3887 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
3888 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
3889 | (long) -offset); | |
3890 | output_asm_insn (buf, operands); | |
3891 | base_reg = regs[0]; | |
3892 | strcpy (buf, "ldm%?ia\t"); | |
3893 | break; | |
3894 | ||
3895 | default: | |
3896 | abort (); | |
3897 | } | |
3898 | ||
3899 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
3900 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
3901 | ||
3902 | for (i = 1; i < nops; i++) | |
3903 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
3904 | reg_names[regs[i]]); | |
3905 | ||
3906 | strcat (buf, "}\t%@ phole ldm"); | |
3907 | ||
3908 | output_asm_insn (buf, operands); | |
3909 | return ""; | |
3910 | } | |
3911 | ||
3912 | int | |
3913 | store_multiple_sequence (operands, nops, regs, base, load_offset) | |
62b10bbc | 3914 | rtx * operands; |
84ed5e79 | 3915 | int nops; |
62b10bbc NC |
3916 | int * regs; |
3917 | int * base; | |
3918 | HOST_WIDE_INT * load_offset; | |
84ed5e79 RE |
3919 | { |
3920 | int unsorted_regs[4]; | |
3921 | HOST_WIDE_INT unsorted_offsets[4]; | |
3922 | int order[4]; | |
ad076f4e | 3923 | int base_reg = -1; |
84ed5e79 RE |
3924 | int i; |
3925 | ||
3926 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
3927 | extended if required. */ | |
3928 | if (nops < 2 || nops > 4) | |
3929 | abort (); | |
3930 | ||
3931 | /* Loop over the operands and check that the memory references are | |
3932 | suitable (ie immediate offsets from the same base register). At | |
3933 | the same time, extract the target register, and the memory | |
3934 | offsets. */ | |
3935 | for (i = 0; i < nops; i++) | |
3936 | { | |
3937 | rtx reg; | |
3938 | rtx offset; | |
3939 | ||
56636818 JL |
3940 | /* Convert a subreg of a mem into the mem itself. */ |
3941 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
d5b7b3ae | 3942 | operands[nops + i] = alter_subreg (operands[nops + i]); |
56636818 | 3943 | |
84ed5e79 RE |
3944 | if (GET_CODE (operands[nops + i]) != MEM) |
3945 | abort (); | |
3946 | ||
3947 | /* Don't reorder volatile memory references; it doesn't seem worth | |
3948 | looking for the case where the order is ok anyway. */ | |
3949 | if (MEM_VOLATILE_P (operands[nops + i])) | |
3950 | return 0; | |
3951 | ||
3952 | offset = const0_rtx; | |
3953 | ||
3954 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
3955 | || (GET_CODE (reg) == SUBREG | |
3956 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
3957 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
3958 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
3959 | == REG) | |
3960 | || (GET_CODE (reg) == SUBREG | |
3961 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
3962 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
3963 | == CONST_INT))) | |
3964 | { | |
3965 | if (i == 0) | |
3966 | { | |
62b10bbc | 3967 | base_reg = REGNO (reg); |
84ed5e79 RE |
3968 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
3969 | ? REGNO (operands[i]) | |
3970 | : REGNO (SUBREG_REG (operands[i]))); | |
3971 | order[0] = 0; | |
3972 | } | |
3973 | else | |
3974 | { | |
6354dc9b | 3975 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
3976 | /* Not addressed from the same base register. */ |
3977 | return 0; | |
3978 | ||
3979 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
3980 | ? REGNO (operands[i]) | |
3981 | : REGNO (SUBREG_REG (operands[i]))); | |
3982 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
3983 | order[0] = i; | |
3984 | } | |
3985 | ||
3986 | /* If it isn't an integer register, then we can't do this. */ | |
3987 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
3988 | return 0; | |
3989 | ||
3990 | unsorted_offsets[i] = INTVAL (offset); | |
3991 | } | |
3992 | else | |
3993 | /* Not a suitable memory address. */ | |
3994 | return 0; | |
3995 | } | |
3996 | ||
3997 | /* All the useful information has now been extracted from the | |
3998 | operands into unsorted_regs and unsorted_offsets; additionally, | |
3999 | order[0] has been set to the lowest numbered register in the | |
4000 | list. Sort the registers into order, and check that the memory | |
4001 | offsets are ascending and adjacent. */ | |
4002 | ||
4003 | for (i = 1; i < nops; i++) | |
4004 | { | |
4005 | int j; | |
4006 | ||
4007 | order[i] = order[i - 1]; | |
4008 | for (j = 0; j < nops; j++) | |
4009 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
4010 | && (order[i] == order[i - 1] | |
4011 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
4012 | order[i] = j; | |
4013 | ||
4014 | /* Have we found a suitable register? if not, one must be used more | |
4015 | than once. */ | |
4016 | if (order[i] == order[i - 1]) | |
4017 | return 0; | |
4018 | ||
4019 | /* Is the memory address adjacent and ascending? */ | |
4020 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
4021 | return 0; | |
4022 | } | |
4023 | ||
4024 | if (base) | |
4025 | { | |
4026 | *base = base_reg; | |
4027 | ||
4028 | for (i = 0; i < nops; i++) | |
4029 | regs[i] = unsorted_regs[order[i]]; | |
4030 | ||
4031 | *load_offset = unsorted_offsets[order[0]]; | |
4032 | } | |
4033 | ||
4034 | if (unsorted_offsets[order[0]] == 0) | |
4035 | return 1; /* stmia */ | |
4036 | ||
4037 | if (unsorted_offsets[order[0]] == 4) | |
4038 | return 2; /* stmib */ | |
4039 | ||
4040 | if (unsorted_offsets[order[nops - 1]] == 0) | |
4041 | return 3; /* stmda */ | |
4042 | ||
4043 | if (unsorted_offsets[order[nops - 1]] == -4) | |
4044 | return 4; /* stmdb */ | |
4045 | ||
4046 | return 0; | |
4047 | } | |
4048 | ||
cd2b33d0 | 4049 | const char * |
84ed5e79 | 4050 | emit_stm_seq (operands, nops) |
62b10bbc | 4051 | rtx * operands; |
84ed5e79 RE |
4052 | int nops; |
4053 | { | |
4054 | int regs[4]; | |
4055 | int base_reg; | |
4056 | HOST_WIDE_INT offset; | |
4057 | char buf[100]; | |
4058 | int i; | |
4059 | ||
4060 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
4061 | { | |
4062 | case 1: | |
4063 | strcpy (buf, "stm%?ia\t"); | |
4064 | break; | |
4065 | ||
4066 | case 2: | |
4067 | strcpy (buf, "stm%?ib\t"); | |
4068 | break; | |
4069 | ||
4070 | case 3: | |
4071 | strcpy (buf, "stm%?da\t"); | |
4072 | break; | |
4073 | ||
4074 | case 4: | |
4075 | strcpy (buf, "stm%?db\t"); | |
4076 | break; | |
4077 | ||
4078 | default: | |
4079 | abort (); | |
4080 | } | |
4081 | ||
4082 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
4083 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
4084 | ||
4085 | for (i = 1; i < nops; i++) | |
4086 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
4087 | reg_names[regs[i]]); | |
4088 | ||
4089 | strcat (buf, "}\t%@ phole stm"); | |
4090 | ||
4091 | output_asm_insn (buf, operands); | |
4092 | return ""; | |
4093 | } | |
4094 | ||
e2c671ba RE |
4095 | int |
4096 | multi_register_push (op, mode) | |
0a81f500 | 4097 | rtx op; |
74bbc178 | 4098 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e2c671ba RE |
4099 | { |
4100 | if (GET_CODE (op) != PARALLEL | |
4101 | || (GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
4102 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
b15bca31 | 4103 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) |
e2c671ba RE |
4104 | return 0; |
4105 | ||
4106 | return 1; | |
4107 | } | |
ff9940b0 | 4108 | \f |
d7d01975 | 4109 | /* Routines for use with attributes. */ |
f3bb6135 | 4110 | |
31fdb4d5 | 4111 | /* Return nonzero if ATTR is a valid attribute for DECL. |
d7d01975 NC |
4112 | ATTRIBUTES are any existing attributes and ARGS are |
4113 | the arguments supplied with ATTR. | |
31fdb4d5 DE |
4114 | |
4115 | Supported attributes: | |
4116 | ||
d5b7b3ae RE |
4117 | naked: |
4118 | don't output any prologue or epilogue code, the user is assumed | |
4119 | to do the right thing. | |
4120 | ||
6d3d9133 NC |
4121 | isr or interrupt: |
4122 | Interrupt Service Routine. | |
4123 | ||
d5b7b3ae RE |
4124 | interfacearm: |
4125 | Always assume that this function will be entered in ARM mode, | |
4126 | not Thumb mode, and that the caller wishes to be returned to in | |
4127 | ARM mode. */ | |
672a6f42 NB |
4128 | static int |
4129 | arm_valid_decl_attribute_p (decl, attributes, attr, args) | |
31fdb4d5 | 4130 | tree decl; |
672a6f42 | 4131 | tree attributes ATTRIBUTE_UNUSED; |
31fdb4d5 DE |
4132 | tree attr; |
4133 | tree args; | |
4134 | { | |
6d3d9133 NC |
4135 | /* The interrupt attribute can take args, so check for it before |
4136 | rejecting other attributes on the grounds that they did have args. */ | |
4137 | if (is_attribute_p ("isr", attr) | |
4138 | || is_attribute_p ("interrupt", attr)) | |
4139 | return TREE_CODE (decl) == FUNCTION_DECL; | |
4140 | ||
31fdb4d5 DE |
4141 | if (args != NULL_TREE) |
4142 | return 0; | |
4143 | ||
4144 | if (is_attribute_p ("naked", attr)) | |
4145 | return TREE_CODE (decl) == FUNCTION_DECL; | |
d19fb8e3 | 4146 | |
d5b7b3ae RE |
4147 | #ifdef ARM_PE |
4148 | if (is_attribute_p ("interfacearm", attr)) | |
4149 | return TREE_CODE (decl) == FUNCTION_DECL; | |
4150 | #endif /* ARM_PE */ | |
4151 | ||
31fdb4d5 DE |
4152 | return 0; |
4153 | } | |
672a6f42 NB |
4154 | |
4155 | #ifdef ARM_PE | |
4156 | ||
4157 | /* ARM/PE has three new attributes: | |
4158 | naked - for interrupt functions | |
4159 | dllexport - for exporting a function/variable that will live in a dll | |
4160 | dllimport - for importing a function/variable from a dll | |
4161 | ||
4162 | Microsoft allows multiple declspecs in one __declspec, separating | |
4163 | them with spaces. We do NOT support this. Instead, use __declspec | |
4164 | multiple times. | |
4165 | */ | |
4166 | ||
4167 | static int | |
4168 | arm_pe_valid_decl_attribute_p (decl, attributes, attr, args) | |
4169 | tree decl; | |
4170 | tree attributes; | |
4171 | tree attr; | |
4172 | tree args; | |
4173 | { | |
4174 | if (args != NULL_TREE) | |
4175 | return 0; | |
4176 | ||
4177 | if (is_attribute_p ("dllexport", attr)) | |
4178 | return 1; | |
4179 | ||
4180 | if (is_attribute_p ("dllimport", attr)) | |
4181 | return 1; | |
4182 | ||
4183 | return arm_valid_decl_attribute_p (decl, attributes, attr, args); | |
4184 | } | |
4185 | ||
4186 | #endif /* ARM_PE */ | |
f3bb6135 | 4187 | \f |
6354dc9b | 4188 | /* Routines for use in generating RTL. */ |
f3bb6135 | 4189 | rtx |
56636818 | 4190 | arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, |
c6df88cb | 4191 | in_struct_p, scalar_p) |
ff9940b0 RE |
4192 | int base_regno; |
4193 | int count; | |
4194 | rtx from; | |
4195 | int up; | |
4196 | int write_back; | |
56636818 JL |
4197 | int unchanging_p; |
4198 | int in_struct_p; | |
c6df88cb | 4199 | int scalar_p; |
ff9940b0 RE |
4200 | { |
4201 | int i = 0, j; | |
4202 | rtx result; | |
4203 | int sign = up ? 1 : -1; | |
56636818 | 4204 | rtx mem; |
ff9940b0 | 4205 | |
d19fb8e3 NC |
4206 | /* XScale has load-store double instructions, but they have stricter |
4207 | alignment requirements than load-store multiple, so we can not | |
4208 | use them. | |
4209 | ||
4210 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
4211 | the pipeline until completion. | |
4212 | ||
4213 | NREGS CYCLES | |
4214 | 1 3 | |
4215 | 2 4 | |
4216 | 3 5 | |
4217 | 4 6 | |
4218 | ||
4219 | An ldr instruction takes 1-3 cycles, but does not block the | |
4220 | pipeline. | |
4221 | ||
4222 | NREGS CYCLES | |
4223 | 1 1-3 | |
4224 | 2 2-6 | |
4225 | 3 3-9 | |
4226 | 4 4-12 | |
4227 | ||
4228 | Best case ldr will always win. However, the more ldr instructions | |
4229 | we issue, the less likely we are to be able to schedule them well. | |
4230 | Using ldr instructions also increases code size. | |
4231 | ||
4232 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
4233 | for counts of 3 or 4 regs. */ | |
4234 | if (arm_is_xscale && count <= 2 && ! optimize_size) | |
4235 | { | |
4236 | rtx seq; | |
4237 | ||
4238 | start_sequence (); | |
4239 | ||
4240 | for (i = 0; i < count; i++) | |
4241 | { | |
4242 | mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign)); | |
4243 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
4244 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
4245 | MEM_SCALAR_P (mem) = scalar_p; | |
4246 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | |
4247 | } | |
4248 | ||
4249 | if (write_back) | |
4250 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
4251 | ||
4252 | seq = gen_sequence (); | |
4253 | end_sequence (); | |
4254 | ||
4255 | return seq; | |
4256 | } | |
4257 | ||
43cffd11 | 4258 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 4259 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 4260 | if (write_back) |
f3bb6135 | 4261 | { |
ff9940b0 | 4262 | XVECEXP (result, 0, 0) |
43cffd11 RE |
4263 | = gen_rtx_SET (GET_MODE (from), from, |
4264 | plus_constant (from, count * 4 * sign)); | |
ff9940b0 RE |
4265 | i = 1; |
4266 | count++; | |
f3bb6135 RE |
4267 | } |
4268 | ||
ff9940b0 | 4269 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 4270 | { |
43cffd11 | 4271 | mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); |
56636818 JL |
4272 | RTX_UNCHANGING_P (mem) = unchanging_p; |
4273 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 4274 | MEM_SCALAR_P (mem) = scalar_p; |
43cffd11 RE |
4275 | XVECEXP (result, 0, i) |
4276 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
f3bb6135 RE |
4277 | } |
4278 | ||
ff9940b0 RE |
4279 | return result; |
4280 | } | |
4281 | ||
f3bb6135 | 4282 | rtx |
56636818 | 4283 | arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, |
c6df88cb | 4284 | in_struct_p, scalar_p) |
ff9940b0 RE |
4285 | int base_regno; |
4286 | int count; | |
4287 | rtx to; | |
4288 | int up; | |
4289 | int write_back; | |
56636818 JL |
4290 | int unchanging_p; |
4291 | int in_struct_p; | |
c6df88cb | 4292 | int scalar_p; |
ff9940b0 RE |
4293 | { |
4294 | int i = 0, j; | |
4295 | rtx result; | |
4296 | int sign = up ? 1 : -1; | |
56636818 | 4297 | rtx mem; |
ff9940b0 | 4298 | |
d19fb8e3 NC |
4299 | /* See arm_gen_load_multiple for discussion of |
4300 | the pros/cons of ldm/stm usage for XScale. */ | |
4301 | if (arm_is_xscale && count <= 2 && ! optimize_size) | |
4302 | { | |
4303 | rtx seq; | |
4304 | ||
4305 | start_sequence (); | |
4306 | ||
4307 | for (i = 0; i < count; i++) | |
4308 | { | |
4309 | mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign)); | |
4310 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
4311 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
4312 | MEM_SCALAR_P (mem) = scalar_p; | |
4313 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | |
4314 | } | |
4315 | ||
4316 | if (write_back) | |
4317 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
4318 | ||
4319 | seq = gen_sequence (); | |
4320 | end_sequence (); | |
4321 | ||
4322 | return seq; | |
4323 | } | |
4324 | ||
43cffd11 | 4325 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 4326 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 4327 | if (write_back) |
f3bb6135 | 4328 | { |
ff9940b0 | 4329 | XVECEXP (result, 0, 0) |
43cffd11 RE |
4330 | = gen_rtx_SET (GET_MODE (to), to, |
4331 | plus_constant (to, count * 4 * sign)); | |
ff9940b0 RE |
4332 | i = 1; |
4333 | count++; | |
f3bb6135 RE |
4334 | } |
4335 | ||
ff9940b0 | 4336 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 4337 | { |
43cffd11 | 4338 | mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); |
56636818 JL |
4339 | RTX_UNCHANGING_P (mem) = unchanging_p; |
4340 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 4341 | MEM_SCALAR_P (mem) = scalar_p; |
56636818 | 4342 | |
43cffd11 RE |
4343 | XVECEXP (result, 0, i) |
4344 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
f3bb6135 RE |
4345 | } |
4346 | ||
ff9940b0 RE |
4347 | return result; |
4348 | } | |
4349 | ||
880e2516 RE |
4350 | int |
4351 | arm_gen_movstrqi (operands) | |
62b10bbc | 4352 | rtx * operands; |
880e2516 RE |
4353 | { |
4354 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
ad076f4e | 4355 | int i; |
880e2516 | 4356 | rtx src, dst; |
ad076f4e | 4357 | rtx st_src, st_dst, fin_src, fin_dst; |
880e2516 | 4358 | rtx part_bytes_reg = NULL; |
56636818 JL |
4359 | rtx mem; |
4360 | int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; | |
c6df88cb | 4361 | int dst_scalar_p, src_scalar_p; |
880e2516 RE |
4362 | |
4363 | if (GET_CODE (operands[2]) != CONST_INT | |
4364 | || GET_CODE (operands[3]) != CONST_INT | |
4365 | || INTVAL (operands[2]) > 64 | |
4366 | || INTVAL (operands[3]) & 3) | |
4367 | return 0; | |
4368 | ||
4369 | st_dst = XEXP (operands[0], 0); | |
4370 | st_src = XEXP (operands[1], 0); | |
56636818 JL |
4371 | |
4372 | dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); | |
4373 | dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); | |
c6df88cb | 4374 | dst_scalar_p = MEM_SCALAR_P (operands[0]); |
56636818 JL |
4375 | src_unchanging_p = RTX_UNCHANGING_P (operands[1]); |
4376 | src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); | |
c6df88cb | 4377 | src_scalar_p = MEM_SCALAR_P (operands[1]); |
56636818 | 4378 | |
880e2516 RE |
4379 | fin_dst = dst = copy_to_mode_reg (SImode, st_dst); |
4380 | fin_src = src = copy_to_mode_reg (SImode, st_src); | |
4381 | ||
d5b7b3ae | 4382 | in_words_to_go = NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
4383 | out_words_to_go = INTVAL (operands[2]) / 4; |
4384 | last_bytes = INTVAL (operands[2]) & 3; | |
4385 | ||
4386 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 4387 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
4388 | |
4389 | for (i = 0; in_words_to_go >= 2; i+=4) | |
4390 | { | |
bd9c7e23 | 4391 | if (in_words_to_go > 4) |
56636818 | 4392 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
c6df88cb MM |
4393 | src_unchanging_p, |
4394 | src_in_struct_p, | |
4395 | src_scalar_p)); | |
bd9c7e23 RE |
4396 | else |
4397 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | |
56636818 | 4398 | FALSE, src_unchanging_p, |
c6df88cb | 4399 | src_in_struct_p, src_scalar_p)); |
bd9c7e23 | 4400 | |
880e2516 RE |
4401 | if (out_words_to_go) |
4402 | { | |
bd9c7e23 | 4403 | if (out_words_to_go > 4) |
56636818 JL |
4404 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
4405 | dst_unchanging_p, | |
c6df88cb MM |
4406 | dst_in_struct_p, |
4407 | dst_scalar_p)); | |
bd9c7e23 RE |
4408 | else if (out_words_to_go != 1) |
4409 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
4410 | dst, TRUE, | |
4411 | (last_bytes == 0 | |
56636818 JL |
4412 | ? FALSE : TRUE), |
4413 | dst_unchanging_p, | |
c6df88cb MM |
4414 | dst_in_struct_p, |
4415 | dst_scalar_p)); | |
880e2516 RE |
4416 | else |
4417 | { | |
43cffd11 | 4418 | mem = gen_rtx_MEM (SImode, dst); |
56636818 JL |
4419 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
4420 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 4421 | MEM_SCALAR_P (mem) = dst_scalar_p; |
43cffd11 | 4422 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 RE |
4423 | if (last_bytes != 0) |
4424 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
880e2516 RE |
4425 | } |
4426 | } | |
4427 | ||
4428 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
4429 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
4430 | } | |
4431 | ||
4432 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
4433 | if (out_words_to_go) | |
62b10bbc NC |
4434 | { |
4435 | rtx sreg; | |
4436 | ||
4437 | mem = gen_rtx_MEM (SImode, src); | |
4438 | RTX_UNCHANGING_P (mem) = src_unchanging_p; | |
4439 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
4440 | MEM_SCALAR_P (mem) = src_scalar_p; | |
4441 | emit_move_insn (sreg = gen_reg_rtx (SImode), mem); | |
4442 | emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); | |
4443 | ||
4444 | mem = gen_rtx_MEM (SImode, dst); | |
4445 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
4446 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
4447 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
4448 | emit_move_insn (mem, sreg); | |
4449 | emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); | |
4450 | in_words_to_go--; | |
4451 | ||
4452 | if (in_words_to_go) /* Sanity check */ | |
4453 | abort (); | |
4454 | } | |
880e2516 RE |
4455 | |
4456 | if (in_words_to_go) | |
4457 | { | |
4458 | if (in_words_to_go < 0) | |
4459 | abort (); | |
4460 | ||
43cffd11 | 4461 | mem = gen_rtx_MEM (SImode, src); |
56636818 JL |
4462 | RTX_UNCHANGING_P (mem) = src_unchanging_p; |
4463 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
c6df88cb | 4464 | MEM_SCALAR_P (mem) = src_scalar_p; |
56636818 | 4465 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
4466 | } |
4467 | ||
d5b7b3ae RE |
4468 | if (last_bytes && part_bytes_reg == NULL) |
4469 | abort (); | |
4470 | ||
880e2516 RE |
4471 | if (BYTES_BIG_ENDIAN && last_bytes) |
4472 | { | |
4473 | rtx tmp = gen_reg_rtx (SImode); | |
4474 | ||
6354dc9b | 4475 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
4476 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
4477 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 RE |
4478 | part_bytes_reg = tmp; |
4479 | ||
4480 | while (last_bytes) | |
4481 | { | |
43cffd11 | 4482 | mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); |
56636818 JL |
4483 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
4484 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 4485 | MEM_SCALAR_P (mem) = dst_scalar_p; |
43cffd11 | 4486 | emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0)); |
62b10bbc | 4487 | |
880e2516 RE |
4488 | if (--last_bytes) |
4489 | { | |
4490 | tmp = gen_reg_rtx (SImode); | |
4491 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
4492 | part_bytes_reg = tmp; | |
4493 | } | |
4494 | } | |
4495 | ||
4496 | } | |
4497 | else | |
4498 | { | |
d5b7b3ae | 4499 | if (last_bytes > 1) |
880e2516 | 4500 | { |
d5b7b3ae | 4501 | mem = gen_rtx_MEM (HImode, dst); |
56636818 JL |
4502 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
4503 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 4504 | MEM_SCALAR_P (mem) = dst_scalar_p; |
d5b7b3ae RE |
4505 | emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0)); |
4506 | last_bytes -= 2; | |
4507 | if (last_bytes) | |
880e2516 RE |
4508 | { |
4509 | rtx tmp = gen_reg_rtx (SImode); | |
bd9c7e23 | 4510 | |
d5b7b3ae RE |
4511 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (2))); |
4512 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); | |
880e2516 RE |
4513 | part_bytes_reg = tmp; |
4514 | } | |
4515 | } | |
d5b7b3ae RE |
4516 | |
4517 | if (last_bytes) | |
4518 | { | |
4519 | mem = gen_rtx_MEM (QImode, dst); | |
4520 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
4521 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
4522 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
4523 | emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0)); | |
4524 | } | |
880e2516 RE |
4525 | } |
4526 | ||
4527 | return 1; | |
4528 | } | |
4529 | ||
5165176d RE |
4530 | /* Generate a memory reference for a half word, such that it will be loaded |
4531 | into the top 16 bits of the word. We can assume that the address is | |
4532 | known to be alignable and of the form reg, or plus (reg, const). */ | |
4533 | rtx | |
d5b7b3ae | 4534 | arm_gen_rotated_half_load (memref) |
5165176d RE |
4535 | rtx memref; |
4536 | { | |
4537 | HOST_WIDE_INT offset = 0; | |
4538 | rtx base = XEXP (memref, 0); | |
4539 | ||
4540 | if (GET_CODE (base) == PLUS) | |
4541 | { | |
4542 | offset = INTVAL (XEXP (base, 1)); | |
4543 | base = XEXP (base, 0); | |
4544 | } | |
4545 | ||
956d6950 | 4546 | /* If we aren't allowed to generate unaligned addresses, then fail. */ |
5f1e6755 | 4547 | if (TARGET_MMU_TRAPS |
5165176d RE |
4548 | && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) |
4549 | return NULL; | |
4550 | ||
43cffd11 | 4551 | base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); |
5165176d RE |
4552 | |
4553 | if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) | |
4554 | return base; | |
4555 | ||
43cffd11 | 4556 | return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); |
5165176d RE |
4557 | } |
4558 | ||
1646cf41 RE |
4559 | /* Select a dominance comparison mode if possible. We support three forms. |
4560 | COND_OR == 0 => (X && Y) | |
4561 | COND_OR == 1 => ((! X( || Y) | |
4562 | COND_OR == 2 => (X || Y) | |
4563 | If we are unable to support a dominance comparsison we return CC mode. | |
4564 | This will then fail to match for the RTL expressions that generate this | |
4565 | call. */ | |
d19fb8e3 | 4566 | |
84ed5e79 | 4567 | static enum machine_mode |
74bbc178 | 4568 | select_dominance_cc_mode (x, y, cond_or) |
84ed5e79 RE |
4569 | rtx x; |
4570 | rtx y; | |
4571 | HOST_WIDE_INT cond_or; | |
4572 | { | |
4573 | enum rtx_code cond1, cond2; | |
4574 | int swapped = 0; | |
4575 | ||
4576 | /* Currently we will probably get the wrong result if the individual | |
4577 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 4578 | reverse a comparison if necessary. */ |
84ed5e79 RE |
4579 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
4580 | != CCmode) | |
4581 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
4582 | != CCmode)) | |
4583 | return CCmode; | |
4584 | ||
1646cf41 RE |
4585 | /* The if_then_else variant of this tests the second condition if the |
4586 | first passes, but is true if the first fails. Reverse the first | |
4587 | condition to get a true "inclusive-or" expression. */ | |
4588 | if (cond_or == 1) | |
84ed5e79 RE |
4589 | cond1 = reverse_condition (cond1); |
4590 | ||
4591 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
4592 | then we can't do this. */ | |
4593 | if (cond1 != cond2 | |
5895f793 RE |
4594 | && !comparison_dominates_p (cond1, cond2) |
4595 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
4596 | return CCmode; |
4597 | ||
4598 | if (swapped) | |
4599 | { | |
4600 | enum rtx_code temp = cond1; | |
4601 | cond1 = cond2; | |
4602 | cond2 = temp; | |
4603 | } | |
4604 | ||
4605 | switch (cond1) | |
4606 | { | |
4607 | case EQ: | |
5895f793 | 4608 | if (cond2 == EQ || !cond_or) |
84ed5e79 RE |
4609 | return CC_DEQmode; |
4610 | ||
4611 | switch (cond2) | |
4612 | { | |
4613 | case LE: return CC_DLEmode; | |
4614 | case LEU: return CC_DLEUmode; | |
4615 | case GE: return CC_DGEmode; | |
4616 | case GEU: return CC_DGEUmode; | |
ad076f4e | 4617 | default: break; |
84ed5e79 RE |
4618 | } |
4619 | ||
4620 | break; | |
4621 | ||
4622 | case LT: | |
5895f793 | 4623 | if (cond2 == LT || !cond_or) |
84ed5e79 RE |
4624 | return CC_DLTmode; |
4625 | if (cond2 == LE) | |
4626 | return CC_DLEmode; | |
4627 | if (cond2 == NE) | |
4628 | return CC_DNEmode; | |
4629 | break; | |
4630 | ||
4631 | case GT: | |
5895f793 | 4632 | if (cond2 == GT || !cond_or) |
84ed5e79 RE |
4633 | return CC_DGTmode; |
4634 | if (cond2 == GE) | |
4635 | return CC_DGEmode; | |
4636 | if (cond2 == NE) | |
4637 | return CC_DNEmode; | |
4638 | break; | |
4639 | ||
4640 | case LTU: | |
5895f793 | 4641 | if (cond2 == LTU || !cond_or) |
84ed5e79 RE |
4642 | return CC_DLTUmode; |
4643 | if (cond2 == LEU) | |
4644 | return CC_DLEUmode; | |
4645 | if (cond2 == NE) | |
4646 | return CC_DNEmode; | |
4647 | break; | |
4648 | ||
4649 | case GTU: | |
5895f793 | 4650 | if (cond2 == GTU || !cond_or) |
84ed5e79 RE |
4651 | return CC_DGTUmode; |
4652 | if (cond2 == GEU) | |
4653 | return CC_DGEUmode; | |
4654 | if (cond2 == NE) | |
4655 | return CC_DNEmode; | |
4656 | break; | |
4657 | ||
4658 | /* The remaining cases only occur when both comparisons are the | |
4659 | same. */ | |
4660 | case NE: | |
4661 | return CC_DNEmode; | |
4662 | ||
4663 | case LE: | |
4664 | return CC_DLEmode; | |
4665 | ||
4666 | case GE: | |
4667 | return CC_DGEmode; | |
4668 | ||
4669 | case LEU: | |
4670 | return CC_DLEUmode; | |
4671 | ||
4672 | case GEU: | |
4673 | return CC_DGEUmode; | |
ad076f4e RE |
4674 | |
4675 | default: | |
4676 | break; | |
84ed5e79 RE |
4677 | } |
4678 | ||
4679 | abort (); | |
4680 | } | |
4681 | ||
4682 | enum machine_mode | |
4683 | arm_select_cc_mode (op, x, y) | |
4684 | enum rtx_code op; | |
4685 | rtx x; | |
4686 | rtx y; | |
4687 | { | |
4688 | /* All floating point compares return CCFP if it is an equality | |
4689 | comparison, and CCFPE otherwise. */ | |
4690 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
4691 | { |
4692 | switch (op) | |
4693 | { | |
4694 | case EQ: | |
4695 | case NE: | |
4696 | case UNORDERED: | |
4697 | case ORDERED: | |
4698 | case UNLT: | |
4699 | case UNLE: | |
4700 | case UNGT: | |
4701 | case UNGE: | |
4702 | case UNEQ: | |
4703 | case LTGT: | |
4704 | return CCFPmode; | |
4705 | ||
4706 | case LT: | |
4707 | case LE: | |
4708 | case GT: | |
4709 | case GE: | |
4710 | return CCFPEmode; | |
4711 | ||
4712 | default: | |
4713 | abort (); | |
4714 | } | |
4715 | } | |
84ed5e79 RE |
4716 | |
4717 | /* A compare with a shifted operand. Because of canonicalization, the | |
4718 | comparison will have to be swapped when we emit the assembler. */ | |
4719 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
4720 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
4721 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
4722 | || GET_CODE (x) == ROTATERT)) | |
4723 | return CC_SWPmode; | |
4724 | ||
956d6950 JL |
4725 | /* This is a special case that is used by combine to allow a |
4726 | comparison of a shifted byte load to be split into a zero-extend | |
84ed5e79 | 4727 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 4728 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
4729 | if (GET_MODE (x) == SImode |
4730 | && GET_CODE (x) == ASHIFT | |
4731 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
4732 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
4733 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
4734 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
4735 | && (op == EQ || op == NE | |
4736 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
4737 | && GET_CODE (y) == CONST_INT) | |
4738 | return CC_Zmode; | |
4739 | ||
1646cf41 RE |
4740 | /* A construct for a conditional compare, if the false arm contains |
4741 | 0, then both conditions must be true, otherwise either condition | |
4742 | must be true. Not all conditions are possible, so CCmode is | |
4743 | returned if it can't be done. */ | |
4744 | if (GET_CODE (x) == IF_THEN_ELSE | |
4745 | && (XEXP (x, 2) == const0_rtx | |
4746 | || XEXP (x, 2) == const1_rtx) | |
4747 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
4748 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
4749 | return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), | |
4750 | INTVAL (XEXP (x, 2))); | |
4751 | ||
4752 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
4753 | if (GET_CODE (x) == AND | |
4754 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
4755 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
4756 | return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0); | |
4757 | ||
4758 | if (GET_CODE (x) == IOR | |
4759 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
4760 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') | |
4761 | return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2); | |
4762 | ||
84ed5e79 RE |
4763 | /* An operation that sets the condition codes as a side-effect, the |
4764 | V flag is not set correctly, so we can only use comparisons where | |
4765 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
4766 | instead. */ | |
4767 | if (GET_MODE (x) == SImode | |
4768 | && y == const0_rtx | |
4769 | && (op == EQ || op == NE || op == LT || op == GE) | |
4770 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
4771 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
4772 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
4773 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
4774 | || GET_CODE (x) == LSHIFTRT | |
4775 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
4776 | || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) | |
4777 | return CC_NOOVmode; | |
4778 | ||
84ed5e79 RE |
4779 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
4780 | return CC_Zmode; | |
4781 | ||
bd9c7e23 RE |
4782 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
4783 | && GET_CODE (x) == PLUS | |
4784 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
4785 | return CC_Cmode; | |
4786 | ||
84ed5e79 RE |
4787 | return CCmode; |
4788 | } | |
4789 | ||
ff9940b0 RE |
4790 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
4791 | return the rtx for register 0 in the proper mode. FP means this is a | |
4792 | floating point compare: I don't think that it is needed on the arm. */ | |
4793 | ||
4794 | rtx | |
d5b7b3ae | 4795 | arm_gen_compare_reg (code, x, y) |
ff9940b0 RE |
4796 | enum rtx_code code; |
4797 | rtx x, y; | |
4798 | { | |
4799 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 4800 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 4801 | |
43cffd11 RE |
4802 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
4803 | gen_rtx_COMPARE (mode, x, y))); | |
ff9940b0 RE |
4804 | |
4805 | return cc_reg; | |
4806 | } | |
4807 | ||
0a81f500 RE |
4808 | void |
4809 | arm_reload_in_hi (operands) | |
62b10bbc | 4810 | rtx * operands; |
0a81f500 | 4811 | { |
f9cc092a RE |
4812 | rtx ref = operands[1]; |
4813 | rtx base, scratch; | |
4814 | HOST_WIDE_INT offset = 0; | |
4815 | ||
4816 | if (GET_CODE (ref) == SUBREG) | |
4817 | { | |
ddef6bc7 | 4818 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
4819 | ref = SUBREG_REG (ref); |
4820 | } | |
4821 | ||
4822 | if (GET_CODE (ref) == REG) | |
4823 | { | |
4824 | /* We have a pseudo which has been spilt onto the stack; there | |
4825 | are two cases here: the first where there is a simple | |
4826 | stack-slot replacement and a second where the stack-slot is | |
4827 | out of range, or is used as a subreg. */ | |
4828 | if (reg_equiv_mem[REGNO (ref)]) | |
4829 | { | |
4830 | ref = reg_equiv_mem[REGNO (ref)]; | |
4831 | base = find_replacement (&XEXP (ref, 0)); | |
4832 | } | |
4833 | else | |
6354dc9b | 4834 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
4835 | base = reg_equiv_address[REGNO (ref)]; |
4836 | } | |
4837 | else | |
4838 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 4839 | |
e5e809f4 JL |
4840 | /* Handle the case where the address is too complex to be offset by 1. */ |
4841 | if (GET_CODE (base) == MINUS | |
4842 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
4843 | { | |
f9cc092a | 4844 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 4845 | |
43cffd11 | 4846 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); |
e5e809f4 JL |
4847 | base = base_plus; |
4848 | } | |
f9cc092a RE |
4849 | else if (GET_CODE (base) == PLUS) |
4850 | { | |
6354dc9b | 4851 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
4852 | HOST_WIDE_INT hi, lo; |
4853 | ||
4854 | offset += INTVAL (XEXP (base, 1)); | |
4855 | base = XEXP (base, 0); | |
4856 | ||
6354dc9b | 4857 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
4858 | /* Valid range for lo is -4095 -> 4095 */ |
4859 | lo = (offset >= 0 | |
4860 | ? (offset & 0xfff) | |
4861 | : -((-offset) & 0xfff)); | |
4862 | ||
4863 | /* Corner case, if lo is the max offset then we would be out of range | |
4864 | once we have added the additional 1 below, so bump the msb into the | |
4865 | pre-loading insn(s). */ | |
4866 | if (lo == 4095) | |
4867 | lo &= 0x7ff; | |
4868 | ||
e5951263 NC |
4869 | hi = ((((offset - lo) & HOST_INT (0xffffffff)) |
4870 | ^ HOST_INT (0x80000000)) | |
4871 | - HOST_INT (0x80000000)); | |
f9cc092a RE |
4872 | |
4873 | if (hi + lo != offset) | |
4874 | abort (); | |
4875 | ||
4876 | if (hi != 0) | |
4877 | { | |
4878 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
4879 | ||
4880 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 4881 | that require more than one insn. */ |
f9cc092a RE |
4882 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
4883 | base = base_plus; | |
4884 | offset = lo; | |
4885 | } | |
4886 | } | |
e5e809f4 | 4887 | |
f9cc092a RE |
4888 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); |
4889 | emit_insn (gen_zero_extendqisi2 (scratch, | |
4890 | gen_rtx_MEM (QImode, | |
4891 | plus_constant (base, | |
4892 | offset)))); | |
43cffd11 RE |
4893 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
4894 | gen_rtx_MEM (QImode, | |
f9cc092a RE |
4895 | plus_constant (base, |
4896 | offset + 1)))); | |
5895f793 | 4897 | if (!BYTES_BIG_ENDIAN) |
43cffd11 RE |
4898 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
4899 | gen_rtx_IOR (SImode, | |
4900 | gen_rtx_ASHIFT | |
4901 | (SImode, | |
4902 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
4903 | GEN_INT (8)), | |
f9cc092a | 4904 | scratch))); |
0a81f500 | 4905 | else |
43cffd11 RE |
4906 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
4907 | gen_rtx_IOR (SImode, | |
f9cc092a | 4908 | gen_rtx_ASHIFT (SImode, scratch, |
43cffd11 RE |
4909 | GEN_INT (8)), |
4910 | gen_rtx_SUBREG (SImode, operands[0], | |
4911 | 0)))); | |
0a81f500 RE |
4912 | } |
4913 | ||
f9cc092a RE |
4914 | /* Handle storing a half-word to memory during reload by synthesising as two |
4915 | byte stores. Take care not to clobber the input values until after we | |
4916 | have moved them somewhere safe. This code assumes that if the DImode | |
4917 | scratch in operands[2] overlaps either the input value or output address | |
4918 | in some way, then that value must die in this insn (we absolutely need | |
4919 | two scratch registers for some corner cases). */ | |
f3bb6135 | 4920 | void |
af48348a | 4921 | arm_reload_out_hi (operands) |
62b10bbc | 4922 | rtx * operands; |
af48348a | 4923 | { |
f9cc092a RE |
4924 | rtx ref = operands[0]; |
4925 | rtx outval = operands[1]; | |
4926 | rtx base, scratch; | |
4927 | HOST_WIDE_INT offset = 0; | |
4928 | ||
4929 | if (GET_CODE (ref) == SUBREG) | |
4930 | { | |
ddef6bc7 | 4931 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
4932 | ref = SUBREG_REG (ref); |
4933 | } | |
4934 | ||
4935 | ||
4936 | if (GET_CODE (ref) == REG) | |
4937 | { | |
4938 | /* We have a pseudo which has been spilt onto the stack; there | |
4939 | are two cases here: the first where there is a simple | |
4940 | stack-slot replacement and a second where the stack-slot is | |
4941 | out of range, or is used as a subreg. */ | |
4942 | if (reg_equiv_mem[REGNO (ref)]) | |
4943 | { | |
4944 | ref = reg_equiv_mem[REGNO (ref)]; | |
4945 | base = find_replacement (&XEXP (ref, 0)); | |
4946 | } | |
4947 | else | |
6354dc9b | 4948 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
4949 | base = reg_equiv_address[REGNO (ref)]; |
4950 | } | |
4951 | else | |
4952 | base = find_replacement (&XEXP (ref, 0)); | |
4953 | ||
4954 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
4955 | ||
4956 | /* Handle the case where the address is too complex to be offset by 1. */ | |
4957 | if (GET_CODE (base) == MINUS | |
4958 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
4959 | { | |
4960 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
4961 | ||
4962 | /* Be careful not to destroy OUTVAL. */ | |
4963 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
4964 | { | |
4965 | /* Updating base_plus might destroy outval, see if we can | |
4966 | swap the scratch and base_plus. */ | |
5895f793 | 4967 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
4968 | { |
4969 | rtx tmp = scratch; | |
4970 | scratch = base_plus; | |
4971 | base_plus = tmp; | |
4972 | } | |
4973 | else | |
4974 | { | |
4975 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
4976 | ||
4977 | /* Be conservative and copy OUTVAL into the scratch now, | |
4978 | this should only be necessary if outval is a subreg | |
4979 | of something larger than a word. */ | |
4980 | /* XXX Might this clobber base? I can't see how it can, | |
4981 | since scratch is known to overlap with OUTVAL, and | |
4982 | must be wider than a word. */ | |
4983 | emit_insn (gen_movhi (scratch_hi, outval)); | |
4984 | outval = scratch_hi; | |
4985 | } | |
4986 | } | |
4987 | ||
4988 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); | |
4989 | base = base_plus; | |
4990 | } | |
4991 | else if (GET_CODE (base) == PLUS) | |
4992 | { | |
6354dc9b | 4993 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
4994 | HOST_WIDE_INT hi, lo; |
4995 | ||
4996 | offset += INTVAL (XEXP (base, 1)); | |
4997 | base = XEXP (base, 0); | |
4998 | ||
6354dc9b | 4999 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
5000 | /* Valid range for lo is -4095 -> 4095 */ |
5001 | lo = (offset >= 0 | |
5002 | ? (offset & 0xfff) | |
5003 | : -((-offset) & 0xfff)); | |
5004 | ||
5005 | /* Corner case, if lo is the max offset then we would be out of range | |
5006 | once we have added the additional 1 below, so bump the msb into the | |
5007 | pre-loading insn(s). */ | |
5008 | if (lo == 4095) | |
5009 | lo &= 0x7ff; | |
5010 | ||
e5951263 NC |
5011 | hi = ((((offset - lo) & HOST_INT (0xffffffff)) |
5012 | ^ HOST_INT (0x80000000)) | |
5895f793 | 5013 | - HOST_INT (0x80000000)); |
f9cc092a RE |
5014 | |
5015 | if (hi + lo != offset) | |
5016 | abort (); | |
5017 | ||
5018 | if (hi != 0) | |
5019 | { | |
5020 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
5021 | ||
5022 | /* Be careful not to destroy OUTVAL. */ | |
5023 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
5024 | { | |
5025 | /* Updating base_plus might destroy outval, see if we | |
5026 | can swap the scratch and base_plus. */ | |
5895f793 | 5027 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
5028 | { |
5029 | rtx tmp = scratch; | |
5030 | scratch = base_plus; | |
5031 | base_plus = tmp; | |
5032 | } | |
5033 | else | |
5034 | { | |
5035 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
5036 | ||
5037 | /* Be conservative and copy outval into scratch now, | |
5038 | this should only be necessary if outval is a | |
5039 | subreg of something larger than a word. */ | |
5040 | /* XXX Might this clobber base? I can't see how it | |
5041 | can, since scratch is known to overlap with | |
5042 | outval. */ | |
5043 | emit_insn (gen_movhi (scratch_hi, outval)); | |
5044 | outval = scratch_hi; | |
5045 | } | |
5046 | } | |
5047 | ||
5048 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 5049 | that require more than one insn. */ |
f9cc092a RE |
5050 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
5051 | base = base_plus; | |
5052 | offset = lo; | |
5053 | } | |
5054 | } | |
af48348a | 5055 | |
b5cc037f RE |
5056 | if (BYTES_BIG_ENDIAN) |
5057 | { | |
f9cc092a RE |
5058 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
5059 | plus_constant (base, offset + 1)), | |
5060 | gen_rtx_SUBREG (QImode, outval, 0))); | |
5061 | emit_insn (gen_lshrsi3 (scratch, | |
5062 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 5063 | GEN_INT (8))); |
f9cc092a RE |
5064 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5065 | gen_rtx_SUBREG (QImode, scratch, 0))); | |
b5cc037f RE |
5066 | } |
5067 | else | |
5068 | { | |
f9cc092a RE |
5069 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5070 | gen_rtx_SUBREG (QImode, outval, 0))); | |
5071 | emit_insn (gen_lshrsi3 (scratch, | |
5072 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 5073 | GEN_INT (8))); |
f9cc092a RE |
5074 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
5075 | plus_constant (base, offset + 1)), | |
5076 | gen_rtx_SUBREG (QImode, scratch, 0))); | |
b5cc037f | 5077 | } |
af48348a | 5078 | } |
2b835d68 | 5079 | \f |
d5b7b3ae RE |
5080 | /* Print a symbolic form of X to the debug file, F. */ |
5081 | static void | |
5082 | arm_print_value (f, x) | |
5083 | FILE * f; | |
5084 | rtx x; | |
5085 | { | |
5086 | switch (GET_CODE (x)) | |
5087 | { | |
5088 | case CONST_INT: | |
5089 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
5090 | return; | |
5091 | ||
5092 | case CONST_DOUBLE: | |
5093 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
5094 | return; | |
5095 | ||
5096 | case CONST_STRING: | |
5097 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
5098 | return; | |
5099 | ||
5100 | case SYMBOL_REF: | |
5101 | fprintf (f, "`%s'", XSTR (x, 0)); | |
5102 | return; | |
5103 | ||
5104 | case LABEL_REF: | |
5105 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
5106 | return; | |
5107 | ||
5108 | case CONST: | |
5109 | arm_print_value (f, XEXP (x, 0)); | |
5110 | return; | |
5111 | ||
5112 | case PLUS: | |
5113 | arm_print_value (f, XEXP (x, 0)); | |
5114 | fprintf (f, "+"); | |
5115 | arm_print_value (f, XEXP (x, 1)); | |
5116 | return; | |
5117 | ||
5118 | case PC: | |
5119 | fprintf (f, "pc"); | |
5120 | return; | |
5121 | ||
5122 | default: | |
5123 | fprintf (f, "????"); | |
5124 | return; | |
5125 | } | |
5126 | } | |
5127 | \f | |
2b835d68 | 5128 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 5129 | |
949d79eb RE |
5130 | /* Arm instructions cannot load a large constant directly into a |
5131 | register; they have to come from a pc relative load. The constant | |
5132 | must therefore be placed in the addressable range of the pc | |
5133 | relative load. Depending on the precise pc relative load | |
5134 | instruction the range is somewhere between 256 bytes and 4k. This | |
5135 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
5136 | generate code to branch around it. |
5137 | ||
949d79eb RE |
5138 | It is important to minimize this, since the branches will slow |
5139 | things down and make the code larger. | |
2b835d68 | 5140 | |
949d79eb RE |
5141 | Normally we can hide the table after an existing unconditional |
5142 | branch so that there is no interruption of the flow, but in the | |
5143 | worst case the code looks like this: | |
2b835d68 RE |
5144 | |
5145 | ldr rn, L1 | |
949d79eb | 5146 | ... |
2b835d68 RE |
5147 | b L2 |
5148 | align | |
5149 | L1: .long value | |
5150 | L2: | |
949d79eb | 5151 | ... |
2b835d68 | 5152 | |
2b835d68 | 5153 | ldr rn, L3 |
949d79eb | 5154 | ... |
2b835d68 RE |
5155 | b L4 |
5156 | align | |
2b835d68 RE |
5157 | L3: .long value |
5158 | L4: | |
949d79eb RE |
5159 | ... |
5160 | ||
5161 | We fix this by performing a scan after scheduling, which notices | |
5162 | which instructions need to have their operands fetched from the | |
5163 | constant table and builds the table. | |
5164 | ||
5165 | The algorithm starts by building a table of all the constants that | |
5166 | need fixing up and all the natural barriers in the function (places | |
5167 | where a constant table can be dropped without breaking the flow). | |
5168 | For each fixup we note how far the pc-relative replacement will be | |
5169 | able to reach and the offset of the instruction into the function. | |
5170 | ||
5171 | Having built the table we then group the fixes together to form | |
5172 | tables that are as large as possible (subject to addressing | |
5173 | constraints) and emit each table of constants after the last | |
5174 | barrier that is within range of all the instructions in the group. | |
5175 | If a group does not contain a barrier, then we forcibly create one | |
5176 | by inserting a jump instruction into the flow. Once the table has | |
5177 | been inserted, the insns are then modified to reference the | |
5178 | relevant entry in the pool. | |
5179 | ||
6354dc9b | 5180 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 5181 | |
d5b7b3ae | 5182 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
5183 | aligning the pools to the start of cache lines; this alignment |
5184 | would need to be taken into account when calculating addressability | |
6354dc9b | 5185 | of a pool. */ |
2b835d68 | 5186 | |
d5b7b3ae RE |
5187 | /* These typedefs are located at the start of this file, so that |
5188 | they can be used in the prototypes there. This comment is to | |
5189 | remind readers of that fact so that the following structures | |
5190 | can be understood more easily. | |
5191 | ||
5192 | typedef struct minipool_node Mnode; | |
5193 | typedef struct minipool_fixup Mfix; */ | |
5194 | ||
5195 | struct minipool_node | |
5196 | { | |
5197 | /* Doubly linked chain of entries. */ | |
5198 | Mnode * next; | |
5199 | Mnode * prev; | |
5200 | /* The maximum offset into the code that this entry can be placed. While | |
5201 | pushing fixes for forward references, all entries are sorted in order | |
5202 | of increasing max_address. */ | |
5203 | HOST_WIDE_INT max_address; | |
5204 | /* Similarly for a entry inserted for a backwards ref. */ | |
5205 | HOST_WIDE_INT min_address; | |
5206 | /* The number of fixes referencing this entry. This can become zero | |
5207 | if we "unpush" an entry. In this case we ignore the entry when we | |
5208 | come to emit the code. */ | |
5209 | int refcount; | |
5210 | /* The offset from the start of the minipool. */ | |
5211 | HOST_WIDE_INT offset; | |
5212 | /* The value in table. */ | |
5213 | rtx value; | |
5214 | /* The mode of value. */ | |
5215 | enum machine_mode mode; | |
5216 | int fix_size; | |
5217 | }; | |
5218 | ||
5219 | struct minipool_fixup | |
2b835d68 | 5220 | { |
d5b7b3ae RE |
5221 | Mfix * next; |
5222 | rtx insn; | |
5223 | HOST_WIDE_INT address; | |
5224 | rtx * loc; | |
5225 | enum machine_mode mode; | |
5226 | int fix_size; | |
5227 | rtx value; | |
5228 | Mnode * minipool; | |
5229 | HOST_WIDE_INT forwards; | |
5230 | HOST_WIDE_INT backwards; | |
5231 | }; | |
2b835d68 | 5232 | |
d5b7b3ae RE |
5233 | /* Fixes less than a word need padding out to a word boundary. */ |
5234 | #define MINIPOOL_FIX_SIZE(mode) \ | |
5235 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 5236 | |
d5b7b3ae RE |
5237 | static Mnode * minipool_vector_head; |
5238 | static Mnode * minipool_vector_tail; | |
5239 | static rtx minipool_vector_label; | |
332072db | 5240 | |
d5b7b3ae RE |
5241 | /* The linked list of all minipool fixes required for this function. */ |
5242 | Mfix * minipool_fix_head; | |
5243 | Mfix * minipool_fix_tail; | |
5244 | /* The fix entry for the current minipool, once it has been placed. */ | |
5245 | Mfix * minipool_barrier; | |
5246 | ||
5247 | /* Determines if INSN is the start of a jump table. Returns the end | |
5248 | of the TABLE or NULL_RTX. */ | |
5249 | static rtx | |
5250 | is_jump_table (insn) | |
5251 | rtx insn; | |
2b835d68 | 5252 | { |
d5b7b3ae | 5253 | rtx table; |
da6558fd | 5254 | |
d5b7b3ae RE |
5255 | if (GET_CODE (insn) == JUMP_INSN |
5256 | && JUMP_LABEL (insn) != NULL | |
5257 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
5258 | == next_real_insn (insn)) | |
5259 | && table != NULL | |
5260 | && GET_CODE (table) == JUMP_INSN | |
5261 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
5262 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
5263 | return table; | |
5264 | ||
5265 | return NULL_RTX; | |
2b835d68 RE |
5266 | } |
5267 | ||
d5b7b3ae RE |
5268 | static HOST_WIDE_INT |
5269 | get_jump_table_size (insn) | |
5270 | rtx insn; | |
2b835d68 | 5271 | { |
d5b7b3ae RE |
5272 | rtx body = PATTERN (insn); |
5273 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
2b835d68 | 5274 | |
d5b7b3ae RE |
5275 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); |
5276 | } | |
2b835d68 | 5277 | |
d5b7b3ae RE |
5278 | /* Move a minipool fix MP from its current location to before MAX_MP. |
5279 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
5280 | contrains may need updating. */ | |
5281 | static Mnode * | |
5282 | move_minipool_fix_forward_ref (mp, max_mp, max_address) | |
5283 | Mnode * mp; | |
5284 | Mnode * max_mp; | |
5285 | HOST_WIDE_INT max_address; | |
5286 | { | |
5287 | /* This should never be true and the code below assumes these are | |
5288 | different. */ | |
5289 | if (mp == max_mp) | |
5290 | abort (); | |
5291 | ||
5292 | if (max_mp == NULL) | |
5293 | { | |
5294 | if (max_address < mp->max_address) | |
5295 | mp->max_address = max_address; | |
5296 | } | |
5297 | else | |
2b835d68 | 5298 | { |
d5b7b3ae RE |
5299 | if (max_address > max_mp->max_address - mp->fix_size) |
5300 | mp->max_address = max_mp->max_address - mp->fix_size; | |
5301 | else | |
5302 | mp->max_address = max_address; | |
2b835d68 | 5303 | |
d5b7b3ae RE |
5304 | /* Unlink MP from its current position. Since max_mp is non-null, |
5305 | mp->prev must be non-null. */ | |
5306 | mp->prev->next = mp->next; | |
5307 | if (mp->next != NULL) | |
5308 | mp->next->prev = mp->prev; | |
5309 | else | |
5310 | minipool_vector_tail = mp->prev; | |
2b835d68 | 5311 | |
d5b7b3ae RE |
5312 | /* Re-insert it before MAX_MP. */ |
5313 | mp->next = max_mp; | |
5314 | mp->prev = max_mp->prev; | |
5315 | max_mp->prev = mp; | |
5316 | ||
5317 | if (mp->prev != NULL) | |
5318 | mp->prev->next = mp; | |
5319 | else | |
5320 | minipool_vector_head = mp; | |
5321 | } | |
2b835d68 | 5322 | |
d5b7b3ae RE |
5323 | /* Save the new entry. */ |
5324 | max_mp = mp; | |
5325 | ||
5326 | /* Scan over the preceeding entries and adjust their addresses as | |
5327 | required. */ | |
5328 | while (mp->prev != NULL | |
5329 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
5330 | { | |
5331 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
5332 | mp = mp->prev; | |
2b835d68 RE |
5333 | } |
5334 | ||
d5b7b3ae | 5335 | return max_mp; |
2b835d68 RE |
5336 | } |
5337 | ||
d5b7b3ae RE |
5338 | /* Add a constant to the minipool for a forward reference. Returns the |
5339 | node added or NULL if the constant will not fit in this pool. */ | |
5340 | static Mnode * | |
5341 | add_minipool_forward_ref (fix) | |
5342 | Mfix * fix; | |
5343 | { | |
5344 | /* If set, max_mp is the first pool_entry that has a lower | |
5345 | constraint than the one we are trying to add. */ | |
5346 | Mnode * max_mp = NULL; | |
5347 | HOST_WIDE_INT max_address = fix->address + fix->forwards; | |
5348 | Mnode * mp; | |
5349 | ||
5350 | /* If this fix's address is greater than the address of the first | |
5351 | entry, then we can't put the fix in this pool. We subtract the | |
5352 | size of the current fix to ensure that if the table is fully | |
5353 | packed we still have enough room to insert this value by suffling | |
5354 | the other fixes forwards. */ | |
5355 | if (minipool_vector_head && | |
5356 | fix->address >= minipool_vector_head->max_address - fix->fix_size) | |
5357 | return NULL; | |
2b835d68 | 5358 | |
d5b7b3ae RE |
5359 | /* Scan the pool to see if a constant with the same value has |
5360 | already been added. While we are doing this, also note the | |
5361 | location where we must insert the constant if it doesn't already | |
5362 | exist. */ | |
5363 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
5364 | { | |
5365 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
5366 | && fix->mode == mp->mode | |
5367 | && (GET_CODE (fix->value) != CODE_LABEL | |
5368 | || (CODE_LABEL_NUMBER (fix->value) | |
5369 | == CODE_LABEL_NUMBER (mp->value))) | |
5370 | && rtx_equal_p (fix->value, mp->value)) | |
5371 | { | |
5372 | /* More than one fix references this entry. */ | |
5373 | mp->refcount++; | |
5374 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
5375 | } | |
5376 | ||
5377 | /* Note the insertion point if necessary. */ | |
5378 | if (max_mp == NULL | |
5379 | && mp->max_address > max_address) | |
5380 | max_mp = mp; | |
5381 | } | |
5382 | ||
5383 | /* The value is not currently in the minipool, so we need to create | |
5384 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
5385 | the end of the list since the placement is less constrained than | |
5386 | any existing entry. Otherwise, we insert the new fix before | |
5387 | MAX_MP and, if neceesary, adjust the constraints on the other | |
5388 | entries. */ | |
5389 | mp = xmalloc (sizeof (* mp)); | |
5390 | mp->fix_size = fix->fix_size; | |
5391 | mp->mode = fix->mode; | |
5392 | mp->value = fix->value; | |
5393 | mp->refcount = 1; | |
5394 | /* Not yet required for a backwards ref. */ | |
5395 | mp->min_address = -65536; | |
5396 | ||
5397 | if (max_mp == NULL) | |
5398 | { | |
5399 | mp->max_address = max_address; | |
5400 | mp->next = NULL; | |
5401 | mp->prev = minipool_vector_tail; | |
5402 | ||
5403 | if (mp->prev == NULL) | |
5404 | { | |
5405 | minipool_vector_head = mp; | |
5406 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 5407 | } |
2b835d68 | 5408 | else |
d5b7b3ae | 5409 | mp->prev->next = mp; |
2b835d68 | 5410 | |
d5b7b3ae RE |
5411 | minipool_vector_tail = mp; |
5412 | } | |
5413 | else | |
5414 | { | |
5415 | if (max_address > max_mp->max_address - mp->fix_size) | |
5416 | mp->max_address = max_mp->max_address - mp->fix_size; | |
5417 | else | |
5418 | mp->max_address = max_address; | |
5419 | ||
5420 | mp->next = max_mp; | |
5421 | mp->prev = max_mp->prev; | |
5422 | max_mp->prev = mp; | |
5423 | if (mp->prev != NULL) | |
5424 | mp->prev->next = mp; | |
5425 | else | |
5426 | minipool_vector_head = mp; | |
5427 | } | |
5428 | ||
5429 | /* Save the new entry. */ | |
5430 | max_mp = mp; | |
5431 | ||
5432 | /* Scan over the preceeding entries and adjust their addresses as | |
5433 | required. */ | |
5434 | while (mp->prev != NULL | |
5435 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
5436 | { | |
5437 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
5438 | mp = mp->prev; | |
2b835d68 RE |
5439 | } |
5440 | ||
d5b7b3ae RE |
5441 | return max_mp; |
5442 | } | |
5443 | ||
5444 | static Mnode * | |
5445 | move_minipool_fix_backward_ref (mp, min_mp, min_address) | |
5446 | Mnode * mp; | |
5447 | Mnode * min_mp; | |
5448 | HOST_WIDE_INT min_address; | |
5449 | { | |
5450 | HOST_WIDE_INT offset; | |
5451 | ||
5452 | /* This should never be true, and the code below assumes these are | |
5453 | different. */ | |
5454 | if (mp == min_mp) | |
5455 | abort (); | |
5456 | ||
5457 | if (min_mp == NULL) | |
2b835d68 | 5458 | { |
d5b7b3ae RE |
5459 | if (min_address > mp->min_address) |
5460 | mp->min_address = min_address; | |
5461 | } | |
5462 | else | |
5463 | { | |
5464 | /* We will adjust this below if it is too loose. */ | |
5465 | mp->min_address = min_address; | |
5466 | ||
5467 | /* Unlink MP from its current position. Since min_mp is non-null, | |
5468 | mp->next must be non-null. */ | |
5469 | mp->next->prev = mp->prev; | |
5470 | if (mp->prev != NULL) | |
5471 | mp->prev->next = mp->next; | |
5472 | else | |
5473 | minipool_vector_head = mp->next; | |
5474 | ||
5475 | /* Reinsert it after MIN_MP. */ | |
5476 | mp->prev = min_mp; | |
5477 | mp->next = min_mp->next; | |
5478 | min_mp->next = mp; | |
5479 | if (mp->next != NULL) | |
5480 | mp->next->prev = mp; | |
2b835d68 | 5481 | else |
d5b7b3ae RE |
5482 | minipool_vector_tail = mp; |
5483 | } | |
5484 | ||
5485 | min_mp = mp; | |
5486 | ||
5487 | offset = 0; | |
5488 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
5489 | { | |
5490 | mp->offset = offset; | |
5491 | if (mp->refcount > 0) | |
5492 | offset += mp->fix_size; | |
5493 | ||
5494 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
5495 | mp->next->min_address = mp->min_address + mp->fix_size; | |
5496 | } | |
5497 | ||
5498 | return min_mp; | |
5499 | } | |
5500 | ||
5501 | /* Add a constant to the minipool for a backward reference. Returns the | |
5502 | node added or NULL if the constant will not fit in this pool. | |
5503 | ||
5504 | Note that the code for insertion for a backwards reference can be | |
5505 | somewhat confusing because the calculated offsets for each fix do | |
5506 | not take into account the size of the pool (which is still under | |
5507 | construction. */ | |
5508 | static Mnode * | |
5509 | add_minipool_backward_ref (fix) | |
5510 | Mfix * fix; | |
5511 | { | |
5512 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
5513 | than the one we are trying to add. */ | |
5514 | Mnode * min_mp = NULL; | |
5515 | /* This can be negative, since it is only a constraint. */ | |
5516 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
5517 | Mnode * mp; | |
5518 | ||
5519 | /* If we can't reach the current pool from this insn, or if we can't | |
5520 | insert this entry at the end of the pool without pushing other | |
5521 | fixes out of range, then we don't try. This ensures that we | |
5522 | can't fail later on. */ | |
5523 | if (min_address >= minipool_barrier->address | |
5524 | || (minipool_vector_tail->min_address + fix->fix_size | |
5525 | >= minipool_barrier->address)) | |
5526 | return NULL; | |
5527 | ||
5528 | /* Scan the pool to see if a constant with the same value has | |
5529 | already been added. While we are doing this, also note the | |
5530 | location where we must insert the constant if it doesn't already | |
5531 | exist. */ | |
5532 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
5533 | { | |
5534 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
5535 | && fix->mode == mp->mode | |
5536 | && (GET_CODE (fix->value) != CODE_LABEL | |
5537 | || (CODE_LABEL_NUMBER (fix->value) | |
5538 | == CODE_LABEL_NUMBER (mp->value))) | |
5539 | && rtx_equal_p (fix->value, mp->value) | |
5540 | /* Check that there is enough slack to move this entry to the | |
5541 | end of the table (this is conservative). */ | |
5542 | && (mp->max_address | |
5543 | > (minipool_barrier->address | |
5544 | + minipool_vector_tail->offset | |
5545 | + minipool_vector_tail->fix_size))) | |
5546 | { | |
5547 | mp->refcount++; | |
5548 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
5549 | } | |
5550 | ||
5551 | if (min_mp != NULL) | |
5552 | mp->min_address += fix->fix_size; | |
5553 | else | |
5554 | { | |
5555 | /* Note the insertion point if necessary. */ | |
5556 | if (mp->min_address < min_address) | |
5557 | min_mp = mp; | |
5558 | else if (mp->max_address | |
5559 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
5560 | { | |
5561 | /* Inserting before this entry would push the fix beyond | |
5562 | its maximum address (which can happen if we have | |
5563 | re-located a forwards fix); force the new fix to come | |
5564 | after it. */ | |
5565 | min_mp = mp; | |
5566 | min_address = mp->min_address + fix->fix_size; | |
5567 | } | |
5568 | } | |
5569 | } | |
5570 | ||
5571 | /* We need to create a new entry. */ | |
5572 | mp = xmalloc (sizeof (* mp)); | |
5573 | mp->fix_size = fix->fix_size; | |
5574 | mp->mode = fix->mode; | |
5575 | mp->value = fix->value; | |
5576 | mp->refcount = 1; | |
5577 | mp->max_address = minipool_barrier->address + 65536; | |
5578 | ||
5579 | mp->min_address = min_address; | |
5580 | ||
5581 | if (min_mp == NULL) | |
5582 | { | |
5583 | mp->prev = NULL; | |
5584 | mp->next = minipool_vector_head; | |
5585 | ||
5586 | if (mp->next == NULL) | |
5587 | { | |
5588 | minipool_vector_tail = mp; | |
5589 | minipool_vector_label = gen_label_rtx (); | |
5590 | } | |
5591 | else | |
5592 | mp->next->prev = mp; | |
5593 | ||
5594 | minipool_vector_head = mp; | |
5595 | } | |
5596 | else | |
5597 | { | |
5598 | mp->next = min_mp->next; | |
5599 | mp->prev = min_mp; | |
5600 | min_mp->next = mp; | |
da6558fd | 5601 | |
d5b7b3ae RE |
5602 | if (mp->next != NULL) |
5603 | mp->next->prev = mp; | |
5604 | else | |
5605 | minipool_vector_tail = mp; | |
5606 | } | |
5607 | ||
5608 | /* Save the new entry. */ | |
5609 | min_mp = mp; | |
5610 | ||
5611 | if (mp->prev) | |
5612 | mp = mp->prev; | |
5613 | else | |
5614 | mp->offset = 0; | |
5615 | ||
5616 | /* Scan over the following entries and adjust their offsets. */ | |
5617 | while (mp->next != NULL) | |
5618 | { | |
5619 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
5620 | mp->next->min_address = mp->min_address + mp->fix_size; | |
5621 | ||
5622 | if (mp->refcount) | |
5623 | mp->next->offset = mp->offset + mp->fix_size; | |
5624 | else | |
5625 | mp->next->offset = mp->offset; | |
5626 | ||
5627 | mp = mp->next; | |
5628 | } | |
5629 | ||
5630 | return min_mp; | |
5631 | } | |
5632 | ||
5633 | static void | |
5634 | assign_minipool_offsets (barrier) | |
5635 | Mfix * barrier; | |
5636 | { | |
5637 | HOST_WIDE_INT offset = 0; | |
5638 | Mnode * mp; | |
5639 | ||
5640 | minipool_barrier = barrier; | |
5641 | ||
5642 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
5643 | { | |
5644 | mp->offset = offset; | |
da6558fd | 5645 | |
d5b7b3ae RE |
5646 | if (mp->refcount > 0) |
5647 | offset += mp->fix_size; | |
5648 | } | |
5649 | } | |
5650 | ||
5651 | /* Output the literal table */ | |
5652 | static void | |
5653 | dump_minipool (scan) | |
5654 | rtx scan; | |
5655 | { | |
5656 | Mnode * mp; | |
5657 | Mnode * nmp; | |
5658 | ||
5659 | if (rtl_dump_file) | |
5660 | fprintf (rtl_dump_file, | |
5661 | ";; Emitting minipool after insn %u; address %ld\n", | |
5662 | INSN_UID (scan), (unsigned long) minipool_barrier->address); | |
5663 | ||
5664 | scan = emit_label_after (gen_label_rtx (), scan); | |
5665 | scan = emit_insn_after (gen_align_4 (), scan); | |
5666 | scan = emit_label_after (minipool_vector_label, scan); | |
5667 | ||
5668 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
5669 | { | |
5670 | if (mp->refcount > 0) | |
5671 | { | |
5672 | if (rtl_dump_file) | |
5673 | { | |
5674 | fprintf (rtl_dump_file, | |
5675 | ";; Offset %u, min %ld, max %ld ", | |
5676 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
5677 | (unsigned long) mp->max_address); | |
5678 | arm_print_value (rtl_dump_file, mp->value); | |
5679 | fputc ('\n', rtl_dump_file); | |
5680 | } | |
5681 | ||
5682 | switch (mp->fix_size) | |
5683 | { | |
5684 | #ifdef HAVE_consttable_1 | |
5685 | case 1: | |
5686 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
5687 | break; | |
5688 | ||
5689 | #endif | |
5690 | #ifdef HAVE_consttable_2 | |
5691 | case 2: | |
5692 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
5693 | break; | |
5694 | ||
5695 | #endif | |
5696 | #ifdef HAVE_consttable_4 | |
5697 | case 4: | |
5698 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
5699 | break; | |
5700 | ||
5701 | #endif | |
5702 | #ifdef HAVE_consttable_8 | |
5703 | case 8: | |
5704 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
5705 | break; | |
5706 | ||
5707 | #endif | |
5708 | default: | |
5709 | abort (); | |
5710 | break; | |
5711 | } | |
5712 | } | |
5713 | ||
5714 | nmp = mp->next; | |
5715 | free (mp); | |
2b835d68 RE |
5716 | } |
5717 | ||
d5b7b3ae RE |
5718 | minipool_vector_head = minipool_vector_tail = NULL; |
5719 | scan = emit_insn_after (gen_consttable_end (), scan); | |
5720 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
5721 | } |
5722 | ||
d5b7b3ae RE |
5723 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
5724 | static int | |
5725 | arm_barrier_cost (insn) | |
5726 | rtx insn; | |
949d79eb | 5727 | { |
d5b7b3ae RE |
5728 | /* Basing the location of the pool on the loop depth is preferable, |
5729 | but at the moment, the basic block information seems to be | |
5730 | corrupt by this stage of the compilation. */ | |
5731 | int base_cost = 50; | |
5732 | rtx next = next_nonnote_insn (insn); | |
5733 | ||
5734 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
5735 | base_cost -= 20; | |
5736 | ||
5737 | switch (GET_CODE (insn)) | |
5738 | { | |
5739 | case CODE_LABEL: | |
5740 | /* It will always be better to place the table before the label, rather | |
5741 | than after it. */ | |
5742 | return 50; | |
949d79eb | 5743 | |
d5b7b3ae RE |
5744 | case INSN: |
5745 | case CALL_INSN: | |
5746 | return base_cost; | |
5747 | ||
5748 | case JUMP_INSN: | |
5749 | return base_cost - 10; | |
5750 | ||
5751 | default: | |
5752 | return base_cost + 10; | |
5753 | } | |
5754 | } | |
5755 | ||
5756 | /* Find the best place in the insn stream in the range | |
5757 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
5758 | Create the barrier by inserting a jump and add a new fix entry for | |
5759 | it. */ | |
5760 | static Mfix * | |
5761 | create_fix_barrier (fix, max_address) | |
5762 | Mfix * fix; | |
5763 | HOST_WIDE_INT max_address; | |
5764 | { | |
5765 | HOST_WIDE_INT count = 0; | |
5766 | rtx barrier; | |
5767 | rtx from = fix->insn; | |
5768 | rtx selected = from; | |
5769 | int selected_cost; | |
5770 | HOST_WIDE_INT selected_address; | |
5771 | Mfix * new_fix; | |
5772 | HOST_WIDE_INT max_count = max_address - fix->address; | |
5773 | rtx label = gen_label_rtx (); | |
5774 | ||
5775 | selected_cost = arm_barrier_cost (from); | |
5776 | selected_address = fix->address; | |
5777 | ||
5778 | while (from && count < max_count) | |
5779 | { | |
5780 | rtx tmp; | |
5781 | int new_cost; | |
5782 | ||
5783 | /* This code shouldn't have been called if there was a natural barrier | |
5784 | within range. */ | |
5785 | if (GET_CODE (from) == BARRIER) | |
5786 | abort (); | |
5787 | ||
5788 | /* Count the length of this insn. */ | |
5789 | count += get_attr_length (from); | |
5790 | ||
5791 | /* If there is a jump table, add its length. */ | |
5792 | tmp = is_jump_table (from); | |
5793 | if (tmp != NULL) | |
5794 | { | |
5795 | count += get_jump_table_size (tmp); | |
5796 | ||
5797 | /* Jump tables aren't in a basic block, so base the cost on | |
5798 | the dispatch insn. If we select this location, we will | |
5799 | still put the pool after the table. */ | |
5800 | new_cost = arm_barrier_cost (from); | |
5801 | ||
5802 | if (count < max_count && new_cost <= selected_cost) | |
5803 | { | |
5804 | selected = tmp; | |
5805 | selected_cost = new_cost; | |
5806 | selected_address = fix->address + count; | |
5807 | } | |
5808 | ||
5809 | /* Continue after the dispatch table. */ | |
5810 | from = NEXT_INSN (tmp); | |
5811 | continue; | |
5812 | } | |
5813 | ||
5814 | new_cost = arm_barrier_cost (from); | |
5815 | ||
5816 | if (count < max_count && new_cost <= selected_cost) | |
5817 | { | |
5818 | selected = from; | |
5819 | selected_cost = new_cost; | |
5820 | selected_address = fix->address + count; | |
5821 | } | |
5822 | ||
5823 | from = NEXT_INSN (from); | |
5824 | } | |
5825 | ||
5826 | /* Create a new JUMP_INSN that branches around a barrier. */ | |
5827 | from = emit_jump_insn_after (gen_jump (label), selected); | |
5828 | JUMP_LABEL (from) = label; | |
5829 | barrier = emit_barrier_after (from); | |
5830 | emit_label_after (label, barrier); | |
5831 | ||
5832 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 5833 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
5834 | new_fix->insn = barrier; |
5835 | new_fix->address = selected_address; | |
5836 | new_fix->next = fix->next; | |
5837 | fix->next = new_fix; | |
5838 | ||
5839 | return new_fix; | |
5840 | } | |
5841 | ||
5842 | /* Record that there is a natural barrier in the insn stream at | |
5843 | ADDRESS. */ | |
949d79eb RE |
5844 | static void |
5845 | push_minipool_barrier (insn, address) | |
2b835d68 | 5846 | rtx insn; |
d5b7b3ae | 5847 | HOST_WIDE_INT address; |
2b835d68 | 5848 | { |
c7319d87 | 5849 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 5850 | |
949d79eb RE |
5851 | fix->insn = insn; |
5852 | fix->address = address; | |
2b835d68 | 5853 | |
949d79eb RE |
5854 | fix->next = NULL; |
5855 | if (minipool_fix_head != NULL) | |
5856 | minipool_fix_tail->next = fix; | |
5857 | else | |
5858 | minipool_fix_head = fix; | |
5859 | ||
5860 | minipool_fix_tail = fix; | |
5861 | } | |
2b835d68 | 5862 | |
d5b7b3ae RE |
5863 | /* Record INSN, which will need fixing up to load a value from the |
5864 | minipool. ADDRESS is the offset of the insn since the start of the | |
5865 | function; LOC is a pointer to the part of the insn which requires | |
5866 | fixing; VALUE is the constant that must be loaded, which is of type | |
5867 | MODE. */ | |
949d79eb RE |
5868 | static void |
5869 | push_minipool_fix (insn, address, loc, mode, value) | |
5870 | rtx insn; | |
d5b7b3ae RE |
5871 | HOST_WIDE_INT address; |
5872 | rtx * loc; | |
949d79eb RE |
5873 | enum machine_mode mode; |
5874 | rtx value; | |
5875 | { | |
c7319d87 | 5876 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb RE |
5877 | |
5878 | #ifdef AOF_ASSEMBLER | |
5879 | /* PIC symbol refereneces need to be converted into offsets into the | |
5880 | based area. */ | |
d5b7b3ae RE |
5881 | /* XXX This shouldn't be done here. */ |
5882 | if (flag_pic && GET_CODE (value) == SYMBOL_REF) | |
949d79eb RE |
5883 | value = aof_pic_entry (value); |
5884 | #endif /* AOF_ASSEMBLER */ | |
5885 | ||
5886 | fix->insn = insn; | |
5887 | fix->address = address; | |
5888 | fix->loc = loc; | |
5889 | fix->mode = mode; | |
d5b7b3ae | 5890 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 5891 | fix->value = value; |
d5b7b3ae RE |
5892 | fix->forwards = get_attr_pool_range (insn); |
5893 | fix->backwards = get_attr_neg_pool_range (insn); | |
5894 | fix->minipool = NULL; | |
949d79eb RE |
5895 | |
5896 | /* If an insn doesn't have a range defined for it, then it isn't | |
5897 | expecting to be reworked by this code. Better to abort now than | |
5898 | to generate duff assembly code. */ | |
d5b7b3ae | 5899 | if (fix->forwards == 0 && fix->backwards == 0) |
949d79eb RE |
5900 | abort (); |
5901 | ||
d5b7b3ae RE |
5902 | if (rtl_dump_file) |
5903 | { | |
5904 | fprintf (rtl_dump_file, | |
5905 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", | |
5906 | GET_MODE_NAME (mode), | |
5907 | INSN_UID (insn), (unsigned long) address, | |
5908 | -1 * (long)fix->backwards, (long)fix->forwards); | |
5909 | arm_print_value (rtl_dump_file, fix->value); | |
5910 | fprintf (rtl_dump_file, "\n"); | |
5911 | } | |
5912 | ||
6354dc9b | 5913 | /* Add it to the chain of fixes. */ |
949d79eb | 5914 | fix->next = NULL; |
d5b7b3ae | 5915 | |
949d79eb RE |
5916 | if (minipool_fix_head != NULL) |
5917 | minipool_fix_tail->next = fix; | |
5918 | else | |
5919 | minipool_fix_head = fix; | |
5920 | ||
5921 | minipool_fix_tail = fix; | |
5922 | } | |
5923 | ||
d5b7b3ae | 5924 | /* Scan INSN and note any of its operands that need fixing. */ |
949d79eb RE |
5925 | static void |
5926 | note_invalid_constants (insn, address) | |
5927 | rtx insn; | |
d5b7b3ae | 5928 | HOST_WIDE_INT address; |
949d79eb RE |
5929 | { |
5930 | int opno; | |
5931 | ||
d5b7b3ae | 5932 | extract_insn (insn); |
949d79eb | 5933 | |
5895f793 | 5934 | if (!constrain_operands (1)) |
949d79eb RE |
5935 | fatal_insn_not_found (insn); |
5936 | ||
d5b7b3ae RE |
5937 | /* Fill in recog_op_alt with information about the constraints of this |
5938 | insn. */ | |
949d79eb RE |
5939 | preprocess_constraints (); |
5940 | ||
1ccbefce | 5941 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 5942 | { |
6354dc9b | 5943 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 5944 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
5945 | continue; |
5946 | ||
5947 | /* If this alternative is a memory reference, then any mention | |
5948 | of constants in this alternative is really to fool reload | |
5949 | into allowing us to accept one there. We need to fix them up | |
5950 | now so that we output the right code. */ | |
5951 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
5952 | { | |
1ccbefce | 5953 | rtx op = recog_data.operand[opno]; |
949d79eb RE |
5954 | |
5955 | if (CONSTANT_P (op)) | |
1ccbefce RH |
5956 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], |
5957 | recog_data.operand_mode[opno], op); | |
d5b7b3ae RE |
5958 | #if 0 |
5959 | /* RWE: Now we look correctly at the operands for the insn, | |
5960 | this shouldn't be needed any more. */ | |
949d79eb | 5961 | #ifndef AOF_ASSEMBLER |
d5b7b3ae | 5962 | /* XXX Is this still needed? */ |
b15bca31 | 5963 | else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM) |
1ccbefce RH |
5964 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], |
5965 | recog_data.operand_mode[opno], | |
5966 | XVECEXP (op, 0, 0)); | |
949d79eb | 5967 | #endif |
d5b7b3ae RE |
5968 | #endif |
5969 | else if (GET_CODE (op) == MEM | |
949d79eb RE |
5970 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
5971 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
1ccbefce RH |
5972 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], |
5973 | recog_data.operand_mode[opno], | |
949d79eb RE |
5974 | get_pool_constant (XEXP (op, 0))); |
5975 | } | |
2b835d68 | 5976 | } |
2b835d68 RE |
5977 | } |
5978 | ||
5979 | void | |
5980 | arm_reorg (first) | |
5981 | rtx first; | |
5982 | { | |
5983 | rtx insn; | |
d5b7b3ae RE |
5984 | HOST_WIDE_INT address = 0; |
5985 | Mfix * fix; | |
ad076f4e | 5986 | |
949d79eb | 5987 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 5988 | |
949d79eb RE |
5989 | /* The first insn must always be a note, or the code below won't |
5990 | scan it properly. */ | |
5991 | if (GET_CODE (first) != NOTE) | |
5992 | abort (); | |
5993 | ||
5994 | /* Scan all the insns and record the operands that will need fixing. */ | |
5995 | for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn)) | |
2b835d68 | 5996 | { |
949d79eb | 5997 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 5998 | push_minipool_barrier (insn, address); |
949d79eb RE |
5999 | else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN |
6000 | || GET_CODE (insn) == JUMP_INSN) | |
6001 | { | |
6002 | rtx table; | |
6003 | ||
6004 | note_invalid_constants (insn, address); | |
6005 | address += get_attr_length (insn); | |
d5b7b3ae | 6006 | |
949d79eb RE |
6007 | /* If the insn is a vector jump, add the size of the table |
6008 | and skip the table. */ | |
d5b7b3ae | 6009 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 6010 | { |
d5b7b3ae | 6011 | address += get_jump_table_size (table); |
949d79eb RE |
6012 | insn = table; |
6013 | } | |
6014 | } | |
6015 | } | |
332072db | 6016 | |
d5b7b3ae RE |
6017 | fix = minipool_fix_head; |
6018 | ||
949d79eb | 6019 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 6020 | while (fix) |
949d79eb | 6021 | { |
d5b7b3ae RE |
6022 | Mfix * ftmp; |
6023 | Mfix * fdel; | |
6024 | Mfix * last_added_fix; | |
6025 | Mfix * last_barrier = NULL; | |
6026 | Mfix * this_fix; | |
949d79eb RE |
6027 | |
6028 | /* Skip any further barriers before the next fix. */ | |
6029 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
6030 | fix = fix->next; | |
6031 | ||
d5b7b3ae | 6032 | /* No more fixes. */ |
949d79eb RE |
6033 | if (fix == NULL) |
6034 | break; | |
332072db | 6035 | |
d5b7b3ae | 6036 | last_added_fix = NULL; |
2b835d68 | 6037 | |
d5b7b3ae | 6038 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 6039 | { |
949d79eb | 6040 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 6041 | { |
d5b7b3ae RE |
6042 | if (ftmp->address >= minipool_vector_head->max_address) |
6043 | break; | |
2b835d68 | 6044 | |
d5b7b3ae | 6045 | last_barrier = ftmp; |
2b835d68 | 6046 | } |
d5b7b3ae RE |
6047 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
6048 | break; | |
6049 | ||
6050 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 6051 | } |
949d79eb | 6052 | |
d5b7b3ae RE |
6053 | /* If we found a barrier, drop back to that; any fixes that we |
6054 | could have reached but come after the barrier will now go in | |
6055 | the next mini-pool. */ | |
949d79eb RE |
6056 | if (last_barrier != NULL) |
6057 | { | |
d5b7b3ae RE |
6058 | /* Reduce the refcount for those fixes that won't go into this |
6059 | pool after all. */ | |
6060 | for (fdel = last_barrier->next; | |
6061 | fdel && fdel != ftmp; | |
6062 | fdel = fdel->next) | |
6063 | { | |
6064 | fdel->minipool->refcount--; | |
6065 | fdel->minipool = NULL; | |
6066 | } | |
6067 | ||
949d79eb RE |
6068 | ftmp = last_barrier; |
6069 | } | |
6070 | else | |
2bfa88dc | 6071 | { |
d5b7b3ae RE |
6072 | /* ftmp is first fix that we can't fit into this pool and |
6073 | there no natural barriers that we could use. Insert a | |
6074 | new barrier in the code somewhere between the previous | |
6075 | fix and this one, and arrange to jump around it. */ | |
6076 | HOST_WIDE_INT max_address; | |
6077 | ||
6078 | /* The last item on the list of fixes must be a barrier, so | |
6079 | we can never run off the end of the list of fixes without | |
6080 | last_barrier being set. */ | |
6081 | if (ftmp == NULL) | |
6082 | abort (); | |
6083 | ||
6084 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
6085 | /* Check that there isn't another fix that is in range that |
6086 | we couldn't fit into this pool because the pool was | |
6087 | already too large: we need to put the pool before such an | |
6088 | instruction. */ | |
d5b7b3ae RE |
6089 | if (ftmp->address < max_address) |
6090 | max_address = ftmp->address; | |
6091 | ||
6092 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
6093 | } | |
6094 | ||
6095 | assign_minipool_offsets (last_barrier); | |
6096 | ||
6097 | while (ftmp) | |
6098 | { | |
6099 | if (GET_CODE (ftmp->insn) != BARRIER | |
6100 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
6101 | == NULL)) | |
6102 | break; | |
2bfa88dc | 6103 | |
d5b7b3ae | 6104 | ftmp = ftmp->next; |
2bfa88dc | 6105 | } |
949d79eb RE |
6106 | |
6107 | /* Scan over the fixes we have identified for this pool, fixing them | |
6108 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 6109 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
6110 | this_fix = this_fix->next) |
6111 | if (GET_CODE (this_fix->insn) != BARRIER) | |
6112 | { | |
949d79eb RE |
6113 | rtx addr |
6114 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, | |
6115 | minipool_vector_label), | |
d5b7b3ae | 6116 | this_fix->minipool->offset); |
949d79eb RE |
6117 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
6118 | } | |
6119 | ||
d5b7b3ae | 6120 | dump_minipool (last_barrier->insn); |
949d79eb | 6121 | fix = ftmp; |
2b835d68 | 6122 | } |
4b632bf1 | 6123 | |
949d79eb RE |
6124 | /* From now on we must synthesize any constants that we can't handle |
6125 | directly. This can happen if the RTL gets split during final | |
6126 | instruction generation. */ | |
4b632bf1 | 6127 | after_arm_reorg = 1; |
c7319d87 RE |
6128 | |
6129 | /* Free the minipool memory. */ | |
6130 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 6131 | } |
cce8749e CH |
6132 | \f |
6133 | /* Routines to output assembly language. */ | |
6134 | ||
f3bb6135 | 6135 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 6136 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 6137 | when cross compiling. */ |
cd2b33d0 | 6138 | const char * |
ff9940b0 | 6139 | fp_immediate_constant (x) |
b5cc037f | 6140 | rtx x; |
ff9940b0 RE |
6141 | { |
6142 | REAL_VALUE_TYPE r; | |
6143 | int i; | |
6144 | ||
6145 | if (!fpa_consts_inited) | |
6146 | init_fpa_table (); | |
6147 | ||
6148 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
6149 | for (i = 0; i < 8; i++) | |
6150 | if (REAL_VALUES_EQUAL (r, values_fpa[i])) | |
6151 | return strings_fpa[i]; | |
f3bb6135 | 6152 | |
ff9940b0 RE |
6153 | abort (); |
6154 | } | |
6155 | ||
9997d19d | 6156 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 6157 | static const char * |
9997d19d | 6158 | fp_const_from_val (r) |
62b10bbc | 6159 | REAL_VALUE_TYPE * r; |
9997d19d RE |
6160 | { |
6161 | int i; | |
6162 | ||
5895f793 | 6163 | if (!fpa_consts_inited) |
9997d19d RE |
6164 | init_fpa_table (); |
6165 | ||
6166 | for (i = 0; i < 8; i++) | |
6167 | if (REAL_VALUES_EQUAL (*r, values_fpa[i])) | |
6168 | return strings_fpa[i]; | |
6169 | ||
6170 | abort (); | |
6171 | } | |
ff9940b0 | 6172 | |
cce8749e CH |
6173 | /* Output the operands of a LDM/STM instruction to STREAM. |
6174 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 NC |
6175 | REG is the base register, either the frame pointer or the stack pointer, |
6176 | INSTR is the possibly suffixed load or store instruction. */ | |
cce8749e | 6177 | |
d5b7b3ae | 6178 | static void |
6d3d9133 | 6179 | print_multi_reg (stream, instr, reg, mask) |
62b10bbc | 6180 | FILE * stream; |
cd2b33d0 | 6181 | const char * instr; |
dd18ae56 NC |
6182 | int reg; |
6183 | int mask; | |
cce8749e CH |
6184 | { |
6185 | int i; | |
6186 | int not_first = FALSE; | |
6187 | ||
1d5473cb | 6188 | fputc ('\t', stream); |
dd18ae56 | 6189 | asm_fprintf (stream, instr, reg); |
1d5473cb | 6190 | fputs (", {", stream); |
62b10bbc | 6191 | |
d5b7b3ae | 6192 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
6193 | if (mask & (1 << i)) |
6194 | { | |
6195 | if (not_first) | |
6196 | fprintf (stream, ", "); | |
62b10bbc | 6197 | |
dd18ae56 | 6198 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
6199 | not_first = TRUE; |
6200 | } | |
f3bb6135 | 6201 | |
6d3d9133 | 6202 | fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^"); |
f3bb6135 | 6203 | } |
cce8749e | 6204 | |
6354dc9b | 6205 | /* Output a 'call' insn. */ |
cce8749e | 6206 | |
cd2b33d0 | 6207 | const char * |
cce8749e | 6208 | output_call (operands) |
62b10bbc | 6209 | rtx * operands; |
cce8749e | 6210 | { |
6354dc9b | 6211 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
cce8749e | 6212 | |
62b10bbc | 6213 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 6214 | { |
62b10bbc | 6215 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 6216 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 6217 | } |
62b10bbc | 6218 | |
1d5473cb | 6219 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
da6558fd | 6220 | |
6cfc7210 | 6221 | if (TARGET_INTERWORK) |
da6558fd NC |
6222 | output_asm_insn ("bx%?\t%0", operands); |
6223 | else | |
6224 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
6225 | ||
f3bb6135 RE |
6226 | return ""; |
6227 | } | |
cce8749e | 6228 | |
ff9940b0 RE |
6229 | static int |
6230 | eliminate_lr2ip (x) | |
62b10bbc | 6231 | rtx * x; |
ff9940b0 RE |
6232 | { |
6233 | int something_changed = 0; | |
62b10bbc | 6234 | rtx x0 = * x; |
ff9940b0 RE |
6235 | int code = GET_CODE (x0); |
6236 | register int i, j; | |
6f7d635c | 6237 | register const char * fmt; |
ff9940b0 RE |
6238 | |
6239 | switch (code) | |
6240 | { | |
6241 | case REG: | |
62b10bbc | 6242 | if (REGNO (x0) == LR_REGNUM) |
ff9940b0 | 6243 | { |
62b10bbc | 6244 | *x = gen_rtx_REG (SImode, IP_REGNUM); |
ff9940b0 RE |
6245 | return 1; |
6246 | } | |
6247 | return 0; | |
6248 | default: | |
6354dc9b | 6249 | /* Scan through the sub-elements and change any references there. */ |
ff9940b0 | 6250 | fmt = GET_RTX_FORMAT (code); |
62b10bbc | 6251 | |
ff9940b0 RE |
6252 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
6253 | if (fmt[i] == 'e') | |
6254 | something_changed |= eliminate_lr2ip (&XEXP (x0, i)); | |
6255 | else if (fmt[i] == 'E') | |
6256 | for (j = 0; j < XVECLEN (x0, i); j++) | |
6257 | something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j)); | |
62b10bbc | 6258 | |
ff9940b0 RE |
6259 | return something_changed; |
6260 | } | |
6261 | } | |
6262 | ||
6354dc9b | 6263 | /* Output a 'call' insn that is a reference in memory. */ |
ff9940b0 | 6264 | |
cd2b33d0 | 6265 | const char * |
ff9940b0 | 6266 | output_call_mem (operands) |
62b10bbc | 6267 | rtx * operands; |
ff9940b0 | 6268 | { |
6354dc9b NC |
6269 | operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */ |
6270 | /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */ | |
ff9940b0 | 6271 | if (eliminate_lr2ip (&operands[0])) |
1d5473cb | 6272 | output_asm_insn ("mov%?\t%|ip, %|lr", operands); |
f3bb6135 | 6273 | |
6cfc7210 | 6274 | if (TARGET_INTERWORK) |
da6558fd NC |
6275 | { |
6276 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
6277 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
6278 | output_asm_insn ("bx%?\t%|ip", operands); | |
6279 | } | |
6280 | else | |
6281 | { | |
6282 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
6283 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
6284 | } | |
6285 | ||
f3bb6135 RE |
6286 | return ""; |
6287 | } | |
ff9940b0 RE |
6288 | |
6289 | ||
6290 | /* Output a move from arm registers to an fpu registers. | |
6291 | OPERANDS[0] is an fpu register. | |
6292 | OPERANDS[1] is the first registers of an arm register pair. */ | |
6293 | ||
cd2b33d0 | 6294 | const char * |
ff9940b0 | 6295 | output_mov_long_double_fpu_from_arm (operands) |
62b10bbc | 6296 | rtx * operands; |
ff9940b0 RE |
6297 | { |
6298 | int arm_reg0 = REGNO (operands[1]); | |
6299 | rtx ops[3]; | |
6300 | ||
62b10bbc NC |
6301 | if (arm_reg0 == IP_REGNUM) |
6302 | abort (); | |
f3bb6135 | 6303 | |
43cffd11 RE |
6304 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
6305 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
6306 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 6307 | |
1d5473cb RE |
6308 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); |
6309 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); | |
62b10bbc | 6310 | |
f3bb6135 RE |
6311 | return ""; |
6312 | } | |
ff9940b0 RE |
6313 | |
6314 | /* Output a move from an fpu register to arm registers. | |
6315 | OPERANDS[0] is the first registers of an arm register pair. | |
6316 | OPERANDS[1] is an fpu register. */ | |
6317 | ||
cd2b33d0 | 6318 | const char * |
ff9940b0 | 6319 | output_mov_long_double_arm_from_fpu (operands) |
62b10bbc | 6320 | rtx * operands; |
ff9940b0 RE |
6321 | { |
6322 | int arm_reg0 = REGNO (operands[0]); | |
6323 | rtx ops[3]; | |
6324 | ||
62b10bbc NC |
6325 | if (arm_reg0 == IP_REGNUM) |
6326 | abort (); | |
f3bb6135 | 6327 | |
43cffd11 RE |
6328 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
6329 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
6330 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 6331 | |
1d5473cb RE |
6332 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
6333 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); | |
f3bb6135 RE |
6334 | return ""; |
6335 | } | |
ff9940b0 RE |
6336 | |
6337 | /* Output a move from arm registers to arm registers of a long double | |
6338 | OPERANDS[0] is the destination. | |
6339 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 6340 | const char * |
ff9940b0 | 6341 | output_mov_long_double_arm_from_arm (operands) |
62b10bbc | 6342 | rtx * operands; |
ff9940b0 | 6343 | { |
6354dc9b | 6344 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
6345 | int dest_start = REGNO (operands[0]); |
6346 | int src_start = REGNO (operands[1]); | |
6347 | rtx ops[2]; | |
6348 | int i; | |
6349 | ||
6350 | if (dest_start < src_start) | |
6351 | { | |
6352 | for (i = 0; i < 3; i++) | |
6353 | { | |
43cffd11 RE |
6354 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
6355 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 6356 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
6357 | } |
6358 | } | |
6359 | else | |
6360 | { | |
6361 | for (i = 2; i >= 0; i--) | |
6362 | { | |
43cffd11 RE |
6363 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
6364 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 6365 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
6366 | } |
6367 | } | |
f3bb6135 | 6368 | |
ff9940b0 RE |
6369 | return ""; |
6370 | } | |
6371 | ||
6372 | ||
cce8749e CH |
6373 | /* Output a move from arm registers to an fpu registers. |
6374 | OPERANDS[0] is an fpu register. | |
6375 | OPERANDS[1] is the first registers of an arm register pair. */ | |
6376 | ||
cd2b33d0 | 6377 | const char * |
cce8749e | 6378 | output_mov_double_fpu_from_arm (operands) |
62b10bbc | 6379 | rtx * operands; |
cce8749e CH |
6380 | { |
6381 | int arm_reg0 = REGNO (operands[1]); | |
6382 | rtx ops[2]; | |
6383 | ||
62b10bbc NC |
6384 | if (arm_reg0 == IP_REGNUM) |
6385 | abort (); | |
6386 | ||
43cffd11 RE |
6387 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
6388 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
6389 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); |
6390 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); | |
f3bb6135 RE |
6391 | return ""; |
6392 | } | |
cce8749e CH |
6393 | |
6394 | /* Output a move from an fpu register to arm registers. | |
6395 | OPERANDS[0] is the first registers of an arm register pair. | |
6396 | OPERANDS[1] is an fpu register. */ | |
6397 | ||
cd2b33d0 | 6398 | const char * |
cce8749e | 6399 | output_mov_double_arm_from_fpu (operands) |
62b10bbc | 6400 | rtx * operands; |
cce8749e CH |
6401 | { |
6402 | int arm_reg0 = REGNO (operands[0]); | |
6403 | rtx ops[2]; | |
6404 | ||
62b10bbc NC |
6405 | if (arm_reg0 == IP_REGNUM) |
6406 | abort (); | |
f3bb6135 | 6407 | |
43cffd11 RE |
6408 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
6409 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
6410 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
6411 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); | |
f3bb6135 RE |
6412 | return ""; |
6413 | } | |
cce8749e CH |
6414 | |
6415 | /* Output a move between double words. | |
6416 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
6417 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
6418 | ||
cd2b33d0 | 6419 | const char * |
cce8749e | 6420 | output_move_double (operands) |
aec3cfba | 6421 | rtx * operands; |
cce8749e CH |
6422 | { |
6423 | enum rtx_code code0 = GET_CODE (operands[0]); | |
6424 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 6425 | rtx otherops[3]; |
cce8749e CH |
6426 | |
6427 | if (code0 == REG) | |
6428 | { | |
6429 | int reg0 = REGNO (operands[0]); | |
6430 | ||
43cffd11 | 6431 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
aec3cfba | 6432 | |
cce8749e CH |
6433 | if (code1 == REG) |
6434 | { | |
6435 | int reg1 = REGNO (operands[1]); | |
62b10bbc NC |
6436 | if (reg1 == IP_REGNUM) |
6437 | abort (); | |
f3bb6135 | 6438 | |
6354dc9b | 6439 | /* Ensure the second source is not overwritten. */ |
c1c2bc04 | 6440 | if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) |
6cfc7210 | 6441 | output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); |
cce8749e | 6442 | else |
6cfc7210 | 6443 | output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); |
cce8749e CH |
6444 | } |
6445 | else if (code1 == CONST_DOUBLE) | |
6446 | { | |
226a5051 RE |
6447 | if (GET_MODE (operands[1]) == DFmode) |
6448 | { | |
6449 | long l[2]; | |
6450 | union real_extract u; | |
6451 | ||
4e135bdd | 6452 | memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u)); |
226a5051 | 6453 | REAL_VALUE_TO_TARGET_DOUBLE (u.d, l); |
d5b7b3ae RE |
6454 | otherops[1] = GEN_INT (l[1]); |
6455 | operands[1] = GEN_INT (l[0]); | |
226a5051 | 6456 | } |
c1c2bc04 RE |
6457 | else if (GET_MODE (operands[1]) != VOIDmode) |
6458 | abort (); | |
6459 | else if (WORDS_BIG_ENDIAN) | |
6460 | { | |
6461 | ||
6462 | otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6463 | operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
6464 | } | |
226a5051 RE |
6465 | else |
6466 | { | |
c1c2bc04 | 6467 | |
226a5051 RE |
6468 | otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
6469 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6470 | } | |
6cfc7210 | 6471 | |
c1c2bc04 RE |
6472 | output_mov_immediate (operands); |
6473 | output_mov_immediate (otherops); | |
cce8749e CH |
6474 | } |
6475 | else if (code1 == CONST_INT) | |
6476 | { | |
56636818 JL |
6477 | #if HOST_BITS_PER_WIDE_INT > 32 |
6478 | /* If HOST_WIDE_INT is more than 32 bits, the intval tells us | |
6479 | what the upper word is. */ | |
6480 | if (WORDS_BIG_ENDIAN) | |
6481 | { | |
6482 | otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
6483 | operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
6484 | } | |
6485 | else | |
6486 | { | |
6487 | otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
6488 | operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
6489 | } | |
6490 | #else | |
6354dc9b | 6491 | /* Sign extend the intval into the high-order word. */ |
c1c2bc04 RE |
6492 | if (WORDS_BIG_ENDIAN) |
6493 | { | |
6494 | otherops[1] = operands[1]; | |
6495 | operands[1] = (INTVAL (operands[1]) < 0 | |
6496 | ? constm1_rtx : const0_rtx); | |
6497 | } | |
ff9940b0 | 6498 | else |
c1c2bc04 | 6499 | otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; |
56636818 | 6500 | #endif |
c1c2bc04 RE |
6501 | output_mov_immediate (otherops); |
6502 | output_mov_immediate (operands); | |
cce8749e CH |
6503 | } |
6504 | else if (code1 == MEM) | |
6505 | { | |
ff9940b0 | 6506 | switch (GET_CODE (XEXP (operands[1], 0))) |
cce8749e | 6507 | { |
ff9940b0 | 6508 | case REG: |
9997d19d | 6509 | output_asm_insn ("ldm%?ia\t%m1, %M0", operands); |
ff9940b0 | 6510 | break; |
2b835d68 | 6511 | |
ff9940b0 | 6512 | case PRE_INC: |
6354dc9b | 6513 | abort (); /* Should never happen now. */ |
ff9940b0 | 6514 | break; |
2b835d68 | 6515 | |
ff9940b0 | 6516 | case PRE_DEC: |
2b835d68 | 6517 | output_asm_insn ("ldm%?db\t%m1!, %M0", operands); |
ff9940b0 | 6518 | break; |
2b835d68 | 6519 | |
ff9940b0 | 6520 | case POST_INC: |
9997d19d | 6521 | output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); |
ff9940b0 | 6522 | break; |
2b835d68 | 6523 | |
ff9940b0 | 6524 | case POST_DEC: |
6354dc9b | 6525 | abort (); /* Should never happen now. */ |
ff9940b0 | 6526 | break; |
2b835d68 RE |
6527 | |
6528 | case LABEL_REF: | |
6529 | case CONST: | |
6530 | output_asm_insn ("adr%?\t%0, %1", operands); | |
6531 | output_asm_insn ("ldm%?ia\t%0, %M0", operands); | |
6532 | break; | |
6533 | ||
ff9940b0 | 6534 | default: |
aec3cfba NC |
6535 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), |
6536 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
cce8749e | 6537 | { |
2b835d68 RE |
6538 | otherops[0] = operands[0]; |
6539 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
6540 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
6541 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) | |
6542 | { | |
6543 | if (GET_CODE (otherops[2]) == CONST_INT) | |
6544 | { | |
6545 | switch (INTVAL (otherops[2])) | |
6546 | { | |
6547 | case -8: | |
6548 | output_asm_insn ("ldm%?db\t%1, %M0", otherops); | |
6549 | return ""; | |
6550 | case -4: | |
6551 | output_asm_insn ("ldm%?da\t%1, %M0", otherops); | |
6552 | return ""; | |
6553 | case 4: | |
6554 | output_asm_insn ("ldm%?ib\t%1, %M0", otherops); | |
6555 | return ""; | |
6556 | } | |
6557 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) | |
6558 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
6559 | else | |
6560 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
6561 | } | |
6562 | else | |
6563 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
6564 | } | |
6565 | else | |
6566 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
6cfc7210 | 6567 | |
2b835d68 RE |
6568 | return "ldm%?ia\t%0, %M0"; |
6569 | } | |
6570 | else | |
6571 | { | |
b72f00af | 6572 | otherops[1] = adjust_address (operands[1], VOIDmode, 4); |
2b835d68 RE |
6573 | /* Take care of overlapping base/data reg. */ |
6574 | if (reg_mentioned_p (operands[0], operands[1])) | |
6575 | { | |
6576 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
6577 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
6578 | } | |
6579 | else | |
6580 | { | |
6581 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
6582 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
6583 | } | |
cce8749e CH |
6584 | } |
6585 | } | |
6586 | } | |
2b835d68 | 6587 | else |
6354dc9b | 6588 | abort (); /* Constraints should prevent this. */ |
cce8749e CH |
6589 | } |
6590 | else if (code0 == MEM && code1 == REG) | |
6591 | { | |
62b10bbc NC |
6592 | if (REGNO (operands[1]) == IP_REGNUM) |
6593 | abort (); | |
2b835d68 | 6594 | |
ff9940b0 RE |
6595 | switch (GET_CODE (XEXP (operands[0], 0))) |
6596 | { | |
6597 | case REG: | |
9997d19d | 6598 | output_asm_insn ("stm%?ia\t%m0, %M1", operands); |
ff9940b0 | 6599 | break; |
2b835d68 | 6600 | |
ff9940b0 | 6601 | case PRE_INC: |
6354dc9b | 6602 | abort (); /* Should never happen now. */ |
ff9940b0 | 6603 | break; |
2b835d68 | 6604 | |
ff9940b0 | 6605 | case PRE_DEC: |
2b835d68 | 6606 | output_asm_insn ("stm%?db\t%m0!, %M1", operands); |
ff9940b0 | 6607 | break; |
2b835d68 | 6608 | |
ff9940b0 | 6609 | case POST_INC: |
9997d19d | 6610 | output_asm_insn ("stm%?ia\t%m0!, %M1", operands); |
ff9940b0 | 6611 | break; |
2b835d68 | 6612 | |
ff9940b0 | 6613 | case POST_DEC: |
6354dc9b | 6614 | abort (); /* Should never happen now. */ |
ff9940b0 | 6615 | break; |
2b835d68 RE |
6616 | |
6617 | case PLUS: | |
6618 | if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
6619 | { | |
6620 | switch (INTVAL (XEXP (XEXP (operands[0], 0), 1))) | |
6621 | { | |
6622 | case -8: | |
6623 | output_asm_insn ("stm%?db\t%m0, %M1", operands); | |
6624 | return ""; | |
6625 | ||
6626 | case -4: | |
6627 | output_asm_insn ("stm%?da\t%m0, %M1", operands); | |
6628 | return ""; | |
6629 | ||
6630 | case 4: | |
6631 | output_asm_insn ("stm%?ib\t%m0, %M1", operands); | |
6632 | return ""; | |
6633 | } | |
6634 | } | |
6635 | /* Fall through */ | |
6636 | ||
ff9940b0 | 6637 | default: |
b72f00af | 6638 | otherops[0] = adjust_address (operands[0], VOIDmode, 4); |
43cffd11 | 6639 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
6640 | output_asm_insn ("str%?\t%1, %0", operands); |
6641 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
6642 | } |
6643 | } | |
2b835d68 | 6644 | else |
62b10bbc | 6645 | abort (); /* Constraints should prevent this */ |
cce8749e | 6646 | |
9997d19d RE |
6647 | return ""; |
6648 | } | |
cce8749e CH |
6649 | |
6650 | ||
6651 | /* Output an arbitrary MOV reg, #n. | |
6652 | OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ | |
6653 | ||
cd2b33d0 | 6654 | const char * |
cce8749e | 6655 | output_mov_immediate (operands) |
62b10bbc | 6656 | rtx * operands; |
cce8749e | 6657 | { |
f3bb6135 | 6658 | HOST_WIDE_INT n = INTVAL (operands[1]); |
cce8749e CH |
6659 | int n_ones = 0; |
6660 | int i; | |
6661 | ||
6662 | /* Try to use one MOV */ | |
cce8749e | 6663 | if (const_ok_for_arm (n)) |
f3bb6135 | 6664 | { |
9997d19d | 6665 | output_asm_insn ("mov%?\t%0, %1", operands); |
f3bb6135 RE |
6666 | return ""; |
6667 | } | |
cce8749e CH |
6668 | |
6669 | /* Try to use one MVN */ | |
f3bb6135 | 6670 | if (const_ok_for_arm (~n)) |
cce8749e | 6671 | { |
f3bb6135 | 6672 | operands[1] = GEN_INT (~n); |
9997d19d | 6673 | output_asm_insn ("mvn%?\t%0, %1", operands); |
f3bb6135 | 6674 | return ""; |
cce8749e CH |
6675 | } |
6676 | ||
6354dc9b | 6677 | /* If all else fails, make it out of ORRs or BICs as appropriate. */ |
cce8749e CH |
6678 | |
6679 | for (i=0; i < 32; i++) | |
6680 | if (n & 1 << i) | |
6681 | n_ones++; | |
6682 | ||
6354dc9b | 6683 | if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ |
e5951263 | 6684 | output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n); |
cce8749e | 6685 | else |
d5b7b3ae | 6686 | output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); |
f3bb6135 RE |
6687 | |
6688 | return ""; | |
6689 | } | |
cce8749e CH |
6690 | |
6691 | ||
6692 | /* Output an ADD r, s, #n where n may be too big for one instruction. If | |
6693 | adding zero to one register, output nothing. */ | |
6694 | ||
cd2b33d0 | 6695 | const char * |
cce8749e | 6696 | output_add_immediate (operands) |
62b10bbc | 6697 | rtx * operands; |
cce8749e | 6698 | { |
f3bb6135 | 6699 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
6700 | |
6701 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
6702 | { | |
6703 | if (n < 0) | |
6704 | output_multi_immediate (operands, | |
9997d19d RE |
6705 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
6706 | -n); | |
cce8749e CH |
6707 | else |
6708 | output_multi_immediate (operands, | |
9997d19d RE |
6709 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
6710 | n); | |
cce8749e | 6711 | } |
f3bb6135 RE |
6712 | |
6713 | return ""; | |
6714 | } | |
cce8749e | 6715 | |
cce8749e CH |
6716 | /* Output a multiple immediate operation. |
6717 | OPERANDS is the vector of operands referred to in the output patterns. | |
6718 | INSTR1 is the output pattern to use for the first constant. | |
6719 | INSTR2 is the output pattern to use for subsequent constants. | |
6720 | IMMED_OP is the index of the constant slot in OPERANDS. | |
6721 | N is the constant value. */ | |
6722 | ||
cd2b33d0 | 6723 | static const char * |
cce8749e | 6724 | output_multi_immediate (operands, instr1, instr2, immed_op, n) |
62b10bbc | 6725 | rtx * operands; |
cd2b33d0 NC |
6726 | const char * instr1; |
6727 | const char * instr2; | |
f3bb6135 RE |
6728 | int immed_op; |
6729 | HOST_WIDE_INT n; | |
cce8749e | 6730 | { |
f3bb6135 | 6731 | #if HOST_BITS_PER_WIDE_INT > 32 |
e5951263 | 6732 | n &= HOST_UINT (0xffffffff); |
f3bb6135 RE |
6733 | #endif |
6734 | ||
cce8749e CH |
6735 | if (n == 0) |
6736 | { | |
6737 | operands[immed_op] = const0_rtx; | |
6354dc9b | 6738 | output_asm_insn (instr1, operands); /* Quick and easy output. */ |
cce8749e CH |
6739 | } |
6740 | else | |
6741 | { | |
6742 | int i; | |
cd2b33d0 | 6743 | const char * instr = instr1; |
cce8749e | 6744 | |
6354dc9b | 6745 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
6746 | for (i = 0; i < 32; i += 2) |
6747 | { | |
6748 | if (n & (3 << i)) | |
6749 | { | |
f3bb6135 RE |
6750 | operands[immed_op] = GEN_INT (n & (255 << i)); |
6751 | output_asm_insn (instr, operands); | |
cce8749e CH |
6752 | instr = instr2; |
6753 | i += 6; | |
6754 | } | |
6755 | } | |
6756 | } | |
cd2b33d0 | 6757 | |
f3bb6135 | 6758 | return ""; |
9997d19d | 6759 | } |
cce8749e CH |
6760 | |
6761 | ||
6762 | /* Return the appropriate ARM instruction for the operation code. | |
6763 | The returned result should not be overwritten. OP is the rtx of the | |
6764 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
6765 | was shifted. */ | |
6766 | ||
cd2b33d0 | 6767 | const char * |
cce8749e CH |
6768 | arithmetic_instr (op, shift_first_arg) |
6769 | rtx op; | |
f3bb6135 | 6770 | int shift_first_arg; |
cce8749e | 6771 | { |
9997d19d | 6772 | switch (GET_CODE (op)) |
cce8749e CH |
6773 | { |
6774 | case PLUS: | |
f3bb6135 RE |
6775 | return "add"; |
6776 | ||
cce8749e | 6777 | case MINUS: |
f3bb6135 RE |
6778 | return shift_first_arg ? "rsb" : "sub"; |
6779 | ||
cce8749e | 6780 | case IOR: |
f3bb6135 RE |
6781 | return "orr"; |
6782 | ||
cce8749e | 6783 | case XOR: |
f3bb6135 RE |
6784 | return "eor"; |
6785 | ||
cce8749e | 6786 | case AND: |
f3bb6135 RE |
6787 | return "and"; |
6788 | ||
cce8749e | 6789 | default: |
f3bb6135 | 6790 | abort (); |
cce8749e | 6791 | } |
f3bb6135 | 6792 | } |
cce8749e CH |
6793 | |
6794 | ||
6795 | /* Ensure valid constant shifts and return the appropriate shift mnemonic | |
6796 | for the operation code. The returned result should not be overwritten. | |
6797 | OP is the rtx code of the shift. | |
9997d19d | 6798 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 6799 | shift. */ |
cce8749e | 6800 | |
cd2b33d0 | 6801 | static const char * |
9997d19d RE |
6802 | shift_op (op, amountp) |
6803 | rtx op; | |
6804 | HOST_WIDE_INT *amountp; | |
cce8749e | 6805 | { |
cd2b33d0 | 6806 | const char * mnem; |
e2c671ba | 6807 | enum rtx_code code = GET_CODE (op); |
cce8749e | 6808 | |
9997d19d RE |
6809 | if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) |
6810 | *amountp = -1; | |
6811 | else if (GET_CODE (XEXP (op, 1)) == CONST_INT) | |
6812 | *amountp = INTVAL (XEXP (op, 1)); | |
6813 | else | |
6814 | abort (); | |
6815 | ||
e2c671ba | 6816 | switch (code) |
cce8749e CH |
6817 | { |
6818 | case ASHIFT: | |
6819 | mnem = "asl"; | |
6820 | break; | |
f3bb6135 | 6821 | |
cce8749e CH |
6822 | case ASHIFTRT: |
6823 | mnem = "asr"; | |
cce8749e | 6824 | break; |
f3bb6135 | 6825 | |
cce8749e CH |
6826 | case LSHIFTRT: |
6827 | mnem = "lsr"; | |
cce8749e | 6828 | break; |
f3bb6135 | 6829 | |
9997d19d RE |
6830 | case ROTATERT: |
6831 | mnem = "ror"; | |
9997d19d RE |
6832 | break; |
6833 | ||
ff9940b0 | 6834 | case MULT: |
e2c671ba RE |
6835 | /* We never have to worry about the amount being other than a |
6836 | power of 2, since this case can never be reloaded from a reg. */ | |
9997d19d RE |
6837 | if (*amountp != -1) |
6838 | *amountp = int_log2 (*amountp); | |
6839 | else | |
6840 | abort (); | |
f3bb6135 RE |
6841 | return "asl"; |
6842 | ||
cce8749e | 6843 | default: |
f3bb6135 | 6844 | abort (); |
cce8749e CH |
6845 | } |
6846 | ||
e2c671ba RE |
6847 | if (*amountp != -1) |
6848 | { | |
6849 | /* This is not 100% correct, but follows from the desire to merge | |
6850 | multiplication by a power of 2 with the recognizer for a | |
6851 | shift. >=32 is not a valid shift for "asl", so we must try and | |
6852 | output a shift that produces the correct arithmetical result. | |
ddd5a7c1 | 6853 | Using lsr #32 is identical except for the fact that the carry bit |
e2c671ba RE |
6854 | is not set correctly if we set the flags; but we never use the |
6855 | carry bit from such an operation, so we can ignore that. */ | |
6856 | if (code == ROTATERT) | |
6857 | *amountp &= 31; /* Rotate is just modulo 32 */ | |
6858 | else if (*amountp != (*amountp & 31)) | |
6859 | { | |
6860 | if (code == ASHIFT) | |
6861 | mnem = "lsr"; | |
6862 | *amountp = 32; | |
6863 | } | |
6864 | ||
6865 | /* Shifts of 0 are no-ops. */ | |
6866 | if (*amountp == 0) | |
6867 | return NULL; | |
6868 | } | |
6869 | ||
9997d19d RE |
6870 | return mnem; |
6871 | } | |
cce8749e CH |
6872 | |
6873 | ||
6354dc9b | 6874 | /* Obtain the shift from the POWER of two. */ |
18af7313 | 6875 | static HOST_WIDE_INT |
cce8749e | 6876 | int_log2 (power) |
f3bb6135 | 6877 | HOST_WIDE_INT power; |
cce8749e | 6878 | { |
f3bb6135 | 6879 | HOST_WIDE_INT shift = 0; |
cce8749e | 6880 | |
e5951263 | 6881 | while ((((HOST_INT (1)) << shift) & power) == 0) |
cce8749e CH |
6882 | { |
6883 | if (shift > 31) | |
f3bb6135 | 6884 | abort (); |
cce8749e CH |
6885 | shift++; |
6886 | } | |
f3bb6135 RE |
6887 | |
6888 | return shift; | |
6889 | } | |
cce8749e | 6890 | |
cce8749e CH |
6891 | /* Output a .ascii pseudo-op, keeping track of lengths. This is because |
6892 | /bin/as is horribly restrictive. */ | |
6cfc7210 | 6893 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
6894 | |
6895 | void | |
6896 | output_ascii_pseudo_op (stream, p, len) | |
62b10bbc | 6897 | FILE * stream; |
3cce094d | 6898 | const unsigned char * p; |
cce8749e CH |
6899 | int len; |
6900 | { | |
6901 | int i; | |
6cfc7210 | 6902 | int len_so_far = 0; |
cce8749e | 6903 | |
6cfc7210 NC |
6904 | fputs ("\t.ascii\t\"", stream); |
6905 | ||
cce8749e CH |
6906 | for (i = 0; i < len; i++) |
6907 | { | |
6908 | register int c = p[i]; | |
6909 | ||
6cfc7210 | 6910 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 6911 | { |
6cfc7210 | 6912 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 6913 | len_so_far = 0; |
cce8749e CH |
6914 | } |
6915 | ||
6cfc7210 | 6916 | switch (c) |
cce8749e | 6917 | { |
6cfc7210 NC |
6918 | case TARGET_TAB: |
6919 | fputs ("\\t", stream); | |
6920 | len_so_far += 2; | |
6921 | break; | |
6922 | ||
6923 | case TARGET_FF: | |
6924 | fputs ("\\f", stream); | |
6925 | len_so_far += 2; | |
6926 | break; | |
6927 | ||
6928 | case TARGET_BS: | |
6929 | fputs ("\\b", stream); | |
6930 | len_so_far += 2; | |
6931 | break; | |
6932 | ||
6933 | case TARGET_CR: | |
6934 | fputs ("\\r", stream); | |
6935 | len_so_far += 2; | |
6936 | break; | |
6937 | ||
6938 | case TARGET_NEWLINE: | |
6939 | fputs ("\\n", stream); | |
6940 | c = p [i + 1]; | |
6941 | if ((c >= ' ' && c <= '~') | |
6942 | || c == TARGET_TAB) | |
6943 | /* This is a good place for a line break. */ | |
6944 | len_so_far = MAX_ASCII_LEN; | |
6945 | else | |
6946 | len_so_far += 2; | |
6947 | break; | |
6948 | ||
6949 | case '\"': | |
6950 | case '\\': | |
6951 | putc ('\\', stream); | |
5895f793 | 6952 | len_so_far++; |
6cfc7210 | 6953 | /* drop through. */ |
f3bb6135 | 6954 | |
6cfc7210 NC |
6955 | default: |
6956 | if (c >= ' ' && c <= '~') | |
6957 | { | |
6958 | putc (c, stream); | |
5895f793 | 6959 | len_so_far++; |
6cfc7210 NC |
6960 | } |
6961 | else | |
6962 | { | |
6963 | fprintf (stream, "\\%03o", c); | |
6964 | len_so_far += 4; | |
6965 | } | |
6966 | break; | |
cce8749e | 6967 | } |
cce8749e | 6968 | } |
f3bb6135 | 6969 | |
cce8749e | 6970 | fputs ("\"\n", stream); |
f3bb6135 | 6971 | } |
cce8749e | 6972 | \f |
6d3d9133 NC |
6973 | /* Compute a bit mask of which registers need to be |
6974 | saved on the stack for the current function. */ | |
6975 | ||
6976 | static unsigned long | |
6977 | arm_compute_save_reg_mask () | |
6978 | { | |
6979 | unsigned int save_reg_mask = 0; | |
6980 | unsigned int reg; | |
6981 | unsigned long func_type = arm_current_func_type (); | |
6982 | ||
6983 | if (IS_NAKED (func_type)) | |
6984 | /* This should never really happen. */ | |
6985 | return 0; | |
6986 | ||
6987 | /* If we are creating a stack frame, then we must save the frame pointer, | |
6988 | IP (which will hold the old stack pointer), LR and the PC. */ | |
6989 | if (frame_pointer_needed) | |
6990 | save_reg_mask |= | |
6991 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
6992 | | (1 << IP_REGNUM) | |
6993 | | (1 << LR_REGNUM) | |
6994 | | (1 << PC_REGNUM); | |
6995 | ||
6996 | /* Volatile functions do not return, so there | |
6997 | is no need to save any other registers. */ | |
6998 | if (IS_VOLATILE (func_type)) | |
6999 | return save_reg_mask; | |
7000 | ||
7b8b8ade | 7001 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 7002 | { |
7b8b8ade NC |
7003 | unsigned int max_reg; |
7004 | ||
7005 | /* Interrupt functions must not corrupt any registers, | |
7006 | even call clobbered ones. If this is a leaf function | |
7007 | we can just examine the registers used by the RTL, but | |
7008 | otherwise we have to assume that whatever function is | |
7009 | called might clobber anything, and so we have to save | |
7010 | all the call-clobbered registers as well. */ | |
7011 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
7012 | /* FIQ handlers have registers r8 - r12 banked, so | |
7013 | we only need to check r0 - r7, Normal ISRs only | |
7014 | bank r14 and r15, so ew must check up to r12. | |
7015 | r13 is the stack pointer which is always preserved, | |
7016 | so we do not need to consider it here. */ | |
7017 | max_reg = 7; | |
7018 | else | |
7019 | max_reg = 12; | |
7020 | ||
7021 | for (reg = 0; reg <= max_reg; reg++) | |
7022 | if (regs_ever_live[reg] | |
7023 | || (! current_function_is_leaf && call_used_regs [reg])) | |
6d3d9133 NC |
7024 | save_reg_mask |= (1 << reg); |
7025 | } | |
7026 | else | |
7027 | { | |
7028 | /* In the normal case we only need to save those registers | |
7029 | which are call saved and which are used by this function. */ | |
7030 | for (reg = 0; reg <= 10; reg++) | |
7031 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
7032 | save_reg_mask |= (1 << reg); | |
7033 | ||
7034 | /* Handle the frame pointer as a special case. */ | |
7035 | if (! TARGET_APCS_FRAME | |
7036 | && ! frame_pointer_needed | |
7037 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] | |
7038 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) | |
7039 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
7040 | ||
7041 | /* If we aren't loading the PIC register, | |
7042 | don't stack it even though it may be live. */ | |
7043 | if (flag_pic | |
7044 | && ! TARGET_SINGLE_PIC_BASE | |
7045 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
7046 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
7047 | } | |
7048 | ||
7049 | /* Decide if we need to save the link register. | |
7050 | Interrupt routines have their own banked link register, | |
7051 | so they never need to save it. | |
7052 | Otheriwse if we do not use the link register we do not need to save | |
7053 | it. If we are pushing other registers onto the stack however, we | |
7054 | can save an instruction in the epilogue by pushing the link register | |
7055 | now and then popping it back into the PC. This incurs extra memory | |
7056 | accesses though, so we only do it when optimising for size, and only | |
7057 | if we know that we will not need a fancy return sequence. */ | |
7058 | if (! IS_INTERRUPT (func_type) | |
7059 | && (regs_ever_live [LR_REGNUM] | |
7060 | || (save_reg_mask | |
7061 | && optimize_size | |
7062 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))) | |
7063 | save_reg_mask |= 1 << LR_REGNUM; | |
7064 | ||
6f7ebcbb NC |
7065 | if (cfun->machine->lr_save_eliminated) |
7066 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
7067 | ||
6d3d9133 NC |
7068 | return save_reg_mask; |
7069 | } | |
7070 | ||
7071 | /* Generate a function exit sequence. If REALLY_RETURN is true, then do | |
7072 | everything bar the final return instruction. */ | |
ff9940b0 | 7073 | |
cd2b33d0 | 7074 | const char * |
84ed5e79 | 7075 | output_return_instruction (operand, really_return, reverse) |
f3bb6135 RE |
7076 | rtx operand; |
7077 | int really_return; | |
84ed5e79 | 7078 | int reverse; |
ff9940b0 | 7079 | { |
6d3d9133 | 7080 | char conditional[10]; |
ff9940b0 | 7081 | char instr[100]; |
6d3d9133 NC |
7082 | int reg; |
7083 | unsigned long live_regs_mask; | |
7084 | unsigned long func_type; | |
7085 | ||
7086 | func_type = arm_current_func_type (); | |
e2c671ba | 7087 | |
6d3d9133 | 7088 | if (IS_NAKED (func_type)) |
d5b7b3ae | 7089 | return ""; |
6d3d9133 NC |
7090 | |
7091 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 7092 | { |
e2c671ba | 7093 | /* If this function was declared non-returning, and we have found a tail |
3a5a4282 PB |
7094 | call, then we have to trust that the called function won't return. */ |
7095 | if (really_return) | |
7096 | { | |
7097 | rtx ops[2]; | |
7098 | ||
7099 | /* Otherwise, trap an attempted return by aborting. */ | |
7100 | ops[0] = operand; | |
7101 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" | |
7102 | : "abort"); | |
7103 | assemble_external_libcall (ops[1]); | |
7104 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
7105 | } | |
7106 | ||
e2c671ba RE |
7107 | return ""; |
7108 | } | |
6d3d9133 | 7109 | |
5895f793 | 7110 | if (current_function_calls_alloca && !really_return) |
62b10bbc | 7111 | abort (); |
ff9940b0 | 7112 | |
6d3d9133 NC |
7113 | /* Construct the conditional part of the instruction(s) to be emitted. */ |
7114 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); | |
d5b7b3ae | 7115 | |
6d3d9133 | 7116 | return_used_this_function = 1; |
ff9940b0 | 7117 | |
6d3d9133 | 7118 | live_regs_mask = arm_compute_save_reg_mask (); |
ff9940b0 | 7119 | |
3a5a4282 | 7120 | /* On some ARM architectures it is faster to use LDR rather than LDM to |
6d3d9133 NC |
7121 | load a single register. On other architectures, the cost is the same. |
7122 | In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */ | |
7123 | if ((live_regs_mask == (1 << LR_REGNUM)) | |
e46ccf7c PB |
7124 | && ! TARGET_INTERWORK |
7125 | && ! IS_INTERRUPT (func_type) | |
6d3d9133 NC |
7126 | && (! really_return || TARGET_APCS_32)) |
7127 | { | |
7128 | if (! really_return) | |
7129 | sprintf (instr, "ldr%s\t%%|lr, [%%|sp], #4", conditional); | |
7130 | else | |
7131 | sprintf (instr, "ldr%s\t%%|pc, [%%|sp], #4", conditional); | |
7132 | } | |
7133 | else if (live_regs_mask) | |
7134 | { | |
7135 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) | |
7136 | /* There are two possible reasons for the IP register being saved. | |
7137 | Either a stack frame was created, in which case IP contains the | |
7138 | old stack pointer, or an ISR routine corrupted it. If this in an | |
7139 | ISR routine then just restore IP, otherwise restore IP into SP. */ | |
7140 | if (! IS_INTERRUPT (func_type)) | |
7141 | { | |
7142 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
7143 | live_regs_mask |= (1 << SP_REGNUM); | |
7144 | } | |
f3bb6135 | 7145 | |
6d3d9133 | 7146 | /* Generate the load multiple instruction to restore the registers. */ |
ff9940b0 | 7147 | if (frame_pointer_needed) |
6d3d9133 | 7148 | sprintf (instr, "ldm%sea\t%%|fp, {", conditional); |
ff9940b0 | 7149 | else |
6d3d9133 | 7150 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
f3bb6135 | 7151 | |
6d3d9133 NC |
7152 | for (reg = 0; reg <= SP_REGNUM; reg++) |
7153 | if (live_regs_mask & (1 << reg)) | |
7154 | { | |
1d5473cb | 7155 | strcat (instr, "%|"); |
6d3d9133 NC |
7156 | strcat (instr, reg_names[reg]); |
7157 | strcat (instr, ", "); | |
7158 | } | |
f3bb6135 | 7159 | |
6d3d9133 NC |
7160 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) |
7161 | { | |
7162 | /* If we are not restoring the LR register then we will | |
7163 | have added one too many commas to the list above. | |
7164 | Replace it with a closing brace. */ | |
7165 | instr [strlen (instr) - 2] = '}'; | |
7166 | } | |
ff9940b0 | 7167 | else |
1d5473cb RE |
7168 | { |
7169 | strcat (instr, "%|"); | |
6d3d9133 NC |
7170 | |
7171 | /* At this point there should only be one or two registers left in | |
7172 | live_regs_mask: always LR, and possibly PC if we created a stack | |
7173 | frame. LR contains the return address. If we do not have any | |
7174 | special requirements for function exit (eg interworking, or ISR) | |
7175 | then we can load this value directly into the PC and save an | |
7176 | instruction. */ | |
7177 | if (! TARGET_INTERWORK | |
7178 | && ! IS_INTERRUPT (func_type) | |
7179 | && really_return) | |
7180 | strcat (instr, reg_names [PC_REGNUM]); | |
da6558fd | 7181 | else |
6d3d9133 NC |
7182 | strcat (instr, reg_names [LR_REGNUM]); |
7183 | ||
7184 | strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^"); | |
1d5473cb | 7185 | } |
da6558fd | 7186 | |
6d3d9133 | 7187 | if (really_return) |
da6558fd | 7188 | { |
6d3d9133 NC |
7189 | /* See if we need to generate an extra instruction to |
7190 | perform the actual function return. */ | |
7191 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
7192 | { | |
7193 | case ARM_FT_ISR: | |
7194 | case ARM_FT_FIQ: | |
7195 | output_asm_insn (instr, & operand); | |
7196 | ||
7197 | strcpy (instr, "sub"); | |
7198 | strcat (instr, conditional); | |
7199 | strcat (instr, "s\t%|pc, %|lr, #4"); | |
7200 | break; | |
7201 | ||
7202 | case ARM_FT_EXCEPTION: | |
7203 | output_asm_insn (instr, & operand); | |
7204 | ||
7205 | strcpy (instr, "mov"); | |
7206 | strcat (instr, conditional); | |
7207 | strcat (instr, "s\t%|pc, %|lr"); | |
7208 | break; | |
7209 | ||
7210 | case ARM_FT_INTERWORKED: | |
7211 | output_asm_insn (instr, & operand); | |
da6558fd | 7212 | |
6d3d9133 NC |
7213 | strcpy (instr, "bx"); |
7214 | strcat (instr, conditional); | |
7215 | strcat (instr, "\t%|lr"); | |
7216 | break; | |
7217 | ||
7218 | default: | |
7219 | /* The return has already been handled | |
7220 | by loading the LR into the PC. */ | |
7221 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
7222 | { | |
7223 | output_asm_insn (instr, & operand); | |
7224 | ||
7225 | strcpy (instr, "mov"); | |
7226 | strcat (instr, conditional); | |
7227 | if (! TARGET_APCS_32) | |
7228 | strcat (instr, "s"); | |
7229 | strcat (instr, "\t%|pc, %|lr"); | |
7230 | } | |
7231 | break; | |
7232 | } | |
da6558fd | 7233 | } |
ff9940b0 RE |
7234 | } |
7235 | else if (really_return) | |
7236 | { | |
6d3d9133 NC |
7237 | switch ((int) ARM_FUNC_TYPE (func_type)) |
7238 | { | |
7239 | case ARM_FT_ISR: | |
7240 | case ARM_FT_FIQ: | |
7241 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); | |
7242 | break; | |
7243 | ||
7244 | case ARM_FT_INTERWORKED: | |
7245 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
7246 | break; | |
7247 | ||
7248 | case ARM_FT_EXCEPTION: | |
7249 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); | |
7250 | break; | |
7251 | ||
7252 | default: | |
7253 | sprintf (instr, "mov%s%s\t%%|pc, %%|lr", | |
7254 | conditional, TARGET_APCS_32 ? "" : "s"); | |
7255 | break; | |
7256 | } | |
ff9940b0 | 7257 | } |
6d3d9133 NC |
7258 | else |
7259 | /* Nothing to load off the stack, and | |
7260 | no return instruction to generate. */ | |
7261 | return ""; | |
f3bb6135 | 7262 | |
6d3d9133 NC |
7263 | output_asm_insn (instr, & operand); |
7264 | ||
ff9940b0 RE |
7265 | return ""; |
7266 | } | |
7267 | ||
ef179a26 NC |
7268 | /* Write the function name into the code section, directly preceding |
7269 | the function prologue. | |
7270 | ||
7271 | Code will be output similar to this: | |
7272 | t0 | |
7273 | .ascii "arm_poke_function_name", 0 | |
7274 | .align | |
7275 | t1 | |
7276 | .word 0xff000000 + (t1 - t0) | |
7277 | arm_poke_function_name | |
7278 | mov ip, sp | |
7279 | stmfd sp!, {fp, ip, lr, pc} | |
7280 | sub fp, ip, #4 | |
7281 | ||
7282 | When performing a stack backtrace, code can inspect the value | |
7283 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
7284 | at location pc - 12 and the top 8 bits are set, then we know | |
7285 | that there is a function name embedded immediately preceding this | |
7286 | location and has length ((pc[-3]) & 0xff000000). | |
7287 | ||
7288 | We assume that pc is declared as a pointer to an unsigned long. | |
7289 | ||
7290 | It is of no benefit to output the function name if we are assembling | |
7291 | a leaf function. These function types will not contain a stack | |
7292 | backtrace structure, therefore it is not possible to determine the | |
7293 | function name. */ | |
7294 | ||
7295 | void | |
7296 | arm_poke_function_name (stream, name) | |
7297 | FILE * stream; | |
7298 | char * name; | |
7299 | { | |
7300 | unsigned long alignlength; | |
7301 | unsigned long length; | |
7302 | rtx x; | |
7303 | ||
d5b7b3ae RE |
7304 | length = strlen (name) + 1; |
7305 | alignlength = ROUND_UP (length); | |
ef179a26 | 7306 | |
949d79eb | 7307 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 7308 | ASM_OUTPUT_ALIGN (stream, 2); |
e5951263 | 7309 | x = GEN_INT (HOST_UINT(0xff000000) + alignlength); |
ef179a26 NC |
7310 | ASM_OUTPUT_INT (stream, x); |
7311 | } | |
7312 | ||
6d3d9133 NC |
7313 | /* Place some comments into the assembler stream |
7314 | describing the current function. */ | |
7315 | ||
cce8749e | 7316 | void |
d5b7b3ae | 7317 | output_arm_prologue (f, frame_size) |
6cfc7210 | 7318 | FILE * f; |
cce8749e CH |
7319 | int frame_size; |
7320 | { | |
6d3d9133 NC |
7321 | unsigned long func_type; |
7322 | ||
7323 | /* Sanity check. */ | |
abaa26e5 | 7324 | if (arm_ccfsm_state || arm_target_insn) |
6d3d9133 | 7325 | abort (); |
31fdb4d5 | 7326 | |
6d3d9133 NC |
7327 | func_type = arm_current_func_type (); |
7328 | ||
7329 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
7330 | { | |
7331 | default: | |
7332 | case ARM_FT_NORMAL: | |
7333 | break; | |
7334 | case ARM_FT_INTERWORKED: | |
7335 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
7336 | break; | |
7337 | case ARM_FT_EXCEPTION_HANDLER: | |
7338 | asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); | |
7339 | break; | |
7340 | case ARM_FT_ISR: | |
7341 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
7342 | break; | |
7343 | case ARM_FT_FIQ: | |
7344 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
7345 | break; | |
7346 | case ARM_FT_EXCEPTION: | |
7347 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
7348 | break; | |
7349 | } | |
ff9940b0 | 7350 | |
6d3d9133 NC |
7351 | if (IS_NAKED (func_type)) |
7352 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
7353 | ||
7354 | if (IS_VOLATILE (func_type)) | |
7355 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
7356 | ||
7357 | if (IS_NESTED (func_type)) | |
7358 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
7359 | ||
dd18ae56 NC |
7360 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n", |
7361 | current_function_args_size, | |
7362 | current_function_pretend_args_size, frame_size); | |
6d3d9133 | 7363 | |
dd18ae56 NC |
7364 | asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n", |
7365 | frame_pointer_needed, | |
7366 | current_function_anonymous_args); | |
cce8749e | 7367 | |
6f7ebcbb NC |
7368 | if (cfun->machine->lr_save_eliminated) |
7369 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
7370 | ||
32de079a RE |
7371 | #ifdef AOF_ASSEMBLER |
7372 | if (flag_pic) | |
dd18ae56 | 7373 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); |
32de079a | 7374 | #endif |
6d3d9133 NC |
7375 | |
7376 | return_used_this_function = 0; | |
f3bb6135 | 7377 | } |
cce8749e | 7378 | |
cd2b33d0 | 7379 | const char * |
0616531f RE |
7380 | arm_output_epilogue (really_return) |
7381 | int really_return; | |
cce8749e | 7382 | { |
949d79eb | 7383 | int reg; |
6f7ebcbb | 7384 | unsigned long saved_regs_mask; |
6d3d9133 | 7385 | unsigned long func_type; |
6354dc9b | 7386 | /* If we need this, then it will always be at least this much. */ |
b111229a | 7387 | int floats_offset = 12; |
cce8749e | 7388 | rtx operands[3]; |
949d79eb | 7389 | int frame_size = get_frame_size (); |
d5b7b3ae | 7390 | FILE * f = asm_out_file; |
6d3d9133 | 7391 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; |
cce8749e | 7392 | |
6d3d9133 NC |
7393 | /* If we have already generated the return instruction |
7394 | then it is futile to generate anything else. */ | |
b36ba79f | 7395 | if (use_return_insn (FALSE) && return_used_this_function) |
949d79eb | 7396 | return ""; |
cce8749e | 7397 | |
6d3d9133 | 7398 | func_type = arm_current_func_type (); |
d5b7b3ae | 7399 | |
6d3d9133 NC |
7400 | if (IS_NAKED (func_type)) |
7401 | /* Naked functions don't have epilogues. */ | |
7402 | return ""; | |
0616531f | 7403 | |
6d3d9133 | 7404 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 7405 | { |
86efdc8e | 7406 | rtx op; |
6d3d9133 NC |
7407 | |
7408 | /* A volatile function should never return. Call abort. */ | |
ed0e6530 | 7409 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 7410 | assemble_external_libcall (op); |
e2c671ba | 7411 | output_asm_insn ("bl\t%a0", &op); |
6d3d9133 | 7412 | |
949d79eb | 7413 | return ""; |
e2c671ba RE |
7414 | } |
7415 | ||
6d3d9133 NC |
7416 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
7417 | && ! really_return) | |
7418 | /* If we are throwing an exception, then we really must | |
7419 | be doing a return, so we can't tail-call. */ | |
7420 | abort (); | |
7421 | ||
6f7ebcbb | 7422 | saved_regs_mask = arm_compute_save_reg_mask (); |
6d3d9133 NC |
7423 | |
7424 | /* Compute how far away the floats will be. */ | |
7425 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++) | |
6f7ebcbb | 7426 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 7427 | floats_offset += 4; |
6d3d9133 | 7428 | |
ff9940b0 | 7429 | if (frame_pointer_needed) |
cce8749e | 7430 | { |
b111229a RE |
7431 | if (arm_fpu_arch == FP_SOFT2) |
7432 | { | |
d5b7b3ae | 7433 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
5895f793 | 7434 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
7435 | { |
7436 | floats_offset += 12; | |
dd18ae56 NC |
7437 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
7438 | reg, FP_REGNUM, floats_offset); | |
b111229a RE |
7439 | } |
7440 | } | |
7441 | else | |
7442 | { | |
d5b7b3ae | 7443 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 7444 | |
d5b7b3ae | 7445 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) |
b111229a | 7446 | { |
5895f793 | 7447 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
7448 | { |
7449 | floats_offset += 12; | |
6cfc7210 | 7450 | |
6354dc9b | 7451 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
7452 | if (start_reg - reg == 3) |
7453 | { | |
dd18ae56 NC |
7454 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
7455 | reg, FP_REGNUM, floats_offset); | |
b111229a RE |
7456 | start_reg = reg - 1; |
7457 | } | |
7458 | } | |
7459 | else | |
7460 | { | |
7461 | if (reg != start_reg) | |
dd18ae56 NC |
7462 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
7463 | reg + 1, start_reg - reg, | |
7464 | FP_REGNUM, floats_offset); | |
b111229a RE |
7465 | start_reg = reg - 1; |
7466 | } | |
7467 | } | |
7468 | ||
7469 | /* Just in case the last register checked also needs unstacking. */ | |
7470 | if (reg != start_reg) | |
dd18ae56 NC |
7471 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
7472 | reg + 1, start_reg - reg, | |
7473 | FP_REGNUM, floats_offset); | |
b111229a | 7474 | } |
6d3d9133 | 7475 | |
6f7ebcbb | 7476 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
7477 | frame generation actually contains the old stack pointer. So a |
7478 | quick way to unwind the stack is just pop the IP register directly | |
7479 | into the stack pointer. */ | |
6f7ebcbb | 7480 | if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) |
6d3d9133 | 7481 | abort (); |
6f7ebcbb NC |
7482 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
7483 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 7484 | |
6f7ebcbb | 7485 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
7486 | only need to restore the LR register (the return address), but to |
7487 | save time we can load it directly into the PC, unless we need a | |
7488 | special function exit sequence, or we are not really returning. */ | |
7489 | if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
7490 | /* Delete the LR from the register mask, so that the LR on | |
7491 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 7492 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 7493 | else |
6f7ebcbb | 7494 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
6d3d9133 | 7495 | |
6f7ebcbb | 7496 | print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask); |
7b8b8ade NC |
7497 | |
7498 | if (IS_INTERRUPT (func_type)) | |
7499 | /* Interrupt handlers will have pushed the | |
7500 | IP onto the stack, so restore it now. */ | |
7501 | print_multi_reg (f, "ldmea\t%r", SP_REGNUM, 1 << IP_REGNUM); | |
cce8749e CH |
7502 | } |
7503 | else | |
7504 | { | |
d2288d8d | 7505 | /* Restore stack pointer if necessary. */ |
56636818 | 7506 | if (frame_size + current_function_outgoing_args_size != 0) |
d2288d8d TG |
7507 | { |
7508 | operands[0] = operands[1] = stack_pointer_rtx; | |
56636818 JL |
7509 | operands[2] = GEN_INT (frame_size |
7510 | + current_function_outgoing_args_size); | |
d2288d8d TG |
7511 | output_add_immediate (operands); |
7512 | } | |
7513 | ||
b111229a RE |
7514 | if (arm_fpu_arch == FP_SOFT2) |
7515 | { | |
d5b7b3ae | 7516 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
5895f793 | 7517 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
dd18ae56 NC |
7518 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
7519 | reg, SP_REGNUM); | |
b111229a RE |
7520 | } |
7521 | else | |
7522 | { | |
d5b7b3ae | 7523 | int start_reg = FIRST_ARM_FP_REGNUM; |
b111229a | 7524 | |
d5b7b3ae | 7525 | for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) |
b111229a | 7526 | { |
5895f793 | 7527 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
7528 | { |
7529 | if (reg - start_reg == 3) | |
7530 | { | |
dd18ae56 NC |
7531 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
7532 | start_reg, SP_REGNUM); | |
b111229a RE |
7533 | start_reg = reg + 1; |
7534 | } | |
7535 | } | |
7536 | else | |
7537 | { | |
7538 | if (reg != start_reg) | |
dd18ae56 NC |
7539 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
7540 | start_reg, reg - start_reg, | |
7541 | SP_REGNUM); | |
6cfc7210 | 7542 | |
b111229a RE |
7543 | start_reg = reg + 1; |
7544 | } | |
7545 | } | |
7546 | ||
7547 | /* Just in case the last register checked also needs unstacking. */ | |
7548 | if (reg != start_reg) | |
dd18ae56 NC |
7549 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
7550 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
7551 | } |
7552 | ||
6d3d9133 NC |
7553 | /* If we can, restore the LR into the PC. */ |
7554 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
7555 | && really_return | |
7556 | && current_function_pretend_args_size == 0 | |
6f7ebcbb | 7557 | && saved_regs_mask & (1 << LR_REGNUM)) |
cce8749e | 7558 | { |
6f7ebcbb NC |
7559 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
7560 | saved_regs_mask |= (1 << PC_REGNUM); | |
6d3d9133 | 7561 | } |
d5b7b3ae | 7562 | |
6d3d9133 NC |
7563 | /* Load the registers off the stack. If we only have one register |
7564 | to load use the LDR instruction - it is faster. */ | |
6f7ebcbb | 7565 | if (saved_regs_mask == (1 << LR_REGNUM)) |
6d3d9133 NC |
7566 | { |
7567 | /* The excpetion handler ignores the LR, so we do | |
7568 | not really need to load it off the stack. */ | |
7569 | if (eh_ofs) | |
7570 | asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); | |
32de079a | 7571 | else |
6d3d9133 | 7572 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 7573 | } |
6f7ebcbb NC |
7574 | else if (saved_regs_mask) |
7575 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); | |
6d3d9133 NC |
7576 | |
7577 | if (current_function_pretend_args_size) | |
cce8749e | 7578 | { |
6d3d9133 NC |
7579 | /* Unwind the pre-pushed regs. */ |
7580 | operands[0] = operands[1] = stack_pointer_rtx; | |
7581 | operands[2] = GEN_INT (current_function_pretend_args_size); | |
7582 | output_add_immediate (operands); | |
7583 | } | |
7584 | } | |
32de079a | 7585 | |
9b598fa0 | 7586 | #if 0 |
6d3d9133 NC |
7587 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER) |
7588 | /* Adjust the stack to remove the exception handler stuff. */ | |
7589 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, | |
7590 | REGNO (eh_ofs)); | |
9b598fa0 | 7591 | #endif |
b111229a | 7592 | |
6d3d9133 NC |
7593 | if (! really_return) |
7594 | return ""; | |
d5b7b3ae | 7595 | |
6d3d9133 NC |
7596 | /* Generate the return instruction. */ |
7597 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
7598 | { | |
7599 | case ARM_FT_EXCEPTION_HANDLER: | |
7600 | /* Even in 26-bit mode we do a mov (rather than a movs) | |
7601 | because we don't have the PSR bits set in the address. */ | |
7602 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); | |
7603 | break; | |
0616531f | 7604 | |
6d3d9133 NC |
7605 | case ARM_FT_ISR: |
7606 | case ARM_FT_FIQ: | |
7607 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
7608 | break; | |
7609 | ||
7610 | case ARM_FT_EXCEPTION: | |
7611 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
7612 | break; | |
7613 | ||
7614 | case ARM_FT_INTERWORKED: | |
7615 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
7616 | break; | |
7617 | ||
7618 | default: | |
7619 | if (frame_pointer_needed) | |
7620 | /* If we used the frame pointer then the return adddress | |
7621 | will have been loaded off the stack directly into the | |
7622 | PC, so there is no need to issue a MOV instruction | |
7623 | here. */ | |
7624 | ; | |
7625 | else if (current_function_pretend_args_size == 0 | |
6f7ebcbb | 7626 | && (saved_regs_mask & (1 << LR_REGNUM))) |
6d3d9133 NC |
7627 | /* Similarly we may have been able to load LR into the PC |
7628 | even if we did not create a stack frame. */ | |
7629 | ; | |
7630 | else if (TARGET_APCS_32) | |
7631 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
7632 | else | |
7633 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
7634 | break; | |
cce8749e | 7635 | } |
f3bb6135 | 7636 | |
949d79eb RE |
7637 | return ""; |
7638 | } | |
7639 | ||
7640 | void | |
eb3921e8 | 7641 | output_func_epilogue (frame_size) |
949d79eb RE |
7642 | int frame_size; |
7643 | { | |
d5b7b3ae RE |
7644 | if (TARGET_THUMB) |
7645 | { | |
7646 | /* ??? Probably not safe to set this here, since it assumes that a | |
7647 | function will be emitted as assembly immediately after we generate | |
7648 | RTL for it. This does not happen for inline functions. */ | |
7649 | return_used_this_function = 0; | |
7650 | } | |
7651 | else | |
7652 | { | |
7653 | if (use_return_insn (FALSE) | |
7654 | && return_used_this_function | |
7655 | && (frame_size + current_function_outgoing_args_size) != 0 | |
5895f793 | 7656 | && !frame_pointer_needed) |
d5b7b3ae | 7657 | abort (); |
f3bb6135 | 7658 | |
d5b7b3ae RE |
7659 | /* Reset the ARM-specific per-function variables. */ |
7660 | current_function_anonymous_args = 0; | |
7661 | after_arm_reorg = 0; | |
7662 | } | |
f3bb6135 | 7663 | } |
e2c671ba | 7664 | |
2c849145 JM |
7665 | /* Generate and emit an insn that we will recognize as a push_multi. |
7666 | Unfortunately, since this insn does not reflect very well the actual | |
7667 | semantics of the operation, we need to annotate the insn for the benefit | |
7668 | of DWARF2 frame unwind information. */ | |
6d3d9133 | 7669 | |
2c849145 | 7670 | static rtx |
e2c671ba RE |
7671 | emit_multi_reg_push (mask) |
7672 | int mask; | |
7673 | { | |
7674 | int num_regs = 0; | |
9b598fa0 | 7675 | int num_dwarf_regs; |
e2c671ba RE |
7676 | int i, j; |
7677 | rtx par; | |
2c849145 | 7678 | rtx dwarf; |
87e27392 | 7679 | int dwarf_par_index; |
2c849145 | 7680 | rtx tmp, reg; |
e2c671ba | 7681 | |
d5b7b3ae | 7682 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 7683 | if (mask & (1 << i)) |
5895f793 | 7684 | num_regs++; |
e2c671ba RE |
7685 | |
7686 | if (num_regs == 0 || num_regs > 16) | |
7687 | abort (); | |
7688 | ||
9b598fa0 RE |
7689 | /* We don't record the PC in the dwarf frame information. */ |
7690 | num_dwarf_regs = num_regs; | |
7691 | if (mask & (1 << PC_REGNUM)) | |
7692 | num_dwarf_regs--; | |
7693 | ||
87e27392 NC |
7694 | /* For the body of the insn we are going to generate an UNSPEC in |
7695 | parallel with several USEs. This allows the insn to be recognised | |
7696 | by the push_multi pattern in the arm.md file. The insn looks | |
7697 | something like this: | |
7698 | ||
7699 | (parallel [ | |
b15bca31 RE |
7700 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
7701 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
7702 | (use (reg:SI 11 fp)) |
7703 | (use (reg:SI 12 ip)) | |
7704 | (use (reg:SI 14 lr)) | |
7705 | (use (reg:SI 15 pc)) | |
7706 | ]) | |
7707 | ||
7708 | For the frame note however, we try to be more explicit and actually | |
7709 | show each register being stored into the stack frame, plus a (single) | |
7710 | decrement of the stack pointer. We do it this way in order to be | |
7711 | friendly to the stack unwinding code, which only wants to see a single | |
7712 | stack decrement per instruction. The RTL we generate for the note looks | |
7713 | something like this: | |
7714 | ||
7715 | (sequence [ | |
7716 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) | |
7717 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
7718 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
7719 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
7720 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
7721 | ]) |
7722 | ||
7723 | This sequence is used both by the code to support stack unwinding for | |
7724 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
7725 | ||
43cffd11 | 7726 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 7727 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
2c849145 | 7728 | RTX_FRAME_RELATED_P (dwarf) = 1; |
87e27392 | 7729 | dwarf_par_index = 1; |
e2c671ba | 7730 | |
d5b7b3ae | 7731 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
7732 | { |
7733 | if (mask & (1 << i)) | |
7734 | { | |
2c849145 JM |
7735 | reg = gen_rtx_REG (SImode, i); |
7736 | ||
e2c671ba | 7737 | XVECEXP (par, 0, 0) |
43cffd11 RE |
7738 | = gen_rtx_SET (VOIDmode, |
7739 | gen_rtx_MEM (BLKmode, | |
7740 | gen_rtx_PRE_DEC (BLKmode, | |
7741 | stack_pointer_rtx)), | |
7742 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 7743 | gen_rtvec (1, reg), |
9b598fa0 | 7744 | UNSPEC_PUSH_MULT)); |
2c849145 | 7745 | |
9b598fa0 RE |
7746 | if (i != PC_REGNUM) |
7747 | { | |
7748 | tmp = gen_rtx_SET (VOIDmode, | |
7749 | gen_rtx_MEM (SImode, stack_pointer_rtx), | |
7750 | reg); | |
7751 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7752 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
7753 | dwarf_par_index++; | |
7754 | } | |
2c849145 | 7755 | |
e2c671ba RE |
7756 | break; |
7757 | } | |
7758 | } | |
7759 | ||
7760 | for (j = 1, i++; j < num_regs; i++) | |
7761 | { | |
7762 | if (mask & (1 << i)) | |
7763 | { | |
2c849145 JM |
7764 | reg = gen_rtx_REG (SImode, i); |
7765 | ||
7766 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
7767 | ||
9b598fa0 RE |
7768 | if (i != PC_REGNUM) |
7769 | { | |
7770 | tmp = gen_rtx_SET (VOIDmode, | |
7771 | gen_rtx_MEM (SImode, | |
7772 | plus_constant (stack_pointer_rtx, | |
7773 | 4 * j)), | |
7774 | reg); | |
7775 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7776 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
7777 | } | |
7778 | ||
e2c671ba RE |
7779 | j++; |
7780 | } | |
7781 | } | |
b111229a | 7782 | |
2c849145 | 7783 | par = emit_insn (par); |
87e27392 NC |
7784 | |
7785 | tmp = gen_rtx_SET (SImode, | |
7786 | stack_pointer_rtx, | |
7787 | gen_rtx_PLUS (SImode, | |
7788 | stack_pointer_rtx, | |
7789 | GEN_INT (-4 * num_regs))); | |
7790 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7791 | XVECEXP (dwarf, 0, 0) = tmp; | |
7792 | ||
2c849145 JM |
7793 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
7794 | REG_NOTES (par)); | |
7795 | return par; | |
b111229a RE |
7796 | } |
7797 | ||
2c849145 | 7798 | static rtx |
b111229a RE |
7799 | emit_sfm (base_reg, count) |
7800 | int base_reg; | |
7801 | int count; | |
7802 | { | |
7803 | rtx par; | |
2c849145 JM |
7804 | rtx dwarf; |
7805 | rtx tmp, reg; | |
b111229a RE |
7806 | int i; |
7807 | ||
43cffd11 | 7808 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 JM |
7809 | dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
7810 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
7811 | ||
7812 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
7813 | |
7814 | XVECEXP (par, 0, 0) | |
7815 | = gen_rtx_SET (VOIDmode, | |
7816 | gen_rtx_MEM (BLKmode, | |
7817 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
7818 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 7819 | gen_rtvec (1, reg), |
b15bca31 | 7820 | UNSPEC_PUSH_MULT)); |
2c849145 JM |
7821 | tmp |
7822 | = gen_rtx_SET (VOIDmode, | |
7823 | gen_rtx_MEM (XFmode, | |
7824 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
7825 | reg); | |
7826 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7827 | XVECEXP (dwarf, 0, count - 1) = tmp; | |
7828 | ||
b111229a | 7829 | for (i = 1; i < count; i++) |
2c849145 JM |
7830 | { |
7831 | reg = gen_rtx_REG (XFmode, base_reg++); | |
7832 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
7833 | ||
7834 | tmp = gen_rtx_SET (VOIDmode, | |
7835 | gen_rtx_MEM (XFmode, | |
7836 | gen_rtx_PRE_DEC (BLKmode, | |
7837 | stack_pointer_rtx)), | |
7838 | reg); | |
7839 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7840 | XVECEXP (dwarf, 0, count - i - 1) = tmp; | |
7841 | } | |
b111229a | 7842 | |
2c849145 JM |
7843 | par = emit_insn (par); |
7844 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
7845 | REG_NOTES (par)); | |
7846 | return par; | |
e2c671ba RE |
7847 | } |
7848 | ||
6d3d9133 NC |
7849 | /* Generate the prologue instructions for entry into an ARM function. */ |
7850 | ||
e2c671ba RE |
7851 | void |
7852 | arm_expand_prologue () | |
7853 | { | |
7854 | int reg; | |
6d3d9133 | 7855 | rtx amount; |
2c849145 | 7856 | rtx insn; |
68dfd979 | 7857 | rtx ip_rtx; |
6d3d9133 NC |
7858 | unsigned long live_regs_mask; |
7859 | unsigned long func_type; | |
68dfd979 | 7860 | int fp_offset = 0; |
d3236b4d | 7861 | |
6d3d9133 | 7862 | func_type = arm_current_func_type (); |
e2c671ba | 7863 | |
31fdb4d5 | 7864 | /* Naked functions don't have prologues. */ |
6d3d9133 | 7865 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
7866 | return; |
7867 | ||
6d3d9133 NC |
7868 | /* Compute which register we will have to save onto the stack. */ |
7869 | live_regs_mask = arm_compute_save_reg_mask (); | |
e2c671ba | 7870 | |
68dfd979 | 7871 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 7872 | |
e2c671ba RE |
7873 | if (frame_pointer_needed) |
7874 | { | |
7b8b8ade NC |
7875 | if (IS_INTERRUPT (func_type)) |
7876 | { | |
7877 | /* Interrupt functions must not corrupt any registers. | |
7878 | Creating a frame pointer however, corrupts the IP | |
7879 | register, so we must push it first. */ | |
7880 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
7881 | RTX_FRAME_RELATED_P (insn) = 1; | |
7882 | } | |
7883 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
7884 | { |
7885 | /* The Static chain register is the same as the IP register | |
7886 | used as a scratch register during stack frame creation. | |
7887 | To get around this need to find somewhere to store IP | |
7888 | whilst the frame is being created. We try the following | |
7889 | places in order: | |
7890 | ||
6d3d9133 | 7891 | 1. The last argument register. |
68dfd979 NC |
7892 | 2. A slot on the stack above the frame. (This only |
7893 | works if the function is not a varargs function). | |
7894 | ||
6d3d9133 NC |
7895 | If neither of these places is available, we abort (for now). |
7896 | ||
34ce3d7b JM |
7897 | Note - we only need to tell the dwarf2 backend about the SP |
7898 | adjustment in the second variant; the static chain register | |
7899 | doesn't need to be unwound, as it doesn't contain a value | |
7900 | inherited from the caller. */ | |
d3236b4d | 7901 | |
68dfd979 NC |
7902 | if (regs_ever_live[3] == 0) |
7903 | { | |
7904 | insn = gen_rtx_REG (SImode, 3); | |
7905 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
d3236b4d | 7906 | insn = emit_insn (insn); |
68dfd979 NC |
7907 | } |
7908 | else if (current_function_pretend_args_size == 0) | |
7909 | { | |
34ce3d7b | 7910 | rtx dwarf; |
68dfd979 NC |
7911 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
7912 | insn = gen_rtx_MEM (SImode, insn); | |
7913 | insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); | |
7914 | insn = emit_insn (insn); | |
34ce3d7b | 7915 | |
68dfd979 | 7916 | fp_offset = 4; |
34ce3d7b JM |
7917 | |
7918 | /* Just tell the dwarf backend that we adjusted SP. */ | |
7919 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
7920 | gen_rtx_PLUS (SImode, stack_pointer_rtx, | |
7921 | GEN_INT (-fp_offset))); | |
7922 | RTX_FRAME_RELATED_P (insn) = 1; | |
7923 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
7924 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
7925 | } |
7926 | else | |
7927 | /* FIXME - the way to handle this situation is to allow | |
7928 | the pretend args to be dumped onto the stack, then | |
7929 | reuse r3 to save IP. This would involve moving the | |
f18969c0 | 7930 | copying of SP into IP until after the pretend args |
68dfd979 | 7931 | have been dumped, but this is not too hard. */ |
f18969c0 PB |
7932 | /* [See e.g. gcc.c-torture/execute/nest-stdar-1.c.] */ |
7933 | error ("Unable to find a temporary location for static chain register"); | |
68dfd979 NC |
7934 | } |
7935 | ||
68dfd979 NC |
7936 | if (fp_offset) |
7937 | { | |
7938 | insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); | |
7939 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
7940 | } | |
7941 | else | |
7942 | insn = gen_movsi (ip_rtx, stack_pointer_rtx); | |
7943 | ||
6d3d9133 | 7944 | insn = emit_insn (insn); |
8e56560e | 7945 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
7946 | } |
7947 | ||
7948 | if (current_function_pretend_args_size) | |
7949 | { | |
6d3d9133 NC |
7950 | /* Push the argument registers, or reserve space for them. */ |
7951 | if (current_function_anonymous_args) | |
2c849145 JM |
7952 | insn = emit_multi_reg_push |
7953 | ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf); | |
e2c671ba | 7954 | else |
2c849145 JM |
7955 | insn = emit_insn |
7956 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
7957 | GEN_INT (-current_function_pretend_args_size))); | |
7958 | RTX_FRAME_RELATED_P (insn) = 1; | |
e2c671ba RE |
7959 | } |
7960 | ||
7961 | if (live_regs_mask) | |
7962 | { | |
2c849145 JM |
7963 | insn = emit_multi_reg_push (live_regs_mask); |
7964 | RTX_FRAME_RELATED_P (insn) = 1; | |
e2c671ba | 7965 | } |
d5b7b3ae | 7966 | |
6d3d9133 | 7967 | if (! IS_VOLATILE (func_type)) |
b111229a | 7968 | { |
6d3d9133 | 7969 | /* Save any floating point call-saved registers used by this function. */ |
b111229a RE |
7970 | if (arm_fpu_arch == FP_SOFT2) |
7971 | { | |
d5b7b3ae | 7972 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) |
5895f793 | 7973 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
2c849145 JM |
7974 | { |
7975 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
7976 | insn = gen_rtx_MEM (XFmode, insn); | |
7977 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
7978 | gen_rtx_REG (XFmode, reg))); | |
7979 | RTX_FRAME_RELATED_P (insn) = 1; | |
7980 | } | |
b111229a RE |
7981 | } |
7982 | else | |
7983 | { | |
d5b7b3ae | 7984 | int start_reg = LAST_ARM_FP_REGNUM; |
b111229a | 7985 | |
d5b7b3ae | 7986 | for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) |
b111229a | 7987 | { |
5895f793 | 7988 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
7989 | { |
7990 | if (start_reg - reg == 3) | |
7991 | { | |
2c849145 JM |
7992 | insn = emit_sfm (reg, 4); |
7993 | RTX_FRAME_RELATED_P (insn) = 1; | |
b111229a RE |
7994 | start_reg = reg - 1; |
7995 | } | |
7996 | } | |
7997 | else | |
7998 | { | |
7999 | if (start_reg != reg) | |
2c849145 JM |
8000 | { |
8001 | insn = emit_sfm (reg + 1, start_reg - reg); | |
8002 | RTX_FRAME_RELATED_P (insn) = 1; | |
8003 | } | |
b111229a RE |
8004 | start_reg = reg - 1; |
8005 | } | |
8006 | } | |
8007 | ||
8008 | if (start_reg != reg) | |
2c849145 JM |
8009 | { |
8010 | insn = emit_sfm (reg + 1, start_reg - reg); | |
8011 | RTX_FRAME_RELATED_P (insn) = 1; | |
8012 | } | |
b111229a RE |
8013 | } |
8014 | } | |
e2c671ba RE |
8015 | |
8016 | if (frame_pointer_needed) | |
2c849145 | 8017 | { |
6d3d9133 | 8018 | /* Create the new frame pointer. */ |
68dfd979 NC |
8019 | insn = GEN_INT (-(4 + current_function_pretend_args_size + fp_offset)); |
8020 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
2c849145 | 8021 | RTX_FRAME_RELATED_P (insn) = 1; |
68dfd979 | 8022 | |
6d3d9133 | 8023 | if (IS_NESTED (func_type)) |
68dfd979 NC |
8024 | { |
8025 | /* Recover the static chain register. */ | |
8026 | if (regs_ever_live [3] == 0) | |
8027 | { | |
8028 | insn = gen_rtx_REG (SImode, 3); | |
8029 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
8030 | insn = emit_insn (insn); | |
68dfd979 NC |
8031 | } |
8032 | else /* if (current_function_pretend_args_size == 0) */ | |
8033 | { | |
8034 | insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4)); | |
8035 | insn = gen_rtx_MEM (SImode, insn); | |
8036 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
8037 | insn = emit_insn (insn); | |
68dfd979 NC |
8038 | } |
8039 | } | |
2c849145 | 8040 | } |
e2c671ba | 8041 | |
6d3d9133 NC |
8042 | amount = GEN_INT (-(get_frame_size () |
8043 | + current_function_outgoing_args_size)); | |
8044 | ||
e2c671ba RE |
8045 | if (amount != const0_rtx) |
8046 | { | |
745b9093 JM |
8047 | /* This add can produce multiple insns for a large constant, so we |
8048 | need to get tricky. */ | |
8049 | rtx last = get_last_insn (); | |
2c849145 JM |
8050 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
8051 | amount)); | |
745b9093 JM |
8052 | do |
8053 | { | |
8054 | last = last ? NEXT_INSN (last) : get_insns (); | |
8055 | RTX_FRAME_RELATED_P (last) = 1; | |
8056 | } | |
8057 | while (last != insn); | |
e04c2d6c RE |
8058 | |
8059 | /* If the frame pointer is needed, emit a special barrier that | |
8060 | will prevent the scheduler from moving stores to the frame | |
8061 | before the stack adjustment. */ | |
8062 | if (frame_pointer_needed) | |
8063 | { | |
8064 | rtx unspec = gen_rtx_UNSPEC (SImode, | |
8065 | gen_rtvec (2, stack_pointer_rtx, | |
b15bca31 RE |
8066 | hard_frame_pointer_rtx), |
8067 | UNSPEC_PRLG_STK); | |
e04c2d6c | 8068 | |
6d3d9133 | 8069 | insn = emit_insn (gen_rtx_CLOBBER (VOIDmode, |
e04c2d6c RE |
8070 | gen_rtx_MEM (BLKmode, unspec))); |
8071 | } | |
e2c671ba RE |
8072 | } |
8073 | ||
8074 | /* If we are profiling, make sure no instructions are scheduled before | |
f5a1b0d2 NC |
8075 | the call to mcount. Similarly if the user has requested no |
8076 | scheduling in the prolog. */ | |
8077 | if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO) | |
e2c671ba | 8078 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
8079 | |
8080 | /* If the link register is being kept alive, with the return address in it, | |
8081 | then make sure that it does not get reused by the ce2 pass. */ | |
8082 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
8083 | { | |
8084 | emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))); | |
8085 | cfun->machine->lr_save_eliminated = 1; | |
8086 | } | |
e2c671ba | 8087 | } |
cce8749e | 8088 | \f |
9997d19d RE |
8089 | /* If CODE is 'd', then the X is a condition operand and the instruction |
8090 | should only be executed if the condition is true. | |
ddd5a7c1 | 8091 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
8092 | should only be executed if the condition is false: however, if the mode |
8093 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
8094 | do this because in these circumstances !GE does not necessarily imply LT; | |
8095 | in these cases the instruction pattern will take care to make sure that | |
8096 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 8097 | doing this instruction unconditionally. |
9997d19d RE |
8098 | If CODE is 'N' then X is a floating point operand that must be negated |
8099 | before output. | |
8100 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
8101 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
8102 | ||
8103 | void | |
8104 | arm_print_operand (stream, x, code) | |
62b10bbc | 8105 | FILE * stream; |
9997d19d RE |
8106 | rtx x; |
8107 | int code; | |
8108 | { | |
8109 | switch (code) | |
8110 | { | |
8111 | case '@': | |
f3139301 | 8112 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
8113 | return; |
8114 | ||
d5b7b3ae RE |
8115 | case '_': |
8116 | fputs (user_label_prefix, stream); | |
8117 | return; | |
8118 | ||
9997d19d | 8119 | case '|': |
f3139301 | 8120 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
8121 | return; |
8122 | ||
8123 | case '?': | |
8124 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
cca0a211 RE |
8125 | { |
8126 | if (TARGET_THUMB || current_insn_predicate != NULL) | |
8127 | abort (); | |
8128 | ||
8129 | fputs (arm_condition_codes[arm_current_cc], stream); | |
8130 | } | |
8131 | else if (current_insn_predicate) | |
8132 | { | |
8133 | enum arm_cond_code code; | |
8134 | ||
8135 | if (TARGET_THUMB) | |
8136 | abort (); | |
8137 | ||
8138 | code = get_arm_condition_code (current_insn_predicate); | |
8139 | fputs (arm_condition_codes[code], stream); | |
8140 | } | |
9997d19d RE |
8141 | return; |
8142 | ||
8143 | case 'N': | |
8144 | { | |
8145 | REAL_VALUE_TYPE r; | |
8146 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
8147 | r = REAL_VALUE_NEGATE (r); | |
8148 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
8149 | } | |
8150 | return; | |
8151 | ||
8152 | case 'B': | |
8153 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
8154 | { |
8155 | HOST_WIDE_INT val; | |
5895f793 | 8156 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 8157 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 8158 | } |
9997d19d RE |
8159 | else |
8160 | { | |
8161 | putc ('~', stream); | |
8162 | output_addr_const (stream, x); | |
8163 | } | |
8164 | return; | |
8165 | ||
8166 | case 'i': | |
8167 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
8168 | return; | |
8169 | ||
8170 | case 'I': | |
8171 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
8172 | return; | |
8173 | ||
8174 | case 'S': | |
8175 | { | |
8176 | HOST_WIDE_INT val; | |
5895f793 | 8177 | const char * shift = shift_op (x, &val); |
9997d19d | 8178 | |
e2c671ba RE |
8179 | if (shift) |
8180 | { | |
5895f793 | 8181 | fprintf (stream, ", %s ", shift_op (x, &val)); |
e2c671ba RE |
8182 | if (val == -1) |
8183 | arm_print_operand (stream, XEXP (x, 1), 0); | |
8184 | else | |
4bc74ece NC |
8185 | { |
8186 | fputc ('#', stream); | |
36ba9cb8 | 8187 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 8188 | } |
e2c671ba | 8189 | } |
9997d19d RE |
8190 | } |
8191 | return; | |
8192 | ||
d5b7b3ae RE |
8193 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
8194 | ||
8195 | In a pair of registers containing a DI or DF value the 'Q' | |
8196 | operand returns the register number of the register containing | |
8197 | the least signficant part of the value. The 'R' operand returns | |
8198 | the register number of the register containing the most | |
8199 | significant part of the value. | |
8200 | ||
8201 | The 'H' operand returns the higher of the two register numbers. | |
8202 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
8203 | same as the 'Q' operand, since the most signficant part of the | |
8204 | value is held in the lower number register. The reverse is true | |
8205 | on systems where WORDS_BIG_ENDIAN is false. | |
8206 | ||
8207 | The purpose of these operands is to distinguish between cases | |
8208 | where the endian-ness of the values is important (for example | |
8209 | when they are added together), and cases where the endian-ness | |
8210 | is irrelevant, but the order of register operations is important. | |
8211 | For example when loading a value from memory into a register | |
8212 | pair, the endian-ness does not matter. Provided that the value | |
8213 | from the lower memory address is put into the lower numbered | |
8214 | register, and the value from the higher address is put into the | |
8215 | higher numbered register, the load will work regardless of whether | |
8216 | the value being loaded is big-wordian or little-wordian. The | |
8217 | order of the two register loads can matter however, if the address | |
8218 | of the memory location is actually held in one of the registers | |
8219 | being overwritten by the load. */ | |
c1c2bc04 | 8220 | case 'Q': |
d5b7b3ae | 8221 | if (REGNO (x) > LAST_ARM_REGNUM) |
c1c2bc04 | 8222 | abort (); |
d5b7b3ae | 8223 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
8224 | return; |
8225 | ||
9997d19d | 8226 | case 'R': |
d5b7b3ae | 8227 | if (REGNO (x) > LAST_ARM_REGNUM) |
9997d19d | 8228 | abort (); |
d5b7b3ae RE |
8229 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
8230 | return; | |
8231 | ||
8232 | case 'H': | |
8233 | if (REGNO (x) > LAST_ARM_REGNUM) | |
8234 | abort (); | |
8235 | asm_fprintf (stream, "%r", REGNO (x) + 1); | |
9997d19d RE |
8236 | return; |
8237 | ||
8238 | case 'm': | |
d5b7b3ae RE |
8239 | asm_fprintf (stream, "%r", |
8240 | GET_CODE (XEXP (x, 0)) == REG | |
8241 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
8242 | return; |
8243 | ||
8244 | case 'M': | |
dd18ae56 | 8245 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae RE |
8246 | REGNO (x), |
8247 | REGNO (x) + NUM_REGS (GET_MODE (x)) - 1); | |
9997d19d RE |
8248 | return; |
8249 | ||
8250 | case 'd': | |
5895f793 | 8251 | if (!x) |
d5b7b3ae RE |
8252 | return; |
8253 | ||
8254 | if (TARGET_ARM) | |
9997d19d RE |
8255 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
8256 | stream); | |
d5b7b3ae RE |
8257 | else |
8258 | fputs (thumb_condition_code (x, 0), stream); | |
9997d19d RE |
8259 | return; |
8260 | ||
8261 | case 'D': | |
5895f793 | 8262 | if (!x) |
d5b7b3ae RE |
8263 | return; |
8264 | ||
8265 | if (TARGET_ARM) | |
8266 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE | |
8267 | (get_arm_condition_code (x))], | |
9997d19d | 8268 | stream); |
d5b7b3ae RE |
8269 | else |
8270 | fputs (thumb_condition_code (x, 1), stream); | |
9997d19d RE |
8271 | return; |
8272 | ||
8273 | default: | |
8274 | if (x == 0) | |
8275 | abort (); | |
8276 | ||
8277 | if (GET_CODE (x) == REG) | |
d5b7b3ae | 8278 | asm_fprintf (stream, "%r", REGNO (x)); |
9997d19d RE |
8279 | else if (GET_CODE (x) == MEM) |
8280 | { | |
8281 | output_memory_reference_mode = GET_MODE (x); | |
8282 | output_address (XEXP (x, 0)); | |
8283 | } | |
8284 | else if (GET_CODE (x) == CONST_DOUBLE) | |
8285 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
8286 | else if (GET_CODE (x) == NEG) | |
6354dc9b | 8287 | abort (); /* This should never happen now. */ |
9997d19d RE |
8288 | else |
8289 | { | |
8290 | fputc ('#', stream); | |
8291 | output_addr_const (stream, x); | |
8292 | } | |
8293 | } | |
8294 | } | |
cce8749e CH |
8295 | \f |
8296 | /* A finite state machine takes care of noticing whether or not instructions | |
8297 | can be conditionally executed, and thus decrease execution time and code | |
8298 | size by deleting branch instructions. The fsm is controlled by | |
8299 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
8300 | ||
8301 | /* The state of the fsm controlling condition codes are: | |
8302 | 0: normal, do nothing special | |
8303 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
8304 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
8305 | 3: make instructions conditional | |
8306 | 4: make instructions conditional | |
8307 | ||
8308 | State transitions (state->state by whom under condition): | |
8309 | 0 -> 1 final_prescan_insn if the `target' is a label | |
8310 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
8311 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
8312 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
8313 | 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached | |
8314 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). | |
8315 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
8316 | (the target insn is arm_target_insn). | |
8317 | ||
ff9940b0 RE |
8318 | If the jump clobbers the conditions then we use states 2 and 4. |
8319 | ||
8320 | A similar thing can be done with conditional return insns. | |
8321 | ||
cce8749e CH |
8322 | XXX In case the `target' is an unconditional branch, this conditionalising |
8323 | of the instructions always reduces code size, but not always execution | |
8324 | time. But then, I want to reduce the code size to somewhere near what | |
8325 | /bin/cc produces. */ | |
8326 | ||
cce8749e CH |
8327 | /* Returns the index of the ARM condition code string in |
8328 | `arm_condition_codes'. COMPARISON should be an rtx like | |
8329 | `(eq (...) (...))'. */ | |
8330 | ||
84ed5e79 | 8331 | static enum arm_cond_code |
cce8749e CH |
8332 | get_arm_condition_code (comparison) |
8333 | rtx comparison; | |
8334 | { | |
5165176d | 8335 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
84ed5e79 RE |
8336 | register int code; |
8337 | register enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
8338 | |
8339 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 8340 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
8341 | XEXP (comparison, 1)); |
8342 | ||
8343 | switch (mode) | |
cce8749e | 8344 | { |
84ed5e79 RE |
8345 | case CC_DNEmode: code = ARM_NE; goto dominance; |
8346 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
8347 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
8348 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
8349 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
8350 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
8351 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
8352 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
8353 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
8354 | case CC_DLTUmode: code = ARM_CC; | |
8355 | ||
8356 | dominance: | |
8357 | if (comp_code != EQ && comp_code != NE) | |
8358 | abort (); | |
8359 | ||
8360 | if (comp_code == EQ) | |
8361 | return ARM_INVERSE_CONDITION_CODE (code); | |
8362 | return code; | |
8363 | ||
5165176d | 8364 | case CC_NOOVmode: |
84ed5e79 | 8365 | switch (comp_code) |
5165176d | 8366 | { |
84ed5e79 RE |
8367 | case NE: return ARM_NE; |
8368 | case EQ: return ARM_EQ; | |
8369 | case GE: return ARM_PL; | |
8370 | case LT: return ARM_MI; | |
5165176d RE |
8371 | default: abort (); |
8372 | } | |
8373 | ||
8374 | case CC_Zmode: | |
84ed5e79 | 8375 | switch (comp_code) |
5165176d | 8376 | { |
84ed5e79 RE |
8377 | case NE: return ARM_NE; |
8378 | case EQ: return ARM_EQ; | |
5165176d RE |
8379 | default: abort (); |
8380 | } | |
8381 | ||
8382 | case CCFPEmode: | |
e45b72c4 RE |
8383 | case CCFPmode: |
8384 | /* These encodings assume that AC=1 in the FPA system control | |
8385 | byte. This allows us to handle all cases except UNEQ and | |
8386 | LTGT. */ | |
84ed5e79 RE |
8387 | switch (comp_code) |
8388 | { | |
8389 | case GE: return ARM_GE; | |
8390 | case GT: return ARM_GT; | |
8391 | case LE: return ARM_LS; | |
8392 | case LT: return ARM_MI; | |
e45b72c4 RE |
8393 | case NE: return ARM_NE; |
8394 | case EQ: return ARM_EQ; | |
8395 | case ORDERED: return ARM_VC; | |
8396 | case UNORDERED: return ARM_VS; | |
8397 | case UNLT: return ARM_LT; | |
8398 | case UNLE: return ARM_LE; | |
8399 | case UNGT: return ARM_HI; | |
8400 | case UNGE: return ARM_PL; | |
8401 | /* UNEQ and LTGT do not have a representation. */ | |
8402 | case UNEQ: /* Fall through. */ | |
8403 | case LTGT: /* Fall through. */ | |
84ed5e79 RE |
8404 | default: abort (); |
8405 | } | |
8406 | ||
8407 | case CC_SWPmode: | |
8408 | switch (comp_code) | |
8409 | { | |
8410 | case NE: return ARM_NE; | |
8411 | case EQ: return ARM_EQ; | |
8412 | case GE: return ARM_LE; | |
8413 | case GT: return ARM_LT; | |
8414 | case LE: return ARM_GE; | |
8415 | case LT: return ARM_GT; | |
8416 | case GEU: return ARM_LS; | |
8417 | case GTU: return ARM_CC; | |
8418 | case LEU: return ARM_CS; | |
8419 | case LTU: return ARM_HI; | |
8420 | default: abort (); | |
8421 | } | |
8422 | ||
bd9c7e23 RE |
8423 | case CC_Cmode: |
8424 | switch (comp_code) | |
8425 | { | |
8426 | case LTU: return ARM_CS; | |
8427 | case GEU: return ARM_CC; | |
8428 | default: abort (); | |
8429 | } | |
8430 | ||
5165176d | 8431 | case CCmode: |
84ed5e79 | 8432 | switch (comp_code) |
5165176d | 8433 | { |
84ed5e79 RE |
8434 | case NE: return ARM_NE; |
8435 | case EQ: return ARM_EQ; | |
8436 | case GE: return ARM_GE; | |
8437 | case GT: return ARM_GT; | |
8438 | case LE: return ARM_LE; | |
8439 | case LT: return ARM_LT; | |
8440 | case GEU: return ARM_CS; | |
8441 | case GTU: return ARM_HI; | |
8442 | case LEU: return ARM_LS; | |
8443 | case LTU: return ARM_CC; | |
5165176d RE |
8444 | default: abort (); |
8445 | } | |
8446 | ||
cce8749e CH |
8447 | default: abort (); |
8448 | } | |
84ed5e79 RE |
8449 | |
8450 | abort (); | |
f3bb6135 | 8451 | } |
cce8749e CH |
8452 | |
8453 | ||
8454 | void | |
74bbc178 | 8455 | arm_final_prescan_insn (insn) |
cce8749e | 8456 | rtx insn; |
cce8749e CH |
8457 | { |
8458 | /* BODY will hold the body of INSN. */ | |
8459 | register rtx body = PATTERN (insn); | |
8460 | ||
8461 | /* This will be 1 if trying to repeat the trick, and things need to be | |
8462 | reversed if it appears to fail. */ | |
8463 | int reverse = 0; | |
8464 | ||
ff9940b0 RE |
8465 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
8466 | taken are clobbered, even if the rtl suggests otherwise. It also | |
8467 | means that we have to grub around within the jump expression to find | |
8468 | out what the conditions are when the jump isn't taken. */ | |
8469 | int jump_clobbers = 0; | |
8470 | ||
6354dc9b | 8471 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 RE |
8472 | int seeking_return = 0; |
8473 | ||
cce8749e CH |
8474 | /* START_INSN will hold the insn from where we start looking. This is the |
8475 | first insn after the following code_label if REVERSE is true. */ | |
8476 | rtx start_insn = insn; | |
8477 | ||
8478 | /* If in state 4, check if the target branch is reached, in order to | |
8479 | change back to state 0. */ | |
8480 | if (arm_ccfsm_state == 4) | |
8481 | { | |
8482 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
8483 | { |
8484 | arm_target_insn = NULL; | |
8485 | arm_ccfsm_state = 0; | |
8486 | } | |
cce8749e CH |
8487 | return; |
8488 | } | |
8489 | ||
8490 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
8491 | unconditional branch to a label, and immediately following this branch | |
8492 | is the previous target label which is only used once, and the label this | |
8493 | branch jumps to is not too far off. */ | |
8494 | if (arm_ccfsm_state == 3) | |
8495 | { | |
8496 | if (simplejump_p (insn)) | |
8497 | { | |
8498 | start_insn = next_nonnote_insn (start_insn); | |
8499 | if (GET_CODE (start_insn) == BARRIER) | |
8500 | { | |
8501 | /* XXX Isn't this always a barrier? */ | |
8502 | start_insn = next_nonnote_insn (start_insn); | |
8503 | } | |
8504 | if (GET_CODE (start_insn) == CODE_LABEL | |
8505 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
8506 | && LABEL_NUSES (start_insn) == 1) | |
8507 | reverse = TRUE; | |
8508 | else | |
8509 | return; | |
8510 | } | |
ff9940b0 RE |
8511 | else if (GET_CODE (body) == RETURN) |
8512 | { | |
8513 | start_insn = next_nonnote_insn (start_insn); | |
8514 | if (GET_CODE (start_insn) == BARRIER) | |
8515 | start_insn = next_nonnote_insn (start_insn); | |
8516 | if (GET_CODE (start_insn) == CODE_LABEL | |
8517 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
8518 | && LABEL_NUSES (start_insn) == 1) | |
8519 | { | |
8520 | reverse = TRUE; | |
8521 | seeking_return = 1; | |
8522 | } | |
8523 | else | |
8524 | return; | |
8525 | } | |
cce8749e CH |
8526 | else |
8527 | return; | |
8528 | } | |
8529 | ||
8530 | if (arm_ccfsm_state != 0 && !reverse) | |
8531 | abort (); | |
8532 | if (GET_CODE (insn) != JUMP_INSN) | |
8533 | return; | |
8534 | ||
ddd5a7c1 | 8535 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
8536 | the jump should always come first */ |
8537 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
8538 | body = XVECEXP (body, 0, 0); | |
8539 | ||
8540 | #if 0 | |
8541 | /* If this is a conditional return then we don't want to know */ | |
8542 | if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
8543 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE | |
8544 | && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN | |
8545 | || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) | |
8546 | return; | |
8547 | #endif | |
8548 | ||
cce8749e CH |
8549 | if (reverse |
8550 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
8551 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
8552 | { | |
bd9c7e23 RE |
8553 | int insns_skipped; |
8554 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
8555 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
8556 | int then_not_else = TRUE; | |
ff9940b0 | 8557 | rtx this_insn = start_insn, label = 0; |
cce8749e | 8558 | |
e45b72c4 RE |
8559 | /* If the jump cannot be done with one instruction, we cannot |
8560 | conditionally execute the instruction in the inverse case. */ | |
ff9940b0 | 8561 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 8562 | { |
5bbe2d40 RE |
8563 | jump_clobbers = 1; |
8564 | return; | |
8565 | } | |
ff9940b0 | 8566 | |
cce8749e CH |
8567 | /* Register the insn jumped to. */ |
8568 | if (reverse) | |
ff9940b0 RE |
8569 | { |
8570 | if (!seeking_return) | |
8571 | label = XEXP (SET_SRC (body), 0); | |
8572 | } | |
cce8749e CH |
8573 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
8574 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
8575 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
8576 | { | |
8577 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
8578 | then_not_else = FALSE; | |
8579 | } | |
ff9940b0 RE |
8580 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
8581 | seeking_return = 1; | |
8582 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
8583 | { | |
8584 | seeking_return = 1; | |
8585 | then_not_else = FALSE; | |
8586 | } | |
cce8749e CH |
8587 | else |
8588 | abort (); | |
8589 | ||
8590 | /* See how many insns this branch skips, and what kind of insns. If all | |
8591 | insns are okay, and the label or unconditional branch to the same | |
8592 | label is not too far away, succeed. */ | |
8593 | for (insns_skipped = 0; | |
b36ba79f | 8594 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
8595 | { |
8596 | rtx scanbody; | |
8597 | ||
8598 | this_insn = next_nonnote_insn (this_insn); | |
8599 | if (!this_insn) | |
8600 | break; | |
8601 | ||
cce8749e CH |
8602 | switch (GET_CODE (this_insn)) |
8603 | { | |
8604 | case CODE_LABEL: | |
8605 | /* Succeed if it is the target label, otherwise fail since | |
8606 | control falls in from somewhere else. */ | |
8607 | if (this_insn == label) | |
8608 | { | |
ff9940b0 RE |
8609 | if (jump_clobbers) |
8610 | { | |
8611 | arm_ccfsm_state = 2; | |
8612 | this_insn = next_nonnote_insn (this_insn); | |
8613 | } | |
8614 | else | |
8615 | arm_ccfsm_state = 1; | |
cce8749e CH |
8616 | succeed = TRUE; |
8617 | } | |
8618 | else | |
8619 | fail = TRUE; | |
8620 | break; | |
8621 | ||
ff9940b0 | 8622 | case BARRIER: |
cce8749e | 8623 | /* Succeed if the following insn is the target label. |
ff9940b0 RE |
8624 | Otherwise fail. |
8625 | If return insns are used then the last insn in a function | |
6354dc9b | 8626 | will be a barrier. */ |
cce8749e | 8627 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 8628 | if (this_insn && this_insn == label) |
cce8749e | 8629 | { |
ff9940b0 RE |
8630 | if (jump_clobbers) |
8631 | { | |
8632 | arm_ccfsm_state = 2; | |
8633 | this_insn = next_nonnote_insn (this_insn); | |
8634 | } | |
8635 | else | |
8636 | arm_ccfsm_state = 1; | |
cce8749e CH |
8637 | succeed = TRUE; |
8638 | } | |
8639 | else | |
8640 | fail = TRUE; | |
8641 | break; | |
8642 | ||
ff9940b0 | 8643 | case CALL_INSN: |
2b835d68 | 8644 | /* If using 32-bit addresses the cc is not preserved over |
914a3b8c | 8645 | calls. */ |
2b835d68 | 8646 | if (TARGET_APCS_32) |
bd9c7e23 RE |
8647 | { |
8648 | /* Succeed if the following insn is the target label, | |
8649 | or if the following two insns are a barrier and | |
8650 | the target label. */ | |
8651 | this_insn = next_nonnote_insn (this_insn); | |
8652 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
8653 | this_insn = next_nonnote_insn (this_insn); | |
8654 | ||
8655 | if (this_insn && this_insn == label | |
b36ba79f | 8656 | && insns_skipped < max_insns_skipped) |
bd9c7e23 RE |
8657 | { |
8658 | if (jump_clobbers) | |
8659 | { | |
8660 | arm_ccfsm_state = 2; | |
8661 | this_insn = next_nonnote_insn (this_insn); | |
8662 | } | |
8663 | else | |
8664 | arm_ccfsm_state = 1; | |
8665 | succeed = TRUE; | |
8666 | } | |
8667 | else | |
8668 | fail = TRUE; | |
8669 | } | |
ff9940b0 | 8670 | break; |
2b835d68 | 8671 | |
cce8749e CH |
8672 | case JUMP_INSN: |
8673 | /* If this is an unconditional branch to the same label, succeed. | |
8674 | If it is to another label, do nothing. If it is conditional, | |
8675 | fail. */ | |
914a3b8c | 8676 | /* XXX Probably, the tests for SET and the PC are unnecessary. */ |
cce8749e | 8677 | |
ed4c4348 | 8678 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
8679 | if (GET_CODE (scanbody) == SET |
8680 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
8681 | { |
8682 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
8683 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
8684 | { | |
8685 | arm_ccfsm_state = 2; | |
8686 | succeed = TRUE; | |
8687 | } | |
8688 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
8689 | fail = TRUE; | |
8690 | } | |
b36ba79f RE |
8691 | /* Fail if a conditional return is undesirable (eg on a |
8692 | StrongARM), but still allow this if optimizing for size. */ | |
8693 | else if (GET_CODE (scanbody) == RETURN | |
5895f793 RE |
8694 | && !use_return_insn (TRUE) |
8695 | && !optimize_size) | |
b36ba79f | 8696 | fail = TRUE; |
ff9940b0 RE |
8697 | else if (GET_CODE (scanbody) == RETURN |
8698 | && seeking_return) | |
8699 | { | |
8700 | arm_ccfsm_state = 2; | |
8701 | succeed = TRUE; | |
8702 | } | |
8703 | else if (GET_CODE (scanbody) == PARALLEL) | |
8704 | { | |
8705 | switch (get_attr_conds (this_insn)) | |
8706 | { | |
8707 | case CONDS_NOCOND: | |
8708 | break; | |
8709 | default: | |
8710 | fail = TRUE; | |
8711 | break; | |
8712 | } | |
8713 | } | |
4e67550b RE |
8714 | else |
8715 | fail = TRUE; /* Unrecognized jump (eg epilogue). */ | |
8716 | ||
cce8749e CH |
8717 | break; |
8718 | ||
8719 | case INSN: | |
ff9940b0 RE |
8720 | /* Instructions using or affecting the condition codes make it |
8721 | fail. */ | |
ed4c4348 | 8722 | scanbody = PATTERN (this_insn); |
5895f793 RE |
8723 | if (!(GET_CODE (scanbody) == SET |
8724 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 8725 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e CH |
8726 | fail = TRUE; |
8727 | break; | |
8728 | ||
8729 | default: | |
8730 | break; | |
8731 | } | |
8732 | } | |
8733 | if (succeed) | |
8734 | { | |
ff9940b0 | 8735 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 8736 | arm_target_label = CODE_LABEL_NUMBER (label); |
ff9940b0 RE |
8737 | else if (seeking_return || arm_ccfsm_state == 2) |
8738 | { | |
8739 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) | |
8740 | { | |
8741 | this_insn = next_nonnote_insn (this_insn); | |
8742 | if (this_insn && (GET_CODE (this_insn) == BARRIER | |
8743 | || GET_CODE (this_insn) == CODE_LABEL)) | |
8744 | abort (); | |
8745 | } | |
8746 | if (!this_insn) | |
8747 | { | |
8748 | /* Oh, dear! we ran off the end.. give up */ | |
df4ae160 | 8749 | recog (PATTERN (insn), insn, NULL); |
ff9940b0 | 8750 | arm_ccfsm_state = 0; |
abaa26e5 | 8751 | arm_target_insn = NULL; |
ff9940b0 RE |
8752 | return; |
8753 | } | |
8754 | arm_target_insn = this_insn; | |
8755 | } | |
cce8749e CH |
8756 | else |
8757 | abort (); | |
ff9940b0 RE |
8758 | if (jump_clobbers) |
8759 | { | |
8760 | if (reverse) | |
8761 | abort (); | |
8762 | arm_current_cc = | |
8763 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), | |
8764 | 0), 0), 1)); | |
8765 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
8766 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
8767 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
8768 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
8769 | } | |
8770 | else | |
8771 | { | |
8772 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
8773 | what it was. */ | |
8774 | if (!reverse) | |
8775 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
8776 | 0)); | |
8777 | } | |
cce8749e | 8778 | |
cce8749e CH |
8779 | if (reverse || then_not_else) |
8780 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
8781 | } | |
d5b7b3ae | 8782 | |
1ccbefce | 8783 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 8784 | destroy this array, but final.c assumes that it remains intact |
ddd5a7c1 | 8785 | across this call; since the insn has been recognized already we |
b020fd92 | 8786 | call recog direct). */ |
df4ae160 | 8787 | recog (PATTERN (insn), insn, NULL); |
cce8749e | 8788 | } |
f3bb6135 | 8789 | } |
cce8749e | 8790 | |
d5b7b3ae RE |
8791 | int |
8792 | arm_regno_class (regno) | |
8793 | int regno; | |
8794 | { | |
8795 | if (TARGET_THUMB) | |
8796 | { | |
8797 | if (regno == STACK_POINTER_REGNUM) | |
8798 | return STACK_REG; | |
8799 | if (regno == CC_REGNUM) | |
8800 | return CC_REG; | |
8801 | if (regno < 8) | |
8802 | return LO_REGS; | |
8803 | return HI_REGS; | |
8804 | } | |
8805 | ||
8806 | if ( regno <= LAST_ARM_REGNUM | |
8807 | || regno == FRAME_POINTER_REGNUM | |
8808 | || regno == ARG_POINTER_REGNUM) | |
8809 | return GENERAL_REGS; | |
8810 | ||
8811 | if (regno == CC_REGNUM) | |
8812 | return NO_REGS; | |
8813 | ||
8814 | return FPU_REGS; | |
8815 | } | |
8816 | ||
8817 | /* Handle a special case when computing the offset | |
8818 | of an argument from the frame pointer. */ | |
8819 | int | |
8820 | arm_debugger_arg_offset (value, addr) | |
8821 | int value; | |
8822 | rtx addr; | |
8823 | { | |
8824 | rtx insn; | |
8825 | ||
8826 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
8827 | if (value != 0) | |
8828 | return 0; | |
8829 | ||
8830 | /* We can only cope with the case where the address is held in a register. */ | |
8831 | if (GET_CODE (addr) != REG) | |
8832 | return 0; | |
8833 | ||
8834 | /* If we are using the frame pointer to point at the argument, then | |
8835 | an offset of 0 is correct. */ | |
cd2b33d0 | 8836 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae RE |
8837 | return 0; |
8838 | ||
8839 | /* If we are using the stack pointer to point at the | |
8840 | argument, then an offset of 0 is correct. */ | |
5895f793 | 8841 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
8842 | && REGNO (addr) == SP_REGNUM) |
8843 | return 0; | |
8844 | ||
8845 | /* Oh dear. The argument is pointed to by a register rather | |
8846 | than being held in a register, or being stored at a known | |
8847 | offset from the frame pointer. Since GDB only understands | |
8848 | those two kinds of argument we must translate the address | |
8849 | held in the register into an offset from the frame pointer. | |
8850 | We do this by searching through the insns for the function | |
8851 | looking to see where this register gets its value. If the | |
8852 | register is initialised from the frame pointer plus an offset | |
8853 | then we are in luck and we can continue, otherwise we give up. | |
8854 | ||
8855 | This code is exercised by producing debugging information | |
8856 | for a function with arguments like this: | |
8857 | ||
8858 | double func (double a, double b, int c, double d) {return d;} | |
8859 | ||
8860 | Without this code the stab for parameter 'd' will be set to | |
8861 | an offset of 0 from the frame pointer, rather than 8. */ | |
8862 | ||
8863 | /* The if() statement says: | |
8864 | ||
8865 | If the insn is a normal instruction | |
8866 | and if the insn is setting the value in a register | |
8867 | and if the register being set is the register holding the address of the argument | |
8868 | and if the address is computing by an addition | |
8869 | that involves adding to a register | |
8870 | which is the frame pointer | |
8871 | a constant integer | |
8872 | ||
8873 | then... */ | |
8874 | ||
8875 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
8876 | { | |
8877 | if ( GET_CODE (insn) == INSN | |
8878 | && GET_CODE (PATTERN (insn)) == SET | |
8879 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
8880 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
8881 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 8882 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
8883 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
8884 | ) | |
8885 | { | |
8886 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
8887 | ||
8888 | break; | |
8889 | } | |
8890 | } | |
8891 | ||
8892 | if (value == 0) | |
8893 | { | |
8894 | debug_rtx (addr); | |
8895 | warning ("Unable to compute real location of stacked parameter"); | |
8896 | value = 8; /* XXX magic hack */ | |
8897 | } | |
8898 | ||
8899 | return value; | |
8900 | } | |
8901 | ||
d19fb8e3 | 8902 | #define def_builtin(NAME, TYPE, CODE) \ |
df4ae160 | 8903 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL) |
d19fb8e3 NC |
8904 | |
8905 | void | |
8906 | arm_init_builtins () | |
8907 | { | |
cbd5937a | 8908 | tree endlink = void_list_node; |
d19fb8e3 NC |
8909 | tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); |
8910 | tree pchar_type_node = build_pointer_type (char_type_node); | |
8911 | ||
8912 | tree int_ftype_int, void_ftype_pchar; | |
8913 | ||
8914 | /* void func (void *) */ | |
8915 | void_ftype_pchar | |
8916 | = build_function_type (void_type_node, | |
8917 | tree_cons (NULL_TREE, pchar_type_node, endlink)); | |
8918 | ||
8919 | /* int func (int) */ | |
8920 | int_ftype_int | |
8921 | = build_function_type (integer_type_node, int_endlink); | |
8922 | ||
8923 | /* Initialize arm V5 builtins. */ | |
8924 | if (arm_arch5) | |
eab4abeb | 8925 | def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ); |
b15bca31 RE |
8926 | |
8927 | /* Initialize arm V5E builtins. */ | |
8928 | if (arm_arch5e) | |
eab4abeb NC |
8929 | def_builtin ("__builtin_prefetch", void_ftype_pchar, |
8930 | ARM_BUILTIN_PREFETCH); | |
d19fb8e3 NC |
8931 | } |
8932 | ||
8933 | /* Expand an expression EXP that calls a built-in function, | |
8934 | with result going to TARGET if that's convenient | |
8935 | (and in mode MODE if that's convenient). | |
8936 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
8937 | IGNORE is nonzero if the value is to be ignored. */ | |
8938 | ||
8939 | rtx | |
8940 | arm_expand_builtin (exp, target, subtarget, mode, ignore) | |
8941 | tree exp; | |
8942 | rtx target; | |
8943 | rtx subtarget ATTRIBUTE_UNUSED; | |
8944 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
8945 | int ignore ATTRIBUTE_UNUSED; | |
8946 | { | |
8947 | enum insn_code icode; | |
8948 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
8949 | tree arglist = TREE_OPERAND (exp, 1); | |
8950 | tree arg0; | |
8951 | rtx op0, pat; | |
8952 | enum machine_mode tmode, mode0; | |
8953 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
8954 | ||
8955 | switch (fcode) | |
8956 | { | |
8957 | default: | |
8958 | break; | |
8959 | ||
8960 | case ARM_BUILTIN_CLZ: | |
8961 | icode = CODE_FOR_clz; | |
8962 | arg0 = TREE_VALUE (arglist); | |
8963 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
8964 | tmode = insn_data[icode].operand[0].mode; | |
8965 | mode0 = insn_data[icode].operand[1].mode; | |
8966 | ||
8967 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
8968 | op0 = copy_to_mode_reg (mode0, op0); | |
8969 | if (target == 0 | |
8970 | || GET_MODE (target) != tmode | |
8971 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
8972 | target = gen_reg_rtx (tmode); | |
8973 | pat = GEN_FCN (icode) (target, op0); | |
8974 | if (! pat) | |
8975 | return 0; | |
8976 | emit_insn (pat); | |
8977 | return target; | |
8978 | ||
8979 | case ARM_BUILTIN_PREFETCH: | |
8980 | icode = CODE_FOR_prefetch; | |
8981 | arg0 = TREE_VALUE (arglist); | |
8982 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
8983 | ||
8984 | op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (Pmode, op0)); | |
8985 | ||
8986 | pat = GEN_FCN (icode) (op0); | |
8987 | if (! pat) | |
8988 | return 0; | |
8989 | emit_insn (pat); | |
8990 | return target; | |
8991 | } | |
8992 | ||
8993 | /* @@@ Should really do something sensible here. */ | |
8994 | return NULL_RTX; | |
8995 | } | |
d5b7b3ae RE |
8996 | \f |
8997 | /* Recursively search through all of the blocks in a function | |
8998 | checking to see if any of the variables created in that | |
8999 | function match the RTX called 'orig'. If they do then | |
9000 | replace them with the RTX called 'new'. */ | |
9001 | ||
9002 | static void | |
9003 | replace_symbols_in_block (block, orig, new) | |
9004 | tree block; | |
9005 | rtx orig; | |
9006 | rtx new; | |
9007 | { | |
9008 | for (; block; block = BLOCK_CHAIN (block)) | |
9009 | { | |
9010 | tree sym; | |
9011 | ||
5895f793 | 9012 | if (!TREE_USED (block)) |
d5b7b3ae RE |
9013 | continue; |
9014 | ||
9015 | for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) | |
9016 | { | |
9017 | if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) | |
9018 | || DECL_IGNORED_P (sym) | |
9019 | || TREE_CODE (sym) != VAR_DECL | |
9020 | || DECL_EXTERNAL (sym) | |
5895f793 | 9021 | || !rtx_equal_p (DECL_RTL (sym), orig) |
d5b7b3ae RE |
9022 | ) |
9023 | continue; | |
9024 | ||
7b8b8ade | 9025 | SET_DECL_RTL (sym, new); |
d5b7b3ae RE |
9026 | } |
9027 | ||
9028 | replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); | |
9029 | } | |
9030 | } | |
9031 | ||
9032 | /* Return the number (counting from 0) of the least significant set | |
9033 | bit in MASK. */ | |
9034 | #ifdef __GNUC__ | |
9035 | inline | |
9036 | #endif | |
9037 | static int | |
9038 | number_of_first_bit_set (mask) | |
9039 | int mask; | |
9040 | { | |
9041 | int bit; | |
9042 | ||
9043 | for (bit = 0; | |
9044 | (mask & (1 << bit)) == 0; | |
5895f793 | 9045 | ++bit) |
d5b7b3ae RE |
9046 | continue; |
9047 | ||
9048 | return bit; | |
9049 | } | |
9050 | ||
9051 | /* Generate code to return from a thumb function. | |
9052 | If 'reg_containing_return_addr' is -1, then the return address is | |
9053 | actually on the stack, at the stack pointer. */ | |
9054 | static void | |
9055 | thumb_exit (f, reg_containing_return_addr, eh_ofs) | |
9056 | FILE * f; | |
9057 | int reg_containing_return_addr; | |
9058 | rtx eh_ofs; | |
9059 | { | |
9060 | unsigned regs_available_for_popping; | |
9061 | unsigned regs_to_pop; | |
9062 | int pops_needed; | |
9063 | unsigned available; | |
9064 | unsigned required; | |
9065 | int mode; | |
9066 | int size; | |
9067 | int restore_a4 = FALSE; | |
9068 | ||
9069 | /* Compute the registers we need to pop. */ | |
9070 | regs_to_pop = 0; | |
9071 | pops_needed = 0; | |
9072 | ||
9073 | /* There is an assumption here, that if eh_ofs is not NULL, the | |
9074 | normal return address will have been pushed. */ | |
9075 | if (reg_containing_return_addr == -1 || eh_ofs) | |
9076 | { | |
9077 | /* When we are generating a return for __builtin_eh_return, | |
9078 | reg_containing_return_addr must specify the return regno. */ | |
9079 | if (eh_ofs && reg_containing_return_addr == -1) | |
9080 | abort (); | |
9081 | ||
9082 | regs_to_pop |= 1 << LR_REGNUM; | |
5895f793 | 9083 | ++pops_needed; |
d5b7b3ae RE |
9084 | } |
9085 | ||
9086 | if (TARGET_BACKTRACE) | |
9087 | { | |
9088 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
9089 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
9090 | pops_needed += 2; | |
9091 | } | |
9092 | ||
9093 | /* If there is nothing to pop then just emit the BX instruction and | |
9094 | return. */ | |
9095 | if (pops_needed == 0) | |
9096 | { | |
9097 | if (eh_ofs) | |
9098 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
9099 | ||
9100 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
9101 | return; | |
9102 | } | |
9103 | /* Otherwise if we are not supporting interworking and we have not created | |
9104 | a backtrace structure and the function was not entered in ARM mode then | |
9105 | just pop the return address straight into the PC. */ | |
5895f793 RE |
9106 | else if (!TARGET_INTERWORK |
9107 | && !TARGET_BACKTRACE | |
9108 | && !is_called_in_ARM_mode (current_function_decl)) | |
d5b7b3ae RE |
9109 | { |
9110 | if (eh_ofs) | |
9111 | { | |
9112 | asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); | |
9113 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
9114 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
9115 | } | |
9116 | else | |
9117 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); | |
9118 | ||
9119 | return; | |
9120 | } | |
9121 | ||
9122 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
9123 | regs_available_for_popping = 0; | |
9124 | ||
9125 | /* If returning via __builtin_eh_return, the bottom three registers | |
9126 | all contain information needed for the return. */ | |
9127 | if (eh_ofs) | |
9128 | size = 12; | |
9129 | else | |
9130 | { | |
9131 | #ifdef RTX_CODE | |
9132 | /* If we can deduce the registers used from the function's | |
9133 | return value. This is more reliable that examining | |
9134 | regs_ever_live[] because that will be set if the register is | |
9135 | ever used in the function, not just if the register is used | |
9136 | to hold a return value. */ | |
9137 | ||
9138 | if (current_function_return_rtx != 0) | |
9139 | mode = GET_MODE (current_function_return_rtx); | |
9140 | else | |
9141 | #endif | |
9142 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
9143 | ||
9144 | size = GET_MODE_SIZE (mode); | |
9145 | ||
9146 | if (size == 0) | |
9147 | { | |
9148 | /* In a void function we can use any argument register. | |
9149 | In a function that returns a structure on the stack | |
9150 | we can use the second and third argument registers. */ | |
9151 | if (mode == VOIDmode) | |
9152 | regs_available_for_popping = | |
9153 | (1 << ARG_REGISTER (1)) | |
9154 | | (1 << ARG_REGISTER (2)) | |
9155 | | (1 << ARG_REGISTER (3)); | |
9156 | else | |
9157 | regs_available_for_popping = | |
9158 | (1 << ARG_REGISTER (2)) | |
9159 | | (1 << ARG_REGISTER (3)); | |
9160 | } | |
9161 | else if (size <= 4) | |
9162 | regs_available_for_popping = | |
9163 | (1 << ARG_REGISTER (2)) | |
9164 | | (1 << ARG_REGISTER (3)); | |
9165 | else if (size <= 8) | |
9166 | regs_available_for_popping = | |
9167 | (1 << ARG_REGISTER (3)); | |
9168 | } | |
9169 | ||
9170 | /* Match registers to be popped with registers into which we pop them. */ | |
9171 | for (available = regs_available_for_popping, | |
9172 | required = regs_to_pop; | |
9173 | required != 0 && available != 0; | |
9174 | available &= ~(available & - available), | |
9175 | required &= ~(required & - required)) | |
9176 | -- pops_needed; | |
9177 | ||
9178 | /* If we have any popping registers left over, remove them. */ | |
9179 | if (available > 0) | |
5895f793 | 9180 | regs_available_for_popping &= ~available; |
d5b7b3ae RE |
9181 | |
9182 | /* Otherwise if we need another popping register we can use | |
9183 | the fourth argument register. */ | |
9184 | else if (pops_needed) | |
9185 | { | |
9186 | /* If we have not found any free argument registers and | |
9187 | reg a4 contains the return address, we must move it. */ | |
9188 | if (regs_available_for_popping == 0 | |
9189 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
9190 | { | |
9191 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
9192 | reg_containing_return_addr = LR_REGNUM; | |
9193 | } | |
9194 | else if (size > 12) | |
9195 | { | |
9196 | /* Register a4 is being used to hold part of the return value, | |
9197 | but we have dire need of a free, low register. */ | |
9198 | restore_a4 = TRUE; | |
9199 | ||
9200 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); | |
9201 | } | |
9202 | ||
9203 | if (reg_containing_return_addr != LAST_ARG_REGNUM) | |
9204 | { | |
9205 | /* The fourth argument register is available. */ | |
9206 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
9207 | ||
5895f793 | 9208 | --pops_needed; |
d5b7b3ae RE |
9209 | } |
9210 | } | |
9211 | ||
9212 | /* Pop as many registers as we can. */ | |
9213 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
9214 | ||
9215 | /* Process the registers we popped. */ | |
9216 | if (reg_containing_return_addr == -1) | |
9217 | { | |
9218 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 9219 | regs_to_pop &= ~(1 << LR_REGNUM); |
d5b7b3ae RE |
9220 | |
9221 | reg_containing_return_addr = | |
9222 | number_of_first_bit_set (regs_available_for_popping); | |
9223 | ||
9224 | /* Remove this register for the mask of available registers, so that | |
9225 | the return address will not be corrupted by futher pops. */ | |
5895f793 | 9226 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
9227 | } |
9228 | ||
9229 | /* If we popped other registers then handle them here. */ | |
9230 | if (regs_available_for_popping) | |
9231 | { | |
9232 | int frame_pointer; | |
9233 | ||
9234 | /* Work out which register currently contains the frame pointer. */ | |
9235 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
9236 | ||
9237 | /* Move it into the correct place. */ | |
9238 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
9239 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
9240 | ||
9241 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
9242 | regs_available_for_popping &= ~(1 << frame_pointer); |
9243 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
d5b7b3ae RE |
9244 | |
9245 | if (regs_available_for_popping) | |
9246 | { | |
9247 | int stack_pointer; | |
9248 | ||
9249 | /* We popped the stack pointer as well, | |
9250 | find the register that contains it. */ | |
9251 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
9252 | ||
9253 | /* Move it into the stack register. */ | |
9254 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
9255 | ||
9256 | /* At this point we have popped all necessary registers, so | |
9257 | do not worry about restoring regs_available_for_popping | |
9258 | to its correct value: | |
9259 | ||
9260 | assert (pops_needed == 0) | |
9261 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
9262 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
9263 | } | |
9264 | else | |
9265 | { | |
9266 | /* Since we have just move the popped value into the frame | |
9267 | pointer, the popping register is available for reuse, and | |
9268 | we know that we still have the stack pointer left to pop. */ | |
9269 | regs_available_for_popping |= (1 << frame_pointer); | |
9270 | } | |
9271 | } | |
9272 | ||
9273 | /* If we still have registers left on the stack, but we no longer have | |
9274 | any registers into which we can pop them, then we must move the return | |
9275 | address into the link register and make available the register that | |
9276 | contained it. */ | |
9277 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
9278 | { | |
9279 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
9280 | ||
9281 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, | |
9282 | reg_containing_return_addr); | |
9283 | ||
9284 | reg_containing_return_addr = LR_REGNUM; | |
9285 | } | |
9286 | ||
9287 | /* If we have registers left on the stack then pop some more. | |
9288 | We know that at most we will want to pop FP and SP. */ | |
9289 | if (pops_needed > 0) | |
9290 | { | |
9291 | int popped_into; | |
9292 | int move_to; | |
9293 | ||
9294 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
9295 | ||
9296 | /* We have popped either FP or SP. | |
9297 | Move whichever one it is into the correct register. */ | |
9298 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
9299 | move_to = number_of_first_bit_set (regs_to_pop); | |
9300 | ||
9301 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
9302 | ||
5895f793 | 9303 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 9304 | |
5895f793 | 9305 | --pops_needed; |
d5b7b3ae RE |
9306 | } |
9307 | ||
9308 | /* If we still have not popped everything then we must have only | |
9309 | had one register available to us and we are now popping the SP. */ | |
9310 | if (pops_needed > 0) | |
9311 | { | |
9312 | int popped_into; | |
9313 | ||
9314 | thumb_pushpop (f, regs_available_for_popping, FALSE); | |
9315 | ||
9316 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
9317 | ||
9318 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
9319 | /* | |
9320 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
9321 | assert (pops_needed == 1) | |
9322 | */ | |
9323 | } | |
9324 | ||
9325 | /* If necessary restore the a4 register. */ | |
9326 | if (restore_a4) | |
9327 | { | |
9328 | if (reg_containing_return_addr != LR_REGNUM) | |
9329 | { | |
9330 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
9331 | reg_containing_return_addr = LR_REGNUM; | |
9332 | } | |
9333 | ||
9334 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); | |
9335 | } | |
9336 | ||
9337 | if (eh_ofs) | |
9338 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
9339 | ||
9340 | /* Return to caller. */ | |
9341 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
9342 | } | |
9343 | ||
9344 | /* Emit code to push or pop registers to or from the stack. */ | |
9345 | static void | |
9346 | thumb_pushpop (f, mask, push) | |
9347 | FILE * f; | |
9348 | int mask; | |
9349 | int push; | |
9350 | { | |
9351 | int regno; | |
9352 | int lo_mask = mask & 0xFF; | |
9353 | ||
5895f793 | 9354 | if (lo_mask == 0 && !push && (mask & (1 << 15))) |
d5b7b3ae RE |
9355 | { |
9356 | /* Special case. Do not generate a POP PC statement here, do it in | |
9357 | thumb_exit() */ | |
9358 | thumb_exit (f, -1, NULL_RTX); | |
9359 | return; | |
9360 | } | |
9361 | ||
9362 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); | |
9363 | ||
9364 | /* Look at the low registers first. */ | |
5895f793 | 9365 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) |
d5b7b3ae RE |
9366 | { |
9367 | if (lo_mask & 1) | |
9368 | { | |
9369 | asm_fprintf (f, "%r", regno); | |
9370 | ||
9371 | if ((lo_mask & ~1) != 0) | |
9372 | fprintf (f, ", "); | |
9373 | } | |
9374 | } | |
9375 | ||
9376 | if (push && (mask & (1 << LR_REGNUM))) | |
9377 | { | |
9378 | /* Catch pushing the LR. */ | |
9379 | if (mask & 0xFF) | |
9380 | fprintf (f, ", "); | |
9381 | ||
9382 | asm_fprintf (f, "%r", LR_REGNUM); | |
9383 | } | |
9384 | else if (!push && (mask & (1 << PC_REGNUM))) | |
9385 | { | |
9386 | /* Catch popping the PC. */ | |
9387 | if (TARGET_INTERWORK || TARGET_BACKTRACE) | |
9388 | { | |
9389 | /* The PC is never poped directly, instead | |
9390 | it is popped into r3 and then BX is used. */ | |
9391 | fprintf (f, "}\n"); | |
9392 | ||
9393 | thumb_exit (f, -1, NULL_RTX); | |
9394 | ||
9395 | return; | |
9396 | } | |
9397 | else | |
9398 | { | |
9399 | if (mask & 0xFF) | |
9400 | fprintf (f, ", "); | |
9401 | ||
9402 | asm_fprintf (f, "%r", PC_REGNUM); | |
9403 | } | |
9404 | } | |
9405 | ||
9406 | fprintf (f, "}\n"); | |
9407 | } | |
9408 | \f | |
9409 | void | |
9410 | thumb_final_prescan_insn (insn) | |
9411 | rtx insn; | |
9412 | { | |
d5b7b3ae | 9413 | if (flag_print_asm_name) |
9d98a694 AO |
9414 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
9415 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
9416 | } |
9417 | ||
9418 | int | |
9419 | thumb_shiftable_const (val) | |
9420 | unsigned HOST_WIDE_INT val; | |
9421 | { | |
9422 | unsigned HOST_WIDE_INT mask = 0xff; | |
9423 | int i; | |
9424 | ||
9425 | if (val == 0) /* XXX */ | |
9426 | return 0; | |
9427 | ||
9428 | for (i = 0; i < 25; i++) | |
9429 | if ((val & (mask << i)) == val) | |
9430 | return 1; | |
9431 | ||
9432 | return 0; | |
9433 | } | |
9434 | ||
9435 | /* Returns non-zero if the current function contains, | |
9436 | or might contain a far jump. */ | |
9437 | int | |
9438 | thumb_far_jump_used_p (int in_prologue) | |
9439 | { | |
9440 | rtx insn; | |
9441 | ||
9442 | /* This test is only important for leaf functions. */ | |
5895f793 | 9443 | /* assert (!leaf_function_p ()); */ |
d5b7b3ae RE |
9444 | |
9445 | /* If we have already decided that far jumps may be used, | |
9446 | do not bother checking again, and always return true even if | |
9447 | it turns out that they are not being used. Once we have made | |
9448 | the decision that far jumps are present (and that hence the link | |
9449 | register will be pushed onto the stack) we cannot go back on it. */ | |
9450 | if (cfun->machine->far_jump_used) | |
9451 | return 1; | |
9452 | ||
9453 | /* If this function is not being called from the prologue/epilogue | |
9454 | generation code then it must be being called from the | |
9455 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5895f793 | 9456 | if (!in_prologue) |
d5b7b3ae RE |
9457 | { |
9458 | /* In this case we know that we are being asked about the elimination | |
9459 | of the arg pointer register. If that register is not being used, | |
9460 | then there are no arguments on the stack, and we do not have to | |
9461 | worry that a far jump might force the prologue to push the link | |
9462 | register, changing the stack offsets. In this case we can just | |
9463 | return false, since the presence of far jumps in the function will | |
9464 | not affect stack offsets. | |
9465 | ||
9466 | If the arg pointer is live (or if it was live, but has now been | |
9467 | eliminated and so set to dead) then we do have to test to see if | |
9468 | the function might contain a far jump. This test can lead to some | |
9469 | false negatives, since before reload is completed, then length of | |
9470 | branch instructions is not known, so gcc defaults to returning their | |
9471 | longest length, which in turn sets the far jump attribute to true. | |
9472 | ||
9473 | A false negative will not result in bad code being generated, but it | |
9474 | will result in a needless push and pop of the link register. We | |
9475 | hope that this does not occur too often. */ | |
9476 | if (regs_ever_live [ARG_POINTER_REGNUM]) | |
9477 | cfun->machine->arg_pointer_live = 1; | |
5895f793 | 9478 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
9479 | return 0; |
9480 | } | |
9481 | ||
9482 | /* Check to see if the function contains a branch | |
9483 | insn with the far jump attribute set. */ | |
9484 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
9485 | { | |
9486 | if (GET_CODE (insn) == JUMP_INSN | |
9487 | /* Ignore tablejump patterns. */ | |
9488 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
9489 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
9490 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
9491 | ) | |
9492 | { | |
9493 | /* Record the fact that we have decied that | |
9494 | the function does use far jumps. */ | |
9495 | cfun->machine->far_jump_used = 1; | |
9496 | return 1; | |
9497 | } | |
9498 | } | |
9499 | ||
9500 | return 0; | |
9501 | } | |
9502 | ||
9503 | /* Return non-zero if FUNC must be entered in ARM mode. */ | |
9504 | int | |
9505 | is_called_in_ARM_mode (func) | |
9506 | tree func; | |
9507 | { | |
9508 | if (TREE_CODE (func) != FUNCTION_DECL) | |
9509 | abort (); | |
9510 | ||
9511 | /* Ignore the problem about functions whoes address is taken. */ | |
9512 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) | |
9513 | return TRUE; | |
9514 | ||
9515 | #ifdef ARM_PE | |
9516 | return lookup_attribute ("interfacearm", DECL_MACHINE_ATTRIBUTES (func)) != NULL_TREE; | |
9517 | #else | |
9518 | return FALSE; | |
9519 | #endif | |
9520 | } | |
9521 | ||
9522 | /* The bits which aren't usefully expanded as rtl. */ | |
400500c4 | 9523 | |
cd2b33d0 | 9524 | const char * |
d5b7b3ae RE |
9525 | thumb_unexpanded_epilogue () |
9526 | { | |
9527 | int regno; | |
9528 | int live_regs_mask = 0; | |
9529 | int high_regs_pushed = 0; | |
9530 | int leaf_function = leaf_function_p (); | |
9531 | int had_to_push_lr; | |
9532 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; | |
9533 | ||
9534 | if (return_used_this_function) | |
9535 | return ""; | |
9536 | ||
9537 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
5895f793 RE |
9538 | if (regs_ever_live[regno] && !call_used_regs[regno] |
9539 | && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) | |
d5b7b3ae RE |
9540 | live_regs_mask |= 1 << regno; |
9541 | ||
9542 | for (regno = 8; regno < 13; regno++) | |
9543 | { | |
5895f793 RE |
9544 | if (regs_ever_live[regno] && !call_used_regs[regno] |
9545 | && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) | |
9546 | high_regs_pushed++; | |
d5b7b3ae RE |
9547 | } |
9548 | ||
9549 | /* The prolog may have pushed some high registers to use as | |
9550 | work registers. eg the testuite file: | |
9551 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c | |
9552 | compiles to produce: | |
9553 | push {r4, r5, r6, r7, lr} | |
9554 | mov r7, r9 | |
9555 | mov r6, r8 | |
9556 | push {r6, r7} | |
9557 | as part of the prolog. We have to undo that pushing here. */ | |
9558 | ||
9559 | if (high_regs_pushed) | |
9560 | { | |
9561 | int mask = live_regs_mask; | |
9562 | int next_hi_reg; | |
9563 | int size; | |
9564 | int mode; | |
9565 | ||
9566 | #ifdef RTX_CODE | |
9567 | /* If we can deduce the registers used from the function's return value. | |
9568 | This is more reliable that examining regs_ever_live[] because that | |
9569 | will be set if the register is ever used in the function, not just if | |
9570 | the register is used to hold a return value. */ | |
9571 | ||
9572 | if (current_function_return_rtx != 0) | |
9573 | mode = GET_MODE (current_function_return_rtx); | |
9574 | else | |
9575 | #endif | |
9576 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
9577 | ||
9578 | size = GET_MODE_SIZE (mode); | |
9579 | ||
9580 | /* Unless we are returning a type of size > 12 register r3 is | |
9581 | available. */ | |
9582 | if (size < 13) | |
9583 | mask |= 1 << 3; | |
9584 | ||
9585 | if (mask == 0) | |
9586 | /* Oh dear! We have no low registers into which we can pop | |
9587 | high registers! */ | |
400500c4 RK |
9588 | internal_error |
9589 | ("no low registers available for popping high registers"); | |
d5b7b3ae RE |
9590 | |
9591 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) | |
5895f793 RE |
9592 | if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg] |
9593 | && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register))) | |
d5b7b3ae RE |
9594 | break; |
9595 | ||
9596 | while (high_regs_pushed) | |
9597 | { | |
9598 | /* Find lo register(s) into which the high register(s) can | |
9599 | be popped. */ | |
9600 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
9601 | { | |
9602 | if (mask & (1 << regno)) | |
9603 | high_regs_pushed--; | |
9604 | if (high_regs_pushed == 0) | |
9605 | break; | |
9606 | } | |
9607 | ||
9608 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
9609 | ||
9610 | /* Pop the values into the low register(s). */ | |
9611 | thumb_pushpop (asm_out_file, mask, 0); | |
9612 | ||
9613 | /* Move the value(s) into the high registers. */ | |
9614 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
9615 | { | |
9616 | if (mask & (1 << regno)) | |
9617 | { | |
9618 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
9619 | regno); | |
9620 | ||
9621 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) | |
5895f793 RE |
9622 | if (regs_ever_live[next_hi_reg] |
9623 | && !call_used_regs[next_hi_reg] | |
9624 | && !(TARGET_SINGLE_PIC_BASE | |
9625 | && (next_hi_reg == arm_pic_register))) | |
d5b7b3ae RE |
9626 | break; |
9627 | } | |
9628 | } | |
9629 | } | |
9630 | } | |
9631 | ||
5895f793 | 9632 | had_to_push_lr = (live_regs_mask || !leaf_function |
d5b7b3ae RE |
9633 | || thumb_far_jump_used_p (1)); |
9634 | ||
9635 | if (TARGET_BACKTRACE | |
9636 | && ((live_regs_mask & 0xFF) == 0) | |
9637 | && regs_ever_live [LAST_ARG_REGNUM] != 0) | |
9638 | { | |
9639 | /* The stack backtrace structure creation code had to | |
9640 | push R7 in order to get a work register, so we pop | |
9641 | it now. */ | |
9642 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
9643 | } | |
9644 | ||
9645 | if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) | |
9646 | { | |
9647 | if (had_to_push_lr | |
5895f793 RE |
9648 | && !is_called_in_ARM_mode (current_function_decl) |
9649 | && !eh_ofs) | |
d5b7b3ae RE |
9650 | live_regs_mask |= 1 << PC_REGNUM; |
9651 | ||
9652 | /* Either no argument registers were pushed or a backtrace | |
9653 | structure was created which includes an adjusted stack | |
9654 | pointer, so just pop everything. */ | |
9655 | if (live_regs_mask) | |
9656 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
9657 | ||
9658 | if (eh_ofs) | |
9659 | thumb_exit (asm_out_file, 2, eh_ofs); | |
9660 | /* We have either just popped the return address into the | |
9661 | PC or it is was kept in LR for the entire function or | |
9662 | it is still on the stack because we do not want to | |
9663 | return by doing a pop {pc}. */ | |
9664 | else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) | |
9665 | thumb_exit (asm_out_file, | |
9666 | (had_to_push_lr | |
9667 | && is_called_in_ARM_mode (current_function_decl)) ? | |
9668 | -1 : LR_REGNUM, NULL_RTX); | |
9669 | } | |
9670 | else | |
9671 | { | |
9672 | /* Pop everything but the return address. */ | |
5895f793 | 9673 | live_regs_mask &= ~(1 << PC_REGNUM); |
d5b7b3ae RE |
9674 | |
9675 | if (live_regs_mask) | |
9676 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE); | |
9677 | ||
9678 | if (had_to_push_lr) | |
9679 | /* Get the return address into a temporary register. */ | |
9680 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0); | |
9681 | ||
9682 | /* Remove the argument registers that were pushed onto the stack. */ | |
9683 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
9684 | SP_REGNUM, SP_REGNUM, | |
9685 | current_function_pretend_args_size); | |
9686 | ||
9687 | if (eh_ofs) | |
9688 | thumb_exit (asm_out_file, 2, eh_ofs); | |
9689 | else | |
9690 | thumb_exit (asm_out_file, | |
9691 | had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); | |
9692 | } | |
9693 | ||
9694 | return ""; | |
9695 | } | |
9696 | ||
9697 | /* Functions to save and restore machine-specific function data. */ | |
9698 | ||
9699 | static void | |
9700 | arm_mark_machine_status (p) | |
9701 | struct function * p; | |
9702 | { | |
6d3d9133 | 9703 | machine_function *machine = p->machine; |
d5b7b3ae | 9704 | |
f7a80099 | 9705 | if (machine) |
9e2f7ec7 | 9706 | ggc_mark_rtx (machine->eh_epilogue_sp_ofs); |
d5b7b3ae RE |
9707 | } |
9708 | ||
9709 | static void | |
9710 | arm_init_machine_status (p) | |
9711 | struct function * p; | |
9712 | { | |
9713 | p->machine = | |
6d3d9133 NC |
9714 | (machine_function *) xcalloc (1, sizeof (machine_function)); |
9715 | ||
9716 | #if ARM_FT_UNKNOWWN != 0 | |
9717 | ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN; | |
9718 | #endif | |
d5b7b3ae RE |
9719 | } |
9720 | ||
f7a80099 NC |
9721 | static void |
9722 | arm_free_machine_status (p) | |
9723 | struct function * p; | |
9724 | { | |
9725 | if (p->machine) | |
9726 | { | |
9727 | free (p->machine); | |
9728 | p->machine = NULL; | |
9729 | } | |
9730 | } | |
9731 | ||
d5b7b3ae RE |
9732 | /* Return an RTX indicating where the return address to the |
9733 | calling function can be found. */ | |
9734 | rtx | |
9735 | arm_return_addr (count, frame) | |
9736 | int count; | |
9737 | rtx frame ATTRIBUTE_UNUSED; | |
9738 | { | |
d5b7b3ae RE |
9739 | if (count != 0) |
9740 | return NULL_RTX; | |
9741 | ||
9e2f7ec7 DD |
9742 | if (TARGET_APCS_32) |
9743 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); | |
9744 | else | |
d5b7b3ae | 9745 | { |
9e2f7ec7 | 9746 | rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), |
d5b7b3ae | 9747 | GEN_INT (RETURN_ADDR_MASK26)); |
9e2f7ec7 | 9748 | return get_func_hard_reg_initial_val (cfun, lr); |
d5b7b3ae | 9749 | } |
d5b7b3ae RE |
9750 | } |
9751 | ||
9752 | /* Do anything needed before RTL is emitted for each function. */ | |
9753 | void | |
9754 | arm_init_expanders () | |
9755 | { | |
9756 | /* Arrange to initialize and mark the machine per-function status. */ | |
9757 | init_machine_status = arm_init_machine_status; | |
9758 | mark_machine_status = arm_mark_machine_status; | |
f7a80099 | 9759 | free_machine_status = arm_free_machine_status; |
d5b7b3ae RE |
9760 | } |
9761 | ||
9762 | /* Generate the rest of a function's prologue. */ | |
9763 | void | |
9764 | thumb_expand_prologue () | |
9765 | { | |
9766 | HOST_WIDE_INT amount = (get_frame_size () | |
9767 | + current_function_outgoing_args_size); | |
6d3d9133 NC |
9768 | unsigned long func_type; |
9769 | ||
9770 | func_type = arm_current_func_type (); | |
d5b7b3ae RE |
9771 | |
9772 | /* Naked functions don't have prologues. */ | |
6d3d9133 | 9773 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
9774 | return; |
9775 | ||
6d3d9133 NC |
9776 | if (IS_INTERRUPT (func_type)) |
9777 | { | |
9778 | error ("Interrupt Service Routines cannot be coded in Thumb mode."); | |
9779 | return; | |
9780 | } | |
9781 | ||
d5b7b3ae RE |
9782 | if (frame_pointer_needed) |
9783 | emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); | |
9784 | ||
9785 | if (amount) | |
9786 | { | |
9787 | amount = ROUND_UP (amount); | |
9788 | ||
9789 | if (amount < 512) | |
9790 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
5895f793 | 9791 | GEN_INT (-amount))); |
d5b7b3ae RE |
9792 | else |
9793 | { | |
9794 | int regno; | |
9795 | rtx reg; | |
9796 | ||
9797 | /* The stack decrement is too big for an immediate value in a single | |
9798 | insn. In theory we could issue multiple subtracts, but after | |
9799 | three of them it becomes more space efficient to place the full | |
9800 | value in the constant pool and load into a register. (Also the | |
9801 | ARM debugger really likes to see only one stack decrement per | |
9802 | function). So instead we look for a scratch register into which | |
9803 | we can load the decrement, and then we subtract this from the | |
9804 | stack pointer. Unfortunately on the thumb the only available | |
9805 | scratch registers are the argument registers, and we cannot use | |
9806 | these as they may hold arguments to the function. Instead we | |
9807 | attempt to locate a call preserved register which is used by this | |
9808 | function. If we can find one, then we know that it will have | |
9809 | been pushed at the start of the prologue and so we can corrupt | |
9810 | it now. */ | |
9811 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
9812 | if (regs_ever_live[regno] | |
5895f793 RE |
9813 | && !call_used_regs[regno] /* Paranoia */ |
9814 | && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)) | |
9815 | && !(frame_pointer_needed | |
9816 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
9817 | break; |
9818 | ||
9819 | if (regno > LAST_LO_REGNUM) /* Very unlikely */ | |
9820 | { | |
9821 | rtx spare = gen_rtx (REG, SImode, IP_REGNUM); | |
9822 | ||
9823 | /* Choose an arbitary, non-argument low register. */ | |
9824 | reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); | |
9825 | ||
9826 | /* Save it by copying it into a high, scratch register. */ | |
9827 | emit_insn (gen_movsi (spare, reg)); | |
9828 | ||
9829 | /* Decrement the stack. */ | |
5895f793 | 9830 | emit_insn (gen_movsi (reg, GEN_INT (-amount))); |
d5b7b3ae RE |
9831 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
9832 | reg)); | |
9833 | ||
9834 | /* Restore the low register's original value. */ | |
9835 | emit_insn (gen_movsi (reg, spare)); | |
9836 | ||
9837 | /* Emit a USE of the restored scratch register, so that flow | |
9838 | analysis will not consider the restore redundant. The | |
9839 | register won't be used again in this function and isn't | |
9840 | restored by the epilogue. */ | |
9841 | emit_insn (gen_rtx_USE (VOIDmode, reg)); | |
9842 | } | |
9843 | else | |
9844 | { | |
9845 | reg = gen_rtx (REG, SImode, regno); | |
9846 | ||
5895f793 | 9847 | emit_insn (gen_movsi (reg, GEN_INT (-amount))); |
d5b7b3ae RE |
9848 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
9849 | reg)); | |
9850 | } | |
9851 | } | |
9852 | } | |
9853 | ||
9854 | if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO) | |
9855 | emit_insn (gen_blockage ()); | |
9856 | } | |
9857 | ||
9858 | void | |
9859 | thumb_expand_epilogue () | |
9860 | { | |
9861 | HOST_WIDE_INT amount = (get_frame_size () | |
9862 | + current_function_outgoing_args_size); | |
6d3d9133 NC |
9863 | |
9864 | /* Naked functions don't have prologues. */ | |
9865 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
9866 | return; |
9867 | ||
9868 | if (frame_pointer_needed) | |
9869 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
9870 | else if (amount) | |
9871 | { | |
9872 | amount = ROUND_UP (amount); | |
9873 | ||
9874 | if (amount < 512) | |
9875 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
9876 | GEN_INT (amount))); | |
9877 | else | |
9878 | { | |
9879 | /* r3 is always free in the epilogue. */ | |
9880 | rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM); | |
9881 | ||
9882 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
9883 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
9884 | } | |
9885 | } | |
9886 | ||
9887 | /* Emit a USE (stack_pointer_rtx), so that | |
9888 | the stack adjustment will not be deleted. */ | |
9889 | emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); | |
9890 | ||
9891 | if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO) | |
9892 | emit_insn (gen_blockage ()); | |
9893 | } | |
9894 | ||
9895 | void | |
9896 | output_thumb_prologue (f) | |
9897 | FILE * f; | |
9898 | { | |
9899 | int live_regs_mask = 0; | |
9900 | int high_regs_pushed = 0; | |
d5b7b3ae RE |
9901 | int regno; |
9902 | ||
6d3d9133 | 9903 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
9904 | return; |
9905 | ||
9906 | if (is_called_in_ARM_mode (current_function_decl)) | |
9907 | { | |
9908 | const char * name; | |
9909 | ||
9910 | if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) | |
9911 | abort (); | |
9912 | if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) | |
9913 | abort (); | |
9914 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
9915 | ||
9916 | /* Generate code sequence to switch us into Thumb mode. */ | |
9917 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 9918 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
9919 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
9920 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
9921 | ||
9922 | /* Generate a label, so that the debugger will notice the | |
9923 | change in instruction sets. This label is also used by | |
9924 | the assembler to bypass the ARM code when this function | |
9925 | is called from a Thumb encoded function elsewhere in the | |
9926 | same file. Hence the definition of STUB_NAME here must | |
9927 | agree with the definition in gas/config/tc-arm.c */ | |
9928 | ||
9929 | #define STUB_NAME ".real_start_of" | |
9930 | ||
9931 | asm_fprintf (f, "\t.code\t16\n"); | |
9932 | #ifdef ARM_PE | |
9933 | if (arm_dllexport_name_p (name)) | |
e5951263 | 9934 | name = arm_strip_name_encoding (name); |
d5b7b3ae RE |
9935 | #endif |
9936 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); | |
9937 | asm_fprintf (f, "\t.thumb_func\n"); | |
9938 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); | |
9939 | } | |
9940 | ||
d5b7b3ae RE |
9941 | if (current_function_pretend_args_size) |
9942 | { | |
6d3d9133 | 9943 | if (current_function_anonymous_args) |
d5b7b3ae RE |
9944 | { |
9945 | int num_pushes; | |
9946 | ||
9947 | asm_fprintf (f, "\tpush\t{"); | |
9948 | ||
9949 | num_pushes = NUM_INTS (current_function_pretend_args_size); | |
9950 | ||
9951 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; | |
9952 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 9953 | regno++) |
d5b7b3ae RE |
9954 | asm_fprintf (f, "%r%s", regno, |
9955 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
9956 | ||
9957 | asm_fprintf (f, "}\n"); | |
9958 | } | |
9959 | else | |
9960 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", | |
9961 | SP_REGNUM, SP_REGNUM, | |
9962 | current_function_pretend_args_size); | |
9963 | } | |
9964 | ||
5895f793 RE |
9965 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
9966 | if (regs_ever_live[regno] && !call_used_regs[regno] | |
9967 | && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) | |
d5b7b3ae RE |
9968 | live_regs_mask |= 1 << regno; |
9969 | ||
5895f793 | 9970 | if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1)) |
d5b7b3ae RE |
9971 | live_regs_mask |= 1 << LR_REGNUM; |
9972 | ||
9973 | if (TARGET_BACKTRACE) | |
9974 | { | |
9975 | int offset; | |
9976 | int work_register = 0; | |
9977 | int wr; | |
9978 | ||
9979 | /* We have been asked to create a stack backtrace structure. | |
9980 | The code looks like this: | |
9981 | ||
9982 | 0 .align 2 | |
9983 | 0 func: | |
9984 | 0 sub SP, #16 Reserve space for 4 registers. | |
9985 | 2 push {R7} Get a work register. | |
9986 | 4 add R7, SP, #20 Get the stack pointer before the push. | |
9987 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
9988 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
9989 | 10 str R7, [SP, #16] Store it. | |
9990 | 12 mov R7, FP Get hold of the current frame pointer. | |
9991 | 14 str R7, [SP, #4] Store it. | |
9992 | 16 mov R7, LR Get hold of the current return address. | |
9993 | 18 str R7, [SP, #12] Store it. | |
9994 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
9995 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
9996 | ||
9997 | if ((live_regs_mask & 0xFF) == 0) | |
9998 | { | |
9999 | /* See if the a4 register is free. */ | |
10000 | ||
10001 | if (regs_ever_live [LAST_ARG_REGNUM] == 0) | |
10002 | work_register = LAST_ARG_REGNUM; | |
10003 | else /* We must push a register of our own */ | |
10004 | live_regs_mask |= (1 << LAST_LO_REGNUM); | |
10005 | } | |
10006 | ||
10007 | if (work_register == 0) | |
10008 | { | |
10009 | /* Select a register from the list that will be pushed to | |
10010 | use as our work register. */ | |
10011 | for (work_register = (LAST_LO_REGNUM + 1); work_register--;) | |
10012 | if ((1 << work_register) & live_regs_mask) | |
10013 | break; | |
10014 | } | |
10015 | ||
10016 | asm_fprintf | |
10017 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
10018 | SP_REGNUM, SP_REGNUM); | |
10019 | ||
10020 | if (live_regs_mask) | |
10021 | thumb_pushpop (f, live_regs_mask, 1); | |
10022 | ||
10023 | for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) | |
10024 | if (wr & live_regs_mask) | |
10025 | offset += 4; | |
10026 | ||
10027 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
10028 | offset + 16 + current_function_pretend_args_size); | |
10029 | ||
10030 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10031 | offset + 4); | |
10032 | ||
10033 | /* Make sure that the instruction fetching the PC is in the right place | |
10034 | to calculate "start of backtrace creation code + 12". */ | |
10035 | if (live_regs_mask) | |
10036 | { | |
10037 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
10038 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10039 | offset + 12); | |
10040 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
10041 | ARM_HARD_FRAME_POINTER_REGNUM); | |
10042 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10043 | offset); | |
10044 | } | |
10045 | else | |
10046 | { | |
10047 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
10048 | ARM_HARD_FRAME_POINTER_REGNUM); | |
10049 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10050 | offset); | |
10051 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
10052 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10053 | offset + 12); | |
10054 | } | |
10055 | ||
10056 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); | |
10057 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
10058 | offset + 8); | |
10059 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
10060 | offset + 12); | |
10061 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
10062 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
10063 | } | |
10064 | else if (live_regs_mask) | |
10065 | thumb_pushpop (f, live_regs_mask, 1); | |
10066 | ||
10067 | for (regno = 8; regno < 13; regno++) | |
10068 | { | |
5895f793 RE |
10069 | if (regs_ever_live[regno] && !call_used_regs[regno] |
10070 | && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) | |
10071 | high_regs_pushed++; | |
d5b7b3ae RE |
10072 | } |
10073 | ||
10074 | if (high_regs_pushed) | |
10075 | { | |
10076 | int pushable_regs = 0; | |
10077 | int mask = live_regs_mask & 0xff; | |
10078 | int next_hi_reg; | |
10079 | ||
10080 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
10081 | { | |
5895f793 RE |
10082 | if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg] |
10083 | && !(TARGET_SINGLE_PIC_BASE | |
10084 | && (next_hi_reg == arm_pic_register))) | |
d5b7b3ae RE |
10085 | break; |
10086 | } | |
10087 | ||
10088 | pushable_regs = mask; | |
10089 | ||
10090 | if (pushable_regs == 0) | |
10091 | { | |
10092 | /* Desperation time -- this probably will never happen. */ | |
10093 | if (regs_ever_live[LAST_ARG_REGNUM] | |
5895f793 | 10094 | || !call_used_regs[LAST_ARG_REGNUM]) |
d5b7b3ae RE |
10095 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); |
10096 | mask = 1 << LAST_ARG_REGNUM; | |
10097 | } | |
10098 | ||
10099 | while (high_regs_pushed > 0) | |
10100 | { | |
10101 | for (regno = LAST_LO_REGNUM; regno >= 0; regno--) | |
10102 | { | |
10103 | if (mask & (1 << regno)) | |
10104 | { | |
10105 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
10106 | ||
5895f793 | 10107 | high_regs_pushed--; |
d5b7b3ae RE |
10108 | |
10109 | if (high_regs_pushed) | |
10110 | for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; | |
10111 | next_hi_reg--) | |
10112 | { | |
10113 | if (regs_ever_live[next_hi_reg] | |
5895f793 RE |
10114 | && !call_used_regs[next_hi_reg] |
10115 | && !(TARGET_SINGLE_PIC_BASE | |
10116 | && (next_hi_reg == arm_pic_register))) | |
d5b7b3ae RE |
10117 | break; |
10118 | } | |
10119 | else | |
10120 | { | |
5895f793 | 10121 | mask &= ~((1 << regno) - 1); |
d5b7b3ae RE |
10122 | break; |
10123 | } | |
10124 | } | |
10125 | } | |
10126 | ||
10127 | thumb_pushpop (f, mask, 1); | |
10128 | } | |
10129 | ||
10130 | if (pushable_regs == 0 | |
10131 | && (regs_ever_live[LAST_ARG_REGNUM] | |
5895f793 | 10132 | || !call_used_regs[LAST_ARG_REGNUM])) |
d5b7b3ae RE |
10133 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
10134 | } | |
10135 | } | |
10136 | ||
10137 | /* Handle the case of a double word load into a low register from | |
10138 | a computed memory address. The computed address may involve a | |
10139 | register which is overwritten by the load. */ | |
10140 | ||
cd2b33d0 | 10141 | const char * |
d5b7b3ae | 10142 | thumb_load_double_from_address (operands) |
400500c4 | 10143 | rtx *operands; |
d5b7b3ae RE |
10144 | { |
10145 | rtx addr; | |
10146 | rtx base; | |
10147 | rtx offset; | |
10148 | rtx arg1; | |
10149 | rtx arg2; | |
10150 | ||
10151 | if (GET_CODE (operands[0]) != REG) | |
400500c4 | 10152 | abort (); |
d5b7b3ae RE |
10153 | |
10154 | if (GET_CODE (operands[1]) != MEM) | |
400500c4 | 10155 | abort (); |
d5b7b3ae RE |
10156 | |
10157 | /* Get the memory address. */ | |
10158 | addr = XEXP (operands[1], 0); | |
10159 | ||
10160 | /* Work out how the memory address is computed. */ | |
10161 | switch (GET_CODE (addr)) | |
10162 | { | |
10163 | case REG: | |
10164 | operands[2] = gen_rtx (MEM, SImode, | |
10165 | plus_constant (XEXP (operands[1], 0), 4)); | |
10166 | ||
10167 | if (REGNO (operands[0]) == REGNO (addr)) | |
10168 | { | |
10169 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10170 | output_asm_insn ("ldr\t%0, %1", operands); | |
10171 | } | |
10172 | else | |
10173 | { | |
10174 | output_asm_insn ("ldr\t%0, %1", operands); | |
10175 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10176 | } | |
10177 | break; | |
10178 | ||
10179 | case CONST: | |
10180 | /* Compute <address> + 4 for the high order load. */ | |
10181 | operands[2] = gen_rtx (MEM, SImode, | |
10182 | plus_constant (XEXP (operands[1], 0), 4)); | |
10183 | ||
10184 | output_asm_insn ("ldr\t%0, %1", operands); | |
10185 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10186 | break; | |
10187 | ||
10188 | case PLUS: | |
10189 | arg1 = XEXP (addr, 0); | |
10190 | arg2 = XEXP (addr, 1); | |
10191 | ||
10192 | if (CONSTANT_P (arg1)) | |
10193 | base = arg2, offset = arg1; | |
10194 | else | |
10195 | base = arg1, offset = arg2; | |
10196 | ||
10197 | if (GET_CODE (base) != REG) | |
400500c4 | 10198 | abort (); |
d5b7b3ae RE |
10199 | |
10200 | /* Catch the case of <address> = <reg> + <reg> */ | |
10201 | if (GET_CODE (offset) == REG) | |
10202 | { | |
10203 | int reg_offset = REGNO (offset); | |
10204 | int reg_base = REGNO (base); | |
10205 | int reg_dest = REGNO (operands[0]); | |
10206 | ||
10207 | /* Add the base and offset registers together into the | |
10208 | higher destination register. */ | |
10209 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
10210 | reg_dest + 1, reg_base, reg_offset); | |
10211 | ||
10212 | /* Load the lower destination register from the address in | |
10213 | the higher destination register. */ | |
10214 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
10215 | reg_dest, reg_dest + 1); | |
10216 | ||
10217 | /* Load the higher destination register from its own address | |
10218 | plus 4. */ | |
10219 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
10220 | reg_dest + 1, reg_dest + 1); | |
10221 | } | |
10222 | else | |
10223 | { | |
10224 | /* Compute <address> + 4 for the high order load. */ | |
10225 | operands[2] = gen_rtx (MEM, SImode, | |
10226 | plus_constant (XEXP (operands[1], 0), 4)); | |
10227 | ||
10228 | /* If the computed address is held in the low order register | |
10229 | then load the high order register first, otherwise always | |
10230 | load the low order register first. */ | |
10231 | if (REGNO (operands[0]) == REGNO (base)) | |
10232 | { | |
10233 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10234 | output_asm_insn ("ldr\t%0, %1", operands); | |
10235 | } | |
10236 | else | |
10237 | { | |
10238 | output_asm_insn ("ldr\t%0, %1", operands); | |
10239 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10240 | } | |
10241 | } | |
10242 | break; | |
10243 | ||
10244 | case LABEL_REF: | |
10245 | /* With no registers to worry about we can just load the value | |
10246 | directly. */ | |
10247 | operands[2] = gen_rtx (MEM, SImode, | |
10248 | plus_constant (XEXP (operands[1], 0), 4)); | |
10249 | ||
10250 | output_asm_insn ("ldr\t%H0, %2", operands); | |
10251 | output_asm_insn ("ldr\t%0, %1", operands); | |
10252 | break; | |
10253 | ||
10254 | default: | |
400500c4 | 10255 | abort (); |
d5b7b3ae RE |
10256 | break; |
10257 | } | |
10258 | ||
10259 | return ""; | |
10260 | } | |
10261 | ||
10262 | ||
cd2b33d0 | 10263 | const char * |
d5b7b3ae RE |
10264 | thumb_output_move_mem_multiple (n, operands) |
10265 | int n; | |
10266 | rtx * operands; | |
10267 | { | |
10268 | rtx tmp; | |
10269 | ||
10270 | switch (n) | |
10271 | { | |
10272 | case 2: | |
ca356f3a | 10273 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 10274 | { |
ca356f3a RE |
10275 | tmp = operands[4]; |
10276 | operands[4] = operands[5]; | |
10277 | operands[5] = tmp; | |
d5b7b3ae | 10278 | } |
ca356f3a RE |
10279 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
10280 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
10281 | break; |
10282 | ||
10283 | case 3: | |
ca356f3a | 10284 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 10285 | { |
ca356f3a RE |
10286 | tmp = operands[4]; |
10287 | operands[4] = operands[5]; | |
10288 | operands[5] = tmp; | |
d5b7b3ae | 10289 | } |
ca356f3a | 10290 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 10291 | { |
ca356f3a RE |
10292 | tmp = operands[5]; |
10293 | operands[5] = operands[6]; | |
10294 | operands[6] = tmp; | |
d5b7b3ae | 10295 | } |
ca356f3a | 10296 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 10297 | { |
ca356f3a RE |
10298 | tmp = operands[4]; |
10299 | operands[4] = operands[5]; | |
10300 | operands[5] = tmp; | |
d5b7b3ae RE |
10301 | } |
10302 | ||
ca356f3a RE |
10303 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
10304 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
10305 | break; |
10306 | ||
10307 | default: | |
10308 | abort (); | |
10309 | } | |
10310 | ||
10311 | return ""; | |
10312 | } | |
10313 | ||
10314 | /* Routines for generating rtl */ | |
10315 | ||
10316 | void | |
10317 | thumb_expand_movstrqi (operands) | |
10318 | rtx * operands; | |
10319 | { | |
10320 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
10321 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
10322 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
10323 | HOST_WIDE_INT offset = 0; | |
10324 | ||
10325 | while (len >= 12) | |
10326 | { | |
ca356f3a | 10327 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
10328 | len -= 12; |
10329 | } | |
10330 | ||
10331 | if (len >= 8) | |
10332 | { | |
ca356f3a | 10333 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
10334 | len -= 8; |
10335 | } | |
10336 | ||
10337 | if (len >= 4) | |
10338 | { | |
10339 | rtx reg = gen_reg_rtx (SImode); | |
10340 | emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in))); | |
10341 | emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg)); | |
10342 | len -= 4; | |
10343 | offset += 4; | |
10344 | } | |
10345 | ||
10346 | if (len >= 2) | |
10347 | { | |
10348 | rtx reg = gen_reg_rtx (HImode); | |
10349 | emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode, | |
10350 | plus_constant (in, offset)))); | |
10351 | emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)), | |
10352 | reg)); | |
10353 | len -= 2; | |
10354 | offset += 2; | |
10355 | } | |
10356 | ||
10357 | if (len) | |
10358 | { | |
10359 | rtx reg = gen_reg_rtx (QImode); | |
10360 | emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode, | |
10361 | plus_constant (in, offset)))); | |
10362 | emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)), | |
10363 | reg)); | |
10364 | } | |
10365 | } | |
10366 | ||
10367 | int | |
10368 | thumb_cmp_operand (op, mode) | |
10369 | rtx op; | |
10370 | enum machine_mode mode; | |
10371 | { | |
10372 | return ((GET_CODE (op) == CONST_INT | |
10373 | && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256) | |
10374 | || register_operand (op, mode)); | |
10375 | } | |
10376 | ||
cd2b33d0 | 10377 | static const char * |
d5b7b3ae RE |
10378 | thumb_condition_code (x, invert) |
10379 | rtx x; | |
10380 | int invert; | |
10381 | { | |
cd2b33d0 | 10382 | static const char * conds[] = |
d5b7b3ae RE |
10383 | { |
10384 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
10385 | "hi", "ls", "ge", "lt", "gt", "le" | |
10386 | }; | |
10387 | int val; | |
10388 | ||
10389 | switch (GET_CODE (x)) | |
10390 | { | |
10391 | case EQ: val = 0; break; | |
10392 | case NE: val = 1; break; | |
10393 | case GEU: val = 2; break; | |
10394 | case LTU: val = 3; break; | |
10395 | case GTU: val = 8; break; | |
10396 | case LEU: val = 9; break; | |
10397 | case GE: val = 10; break; | |
10398 | case LT: val = 11; break; | |
10399 | case GT: val = 12; break; | |
10400 | case LE: val = 13; break; | |
10401 | default: | |
10402 | abort (); | |
10403 | } | |
10404 | ||
10405 | return conds[val ^ invert]; | |
10406 | } | |
10407 | ||
10408 | /* Handle storing a half-word to memory during reload. */ | |
10409 | void | |
10410 | thumb_reload_out_hi (operands) | |
10411 | rtx * operands; | |
10412 | { | |
10413 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
10414 | } | |
10415 | ||
10416 | /* Handle storing a half-word to memory during reload. */ | |
10417 | void | |
10418 | thumb_reload_in_hi (operands) | |
10419 | rtx * operands ATTRIBUTE_UNUSED; | |
10420 | { | |
10421 | abort (); | |
10422 | } | |
10423 | ||
c27ba912 DM |
10424 | /* Return the length of a function name prefix |
10425 | that starts with the character 'c'. */ | |
10426 | static int | |
10427 | arm_get_strip_length (char c) | |
10428 | { | |
10429 | switch (c) | |
10430 | { | |
10431 | ARM_NAME_ENCODING_LENGTHS | |
10432 | default: return 0; | |
10433 | } | |
10434 | } | |
10435 | ||
10436 | /* Return a pointer to a function's name with any | |
10437 | and all prefix encodings stripped from it. */ | |
10438 | const char * | |
10439 | arm_strip_name_encoding (const char * name) | |
10440 | { | |
10441 | int skip; | |
10442 | ||
10443 | while ((skip = arm_get_strip_length (* name))) | |
10444 | name += skip; | |
10445 | ||
10446 | return name; | |
10447 | } | |
10448 | ||
2b835d68 | 10449 | #ifdef AOF_ASSEMBLER |
6354dc9b | 10450 | /* Special functions only needed when producing AOF syntax assembler. */ |
2b835d68 | 10451 | |
32de079a RE |
10452 | rtx aof_pic_label = NULL_RTX; |
10453 | struct pic_chain | |
10454 | { | |
62b10bbc NC |
10455 | struct pic_chain * next; |
10456 | char * symname; | |
32de079a RE |
10457 | }; |
10458 | ||
62b10bbc | 10459 | static struct pic_chain * aof_pic_chain = NULL; |
32de079a RE |
10460 | |
10461 | rtx | |
10462 | aof_pic_entry (x) | |
10463 | rtx x; | |
10464 | { | |
62b10bbc | 10465 | struct pic_chain ** chainp; |
32de079a RE |
10466 | int offset; |
10467 | ||
10468 | if (aof_pic_label == NULL_RTX) | |
10469 | { | |
92a432f4 RE |
10470 | /* We mark this here and not in arm_add_gc_roots() to avoid |
10471 | polluting even more code with ifdefs, and because it never | |
10472 | contains anything useful until we assign to it here. */ | |
5895f793 | 10473 | ggc_add_rtx_root (&aof_pic_label, 1); |
43cffd11 | 10474 | aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); |
32de079a RE |
10475 | } |
10476 | ||
10477 | for (offset = 0, chainp = &aof_pic_chain; *chainp; | |
10478 | offset += 4, chainp = &(*chainp)->next) | |
10479 | if ((*chainp)->symname == XSTR (x, 0)) | |
10480 | return plus_constant (aof_pic_label, offset); | |
10481 | ||
10482 | *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); | |
10483 | (*chainp)->next = NULL; | |
10484 | (*chainp)->symname = XSTR (x, 0); | |
10485 | return plus_constant (aof_pic_label, offset); | |
10486 | } | |
10487 | ||
10488 | void | |
10489 | aof_dump_pic_table (f) | |
62b10bbc | 10490 | FILE * f; |
32de079a | 10491 | { |
62b10bbc | 10492 | struct pic_chain * chain; |
32de079a RE |
10493 | |
10494 | if (aof_pic_chain == NULL) | |
10495 | return; | |
10496 | ||
dd18ae56 NC |
10497 | asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", |
10498 | PIC_OFFSET_TABLE_REGNUM, | |
10499 | PIC_OFFSET_TABLE_REGNUM); | |
32de079a RE |
10500 | fputs ("|x$adcons|\n", f); |
10501 | ||
10502 | for (chain = aof_pic_chain; chain; chain = chain->next) | |
10503 | { | |
10504 | fputs ("\tDCD\t", f); | |
10505 | assemble_name (f, chain->symname); | |
10506 | fputs ("\n", f); | |
10507 | } | |
10508 | } | |
10509 | ||
2b835d68 RE |
10510 | int arm_text_section_count = 1; |
10511 | ||
10512 | char * | |
84ed5e79 | 10513 | aof_text_section () |
2b835d68 RE |
10514 | { |
10515 | static char buf[100]; | |
2b835d68 RE |
10516 | sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", |
10517 | arm_text_section_count++); | |
10518 | if (flag_pic) | |
10519 | strcat (buf, ", PIC, REENTRANT"); | |
10520 | return buf; | |
10521 | } | |
10522 | ||
10523 | static int arm_data_section_count = 1; | |
10524 | ||
10525 | char * | |
10526 | aof_data_section () | |
10527 | { | |
10528 | static char buf[100]; | |
10529 | sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); | |
10530 | return buf; | |
10531 | } | |
10532 | ||
10533 | /* The AOF assembler is religiously strict about declarations of | |
10534 | imported and exported symbols, so that it is impossible to declare | |
956d6950 | 10535 | a function as imported near the beginning of the file, and then to |
2b835d68 RE |
10536 | export it later on. It is, however, possible to delay the decision |
10537 | until all the functions in the file have been compiled. To get | |
10538 | around this, we maintain a list of the imports and exports, and | |
10539 | delete from it any that are subsequently defined. At the end of | |
10540 | compilation we spit the remainder of the list out before the END | |
10541 | directive. */ | |
10542 | ||
10543 | struct import | |
10544 | { | |
62b10bbc NC |
10545 | struct import * next; |
10546 | char * name; | |
2b835d68 RE |
10547 | }; |
10548 | ||
62b10bbc | 10549 | static struct import * imports_list = NULL; |
2b835d68 RE |
10550 | |
10551 | void | |
10552 | aof_add_import (name) | |
62b10bbc | 10553 | char * name; |
2b835d68 | 10554 | { |
62b10bbc | 10555 | struct import * new; |
2b835d68 RE |
10556 | |
10557 | for (new = imports_list; new; new = new->next) | |
10558 | if (new->name == name) | |
10559 | return; | |
10560 | ||
10561 | new = (struct import *) xmalloc (sizeof (struct import)); | |
10562 | new->next = imports_list; | |
10563 | imports_list = new; | |
10564 | new->name = name; | |
10565 | } | |
10566 | ||
10567 | void | |
10568 | aof_delete_import (name) | |
62b10bbc | 10569 | char * name; |
2b835d68 | 10570 | { |
62b10bbc | 10571 | struct import ** old; |
2b835d68 RE |
10572 | |
10573 | for (old = &imports_list; *old; old = & (*old)->next) | |
10574 | { | |
10575 | if ((*old)->name == name) | |
10576 | { | |
10577 | *old = (*old)->next; | |
10578 | return; | |
10579 | } | |
10580 | } | |
10581 | } | |
10582 | ||
10583 | int arm_main_function = 0; | |
10584 | ||
10585 | void | |
10586 | aof_dump_imports (f) | |
62b10bbc | 10587 | FILE * f; |
2b835d68 RE |
10588 | { |
10589 | /* The AOF assembler needs this to cause the startup code to be extracted | |
10590 | from the library. Brining in __main causes the whole thing to work | |
10591 | automagically. */ | |
10592 | if (arm_main_function) | |
10593 | { | |
10594 | text_section (); | |
10595 | fputs ("\tIMPORT __main\n", f); | |
10596 | fputs ("\tDCD __main\n", f); | |
10597 | } | |
10598 | ||
10599 | /* Now dump the remaining imports. */ | |
10600 | while (imports_list) | |
10601 | { | |
10602 | fprintf (f, "\tIMPORT\t"); | |
10603 | assemble_name (f, imports_list->name); | |
10604 | fputc ('\n', f); | |
10605 | imports_list = imports_list->next; | |
10606 | } | |
10607 | } | |
10608 | #endif /* AOF_ASSEMBLER */ |