]> gcc.gnu.org Git - gcc.git/blame - gcc/config/arm/arm.c
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ug_words: Add entries for -gnatw.b/-gnatw.B
[gcc.git] / gcc / config / arm / arm.c
CommitLineData
b36ba79f 1/* Output routines for GCC for ARM.
f954388e 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
bf98ec6c 3 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
cce8749e 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
956d6950 5 and Martin Simmons (@harleqn.co.uk).
b36ba79f 6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
cce8749e 7
4f448245 8 This file is part of GCC.
cce8749e 9
4f448245
NC		 10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
2f83c7d6 12 by the Free Software Foundation; either version 3, or (at your
4f448245 13 option) any later version.
cce8749e 14
4f448245
NC		 15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
cce8749e 19
4f448245 20 You should have received a copy of the GNU General Public License
2f83c7d6
NC		 21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
f676971a 23
56636818 24#include "config.h"
43cffd11 25#include "system.h"
4977bab6
ZW		 26#include "coretypes.h"
27#include "tm.h"
cce8749e 28#include "rtl.h"
d5b7b3ae 29#include "tree.h"
c7319d87 30#include "obstack.h"
cce8749e
CH		 31#include "regs.h"
32#include "hard-reg-set.h"
33#include "real.h"
34#include "insn-config.h"
35#include "conditions.h"
cce8749e
CH		 36#include "output.h"
37#include "insn-attr.h"
38#include "flags.h"
af48348a 39#include "reload.h"
49ad7cfa 40#include "function.h"
bee06f3d 41#include "expr.h"
e78d8e51 42#include "optabs.h"
ad076f4e 43#include "toplev.h"
aec3cfba 44#include "recog.h"
92a432f4 45#include "ggc.h"
d5b7b3ae 46#include "except.h"
8b97c5f8 47#include "c-pragma.h"
7b8b8ade 48#include "integrate.h"
c27ba912 49#include "tm_p.h"
672a6f42
NB		 50#include "target.h"
51#include "target-def.h"
980e61bb 52#include "debug.h"
6e34d3a3 53#include "langhooks.h"
6fb5fa3c 54#include "df.h"
cce8749e 55
d5b7b3ae
RE		 56/* Forward definitions of types. */
57typedef struct minipool_node Mnode;
58typedef struct minipool_fixup Mfix;
59
1d6e90ac
NC		 60const struct attribute_spec arm_attribute_table[];
61
b76c3c4b
PB		 62void (*arm_lang_output_object_attributes_hook)(void);
63
d5b7b3ae 64/* Forward function declarations. */
35596784 65static int arm_compute_static_chain_stack_bytes (void);
5848830f 66static arm_stack_offsets *arm_get_frame_offsets (void);
e32bac5b 67static void arm_add_gc_roots (void);
a406f566
MM		 68static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
69 HOST_WIDE_INT, rtx, rtx, int, int);
e32bac5b
RE		 70static unsigned bit_count (unsigned long);
71static int arm_address_register_rtx_p (rtx, int);
1e1ab407 72static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
5b3e6663
PB		 73static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
74static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
75inline static int thumb1_index_register_rtx_p (rtx, int);
5848830f 76static int thumb_far_jump_used_p (void);
57934c39 77static bool thumb_force_lr_save (void);
e32bac5b 78static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
e32bac5b 79static rtx emit_sfm (int, int);
466e4b7a 80static unsigned arm_size_return_regs (void);
e32bac5b 81static bool arm_assemble_integer (rtx, unsigned int, int);
e32bac5b
RE		 82static const char *fp_const_from_val (REAL_VALUE_TYPE *);
83static arm_cc get_arm_condition_code (rtx);
e32bac5b
RE		 84static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
85static rtx is_jump_table (rtx);
86static const char *output_multi_immediate (rtx *, const char *, const char *,
87 int, HOST_WIDE_INT);
e32bac5b
RE		 88static const char *shift_op (rtx, HOST_WIDE_INT *);
89static struct machine_function *arm_init_machine_status (void);
c9ca9b88 90static void thumb_exit (FILE *, int);
e32bac5b
RE		 91static rtx is_jump_table (rtx);
92static HOST_WIDE_INT get_jump_table_size (rtx);
93static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94static Mnode *add_minipool_forward_ref (Mfix *);
95static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96static Mnode *add_minipool_backward_ref (Mfix *);
97static void assign_minipool_offsets (Mfix *);
98static void arm_print_value (FILE *, rtx);
99static void dump_minipool (rtx);
100static int arm_barrier_cost (rtx);
101static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
104 rtx);
105static void arm_reorg (void);
106static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
e32bac5b
RE		 107static unsigned long arm_compute_save_reg0_reg12_mask (void);
108static unsigned long arm_compute_save_reg_mask (void);
109static unsigned long arm_isr_value (tree);
110static unsigned long arm_compute_func_type (void);
111static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
112static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
7bff66a7 113#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
04fb56d5 114static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
7bff66a7 115#endif
e32bac5b
RE		 116static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
117static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
5b3e6663 118static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
3101faab 119static int arm_comp_type_attributes (const_tree, const_tree);
e32bac5b
RE		 120static void arm_set_default_type_attributes (tree);
121static int arm_adjust_cost (rtx, rtx, rtx, int);
e32bac5b
RE		 122static int count_insns_for_constant (HOST_WIDE_INT, int);
123static int arm_get_strip_length (int);
124static bool arm_function_ok_for_sibcall (tree, tree);
125static void arm_internal_label (FILE *, const char *, unsigned long);
126static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 tree);
128static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
21b5653c 129static bool arm_size_rtx_costs (rtx, int, int, int *);
9b66ebb1
PB		 130static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
131static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
132static bool arm_xscale_rtx_costs (rtx, int, int, int *);
133static bool arm_9e_rtx_costs (rtx, int, int, int *);
e32bac5b
RE		 134static int arm_address_cost (rtx);
135static bool arm_memory_load_p (rtx);
136static bool arm_cirrus_insn_p (rtx);
137static void cirrus_reorg (rtx);
5a9335ef
NC		 138static void arm_init_builtins (void);
139static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
140static void arm_init_iwmmxt_builtins (void);
141static rtx safe_vector_operand (rtx, enum machine_mode);
142static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
143static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
144static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
a406f566 145static void emit_constant_insn (rtx cond, rtx pattern);
d66437c5 146static rtx emit_set_insn (rtx, rtx);
78a52f11
RH		 147static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 tree, bool);
5a9335ef 149
7abc66b1 150#ifdef OBJECT_FORMAT_ELF
9403b7f7
RS		 151static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
152static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
7abc66b1 153#endif
fb49053f 154#ifndef ARM_PE
e32bac5b 155static void arm_encode_section_info (tree, rtx, int);
fb49053f 156#endif
b12a00f1
RE		 157
158static void arm_file_end (void);
6c6aa1af 159static void arm_file_start (void);
b12a00f1 160
1cc9f5f5
KH		 161static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
162 tree, int *, int);
8cd5a4e0 163static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
586de218
KG		 164 enum machine_mode, const_tree, bool);
165static bool arm_promote_prototypes (const_tree);
6b045785 166static bool arm_default_short_enums (void);
13c1cd82 167static bool arm_align_anon_bitfield (void);
586de218
KG		 168static bool arm_return_in_msb (const_tree);
169static bool arm_must_pass_in_stack (enum machine_mode, const_tree);
23668cf7 170static bool arm_return_in_memory (const_tree, const_tree);
617a1b71
PB		 171#ifdef TARGET_UNWIND_INFO
172static void arm_unwind_emit (FILE *, rtx);
173static bool arm_output_ttype (rtx);
174#endif
5b3e6663 175static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
c237e94a 176
4185ae53
PB		 177static tree arm_cxx_guard_type (void);
178static bool arm_cxx_guard_mask_bit (void);
46e995e0
PB		 179static tree arm_get_cookie_size (tree);
180static bool arm_cookie_has_size (void);
44d10c10 181static bool arm_cxx_cdtor_returns_this (void);
505970fc 182static bool arm_cxx_key_method_may_be_inline (void);
1e731102
MM		 183static void arm_cxx_determine_class_data_visibility (tree);
184static bool arm_cxx_class_data_always_comdat (void);
9f62c3e3 185static bool arm_cxx_use_aeabi_atexit (void);
b3f8d95d 186static void arm_init_libfuncs (void);
c54c7322 187static bool arm_handle_option (size_t, const char *, int);
67e6ba46 188static void arm_target_help (void);
273a2526 189static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
d3585b76
DJ		 190static bool arm_cannot_copy_insn_p (rtx);
191static bool arm_tls_symbol_p (rtx x);
bd4dc3cd 192static int arm_issue_rate (void);
afcc986d 193static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
007e61c2 194static bool arm_allocate_stack_slots_for_args (void);
d3585b76 195
672a6f42
NB		 196\f
197/* Initialize the GCC target structure. */
b2ca3702 198#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1d6e90ac 199#undef TARGET_MERGE_DECL_ATTRIBUTES
672a6f42
NB		 200#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
201#endif
f3bb6135 202
1d6e90ac 203#undef TARGET_ATTRIBUTE_TABLE
91d231cb 204#define TARGET_ATTRIBUTE_TABLE arm_attribute_table
672a6f42 205
6c6aa1af
PB		 206#undef TARGET_ASM_FILE_START
207#define TARGET_ASM_FILE_START arm_file_start
b12a00f1
RE		 208#undef TARGET_ASM_FILE_END
209#define TARGET_ASM_FILE_END arm_file_end
210
1d6e90ac 211#undef TARGET_ASM_ALIGNED_SI_OP
301d03af 212#define TARGET_ASM_ALIGNED_SI_OP NULL
1d6e90ac 213#undef TARGET_ASM_INTEGER
301d03af 214#define TARGET_ASM_INTEGER arm_assemble_integer
301d03af 215
1d6e90ac 216#undef TARGET_ASM_FUNCTION_PROLOGUE
08c148a8
NB		 217#define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
218
1d6e90ac 219#undef TARGET_ASM_FUNCTION_EPILOGUE
08c148a8
NB		 220#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
221
c54c7322
RS		 222#undef TARGET_DEFAULT_TARGET_FLAGS
223#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
224#undef TARGET_HANDLE_OPTION
225#define TARGET_HANDLE_OPTION arm_handle_option
67e6ba46
NC		 226#undef TARGET_HELP
227#define TARGET_HELP arm_target_help
c54c7322 228
1d6e90ac 229#undef TARGET_COMP_TYPE_ATTRIBUTES
8d8e52be
JM		 230#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
231
1d6e90ac 232#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
8d8e52be
JM		 233#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
234
1d6e90ac 235#undef TARGET_SCHED_ADJUST_COST
c237e94a
ZW		 236#define TARGET_SCHED_ADJUST_COST arm_adjust_cost
237
fb49053f
RH		 238#undef TARGET_ENCODE_SECTION_INFO
239#ifdef ARM_PE
240#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
241#else
242#define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
243#endif
244
5a9335ef 245#undef TARGET_STRIP_NAME_ENCODING
772c5265
RH		 246#define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
247
5a9335ef 248#undef TARGET_ASM_INTERNAL_LABEL
4977bab6
ZW		 249#define TARGET_ASM_INTERNAL_LABEL arm_internal_label
250
5a9335ef 251#undef TARGET_FUNCTION_OK_FOR_SIBCALL
4977bab6
ZW		 252#define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
253
5a9335ef 254#undef TARGET_ASM_OUTPUT_MI_THUNK
c590b625 255#define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
5a9335ef 256#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3961e8fe 257#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
c590b625 258
9b66ebb1 259/* This will be overridden in arm_override_options. */
5a9335ef 260#undef TARGET_RTX_COSTS
9b66ebb1 261#define TARGET_RTX_COSTS arm_slowmul_rtx_costs
5a9335ef 262#undef TARGET_ADDRESS_COST
dcefdf67 263#define TARGET_ADDRESS_COST arm_address_cost
3c50106f 264
273a2526
RS		 265#undef TARGET_SHIFT_TRUNCATION_MASK
266#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
f676971a
EC		 267#undef TARGET_VECTOR_MODE_SUPPORTED_P
268#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
269
5a9335ef 270#undef TARGET_MACHINE_DEPENDENT_REORG
18dbd950
RS		 271#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
272
5a9335ef
NC		 273#undef TARGET_INIT_BUILTINS
274#define TARGET_INIT_BUILTINS arm_init_builtins
275#undef TARGET_EXPAND_BUILTIN
276#define TARGET_EXPAND_BUILTIN arm_expand_builtin
277
b3f8d95d
MM		 278#undef TARGET_INIT_LIBFUNCS
279#define TARGET_INIT_LIBFUNCS arm_init_libfuncs
280
f9ba5949 281#undef TARGET_PROMOTE_FUNCTION_ARGS
586de218 282#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
d4453b7a 283#undef TARGET_PROMOTE_FUNCTION_RETURN
586de218 284#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
f9ba5949 285#undef TARGET_PROMOTE_PROTOTYPES
70301b45 286#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
8cd5a4e0
RH		 287#undef TARGET_PASS_BY_REFERENCE
288#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
78a52f11
RH		 289#undef TARGET_ARG_PARTIAL_BYTES
290#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
f9ba5949 291
1cc9f5f5
KH		 292#undef TARGET_SETUP_INCOMING_VARARGS
293#define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
294
007e61c2
PB		 295#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
296#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
297
6b045785
PB		 298#undef TARGET_DEFAULT_SHORT_ENUMS
299#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
300
13c1cd82
PB		 301#undef TARGET_ALIGN_ANON_BITFIELD
302#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
303
c2a64439
PB		 304#undef TARGET_NARROW_VOLATILE_BITFIELD
305#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
306
4185ae53
PB		 307#undef TARGET_CXX_GUARD_TYPE
308#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
309
310#undef TARGET_CXX_GUARD_MASK_BIT
311#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
312
46e995e0
PB		 313#undef TARGET_CXX_GET_COOKIE_SIZE
314#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
315
316#undef TARGET_CXX_COOKIE_HAS_SIZE
317#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
318
44d10c10
PB		 319#undef TARGET_CXX_CDTOR_RETURNS_THIS
320#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
321
505970fc
MM		 322#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
323#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
324
9f62c3e3
PB		 325#undef TARGET_CXX_USE_AEABI_ATEXIT
326#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
327
1e731102
MM		 328#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
329#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
330 arm_cxx_determine_class_data_visibility
331
332#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
333#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
505970fc 334
866af8a9
JB		 335#undef TARGET_RETURN_IN_MSB
336#define TARGET_RETURN_IN_MSB arm_return_in_msb
337
23668cf7
CLT		 338#undef TARGET_RETURN_IN_MEMORY
339#define TARGET_RETURN_IN_MEMORY arm_return_in_memory
340
866af8a9
JB		 341#undef TARGET_MUST_PASS_IN_STACK
342#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
343
617a1b71
PB		 344#ifdef TARGET_UNWIND_INFO
345#undef TARGET_UNWIND_EMIT
346#define TARGET_UNWIND_EMIT arm_unwind_emit
347
348/* EABI unwinding tables use a different format for the typeinfo tables. */
349#undef TARGET_ASM_TTYPE
350#define TARGET_ASM_TTYPE arm_output_ttype
351
352#undef TARGET_ARM_EABI_UNWINDER
353#define TARGET_ARM_EABI_UNWINDER true
354#endif /* TARGET_UNWIND_INFO */
355
5b3e6663
PB		 356#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
357#define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
358
d3585b76
DJ		 359#undef TARGET_CANNOT_COPY_INSN_P
360#define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
361
362#ifdef HAVE_AS_TLS
363#undef TARGET_HAVE_TLS
364#define TARGET_HAVE_TLS true
365#endif
366
367#undef TARGET_CANNOT_FORCE_CONST_MEM
8426b956 368#define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem
d3585b76 369
bd4dc3cd
PB		 370#undef TARGET_SCHED_ISSUE_RATE
371#define TARGET_SCHED_ISSUE_RATE arm_issue_rate
372
608063c3
JB		 373#undef TARGET_MANGLE_TYPE
374#define TARGET_MANGLE_TYPE arm_mangle_type
375
afcc986d
JM		 376#ifdef HAVE_AS_TLS
377#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
378#define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
379#endif
380
f6897b10 381struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 382\f
c7319d87
RE		 383/* Obstack for minipool constant handling. */
384static struct obstack minipool_obstack;
1d6e90ac 385static char * minipool_startobj;
c7319d87 386
1d6e90ac
NC		 387/* The maximum number of insns skipped which
388 will be conditionalised if possible. */
c27ba912
DM		 389static int max_insns_skipped = 5;
390
391extern FILE * asm_out_file;
392
6354dc9b 393/* True if we are currently building a constant table. */
13bd191d
PB		 394int making_const_table;
395
60d0536b 396/* Define the information needed to generate branch insns. This is
6354dc9b 397 stored from the compare operation. */
ff9940b0 398rtx arm_compare_op0, arm_compare_op1;
ff9940b0 399
9b66ebb1
PB		 400/* The processor for which instructions should be scheduled. */
401enum processor_type arm_tune = arm_none;
402
2f8e468b 403/* The default processor used if not overridden by commandline. */
6c6aa1af
PB		 404static enum processor_type arm_default_cpu = arm_none;
405
9b66ebb1
PB		 406/* Which floating point model to use. */
407enum arm_fp_model arm_fp_model;
bee06f3d 408
9b66ebb1 409/* Which floating point hardware is available. */
29ad9694 410enum fputype arm_fpu_arch;
b111229a 411
9b66ebb1
PB		 412/* Which floating point hardware to schedule for. */
413enum fputype arm_fpu_tune;
414
415/* Whether to use floating point hardware. */
416enum float_abi_type arm_float_abi;
417
5848830f
PB		 418/* Which ABI to use. */
419enum arm_abi_type arm_abi;
420
d3585b76
DJ		 421/* Which thread pointer model to use. */
422enum arm_tp_type target_thread_pointer = TP_AUTO;
423
b355a481 424/* Used to parse -mstructure_size_boundary command line option. */
723ae7c1 425int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
b355a481 426
b12a00f1 427/* Used for Thumb call_via trampolines. */
57ecec57 428rtx thumb_call_via_label[14];
b12a00f1
RE		 429static int thumb_call_reg_needed;
430
aec3cfba 431/* Bit values used to identify processor capabilities. */
62b10bbc 432#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
9b66ebb1 433#define FL_ARCH3M (1 << 1) /* Extended multiply */
62b10bbc
NC		 434#define FL_MODE26 (1 << 2) /* 26-bit mode support */
435#define FL_MODE32 (1 << 3) /* 32-bit mode support */
436#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
437#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
438#define FL_THUMB (1 << 6) /* Thumb aware */
439#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
440#define FL_STRONG (1 << 8) /* StrongARM */
6bc82793 441#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
d19fb8e3 442#define FL_XSCALE (1 << 10) /* XScale */
9b6b54e2 443#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
9b66ebb1 444#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
81f9037c
MM		 445 media instructions. */
446#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
abac3b49
RE		 447#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
448 Note: ARM6 & 7 derivatives only. */
d3585b76 449#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
5b3e6663
PB		 450#define FL_THUMB2 (1 << 16) /* Thumb-2. */
451#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
452 profile. */
7a085dce 453#define FL_DIV (1 << 18) /* Hardware divide. */
f1adb0a9 454#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
88f77cba 455#define FL_NEON (1 << 20) /* Neon instructions. */
aec3cfba 456
9b66ebb1
PB		 457#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
458
5b3e6663
PB		 459#define FL_FOR_ARCH2 FL_NOTM
460#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
78011587
PB		 461#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
462#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
463#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
464#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
465#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
466#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
467#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
468#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
469#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
470#define FL_FOR_ARCH6J FL_FOR_ARCH6
d3585b76 471#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
fa91adc6 472#define FL_FOR_ARCH6Z FL_FOR_ARCH6
d3585b76 473#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
5b3e6663 474#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
bf98ec6c 475#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
5b3e6663
PB		 476#define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
477#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
478#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
479#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
78011587 480
1d6e90ac
NC		 481/* The bits in this mask specify which
482 instructions we are allowed to generate. */
0977774b 483static unsigned long insn_flags = 0;
d5b7b3ae 484
aec3cfba 485/* The bits in this mask specify which instruction scheduling options should
9b66ebb1 486 be used. */
0977774b 487static unsigned long tune_flags = 0;
aec3cfba
NC		 488
489/* The following are used in the arm.md file as equivalents to bits
490 in the above two flag variables. */
491
9b66ebb1
PB		 492/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
493int arm_arch3m = 0;
2b835d68 494
6354dc9b 495/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
2b835d68
RE		 496int arm_arch4 = 0;
497
68d560d4
RE		 498/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
499int arm_arch4t = 0;
500
6354dc9b 501/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
62b10bbc
NC		 502int arm_arch5 = 0;
503
b15bca31
RE		 504/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
505int arm_arch5e = 0;
506
9b66ebb1
PB		 507/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
508int arm_arch6 = 0;
509
d3585b76
DJ		 510/* Nonzero if this chip supports the ARM 6K extensions. */
511int arm_arch6k = 0;
512
5b3e6663
PB		 513/* Nonzero if instructions not present in the 'M' profile can be used. */
514int arm_arch_notm = 0;
515
aec3cfba 516/* Nonzero if this chip can benefit from load scheduling. */
f5a1b0d2
NC		 517int arm_ld_sched = 0;
518
519/* Nonzero if this chip is a StrongARM. */
abac3b49 520int arm_tune_strongarm = 0;
f5a1b0d2 521
78011587
PB		 522/* Nonzero if this chip is a Cirrus variant. */
523int arm_arch_cirrus = 0;
524
5a9335ef
NC		 525/* Nonzero if this chip supports Intel Wireless MMX technology. */
526int arm_arch_iwmmxt = 0;
527
d19fb8e3 528/* Nonzero if this chip is an XScale. */
4b3c2e48
PB		 529int arm_arch_xscale = 0;
530
531/* Nonzero if tuning for XScale */
532int arm_tune_xscale = 0;
d19fb8e3 533
e0b92319 534/* Nonzero if we want to tune for stores that access the write-buffer.
c5d34bb2 535 This typically means an ARM6 or ARM7 with MMU or MPU. */
abac3b49 536int arm_tune_wbuf = 0;
b111229a 537
0616531f
RE		 538/* Nonzero if generating Thumb instructions. */
539int thumb_code = 0;
540
2ad4dcf9 541/* Nonzero if we should define __THUMB_INTERWORK__ in the
f676971a 542 preprocessor.
2ad4dcf9
RE		 543 XXX This is a bit of a hack, it's intended to help work around
544 problems in GLD which doesn't understand that armv5t code is
545 interworking clean. */
546int arm_cpp_interwork = 0;
547
5b3e6663
PB		 548/* Nonzero if chip supports Thumb 2. */
549int arm_arch_thumb2;
550
551/* Nonzero if chip supports integer division instruction. */
552int arm_arch_hwdiv;
553
cce8749e
CH		 554/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
555 must report the mode of the memory reference from PRINT_OPERAND to
556 PRINT_OPERAND_ADDRESS. */
f3bb6135 557enum machine_mode output_memory_reference_mode;
cce8749e 558
32de079a 559/* The register number to be used for the PIC offset register. */
020a4035 560unsigned arm_pic_register = INVALID_REGNUM;
32de079a 561
ff9940b0 562/* Set to 1 when a return insn is output, this means that the epilogue
6354dc9b 563 is not needed. */
d5b7b3ae 564int return_used_this_function;
ff9940b0 565
aec3cfba
NC		 566/* Set to 1 after arm_reorg has started. Reset to start at the start of
567 the next function. */
4b632bf1
RE		 568static int after_arm_reorg = 0;
569
aec3cfba 570/* The maximum number of insns to be used when loading a constant. */
2b835d68
RE		 571static int arm_constant_limit = 3;
572
cce8749e
CH		 573/* For an explanation of these variables, see final_prescan_insn below. */
574int arm_ccfsm_state;
5b3e6663 575/* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
84ed5e79 576enum arm_cond_code arm_current_cc;
cce8749e
CH		 577rtx arm_target_insn;
578int arm_target_label;
5b3e6663
PB		 579/* The number of conditionally executed insns, including the current insn. */
580int arm_condexec_count = 0;
581/* A bitmask specifying the patterns for the IT block.
582 Zero means do not output an IT block before this insn. */
583int arm_condexec_mask = 0;
584/* The number of bits used in arm_condexec_mask. */
585int arm_condexec_masklen = 0;
9997d19d
RE		 586
587/* The condition codes of the ARM, and the inverse function. */
1d6e90ac 588static const char * const arm_condition_codes[] =
9997d19d
RE		 589{
590 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
591 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
592};
593
5b3e6663 594#define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
f5a1b0d2 595#define streq(string1, string2) (strcmp (string1, string2) == 0)
5b3e6663
PB		 596
597#define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
598 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
599 | (1 << PIC_OFFSET_TABLE_REGNUM)))
2b835d68 600\f
6354dc9b 601/* Initialization code. */
2b835d68 602
2b835d68
RE		 603struct processors
604{
8b60264b 605 const char *const name;
9b66ebb1 606 enum processor_type core;
78011587 607 const char *arch;
0977774b 608 const unsigned long flags;
9b66ebb1 609 bool (* rtx_costs) (rtx, int, int, int *);
2b835d68
RE		 610};
611
612/* Not all of these give usefully different compilation alternatives,
613 but there is no simple way of generalizing them. */
8b60264b 614static const struct processors all_cores[] =
f5a1b0d2
NC		 615{
616 /* ARM Cores */
d98a72fd
RE		 617#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
618 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
9b66ebb1
PB		 619#include "arm-cores.def"
620#undef ARM_CORE
78011587 621 {NULL, arm_none, NULL, 0, NULL}
f5a1b0d2
NC		 622};
623
8b60264b 624static const struct processors all_architectures[] =
2b835d68 625{
f5a1b0d2 626 /* ARM Architectures */
9b66ebb1
PB		 627 /* We don't specify rtx_costs here as it will be figured out
628 from the core. */
f676971a 629
78011587
PB		 630 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
631 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
632 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
633 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
634 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
b111229a
RE		 635 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
636 implementations that support it, so we will leave it out for now. */
78011587
PB		 637 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
638 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
639 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
640 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
641 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
642 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
643 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
fa91adc6
PB		 644 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
645 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
646 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
5b3e6663 647 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
bf98ec6c 648 {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL},
5b3e6663
PB		 649 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
650 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
651 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
652 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
78011587
PB		 653 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
654 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
655 {NULL, arm_none, NULL, 0 , NULL}
f5a1b0d2
NC		 656};
657
c54c7322
RS		 658struct arm_cpu_select
659{
660 const char * string;
661 const char * name;
662 const struct processors * processors;
663};
664
9a9f7594 665/* This is a magic structure. The 'string' field is magically filled in
f5a1b0d2
NC		 666 with a pointer to the value specified by the user on the command line
667 assuming that the user has specified such a value. */
668
c54c7322 669static struct arm_cpu_select arm_select[] =
f5a1b0d2 670{
f676971a 671 /* string name processors */
f5a1b0d2
NC		 672 { NULL, "-mcpu=", all_cores },
673 { NULL, "-march=", all_architectures },
674 { NULL, "-mtune=", all_cores }
2b835d68
RE		 675};
676
e6fffade
RE		 677/* Defines representing the indexes into the above table. */
678#define ARM_OPT_SET_CPU 0
679#define ARM_OPT_SET_ARCH 1
680#define ARM_OPT_SET_TUNE 2
78011587 681
afc0a4ba 682/* The name of the preprocessor macro to define for this architecture. */
78011587
PB		 683
684char arm_arch_name[] = "__ARM_ARCH_0UNK__";
685
9b66ebb1
PB		 686struct fpu_desc
687{
688 const char * name;
689 enum fputype fpu;
690};
691
692
56f42830 693/* Available values for -mfpu=. */
9b66ebb1
PB		 694
695static const struct fpu_desc all_fpus[] =
696{
697 {"fpa", FPUTYPE_FPA},
698 {"fpe2", FPUTYPE_FPA_EMU2},
699 {"fpe3", FPUTYPE_FPA_EMU2},
700 {"maverick", FPUTYPE_MAVERICK},
f1adb0a9
JB		 701 {"vfp", FPUTYPE_VFP},
702 {"vfp3", FPUTYPE_VFP3},
88f77cba 703 {"neon", FPUTYPE_NEON}
9b66ebb1
PB		 704};
705
706
707/* Floating point models used by the different hardware.
708 See fputype in arm.h. */
709
710static const enum fputype fp_model_for_fpu[] =
711{
712 /* No FP hardware. */
713 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
714 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
715 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
716 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
717 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
f1adb0a9 718 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */
88f77cba
JB		 719 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */
720 ARM_FP_MODEL_VFP /* FPUTYPE_NEON */
9b66ebb1
PB		 721};
722
723
724struct float_abi
725{
726 const char * name;
727 enum float_abi_type abi_type;
728};
729
730
731/* Available values for -mfloat-abi=. */
732
733static const struct float_abi all_float_abis[] =
734{
735 {"soft", ARM_FLOAT_ABI_SOFT},
736 {"softfp", ARM_FLOAT_ABI_SOFTFP},
737 {"hard", ARM_FLOAT_ABI_HARD}
738};
739
740
5848830f
PB		 741struct abi_name
742{
743 const char *name;
744 enum arm_abi_type abi_type;
745};
746
747
748/* Available values for -mabi=. */
749
750static const struct abi_name arm_all_abis[] =
751{
752 {"apcs-gnu", ARM_ABI_APCS},
753 {"atpcs", ARM_ABI_ATPCS},
754 {"aapcs", ARM_ABI_AAPCS},
077fc835
KH		 755 {"iwmmxt", ARM_ABI_IWMMXT},
756 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
5848830f
PB		 757};
758
d3585b76
DJ		 759/* Supported TLS relocations. */
760
761enum tls_reloc {
762 TLS_GD32,
763 TLS_LDM32,
764 TLS_LDO32,
765 TLS_IE32,
766 TLS_LE32
767};
768
d66437c5
RE		 769/* Emit an insn that's a simple single-set. Both the operands must be known
770 to be valid. */
771inline static rtx
772emit_set_insn (rtx x, rtx y)
773{
774 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
775}
776
0977774b
JT		 777/* Return the number of bits set in VALUE. */
778static unsigned
e32bac5b 779bit_count (unsigned long value)
aec3cfba 780{
d5b7b3ae 781 unsigned long count = 0;
f676971a 782
aec3cfba
NC		 783 while (value)
784 {
0977774b
JT		 785 count++;
786 value &= value - 1; /* Clear the least-significant set bit. */
aec3cfba
NC		 787 }
788
789 return count;
790}
791
c112cf2b 792/* Set up library functions unique to ARM. */
b3f8d95d
MM		 793
794static void
795arm_init_libfuncs (void)
796{
797 /* There are no special library functions unless we are using the
798 ARM BPABI. */
799 if (!TARGET_BPABI)
800 return;
801
802 /* The functions below are described in Section 4 of the "Run-Time
803 ABI for the ARM architecture", Version 1.0. */
804
805 /* Double-precision floating-point arithmetic. Table 2. */
806 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
807 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
808 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
809 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
810 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
811
c112cf2b 812 /* Double-precision comparisons. Table 3. */
b3f8d95d
MM		 813 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
814 set_optab_libfunc (ne_optab, DFmode, NULL);
815 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
816 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
817 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
818 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
819 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
820
821 /* Single-precision floating-point arithmetic. Table 4. */
822 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
823 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
824 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
825 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
826 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
f676971a 827
c112cf2b 828 /* Single-precision comparisons. Table 5. */
b3f8d95d
MM		 829 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
830 set_optab_libfunc (ne_optab, SFmode, NULL);
831 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
832 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
833 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
834 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
835 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
836
837 /* Floating-point to integer conversions. Table 6. */
838 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
839 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
840 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
841 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
842 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
843 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
844 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
845 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
846
847 /* Conversions between floating types. Table 7. */
848 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
849 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
850
c112cf2b 851 /* Integer to floating-point conversions. Table 8. */
b3f8d95d
MM		 852 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
853 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
854 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
855 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
856 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
857 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
858 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
859 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
860
861 /* Long long. Table 9. */
862 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
863 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
864 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
865 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
866 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
867 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
868 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
869 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
870
871 /* Integer (32/32->32) division. \S 4.3.1. */
872 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
873 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
874
875 /* The divmod functions are designed so that they can be used for
876 plain division, even though they return both the quotient and the
877 remainder. The quotient is returned in the usual location (i.e.,
878 r0 for SImode, {r0, r1} for DImode), just as would be expected
879 for an ordinary division routine. Because the AAPCS calling
880 conventions specify that all of { r0, r1, r2, r3 } are
881 callee-saved registers, there is no need to tell the compiler
882 explicitly that those registers are clobbered by these
883 routines. */
884 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
885 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
e993ba8f
DJ		 886
887 /* For SImode division the ABI provides div-without-mod routines,
888 which are faster. */
889 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
890 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
01c19d47
PB		 891
892 /* We don't have mod libcalls. Fortunately gcc knows how to use the
893 divmod libcalls instead. */
894 set_optab_libfunc (smod_optab, DImode, NULL);
895 set_optab_libfunc (umod_optab, DImode, NULL);
896 set_optab_libfunc (smod_optab, SImode, NULL);
897 set_optab_libfunc (umod_optab, SImode, NULL);
b3f8d95d
MM		 898}
899
c54c7322
RS		 900/* Implement TARGET_HANDLE_OPTION. */
901
902static bool
903arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
904{
905 switch (code)
906 {
c54c7322
RS		 907 case OPT_march_:
908 arm_select[1].string = arg;
909 return true;
910
911 case OPT_mcpu_:
912 arm_select[0].string = arg;
913 return true;
914
c54c7322
RS		 915 case OPT_mhard_float:
916 target_float_abi_name = "hard";
917 return true;
918
c54c7322
RS		 919 case OPT_msoft_float:
920 target_float_abi_name = "soft";
921 return true;
922
c54c7322
RS		 923 case OPT_mtune_:
924 arm_select[2].string = arg;
925 return true;
926
927 default:
928 return true;
929 }
930}
931
67e6ba46
NC		 932static void
933arm_target_help (void)
934{
935 int i;
936 static int columns = 0;
937 int remaining;
938
939 /* If we have not done so already, obtain the desired maximum width of
940 the output. Note - this is a duplication of the code at the start of
941 gcc/opts.c:print_specific_help() - the two copies should probably be
942 replaced by a single function. */
943 if (columns == 0)
944 {
945 const char *p;
946
947 GET_ENVIRONMENT (p, "COLUMNS");
948 if (p != NULL)
949 {
950 int value = atoi (p);
951
952 if (value > 0)
953 columns = value;
954 }
955
956 if (columns == 0)
957 /* Use a reasonable default. */
958 columns = 80;
959 }
960
961 printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n");
962
963 /* The - 2 is because we know that the last entry in the array is NULL. */
964 i = ARRAY_SIZE (all_cores) - 2;
965 gcc_assert (i > 0);
966 printf (" %s", all_cores[i].name);
967 remaining = columns - (strlen (all_cores[i].name) + 4);
968 gcc_assert (remaining >= 0);
969
970 while (i--)
971 {
972 int len = strlen (all_cores[i].name);
973
974 if (remaining > len + 2)
975 {
976 printf (", %s", all_cores[i].name);
977 remaining -= len + 2;
978 }
979 else
980 {
981 if (remaining > 0)
982 printf (",");
983 printf ("\n %s", all_cores[i].name);
984 remaining = columns - (len + 4);
985 }
986 }
987
988 printf ("\n\n Known ARM architectures (for use with the -march= option):\n");
989
990 i = ARRAY_SIZE (all_architectures) - 2;
991 gcc_assert (i > 0);
992
993 printf (" %s", all_architectures[i].name);
994 remaining = columns - (strlen (all_architectures[i].name) + 4);
995 gcc_assert (remaining >= 0);
996
997 while (i--)
998 {
999 int len = strlen (all_architectures[i].name);
1000
1001 if (remaining > len + 2)
1002 {
1003 printf (", %s", all_architectures[i].name);
1004 remaining -= len + 2;
1005 }
1006 else
1007 {
1008 if (remaining > 0)
1009 printf (",");
1010 printf ("\n %s", all_architectures[i].name);
1011 remaining = columns - (len + 4);
1012 }
1013 }
1014 printf ("\n");
1015
1016}
1017
2b835d68
RE		 1018/* Fix up any incompatible options that the user has specified.
1019 This has now turned into a maze. */
1020void
e32bac5b 1021arm_override_options (void)
2b835d68 1022{
ed4c4348 1023 unsigned i;
e6fffade 1024 enum processor_type target_arch_cpu = arm_none;
9b66ebb1 1025
f5a1b0d2 1026 /* Set up the flags based on the cpu/architecture selected by the user. */
b6a1cbae 1027 for (i = ARRAY_SIZE (arm_select); i--;)
bd9c7e23 1028 {
f5a1b0d2 1029 struct arm_cpu_select * ptr = arm_select + i;
f676971a 1030
f5a1b0d2 1031 if (ptr->string != NULL && ptr->string[0] != '\0')
bd9c7e23 1032 {
13bd191d 1033 const struct processors * sel;
bd9c7e23 1034
5895f793 1035 for (sel = ptr->processors; sel->name != NULL; sel++)
f5a1b0d2 1036 if (streq (ptr->string, sel->name))
bd9c7e23 1037 {
78011587 1038 /* Set the architecture define. */
e6fffade 1039 if (i != ARM_OPT_SET_TUNE)
78011587
PB		 1040 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1041
9b66ebb1
PB		 1042 /* Determine the processor core for which we should
1043 tune code-generation. */
1044 if (/* -mcpu= is a sensible default. */
e6fffade 1045 i == ARM_OPT_SET_CPU
9b66ebb1 1046 /* -mtune= overrides -mcpu= and -march=. */
e6fffade 1047 || i == ARM_OPT_SET_TUNE)
9b66ebb1
PB		 1048 arm_tune = (enum processor_type) (sel - ptr->processors);
1049
e6fffade
RE		 1050 /* Remember the CPU associated with this architecture.
1051 If no other option is used to set the CPU type,
1052 we'll use this to guess the most suitable tuning
1053 options. */
1054 if (i == ARM_OPT_SET_ARCH)
1055 target_arch_cpu = sel->core;
e0b92319 1056
e6fffade 1057 if (i != ARM_OPT_SET_TUNE)
b111229a 1058 {
aec3cfba
NC		 1059 /* If we have been given an architecture and a processor
1060 make sure that they are compatible. We only generate
1061 a warning though, and we prefer the CPU over the
6354dc9b 1062 architecture. */
aec3cfba 1063 if (insn_flags != 0 && (insn_flags ^ sel->flags))
d4ee4d25 1064 warning (0, "switch -mcpu=%s conflicts with -march= switch",
aec3cfba 1065 ptr->string);
f676971a 1066
aec3cfba 1067 insn_flags = sel->flags;
b111229a 1068 }
f676971a 1069
bd9c7e23
RE		 1070 break;
1071 }
1072
1073 if (sel->name == NULL)
1074 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1075 }
1076 }
f676971a 1077
e6fffade
RE		 1078 /* Guess the tuning options from the architecture if necessary. */
1079 if (arm_tune == arm_none)
1080 arm_tune = target_arch_cpu;
1081
f5a1b0d2 1082 /* If the user did not specify a processor, choose one for them. */
aec3cfba 1083 if (insn_flags == 0)
f5a1b0d2 1084 {
8b60264b 1085 const struct processors * sel;
aec3cfba 1086 unsigned int sought;
78011587 1087 enum processor_type cpu;
aec3cfba 1088
78011587
PB		 1089 cpu = TARGET_CPU_DEFAULT;
1090 if (cpu == arm_none)
1091 {
1092#ifdef SUBTARGET_CPU_DEFAULT
1093 /* Use the subtarget default CPU if none was specified by
1094 configure. */
1095 cpu = SUBTARGET_CPU_DEFAULT;
1096#endif
1097 /* Default to ARM6. */
1098 if (cpu == arm_none)
1099 cpu = arm6;
1100 }
1101 sel = &all_cores[cpu];
aec3cfba
NC		 1102
1103 insn_flags = sel->flags;
9b66ebb1 1104
aec3cfba
NC		 1105 /* Now check to see if the user has specified some command line
1106 switch that require certain abilities from the cpu. */
1107 sought = 0;
f676971a 1108
d5b7b3ae 1109 if (TARGET_INTERWORK || TARGET_THUMB)
f5a1b0d2 1110 {
aec3cfba 1111 sought |= (FL_THUMB | FL_MODE32);
f676971a 1112
d5b7b3ae 1113 /* There are no ARM processors that support both APCS-26 and
aec3cfba
NC		 1114 interworking. Therefore we force FL_MODE26 to be removed
1115 from insn_flags here (if it was set), so that the search
1116 below will always be able to find a compatible processor. */
5895f793 1117 insn_flags &= ~FL_MODE26;
f5a1b0d2 1118 }
f676971a 1119
aec3cfba 1120 if (sought != 0 && ((sought & insn_flags) != sought))
f5a1b0d2 1121 {
aec3cfba
NC		 1122 /* Try to locate a CPU type that supports all of the abilities
1123 of the default CPU, plus the extra abilities requested by
1124 the user. */
5895f793 1125 for (sel = all_cores; sel->name != NULL; sel++)
aec3cfba 1126 if ((sel->flags & sought) == (sought | insn_flags))
f5a1b0d2
NC		 1127 break;
1128
1129 if (sel->name == NULL)
aec3cfba 1130 {
0977774b 1131 unsigned current_bit_count = 0;
8b60264b 1132 const struct processors * best_fit = NULL;
f676971a 1133
aec3cfba
NC		 1134 /* Ideally we would like to issue an error message here
1135 saying that it was not possible to find a CPU compatible
1136 with the default CPU, but which also supports the command
1137 line options specified by the programmer, and so they
1138 ought to use the -mcpu=<name> command line option to
1139 override the default CPU type.
1140
61f0ccff
RE		 1141 If we cannot find a cpu that has both the
1142 characteristics of the default cpu and the given
1143 command line options we scan the array again looking
1144 for a best match. */
5895f793 1145 for (sel = all_cores; sel->name != NULL; sel++)
aec3cfba
NC		 1146 if ((sel->flags & sought) == sought)
1147 {
0977774b 1148 unsigned count;
aec3cfba
NC		 1149
1150 count = bit_count (sel->flags & insn_flags);
1151
1152 if (count >= current_bit_count)
1153 {
1154 best_fit = sel;
1155 current_bit_count = count;
1156 }
1157 }
f5a1b0d2 1158
e6d29d15
NS		 1159 gcc_assert (best_fit);
1160 sel = best_fit;
aec3cfba
NC		 1161 }
1162
1163 insn_flags = sel->flags;
f5a1b0d2 1164 }
78011587 1165 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
6c6aa1af 1166 arm_default_cpu = (enum processor_type) (sel - all_cores);
9b66ebb1 1167 if (arm_tune == arm_none)
6c6aa1af 1168 arm_tune = arm_default_cpu;
f5a1b0d2 1169 }
f676971a 1170
9b66ebb1
PB		 1171 /* The processor for which we should tune should now have been
1172 chosen. */
e6d29d15 1173 gcc_assert (arm_tune != arm_none);
f676971a 1174
9b66ebb1 1175 tune_flags = all_cores[(int)arm_tune].flags;
21b5653c
RE		 1176 if (optimize_size)
1177 targetm.rtx_costs = arm_size_rtx_costs;
1178 else
1179 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
e26053d1 1180
f5a1b0d2
NC		 1181 /* Make sure that the processor choice does not conflict with any of the
1182 other command line choices. */
5b3e6663
PB		 1183 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1184 error ("target CPU does not support ARM mode");
1185
6cfc7210 1186 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
f5a1b0d2 1187 {
d4ee4d25 1188 warning (0, "target CPU does not support interworking" );
c54c7322 1189 target_flags &= ~MASK_INTERWORK;
f5a1b0d2 1190 }
f676971a 1191
d5b7b3ae
RE		 1192 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1193 {
d4ee4d25 1194 warning (0, "target CPU does not support THUMB instructions");
c54c7322 1195 target_flags &= ~MASK_THUMB;
d5b7b3ae
RE		 1196 }
1197
1198 if (TARGET_APCS_FRAME && TARGET_THUMB)
1199 {
d4ee4d25 1200 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
c54c7322 1201 target_flags &= ~MASK_APCS_FRAME;
d5b7b3ae 1202 }
d19fb8e3 1203
da8ce8be
RE		 1204 /* Callee super interworking implies thumb interworking. Adding
1205 this to the flags here simplifies the logic elsewhere. */
1206 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1207 target_flags |= MASK_INTERWORK;
1208
d5b7b3ae
RE		 1209 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1210 from here where no function is being compiled currently. */
c54c7322 1211 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
d4ee4d25 1212 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
d5b7b3ae
RE		 1213
1214 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
d4ee4d25 1215 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
d5b7b3ae
RE		 1216
1217 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
d4ee4d25 1218 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
d5b7b3ae 1219
5895f793 1220 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
f5a1b0d2 1221 {
d4ee4d25 1222 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
c54c7322 1223 target_flags |= MASK_APCS_FRAME;
f5a1b0d2 1224 }
f676971a 1225
2b835d68 1226 if (TARGET_POKE_FUNCTION_NAME)
c54c7322 1227 target_flags |= MASK_APCS_FRAME;
f676971a 1228
2b835d68 1229 if (TARGET_APCS_REENT && flag_pic)
400500c4 1230 error ("-fpic and -mapcs-reent are incompatible");
f676971a 1231
2b835d68 1232 if (TARGET_APCS_REENT)
d4ee4d25 1233 warning (0, "APCS reentrant code not supported. Ignored");
f676971a 1234
d5b7b3ae
RE		 1235 /* If this target is normally configured to use APCS frames, warn if they
1236 are turned off and debugging is turned on. */
1237 if (TARGET_ARM
1238 && write_symbols != NO_DEBUG
5895f793 1239 && !TARGET_APCS_FRAME
c54c7322 1240 && (TARGET_DEFAULT & MASK_APCS_FRAME))
d4ee4d25 1241 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
f676971a 1242
2b835d68 1243 if (TARGET_APCS_FLOAT)
d4ee4d25 1244 warning (0, "passing floating point arguments in fp regs not yet supported");
f676971a 1245
4912a07c 1246 /* Initialize boolean versions of the flags, for use in the arm.md file. */
9b66ebb1
PB		 1247 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1248 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
68d560d4 1249 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
9b66ebb1
PB		 1250 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1251 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1252 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
d3585b76 1253 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
5b3e6663
PB		 1254 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1255 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
9b66ebb1 1256 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
78011587 1257 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
9b66ebb1
PB		 1258
1259 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
abac3b49 1260 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
9b66ebb1 1261 thumb_code = (TARGET_ARM == 0);
abac3b49 1262 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
9b66ebb1
PB		 1263 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1264 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
5b3e6663 1265 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
5a9335ef 1266
68d560d4
RE		 1267 /* V5 code we generate is completely interworking capable, so we turn off
1268 TARGET_INTERWORK here to avoid many tests later on. */
2ad4dcf9
RE		 1269
1270 /* XXX However, we must pass the right pre-processor defines to CPP
1271 or GLD can get confused. This is a hack. */
1272 if (TARGET_INTERWORK)
1273 arm_cpp_interwork = 1;
1274
68d560d4 1275 if (arm_arch5)
c54c7322 1276 target_flags &= ~MASK_INTERWORK;
68d560d4 1277
5848830f
PB		 1278 if (target_abi_name)
1279 {
1280 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1281 {
1282 if (streq (arm_all_abis[i].name, target_abi_name))
1283 {
1284 arm_abi = arm_all_abis[i].abi_type;
1285 break;
1286 }
1287 }
1288 if (i == ARRAY_SIZE (arm_all_abis))
1289 error ("invalid ABI option: -mabi=%s", target_abi_name);
1290 }
1291 else
c805f22e 1292 arm_abi = ARM_DEFAULT_ABI;
5848830f
PB		 1293
1294 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1295 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1296
1297 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1298 error ("iwmmxt abi requires an iwmmxt capable cpu");
6f7ebcbb 1299
9b66ebb1
PB		 1300 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1301 if (target_fpu_name == NULL && target_fpe_name != NULL)
9b6b54e2 1302 {
9b66ebb1
PB		 1303 if (streq (target_fpe_name, "2"))
1304 target_fpu_name = "fpe2";
1305 else if (streq (target_fpe_name, "3"))
1306 target_fpu_name = "fpe3";
1307 else
1308 error ("invalid floating point emulation option: -mfpe=%s",
1309 target_fpe_name);
1310 }
1311 if (target_fpu_name != NULL)
1312 {
1313 /* The user specified a FPU. */
1314 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1315 {
1316 if (streq (all_fpus[i].name, target_fpu_name))
1317 {
1318 arm_fpu_arch = all_fpus[i].fpu;
1319 arm_fpu_tune = arm_fpu_arch;
1320 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1321 break;
1322 }
1323 }
1324 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1325 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
9b6b54e2
NC		 1326 }
1327 else
2b835d68 1328 {
9b66ebb1 1329#ifdef FPUTYPE_DEFAULT
78011587 1330 /* Use the default if it is specified for this platform. */
9b66ebb1
PB		 1331 arm_fpu_arch = FPUTYPE_DEFAULT;
1332 arm_fpu_tune = FPUTYPE_DEFAULT;
1333#else
1334 /* Pick one based on CPU type. */
78011587 1335 /* ??? Some targets assume FPA is the default.
9b66ebb1
PB		 1336 if ((insn_flags & FL_VFP) != 0)
1337 arm_fpu_arch = FPUTYPE_VFP;
78011587
PB		 1338 else
1339 */
1340 if (arm_arch_cirrus)
9b66ebb1
PB		 1341 arm_fpu_arch = FPUTYPE_MAVERICK;
1342 else
29ad9694 1343 arm_fpu_arch = FPUTYPE_FPA_EMU2;
9b66ebb1
PB		 1344#endif
1345 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1346 arm_fpu_tune = FPUTYPE_FPA;
2b835d68 1347 else
9b66ebb1
PB		 1348 arm_fpu_tune = arm_fpu_arch;
1349 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
e6d29d15 1350 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
9b66ebb1
PB		 1351 }
1352
1353 if (target_float_abi_name != NULL)
1354 {
1355 /* The user specified a FP ABI. */
1356 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1357 {
1358 if (streq (all_float_abis[i].name, target_float_abi_name))
1359 {
1360 arm_float_abi = all_float_abis[i].abi_type;
1361 break;
1362 }
1363 }
1364 if (i == ARRAY_SIZE (all_float_abis))
1365 error ("invalid floating point abi: -mfloat-abi=%s",
1366 target_float_abi_name);
2b835d68 1367 }
3d8532aa
PB		 1368 else
1369 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
9b66ebb1 1370
72cdc543
PB		 1371 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1372 sorry ("-mfloat-abi=hard and VFP");
1373
87b24aaf
PB		 1374 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1375 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1376 will ever exist. GCC makes no attempt to support this combination. */
1377 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1378 sorry ("iWMMXt and hardware floating point");
1379
5b3e6663
PB		 1380 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1381 if (TARGET_THUMB2 && TARGET_IWMMXT)
1382 sorry ("Thumb-2 iWMMXt");
1383
9b66ebb1
PB		 1384 /* If soft-float is specified then don't use FPU. */
1385 if (TARGET_SOFT_FLOAT)
1386 arm_fpu_arch = FPUTYPE_NONE;
f676971a 1387
f5a1b0d2
NC		 1388 /* For arm2/3 there is no need to do any scheduling if there is only
1389 a floating point emulator, or we are doing software floating-point. */
9b66ebb1
PB		 1390 if ((TARGET_SOFT_FLOAT
1391 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1392 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
ed0e6530 1393 && (tune_flags & FL_MODE32) == 0)
f5a1b0d2 1394 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
f676971a 1395
d3585b76
DJ		 1396 if (target_thread_switch)
1397 {
1398 if (strcmp (target_thread_switch, "soft") == 0)
1399 target_thread_pointer = TP_SOFT;
1400 else if (strcmp (target_thread_switch, "auto") == 0)
1401 target_thread_pointer = TP_AUTO;
1402 else if (strcmp (target_thread_switch, "cp15") == 0)
1403 target_thread_pointer = TP_CP15;
1404 else
1405 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1406 }
1407
1408 /* Use the cp15 method if it is available. */
1409 if (target_thread_pointer == TP_AUTO)
1410 {
1411 if (arm_arch6k && !TARGET_THUMB)
1412 target_thread_pointer = TP_CP15;
1413 else
1414 target_thread_pointer = TP_SOFT;
1415 }
1416
5b3e6663
PB		 1417 if (TARGET_HARD_TP && TARGET_THUMB1)
1418 error ("can not use -mtp=cp15 with 16-bit Thumb");
d3585b76 1419
5848830f 1420 /* Override the default structure alignment for AAPCS ABI. */
077fc835 1421 if (TARGET_AAPCS_BASED)
5848830f
PB		 1422 arm_structure_size_boundary = 8;
1423
b355a481
NC		 1424 if (structure_size_string != NULL)
1425 {
1426 int size = strtol (structure_size_string, NULL, 0);
5848830f
PB		 1427
1428 if (size == 8 || size == 32
1429 || (ARM_DOUBLEWORD_ALIGN && size == 64))
b355a481
NC		 1430 arm_structure_size_boundary = size;
1431 else
d4ee4d25 1432 warning (0, "structure size boundary can only be set to %s",
5848830f 1433 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
b355a481 1434 }
ed0e6530 1435
9403b7f7
RS		 1436 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1437 {
1438 error ("RTP PIC is incompatible with Thumb");
1439 flag_pic = 0;
1440 }
1441
c147eacb
PB		 1442 /* If stack checking is disabled, we can use r10 as the PIC register,
1443 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1444 if (flag_pic && TARGET_SINGLE_PIC_BASE)
9403b7f7
RS		 1445 {
1446 if (TARGET_VXWORKS_RTP)
1447 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1448 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1449 }
1450
1451 if (flag_pic && TARGET_VXWORKS_RTP)
1452 arm_pic_register = 9;
c147eacb 1453
ed0e6530
PB		 1454 if (arm_pic_register_string != NULL)
1455 {
5b43fed1 1456 int pic_register = decode_reg_name (arm_pic_register_string);
e26053d1 1457
5895f793 1458 if (!flag_pic)
d4ee4d25 1459 warning (0, "-mpic-register= is useless without -fpic");
ed0e6530 1460
ed0e6530 1461 /* Prevent the user from choosing an obviously stupid PIC register. */
5b43fed1
RH		 1462 else if (pic_register < 0 || call_used_regs[pic_register]
1463 || pic_register == HARD_FRAME_POINTER_REGNUM
1464 || pic_register == STACK_POINTER_REGNUM
9403b7f7
RS		 1465 || pic_register >= PC_REGNUM
1466 || (TARGET_VXWORKS_RTP
1467 && (unsigned int) pic_register != arm_pic_register))
c725bd79 1468 error ("unable to use '%s' for PIC register", arm_pic_register_string);
ed0e6530
PB		 1469 else
1470 arm_pic_register = pic_register;
1471 }
d5b7b3ae 1472
5b3e6663 1473 /* ??? We might want scheduling for thumb2. */
d5b7b3ae
RE		 1474 if (TARGET_THUMB && flag_schedule_insns)
1475 {
1476 /* Don't warn since it's on by default in -O2. */
1477 flag_schedule_insns = 0;
1478 }
1479
f5a1b0d2 1480 if (optimize_size)
be03ccc9 1481 {
577d6328 1482 arm_constant_limit = 1;
be03ccc9
NP		 1483
1484 /* If optimizing for size, bump the number of instructions that we
d6b4baa4 1485 are prepared to conditionally execute (even on a StrongARM). */
be03ccc9
NP		 1486 max_insns_skipped = 6;
1487 }
1488 else
1489 {
1490 /* For processors with load scheduling, it never costs more than
1491 2 cycles to load a constant, and the load scheduler may well
1492 reduce that to 1. */
2075b05d 1493 if (arm_ld_sched)
be03ccc9
NP		 1494 arm_constant_limit = 1;
1495
1496 /* On XScale the longer latency of a load makes it more difficult
1497 to achieve a good schedule, so it's faster to synthesize
d6b4baa4 1498 constants that can be done in two insns. */
be03ccc9
NP		 1499 if (arm_tune_xscale)
1500 arm_constant_limit = 2;
1501
1502 /* StrongARM has early execution of branches, so a sequence
1503 that is worth skipping is shorter. */
abac3b49 1504 if (arm_tune_strongarm)
be03ccc9
NP		 1505 max_insns_skipped = 3;
1506 }
92a432f4
RE		 1507
1508 /* Register global variables with the garbage collector. */
1509 arm_add_gc_roots ();
1510}
1511
1512static void
e32bac5b 1513arm_add_gc_roots (void)
92a432f4 1514{
c7319d87
RE		 1515 gcc_obstack_init(&minipool_obstack);
1516 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
2b835d68 1517}
cce8749e 1518\f
6d3d9133
NC		 1519/* A table of known ARM exception types.
1520 For use with the interrupt function attribute. */
1521
1522typedef struct
1523{
8b60264b
KG		 1524 const char *const arg;
1525 const unsigned long return_value;
6d3d9133
NC		 1526}
1527isr_attribute_arg;
1528
8b60264b 1529static const isr_attribute_arg isr_attribute_args [] =
6d3d9133
NC		 1530{
1531 { "IRQ", ARM_FT_ISR },
1532 { "irq", ARM_FT_ISR },
1533 { "FIQ", ARM_FT_FIQ },
1534 { "fiq", ARM_FT_FIQ },
1535 { "ABORT", ARM_FT_ISR },
1536 { "abort", ARM_FT_ISR },
1537 { "ABORT", ARM_FT_ISR },
1538 { "abort", ARM_FT_ISR },
1539 { "UNDEF", ARM_FT_EXCEPTION },
1540 { "undef", ARM_FT_EXCEPTION },
1541 { "SWI", ARM_FT_EXCEPTION },
1542 { "swi", ARM_FT_EXCEPTION },
1543 { NULL, ARM_FT_NORMAL }
1544};
1545
1546/* Returns the (interrupt) function type of the current
1547 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1548
1549static unsigned long
e32bac5b 1550arm_isr_value (tree argument)
6d3d9133 1551{
8b60264b 1552 const isr_attribute_arg * ptr;
1d6e90ac 1553 const char * arg;
6d3d9133 1554
5b3e6663
PB		 1555 if (!arm_arch_notm)
1556 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1557
6d3d9133
NC		 1558 /* No argument - default to IRQ. */
1559 if (argument == NULL_TREE)
1560 return ARM_FT_ISR;
1561
1562 /* Get the value of the argument. */
1563 if (TREE_VALUE (argument) == NULL_TREE
1564 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1565 return ARM_FT_UNKNOWN;
1566
1567 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1568
1569 /* Check it against the list of known arguments. */
5a9335ef 1570 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1d6e90ac
NC		 1571 if (streq (arg, ptr->arg))
1572 return ptr->return_value;
6d3d9133 1573
05713b80 1574 /* An unrecognized interrupt type. */
6d3d9133
NC		 1575 return ARM_FT_UNKNOWN;
1576}
1577
1578/* Computes the type of the current function. */
1579
1580static unsigned long
e32bac5b 1581arm_compute_func_type (void)
6d3d9133
NC		 1582{
1583 unsigned long type = ARM_FT_UNKNOWN;
1584 tree a;
1585 tree attr;
f676971a 1586
e6d29d15 1587 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
6d3d9133
NC		 1588
1589 /* Decide if the current function is volatile. Such functions
1590 never return, and many memory cycles can be saved by not storing
1591 register values that will never be needed again. This optimization
1592 was added to speed up context switching in a kernel application. */
1593 if (optimize > 0
cf1955dc
PB		 1594 && (TREE_NOTHROW (current_function_decl)
1595 || !(flag_unwind_tables
1596 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
6d3d9133
NC		 1597 && TREE_THIS_VOLATILE (current_function_decl))
1598 type |= ARM_FT_VOLATILE;
f676971a 1599
6de9cd9a 1600 if (cfun->static_chain_decl != NULL)
6d3d9133
NC		 1601 type |= ARM_FT_NESTED;
1602
91d231cb 1603 attr = DECL_ATTRIBUTES (current_function_decl);
f676971a 1604
6d3d9133
NC		 1605 a = lookup_attribute ("naked", attr);
1606 if (a != NULL_TREE)
1607 type |= ARM_FT_NAKED;
1608
c9ca9b88
PB		 1609 a = lookup_attribute ("isr", attr);
1610 if (a == NULL_TREE)
1611 a = lookup_attribute ("interrupt", attr);
f676971a 1612
c9ca9b88
PB		 1613 if (a == NULL_TREE)
1614 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
6d3d9133 1615 else
c9ca9b88 1616 type |= arm_isr_value (TREE_VALUE (a));
f676971a 1617
6d3d9133
NC		 1618 return type;
1619}
1620
1621/* Returns the type of the current function. */
1622
1623unsigned long
e32bac5b 1624arm_current_func_type (void)
6d3d9133
NC		 1625{
1626 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1627 cfun->machine->func_type = arm_compute_func_type ();
1628
1629 return cfun->machine->func_type;
1630}
007e61c2
PB		 1631
1632bool
1633arm_allocate_stack_slots_for_args (void)
1634{
1635 /* Naked functions should not allocate stack slots for arguments. */
1636 return !IS_NAKED (arm_current_func_type ());
1637}
1638
6d3d9133 1639\f
f676971a 1640/* Return 1 if it is possible to return using a single instruction.
a72d4945
RE		 1641 If SIBLING is non-null, this is a test for a return before a sibling
1642 call. SIBLING is the call insn, so we can examine its register usage. */
6d3d9133 1643
ff9940b0 1644int
a72d4945 1645use_return_insn (int iscond, rtx sibling)
ff9940b0
RE		 1646{
1647 int regno;
9b598fa0 1648 unsigned int func_type;
d5db54a1 1649 unsigned long saved_int_regs;
a72d4945 1650 unsigned HOST_WIDE_INT stack_adjust;
5848830f 1651 arm_stack_offsets *offsets;
ff9940b0 1652
d5b7b3ae 1653 /* Never use a return instruction before reload has run. */
6d3d9133
NC		 1654 if (!reload_completed)
1655 return 0;
efc2515b 1656
9b598fa0
RE		 1657 func_type = arm_current_func_type ();
1658
5b3e6663 1659 /* Naked, volatile and stack alignment functions need special
3a7731fd 1660 consideration. */
5b3e6663 1661 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
6d3d9133 1662 return 0;
06bea5aa 1663
a15908a4
PB		 1664 /* So do interrupt functions that use the frame pointer and Thumb
1665 interrupt functions. */
1666 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
06bea5aa 1667 return 0;
a72d4945 1668
5848830f
PB		 1669 offsets = arm_get_frame_offsets ();
1670 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
a72d4945 1671
6d3d9133 1672 /* As do variadic functions. */
38173d38 1673 if (crtl->args.pretend_args_size
3cb66fd7 1674 || cfun->machine->uses_anonymous_args
699a4925 1675 /* Or if the function calls __builtin_eh_return () */
e3b5732b 1676 || crtl->calls_eh_return
699a4925 1677 /* Or if the function calls alloca */
e3b5732b 1678 || cfun->calls_alloca
a72d4945
RE		 1679 /* Or if there is a stack adjustment. However, if the stack pointer
1680 is saved on the stack, we can use a pre-incrementing stack load. */
ec6237e4
PB		 1681 || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed
1682 && stack_adjust == 4)))
ff9940b0
RE		 1683 return 0;
1684
954954d1 1685 saved_int_regs = offsets->saved_regs_mask;
d5db54a1 1686
a72d4945
RE		 1687 /* Unfortunately, the insn
1688
1689 ldmib sp, {..., sp, ...}
1690
1691 triggers a bug on most SA-110 based devices, such that the stack
1692 pointer won't be correctly restored if the instruction takes a
839a4992 1693 page fault. We work around this problem by popping r3 along with
a72d4945 1694 the other registers, since that is never slower than executing
f676971a 1695 another instruction.
a72d4945
RE		 1696
1697 We test for !arm_arch5 here, because code for any architecture
1698 less than this could potentially be run on one of the buggy
1699 chips. */
5b3e6663 1700 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
a72d4945
RE		 1701 {
1702 /* Validate that r3 is a call-clobbered register (always true in
d6b4baa4 1703 the default abi) ... */
a72d4945
RE		 1704 if (!call_used_regs[3])
1705 return 0;
1706
4f5dfed0
JC		 1707 /* ... that it isn't being used for a return value ... */
1708 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1709 return 0;
1710
1711 /* ... or for a tail-call argument ... */
a72d4945
RE		 1712 if (sibling)
1713 {
e6d29d15 1714 gcc_assert (GET_CODE (sibling) == CALL_INSN);
a72d4945
RE		 1715
1716 if (find_regno_fusage (sibling, USE, 3))
1717 return 0;
1718 }
1719
1720 /* ... and that there are no call-saved registers in r0-r2
1721 (always true in the default ABI). */
1722 if (saved_int_regs & 0x7)
1723 return 0;
1724 }
1725
b111229a 1726 /* Can't be done if interworking with Thumb, and any registers have been
d5db54a1 1727 stacked. */
a15908a4 1728 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
b36ba79f 1729 return 0;
d5db54a1
RE		 1730
1731 /* On StrongARM, conditional returns are expensive if they aren't
1732 taken and multiple registers have been stacked. */
abac3b49 1733 if (iscond && arm_tune_strongarm)
6ed30148 1734 {
f676971a 1735 /* Conditional return when just the LR is stored is a simple
d5db54a1
RE		 1736 conditional-load instruction, that's not expensive. */
1737 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1738 return 0;
6ed30148 1739
020a4035
RE		 1740 if (flag_pic
1741 && arm_pic_register != INVALID_REGNUM
6fb5fa3c 1742 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
b111229a 1743 return 0;
6ed30148 1744 }
d5db54a1
RE		 1745
1746 /* If there are saved registers but the LR isn't saved, then we need
1747 two instructions for the return. */
1748 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1749 return 0;
1750
3b684012 1751 /* Can't be done if any of the FPA regs are pushed,
6d3d9133 1752 since this also requires an insn. */
9b66ebb1
PB		 1753 if (TARGET_HARD_FLOAT && TARGET_FPA)
1754 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
6fb5fa3c 1755 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
9b66ebb1
PB		 1756 return 0;
1757
1758 /* Likewise VFP regs. */
1759 if (TARGET_HARD_FLOAT && TARGET_VFP)
1760 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
6fb5fa3c 1761 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
d5b7b3ae 1762 return 0;
ff9940b0 1763
5a9335ef
NC		 1764 if (TARGET_REALLY_IWMMXT)
1765 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
6fb5fa3c 1766 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
5a9335ef
NC		 1767 return 0;
1768
ff9940b0
RE		 1769 return 1;
1770}
1771
cce8749e
CH		 1772/* Return TRUE if int I is a valid immediate ARM constant. */
1773
1774int
e32bac5b 1775const_ok_for_arm (HOST_WIDE_INT i)
cce8749e 1776{
4642ccb1 1777 int lowbit;
e0b92319 1778
f676971a 1779 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
56636818 1780 be all zero, or all one. */
30cf4896
KG		 1781 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1782 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1783 != ((~(unsigned HOST_WIDE_INT) 0)
1784 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
56636818 1785 return FALSE;
f676971a 1786
4642ccb1 1787 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
e0b92319 1788
4642ccb1
RE		 1789 /* Fast return for 0 and small values. We must do this for zero, since
1790 the code below can't handle that one case. */
1791 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
e2c671ba
RE		 1792 return TRUE;
1793
5b3e6663
PB		 1794 /* Get the number of trailing zeros. */
1795 lowbit = ffs((int) i) - 1;
1796
1797 /* Only even shifts are allowed in ARM mode so round down to the
1798 nearest even number. */
1799 if (TARGET_ARM)
1800 lowbit &= ~1;
4642ccb1
RE		 1801
1802 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1803 return TRUE;
5b3e6663
PB		 1804
1805 if (TARGET_ARM)
1806 {
1807 /* Allow rotated constants in ARM mode. */
1808 if (lowbit <= 4
4642ccb1
RE		 1809 && ((i & ~0xc000003f) == 0
1810 || (i & ~0xf000000f) == 0
1811 || (i & ~0xfc000003) == 0))
5b3e6663
PB		 1812 return TRUE;
1813 }
1814 else
1815 {
1816 HOST_WIDE_INT v;
1817
1818 /* Allow repeated pattern. */
1819 v = i & 0xff;
1820 v |= v << 16;
1821 if (i == v || i == (v | (v << 8)))
1822 return TRUE;
1823 }
cce8749e 1824
f3bb6135
RE		 1825 return FALSE;
1826}
cce8749e 1827
6354dc9b 1828/* Return true if I is a valid constant for the operation CODE. */
74bbc178 1829static int
e32bac5b 1830const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
e2c671ba
RE		 1831{
1832 if (const_ok_for_arm (i))
1833 return 1;
1834
1835 switch (code)
1836 {
1837 case PLUS:
1838 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1839
1840 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1841 case XOR:
1842 case IOR:
1843 return 0;
1844
1845 case AND:
1846 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1847
1848 default:
e6d29d15 1849 gcc_unreachable ();
e2c671ba
RE		 1850 }
1851}
1852
1853/* Emit a sequence of insns to handle a large constant.
1854 CODE is the code of the operation required, it can be any of SET, PLUS,
1855 IOR, AND, XOR, MINUS;
1856 MODE is the mode in which the operation is being performed;
1857 VAL is the integer to operate on;
1858 SOURCE is the other operand (a register, or a null-pointer for SET);
1859 SUBTARGETS means it is safe to create scratch registers if that will
2b835d68
RE		 1860 either produce a simpler sequence, or we will want to cse the values.
1861 Return value is the number of insns emitted. */
e2c671ba 1862
5b3e6663 1863/* ??? Tweak this for thumb2. */
e2c671ba 1864int
a406f566 1865arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
e32bac5b 1866 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
2b835d68 1867{
a406f566
MM		 1868 rtx cond;
1869
1870 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1871 cond = COND_EXEC_TEST (PATTERN (insn));
1872 else
1873 cond = NULL_RTX;
1874
2b835d68
RE		 1875 if (subtargets || code == SET
1876 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1877 && REGNO (target) != REGNO (source)))
1878 {
4b632bf1 1879 /* After arm_reorg has been called, we can't fix up expensive
05713b80 1880 constants by pushing them into memory so we must synthesize
4b632bf1
RE		 1881 them in-line, regardless of the cost. This is only likely to
1882 be more costly on chips that have load delay slots and we are
1883 compiling without running the scheduler (so no splitting
aec3cfba
NC		 1884 occurred before the final instruction emission).
1885
1886 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
aec3cfba 1887 */
5895f793 1888 if (!after_arm_reorg
a406f566 1889 && !cond
f676971a 1890 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
a406f566 1891 1, 0)
4b632bf1 1892 > arm_constant_limit + (code != SET)))
2b835d68
RE		 1893 {
1894 if (code == SET)
1895 {
1896 /* Currently SET is the only monadic value for CODE, all
1897 the rest are diadic. */
d66437c5 1898 emit_set_insn (target, GEN_INT (val));
2b835d68
RE		 1899 return 1;
1900 }
1901 else
1902 {
1903 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1904
d66437c5 1905 emit_set_insn (temp, GEN_INT (val));
2b835d68
RE		 1906 /* For MINUS, the value is subtracted from, since we never
1907 have subtraction of a constant. */
1908 if (code == MINUS)
d66437c5 1909 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
2b835d68 1910 else
d66437c5
RE		 1911 emit_set_insn (target,
1912 gen_rtx_fmt_ee (code, mode, source, temp));
2b835d68
RE		 1913 return 2;
1914 }
1915 }
1916 }
1917
f676971a 1918 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
a406f566 1919 1);
2b835d68
RE		 1920}
1921
5b3e6663
PB		 1922/* Return the number of ARM instructions required to synthesize the given
1923 constant. */
ceebdb09 1924static int
e32bac5b 1925count_insns_for_constant (HOST_WIDE_INT remainder, int i)
ceebdb09
PB		 1926{
1927 HOST_WIDE_INT temp1;
1928 int num_insns = 0;
1929 do
1930 {
1931 int end;
f676971a 1932
ceebdb09
PB		 1933 if (i <= 0)
1934 i += 32;
1935 if (remainder & (3 << (i - 2)))
1936 {
1937 end = i - 8;
1938 if (end < 0)
1939 end += 32;
1940 temp1 = remainder & ((0x0ff << end)
1941 | ((i < end) ? (0xff >> (32 - end)) : 0));
1942 remainder &= ~temp1;
1943 num_insns++;
1944 i -= 6;
1945 }
1946 i -= 2;
1947 } while (remainder);
1948 return num_insns;
1949}
1950
a406f566
MM		 1951/* Emit an instruction with the indicated PATTERN. If COND is
1952 non-NULL, conditionalize the execution of the instruction on COND
1953 being true. */
1954
1955static void
1956emit_constant_insn (rtx cond, rtx pattern)
1957{
1958 if (cond)
1959 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1960 emit_insn (pattern);
1961}
1962
2b835d68
RE		 1963/* As above, but extra parameter GENERATE which, if clear, suppresses
1964 RTL generation. */
5b3e6663 1965/* ??? This needs more work for thumb2. */
1d6e90ac 1966
d5b7b3ae 1967static int
a406f566 1968arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
e32bac5b
RE		 1969 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1970 int generate)
e2c671ba 1971{
e2c671ba
RE		 1972 int can_invert = 0;
1973 int can_negate = 0;
1974 int can_negate_initial = 0;
1975 int can_shift = 0;
1976 int i;
1977 int num_bits_set = 0;
1978 int set_sign_bit_copies = 0;
1979 int clear_sign_bit_copies = 0;
1980 int clear_zero_bit_copies = 0;
1981 int set_zero_bit_copies = 0;
1982 int insns = 0;
e2c671ba 1983 unsigned HOST_WIDE_INT temp1, temp2;
30cf4896 1984 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
e2c671ba 1985
d5b7b3ae 1986 /* Find out which operations are safe for a given CODE. Also do a quick
e2c671ba
RE		 1987 check for degenerate cases; these can occur when DImode operations
1988 are split. */
1989 switch (code)
1990 {
1991 case SET:
1992 can_invert = 1;
1993 can_shift = 1;
1994 can_negate = 1;
1995 break;
1996
1997 case PLUS:
1998 can_negate = 1;
1999 can_negate_initial = 1;
2000 break;
2001
2002 case IOR:
30cf4896 2003 if (remainder == 0xffffffff)
e2c671ba 2004 {
2b835d68 2005 if (generate)
a406f566
MM		 2006 emit_constant_insn (cond,
2007 gen_rtx_SET (VOIDmode, target,
2008 GEN_INT (ARM_SIGN_EXTEND (val))));
e2c671ba
RE		 2009 return 1;
2010 }
2011 if (remainder == 0)
2012 {
2013 if (reload_completed && rtx_equal_p (target, source))
2014 return 0;
2b835d68 2015 if (generate)
a406f566
MM		 2016 emit_constant_insn (cond,
2017 gen_rtx_SET (VOIDmode, target, source));
e2c671ba
RE		 2018 return 1;
2019 }
2020 break;
2021
2022 case AND:
2023 if (remainder == 0)
2024 {
2b835d68 2025 if (generate)
a406f566
MM		 2026 emit_constant_insn (cond,
2027 gen_rtx_SET (VOIDmode, target, const0_rtx));
e2c671ba
RE		 2028 return 1;
2029 }
30cf4896 2030 if (remainder == 0xffffffff)
e2c671ba
RE		 2031 {
2032 if (reload_completed && rtx_equal_p (target, source))
2033 return 0;
2b835d68 2034 if (generate)
a406f566
MM		 2035 emit_constant_insn (cond,
2036 gen_rtx_SET (VOIDmode, target, source));
e2c671ba
RE		 2037 return 1;
2038 }
2039 can_invert = 1;
2040 break;
2041
2042 case XOR:
2043 if (remainder == 0)
2044 {
2045 if (reload_completed && rtx_equal_p (target, source))
2046 return 0;
2b835d68 2047 if (generate)
a406f566
MM		 2048 emit_constant_insn (cond,
2049 gen_rtx_SET (VOIDmode, target, source));
e2c671ba
RE		 2050 return 1;
2051 }
e0b92319 2052
e6d29d15
NS		 2053 /* We don't know how to handle other cases yet. */
2054 gcc_assert (remainder == 0xffffffff);
e0b92319 2055
e6d29d15
NS		 2056 if (generate)
2057 emit_constant_insn (cond,
2058 gen_rtx_SET (VOIDmode, target,
2059 gen_rtx_NOT (mode, source)));
2060 return 1;
e2c671ba
RE		 2061
2062 case MINUS:
2063 /* We treat MINUS as (val - source), since (source - val) is always
2064 passed as (source + (-val)). */
2065 if (remainder == 0)
2066 {
2b835d68 2067 if (generate)
a406f566
MM		 2068 emit_constant_insn (cond,
2069 gen_rtx_SET (VOIDmode, target,
2070 gen_rtx_NEG (mode, source)));
e2c671ba
RE		 2071 return 1;
2072 }
2073 if (const_ok_for_arm (val))
2074 {
2b835d68 2075 if (generate)
a406f566 2076 emit_constant_insn (cond,
f676971a 2077 gen_rtx_SET (VOIDmode, target,
a406f566
MM		 2078 gen_rtx_MINUS (mode, GEN_INT (val),
2079 source)));
e2c671ba
RE		 2080 return 1;
2081 }
2082 can_negate = 1;
2083
2084 break;
2085
2086 default:
e6d29d15 2087 gcc_unreachable ();
e2c671ba
RE		 2088 }
2089
6354dc9b 2090 /* If we can do it in one insn get out quickly. */
e2c671ba
RE		 2091 if (const_ok_for_arm (val)
2092 || (can_negate_initial && const_ok_for_arm (-val))
2093 || (can_invert && const_ok_for_arm (~val)))
2094 {
2b835d68 2095 if (generate)
a406f566
MM		 2096 emit_constant_insn (cond,
2097 gen_rtx_SET (VOIDmode, target,
f676971a 2098 (source
a406f566
MM		 2099 ? gen_rtx_fmt_ee (code, mode, source,
2100 GEN_INT (val))
2101 : GEN_INT (val))));
e2c671ba
RE		 2102 return 1;
2103 }
2104
e2c671ba 2105 /* Calculate a few attributes that may be useful for specific
6354dc9b 2106 optimizations. */
e2c671ba
RE		 2107 for (i = 31; i >= 0; i--)
2108 {
2109 if ((remainder & (1 << i)) == 0)
2110 clear_sign_bit_copies++;
2111 else
2112 break;
2113 }
2114
2115 for (i = 31; i >= 0; i--)
2116 {
2117 if ((remainder & (1 << i)) != 0)
2118 set_sign_bit_copies++;
2119 else
2120 break;
2121 }
2122
2123 for (i = 0; i <= 31; i++)
2124 {
2125 if ((remainder & (1 << i)) == 0)
2126 clear_zero_bit_copies++;
2127 else
2128 break;
2129 }
2130
2131 for (i = 0; i <= 31; i++)
2132 {
2133 if ((remainder & (1 << i)) != 0)
2134 set_zero_bit_copies++;
2135 else
2136 break;
2137 }
2138
2139 switch (code)
2140 {
2141 case SET:
5b3e6663
PB		 2142 /* See if we can use movw. */
2143 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2144 {
2145 if (generate)
2146 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2147 GEN_INT (val)));
2148 return 1;
2149 }
2150
e2c671ba
RE		 2151 /* See if we can do this by sign_extending a constant that is known
2152 to be negative. This is a good, way of doing it, since the shift
2153 may well merge into a subsequent insn. */
2154 if (set_sign_bit_copies > 1)
2155 {
2156 if (const_ok_for_arm
f676971a 2157 (temp1 = ARM_SIGN_EXTEND (remainder
e2c671ba
RE		 2158 << (set_sign_bit_copies - 1))))
2159 {
2b835d68
RE		 2160 if (generate)
2161 {
d499463f 2162 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
a406f566 2163 emit_constant_insn (cond,
f676971a 2164 gen_rtx_SET (VOIDmode, new_src,
a406f566
MM		 2165 GEN_INT (temp1)));
2166 emit_constant_insn (cond,
f676971a 2167 gen_ashrsi3 (target, new_src,
a406f566 2168 GEN_INT (set_sign_bit_copies - 1)));
2b835d68 2169 }
e2c671ba
RE		 2170 return 2;
2171 }
2172 /* For an inverted constant, we will need to set the low bits,
2173 these will be shifted out of harm's way. */
2174 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2175 if (const_ok_for_arm (~temp1))
2176 {
2b835d68
RE		 2177 if (generate)
2178 {
d499463f 2179 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
a406f566
MM		 2180 emit_constant_insn (cond,
2181 gen_rtx_SET (VOIDmode, new_src,
2182 GEN_INT (temp1)));
2183 emit_constant_insn (cond,
f676971a 2184 gen_ashrsi3 (target, new_src,
a406f566 2185 GEN_INT (set_sign_bit_copies - 1)));
2b835d68 2186 }
e2c671ba
RE		 2187 return 2;
2188 }
2189 }
2190
c87e6352
RE		 2191 /* See if we can calculate the value as the difference between two
2192 valid immediates. */
2193 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2194 {
2195 int topshift = clear_sign_bit_copies & ~1;
2196
fa2c88a0
RE		 2197 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2198 & (0xff000000 >> topshift));
c87e6352
RE		 2199
2200 /* If temp1 is zero, then that means the 9 most significant
2201 bits of remainder were 1 and we've caused it to overflow.
2202 When topshift is 0 we don't need to do anything since we
2203 can borrow from 'bit 32'. */
2204 if (temp1 == 0 && topshift != 0)
2205 temp1 = 0x80000000 >> (topshift - 1);
2206
fa2c88a0 2207 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
e0b92319 2208
c87e6352
RE		 2209 if (const_ok_for_arm (temp2))
2210 {
2211 if (generate)
2212 {
2213 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2214 emit_constant_insn (cond,
2215 gen_rtx_SET (VOIDmode, new_src,
2216 GEN_INT (temp1)));
2217 emit_constant_insn (cond,
2218 gen_addsi3 (target, new_src,
2219 GEN_INT (-temp2)));
2220 }
2221
2222 return 2;
2223 }
2224 }
2225
e2c671ba
RE		 2226 /* See if we can generate this by setting the bottom (or the top)
2227 16 bits, and then shifting these into the other half of the
2228 word. We only look for the simplest cases, to do more would cost
2229 too much. Be careful, however, not to generate this when the
2230 alternative would take fewer insns. */
30cf4896 2231 if (val & 0xffff0000)
e2c671ba 2232 {
30cf4896 2233 temp1 = remainder & 0xffff0000;
e2c671ba
RE		 2234 temp2 = remainder & 0x0000ffff;
2235
6354dc9b 2236 /* Overlaps outside this range are best done using other methods. */
e2c671ba
RE		 2237 for (i = 9; i < 24; i++)
2238 {
30cf4896 2239 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
5895f793 2240 && !const_ok_for_arm (temp2))
e2c671ba 2241 {
d499463f
RE		 2242 rtx new_src = (subtargets
2243 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2244 : target);
a406f566 2245 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2b835d68 2246 source, subtargets, generate);
e2c671ba 2247 source = new_src;
2b835d68 2248 if (generate)
f676971a 2249 emit_constant_insn
a406f566
MM		 2250 (cond,
2251 gen_rtx_SET
2252 (VOIDmode, target,
2253 gen_rtx_IOR (mode,
2254 gen_rtx_ASHIFT (mode, source,
2255 GEN_INT (i)),
2256 source)));
e2c671ba
RE		 2257 return insns + 1;
2258 }
2259 }
2260
6354dc9b 2261 /* Don't duplicate cases already considered. */
e2c671ba
RE		 2262 for (i = 17; i < 24; i++)
2263 {
2264 if (((temp1 | (temp1 >> i)) == remainder)
5895f793 2265 && !const_ok_for_arm (temp1))
e2c671ba 2266 {
d499463f
RE		 2267 rtx new_src = (subtargets
2268 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2269 : target);
a406f566 2270 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2b835d68 2271 source, subtargets, generate);
e2c671ba 2272 source = new_src;
2b835d68 2273 if (generate)
a406f566
MM		 2274 emit_constant_insn
2275 (cond,
2276 gen_rtx_SET (VOIDmode, target,
43cffd11
RE		 2277 gen_rtx_IOR
2278 (mode,
2279 gen_rtx_LSHIFTRT (mode, source,
2280 GEN_INT (i)),
2281 source)));
e2c671ba
RE		 2282 return insns + 1;
2283 }
2284 }
2285 }
2286 break;
2287
2288 case IOR:
2289 case XOR:
7b64da89
RE		 2290 /* If we have IOR or XOR, and the constant can be loaded in a
2291 single instruction, and we can find a temporary to put it in,
e2c671ba
RE		 2292 then this can be done in two instructions instead of 3-4. */
2293 if (subtargets
d499463f 2294 /* TARGET can't be NULL if SUBTARGETS is 0 */
5895f793 2295 || (reload_completed && !reg_mentioned_p (target, source)))
e2c671ba 2296 {
5895f793 2297 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
e2c671ba 2298 {
2b835d68
RE		 2299 if (generate)
2300 {
2301 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
e2c671ba 2302
a406f566 2303 emit_constant_insn (cond,
f676971a 2304 gen_rtx_SET (VOIDmode, sub,
a406f566
MM		 2305 GEN_INT (val)));
2306 emit_constant_insn (cond,
f676971a 2307 gen_rtx_SET (VOIDmode, target,
a406f566
MM		 2308 gen_rtx_fmt_ee (code, mode,
2309 source, sub)));
2b835d68 2310 }
e2c671ba
RE		 2311 return 2;
2312 }
2313 }
2314
2315 if (code == XOR)
2316 break;
2317
2318 if (set_sign_bit_copies > 8
2319 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2320 {
2b835d68
RE		 2321 if (generate)
2322 {
2323 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2324 rtx shift = GEN_INT (set_sign_bit_copies);
2325
f676971a 2326 emit_constant_insn
a406f566
MM		 2327 (cond,
2328 gen_rtx_SET (VOIDmode, sub,
f676971a 2329 gen_rtx_NOT (mode,
a406f566 2330 gen_rtx_ASHIFT (mode,
f676971a 2331 source,
a406f566 2332 shift))));
f676971a 2333 emit_constant_insn
a406f566
MM		 2334 (cond,
2335 gen_rtx_SET (VOIDmode, target,
2336 gen_rtx_NOT (mode,
2337 gen_rtx_LSHIFTRT (mode, sub,
2338 shift))));
2b835d68 2339 }
e2c671ba
RE		 2340 return 2;
2341 }
2342
2343 if (set_zero_bit_copies > 8
2344 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2345 {
2b835d68
RE		 2346 if (generate)
2347 {
2348 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2349 rtx shift = GEN_INT (set_zero_bit_copies);
2350
a406f566
MM		 2351 emit_constant_insn
2352 (cond,
2353 gen_rtx_SET (VOIDmode, sub,
2354 gen_rtx_NOT (mode,
2355 gen_rtx_LSHIFTRT (mode,
2356 source,
2357 shift))));
f676971a 2358 emit_constant_insn
a406f566
MM		 2359 (cond,
2360 gen_rtx_SET (VOIDmode, target,
2361 gen_rtx_NOT (mode,
2362 gen_rtx_ASHIFT (mode, sub,
2363 shift))));
2b835d68 2364 }
e2c671ba
RE		 2365 return 2;
2366 }
2367
5895f793 2368 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
e2c671ba 2369 {
2b835d68
RE		 2370 if (generate)
2371 {
2372 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
a406f566
MM		 2373 emit_constant_insn (cond,
2374 gen_rtx_SET (VOIDmode, sub,
2375 gen_rtx_NOT (mode, source)));
2b835d68
RE		 2376 source = sub;
2377 if (subtargets)
2378 sub = gen_reg_rtx (mode);
a406f566
MM		 2379 emit_constant_insn (cond,
2380 gen_rtx_SET (VOIDmode, sub,
f676971a 2381 gen_rtx_AND (mode, source,
a406f566
MM		 2382 GEN_INT (temp1))));
2383 emit_constant_insn (cond,
2384 gen_rtx_SET (VOIDmode, target,
2385 gen_rtx_NOT (mode, sub)));
2b835d68 2386 }
e2c671ba
RE		 2387 return 3;
2388 }
2389 break;
2390
2391 case AND:
2392 /* See if two shifts will do 2 or more insn's worth of work. */
2393 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2394 {
30cf4896 2395 HOST_WIDE_INT shift_mask = ((0xffffffff
e2c671ba 2396 << (32 - clear_sign_bit_copies))
30cf4896 2397 & 0xffffffff);
e2c671ba 2398
30cf4896 2399 if ((remainder | shift_mask) != 0xffffffff)
e2c671ba 2400 {
2b835d68
RE		 2401 if (generate)
2402 {
d499463f 2403 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
f676971a 2404 insns = arm_gen_constant (AND, mode, cond,
a406f566 2405 remainder | shift_mask,
d499463f
RE		 2406 new_src, source, subtargets, 1);
2407 source = new_src;
2b835d68
RE		 2408 }
2409 else
d499463f
RE		 2410 {
2411 rtx targ = subtargets ? NULL_RTX : target;
a406f566
MM		 2412 insns = arm_gen_constant (AND, mode, cond,
2413 remainder | shift_mask,
d499463f
RE		 2414 targ, source, subtargets, 0);
2415 }
2b835d68
RE		 2416 }
2417
2418 if (generate)
2419 {
d499463f
RE		 2420 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2421 rtx shift = GEN_INT (clear_sign_bit_copies);
2422
2423 emit_insn (gen_ashlsi3 (new_src, source, shift));
2424 emit_insn (gen_lshrsi3 (target, new_src, shift));
e2c671ba
RE		 2425 }
2426
e2c671ba
RE		 2427 return insns + 2;
2428 }
2429
2430 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2431 {
2432 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
f676971a 2433
30cf4896 2434 if ((remainder | shift_mask) != 0xffffffff)
e2c671ba 2435 {
2b835d68
RE		 2436 if (generate)
2437 {
d499463f
RE		 2438 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2439
a406f566
MM		 2440 insns = arm_gen_constant (AND, mode, cond,
2441 remainder | shift_mask,
d499463f
RE		 2442 new_src, source, subtargets, 1);
2443 source = new_src;
2b835d68
RE		 2444 }
2445 else
d499463f
RE		 2446 {
2447 rtx targ = subtargets ? NULL_RTX : target;
2448
a406f566
MM		 2449 insns = arm_gen_constant (AND, mode, cond,
2450 remainder | shift_mask,
d499463f
RE		 2451 targ, source, subtargets, 0);
2452 }
2b835d68
RE		 2453 }
2454
2455 if (generate)
2456 {
d499463f
RE		 2457 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2458 rtx shift = GEN_INT (clear_zero_bit_copies);
2459
2460 emit_insn (gen_lshrsi3 (new_src, source, shift));
2461 emit_insn (gen_ashlsi3 (target, new_src, shift));
e2c671ba
RE		 2462 }
2463
e2c671ba
RE		 2464 return insns + 2;
2465 }
2466
2467 break;
2468
2469 default:
2470 break;
2471 }
2472
2473 for (i = 0; i < 32; i++)
2474 if (remainder & (1 << i))
2475 num_bits_set++;
2476
2477 if (code == AND || (can_invert && num_bits_set > 16))
30cf4896 2478 remainder = (~remainder) & 0xffffffff;
e2c671ba 2479 else if (code == PLUS && num_bits_set > 16)
30cf4896 2480 remainder = (-remainder) & 0xffffffff;
e2c671ba
RE		 2481 else
2482 {
2483 can_invert = 0;
2484 can_negate = 0;
2485 }
2486
2487 /* Now try and find a way of doing the job in either two or three
2488 instructions.
2489 We start by looking for the largest block of zeros that are aligned on
2490 a 2-bit boundary, we then fill up the temps, wrapping around to the
2491 top of the word when we drop off the bottom.
5b3e6663
PB		 2492 In the worst case this code should produce no more than four insns.
2493 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2494 best place to start. */
2495
2496 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2497 the same. */
e2c671ba
RE		 2498 {
2499 int best_start = 0;
5b3e6663 2500 if (!TARGET_THUMB2)
e2c671ba 2501 {
5b3e6663 2502 int best_consecutive_zeros = 0;
e2c671ba 2503
5b3e6663 2504 for (i = 0; i < 32; i += 2)
e2c671ba 2505 {
5b3e6663
PB		 2506 int consecutive_zeros = 0;
2507
2508 if (!(remainder & (3 << i)))
e2c671ba 2509 {
5b3e6663
PB		 2510 while ((i < 32) && !(remainder & (3 << i)))
2511 {
2512 consecutive_zeros += 2;
2513 i += 2;
2514 }
2515 if (consecutive_zeros > best_consecutive_zeros)
2516 {
2517 best_consecutive_zeros = consecutive_zeros;
2518 best_start = i - consecutive_zeros;
2519 }
2520 i -= 2;
e2c671ba 2521 }
e2c671ba 2522 }
ceebdb09 2523
5b3e6663
PB		 2524 /* So long as it won't require any more insns to do so, it's
2525 desirable to emit a small constant (in bits 0...9) in the last
2526 insn. This way there is more chance that it can be combined with
2527 a later addressing insn to form a pre-indexed load or store
2528 operation. Consider:
2529
2530 *((volatile int *)0xe0000100) = 1;
2531 *((volatile int *)0xe0000110) = 2;
2532
2533 We want this to wind up as:
2534
2535 mov rA, #0xe0000000
2536 mov rB, #1
2537 str rB, [rA, #0x100]
2538 mov rB, #2
2539 str rB, [rA, #0x110]
2540
2541 rather than having to synthesize both large constants from scratch.
2542
2543 Therefore, we calculate how many insns would be required to emit
2544 the constant starting from `best_start', and also starting from
2545 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2546 yield a shorter sequence, we may as well use zero. */
2547 if (best_start != 0
2548 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2549 && (count_insns_for_constant (remainder, 0) <=
2550 count_insns_for_constant (remainder, best_start)))
2551 best_start = 0;
2552 }
ceebdb09
PB		 2553
2554 /* Now start emitting the insns. */
e2c671ba
RE		 2555 i = best_start;
2556 do
2557 {
2558 int end;
2559
2560 if (i <= 0)
2561 i += 32;
2562 if (remainder & (3 << (i - 2)))
2563 {
2564 end = i - 8;
2565 if (end < 0)
2566 end += 32;
2567 temp1 = remainder & ((0x0ff << end)
2568 | ((i < end) ? (0xff >> (32 - end)) : 0));
2569 remainder &= ~temp1;
2570
d499463f 2571 if (generate)
e2c671ba 2572 {
9503f3d1
RH		 2573 rtx new_src, temp1_rtx;
2574
2575 if (code == SET || code == MINUS)
2576 {
2577 new_src = (subtargets ? gen_reg_rtx (mode) : target);
96ae8197 2578 if (can_invert && code != MINUS)
9503f3d1
RH		 2579 temp1 = ~temp1;
2580 }
2581 else
2582 {
96ae8197 2583 if (remainder && subtargets)
9503f3d1 2584 new_src = gen_reg_rtx (mode);
96ae8197
NC		 2585 else
2586 new_src = target;
9503f3d1
RH		 2587 if (can_invert)
2588 temp1 = ~temp1;
2589 else if (can_negate)
2590 temp1 = -temp1;
2591 }
2592
2593 temp1 = trunc_int_for_mode (temp1, mode);
2594 temp1_rtx = GEN_INT (temp1);
d499463f
RE		 2595
2596 if (code == SET)
9503f3d1 2597 ;
d499463f 2598 else if (code == MINUS)
9503f3d1 2599 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
d499463f 2600 else
9503f3d1
RH		 2601 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2602
a406f566 2603 emit_constant_insn (cond,
f676971a 2604 gen_rtx_SET (VOIDmode, new_src,
a406f566 2605 temp1_rtx));
d499463f 2606 source = new_src;
e2c671ba
RE		 2607 }
2608
d499463f
RE		 2609 if (code == SET)
2610 {
2611 can_invert = 0;
2612 code = PLUS;
2613 }
2614 else if (code == MINUS)
2615 code = PLUS;
2616
e2c671ba 2617 insns++;
5b3e6663
PB		 2618 if (TARGET_ARM)
2619 i -= 6;
2620 else
2621 i -= 7;
e2c671ba 2622 }
7a085dce 2623 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
5b3e6663
PB		 2624 shifts. */
2625 if (TARGET_ARM)
2626 i -= 2;
2627 else
2628 i--;
1d6e90ac
NC		 2629 }
2630 while (remainder);
e2c671ba 2631 }
1d6e90ac 2632
e2c671ba
RE		 2633 return insns;
2634}
2635
bd9c7e23
RE		 2636/* Canonicalize a comparison so that we are more likely to recognize it.
2637 This can be done for a few constant compares, where we can make the
2638 immediate value easier to load. */
1d6e90ac 2639
bd9c7e23 2640enum rtx_code
a14b88bb
PB		 2641arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2642 rtx * op1)
bd9c7e23 2643{
ad076f4e 2644 unsigned HOST_WIDE_INT i = INTVAL (*op1);
a14b88bb
PB		 2645 unsigned HOST_WIDE_INT maxval;
2646 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
bd9c7e23
RE		 2647
2648 switch (code)
2649 {
2650 case EQ:
2651 case NE:
2652 return code;
2653
2654 case GT:
2655 case LE:
a14b88bb 2656 if (i != maxval
5895f793 2657 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
bd9c7e23 2658 {
5895f793 2659 *op1 = GEN_INT (i + 1);
bd9c7e23
RE		 2660 return code == GT ? GE : LT;
2661 }
2662 break;
2663
2664 case GE:
2665 case LT:
a14b88bb 2666 if (i != ~maxval
5895f793 2667 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
bd9c7e23 2668 {
5895f793 2669 *op1 = GEN_INT (i - 1);
bd9c7e23
RE		 2670 return code == GE ? GT : LE;
2671 }
2672 break;
2673
2674 case GTU:
2675 case LEU:
30cf4896 2676 if (i != ~((unsigned HOST_WIDE_INT) 0)
5895f793 2677 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
bd9c7e23
RE		 2678 {
2679 *op1 = GEN_INT (i + 1);
2680 return code == GTU ? GEU : LTU;
2681 }
2682 break;
2683
2684 case GEU:
2685 case LTU:
2686 if (i != 0
5895f793 2687 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
bd9c7e23
RE		 2688 {
2689 *op1 = GEN_INT (i - 1);
2690 return code == GEU ? GTU : LEU;
2691 }
2692 break;
2693
2694 default:
e6d29d15 2695 gcc_unreachable ();
bd9c7e23
RE		 2696 }
2697
2698 return code;
2699}
bd9c7e23 2700
d4453b7a
PB		 2701
2702/* Define how to find the value returned by a function. */
2703
9f7bf991 2704rtx
586de218 2705arm_function_value(const_tree type, const_tree func ATTRIBUTE_UNUSED)
d4453b7a
PB		 2706{
2707 enum machine_mode mode;
2708 int unsignedp ATTRIBUTE_UNUSED;
2709 rtx r ATTRIBUTE_UNUSED;
2710
d4453b7a
PB		 2711 mode = TYPE_MODE (type);
2712 /* Promote integer types. */
2713 if (INTEGRAL_TYPE_P (type))
2714 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
866af8a9
JB		 2715
2716 /* Promotes small structs returned in a register to full-word size
2717 for big-endian AAPCS. */
2718 if (arm_return_in_msb (type))
2719 {
2720 HOST_WIDE_INT size = int_size_in_bytes (type);
2721 if (size % UNITS_PER_WORD != 0)
2722 {
2723 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2724 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2725 }
2726 }
e0b92319 2727
d4453b7a
PB		 2728 return LIBCALL_VALUE(mode);
2729}
2730
e0b92319 2731/* Determine the amount of memory needed to store the possible return
9f7bf991
RE		 2732 registers of an untyped call. */
2733int
2734arm_apply_result_size (void)
2735{
2736 int size = 16;
2737
2738 if (TARGET_ARM)
2739 {
2740 if (TARGET_HARD_FLOAT_ABI)
2741 {
2742 if (TARGET_FPA)
2743 size += 12;
2744 if (TARGET_MAVERICK)
2745 size += 8;
2746 }
2747 if (TARGET_IWMMXT_ABI)
2748 size += 8;
2749 }
2750
2751 return size;
2752}
d4453b7a 2753
f5a1b0d2 2754/* Decide whether a type should be returned in memory (true)
23668cf7 2755 or in a register (false). This is called as the target hook
81464b2c 2756 TARGET_RETURN_IN_MEMORY. */
23668cf7 2757static bool
81464b2c 2758arm_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
2b835d68 2759{
dc0ba55a
JT		 2760 HOST_WIDE_INT size;
2761
88f77cba
JB		 2762 size = int_size_in_bytes (type);
2763
2764 /* Vector values should be returned using ARM registers, not memory (unless
2765 they're over 16 bytes, which will break since we only have four
2766 call-clobbered registers to play with). */
2767 if (TREE_CODE (type) == VECTOR_TYPE)
2768 return (size < 0 || size > (4 * UNITS_PER_WORD));
2769
3dd7ab65
JB		 2770 if (!AGGREGATE_TYPE_P (type) &&
2771 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2772 /* All simple types are returned in registers.
2773 For AAPCS, complex types are treated the same as aggregates. */
d7d01975 2774 return 0;
dc0ba55a 2775
5848830f 2776 if (arm_abi != ARM_ABI_APCS)
dc0ba55a 2777 {
5848830f 2778 /* ATPCS and later return aggregate types in memory only if they are
dc0ba55a
JT		 2779 larger than a word (or are variable size). */
2780 return (size < 0 || size > UNITS_PER_WORD);
2781 }
f676971a 2782
6bc82793 2783 /* For the arm-wince targets we choose to be compatible with Microsoft's
d5b7b3ae
RE		 2784 ARM and Thumb compilers, which always return aggregates in memory. */
2785#ifndef ARM_WINCE
e529bd42
NC		 2786 /* All structures/unions bigger than one word are returned in memory.
2787 Also catch the case where int_size_in_bytes returns -1. In this case
6bc82793 2788 the aggregate is either huge or of variable size, and in either case
e529bd42 2789 we will want to return it via memory and not in a register. */
dc0ba55a 2790 if (size < 0 || size > UNITS_PER_WORD)
d7d01975 2791 return 1;
f676971a 2792
d7d01975 2793 if (TREE_CODE (type) == RECORD_TYPE)
2b835d68
RE		 2794 {
2795 tree field;
2796
3a2ea258
RE		 2797 /* For a struct the APCS says that we only return in a register
2798 if the type is 'integer like' and every addressable element
2799 has an offset of zero. For practical purposes this means
2800 that the structure can have at most one non bit-field element
2801 and that this element must be the first one in the structure. */
f676971a 2802
f5a1b0d2
NC		 2803 /* Find the first field, ignoring non FIELD_DECL things which will
2804 have been created by C++. */
2805 for (field = TYPE_FIELDS (type);
2806 field && TREE_CODE (field) != FIELD_DECL;
2807 field = TREE_CHAIN (field))
2808 continue;
f676971a 2809
f5a1b0d2 2810 if (field == NULL)
9e291dbe 2811 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
f5a1b0d2 2812
d5b7b3ae
RE		 2813 /* Check that the first field is valid for returning in a register. */
2814
2815 /* ... Floats are not allowed */
9e291dbe 2816 if (FLOAT_TYPE_P (TREE_TYPE (field)))
3a2ea258
RE		 2817 return 1;
2818
d5b7b3ae
RE		 2819 /* ... Aggregates that are not themselves valid for returning in
2820 a register are not allowed. */
81464b2c 2821 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
3a2ea258 2822 return 1;
6f7ebcbb 2823
3a2ea258
RE		 2824 /* Now check the remaining fields, if any. Only bitfields are allowed,
2825 since they are not addressable. */
f5a1b0d2
NC		 2826 for (field = TREE_CHAIN (field);
2827 field;
2828 field = TREE_CHAIN (field))
2829 {
2830 if (TREE_CODE (field) != FIELD_DECL)
2831 continue;
f676971a 2832
5895f793 2833 if (!DECL_BIT_FIELD_TYPE (field))
f5a1b0d2
NC		 2834 return 1;
2835 }
2b835d68
RE		 2836
2837 return 0;
2838 }
f676971a 2839
d7d01975 2840 if (TREE_CODE (type) == UNION_TYPE)
2b835d68
RE		 2841 {
2842 tree field;
2843
2844 /* Unions can be returned in registers if every element is
2845 integral, or can be returned in an integer register. */
f5a1b0d2
NC		 2846 for (field = TYPE_FIELDS (type);
2847 field;
2848 field = TREE_CHAIN (field))
2b835d68 2849 {
f5a1b0d2
NC		 2850 if (TREE_CODE (field) != FIELD_DECL)
2851 continue;
2852
6cc8c0b3
NC		 2853 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2854 return 1;
f676971a 2855
81464b2c 2856 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
2b835d68
RE		 2857 return 1;
2858 }
f676971a 2859
2b835d68
RE		 2860 return 0;
2861 }
f676971a
EC		 2862#endif /* not ARM_WINCE */
2863
d5b7b3ae 2864 /* Return all other types in memory. */
2b835d68
RE		 2865 return 1;
2866}
2867
d6b4baa4 2868/* Indicate whether or not words of a double are in big-endian order. */
3717da94
JT		 2869
2870int
e32bac5b 2871arm_float_words_big_endian (void)
3717da94 2872{
9b66ebb1 2873 if (TARGET_MAVERICK)
9b6b54e2 2874 return 0;
3717da94
JT		 2875
2876 /* For FPA, float words are always big-endian. For VFP, floats words
2877 follow the memory system mode. */
2878
9b66ebb1 2879 if (TARGET_FPA)
3717da94 2880 {
3717da94
JT		 2881 return 1;
2882 }
2883
2884 if (TARGET_VFP)
2885 return (TARGET_BIG_END ? 1 : 0);
2886
2887 return 1;
2888}
2889
82e9d970
PB		 2890/* Initialize a variable CUM of type CUMULATIVE_ARGS
2891 for a call to a function whose data type is FNTYPE.
2892 For a library call, FNTYPE is NULL. */
2893void
f676971a 2894arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
e32bac5b
RE		 2895 rtx libname ATTRIBUTE_UNUSED,
2896 tree fndecl ATTRIBUTE_UNUSED)
82e9d970
PB		 2897{
2898 /* On the ARM, the offset starts at 0. */
29e339b9 2899 pcum->nregs = 0;
5a9335ef 2900 pcum->iwmmxt_nregs = 0;
5848830f 2901 pcum->can_split = true;
f676971a 2902
5a9335ef
NC		 2903 /* Varargs vectors are treated the same as long long.
2904 named_count avoids having to change the way arm handles 'named' */
2905 pcum->named_count = 0;
2906 pcum->nargs = 0;
2907
2908 if (TARGET_REALLY_IWMMXT && fntype)
2909 {
2910 tree fn_arg;
2911
2912 for (fn_arg = TYPE_ARG_TYPES (fntype);
2913 fn_arg;
2914 fn_arg = TREE_CHAIN (fn_arg))
2915 pcum->named_count += 1;
2916
2917 if (! pcum->named_count)
2918 pcum->named_count = INT_MAX;
2919 }
82e9d970
PB		 2920}
2921
5848830f
PB		 2922
2923/* Return true if mode/type need doubleword alignment. */
2924bool
2925arm_needs_doubleword_align (enum machine_mode mode, tree type)
2926{
65a939f7
PB		 2927 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2928 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
5848830f
PB		 2929}
2930
2931
82e9d970
PB		 2932/* Determine where to put an argument to a function.
2933 Value is zero to push the argument on the stack,
2934 or a hard register in which to store the argument.
2935
2936 MODE is the argument's machine mode.
2937 TYPE is the data type of the argument (as a tree).
2938 This is null for libcalls where that information may
2939 not be available.
2940 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2941 the preceding args and about the function being called.
2942 NAMED is nonzero if this argument is a named parameter
2943 (otherwise it is an extra parameter matching an ellipsis). */
1d6e90ac 2944
82e9d970 2945rtx
e32bac5b 2946arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
5848830f 2947 tree type, int named)
82e9d970 2948{
5848830f
PB		 2949 int nregs;
2950
2951 /* Varargs vectors are treated the same as long long.
2952 named_count avoids having to change the way arm handles 'named' */
2953 if (TARGET_IWMMXT_ABI
f676971a 2954 && arm_vector_mode_supported_p (mode)
5848830f 2955 && pcum->named_count > pcum->nargs + 1)
5a9335ef 2956 {
5848830f
PB		 2957 if (pcum->iwmmxt_nregs <= 9)
2958 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2959 else
5a9335ef 2960 {
5848830f
PB		 2961 pcum->can_split = false;
2962 return NULL_RTX;
5a9335ef 2963 }
5a9335ef
NC		 2964 }
2965
5848830f
PB		 2966 /* Put doubleword aligned quantities in even register pairs. */
2967 if (pcum->nregs & 1
2968 && ARM_DOUBLEWORD_ALIGN
2969 && arm_needs_doubleword_align (mode, type))
2970 pcum->nregs++;
2971
82e9d970 2972 if (mode == VOIDmode)
25a65198
RS		 2973 /* Pick an arbitrary value for operand 2 of the call insn. */
2974 return const0_rtx;
5848830f 2975
666c27b9 2976 /* Only allow splitting an arg between regs and memory if all preceding
5848830f
PB		 2977 args were allocated to regs. For args passed by reference we only count
2978 the reference pointer. */
2979 if (pcum->can_split)
2980 nregs = 1;
2981 else
2982 nregs = ARM_NUM_REGS2 (mode, type);
2983
2984 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
82e9d970 2985 return NULL_RTX;
f676971a 2986
82e9d970
PB		 2987 return gen_rtx_REG (mode, pcum->nregs);
2988}
1741620c 2989
78a52f11
RH		 2990static int
2991arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2992 tree type, bool named ATTRIBUTE_UNUSED)
2993{
2994 int nregs = pcum->nregs;
2995
88f77cba 2996 if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode))
78a52f11
RH		 2997 return 0;
2998
2999 if (NUM_ARG_REGS > nregs
3000 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
3001 && pcum->can_split)
3002 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
3003
3004 return 0;
3005}
3006
1741620c
JD		 3007/* Variable sized types are passed by reference. This is a GCC
3008 extension to the ARM ABI. */
3009
8cd5a4e0
RH		 3010static bool
3011arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3012 enum machine_mode mode ATTRIBUTE_UNUSED,
586de218 3013 const_tree type, bool named ATTRIBUTE_UNUSED)
1741620c
JD		 3014{
3015 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3016}
82e9d970 3017\f
c27ba912
DM		 3018/* Encode the current state of the #pragma [no_]long_calls. */
3019typedef enum
82e9d970 3020{
6fc0bb99 3021 OFF, /* No #pragma [no_]long_calls is in effect. */
c27ba912
DM		 3022 LONG, /* #pragma long_calls is in effect. */
3023 SHORT /* #pragma no_long_calls is in effect. */
3024} arm_pragma_enum;
82e9d970 3025
c27ba912 3026static arm_pragma_enum arm_pragma_long_calls = OFF;
82e9d970 3027
8b97c5f8 3028void
e32bac5b 3029arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
82e9d970 3030{
8b97c5f8
ZW		 3031 arm_pragma_long_calls = LONG;
3032}
3033
3034void
e32bac5b 3035arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 3036{
3037 arm_pragma_long_calls = SHORT;
3038}
3039
3040void
e32bac5b 3041arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
8b97c5f8
ZW		 3042{
3043 arm_pragma_long_calls = OFF;
82e9d970
PB		 3044}
3045\f
91d231cb
JM		 3046/* Table of machine attributes. */
3047const struct attribute_spec arm_attribute_table[] =
82e9d970 3048{
91d231cb 3049 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
82e9d970
PB		 3050 /* Function calls made to this symbol must be done indirectly, because
3051 it may lie outside of the 26 bit addressing range of a normal function
3052 call. */
91d231cb 3053 { "long_call", 0, 0, false, true, true, NULL },
82e9d970
PB		 3054 /* Whereas these functions are always known to reside within the 26 bit
3055 addressing range. */
91d231cb 3056 { "short_call", 0, 0, false, true, true, NULL },
f676971a 3057 /* Interrupt Service Routines have special prologue and epilogue requirements. */
91d231cb
JM		 3058 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
3059 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
3060 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3061#ifdef ARM_PE
3062 /* ARM/PE has three new attributes:
3063 interfacearm - ?
3064 dllexport - for exporting a function/variable that will live in a dll
3065 dllimport - for importing a function/variable from a dll
3066
3067 Microsoft allows multiple declspecs in one __declspec, separating
3068 them with spaces. We do NOT support this. Instead, use __declspec
3069 multiple times.
3070 */
3071 { "dllimport", 0, 0, true, false, false, NULL },
3072 { "dllexport", 0, 0, true, false, false, NULL },
3073 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
b2ca3702
MM		 3074#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
3075 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
3076 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
04fb56d5 3077 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
91d231cb
JM		 3078#endif
3079 { NULL, 0, 0, false, false, false, NULL }
3080};
6d3d9133 3081
91d231cb
JM		 3082/* Handle an attribute requiring a FUNCTION_DECL;
3083 arguments as in struct attribute_spec.handler. */
3084static tree
e32bac5b
RE		 3085arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
3086 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
91d231cb
JM		 3087{
3088 if (TREE_CODE (*node) != FUNCTION_DECL)
3089 {
5c498b10 3090 warning (OPT_Wattributes, "%qs attribute only applies to functions",
91d231cb
JM		 3091 IDENTIFIER_POINTER (name));
3092 *no_add_attrs = true;
3093 }
3094
3095 return NULL_TREE;
3096}
3097
3098/* Handle an "interrupt" or "isr" attribute;
3099 arguments as in struct attribute_spec.handler. */
3100static tree
e32bac5b
RE		 3101arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3102 bool *no_add_attrs)
91d231cb
JM		 3103{
3104 if (DECL_P (*node))
3105 {
3106 if (TREE_CODE (*node) != FUNCTION_DECL)
3107 {
5c498b10 3108 warning (OPT_Wattributes, "%qs attribute only applies to functions",
91d231cb
JM		 3109 IDENTIFIER_POINTER (name));
3110 *no_add_attrs = true;
3111 }
3112 /* FIXME: the argument if any is checked for type attributes;
3113 should it be checked for decl ones? */
3114 }
3115 else
3116 {
3117 if (TREE_CODE (*node) == FUNCTION_TYPE
3118 || TREE_CODE (*node) == METHOD_TYPE)
3119 {
3120 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3121 {
5c498b10
DD		 3122 warning (OPT_Wattributes, "%qs attribute ignored",
3123 IDENTIFIER_POINTER (name));
91d231cb
JM		 3124 *no_add_attrs = true;
3125 }
3126 }
3127 else if (TREE_CODE (*node) == POINTER_TYPE
3128 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3129 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3130 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3131 {
8dd16ecc 3132 *node = build_variant_type_copy (*node);
1d6e90ac
NC		 3133 TREE_TYPE (*node) = build_type_attribute_variant
3134 (TREE_TYPE (*node),
3135 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
91d231cb
JM		 3136 *no_add_attrs = true;
3137 }
3138 else
3139 {
3140 /* Possibly pass this attribute on from the type to a decl. */
3141 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3142 | (int) ATTR_FLAG_FUNCTION_NEXT
3143 | (int) ATTR_FLAG_ARRAY_NEXT))
3144 {
3145 *no_add_attrs = true;
3146 return tree_cons (name, args, NULL_TREE);
3147 }
3148 else
3149 {
5c498b10
DD		 3150 warning (OPT_Wattributes, "%qs attribute ignored",
3151 IDENTIFIER_POINTER (name));
91d231cb
JM		 3152 }
3153 }
3154 }
3155
3156 return NULL_TREE;
82e9d970
PB		 3157}
3158
7bff66a7 3159#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
04fb56d5
MM		 3160/* Handle the "notshared" attribute. This attribute is another way of
3161 requesting hidden visibility. ARM's compiler supports
3162 "__declspec(notshared)"; we support the same thing via an
3163 attribute. */
3164
3165static tree
e0b92319
NC		 3166arm_handle_notshared_attribute (tree *node,
3167 tree name ATTRIBUTE_UNUSED,
3168 tree args ATTRIBUTE_UNUSED,
3169 int flags ATTRIBUTE_UNUSED,
04fb56d5
MM		 3170 bool *no_add_attrs)
3171{
3172 tree decl = TYPE_NAME (*node);
3173
3174 if (decl)
3175 {
3176 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3177 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3178 *no_add_attrs = false;
3179 }
3180 return NULL_TREE;
3181}
7bff66a7 3182#endif
04fb56d5 3183
82e9d970
PB		 3184/* Return 0 if the attributes for two types are incompatible, 1 if they
3185 are compatible, and 2 if they are nearly compatible (which causes a
3186 warning to be generated). */
8d8e52be 3187static int
3101faab 3188arm_comp_type_attributes (const_tree type1, const_tree type2)
82e9d970 3189{
1cb8d58a 3190 int l1, l2, s1, s2;
f676971a 3191
82e9d970
PB		 3192 /* Check for mismatch of non-default calling convention. */
3193 if (TREE_CODE (type1) != FUNCTION_TYPE)
3194 return 1;
3195
3196 /* Check for mismatched call attributes. */
1cb8d58a
NC		 3197 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3198 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3199 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3200 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
bd7fc26f
NC		 3201
3202 /* Only bother to check if an attribute is defined. */
3203 if (l1 | l2 | s1 | s2)
3204 {
3205 /* If one type has an attribute, the other must have the same attribute. */
1cb8d58a 3206 if ((l1 != l2) || (s1 != s2))
bd7fc26f 3207 return 0;
82e9d970 3208
bd7fc26f
NC		 3209 /* Disallow mixed attributes. */
3210 if ((l1 & s2) || (l2 & s1))
3211 return 0;
3212 }
f676971a 3213
6d3d9133
NC		 3214 /* Check for mismatched ISR attribute. */
3215 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3216 if (! l1)
3217 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3218 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3219 if (! l2)
3220 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3221 if (l1 != l2)
3222 return 0;
3223
bd7fc26f 3224 return 1;
82e9d970
PB		 3225}
3226
c27ba912
DM		 3227/* Assigns default attributes to newly defined type. This is used to
3228 set short_call/long_call attributes for function types of
3229 functions defined inside corresponding #pragma scopes. */
8d8e52be 3230static void
e32bac5b 3231arm_set_default_type_attributes (tree type)
c27ba912
DM		 3232{
3233 /* Add __attribute__ ((long_call)) to all functions, when
3234 inside #pragma long_calls or __attribute__ ((short_call)),
3235 when inside #pragma no_long_calls. */
3236 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3237 {
3238 tree type_attr_list, attr_name;
3239 type_attr_list = TYPE_ATTRIBUTES (type);
3240
3241 if (arm_pragma_long_calls == LONG)
3242 attr_name = get_identifier ("long_call");
3243 else if (arm_pragma_long_calls == SHORT)
3244 attr_name = get_identifier ("short_call");
3245 else
3246 return;
3247
3248 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3249 TYPE_ATTRIBUTES (type) = type_attr_list;
3250 }
3251}
3252\f
25a65198
RS		 3253/* Return true if DECL is known to be linked into section SECTION. */
3254
3255static bool
3256arm_function_in_section_p (tree decl, section *section)
c27ba912 3257{
25a65198
RS		 3258 /* We can only be certain about functions defined in the same
3259 compilation unit. */
3260 if (!TREE_STATIC (decl))
3261 return false;
c27ba912 3262
25a65198
RS		 3263 /* Make sure that SYMBOL always binds to the definition in this
3264 compilation unit. */
3265 if (!targetm.binds_local_p (decl))
3266 return false;
c27ba912 3267
25a65198
RS		 3268 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3269 if (!DECL_SECTION_NAME (decl))
3270 {
25a65198
RS		 3271 /* Make sure that we will not create a unique section for DECL. */
3272 if (flag_function_sections || DECL_ONE_ONLY (decl))
3273 return false;
3274 }
3275
3276 return function_section (decl) == section;
c27ba912
DM		 3277}
3278
a50aa827 3279/* Return nonzero if a 32-bit "long_call" should be generated for
25a65198
RS		 3280 a call from the current function to DECL. We generate a long_call
3281 if the function:
c27ba912
DM		 3282
3283 a. has an __attribute__((long call))
3284 or b. is within the scope of a #pragma long_calls
3285 or c. the -mlong-calls command line switch has been specified
3286
3287 However we do not generate a long call if the function:
f676971a 3288
c27ba912
DM		 3289 d. has an __attribute__ ((short_call))
3290 or e. is inside the scope of a #pragma no_long_calls
25a65198 3291 or f. is defined in the same section as the current function. */
c27ba912 3292
25a65198
RS		 3293bool
3294arm_is_long_call_p (tree decl)
3295{
3296 tree attrs;
c27ba912 3297
25a65198
RS		 3298 if (!decl)
3299 return TARGET_LONG_CALLS;
c27ba912 3300
25a65198
RS		 3301 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3302 if (lookup_attribute ("short_call", attrs))
3303 return false;
c27ba912 3304
25a65198
RS		 3305 /* For "f", be conservative, and only cater for cases in which the
3306 whole of the current function is placed in the same section. */
3307 if (!flag_reorder_blocks_and_partition
3308 && arm_function_in_section_p (decl, current_function_section ()))
3309 return false;
a77655b1 3310
25a65198
RS		 3311 if (lookup_attribute ("long_call", attrs))
3312 return true;
f676971a 3313
25a65198 3314 return TARGET_LONG_CALLS;
c27ba912 3315}
f99fce0c 3316
825dda42 3317/* Return nonzero if it is ok to make a tail-call to DECL. */
4977bab6 3318static bool
e32bac5b 3319arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
f99fce0c 3320{
5b3e6663 3321 unsigned long func_type;
f99fce0c 3322
5a9335ef
NC		 3323 if (cfun->machine->sibcall_blocked)
3324 return false;
3325
f99fce0c
RE		 3326 /* Never tailcall something for which we have no decl, or if we
3327 are in Thumb mode. */
3328 if (decl == NULL || TARGET_THUMB)
4977bab6 3329 return false;
f99fce0c 3330
9403b7f7
RS		 3331 /* The PIC register is live on entry to VxWorks PLT entries, so we
3332 must make the call before restoring the PIC register. */
3333 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
3334 return false;
3335
f99fce0c 3336 /* Cannot tail-call to long calls, since these are out of range of
25a65198
RS		 3337 a branch instruction. */
3338 if (arm_is_long_call_p (decl))
4977bab6 3339 return false;
f99fce0c
RE		 3340
3341 /* If we are interworking and the function is not declared static
f676971a 3342 then we can't tail-call it unless we know that it exists in this
f99fce0c 3343 compilation unit (since it might be a Thumb routine). */
5895f793 3344 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
4977bab6 3345 return false;
f99fce0c 3346
5b3e6663 3347 func_type = arm_current_func_type ();
6d3d9133 3348 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
5b3e6663
PB		 3349 if (IS_INTERRUPT (func_type))
3350 return false;
3351
3352 /* Never tailcall if function may be called with a misaligned SP. */
3353 if (IS_STACKALIGN (func_type))
4977bab6 3354 return false;
6d3d9133 3355
f99fce0c 3356 /* Everything else is ok. */
4977bab6 3357 return true;
f99fce0c
RE		 3358}
3359
82e9d970 3360\f
6b990f6b
RE		 3361/* Addressing mode support functions. */
3362
0b4be7de 3363/* Return nonzero if X is a legitimate immediate operand when compiling
020a4035 3364 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
32de079a 3365int
e32bac5b 3366legitimate_pic_operand_p (rtx x)
32de079a 3367{
020a4035
RE		 3368 if (GET_CODE (x) == SYMBOL_REF
3369 || (GET_CODE (x) == CONST
3370 && GET_CODE (XEXP (x, 0)) == PLUS
3371 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
32de079a
RE		 3372 return 0;
3373
3374 return 1;
3375}
3376
9403b7f7
RS		 3377/* Record that the current function needs a PIC register. Initialize
3378 cfun->machine->pic_reg if we have not already done so. */
3379
3380static void
3381require_pic_register (void)
3382{
3383 /* A lot of the logic here is made obscure by the fact that this
3384 routine gets called as part of the rtx cost estimation process.
3385 We don't want those calls to affect any assumptions about the real
3386 function; and further, we can't call entry_of_function() until we
3387 start the real expansion process. */
e3b5732b 3388 if (!crtl->uses_pic_offset_table)
9403b7f7 3389 {
b3a13419 3390 gcc_assert (can_create_pseudo_p ());
9403b7f7
RS		 3391 if (arm_pic_register != INVALID_REGNUM)
3392 {
3393 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3394
3395 /* Play games to avoid marking the function as needing pic
3396 if we are being called as part of the cost-estimation
3397 process. */
3398 if (current_ir_type () != IR_GIMPLE)
e3b5732b 3399 crtl->uses_pic_offset_table = 1;
9403b7f7
RS		 3400 }
3401 else
3402 {
3403 rtx seq;
3404
3405 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3406
3407 /* Play games to avoid marking the function as needing pic
3408 if we are being called as part of the cost-estimation
3409 process. */
3410 if (current_ir_type () != IR_GIMPLE)
3411 {
e3b5732b 3412 crtl->uses_pic_offset_table = 1;
9403b7f7
RS		 3413 start_sequence ();
3414
3415 arm_load_pic_register (0UL);
3416
3417 seq = get_insns ();
3418 end_sequence ();
3419 emit_insn_after (seq, entry_of_function ());
3420 }
3421 }
3422 }
3423}
3424
32de079a 3425rtx
e32bac5b 3426legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
32de079a 3427{
a3c48721
RE		 3428 if (GET_CODE (orig) == SYMBOL_REF
3429 || GET_CODE (orig) == LABEL_REF)
32de079a
RE		 3430 {
3431 rtx pic_ref, address;
3432 rtx insn;
3433 int subregs = 0;
3434
9403b7f7
RS		 3435 /* If this function doesn't have a pic register, create one now. */
3436 require_pic_register ();
020a4035 3437
32de079a
RE		 3438 if (reg == 0)
3439 {
b3a13419 3440 gcc_assert (can_create_pseudo_p ());
e6d29d15 3441 reg = gen_reg_rtx (Pmode);
32de079a
RE		 3442
3443 subregs = 1;
3444 }
3445
32de079a
RE		 3446 if (subregs)
3447 address = gen_reg_rtx (Pmode);
3448 else
3449 address = reg;
3450
4bec9f7d
NC		 3451 if (TARGET_ARM)
3452 emit_insn (gen_pic_load_addr_arm (address, orig));
5b3e6663
PB		 3453 else if (TARGET_THUMB2)
3454 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3455 else /* TARGET_THUMB1 */
3456 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
32de079a 3457
9403b7f7
RS		 3458 /* VxWorks does not impose a fixed gap between segments; the run-time
3459 gap can be different from the object-file gap. We therefore can't
3460 use GOTOFF unless we are absolutely sure that the symbol is in the
3461 same segment as the GOT. Unfortunately, the flexibility of linker
3462 scripts means that we can't be sure of that in general, so assume
3463 that GOTOFF is never valid on VxWorks. */
14f583b8 3464 if ((GET_CODE (orig) == LABEL_REF
f676971a 3465 || (GET_CODE (orig) == SYMBOL_REF &&
94428622 3466 SYMBOL_REF_LOCAL_P (orig)))
9403b7f7
RS		 3467 && NEED_GOT_RELOC
3468 && !TARGET_VXWORKS_RTP)
020a4035 3469 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
a3c48721
RE		 3470 else
3471 {
542a8afa 3472 pic_ref = gen_const_mem (Pmode,
020a4035 3473 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
542a8afa 3474 address));
a3c48721
RE		 3475 }
3476
32de079a 3477 insn = emit_move_insn (reg, pic_ref);
96a3900d 3478
32de079a
RE		 3479 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3480 by loop. */
bd94cb6e
SB		 3481 set_unique_reg_note (insn, REG_EQUAL, orig);
3482
32de079a
RE		 3483 return reg;
3484 }
3485 else if (GET_CODE (orig) == CONST)
3486 {
3487 rtx base, offset;
3488
3489 if (GET_CODE (XEXP (orig, 0)) == PLUS
020a4035 3490 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
32de079a
RE		 3491 return orig;
3492
d3585b76
DJ		 3493 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3494 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3495 return orig;
3496
32de079a
RE		 3497 if (reg == 0)
3498 {
b3a13419 3499 gcc_assert (can_create_pseudo_p ());
e6d29d15 3500 reg = gen_reg_rtx (Pmode);
32de079a
RE		 3501 }
3502
e6d29d15 3503 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
e0b92319 3504
e6d29d15
NS		 3505 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3506 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3507 base == reg ? 0 : reg);
32de079a
RE		 3508
3509 if (GET_CODE (offset) == CONST_INT)
3510 {
3511 /* The base register doesn't really matter, we only want to
3512 test the index for the appropriate mode. */
1e1ab407 3513 if (!arm_legitimate_index_p (mode, offset, SET, 0))
6b990f6b 3514 {
b3a13419 3515 gcc_assert (can_create_pseudo_p ());
e6d29d15 3516 offset = force_reg (Pmode, offset);
6b990f6b 3517 }
32de079a 3518
32de079a 3519 if (GET_CODE (offset) == CONST_INT)
ed8908e7 3520 return plus_constant (base, INTVAL (offset));
32de079a
RE		 3521 }
3522
3523 if (GET_MODE_SIZE (mode) > 4
3524 && (GET_MODE_CLASS (mode) == MODE_INT
3525 || TARGET_SOFT_FLOAT))
3526 {
3527 emit_insn (gen_addsi3 (reg, base, offset));
3528 return reg;
3529 }
3530
43cffd11 3531 return gen_rtx_PLUS (Pmode, base, offset);
32de079a 3532 }
32de079a
RE		 3533
3534 return orig;
3535}
3536
57934c39 3537
5b3e6663 3538/* Find a spare register to use during the prolog of a function. */
57934c39
PB		 3539
3540static int
b279b20a 3541thumb_find_work_register (unsigned long pushed_regs_mask)
57934c39
PB		 3542{
3543 int reg;
3544
b279b20a
NC		 3545 /* Check the argument registers first as these are call-used. The
3546 register allocation order means that sometimes r3 might be used
3547 but earlier argument registers might not, so check them all. */
3548 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
6fb5fa3c 3549 if (!df_regs_ever_live_p (reg))
b279b20a
NC		 3550 return reg;
3551
3552 /* Before going on to check the call-saved registers we can try a couple
3553 more ways of deducing that r3 is available. The first is when we are
3554 pushing anonymous arguments onto the stack and we have less than 4
3555 registers worth of fixed arguments(*). In this case r3 will be part of
3556 the variable argument list and so we can be sure that it will be
3557 pushed right at the start of the function. Hence it will be available
3558 for the rest of the prologue.
38173d38 3559 (*): ie crtl->args.pretend_args_size is greater than 0. */
b279b20a 3560 if (cfun->machine->uses_anonymous_args
38173d38 3561 && crtl->args.pretend_args_size > 0)
57934c39
PB		 3562 return LAST_ARG_REGNUM;
3563
b279b20a
NC		 3564 /* The other case is when we have fixed arguments but less than 4 registers
3565 worth. In this case r3 might be used in the body of the function, but
3566 it is not being used to convey an argument into the function. In theory
38173d38 3567 we could just check crtl->args.size to see how many bytes are
b279b20a
NC		 3568 being passed in argument registers, but it seems that it is unreliable.
3569 Sometimes it will have the value 0 when in fact arguments are being
3570 passed. (See testcase execute/20021111-1.c for an example). So we also
3571 check the args_info.nregs field as well. The problem with this field is
3572 that it makes no allowances for arguments that are passed to the
3573 function but which are not used. Hence we could miss an opportunity
3574 when a function has an unused argument in r3. But it is better to be
3575 safe than to be sorry. */
3576 if (! cfun->machine->uses_anonymous_args
38173d38
JH		 3577 && crtl->args.size >= 0
3578 && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
f6d2671e 3579 && crtl->args.info.nregs < 4)
b279b20a 3580 return LAST_ARG_REGNUM;
e0b92319 3581
b279b20a
NC		 3582 /* Otherwise look for a call-saved register that is going to be pushed. */
3583 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3584 if (pushed_regs_mask & (1 << reg))
57934c39
PB		 3585 return reg;
3586
5b3e6663
PB		 3587 if (TARGET_THUMB2)
3588 {
3589 /* Thumb-2 can use high regs. */
3590 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3591 if (pushed_regs_mask & (1 << reg))
3592 return reg;
3593 }
b279b20a
NC		 3594 /* Something went wrong - thumb_compute_save_reg_mask()
3595 should have arranged for a suitable register to be pushed. */
e6d29d15 3596 gcc_unreachable ();
57934c39
PB		 3597}
3598
f16fe45f 3599static GTY(()) int pic_labelno;
876f13b0 3600
fe013435
PB		 3601/* Generate code to load the PIC register. In thumb mode SCRATCH is a
3602 low register. */
876f13b0 3603
32de079a 3604void
e55ef7f4 3605arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
32de079a 3606{
9403b7f7 3607 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
32de079a
RE		 3608 rtx global_offset_table;
3609
e3b5732b 3610 if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
32de079a
RE		 3611 return;
3612
e6d29d15 3613 gcc_assert (flag_pic);
32de079a 3614
9403b7f7
RS		 3615 pic_reg = cfun->machine->pic_reg;
3616 if (TARGET_VXWORKS_RTP)
3617 {
3618 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
3619 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3620 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
43cffd11 3621
9403b7f7 3622 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
f676971a 3623
9403b7f7
RS		 3624 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
3625 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
4bec9f7d 3626 }
9403b7f7 3627 else
5b3e6663 3628 {
9403b7f7
RS		 3629 /* We use an UNSPEC rather than a LABEL_REF because this label
3630 never appears in the code stream. */
3631
3632 labelno = GEN_INT (pic_labelno++);
3633 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3634 l1 = gen_rtx_CONST (VOIDmode, l1);
3635
3636 global_offset_table
3637 = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3638 /* On the ARM the PC register contains 'dot + 8' at the time of the
3639 addition, on the Thumb it is 'dot + 4'. */
3640 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3641 if (GOT_PCREL)
5b3e6663 3642 {
9403b7f7
RS		 3643 pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
3644 pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
5b3e6663
PB		 3645 }
3646 else
9403b7f7
RS		 3647 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3648
3649 pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
3650 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3651
3652 if (TARGET_ARM)
5b3e6663 3653 {
9403b7f7
RS		 3654 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3655 emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno));
5b3e6663 3656 }
9403b7f7
RS		 3657 else if (TARGET_THUMB2)
3658 {
3659 /* Thumb-2 only allows very limited access to the PC. Calculate the
3660 address in a temporary register. */
3661 if (arm_pic_register != INVALID_REGNUM)
3662 {
3663 pic_tmp = gen_rtx_REG (SImode,
3664 thumb_find_work_register (saved_regs));
3665 }
3666 else
3667 {
b3a13419 3668 gcc_assert (can_create_pseudo_p ());
9403b7f7
RS		 3669 pic_tmp = gen_reg_rtx (Pmode);
3670 }
5b3e6663 3671
9403b7f7
RS		 3672 emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx));
3673 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3674 emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp));
3675 }
3676 else /* TARGET_THUMB1 */
876f13b0 3677 {
9403b7f7
RS		 3678 if (arm_pic_register != INVALID_REGNUM
3679 && REGNO (pic_reg) > LAST_LO_REGNUM)
3680 {
3681 /* We will have pushed the pic register, so we should always be
3682 able to find a work register. */
3683 pic_tmp = gen_rtx_REG (SImode,
3684 thumb_find_work_register (saved_regs));
3685 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3686 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3687 }
3688 else
3689 emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx));
3690 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
876f13b0 3691 }
4bec9f7d 3692 }
32de079a 3693
32de079a
RE		 3694 /* Need to emit this whether or not we obey regdecls,
3695 since setjmp/longjmp can cause life info to screw up. */
c41c1387 3696 emit_use (pic_reg);
32de079a
RE		 3697}
3698
876f13b0 3699
6b990f6b
RE		 3700/* Return nonzero if X is valid as an ARM state addressing register. */
3701static int
e32bac5b 3702arm_address_register_rtx_p (rtx x, int strict_p)
6b990f6b
RE		 3703{
3704 int regno;
3705
3706 if (GET_CODE (x) != REG)
3707 return 0;
3708
3709 regno = REGNO (x);
3710
3711 if (strict_p)
3712 return ARM_REGNO_OK_FOR_BASE_P (regno);
3713
3714 return (regno <= LAST_ARM_REGNUM
3715 || regno >= FIRST_PSEUDO_REGISTER
3716 || regno == FRAME_POINTER_REGNUM
3717 || regno == ARG_POINTER_REGNUM);
3718}
3719
d3585b76
DJ		 3720/* Return TRUE if this rtx is the difference of a symbol and a label,
3721 and will reduce to a PC-relative relocation in the object file.
3722 Expressions like this can be left alone when generating PIC, rather
3723 than forced through the GOT. */
3724static int
3725pcrel_constant_p (rtx x)
3726{
3727 if (GET_CODE (x) == MINUS)
3728 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3729
3730 return FALSE;
3731}
3732
6b990f6b
RE		 3733/* Return nonzero if X is a valid ARM state address operand. */
3734int
1e1ab407
RE		 3735arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3736 int strict_p)
6b990f6b 3737{
fdd695fd
PB		 3738 bool use_ldrd;
3739 enum rtx_code code = GET_CODE (x);
f676971a 3740
6b990f6b
RE		 3741 if (arm_address_register_rtx_p (x, strict_p))
3742 return 1;
3743
fdd695fd
PB		 3744 use_ldrd = (TARGET_LDRD
3745 && (mode == DImode
3746 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3747
3748 if (code == POST_INC || code == PRE_DEC
3749 || ((code == PRE_INC || code == POST_DEC)
3750 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
6b990f6b
RE		 3751 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3752
fdd695fd 3753 else if ((code == POST_MODIFY || code == PRE_MODIFY)
6b990f6b
RE		 3754 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3755 && GET_CODE (XEXP (x, 1)) == PLUS
386d3a16 3756 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
fdd695fd
PB		 3757 {
3758 rtx addend = XEXP (XEXP (x, 1), 1);
3759
112cdef5 3760 /* Don't allow ldrd post increment by register because it's hard
fdd695fd
PB		 3761 to fixup invalid register choices. */
3762 if (use_ldrd
3763 && GET_CODE (x) == POST_MODIFY
3764 && GET_CODE (addend) == REG)
3765 return 0;
3766
3767 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3768 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3769 }
6b990f6b
RE		 3770
3771 /* After reload constants split into minipools will have addresses
3772 from a LABEL_REF. */
0bfb39ef 3773 else if (reload_completed
fdd695fd
PB		 3774 && (code == LABEL_REF
3775 || (code == CONST
6b990f6b
RE		 3776 && GET_CODE (XEXP (x, 0)) == PLUS
3777 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3778 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3779 return 1;
3780
88f77cba 3781 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
6b990f6b
RE		 3782 return 0;
3783
fdd695fd 3784 else if (code == PLUS)
6b990f6b
RE		 3785 {
3786 rtx xop0 = XEXP (x, 0);
3787 rtx xop1 = XEXP (x, 1);
3788
3789 return ((arm_address_register_rtx_p (xop0, strict_p)
1e1ab407 3790 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
6b990f6b 3791 || (arm_address_register_rtx_p (xop1, strict_p)
1e1ab407 3792 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
6b990f6b
RE		 3793 }
3794
3795#if 0
3796 /* Reload currently can't handle MINUS, so disable this for now */
3797 else if (GET_CODE (x) == MINUS)
3798 {
3799 rtx xop0 = XEXP (x, 0);
3800 rtx xop1 = XEXP (x, 1);
3801
3802 return (arm_address_register_rtx_p (xop0, strict_p)
1e1ab407 3803 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
6b990f6b
RE		 3804 }
3805#endif
3806
3807 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
fdd695fd 3808 && code == SYMBOL_REF
6b990f6b
RE		 3809 && CONSTANT_POOL_ADDRESS_P (x)
3810 && ! (flag_pic
d3585b76
DJ		 3811 && symbol_mentioned_p (get_pool_constant (x))
3812 && ! pcrel_constant_p (get_pool_constant (x))))
6b990f6b
RE		 3813 return 1;
3814
6b990f6b
RE		 3815 return 0;
3816}
3817
5b3e6663
PB		 3818/* Return nonzero if X is a valid Thumb-2 address operand. */
3819int
3820thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3821{
3822 bool use_ldrd;
3823 enum rtx_code code = GET_CODE (x);
3824
3825 if (arm_address_register_rtx_p (x, strict_p))
3826 return 1;
3827
3828 use_ldrd = (TARGET_LDRD
3829 && (mode == DImode
3830 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3831
3832 if (code == POST_INC || code == PRE_DEC
3833 || ((code == PRE_INC || code == POST_DEC)
3834 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3835 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3836
3837 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3838 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3839 && GET_CODE (XEXP (x, 1)) == PLUS
3840 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3841 {
3842 /* Thumb-2 only has autoincrement by constant. */
3843 rtx addend = XEXP (XEXP (x, 1), 1);
3844 HOST_WIDE_INT offset;
3845
3846 if (GET_CODE (addend) != CONST_INT)
3847 return 0;
3848
3849 offset = INTVAL(addend);
3850 if (GET_MODE_SIZE (mode) <= 4)
3851 return (offset > -256 && offset < 256);
3852
3853 return (use_ldrd && offset > -1024 && offset < 1024
3854 && (offset & 3) == 0);
3855 }
3856
3857 /* After reload constants split into minipools will have addresses
3858 from a LABEL_REF. */
3859 else if (reload_completed
3860 && (code == LABEL_REF
3861 || (code == CONST
3862 && GET_CODE (XEXP (x, 0)) == PLUS
3863 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3864 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3865 return 1;
3866
88f77cba 3867 else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode)))
5b3e6663
PB		 3868 return 0;
3869
3870 else if (code == PLUS)
3871 {
3872 rtx xop0 = XEXP (x, 0);
3873 rtx xop1 = XEXP (x, 1);
3874
3875 return ((arm_address_register_rtx_p (xop0, strict_p)
3876 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3877 || (arm_address_register_rtx_p (xop1, strict_p)
3878 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3879 }
3880
3881 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3882 && code == SYMBOL_REF
3883 && CONSTANT_POOL_ADDRESS_P (x)
3884 && ! (flag_pic
3885 && symbol_mentioned_p (get_pool_constant (x))
3886 && ! pcrel_constant_p (get_pool_constant (x))))
3887 return 1;
3888
3889 return 0;
3890}
3891
6b990f6b
RE		 3892/* Return nonzero if INDEX is valid for an address index operand in
3893 ARM state. */
3894static int
1e1ab407
RE		 3895arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3896 int strict_p)
6b990f6b
RE		 3897{
3898 HOST_WIDE_INT range;
3899 enum rtx_code code = GET_CODE (index);
3900
778ebdd9
PB		 3901 /* Standard coprocessor addressing modes. */
3902 if (TARGET_HARD_FLOAT
3903 && (TARGET_FPA || TARGET_MAVERICK)
3904 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3905 || (TARGET_MAVERICK && mode == DImode)))
6b990f6b
RE		 3906 return (code == CONST_INT && INTVAL (index) < 1024
3907 && INTVAL (index) > -1024
3908 && (INTVAL (index) & 3) == 0);
3909
88f77cba
JB		 3910 if (TARGET_NEON
3911 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
3912 return (code == CONST_INT
3913 && INTVAL (index) < 1016
3914 && INTVAL (index) > -1024
3915 && (INTVAL (index) & 3) == 0);
3916
5a9335ef
NC		 3917 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3918 return (code == CONST_INT
3657dc3e
PB		 3919 && INTVAL (index) < 1024
3920 && INTVAL (index) > -1024
3921 && (INTVAL (index) & 3) == 0);
5a9335ef 3922
fdd695fd
PB		 3923 if (arm_address_register_rtx_p (index, strict_p)
3924 && (GET_MODE_SIZE (mode) <= 4))
3925 return 1;
3926
3927 if (mode == DImode || mode == DFmode)
3928 {
3929 if (code == CONST_INT)
3930 {
3931 HOST_WIDE_INT val = INTVAL (index);
3932
3933 if (TARGET_LDRD)
3934 return val > -256 && val < 256;
3935 else
f372c932 3936 return val > -4096 && val < 4092;
fdd695fd
PB		 3937 }
3938
3939 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3940 }
3941
6b990f6b 3942 if (GET_MODE_SIZE (mode) <= 4
1e1ab407
RE		 3943 && ! (arm_arch4
3944 && (mode == HImode
3945 || (mode == QImode && outer == SIGN_EXTEND))))
6b990f6b 3946 {
1e1ab407
RE		 3947 if (code == MULT)
3948 {
3949 rtx xiop0 = XEXP (index, 0);
3950 rtx xiop1 = XEXP (index, 1);
3951
3952 return ((arm_address_register_rtx_p (xiop0, strict_p)
3953 && power_of_two_operand (xiop1, SImode))
3954 || (arm_address_register_rtx_p (xiop1, strict_p)
3955 && power_of_two_operand (xiop0, SImode)));
3956 }
3957 else if (code == LSHIFTRT || code == ASHIFTRT
3958 || code == ASHIFT || code == ROTATERT)
3959 {
3960 rtx op = XEXP (index, 1);
6b990f6b 3961
1e1ab407
RE		 3962 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3963 && GET_CODE (op) == CONST_INT
3964 && INTVAL (op) > 0
3965 && INTVAL (op) <= 31);
3966 }
6b990f6b
RE		 3967 }
3968
1e1ab407
RE		 3969 /* For ARM v4 we may be doing a sign-extend operation during the
3970 load. */
e1471c91 3971 if (arm_arch4)
1e1ab407
RE		 3972 {
3973 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3974 range = 256;
3975 else
3976 range = 4096;
3977 }
e1471c91
RE		 3978 else
3979 range = (mode == HImode) ? 4095 : 4096;
6b990f6b
RE		 3980
3981 return (code == CONST_INT
3982 && INTVAL (index) < range
3983 && INTVAL (index) > -range);
76a318e9
RE		 3984}
3985
5b3e6663
PB		 3986/* Return true if OP is a valid index scaling factor for Thumb-2 address
3987 index operand. i.e. 1, 2, 4 or 8. */
3988static bool
3989thumb2_index_mul_operand (rtx op)
3990{
3991 HOST_WIDE_INT val;
3992
3993 if (GET_CODE(op) != CONST_INT)
3994 return false;
3995
3996 val = INTVAL(op);
3997 return (val == 1 || val == 2 || val == 4 || val == 8);
3998}
3999
4000/* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
4001static int
4002thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
4003{
4004 enum rtx_code code = GET_CODE (index);
4005
4006 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
4007 /* Standard coprocessor addressing modes. */
4008 if (TARGET_HARD_FLOAT
4009 && (TARGET_FPA || TARGET_MAVERICK)
4010 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4011 || (TARGET_MAVERICK && mode == DImode)))
4012 return (code == CONST_INT && INTVAL (index) < 1024
4013 && INTVAL (index) > -1024
4014 && (INTVAL (index) & 3) == 0);
4015
4016 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
fe2d934b
PB		 4017 {
4018 /* For DImode assume values will usually live in core regs
4019 and only allow LDRD addressing modes. */
4020 if (!TARGET_LDRD || mode != DImode)
4021 return (code == CONST_INT
4022 && INTVAL (index) < 1024
4023 && INTVAL (index) > -1024
4024 && (INTVAL (index) & 3) == 0);
4025 }
5b3e6663 4026
88f77cba
JB		 4027 if (TARGET_NEON
4028 && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode)))
4029 return (code == CONST_INT
4030 && INTVAL (index) < 1016
4031 && INTVAL (index) > -1024
4032 && (INTVAL (index) & 3) == 0);
4033
5b3e6663
PB		 4034 if (arm_address_register_rtx_p (index, strict_p)
4035 && (GET_MODE_SIZE (mode) <= 4))
4036 return 1;
4037
4038 if (mode == DImode || mode == DFmode)
4039 {
4040 HOST_WIDE_INT val = INTVAL (index);
4041 /* ??? Can we assume ldrd for thumb2? */
4042 /* Thumb-2 ldrd only has reg+const addressing modes. */
4043 if (code != CONST_INT)
4044 return 0;
4045
4046 /* ldrd supports offsets of +-1020.
4047 However the ldr fallback does not. */
4048 return val > -256 && val < 256 && (val & 3) == 0;
4049 }
4050
4051 if (code == MULT)
4052 {
4053 rtx xiop0 = XEXP (index, 0);
4054 rtx xiop1 = XEXP (index, 1);
4055
4056 return ((arm_address_register_rtx_p (xiop0, strict_p)
4057 && thumb2_index_mul_operand (xiop1))
4058 || (arm_address_register_rtx_p (xiop1, strict_p)
4059 && thumb2_index_mul_operand (xiop0)));
4060 }
4061 else if (code == ASHIFT)
4062 {
4063 rtx op = XEXP (index, 1);
4064
4065 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
4066 && GET_CODE (op) == CONST_INT
4067 && INTVAL (op) > 0
4068 && INTVAL (op) <= 3);
4069 }
4070
4071 return (code == CONST_INT
4072 && INTVAL (index) < 4096
4073 && INTVAL (index) > -256);
4074}
4075
4076/* Return nonzero if X is valid as a 16-bit Thumb state base register. */
76a318e9 4077static int
5b3e6663 4078thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
76a318e9
RE		 4079{
4080 int regno;
4081
4082 if (GET_CODE (x) != REG)
4083 return 0;
4084
4085 regno = REGNO (x);
4086
4087 if (strict_p)
5b3e6663 4088 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
76a318e9
RE		 4089
4090 return (regno <= LAST_LO_REGNUM
07e58265 4091 || regno > LAST_VIRTUAL_REGISTER
76a318e9
RE		 4092 || regno == FRAME_POINTER_REGNUM
4093 || (GET_MODE_SIZE (mode) >= 4
4094 && (regno == STACK_POINTER_REGNUM
edf7cee8 4095 || regno >= FIRST_PSEUDO_REGISTER
76a318e9
RE		 4096 || x == hard_frame_pointer_rtx
4097 || x == arg_pointer_rtx)));
4098}
4099
4100/* Return nonzero if x is a legitimate index register. This is the case
4101 for any base register that can access a QImode object. */
4102inline static int
5b3e6663 4103thumb1_index_register_rtx_p (rtx x, int strict_p)
76a318e9 4104{
5b3e6663 4105 return thumb1_base_register_rtx_p (x, QImode, strict_p);
76a318e9
RE		 4106}
4107
5b3e6663 4108/* Return nonzero if x is a legitimate 16-bit Thumb-state address.
f676971a 4109
76a318e9
RE		 4110 The AP may be eliminated to either the SP or the FP, so we use the
4111 least common denominator, e.g. SImode, and offsets from 0 to 64.
4112
4113 ??? Verify whether the above is the right approach.
4114
4115 ??? Also, the FP may be eliminated to the SP, so perhaps that
4116 needs special handling also.
4117
4118 ??? Look at how the mips16 port solves this problem. It probably uses
4119 better ways to solve some of these problems.
4120
4121 Although it is not incorrect, we don't accept QImode and HImode
4122 addresses based on the frame pointer or arg pointer until the
4123 reload pass starts. This is so that eliminating such addresses
4124 into stack based ones won't produce impossible code. */
4125int
5b3e6663 4126thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
76a318e9
RE		 4127{
4128 /* ??? Not clear if this is right. Experiment. */
4129 if (GET_MODE_SIZE (mode) < 4
4130 && !(reload_in_progress || reload_completed)
4131 && (reg_mentioned_p (frame_pointer_rtx, x)
4132 || reg_mentioned_p (arg_pointer_rtx, x)
4133 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4134 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4135 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4136 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4137 return 0;
4138
4139 /* Accept any base register. SP only in SImode or larger. */
5b3e6663 4140 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
76a318e9
RE		 4141 return 1;
4142
18dbd950 4143 /* This is PC relative data before arm_reorg runs. */
76a318e9
RE		 4144 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4145 && GET_CODE (x) == SYMBOL_REF
020a4035 4146 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
76a318e9
RE		 4147 return 1;
4148
18dbd950 4149 /* This is PC relative data after arm_reorg runs. */
76a318e9
RE		 4150 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4151 && (GET_CODE (x) == LABEL_REF
4152 || (GET_CODE (x) == CONST
4153 && GET_CODE (XEXP (x, 0)) == PLUS
4154 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4155 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4156 return 1;
4157
4158 /* Post-inc indexing only supported for SImode and larger. */
4159 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
5b3e6663 4160 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
76a318e9
RE		 4161 return 1;
4162
4163 else if (GET_CODE (x) == PLUS)
4164 {
4165 /* REG+REG address can be any two index registers. */
4166 /* We disallow FRAME+REG addressing since we know that FRAME
4167 will be replaced with STACK, and SP relative addressing only
4168 permits SP+OFFSET. */
4169 if (GET_MODE_SIZE (mode) <= 4
4170 && XEXP (x, 0) != frame_pointer_rtx
4171 && XEXP (x, 1) != frame_pointer_rtx
5b3e6663
PB		 4172 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4173 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
76a318e9
RE		 4174 return 1;
4175
4176 /* REG+const has 5-7 bit offset for non-SP registers. */
5b3e6663 4177 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
76a318e9
RE		 4178 || XEXP (x, 0) == arg_pointer_rtx)
4179 && GET_CODE (XEXP (x, 1)) == CONST_INT
4180 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4181 return 1;
4182
a50aa827 4183 /* REG+const has 10-bit offset for SP, but only SImode and
76a318e9
RE		 4184 larger is supported. */
4185 /* ??? Should probably check for DI/DFmode overflow here
4186 just like GO_IF_LEGITIMATE_OFFSET does. */
4187 else if (GET_CODE (XEXP (x, 0)) == REG
4188 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4189 && GET_MODE_SIZE (mode) >= 4
4190 && GET_CODE (XEXP (x, 1)) == CONST_INT
4191 && INTVAL (XEXP (x, 1)) >= 0
4192 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4193 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4194 return 1;
4195
4196 else if (GET_CODE (XEXP (x, 0)) == REG
c5289e45
RE		 4197 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4198 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4199 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4200 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
76a318e9
RE		 4201 && GET_MODE_SIZE (mode) >= 4
4202 && GET_CODE (XEXP (x, 1)) == CONST_INT
4203 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4204 return 1;
4205 }
4206
4207 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
f954388e 4208 && GET_MODE_SIZE (mode) == 4
76a318e9
RE		 4209 && GET_CODE (x) == SYMBOL_REF
4210 && CONSTANT_POOL_ADDRESS_P (x)
d3585b76
DJ		 4211 && ! (flag_pic
4212 && symbol_mentioned_p (get_pool_constant (x))
4213 && ! pcrel_constant_p (get_pool_constant (x))))
76a318e9
RE		 4214 return 1;
4215
4216 return 0;
4217}
4218
4219/* Return nonzero if VAL can be used as an offset in a Thumb-state address
4220 instruction of mode MODE. */
4221int
e32bac5b 4222thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
76a318e9
RE		 4223{
4224 switch (GET_MODE_SIZE (mode))
4225 {
4226 case 1:
4227 return val >= 0 && val < 32;
4228
4229 case 2:
4230 return val >= 0 && val < 64 && (val & 1) == 0;
4231
4232 default:
4233 return (val >= 0
4234 && (val + GET_MODE_SIZE (mode)) <= 128
4235 && (val & 3) == 0);
4236 }
4237}
4238
d3585b76
DJ		 4239/* Build the SYMBOL_REF for __tls_get_addr. */
4240
4241static GTY(()) rtx tls_get_addr_libfunc;
4242
4243static rtx
4244get_tls_get_addr (void)
4245{
4246 if (!tls_get_addr_libfunc)
4247 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4248 return tls_get_addr_libfunc;
4249}
4250
4251static rtx
4252arm_load_tp (rtx target)
4253{
4254 if (!target)
4255 target = gen_reg_rtx (SImode);
4256
4257 if (TARGET_HARD_TP)
4258 {
4259 /* Can return in any reg. */
4260 emit_insn (gen_load_tp_hard (target));
4261 }
4262 else
4263 {
4264 /* Always returned in r0. Immediately copy the result into a pseudo,
4265 otherwise other uses of r0 (e.g. setting up function arguments) may
4266 clobber the value. */
4267
4268 rtx tmp;
4269
4270 emit_insn (gen_load_tp_soft ());
4271
4272 tmp = gen_rtx_REG (SImode, 0);
4273 emit_move_insn (target, tmp);
4274 }
4275 return target;
4276}
4277
4278static rtx
4279load_tls_operand (rtx x, rtx reg)
4280{
4281 rtx tmp;
4282
4283 if (reg == NULL_RTX)
4284 reg = gen_reg_rtx (SImode);
4285
4286 tmp = gen_rtx_CONST (SImode, x);
4287
4288 emit_move_insn (reg, tmp);
4289
4290 return reg;
4291}
4292
4293static rtx
4294arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4295{
f16fe45f 4296 rtx insns, label, labelno, sum;
d3585b76
DJ		 4297
4298 start_sequence ();
4299
f16fe45f
DJ		 4300 labelno = GEN_INT (pic_labelno++);
4301 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4302 label = gen_rtx_CONST (VOIDmode, label);
4303
d3585b76 4304 sum = gen_rtx_UNSPEC (Pmode,
f16fe45f 4305 gen_rtvec (4, x, GEN_INT (reloc), label,
d3585b76
DJ		 4306 GEN_INT (TARGET_ARM ? 8 : 4)),
4307 UNSPEC_TLS);
4308 reg = load_tls_operand (sum, reg);
4309
4310 if (TARGET_ARM)
f16fe45f 4311 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
5b3e6663
PB		 4312 else if (TARGET_THUMB2)
4313 {
4314 rtx tmp;
4315 /* Thumb-2 only allows very limited access to the PC. Calculate
4316 the address in a temporary register. */
4317 tmp = gen_reg_rtx (SImode);
4318 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4319 emit_insn (gen_addsi3(reg, reg, tmp));
4320 }
4321 else /* TARGET_THUMB1 */
f16fe45f 4322 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
d3585b76
DJ		 4323
4324 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4325 Pmode, 1, reg, Pmode);
4326
4327 insns = get_insns ();
4328 end_sequence ();
4329
4330 return insns;
4331}
4332
4333rtx
4334legitimize_tls_address (rtx x, rtx reg)
4335{
f16fe45f 4336 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
d3585b76
DJ		 4337 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4338
4339 switch (model)
4340 {
4341 case TLS_MODEL_GLOBAL_DYNAMIC:
4342 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4343 dest = gen_reg_rtx (Pmode);
4344 emit_libcall_block (insns, dest, ret, x);
4345 return dest;
4346
4347 case TLS_MODEL_LOCAL_DYNAMIC:
4348 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4349
4350 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4351 share the LDM result with other LD model accesses. */
4352 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4353 UNSPEC_TLS);
4354 dest = gen_reg_rtx (Pmode);
e66e1c68 4355 emit_libcall_block (insns, dest, ret, eqv);
d3585b76
DJ		 4356
4357 /* Load the addend. */
4358 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4359 UNSPEC_TLS);
4360 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4361 return gen_rtx_PLUS (Pmode, dest, addend);
4362
4363 case TLS_MODEL_INITIAL_EXEC:
f16fe45f
DJ		 4364 labelno = GEN_INT (pic_labelno++);
4365 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4366 label = gen_rtx_CONST (VOIDmode, label);
d3585b76 4367 sum = gen_rtx_UNSPEC (Pmode,
f16fe45f 4368 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
d3585b76
DJ		 4369 GEN_INT (TARGET_ARM ? 8 : 4)),
4370 UNSPEC_TLS);
4371 reg = load_tls_operand (sum, reg);
4372
4373 if (TARGET_ARM)
f16fe45f 4374 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
5b3e6663
PB		 4375 else if (TARGET_THUMB2)
4376 {
4377 rtx tmp;
4378 /* Thumb-2 only allows very limited access to the PC. Calculate
4379 the address in a temporary register. */
4380 tmp = gen_reg_rtx (SImode);
4381 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4382 emit_insn (gen_addsi3(reg, reg, tmp));
4383 emit_move_insn (reg, gen_const_mem (SImode, reg));
4384 }
d3585b76
DJ		 4385 else
4386 {
f16fe45f 4387 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
d3585b76
DJ		 4388 emit_move_insn (reg, gen_const_mem (SImode, reg));
4389 }
4390
4391 tp = arm_load_tp (NULL_RTX);
4392
4393 return gen_rtx_PLUS (Pmode, tp, reg);
4394
4395 case TLS_MODEL_LOCAL_EXEC:
4396 tp = arm_load_tp (NULL_RTX);
4397
4398 reg = gen_rtx_UNSPEC (Pmode,
4399 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4400 UNSPEC_TLS);
4401 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4402
4403 return gen_rtx_PLUS (Pmode, tp, reg);
4404
4405 default:
4406 abort ();
4407 }
4408}
4409
ccf4d512
RE		 4410/* Try machine-dependent ways of modifying an illegitimate address
4411 to be legitimate. If we find one, return the new, valid address. */
ccf4d512 4412rtx
e32bac5b 4413arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
ccf4d512 4414{
d3585b76
DJ		 4415 if (arm_tls_symbol_p (x))
4416 return legitimize_tls_address (x, NULL_RTX);
4417
ccf4d512
RE		 4418 if (GET_CODE (x) == PLUS)
4419 {
4420 rtx xop0 = XEXP (x, 0);
4421 rtx xop1 = XEXP (x, 1);
4422
4423 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4424 xop0 = force_reg (SImode, xop0);
4425
4426 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4427 xop1 = force_reg (SImode, xop1);
4428
4429 if (ARM_BASE_REGISTER_RTX_P (xop0)
4430 && GET_CODE (xop1) == CONST_INT)
4431 {
4432 HOST_WIDE_INT n, low_n;
4433 rtx base_reg, val;
4434 n = INTVAL (xop1);
4435
9b66ebb1
PB		 4436 /* VFP addressing modes actually allow greater offsets, but for
4437 now we just stick with the lowest common denominator. */
4438 if (mode == DImode
4439 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
ccf4d512
RE		 4440 {
4441 low_n = n & 0x0f;
4442 n &= ~0x0f;
4443 if (low_n > 4)
4444 {
4445 n += 16;
4446 low_n -= 16;
4447 }
4448 }
4449 else
4450 {
4451 low_n = ((mode) == TImode ? 0
4452 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4453 n -= low_n;
4454 }
4455
4456 base_reg = gen_reg_rtx (SImode);
d66437c5 4457 val = force_operand (plus_constant (xop0, n), NULL_RTX);
ccf4d512 4458 emit_move_insn (base_reg, val);
d66437c5 4459 x = plus_constant (base_reg, low_n);
ccf4d512
RE		 4460 }
4461 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4462 x = gen_rtx_PLUS (SImode, xop0, xop1);
4463 }
4464
4465 /* XXX We don't allow MINUS any more -- see comment in
4466 arm_legitimate_address_p (). */
4467 else if (GET_CODE (x) == MINUS)
4468 {
4469 rtx xop0 = XEXP (x, 0);
4470 rtx xop1 = XEXP (x, 1);
4471
4472 if (CONSTANT_P (xop0))
4473 xop0 = force_reg (SImode, xop0);
4474
4475 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4476 xop1 = force_reg (SImode, xop1);
4477
4478 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4479 x = gen_rtx_MINUS (SImode, xop0, xop1);
4480 }
4481
86805759
NP		 4482 /* Make sure to take full advantage of the pre-indexed addressing mode
4483 with absolute addresses which often allows for the base register to
4484 be factorized for multiple adjacent memory references, and it might
4485 even allows for the mini pool to be avoided entirely. */
4486 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4487 {
4488 unsigned int bits;
4489 HOST_WIDE_INT mask, base, index;
4490 rtx base_reg;
4491
a50aa827
KH		 4492 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4493 use a 8-bit index. So let's use a 12-bit index for SImode only and
86805759
NP		 4494 hope that arm_gen_constant will enable ldrb to use more bits. */
4495 bits = (mode == SImode) ? 12 : 8;
4496 mask = (1 << bits) - 1;
4497 base = INTVAL (x) & ~mask;
4498 index = INTVAL (x) & mask;
b107d743 4499 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
86805759
NP		 4500 {
4501 /* It'll most probably be more efficient to generate the base
4502 with more bits set and use a negative index instead. */
4503 base |= mask;
4504 index -= mask;
4505 }
4506 base_reg = force_reg (SImode, GEN_INT (base));
d66437c5 4507 x = plus_constant (base_reg, index);
86805759
NP		 4508 }
4509
ccf4d512
RE		 4510 if (flag_pic)
4511 {
4512 /* We need to find and carefully transform any SYMBOL and LABEL
4513 references; so go back to the original address expression. */
4514 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4515
4516 if (new_x != orig_x)
4517 x = new_x;
4518 }
4519
4520 return x;
4521}
4522
6f5b4f3e
RE		 4523
4524/* Try machine-dependent ways of modifying an illegitimate Thumb address
4525 to be legitimate. If we find one, return the new, valid address. */
4526rtx
4527thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4528{
d3585b76
DJ		 4529 if (arm_tls_symbol_p (x))
4530 return legitimize_tls_address (x, NULL_RTX);
4531
6f5b4f3e
RE		 4532 if (GET_CODE (x) == PLUS
4533 && GET_CODE (XEXP (x, 1)) == CONST_INT
4534 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4535 || INTVAL (XEXP (x, 1)) < 0))
4536 {
4537 rtx xop0 = XEXP (x, 0);
4538 rtx xop1 = XEXP (x, 1);
4539 HOST_WIDE_INT offset = INTVAL (xop1);
4540
4541 /* Try and fold the offset into a biasing of the base register and
4542 then offsetting that. Don't do this when optimizing for space
4543 since it can cause too many CSEs. */
4544 if (optimize_size && offset >= 0
4545 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4546 {
4547 HOST_WIDE_INT delta;
4548
4549 if (offset >= 256)
4550 delta = offset - (256 - GET_MODE_SIZE (mode));
4551 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4552 delta = 31 * GET_MODE_SIZE (mode);
4553 else
4554 delta = offset & (~31 * GET_MODE_SIZE (mode));
4555
4556 xop0 = force_operand (plus_constant (xop0, offset - delta),
4557 NULL_RTX);
4558 x = plus_constant (xop0, delta);
4559 }
4560 else if (offset < 0 && offset > -256)
4561 /* Small negative offsets are best done with a subtract before the
4562 dereference, forcing these into a register normally takes two
4563 instructions. */
4564 x = force_operand (x, NULL_RTX);
4565 else
4566 {
4567 /* For the remaining cases, force the constant into a register. */
4568 xop1 = force_reg (SImode, xop1);
4569 x = gen_rtx_PLUS (SImode, xop0, xop1);
4570 }
4571 }
4572 else if (GET_CODE (x) == PLUS
4573 && s_register_operand (XEXP (x, 1), SImode)
4574 && !s_register_operand (XEXP (x, 0), SImode))
4575 {
4576 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4577
4578 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4579 }
4580
4581 if (flag_pic)
4582 {
4583 /* We need to find and carefully transform any SYMBOL and LABEL
4584 references; so go back to the original address expression. */
4585 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4586
4587 if (new_x != orig_x)
4588 x = new_x;
4589 }
4590
4591 return x;
4592}
4593
a132dad6 4594rtx
e0b92319
NC		 4595thumb_legitimize_reload_address (rtx *x_p,
4596 enum machine_mode mode,
4597 int opnum, int type,
4598 int ind_levels ATTRIBUTE_UNUSED)
a132dad6
RE		 4599{
4600 rtx x = *x_p;
e0b92319 4601
a132dad6
RE		 4602 if (GET_CODE (x) == PLUS
4603 && GET_MODE_SIZE (mode) < 4
4604 && REG_P (XEXP (x, 0))
4605 && XEXP (x, 0) == stack_pointer_rtx
4606 && GET_CODE (XEXP (x, 1)) == CONST_INT
4607 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4608 {
4609 rtx orig_x = x;
4610
4611 x = copy_rtx (x);
4612 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4613 Pmode, VOIDmode, 0, 0, opnum, type);
4614 return x;
4615 }
4616
4617 /* If both registers are hi-regs, then it's better to reload the
4618 entire expression rather than each register individually. That
4619 only requires one reload register rather than two. */
4620 if (GET_CODE (x) == PLUS
4621 && REG_P (XEXP (x, 0))
4622 && REG_P (XEXP (x, 1))
4623 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4624 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4625 {
4626 rtx orig_x = x;
4627
4628 x = copy_rtx (x);
4629 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4630 Pmode, VOIDmode, 0, 0, opnum, type);
4631 return x;
4632 }
4633
4634 return NULL;
4635}
d3585b76
DJ		 4636
4637/* Test for various thread-local symbols. */
4638
4639/* Return TRUE if X is a thread-local symbol. */
4640
4641static bool
4642arm_tls_symbol_p (rtx x)
4643{
4644 if (! TARGET_HAVE_TLS)
4645 return false;
4646
4647 if (GET_CODE (x) != SYMBOL_REF)
4648 return false;
4649
4650 return SYMBOL_REF_TLS_MODEL (x) != 0;
4651}
4652
4653/* Helper for arm_tls_referenced_p. */
4654
4655static int
4656arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4657{
4658 if (GET_CODE (*x) == SYMBOL_REF)
4659 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4660
4661 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4662 TLS offsets, not real symbol references. */
4663 if (GET_CODE (*x) == UNSPEC
4664 && XINT (*x, 1) == UNSPEC_TLS)
4665 return -1;
4666
4667 return 0;
4668}
4669
4670/* Return TRUE if X contains any TLS symbol references. */
4671
4672bool
4673arm_tls_referenced_p (rtx x)
4674{
4675 if (! TARGET_HAVE_TLS)
4676 return false;
4677
4678 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4679}
8426b956
RS		 4680
4681/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
4682
4683bool
4684arm_cannot_force_const_mem (rtx x)
4685{
4686 rtx base, offset;
4687
4688 if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
4689 {
4690 split_const (x, &base, &offset);
4691 if (GET_CODE (base) == SYMBOL_REF
4692 && !offset_within_block_p (base, INTVAL (offset)))
4693 return true;
4694 }
4695 return arm_tls_referenced_p (x);
4696}
6b990f6b 4697\f
e2c671ba
RE		 4698#define REG_OR_SUBREG_REG(X) \
4699 (GET_CODE (X) == REG \
4700 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4701
4702#define REG_OR_SUBREG_RTX(X) \
4703 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4704
d5b7b3ae
RE		 4705#ifndef COSTS_N_INSNS
4706#define COSTS_N_INSNS(N) ((N) * 4 - 2)
4707#endif
3c50106f 4708static inline int
5b3e6663 4709thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
e2c671ba
RE		 4710{
4711 enum machine_mode mode = GET_MODE (x);
e2c671ba 4712
9b66ebb1 4713 switch (code)
d5b7b3ae 4714 {
9b66ebb1
PB		 4715 case ASHIFT:
4716 case ASHIFTRT:
4717 case LSHIFTRT:
f676971a 4718 case ROTATERT:
9b66ebb1
PB		 4719 case PLUS:
4720 case MINUS:
4721 case COMPARE:
4722 case NEG:
f676971a 4723 case NOT:
9b66ebb1 4724 return COSTS_N_INSNS (1);
f676971a
EC		 4725
4726 case MULT:
4727 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4728 {
4729 int cycles = 0;
9b66ebb1 4730 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
f676971a
EC		 4731
4732 while (i)
4733 {
4734 i >>= 2;
4735 cycles++;
4736 }
4737 return COSTS_N_INSNS (2) + cycles;
9b66ebb1
PB		 4738 }
4739 return COSTS_N_INSNS (1) + 16;
f676971a
EC		 4740
4741 case SET:
4742 return (COSTS_N_INSNS (1)
4743 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
9b66ebb1 4744 + GET_CODE (SET_DEST (x)) == MEM));
f676971a
EC		 4745
4746 case CONST_INT:
4747 if (outer == SET)
4748 {
4749 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4750 return 0;
4751 if (thumb_shiftable_const (INTVAL (x)))
4752 return COSTS_N_INSNS (2);
4753 return COSTS_N_INSNS (3);
4754 }
9b66ebb1 4755 else if ((outer == PLUS || outer == COMPARE)
f676971a 4756 && INTVAL (x) < 256 && INTVAL (x) > -256)
9b66ebb1
PB		 4757 return 0;
4758 else if (outer == AND
4759 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4760 return COSTS_N_INSNS (1);
f676971a
EC		 4761 else if (outer == ASHIFT || outer == ASHIFTRT
4762 || outer == LSHIFTRT)
4763 return 0;
9b66ebb1 4764 return COSTS_N_INSNS (2);
f676971a
EC		 4765
4766 case CONST:
4767 case CONST_DOUBLE:
4768 case LABEL_REF:
4769 case SYMBOL_REF:
9b66ebb1 4770 return COSTS_N_INSNS (3);
f676971a 4771
9b66ebb1
PB		 4772 case UDIV:
4773 case UMOD:
4774 case DIV:
4775 case MOD:
4776 return 100;
d5b7b3ae 4777
9b66ebb1
PB		 4778 case TRUNCATE:
4779 return 99;
d5b7b3ae 4780
9b66ebb1
PB		 4781 case AND:
4782 case XOR:
f676971a 4783 case IOR:
ff482c8d 4784 /* XXX guess. */
9b66ebb1 4785 return 8;
d5b7b3ae 4786
9b66ebb1
PB		 4787 case MEM:
4788 /* XXX another guess. */
4789 /* Memory costs quite a lot for the first word, but subsequent words
4790 load at the equivalent of a single insn each. */
4791 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4792 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4793 ? 4 : 0));
4794
4795 case IF_THEN_ELSE:
ff482c8d 4796 /* XXX a guess. */
9b66ebb1
PB		 4797 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4798 return 14;
4799 return 2;
4800
4801 case ZERO_EXTEND:
4802 /* XXX still guessing. */
4803 switch (GET_MODE (XEXP (x, 0)))
4804 {
4805 case QImode:
4806 return (1 + (mode == DImode ? 4 : 0)
4807 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
f676971a 4808
9b66ebb1
PB		 4809 case HImode:
4810 return (4 + (mode == DImode ? 4 : 0)
4811 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
f676971a 4812
9b66ebb1
PB		 4813 case SImode:
4814 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
f676971a 4815
d5b7b3ae
RE		 4816 default:
4817 return 99;
d5b7b3ae 4818 }
f676971a 4819
9b66ebb1
PB		 4820 default:
4821 return 99;
d5b7b3ae 4822 }
9b66ebb1
PB		 4823}
4824
4825
4826/* Worker routine for arm_rtx_costs. */
5b3e6663 4827/* ??? This needs updating for thumb2. */
9b66ebb1
PB		 4828static inline int
4829arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4830{
4831 enum machine_mode mode = GET_MODE (x);
4832 enum rtx_code subcode;
4833 int extra_cost;
4834
e2c671ba
RE		 4835 switch (code)
4836 {
4837 case MEM:
4838 /* Memory costs quite a lot for the first word, but subsequent words
4839 load at the equivalent of a single insn each. */
4840 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
48f6efae
NC		 4841 + (GET_CODE (x) == SYMBOL_REF
4842 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
e2c671ba
RE		 4843
4844 case DIV:
4845 case MOD:
b9c53150
RS		 4846 case UDIV:
4847 case UMOD:
4848 return optimize_size ? COSTS_N_INSNS (2) : 100;
e2c671ba
RE		 4849
4850 case ROTATE:
4851 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4852 return 4;
4853 /* Fall through */
4854 case ROTATERT:
4855 if (mode != SImode)
4856 return 8;
4857 /* Fall through */
4858 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4859 if (mode == DImode)
4860 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
f676971a 4861 + ((GET_CODE (XEXP (x, 0)) == REG
e2c671ba
RE		 4862 || (GET_CODE (XEXP (x, 0)) == SUBREG
4863 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4864 ? 0 : 8));
4865 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4866 || (GET_CODE (XEXP (x, 0)) == SUBREG
4867 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4868 ? 0 : 4)
4869 + ((GET_CODE (XEXP (x, 1)) == REG
4870 || (GET_CODE (XEXP (x, 1)) == SUBREG
4871 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4872 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4873 ? 0 : 4));
4874
4875 case MINUS:
26b53f80
PB		 4876 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4877 {
4878 extra_cost = rtx_cost (XEXP (x, 1), code);
4879 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4880 extra_cost += 4 * ARM_NUM_REGS (mode);
4881 return extra_cost;
4882 }
4883
e2c671ba
RE		 4884 if (mode == DImode)
4885 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4886 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4887 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4888 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4889 ? 0 : 8));
4890
4891 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4892 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4893 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
9b66ebb1 4894 && arm_const_double_rtx (XEXP (x, 1))))
e2c671ba
RE		 4895 ? 0 : 8)
4896 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4897 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
9b66ebb1 4898 && arm_const_double_rtx (XEXP (x, 0))))
e2c671ba
RE		 4899 ? 0 : 8));
4900
4901 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4902 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4903 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4904 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4905 || subcode == ASHIFTRT || subcode == LSHIFTRT
4906 || subcode == ROTATE || subcode == ROTATERT
4907 || (subcode == MULT
4908 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4909 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4910 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4911 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4912 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4913 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4914 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4915 return 1;
4916 /* Fall through */
4917
f676971a 4918 case PLUS:
ff069900
PB		 4919 if (arm_arch6 && mode == SImode
4920 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4921 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4922 return 1 + (GET_CODE (XEXP (XEXP (x, 0), 0)) == MEM ? 10 : 0)
4923 + (GET_CODE (XEXP (x, 1)) == MEM ? 10 : 0);
4924
26da58dd
PB		 4925 if (GET_CODE (XEXP (x, 0)) == MULT)
4926 {
4927 extra_cost = rtx_cost (XEXP (x, 0), code);
4928 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4929 extra_cost += 4 * ARM_NUM_REGS (mode);
4930 return extra_cost;
4931 }
4932
e2c671ba
RE		 4933 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4934 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4935 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4936 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
9b66ebb1 4937 && arm_const_double_rtx (XEXP (x, 1))))
e2c671ba
RE		 4938 ? 0 : 8));
4939
4940 /* Fall through */
f676971a 4941 case AND: case XOR: case IOR:
e2c671ba
RE		 4942 extra_cost = 0;
4943
4944 /* Normally the frame registers will be spilt into reg+const during
4945 reload, so it is a bad idea to combine them with other instructions,
4946 since then they might not be moved outside of loops. As a compromise
4947 we allow integration with ops that have a constant as their second
4948 operand. */
4949 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4950 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4951 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4952 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4953 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4954 extra_cost = 4;
4955
4956 if (mode == DImode)
4957 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4958 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4959 || (GET_CODE (XEXP (x, 1)) == CONST_INT
74bbc178 4960 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
e2c671ba
RE		 4961 ? 0 : 8));
4962
4963 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4964 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4965 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4966 || (GET_CODE (XEXP (x, 1)) == CONST_INT
74bbc178 4967 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
e2c671ba
RE		 4968 ? 0 : 4));
4969
4970 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4971 return (1 + extra_cost
4972 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4973 || subcode == LSHIFTRT || subcode == ASHIFTRT
4974 || subcode == ROTATE || subcode == ROTATERT
4975 || (subcode == MULT
4976 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4977 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
ad076f4e 4978 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
e2c671ba
RE		 4979 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4980 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
ad076f4e 4981 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
e2c671ba
RE		 4982 ? 0 : 4));
4983
4984 return 8;
4985
4986 case MULT:
9b66ebb1 4987 /* This should have been handled by the CPU specific routines. */
e6d29d15 4988 gcc_unreachable ();
e2c671ba 4989
56636818 4990 case TRUNCATE:
9b66ebb1 4991 if (arm_arch3m && mode == SImode
56636818
JL		 4992 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4993 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4994 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4995 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4996 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4997 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4998 return 8;
4999 return 99;
5000
e2c671ba
RE		 5001 case NEG:
5002 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5003 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
5004 /* Fall through */
5005 case NOT:
5006 if (mode == DImode)
5007 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
5008
5009 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
5010
5011 case IF_THEN_ELSE:
5012 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
5013 return 14;
5014 return 2;
5015
5016 case COMPARE:
5017 return 1;
5018
5019 case ABS:
5020 return 4 + (mode == DImode ? 4 : 0);
5021
5022 case SIGN_EXTEND:
ff069900
PB		 5023 if (arm_arch_thumb2 && mode == SImode)
5024 return 1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0);
5025
e2c671ba
RE		 5026 if (GET_MODE (XEXP (x, 0)) == QImode)
5027 return (4 + (mode == DImode ? 4 : 0)
5028 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5029 /* Fall through */
5030 case ZERO_EXTEND:
ff069900
PB		 5031 if (arm_arch6 && mode == SImode)
5032 return 1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0);
5033
e2c671ba
RE		 5034 switch (GET_MODE (XEXP (x, 0)))
5035 {
5036 case QImode:
5037 return (1 + (mode == DImode ? 4 : 0)
5038 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5039
5040 case HImode:
5041 return (4 + (mode == DImode ? 4 : 0)
5042 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5043
5044 case SImode:
5045 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
ad076f4e 5046
5a9335ef
NC		 5047 case V8QImode:
5048 case V4HImode:
5049 case V2SImode:
5050 case V4QImode:
5051 case V2HImode:
5052 return 1;
5053
ad076f4e 5054 default:
e6d29d15 5055 gcc_unreachable ();
e2c671ba 5056 }
e6d29d15 5057 gcc_unreachable ();
e2c671ba 5058
f676971a
EC		 5059 case CONST_INT:
5060 if (const_ok_for_arm (INTVAL (x)))
5061 return outer == SET ? 2 : -1;
5062 else if (outer == AND
5063 && const_ok_for_arm (~INTVAL (x)))
5064 return -1;
5065 else if ((outer == COMPARE
5066 || outer == PLUS || outer == MINUS)
5067 && const_ok_for_arm (-INTVAL (x)))
5068 return -1;
5069 else
d5b7b3ae 5070 return 5;
f676971a
EC		 5071
5072 case CONST:
5073 case LABEL_REF:
5074 case SYMBOL_REF:
d5b7b3ae 5075 return 6;
f676971a
EC		 5076
5077 case CONST_DOUBLE:
f1adb0a9 5078 if (arm_const_double_rtx (x) || vfp3_const_double_rtx (x))
f676971a
EC		 5079 return outer == SET ? 2 : -1;
5080 else if ((outer == COMPARE || outer == PLUS)
5081 && neg_const_double_rtx_ok_for_fpa (x))
5082 return -1;
d5b7b3ae 5083 return 7;
f676971a 5084
e2c671ba
RE		 5085 default:
5086 return 99;
5087 }
5088}
32de079a 5089
21b5653c
RE		 5090/* RTX costs when optimizing for size. */
5091static bool
5092arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
5093{
5094 enum machine_mode mode = GET_MODE (x);
5095
09754904 5096 if (TARGET_THUMB1)
21b5653c
RE		 5097 {
5098 /* XXX TBD. For now, use the standard costs. */
5b3e6663 5099 *total = thumb1_rtx_costs (x, code, outer_code);
21b5653c
RE		 5100 return true;
5101 }
5102
09754904 5103 /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */
21b5653c
RE		 5104 switch (code)
5105 {
5106 case MEM:
f676971a 5107 /* A memory access costs 1 insn if the mode is small, or the address is
21b5653c
RE		 5108 a single register, otherwise it costs one insn per word. */
5109 if (REG_P (XEXP (x, 0)))
5110 *total = COSTS_N_INSNS (1);
5111 else
5112 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5113 return true;
5114
5115 case DIV:
5116 case MOD:
5117 case UDIV:
5118 case UMOD:
5119 /* Needs a libcall, so it costs about this. */
5120 *total = COSTS_N_INSNS (2);
5121 return false;
5122
5123 case ROTATE:
5124 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
5125 {
5126 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
5127 return true;
5128 }
5129 /* Fall through */
5130 case ROTATERT:
5131 case ASHIFT:
5132 case LSHIFTRT:
5133 case ASHIFTRT:
5134 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
5135 {
5136 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
5137 return true;
5138 }
5139 else if (mode == SImode)
5140 {
5141 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5142 /* Slightly disparage register shifts, but not by much. */
5143 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5144 *total += 1 + rtx_cost (XEXP (x, 1), code);
5145 return true;
5146 }
5147
5148 /* Needs a libcall. */
5149 *total = COSTS_N_INSNS (2);
5150 return false;
5151
5152 case MINUS:
5153 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5154 {
5155 *total = COSTS_N_INSNS (1);
5156 return false;
5157 }
5158
5159 if (mode == SImode)
5160 {
5161 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5162 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5163
5164 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5165 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5166 || subcode1 == ROTATE || subcode1 == ROTATERT
5167 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5168 || subcode1 == ASHIFTRT)
5169 {
5170 /* It's just the cost of the two operands. */
5171 *total = 0;
5172 return false;
5173 }
5174
5175 *total = COSTS_N_INSNS (1);
5176 return false;
5177 }
5178
5179 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5180 return false;
5181
f676971a 5182 case PLUS:
21b5653c
RE		 5183 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5184 {
5185 *total = COSTS_N_INSNS (1);
5186 return false;
5187 }
5188
5189 /* Fall through */
5190 case AND: case XOR: case IOR:
5191 if (mode == SImode)
5192 {
5193 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5194
5195 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5196 || subcode == LSHIFTRT || subcode == ASHIFTRT
5197 || (code == AND && subcode == NOT))
5198 {
5199 /* It's just the cost of the two operands. */
5200 *total = 0;
5201 return false;
5202 }
5203 }
5204
5205 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5206 return false;
5207
5208 case MULT:
5209 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5210 return false;
5211
5212 case NEG:
5213 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5214 *total = COSTS_N_INSNS (1);
5215 /* Fall through */
5216 case NOT:
5217 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5218
5219 return false;
5220
5221 case IF_THEN_ELSE:
5222 *total = 0;
5223 return false;
5224
5225 case COMPARE:
5226 if (cc_register (XEXP (x, 0), VOIDmode))
5227 * total = 0;
5228 else
5229 *total = COSTS_N_INSNS (1);
5230 return false;
5231
5232 case ABS:
5233 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5234 *total = COSTS_N_INSNS (1);
5235 else
5236 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5237 return false;
5238
5239 case SIGN_EXTEND:
5240 *total = 0;
5241 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5242 {
5243 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5244 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5245 }
5246 if (mode == DImode)
5247 *total += COSTS_N_INSNS (1);
5248 return false;
5249
5250 case ZERO_EXTEND:
5251 *total = 0;
5252 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5253 {
5254 switch (GET_MODE (XEXP (x, 0)))
5255 {
5256 case QImode:
5257 *total += COSTS_N_INSNS (1);
5258 break;
5259
5260 case HImode:
5261 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
f676971a 5262
21b5653c
RE		 5263 case SImode:
5264 break;
5265
5266 default:
5267 *total += COSTS_N_INSNS (2);
5268 }
5269 }
5270
5271 if (mode == DImode)
5272 *total += COSTS_N_INSNS (1);
5273
5274 return false;
5275
f676971a
EC		 5276 case CONST_INT:
5277 if (const_ok_for_arm (INTVAL (x)))
21b5653c
RE		 5278 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5279 else if (const_ok_for_arm (~INTVAL (x)))
5280 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5281 else if (const_ok_for_arm (-INTVAL (x)))
5282 {
5283 if (outer_code == COMPARE || outer_code == PLUS
5284 || outer_code == MINUS)
5285 *total = 0;
5286 else
5287 *total = COSTS_N_INSNS (1);
5288 }
5289 else
5290 *total = COSTS_N_INSNS (2);
5291 return true;
f676971a
EC		 5292
5293 case CONST:
5294 case LABEL_REF:
5295 case SYMBOL_REF:
21b5653c
RE		 5296 *total = COSTS_N_INSNS (2);
5297 return true;
f676971a 5298
21b5653c
RE		 5299 case CONST_DOUBLE:
5300 *total = COSTS_N_INSNS (4);
5301 return true;
5302
5303 default:
5304 if (mode != VOIDmode)
5305 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5306 else
5307 *total = COSTS_N_INSNS (4); /* How knows? */
5308 return false;
5309 }
5310}
5311
5b3e6663
PB		 5312/* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5313 supported on any "slowmul" cores, so it can be ignored. */
9b66ebb1 5314
3c50106f 5315static bool
9b66ebb1 5316arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3c50106f 5317{
9b66ebb1
PB		 5318 enum machine_mode mode = GET_MODE (x);
5319
5320 if (TARGET_THUMB)
5321 {
5b3e6663 5322 *total = thumb1_rtx_costs (x, code, outer_code);
9b66ebb1
PB		 5323 return true;
5324 }
f676971a 5325
9b66ebb1
PB		 5326 switch (code)
5327 {
5328 case MULT:
5329 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5330 || mode == DImode)
5331 {
5332 *total = 30;
5333 return true;
5334 }
5335
5336 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5337 {
5338 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5339 & (unsigned HOST_WIDE_INT) 0xffffffff);
5340 int cost, const_ok = const_ok_for_arm (i);
5341 int j, booth_unit_size;
5342
f676971a 5343 /* Tune as appropriate. */
9b66ebb1
PB		 5344 cost = const_ok ? 4 : 8;
5345 booth_unit_size = 2;
5346 for (j = 0; i && j < 32; j += booth_unit_size)
5347 {
5348 i >>= booth_unit_size;
5349 cost += 2;
5350 }
5351
5352 *total = cost;
5353 return true;
5354 }
5355
5356 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5357 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5358 return true;
f676971a 5359
9b66ebb1
PB		 5360 default:
5361 *total = arm_rtx_costs_1 (x, code, outer_code);
5362 return true;
5363 }
3c50106f
RH		 5364}
5365
9b66ebb1
PB		 5366
5367/* RTX cost for cores with a fast multiply unit (M variants). */
5368
5369static bool
5370arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5371{
5372 enum machine_mode mode = GET_MODE (x);
5373
5b3e6663 5374 if (TARGET_THUMB1)
9b66ebb1 5375 {
5b3e6663 5376 *total = thumb1_rtx_costs (x, code, outer_code);
9b66ebb1
PB		 5377 return true;
5378 }
f676971a 5379
5b3e6663 5380 /* ??? should thumb2 use different costs? */
9b66ebb1
PB		 5381 switch (code)
5382 {
5383 case MULT:
5384 /* There is no point basing this on the tuning, since it is always the
5385 fast variant if it exists at all. */
5386 if (mode == DImode
5387 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5388 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5389 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5390 {
5391 *total = 8;
5392 return true;
5393 }
f676971a 5394
9b66ebb1
PB		 5395
5396 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5397 || mode == DImode)
5398 {
5399 *total = 30;
5400 return true;
5401 }
5402
5403 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5404 {
5405 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5406 & (unsigned HOST_WIDE_INT) 0xffffffff);
5407 int cost, const_ok = const_ok_for_arm (i);
5408 int j, booth_unit_size;
5409
f676971a 5410 /* Tune as appropriate. */
9b66ebb1
PB		 5411 cost = const_ok ? 4 : 8;
5412 booth_unit_size = 8;
5413 for (j = 0; i && j < 32; j += booth_unit_size)
5414 {
5415 i >>= booth_unit_size;
5416 cost += 2;
5417 }
5418
5419 *total = cost;
5420 return true;
5421 }
5422
5423 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5424 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5425 return true;
f676971a 5426
9b66ebb1
PB		 5427 default:
5428 *total = arm_rtx_costs_1 (x, code, outer_code);
5429 return true;
5430 }
5431}
5432
5433
5b3e6663
PB		 5434/* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5435 so it can be ignored. */
9b66ebb1
PB		 5436
5437static bool
5438arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5439{
5440 enum machine_mode mode = GET_MODE (x);
5441
5442 if (TARGET_THUMB)
5443 {
5b3e6663 5444 *total = thumb1_rtx_costs (x, code, outer_code);
9b66ebb1
PB		 5445 return true;
5446 }
f676971a 5447
9b66ebb1
PB		 5448 switch (code)
5449 {
5450 case MULT:
5451 /* There is no point basing this on the tuning, since it is always the
5452 fast variant if it exists at all. */
5453 if (mode == DImode
5454 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5455 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5456 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5457 {
5458 *total = 8;
5459 return true;
5460 }
f676971a 5461
9b66ebb1
PB		 5462
5463 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5464 || mode == DImode)
5465 {
5466 *total = 30;
5467 return true;
5468 }
5469
5470 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5471 {
5472 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5473 & (unsigned HOST_WIDE_INT) 0xffffffff);
5474 int cost, const_ok = const_ok_for_arm (i);
5475 unsigned HOST_WIDE_INT masked_const;
5476
5477 /* The cost will be related to two insns.
ff482c8d 5478 First a load of the constant (MOV or LDR), then a multiply. */
9b66ebb1
PB		 5479 cost = 2;
5480 if (! const_ok)
5481 cost += 1; /* LDR is probably more expensive because
ff482c8d 5482 of longer result latency. */
9b66ebb1
PB		 5483 masked_const = i & 0xffff8000;
5484 if (masked_const != 0 && masked_const != 0xffff8000)
5485 {
5486 masked_const = i & 0xf8000000;
5487 if (masked_const == 0 || masked_const == 0xf8000000)
5488 cost += 1;
5489 else
5490 cost += 2;
5491 }
5492 *total = cost;
5493 return true;
5494 }
5495
5496 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5497 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5498 return true;
f676971a 5499
06d5588c
ILT		 5500 case COMPARE:
5501 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5502 will stall until the multiplication is complete. */
5503 if (GET_CODE (XEXP (x, 0)) == MULT)
5504 *total = 4 + rtx_cost (XEXP (x, 0), code);
5505 else
5506 *total = arm_rtx_costs_1 (x, code, outer_code);
5507 return true;
5508
9b66ebb1
PB		 5509 default:
5510 *total = arm_rtx_costs_1 (x, code, outer_code);
5511 return true;
5512 }
5513}
5514
5515
5516/* RTX costs for 9e (and later) cores. */
5517
5518static bool
5519arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5520{
5521 enum machine_mode mode = GET_MODE (x);
5522 int nonreg_cost;
5523 int cost;
f676971a 5524
5b3e6663 5525 if (TARGET_THUMB1)
9b66ebb1
PB		 5526 {
5527 switch (code)
5528 {
5529 case MULT:
5530 *total = COSTS_N_INSNS (3);
5531 return true;
f676971a 5532
9b66ebb1 5533 default:
5b3e6663 5534 *total = thumb1_rtx_costs (x, code, outer_code);
9b66ebb1
PB		 5535 return true;
5536 }
5537 }
f676971a 5538
9b66ebb1
PB		 5539 switch (code)
5540 {
5541 case MULT:
5542 /* There is no point basing this on the tuning, since it is always the
5543 fast variant if it exists at all. */
5544 if (mode == DImode
5545 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5546 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5547 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5548 {
5549 *total = 3;
5550 return true;
5551 }
f676971a 5552
9b66ebb1
PB		 5553
5554 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5555 {
5556 *total = 30;
5557 return true;
5558 }
5559 if (mode == DImode)
5560 {
5561 cost = 7;
5562 nonreg_cost = 8;
5563 }
5564 else
5565 {
5566 cost = 2;
5567 nonreg_cost = 4;
5568 }
5569
5570
5571 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5572 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5573 return true;
f676971a 5574
9b66ebb1
PB		 5575 default:
5576 *total = arm_rtx_costs_1 (x, code, outer_code);
5577 return true;
5578 }
5579}
dcefdf67
RH		 5580/* All address computations that can be done are free, but rtx cost returns
5581 the same for practically all of them. So we weight the different types
5582 of address here in the order (most pref first):
d6b4baa4 5583 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
d2b6eb76
ZW		 5584static inline int
5585arm_arm_address_cost (rtx x)
5586{
5587 enum rtx_code c = GET_CODE (x);
5588
5589 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5590 return 0;
5591 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5592 return 10;
5593
5594 if (c == PLUS || c == MINUS)
5595 {
d2b6eb76
ZW		 5596 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5597 return 2;
5598
ec8e098d 5599 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
d2b6eb76
ZW		 5600 return 3;
5601
5602 return 4;
5603 }
5604
5605 return 6;
5606}
5607
5608static inline int
5609arm_thumb_address_cost (rtx x)
5610{
5611 enum rtx_code c = GET_CODE (x);
5612
5613 if (c == REG)
5614 return 1;
5615 if (c == PLUS
5616 && GET_CODE (XEXP (x, 0)) == REG
5617 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5618 return 1;
5619
5620 return 2;
5621}
5622
dcefdf67 5623static int
e32bac5b 5624arm_address_cost (rtx x)
dcefdf67 5625{
5b3e6663 5626 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
dcefdf67
RH		 5627}
5628
c237e94a 5629static int
e32bac5b 5630arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
32de079a
RE		 5631{
5632 rtx i_pat, d_pat;
5633
d19fb8e3
NC		 5634 /* Some true dependencies can have a higher cost depending
5635 on precisely how certain input operands are used. */
4b3c2e48 5636 if (arm_tune_xscale
d19fb8e3 5637 && REG_NOTE_KIND (link) == 0
eda833e3
BE		 5638 && recog_memoized (insn) >= 0
5639 && recog_memoized (dep) >= 0)
d19fb8e3
NC		 5640 {
5641 int shift_opnum = get_attr_shift (insn);
5642 enum attr_type attr_type = get_attr_type (dep);
5643
5644 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5645 operand for INSN. If we have a shifted input operand and the
5646 instruction we depend on is another ALU instruction, then we may
5647 have to account for an additional stall. */
9b66ebb1
PB		 5648 if (shift_opnum != 0
5649 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
d19fb8e3
NC		 5650 {
5651 rtx shifted_operand;
5652 int opno;
f676971a 5653
d19fb8e3
NC		 5654 /* Get the shifted operand. */
5655 extract_insn (insn);
5656 shifted_operand = recog_data.operand[shift_opnum];
5657
5658 /* Iterate over all the operands in DEP. If we write an operand
5659 that overlaps with SHIFTED_OPERAND, then we have increase the
5660 cost of this dependency. */
5661 extract_insn (dep);
5662 preprocess_constraints ();
5663 for (opno = 0; opno < recog_data.n_operands; opno++)
5664 {
5665 /* We can ignore strict inputs. */
5666 if (recog_data.operand_type[opno] == OP_IN)
5667 continue;
5668
5669 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5670 shifted_operand))
5671 return 2;
5672 }
5673 }
5674 }
5675
6354dc9b 5676 /* XXX This is not strictly true for the FPA. */
d5b7b3ae
RE		 5677 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5678 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
b36ba79f
RE		 5679 return 0;
5680
d5b7b3ae
RE		 5681 /* Call insns don't incur a stall, even if they follow a load. */
5682 if (REG_NOTE_KIND (link) == 0
5683 && GET_CODE (insn) == CALL_INSN)
5684 return 1;
5685
32de079a
RE		 5686 if ((i_pat = single_set (insn)) != NULL
5687 && GET_CODE (SET_SRC (i_pat)) == MEM
5688 && (d_pat = single_set (dep)) != NULL
5689 && GET_CODE (SET_DEST (d_pat)) == MEM)
5690 {
48f6efae 5691 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
32de079a
RE		 5692 /* This is a load after a store, there is no conflict if the load reads
5693 from a cached area. Assume that loads from the stack, and from the
f676971a 5694 constant pool are cached, and that others will miss. This is a
6354dc9b 5695 hack. */
f676971a 5696
48f6efae
NC		 5697 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5698 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5699 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5700 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
949d79eb 5701 return 1;
32de079a
RE		 5702 }
5703
5704 return cost;
5705}
5706
9b66ebb1 5707static int fp_consts_inited = 0;
ff9940b0 5708
9b66ebb1
PB		 5709/* Only zero is valid for VFP. Other values are also valid for FPA. */
5710static const char * const strings_fp[8] =
62b10bbc 5711{
2b835d68
RE		 5712 "0", "1", "2", "3",
5713 "4", "5", "0.5", "10"
5714};
ff9940b0 5715
9b66ebb1 5716static REAL_VALUE_TYPE values_fp[8];
ff9940b0
RE		 5717
5718static void
9b66ebb1 5719init_fp_table (void)
ff9940b0
RE		 5720{
5721 int i;
5722 REAL_VALUE_TYPE r;
5723
9b66ebb1
PB		 5724 if (TARGET_VFP)
5725 fp_consts_inited = 1;
5726 else
5727 fp_consts_inited = 8;
5728
5729 for (i = 0; i < fp_consts_inited; i++)
ff9940b0 5730 {
9b66ebb1
PB		 5731 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5732 values_fp[i] = r;
ff9940b0 5733 }
ff9940b0
RE		 5734}
5735
9b66ebb1 5736/* Return TRUE if rtx X is a valid immediate FP constant. */
cce8749e 5737int
9b66ebb1 5738arm_const_double_rtx (rtx x)
cce8749e 5739{
ff9940b0
RE		 5740 REAL_VALUE_TYPE r;
5741 int i;
f676971a 5742
9b66ebb1
PB		 5743 if (!fp_consts_inited)
5744 init_fp_table ();
f676971a 5745
ff9940b0
RE		 5746 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5747 if (REAL_VALUE_MINUS_ZERO (r))
5748 return 0;
f3bb6135 5749
9b66ebb1
PB		 5750 for (i = 0; i < fp_consts_inited; i++)
5751 if (REAL_VALUES_EQUAL (r, values_fp[i]))
ff9940b0 5752 return 1;
f3bb6135 5753
ff9940b0 5754 return 0;
f3bb6135 5755}
ff9940b0 5756
3b684012 5757/* Return TRUE if rtx X is a valid immediate FPA constant. */
ff9940b0 5758int
e32bac5b 5759neg_const_double_rtx_ok_for_fpa (rtx x)
ff9940b0
RE		 5760{
5761 REAL_VALUE_TYPE r;
5762 int i;
f676971a 5763
9b66ebb1
PB		 5764 if (!fp_consts_inited)
5765 init_fp_table ();
f676971a 5766
ff9940b0
RE		 5767 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5768 r = REAL_VALUE_NEGATE (r);
5769 if (REAL_VALUE_MINUS_ZERO (r))
5770 return 0;
f3bb6135 5771
ff9940b0 5772 for (i = 0; i < 8; i++)
9b66ebb1 5773 if (REAL_VALUES_EQUAL (r, values_fp[i]))
ff9940b0 5774 return 1;
f3bb6135 5775
ff9940b0 5776 return 0;
f3bb6135 5777}
f1adb0a9
JB		 5778
5779
5780/* VFPv3 has a fairly wide range of representable immediates, formed from
5781 "quarter-precision" floating-point values. These can be evaluated using this
5782 formula (with ^ for exponentiation):
5783
5784 -1^s * n * 2^-r
5785
5786 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
5787 16 <= n <= 31 and 0 <= r <= 7.
5788
5789 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
5790
5791 - A (most-significant) is the sign bit.
5792 - BCD are the exponent (encoded as r XOR 3).
5793 - EFGH are the mantissa (encoded as n - 16).
5794*/
5795
5796/* Return an integer index for a VFPv3 immediate operand X suitable for the
5797 fconst[sd] instruction, or -1 if X isn't suitable. */
5798static int
5799vfp3_const_double_index (rtx x)
5800{
5801 REAL_VALUE_TYPE r, m;
5802 int sign, exponent;
5803 unsigned HOST_WIDE_INT mantissa, mant_hi;
5804 unsigned HOST_WIDE_INT mask;
8e39e9af 5805 HOST_WIDE_INT m1, m2;
f1adb0a9
JB		 5806 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
5807
5808 if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
5809 return -1;
5810
5811 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5812
5813 /* We can't represent these things, so detect them first. */
5814 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
5815 return -1;
5816
5817 /* Extract sign, exponent and mantissa. */
5818 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
5819 r = REAL_VALUE_ABS (r);
5820 exponent = REAL_EXP (&r);
5821 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
5822 highest (sign) bit, with a fixed binary point at bit point_pos.
5823 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
5824 bits for the mantissa, this may fail (low bits would be lost). */
5825 real_ldexp (&m, &r, point_pos - exponent);
8e39e9af
RE		 5826 REAL_VALUE_TO_INT (&m1, &m2, m);
5827 mantissa = m1;
5828 mant_hi = m2;
f1adb0a9
JB		 5829
5830 /* If there are bits set in the low part of the mantissa, we can't
5831 represent this value. */
5832 if (mantissa != 0)
5833 return -1;
5834
5835 /* Now make it so that mantissa contains the most-significant bits, and move
5836 the point_pos to indicate that the least-significant bits have been
5837 discarded. */
5838 point_pos -= HOST_BITS_PER_WIDE_INT;
5839 mantissa = mant_hi;
5840
5841 /* We can permit four significant bits of mantissa only, plus a high bit
5842 which is always 1. */
5843 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
5844 if ((mantissa & mask) != 0)
5845 return -1;
5846
5847 /* Now we know the mantissa is in range, chop off the unneeded bits. */
5848 mantissa >>= point_pos - 5;
5849
5850 /* The mantissa may be zero. Disallow that case. (It's possible to load the
5851 floating-point immediate zero with Neon using an integer-zero load, but
5852 that case is handled elsewhere.) */
5853 if (mantissa == 0)
5854 return -1;
5855
5856 gcc_assert (mantissa >= 16 && mantissa <= 31);
5857
5858 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
6ed3da00
KH		 5859 normalized significands are in the range [1, 2). (Our mantissa is shifted
5860 left 4 places at this point relative to normalized IEEE754 values). GCC
f1adb0a9
JB		 5861 internally uses [0.5, 1) (see real.c), so the exponent returned from
5862 REAL_EXP must be altered. */
5863 exponent = 5 - exponent;
5864
5865 if (exponent < 0 || exponent > 7)
5866 return -1;
5867
5868 /* Sign, mantissa and exponent are now in the correct form to plug into the
15dc95cb 5869 formula described in the comment above. */
f1adb0a9
JB		 5870 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
5871}
5872
5873/* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
5874int
5875vfp3_const_double_rtx (rtx x)
5876{
5877 if (!TARGET_VFP3)
5878 return 0;
5879
5880 return vfp3_const_double_index (x) != -1;
5881}
5882
88f77cba
JB		 5883/* Recognize immediates which can be used in various Neon instructions. Legal
5884 immediates are described by the following table (for VMVN variants, the
5885 bitwise inverse of the constant shown is recognized. In either case, VMOV
5886 is output and the correct instruction to use for a given constant is chosen
5887 by the assembler). The constant shown is replicated across all elements of
5888 the destination vector.
5889
5890 insn elems variant constant (binary)
5891 ---- ----- ------- -----------------
5892 vmov i32 0 00000000 00000000 00000000 abcdefgh
5893 vmov i32 1 00000000 00000000 abcdefgh 00000000
5894 vmov i32 2 00000000 abcdefgh 00000000 00000000
5895 vmov i32 3 abcdefgh 00000000 00000000 00000000
5896 vmov i16 4 00000000 abcdefgh
5897 vmov i16 5 abcdefgh 00000000
5898 vmvn i32 6 00000000 00000000 00000000 abcdefgh
5899 vmvn i32 7 00000000 00000000 abcdefgh 00000000
5900 vmvn i32 8 00000000 abcdefgh 00000000 00000000
5901 vmvn i32 9 abcdefgh 00000000 00000000 00000000
5902 vmvn i16 10 00000000 abcdefgh
5903 vmvn i16 11 abcdefgh 00000000
5904 vmov i32 12 00000000 00000000 abcdefgh 11111111
5905 vmvn i32 13 00000000 00000000 abcdefgh 11111111
5906 vmov i32 14 00000000 abcdefgh 11111111 11111111
5907 vmvn i32 15 00000000 abcdefgh 11111111 11111111
5908 vmov i8 16 abcdefgh
5909 vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
5910 eeeeeeee ffffffff gggggggg hhhhhhhh
5911 vmov f32 18 aBbbbbbc defgh000 00000000 00000000
5912
5913 For case 18, B = !b. Representable values are exactly those accepted by
5914 vfp3_const_double_index, but are output as floating-point numbers rather
5915 than indices.
5916
5917 Variants 0-5 (inclusive) may also be used as immediates for the second
5918 operand of VORR/VBIC instructions.
5919
5920 The INVERSE argument causes the bitwise inverse of the given operand to be
5921 recognized instead (used for recognizing legal immediates for the VAND/VORN
5922 pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is
5923 *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be
5924 output, rather than the real insns vbic/vorr).
5925
5926 INVERSE makes no difference to the recognition of float vectors.
5927
5928 The return value is the variant of immediate as shown in the above table, or
5929 -1 if the given value doesn't match any of the listed patterns.
5930*/
5931static int
5932neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
5933 rtx *modconst, int *elementwidth)
5934{
5935#define CHECK(STRIDE, ELSIZE, CLASS, TEST) \
5936 matches = 1; \
5937 for (i = 0; i < idx; i += (STRIDE)) \
5938 if (!(TEST)) \
5939 matches = 0; \
5940 if (matches) \
5941 { \
5942 immtype = (CLASS); \
5943 elsize = (ELSIZE); \
5944 break; \
5945 }
5946
5947 unsigned int i, elsize, idx = 0, n_elts = CONST_VECTOR_NUNITS (op);
5948 unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode));
5949 unsigned char bytes[16];
5950 int immtype = -1, matches;
5951 unsigned int invmask = inverse ? 0xff : 0;
5952
5953 /* Vectors of float constants. */
5954 if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
5955 {
5956 rtx el0 = CONST_VECTOR_ELT (op, 0);
5957 REAL_VALUE_TYPE r0;
5958
5959 if (!vfp3_const_double_rtx (el0))
5960 return -1;
5961
5962 REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
5963
5964 for (i = 1; i < n_elts; i++)
5965 {
5966 rtx elt = CONST_VECTOR_ELT (op, i);
5967 REAL_VALUE_TYPE re;
5968
5969 REAL_VALUE_FROM_CONST_DOUBLE (re, elt);
5970
5971 if (!REAL_VALUES_EQUAL (r0, re))
5972 return -1;
5973 }
5974
5975 if (modconst)
5976 *modconst = CONST_VECTOR_ELT (op, 0);
5977
5978 if (elementwidth)
5979 *elementwidth = 0;
5980
5981 return 18;
5982 }
5983
5984 /* Splat vector constant out into a byte vector. */
5985 for (i = 0; i < n_elts; i++)
5986 {
5987 rtx el = CONST_VECTOR_ELT (op, i);
5988 unsigned HOST_WIDE_INT elpart;
5989 unsigned int part, parts;
5990
5991 if (GET_CODE (el) == CONST_INT)
5992 {
5993 elpart = INTVAL (el);
5994 parts = 1;
5995 }
5996 else if (GET_CODE (el) == CONST_DOUBLE)
5997 {
5998 elpart = CONST_DOUBLE_LOW (el);
5999 parts = 2;
6000 }
6001 else
6002 gcc_unreachable ();
6003
6004 for (part = 0; part < parts; part++)
6005 {
6006 unsigned int byte;
6007 for (byte = 0; byte < innersize; byte++)
6008 {
6009 bytes[idx++] = (elpart & 0xff) ^ invmask;
6010 elpart >>= BITS_PER_UNIT;
6011 }
6012 if (GET_CODE (el) == CONST_DOUBLE)
6013 elpart = CONST_DOUBLE_HIGH (el);
6014 }
6015 }
6016
6017 /* Sanity check. */
6018 gcc_assert (idx == GET_MODE_SIZE (mode));
6019
6020 do
6021 {
6022 CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
6023 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6024
6025 CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
6026 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6027
6028 CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
6029 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
6030
6031 CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
6032 && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]);
6033
6034 CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0);
6035
6036 CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]);
6037
6038 CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
6039 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6040
6041 CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
6042 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6043
6044 CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
6045 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
6046
6047 CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
6048 && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]);
6049
6050 CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff);
6051
6052 CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]);
6053
6054 CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
6055 && bytes[i + 2] == 0 && bytes[i + 3] == 0);
6056
6057 CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
6058 && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff);
6059
6060 CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
6061 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0);
6062
6063 CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
6064 && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff);
6065
6066 CHECK (1, 8, 16, bytes[i] == bytes[0]);
6067
6068 CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
6069 && bytes[i] == bytes[(i + 8) % idx]);
6070 }
6071 while (0);
6072
6073 if (immtype == -1)
6074 return -1;
6075
6076 if (elementwidth)
6077 *elementwidth = elsize;
6078
6079 if (modconst)
6080 {
6081 unsigned HOST_WIDE_INT imm = 0;
6082
cea618ac 6083 /* Un-invert bytes of recognized vector, if necessary. */
88f77cba
JB		 6084 if (invmask != 0)
6085 for (i = 0; i < idx; i++)
6086 bytes[i] ^= invmask;
6087
6088 if (immtype == 17)
6089 {
6090 /* FIXME: Broken on 32-bit H_W_I hosts. */
6091 gcc_assert (sizeof (HOST_WIDE_INT) == 8);
6092
6093 for (i = 0; i < 8; i++)
6094 imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0)
6095 << (i * BITS_PER_UNIT);
6096
6097 *modconst = GEN_INT (imm);
6098 }
6099 else
6100 {
6101 unsigned HOST_WIDE_INT imm = 0;
6102
6103 for (i = 0; i < elsize / BITS_PER_UNIT; i++)
6104 imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT);
6105
6106 *modconst = GEN_INT (imm);
6107 }
6108 }
6109
6110 return immtype;
6111#undef CHECK
6112}
6113
6114/* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly,
6115 VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for
6116 float elements), and a modified constant (whatever should be output for a
6117 VMOV) in *MODCONST. */
6118
6119int
6120neon_immediate_valid_for_move (rtx op, enum machine_mode mode,
6121 rtx *modconst, int *elementwidth)
6122{
6123 rtx tmpconst;
6124 int tmpwidth;
6125 int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth);
6126
6127 if (retval == -1)
6128 return 0;
6129
6130 if (modconst)
6131 *modconst = tmpconst;
6132
6133 if (elementwidth)
6134 *elementwidth = tmpwidth;
6135
6136 return 1;
6137}
6138
6139/* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If
6140 the immediate is valid, write a constant suitable for using as an operand
6141 to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to
6142 *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */
6143
6144int
6145neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse,
6146 rtx *modconst, int *elementwidth)
6147{
6148 rtx tmpconst;
6149 int tmpwidth;
6150 int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth);
6151
6152 if (retval < 0 || retval > 5)
6153 return 0;
6154
6155 if (modconst)
6156 *modconst = tmpconst;
6157
6158 if (elementwidth)
6159 *elementwidth = tmpwidth;
6160
6161 return 1;
6162}
6163
6164/* Return a string suitable for output of Neon immediate logic operation
6165 MNEM. */
6166
6167char *
6168neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode,
6169 int inverse, int quad)
6170{
6171 int width, is_valid;
6172 static char templ[40];
6173
6174 is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width);
6175
6176 gcc_assert (is_valid != 0);
6177
6178 if (quad)
6179 sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width);
6180 else
6181 sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width);
6182
6183 return templ;
6184}
6185
6186/* Output a sequence of pairwise operations to implement a reduction.
6187 NOTE: We do "too much work" here, because pairwise operations work on two
6188 registers-worth of operands in one go. Unfortunately we can't exploit those
6189 extra calculations to do the full operation in fewer steps, I don't think.
6190 Although all vector elements of the result but the first are ignored, we
6191 actually calculate the same result in each of the elements. An alternative
6192 such as initially loading a vector with zero to use as each of the second
6193 operands would use up an additional register and take an extra instruction,
6194 for no particular gain. */
6195
6196void
6197neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
6198 rtx (*reduc) (rtx, rtx, rtx))
6199{
6200 enum machine_mode inner = GET_MODE_INNER (mode);
6201 unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner);
6202 rtx tmpsum = op1;
6203
6204 for (i = parts / 2; i >= 1; i /= 2)
6205 {
6206 rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode);
6207 emit_insn (reduc (dest, tmpsum, tmpsum));
6208 tmpsum = dest;
6209 }
6210}
6211
cea618ac 6212/* Initialize a vector with non-constant elements. FIXME: We can do better
88f77cba
JB		 6213 than the current implementation (building a vector on the stack and then
6214 loading it) in many cases. See rs6000.c. */
6215
6216void
6217neon_expand_vector_init (rtx target, rtx vals)
6218{
6219 enum machine_mode mode = GET_MODE (target);
6220 enum machine_mode inner = GET_MODE_INNER (mode);
6221 unsigned int i, n_elts = GET_MODE_NUNITS (mode);
6222 rtx mem;
6223
6224 gcc_assert (VECTOR_MODE_P (mode));
6225
6226 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
6227 for (i = 0; i < n_elts; i++)
6228 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
6229 XVECEXP (vals, 0, i));
6230
6231 emit_move_insn (target, mem);
6232}
6233
b617fc71
JB		 6234/* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise
6235 ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so
6236 reported source locations are bogus. */
6237
6238static void
6239bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
6240 const char *err)
6241{
6242 HOST_WIDE_INT lane;
6243
6244 gcc_assert (GET_CODE (operand) == CONST_INT);
6245
6246 lane = INTVAL (operand);
6247
6248 if (lane < low || lane >= high)
6249 error (err);
6250}
6251
6252/* Bounds-check lanes. */
6253
6254void
6255neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
6256{
6257 bounds_check (operand, low, high, "lane out of range");
6258}
6259
6260/* Bounds-check constants. */
6261
6262void
6263neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
6264{
6265 bounds_check (operand, low, high, "constant out of range");
6266}
6267
6268HOST_WIDE_INT
6269neon_element_bits (enum machine_mode mode)
6270{
6271 if (mode == DImode)
6272 return GET_MODE_BITSIZE (mode);
6273 else
6274 return GET_MODE_BITSIZE (GET_MODE_INNER (mode));
6275}
6276
cce8749e
CH		 6277\f
6278/* Predicates for `match_operand' and `match_operator'. */
6279
9b6b54e2 6280/* Return nonzero if OP is a valid Cirrus memory address pattern. */
9b6b54e2 6281int
e32bac5b 6282cirrus_memory_offset (rtx op)
9b6b54e2
NC		 6283{
6284 /* Reject eliminable registers. */
6285 if (! (reload_in_progress || reload_completed)
6286 && ( reg_mentioned_p (frame_pointer_rtx, op)
6287 || reg_mentioned_p (arg_pointer_rtx, op)
6288 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6289 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6290 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6291 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6292 return 0;
6293
6294 if (GET_CODE (op) == MEM)
6295 {
6296 rtx ind;
6297
6298 ind = XEXP (op, 0);
6299
6300 /* Match: (mem (reg)). */
6301 if (GET_CODE (ind) == REG)
6302 return 1;
6303
6304 /* Match:
6305 (mem (plus (reg)
6306 (const))). */
6307 if (GET_CODE (ind) == PLUS
6308 && GET_CODE (XEXP (ind, 0)) == REG
6309 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6310 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
6311 return 1;
6312 }
6313
6314 return 0;
6315}
6316
f26b8ec9 6317/* Return TRUE if OP is a valid coprocessor memory address pattern.
5b3e6663
PB		 6318 WB is true if full writeback address modes are allowed and is false
6319 if limited writeback address modes (POST_INC and PRE_DEC) are
6320 allowed. */
9b66ebb1
PB		 6321
6322int
fdd695fd 6323arm_coproc_mem_operand (rtx op, bool wb)
9b66ebb1 6324{
fdd695fd 6325 rtx ind;
9b66ebb1 6326
fdd695fd 6327 /* Reject eliminable registers. */
9b66ebb1
PB		 6328 if (! (reload_in_progress || reload_completed)
6329 && ( reg_mentioned_p (frame_pointer_rtx, op)
6330 || reg_mentioned_p (arg_pointer_rtx, op)
6331 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6332 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6333 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6334 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6335 return FALSE;
6336
59b9a953 6337 /* Constants are converted into offsets from labels. */
fdd695fd
PB		 6338 if (GET_CODE (op) != MEM)
6339 return FALSE;
9b66ebb1 6340
fdd695fd 6341 ind = XEXP (op, 0);
9b66ebb1 6342
fdd695fd
PB		 6343 if (reload_completed
6344 && (GET_CODE (ind) == LABEL_REF
6345 || (GET_CODE (ind) == CONST
6346 && GET_CODE (XEXP (ind, 0)) == PLUS
6347 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6348 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6349 return TRUE;
9b66ebb1 6350
fdd695fd
PB		 6351 /* Match: (mem (reg)). */
6352 if (GET_CODE (ind) == REG)
6353 return arm_address_register_rtx_p (ind, 0);
6354
5b3e6663
PB		 6355 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
6356 acceptable in any case (subject to verification by
6357 arm_address_register_rtx_p). We need WB to be true to accept
6358 PRE_INC and POST_DEC. */
6359 if (GET_CODE (ind) == POST_INC
6360 || GET_CODE (ind) == PRE_DEC
6361 || (wb
6362 && (GET_CODE (ind) == PRE_INC
6363 || GET_CODE (ind) == POST_DEC)))
fdd695fd
PB		 6364 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
6365
6366 if (wb
6367 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
6368 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
6369 && GET_CODE (XEXP (ind, 1)) == PLUS
6370 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
6371 ind = XEXP (ind, 1);
6372
6373 /* Match:
6374 (plus (reg)
6375 (const)). */
6376 if (GET_CODE (ind) == PLUS
6377 && GET_CODE (XEXP (ind, 0)) == REG
6378 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6379 && GET_CODE (XEXP (ind, 1)) == CONST_INT
6380 && INTVAL (XEXP (ind, 1)) > -1024
6381 && INTVAL (XEXP (ind, 1)) < 1024
6382 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
6383 return TRUE;
9b66ebb1
PB		 6384
6385 return FALSE;
6386}
6387
88f77cba
JB		 6388/* Return TRUE if OP is a memory operand which we can load or store a vector
6389 to/from. If CORE is true, we're moving from ARM registers not Neon
6390 registers. */
6391int
6392neon_vector_mem_operand (rtx op, bool core)
6393{
6394 rtx ind;
6395
6396 /* Reject eliminable registers. */
6397 if (! (reload_in_progress || reload_completed)
6398 && ( reg_mentioned_p (frame_pointer_rtx, op)
6399 || reg_mentioned_p (arg_pointer_rtx, op)
6400 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6401 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6402 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6403 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6404 return FALSE;
6405
6406 /* Constants are converted into offsets from labels. */
6407 if (GET_CODE (op) != MEM)
6408 return FALSE;
6409
6410 ind = XEXP (op, 0);
6411
6412 if (reload_completed
6413 && (GET_CODE (ind) == LABEL_REF
6414 || (GET_CODE (ind) == CONST
6415 && GET_CODE (XEXP (ind, 0)) == PLUS
6416 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6417 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6418 return TRUE;
6419
6420 /* Match: (mem (reg)). */
6421 if (GET_CODE (ind) == REG)
6422 return arm_address_register_rtx_p (ind, 0);
6423
6424 /* Allow post-increment with Neon registers. */
6425 if (!core && GET_CODE (ind) == POST_INC)
6426 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
6427
6428#if 0
6429 /* FIXME: We can support this too if we use VLD1/VST1. */
6430 if (!core
6431 && GET_CODE (ind) == POST_MODIFY
6432 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
6433 && GET_CODE (XEXP (ind, 1)) == PLUS
6434 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
6435 ind = XEXP (ind, 1);
6436#endif
6437
6438 /* Match:
6439 (plus (reg)
6440 (const)). */
6441 if (!core
6442 && GET_CODE (ind) == PLUS
6443 && GET_CODE (XEXP (ind, 0)) == REG
6444 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
6445 && GET_CODE (XEXP (ind, 1)) == CONST_INT
6446 && INTVAL (XEXP (ind, 1)) > -1024
6447 && INTVAL (XEXP (ind, 1)) < 1016
6448 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
6449 return TRUE;
6450
6451 return FALSE;
6452}
6453
6454/* Return TRUE if OP is a mem suitable for loading/storing a Neon struct
6455 type. */
6456int
6457neon_struct_mem_operand (rtx op)
6458{
6459 rtx ind;
6460
6461 /* Reject eliminable registers. */
6462 if (! (reload_in_progress || reload_completed)
6463 && ( reg_mentioned_p (frame_pointer_rtx, op)
6464 || reg_mentioned_p (arg_pointer_rtx, op)
6465 || reg_mentioned_p (virtual_incoming_args_rtx, op)
6466 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
6467 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
6468 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
6469 return FALSE;
6470
6471 /* Constants are converted into offsets from labels. */
6472 if (GET_CODE (op) != MEM)
6473 return FALSE;
6474
6475 ind = XEXP (op, 0);
6476
6477 if (reload_completed
6478 && (GET_CODE (ind) == LABEL_REF
6479 || (GET_CODE (ind) == CONST
6480 && GET_CODE (XEXP (ind, 0)) == PLUS
6481 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
6482 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
6483 return TRUE;
6484
6485 /* Match: (mem (reg)). */
6486 if (GET_CODE (ind) == REG)
6487 return arm_address_register_rtx_p (ind, 0);
6488
6489 return FALSE;
6490}
6491
6555b6bd
RE		 6492/* Return true if X is a register that will be eliminated later on. */
6493int
6494arm_eliminable_register (rtx x)
6495{
6496 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
6497 || REGNO (x) == ARG_POINTER_REGNUM
6498 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
6499 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
6500}
9b66ebb1 6501
9b66ebb1 6502/* Return GENERAL_REGS if a scratch register required to reload x to/from
fe2d934b 6503 coprocessor registers. Otherwise return NO_REGS. */
9b66ebb1
PB		 6504
6505enum reg_class
fe2d934b 6506coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
9b66ebb1 6507{
88f77cba
JB		 6508 if (TARGET_NEON
6509 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
6510 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
6511 && neon_vector_mem_operand (x, FALSE))
6512 return NO_REGS;
6513
fe2d934b 6514 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
9b66ebb1
PB		 6515 return NO_REGS;
6516
6517 return GENERAL_REGS;
6518}
6519
866af8a9
JB		 6520/* Values which must be returned in the most-significant end of the return
6521 register. */
6522
6523static bool
586de218 6524arm_return_in_msb (const_tree valtype)
866af8a9
JB		 6525{
6526 return (TARGET_AAPCS_BASED
6527 && BYTES_BIG_ENDIAN
6528 && (AGGREGATE_TYPE_P (valtype)
6529 || TREE_CODE (valtype) == COMPLEX_TYPE));
6530}
9b66ebb1 6531
f0375c66
NC		 6532/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
6533 Use by the Cirrus Maverick code which has to workaround
6534 a hardware bug triggered by such instructions. */
f0375c66 6535static bool
e32bac5b 6536arm_memory_load_p (rtx insn)
9b6b54e2
NC		 6537{
6538 rtx body, lhs, rhs;;
6539
f0375c66
NC		 6540 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
6541 return false;
9b6b54e2
NC		 6542
6543 body = PATTERN (insn);
6544
6545 if (GET_CODE (body) != SET)
f0375c66 6546 return false;
9b6b54e2
NC		 6547
6548 lhs = XEXP (body, 0);
6549 rhs = XEXP (body, 1);
6550
f0375c66
NC		 6551 lhs = REG_OR_SUBREG_RTX (lhs);
6552
6553 /* If the destination is not a general purpose
6554 register we do not have to worry. */
6555 if (GET_CODE (lhs) != REG
6556 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
6557 return false;
6558
6559 /* As well as loads from memory we also have to react
6560 to loads of invalid constants which will be turned
6561 into loads from the minipool. */
6562 return (GET_CODE (rhs) == MEM
6563 || GET_CODE (rhs) == SYMBOL_REF
6564 || note_invalid_constants (insn, -1, false));
9b6b54e2
NC		 6565}
6566
f0375c66 6567/* Return TRUE if INSN is a Cirrus instruction. */
f0375c66 6568static bool
e32bac5b 6569arm_cirrus_insn_p (rtx insn)
9b6b54e2
NC		 6570{
6571 enum attr_cirrus attr;
6572
e6d29d15 6573 /* get_attr cannot accept USE or CLOBBER. */
9b6b54e2
NC		 6574 if (!insn
6575 || GET_CODE (insn) != INSN
6576 || GET_CODE (PATTERN (insn)) == USE
6577 || GET_CODE (PATTERN (insn)) == CLOBBER)
6578 return 0;
6579
6580 attr = get_attr_cirrus (insn);
6581
f0375c66 6582 return attr != CIRRUS_NOT;
9b6b54e2
NC		 6583}
6584
6585/* Cirrus reorg for invalid instruction combinations. */
9b6b54e2 6586static void
e32bac5b 6587cirrus_reorg (rtx first)
9b6b54e2
NC		 6588{
6589 enum attr_cirrus attr;
6590 rtx body = PATTERN (first);
6591 rtx t;
6592 int nops;
6593
6594 /* Any branch must be followed by 2 non Cirrus instructions. */
6595 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
6596 {
6597 nops = 0;
6598 t = next_nonnote_insn (first);
6599
f0375c66 6600 if (arm_cirrus_insn_p (t))
9b6b54e2
NC		 6601 ++ nops;
6602
f0375c66 6603 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
9b6b54e2
NC		 6604 ++ nops;
6605
6606 while (nops --)
6607 emit_insn_after (gen_nop (), first);
6608
6609 return;
6610 }
6611
6612 /* (float (blah)) is in parallel with a clobber. */
6613 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6614 body = XVECEXP (body, 0, 0);
6615
6616 if (GET_CODE (body) == SET)
6617 {
6618 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
6619
6620 /* cfldrd, cfldr64, cfstrd, cfstr64 must
6621 be followed by a non Cirrus insn. */
6622 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
6623 {
f0375c66 6624 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
9b6b54e2
NC		 6625 emit_insn_after (gen_nop (), first);
6626
6627 return;
6628 }
f0375c66 6629 else if (arm_memory_load_p (first))
9b6b54e2
NC		 6630 {
6631 unsigned int arm_regno;
6632
6633 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
6634 ldr/cfmv64hr combination where the Rd field is the same
6635 in both instructions must be split with a non Cirrus
6636 insn. Example:
6637
6638 ldr r0, blah
6639 nop
6640 cfmvsr mvf0, r0. */
6641
6642 /* Get Arm register number for ldr insn. */
6643 if (GET_CODE (lhs) == REG)
6644 arm_regno = REGNO (lhs);
9b6b54e2 6645 else
e6d29d15
NS		 6646 {
6647 gcc_assert (GET_CODE (rhs) == REG);
6648 arm_regno = REGNO (rhs);
6649 }
9b6b54e2
NC		 6650
6651 /* Next insn. */
6652 first = next_nonnote_insn (first);
6653
f0375c66 6654 if (! arm_cirrus_insn_p (first))
9b6b54e2
NC		 6655 return;
6656
6657 body = PATTERN (first);
6658
6659 /* (float (blah)) is in parallel with a clobber. */
6660 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
6661 body = XVECEXP (body, 0, 0);
6662
6663 if (GET_CODE (body) == FLOAT)
6664 body = XEXP (body, 0);
6665
6666 if (get_attr_cirrus (first) == CIRRUS_MOVE
6667 && GET_CODE (XEXP (body, 1)) == REG
6668 && arm_regno == REGNO (XEXP (body, 1)))
6669 emit_insn_after (gen_nop (), first);
6670
6671 return;
6672 }
6673 }
6674
e6d29d15 6675 /* get_attr cannot accept USE or CLOBBER. */
9b6b54e2
NC		 6676 if (!first
6677 || GET_CODE (first) != INSN
6678 || GET_CODE (PATTERN (first)) == USE
6679 || GET_CODE (PATTERN (first)) == CLOBBER)
6680 return;
6681
6682 attr = get_attr_cirrus (first);
6683
6684 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
6685 must be followed by a non-coprocessor instruction. */
6686 if (attr == CIRRUS_COMPARE)
6687 {
6688 nops = 0;
6689
6690 t = next_nonnote_insn (first);
6691
f0375c66 6692 if (arm_cirrus_insn_p (t))
9b6b54e2
NC		 6693 ++ nops;
6694
f0375c66 6695 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
9b6b54e2
NC		 6696 ++ nops;
6697
6698 while (nops --)
6699 emit_insn_after (gen_nop (), first);
6700
6701 return;
6702 }
6703}
6704
2b835d68
RE		 6705/* Return TRUE if X references a SYMBOL_REF. */
6706int
e32bac5b 6707symbol_mentioned_p (rtx x)
2b835d68 6708{
1d6e90ac
NC		 6709 const char * fmt;
6710 int i;
2b835d68
RE		 6711
6712 if (GET_CODE (x) == SYMBOL_REF)
6713 return 1;
6714
d3585b76
DJ		 6715 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
6716 are constant offsets, not symbols. */
6717 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6718 return 0;
6719
2b835d68 6720 fmt = GET_RTX_FORMAT (GET_CODE (x));
f676971a 6721
2b835d68
RE		 6722 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6723 {
6724 if (fmt[i] == 'E')
6725 {
1d6e90ac 6726 int j;
2b835d68
RE		 6727
6728 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6729 if (symbol_mentioned_p (XVECEXP (x, i, j)))
6730 return 1;
6731 }
6732 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
6733 return 1;
6734 }
6735
6736 return 0;
6737}
6738
6739/* Return TRUE if X references a LABEL_REF. */
6740int
e32bac5b 6741label_mentioned_p (rtx x)
2b835d68 6742{
1d6e90ac
NC		 6743 const char * fmt;
6744 int i;
2b835d68
RE		 6745
6746 if (GET_CODE (x) == LABEL_REF)
6747 return 1;
6748
d3585b76
DJ		 6749 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6750 instruction, but they are constant offsets, not symbols. */
6751 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6752 return 0;
6753
2b835d68
RE		 6754 fmt = GET_RTX_FORMAT (GET_CODE (x));
6755 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6756 {
6757 if (fmt[i] == 'E')
6758 {
1d6e90ac 6759 int j;
2b835d68
RE		 6760
6761 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6762 if (label_mentioned_p (XVECEXP (x, i, j)))
6763 return 1;
6764 }
6765 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6766 return 1;
6767 }
6768
6769 return 0;
6770}
6771
d3585b76
DJ		 6772int
6773tls_mentioned_p (rtx x)
6774{
6775 switch (GET_CODE (x))
6776 {
6777 case CONST:
6778 return tls_mentioned_p (XEXP (x, 0));
6779
6780 case UNSPEC:
6781 if (XINT (x, 1) == UNSPEC_TLS)
6782 return 1;
6783
6784 default:
6785 return 0;
6786 }
6787}
6788
6789/* Must not copy a SET whose source operand is PC-relative. */
6790
6791static bool
6792arm_cannot_copy_insn_p (rtx insn)
6793{
6794 rtx pat = PATTERN (insn);
6795
10ae7c7b 6796 if (GET_CODE (pat) == SET)
d3585b76 6797 {
10ae7c7b 6798 rtx rhs = SET_SRC (pat);
d3585b76
DJ		 6799
6800 if (GET_CODE (rhs) == UNSPEC
6801 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6802 return TRUE;
6803
6804 if (GET_CODE (rhs) == MEM
6805 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6806 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6807 return TRUE;
6808 }
6809
6810 return FALSE;
6811}
6812
ff9940b0 6813enum rtx_code
e32bac5b 6814minmax_code (rtx x)
ff9940b0
RE		 6815{
6816 enum rtx_code code = GET_CODE (x);
6817
e6d29d15
NS		 6818 switch (code)
6819 {
6820 case SMAX:
6821 return GE;
6822 case SMIN:
6823 return LE;
6824 case UMIN:
6825 return LEU;
6826 case UMAX:
6827 return GEU;
6828 default:
6829 gcc_unreachable ();
6830 }
ff9940b0
RE		 6831}
6832
6354dc9b 6833/* Return 1 if memory locations are adjacent. */
f3bb6135 6834int
e32bac5b 6835adjacent_mem_locations (rtx a, rtx b)
ff9940b0 6836{
15b5c4c1
RE		 6837 /* We don't guarantee to preserve the order of these memory refs. */
6838 if (volatile_refs_p (a) || volatile_refs_p (b))
6839 return 0;
6840
ff9940b0
RE		 6841 if ((GET_CODE (XEXP (a, 0)) == REG
6842 || (GET_CODE (XEXP (a, 0)) == PLUS
6843 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6844 && (GET_CODE (XEXP (b, 0)) == REG
6845 || (GET_CODE (XEXP (b, 0)) == PLUS
6846 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6847 {
6555b6bd
RE		 6848 HOST_WIDE_INT val0 = 0, val1 = 0;
6849 rtx reg0, reg1;
6850 int val_diff;
f676971a 6851
ff9940b0
RE		 6852 if (GET_CODE (XEXP (a, 0)) == PLUS)
6853 {
6555b6bd 6854 reg0 = XEXP (XEXP (a, 0), 0);
ff9940b0
RE		 6855 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6856 }
6857 else
6555b6bd 6858 reg0 = XEXP (a, 0);
1d6e90ac 6859
ff9940b0
RE		 6860 if (GET_CODE (XEXP (b, 0)) == PLUS)
6861 {
6555b6bd 6862 reg1 = XEXP (XEXP (b, 0), 0);
ff9940b0
RE		 6863 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6864 }
6865 else
6555b6bd 6866 reg1 = XEXP (b, 0);
1d6e90ac 6867
e32bac5b
RE		 6868 /* Don't accept any offset that will require multiple
6869 instructions to handle, since this would cause the
6870 arith_adjacentmem pattern to output an overlong sequence. */
c75a3ddc
PB		 6871 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6872 return 0;
f676971a 6873
6555b6bd
RE		 6874 /* Don't allow an eliminable register: register elimination can make
6875 the offset too large. */
6876 if (arm_eliminable_register (reg0))
6877 return 0;
6878
6879 val_diff = val1 - val0;
15b5c4c1
RE		 6880
6881 if (arm_ld_sched)
6882 {
6883 /* If the target has load delay slots, then there's no benefit
6884 to using an ldm instruction unless the offset is zero and
6885 we are optimizing for size. */
6886 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6887 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6888 && (val_diff == 4 || val_diff == -4));
6889 }
6890
6555b6bd
RE		 6891 return ((REGNO (reg0) == REGNO (reg1))
6892 && (val_diff == 4 || val_diff == -4));
ff9940b0 6893 }
6555b6bd 6894
ff9940b0
RE		 6895 return 0;
6896}
6897
84ed5e79 6898int
e32bac5b
RE		 6899load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6900 HOST_WIDE_INT *load_offset)
84ed5e79
RE		 6901{
6902 int unsorted_regs[4];
6903 HOST_WIDE_INT unsorted_offsets[4];
6904 int order[4];
ad076f4e 6905 int base_reg = -1;
84ed5e79
RE		 6906 int i;
6907
1d6e90ac
NC		 6908 /* Can only handle 2, 3, or 4 insns at present,
6909 though could be easily extended if required. */
e6d29d15 6910 gcc_assert (nops >= 2 && nops <= 4);
84ed5e79
RE		 6911
6912 /* Loop over the operands and check that the memory references are
112cdef5 6913 suitable (i.e. immediate offsets from the same base register). At
84ed5e79
RE		 6914 the same time, extract the target register, and the memory
6915 offsets. */
6916 for (i = 0; i < nops; i++)
6917 {
6918 rtx reg;
6919 rtx offset;
6920
56636818
JL		 6921 /* Convert a subreg of a mem into the mem itself. */
6922 if (GET_CODE (operands[nops + i]) == SUBREG)
4e26a7af 6923 operands[nops + i] = alter_subreg (operands + (nops + i));
56636818 6924
e6d29d15 6925 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
84ed5e79
RE		 6926
6927 /* Don't reorder volatile memory references; it doesn't seem worth
6928 looking for the case where the order is ok anyway. */
6929 if (MEM_VOLATILE_P (operands[nops + i]))
6930 return 0;
6931
6932 offset = const0_rtx;
6933
6934 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6935 || (GET_CODE (reg) == SUBREG
6936 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6937 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6938 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6939 == REG)
6940 || (GET_CODE (reg) == SUBREG
6941 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6942 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6943 == CONST_INT)))
6944 {
6945 if (i == 0)
6946 {
d5b7b3ae 6947 base_reg = REGNO (reg);
84ed5e79
RE		 6948 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6949 ? REGNO (operands[i])
6950 : REGNO (SUBREG_REG (operands[i])));
6951 order[0] = 0;
6952 }
f676971a 6953 else
84ed5e79 6954 {
6354dc9b 6955 if (base_reg != (int) REGNO (reg))
84ed5e79
RE		 6956 /* Not addressed from the same base register. */
6957 return 0;
6958
6959 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6960 ? REGNO (operands[i])
6961 : REGNO (SUBREG_REG (operands[i])));
6962 if (unsorted_regs[i] < unsorted_regs[order[0]])
6963 order[0] = i;
6964 }
6965
6966 /* If it isn't an integer register, or if it overwrites the
6967 base register but isn't the last insn in the list, then
6968 we can't do this. */
6969 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6970 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6971 return 0;
6972
6973 unsorted_offsets[i] = INTVAL (offset);
6974 }
6975 else
6976 /* Not a suitable memory address. */
6977 return 0;
6978 }
6979
6980 /* All the useful information has now been extracted from the
6981 operands into unsorted_regs and unsorted_offsets; additionally,
6982 order[0] has been set to the lowest numbered register in the
6983 list. Sort the registers into order, and check that the memory
6984 offsets are ascending and adjacent. */
6985
6986 for (i = 1; i < nops; i++)
6987 {
6988 int j;
6989
6990 order[i] = order[i - 1];
6991 for (j = 0; j < nops; j++)
6992 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6993 && (order[i] == order[i - 1]
6994 || unsorted_regs[j] < unsorted_regs[order[i]]))
6995 order[i] = j;
6996
6997 /* Have we found a suitable register? if not, one must be used more
6998 than once. */
6999 if (order[i] == order[i - 1])
7000 return 0;
7001
7002 /* Is the memory address adjacent and ascending? */
7003 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
7004 return 0;
7005 }
7006
7007 if (base)
7008 {
7009 *base = base_reg;
7010
7011 for (i = 0; i < nops; i++)
7012 regs[i] = unsorted_regs[order[i]];
7013
7014 *load_offset = unsorted_offsets[order[0]];
7015 }
7016
7017 if (unsorted_offsets[order[0]] == 0)
7018 return 1; /* ldmia */
7019
5b3e6663 7020 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
84ed5e79
RE		 7021 return 2; /* ldmib */
7022
5b3e6663 7023 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
84ed5e79
RE		 7024 return 3; /* ldmda */
7025
7026 if (unsorted_offsets[order[nops - 1]] == -4)
7027 return 4; /* ldmdb */
7028
949d79eb
RE		 7029 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
7030 if the offset isn't small enough. The reason 2 ldrs are faster
7031 is because these ARMs are able to do more than one cache access
7032 in a single cycle. The ARM9 and StrongARM have Harvard caches,
7033 whilst the ARM8 has a double bandwidth cache. This means that
7034 these cores can do both an instruction fetch and a data fetch in
7035 a single cycle, so the trick of calculating the address into a
7036 scratch register (one of the result regs) and then doing a load
7037 multiple actually becomes slower (and no smaller in code size).
7038 That is the transformation
f676971a 7039
6cc8c0b3
NC		 7040 ldr rd1, [rbase + offset]
7041 ldr rd2, [rbase + offset + 4]
f676971a 7042
6cc8c0b3 7043 to
f676971a 7044
6cc8c0b3
NC		 7045 add rd1, rbase, offset
7046 ldmia rd1, {rd1, rd2}
f676971a 7047
949d79eb
RE		 7048 produces worse code -- '3 cycles + any stalls on rd2' instead of
7049 '2 cycles + any stalls on rd2'. On ARMs with only one cache
7050 access per cycle, the first sequence could never complete in less
7051 than 6 cycles, whereas the ldm sequence would only take 5 and
7052 would make better use of sequential accesses if not hitting the
7053 cache.
7054
7055 We cheat here and test 'arm_ld_sched' which we currently know to
7056 only be true for the ARM8, ARM9 and StrongARM. If this ever
7057 changes, then the test below needs to be reworked. */
f5a1b0d2 7058 if (nops == 2 && arm_ld_sched)
b36ba79f
RE		 7059 return 0;
7060
84ed5e79
RE		 7061 /* Can't do it without setting up the offset, only do this if it takes
7062 no more than one insn. */
f676971a 7063 return (const_ok_for_arm (unsorted_offsets[order[0]])
84ed5e79
RE		 7064 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
7065}
7066
cd2b33d0 7067const char *
e32bac5b 7068emit_ldm_seq (rtx *operands, int nops)
84ed5e79
RE		 7069{
7070 int regs[4];
7071 int base_reg;
7072 HOST_WIDE_INT offset;
7073 char buf[100];
7074 int i;
7075
7076 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
7077 {
7078 case 1:
5b3e6663 7079 strcpy (buf, "ldm%(ia%)\t");
84ed5e79
RE		 7080 break;
7081
7082 case 2:
5b3e6663 7083 strcpy (buf, "ldm%(ib%)\t");
84ed5e79
RE		 7084 break;
7085
7086 case 3:
5b3e6663 7087 strcpy (buf, "ldm%(da%)\t");
84ed5e79
RE		 7088 break;
7089
7090 case 4:
5b3e6663 7091 strcpy (buf, "ldm%(db%)\t");
84ed5e79
RE		 7092 break;
7093
7094 case 5:
7095 if (offset >= 0)
7096 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
7097 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
7098 (long) offset);
7099 else
7100 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
7101 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
7102 (long) -offset);
7103 output_asm_insn (buf, operands);
7104 base_reg = regs[0];
5b3e6663 7105 strcpy (buf, "ldm%(ia%)\t");
84ed5e79
RE		 7106 break;
7107
7108 default:
e6d29d15 7109 gcc_unreachable ();
84ed5e79
RE		 7110 }
7111
f676971a 7112 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
84ed5e79
RE		 7113 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
7114
7115 for (i = 1; i < nops; i++)
7116 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
7117 reg_names[regs[i]]);
7118
7119 strcat (buf, "}\t%@ phole ldm");
7120
7121 output_asm_insn (buf, operands);
7122 return "";
7123}
7124
7125int
e32bac5b
RE		 7126store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
7127 HOST_WIDE_INT * load_offset)
84ed5e79
RE		 7128{
7129 int unsorted_regs[4];
7130 HOST_WIDE_INT unsorted_offsets[4];
7131 int order[4];
ad076f4e 7132 int base_reg = -1;
84ed5e79
RE		 7133 int i;
7134
7135 /* Can only handle 2, 3, or 4 insns at present, though could be easily
7136 extended if required. */
e6d29d15 7137 gcc_assert (nops >= 2 && nops <= 4);
84ed5e79
RE		 7138
7139 /* Loop over the operands and check that the memory references are
112cdef5 7140 suitable (i.e. immediate offsets from the same base register). At
84ed5e79
RE		 7141 the same time, extract the target register, and the memory
7142 offsets. */
7143 for (i = 0; i < nops; i++)
7144 {
7145 rtx reg;
7146 rtx offset;
7147
56636818
JL		 7148 /* Convert a subreg of a mem into the mem itself. */
7149 if (GET_CODE (operands[nops + i]) == SUBREG)
4e26a7af 7150 operands[nops + i] = alter_subreg (operands + (nops + i));
56636818 7151
e6d29d15 7152 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
84ed5e79
RE		 7153
7154 /* Don't reorder volatile memory references; it doesn't seem worth
7155 looking for the case where the order is ok anyway. */
7156 if (MEM_VOLATILE_P (operands[nops + i]))
7157 return 0;
7158
7159 offset = const0_rtx;
7160
7161 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
7162 || (GET_CODE (reg) == SUBREG
7163 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
7164 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
7165 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
7166 == REG)
7167 || (GET_CODE (reg) == SUBREG
7168 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
7169 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
7170 == CONST_INT)))
7171 {
7172 if (i == 0)
7173 {
62b10bbc 7174 base_reg = REGNO (reg);
84ed5e79
RE		 7175 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
7176 ? REGNO (operands[i])
7177 : REGNO (SUBREG_REG (operands[i])));
7178 order[0] = 0;
7179 }
f676971a 7180 else
84ed5e79 7181 {
6354dc9b 7182 if (base_reg != (int) REGNO (reg))
84ed5e79
RE		 7183 /* Not addressed from the same base register. */
7184 return 0;
7185
7186 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
7187 ? REGNO (operands[i])
7188 : REGNO (SUBREG_REG (operands[i])));
7189 if (unsorted_regs[i] < unsorted_regs[order[0]])
7190 order[0] = i;
7191 }
7192
7193 /* If it isn't an integer register, then we can't do this. */
7194 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
7195 return 0;
7196
7197 unsorted_offsets[i] = INTVAL (offset);
7198 }
7199 else
7200 /* Not a suitable memory address. */
7201 return 0;
7202 }
7203
7204 /* All the useful information has now been extracted from the
7205 operands into unsorted_regs and unsorted_offsets; additionally,
7206 order[0] has been set to the lowest numbered register in the
7207 list. Sort the registers into order, and check that the memory
7208 offsets are ascending and adjacent. */
7209
7210 for (i = 1; i < nops; i++)
7211 {
7212 int j;
7213
7214 order[i] = order[i - 1];
7215 for (j = 0; j < nops; j++)
7216 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
7217 && (order[i] == order[i - 1]
7218 || unsorted_regs[j] < unsorted_regs[order[i]]))
7219 order[i] = j;
7220
7221 /* Have we found a suitable register? if not, one must be used more
7222 than once. */
7223 if (order[i] == order[i - 1])
7224 return 0;
7225
7226 /* Is the memory address adjacent and ascending? */
7227 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
7228 return 0;
7229 }
7230
7231 if (base)
7232 {
7233 *base = base_reg;
7234
7235 for (i = 0; i < nops; i++)
7236 regs[i] = unsorted_regs[order[i]];
7237
7238 *load_offset = unsorted_offsets[order[0]];
7239 }
7240
7241 if (unsorted_offsets[order[0]] == 0)
7242 return 1; /* stmia */
7243
7244 if (unsorted_offsets[order[0]] == 4)
7245 return 2; /* stmib */
7246
7247 if (unsorted_offsets[order[nops - 1]] == 0)
7248 return 3; /* stmda */
7249
7250 if (unsorted_offsets[order[nops - 1]] == -4)
7251 return 4; /* stmdb */
7252
7253 return 0;
7254}
7255
cd2b33d0 7256const char *
e32bac5b 7257emit_stm_seq (rtx *operands, int nops)
84ed5e79
RE		 7258{
7259 int regs[4];
7260 int base_reg;
7261 HOST_WIDE_INT offset;
7262 char buf[100];
7263 int i;
7264
7265 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
7266 {
7267 case 1:
5b3e6663 7268 strcpy (buf, "stm%(ia%)\t");
84ed5e79
RE		 7269 break;
7270
7271 case 2:
5b3e6663 7272 strcpy (buf, "stm%(ib%)\t");
84ed5e79
RE		 7273 break;
7274
7275 case 3:
5b3e6663 7276 strcpy (buf, "stm%(da%)\t");
84ed5e79
RE		 7277 break;
7278
7279 case 4:
5b3e6663 7280 strcpy (buf, "stm%(db%)\t");
84ed5e79
RE		 7281 break;
7282
7283 default:
e6d29d15 7284 gcc_unreachable ();
84ed5e79
RE		 7285 }
7286
f676971a 7287 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
84ed5e79
RE		 7288 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
7289
7290 for (i = 1; i < nops; i++)
7291 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
7292 reg_names[regs[i]]);
7293
7294 strcat (buf, "}\t%@ phole stm");
7295
7296 output_asm_insn (buf, operands);
7297 return "";
7298}
ff9940b0 7299\f
6354dc9b 7300/* Routines for use in generating RTL. */
1d6e90ac 7301
f3bb6135 7302rtx
e32bac5b 7303arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
50ed9cea 7304 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
ff9940b0 7305{
50ed9cea 7306 HOST_WIDE_INT offset = *offsetp;
ff9940b0
RE		 7307 int i = 0, j;
7308 rtx result;
7309 int sign = up ? 1 : -1;
50ed9cea 7310 rtx mem, addr;
ff9940b0 7311
d19fb8e3 7312 /* XScale has load-store double instructions, but they have stricter
1e5f1716 7313 alignment requirements than load-store multiple, so we cannot
d19fb8e3
NC		 7314 use them.
7315
7316 For XScale ldm requires 2 + NREGS cycles to complete and blocks
7317 the pipeline until completion.
7318
7319 NREGS CYCLES
7320 1 3
7321 2 4
7322 3 5
7323 4 6
7324
7325 An ldr instruction takes 1-3 cycles, but does not block the
7326 pipeline.
7327
7328 NREGS CYCLES
7329 1 1-3
7330 2 2-6
7331 3 3-9
7332 4 4-12
7333
7334 Best case ldr will always win. However, the more ldr instructions
7335 we issue, the less likely we are to be able to schedule them well.
7336 Using ldr instructions also increases code size.
7337
7338 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
7339 for counts of 3 or 4 regs. */
4b3c2e48 7340 if (arm_tune_xscale && count <= 2 && ! optimize_size)
d19fb8e3
NC		 7341 {
7342 rtx seq;
f676971a 7343
d19fb8e3 7344 start_sequence ();
f676971a 7345
d19fb8e3
NC		 7346 for (i = 0; i < count; i++)
7347 {
50ed9cea
RH		 7348 addr = plus_constant (from, i * 4 * sign);
7349 mem = adjust_automodify_address (basemem, SImode, addr, offset);
d19fb8e3 7350 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
50ed9cea 7351 offset += 4 * sign;
d19fb8e3
NC		 7352 }
7353
7354 if (write_back)
50ed9cea
RH		 7355 {
7356 emit_move_insn (from, plus_constant (from, count * 4 * sign));
7357 *offsetp = offset;
7358 }
d19fb8e3 7359
2f937369 7360 seq = get_insns ();
d19fb8e3 7361 end_sequence ();
f676971a 7362
d19fb8e3
NC		 7363 return seq;
7364 }
7365
43cffd11 7366 result = gen_rtx_PARALLEL (VOIDmode,
41e3f998 7367 rtvec_alloc (count + (write_back ? 1 : 0)));
ff9940b0 7368 if (write_back)
f3bb6135 7369 {
ff9940b0 7370 XVECEXP (result, 0, 0)
d66437c5 7371 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
ff9940b0
RE		 7372 i = 1;
7373 count++;
f3bb6135
RE		 7374 }
7375
ff9940b0 7376 for (j = 0; i < count; i++, j++)
f3bb6135 7377 {
50ed9cea
RH		 7378 addr = plus_constant (from, j * 4 * sign);
7379 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
43cffd11
RE		 7380 XVECEXP (result, 0, i)
7381 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
50ed9cea 7382 offset += 4 * sign;
f3bb6135
RE		 7383 }
7384
50ed9cea
RH		 7385 if (write_back)
7386 *offsetp = offset;
7387
ff9940b0
RE		 7388 return result;
7389}
7390
f3bb6135 7391rtx
e32bac5b 7392arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
50ed9cea 7393 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
ff9940b0 7394{
50ed9cea 7395 HOST_WIDE_INT offset = *offsetp;
ff9940b0
RE		 7396 int i = 0, j;
7397 rtx result;
7398 int sign = up ? 1 : -1;
50ed9cea 7399 rtx mem, addr;
ff9940b0 7400
d19fb8e3
NC		 7401 /* See arm_gen_load_multiple for discussion of
7402 the pros/cons of ldm/stm usage for XScale. */
4b3c2e48 7403 if (arm_tune_xscale && count <= 2 && ! optimize_size)
d19fb8e3
NC		 7404 {
7405 rtx seq;
f676971a 7406
d19fb8e3 7407 start_sequence ();
f676971a 7408
d19fb8e3
NC		 7409 for (i = 0; i < count; i++)
7410 {
50ed9cea
RH		 7411 addr = plus_constant (to, i * 4 * sign);
7412 mem = adjust_automodify_address (basemem, SImode, addr, offset);
d19fb8e3 7413 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
50ed9cea 7414 offset += 4 * sign;
d19fb8e3
NC		 7415 }
7416
7417 if (write_back)
50ed9cea
RH		 7418 {
7419 emit_move_insn (to, plus_constant (to, count * 4 * sign));
7420 *offsetp = offset;
7421 }
d19fb8e3 7422
2f937369 7423 seq = get_insns ();
d19fb8e3 7424 end_sequence ();
f676971a 7425
d19fb8e3
NC		 7426 return seq;
7427 }
7428
43cffd11 7429 result = gen_rtx_PARALLEL (VOIDmode,
41e3f998 7430 rtvec_alloc (count + (write_back ? 1 : 0)));
ff9940b0 7431 if (write_back)
f3bb6135 7432 {
ff9940b0 7433 XVECEXP (result, 0, 0)
d66437c5 7434 = gen_rtx_SET (VOIDmode, to,
43cffd11 7435 plus_constant (to, count * 4 * sign));
ff9940b0
RE		 7436 i = 1;
7437 count++;
f3bb6135
RE		 7438 }
7439
ff9940b0 7440 for (j = 0; i < count; i++, j++)
f3bb6135 7441 {
50ed9cea
RH		 7442 addr = plus_constant (to, j * 4 * sign);
7443 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
43cffd11
RE		 7444 XVECEXP (result, 0, i)
7445 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
50ed9cea 7446 offset += 4 * sign;
f3bb6135
RE		 7447 }
7448
50ed9cea
RH		 7449 if (write_back)
7450 *offsetp = offset;
7451
ff9940b0
RE		 7452 return result;
7453}
7454
880e2516 7455int
70128ad9 7456arm_gen_movmemqi (rtx *operands)
880e2516
RE		 7457{
7458 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
50ed9cea 7459 HOST_WIDE_INT srcoffset, dstoffset;
ad076f4e 7460 int i;
50ed9cea 7461 rtx src, dst, srcbase, dstbase;
880e2516 7462 rtx part_bytes_reg = NULL;
56636818 7463 rtx mem;
880e2516
RE		 7464
7465 if (GET_CODE (operands[2]) != CONST_INT
7466 || GET_CODE (operands[3]) != CONST_INT
7467 || INTVAL (operands[2]) > 64
7468 || INTVAL (operands[3]) & 3)
7469 return 0;
7470
50ed9cea
RH		 7471 dstbase = operands[0];
7472 srcbase = operands[1];
56636818 7473
50ed9cea
RH		 7474 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
7475 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
880e2516 7476
e9d7b180 7477 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
880e2516
RE		 7478 out_words_to_go = INTVAL (operands[2]) / 4;
7479 last_bytes = INTVAL (operands[2]) & 3;
50ed9cea 7480 dstoffset = srcoffset = 0;
880e2516
RE		 7481
7482 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
43cffd11 7483 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
880e2516
RE		 7484
7485 for (i = 0; in_words_to_go >= 2; i+=4)
7486 {
bd9c7e23 7487 if (in_words_to_go > 4)
56636818 7488 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
50ed9cea 7489 srcbase, &srcoffset));
bd9c7e23 7490 else
f676971a 7491 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
50ed9cea 7492 FALSE, srcbase, &srcoffset));
bd9c7e23 7493
880e2516
RE		 7494 if (out_words_to_go)
7495 {
bd9c7e23 7496 if (out_words_to_go > 4)
56636818 7497 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
50ed9cea 7498 dstbase, &dstoffset));
bd9c7e23
RE		 7499 else if (out_words_to_go != 1)
7500 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
f676971a 7501 dst, TRUE,
bd9c7e23 7502 (last_bytes == 0
56636818 7503 ? FALSE : TRUE),
50ed9cea 7504 dstbase, &dstoffset));
880e2516
RE		 7505 else
7506 {
50ed9cea 7507 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
43cffd11 7508 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
bd9c7e23 7509 if (last_bytes != 0)
50ed9cea
RH		 7510 {
7511 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
7512 dstoffset += 4;
7513 }
880e2516
RE		 7514 }
7515 }
7516
7517 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
7518 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
7519 }
7520
7521 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
7522 if (out_words_to_go)
62b10bbc
NC		 7523 {
7524 rtx sreg;
f676971a 7525
50ed9cea
RH		 7526 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
7527 sreg = copy_to_reg (mem);
7528
7529 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
62b10bbc 7530 emit_move_insn (mem, sreg);
62b10bbc 7531 in_words_to_go--;
f676971a 7532
e6d29d15 7533 gcc_assert (!in_words_to_go); /* Sanity check */
62b10bbc 7534 }
880e2516
RE		 7535
7536 if (in_words_to_go)
7537 {
e6d29d15 7538 gcc_assert (in_words_to_go > 0);
880e2516 7539
50ed9cea 7540 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
56636818 7541 part_bytes_reg = copy_to_mode_reg (SImode, mem);
880e2516
RE		 7542 }
7543
e6d29d15 7544 gcc_assert (!last_bytes || part_bytes_reg);
d5b7b3ae 7545
880e2516
RE		 7546 if (BYTES_BIG_ENDIAN && last_bytes)
7547 {
7548 rtx tmp = gen_reg_rtx (SImode);
7549
6354dc9b 7550 /* The bytes we want are in the top end of the word. */
bee06f3d
RE		 7551 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
7552 GEN_INT (8 * (4 - last_bytes))));
880e2516 7553 part_bytes_reg = tmp;
f676971a 7554
880e2516
RE		 7555 while (last_bytes)
7556 {
50ed9cea
RH		 7557 mem = adjust_automodify_address (dstbase, QImode,
7558 plus_constant (dst, last_bytes - 1),
7559 dstoffset + last_bytes - 1);
5d5603e2
BS		 7560 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7561
880e2516
RE		 7562 if (--last_bytes)
7563 {
7564 tmp = gen_reg_rtx (SImode);
7565 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
7566 part_bytes_reg = tmp;
7567 }
7568 }
f676971a 7569
880e2516
RE		 7570 }
7571 else
7572 {
d5b7b3ae 7573 if (last_bytes > 1)
880e2516 7574 {
50ed9cea 7575 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
5d5603e2 7576 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
d5b7b3ae
RE		 7577 last_bytes -= 2;
7578 if (last_bytes)
880e2516
RE		 7579 {
7580 rtx tmp = gen_reg_rtx (SImode);
a556fd39 7581 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
d5b7b3ae 7582 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
880e2516 7583 part_bytes_reg = tmp;
50ed9cea 7584 dstoffset += 2;
880e2516
RE		 7585 }
7586 }
f676971a 7587
d5b7b3ae
RE		 7588 if (last_bytes)
7589 {
50ed9cea 7590 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
5d5603e2 7591 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
d5b7b3ae 7592 }
880e2516
RE		 7593 }
7594
7595 return 1;
7596}
7597
03f1640c
RE		 7598/* Select a dominance comparison mode if possible for a test of the general
7599 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
f676971a 7600 COND_OR == DOM_CC_X_AND_Y => (X && Y)
03f1640c 7601 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
f676971a 7602 COND_OR == DOM_CC_X_OR_Y => (X || Y)
03f1640c 7603 In all cases OP will be either EQ or NE, but we don't need to know which
f676971a 7604 here. If we are unable to support a dominance comparison we return
03f1640c
RE		 7605 CC mode. This will then fail to match for the RTL expressions that
7606 generate this call. */
03f1640c 7607enum machine_mode
e32bac5b 7608arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
84ed5e79
RE		 7609{
7610 enum rtx_code cond1, cond2;
7611 int swapped = 0;
7612
7613 /* Currently we will probably get the wrong result if the individual
7614 comparisons are not simple. This also ensures that it is safe to
956d6950 7615 reverse a comparison if necessary. */
84ed5e79
RE		 7616 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
7617 != CCmode)
7618 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
7619 != CCmode))
7620 return CCmode;
7621
1646cf41
RE		 7622 /* The if_then_else variant of this tests the second condition if the
7623 first passes, but is true if the first fails. Reverse the first
7624 condition to get a true "inclusive-or" expression. */
03f1640c 7625 if (cond_or == DOM_CC_NX_OR_Y)
84ed5e79
RE		 7626 cond1 = reverse_condition (cond1);
7627
7628 /* If the comparisons are not equal, and one doesn't dominate the other,
7629 then we can't do this. */
f676971a 7630 if (cond1 != cond2
5895f793
RE		 7631 && !comparison_dominates_p (cond1, cond2)
7632 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
84ed5e79
RE		 7633 return CCmode;
7634
7635 if (swapped)
7636 {
7637 enum rtx_code temp = cond1;
7638 cond1 = cond2;
7639 cond2 = temp;
7640 }
7641
7642 switch (cond1)
7643 {
7644 case EQ:
e6d29d15 7645 if (cond_or == DOM_CC_X_AND_Y)
84ed5e79
RE		 7646 return CC_DEQmode;
7647
7648 switch (cond2)
7649 {
e6d29d15 7650 case EQ: return CC_DEQmode;
84ed5e79
RE		 7651 case LE: return CC_DLEmode;
7652 case LEU: return CC_DLEUmode;
7653 case GE: return CC_DGEmode;
7654 case GEU: return CC_DGEUmode;
e6d29d15 7655 default: gcc_unreachable ();
84ed5e79
RE		 7656 }
7657
84ed5e79 7658 case LT:
e6d29d15 7659 if (cond_or == DOM_CC_X_AND_Y)
84ed5e79 7660 return CC_DLTmode;
e0b92319 7661
e6d29d15
NS		 7662 switch (cond2)
7663 {
7664 case LT:
7665 return CC_DLTmode;
7666 case LE:
7667 return CC_DLEmode;
7668 case NE:
7669 return CC_DNEmode;
7670 default:
7671 gcc_unreachable ();
7672 }
84ed5e79
RE		 7673
7674 case GT:
e6d29d15 7675 if (cond_or == DOM_CC_X_AND_Y)
84ed5e79 7676 return CC_DGTmode;
e6d29d15
NS		 7677
7678 switch (cond2)
7679 {
7680 case GT:
7681 return CC_DGTmode;
7682 case GE:
7683 return CC_DGEmode;
7684 case NE:
7685 return CC_DNEmode;
7686 default:
7687 gcc_unreachable ();
7688 }
f676971a 7689
84ed5e79 7690 case LTU:
e6d29d15 7691 if (cond_or == DOM_CC_X_AND_Y)
84ed5e79 7692 return CC_DLTUmode;
e6d29d15
NS		 7693
7694 switch (cond2)
7695 {
7696 case LTU:
7697 return CC_DLTUmode;
7698 case LEU:
7699 return CC_DLEUmode;
7700 case NE:
7701 return CC_DNEmode;
7702 default:
7703 gcc_unreachable ();
7704 }
84ed5e79
RE		 7705
7706 case GTU:
e6d29d15 7707 if (cond_or == DOM_CC_X_AND_Y)
84ed5e79 7708 return CC_DGTUmode;
e0b92319 7709
e6d29d15
NS		 7710 switch (cond2)
7711 {
7712 case GTU:
7713 return CC_DGTUmode;
7714 case GEU:
7715 return CC_DGEUmode;
7716 case NE:
7717 return CC_DNEmode;
7718 default:
7719 gcc_unreachable ();
7720 }
84ed5e79
RE		 7721
7722 /* The remaining cases only occur when both comparisons are the
7723 same. */
7724 case NE:
e6d29d15 7725 gcc_assert (cond1 == cond2);
84ed5e79
RE		 7726 return CC_DNEmode;
7727
7728 case LE:
e6d29d15 7729 gcc_assert (cond1 == cond2);
84ed5e79
RE		 7730 return CC_DLEmode;
7731
7732 case GE:
e6d29d15 7733 gcc_assert (cond1 == cond2);
84ed5e79
RE		 7734 return CC_DGEmode;
7735
7736 case LEU:
e6d29d15 7737 gcc_assert (cond1 == cond2);
84ed5e79
RE		 7738 return CC_DLEUmode;
7739
7740 case GEU:
e6d29d15 7741 gcc_assert (cond1 == cond2);
84ed5e79 7742 return CC_DGEUmode;
ad076f4e
RE		 7743
7744 default:
e6d29d15 7745 gcc_unreachable ();
84ed5e79 7746 }
84ed5e79
RE		 7747}
7748
7749enum machine_mode
e32bac5b 7750arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
84ed5e79
RE		 7751{
7752 /* All floating point compares return CCFP if it is an equality
7753 comparison, and CCFPE otherwise. */
7754 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
e45b72c4
RE		 7755 {
7756 switch (op)
7757 {
7758 case EQ:
7759 case NE:
7760 case UNORDERED:
7761 case ORDERED:
7762 case UNLT:
7763 case UNLE:
7764 case UNGT:
7765 case UNGE:
7766 case UNEQ:
7767 case LTGT:
7768 return CCFPmode;
7769
7770 case LT:
7771 case LE:
7772 case GT:
7773 case GE:
9b66ebb1 7774 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
9b6b54e2 7775 return CCFPmode;
e45b72c4
RE		 7776 return CCFPEmode;
7777
7778 default:
e6d29d15 7779 gcc_unreachable ();
e45b72c4
RE		 7780 }
7781 }
f676971a 7782
84ed5e79
RE		 7783 /* A compare with a shifted operand. Because of canonicalization, the
7784 comparison will have to be swapped when we emit the assembler. */
7785 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7786 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7787 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7788 || GET_CODE (x) == ROTATERT))
7789 return CC_SWPmode;
7790
04d8b819
RE		 7791 /* This operation is performed swapped, but since we only rely on the Z
7792 flag we don't need an additional mode. */
7793 if (GET_MODE (y) == SImode && REG_P (y)
7794 && GET_CODE (x) == NEG
7795 && (op == EQ || op == NE))
7796 return CC_Zmode;
7797
f676971a 7798 /* This is a special case that is used by combine to allow a
956d6950 7799 comparison of a shifted byte load to be split into a zero-extend
84ed5e79 7800 followed by a comparison of the shifted integer (only valid for
956d6950 7801 equalities and unsigned inequalities). */
84ed5e79
RE		 7802 if (GET_MODE (x) == SImode
7803 && GET_CODE (x) == ASHIFT
7804 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7805 && GET_CODE (XEXP (x, 0)) == SUBREG
7806 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7807 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7808 && (op == EQ || op == NE
7809 || op == GEU || op == GTU || op == LTU || op == LEU)
7810 && GET_CODE (y) == CONST_INT)
7811 return CC_Zmode;
7812
1646cf41
RE		 7813 /* A construct for a conditional compare, if the false arm contains
7814 0, then both conditions must be true, otherwise either condition
7815 must be true. Not all conditions are possible, so CCmode is
7816 returned if it can't be done. */
7817 if (GET_CODE (x) == IF_THEN_ELSE
7818 && (XEXP (x, 2) == const0_rtx
7819 || XEXP (x, 2) == const1_rtx)
ec8e098d
PB		 7820 && COMPARISON_P (XEXP (x, 0))
7821 && COMPARISON_P (XEXP (x, 1)))
f676971a 7822 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
03f1640c 7823 INTVAL (XEXP (x, 2)));
1646cf41
RE		 7824
7825 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7826 if (GET_CODE (x) == AND
ec8e098d
PB		 7827 && COMPARISON_P (XEXP (x, 0))
7828 && COMPARISON_P (XEXP (x, 1)))
03f1640c
RE		 7829 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7830 DOM_CC_X_AND_Y);
1646cf41
RE		 7831
7832 if (GET_CODE (x) == IOR
ec8e098d
PB		 7833 && COMPARISON_P (XEXP (x, 0))
7834 && COMPARISON_P (XEXP (x, 1)))
03f1640c
RE		 7835 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7836 DOM_CC_X_OR_Y);
1646cf41 7837
defc0463
RE		 7838 /* An operation (on Thumb) where we want to test for a single bit.
7839 This is done by shifting that bit up into the top bit of a
7840 scratch register; we can then branch on the sign bit. */
5b3e6663 7841 if (TARGET_THUMB1
defc0463
RE		 7842 && GET_MODE (x) == SImode
7843 && (op == EQ || op == NE)
f9fa4363
RE		 7844 && GET_CODE (x) == ZERO_EXTRACT
7845 && XEXP (x, 1) == const1_rtx)
defc0463
RE		 7846 return CC_Nmode;
7847
84ed5e79
RE		 7848 /* An operation that sets the condition codes as a side-effect, the
7849 V flag is not set correctly, so we can only use comparisons where
7850 this doesn't matter. (For LT and GE we can use "mi" and "pl"
defc0463 7851 instead.) */
5b3e6663 7852 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
84ed5e79
RE		 7853 if (GET_MODE (x) == SImode
7854 && y == const0_rtx
7855 && (op == EQ || op == NE || op == LT || op == GE)
7856 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7857 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7858 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7859 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7860 || GET_CODE (x) == LSHIFTRT
7861 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
defc0463 7862 || GET_CODE (x) == ROTATERT
5b3e6663 7863 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
84ed5e79
RE		 7864 return CC_NOOVmode;
7865
84ed5e79
RE		 7866 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7867 return CC_Zmode;
7868
bd9c7e23
RE		 7869 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7870 && GET_CODE (x) == PLUS
7871 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7872 return CC_Cmode;
7873
84ed5e79
RE		 7874 return CCmode;
7875}
7876
ff9940b0
RE		 7877/* X and Y are two things to compare using CODE. Emit the compare insn and
7878 return the rtx for register 0 in the proper mode. FP means this is a
7879 floating point compare: I don't think that it is needed on the arm. */
ff9940b0 7880rtx
e32bac5b 7881arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
ff9940b0
RE		 7882{
7883 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
d5b7b3ae 7884 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
ff9940b0 7885
d66437c5 7886 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
ff9940b0
RE		 7887
7888 return cc_reg;
7889}
7890
fcd53748
JT		 7891/* Generate a sequence of insns that will generate the correct return
7892 address mask depending on the physical architecture that the program
7893 is running on. */
fcd53748 7894rtx
e32bac5b 7895arm_gen_return_addr_mask (void)
fcd53748
JT		 7896{
7897 rtx reg = gen_reg_rtx (Pmode);
7898
7899 emit_insn (gen_return_addr_mask (reg));
7900 return reg;
7901}
7902
0a81f500 7903void
e32bac5b 7904arm_reload_in_hi (rtx *operands)
0a81f500 7905{
f9cc092a
RE		 7906 rtx ref = operands[1];
7907 rtx base, scratch;
7908 HOST_WIDE_INT offset = 0;
7909
7910 if (GET_CODE (ref) == SUBREG)
7911 {
ddef6bc7 7912 offset = SUBREG_BYTE (ref);
f9cc092a
RE		 7913 ref = SUBREG_REG (ref);
7914 }
7915
7916 if (GET_CODE (ref) == REG)
7917 {
7918 /* We have a pseudo which has been spilt onto the stack; there
7919 are two cases here: the first where there is a simple
7920 stack-slot replacement and a second where the stack-slot is
7921 out of range, or is used as a subreg. */
7922 if (reg_equiv_mem[REGNO (ref)])
7923 {
7924 ref = reg_equiv_mem[REGNO (ref)];
7925 base = find_replacement (&XEXP (ref, 0));
7926 }
7927 else
6354dc9b 7928 /* The slot is out of range, or was dressed up in a SUBREG. */
f9cc092a
RE		 7929 base = reg_equiv_address[REGNO (ref)];
7930 }
7931 else
7932 base = find_replacement (&XEXP (ref, 0));
0a81f500 7933
e5e809f4
JL		 7934 /* Handle the case where the address is too complex to be offset by 1. */
7935 if (GET_CODE (base) == MINUS
7936 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7937 {
f9cc092a 7938 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
e5e809f4 7939
d66437c5 7940 emit_set_insn (base_plus, base);
e5e809f4
JL		 7941 base = base_plus;
7942 }
f9cc092a
RE		 7943 else if (GET_CODE (base) == PLUS)
7944 {
6354dc9b 7945 /* The addend must be CONST_INT, or we would have dealt with it above. */
f9cc092a
RE		 7946 HOST_WIDE_INT hi, lo;
7947
7948 offset += INTVAL (XEXP (base, 1));
7949 base = XEXP (base, 0);
7950
6354dc9b 7951 /* Rework the address into a legal sequence of insns. */
f9cc092a
RE		 7952 /* Valid range for lo is -4095 -> 4095 */
7953 lo = (offset >= 0
7954 ? (offset & 0xfff)
7955 : -((-offset) & 0xfff));
7956
7957 /* Corner case, if lo is the max offset then we would be out of range
7958 once we have added the additional 1 below, so bump the msb into the
7959 pre-loading insn(s). */
7960 if (lo == 4095)
7961 lo &= 0x7ff;
7962
30cf4896
KG		 7963 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7964 ^ (HOST_WIDE_INT) 0x80000000)
7965 - (HOST_WIDE_INT) 0x80000000);
f9cc092a 7966
e6d29d15 7967 gcc_assert (hi + lo == offset);
f9cc092a
RE		 7968
7969 if (hi != 0)
7970 {
7971 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7972
7973 /* Get the base address; addsi3 knows how to handle constants
6354dc9b 7974 that require more than one insn. */
f9cc092a
RE		 7975 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7976 base = base_plus;
7977 offset = lo;
7978 }
7979 }
e5e809f4 7980
3a1944a6
RE		 7981 /* Operands[2] may overlap operands[0] (though it won't overlap
7982 operands[1]), that's why we asked for a DImode reg -- so we can
7983 use the bit that does not overlap. */
7984 if (REGNO (operands[2]) == REGNO (operands[0]))
7985 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7986 else
7987 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7988
f9cc092a
RE		 7989 emit_insn (gen_zero_extendqisi2 (scratch,
7990 gen_rtx_MEM (QImode,
7991 plus_constant (base,
7992 offset))));
43cffd11 7993 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
f676971a 7994 gen_rtx_MEM (QImode,
f9cc092a
RE		 7995 plus_constant (base,
7996 offset + 1))));
5895f793 7997 if (!BYTES_BIG_ENDIAN)
d66437c5
RE		 7998 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7999 gen_rtx_IOR (SImode,
8000 gen_rtx_ASHIFT
8001 (SImode,
8002 gen_rtx_SUBREG (SImode, operands[0], 0),
8003 GEN_INT (8)),
8004 scratch));
0a81f500 8005 else
d66437c5
RE		 8006 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
8007 gen_rtx_IOR (SImode,
8008 gen_rtx_ASHIFT (SImode, scratch,
8009 GEN_INT (8)),
8010 gen_rtx_SUBREG (SImode, operands[0], 0)));
0a81f500
RE		 8011}
8012
72ac76be 8013/* Handle storing a half-word to memory during reload by synthesizing as two
f9cc092a
RE		 8014 byte stores. Take care not to clobber the input values until after we
8015 have moved them somewhere safe. This code assumes that if the DImode
8016 scratch in operands[2] overlaps either the input value or output address
8017 in some way, then that value must die in this insn (we absolutely need
8018 two scratch registers for some corner cases). */
f3bb6135 8019void
e32bac5b 8020arm_reload_out_hi (rtx *operands)
af48348a 8021{
f9cc092a
RE		 8022 rtx ref = operands[0];
8023 rtx outval = operands[1];
8024 rtx base, scratch;
8025 HOST_WIDE_INT offset = 0;
8026
8027 if (GET_CODE (ref) == SUBREG)
8028 {
ddef6bc7 8029 offset = SUBREG_BYTE (ref);
f9cc092a
RE		 8030 ref = SUBREG_REG (ref);
8031 }
8032
f9cc092a
RE		 8033 if (GET_CODE (ref) == REG)
8034 {
8035 /* We have a pseudo which has been spilt onto the stack; there
8036 are two cases here: the first where there is a simple
8037 stack-slot replacement and a second where the stack-slot is
8038 out of range, or is used as a subreg. */
8039 if (reg_equiv_mem[REGNO (ref)])
8040 {
8041 ref = reg_equiv_mem[REGNO (ref)];
8042 base = find_replacement (&XEXP (ref, 0));
8043 }
8044 else
6354dc9b 8045 /* The slot is out of range, or was dressed up in a SUBREG. */
f9cc092a
RE		 8046 base = reg_equiv_address[REGNO (ref)];
8047 }
8048 else
8049 base = find_replacement (&XEXP (ref, 0));
8050
8051 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
8052
8053 /* Handle the case where the address is too complex to be offset by 1. */
8054 if (GET_CODE (base) == MINUS
8055 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
8056 {
8057 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8058
8059 /* Be careful not to destroy OUTVAL. */
8060 if (reg_overlap_mentioned_p (base_plus, outval))
8061 {
8062 /* Updating base_plus might destroy outval, see if we can
8063 swap the scratch and base_plus. */
5895f793 8064 if (!reg_overlap_mentioned_p (scratch, outval))
f9cc092a
RE		 8065 {
8066 rtx tmp = scratch;
8067 scratch = base_plus;
8068 base_plus = tmp;
8069 }
8070 else
8071 {
8072 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
8073
8074 /* Be conservative and copy OUTVAL into the scratch now,
8075 this should only be necessary if outval is a subreg
8076 of something larger than a word. */
8077 /* XXX Might this clobber base? I can't see how it can,
8078 since scratch is known to overlap with OUTVAL, and
8079 must be wider than a word. */
8080 emit_insn (gen_movhi (scratch_hi, outval));
8081 outval = scratch_hi;
8082 }
8083 }
8084
d66437c5 8085 emit_set_insn (base_plus, base);
f9cc092a
RE		 8086 base = base_plus;
8087 }
8088 else if (GET_CODE (base) == PLUS)
8089 {
6354dc9b 8090 /* The addend must be CONST_INT, or we would have dealt with it above. */
f9cc092a
RE		 8091 HOST_WIDE_INT hi, lo;
8092
8093 offset += INTVAL (XEXP (base, 1));
8094 base = XEXP (base, 0);
8095
6354dc9b 8096 /* Rework the address into a legal sequence of insns. */
f9cc092a
RE		 8097 /* Valid range for lo is -4095 -> 4095 */
8098 lo = (offset >= 0
8099 ? (offset & 0xfff)
8100 : -((-offset) & 0xfff));
8101
8102 /* Corner case, if lo is the max offset then we would be out of range
8103 once we have added the additional 1 below, so bump the msb into the
8104 pre-loading insn(s). */
8105 if (lo == 4095)
8106 lo &= 0x7ff;
8107
30cf4896
KG		 8108 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
8109 ^ (HOST_WIDE_INT) 0x80000000)
8110 - (HOST_WIDE_INT) 0x80000000);
f9cc092a 8111
e6d29d15 8112 gcc_assert (hi + lo == offset);
f9cc092a
RE		 8113
8114 if (hi != 0)
8115 {
8116 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8117
8118 /* Be careful not to destroy OUTVAL. */
8119 if (reg_overlap_mentioned_p (base_plus, outval))
8120 {
8121 /* Updating base_plus might destroy outval, see if we
8122 can swap the scratch and base_plus. */
5895f793 8123 if (!reg_overlap_mentioned_p (scratch, outval))
f9cc092a
RE		 8124 {
8125 rtx tmp = scratch;
8126 scratch = base_plus;
8127 base_plus = tmp;
8128 }
8129 else
8130 {
8131 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
8132
8133 /* Be conservative and copy outval into scratch now,
8134 this should only be necessary if outval is a
8135 subreg of something larger than a word. */
8136 /* XXX Might this clobber base? I can't see how it
8137 can, since scratch is known to overlap with
8138 outval. */
8139 emit_insn (gen_movhi (scratch_hi, outval));
8140 outval = scratch_hi;
8141 }
8142 }
8143
8144 /* Get the base address; addsi3 knows how to handle constants
6354dc9b 8145 that require more than one insn. */
f9cc092a
RE		 8146 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
8147 base = base_plus;
8148 offset = lo;
8149 }
8150 }
af48348a 8151
b5cc037f
RE		 8152 if (BYTES_BIG_ENDIAN)
8153 {
f676971a 8154 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
f9cc092a 8155 plus_constant (base, offset + 1)),
5d5603e2 8156 gen_lowpart (QImode, outval)));
f9cc092a
RE		 8157 emit_insn (gen_lshrsi3 (scratch,
8158 gen_rtx_SUBREG (SImode, outval, 0),
b5cc037f 8159 GEN_INT (8)));
f9cc092a 8160 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5d5603e2 8161 gen_lowpart (QImode, scratch)));
b5cc037f
RE		 8162 }
8163 else
8164 {
f9cc092a 8165 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5d5603e2 8166 gen_lowpart (QImode, outval)));
f9cc092a
RE		 8167 emit_insn (gen_lshrsi3 (scratch,
8168 gen_rtx_SUBREG (SImode, outval, 0),
b5cc037f 8169 GEN_INT (8)));
f9cc092a
RE		 8170 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
8171 plus_constant (base, offset + 1)),
5d5603e2 8172 gen_lowpart (QImode, scratch)));
b5cc037f 8173 }
af48348a 8174}
866af8a9
JB		 8175
8176/* Return true if a type must be passed in memory. For AAPCS, small aggregates
8177 (padded to the size of a word) should be passed in a register. */
8178
8179static bool
586de218 8180arm_must_pass_in_stack (enum machine_mode mode, const_tree type)
866af8a9
JB		 8181{
8182 if (TARGET_AAPCS_BASED)
8183 return must_pass_in_stack_var_size (mode, type);
8184 else
8185 return must_pass_in_stack_var_size_or_pad (mode, type);
8186}
8187
8188
8189/* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
8190 Return true if an argument passed on the stack should be padded upwards,
5a29b385
PB		 8191 i.e. if the least-significant byte has useful data.
8192 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
8193 aggregate types are placed in the lowest memory address. */
866af8a9
JB		 8194
8195bool
586de218 8196arm_pad_arg_upward (enum machine_mode mode, const_tree type)
866af8a9
JB		 8197{
8198 if (!TARGET_AAPCS_BASED)
5a29b385 8199 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
866af8a9
JB		 8200
8201 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
8202 return false;
8203
8204 return true;
8205}
8206
8207
8208/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
8209 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
8210 byte of the register has useful data, and return the opposite if the
8211 most significant byte does.
8212 For AAPCS, small aggregates and small complex types are always padded
8213 upwards. */
8214
8215bool
8216arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
8217 tree type, int first ATTRIBUTE_UNUSED)
8218{
8219 if (TARGET_AAPCS_BASED
8220 && BYTES_BIG_ENDIAN
8221 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
8222 && int_size_in_bytes (type) <= 4)
8223 return true;
8224
8225 /* Otherwise, use default padding. */
8226 return !BYTES_BIG_ENDIAN;
8227}
8228
2b835d68 8229\f
d5b7b3ae
RE		 8230/* Print a symbolic form of X to the debug file, F. */
8231static void
e32bac5b 8232arm_print_value (FILE *f, rtx x)
d5b7b3ae
RE		 8233{
8234 switch (GET_CODE (x))
8235 {
8236 case CONST_INT:
8237 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
8238 return;
8239
8240 case CONST_DOUBLE:
8241 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
8242 return;
8243
5a9335ef
NC		 8244 case CONST_VECTOR:
8245 {
8246 int i;
8247
8248 fprintf (f, "<");
8249 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
8250 {
8251 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
8252 if (i < (CONST_VECTOR_NUNITS (x) - 1))
8253 fputc (',', f);
8254 }
8255 fprintf (f, ">");
8256 }
8257 return;
8258
d5b7b3ae
RE		 8259 case CONST_STRING:
8260 fprintf (f, "\"%s\"", XSTR (x, 0));
8261 return;
8262
8263 case SYMBOL_REF:
8264 fprintf (f, "`%s'", XSTR (x, 0));
8265 return;
8266
8267 case LABEL_REF:
8268 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
8269 return;
8270
8271 case CONST:
8272 arm_print_value (f, XEXP (x, 0));
8273 return;
8274
8275 case PLUS:
8276 arm_print_value (f, XEXP (x, 0));
8277 fprintf (f, "+");
8278 arm_print_value (f, XEXP (x, 1));
8279 return;
8280
8281 case PC:
8282 fprintf (f, "pc");
8283 return;
8284
8285 default:
8286 fprintf (f, "????");
8287 return;
8288 }
8289}
8290\f
2b835d68 8291/* Routines for manipulation of the constant pool. */
2b835d68 8292
949d79eb
RE		 8293/* Arm instructions cannot load a large constant directly into a
8294 register; they have to come from a pc relative load. The constant
8295 must therefore be placed in the addressable range of the pc
8296 relative load. Depending on the precise pc relative load
8297 instruction the range is somewhere between 256 bytes and 4k. This
8298 means that we often have to dump a constant inside a function, and
2b835d68
RE		 8299 generate code to branch around it.
8300
949d79eb
RE		 8301 It is important to minimize this, since the branches will slow
8302 things down and make the code larger.
2b835d68 8303
949d79eb
RE		 8304 Normally we can hide the table after an existing unconditional
8305 branch so that there is no interruption of the flow, but in the
8306 worst case the code looks like this:
2b835d68
RE		 8307
8308 ldr rn, L1
949d79eb 8309 ...
2b835d68
RE		 8310 b L2
8311 align
8312 L1: .long value
8313 L2:
949d79eb 8314 ...
2b835d68 8315
2b835d68 8316 ldr rn, L3
949d79eb 8317 ...
2b835d68
RE		 8318 b L4
8319 align
2b835d68
RE		 8320 L3: .long value
8321 L4:
949d79eb
RE		 8322 ...
8323
8324 We fix this by performing a scan after scheduling, which notices
8325 which instructions need to have their operands fetched from the
8326 constant table and builds the table.
8327
8328 The algorithm starts by building a table of all the constants that
8329 need fixing up and all the natural barriers in the function (places
8330 where a constant table can be dropped without breaking the flow).
8331 For each fixup we note how far the pc-relative replacement will be
8332 able to reach and the offset of the instruction into the function.
8333
8334 Having built the table we then group the fixes together to form
8335 tables that are as large as possible (subject to addressing
8336 constraints) and emit each table of constants after the last
8337 barrier that is within range of all the instructions in the group.
8338 If a group does not contain a barrier, then we forcibly create one
8339 by inserting a jump instruction into the flow. Once the table has
8340 been inserted, the insns are then modified to reference the
8341 relevant entry in the pool.
8342
6354dc9b 8343 Possible enhancements to the algorithm (not implemented) are:
949d79eb 8344
d5b7b3ae 8345 1) For some processors and object formats, there may be benefit in
949d79eb
RE		 8346 aligning the pools to the start of cache lines; this alignment
8347 would need to be taken into account when calculating addressability
6354dc9b 8348 of a pool. */
2b835d68 8349
d5b7b3ae
RE		 8350/* These typedefs are located at the start of this file, so that
8351 they can be used in the prototypes there. This comment is to
8352 remind readers of that fact so that the following structures
8353 can be understood more easily.
8354
8355 typedef struct minipool_node Mnode;
8356 typedef struct minipool_fixup Mfix; */
8357
8358struct minipool_node
8359{
8360 /* Doubly linked chain of entries. */
8361 Mnode * next;
8362 Mnode * prev;
8363 /* The maximum offset into the code that this entry can be placed. While
8364 pushing fixes for forward references, all entries are sorted in order
8365 of increasing max_address. */
8366 HOST_WIDE_INT max_address;
5519a4f9 8367 /* Similarly for an entry inserted for a backwards ref. */
d5b7b3ae
RE		 8368 HOST_WIDE_INT min_address;
8369 /* The number of fixes referencing this entry. This can become zero
8370 if we "unpush" an entry. In this case we ignore the entry when we
8371 come to emit the code. */
8372 int refcount;
8373 /* The offset from the start of the minipool. */
8374 HOST_WIDE_INT offset;
8375 /* The value in table. */
8376 rtx value;
8377 /* The mode of value. */
8378 enum machine_mode mode;
5a9335ef
NC		 8379 /* The size of the value. With iWMMXt enabled
8380 sizes > 4 also imply an alignment of 8-bytes. */
d5b7b3ae
RE		 8381 int fix_size;
8382};
8383
8384struct minipool_fixup
2b835d68 8385{
d5b7b3ae
RE		 8386 Mfix * next;
8387 rtx insn;
8388 HOST_WIDE_INT address;
8389 rtx * loc;
8390 enum machine_mode mode;
8391 int fix_size;
8392 rtx value;
8393 Mnode * minipool;
8394 HOST_WIDE_INT forwards;
8395 HOST_WIDE_INT backwards;
8396};
2b835d68 8397
d5b7b3ae
RE		 8398/* Fixes less than a word need padding out to a word boundary. */
8399#define MINIPOOL_FIX_SIZE(mode) \
8400 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
2b835d68 8401
d5b7b3ae
RE		 8402static Mnode * minipool_vector_head;
8403static Mnode * minipool_vector_tail;
8404static rtx minipool_vector_label;
34a9f549 8405static int minipool_pad;
332072db 8406
d5b7b3ae
RE		 8407/* The linked list of all minipool fixes required for this function. */
8408Mfix * minipool_fix_head;
8409Mfix * minipool_fix_tail;
8410/* The fix entry for the current minipool, once it has been placed. */
8411Mfix * minipool_barrier;
8412
8413/* Determines if INSN is the start of a jump table. Returns the end
8414 of the TABLE or NULL_RTX. */
8415static rtx
e32bac5b 8416is_jump_table (rtx insn)
2b835d68 8417{
d5b7b3ae 8418 rtx table;
f676971a 8419
d5b7b3ae
RE		 8420 if (GET_CODE (insn) == JUMP_INSN
8421 && JUMP_LABEL (insn) != NULL
8422 && ((table = next_real_insn (JUMP_LABEL (insn)))
8423 == next_real_insn (insn))
8424 && table != NULL
8425 && GET_CODE (table) == JUMP_INSN
8426 && (GET_CODE (PATTERN (table)) == ADDR_VEC
8427 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
8428 return table;
8429
8430 return NULL_RTX;
2b835d68
RE		 8431}
8432
657d9449
RE		 8433#ifndef JUMP_TABLES_IN_TEXT_SECTION
8434#define JUMP_TABLES_IN_TEXT_SECTION 0
8435#endif
8436
d5b7b3ae 8437static HOST_WIDE_INT
e32bac5b 8438get_jump_table_size (rtx insn)
2b835d68 8439{
657d9449
RE		 8440 /* ADDR_VECs only take room if read-only data does into the text
8441 section. */
d6b5193b 8442 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
657d9449
RE		 8443 {
8444 rtx body = PATTERN (insn);
8445 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5b3e6663
PB		 8446 HOST_WIDE_INT size;
8447 HOST_WIDE_INT modesize;
2b835d68 8448
5b3e6663
PB		 8449 modesize = GET_MODE_SIZE (GET_MODE (body));
8450 size = modesize * XVECLEN (body, elt);
8451 switch (modesize)
8452 {
8453 case 1:
88512ba0 8454 /* Round up size of TBB table to a halfword boundary. */
5b3e6663
PB		 8455 size = (size + 1) & ~(HOST_WIDE_INT)1;
8456 break;
8457 case 2:
7a085dce 8458 /* No padding necessary for TBH. */
5b3e6663
PB		 8459 break;
8460 case 4:
8461 /* Add two bytes for alignment on Thumb. */
8462 if (TARGET_THUMB)
8463 size += 2;
8464 break;
8465 default:
8466 gcc_unreachable ();
8467 }
8468 return size;
657d9449
RE		 8469 }
8470
8471 return 0;
d5b7b3ae 8472}
2b835d68 8473
d5b7b3ae
RE		 8474/* Move a minipool fix MP from its current location to before MAX_MP.
8475 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
093354e0 8476 constraints may need updating. */
d5b7b3ae 8477static Mnode *
e32bac5b
RE		 8478move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
8479 HOST_WIDE_INT max_address)
d5b7b3ae 8480{
e6d29d15
NS		 8481 /* The code below assumes these are different. */
8482 gcc_assert (mp != max_mp);
d5b7b3ae
RE		 8483
8484 if (max_mp == NULL)
8485 {
8486 if (max_address < mp->max_address)
8487 mp->max_address = max_address;
8488 }
8489 else
2b835d68 8490 {
d5b7b3ae
RE		 8491 if (max_address > max_mp->max_address - mp->fix_size)
8492 mp->max_address = max_mp->max_address - mp->fix_size;
8493 else
8494 mp->max_address = max_address;
2b835d68 8495
d5b7b3ae
RE		 8496 /* Unlink MP from its current position. Since max_mp is non-null,
8497 mp->prev must be non-null. */
8498 mp->prev->next = mp->next;
8499 if (mp->next != NULL)
8500 mp->next->prev = mp->prev;
8501 else
8502 minipool_vector_tail = mp->prev;
2b835d68 8503
d5b7b3ae
RE		 8504 /* Re-insert it before MAX_MP. */
8505 mp->next = max_mp;
8506 mp->prev = max_mp->prev;
8507 max_mp->prev = mp;
f676971a 8508
d5b7b3ae
RE		 8509 if (mp->prev != NULL)
8510 mp->prev->next = mp;
8511 else
8512 minipool_vector_head = mp;
8513 }
2b835d68 8514
d5b7b3ae
RE		 8515 /* Save the new entry. */
8516 max_mp = mp;
8517
d6a7951f 8518 /* Scan over the preceding entries and adjust their addresses as
d5b7b3ae
RE		 8519 required. */
8520 while (mp->prev != NULL
8521 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8522 {
8523 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8524 mp = mp->prev;
2b835d68
RE		 8525 }
8526
d5b7b3ae 8527 return max_mp;
2b835d68
RE		 8528}
8529
d5b7b3ae
RE		 8530/* Add a constant to the minipool for a forward reference. Returns the
8531 node added or NULL if the constant will not fit in this pool. */
8532static Mnode *
e32bac5b 8533add_minipool_forward_ref (Mfix *fix)
d5b7b3ae
RE		 8534{
8535 /* If set, max_mp is the first pool_entry that has a lower
8536 constraint than the one we are trying to add. */
8537 Mnode * max_mp = NULL;
34a9f549 8538 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
d5b7b3ae 8539 Mnode * mp;
f676971a 8540
7a7017bc
PB		 8541 /* If the minipool starts before the end of FIX->INSN then this FIX
8542 can not be placed into the current pool. Furthermore, adding the
8543 new constant pool entry may cause the pool to start FIX_SIZE bytes
8544 earlier. */
d5b7b3ae 8545 if (minipool_vector_head &&
7a7017bc
PB		 8546 (fix->address + get_attr_length (fix->insn)
8547 >= minipool_vector_head->max_address - fix->fix_size))
d5b7b3ae 8548 return NULL;
2b835d68 8549
d5b7b3ae
RE		 8550 /* Scan the pool to see if a constant with the same value has
8551 already been added. While we are doing this, also note the
8552 location where we must insert the constant if it doesn't already
8553 exist. */
8554 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8555 {
8556 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8557 && fix->mode == mp->mode
8558 && (GET_CODE (fix->value) != CODE_LABEL
8559 || (CODE_LABEL_NUMBER (fix->value)
8560 == CODE_LABEL_NUMBER (mp->value)))
8561 && rtx_equal_p (fix->value, mp->value))
8562 {
8563 /* More than one fix references this entry. */
8564 mp->refcount++;
8565 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
8566 }
8567
8568 /* Note the insertion point if necessary. */
8569 if (max_mp == NULL
8570 && mp->max_address > max_address)
8571 max_mp = mp;
5a9335ef
NC		 8572
8573 /* If we are inserting an 8-bytes aligned quantity and
8574 we have not already found an insertion point, then
8575 make sure that all such 8-byte aligned quantities are
8576 placed at the start of the pool. */
5848830f 8577 if (ARM_DOUBLEWORD_ALIGN
5a9335ef 8578 && max_mp == NULL
88f77cba
JB		 8579 && fix->fix_size >= 8
8580 && mp->fix_size < 8)
5a9335ef
NC		 8581 {
8582 max_mp = mp;
8583 max_address = mp->max_address;
8584 }
d5b7b3ae
RE		 8585 }
8586
8587 /* The value is not currently in the minipool, so we need to create
8588 a new entry for it. If MAX_MP is NULL, the entry will be put on
8589 the end of the list since the placement is less constrained than
8590 any existing entry. Otherwise, we insert the new fix before
6bc82793 8591 MAX_MP and, if necessary, adjust the constraints on the other
d5b7b3ae 8592 entries. */
5ed6ace5 8593 mp = XNEW (Mnode);
d5b7b3ae
RE		 8594 mp->fix_size = fix->fix_size;
8595 mp->mode = fix->mode;
8596 mp->value = fix->value;
8597 mp->refcount = 1;
8598 /* Not yet required for a backwards ref. */
8599 mp->min_address = -65536;
8600
8601 if (max_mp == NULL)
8602 {
8603 mp->max_address = max_address;
8604 mp->next = NULL;
8605 mp->prev = minipool_vector_tail;
8606
8607 if (mp->prev == NULL)
8608 {
8609 minipool_vector_head = mp;
8610 minipool_vector_label = gen_label_rtx ();
7551cbc7 8611 }
2b835d68 8612 else
d5b7b3ae 8613 mp->prev->next = mp;
2b835d68 8614
d5b7b3ae
RE		 8615 minipool_vector_tail = mp;
8616 }
8617 else
8618 {
8619 if (max_address > max_mp->max_address - mp->fix_size)
8620 mp->max_address = max_mp->max_address - mp->fix_size;
8621 else
8622 mp->max_address = max_address;
8623
8624 mp->next = max_mp;
8625 mp->prev = max_mp->prev;
8626 max_mp->prev = mp;
8627 if (mp->prev != NULL)
8628 mp->prev->next = mp;
8629 else
8630 minipool_vector_head = mp;
8631 }
8632
8633 /* Save the new entry. */
8634 max_mp = mp;
8635
d6a7951f 8636 /* Scan over the preceding entries and adjust their addresses as
d5b7b3ae
RE		 8637 required. */
8638 while (mp->prev != NULL
8639 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8640 {
8641 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8642 mp = mp->prev;
2b835d68
RE		 8643 }
8644
d5b7b3ae
RE		 8645 return max_mp;
8646}
8647
8648static Mnode *
e32bac5b
RE		 8649move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
8650 HOST_WIDE_INT min_address)
d5b7b3ae
RE		 8651{
8652 HOST_WIDE_INT offset;
8653
e6d29d15
NS		 8654 /* The code below assumes these are different. */
8655 gcc_assert (mp != min_mp);
d5b7b3ae
RE		 8656
8657 if (min_mp == NULL)
2b835d68 8658 {
d5b7b3ae
RE		 8659 if (min_address > mp->min_address)
8660 mp->min_address = min_address;
8661 }
8662 else
8663 {
8664 /* We will adjust this below if it is too loose. */
8665 mp->min_address = min_address;
8666
8667 /* Unlink MP from its current position. Since min_mp is non-null,
8668 mp->next must be non-null. */
8669 mp->next->prev = mp->prev;
8670 if (mp->prev != NULL)
8671 mp->prev->next = mp->next;
8672 else
8673 minipool_vector_head = mp->next;
8674
8675 /* Reinsert it after MIN_MP. */
8676 mp->prev = min_mp;
8677 mp->next = min_mp->next;
8678 min_mp->next = mp;
8679 if (mp->next != NULL)
8680 mp->next->prev = mp;
2b835d68 8681 else
d5b7b3ae
RE		 8682 minipool_vector_tail = mp;
8683 }
8684
8685 min_mp = mp;
8686
8687 offset = 0;
8688 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8689 {
8690 mp->offset = offset;
8691 if (mp->refcount > 0)
8692 offset += mp->fix_size;
8693
8694 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
8695 mp->next->min_address = mp->min_address + mp->fix_size;
8696 }
8697
8698 return min_mp;
f676971a 8699}
d5b7b3ae
RE		 8700
8701/* Add a constant to the minipool for a backward reference. Returns the
f676971a 8702 node added or NULL if the constant will not fit in this pool.
d5b7b3ae
RE		 8703
8704 Note that the code for insertion for a backwards reference can be
8705 somewhat confusing because the calculated offsets for each fix do
8706 not take into account the size of the pool (which is still under
8707 construction. */
8708static Mnode *
e32bac5b 8709add_minipool_backward_ref (Mfix *fix)
d5b7b3ae
RE		 8710{
8711 /* If set, min_mp is the last pool_entry that has a lower constraint
8712 than the one we are trying to add. */
e32bac5b 8713 Mnode *min_mp = NULL;
d5b7b3ae
RE		 8714 /* This can be negative, since it is only a constraint. */
8715 HOST_WIDE_INT min_address = fix->address - fix->backwards;
e32bac5b 8716 Mnode *mp;
d5b7b3ae
RE		 8717
8718 /* If we can't reach the current pool from this insn, or if we can't
8719 insert this entry at the end of the pool without pushing other
8720 fixes out of range, then we don't try. This ensures that we
8721 can't fail later on. */
8722 if (min_address >= minipool_barrier->address
8723 || (minipool_vector_tail->min_address + fix->fix_size
8724 >= minipool_barrier->address))
8725 return NULL;
8726
8727 /* Scan the pool to see if a constant with the same value has
8728 already been added. While we are doing this, also note the
8729 location where we must insert the constant if it doesn't already
8730 exist. */
8731 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
8732 {
8733 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8734 && fix->mode == mp->mode
8735 && (GET_CODE (fix->value) != CODE_LABEL
8736 || (CODE_LABEL_NUMBER (fix->value)
8737 == CODE_LABEL_NUMBER (mp->value)))
8738 && rtx_equal_p (fix->value, mp->value)
8739 /* Check that there is enough slack to move this entry to the
8740 end of the table (this is conservative). */
f676971a
EC		 8741 && (mp->max_address
8742 > (minipool_barrier->address
d5b7b3ae
RE		 8743 + minipool_vector_tail->offset
8744 + minipool_vector_tail->fix_size)))
8745 {
8746 mp->refcount++;
8747 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8748 }
8749
8750 if (min_mp != NULL)
8751 mp->min_address += fix->fix_size;
8752 else
8753 {
8754 /* Note the insertion point if necessary. */
8755 if (mp->min_address < min_address)
5a9335ef
NC		 8756 {
8757 /* For now, we do not allow the insertion of 8-byte alignment
8758 requiring nodes anywhere but at the start of the pool. */
5848830f 8759 if (ARM_DOUBLEWORD_ALIGN
88f77cba 8760 && fix->fix_size >= 8 && mp->fix_size < 8)
5a9335ef
NC		 8761 return NULL;
8762 else
8763 min_mp = mp;
8764 }
d5b7b3ae
RE		 8765 else if (mp->max_address
8766 < minipool_barrier->address + mp->offset + fix->fix_size)
8767 {
8768 /* Inserting before this entry would push the fix beyond
8769 its maximum address (which can happen if we have
8770 re-located a forwards fix); force the new fix to come
8771 after it. */
8772 min_mp = mp;
8773 min_address = mp->min_address + fix->fix_size;
8774 }
5a9335ef
NC		 8775 /* If we are inserting an 8-bytes aligned quantity and
8776 we have not already found an insertion point, then
8777 make sure that all such 8-byte aligned quantities are
8778 placed at the start of the pool. */
5848830f 8779 else if (ARM_DOUBLEWORD_ALIGN
5a9335ef 8780 && min_mp == NULL
88f77cba 8781 && fix->fix_size >= 8
5a9335ef
NC		 8782 && mp->fix_size < 8)
8783 {
8784 min_mp = mp;
8785 min_address = mp->min_address + fix->fix_size;
8786 }
d5b7b3ae
RE		 8787 }
8788 }
8789
8790 /* We need to create a new entry. */
5ed6ace5 8791 mp = XNEW (Mnode);
d5b7b3ae
RE		 8792 mp->fix_size = fix->fix_size;
8793 mp->mode = fix->mode;
8794 mp->value = fix->value;
8795 mp->refcount = 1;
8796 mp->max_address = minipool_barrier->address + 65536;
8797
8798 mp->min_address = min_address;
8799
8800 if (min_mp == NULL)
8801 {
8802 mp->prev = NULL;
8803 mp->next = minipool_vector_head;
8804
8805 if (mp->next == NULL)
8806 {
8807 minipool_vector_tail = mp;
8808 minipool_vector_label = gen_label_rtx ();
8809 }
8810 else
8811 mp->next->prev = mp;
8812
8813 minipool_vector_head = mp;
8814 }
8815 else
8816 {
8817 mp->next = min_mp->next;
8818 mp->prev = min_mp;
8819 min_mp->next = mp;
f676971a 8820
d5b7b3ae
RE		 8821 if (mp->next != NULL)
8822 mp->next->prev = mp;
8823 else
8824 minipool_vector_tail = mp;
8825 }
8826
8827 /* Save the new entry. */
8828 min_mp = mp;
8829
8830 if (mp->prev)
8831 mp = mp->prev;
8832 else
8833 mp->offset = 0;
8834
8835 /* Scan over the following entries and adjust their offsets. */
8836 while (mp->next != NULL)
8837 {
8838 if (mp->next->min_address < mp->min_address + mp->fix_size)
8839 mp->next->min_address = mp->min_address + mp->fix_size;
8840
8841 if (mp->refcount)
8842 mp->next->offset = mp->offset + mp->fix_size;
8843 else
8844 mp->next->offset = mp->offset;
8845
8846 mp = mp->next;
8847 }
8848
8849 return min_mp;
8850}
8851
8852static void
e32bac5b 8853assign_minipool_offsets (Mfix *barrier)
d5b7b3ae
RE		 8854{
8855 HOST_WIDE_INT offset = 0;
e32bac5b 8856 Mnode *mp;
d5b7b3ae
RE		 8857
8858 minipool_barrier = barrier;
8859
8860 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8861 {
8862 mp->offset = offset;
f676971a 8863
d5b7b3ae
RE		 8864 if (mp->refcount > 0)
8865 offset += mp->fix_size;
8866 }
8867}
8868
8869/* Output the literal table */
8870static void
e32bac5b 8871dump_minipool (rtx scan)
d5b7b3ae 8872{
5a9335ef
NC		 8873 Mnode * mp;
8874 Mnode * nmp;
8875 int align64 = 0;
8876
5848830f 8877 if (ARM_DOUBLEWORD_ALIGN)
5a9335ef 8878 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
88f77cba 8879 if (mp->refcount > 0 && mp->fix_size >= 8)
5a9335ef
NC		 8880 {
8881 align64 = 1;
8882 break;
8883 }
d5b7b3ae 8884
c263766c
RH		 8885 if (dump_file)
8886 fprintf (dump_file,
5a9335ef
NC		 8887 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8888 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
d5b7b3ae
RE		 8889
8890 scan = emit_label_after (gen_label_rtx (), scan);
5a9335ef 8891 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
d5b7b3ae
RE		 8892 scan = emit_label_after (minipool_vector_label, scan);
8893
8894 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8895 {
8896 if (mp->refcount > 0)
8897 {
c263766c 8898 if (dump_file)
d5b7b3ae 8899 {
f676971a 8900 fprintf (dump_file,
d5b7b3ae
RE		 8901 ";; Offset %u, min %ld, max %ld ",
8902 (unsigned) mp->offset, (unsigned long) mp->min_address,
8903 (unsigned long) mp->max_address);
c263766c
RH		 8904 arm_print_value (dump_file, mp->value);
8905 fputc ('\n', dump_file);
d5b7b3ae
RE		 8906 }
8907
8908 switch (mp->fix_size)
8909 {
8910#ifdef HAVE_consttable_1
8911 case 1:
8912 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8913 break;
8914
8915#endif
8916#ifdef HAVE_consttable_2
8917 case 2:
8918 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8919 break;
8920
8921#endif
8922#ifdef HAVE_consttable_4
8923 case 4:
8924 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8925 break;
8926
8927#endif
8928#ifdef HAVE_consttable_8
8929 case 8:
8930 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8931 break;
8932
88f77cba
JB		 8933#endif
8934#ifdef HAVE_consttable_16
8935 case 16:
8936 scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
8937 break;
8938
d5b7b3ae
RE		 8939#endif
8940 default:
e6d29d15 8941 gcc_unreachable ();
d5b7b3ae
RE		 8942 }
8943 }
8944
8945 nmp = mp->next;
8946 free (mp);
2b835d68
RE		 8947 }
8948
d5b7b3ae
RE		 8949 minipool_vector_head = minipool_vector_tail = NULL;
8950 scan = emit_insn_after (gen_consttable_end (), scan);
8951 scan = emit_barrier_after (scan);
2b835d68
RE		 8952}
8953
d5b7b3ae
RE		 8954/* Return the cost of forcibly inserting a barrier after INSN. */
8955static int
e32bac5b 8956arm_barrier_cost (rtx insn)
949d79eb 8957{
d5b7b3ae
RE		 8958 /* Basing the location of the pool on the loop depth is preferable,
8959 but at the moment, the basic block information seems to be
8960 corrupt by this stage of the compilation. */
8961 int base_cost = 50;
8962 rtx next = next_nonnote_insn (insn);
8963
8964 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8965 base_cost -= 20;
8966
8967 switch (GET_CODE (insn))
8968 {
8969 case CODE_LABEL:
8970 /* It will always be better to place the table before the label, rather
8971 than after it. */
f676971a 8972 return 50;
949d79eb 8973
d5b7b3ae
RE		 8974 case INSN:
8975 case CALL_INSN:
8976 return base_cost;
8977
8978 case JUMP_INSN:
8979 return base_cost - 10;
8980
8981 default:
8982 return base_cost + 10;
8983 }
8984}
8985
8986/* Find the best place in the insn stream in the range
8987 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8988 Create the barrier by inserting a jump and add a new fix entry for
8989 it. */
8990static Mfix *
e32bac5b 8991create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
d5b7b3ae
RE		 8992{
8993 HOST_WIDE_INT count = 0;
8994 rtx barrier;
8995 rtx from = fix->insn;
7a7017bc
PB		 8996 /* The instruction after which we will insert the jump. */
8997 rtx selected = NULL;
d5b7b3ae 8998 int selected_cost;
7a7017bc 8999 /* The address at which the jump instruction will be placed. */
d5b7b3ae
RE		 9000 HOST_WIDE_INT selected_address;
9001 Mfix * new_fix;
9002 HOST_WIDE_INT max_count = max_address - fix->address;
9003 rtx label = gen_label_rtx ();
9004
9005 selected_cost = arm_barrier_cost (from);
9006 selected_address = fix->address;
9007
9008 while (from && count < max_count)
9009 {
9010 rtx tmp;
9011 int new_cost;
9012
9013 /* This code shouldn't have been called if there was a natural barrier
9014 within range. */
e6d29d15 9015 gcc_assert (GET_CODE (from) != BARRIER);
d5b7b3ae
RE		 9016
9017 /* Count the length of this insn. */
9018 count += get_attr_length (from);
9019
9020 /* If there is a jump table, add its length. */
9021 tmp = is_jump_table (from);
9022 if (tmp != NULL)
9023 {
9024 count += get_jump_table_size (tmp);
9025
9026 /* Jump tables aren't in a basic block, so base the cost on
9027 the dispatch insn. If we select this location, we will
9028 still put the pool after the table. */
9029 new_cost = arm_barrier_cost (from);
9030
7a7017bc
PB		 9031 if (count < max_count
9032 && (!selected || new_cost <= selected_cost))
d5b7b3ae
RE		 9033 {
9034 selected = tmp;
9035 selected_cost = new_cost;
9036 selected_address = fix->address + count;
9037 }
9038
9039 /* Continue after the dispatch table. */
9040 from = NEXT_INSN (tmp);
9041 continue;
9042 }
9043
9044 new_cost = arm_barrier_cost (from);
f676971a 9045
7a7017bc
PB		 9046 if (count < max_count
9047 && (!selected || new_cost <= selected_cost))
d5b7b3ae
RE		 9048 {
9049 selected = from;
9050 selected_cost = new_cost;
9051 selected_address = fix->address + count;
9052 }
9053
9054 from = NEXT_INSN (from);
9055 }
9056
7a7017bc
PB		 9057 /* Make sure that we found a place to insert the jump. */
9058 gcc_assert (selected);
9059
d5b7b3ae
RE		 9060 /* Create a new JUMP_INSN that branches around a barrier. */
9061 from = emit_jump_insn_after (gen_jump (label), selected);
9062 JUMP_LABEL (from) = label;
9063 barrier = emit_barrier_after (from);
9064 emit_label_after (label, barrier);
9065
9066 /* Create a minipool barrier entry for the new barrier. */
c7319d87 9067 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
d5b7b3ae
RE		 9068 new_fix->insn = barrier;
9069 new_fix->address = selected_address;
9070 new_fix->next = fix->next;
9071 fix->next = new_fix;
9072
9073 return new_fix;
9074}
9075
9076/* Record that there is a natural barrier in the insn stream at
9077 ADDRESS. */
949d79eb 9078static void
e32bac5b 9079push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
2b835d68 9080{
c7319d87 9081 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
ad076f4e 9082
949d79eb
RE		 9083 fix->insn = insn;
9084 fix->address = address;
2b835d68 9085
949d79eb
RE		 9086 fix->next = NULL;
9087 if (minipool_fix_head != NULL)
9088 minipool_fix_tail->next = fix;
9089 else
9090 minipool_fix_head = fix;
9091
9092 minipool_fix_tail = fix;
9093}
2b835d68 9094
d5b7b3ae
RE		 9095/* Record INSN, which will need fixing up to load a value from the
9096 minipool. ADDRESS is the offset of the insn since the start of the
9097 function; LOC is a pointer to the part of the insn which requires
9098 fixing; VALUE is the constant that must be loaded, which is of type
9099 MODE. */
949d79eb 9100static void
e32bac5b
RE		 9101push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
9102 enum machine_mode mode, rtx value)
949d79eb 9103{
c7319d87 9104 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
949d79eb 9105
949d79eb
RE		 9106 fix->insn = insn;
9107 fix->address = address;
9108 fix->loc = loc;
9109 fix->mode = mode;
d5b7b3ae 9110 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
949d79eb 9111 fix->value = value;
d5b7b3ae
RE		 9112 fix->forwards = get_attr_pool_range (insn);
9113 fix->backwards = get_attr_neg_pool_range (insn);
9114 fix->minipool = NULL;
949d79eb
RE		 9115
9116 /* If an insn doesn't have a range defined for it, then it isn't
e6d29d15 9117 expecting to be reworked by this code. Better to stop now than
949d79eb 9118 to generate duff assembly code. */
e6d29d15 9119 gcc_assert (fix->forwards || fix->backwards);
949d79eb 9120
34a9f549
PB		 9121 /* If an entry requires 8-byte alignment then assume all constant pools
9122 require 4 bytes of padding. Trying to do this later on a per-pool
917f1b7e 9123 basis is awkward because existing pool entries have to be modified. */
88f77cba 9124 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8)
34a9f549 9125 minipool_pad = 4;
5a9335ef 9126
c263766c 9127 if (dump_file)
d5b7b3ae 9128 {
c263766c 9129 fprintf (dump_file,
d5b7b3ae
RE		 9130 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
9131 GET_MODE_NAME (mode),
f676971a 9132 INSN_UID (insn), (unsigned long) address,
d5b7b3ae 9133 -1 * (long)fix->backwards, (long)fix->forwards);
c263766c
RH		 9134 arm_print_value (dump_file, fix->value);
9135 fprintf (dump_file, "\n");
d5b7b3ae
RE		 9136 }
9137
6354dc9b 9138 /* Add it to the chain of fixes. */
949d79eb 9139 fix->next = NULL;
f676971a 9140
949d79eb
RE		 9141 if (minipool_fix_head != NULL)
9142 minipool_fix_tail->next = fix;
9143 else
9144 minipool_fix_head = fix;
9145
9146 minipool_fix_tail = fix;
9147}
9148
9b901d50 9149/* Return the cost of synthesizing a 64-bit constant VAL inline.
2075b05d
RE		 9150 Returns the number of insns needed, or 99 if we don't know how to
9151 do it. */
9152int
9153arm_const_double_inline_cost (rtx val)
b9e8bfda 9154{
9b901d50
RE		 9155 rtx lowpart, highpart;
9156 enum machine_mode mode;
e0b92319 9157
9b901d50 9158 mode = GET_MODE (val);
b9e8bfda 9159
9b901d50
RE		 9160 if (mode == VOIDmode)
9161 mode = DImode;
9162
9163 gcc_assert (GET_MODE_SIZE (mode) == 8);
e0b92319 9164
9b901d50
RE		 9165 lowpart = gen_lowpart (SImode, val);
9166 highpart = gen_highpart_mode (SImode, mode, val);
e0b92319 9167
9b901d50
RE		 9168 gcc_assert (GET_CODE (lowpart) == CONST_INT);
9169 gcc_assert (GET_CODE (highpart) == CONST_INT);
9170
9171 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
2075b05d 9172 NULL_RTX, NULL_RTX, 0, 0)
9b901d50 9173 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
2075b05d
RE		 9174 NULL_RTX, NULL_RTX, 0, 0));
9175}
9176
f3b569ca 9177/* Return true if it is worthwhile to split a 64-bit constant into two
b4a58f80
RE		 9178 32-bit operations. This is the case if optimizing for size, or
9179 if we have load delay slots, or if one 32-bit part can be done with
9180 a single data operation. */
9181bool
9182arm_const_double_by_parts (rtx val)
9183{
9184 enum machine_mode mode = GET_MODE (val);
9185 rtx part;
9186
9187 if (optimize_size || arm_ld_sched)
9188 return true;
9189
9190 if (mode == VOIDmode)
9191 mode = DImode;
e0b92319 9192
b4a58f80 9193 part = gen_highpart_mode (SImode, mode, val);
e0b92319 9194
b4a58f80 9195 gcc_assert (GET_CODE (part) == CONST_INT);
e0b92319 9196
b4a58f80
RE		 9197 if (const_ok_for_arm (INTVAL (part))
9198 || const_ok_for_arm (~INTVAL (part)))
9199 return true;
e0b92319 9200
b4a58f80 9201 part = gen_lowpart (SImode, val);
e0b92319 9202
b4a58f80 9203 gcc_assert (GET_CODE (part) == CONST_INT);
e0b92319 9204
b4a58f80
RE		 9205 if (const_ok_for_arm (INTVAL (part))
9206 || const_ok_for_arm (~INTVAL (part)))
9207 return true;
e0b92319 9208
b4a58f80
RE		 9209 return false;
9210}
9211
f0375c66
NC		 9212/* Scan INSN and note any of its operands that need fixing.
9213 If DO_PUSHES is false we do not actually push any of the fixups
9b901d50 9214 needed. The function returns TRUE if any fixups were needed/pushed.
f0375c66
NC		 9215 This is used by arm_memory_load_p() which needs to know about loads
9216 of constants that will be converted into minipool loads. */
f0375c66 9217static bool
e32bac5b 9218note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
949d79eb 9219{
f0375c66 9220 bool result = false;
949d79eb
RE		 9221 int opno;
9222
d5b7b3ae 9223 extract_insn (insn);
949d79eb 9224
5895f793 9225 if (!constrain_operands (1))
949d79eb
RE		 9226 fatal_insn_not_found (insn);
9227
8c2a5582
RE		 9228 if (recog_data.n_alternatives == 0)
9229 return false;
9230
9b901d50
RE		 9231 /* Fill in recog_op_alt with information about the constraints of
9232 this insn. */
949d79eb
RE		 9233 preprocess_constraints ();
9234
1ccbefce 9235 for (opno = 0; opno < recog_data.n_operands; opno++)
949d79eb 9236 {
6354dc9b 9237 /* Things we need to fix can only occur in inputs. */
36ab44c7 9238 if (recog_data.operand_type[opno] != OP_IN)
949d79eb
RE		 9239 continue;
9240
9241 /* If this alternative is a memory reference, then any mention
9242 of constants in this alternative is really to fool reload
9243 into allowing us to accept one there. We need to fix them up
9244 now so that we output the right code. */
9245 if (recog_op_alt[opno][which_alternative].memory_ok)
9246 {
1ccbefce 9247 rtx op = recog_data.operand[opno];
949d79eb 9248
9b901d50 9249 if (CONSTANT_P (op))
f0375c66
NC		 9250 {
9251 if (do_pushes)
9252 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
9253 recog_data.operand_mode[opno], op);
9254 result = true;
9255 }
d5b7b3ae 9256 else if (GET_CODE (op) == MEM
949d79eb
RE		 9257 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
9258 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
f0375c66
NC		 9259 {
9260 if (do_pushes)
244b1afb
RE		 9261 {
9262 rtx cop = avoid_constant_pool_reference (op);
9263
9264 /* Casting the address of something to a mode narrower
9265 than a word can cause avoid_constant_pool_reference()
9266 to return the pool reference itself. That's no good to
f676971a 9267 us here. Lets just hope that we can use the
244b1afb
RE		 9268 constant pool value directly. */
9269 if (op == cop)
c769a35d 9270 cop = get_pool_constant (XEXP (op, 0));
244b1afb
RE		 9271
9272 push_minipool_fix (insn, address,
9273 recog_data.operand_loc[opno],
c769a35d 9274 recog_data.operand_mode[opno], cop);
244b1afb 9275 }
f0375c66
NC		 9276
9277 result = true;
9278 }
949d79eb 9279 }
2b835d68 9280 }
f0375c66
NC		 9281
9282 return result;
2b835d68
RE		 9283}
9284
18dbd950
RS		 9285/* Gcc puts the pool in the wrong place for ARM, since we can only
9286 load addresses a limited distance around the pc. We do some
9287 special munging to move the constant pool values to the correct
9288 point in the code. */
18dbd950 9289static void
e32bac5b 9290arm_reorg (void)
2b835d68
RE		 9291{
9292 rtx insn;
d5b7b3ae
RE		 9293 HOST_WIDE_INT address = 0;
9294 Mfix * fix;
ad076f4e 9295
949d79eb 9296 minipool_fix_head = minipool_fix_tail = NULL;
2b835d68 9297
949d79eb
RE		 9298 /* The first insn must always be a note, or the code below won't
9299 scan it properly. */
18dbd950 9300 insn = get_insns ();
e6d29d15 9301 gcc_assert (GET_CODE (insn) == NOTE);
34a9f549 9302 minipool_pad = 0;
949d79eb
RE		 9303
9304 /* Scan all the insns and record the operands that will need fixing. */
18dbd950 9305 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
2b835d68 9306 {
9b6b54e2 9307 if (TARGET_CIRRUS_FIX_INVALID_INSNS
f0375c66 9308 && (arm_cirrus_insn_p (insn)
9b6b54e2 9309 || GET_CODE (insn) == JUMP_INSN
f0375c66 9310 || arm_memory_load_p (insn)))
9b6b54e2
NC		 9311 cirrus_reorg (insn);
9312
949d79eb 9313 if (GET_CODE (insn) == BARRIER)
d5b7b3ae 9314 push_minipool_barrier (insn, address);
f0375c66 9315 else if (INSN_P (insn))
949d79eb
RE		 9316 {
9317 rtx table;
9318
f0375c66 9319 note_invalid_constants (insn, address, true);
949d79eb 9320 address += get_attr_length (insn);
d5b7b3ae 9321
949d79eb
RE		 9322 /* If the insn is a vector jump, add the size of the table
9323 and skip the table. */
d5b7b3ae 9324 if ((table = is_jump_table (insn)) != NULL)
2b835d68 9325 {
d5b7b3ae 9326 address += get_jump_table_size (table);
949d79eb
RE		 9327 insn = table;
9328 }
9329 }
9330 }
332072db 9331
d5b7b3ae 9332 fix = minipool_fix_head;
f676971a 9333
949d79eb 9334 /* Now scan the fixups and perform the required changes. */
d5b7b3ae 9335 while (fix)
949d79eb 9336 {
d5b7b3ae
RE		 9337 Mfix * ftmp;
9338 Mfix * fdel;
9339 Mfix * last_added_fix;
9340 Mfix * last_barrier = NULL;
9341 Mfix * this_fix;
949d79eb
RE		 9342
9343 /* Skip any further barriers before the next fix. */
9344 while (fix && GET_CODE (fix->insn) == BARRIER)
9345 fix = fix->next;
9346
d5b7b3ae 9347 /* No more fixes. */
949d79eb
RE		 9348 if (fix == NULL)
9349 break;
332072db 9350
d5b7b3ae 9351 last_added_fix = NULL;
2b835d68 9352
d5b7b3ae 9353 for (ftmp = fix; ftmp; ftmp = ftmp->next)
949d79eb 9354 {
949d79eb 9355 if (GET_CODE (ftmp->insn) == BARRIER)
949d79eb 9356 {
d5b7b3ae
RE		 9357 if (ftmp->address >= minipool_vector_head->max_address)
9358 break;
2b835d68 9359
d5b7b3ae 9360 last_barrier = ftmp;
2b835d68 9361 }
d5b7b3ae
RE		 9362 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
9363 break;
9364
9365 last_added_fix = ftmp; /* Keep track of the last fix added. */
2b835d68 9366 }
949d79eb 9367
d5b7b3ae
RE		 9368 /* If we found a barrier, drop back to that; any fixes that we
9369 could have reached but come after the barrier will now go in
9370 the next mini-pool. */
949d79eb
RE		 9371 if (last_barrier != NULL)
9372 {
f676971a 9373 /* Reduce the refcount for those fixes that won't go into this
d5b7b3ae
RE		 9374 pool after all. */
9375 for (fdel = last_barrier->next;
9376 fdel && fdel != ftmp;
9377 fdel = fdel->next)
9378 {
9379 fdel->minipool->refcount--;
9380 fdel->minipool = NULL;
9381 }
9382
949d79eb
RE		 9383 ftmp = last_barrier;
9384 }
9385 else
2bfa88dc 9386 {
d5b7b3ae
RE		 9387 /* ftmp is first fix that we can't fit into this pool and
9388 there no natural barriers that we could use. Insert a
9389 new barrier in the code somewhere between the previous
9390 fix and this one, and arrange to jump around it. */
9391 HOST_WIDE_INT max_address;
9392
9393 /* The last item on the list of fixes must be a barrier, so
9394 we can never run off the end of the list of fixes without
9395 last_barrier being set. */
e6d29d15 9396 gcc_assert (ftmp);
d5b7b3ae
RE		 9397
9398 max_address = minipool_vector_head->max_address;
2bfa88dc
RE		 9399 /* Check that there isn't another fix that is in range that
9400 we couldn't fit into this pool because the pool was
9401 already too large: we need to put the pool before such an
7a7017bc
PB		 9402 instruction. The pool itself may come just after the
9403 fix because create_fix_barrier also allows space for a
9404 jump instruction. */
d5b7b3ae 9405 if (ftmp->address < max_address)
7a7017bc 9406 max_address = ftmp->address + 1;
d5b7b3ae
RE		 9407
9408 last_barrier = create_fix_barrier (last_added_fix, max_address);
9409 }
9410
9411 assign_minipool_offsets (last_barrier);
9412
9413 while (ftmp)
9414 {
9415 if (GET_CODE (ftmp->insn) != BARRIER
9416 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
9417 == NULL))
9418 break;
2bfa88dc 9419
d5b7b3ae 9420 ftmp = ftmp->next;
2bfa88dc 9421 }
949d79eb
RE		 9422
9423 /* Scan over the fixes we have identified for this pool, fixing them
9424 up and adding the constants to the pool itself. */
d5b7b3ae 9425 for (this_fix = fix; this_fix && ftmp != this_fix;
949d79eb
RE		 9426 this_fix = this_fix->next)
9427 if (GET_CODE (this_fix->insn) != BARRIER)
9428 {
949d79eb 9429 rtx addr
f676971a 9430 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
949d79eb 9431 minipool_vector_label),
d5b7b3ae 9432 this_fix->minipool->offset);
949d79eb
RE		 9433 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
9434 }
9435
d5b7b3ae 9436 dump_minipool (last_barrier->insn);
949d79eb 9437 fix = ftmp;
2b835d68 9438 }
4b632bf1 9439
949d79eb
RE		 9440 /* From now on we must synthesize any constants that we can't handle
9441 directly. This can happen if the RTL gets split during final
9442 instruction generation. */
4b632bf1 9443 after_arm_reorg = 1;
c7319d87
RE		 9444
9445 /* Free the minipool memory. */
9446 obstack_free (&minipool_obstack, minipool_startobj);
2b835d68 9447}
cce8749e
CH		 9448\f
9449/* Routines to output assembly language. */
9450
f3bb6135 9451/* If the rtx is the correct value then return the string of the number.
ff9940b0 9452 In this way we can ensure that valid double constants are generated even
6354dc9b 9453 when cross compiling. */
cd2b33d0 9454const char *
e32bac5b 9455fp_immediate_constant (rtx x)
ff9940b0
RE		 9456{
9457 REAL_VALUE_TYPE r;
9458 int i;
f676971a 9459
9b66ebb1
PB		 9460 if (!fp_consts_inited)
9461 init_fp_table ();
f676971a 9462
ff9940b0
RE		 9463 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9464 for (i = 0; i < 8; i++)
9b66ebb1
PB		 9465 if (REAL_VALUES_EQUAL (r, values_fp[i]))
9466 return strings_fp[i];
f3bb6135 9467
e6d29d15 9468 gcc_unreachable ();
ff9940b0
RE		 9469}
9470
9997d19d 9471/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
cd2b33d0 9472static const char *
e32bac5b 9473fp_const_from_val (REAL_VALUE_TYPE *r)
9997d19d
RE		 9474{
9475 int i;
9476
9b66ebb1
PB		 9477 if (!fp_consts_inited)
9478 init_fp_table ();
9997d19d
RE		 9479
9480 for (i = 0; i < 8; i++)
9b66ebb1
PB		 9481 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
9482 return strings_fp[i];
9997d19d 9483
e6d29d15 9484 gcc_unreachable ();
9997d19d 9485}
ff9940b0 9486
cce8749e
CH		 9487/* Output the operands of a LDM/STM instruction to STREAM.
9488 MASK is the ARM register set mask of which only bits 0-15 are important.
6d3d9133 9489 REG is the base register, either the frame pointer or the stack pointer,
a15908a4
PB		 9490 INSTR is the possibly suffixed load or store instruction.
9491 RFE is nonzero if the instruction should also copy spsr to cpsr. */
b279b20a 9492
d5b7b3ae 9493static void
b279b20a 9494print_multi_reg (FILE *stream, const char *instr, unsigned reg,
a15908a4 9495 unsigned long mask, int rfe)
cce8749e 9496{
b279b20a
NC		 9497 unsigned i;
9498 bool not_first = FALSE;
cce8749e 9499
a15908a4 9500 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
1d5473cb 9501 fputc ('\t', stream);
dd18ae56 9502 asm_fprintf (stream, instr, reg);
5b3e6663 9503 fputc ('{', stream);
f676971a 9504
d5b7b3ae 9505 for (i = 0; i <= LAST_ARM_REGNUM; i++)
cce8749e
CH		 9506 if (mask & (1 << i))
9507 {
9508 if (not_first)
9509 fprintf (stream, ", ");
f676971a 9510
dd18ae56 9511 asm_fprintf (stream, "%r", i);
cce8749e
CH		 9512 not_first = TRUE;
9513 }
f3bb6135 9514
a15908a4
PB		 9515 if (rfe)
9516 fprintf (stream, "}^\n");
9517 else
9518 fprintf (stream, "}\n");
f3bb6135 9519}
cce8749e 9520
9b66ebb1 9521
8edfc4cc 9522/* Output a FLDMD instruction to STREAM.
9728c9d1
PB		 9523 BASE if the register containing the address.
9524 REG and COUNT specify the register range.
8edfc4cc
MS		 9525 Extra registers may be added to avoid hardware bugs.
9526
9527 We output FLDMD even for ARMv5 VFP implementations. Although
9528 FLDMD is technically not supported until ARMv6, it is believed
9529 that all VFP implementations support its use in this context. */
9b66ebb1
PB		 9530
9531static void
8edfc4cc 9532vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
9b66ebb1
PB		 9533{
9534 int i;
9535
9728c9d1
PB		 9536 /* Workaround ARM10 VFPr1 bug. */
9537 if (count == 2 && !arm_arch6)
9538 {
9539 if (reg == 15)
9540 reg--;
9541 count++;
9542 }
9543
f1adb0a9
JB		 9544 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
9545 load into multiple parts if we have to handle more than 16 registers. */
9546 if (count > 16)
9547 {
9548 vfp_output_fldmd (stream, base, reg, 16);
9549 vfp_output_fldmd (stream, base, reg + 16, count - 16);
9550 return;
9551 }
9552
9b66ebb1 9553 fputc ('\t', stream);
8edfc4cc 9554 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
9b66ebb1 9555
9728c9d1 9556 for (i = reg; i < reg + count; i++)
9b66ebb1 9557 {
9728c9d1 9558 if (i > reg)
9b66ebb1 9559 fputs (", ", stream);
9728c9d1 9560 asm_fprintf (stream, "d%d", i);
9b66ebb1
PB		 9561 }
9562 fputs ("}\n", stream);
9728c9d1 9563
9b66ebb1
PB		 9564}
9565
9566
9567/* Output the assembly for a store multiple. */
9568
9569const char *
8edfc4cc 9570vfp_output_fstmd (rtx * operands)
9b66ebb1
PB		 9571{
9572 char pattern[100];
9573 int p;
9574 int base;
9575 int i;
9576
8edfc4cc 9577 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
9b66ebb1
PB		 9578 p = strlen (pattern);
9579
e6d29d15 9580 gcc_assert (GET_CODE (operands[1]) == REG);
9b66ebb1
PB		 9581
9582 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
9583 for (i = 1; i < XVECLEN (operands[2], 0); i++)
9584 {
9585 p += sprintf (&pattern[p], ", d%d", base + i);
9586 }
9587 strcpy (&pattern[p], "}");
9588
9589 output_asm_insn (pattern, operands);
9590 return "";
9591}
9592
9593
9728c9d1
PB		 9594/* Emit RTL to save block of VFP register pairs to the stack. Returns the
9595 number of bytes pushed. */
9b66ebb1 9596
9728c9d1 9597static int
8edfc4cc 9598vfp_emit_fstmd (int base_reg, int count)
9b66ebb1
PB		 9599{
9600 rtx par;
9601 rtx dwarf;
9602 rtx tmp, reg;
9603 int i;
9604
9728c9d1
PB		 9605 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
9606 register pairs are stored by a store multiple insn. We avoid this
9607 by pushing an extra pair. */
9608 if (count == 2 && !arm_arch6)
9609 {
9610 if (base_reg == LAST_VFP_REGNUM - 3)
9611 base_reg -= 2;
9612 count++;
9613 }
9614
f1adb0a9
JB		 9615 /* FSTMD may not store more than 16 doubleword registers at once. Split
9616 larger stores into multiple parts (up to a maximum of two, in
9617 practice). */
9618 if (count > 16)
9619 {
9620 int saved;
9621 /* NOTE: base_reg is an internal register number, so each D register
9622 counts as 2. */
9623 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
9624 saved += vfp_emit_fstmd (base_reg, 16);
9625 return saved;
9626 }
9627
9b66ebb1
PB		 9628 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9629 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9630
9631 reg = gen_rtx_REG (DFmode, base_reg);
9632 base_reg += 2;
9633
9634 XVECEXP (par, 0, 0)
9635 = gen_rtx_SET (VOIDmode,
31fa16b6
RE		 9636 gen_frame_mem (BLKmode,
9637 gen_rtx_PRE_DEC (BLKmode,
9638 stack_pointer_rtx)),
9b66ebb1
PB		 9639 gen_rtx_UNSPEC (BLKmode,
9640 gen_rtvec (1, reg),
9641 UNSPEC_PUSH_MULT));
9642
9643 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8edfc4cc 9644 plus_constant (stack_pointer_rtx, -(count * 8)));
9b66ebb1
PB		 9645 RTX_FRAME_RELATED_P (tmp) = 1;
9646 XVECEXP (dwarf, 0, 0) = tmp;
9647
9648 tmp = gen_rtx_SET (VOIDmode,
31fa16b6 9649 gen_frame_mem (DFmode, stack_pointer_rtx),
9b66ebb1
PB		 9650 reg);
9651 RTX_FRAME_RELATED_P (tmp) = 1;
9652 XVECEXP (dwarf, 0, 1) = tmp;
9653
9654 for (i = 1; i < count; i++)
9655 {
9656 reg = gen_rtx_REG (DFmode, base_reg);
9657 base_reg += 2;
9658 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9659
9660 tmp = gen_rtx_SET (VOIDmode,
31fa16b6 9661 gen_frame_mem (DFmode,
d66437c5
RE		 9662 plus_constant (stack_pointer_rtx,
9663 i * 8)),
9b66ebb1
PB		 9664 reg);
9665 RTX_FRAME_RELATED_P (tmp) = 1;
9666 XVECEXP (dwarf, 0, i + 1) = tmp;
9667 }
9668
9669 par = emit_insn (par);
9670 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9671 REG_NOTES (par));
9728c9d1
PB		 9672 RTX_FRAME_RELATED_P (par) = 1;
9673
8edfc4cc 9674 return count * 8;
9b66ebb1
PB		 9675}
9676
9403b7f7
RS		 9677/* Emit a call instruction with pattern PAT. ADDR is the address of
9678 the call target. */
9679
9680void
9681arm_emit_call_insn (rtx pat, rtx addr)
9682{
9683 rtx insn;
9684
9685 insn = emit_call_insn (pat);
9686
9687 /* The PIC register is live on entry to VxWorks PIC PLT entries.
9688 If the call might use such an entry, add a use of the PIC register
9689 to the instruction's CALL_INSN_FUNCTION_USAGE. */
9690 if (TARGET_VXWORKS_RTP
9691 && flag_pic
9692 && GET_CODE (addr) == SYMBOL_REF
9693 && (SYMBOL_REF_DECL (addr)
9694 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
9695 : !SYMBOL_REF_LOCAL_P (addr)))
9696 {
9697 require_pic_register ();
9698 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
9699 }
9700}
9b66ebb1 9701
6354dc9b 9702/* Output a 'call' insn. */
cd2b33d0 9703const char *
e32bac5b 9704output_call (rtx *operands)
cce8749e 9705{
e6d29d15 9706 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
cce8749e 9707
68d560d4 9708 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
62b10bbc 9709 if (REGNO (operands[0]) == LR_REGNUM)
cce8749e 9710 {
62b10bbc 9711 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
1d5473cb 9712 output_asm_insn ("mov%?\t%0, %|lr", operands);
cce8749e 9713 }
f676971a 9714
1d5473cb 9715 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
f676971a 9716
68d560d4 9717 if (TARGET_INTERWORK || arm_arch4t)
da6558fd
NC		 9718 output_asm_insn ("bx%?\t%0", operands);
9719 else
9720 output_asm_insn ("mov%?\t%|pc, %0", operands);
f676971a 9721
f3bb6135
RE		 9722 return "";
9723}
cce8749e 9724
6354dc9b 9725/* Output a 'call' insn that is a reference in memory. */
cd2b33d0 9726const char *
e32bac5b 9727output_call_mem (rtx *operands)
ff9940b0 9728{
68d560d4 9729 if (TARGET_INTERWORK && !arm_arch5)
da6558fd
NC		 9730 {
9731 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9732 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9733 output_asm_insn ("bx%?\t%|ip", operands);
9734 }
6ab5da80
RE		 9735 else if (regno_use_in (LR_REGNUM, operands[0]))
9736 {
9737 /* LR is used in the memory address. We load the address in the
9738 first instruction. It's safe to use IP as the target of the
9739 load since the call will kill it anyway. */
9740 output_asm_insn ("ldr%?\t%|ip, %0", operands);
68d560d4 9741 if (arm_arch5)
07ec3810 9742 output_asm_insn ("blx%?\t%|ip", operands);
68d560d4
RE		 9743 else
9744 {
9745 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9746 if (arm_arch4t)
9747 output_asm_insn ("bx%?\t%|ip", operands);
9748 else
9749 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
9750 }
6ab5da80 9751 }
da6558fd
NC		 9752 else
9753 {
9754 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9755 output_asm_insn ("ldr%?\t%|pc, %0", operands);
9756 }
9757
f3bb6135
RE		 9758 return "";
9759}
ff9940b0
RE		 9760
9761
3b684012
RE		 9762/* Output a move from arm registers to an fpa registers.
9763 OPERANDS[0] is an fpa register.
ff9940b0 9764 OPERANDS[1] is the first registers of an arm register pair. */
cd2b33d0 9765const char *
e32bac5b 9766output_mov_long_double_fpa_from_arm (rtx *operands)
ff9940b0
RE		 9767{
9768 int arm_reg0 = REGNO (operands[1]);
9769 rtx ops[3];
9770
e6d29d15 9771 gcc_assert (arm_reg0 != IP_REGNUM);
f3bb6135 9772
43cffd11
RE		 9773 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9774 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9775 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
f676971a 9776
5b3e6663 9777 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
1d5473cb 9778 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
f676971a 9779
f3bb6135
RE		 9780 return "";
9781}
ff9940b0 9782
3b684012 9783/* Output a move from an fpa register to arm registers.
ff9940b0 9784 OPERANDS[0] is the first registers of an arm register pair.
3b684012 9785 OPERANDS[1] is an fpa register. */
cd2b33d0 9786const char *
e32bac5b 9787output_mov_long_double_arm_from_fpa (rtx *operands)
ff9940b0
RE		 9788{
9789 int arm_reg0 = REGNO (operands[0]);
9790 rtx ops[3];
9791
e6d29d15 9792 gcc_assert (arm_reg0 != IP_REGNUM);
f3bb6135 9793
43cffd11
RE		 9794 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9795 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9796 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
ff9940b0 9797
1d5473cb 9798 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
5b3e6663 9799 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
f3bb6135
RE		 9800 return "";
9801}
ff9940b0
RE		 9802
9803/* Output a move from arm registers to arm registers of a long double
9804 OPERANDS[0] is the destination.
9805 OPERANDS[1] is the source. */
cd2b33d0 9806const char *
e32bac5b 9807output_mov_long_double_arm_from_arm (rtx *operands)
ff9940b0 9808{
6354dc9b 9809 /* We have to be careful here because the two might overlap. */
ff9940b0
RE		 9810 int dest_start = REGNO (operands[0]);
9811 int src_start = REGNO (operands[1]);
9812 rtx ops[2];
9813 int i;
9814
9815 if (dest_start < src_start)
9816 {
9817 for (i = 0; i < 3; i++)
9818 {
43cffd11
RE		 9819 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9820 ops[1] = gen_rtx_REG (SImode, src_start + i);
9997d19d 9821 output_asm_insn ("mov%?\t%0, %1", ops);
ff9940b0
RE		 9822 }
9823 }
9824 else
9825 {
9826 for (i = 2; i >= 0; i--)
9827 {
43cffd11
RE		 9828 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9829 ops[1] = gen_rtx_REG (SImode, src_start + i);
9997d19d 9830 output_asm_insn ("mov%?\t%0, %1", ops);
ff9940b0
RE		 9831 }
9832 }
f3bb6135 9833
ff9940b0
RE		 9834 return "";
9835}
9836
9837
3b684012
RE		 9838/* Output a move from arm registers to an fpa registers.
9839 OPERANDS[0] is an fpa register.
cce8749e 9840 OPERANDS[1] is the first registers of an arm register pair. */
cd2b33d0 9841const char *
e32bac5b 9842output_mov_double_fpa_from_arm (rtx *operands)
cce8749e
CH		 9843{
9844 int arm_reg0 = REGNO (operands[1]);
9845 rtx ops[2];
9846
e6d29d15 9847 gcc_assert (arm_reg0 != IP_REGNUM);
f676971a 9848
43cffd11
RE		 9849 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9850 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
5b3e6663 9851 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
1d5473cb 9852 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
f3bb6135
RE		 9853 return "";
9854}
cce8749e 9855
3b684012 9856/* Output a move from an fpa register to arm registers.
cce8749e 9857 OPERANDS[0] is the first registers of an arm register pair.
3b684012 9858 OPERANDS[1] is an fpa register. */
cd2b33d0 9859const char *
e32bac5b 9860output_mov_double_arm_from_fpa (rtx *operands)
cce8749e
CH		 9861{
9862 int arm_reg0 = REGNO (operands[0]);
9863 rtx ops[2];
9864
e6d29d15 9865 gcc_assert (arm_reg0 != IP_REGNUM);
f3bb6135 9866
43cffd11
RE		 9867 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9868 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
1d5473cb 9869 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
5b3e6663 9870 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
f3bb6135
RE		 9871 return "";
9872}
cce8749e
CH		 9873
9874/* Output a move between double words.
9875 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9876 or MEM<-REG and all MEMs must be offsettable addresses. */
cd2b33d0 9877const char *
e32bac5b 9878output_move_double (rtx *operands)
cce8749e
CH		 9879{
9880 enum rtx_code code0 = GET_CODE (operands[0]);
9881 enum rtx_code code1 = GET_CODE (operands[1]);
56636818 9882 rtx otherops[3];
cce8749e
CH		 9883
9884 if (code0 == REG)
9885 {
9886 int reg0 = REGNO (operands[0]);
9887
43cffd11 9888 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
f676971a 9889
e6d29d15
NS		 9890 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9891
9892 switch (GET_CODE (XEXP (operands[1], 0)))
cce8749e 9893 {
e6d29d15 9894 case REG:
5dea0c19
PB		 9895 if (TARGET_LDRD)
9896 output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands);
9897 else
9898 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
e6d29d15 9899 break;
e0b92319 9900
e6d29d15
NS		 9901 case PRE_INC:
9902 gcc_assert (TARGET_LDRD);
5b3e6663 9903 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
e6d29d15 9904 break;
e0b92319 9905
e6d29d15 9906 case PRE_DEC:
5b3e6663
PB		 9907 if (TARGET_LDRD)
9908 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9909 else
9910 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
e6d29d15 9911 break;
e0b92319 9912
e6d29d15 9913 case POST_INC:
5dea0c19
PB		 9914 if (TARGET_LDRD)
9915 output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands);
9916 else
9917 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
e6d29d15 9918 break;
e0b92319 9919
e6d29d15
NS		 9920 case POST_DEC:
9921 gcc_assert (TARGET_LDRD);
5b3e6663 9922 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
e6d29d15 9923 break;
e0b92319 9924
e6d29d15
NS		 9925 case PRE_MODIFY:
9926 case POST_MODIFY:
9927 otherops[0] = operands[0];
9928 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9929 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
e0b92319 9930
e6d29d15 9931 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
cce8749e 9932 {
e6d29d15 9933 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
fdd695fd 9934 {
e6d29d15
NS		 9935 /* Registers overlap so split out the increment. */
9936 output_asm_insn ("add%?\t%1, %1, %2", otherops);
5b3e6663 9937 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
fdd695fd
PB		 9938 }
9939 else
fe2d934b
PB		 9940 {
9941 /* IWMMXT allows offsets larger than ldrd can handle,
9942 fix these up with a pair of ldr. */
9943 if (GET_CODE (otherops[2]) == CONST_INT
9944 && (INTVAL(otherops[2]) <= -256
9945 || INTVAL(otherops[2]) >= 256))
9946 {
9947 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9948 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9949 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9950 }
9951 else
9952 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9953 }
e6d29d15
NS		 9954 }
9955 else
9956 {
fe2d934b
PB		 9957 /* IWMMXT allows offsets larger than ldrd can handle,
9958 fix these up with a pair of ldr. */
9959 if (GET_CODE (otherops[2]) == CONST_INT
9960 && (INTVAL(otherops[2]) <= -256
9961 || INTVAL(otherops[2]) >= 256))
9962 {
9963 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9964 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9965 otherops[0] = operands[0];
9966 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9967 }
9968 else
9969 /* We only allow constant increments, so this is safe. */
9970 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
e6d29d15
NS		 9971 }
9972 break;
e0b92319 9973
e6d29d15
NS		 9974 case LABEL_REF:
9975 case CONST:
5dea0c19
PB		 9976 /* We might be able to use ldrd %0, %1 here. However the range is
9977 different to ldr/adr, and it is broken on some ARMv7-M
9978 implementations. */
e6d29d15 9979 output_asm_insn ("adr%?\t%0, %1", operands);
5dea0c19
PB		 9980 if (TARGET_LDRD)
9981 output_asm_insn ("ldr%(d%)\t%0, [%0]", operands);
9982 else
9983 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
e6d29d15 9984 break;
e0b92319 9985
5b3e6663 9986 /* ??? This needs checking for thumb2. */
e6d29d15
NS		 9987 default:
9988 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9989 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9990 {
9991 otherops[0] = operands[0];
9992 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9993 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
e0b92319 9994
e6d29d15 9995 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
fdd695fd 9996 {
5dea0c19 9997 if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
2b835d68 9998 {
e6d29d15 9999 switch ((int) INTVAL (otherops[2]))
2b835d68 10000 {
e6d29d15 10001 case -8:
5b3e6663 10002 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
e6d29d15
NS		 10003 return "";
10004 case -4:
5b3e6663
PB		 10005 if (TARGET_THUMB2)
10006 break;
10007 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
e6d29d15
NS		 10008 return "";
10009 case 4:
5b3e6663
PB		 10010 if (TARGET_THUMB2)
10011 break;
10012 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
e6d29d15 10013 return "";
fdd695fd 10014 }
e6d29d15
NS		 10015 }
10016 if (TARGET_LDRD
10017 && (GET_CODE (otherops[2]) == REG
10018 || (GET_CODE (otherops[2]) == CONST_INT
10019 && INTVAL (otherops[2]) > -256
10020 && INTVAL (otherops[2]) < 256)))
10021 {
10022 if (reg_overlap_mentioned_p (otherops[0],
10023 otherops[2]))
fdd695fd 10024 {
e6d29d15
NS		 10025 /* Swap base and index registers over to
10026 avoid a conflict. */
10027 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
10028 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
fdd695fd 10029 }
e6d29d15
NS		 10030 /* If both registers conflict, it will usually
10031 have been fixed by a splitter. */
10032 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
fdd695fd 10033 {
e6d29d15 10034 output_asm_insn ("add%?\t%1, %1, %2", otherops);
5b3e6663 10035 output_asm_insn ("ldr%(d%)\t%0, [%1]",
e6d29d15 10036 otherops);
2b835d68
RE		 10037 }
10038 else
5b3e6663 10039 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
e6d29d15 10040 return "";
2b835d68 10041 }
e0b92319 10042
e6d29d15 10043 if (GET_CODE (otherops[2]) == CONST_INT)
2b835d68 10044 {
e6d29d15
NS		 10045 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
10046 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
10047 else
10048 output_asm_insn ("add%?\t%0, %1, %2", otherops);
2b835d68
RE		 10049 }
10050 else
e6d29d15
NS		 10051 output_asm_insn ("add%?\t%0, %1, %2", otherops);
10052 }
10053 else
10054 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
10055
5dea0c19
PB		 10056 if (TARGET_LDRD)
10057 return "ldr%(d%)\t%0, [%0]";
10058
5b3e6663 10059 return "ldm%(ia%)\t%0, %M0";
e6d29d15
NS		 10060 }
10061 else
10062 {
10063 otherops[1] = adjust_address (operands[1], SImode, 4);
10064 /* Take care of overlapping base/data reg. */
10065 if (reg_mentioned_p (operands[0], operands[1]))
10066 {
10067 output_asm_insn ("ldr%?\t%0, %1", otherops);
10068 output_asm_insn ("ldr%?\t%0, %1", operands);
10069 }
10070 else
10071 {
10072 output_asm_insn ("ldr%?\t%0, %1", operands);
10073 output_asm_insn ("ldr%?\t%0, %1", otherops);
cce8749e
CH		 10074 }
10075 }
10076 }
cce8749e 10077 }
e6d29d15 10078 else
cce8749e 10079 {
e6d29d15
NS		 10080 /* Constraints should ensure this. */
10081 gcc_assert (code0 == MEM && code1 == REG);
10082 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
2b835d68 10083
ff9940b0
RE		 10084 switch (GET_CODE (XEXP (operands[0], 0)))
10085 {
10086 case REG:
5dea0c19
PB		 10087 if (TARGET_LDRD)
10088 output_asm_insn ("str%(d%)\t%1, [%m0]", operands);
10089 else
10090 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
ff9940b0 10091 break;
2b835d68 10092
ff9940b0 10093 case PRE_INC:
e6d29d15 10094 gcc_assert (TARGET_LDRD);
5b3e6663 10095 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
ff9940b0 10096 break;
2b835d68 10097
ff9940b0 10098 case PRE_DEC:
5b3e6663
PB		 10099 if (TARGET_LDRD)
10100 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
10101 else
10102 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
ff9940b0 10103 break;
2b835d68 10104
ff9940b0 10105 case POST_INC:
5dea0c19
PB		 10106 if (TARGET_LDRD)
10107 output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands);
10108 else
10109 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
ff9940b0 10110 break;
2b835d68 10111
ff9940b0 10112 case POST_DEC:
e6d29d15 10113 gcc_assert (TARGET_LDRD);
5b3e6663 10114 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
fdd695fd
PB		 10115 break;
10116
10117 case PRE_MODIFY:
10118 case POST_MODIFY:
10119 otherops[0] = operands[1];
10120 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
10121 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
10122
fe2d934b
PB		 10123 /* IWMMXT allows offsets larger than ldrd can handle,
10124 fix these up with a pair of ldr. */
10125 if (GET_CODE (otherops[2]) == CONST_INT
10126 && (INTVAL(otherops[2]) <= -256
10127 || INTVAL(otherops[2]) >= 256))
10128 {
10129 rtx reg1;
10130 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
10131 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
10132 {
10133 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
10134 otherops[0] = reg1;
10135 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
10136 }
10137 else
10138 {
10139 otherops[0] = reg1;
10140 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
10141 otherops[0] = operands[1];
10142 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
10143 }
10144 }
10145 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
5b3e6663 10146 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
fdd695fd 10147 else
5b3e6663 10148 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
ff9940b0 10149 break;
2b835d68
RE		 10150
10151 case PLUS:
fdd695fd 10152 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
5dea0c19 10153 if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD)
2b835d68 10154 {
06bea5aa 10155 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
2b835d68
RE		 10156 {
10157 case -8:
5b3e6663 10158 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
2b835d68
RE		 10159 return "";
10160
10161 case -4:
5b3e6663
PB		 10162 if (TARGET_THUMB2)
10163 break;
10164 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
2b835d68
RE		 10165 return "";
10166
10167 case 4:
5b3e6663
PB		 10168 if (TARGET_THUMB2)
10169 break;
10170 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
2b835d68
RE		 10171 return "";
10172 }
10173 }
fdd695fd
PB		 10174 if (TARGET_LDRD
10175 && (GET_CODE (otherops[2]) == REG
10176 || (GET_CODE (otherops[2]) == CONST_INT
10177 && INTVAL (otherops[2]) > -256
10178 && INTVAL (otherops[2]) < 256)))
10179 {
10180 otherops[0] = operands[1];
10181 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
5b3e6663 10182 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
fdd695fd
PB		 10183 return "";
10184 }
2b835d68
RE		 10185 /* Fall through */
10186
ff9940b0 10187 default:
a4a37b30 10188 otherops[0] = adjust_address (operands[0], SImode, 4);
43cffd11 10189 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9997d19d
RE		 10190 output_asm_insn ("str%?\t%1, %0", operands);
10191 output_asm_insn ("str%?\t%1, %0", otherops);
cce8749e
CH		 10192 }
10193 }
cce8749e 10194
9997d19d
RE		 10195 return "";
10196}
cce8749e 10197
88f77cba
JB		 10198/* Output a move, load or store for quad-word vectors in ARM registers. Only
10199 handles MEMs accepted by neon_vector_mem_operand with CORE=true. */
5b3e6663
PB		 10200
10201const char *
88f77cba 10202output_move_quad (rtx *operands)
5b3e6663 10203{
88f77cba
JB		 10204 if (REG_P (operands[0]))
10205 {
10206 /* Load, or reg->reg move. */
5b3e6663 10207
88f77cba
JB		 10208 if (MEM_P (operands[1]))
10209 {
10210 switch (GET_CODE (XEXP (operands[1], 0)))
10211 {
10212 case REG:
10213 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
10214 break;
10215
10216 case LABEL_REF:
10217 case CONST:
10218 output_asm_insn ("adr%?\t%0, %1", operands);
10219 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
10220 break;
10221
10222 default:
10223 gcc_unreachable ();
10224 }
10225 }
10226 else
10227 {
10228 rtx ops[2];
10229 int dest, src, i;
5b3e6663 10230
88f77cba 10231 gcc_assert (REG_P (operands[1]));
5b3e6663 10232
88f77cba
JB		 10233 dest = REGNO (operands[0]);
10234 src = REGNO (operands[1]);
5b3e6663 10235
88f77cba
JB		 10236 /* This seems pretty dumb, but hopefully GCC won't try to do it
10237 very often. */
10238 if (dest < src)
10239 for (i = 0; i < 4; i++)
10240 {
10241 ops[0] = gen_rtx_REG (SImode, dest + i);
10242 ops[1] = gen_rtx_REG (SImode, src + i);
10243 output_asm_insn ("mov%?\t%0, %1", ops);
10244 }
10245 else
10246 for (i = 3; i >= 0; i--)
10247 {
10248 ops[0] = gen_rtx_REG (SImode, dest + i);
10249 ops[1] = gen_rtx_REG (SImode, src + i);
10250 output_asm_insn ("mov%?\t%0, %1", ops);
10251 }
10252 }
10253 }
10254 else
10255 {
10256 gcc_assert (MEM_P (operands[0]));
10257 gcc_assert (REG_P (operands[1]));
10258 gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0]));
10259
10260 switch (GET_CODE (XEXP (operands[0], 0)))
10261 {
10262 case REG:
10263 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
10264 break;
10265
10266 default:
10267 gcc_unreachable ();
10268 }
10269 }
10270
10271 return "";
10272}
10273
10274/* Output a VFP load or store instruction. */
10275
10276const char *
10277output_move_vfp (rtx *operands)
10278{
10279 rtx reg, mem, addr, ops[2];
10280 int load = REG_P (operands[0]);
10281 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
10282 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
10283 const char *template;
10284 char buff[50];
10285 enum machine_mode mode;
10286
10287 reg = operands[!load];
10288 mem = operands[load];
10289
10290 mode = GET_MODE (reg);
10291
10292 gcc_assert (REG_P (reg));
10293 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
10294 gcc_assert (mode == SFmode
10295 || mode == DFmode
10296 || mode == SImode
10297 || mode == DImode
10298 || (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
10299 gcc_assert (MEM_P (mem));
10300
10301 addr = XEXP (mem, 0);
10302
10303 switch (GET_CODE (addr))
10304 {
10305 case PRE_DEC:
10306 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
10307 ops[0] = XEXP (addr, 0);
10308 ops[1] = reg;
5b3e6663
PB		 10309 break;
10310
10311 case POST_INC:
10312 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
10313 ops[0] = XEXP (addr, 0);
10314 ops[1] = reg;
10315 break;
10316
10317 default:
10318 template = "f%s%c%%?\t%%%s0, %%1%s";
10319 ops[0] = reg;
10320 ops[1] = mem;
10321 break;
10322 }
10323
10324 sprintf (buff, template,
10325 load ? "ld" : "st",
10326 dp ? 'd' : 's',
10327 dp ? "P" : "",
10328 integer_p ? "\t%@ int" : "");
10329 output_asm_insn (buff, ops);
10330
10331 return "";
10332}
10333
88f77cba
JB		 10334/* Output a Neon quad-word load or store, or a load or store for
10335 larger structure modes. We could also support post-modify forms using
10336 VLD1/VST1 (for the vectorizer, and perhaps otherwise), but we don't do that
10337 yet.
10338 WARNING: The ordering of elements in memory is weird in big-endian mode,
10339 because we use VSTM instead of VST1, to make it easy to make vector stores
10340 via ARM registers write values in the same order as stores direct from Neon
10341 registers. For example, the byte ordering of a quadword vector with 16-byte
10342 elements like this:
10343
10344 [e7:e6:e5:e4:e3:e2:e1:e0] (highest-numbered element first)
10345
10346 will be (with lowest address first, h = most-significant byte,
10347 l = least-significant byte of element):
10348
10349 [e3h, e3l, e2h, e2l, e1h, e1l, e0h, e0l,
10350 e7h, e7l, e6h, e6l, e5h, e5l, e4h, e4l]
10351
10352 When necessary, quadword registers (dN, dN+1) are moved to ARM registers from
10353 rN in the order:
10354
10355 dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
10356
10357 So that STM/LDM can be used on vectors in ARM registers, and the same memory
10358 layout will result as if VSTM/VLDM were used. */
10359
10360const char *
10361output_move_neon (rtx *operands)
10362{
10363 rtx reg, mem, addr, ops[2];
10364 int regno, load = REG_P (operands[0]);
10365 const char *template;
10366 char buff[50];
10367 enum machine_mode mode;
10368
10369 reg = operands[!load];
10370 mem = operands[load];
10371
10372 mode = GET_MODE (reg);
10373
10374 gcc_assert (REG_P (reg));
10375 regno = REGNO (reg);
10376 gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno)
10377 || NEON_REGNO_OK_FOR_QUAD (regno));
10378 gcc_assert (VALID_NEON_DREG_MODE (mode)
10379 || VALID_NEON_QREG_MODE (mode)
10380 || VALID_NEON_STRUCT_MODE (mode));
10381 gcc_assert (MEM_P (mem));
10382
10383 addr = XEXP (mem, 0);
10384
10385 /* Strip off const from addresses like (const (plus (...))). */
10386 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
10387 addr = XEXP (addr, 0);
10388
10389 switch (GET_CODE (addr))
10390 {
10391 case POST_INC:
10392 template = "v%smia%%?\t%%0!, %%h1";
10393 ops[0] = XEXP (addr, 0);
10394 ops[1] = reg;
10395 break;
10396
10397 case POST_MODIFY:
10398 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
10399 gcc_unreachable ();
10400
10401 case LABEL_REF:
10402 case PLUS:
10403 {
10404 int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
10405 int i;
10406 int overlap = -1;
10407 for (i = 0; i < nregs; i++)
10408 {
10409 /* We're only using DImode here because it's a convenient size. */
10410 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
10411 ops[1] = adjust_address (mem, SImode, 8 * i);
10412 if (reg_overlap_mentioned_p (ops[0], mem))
10413 {
10414 gcc_assert (overlap == -1);
10415 overlap = i;
10416 }
10417 else
10418 {
10419 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
10420 output_asm_insn (buff, ops);
10421 }
10422 }
10423 if (overlap != -1)
10424 {
10425 ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
10426 ops[1] = adjust_address (mem, SImode, 8 * overlap);
10427 sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
10428 output_asm_insn (buff, ops);
10429 }
10430
10431 return "";
10432 }
10433
10434 default:
10435 template = "v%smia%%?\t%%m0, %%h1";
10436 ops[0] = mem;
10437 ops[1] = reg;
10438 }
10439
10440 sprintf (buff, template, load ? "ld" : "st");
10441 output_asm_insn (buff, ops);
10442
10443 return "";
10444}
10445
1d6e90ac
NC		 10446/* Output an ADD r, s, #n where n may be too big for one instruction.
10447 If adding zero to one register, output nothing. */
cd2b33d0 10448const char *
e32bac5b 10449output_add_immediate (rtx *operands)
cce8749e 10450{
f3bb6135 10451 HOST_WIDE_INT n = INTVAL (operands[2]);
cce8749e
CH		 10452
10453 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
10454 {
10455 if (n < 0)
10456 output_multi_immediate (operands,
9997d19d
RE		 10457 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
10458 -n);
cce8749e
CH		 10459 else
10460 output_multi_immediate (operands,
9997d19d
RE		 10461 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
10462 n);
cce8749e 10463 }
f3bb6135
RE		 10464
10465 return "";
10466}
cce8749e 10467
cce8749e
CH		 10468/* Output a multiple immediate operation.
10469 OPERANDS is the vector of operands referred to in the output patterns.
10470 INSTR1 is the output pattern to use for the first constant.
10471 INSTR2 is the output pattern to use for subsequent constants.
10472 IMMED_OP is the index of the constant slot in OPERANDS.
10473 N is the constant value. */
cd2b33d0 10474static const char *
e32bac5b
RE		 10475output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
10476 int immed_op, HOST_WIDE_INT n)
cce8749e 10477{
f3bb6135 10478#if HOST_BITS_PER_WIDE_INT > 32
30cf4896 10479 n &= 0xffffffff;
f3bb6135
RE		 10480#endif
10481
cce8749e
CH		 10482 if (n == 0)
10483 {
1d6e90ac 10484 /* Quick and easy output. */
cce8749e 10485 operands[immed_op] = const0_rtx;
1d6e90ac 10486 output_asm_insn (instr1, operands);
cce8749e
CH		 10487 }
10488 else
10489 {
10490 int i;
cd2b33d0 10491 const char * instr = instr1;
cce8749e 10492
6354dc9b 10493 /* Note that n is never zero here (which would give no output). */
cce8749e
CH		 10494 for (i = 0; i < 32; i += 2)
10495 {
10496 if (n & (3 << i))
10497 {
f3bb6135
RE		 10498 operands[immed_op] = GEN_INT (n & (255 << i));
10499 output_asm_insn (instr, operands);
cce8749e
CH		 10500 instr = instr2;
10501 i += 6;
10502 }
10503 }
10504 }
f676971a 10505
f3bb6135 10506 return "";
9997d19d 10507}
cce8749e 10508
5b3e6663
PB		 10509/* Return the name of a shifter operation. */
10510static const char *
10511arm_shift_nmem(enum rtx_code code)
10512{
10513 switch (code)
10514 {
10515 case ASHIFT:
10516 return ARM_LSL_NAME;
10517
10518 case ASHIFTRT:
10519 return "asr";
10520
10521 case LSHIFTRT:
10522 return "lsr";
10523
10524 case ROTATERT:
10525 return "ror";
10526
10527 default:
10528 abort();
10529 }
10530}
10531
cce8749e
CH		 10532/* Return the appropriate ARM instruction for the operation code.
10533 The returned result should not be overwritten. OP is the rtx of the
10534 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
10535 was shifted. */
cd2b33d0 10536const char *
e32bac5b 10537arithmetic_instr (rtx op, int shift_first_arg)
cce8749e 10538{
9997d19d 10539 switch (GET_CODE (op))
cce8749e
CH		 10540 {
10541 case PLUS:
f3bb6135
RE		 10542 return "add";
10543
cce8749e 10544 case MINUS:
f3bb6135
RE		 10545 return shift_first_arg ? "rsb" : "sub";
10546
cce8749e 10547 case IOR:
f3bb6135
RE		 10548 return "orr";
10549
cce8749e 10550 case XOR:
f3bb6135
RE		 10551 return "eor";
10552
cce8749e 10553 case AND:
f3bb6135
RE		 10554 return "and";
10555
5b3e6663
PB		 10556 case ASHIFT:
10557 case ASHIFTRT:
10558 case LSHIFTRT:
10559 case ROTATERT:
10560 return arm_shift_nmem(GET_CODE(op));
10561
cce8749e 10562 default:
e6d29d15 10563 gcc_unreachable ();
cce8749e 10564 }
f3bb6135 10565}
cce8749e 10566
cce8749e
CH		 10567/* Ensure valid constant shifts and return the appropriate shift mnemonic
10568 for the operation code. The returned result should not be overwritten.
10569 OP is the rtx code of the shift.
9997d19d 10570 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6354dc9b 10571 shift. */
cd2b33d0 10572static const char *
e32bac5b 10573shift_op (rtx op, HOST_WIDE_INT *amountp)
cce8749e 10574{
cd2b33d0 10575 const char * mnem;
e2c671ba 10576 enum rtx_code code = GET_CODE (op);
cce8749e 10577
e6d29d15
NS		 10578 switch (GET_CODE (XEXP (op, 1)))
10579 {
10580 case REG:
10581 case SUBREG:
10582 *amountp = -1;
10583 break;
10584
10585 case CONST_INT:
10586 *amountp = INTVAL (XEXP (op, 1));
10587 break;
10588
10589 default:
10590 gcc_unreachable ();
10591 }
9997d19d 10592
e2c671ba 10593 switch (code)
cce8749e 10594 {
a657c98a 10595 case ROTATE:
e6d29d15 10596 gcc_assert (*amountp != -1);
a657c98a 10597 *amountp = 32 - *amountp;
5b3e6663 10598 code = ROTATERT;
a657c98a
RE		 10599
10600 /* Fall through. */
10601
5b3e6663
PB		 10602 case ASHIFT:
10603 case ASHIFTRT:
10604 case LSHIFTRT:
9997d19d 10605 case ROTATERT:
5b3e6663 10606 mnem = arm_shift_nmem(code);
9997d19d
RE		 10607 break;
10608
ff9940b0 10609 case MULT:
e2c671ba
RE		 10610 /* We never have to worry about the amount being other than a
10611 power of 2, since this case can never be reloaded from a reg. */
e6d29d15
NS		 10612 gcc_assert (*amountp != -1);
10613 *amountp = int_log2 (*amountp);
5b3e6663 10614 return ARM_LSL_NAME;
f3bb6135 10615
cce8749e 10616 default:
e6d29d15 10617 gcc_unreachable ();
cce8749e
CH		 10618 }
10619
e2c671ba
RE		 10620 if (*amountp != -1)
10621 {
10622 /* This is not 100% correct, but follows from the desire to merge
10623 multiplication by a power of 2 with the recognizer for a
5b3e6663 10624 shift. >=32 is not a valid shift for "lsl", so we must try and
e2c671ba 10625 output a shift that produces the correct arithmetical result.
ddd5a7c1 10626 Using lsr #32 is identical except for the fact that the carry bit
f676971a 10627 is not set correctly if we set the flags; but we never use the
e2c671ba
RE		 10628 carry bit from such an operation, so we can ignore that. */
10629 if (code == ROTATERT)
1d6e90ac
NC		 10630 /* Rotate is just modulo 32. */
10631 *amountp &= 31;
e2c671ba
RE		 10632 else if (*amountp != (*amountp & 31))
10633 {
10634 if (code == ASHIFT)
10635 mnem = "lsr";
10636 *amountp = 32;
10637 }
10638
10639 /* Shifts of 0 are no-ops. */
10640 if (*amountp == 0)
10641 return NULL;
f676971a 10642 }
e2c671ba 10643
9997d19d
RE		 10644 return mnem;
10645}
cce8749e 10646
6354dc9b 10647/* Obtain the shift from the POWER of two. */
1d6e90ac 10648
18af7313 10649static HOST_WIDE_INT
e32bac5b 10650int_log2 (HOST_WIDE_INT power)
cce8749e 10651{
f3bb6135 10652 HOST_WIDE_INT shift = 0;
cce8749e 10653
30cf4896 10654 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
cce8749e 10655 {
e6d29d15 10656 gcc_assert (shift <= 31);
e32bac5b 10657 shift++;
cce8749e 10658 }
f3bb6135
RE		 10659
10660 return shift;
10661}
cce8749e 10662
c5ff069d
ZW		 10663/* Output a .ascii pseudo-op, keeping track of lengths. This is
10664 because /bin/as is horribly restrictive. The judgement about
10665 whether or not each character is 'printable' (and can be output as
10666 is) or not (and must be printed with an octal escape) must be made
10667 with reference to the *host* character set -- the situation is
10668 similar to that discussed in the comments above pp_c_char in
10669 c-pretty-print.c. */
10670
6cfc7210 10671#define MAX_ASCII_LEN 51
cce8749e
CH		 10672
10673void
e32bac5b 10674output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
cce8749e
CH		 10675{
10676 int i;
6cfc7210 10677 int len_so_far = 0;
cce8749e 10678
6cfc7210 10679 fputs ("\t.ascii\t\"", stream);
f676971a 10680
cce8749e
CH		 10681 for (i = 0; i < len; i++)
10682 {
1d6e90ac 10683 int c = p[i];
cce8749e 10684
6cfc7210 10685 if (len_so_far >= MAX_ASCII_LEN)
cce8749e 10686 {
6cfc7210 10687 fputs ("\"\n\t.ascii\t\"", stream);
cce8749e 10688 len_so_far = 0;
cce8749e
CH		 10689 }
10690
c5ff069d 10691 if (ISPRINT (c))
cce8749e 10692 {
c5ff069d 10693 if (c == '\\' || c == '\"')
6cfc7210 10694 {
c5ff069d 10695 putc ('\\', stream);
5895f793 10696 len_so_far++;
6cfc7210 10697 }
c5ff069d
ZW		 10698 putc (c, stream);
10699 len_so_far++;
10700 }
10701 else
10702 {
10703 fprintf (stream, "\\%03o", c);
10704 len_so_far += 4;
cce8749e 10705 }
cce8749e 10706 }
f3bb6135 10707
cce8749e 10708 fputs ("\"\n", stream);
f3bb6135 10709}
cce8749e 10710\f
c9ca9b88 10711/* Compute the register save mask for registers 0 through 12
5848830f 10712 inclusive. This code is used by arm_compute_save_reg_mask. */
b279b20a 10713
6d3d9133 10714static unsigned long
e32bac5b 10715arm_compute_save_reg0_reg12_mask (void)
6d3d9133 10716{
121308d4 10717 unsigned long func_type = arm_current_func_type ();
b279b20a 10718 unsigned long save_reg_mask = 0;
6d3d9133 10719 unsigned int reg;
6d3d9133 10720
7b8b8ade 10721 if (IS_INTERRUPT (func_type))
6d3d9133 10722 {
7b8b8ade 10723 unsigned int max_reg;
7b8b8ade
NC		 10724 /* Interrupt functions must not corrupt any registers,
10725 even call clobbered ones. If this is a leaf function
10726 we can just examine the registers used by the RTL, but
10727 otherwise we have to assume that whatever function is
10728 called might clobber anything, and so we have to save
10729 all the call-clobbered registers as well. */
10730 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
10731 /* FIQ handlers have registers r8 - r12 banked, so
10732 we only need to check r0 - r7, Normal ISRs only
121308d4 10733 bank r14 and r15, so we must check up to r12.
7b8b8ade
NC		 10734 r13 is the stack pointer which is always preserved,
10735 so we do not need to consider it here. */
10736 max_reg = 7;
10737 else
10738 max_reg = 12;
f676971a 10739
7b8b8ade 10740 for (reg = 0; reg <= max_reg; reg++)
6fb5fa3c
DB		 10741 if (df_regs_ever_live_p (reg)
10742 || (! current_function_is_leaf && call_used_regs[reg]))
6d3d9133 10743 save_reg_mask |= (1 << reg);
cfa01aab 10744
286d28c3 10745 /* Also save the pic base register if necessary. */
cfa01aab
PB		 10746 if (flag_pic
10747 && !TARGET_SINGLE_PIC_BASE
020a4035 10748 && arm_pic_register != INVALID_REGNUM
e3b5732b 10749 && crtl->uses_pic_offset_table)
cfa01aab 10750 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
6d3d9133
NC		 10751 }
10752 else
10753 {
10754 /* In the normal case we only need to save those registers
10755 which are call saved and which are used by this function. */
ec6237e4 10756 for (reg = 0; reg <= 11; reg++)
6fb5fa3c 10757 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
6d3d9133
NC		 10758 save_reg_mask |= (1 << reg);
10759
10760 /* Handle the frame pointer as a special case. */
ec6237e4 10761 if (frame_pointer_needed)
6d3d9133
NC		 10762 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10763
10764 /* If we aren't loading the PIC register,
10765 don't stack it even though it may be live. */
10766 if (flag_pic
e0b92319 10767 && !TARGET_SINGLE_PIC_BASE
020a4035 10768 && arm_pic_register != INVALID_REGNUM
6fb5fa3c 10769 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
e3b5732b 10770 || crtl->uses_pic_offset_table))
6d3d9133 10771 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
5b3e6663
PB		 10772
10773 /* The prologue will copy SP into R0, so save it. */
10774 if (IS_STACKALIGN (func_type))
10775 save_reg_mask |= 1;
6d3d9133
NC		 10776 }
10777
c9ca9b88 10778 /* Save registers so the exception handler can modify them. */
e3b5732b 10779 if (crtl->calls_eh_return)
c9ca9b88
PB		 10780 {
10781 unsigned int i;
f676971a 10782
c9ca9b88
PB		 10783 for (i = 0; ; i++)
10784 {
10785 reg = EH_RETURN_DATA_REGNO (i);
10786 if (reg == INVALID_REGNUM)
10787 break;
10788 save_reg_mask |= 1 << reg;
10789 }
10790 }
10791
121308d4
NC		 10792 return save_reg_mask;
10793}
10794
5b3e6663 10795
35596784
AJ		 10796/* Compute the number of bytes used to store the static chain register on the
10797 stack, above the stack frame. We need to know this accurately to get the
10798 alignment of the rest of the stack frame correct. */
10799
10800static int arm_compute_static_chain_stack_bytes (void)
10801{
10802 unsigned long func_type = arm_current_func_type ();
10803 int static_chain_stack_bytes = 0;
10804
10805 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM &&
10806 IS_NESTED (func_type) &&
10807 df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0)
10808 static_chain_stack_bytes = 4;
10809
10810 return static_chain_stack_bytes;
10811}
10812
10813
121308d4 10814/* Compute a bit mask of which registers need to be
954954d1
PB		 10815 saved on the stack for the current function.
10816 This is used by arm_get_frame_offsets, which may add extra registers. */
121308d4
NC		 10817
10818static unsigned long
e32bac5b 10819arm_compute_save_reg_mask (void)
121308d4
NC		 10820{
10821 unsigned int save_reg_mask = 0;
10822 unsigned long func_type = arm_current_func_type ();
5b3e6663 10823 unsigned int reg;
121308d4
NC		 10824
10825 if (IS_NAKED (func_type))
10826 /* This should never really happen. */
10827 return 0;
10828
10829 /* If we are creating a stack frame, then we must save the frame pointer,
10830 IP (which will hold the old stack pointer), LR and the PC. */
ec6237e4 10831 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
121308d4
NC		 10832 save_reg_mask |=
10833 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
10834 | (1 << IP_REGNUM)
10835 | (1 << LR_REGNUM)
10836 | (1 << PC_REGNUM);
10837
10838 /* Volatile functions do not return, so there
10839 is no need to save any other registers. */
10840 if (IS_VOLATILE (func_type))
10841 return save_reg_mask;
10842
10843 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
10844
6d3d9133
NC		 10845 /* Decide if we need to save the link register.
10846 Interrupt routines have their own banked link register,
10847 so they never need to save it.
1768c26f 10848 Otherwise if we do not use the link register we do not need to save
6d3d9133
NC		 10849 it. If we are pushing other registers onto the stack however, we
10850 can save an instruction in the epilogue by pushing the link register
10851 now and then popping it back into the PC. This incurs extra memory
72ac76be 10852 accesses though, so we only do it when optimizing for size, and only
6d3d9133 10853 if we know that we will not need a fancy return sequence. */
6fb5fa3c
DB		 10854 if (df_regs_ever_live_p (LR_REGNUM)
10855 || (save_reg_mask
10856 && optimize_size
10857 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
e3b5732b 10858 && !crtl->calls_eh_return))
6d3d9133
NC		 10859 save_reg_mask |= 1 << LR_REGNUM;
10860
6f7ebcbb
NC		 10861 if (cfun->machine->lr_save_eliminated)
10862 save_reg_mask &= ~ (1 << LR_REGNUM);
10863
5a9335ef
NC		 10864 if (TARGET_REALLY_IWMMXT
10865 && ((bit_count (save_reg_mask)
35596784
AJ		 10866 + ARM_NUM_INTS (crtl->args.pretend_args_size +
10867 arm_compute_static_chain_stack_bytes())
10868 ) % 2) != 0)
5a9335ef 10869 {
5a9335ef
NC		 10870 /* The total number of registers that are going to be pushed
10871 onto the stack is odd. We need to ensure that the stack
10872 is 64-bit aligned before we start to save iWMMXt registers,
10873 and also before we start to create locals. (A local variable
10874 might be a double or long long which we will load/store using
10875 an iWMMXt instruction). Therefore we need to push another
10876 ARM register, so that the stack will be 64-bit aligned. We
10877 try to avoid using the arg registers (r0 -r3) as they might be
10878 used to pass values in a tail call. */
10879 for (reg = 4; reg <= 12; reg++)
10880 if ((save_reg_mask & (1 << reg)) == 0)
10881 break;
10882
10883 if (reg <= 12)
10884 save_reg_mask |= (1 << reg);
10885 else
10886 {
10887 cfun->machine->sibcall_blocked = 1;
10888 save_reg_mask |= (1 << 3);
10889 }
10890 }
10891
5b3e6663
PB		 10892 /* We may need to push an additional register for use initializing the
10893 PIC base register. */
10894 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
10895 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
10896 {
10897 reg = thumb_find_work_register (1 << 4);
10898 if (!call_used_regs[reg])
10899 save_reg_mask |= (1 << reg);
10900 }
10901
6d3d9133
NC		 10902 return save_reg_mask;
10903}
10904
9728c9d1 10905
57934c39
PB		 10906/* Compute a bit mask of which registers need to be
10907 saved on the stack for the current function. */
10908static unsigned long
5b3e6663 10909thumb1_compute_save_reg_mask (void)
57934c39
PB		 10910{
10911 unsigned long mask;
b279b20a 10912 unsigned reg;
57934c39
PB		 10913
10914 mask = 0;
10915 for (reg = 0; reg < 12; reg ++)
6fb5fa3c 10916 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
b279b20a 10917 mask |= 1 << reg;
57934c39 10918
39c39be0
RE		 10919 if (flag_pic
10920 && !TARGET_SINGLE_PIC_BASE
020a4035 10921 && arm_pic_register != INVALID_REGNUM
e3b5732b 10922 && crtl->uses_pic_offset_table)
39c39be0 10923 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
b279b20a 10924
a2503645
RS		 10925 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
10926 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
10927 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
57934c39 10928
b279b20a 10929 /* LR will also be pushed if any lo regs are pushed. */
57934c39
PB		 10930 if (mask & 0xff || thumb_force_lr_save ())
10931 mask |= (1 << LR_REGNUM);
10932
b279b20a
NC		 10933 /* Make sure we have a low work register if we need one.
10934 We will need one if we are going to push a high register,
10935 but we are not currently intending to push a low register. */
10936 if ((mask & 0xff) == 0
57934c39 10937 && ((mask & 0x0f00) || TARGET_BACKTRACE))
b279b20a
NC		 10938 {
10939 /* Use thumb_find_work_register to choose which register
10940 we will use. If the register is live then we will
10941 have to push it. Use LAST_LO_REGNUM as our fallback
10942 choice for the register to select. */
10943 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
19e723f4
PB		 10944 /* Make sure the register returned by thumb_find_work_register is
10945 not part of the return value. */
954954d1 10946 if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ())
19e723f4 10947 reg = LAST_LO_REGNUM;
b279b20a
NC		 10948
10949 if (! call_used_regs[reg])
10950 mask |= 1 << reg;
10951 }
57934c39 10952
35596784
AJ		 10953 /* The 504 below is 8 bytes less than 512 because there are two possible
10954 alignment words. We can't tell here if they will be present or not so we
10955 have to play it safe and assume that they are. */
10956 if ((CALLER_INTERWORKING_SLOT_SIZE +
10957 ROUND_UP_WORD (get_frame_size ()) +
10958 crtl->outgoing_args_size) >= 504)
10959 {
10960 /* This is the same as the code in thumb1_expand_prologue() which
10961 determines which register to use for stack decrement. */
10962 for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++)
10963 if (mask & (1 << reg))
10964 break;
10965
10966 if (reg > LAST_LO_REGNUM)
10967 {
10968 /* Make sure we have a register available for stack decrement. */
10969 mask |= 1 << LAST_LO_REGNUM;
10970 }
10971 }
10972
57934c39
PB		 10973 return mask;
10974}
10975
10976
9728c9d1
PB		 10977/* Return the number of bytes required to save VFP registers. */
10978static int
10979arm_get_vfp_saved_size (void)
10980{
10981 unsigned int regno;
10982 int count;
10983 int saved;
10984
10985 saved = 0;
10986 /* Space for saved VFP registers. */
10987 if (TARGET_HARD_FLOAT && TARGET_VFP)
10988 {
10989 count = 0;
10990 for (regno = FIRST_VFP_REGNUM;
10991 regno < LAST_VFP_REGNUM;
10992 regno += 2)
10993 {
6fb5fa3c
DB		 10994 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
10995 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
9728c9d1
PB		 10996 {
10997 if (count > 0)
10998 {
10999 /* Workaround ARM10 VFPr1 bug. */
11000 if (count == 2 && !arm_arch6)
11001 count++;
8edfc4cc 11002 saved += count * 8;
9728c9d1
PB		 11003 }
11004 count = 0;
11005 }
11006 else
11007 count++;
11008 }
11009 if (count > 0)
11010 {
11011 if (count == 2 && !arm_arch6)
11012 count++;
8edfc4cc 11013 saved += count * 8;
9728c9d1
PB		 11014 }
11015 }
11016 return saved;
11017}
11018
11019
699a4925 11020/* Generate a function exit sequence. If REALLY_RETURN is false, then do
6d3d9133 11021 everything bar the final return instruction. */
cd2b33d0 11022const char *
e32bac5b 11023output_return_instruction (rtx operand, int really_return, int reverse)
ff9940b0 11024{
6d3d9133 11025 char conditional[10];
ff9940b0 11026 char instr[100];
b279b20a 11027 unsigned reg;
6d3d9133
NC		 11028 unsigned long live_regs_mask;
11029 unsigned long func_type;
5848830f 11030 arm_stack_offsets *offsets;
e26053d1 11031
6d3d9133 11032 func_type = arm_current_func_type ();
e2c671ba 11033
6d3d9133 11034 if (IS_NAKED (func_type))
d5b7b3ae 11035 return "";
6d3d9133
NC		 11036
11037 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
e2c671ba 11038 {
699a4925
RE		 11039 /* If this function was declared non-returning, and we have
11040 found a tail call, then we have to trust that the called
11041 function won't return. */
3a5a4282
PB		 11042 if (really_return)
11043 {
11044 rtx ops[2];
f676971a 11045
3a5a4282
PB		 11046 /* Otherwise, trap an attempted return by aborting. */
11047 ops[0] = operand;
f676971a 11048 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
3a5a4282
PB		 11049 : "abort");
11050 assemble_external_libcall (ops[1]);
11051 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
11052 }
f676971a 11053
e2c671ba
RE		 11054 return "";
11055 }
6d3d9133 11056
e3b5732b 11057 gcc_assert (!cfun->calls_alloca || really_return);
ff9940b0 11058
c414f8a9 11059 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
d5b7b3ae 11060
6d3d9133 11061 return_used_this_function = 1;
ff9940b0 11062
954954d1
PB		 11063 offsets = arm_get_frame_offsets ();
11064 live_regs_mask = offsets->saved_regs_mask;
ff9940b0 11065
1768c26f 11066 if (live_regs_mask)
6d3d9133 11067 {
1768c26f
PB		 11068 const char * return_reg;
11069
f676971a 11070 /* If we do not have any special requirements for function exit
a15908a4 11071 (e.g. interworking) then we can load the return address
1768c26f
PB		 11072 directly into the PC. Otherwise we must load it into LR. */
11073 if (really_return
a15908a4 11074 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
1768c26f 11075 return_reg = reg_names[PC_REGNUM];
6d3d9133 11076 else
1768c26f
PB		 11077 return_reg = reg_names[LR_REGNUM];
11078
6d3d9133 11079 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
b034930f
ILT		 11080 {
11081 /* There are three possible reasons for the IP register
11082 being saved. 1) a stack frame was created, in which case
11083 IP contains the old stack pointer, or 2) an ISR routine
11084 corrupted it, or 3) it was saved to align the stack on
11085 iWMMXt. In case 1, restore IP into SP, otherwise just
11086 restore IP. */
11087 if (frame_pointer_needed)
11088 {
11089 live_regs_mask &= ~ (1 << IP_REGNUM);
11090 live_regs_mask |= (1 << SP_REGNUM);
11091 }
11092 else
e6d29d15 11093 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
b034930f 11094 }
f3bb6135 11095
3a7731fd
PB		 11096 /* On some ARM architectures it is faster to use LDR rather than
11097 LDM to load a single register. On other architectures, the
11098 cost is the same. In 26 bit mode, or for exception handlers,
11099 we have to use LDM to load the PC so that the CPSR is also
11100 restored. */
11101 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
b279b20a
NC		 11102 if (live_regs_mask == (1U << reg))
11103 break;
11104
3a7731fd
PB		 11105 if (reg <= LAST_ARM_REGNUM
11106 && (reg != LR_REGNUM
f676971a 11107 || ! really_return
61f0ccff 11108 || ! IS_INTERRUPT (func_type)))
3a7731fd 11109 {
f676971a 11110 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
3a7731fd 11111 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
6d3d9133 11112 }
ff9940b0 11113 else
1d5473cb 11114 {
1768c26f
PB		 11115 char *p;
11116 int first = 1;
6d3d9133 11117
699a4925
RE		 11118 /* Generate the load multiple instruction to restore the
11119 registers. Note we can get here, even if
11120 frame_pointer_needed is true, but only if sp already
11121 points to the base of the saved core registers. */
11122 if (live_regs_mask & (1 << SP_REGNUM))
a72d4945 11123 {
5848830f
PB		 11124 unsigned HOST_WIDE_INT stack_adjust;
11125
5848830f 11126 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
e6d29d15 11127 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
a72d4945 11128
5b3e6663 11129 if (stack_adjust && arm_arch5 && TARGET_ARM)
a72d4945
RE		 11130 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
11131 else
11132 {
b279b20a
NC		 11133 /* If we can't use ldmib (SA110 bug),
11134 then try to pop r3 instead. */
a72d4945
RE		 11135 if (stack_adjust)
11136 live_regs_mask |= 1 << 3;
11137 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
11138 }
11139 }
da6558fd 11140 else
1768c26f
PB		 11141 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
11142
11143 p = instr + strlen (instr);
6d3d9133 11144
1768c26f
PB		 11145 for (reg = 0; reg <= SP_REGNUM; reg++)
11146 if (live_regs_mask & (1 << reg))
11147 {
11148 int l = strlen (reg_names[reg]);
11149
11150 if (first)
11151 first = 0;
11152 else
11153 {
11154 memcpy (p, ", ", 2);
11155 p += 2;
11156 }
11157
11158 memcpy (p, "%|", 2);
11159 memcpy (p + 2, reg_names[reg], l);
11160 p += l + 2;
11161 }
f676971a 11162
1768c26f
PB		 11163 if (live_regs_mask & (1 << LR_REGNUM))
11164 {
b17fe233 11165 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
61f0ccff
RE		 11166 /* If returning from an interrupt, restore the CPSR. */
11167 if (IS_INTERRUPT (func_type))
b17fe233 11168 strcat (p, "^");
1768c26f
PB		 11169 }
11170 else
11171 strcpy (p, "}");
1d5473cb 11172 }
da6558fd 11173
1768c26f
PB		 11174 output_asm_insn (instr, & operand);
11175
3a7731fd
PB		 11176 /* See if we need to generate an extra instruction to
11177 perform the actual function return. */
11178 if (really_return
11179 && func_type != ARM_FT_INTERWORKED
11180 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
da6558fd 11181 {
3a7731fd
PB		 11182 /* The return has already been handled
11183 by loading the LR into the PC. */
11184 really_return = 0;
da6558fd 11185 }
ff9940b0 11186 }
e26053d1 11187
1768c26f 11188 if (really_return)
ff9940b0 11189 {
6d3d9133
NC		 11190 switch ((int) ARM_FUNC_TYPE (func_type))
11191 {
11192 case ARM_FT_ISR:
11193 case ARM_FT_FIQ:
5b3e6663 11194 /* ??? This is wrong for unified assembly syntax. */
6d3d9133
NC		 11195 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
11196 break;
11197
11198 case ARM_FT_INTERWORKED:
11199 sprintf (instr, "bx%s\t%%|lr", conditional);
11200 break;
11201
11202 case ARM_FT_EXCEPTION:
5b3e6663 11203 /* ??? This is wrong for unified assembly syntax. */
6d3d9133
NC		 11204 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
11205 break;
11206
11207 default:
68d560d4
RE		 11208 /* Use bx if it's available. */
11209 if (arm_arch5 || arm_arch4t)
f676971a 11210 sprintf (instr, "bx%s\t%%|lr", conditional);
1768c26f 11211 else
61f0ccff 11212 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
6d3d9133
NC		 11213 break;
11214 }
1768c26f
PB		 11215
11216 output_asm_insn (instr, & operand);
ff9940b0 11217 }
f3bb6135 11218
ff9940b0
RE		 11219 return "";
11220}
11221
ef179a26
NC		 11222/* Write the function name into the code section, directly preceding
11223 the function prologue.
11224
11225 Code will be output similar to this:
11226 t0
11227 .ascii "arm_poke_function_name", 0
11228 .align
11229 t1
11230 .word 0xff000000 + (t1 - t0)
11231 arm_poke_function_name
11232 mov ip, sp
11233 stmfd sp!, {fp, ip, lr, pc}
11234 sub fp, ip, #4
11235
11236 When performing a stack backtrace, code can inspect the value
11237 of 'pc' stored at 'fp' + 0. If the trace function then looks
11238 at location pc - 12 and the top 8 bits are set, then we know
11239 that there is a function name embedded immediately preceding this
11240 location and has length ((pc[-3]) & 0xff000000).
11241
11242 We assume that pc is declared as a pointer to an unsigned long.
11243
11244 It is of no benefit to output the function name if we are assembling
11245 a leaf function. These function types will not contain a stack
11246 backtrace structure, therefore it is not possible to determine the
11247 function name. */
ef179a26 11248void
e32bac5b 11249arm_poke_function_name (FILE *stream, const char *name)
ef179a26
NC		 11250{
11251 unsigned long alignlength;
11252 unsigned long length;
11253 rtx x;
11254
d5b7b3ae 11255 length = strlen (name) + 1;
0c2ca901 11256 alignlength = ROUND_UP_WORD (length);
f676971a 11257
949d79eb 11258 ASM_OUTPUT_ASCII (stream, name, length);
ef179a26 11259 ASM_OUTPUT_ALIGN (stream, 2);
30cf4896 11260 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
301d03af 11261 assemble_aligned_integer (UNITS_PER_WORD, x);
ef179a26
NC		 11262}
11263
6d3d9133
NC		 11264/* Place some comments into the assembler stream
11265 describing the current function. */
08c148a8 11266static void
e32bac5b 11267arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
cce8749e 11268{
6d3d9133 11269 unsigned long func_type;
08c148a8 11270
5b3e6663 11271 if (TARGET_THUMB1)
08c148a8 11272 {
5b3e6663 11273 thumb1_output_function_prologue (f, frame_size);
08c148a8
NB		 11274 return;
11275 }
f676971a 11276
6d3d9133 11277 /* Sanity check. */
e6d29d15 11278 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
31fdb4d5 11279
6d3d9133 11280 func_type = arm_current_func_type ();
f676971a 11281
6d3d9133
NC		 11282 switch ((int) ARM_FUNC_TYPE (func_type))
11283 {
11284 default:
11285 case ARM_FT_NORMAL:
11286 break;
11287 case ARM_FT_INTERWORKED:
11288 asm_fprintf (f, "\t%@ Function supports interworking.\n");
11289 break;
6d3d9133
NC		 11290 case ARM_FT_ISR:
11291 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
11292 break;
11293 case ARM_FT_FIQ:
11294 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
11295 break;
11296 case ARM_FT_EXCEPTION:
11297 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
11298 break;
11299 }
f676971a 11300
6d3d9133
NC		 11301 if (IS_NAKED (func_type))
11302 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
11303
11304 if (IS_VOLATILE (func_type))
11305 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
11306
11307 if (IS_NESTED (func_type))
11308 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
5b3e6663
PB		 11309 if (IS_STACKALIGN (func_type))
11310 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
f676971a 11311
c53dddc2 11312 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
38173d38
JH		 11313 crtl->args.size,
11314 crtl->args.pretend_args_size, frame_size);
6d3d9133 11315
3cb66fd7 11316 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
dd18ae56 11317 frame_pointer_needed,
3cb66fd7 11318 cfun->machine->uses_anonymous_args);
cce8749e 11319
6f7ebcbb
NC		 11320 if (cfun->machine->lr_save_eliminated)
11321 asm_fprintf (f, "\t%@ link register save eliminated.\n");
11322
e3b5732b 11323 if (crtl->calls_eh_return)
c9ca9b88
PB		 11324 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
11325
f676971a 11326 return_used_this_function = 0;
f3bb6135 11327}
cce8749e 11328
cd2b33d0 11329const char *
a72d4945 11330arm_output_epilogue (rtx sibling)
cce8749e 11331{
949d79eb 11332 int reg;
6f7ebcbb 11333 unsigned long saved_regs_mask;
6d3d9133 11334 unsigned long func_type;
f676971a 11335 /* Floats_offset is the offset from the "virtual" frame. In an APCS
c882c7ac
RE		 11336 frame that is $fp + 4 for a non-variadic function. */
11337 int floats_offset = 0;
cce8749e 11338 rtx operands[3];
d5b7b3ae 11339 FILE * f = asm_out_file;
5a9335ef 11340 unsigned int lrm_count = 0;
a72d4945 11341 int really_return = (sibling == NULL);
9b66ebb1 11342 int start_reg;
5848830f 11343 arm_stack_offsets *offsets;
cce8749e 11344
6d3d9133
NC		 11345 /* If we have already generated the return instruction
11346 then it is futile to generate anything else. */
a72d4945 11347 if (use_return_insn (FALSE, sibling) && return_used_this_function)
949d79eb 11348 return "";
cce8749e 11349
6d3d9133 11350 func_type = arm_current_func_type ();
d5b7b3ae 11351
6d3d9133
NC		 11352 if (IS_NAKED (func_type))
11353 /* Naked functions don't have epilogues. */
11354 return "";
0616531f 11355
6d3d9133 11356 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
e2c671ba 11357 {
86efdc8e 11358 rtx op;
f676971a 11359
6d3d9133 11360 /* A volatile function should never return. Call abort. */
ed0e6530 11361 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
2b835d68 11362 assemble_external_libcall (op);
e2c671ba 11363 output_asm_insn ("bl\t%a0", &op);
f676971a 11364
949d79eb 11365 return "";
e2c671ba
RE		 11366 }
11367
e6d29d15
NS		 11368 /* If we are throwing an exception, then we really must be doing a
11369 return, so we can't tail-call. */
e3b5732b 11370 gcc_assert (!crtl->calls_eh_return || really_return);
f676971a 11371
5848830f 11372 offsets = arm_get_frame_offsets ();
954954d1 11373 saved_regs_mask = offsets->saved_regs_mask;
5a9335ef
NC		 11374
11375 if (TARGET_IWMMXT)
11376 lrm_count = bit_count (saved_regs_mask);
11377
5848830f 11378 floats_offset = offsets->saved_args;
6d3d9133 11379 /* Compute how far away the floats will be. */
5a9335ef 11380 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
6f7ebcbb 11381 if (saved_regs_mask & (1 << reg))
6ed30148 11382 floats_offset += 4;
f676971a 11383
ec6237e4 11384 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
cce8749e 11385 {
9b66ebb1 11386 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
5848830f 11387 int vfp_offset = offsets->frame;
c882c7ac 11388
29ad9694 11389 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
b111229a 11390 {
9b66ebb1 11391 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
6fb5fa3c 11392 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
b111229a
RE		 11393 {
11394 floats_offset += 12;
f676971a 11395 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
c882c7ac 11396 reg, FP_REGNUM, floats_offset - vfp_offset);
b111229a
RE		 11397 }
11398 }
11399 else
11400 {
9b66ebb1 11401 start_reg = LAST_FPA_REGNUM;
b111229a 11402
9b66ebb1 11403 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
b111229a 11404 {
6fb5fa3c 11405 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
b111229a
RE		 11406 {
11407 floats_offset += 12;
f676971a 11408
6354dc9b 11409 /* We can't unstack more than four registers at once. */
b111229a
RE		 11410 if (start_reg - reg == 3)
11411 {
dd18ae56 11412 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
c882c7ac 11413 reg, FP_REGNUM, floats_offset - vfp_offset);
b111229a
RE		 11414 start_reg = reg - 1;
11415 }
11416 }
11417 else
11418 {
11419 if (reg != start_reg)
dd18ae56
NC		 11420 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
11421 reg + 1, start_reg - reg,
c882c7ac 11422 FP_REGNUM, floats_offset - vfp_offset);
b111229a
RE		 11423 start_reg = reg - 1;
11424 }
11425 }
11426
11427 /* Just in case the last register checked also needs unstacking. */
11428 if (reg != start_reg)
dd18ae56
NC		 11429 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
11430 reg + 1, start_reg - reg,
c882c7ac 11431 FP_REGNUM, floats_offset - vfp_offset);
b111229a 11432 }
6d3d9133 11433
9b66ebb1
PB		 11434 if (TARGET_HARD_FLOAT && TARGET_VFP)
11435 {
9728c9d1 11436 int saved_size;
9b66ebb1 11437
8edfc4cc
MS		 11438 /* The fldmd insns do not have base+offset addressing
11439 modes, so we use IP to hold the address. */
9728c9d1 11440 saved_size = arm_get_vfp_saved_size ();
9b66ebb1 11441
9728c9d1 11442 if (saved_size > 0)
9b66ebb1 11443 {
9728c9d1 11444 floats_offset += saved_size;
9b66ebb1
PB		 11445 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
11446 FP_REGNUM, floats_offset - vfp_offset);
11447 }
11448 start_reg = FIRST_VFP_REGNUM;
11449 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11450 {
6fb5fa3c
DB		 11451 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11452 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
9b66ebb1
PB		 11453 {
11454 if (start_reg != reg)
8edfc4cc 11455 vfp_output_fldmd (f, IP_REGNUM,
9728c9d1
PB		 11456 (start_reg - FIRST_VFP_REGNUM) / 2,
11457 (reg - start_reg) / 2);
9b66ebb1
PB		 11458 start_reg = reg + 2;
11459 }
11460 }
11461 if (start_reg != reg)
8edfc4cc 11462 vfp_output_fldmd (f, IP_REGNUM,
9728c9d1
PB		 11463 (start_reg - FIRST_VFP_REGNUM) / 2,
11464 (reg - start_reg) / 2);
9b66ebb1
PB		 11465 }
11466
5a9335ef
NC		 11467 if (TARGET_IWMMXT)
11468 {
11469 /* The frame pointer is guaranteed to be non-double-word aligned.
11470 This is because it is set to (old_stack_pointer - 4) and the
11471 old_stack_pointer was double word aligned. Thus the offset to
11472 the iWMMXt registers to be loaded must also be non-double-word
11473 sized, so that the resultant address *is* double-word aligned.
11474 We can ignore floats_offset since that was already included in
11475 the live_regs_mask. */
11476 lrm_count += (lrm_count % 2 ? 2 : 1);
f676971a 11477
01d4c813 11478 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
6fb5fa3c 11479 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
5a9335ef 11480 {
f676971a 11481 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
5a9335ef 11482 reg, FP_REGNUM, lrm_count * 4);
f676971a 11483 lrm_count += 2;
5a9335ef
NC		 11484 }
11485 }
11486
6f7ebcbb 11487 /* saved_regs_mask should contain the IP, which at the time of stack
6d3d9133
NC		 11488 frame generation actually contains the old stack pointer. So a
11489 quick way to unwind the stack is just pop the IP register directly
11490 into the stack pointer. */
e6d29d15 11491 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
6f7ebcbb
NC		 11492 saved_regs_mask &= ~ (1 << IP_REGNUM);
11493 saved_regs_mask |= (1 << SP_REGNUM);
6d3d9133 11494
6f7ebcbb 11495 /* There are two registers left in saved_regs_mask - LR and PC. We
6d3d9133
NC		 11496 only need to restore the LR register (the return address), but to
11497 save time we can load it directly into the PC, unless we need a
11498 special function exit sequence, or we are not really returning. */
c9ca9b88
PB		 11499 if (really_return
11500 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
e3b5732b 11501 && !crtl->calls_eh_return)
6d3d9133
NC		 11502 /* Delete the LR from the register mask, so that the LR on
11503 the stack is loaded into the PC in the register mask. */
6f7ebcbb 11504 saved_regs_mask &= ~ (1 << LR_REGNUM);
b111229a 11505 else
6f7ebcbb 11506 saved_regs_mask &= ~ (1 << PC_REGNUM);
efc2515b
RE		 11507
11508 /* We must use SP as the base register, because SP is one of the
11509 registers being restored. If an interrupt or page fault
11510 happens in the ldm instruction, the SP might or might not
11511 have been restored. That would be bad, as then SP will no
11512 longer indicate the safe area of stack, and we can get stack
11513 corruption. Using SP as the base register means that it will
11514 be reset correctly to the original value, should an interrupt
699a4925
RE		 11515 occur. If the stack pointer already points at the right
11516 place, then omit the subtraction. */
5848830f 11517 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
e3b5732b 11518 || cfun->calls_alloca)
699a4925
RE		 11519 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
11520 4 * bit_count (saved_regs_mask));
a15908a4 11521 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
7b8b8ade
NC		 11522
11523 if (IS_INTERRUPT (func_type))
11524 /* Interrupt handlers will have pushed the
11525 IP onto the stack, so restore it now. */
a15908a4 11526 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
cce8749e
CH		 11527 }
11528 else
11529 {
ec6237e4
PB		 11530 /* This branch is executed for ARM mode (non-apcs frames) and
11531 Thumb-2 mode. Frame layout is essentially the same for those
11532 cases, except that in ARM mode frame pointer points to the
11533 first saved register, while in Thumb-2 mode the frame pointer points
11534 to the last saved register.
11535
11536 It is possible to make frame pointer point to last saved
11537 register in both cases, and remove some conditionals below.
11538 That means that fp setup in prologue would be just "mov fp, sp"
11539 and sp restore in epilogue would be just "mov sp, fp", whereas
11540 now we have to use add/sub in those cases. However, the value
11541 of that would be marginal, as both mov and add/sub are 32-bit
11542 in ARM mode, and it would require extra conditionals
11543 in arm_expand_prologue to distingish ARM-apcs-frame case
11544 (where frame pointer is required to point at first register)
11545 and ARM-non-apcs-frame. Therefore, such change is postponed
11546 until real need arise. */
5b3e6663 11547 HOST_WIDE_INT amount;
a15908a4 11548 int rfe;
d2288d8d 11549 /* Restore stack pointer if necessary. */
ec6237e4 11550 if (TARGET_ARM && frame_pointer_needed)
5b3e6663
PB		 11551 {
11552 operands[0] = stack_pointer_rtx;
ec6237e4
PB		 11553 operands[1] = hard_frame_pointer_rtx;
11554
11555 operands[2] = GEN_INT (offsets->frame - offsets->saved_regs);
11556 output_add_immediate (operands);
5b3e6663 11557 }
ec6237e4 11558 else
5b3e6663 11559 {
ec6237e4
PB		 11560 if (frame_pointer_needed)
11561 {
11562 /* For Thumb-2 restore sp from the frame pointer.
11563 Operand restrictions mean we have to incrememnt FP, then copy
11564 to SP. */
11565 amount = offsets->locals_base - offsets->saved_regs;
11566 operands[0] = hard_frame_pointer_rtx;
11567 }
11568 else
11569 {
954954d1 11570 unsigned long count;
ec6237e4
PB		 11571 operands[0] = stack_pointer_rtx;
11572 amount = offsets->outgoing_args - offsets->saved_regs;
954954d1
PB		 11573 /* pop call clobbered registers if it avoids a
11574 separate stack adjustment. */
11575 count = offsets->saved_regs - offsets->saved_args;
11576 if (optimize_size
11577 && count != 0
e3b5732b 11578 && !crtl->calls_eh_return
954954d1
PB		 11579 && bit_count(saved_regs_mask) * 4 == count
11580 && !IS_INTERRUPT (func_type)
e3b5732b 11581 && !crtl->tail_call_emit)
954954d1
PB		 11582 {
11583 unsigned long mask;
11584 mask = (1 << (arm_size_return_regs() / 4)) - 1;
11585 mask ^= 0xf;
11586 mask &= ~saved_regs_mask;
11587 reg = 0;
11588 while (bit_count (mask) * 4 > amount)
11589 {
11590 while ((mask & (1 << reg)) == 0)
11591 reg++;
11592 mask &= ~(1 << reg);
11593 }
11594 if (bit_count (mask) * 4 == amount) {
11595 amount = 0;
11596 saved_regs_mask |= mask;
11597 }
11598 }
ec6237e4
PB		 11599 }
11600
11601 if (amount)
11602 {
11603 operands[1] = operands[0];
11604 operands[2] = GEN_INT (amount);
11605 output_add_immediate (operands);
11606 }
11607 if (frame_pointer_needed)
11608 asm_fprintf (f, "\tmov\t%r, %r\n",
11609 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
d2288d8d
TG		 11610 }
11611
29ad9694 11612 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
b111229a 11613 {
9b66ebb1 11614 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
6fb5fa3c 11615 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
dd18ae56
NC		 11616 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
11617 reg, SP_REGNUM);
b111229a
RE		 11618 }
11619 else
11620 {
9b66ebb1 11621 start_reg = FIRST_FPA_REGNUM;
b111229a 11622
9b66ebb1 11623 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
b111229a 11624 {
6fb5fa3c 11625 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
b111229a
RE		 11626 {
11627 if (reg - start_reg == 3)
11628 {
dd18ae56
NC		 11629 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
11630 start_reg, SP_REGNUM);
b111229a
RE		 11631 start_reg = reg + 1;
11632 }
11633 }
11634 else
11635 {
11636 if (reg != start_reg)
dd18ae56
NC		 11637 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
11638 start_reg, reg - start_reg,
11639 SP_REGNUM);
f676971a 11640
b111229a
RE		 11641 start_reg = reg + 1;
11642 }
11643 }
11644
11645 /* Just in case the last register checked also needs unstacking. */
11646 if (reg != start_reg)
dd18ae56
NC		 11647 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
11648 start_reg, reg - start_reg, SP_REGNUM);
b111229a
RE		 11649 }
11650
9b66ebb1
PB		 11651 if (TARGET_HARD_FLOAT && TARGET_VFP)
11652 {
11653 start_reg = FIRST_VFP_REGNUM;
11654 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11655 {
6fb5fa3c
DB		 11656 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11657 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
9b66ebb1
PB		 11658 {
11659 if (start_reg != reg)
8edfc4cc 11660 vfp_output_fldmd (f, SP_REGNUM,
9728c9d1
PB		 11661 (start_reg - FIRST_VFP_REGNUM) / 2,
11662 (reg - start_reg) / 2);
9b66ebb1
PB		 11663 start_reg = reg + 2;
11664 }
11665 }
11666 if (start_reg != reg)
8edfc4cc 11667 vfp_output_fldmd (f, SP_REGNUM,
9728c9d1
PB		 11668 (start_reg - FIRST_VFP_REGNUM) / 2,
11669 (reg - start_reg) / 2);
9b66ebb1 11670 }
5a9335ef
NC		 11671 if (TARGET_IWMMXT)
11672 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
6fb5fa3c 11673 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
01d4c813 11674 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
5a9335ef 11675
6d3d9133 11676 /* If we can, restore the LR into the PC. */
a15908a4
PB		 11677 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
11678 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
5b3e6663 11679 && !IS_STACKALIGN (func_type)
6d3d9133 11680 && really_return
38173d38 11681 && crtl->args.pretend_args_size == 0
c9ca9b88 11682 && saved_regs_mask & (1 << LR_REGNUM)
e3b5732b 11683 && !crtl->calls_eh_return)
cce8749e 11684 {
6f7ebcbb
NC		 11685 saved_regs_mask &= ~ (1 << LR_REGNUM);
11686 saved_regs_mask |= (1 << PC_REGNUM);
a15908a4 11687 rfe = IS_INTERRUPT (func_type);
6d3d9133 11688 }
a15908a4
PB		 11689 else
11690 rfe = 0;
d5b7b3ae 11691
6d3d9133 11692 /* Load the registers off the stack. If we only have one register
5b3e6663
PB		 11693 to load use the LDR instruction - it is faster. For Thumb-2
11694 always use pop and the assembler will pick the best instruction.*/
a15908a4
PB		 11695 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
11696 && !IS_INTERRUPT(func_type))
6d3d9133 11697 {
c9ca9b88 11698 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
cce8749e 11699 }
6f7ebcbb 11700 else if (saved_regs_mask)
f1acdf8b
NC		 11701 {
11702 if (saved_regs_mask & (1 << SP_REGNUM))
11703 /* Note - write back to the stack register is not enabled
112cdef5 11704 (i.e. "ldmfd sp!..."). We know that the stack pointer is
f1acdf8b
NC		 11705 in the list of registers and if we add writeback the
11706 instruction becomes UNPREDICTABLE. */
a15908a4
PB		 11707 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
11708 rfe);
5b3e6663 11709 else if (TARGET_ARM)
a15908a4
PB		 11710 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
11711 rfe);
f1acdf8b 11712 else
a15908a4 11713 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
f1acdf8b 11714 }
6d3d9133 11715
38173d38 11716 if (crtl->args.pretend_args_size)
cce8749e 11717 {
6d3d9133
NC		 11718 /* Unwind the pre-pushed regs. */
11719 operands[0] = operands[1] = stack_pointer_rtx;
38173d38 11720 operands[2] = GEN_INT (crtl->args.pretend_args_size);
6d3d9133
NC		 11721 output_add_immediate (operands);
11722 }
11723 }
32de079a 11724
2966b00e 11725 /* We may have already restored PC directly from the stack. */
0cc3dda8 11726 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
6d3d9133 11727 return "";
d5b7b3ae 11728
c9ca9b88 11729 /* Stack adjustment for exception handler. */
e3b5732b 11730 if (crtl->calls_eh_return)
f676971a 11731 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
c9ca9b88
PB		 11732 ARM_EH_STACKADJ_REGNUM);
11733
6d3d9133
NC		 11734 /* Generate the return instruction. */
11735 switch ((int) ARM_FUNC_TYPE (func_type))
11736 {
6d3d9133
NC		 11737 case ARM_FT_ISR:
11738 case ARM_FT_FIQ:
11739 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
11740 break;
11741
11742 case ARM_FT_EXCEPTION:
11743 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
11744 break;
11745
11746 case ARM_FT_INTERWORKED:
11747 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
11748 break;
11749
11750 default:
5b3e6663
PB		 11751 if (IS_STACKALIGN (func_type))
11752 {
11753 /* See comment in arm_expand_prologue. */
11754 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
11755 }
68d560d4
RE		 11756 if (arm_arch5 || arm_arch4t)
11757 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
11758 else
11759 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
6d3d9133 11760 break;
cce8749e 11761 }
f3bb6135 11762
949d79eb
RE		 11763 return "";
11764}
11765
08c148a8 11766static void
e32bac5b 11767arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
5848830f 11768 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
949d79eb 11769{
5848830f
PB		 11770 arm_stack_offsets *offsets;
11771
5b3e6663 11772 if (TARGET_THUMB1)
d5b7b3ae 11773 {
b12a00f1
RE		 11774 int regno;
11775
11776 /* Emit any call-via-reg trampolines that are needed for v4t support
11777 of call_reg and call_value_reg type insns. */
57ecec57 11778 for (regno = 0; regno < LR_REGNUM; regno++)
b12a00f1
RE		 11779 {
11780 rtx label = cfun->machine->call_via[regno];
11781
11782 if (label != NULL)
11783 {
d6b5193b 11784 switch_to_section (function_section (current_function_decl));
b12a00f1
RE		 11785 targetm.asm_out.internal_label (asm_out_file, "L",
11786 CODE_LABEL_NUMBER (label));
11787 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
11788 }
11789 }
11790
d5b7b3ae
RE		 11791 /* ??? Probably not safe to set this here, since it assumes that a
11792 function will be emitted as assembly immediately after we generate
11793 RTL for it. This does not happen for inline functions. */
11794 return_used_this_function = 0;
11795 }
5b3e6663 11796 else /* TARGET_32BIT */
d5b7b3ae 11797 {
0977774b 11798 /* We need to take into account any stack-frame rounding. */
5848830f 11799 offsets = arm_get_frame_offsets ();
0977774b 11800
e6d29d15
NS		 11801 gcc_assert (!use_return_insn (FALSE, NULL)
11802 || !return_used_this_function
11803 || offsets->saved_regs == offsets->outgoing_args
11804 || frame_pointer_needed);
f3bb6135 11805
d5b7b3ae 11806 /* Reset the ARM-specific per-function variables. */
d5b7b3ae
RE		 11807 after_arm_reorg = 0;
11808 }
f3bb6135 11809}
e2c671ba 11810
2c849145
JM		 11811/* Generate and emit an insn that we will recognize as a push_multi.
11812 Unfortunately, since this insn does not reflect very well the actual
11813 semantics of the operation, we need to annotate the insn for the benefit
11814 of DWARF2 frame unwind information. */
2c849145 11815static rtx
b279b20a 11816emit_multi_reg_push (unsigned long mask)
e2c671ba
RE		 11817{
11818 int num_regs = 0;
9b598fa0 11819 int num_dwarf_regs;
e2c671ba
RE		 11820 int i, j;
11821 rtx par;
2c849145 11822 rtx dwarf;
87e27392 11823 int dwarf_par_index;
2c849145 11824 rtx tmp, reg;
e2c671ba 11825
d5b7b3ae 11826 for (i = 0; i <= LAST_ARM_REGNUM; i++)
e2c671ba 11827 if (mask & (1 << i))
5895f793 11828 num_regs++;
e2c671ba 11829
e6d29d15 11830 gcc_assert (num_regs && num_regs <= 16);
e2c671ba 11831
9b598fa0
RE		 11832 /* We don't record the PC in the dwarf frame information. */
11833 num_dwarf_regs = num_regs;
11834 if (mask & (1 << PC_REGNUM))
11835 num_dwarf_regs--;
11836
87e27392 11837 /* For the body of the insn we are going to generate an UNSPEC in
05713b80 11838 parallel with several USEs. This allows the insn to be recognized
87e27392
NC		 11839 by the push_multi pattern in the arm.md file. The insn looks
11840 something like this:
11841
f676971a 11842 (parallel [
b15bca31
RE		 11843 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
11844 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
87e27392
NC		 11845 (use (reg:SI 11 fp))
11846 (use (reg:SI 12 ip))
11847 (use (reg:SI 14 lr))
11848 (use (reg:SI 15 pc))
11849 ])
11850
11851 For the frame note however, we try to be more explicit and actually
11852 show each register being stored into the stack frame, plus a (single)
11853 decrement of the stack pointer. We do it this way in order to be
11854 friendly to the stack unwinding code, which only wants to see a single
11855 stack decrement per instruction. The RTL we generate for the note looks
11856 something like this:
11857
f676971a 11858 (sequence [
87e27392
NC		 11859 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
11860 (set (mem:SI (reg:SI sp)) (reg:SI r4))
11861 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
11862 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
11863 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
87e27392
NC		 11864 ])
11865
11866 This sequence is used both by the code to support stack unwinding for
11867 exceptions handlers and the code to generate dwarf2 frame debugging. */
f676971a 11868
43cffd11 11869 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9b598fa0 11870 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
87e27392 11871 dwarf_par_index = 1;
e2c671ba 11872
d5b7b3ae 11873 for (i = 0; i <= LAST_ARM_REGNUM; i++)
e2c671ba
RE		 11874 {
11875 if (mask & (1 << i))
11876 {
2c849145
JM		 11877 reg = gen_rtx_REG (SImode, i);
11878
e2c671ba 11879 XVECEXP (par, 0, 0)
43cffd11 11880 = gen_rtx_SET (VOIDmode,
31fa16b6
RE		 11881 gen_frame_mem (BLKmode,
11882 gen_rtx_PRE_DEC (BLKmode,
11883 stack_pointer_rtx)),
43cffd11 11884 gen_rtx_UNSPEC (BLKmode,
2c849145 11885 gen_rtvec (1, reg),
9b598fa0 11886 UNSPEC_PUSH_MULT));
2c849145 11887
9b598fa0
RE		 11888 if (i != PC_REGNUM)
11889 {
11890 tmp = gen_rtx_SET (VOIDmode,
31fa16b6 11891 gen_frame_mem (SImode, stack_pointer_rtx),
9b598fa0
RE		 11892 reg);
11893 RTX_FRAME_RELATED_P (tmp) = 1;
11894 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
11895 dwarf_par_index++;
11896 }
2c849145 11897
e2c671ba
RE		 11898 break;
11899 }
11900 }
11901
11902 for (j = 1, i++; j < num_regs; i++)
11903 {
11904 if (mask & (1 << i))
11905 {
2c849145
JM		 11906 reg = gen_rtx_REG (SImode, i);
11907
11908 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
11909
9b598fa0
RE		 11910 if (i != PC_REGNUM)
11911 {
31fa16b6
RE		 11912 tmp
11913 = gen_rtx_SET (VOIDmode,
11914 gen_frame_mem (SImode,
9b598fa0
RE		 11915 plus_constant (stack_pointer_rtx,
11916 4 * j)),
31fa16b6 11917 reg);
9b598fa0
RE		 11918 RTX_FRAME_RELATED_P (tmp) = 1;
11919 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
11920 }
11921
e2c671ba
RE		 11922 j++;
11923 }
11924 }
b111229a 11925
2c849145 11926 par = emit_insn (par);
f676971a 11927
d66437c5 11928 tmp = gen_rtx_SET (VOIDmode,
87e27392 11929 stack_pointer_rtx,
d66437c5 11930 plus_constant (stack_pointer_rtx, -4 * num_regs));
87e27392
NC		 11931 RTX_FRAME_RELATED_P (tmp) = 1;
11932 XVECEXP (dwarf, 0, 0) = tmp;
f676971a 11933
2c849145
JM		 11934 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11935 REG_NOTES (par));
11936 return par;
b111229a
RE		 11937}
11938
4f5dfed0 11939/* Calculate the size of the return value that is passed in registers. */
466e4b7a 11940static unsigned
4f5dfed0
JC		 11941arm_size_return_regs (void)
11942{
11943 enum machine_mode mode;
11944
38173d38
JH		 11945 if (crtl->return_rtx != 0)
11946 mode = GET_MODE (crtl->return_rtx);
4f5dfed0
JC		 11947 else
11948 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11949
11950 return GET_MODE_SIZE (mode);
11951}
11952
2c849145 11953static rtx
e32bac5b 11954emit_sfm (int base_reg, int count)
b111229a
RE		 11955{
11956 rtx par;
2c849145
JM		 11957 rtx dwarf;
11958 rtx tmp, reg;
b111229a
RE		 11959 int i;
11960
43cffd11 11961 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8ee6eb4e 11962 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
2c849145
JM		 11963
11964 reg = gen_rtx_REG (XFmode, base_reg++);
43cffd11
RE		 11965
11966 XVECEXP (par, 0, 0)
f676971a 11967 = gen_rtx_SET (VOIDmode,
31fa16b6
RE		 11968 gen_frame_mem (BLKmode,
11969 gen_rtx_PRE_DEC (BLKmode,
11970 stack_pointer_rtx)),
43cffd11 11971 gen_rtx_UNSPEC (BLKmode,
2c849145 11972 gen_rtvec (1, reg),
b15bca31 11973 UNSPEC_PUSH_MULT));
f676971a 11974 tmp = gen_rtx_SET (VOIDmode,
31fa16b6 11975 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
2c849145 11976 RTX_FRAME_RELATED_P (tmp) = 1;
f676971a
EC		 11977 XVECEXP (dwarf, 0, 1) = tmp;
11978
b111229a 11979 for (i = 1; i < count; i++)
2c849145
JM		 11980 {
11981 reg = gen_rtx_REG (XFmode, base_reg++);
11982 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
11983
f676971a 11984 tmp = gen_rtx_SET (VOIDmode,
31fa16b6
RE		 11985 gen_frame_mem (XFmode,
11986 plus_constant (stack_pointer_rtx,
11987 i * 12)),
2c849145
JM		 11988 reg);
11989 RTX_FRAME_RELATED_P (tmp) = 1;
f676971a 11990 XVECEXP (dwarf, 0, i + 1) = tmp;
2c849145 11991 }
b111229a 11992
8ee6eb4e
PB		 11993 tmp = gen_rtx_SET (VOIDmode,
11994 stack_pointer_rtx,
d66437c5
RE		 11995 plus_constant (stack_pointer_rtx, -12 * count));
11996
8ee6eb4e
PB		 11997 RTX_FRAME_RELATED_P (tmp) = 1;
11998 XVECEXP (dwarf, 0, 0) = tmp;
11999
2c849145
JM		 12000 par = emit_insn (par);
12001 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12002 REG_NOTES (par));
12003 return par;
e2c671ba
RE		 12004}
12005
9b66ebb1 12006
3c7ad43e
PB		 12007/* Return true if the current function needs to save/restore LR. */
12008
12009static bool
12010thumb_force_lr_save (void)
12011{
12012 return !cfun->machine->lr_save_eliminated
12013 && (!leaf_function_p ()
12014 || thumb_far_jump_used_p ()
6fb5fa3c 12015 || df_regs_ever_live_p (LR_REGNUM));
3c7ad43e
PB		 12016}
12017
12018
095bb276
NC		 12019/* Compute the distance from register FROM to register TO.
12020 These can be the arg pointer (26), the soft frame pointer (25),
12021 the stack pointer (13) or the hard frame pointer (11).
c9ca9b88 12022 In thumb mode r7 is used as the soft frame pointer, if needed.
095bb276
NC		 12023 Typical stack layout looks like this:
12024
12025 old stack pointer -> | |
12026 ----
12027 | | \
12028 | | saved arguments for
12029 | | vararg functions
12030 | | /
12031 --
12032 hard FP & arg pointer -> | | \
12033 | | stack
12034 | | frame
12035 | | /
12036 --
12037 | | \
12038 | | call saved
12039 | | registers
12040 soft frame pointer -> | | /
12041 --
12042 | | \
12043 | | local
12044 | | variables
2591db65 12045 locals base pointer -> | | /
095bb276
NC		 12046 --
12047 | | \
12048 | | outgoing
12049 | | arguments
12050 current stack pointer -> | | /
12051 --
12052
43aa4e05 12053 For a given function some or all of these stack components
095bb276
NC		 12054 may not be needed, giving rise to the possibility of
12055 eliminating some of the registers.
12056
825dda42 12057 The values returned by this function must reflect the behavior
095bb276
NC		 12058 of arm_expand_prologue() and arm_compute_save_reg_mask().
12059
12060 The sign of the number returned reflects the direction of stack
12061 growth, so the values are positive for all eliminations except
5848830f
PB		 12062 from the soft frame pointer to the hard frame pointer.
12063
12064 SFP may point just inside the local variables block to ensure correct
12065 alignment. */
12066
12067
12068/* Calculate stack offsets. These are used to calculate register elimination
954954d1
PB		 12069 offsets and in prologue/epilogue code. Also calculates which registers
12070 should be saved. */
5848830f
PB		 12071
12072static arm_stack_offsets *
12073arm_get_frame_offsets (void)
095bb276 12074{
5848830f 12075 struct arm_stack_offsets *offsets;
095bb276 12076 unsigned long func_type;
5848830f 12077 int leaf;
5848830f 12078 int saved;
954954d1 12079 int core_saved;
5848830f 12080 HOST_WIDE_INT frame_size;
954954d1 12081 int i;
5848830f
PB		 12082
12083 offsets = &cfun->machine->stack_offsets;
f676971a 12084
5848830f
PB		 12085 /* We need to know if we are a leaf function. Unfortunately, it
12086 is possible to be called after start_sequence has been called,
12087 which causes get_insns to return the insns for the sequence,
12088 not the function, which will cause leaf_function_p to return
12089 the incorrect result.
095bb276 12090
5848830f
PB		 12091 to know about leaf functions once reload has completed, and the
12092 frame size cannot be changed after that time, so we can safely
12093 use the cached value. */
12094
12095 if (reload_completed)
12096 return offsets;
12097
666c27b9
KH		 12098 /* Initially this is the size of the local variables. It will translated
12099 into an offset once we have determined the size of preceding data. */
5848830f
PB		 12100 frame_size = ROUND_UP_WORD (get_frame_size ());
12101
12102 leaf = leaf_function_p ();
12103
12104 /* Space for variadic functions. */
38173d38 12105 offsets->saved_args = crtl->args.pretend_args_size;
5848830f 12106
5b3e6663 12107 /* In Thumb mode this is incorrect, but never used. */
35596784
AJ		 12108 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) +
12109 arm_compute_static_chain_stack_bytes();
5848830f 12110
5b3e6663 12111 if (TARGET_32BIT)
095bb276 12112 {
5848830f 12113 unsigned int regno;
ef7112de 12114
954954d1
PB		 12115 offsets->saved_regs_mask = arm_compute_save_reg_mask ();
12116 core_saved = bit_count (offsets->saved_regs_mask) * 4;
12117 saved = core_saved;
5a9335ef 12118
5848830f
PB		 12119 /* We know that SP will be doubleword aligned on entry, and we must
12120 preserve that condition at any subroutine call. We also require the
12121 soft frame pointer to be doubleword aligned. */
12122
12123 if (TARGET_REALLY_IWMMXT)
9b66ebb1 12124 {
5848830f
PB		 12125 /* Check for the call-saved iWMMXt registers. */
12126 for (regno = FIRST_IWMMXT_REGNUM;
12127 regno <= LAST_IWMMXT_REGNUM;
12128 regno++)
6fb5fa3c 12129 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
5848830f
PB		 12130 saved += 8;
12131 }
12132
12133 func_type = arm_current_func_type ();
12134 if (! IS_VOLATILE (func_type))
12135 {
12136 /* Space for saved FPA registers. */
12137 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
6fb5fa3c 12138 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
5848830f
PB		 12139 saved += 12;
12140
12141 /* Space for saved VFP registers. */
12142 if (TARGET_HARD_FLOAT && TARGET_VFP)
9728c9d1 12143 saved += arm_get_vfp_saved_size ();
9b66ebb1 12144 }
5848830f 12145 }
5b3e6663 12146 else /* TARGET_THUMB1 */
5848830f 12147 {
954954d1
PB		 12148 offsets->saved_regs_mask = thumb1_compute_save_reg_mask ();
12149 core_saved = bit_count (offsets->saved_regs_mask) * 4;
12150 saved = core_saved;
5848830f 12151 if (TARGET_BACKTRACE)
57934c39 12152 saved += 16;
5848830f 12153 }
9b66ebb1 12154
5848830f 12155 /* Saved registers include the stack frame. */
35596784
AJ		 12156 offsets->saved_regs = offsets->saved_args + saved +
12157 arm_compute_static_chain_stack_bytes();
a2503645 12158 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
5848830f
PB		 12159 /* A leaf function does not need any stack alignment if it has nothing
12160 on the stack. */
12161 if (leaf && frame_size == 0)
12162 {
12163 offsets->outgoing_args = offsets->soft_frame;
a3a531ec 12164 offsets->locals_base = offsets->soft_frame;
5848830f
PB		 12165 return offsets;
12166 }
12167
12168 /* Ensure SFP has the correct alignment. */
12169 if (ARM_DOUBLEWORD_ALIGN
12170 && (offsets->soft_frame & 7))
954954d1
PB		 12171 {
12172 offsets->soft_frame += 4;
12173 /* Try to align stack by pushing an extra reg. Don't bother doing this
12174 when there is a stack frame as the alignment will be rolled into
12175 the normal stack adjustment. */
38173d38 12176 if (frame_size + crtl->outgoing_args_size == 0)
954954d1
PB		 12177 {
12178 int reg = -1;
12179
12180 for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
12181 {
12182 if ((offsets->saved_regs_mask & (1 << i)) == 0)
12183 {
12184 reg = i;
12185 break;
12186 }
12187 }
12188
12189 if (reg == -1 && arm_size_return_regs () <= 12
e3b5732b 12190 && !crtl->tail_call_emit)
954954d1
PB		 12191 {
12192 /* Push/pop an argument register (r3) if all callee saved
12193 registers are already being pushed. */
12194 reg = 3;
12195 }
12196
12197 if (reg != -1)
12198 {
12199 offsets->saved_regs += 4;
12200 offsets->saved_regs_mask |= (1 << reg);
12201 }
12202 }
12203 }
5848830f 12204
2591db65
RE		 12205 offsets->locals_base = offsets->soft_frame + frame_size;
12206 offsets->outgoing_args = (offsets->locals_base
38173d38 12207 + crtl->outgoing_args_size);
5848830f
PB		 12208
12209 if (ARM_DOUBLEWORD_ALIGN)
12210 {
12211 /* Ensure SP remains doubleword aligned. */
12212 if (offsets->outgoing_args & 7)
12213 offsets->outgoing_args += 4;
e6d29d15 12214 gcc_assert (!(offsets->outgoing_args & 7));
095bb276
NC		 12215 }
12216
5848830f
PB		 12217 return offsets;
12218}
12219
12220
666c27b9 12221/* Calculate the relative offsets for the different stack pointers. Positive
5848830f
PB		 12222 offsets are in the direction of stack growth. */
12223
b3f8d95d 12224HOST_WIDE_INT
5848830f
PB		 12225arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
12226{
12227 arm_stack_offsets *offsets;
12228
12229 offsets = arm_get_frame_offsets ();
095bb276 12230
095bb276
NC		 12231 /* OK, now we have enough information to compute the distances.
12232 There must be an entry in these switch tables for each pair
12233 of registers in ELIMINABLE_REGS, even if some of the entries
12234 seem to be redundant or useless. */
12235 switch (from)
12236 {
12237 case ARG_POINTER_REGNUM:
12238 switch (to)
12239 {
12240 case THUMB_HARD_FRAME_POINTER_REGNUM:
12241 return 0;
12242
12243 case FRAME_POINTER_REGNUM:
12244 /* This is the reverse of the soft frame pointer
12245 to hard frame pointer elimination below. */
5848830f 12246 return offsets->soft_frame - offsets->saved_args;
095bb276
NC		 12247
12248 case ARM_HARD_FRAME_POINTER_REGNUM:
35596784
AJ		 12249 /* This is only non-zero in the case where the static chain register
12250 is stored above the frame. */
12251 return offsets->frame - offsets->saved_args - 4;
095bb276
NC		 12252
12253 case STACK_POINTER_REGNUM:
12254 /* If nothing has been pushed on the stack at all
12255 then this will return -4. This *is* correct! */
5848830f 12256 return offsets->outgoing_args - (offsets->saved_args + 4);
095bb276
NC		 12257
12258 default:
e6d29d15 12259 gcc_unreachable ();
095bb276 12260 }
e6d29d15 12261 gcc_unreachable ();
095bb276
NC		 12262
12263 case FRAME_POINTER_REGNUM:
12264 switch (to)
12265 {
12266 case THUMB_HARD_FRAME_POINTER_REGNUM:
12267 return 0;
12268
12269 case ARM_HARD_FRAME_POINTER_REGNUM:
12270 /* The hard frame pointer points to the top entry in the
12271 stack frame. The soft frame pointer to the bottom entry
12272 in the stack frame. If there is no stack frame at all,
12273 then they are identical. */
5848830f
PB		 12274
12275 return offsets->frame - offsets->soft_frame;
095bb276
NC		 12276
12277 case STACK_POINTER_REGNUM:
5848830f 12278 return offsets->outgoing_args - offsets->soft_frame;
095bb276
NC		 12279
12280 default:
e6d29d15 12281 gcc_unreachable ();
095bb276 12282 }
e6d29d15 12283 gcc_unreachable ();
095bb276
NC		 12284
12285 default:
12286 /* You cannot eliminate from the stack pointer.
12287 In theory you could eliminate from the hard frame
12288 pointer to the stack pointer, but this will never
12289 happen, since if a stack frame is not needed the
12290 hard frame pointer will never be used. */
e6d29d15 12291 gcc_unreachable ();
095bb276
NC		 12292 }
12293}
12294
0977774b 12295
7a085dce 12296/* Emit RTL to save coprocessor registers on function entry. Returns the
5b3e6663
PB		 12297 number of bytes pushed. */
12298
12299static int
12300arm_save_coproc_regs(void)
12301{
12302 int saved_size = 0;
12303 unsigned reg;
12304 unsigned start_reg;
12305 rtx insn;
12306
12307 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
6fb5fa3c 12308 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
5b3e6663
PB		 12309 {
12310 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
12311 insn = gen_rtx_MEM (V2SImode, insn);
12312 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
12313 RTX_FRAME_RELATED_P (insn) = 1;
12314 saved_size += 8;
12315 }
12316
12317 /* Save any floating point call-saved registers used by this
12318 function. */
12319 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
12320 {
12321 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
6fb5fa3c 12322 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
5b3e6663
PB		 12323 {
12324 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
12325 insn = gen_rtx_MEM (XFmode, insn);
12326 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
12327 RTX_FRAME_RELATED_P (insn) = 1;
12328 saved_size += 12;
12329 }
12330 }
12331 else
12332 {
12333 start_reg = LAST_FPA_REGNUM;
12334
12335 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
12336 {
6fb5fa3c 12337 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
5b3e6663
PB		 12338 {
12339 if (start_reg - reg == 3)
12340 {
12341 insn = emit_sfm (reg, 4);
12342 RTX_FRAME_RELATED_P (insn) = 1;
12343 saved_size += 48;
12344 start_reg = reg - 1;
12345 }
12346 }
12347 else
12348 {
12349 if (start_reg != reg)
12350 {
12351 insn = emit_sfm (reg + 1, start_reg - reg);
12352 RTX_FRAME_RELATED_P (insn) = 1;
12353 saved_size += (start_reg - reg) * 12;
12354 }
12355 start_reg = reg - 1;
12356 }
12357 }
12358
12359 if (start_reg != reg)
12360 {
12361 insn = emit_sfm (reg + 1, start_reg - reg);
12362 saved_size += (start_reg - reg) * 12;
12363 RTX_FRAME_RELATED_P (insn) = 1;
12364 }
12365 }
12366 if (TARGET_HARD_FLOAT && TARGET_VFP)
12367 {
12368 start_reg = FIRST_VFP_REGNUM;
12369
12370 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
12371 {
6fb5fa3c
DB		 12372 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
12373 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
5b3e6663
PB		 12374 {
12375 if (start_reg != reg)
12376 saved_size += vfp_emit_fstmd (start_reg,
12377 (reg - start_reg) / 2);
12378 start_reg = reg + 2;
12379 }
12380 }
12381 if (start_reg != reg)
12382 saved_size += vfp_emit_fstmd (start_reg,
12383 (reg - start_reg) / 2);
12384 }
12385 return saved_size;
12386}
12387
12388
12389/* Set the Thumb frame pointer from the stack pointer. */
12390
12391static void
12392thumb_set_frame_pointer (arm_stack_offsets *offsets)
12393{
12394 HOST_WIDE_INT amount;
12395 rtx insn, dwarf;
12396
12397 amount = offsets->outgoing_args - offsets->locals_base;
12398 if (amount < 1024)
12399 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12400 stack_pointer_rtx, GEN_INT (amount)));
12401 else
12402 {
12403 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
f5c630c3
PB		 12404 /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1
12405 expects the first two operands to be the same. */
12406 if (TARGET_THUMB2)
12407 {
12408 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12409 stack_pointer_rtx,
12410 hard_frame_pointer_rtx));
12411 }
12412 else
12413 {
12414 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12415 hard_frame_pointer_rtx,
12416 stack_pointer_rtx));
12417 }
5b3e6663
PB		 12418 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
12419 plus_constant (stack_pointer_rtx, amount));
12420 RTX_FRAME_RELATED_P (dwarf) = 1;
12421 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
12422 REG_NOTES (insn));
12423 }
12424
12425 RTX_FRAME_RELATED_P (insn) = 1;
12426}
12427
12428/* Generate the prologue instructions for entry into an ARM or Thumb-2
12429 function. */
e2c671ba 12430void
e32bac5b 12431arm_expand_prologue (void)
e2c671ba 12432{
6d3d9133 12433 rtx amount;
2c849145 12434 rtx insn;
68dfd979 12435 rtx ip_rtx;
6d3d9133
NC		 12436 unsigned long live_regs_mask;
12437 unsigned long func_type;
68dfd979 12438 int fp_offset = 0;
095bb276 12439 int saved_pretend_args = 0;
5848830f 12440 int saved_regs = 0;
b9705a21 12441 unsigned HOST_WIDE_INT args_to_push;
5848830f 12442 arm_stack_offsets *offsets;
d3236b4d 12443
6d3d9133 12444 func_type = arm_current_func_type ();
e2c671ba 12445
31fdb4d5 12446 /* Naked functions don't have prologues. */
6d3d9133 12447 if (IS_NAKED (func_type))
31fdb4d5
DE		 12448 return;
12449
095bb276 12450 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
38173d38 12451 args_to_push = crtl->args.pretend_args_size;
f676971a 12452
6d3d9133 12453 /* Compute which register we will have to save onto the stack. */
954954d1
PB		 12454 offsets = arm_get_frame_offsets ();
12455 live_regs_mask = offsets->saved_regs_mask;
e2c671ba 12456
68dfd979 12457 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
d3236b4d 12458
5b3e6663
PB		 12459 if (IS_STACKALIGN (func_type))
12460 {
12461 rtx dwarf;
12462 rtx r0;
12463 rtx r1;
12464 /* Handle a word-aligned stack pointer. We generate the following:
12465
12466 mov r0, sp
12467 bic r1, r0, #7
12468 mov sp, r1
12469 <save and restore r0 in normal prologue/epilogue>
12470 mov sp, r0
12471 bx lr
12472
12473 The unwinder doesn't need to know about the stack realignment.
12474 Just tell it we saved SP in r0. */
12475 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
12476
12477 r0 = gen_rtx_REG (SImode, 0);
12478 r1 = gen_rtx_REG (SImode, 1);
44bfa35b
NF		 12479 /* Use a real rtvec rather than NULL_RTVEC so the rest of the
12480 compiler won't choke. */
12481 dwarf = gen_rtx_UNSPEC (SImode, rtvec_alloc (0), UNSPEC_STACK_ALIGN);
5b3e6663
PB		 12482 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
12483 insn = gen_movsi (r0, stack_pointer_rtx);
12484 RTX_FRAME_RELATED_P (insn) = 1;
12485 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12486 dwarf, REG_NOTES (insn));
12487 emit_insn (insn);
12488 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
12489 emit_insn (gen_movsi (stack_pointer_rtx, r1));
12490 }
12491
ec6237e4
PB		 12492 /* For APCS frames, if IP register is clobbered
12493 when creating frame, save that register in a special
12494 way. */
12495 if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM)
e2c671ba 12496 {
7b8b8ade
NC		 12497 if (IS_INTERRUPT (func_type))
12498 {
12499 /* Interrupt functions must not corrupt any registers.
12500 Creating a frame pointer however, corrupts the IP
12501 register, so we must push it first. */
12502 insn = emit_multi_reg_push (1 << IP_REGNUM);
121308d4
NC		 12503
12504 /* Do not set RTX_FRAME_RELATED_P on this insn.
12505 The dwarf stack unwinding code only wants to see one
12506 stack decrement per function, and this is not it. If
12507 this instruction is labeled as being part of the frame
12508 creation sequence then dwarf2out_frame_debug_expr will
e6d29d15 12509 die when it encounters the assignment of IP to FP
121308d4
NC		 12510 later on, since the use of SP here establishes SP as
12511 the CFA register and not IP.
12512
12513 Anyway this instruction is not really part of the stack
12514 frame creation although it is part of the prologue. */
7b8b8ade
NC		 12515 }
12516 else if (IS_NESTED (func_type))
68dfd979
NC		 12517 {
12518 /* The Static chain register is the same as the IP register
12519 used as a scratch register during stack frame creation.
12520 To get around this need to find somewhere to store IP
12521 whilst the frame is being created. We try the following
12522 places in order:
f676971a 12523
6d3d9133 12524 1. The last argument register.
68dfd979
NC		 12525 2. A slot on the stack above the frame. (This only
12526 works if the function is not a varargs function).
095bb276
NC		 12527 3. Register r3, after pushing the argument registers
12528 onto the stack.
6d3d9133 12529
34ce3d7b
JM		 12530 Note - we only need to tell the dwarf2 backend about the SP
12531 adjustment in the second variant; the static chain register
12532 doesn't need to be unwound, as it doesn't contain a value
12533 inherited from the caller. */
d3236b4d 12534
6fb5fa3c 12535 if (df_regs_ever_live_p (3) == false)
d66437c5 12536 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
095bb276 12537 else if (args_to_push == 0)
68dfd979 12538 {
35596784
AJ		 12539 gcc_assert(arm_compute_static_chain_stack_bytes() == 4);
12540 saved_regs += 4;
12541
34ce3d7b 12542 rtx dwarf;
34ce3d7b 12543
d66437c5
RE		 12544 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
12545 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
68dfd979 12546 fp_offset = 4;
34ce3d7b
JM		 12547
12548 /* Just tell the dwarf backend that we adjusted SP. */
12549 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
d66437c5
RE		 12550 plus_constant (stack_pointer_rtx,
12551 -fp_offset));
34ce3d7b
JM		 12552 RTX_FRAME_RELATED_P (insn) = 1;
12553 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12554 dwarf, REG_NOTES (insn));
68dfd979
NC		 12555 }
12556 else
095bb276
NC		 12557 {
12558 /* Store the args on the stack. */
3cb66fd7 12559 if (cfun->machine->uses_anonymous_args)
095bb276
NC		 12560 insn = emit_multi_reg_push
12561 ((0xf0 >> (args_to_push / 4)) & 0xf);
12562 else
12563 insn = emit_insn
f676971a 12564 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
095bb276
NC		 12565 GEN_INT (- args_to_push)));
12566
12567 RTX_FRAME_RELATED_P (insn) = 1;
12568
12569 saved_pretend_args = 1;
12570 fp_offset = args_to_push;
12571 args_to_push = 0;
12572
12573 /* Now reuse r3 to preserve IP. */
d66437c5 12574 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
095bb276 12575 }
68dfd979
NC		 12576 }
12577
d66437c5
RE		 12578 insn = emit_set_insn (ip_rtx,
12579 plus_constant (stack_pointer_rtx, fp_offset));
8e56560e 12580 RTX_FRAME_RELATED_P (insn) = 1;
e2c671ba
RE		 12581 }
12582
095bb276 12583 if (args_to_push)
e2c671ba 12584 {
6d3d9133 12585 /* Push the argument registers, or reserve space for them. */
3cb66fd7 12586 if (cfun->machine->uses_anonymous_args)
2c849145 12587 insn = emit_multi_reg_push
095bb276 12588 ((0xf0 >> (args_to_push / 4)) & 0xf);
e2c671ba 12589 else
2c849145 12590 insn = emit_insn
f676971a 12591 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
095bb276 12592 GEN_INT (- args_to_push)));
2c849145 12593 RTX_FRAME_RELATED_P (insn) = 1;
e2c671ba
RE		 12594 }
12595
06bea5aa 12596 /* If this is an interrupt service routine, and the link register
ec6237e4
PB		 12597 is going to be pushed, and we're not generating extra
12598 push of IP (needed when frame is needed and frame layout if apcs),
06bea5aa
NC		 12599 subtracting four from LR now will mean that the function return
12600 can be done with a single instruction. */
3a7731fd 12601 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
06bea5aa 12602 && (live_regs_mask & (1 << LR_REGNUM)) != 0
ec6237e4 12603 && !(frame_pointer_needed && TARGET_APCS_FRAME)
a15908a4 12604 && TARGET_ARM)
d66437c5
RE		 12605 {
12606 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
12607
12608 emit_set_insn (lr, plus_constant (lr, -4));
12609 }
3a7731fd 12610
e2c671ba
RE		 12611 if (live_regs_mask)
12612 {
5848830f 12613 saved_regs += bit_count (live_regs_mask) * 4;
954954d1
PB		 12614 if (optimize_size && !frame_pointer_needed
12615 && saved_regs == offsets->saved_regs - offsets->saved_args)
12616 {
12617 /* If no coprocessor registers are being pushed and we don't have
12618 to worry about a frame pointer then push extra registers to
12619 create the stack frame. This is done is a way that does not
12620 alter the frame layout, so is independent of the epilogue. */
12621 int n;
12622 int frame;
12623 n = 0;
12624 while (n < 8 && (live_regs_mask & (1 << n)) == 0)
12625 n++;
12626 frame = offsets->outgoing_args - (offsets->saved_args + saved_regs);
12627 if (frame && n * 4 >= frame)
12628 {
12629 n = frame / 4;
12630 live_regs_mask |= (1 << n) - 1;
12631 saved_regs += frame;
12632 }
12633 }
12634 insn = emit_multi_reg_push (live_regs_mask);
2c849145 12635 RTX_FRAME_RELATED_P (insn) = 1;
e2c671ba 12636 }
d5b7b3ae 12637
6d3d9133 12638 if (! IS_VOLATILE (func_type))
5b3e6663 12639 saved_regs += arm_save_coproc_regs ();
b111229a 12640
5b3e6663
PB		 12641 if (frame_pointer_needed && TARGET_ARM)
12642 {
12643 /* Create the new frame pointer. */
ec6237e4 12644 if (TARGET_APCS_FRAME)
9b66ebb1 12645 {
5b3e6663
PB		 12646 insn = GEN_INT (-(4 + args_to_push + fp_offset));
12647 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
12648 RTX_FRAME_RELATED_P (insn) = 1;
9b66ebb1 12649
5b3e6663 12650 if (IS_NESTED (func_type))
9b66ebb1 12651 {
5b3e6663 12652 /* Recover the static chain register. */
6fb5fa3c 12653 if (!df_regs_ever_live_p (3)
5b3e6663
PB		 12654 || saved_pretend_args)
12655 insn = gen_rtx_REG (SImode, 3);
38173d38 12656 else /* if (crtl->args.pretend_args_size == 0) */
9b66ebb1 12657 {
5b3e6663
PB		 12658 insn = plus_constant (hard_frame_pointer_rtx, 4);
12659 insn = gen_frame_mem (SImode, insn);
9b66ebb1 12660 }
5b3e6663
PB		 12661 emit_set_insn (ip_rtx, insn);
12662 /* Add a USE to stop propagate_one_insn() from barfing. */
12663 emit_insn (gen_prologue_use (ip_rtx));
9b66ebb1 12664 }
68dfd979 12665 }
ec6237e4
PB		 12666 else
12667 {
12668 insn = GEN_INT (saved_regs - 4);
12669 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
12670 stack_pointer_rtx, insn));
12671 RTX_FRAME_RELATED_P (insn) = 1;
12672 }
2c849145 12673 }
e2c671ba 12674
5848830f 12675 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
e2c671ba 12676 {
745b9093
JM		 12677 /* This add can produce multiple insns for a large constant, so we
12678 need to get tricky. */
12679 rtx last = get_last_insn ();
5848830f
PB		 12680
12681 amount = GEN_INT (offsets->saved_args + saved_regs
12682 - offsets->outgoing_args);
12683
2c849145
JM		 12684 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12685 amount));
745b9093
JM		 12686 do
12687 {
12688 last = last ? NEXT_INSN (last) : get_insns ();
12689 RTX_FRAME_RELATED_P (last) = 1;
12690 }
12691 while (last != insn);
e04c2d6c
RE		 12692
12693 /* If the frame pointer is needed, emit a special barrier that
12694 will prevent the scheduler from moving stores to the frame
12695 before the stack adjustment. */
12696 if (frame_pointer_needed)
3894f59e
RE		 12697 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
12698 hard_frame_pointer_rtx));
e2c671ba
RE		 12699 }
12700
876f13b0 12701
5b3e6663
PB		 12702 if (frame_pointer_needed && TARGET_THUMB2)
12703 thumb_set_frame_pointer (offsets);
12704
020a4035 12705 if (flag_pic && arm_pic_register != INVALID_REGNUM)
5b3e6663
PB		 12706 {
12707 unsigned long mask;
12708
12709 mask = live_regs_mask;
12710 mask &= THUMB2_WORK_REGS;
12711 if (!IS_NESTED (func_type))
12712 mask |= (1 << IP_REGNUM);
12713 arm_load_pic_register (mask);
12714 }
876f13b0 12715
e2c671ba 12716 /* If we are profiling, make sure no instructions are scheduled before
f5a1b0d2 12717 the call to mcount. Similarly if the user has requested no
74d9c39f
DJ		 12718 scheduling in the prolog. Similarly if we want non-call exceptions
12719 using the EABI unwinder, to prevent faulting instructions from being
12720 swapped with a stack adjustment. */
e3b5732b 12721 if (crtl->profile || !TARGET_SCHED_PROLOG
74d9c39f 12722 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
e2c671ba 12723 emit_insn (gen_blockage ());
6f7ebcbb
NC		 12724
12725 /* If the link register is being kept alive, with the return address in it,
12726 then make sure that it does not get reused by the ce2 pass. */
12727 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
6fb5fa3c 12728 cfun->machine->lr_save_eliminated = 1;
e2c671ba 12729}
cce8749e 12730\f
5b3e6663
PB		 12731/* Print condition code to STREAM. Helper function for arm_print_operand. */
12732static void
12733arm_print_condition (FILE *stream)
12734{
12735 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
12736 {
12737 /* Branch conversion is not implemented for Thumb-2. */
12738 if (TARGET_THUMB)
12739 {
12740 output_operand_lossage ("predicated Thumb instruction");
12741 return;
12742 }
12743 if (current_insn_predicate != NULL)
12744 {
12745 output_operand_lossage
12746 ("predicated instruction in conditional sequence");
12747 return;
12748 }
12749
12750 fputs (arm_condition_codes[arm_current_cc], stream);
12751 }
12752 else if (current_insn_predicate)
12753 {
12754 enum arm_cond_code code;
12755
12756 if (TARGET_THUMB1)
12757 {
12758 output_operand_lossage ("predicated Thumb instruction");
12759 return;
12760 }
12761
12762 code = get_arm_condition_code (current_insn_predicate);
12763 fputs (arm_condition_codes[code], stream);
12764 }
12765}
12766
12767
9997d19d
RE		 12768/* If CODE is 'd', then the X is a condition operand and the instruction
12769 should only be executed if the condition is true.
ddd5a7c1 12770 if CODE is 'D', then the X is a condition operand and the instruction
9997d19d
RE		 12771 should only be executed if the condition is false: however, if the mode
12772 of the comparison is CCFPEmode, then always execute the instruction -- we
12773 do this because in these circumstances !GE does not necessarily imply LT;
12774 in these cases the instruction pattern will take care to make sure that
12775 an instruction containing %d will follow, thereby undoing the effects of
ddd5a7c1 12776 doing this instruction unconditionally.
9997d19d
RE		 12777 If CODE is 'N' then X is a floating point operand that must be negated
12778 before output.
12779 If CODE is 'B' then output a bitwise inverted value of X (a const int).
12780 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9997d19d 12781void
e32bac5b 12782arm_print_operand (FILE *stream, rtx x, int code)
9997d19d
RE		 12783{
12784 switch (code)
12785 {
12786 case '@':
f3139301 12787 fputs (ASM_COMMENT_START, stream);
9997d19d
RE		 12788 return;
12789
d5b7b3ae
RE		 12790 case '_':
12791 fputs (user_label_prefix, stream);
12792 return;
f676971a 12793
9997d19d 12794 case '|':
f3139301 12795 fputs (REGISTER_PREFIX, stream);
9997d19d
RE		 12796 return;
12797
12798 case '?':
5b3e6663
PB		 12799 arm_print_condition (stream);
12800 return;
cca0a211 12801
5b3e6663
PB		 12802 case '(':
12803 /* Nothing in unified syntax, otherwise the current condition code. */
12804 if (!TARGET_UNIFIED_ASM)
12805 arm_print_condition (stream);
12806 break;
12807
12808 case ')':
12809 /* The current condition code in unified syntax, otherwise nothing. */
12810 if (TARGET_UNIFIED_ASM)
12811 arm_print_condition (stream);
12812 break;
12813
12814 case '.':
12815 /* The current condition code for a condition code setting instruction.
7a085dce 12816 Preceded by 's' in unified syntax, otherwise followed by 's'. */
5b3e6663
PB		 12817 if (TARGET_UNIFIED_ASM)
12818 {
12819 fputc('s', stream);
12820 arm_print_condition (stream);
cca0a211 12821 }
5b3e6663 12822 else
cca0a211 12823 {
5b3e6663
PB		 12824 arm_print_condition (stream);
12825 fputc('s', stream);
cca0a211 12826 }
9997d19d
RE		 12827 return;
12828
5b3e6663
PB		 12829 case '!':
12830 /* If the instruction is conditionally executed then print
12831 the current condition code, otherwise print 's'. */
12832 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
12833 if (current_insn_predicate)
12834 arm_print_condition (stream);
12835 else
12836 fputc('s', stream);
12837 break;
12838
88f77cba 12839 /* %# is a "break" sequence. It doesn't output anything, but is used to
cea618ac 12840 separate e.g. operand numbers from following text, if that text consists
88f77cba
JB		 12841 of further digits which we don't want to be part of the operand
12842 number. */
12843 case '#':
12844 return;
12845
9997d19d
RE		 12846 case 'N':
12847 {
12848 REAL_VALUE_TYPE r;
12849 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
12850 r = REAL_VALUE_NEGATE (r);
12851 fprintf (stream, "%s", fp_const_from_val (&r));
12852 }
12853 return;
12854
88f77cba
JB		 12855 /* An integer without a preceding # sign. */
12856 case 'c':
12857 gcc_assert (GET_CODE (x) == CONST_INT);
12858 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
12859 return;
12860
9997d19d
RE		 12861 case 'B':
12862 if (GET_CODE (x) == CONST_INT)
4bc74ece
NC		 12863 {
12864 HOST_WIDE_INT val;
5895f793 12865 val = ARM_SIGN_EXTEND (~INTVAL (x));
36ba9cb8 12866 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
4bc74ece 12867 }
9997d19d
RE		 12868 else
12869 {
12870 putc ('~', stream);
12871 output_addr_const (stream, x);
12872 }
12873 return;
12874
5b3e6663
PB		 12875 case 'L':
12876 /* The low 16 bits of an immediate constant. */
12877 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
12878 return;
12879
9997d19d
RE		 12880 case 'i':
12881 fprintf (stream, "%s", arithmetic_instr (x, 1));
12882 return;
12883
9b6b54e2
NC		 12884 /* Truncate Cirrus shift counts. */
12885 case 's':
12886 if (GET_CODE (x) == CONST_INT)
12887 {
12888 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
12889 return;
12890 }
12891 arm_print_operand (stream, x, 0);
12892 return;
12893
9997d19d
RE		 12894 case 'I':
12895 fprintf (stream, "%s", arithmetic_instr (x, 0));
12896 return;
12897
12898 case 'S':
12899 {
12900 HOST_WIDE_INT val;
beed32b8
RE		 12901 const char *shift;
12902
12903 if (!shift_operator (x, SImode))
12904 {
12905 output_operand_lossage ("invalid shift operand");
12906 break;
12907 }
12908
12909 shift = shift_op (x, &val);
9997d19d 12910
e2c671ba
RE		 12911 if (shift)
12912 {
beed32b8 12913 fprintf (stream, ", %s ", shift);
e2c671ba
RE		 12914 if (val == -1)
12915 arm_print_operand (stream, XEXP (x, 1), 0);
12916 else
4a0a75dd 12917 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
e2c671ba 12918 }
9997d19d
RE		 12919 }
12920 return;
12921
d5b7b3ae 12922 /* An explanation of the 'Q', 'R' and 'H' register operands:
f676971a 12923
d5b7b3ae
RE		 12924 In a pair of registers containing a DI or DF value the 'Q'
12925 operand returns the register number of the register containing
093354e0 12926 the least significant part of the value. The 'R' operand returns
d5b7b3ae
RE		 12927 the register number of the register containing the most
12928 significant part of the value.
f676971a 12929
d5b7b3ae
RE		 12930 The 'H' operand returns the higher of the two register numbers.
12931 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
093354e0 12932 same as the 'Q' operand, since the most significant part of the
d5b7b3ae
RE		 12933 value is held in the lower number register. The reverse is true
12934 on systems where WORDS_BIG_ENDIAN is false.
f676971a 12935
d5b7b3ae
RE		 12936 The purpose of these operands is to distinguish between cases
12937 where the endian-ness of the values is important (for example
12938 when they are added together), and cases where the endian-ness
12939 is irrelevant, but the order of register operations is important.
12940 For example when loading a value from memory into a register
12941 pair, the endian-ness does not matter. Provided that the value
12942 from the lower memory address is put into the lower numbered
12943 register, and the value from the higher address is put into the
12944 higher numbered register, the load will work regardless of whether
12945 the value being loaded is big-wordian or little-wordian. The
12946 order of the two register loads can matter however, if the address
12947 of the memory location is actually held in one of the registers
12948 being overwritten by the load. */
c1c2bc04 12949 case 'Q':
22de4c3d
RE		 12950 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12951 {
12952 output_operand_lossage ("invalid operand for code '%c'", code);
12953 return;
12954 }
12955
d5b7b3ae 12956 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
c1c2bc04
RE		 12957 return;
12958
9997d19d 12959 case 'R':
22de4c3d
RE		 12960 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12961 {
12962 output_operand_lossage ("invalid operand for code '%c'", code);
12963 return;
12964 }
12965
d5b7b3ae
RE		 12966 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
12967 return;
12968
12969 case 'H':
22de4c3d
RE		 12970 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12971 {
12972 output_operand_lossage ("invalid operand for code '%c'", code);
12973 return;
12974 }
12975
d5b7b3ae 12976 asm_fprintf (stream, "%r", REGNO (x) + 1);
9997d19d
RE		 12977 return;
12978
88f77cba
JB		 12979 case 'J':
12980 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12981 {
12982 output_operand_lossage ("invalid operand for code '%c'", code);
12983 return;
12984 }
12985
12986 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2));
12987 return;
12988
12989 case 'K':
12990 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12991 {
12992 output_operand_lossage ("invalid operand for code '%c'", code);
12993 return;
12994 }
12995
12996 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3));
12997 return;
12998
9997d19d 12999 case 'm':
f676971a 13000 asm_fprintf (stream, "%r",
d5b7b3ae
RE		 13001 GET_CODE (XEXP (x, 0)) == REG
13002 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9997d19d
RE		 13003 return;
13004
13005 case 'M':
dd18ae56 13006 asm_fprintf (stream, "{%r-%r}",
d5b7b3ae 13007 REGNO (x),
e9d7b180 13008 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9997d19d
RE		 13009 return;
13010
88f77cba
JB		 13011 /* Like 'M', but writing doubleword vector registers, for use by Neon
13012 insns. */
13013 case 'h':
13014 {
13015 int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2;
13016 int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2;
13017 if (numregs == 1)
13018 asm_fprintf (stream, "{d%d}", regno);
13019 else
13020 asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1);
13021 }
13022 return;
13023
9997d19d 13024 case 'd':
64e92a26
RE		 13025 /* CONST_TRUE_RTX means always -- that's the default. */
13026 if (x == const_true_rtx)
d5b7b3ae 13027 return;
f676971a 13028
22de4c3d
RE		 13029 if (!COMPARISON_P (x))
13030 {
13031 output_operand_lossage ("invalid operand for code '%c'", code);
13032 return;
13033 }
13034
defc0463
RE		 13035 fputs (arm_condition_codes[get_arm_condition_code (x)],
13036 stream);
9997d19d
RE		 13037 return;
13038
13039 case 'D':
112cdef5 13040 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
64e92a26
RE		 13041 want to do that. */
13042 if (x == const_true_rtx)
22de4c3d 13043 {
4dad0aca 13044 output_operand_lossage ("instruction never executed");
22de4c3d
RE		 13045 return;
13046 }
13047 if (!COMPARISON_P (x))
13048 {
13049 output_operand_lossage ("invalid operand for code '%c'", code);
13050 return;
13051 }
d5b7b3ae 13052
defc0463
RE		 13053 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
13054 (get_arm_condition_code (x))],
13055 stream);
9997d19d
RE		 13056 return;
13057
9b6b54e2
NC		 13058 /* Cirrus registers can be accessed in a variety of ways:
13059 single floating point (f)
13060 double floating point (d)
13061 32bit integer (fx)
13062 64bit integer (dx). */
13063 case 'W': /* Cirrus register in F mode. */
13064 case 'X': /* Cirrus register in D mode. */
13065 case 'Y': /* Cirrus register in FX mode. */
13066 case 'Z': /* Cirrus register in DX mode. */
e6d29d15
NS		 13067 gcc_assert (GET_CODE (x) == REG
13068 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
9b6b54e2
NC		 13069
13070 fprintf (stream, "mv%s%s",
13071 code == 'W' ? "f"
13072 : code == 'X' ? "d"
13073 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
13074
13075 return;
13076
13077 /* Print cirrus register in the mode specified by the register's mode. */
13078 case 'V':
13079 {
13080 int mode = GET_MODE (x);
13081
13082 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
22de4c3d
RE		 13083 {
13084 output_operand_lossage ("invalid operand for code '%c'", code);
13085 return;
13086 }
9b6b54e2
NC		 13087
13088 fprintf (stream, "mv%s%s",
13089 mode == DFmode ? "d"
13090 : mode == SImode ? "fx"
13091 : mode == DImode ? "dx"
13092 : "f", reg_names[REGNO (x)] + 2);
13093
13094 return;
13095 }
13096
5a9335ef
NC		 13097 case 'U':
13098 if (GET_CODE (x) != REG
13099 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
13100 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
13101 /* Bad value for wCG register number. */
22de4c3d
RE		 13102 {
13103 output_operand_lossage ("invalid operand for code '%c'", code);
13104 return;
13105 }
13106
5a9335ef
NC		 13107 else
13108 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
13109 return;
13110
13111 /* Print an iWMMXt control register name. */
13112 case 'w':
13113 if (GET_CODE (x) != CONST_INT
13114 || INTVAL (x) < 0
13115 || INTVAL (x) >= 16)
13116 /* Bad value for wC register number. */
22de4c3d
RE		 13117 {
13118 output_operand_lossage ("invalid operand for code '%c'", code);
13119 return;
13120 }
13121
5a9335ef
NC		 13122 else
13123 {
13124 static const char * wc_reg_names [16] =
13125 {
13126 "wCID", "wCon", "wCSSF", "wCASF",
13127 "wC4", "wC5", "wC6", "wC7",
13128 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
13129 "wC12", "wC13", "wC14", "wC15"
13130 };
f676971a 13131
5a9335ef
NC		 13132 fprintf (stream, wc_reg_names [INTVAL (x)]);
13133 }
13134 return;
13135
88f77cba 13136 /* Print a VFP/Neon double precision or quad precision register name. */
9b66ebb1 13137 case 'P':
88f77cba 13138 case 'q':
9b66ebb1
PB		 13139 {
13140 int mode = GET_MODE (x);
88f77cba
JB		 13141 int is_quad = (code == 'q');
13142 int regno;
9b66ebb1 13143
88f77cba 13144 if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8))
22de4c3d
RE		 13145 {
13146 output_operand_lossage ("invalid operand for code '%c'", code);
13147 return;
13148 }
9b66ebb1
PB		 13149
13150 if (GET_CODE (x) != REG
13151 || !IS_VFP_REGNUM (REGNO (x)))
22de4c3d
RE		 13152 {
13153 output_operand_lossage ("invalid operand for code '%c'", code);
13154 return;
13155 }
9b66ebb1 13156
88f77cba
JB		 13157 regno = REGNO (x);
13158 if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno))
13159 || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno)))
22de4c3d
RE		 13160 {
13161 output_operand_lossage ("invalid operand for code '%c'", code);
13162 return;
13163 }
9b66ebb1 13164
88f77cba
JB		 13165 fprintf (stream, "%c%d", is_quad ? 'q' : 'd',
13166 (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1));
13167 }
13168 return;
13169
13170 /* These two codes print the low/high doubleword register of a Neon quad
13171 register, respectively. For pair-structure types, can also print
13172 low/high quadword registers. */
13173 case 'e':
13174 case 'f':
13175 {
13176 int mode = GET_MODE (x);
13177 int regno;
13178
13179 if ((GET_MODE_SIZE (mode) != 16
13180 && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG)
13181 {
13182 output_operand_lossage ("invalid operand for code '%c'", code);
13183 return;
13184 }
13185
13186 regno = REGNO (x);
13187 if (!NEON_REGNO_OK_FOR_QUAD (regno))
13188 {
13189 output_operand_lossage ("invalid operand for code '%c'", code);
13190 return;
13191 }
13192
13193 if (GET_MODE_SIZE (mode) == 16)
13194 fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1)
13195 + (code == 'f' ? 1 : 0));
13196 else
13197 fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2)
13198 + (code == 'f' ? 1 : 0));
9b66ebb1
PB		 13199 }
13200 return;
13201
f1adb0a9
JB		 13202 /* Print a VFPv3 floating-point constant, represented as an integer
13203 index. */
13204 case 'G':
13205 {
13206 int index = vfp3_const_double_index (x);
13207 gcc_assert (index != -1);
13208 fprintf (stream, "%d", index);
13209 }
13210 return;
13211
88f77cba
JB		 13212 /* Print bits representing opcode features for Neon.
13213
13214 Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed
13215 and polynomials as unsigned.
13216
13217 Bit 1 is 1 for floats and polynomials, 0 for ordinary integers.
13218
13219 Bit 2 is 1 for rounding functions, 0 otherwise. */
13220
13221 /* Identify the type as 's', 'u', 'p' or 'f'. */
13222 case 'T':
13223 {
13224 HOST_WIDE_INT bits = INTVAL (x);
13225 fputc ("uspf"[bits & 3], stream);
13226 }
13227 return;
13228
13229 /* Likewise, but signed and unsigned integers are both 'i'. */
13230 case 'F':
13231 {
13232 HOST_WIDE_INT bits = INTVAL (x);
13233 fputc ("iipf"[bits & 3], stream);
13234 }
13235 return;
13236
13237 /* As for 'T', but emit 'u' instead of 'p'. */
13238 case 't':
13239 {
13240 HOST_WIDE_INT bits = INTVAL (x);
13241 fputc ("usuf"[bits & 3], stream);
13242 }
13243 return;
13244
13245 /* Bit 2: rounding (vs none). */
13246 case 'O':
13247 {
13248 HOST_WIDE_INT bits = INTVAL (x);
13249 fputs ((bits & 4) != 0 ? "r" : "", stream);
13250 }
13251 return;
13252
9997d19d
RE		 13253 default:
13254 if (x == 0)
22de4c3d
RE		 13255 {
13256 output_operand_lossage ("missing operand");
13257 return;
13258 }
9997d19d 13259
e6d29d15 13260 switch (GET_CODE (x))
9997d19d 13261 {
e6d29d15
NS		 13262 case REG:
13263 asm_fprintf (stream, "%r", REGNO (x));
13264 break;
13265
13266 case MEM:
9997d19d
RE		 13267 output_memory_reference_mode = GET_MODE (x);
13268 output_address (XEXP (x, 0));
e6d29d15
NS		 13269 break;
13270
13271 case CONST_DOUBLE:
88f77cba
JB		 13272 if (TARGET_NEON)
13273 {
13274 char fpstr[20];
13275 real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x),
13276 sizeof (fpstr), 0, 1);
13277 fprintf (stream, "#%s", fpstr);
13278 }
13279 else
13280 fprintf (stream, "#%s", fp_immediate_constant (x));
e6d29d15
NS		 13281 break;
13282
13283 default:
13284 gcc_assert (GET_CODE (x) != NEG);
9997d19d
RE		 13285 fputc ('#', stream);
13286 output_addr_const (stream, x);
e6d29d15 13287 break;
9997d19d
RE		 13288 }
13289 }
13290}
cce8749e 13291\f
301d03af
RS		 13292/* Target hook for assembling integer objects. The ARM version needs to
13293 handle word-sized values specially. */
301d03af 13294static bool
e32bac5b 13295arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af 13296{
88f77cba
JB		 13297 enum machine_mode mode;
13298
301d03af
RS		 13299 if (size == UNITS_PER_WORD && aligned_p)
13300 {
13301 fputs ("\t.word\t", asm_out_file);
13302 output_addr_const (asm_out_file, x);
13303
13304 /* Mark symbols as position independent. We only do this in the
d6b4baa4 13305 .text segment, not in the .data segment. */
301d03af
RS		 13306 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
13307 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
13308 {
9403b7f7
RS		 13309 /* See legitimize_pic_address for an explanation of the
13310 TARGET_VXWORKS_RTP check. */
13311 if (TARGET_VXWORKS_RTP
13312 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
301d03af 13313 fputs ("(GOT)", asm_out_file);
9403b7f7
RS		 13314 else
13315 fputs ("(GOTOFF)", asm_out_file);
301d03af
RS		 13316 }
13317 fputc ('\n', asm_out_file);
13318 return true;
13319 }
1d6e90ac 13320
88f77cba
JB		 13321 mode = GET_MODE (x);
13322
13323 if (arm_vector_mode_supported_p (mode))
5a9335ef
NC		 13324 {
13325 int i, units;
88f77cba 13326 unsigned int invmask = 0, parts_per_word;
5a9335ef 13327
e6d29d15 13328 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5a9335ef
NC		 13329
13330 units = CONST_VECTOR_NUNITS (x);
88f77cba 13331 size = GET_MODE_SIZE (GET_MODE_INNER (mode));
5a9335ef 13332
88f77cba
JB		 13333 /* For big-endian Neon vectors, we must permute the vector to the form
13334 which, when loaded by a VLDR or VLDM instruction, will give a vector
13335 with the elements in the right order. */
13336 if (TARGET_NEON && WORDS_BIG_ENDIAN)
13337 {
13338 parts_per_word = UNITS_PER_WORD / size;
13339 /* FIXME: This might be wrong for 64-bit vector elements, but we don't
13340 support those anywhere yet. */
13341 invmask = (parts_per_word == 0) ? 0 : (1 << (parts_per_word - 1)) - 1;
13342 }
5a9335ef 13343
88f77cba
JB		 13344 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13345 for (i = 0; i < units; i++)
13346 {
13347 rtx elt = CONST_VECTOR_ELT (x, i ^ invmask);
13348 assemble_integer
13349 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
13350 }
13351 else
13352 for (i = 0; i < units; i++)
13353 {
13354 rtx elt = CONST_VECTOR_ELT (x, i);
13355 REAL_VALUE_TYPE rval;
5a9335ef 13356
88f77cba
JB		 13357 REAL_VALUE_FROM_CONST_DOUBLE (rval, elt);
13358
13359 assemble_real
13360 (rval, GET_MODE_INNER (mode),
13361 i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT);
13362 }
5a9335ef
NC		 13363
13364 return true;
13365 }
13366
301d03af
RS		 13367 return default_assemble_integer (x, size, aligned_p);
13368}
7abc66b1 13369
7abc66b1 13370static void
9f296620 13371arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
7abc66b1 13372{
50603eed
PB		 13373 section *s;
13374
7abc66b1
JB		 13375 if (!TARGET_AAPCS_BASED)
13376 {
9f296620
MM		 13377 (is_ctor ?
13378 default_named_section_asm_out_constructor
13379 : default_named_section_asm_out_destructor) (symbol, priority);
7abc66b1
JB		 13380 return;
13381 }
13382
13383 /* Put these in the .init_array section, using a special relocation. */
50603eed
PB		 13384 if (priority != DEFAULT_INIT_PRIORITY)
13385 {
13386 char buf[18];
9f296620
MM		 13387 sprintf (buf, "%s.%.5u",
13388 is_ctor ? ".init_array" : ".fini_array",
13389 priority);
50603eed
PB		 13390 s = get_section (buf, SECTION_WRITE, NULL_TREE);
13391 }
9f296620 13392 else if (is_ctor)
50603eed 13393 s = ctors_section;
9f296620
MM		 13394 else
13395 s = dtors_section;
50603eed
PB		 13396
13397 switch_to_section (s);
7abc66b1
JB		 13398 assemble_align (POINTER_SIZE);
13399 fputs ("\t.word\t", asm_out_file);
13400 output_addr_const (asm_out_file, symbol);
13401 fputs ("(target1)\n", asm_out_file);
13402}
9f296620
MM		 13403
13404/* Add a function to the list of static constructors. */
13405
13406static void
13407arm_elf_asm_constructor (rtx symbol, int priority)
13408{
13409 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
13410}
13411
13412/* Add a function to the list of static destructors. */
13413
13414static void
13415arm_elf_asm_destructor (rtx symbol, int priority)
13416{
13417 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
13418}
301d03af 13419\f
cce8749e
CH		 13420/* A finite state machine takes care of noticing whether or not instructions
13421 can be conditionally executed, and thus decrease execution time and code
13422 size by deleting branch instructions. The fsm is controlled by
13423 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
13424
13425/* The state of the fsm controlling condition codes are:
13426 0: normal, do nothing special
13427 1: make ASM_OUTPUT_OPCODE not output this instruction
13428 2: make ASM_OUTPUT_OPCODE not output this instruction
13429 3: make instructions conditional
13430 4: make instructions conditional
13431
13432 State transitions (state->state by whom under condition):
13433 0 -> 1 final_prescan_insn if the `target' is a label
13434 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
13435 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
13436 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
4977bab6 13437 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
cce8749e
CH		 13438 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
13439 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
13440 (the target insn is arm_target_insn).
13441
ff9940b0
RE		 13442 If the jump clobbers the conditions then we use states 2 and 4.
13443
13444 A similar thing can be done with conditional return insns.
13445
cce8749e
CH		 13446 XXX In case the `target' is an unconditional branch, this conditionalising
13447 of the instructions always reduces code size, but not always execution
13448 time. But then, I want to reduce the code size to somewhere near what
13449 /bin/cc produces. */
13450
5b3e6663
PB		 13451/* In addition to this, state is maintained for Thumb-2 COND_EXEC
13452 instructions. When a COND_EXEC instruction is seen the subsequent
13453 instructions are scanned so that multiple conditional instructions can be
13454 combined into a single IT block. arm_condexec_count and arm_condexec_mask
13455 specify the length and true/false mask for the IT block. These will be
13456 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
13457
cce8749e
CH		 13458/* Returns the index of the ARM condition code string in
13459 `arm_condition_codes'. COMPARISON should be an rtx like
13460 `(eq (...) (...))'. */
84ed5e79 13461static enum arm_cond_code
e32bac5b 13462get_arm_condition_code (rtx comparison)
cce8749e 13463{
5165176d 13464 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
1d6e90ac
NC		 13465 int code;
13466 enum rtx_code comp_code = GET_CODE (comparison);
5165176d
RE		 13467
13468 if (GET_MODE_CLASS (mode) != MODE_CC)
84ed5e79 13469 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
5165176d
RE		 13470 XEXP (comparison, 1));
13471
13472 switch (mode)
cce8749e 13473 {
84ed5e79
RE		 13474 case CC_DNEmode: code = ARM_NE; goto dominance;
13475 case CC_DEQmode: code = ARM_EQ; goto dominance;
13476 case CC_DGEmode: code = ARM_GE; goto dominance;
13477 case CC_DGTmode: code = ARM_GT; goto dominance;
13478 case CC_DLEmode: code = ARM_LE; goto dominance;
13479 case CC_DLTmode: code = ARM_LT; goto dominance;
13480 case CC_DGEUmode: code = ARM_CS; goto dominance;
13481 case CC_DGTUmode: code = ARM_HI; goto dominance;
13482 case CC_DLEUmode: code = ARM_LS; goto dominance;
13483 case CC_DLTUmode: code = ARM_CC;
13484
13485 dominance:
e6d29d15 13486 gcc_assert (comp_code == EQ || comp_code == NE);
84ed5e79
RE		 13487
13488 if (comp_code == EQ)
13489 return ARM_INVERSE_CONDITION_CODE (code);
13490 return code;
13491
5165176d 13492 case CC_NOOVmode:
84ed5e79 13493 switch (comp_code)
5165176d 13494 {
84ed5e79
RE		 13495 case NE: return ARM_NE;
13496 case EQ: return ARM_EQ;
13497 case GE: return ARM_PL;
13498 case LT: return ARM_MI;
e6d29d15 13499 default: gcc_unreachable ();
5165176d
RE		 13500 }
13501
13502 case CC_Zmode:
84ed5e79 13503 switch (comp_code)
5165176d 13504 {
84ed5e79
RE		 13505 case NE: return ARM_NE;
13506 case EQ: return ARM_EQ;
e6d29d15 13507 default: gcc_unreachable ();
5165176d
RE		 13508 }
13509
defc0463
RE		 13510 case CC_Nmode:
13511 switch (comp_code)
13512 {
13513 case NE: return ARM_MI;
13514 case EQ: return ARM_PL;
e6d29d15 13515 default: gcc_unreachable ();
defc0463
RE		 13516 }
13517
5165176d 13518 case CCFPEmode:
e45b72c4
RE		 13519 case CCFPmode:
13520 /* These encodings assume that AC=1 in the FPA system control
13521 byte. This allows us to handle all cases except UNEQ and
13522 LTGT. */
84ed5e79
RE		 13523 switch (comp_code)
13524 {
13525 case GE: return ARM_GE;
13526 case GT: return ARM_GT;
13527 case LE: return ARM_LS;
13528 case LT: return ARM_MI;
e45b72c4
RE		 13529 case NE: return ARM_NE;
13530 case EQ: return ARM_EQ;
13531 case ORDERED: return ARM_VC;
13532 case UNORDERED: return ARM_VS;
13533 case UNLT: return ARM_LT;
13534 case UNLE: return ARM_LE;
13535 case UNGT: return ARM_HI;
13536 case UNGE: return ARM_PL;
13537 /* UNEQ and LTGT do not have a representation. */
13538 case UNEQ: /* Fall through. */
13539 case LTGT: /* Fall through. */
e6d29d15 13540 default: gcc_unreachable ();
84ed5e79
RE		 13541 }
13542
13543 case CC_SWPmode:
13544 switch (comp_code)
13545 {
13546 case NE: return ARM_NE;
13547 case EQ: return ARM_EQ;
13548 case GE: return ARM_LE;
13549 case GT: return ARM_LT;
13550 case LE: return ARM_GE;
13551 case LT: return ARM_GT;
13552 case GEU: return ARM_LS;
13553 case GTU: return ARM_CC;
13554 case LEU: return ARM_CS;
13555 case LTU: return ARM_HI;
e6d29d15 13556 default: gcc_unreachable ();
84ed5e79
RE		 13557 }
13558
bd9c7e23
RE		 13559 case CC_Cmode:
13560 switch (comp_code)
13561 {
13562 case LTU: return ARM_CS;
13563 case GEU: return ARM_CC;
e6d29d15 13564 default: gcc_unreachable ();
bd9c7e23 13565 }
f676971a 13566
5165176d 13567 case CCmode:
84ed5e79 13568 switch (comp_code)
5165176d 13569 {
84ed5e79
RE		 13570 case NE: return ARM_NE;
13571 case EQ: return ARM_EQ;
13572 case GE: return ARM_GE;
13573 case GT: return ARM_GT;
13574 case LE: return ARM_LE;
13575 case LT: return ARM_LT;
13576 case GEU: return ARM_CS;
13577 case GTU: return ARM_HI;
13578 case LEU: return ARM_LS;
13579 case LTU: return ARM_CC;
e6d29d15 13580 default: gcc_unreachable ();
5165176d
RE		 13581 }
13582
e6d29d15 13583 default: gcc_unreachable ();
cce8749e 13584 }
f3bb6135 13585}
cce8749e 13586
44c7bd63 13587/* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
5b3e6663
PB		 13588 instructions. */
13589void
13590thumb2_final_prescan_insn (rtx insn)
13591{
13592 rtx first_insn = insn;
13593 rtx body = PATTERN (insn);
13594 rtx predicate;
13595 enum arm_cond_code code;
13596 int n;
13597 int mask;
13598
13599 /* Remove the previous insn from the count of insns to be output. */
13600 if (arm_condexec_count)
13601 arm_condexec_count--;
13602
13603 /* Nothing to do if we are already inside a conditional block. */
13604 if (arm_condexec_count)
13605 return;
13606
13607 if (GET_CODE (body) != COND_EXEC)
13608 return;
13609
13610 /* Conditional jumps are implemented directly. */
13611 if (GET_CODE (insn) == JUMP_INSN)
13612 return;
13613
13614 predicate = COND_EXEC_TEST (body);
13615 arm_current_cc = get_arm_condition_code (predicate);
13616
13617 n = get_attr_ce_count (insn);
13618 arm_condexec_count = 1;
13619 arm_condexec_mask = (1 << n) - 1;
13620 arm_condexec_masklen = n;
13621 /* See if subsequent instructions can be combined into the same block. */
13622 for (;;)
13623 {
13624 insn = next_nonnote_insn (insn);
13625
13626 /* Jumping into the middle of an IT block is illegal, so a label or
13627 barrier terminates the block. */
13628 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
13629 break;
13630
13631 body = PATTERN (insn);
13632 /* USE and CLOBBER aren't really insns, so just skip them. */
13633 if (GET_CODE (body) == USE
13634 || GET_CODE (body) == CLOBBER)
5b0202af 13635 continue;
5b3e6663 13636
7a085dce 13637 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
5b3e6663
PB		 13638 if (GET_CODE (body) != COND_EXEC)
13639 break;
13640 /* Allow up to 4 conditionally executed instructions in a block. */
13641 n = get_attr_ce_count (insn);
13642 if (arm_condexec_masklen + n > 4)
13643 break;
13644
13645 predicate = COND_EXEC_TEST (body);
13646 code = get_arm_condition_code (predicate);
13647 mask = (1 << n) - 1;
13648 if (arm_current_cc == code)
13649 arm_condexec_mask |= (mask << arm_condexec_masklen);
13650 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
13651 break;
13652
13653 arm_condexec_count++;
13654 arm_condexec_masklen += n;
13655
13656 /* A jump must be the last instruction in a conditional block. */
13657 if (GET_CODE(insn) == JUMP_INSN)
13658 break;
13659 }
13660 /* Restore recog_data (getting the attributes of other insns can
13661 destroy this array, but final.c assumes that it remains intact
13662 across this call). */
13663 extract_constrain_insn_cached (first_insn);
13664}
13665
cce8749e 13666void
e32bac5b 13667arm_final_prescan_insn (rtx insn)
cce8749e
CH		 13668{
13669 /* BODY will hold the body of INSN. */
1d6e90ac 13670 rtx body = PATTERN (insn);
cce8749e
CH		 13671
13672 /* This will be 1 if trying to repeat the trick, and things need to be
13673 reversed if it appears to fail. */
13674 int reverse = 0;
13675
ff9940b0
RE		 13676 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
13677 taken are clobbered, even if the rtl suggests otherwise. It also
13678 means that we have to grub around within the jump expression to find
13679 out what the conditions are when the jump isn't taken. */
13680 int jump_clobbers = 0;
f676971a 13681
6354dc9b 13682 /* If we start with a return insn, we only succeed if we find another one. */
ff9940b0 13683 int seeking_return = 0;
f676971a 13684
cce8749e
CH		 13685 /* START_INSN will hold the insn from where we start looking. This is the
13686 first insn after the following code_label if REVERSE is true. */
13687 rtx start_insn = insn;
13688
13689 /* If in state 4, check if the target branch is reached, in order to
13690 change back to state 0. */
13691 if (arm_ccfsm_state == 4)
13692 {
13693 if (insn == arm_target_insn)
f5a1b0d2
NC		 13694 {
13695 arm_target_insn = NULL;
13696 arm_ccfsm_state = 0;
13697 }
cce8749e
CH		 13698 return;
13699 }
13700
13701 /* If in state 3, it is possible to repeat the trick, if this insn is an
13702 unconditional branch to a label, and immediately following this branch
13703 is the previous target label which is only used once, and the label this
13704 branch jumps to is not too far off. */
13705 if (arm_ccfsm_state == 3)
13706 {
13707 if (simplejump_p (insn))
13708 {
13709 start_insn = next_nonnote_insn (start_insn);
13710 if (GET_CODE (start_insn) == BARRIER)
13711 {
13712 /* XXX Isn't this always a barrier? */
13713 start_insn = next_nonnote_insn (start_insn);
13714 }
13715 if (GET_CODE (start_insn) == CODE_LABEL
13716 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
13717 && LABEL_NUSES (start_insn) == 1)
13718 reverse = TRUE;
13719 else
13720 return;
13721 }
ff9940b0
RE		 13722 else if (GET_CODE (body) == RETURN)
13723 {
13724 start_insn = next_nonnote_insn (start_insn);
13725 if (GET_CODE (start_insn) == BARRIER)
13726 start_insn = next_nonnote_insn (start_insn);
13727 if (GET_CODE (start_insn) == CODE_LABEL
13728 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
13729 && LABEL_NUSES (start_insn) == 1)
13730 {
13731 reverse = TRUE;
13732 seeking_return = 1;
13733 }
13734 else
13735 return;
13736 }
cce8749e
CH		 13737 else
13738 return;
13739 }
13740
e6d29d15 13741 gcc_assert (!arm_ccfsm_state || reverse);
cce8749e
CH		 13742 if (GET_CODE (insn) != JUMP_INSN)
13743 return;
13744
f676971a 13745 /* This jump might be paralleled with a clobber of the condition codes
ff9940b0
RE		 13746 the jump should always come first */
13747 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
13748 body = XVECEXP (body, 0, 0);
13749
cce8749e
CH		 13750 if (reverse
13751 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
13752 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
13753 {
bd9c7e23
RE		 13754 int insns_skipped;
13755 int fail = FALSE, succeed = FALSE;
cce8749e
CH		 13756 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
13757 int then_not_else = TRUE;
ff9940b0 13758 rtx this_insn = start_insn, label = 0;
cce8749e 13759
f676971a 13760 /* If the jump cannot be done with one instruction, we cannot
e45b72c4 13761 conditionally execute the instruction in the inverse case. */
ff9940b0 13762 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
5bbe2d40 13763 {
5bbe2d40
RE		 13764 jump_clobbers = 1;
13765 return;
13766 }
f676971a 13767
cce8749e
CH		 13768 /* Register the insn jumped to. */
13769 if (reverse)
ff9940b0
RE		 13770 {
13771 if (!seeking_return)
13772 label = XEXP (SET_SRC (body), 0);
13773 }
cce8749e
CH		 13774 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
13775 label = XEXP (XEXP (SET_SRC (body), 1), 0);
13776 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
13777 {
13778 label = XEXP (XEXP (SET_SRC (body), 2), 0);
13779 then_not_else = FALSE;
13780 }
ff9940b0
RE		 13781 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
13782 seeking_return = 1;
13783 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
13784 {
13785 seeking_return = 1;
13786 then_not_else = FALSE;
13787 }
cce8749e 13788 else
e6d29d15 13789 gcc_unreachable ();
cce8749e
CH		 13790
13791 /* See how many insns this branch skips, and what kind of insns. If all
13792 insns are okay, and the label or unconditional branch to the same
13793 label is not too far away, succeed. */
13794 for (insns_skipped = 0;
b36ba79f 13795 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
cce8749e
CH		 13796 {
13797 rtx scanbody;
13798
13799 this_insn = next_nonnote_insn (this_insn);
13800 if (!this_insn)
13801 break;
13802
cce8749e
CH		 13803 switch (GET_CODE (this_insn))
13804 {
13805 case CODE_LABEL:
13806 /* Succeed if it is the target label, otherwise fail since
13807 control falls in from somewhere else. */
13808 if (this_insn == label)
13809 {
ff9940b0
RE		 13810 if (jump_clobbers)
13811 {
13812 arm_ccfsm_state = 2;
13813 this_insn = next_nonnote_insn (this_insn);
13814 }
13815 else
13816 arm_ccfsm_state = 1;
cce8749e
CH		 13817 succeed = TRUE;
13818 }
13819 else
13820 fail = TRUE;
13821 break;
13822
ff9940b0 13823 case BARRIER:
cce8749e 13824 /* Succeed if the following insn is the target label.
f676971a
EC		 13825 Otherwise fail.
13826 If return insns are used then the last insn in a function
6354dc9b 13827 will be a barrier. */
cce8749e 13828 this_insn = next_nonnote_insn (this_insn);
ff9940b0 13829 if (this_insn && this_insn == label)
cce8749e 13830 {
ff9940b0
RE		 13831 if (jump_clobbers)
13832 {
13833 arm_ccfsm_state = 2;
13834 this_insn = next_nonnote_insn (this_insn);
13835 }
13836 else
13837 arm_ccfsm_state = 1;
cce8749e
CH		 13838 succeed = TRUE;
13839 }
13840 else
13841 fail = TRUE;
13842 break;
13843
ff9940b0 13844 case CALL_INSN:
68d560d4
RE		 13845 /* The AAPCS says that conditional calls should not be
13846 used since they make interworking inefficient (the
13847 linker can't transform BL<cond> into BLX). That's
13848 only a problem if the machine has BLX. */
13849 if (arm_arch5)
13850 {
13851 fail = TRUE;
13852 break;
13853 }
13854
61f0ccff
RE		 13855 /* Succeed if the following insn is the target label, or
13856 if the following two insns are a barrier and the
13857 target label. */
13858 this_insn = next_nonnote_insn (this_insn);
13859 if (this_insn && GET_CODE (this_insn) == BARRIER)
13860 this_insn = next_nonnote_insn (this_insn);
bd9c7e23 13861
61f0ccff
RE		 13862 if (this_insn && this_insn == label
13863 && insns_skipped < max_insns_skipped)
13864 {
13865 if (jump_clobbers)
bd9c7e23 13866 {
61f0ccff
RE		 13867 arm_ccfsm_state = 2;
13868 this_insn = next_nonnote_insn (this_insn);
bd9c7e23
RE		 13869 }
13870 else
61f0ccff
RE		 13871 arm_ccfsm_state = 1;
13872 succeed = TRUE;
bd9c7e23 13873 }
61f0ccff
RE		 13874 else
13875 fail = TRUE;
ff9940b0 13876 break;
2b835d68 13877
cce8749e
CH		 13878 case JUMP_INSN:
13879 /* If this is an unconditional branch to the same label, succeed.
13880 If it is to another label, do nothing. If it is conditional,
13881 fail. */
e32bac5b
RE		 13882 /* XXX Probably, the tests for SET and the PC are
13883 unnecessary. */
cce8749e 13884
ed4c4348 13885 scanbody = PATTERN (this_insn);
ff9940b0
RE		 13886 if (GET_CODE (scanbody) == SET
13887 && GET_CODE (SET_DEST (scanbody)) == PC)
cce8749e
CH		 13888 {
13889 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
13890 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
13891 {
13892 arm_ccfsm_state = 2;
13893 succeed = TRUE;
13894 }
13895 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
13896 fail = TRUE;
13897 }
112cdef5 13898 /* Fail if a conditional return is undesirable (e.g. on a
b36ba79f
RE		 13899 StrongARM), but still allow this if optimizing for size. */
13900 else if (GET_CODE (scanbody) == RETURN
a72d4945 13901 && !use_return_insn (TRUE, NULL)
5895f793 13902 && !optimize_size)
b36ba79f 13903 fail = TRUE;
ff9940b0
RE		 13904 else if (GET_CODE (scanbody) == RETURN
13905 && seeking_return)
13906 {
13907 arm_ccfsm_state = 2;
13908 succeed = TRUE;
13909 }
13910 else if (GET_CODE (scanbody) == PARALLEL)
13911 {
13912 switch (get_attr_conds (this_insn))
13913 {
13914 case CONDS_NOCOND:
13915 break;
13916 default:
13917 fail = TRUE;
13918 break;
13919 }
13920 }
4e67550b 13921 else
112cdef5 13922 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
4e67550b 13923
cce8749e
CH		 13924 break;
13925
13926 case INSN:
ff9940b0
RE		 13927 /* Instructions using or affecting the condition codes make it
13928 fail. */
ed4c4348 13929 scanbody = PATTERN (this_insn);
5895f793
RE		 13930 if (!(GET_CODE (scanbody) == SET
13931 || GET_CODE (scanbody) == PARALLEL)
74641843 13932 || get_attr_conds (this_insn) != CONDS_NOCOND)
cce8749e 13933 fail = TRUE;
9b6b54e2
NC		 13934
13935 /* A conditional cirrus instruction must be followed by
13936 a non Cirrus instruction. However, since we
13937 conditionalize instructions in this function and by
13938 the time we get here we can't add instructions
13939 (nops), because shorten_branches() has already been
13940 called, we will disable conditionalizing Cirrus
13941 instructions to be safe. */
13942 if (GET_CODE (scanbody) != USE
13943 && GET_CODE (scanbody) != CLOBBER
f0375c66 13944 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
9b6b54e2 13945 fail = TRUE;
cce8749e
CH		 13946 break;
13947
13948 default:
13949 break;
13950 }
13951 }
13952 if (succeed)
13953 {
ff9940b0 13954 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
cce8749e 13955 arm_target_label = CODE_LABEL_NUMBER (label);
e6d29d15 13956 else
ff9940b0 13957 {
e6d29d15 13958 gcc_assert (seeking_return || arm_ccfsm_state == 2);
e0b92319 13959
ff9940b0
RE		 13960 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
13961 {
13962 this_insn = next_nonnote_insn (this_insn);
e6d29d15
NS		 13963 gcc_assert (!this_insn
13964 || (GET_CODE (this_insn) != BARRIER
13965 && GET_CODE (this_insn) != CODE_LABEL));
ff9940b0
RE		 13966 }
13967 if (!this_insn)
13968 {
d6b4baa4 13969 /* Oh, dear! we ran off the end.. give up. */
5b3e6663 13970 extract_constrain_insn_cached (insn);
ff9940b0 13971 arm_ccfsm_state = 0;
abaa26e5 13972 arm_target_insn = NULL;
ff9940b0
RE		 13973 return;
13974 }
13975 arm_target_insn = this_insn;
13976 }
ff9940b0
RE		 13977 if (jump_clobbers)
13978 {
e6d29d15 13979 gcc_assert (!reverse);
f676971a 13980 arm_current_cc =
ff9940b0
RE		 13981 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
13982 0), 0), 1));
13983 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
13984 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13985 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
13986 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13987 }
13988 else
13989 {
13990 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
13991 what it was. */
13992 if (!reverse)
13993 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
13994 0));
13995 }
cce8749e 13996
cce8749e
CH		 13997 if (reverse || then_not_else)
13998 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
13999 }
f676971a 14000
1ccbefce 14001 /* Restore recog_data (getting the attributes of other insns can
ff9940b0 14002 destroy this array, but final.c assumes that it remains intact
5b3e6663
PB		 14003 across this call. */
14004 extract_constrain_insn_cached (insn);
14005 }
14006}
14007
14008/* Output IT instructions. */
14009void
14010thumb2_asm_output_opcode (FILE * stream)
14011{
14012 char buff[5];
14013 int n;
14014
14015 if (arm_condexec_mask)
14016 {
14017 for (n = 0; n < arm_condexec_masklen; n++)
14018 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
14019 buff[n] = 0;
14020 asm_fprintf(stream, "i%s\t%s\n\t", buff,
14021 arm_condition_codes[arm_current_cc]);
14022 arm_condexec_mask = 0;
cce8749e 14023 }
f3bb6135 14024}
cce8749e 14025
4b02997f 14026/* Returns true if REGNO is a valid register
21b5653c 14027 for holding a quantity of type MODE. */
4b02997f 14028int
e32bac5b 14029arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
4b02997f
NC		 14030{
14031 if (GET_MODE_CLASS (mode) == MODE_CC)
a6a5de04
RE		 14032 return (regno == CC_REGNUM
14033 || (TARGET_HARD_FLOAT && TARGET_VFP
14034 && regno == VFPCC_REGNUM));
f676971a 14035
5b3e6663 14036 if (TARGET_THUMB1)
4b02997f
NC		 14037 /* For the Thumb we only allow values bigger than SImode in
14038 registers 0 - 6, so that there is always a second low
14039 register available to hold the upper part of the value.
14040 We probably we ought to ensure that the register is the
14041 start of an even numbered register pair. */
e9d7b180 14042 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
4b02997f 14043
a6a5de04
RE		 14044 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
14045 && IS_CIRRUS_REGNUM (regno))
9b6b54e2
NC		 14046 /* We have outlawed SI values in Cirrus registers because they
14047 reside in the lower 32 bits, but SF values reside in the
14048 upper 32 bits. This causes gcc all sorts of grief. We can't
14049 even split the registers into pairs because Cirrus SI values
14050 get sign extended to 64bits-- aldyh. */
14051 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
14052
a6a5de04
RE		 14053 if (TARGET_HARD_FLOAT && TARGET_VFP
14054 && IS_VFP_REGNUM (regno))
9b66ebb1
PB		 14055 {
14056 if (mode == SFmode || mode == SImode)
f1adb0a9 14057 return VFP_REGNO_OK_FOR_SINGLE (regno);
9b66ebb1 14058
9b66ebb1 14059 if (mode == DFmode)
f1adb0a9 14060 return VFP_REGNO_OK_FOR_DOUBLE (regno);
88f77cba
JB		 14061
14062 if (TARGET_NEON)
14063 return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
14064 || (VALID_NEON_QREG_MODE (mode)
14065 && NEON_REGNO_OK_FOR_QUAD (regno))
14066 || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2))
14067 || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3))
14068 || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4))
14069 || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6))
14070 || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8));
14071
9b66ebb1
PB		 14072 return FALSE;
14073 }
14074
a6a5de04
RE		 14075 if (TARGET_REALLY_IWMMXT)
14076 {
14077 if (IS_IWMMXT_GR_REGNUM (regno))
14078 return mode == SImode;
5a9335ef 14079
a6a5de04
RE		 14080 if (IS_IWMMXT_REGNUM (regno))
14081 return VALID_IWMMXT_REG_MODE (mode);
14082 }
14083
fdd695fd
PB		 14084 /* We allow any value to be stored in the general registers.
14085 Restrict doubleword quantities to even register pairs so that we can
88f77cba
JB		 14086 use ldrd. Do not allow Neon structure opaque modes in general registers;
14087 they would use too many. */
4b02997f 14088 if (regno <= LAST_ARM_REGNUM)
88f77cba
JB		 14089 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
14090 && !VALID_NEON_STRUCT_MODE (mode);
4b02997f 14091
a6a5de04 14092 if (regno == FRAME_POINTER_REGNUM
4b02997f
NC		 14093 || regno == ARG_POINTER_REGNUM)
14094 /* We only allow integers in the fake hard registers. */
14095 return GET_MODE_CLASS (mode) == MODE_INT;
14096
3b684012 14097 /* The only registers left are the FPA registers
4b02997f 14098 which we only allow to hold FP values. */
a6a5de04
RE		 14099 return (TARGET_HARD_FLOAT && TARGET_FPA
14100 && GET_MODE_CLASS (mode) == MODE_FLOAT
14101 && regno >= FIRST_FPA_REGNUM
14102 && regno <= LAST_FPA_REGNUM);
4b02997f
NC		 14103}
14104
5b3e6663
PB		 14105/* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
14106 not used in arm mode. */
d5b7b3ae 14107int
e32bac5b 14108arm_regno_class (int regno)
d5b7b3ae 14109{
5b3e6663 14110 if (TARGET_THUMB1)
d5b7b3ae
RE		 14111 {
14112 if (regno == STACK_POINTER_REGNUM)
14113 return STACK_REG;
14114 if (regno == CC_REGNUM)
14115 return CC_REG;
14116 if (regno < 8)
14117 return LO_REGS;
14118 return HI_REGS;
14119 }
14120
5b3e6663
PB		 14121 if (TARGET_THUMB2 && regno < 8)
14122 return LO_REGS;
14123
d5b7b3ae
RE		 14124 if ( regno <= LAST_ARM_REGNUM
14125 || regno == FRAME_POINTER_REGNUM
14126 || regno == ARG_POINTER_REGNUM)
5b3e6663 14127 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
f676971a 14128
9b66ebb1 14129 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
5b3e6663 14130 return TARGET_THUMB2 ? CC_REG : NO_REGS;
d5b7b3ae 14131
9b6b54e2
NC		 14132 if (IS_CIRRUS_REGNUM (regno))
14133 return CIRRUS_REGS;
14134
9b66ebb1 14135 if (IS_VFP_REGNUM (regno))
f1adb0a9
JB		 14136 {
14137 if (regno <= D7_VFP_REGNUM)
14138 return VFP_D0_D7_REGS;
14139 else if (regno <= LAST_LO_VFP_REGNUM)
14140 return VFP_LO_REGS;
14141 else
14142 return VFP_HI_REGS;
14143 }
9b66ebb1 14144
5a9335ef
NC		 14145 if (IS_IWMMXT_REGNUM (regno))
14146 return IWMMXT_REGS;
14147
e99faaaa
ILT		 14148 if (IS_IWMMXT_GR_REGNUM (regno))
14149 return IWMMXT_GR_REGS;
14150
3b684012 14151 return FPA_REGS;
d5b7b3ae
RE		 14152}
14153
14154/* Handle a special case when computing the offset
14155 of an argument from the frame pointer. */
14156int
e32bac5b 14157arm_debugger_arg_offset (int value, rtx addr)
d5b7b3ae
RE		 14158{
14159 rtx insn;
14160
14161 /* We are only interested if dbxout_parms() failed to compute the offset. */
14162 if (value != 0)
14163 return 0;
14164
14165 /* We can only cope with the case where the address is held in a register. */
14166 if (GET_CODE (addr) != REG)
14167 return 0;
14168
14169 /* If we are using the frame pointer to point at the argument, then
14170 an offset of 0 is correct. */
cd2b33d0 14171 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
d5b7b3ae 14172 return 0;
f676971a 14173
d5b7b3ae
RE		 14174 /* If we are using the stack pointer to point at the
14175 argument, then an offset of 0 is correct. */
5b3e6663 14176 /* ??? Check this is consistent with thumb2 frame layout. */
5895f793 14177 if ((TARGET_THUMB || !frame_pointer_needed)
d5b7b3ae
RE		 14178 && REGNO (addr) == SP_REGNUM)
14179 return 0;
f676971a 14180
d5b7b3ae
RE		 14181 /* Oh dear. The argument is pointed to by a register rather
14182 than being held in a register, or being stored at a known
14183 offset from the frame pointer. Since GDB only understands
14184 those two kinds of argument we must translate the address
14185 held in the register into an offset from the frame pointer.
14186 We do this by searching through the insns for the function
14187 looking to see where this register gets its value. If the
4912a07c 14188 register is initialized from the frame pointer plus an offset
d5b7b3ae 14189 then we are in luck and we can continue, otherwise we give up.
f676971a 14190
d5b7b3ae
RE		 14191 This code is exercised by producing debugging information
14192 for a function with arguments like this:
f676971a 14193
d5b7b3ae 14194 double func (double a, double b, int c, double d) {return d;}
f676971a 14195
d5b7b3ae
RE		 14196 Without this code the stab for parameter 'd' will be set to
14197 an offset of 0 from the frame pointer, rather than 8. */
14198
14199 /* The if() statement says:
14200
14201 If the insn is a normal instruction
14202 and if the insn is setting the value in a register
14203 and if the register being set is the register holding the address of the argument
14204 and if the address is computing by an addition
14205 that involves adding to a register
14206 which is the frame pointer
14207 a constant integer
14208
d6b4baa4 14209 then... */
f676971a 14210
d5b7b3ae
RE		 14211 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14212 {
f676971a 14213 if ( GET_CODE (insn) == INSN
d5b7b3ae
RE		 14214 && GET_CODE (PATTERN (insn)) == SET
14215 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
14216 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
14217 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
cd2b33d0 14218 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
d5b7b3ae
RE		 14219 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
14220 )
14221 {
14222 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
f676971a 14223
d5b7b3ae
RE		 14224 break;
14225 }
14226 }
f676971a 14227
d5b7b3ae
RE		 14228 if (value == 0)
14229 {
14230 debug_rtx (addr);
d4ee4d25 14231 warning (0, "unable to compute real location of stacked parameter");
d5b7b3ae
RE		 14232 value = 8; /* XXX magic hack */
14233 }
14234
14235 return value;
14236}
d5b7b3ae 14237\f
5a9335ef
NC		 14238#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
14239 do \
14240 { \
14241 if ((MASK) & insn_flags) \
c79efc4d
RÁE		 14242 add_builtin_function ((NAME), (TYPE), (CODE), \
14243 BUILT_IN_MD, NULL, NULL_TREE); \
5a9335ef
NC		 14244 } \
14245 while (0)
14246
14247struct builtin_description
14248{
14249 const unsigned int mask;
14250 const enum insn_code icode;
14251 const char * const name;
14252 const enum arm_builtins code;
14253 const enum rtx_code comparison;
14254 const unsigned int flag;
14255};
14256
14257static const struct builtin_description bdesc_2arg[] =
14258{
14259#define IWMMXT_BUILTIN(code, string, builtin) \
14260 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
14261 ARM_BUILTIN_##builtin, 0, 0 },
14262
14263 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
14264 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
14265 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
14266 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
14267 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
14268 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
14269 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
14270 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
14271 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
14272 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
14273 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
14274 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
14275 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
14276 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
14277 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
14278 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
14279 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
14280 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
14281 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
f07a6b21
BE		 14282 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
14283 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
5a9335ef
NC		 14284 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
14285 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
14286 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
14287 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
14288 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
14289 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
14290 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
14291 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
14292 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
14293 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
14294 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
14295 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
14296 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
14297 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
14298 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
14299 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
14300 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
14301 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
14302 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
14303 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
14304 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
14305 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
14306 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
14307 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
14308 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
14309 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
14310 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
14311 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
14312 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
14313 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
14314 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
14315 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
14316 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
14317 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
14318 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
14319 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
14320 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
14321
14322#define IWMMXT_BUILTIN2(code, builtin) \
14323 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
f676971a 14324
5a9335ef
NC		 14325 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
14326 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
14327 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
14328 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
14329 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
14330 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
14331 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
88f77cba 14332 IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI)
5a9335ef 14333 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
88f77cba 14334 IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI)
5a9335ef
NC		 14335 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
14336 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
14337 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
88f77cba 14338 IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI)
5a9335ef 14339 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
88f77cba 14340 IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI)
5a9335ef 14341 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
9b66ebb1 14342 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
5a9335ef 14343 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
88f77cba 14344 IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI)
5a9335ef 14345 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
88f77cba 14346 IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI)
5a9335ef 14347 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
9b66ebb1 14348 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
5a9335ef
NC		 14349 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
14350 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
14351 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
14352 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
14353 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
14354 IWMMXT_BUILTIN2 (rordi3, WRORDI)
14355 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
14356 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
14357};
14358
14359static const struct builtin_description bdesc_1arg[] =
14360{
14361 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
14362 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
14363 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
14364 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
14365 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
14366 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
14367 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
14368 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
14369 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
14370 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
14371 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
14372 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
14373 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
14374 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
14375 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
14376 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
14377 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
14378 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
14379};
14380
14381/* Set up all the iWMMXt builtins. This is
14382 not called if TARGET_IWMMXT is zero. */
14383
14384static void
14385arm_init_iwmmxt_builtins (void)
14386{
14387 const struct builtin_description * d;
14388 size_t i;
14389 tree endlink = void_list_node;
14390
4a5eab38
PB		 14391 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
14392 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
14393 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
14394
5a9335ef
NC		 14395 tree int_ftype_int
14396 = build_function_type (integer_type_node,
14397 tree_cons (NULL_TREE, integer_type_node, endlink));
14398 tree v8qi_ftype_v8qi_v8qi_int
14399 = build_function_type (V8QI_type_node,
14400 tree_cons (NULL_TREE, V8QI_type_node,
14401 tree_cons (NULL_TREE, V8QI_type_node,
14402 tree_cons (NULL_TREE,
14403 integer_type_node,
14404 endlink))));
14405 tree v4hi_ftype_v4hi_int
14406 = build_function_type (V4HI_type_node,
14407 tree_cons (NULL_TREE, V4HI_type_node,
14408 tree_cons (NULL_TREE, integer_type_node,
14409 endlink)));
14410 tree v2si_ftype_v2si_int
14411 = build_function_type (V2SI_type_node,
14412 tree_cons (NULL_TREE, V2SI_type_node,
14413 tree_cons (NULL_TREE, integer_type_node,
14414 endlink)));
14415 tree v2si_ftype_di_di
14416 = build_function_type (V2SI_type_node,
14417 tree_cons (NULL_TREE, long_long_integer_type_node,
14418 tree_cons (NULL_TREE, long_long_integer_type_node,
14419 endlink)));
14420 tree di_ftype_di_int
14421 = build_function_type (long_long_integer_type_node,
14422 tree_cons (NULL_TREE, long_long_integer_type_node,
14423 tree_cons (NULL_TREE, integer_type_node,
14424 endlink)));
14425 tree di_ftype_di_int_int
14426 = build_function_type (long_long_integer_type_node,
14427 tree_cons (NULL_TREE, long_long_integer_type_node,
14428 tree_cons (NULL_TREE, integer_type_node,
14429 tree_cons (NULL_TREE,
14430 integer_type_node,
14431 endlink))));
14432 tree int_ftype_v8qi
14433 = build_function_type (integer_type_node,
14434 tree_cons (NULL_TREE, V8QI_type_node,
14435 endlink));
14436 tree int_ftype_v4hi
14437 = build_function_type (integer_type_node,
14438 tree_cons (NULL_TREE, V4HI_type_node,
14439 endlink));
14440 tree int_ftype_v2si
14441 = build_function_type (integer_type_node,
14442 tree_cons (NULL_TREE, V2SI_type_node,
14443 endlink));
14444 tree int_ftype_v8qi_int
14445 = build_function_type (integer_type_node,
14446 tree_cons (NULL_TREE, V8QI_type_node,
14447 tree_cons (NULL_TREE, integer_type_node,
14448 endlink)));
14449 tree int_ftype_v4hi_int
14450 = build_function_type (integer_type_node,
14451 tree_cons (NULL_TREE, V4HI_type_node,
14452 tree_cons (NULL_TREE, integer_type_node,
14453 endlink)));
14454 tree int_ftype_v2si_int
14455 = build_function_type (integer_type_node,
14456 tree_cons (NULL_TREE, V2SI_type_node,
14457 tree_cons (NULL_TREE, integer_type_node,
14458 endlink)));
14459 tree v8qi_ftype_v8qi_int_int
14460 = build_function_type (V8QI_type_node,
14461 tree_cons (NULL_TREE, V8QI_type_node,
14462 tree_cons (NULL_TREE, integer_type_node,
14463 tree_cons (NULL_TREE,
14464 integer_type_node,
14465 endlink))));
14466 tree v4hi_ftype_v4hi_int_int
14467 = build_function_type (V4HI_type_node,
14468 tree_cons (NULL_TREE, V4HI_type_node,
14469 tree_cons (NULL_TREE, integer_type_node,
14470 tree_cons (NULL_TREE,
14471 integer_type_node,
14472 endlink))));
14473 tree v2si_ftype_v2si_int_int
14474 = build_function_type (V2SI_type_node,
14475 tree_cons (NULL_TREE, V2SI_type_node,
14476 tree_cons (NULL_TREE, integer_type_node,
14477 tree_cons (NULL_TREE,
14478 integer_type_node,
14479 endlink))));
14480 /* Miscellaneous. */
14481 tree v8qi_ftype_v4hi_v4hi
14482 = build_function_type (V8QI_type_node,
14483 tree_cons (NULL_TREE, V4HI_type_node,
14484 tree_cons (NULL_TREE, V4HI_type_node,
14485 endlink)));
14486 tree v4hi_ftype_v2si_v2si
14487 = build_function_type (V4HI_type_node,
14488 tree_cons (NULL_TREE, V2SI_type_node,
14489 tree_cons (NULL_TREE, V2SI_type_node,
14490 endlink)));
14491 tree v2si_ftype_v4hi_v4hi
14492 = build_function_type (V2SI_type_node,
14493 tree_cons (NULL_TREE, V4HI_type_node,
14494 tree_cons (NULL_TREE, V4HI_type_node,
14495 endlink)));
14496 tree v2si_ftype_v8qi_v8qi
14497 = build_function_type (V2SI_type_node,
14498 tree_cons (NULL_TREE, V8QI_type_node,
14499 tree_cons (NULL_TREE, V8QI_type_node,
14500 endlink)));
14501 tree v4hi_ftype_v4hi_di
14502 = build_function_type (V4HI_type_node,
14503 tree_cons (NULL_TREE, V4HI_type_node,
14504 tree_cons (NULL_TREE,
14505 long_long_integer_type_node,
14506 endlink)));
14507 tree v2si_ftype_v2si_di
14508 = build_function_type (V2SI_type_node,
14509 tree_cons (NULL_TREE, V2SI_type_node,
14510 tree_cons (NULL_TREE,
14511 long_long_integer_type_node,
14512 endlink)));
14513 tree void_ftype_int_int
14514 = build_function_type (void_type_node,
14515 tree_cons (NULL_TREE, integer_type_node,
14516 tree_cons (NULL_TREE, integer_type_node,
14517 endlink)));
14518 tree di_ftype_void
14519 = build_function_type (long_long_unsigned_type_node, endlink);
14520 tree di_ftype_v8qi
14521 = build_function_type (long_long_integer_type_node,
14522 tree_cons (NULL_TREE, V8QI_type_node,
14523 endlink));
14524 tree di_ftype_v4hi
14525 = build_function_type (long_long_integer_type_node,
14526 tree_cons (NULL_TREE, V4HI_type_node,
14527 endlink));
14528 tree di_ftype_v2si
14529 = build_function_type (long_long_integer_type_node,
14530 tree_cons (NULL_TREE, V2SI_type_node,
14531 endlink));
14532 tree v2si_ftype_v4hi
14533 = build_function_type (V2SI_type_node,
14534 tree_cons (NULL_TREE, V4HI_type_node,
14535 endlink));
14536 tree v4hi_ftype_v8qi
14537 = build_function_type (V4HI_type_node,
14538 tree_cons (NULL_TREE, V8QI_type_node,
14539 endlink));
14540
14541 tree di_ftype_di_v4hi_v4hi
14542 = build_function_type (long_long_unsigned_type_node,
14543 tree_cons (NULL_TREE,
14544 long_long_unsigned_type_node,
14545 tree_cons (NULL_TREE, V4HI_type_node,
14546 tree_cons (NULL_TREE,
14547 V4HI_type_node,
14548 endlink))));
14549
14550 tree di_ftype_v4hi_v4hi
14551 = build_function_type (long_long_unsigned_type_node,
14552 tree_cons (NULL_TREE, V4HI_type_node,
14553 tree_cons (NULL_TREE, V4HI_type_node,
14554 endlink)));
14555
14556 /* Normal vector binops. */
14557 tree v8qi_ftype_v8qi_v8qi
14558 = build_function_type (V8QI_type_node,
14559 tree_cons (NULL_TREE, V8QI_type_node,
14560 tree_cons (NULL_TREE, V8QI_type_node,
14561 endlink)));
14562 tree v4hi_ftype_v4hi_v4hi
14563 = build_function_type (V4HI_type_node,
14564 tree_cons (NULL_TREE, V4HI_type_node,
14565 tree_cons (NULL_TREE, V4HI_type_node,
14566 endlink)));
14567 tree v2si_ftype_v2si_v2si
14568 = build_function_type (V2SI_type_node,
14569 tree_cons (NULL_TREE, V2SI_type_node,
14570 tree_cons (NULL_TREE, V2SI_type_node,
14571 endlink)));
14572 tree di_ftype_di_di
14573 = build_function_type (long_long_unsigned_type_node,
14574 tree_cons (NULL_TREE, long_long_unsigned_type_node,
14575 tree_cons (NULL_TREE,
14576 long_long_unsigned_type_node,
14577 endlink)));
14578
14579 /* Add all builtins that are more or less simple operations on two
14580 operands. */
e97a46ce 14581 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
5a9335ef
NC		 14582 {
14583 /* Use one of the operands; the target can have a different mode for
14584 mask-generating compares. */
14585 enum machine_mode mode;
14586 tree type;
14587
14588 if (d->name == 0)
14589 continue;
14590
14591 mode = insn_data[d->icode].operand[1].mode;
14592
14593 switch (mode)
14594 {
14595 case V8QImode:
14596 type = v8qi_ftype_v8qi_v8qi;
14597 break;
14598 case V4HImode:
14599 type = v4hi_ftype_v4hi_v4hi;
14600 break;
14601 case V2SImode:
14602 type = v2si_ftype_v2si_v2si;
14603 break;
14604 case DImode:
14605 type = di_ftype_di_di;
14606 break;
14607
14608 default:
e6d29d15 14609 gcc_unreachable ();
5a9335ef
NC		 14610 }
14611
14612 def_mbuiltin (d->mask, d->name, type, d->code);
14613 }
14614
14615 /* Add the remaining MMX insns with somewhat more complicated types. */
14616 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
14617 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
14618 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
14619
14620 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
14621 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
14622 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
14623 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
14624 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
14625 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
14626
14627 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
14628 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
14629 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
14630 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
14631 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
14632 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
14633
14634 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
14635 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
14636 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
14637 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
14638 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
14639 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
14640
14641 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
14642 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
14643 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
14644 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
14645 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
14646 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
14647
14648 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
14649
14650 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
14651 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
14652 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
14653 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
14654
14655 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
14656 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
14657 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
14658 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
14659 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
14660 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
14661 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
14662 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
14663 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
14664
14665 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
14666 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
14667 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
14668
14669 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
14670 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
14671 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
14672
14673 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
14674 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
14675 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
14676 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
14677 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
14678 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
14679
14680 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
14681 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
14682 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
14683 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
14684 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
14685 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
14686 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
14687 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
14688 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
14689 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
14690 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
14691 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
14692
14693 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
14694 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
14695 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
14696 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
14697
14698 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
14699 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
14700 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
14701 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
14702 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
14703 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
14704 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
14705}
14706
d3585b76
DJ		 14707static void
14708arm_init_tls_builtins (void)
14709{
ebfe65a3 14710 tree ftype, decl;
d3585b76
DJ		 14711
14712 ftype = build_function_type (ptr_type_node, void_list_node);
ebfe65a3
JJ		 14713 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
14714 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
14715 NULL, NULL_TREE);
14716 TREE_NOTHROW (decl) = 1;
14717 TREE_READONLY (decl) = 1;
d3585b76
DJ		 14718}
14719
88f77cba
JB		 14720typedef enum {
14721 T_V8QI = 0x0001,
14722 T_V4HI = 0x0002,
14723 T_V2SI = 0x0004,
14724 T_V2SF = 0x0008,
14725 T_DI = 0x0010,
14726 T_V16QI = 0x0020,
14727 T_V8HI = 0x0040,
14728 T_V4SI = 0x0080,
14729 T_V4SF = 0x0100,
14730 T_V2DI = 0x0200,
14731 T_TI = 0x0400,
14732 T_EI = 0x0800,
14733 T_OI = 0x1000
14734} neon_builtin_type_bits;
14735
14736#define v8qi_UP T_V8QI
14737#define v4hi_UP T_V4HI
14738#define v2si_UP T_V2SI
14739#define v2sf_UP T_V2SF
14740#define di_UP T_DI
14741#define v16qi_UP T_V16QI
14742#define v8hi_UP T_V8HI
14743#define v4si_UP T_V4SI
14744#define v4sf_UP T_V4SF
14745#define v2di_UP T_V2DI
14746#define ti_UP T_TI
14747#define ei_UP T_EI
14748#define oi_UP T_OI
14749
14750#define UP(X) X##_UP
14751
14752#define T_MAX 13
14753
14754typedef enum {
14755 NEON_BINOP,
14756 NEON_TERNOP,
14757 NEON_UNOP,
14758 NEON_GETLANE,
14759 NEON_SETLANE,
14760 NEON_CREATE,
14761 NEON_DUP,
14762 NEON_DUPLANE,
14763 NEON_COMBINE,
14764 NEON_SPLIT,
14765 NEON_LANEMUL,
14766 NEON_LANEMULL,
14767 NEON_LANEMULH,
14768 NEON_LANEMAC,
14769 NEON_SCALARMUL,
14770 NEON_SCALARMULL,
14771 NEON_SCALARMULH,
14772 NEON_SCALARMAC,
14773 NEON_CONVERT,
14774 NEON_FIXCONV,
14775 NEON_SELECT,
14776 NEON_RESULTPAIR,
14777 NEON_REINTERP,
14778 NEON_VTBL,
14779 NEON_VTBX,
14780 NEON_LOAD1,
14781 NEON_LOAD1LANE,
14782 NEON_STORE1,
14783 NEON_STORE1LANE,
14784 NEON_LOADSTRUCT,
14785 NEON_LOADSTRUCTLANE,
14786 NEON_STORESTRUCT,
14787 NEON_STORESTRUCTLANE,
14788 NEON_LOGICBINOP,
14789 NEON_SHIFTINSERT,
14790 NEON_SHIFTIMM,
14791 NEON_SHIFTACC
14792} neon_itype;
14793
14794typedef struct {
14795 const char *name;
14796 const neon_itype itype;
14797 const neon_builtin_type_bits bits;
14798 const enum insn_code codes[T_MAX];
14799 const unsigned int num_vars;
14800 unsigned int base_fcode;
14801} neon_builtin_datum;
14802
14803#define CF(N,X) CODE_FOR_neon_##N##X
14804
14805#define VAR1(T, N, A) \
14806 #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0
14807#define VAR2(T, N, A, B) \
14808 #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0
14809#define VAR3(T, N, A, B, C) \
14810 #N, NEON_##T, UP (A) | UP (B) | UP (C), \
14811 { CF (N, A), CF (N, B), CF (N, C) }, 3, 0
14812#define VAR4(T, N, A, B, C, D) \
14813 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \
14814 { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0
14815#define VAR5(T, N, A, B, C, D, E) \
14816 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \
14817 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0
14818#define VAR6(T, N, A, B, C, D, E, F) \
14819 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \
14820 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0
14821#define VAR7(T, N, A, B, C, D, E, F, G) \
14822 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \
14823 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14824 CF (N, G) }, 7, 0
14825#define VAR8(T, N, A, B, C, D, E, F, G, H) \
14826 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14827 | UP (H), \
14828 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14829 CF (N, G), CF (N, H) }, 8, 0
14830#define VAR9(T, N, A, B, C, D, E, F, G, H, I) \
14831 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14832 | UP (H) | UP (I), \
14833 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14834 CF (N, G), CF (N, H), CF (N, I) }, 9, 0
14835#define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \
14836 #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \
14837 | UP (H) | UP (I) | UP (J), \
14838 { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \
14839 CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0
14840
14841/* The mode entries in the following table correspond to the "key" type of the
14842 instruction variant, i.e. equivalent to that which would be specified after
14843 the assembler mnemonic, which usually refers to the last vector operand.
14844 (Signed/unsigned/polynomial types are not differentiated between though, and
14845 are all mapped onto the same mode for a given element size.) The modes
14846 listed per instruction should be the same as those defined for that
14847 instruction's pattern in neon.md.
14848 WARNING: Variants should be listed in the same increasing order as
14849 neon_builtin_type_bits. */
14850
14851static neon_builtin_datum neon_builtin_data[] =
14852{
14853 { VAR10 (BINOP, vadd,
14854 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14855 { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) },
14856 { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) },
14857 { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14858 { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14859 { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) },
14860 { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14861 { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14862 { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) },
14863 { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14864 { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) },
14865 { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) },
14866 { VAR2 (TERNOP, vqdmlal, v4hi, v2si) },
14867 { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) },
14868 { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) },
14869 { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) },
14870 { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) },
14871 { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) },
14872 { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) },
14873 { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) },
14874 { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) },
14875 { VAR2 (BINOP, vqdmull, v4hi, v2si) },
14876 { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14877 { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14878 { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14879 { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) },
14880 { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) },
14881 { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) },
14882 { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14883 { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14884 { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14885 { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) },
14886 { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14887 { VAR10 (BINOP, vsub,
14888 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14889 { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) },
14890 { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) },
14891 { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14892 { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14893 { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) },
14894 { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14895 { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14896 { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14897 { VAR2 (BINOP, vcage, v2sf, v4sf) },
14898 { VAR2 (BINOP, vcagt, v2sf, v4sf) },
14899 { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14900 { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14901 { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) },
14902 { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14903 { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) },
14904 { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14905 { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14906 { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) },
14907 { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14908 { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14909 { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) },
14910 { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) },
14911 { VAR2 (BINOP, vrecps, v2sf, v4sf) },
14912 { VAR2 (BINOP, vrsqrts, v2sf, v4sf) },
14913 { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14914 { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) },
14915 { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14916 { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14917 { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14918 { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14919 { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14920 { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14921 { VAR2 (UNOP, vcnt, v8qi, v16qi) },
14922 { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) },
14923 { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) },
14924 { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) },
14925 /* FIXME: vget_lane supports more variants than this! */
14926 { VAR10 (GETLANE, vget_lane,
14927 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14928 { VAR10 (SETLANE, vset_lane,
14929 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14930 { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) },
14931 { VAR10 (DUP, vdup_n,
14932 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14933 { VAR10 (DUPLANE, vdup_lane,
14934 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14935 { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) },
14936 { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) },
14937 { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) },
14938 { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) },
14939 { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) },
14940 { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) },
14941 { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) },
14942 { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14943 { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14944 { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) },
14945 { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) },
14946 { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14947 { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) },
14948 { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) },
14949 { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14950 { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14951 { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) },
14952 { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) },
14953 { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
14954 { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) },
14955 { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) },
14956 { VAR10 (BINOP, vext,
14957 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14958 { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14959 { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) },
14960 { VAR2 (UNOP, vrev16, v8qi, v16qi) },
14961 { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) },
14962 { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) },
14963 { VAR10 (SELECT, vbsl,
14964 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14965 { VAR1 (VTBL, vtbl1, v8qi) },
14966 { VAR1 (VTBL, vtbl2, v8qi) },
14967 { VAR1 (VTBL, vtbl3, v8qi) },
14968 { VAR1 (VTBL, vtbl4, v8qi) },
14969 { VAR1 (VTBX, vtbx1, v8qi) },
14970 { VAR1 (VTBX, vtbx2, v8qi) },
14971 { VAR1 (VTBX, vtbx3, v8qi) },
14972 { VAR1 (VTBX, vtbx4, v8qi) },
14973 { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14974 { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14975 { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) },
14976 { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) },
14977 { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) },
14978 { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) },
14979 { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) },
14980 { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) },
14981 { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) },
14982 { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) },
14983 { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) },
14984 { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) },
14985 { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) },
14986 { VAR10 (LOAD1, vld1,
14987 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14988 { VAR10 (LOAD1LANE, vld1_lane,
14989 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14990 { VAR10 (LOAD1, vld1_dup,
14991 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14992 { VAR10 (STORE1, vst1,
14993 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14994 { VAR10 (STORE1LANE, vst1_lane,
14995 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
14996 { VAR9 (LOADSTRUCT,
14997 vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
14998 { VAR7 (LOADSTRUCTLANE, vld2_lane,
14999 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15000 { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) },
15001 { VAR9 (STORESTRUCT, vst2,
15002 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
15003 { VAR7 (STORESTRUCTLANE, vst2_lane,
15004 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15005 { VAR9 (LOADSTRUCT,
15006 vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
15007 { VAR7 (LOADSTRUCTLANE, vld3_lane,
15008 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15009 { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) },
15010 { VAR9 (STORESTRUCT, vst3,
15011 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
15012 { VAR7 (STORESTRUCTLANE, vst3_lane,
15013 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15014 { VAR9 (LOADSTRUCT, vld4,
15015 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
15016 { VAR7 (LOADSTRUCTLANE, vld4_lane,
15017 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15018 { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) },
15019 { VAR9 (STORESTRUCT, vst4,
15020 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) },
15021 { VAR7 (STORESTRUCTLANE, vst4_lane,
15022 v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) },
15023 { VAR10 (LOGICBINOP, vand,
15024 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
15025 { VAR10 (LOGICBINOP, vorr,
15026 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
15027 { VAR10 (BINOP, veor,
15028 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
15029 { VAR10 (LOGICBINOP, vbic,
15030 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) },
15031 { VAR10 (LOGICBINOP, vorn,
15032 v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }
15033};
15034
15035#undef CF
15036#undef VAR1
15037#undef VAR2
15038#undef VAR3
15039#undef VAR4
15040#undef VAR5
15041#undef VAR6
15042#undef VAR7
15043#undef VAR8
15044#undef VAR9
15045#undef VAR10
15046
15047static void
15048arm_init_neon_builtins (void)
15049{
15050 unsigned int i, fcode = ARM_BUILTIN_NEON_BASE;
15051
af06585a
JM		 15052 tree neon_intQI_type_node;
15053 tree neon_intHI_type_node;
15054 tree neon_polyQI_type_node;
15055 tree neon_polyHI_type_node;
15056 tree neon_intSI_type_node;
15057 tree neon_intDI_type_node;
15058 tree neon_float_type_node;
15059
15060 tree intQI_pointer_node;
15061 tree intHI_pointer_node;
15062 tree intSI_pointer_node;
15063 tree intDI_pointer_node;
15064 tree float_pointer_node;
15065
15066 tree const_intQI_node;
15067 tree const_intHI_node;
15068 tree const_intSI_node;
15069 tree const_intDI_node;
15070 tree const_float_node;
15071
15072 tree const_intQI_pointer_node;
15073 tree const_intHI_pointer_node;
15074 tree const_intSI_pointer_node;
15075 tree const_intDI_pointer_node;
15076 tree const_float_pointer_node;
15077
15078 tree V8QI_type_node;
15079 tree V4HI_type_node;
15080 tree V2SI_type_node;
15081 tree V2SF_type_node;
15082 tree V16QI_type_node;
15083 tree V8HI_type_node;
15084 tree V4SI_type_node;
15085 tree V4SF_type_node;
15086 tree V2DI_type_node;
15087
15088 tree intUQI_type_node;
15089 tree intUHI_type_node;
15090 tree intUSI_type_node;
15091 tree intUDI_type_node;
15092
15093 tree intEI_type_node;
15094 tree intOI_type_node;
15095 tree intCI_type_node;
15096 tree intXI_type_node;
15097
15098 tree V8QI_pointer_node;
15099 tree V4HI_pointer_node;
15100 tree V2SI_pointer_node;
15101 tree V2SF_pointer_node;
15102 tree V16QI_pointer_node;
15103 tree V8HI_pointer_node;
15104 tree V4SI_pointer_node;
15105 tree V4SF_pointer_node;
15106 tree V2DI_pointer_node;
15107
15108 tree void_ftype_pv8qi_v8qi_v8qi;
15109 tree void_ftype_pv4hi_v4hi_v4hi;
15110 tree void_ftype_pv2si_v2si_v2si;
15111 tree void_ftype_pv2sf_v2sf_v2sf;
15112 tree void_ftype_pdi_di_di;
15113 tree void_ftype_pv16qi_v16qi_v16qi;
15114 tree void_ftype_pv8hi_v8hi_v8hi;
15115 tree void_ftype_pv4si_v4si_v4si;
15116 tree void_ftype_pv4sf_v4sf_v4sf;
15117 tree void_ftype_pv2di_v2di_v2di;
15118
15119 tree reinterp_ftype_dreg[5][5];
15120 tree reinterp_ftype_qreg[5][5];
15121 tree dreg_types[5], qreg_types[5];
15122
88f77cba
JB		 15123 /* Create distinguished type nodes for NEON vector element types,
15124 and pointers to values of such types, so we can detect them later. */
af06585a
JM		 15125 neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
15126 neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
15127 neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode));
15128 neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode));
15129 neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode));
15130 neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode));
15131 neon_float_type_node = make_node (REAL_TYPE);
15132 TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE;
15133 layout_type (neon_float_type_node);
15134
bcbdbbb0
JM		 15135 /* Define typedefs which exactly correspond to the modes we are basing vector
15136 types on. If you change these names you'll need to change
15137 the table used by arm_mangle_type too. */
15138 (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node,
15139 "__builtin_neon_qi");
15140 (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node,
15141 "__builtin_neon_hi");
15142 (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node,
15143 "__builtin_neon_si");
15144 (*lang_hooks.types.register_builtin_type) (neon_float_type_node,
15145 "__builtin_neon_sf");
15146 (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node,
15147 "__builtin_neon_di");
15148 (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node,
15149 "__builtin_neon_poly8");
15150 (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node,
15151 "__builtin_neon_poly16");
15152
af06585a
JM		 15153 intQI_pointer_node = build_pointer_type (neon_intQI_type_node);
15154 intHI_pointer_node = build_pointer_type (neon_intHI_type_node);
15155 intSI_pointer_node = build_pointer_type (neon_intSI_type_node);
15156 intDI_pointer_node = build_pointer_type (neon_intDI_type_node);
15157 float_pointer_node = build_pointer_type (neon_float_type_node);
88f77cba
JB		 15158
15159 /* Next create constant-qualified versions of the above types. */
af06585a
JM		 15160 const_intQI_node = build_qualified_type (neon_intQI_type_node,
15161 TYPE_QUAL_CONST);
15162 const_intHI_node = build_qualified_type (neon_intHI_type_node,
15163 TYPE_QUAL_CONST);
15164 const_intSI_node = build_qualified_type (neon_intSI_type_node,
15165 TYPE_QUAL_CONST);
15166 const_intDI_node = build_qualified_type (neon_intDI_type_node,
15167 TYPE_QUAL_CONST);
15168 const_float_node = build_qualified_type (neon_float_type_node,
15169 TYPE_QUAL_CONST);
15170
15171 const_intQI_pointer_node = build_pointer_type (const_intQI_node);
15172 const_intHI_pointer_node = build_pointer_type (const_intHI_node);
15173 const_intSI_pointer_node = build_pointer_type (const_intSI_node);
15174 const_intDI_pointer_node = build_pointer_type (const_intDI_node);
15175 const_float_pointer_node = build_pointer_type (const_float_node);
88f77cba
JB		 15176
15177 /* Now create vector types based on our NEON element types. */
15178 /* 64-bit vectors. */
af06585a 15179 V8QI_type_node =
88f77cba 15180 build_vector_type_for_mode (neon_intQI_type_node, V8QImode);
af06585a 15181 V4HI_type_node =
88f77cba 15182 build_vector_type_for_mode (neon_intHI_type_node, V4HImode);
af06585a 15183 V2SI_type_node =
88f77cba 15184 build_vector_type_for_mode (neon_intSI_type_node, V2SImode);
af06585a 15185 V2SF_type_node =
88f77cba
JB		 15186 build_vector_type_for_mode (neon_float_type_node, V2SFmode);
15187 /* 128-bit vectors. */
af06585a 15188 V16QI_type_node =
88f77cba 15189 build_vector_type_for_mode (neon_intQI_type_node, V16QImode);
af06585a 15190 V8HI_type_node =
88f77cba 15191 build_vector_type_for_mode (neon_intHI_type_node, V8HImode);
af06585a 15192 V4SI_type_node =
88f77cba 15193 build_vector_type_for_mode (neon_intSI_type_node, V4SImode);
af06585a 15194 V4SF_type_node =
88f77cba 15195 build_vector_type_for_mode (neon_float_type_node, V4SFmode);
af06585a 15196 V2DI_type_node =
88f77cba
JB		 15197 build_vector_type_for_mode (neon_intDI_type_node, V2DImode);
15198
15199 /* Unsigned integer types for various mode sizes. */
af06585a
JM		 15200 intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode));
15201 intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode));
15202 intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode));
15203 intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode));
88f77cba 15204
bcbdbbb0
JM		 15205 (*lang_hooks.types.register_builtin_type) (intUQI_type_node,
15206 "__builtin_neon_uqi");
15207 (*lang_hooks.types.register_builtin_type) (intUHI_type_node,
15208 "__builtin_neon_uhi");
15209 (*lang_hooks.types.register_builtin_type) (intUSI_type_node,
15210 "__builtin_neon_usi");
15211 (*lang_hooks.types.register_builtin_type) (intUDI_type_node,
15212 "__builtin_neon_udi");
15213
88f77cba 15214 /* Opaque integer types for structures of vectors. */
af06585a
JM		 15215 intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode));
15216 intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode));
15217 intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode));
15218 intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode));
88f77cba 15219
bcbdbbb0
JM		 15220 (*lang_hooks.types.register_builtin_type) (intTI_type_node,
15221 "__builtin_neon_ti");
15222 (*lang_hooks.types.register_builtin_type) (intEI_type_node,
15223 "__builtin_neon_ei");
15224 (*lang_hooks.types.register_builtin_type) (intOI_type_node,
15225 "__builtin_neon_oi");
15226 (*lang_hooks.types.register_builtin_type) (intCI_type_node,
15227 "__builtin_neon_ci");
15228 (*lang_hooks.types.register_builtin_type) (intXI_type_node,
15229 "__builtin_neon_xi");
15230
88f77cba 15231 /* Pointers to vector types. */
af06585a
JM		 15232 V8QI_pointer_node = build_pointer_type (V8QI_type_node);
15233 V4HI_pointer_node = build_pointer_type (V4HI_type_node);
15234 V2SI_pointer_node = build_pointer_type (V2SI_type_node);
15235 V2SF_pointer_node = build_pointer_type (V2SF_type_node);
15236 V16QI_pointer_node = build_pointer_type (V16QI_type_node);
15237 V8HI_pointer_node = build_pointer_type (V8HI_type_node);
15238 V4SI_pointer_node = build_pointer_type (V4SI_type_node);
15239 V4SF_pointer_node = build_pointer_type (V4SF_type_node);
15240 V2DI_pointer_node = build_pointer_type (V2DI_type_node);
88f77cba
JB		 15241
15242 /* Operations which return results as pairs. */
af06585a 15243 void_ftype_pv8qi_v8qi_v8qi =
88f77cba
JB		 15244 build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node,
15245 V8QI_type_node, NULL);
af06585a 15246 void_ftype_pv4hi_v4hi_v4hi =
88f77cba
JB		 15247 build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node,
15248 V4HI_type_node, NULL);
af06585a 15249 void_ftype_pv2si_v2si_v2si =
88f77cba
JB		 15250 build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node,
15251 V2SI_type_node, NULL);
af06585a 15252 void_ftype_pv2sf_v2sf_v2sf =
88f77cba
JB		 15253 build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node,
15254 V2SF_type_node, NULL);
af06585a 15255 void_ftype_pdi_di_di =
88f77cba
JB		 15256 build_function_type_list (void_type_node, intDI_pointer_node,
15257 neon_intDI_type_node, neon_intDI_type_node, NULL);
af06585a 15258 void_ftype_pv16qi_v16qi_v16qi =
88f77cba
JB		 15259 build_function_type_list (void_type_node, V16QI_pointer_node,
15260 V16QI_type_node, V16QI_type_node, NULL);
af06585a 15261 void_ftype_pv8hi_v8hi_v8hi =
88f77cba
JB		 15262 build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node,
15263 V8HI_type_node, NULL);
af06585a 15264 void_ftype_pv4si_v4si_v4si =
88f77cba
JB		 15265 build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node,
15266 V4SI_type_node, NULL);
af06585a 15267 void_ftype_pv4sf_v4sf_v4sf =
88f77cba
JB		 15268 build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node,
15269 V4SF_type_node, NULL);
af06585a 15270 void_ftype_pv2di_v2di_v2di =
88f77cba
JB		 15271 build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node,
15272 V2DI_type_node, NULL);
15273
88f77cba
JB		 15274 dreg_types[0] = V8QI_type_node;
15275 dreg_types[1] = V4HI_type_node;
15276 dreg_types[2] = V2SI_type_node;
15277 dreg_types[3] = V2SF_type_node;
15278 dreg_types[4] = neon_intDI_type_node;
15279
15280 qreg_types[0] = V16QI_type_node;
15281 qreg_types[1] = V8HI_type_node;
15282 qreg_types[2] = V4SI_type_node;
15283 qreg_types[3] = V4SF_type_node;
15284 qreg_types[4] = V2DI_type_node;
15285
15286 for (i = 0; i < 5; i++)
15287 {
15288 int j;
15289 for (j = 0; j < 5; j++)
15290 {
15291 reinterp_ftype_dreg[i][j]
15292 = build_function_type_list (dreg_types[i], dreg_types[j], NULL);
15293 reinterp_ftype_qreg[i][j]
15294 = build_function_type_list (qreg_types[i], qreg_types[j], NULL);
15295 }
15296 }
15297
15298 for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++)
15299 {
15300 neon_builtin_datum *d = &neon_builtin_data[i];
15301 unsigned int j, codeidx = 0;
15302
15303 d->base_fcode = fcode;
15304
15305 for (j = 0; j < T_MAX; j++)
15306 {
15307 const char* const modenames[] = {
15308 "v8qi", "v4hi", "v2si", "v2sf", "di",
15309 "v16qi", "v8hi", "v4si", "v4sf", "v2di"
15310 };
15311 char namebuf[60];
15312 tree ftype = NULL;
15313 enum insn_code icode;
15314 int is_load = 0, is_store = 0;
15315
15316 if ((d->bits & (1 << j)) == 0)
15317 continue;
15318
15319 icode = d->codes[codeidx++];
15320
15321 switch (d->itype)
15322 {
15323 case NEON_LOAD1:
15324 case NEON_LOAD1LANE:
15325 case NEON_LOADSTRUCT:
15326 case NEON_LOADSTRUCTLANE:
15327 is_load = 1;
15328 /* Fall through. */
15329 case NEON_STORE1:
15330 case NEON_STORE1LANE:
15331 case NEON_STORESTRUCT:
15332 case NEON_STORESTRUCTLANE:
15333 if (!is_load)
15334 is_store = 1;
15335 /* Fall through. */
15336 case NEON_UNOP:
15337 case NEON_BINOP:
15338 case NEON_LOGICBINOP:
15339 case NEON_SHIFTINSERT:
15340 case NEON_TERNOP:
15341 case NEON_GETLANE:
15342 case NEON_SETLANE:
15343 case NEON_CREATE:
15344 case NEON_DUP:
15345 case NEON_DUPLANE:
15346 case NEON_SHIFTIMM:
15347 case NEON_SHIFTACC:
15348 case NEON_COMBINE:
15349 case NEON_SPLIT:
15350 case NEON_CONVERT:
15351 case NEON_FIXCONV:
15352 case NEON_LANEMUL:
15353 case NEON_LANEMULL:
15354 case NEON_LANEMULH:
15355 case NEON_LANEMAC:
15356 case NEON_SCALARMUL:
15357 case NEON_SCALARMULL:
15358 case NEON_SCALARMULH:
15359 case NEON_SCALARMAC:
15360 case NEON_SELECT:
15361 case NEON_VTBL:
15362 case NEON_VTBX:
15363 {
15364 int k;
15365 tree return_type = void_type_node, args = void_list_node;
15366
15367 /* Build a function type directly from the insn_data for this
15368 builtin. The build_function_type() function takes care of
15369 removing duplicates for us. */
15370 for (k = insn_data[icode].n_operands - 1; k >= 0; k--)
15371 {
15372 tree eltype;
15373
15374 if (is_load && k == 1)
15375 {
15376 /* Neon load patterns always have the memory operand
15377 (a SImode pointer) in the operand 1 position. We
15378 want a const pointer to the element type in that
15379 position. */
15380 gcc_assert (insn_data[icode].operand[k].mode == SImode);
15381
15382 switch (1 << j)
15383 {
15384 case T_V8QI:
15385 case T_V16QI:
15386 eltype = const_intQI_pointer_node;
15387 break;
15388
15389 case T_V4HI:
15390 case T_V8HI:
15391 eltype = const_intHI_pointer_node;
15392 break;
15393
15394 case T_V2SI:
15395 case T_V4SI:
15396 eltype = const_intSI_pointer_node;
15397 break;
15398
15399 case T_V2SF:
15400 case T_V4SF:
15401 eltype = const_float_pointer_node;
15402 break;
15403
15404 case T_DI:
15405 case T_V2DI:
15406 eltype = const_intDI_pointer_node;
15407 break;
15408
15409 default: gcc_unreachable ();
15410 }
15411 }
15412 else if (is_store && k == 0)
15413 {
15414 /* Similarly, Neon store patterns use operand 0 as
15415 the memory location to store to (a SImode pointer).
15416 Use a pointer to the element type of the store in
15417 that position. */
15418 gcc_assert (insn_data[icode].operand[k].mode == SImode);
15419
15420 switch (1 << j)
15421 {
15422 case T_V8QI:
15423 case T_V16QI:
15424 eltype = intQI_pointer_node;
15425 break;
15426
15427 case T_V4HI:
15428 case T_V8HI:
15429 eltype = intHI_pointer_node;
15430 break;
15431
15432 case T_V2SI:
15433 case T_V4SI:
15434 eltype = intSI_pointer_node;
15435 break;
15436
15437 case T_V2SF:
15438 case T_V4SF:
15439 eltype = float_pointer_node;
15440 break;
15441
15442 case T_DI:
15443 case T_V2DI:
15444 eltype = intDI_pointer_node;
15445 break;
15446
15447 default: gcc_unreachable ();
15448 }
15449 }
15450 else
15451 {
15452 switch (insn_data[icode].operand[k].mode)
15453 {
15454 case VOIDmode: eltype = void_type_node; break;
15455 /* Scalars. */
15456 case QImode: eltype = neon_intQI_type_node; break;
15457 case HImode: eltype = neon_intHI_type_node; break;
15458 case SImode: eltype = neon_intSI_type_node; break;
15459 case SFmode: eltype = neon_float_type_node; break;
15460 case DImode: eltype = neon_intDI_type_node; break;
15461 case TImode: eltype = intTI_type_node; break;
15462 case EImode: eltype = intEI_type_node; break;
15463 case OImode: eltype = intOI_type_node; break;
15464 case CImode: eltype = intCI_type_node; break;
15465 case XImode: eltype = intXI_type_node; break;
15466 /* 64-bit vectors. */
15467 case V8QImode: eltype = V8QI_type_node; break;
15468 case V4HImode: eltype = V4HI_type_node; break;
15469 case V2SImode: eltype = V2SI_type_node; break;
15470 case V2SFmode: eltype = V2SF_type_node; break;
15471 /* 128-bit vectors. */
15472 case V16QImode: eltype = V16QI_type_node; break;
15473 case V8HImode: eltype = V8HI_type_node; break;
15474 case V4SImode: eltype = V4SI_type_node; break;
15475 case V4SFmode: eltype = V4SF_type_node; break;
15476 case V2DImode: eltype = V2DI_type_node; break;
15477 default: gcc_unreachable ();
15478 }
15479 }
15480
15481 if (k == 0 && !is_store)
15482 return_type = eltype;
15483 else
15484 args = tree_cons (NULL_TREE, eltype, args);
15485 }
15486
15487 ftype = build_function_type (return_type, args);
15488 }
15489 break;
15490
15491 case NEON_RESULTPAIR:
15492 {
15493 switch (insn_data[icode].operand[1].mode)
15494 {
15495 case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break;
15496 case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break;
15497 case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break;
15498 case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break;
15499 case DImode: ftype = void_ftype_pdi_di_di; break;
15500 case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break;
15501 case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break;
15502 case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break;
15503 case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break;
15504 case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break;
15505 default: gcc_unreachable ();
15506 }
15507 }
15508 break;
15509
15510 case NEON_REINTERP:
15511 {
15512 /* We iterate over 5 doubleword types, then 5 quadword
15513 types. */
15514 int rhs = j % 5;
15515 switch (insn_data[icode].operand[0].mode)
15516 {
15517 case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break;
15518 case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break;
15519 case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break;
15520 case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break;
15521 case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break;
15522 case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break;
15523 case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break;
15524 case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break;
15525 case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break;
15526 case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break;
15527 default: gcc_unreachable ();
15528 }
15529 }
15530 break;
15531
15532 default:
15533 gcc_unreachable ();
15534 }
15535
15536 gcc_assert (ftype != NULL);
15537
15538 sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]);
15539
15540 add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL,
15541 NULL_TREE);
15542 }
15543 }
15544}
15545
5a9335ef
NC		 15546static void
15547arm_init_builtins (void)
15548{
d3585b76
DJ		 15549 arm_init_tls_builtins ();
15550
5a9335ef
NC		 15551 if (TARGET_REALLY_IWMMXT)
15552 arm_init_iwmmxt_builtins ();
88f77cba
JB		 15553
15554 if (TARGET_NEON)
15555 arm_init_neon_builtins ();
5a9335ef
NC		 15556}
15557
15558/* Errors in the source file can cause expand_expr to return const0_rtx
15559 where we expect a vector. To avoid crashing, use one of the vector
15560 clear instructions. */
15561
15562static rtx
15563safe_vector_operand (rtx x, enum machine_mode mode)
15564{
15565 if (x != const0_rtx)
15566 return x;
15567 x = gen_reg_rtx (mode);
15568
15569 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
15570 : gen_rtx_SUBREG (DImode, x, 0)));
15571 return x;
15572}
15573
15574/* Subroutine of arm_expand_builtin to take care of binop insns. */
15575
15576static rtx
15577arm_expand_binop_builtin (enum insn_code icode,
5039610b 15578 tree exp, rtx target)
5a9335ef
NC		 15579{
15580 rtx pat;
5039610b
SL		 15581 tree arg0 = CALL_EXPR_ARG (exp, 0);
15582 tree arg1 = CALL_EXPR_ARG (exp, 1);
84217346
MD		 15583 rtx op0 = expand_normal (arg0);
15584 rtx op1 = expand_normal (arg1);
5a9335ef
NC		 15585 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15586 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15587 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
15588
15589 if (VECTOR_MODE_P (mode0))
15590 op0 = safe_vector_operand (op0, mode0);
15591 if (VECTOR_MODE_P (mode1))
15592 op1 = safe_vector_operand (op1, mode1);
15593
15594 if (! target
15595 || GET_MODE (target) != tmode
15596 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15597 target = gen_reg_rtx (tmode);
15598
e6d29d15 15599 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
5a9335ef
NC		 15600
15601 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15602 op0 = copy_to_mode_reg (mode0, op0);
15603 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15604 op1 = copy_to_mode_reg (mode1, op1);
15605
15606 pat = GEN_FCN (icode) (target, op0, op1);
15607 if (! pat)
15608 return 0;
15609 emit_insn (pat);
15610 return target;
15611}
15612
15613/* Subroutine of arm_expand_builtin to take care of unop insns. */
15614
15615static rtx
15616arm_expand_unop_builtin (enum insn_code icode,
5039610b 15617 tree exp, rtx target, int do_load)
5a9335ef
NC		 15618{
15619 rtx pat;
5039610b 15620 tree arg0 = CALL_EXPR_ARG (exp, 0);
84217346 15621 rtx op0 = expand_normal (arg0);
5a9335ef
NC		 15622 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15623 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
15624
15625 if (! target
15626 || GET_MODE (target) != tmode
15627 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15628 target = gen_reg_rtx (tmode);
15629 if (do_load)
15630 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15631 else
15632 {
15633 if (VECTOR_MODE_P (mode0))
15634 op0 = safe_vector_operand (op0, mode0);
15635
15636 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15637 op0 = copy_to_mode_reg (mode0, op0);
15638 }
15639
15640 pat = GEN_FCN (icode) (target, op0);
15641 if (! pat)
15642 return 0;
15643 emit_insn (pat);
15644 return target;
15645}
15646
88f77cba
JB		 15647static int
15648neon_builtin_compare (const void *a, const void *b)
15649{
5ead67f6
KG		 15650 const neon_builtin_datum *const key = (const neon_builtin_datum *) a;
15651 const neon_builtin_datum *const memb = (const neon_builtin_datum *) b;
88f77cba
JB		 15652 unsigned int soughtcode = key->base_fcode;
15653
15654 if (soughtcode >= memb->base_fcode
15655 && soughtcode < memb->base_fcode + memb->num_vars)
15656 return 0;
15657 else if (soughtcode < memb->base_fcode)
15658 return -1;
15659 else
15660 return 1;
15661}
15662
15663static enum insn_code
15664locate_neon_builtin_icode (int fcode, neon_itype *itype)
15665{
15666 neon_builtin_datum key, *found;
15667 int idx;
15668
15669 key.base_fcode = fcode;
5ead67f6
KG		 15670 found = (neon_builtin_datum *)
15671 bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data),
88f77cba
JB		 15672 sizeof (neon_builtin_data[0]), neon_builtin_compare);
15673 gcc_assert (found);
15674 idx = fcode - (int) found->base_fcode;
15675 gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars);
15676
15677 if (itype)
15678 *itype = found->itype;
15679
15680 return found->codes[idx];
15681}
15682
15683typedef enum {
15684 NEON_ARG_COPY_TO_REG,
15685 NEON_ARG_CONSTANT,
15686 NEON_ARG_STOP
15687} builtin_arg;
15688
15689#define NEON_MAX_BUILTIN_ARGS 5
15690
15691/* Expand a Neon builtin. */
15692static rtx
15693arm_expand_neon_args (rtx target, int icode, int have_retval,
15694 tree exp, ...)
15695{
15696 va_list ap;
15697 rtx pat;
15698 tree arg[NEON_MAX_BUILTIN_ARGS];
15699 rtx op[NEON_MAX_BUILTIN_ARGS];
15700 enum machine_mode tmode = insn_data[icode].operand[0].mode;
15701 enum machine_mode mode[NEON_MAX_BUILTIN_ARGS];
15702 int argc = 0;
15703
15704 if (have_retval
15705 && (!target
15706 || GET_MODE (target) != tmode
15707 || !(*insn_data[icode].operand[0].predicate) (target, tmode)))
15708 target = gen_reg_rtx (tmode);
15709
15710 va_start (ap, exp);
15711
15712 for (;;)
15713 {
15714 builtin_arg thisarg = va_arg (ap, int);
15715
15716 if (thisarg == NEON_ARG_STOP)
15717 break;
15718 else
15719 {
15720 arg[argc] = CALL_EXPR_ARG (exp, argc);
15721 op[argc] = expand_normal (arg[argc]);
15722 mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
15723
15724 switch (thisarg)
15725 {
15726 case NEON_ARG_COPY_TO_REG:
15727 /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/
15728 if (!(*insn_data[icode].operand[argc + have_retval].predicate)
15729 (op[argc], mode[argc]))
15730 op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
15731 break;
15732
15733 case NEON_ARG_CONSTANT:
15734 /* FIXME: This error message is somewhat unhelpful. */
15735 if (!(*insn_data[icode].operand[argc + have_retval].predicate)
15736 (op[argc], mode[argc]))
15737 error ("argument must be a constant");
15738 break;
15739
15740 case NEON_ARG_STOP:
15741 gcc_unreachable ();
15742 }
15743
15744 argc++;
15745 }
15746 }
15747
15748 va_end (ap);
15749
15750 if (have_retval)
15751 switch (argc)
15752 {
15753 case 1:
15754 pat = GEN_FCN (icode) (target, op[0]);
15755 break;
15756
15757 case 2:
15758 pat = GEN_FCN (icode) (target, op[0], op[1]);
15759 break;
15760
15761 case 3:
15762 pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
15763 break;
15764
15765 case 4:
15766 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
15767 break;
15768
15769 case 5:
15770 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
15771 break;
15772
15773 default:
15774 gcc_unreachable ();
15775 }
15776 else
15777 switch (argc)
15778 {
15779 case 1:
15780 pat = GEN_FCN (icode) (op[0]);
15781 break;
15782
15783 case 2:
15784 pat = GEN_FCN (icode) (op[0], op[1]);
15785 break;
15786
15787 case 3:
15788 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
15789 break;
15790
15791 case 4:
15792 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
15793 break;
15794
15795 case 5:
15796 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
15797 break;
15798
15799 default:
15800 gcc_unreachable ();
15801 }
15802
15803 if (!pat)
15804 return 0;
15805
15806 emit_insn (pat);
15807
15808 return target;
15809}
15810
15811/* Expand a Neon builtin. These are "special" because they don't have symbolic
15812 constants defined per-instruction or per instruction-variant. Instead, the
15813 required info is looked up in the table neon_builtin_data. */
15814static rtx
15815arm_expand_neon_builtin (int fcode, tree exp, rtx target)
15816{
15817 neon_itype itype;
15818 enum insn_code icode = locate_neon_builtin_icode (fcode, &itype);
15819
15820 switch (itype)
15821 {
15822 case NEON_UNOP:
15823 case NEON_CONVERT:
15824 case NEON_DUPLANE:
15825 return arm_expand_neon_args (target, icode, 1, exp,
15826 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP);
15827
15828 case NEON_BINOP:
15829 case NEON_SETLANE:
15830 case NEON_SCALARMUL:
15831 case NEON_SCALARMULL:
15832 case NEON_SCALARMULH:
15833 case NEON_SHIFTINSERT:
15834 case NEON_LOGICBINOP:
15835 return arm_expand_neon_args (target, icode, 1, exp,
15836 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15837 NEON_ARG_STOP);
15838
15839 case NEON_TERNOP:
15840 return arm_expand_neon_args (target, icode, 1, exp,
15841 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15842 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15843
15844 case NEON_GETLANE:
15845 case NEON_FIXCONV:
15846 case NEON_SHIFTIMM:
15847 return arm_expand_neon_args (target, icode, 1, exp,
15848 NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT,
15849 NEON_ARG_STOP);
15850
15851 case NEON_CREATE:
15852 return arm_expand_neon_args (target, icode, 1, exp,
15853 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15854
15855 case NEON_DUP:
15856 case NEON_SPLIT:
15857 case NEON_REINTERP:
15858 return arm_expand_neon_args (target, icode, 1, exp,
15859 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15860
15861 case NEON_COMBINE:
15862 case NEON_VTBL:
15863 return arm_expand_neon_args (target, icode, 1, exp,
15864 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15865
15866 case NEON_RESULTPAIR:
15867 return arm_expand_neon_args (target, icode, 0, exp,
15868 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15869 NEON_ARG_STOP);
15870
15871 case NEON_LANEMUL:
15872 case NEON_LANEMULL:
15873 case NEON_LANEMULH:
15874 return arm_expand_neon_args (target, icode, 1, exp,
15875 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15876 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15877
15878 case NEON_LANEMAC:
15879 return arm_expand_neon_args (target, icode, 1, exp,
15880 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15881 NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP);
15882
15883 case NEON_SHIFTACC:
15884 return arm_expand_neon_args (target, icode, 1, exp,
15885 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15886 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15887
15888 case NEON_SCALARMAC:
15889 return arm_expand_neon_args (target, icode, 1, exp,
15890 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15891 NEON_ARG_CONSTANT, NEON_ARG_STOP);
15892
15893 case NEON_SELECT:
15894 case NEON_VTBX:
15895 return arm_expand_neon_args (target, icode, 1, exp,
15896 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG,
15897 NEON_ARG_STOP);
15898
15899 case NEON_LOAD1:
15900 case NEON_LOADSTRUCT:
15901 return arm_expand_neon_args (target, icode, 1, exp,
15902 NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15903
15904 case NEON_LOAD1LANE:
15905 case NEON_LOADSTRUCTLANE:
15906 return arm_expand_neon_args (target, icode, 1, exp,
15907 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15908 NEON_ARG_STOP);
15909
15910 case NEON_STORE1:
15911 case NEON_STORESTRUCT:
15912 return arm_expand_neon_args (target, icode, 0, exp,
15913 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP);
15914
15915 case NEON_STORE1LANE:
15916 case NEON_STORESTRUCTLANE:
15917 return arm_expand_neon_args (target, icode, 0, exp,
15918 NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT,
15919 NEON_ARG_STOP);
15920 }
15921
15922 gcc_unreachable ();
15923}
15924
15925/* Emit code to reinterpret one Neon type as another, without altering bits. */
15926void
15927neon_reinterpret (rtx dest, rtx src)
15928{
15929 emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src));
15930}
15931
15932/* Emit code to place a Neon pair result in memory locations (with equal
15933 registers). */
15934void
15935neon_emit_pair_result_insn (enum machine_mode mode,
15936 rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr,
15937 rtx op1, rtx op2)
15938{
15939 rtx mem = gen_rtx_MEM (mode, destaddr);
15940 rtx tmp1 = gen_reg_rtx (mode);
15941 rtx tmp2 = gen_reg_rtx (mode);
15942
15943 emit_insn (intfn (tmp1, op1, tmp2, op2));
15944
15945 emit_move_insn (mem, tmp1);
15946 mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
15947 emit_move_insn (mem, tmp2);
15948}
15949
15950/* Set up operands for a register copy from src to dest, taking care not to
15951 clobber registers in the process.
15952 FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't
15953 be called with a large N, so that should be OK. */
15954
15955void
15956neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count)
15957{
15958 unsigned int copied = 0, opctr = 0;
15959 unsigned int done = (1 << count) - 1;
15960 unsigned int i, j;
15961
15962 while (copied != done)
15963 {
15964 for (i = 0; i < count; i++)
15965 {
15966 int good = 1;
15967
15968 for (j = 0; good && j < count; j++)
15969 if (i != j && (copied & (1 << j)) == 0
15970 && reg_overlap_mentioned_p (src[j], dest[i]))
15971 good = 0;
15972
15973 if (good)
15974 {
15975 operands[opctr++] = dest[i];
15976 operands[opctr++] = src[i];
15977 copied |= 1 << i;
15978 }
15979 }
15980 }
15981
15982 gcc_assert (opctr == count * 2);
15983}
15984
5a9335ef
NC		 15985/* Expand an expression EXP that calls a built-in function,
15986 with result going to TARGET if that's convenient
15987 (and in mode MODE if that's convenient).
15988 SUBTARGET may be used as the target for computing one of EXP's operands.
15989 IGNORE is nonzero if the value is to be ignored. */
15990
15991static rtx
15992arm_expand_builtin (tree exp,
15993 rtx target,
15994 rtx subtarget ATTRIBUTE_UNUSED,
15995 enum machine_mode mode ATTRIBUTE_UNUSED,
15996 int ignore ATTRIBUTE_UNUSED)
15997{
15998 const struct builtin_description * d;
15999 enum insn_code icode;
5039610b 16000 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
5a9335ef
NC		 16001 tree arg0;
16002 tree arg1;
16003 tree arg2;
16004 rtx op0;
16005 rtx op1;
16006 rtx op2;
16007 rtx pat;
16008 int fcode = DECL_FUNCTION_CODE (fndecl);
16009 size_t i;
16010 enum machine_mode tmode;
16011 enum machine_mode mode0;
16012 enum machine_mode mode1;
16013 enum machine_mode mode2;
16014
88f77cba
JB		 16015 if (fcode >= ARM_BUILTIN_NEON_BASE)
16016 return arm_expand_neon_builtin (fcode, exp, target);
16017
5a9335ef
NC		 16018 switch (fcode)
16019 {
16020 case ARM_BUILTIN_TEXTRMSB:
16021 case ARM_BUILTIN_TEXTRMUB:
16022 case ARM_BUILTIN_TEXTRMSH:
16023 case ARM_BUILTIN_TEXTRMUH:
16024 case ARM_BUILTIN_TEXTRMSW:
16025 case ARM_BUILTIN_TEXTRMUW:
16026 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
16027 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
16028 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
16029 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
16030 : CODE_FOR_iwmmxt_textrmw);
16031
5039610b
SL		 16032 arg0 = CALL_EXPR_ARG (exp, 0);
16033 arg1 = CALL_EXPR_ARG (exp, 1);
84217346
MD		 16034 op0 = expand_normal (arg0);
16035 op1 = expand_normal (arg1);
5a9335ef
NC		 16036 tmode = insn_data[icode].operand[0].mode;
16037 mode0 = insn_data[icode].operand[1].mode;
16038 mode1 = insn_data[icode].operand[2].mode;
16039
16040 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
16041 op0 = copy_to_mode_reg (mode0, op0);
16042 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
16043 {
16044 /* @@@ better error message */
16045 error ("selector must be an immediate");
16046 return gen_reg_rtx (tmode);
16047 }
16048 if (target == 0
16049 || GET_MODE (target) != tmode
16050 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16051 target = gen_reg_rtx (tmode);
16052 pat = GEN_FCN (icode) (target, op0, op1);
16053 if (! pat)
16054 return 0;
16055 emit_insn (pat);
16056 return target;
16057
16058 case ARM_BUILTIN_TINSRB:
16059 case ARM_BUILTIN_TINSRH:
16060 case ARM_BUILTIN_TINSRW:
16061 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
16062 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
16063 : CODE_FOR_iwmmxt_tinsrw);
5039610b
SL		 16064 arg0 = CALL_EXPR_ARG (exp, 0);
16065 arg1 = CALL_EXPR_ARG (exp, 1);
16066 arg2 = CALL_EXPR_ARG (exp, 2);
84217346
MD		 16067 op0 = expand_normal (arg0);
16068 op1 = expand_normal (arg1);
16069 op2 = expand_normal (arg2);
5a9335ef
NC		 16070 tmode = insn_data[icode].operand[0].mode;
16071 mode0 = insn_data[icode].operand[1].mode;
16072 mode1 = insn_data[icode].operand[2].mode;
16073 mode2 = insn_data[icode].operand[3].mode;
16074
16075 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
16076 op0 = copy_to_mode_reg (mode0, op0);
16077 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
16078 op1 = copy_to_mode_reg (mode1, op1);
16079 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
16080 {
16081 /* @@@ better error message */
16082 error ("selector must be an immediate");
16083 return const0_rtx;
16084 }
16085 if (target == 0
16086 || GET_MODE (target) != tmode
16087 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16088 target = gen_reg_rtx (tmode);
16089 pat = GEN_FCN (icode) (target, op0, op1, op2);
16090 if (! pat)
16091 return 0;
16092 emit_insn (pat);
16093 return target;
16094
16095 case ARM_BUILTIN_SETWCX:
5039610b
SL		 16096 arg0 = CALL_EXPR_ARG (exp, 0);
16097 arg1 = CALL_EXPR_ARG (exp, 1);
84217346
MD		 16098 op0 = force_reg (SImode, expand_normal (arg0));
16099 op1 = expand_normal (arg1);
f07a6b21 16100 emit_insn (gen_iwmmxt_tmcr (op1, op0));
5a9335ef
NC		 16101 return 0;
16102
16103 case ARM_BUILTIN_GETWCX:
5039610b 16104 arg0 = CALL_EXPR_ARG (exp, 0);
84217346 16105 op0 = expand_normal (arg0);
5a9335ef
NC		 16106 target = gen_reg_rtx (SImode);
16107 emit_insn (gen_iwmmxt_tmrc (target, op0));
16108 return target;
16109
16110 case ARM_BUILTIN_WSHUFH:
16111 icode = CODE_FOR_iwmmxt_wshufh;
5039610b
SL		 16112 arg0 = CALL_EXPR_ARG (exp, 0);
16113 arg1 = CALL_EXPR_ARG (exp, 1);
84217346
MD		 16114 op0 = expand_normal (arg0);
16115 op1 = expand_normal (arg1);
5a9335ef
NC		 16116 tmode = insn_data[icode].operand[0].mode;
16117 mode1 = insn_data[icode].operand[1].mode;
16118 mode2 = insn_data[icode].operand[2].mode;
16119
16120 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
16121 op0 = copy_to_mode_reg (mode1, op0);
16122 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
16123 {
16124 /* @@@ better error message */
16125 error ("mask must be an immediate");
16126 return const0_rtx;
16127 }
16128 if (target == 0
16129 || GET_MODE (target) != tmode
16130 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16131 target = gen_reg_rtx (tmode);
16132 pat = GEN_FCN (icode) (target, op0, op1);
16133 if (! pat)
16134 return 0;
16135 emit_insn (pat);
16136 return target;
16137
16138 case ARM_BUILTIN_WSADB:
5039610b 16139 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
5a9335ef 16140 case ARM_BUILTIN_WSADH:
5039610b 16141 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
5a9335ef 16142 case ARM_BUILTIN_WSADBZ:
5039610b 16143 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
5a9335ef 16144 case ARM_BUILTIN_WSADHZ:
5039610b 16145 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
5a9335ef
NC		 16146
16147 /* Several three-argument builtins. */
16148 case ARM_BUILTIN_WMACS:
16149 case ARM_BUILTIN_WMACU:
16150 case ARM_BUILTIN_WALIGN:
16151 case ARM_BUILTIN_TMIA:
16152 case ARM_BUILTIN_TMIAPH:
16153 case ARM_BUILTIN_TMIATT:
16154 case ARM_BUILTIN_TMIATB:
16155 case ARM_BUILTIN_TMIABT:
16156 case ARM_BUILTIN_TMIABB:
16157 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
16158 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
16159 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
16160 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
16161 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
16162 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
16163 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
16164 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
16165 : CODE_FOR_iwmmxt_walign);
5039610b
SL		 16166 arg0 = CALL_EXPR_ARG (exp, 0);
16167 arg1 = CALL_EXPR_ARG (exp, 1);
16168 arg2 = CALL_EXPR_ARG (exp, 2);
84217346
MD		 16169 op0 = expand_normal (arg0);
16170 op1 = expand_normal (arg1);
16171 op2 = expand_normal (arg2);
5a9335ef
NC		 16172 tmode = insn_data[icode].operand[0].mode;
16173 mode0 = insn_data[icode].operand[1].mode;
16174 mode1 = insn_data[icode].operand[2].mode;
16175 mode2 = insn_data[icode].operand[3].mode;
16176
16177 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
16178 op0 = copy_to_mode_reg (mode0, op0);
16179 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
16180 op1 = copy_to_mode_reg (mode1, op1);
16181 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
16182 op2 = copy_to_mode_reg (mode2, op2);
16183 if (target == 0
16184 || GET_MODE (target) != tmode
16185 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
16186 target = gen_reg_rtx (tmode);
16187 pat = GEN_FCN (icode) (target, op0, op1, op2);
16188 if (! pat)
16189 return 0;
16190 emit_insn (pat);
16191 return target;
f676971a 16192
5a9335ef
NC		 16193 case ARM_BUILTIN_WZERO:
16194 target = gen_reg_rtx (DImode);
16195 emit_insn (gen_iwmmxt_clrdi (target));
16196 return target;
16197
d3585b76
DJ		 16198 case ARM_BUILTIN_THREAD_POINTER:
16199 return arm_load_tp (target);
16200
5a9335ef
NC		 16201 default:
16202 break;
16203 }
16204
e97a46ce 16205 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
5a9335ef 16206 if (d->code == (const enum arm_builtins) fcode)
5039610b 16207 return arm_expand_binop_builtin (d->icode, exp, target);
5a9335ef 16208
e97a46ce 16209 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
5a9335ef 16210 if (d->code == (const enum arm_builtins) fcode)
5039610b 16211 return arm_expand_unop_builtin (d->icode, exp, target, 0);
5a9335ef
NC		 16212
16213 /* @@@ Should really do something sensible here. */
16214 return NULL_RTX;
16215}
16216\f
1d6e90ac
NC		 16217/* Return the number (counting from 0) of
16218 the least significant set bit in MASK. */
16219
e32bac5b 16220inline static int
b279b20a 16221number_of_first_bit_set (unsigned mask)
d5b7b3ae
RE		 16222{
16223 int bit;
16224
16225 for (bit = 0;
16226 (mask & (1 << bit)) == 0;
5895f793 16227 ++bit)
d5b7b3ae
RE		 16228 continue;
16229
16230 return bit;
16231}
16232
b279b20a
NC		 16233/* Emit code to push or pop registers to or from the stack. F is the
16234 assembly file. MASK is the registers to push or pop. PUSH is
16235 nonzero if we should push, and zero if we should pop. For debugging
16236 output, if pushing, adjust CFA_OFFSET by the amount of space added
16237 to the stack. REAL_REGS should have the same number of bits set as
16238 MASK, and will be used instead (in the same order) to describe which
16239 registers were saved - this is used to mark the save slots when we
16240 push high registers after moving them to low registers. */
16241static void
16242thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
16243 unsigned long real_regs)
16244{
16245 int regno;
16246 int lo_mask = mask & 0xFF;
16247 int pushed_words = 0;
16248
e6d29d15 16249 gcc_assert (mask);
b279b20a
NC		 16250
16251 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
16252 {
16253 /* Special case. Do not generate a POP PC statement here, do it in
16254 thumb_exit() */
16255 thumb_exit (f, -1);
16256 return;
16257 }
16258
617a1b71
PB		 16259 if (ARM_EABI_UNWIND_TABLES && push)
16260 {
16261 fprintf (f, "\t.save\t{");
16262 for (regno = 0; regno < 15; regno++)
16263 {
16264 if (real_regs & (1 << regno))
16265 {
16266 if (real_regs & ((1 << regno) -1))
16267 fprintf (f, ", ");
16268 asm_fprintf (f, "%r", regno);
16269 }
16270 }
16271 fprintf (f, "}\n");
16272 }
16273
b279b20a
NC		 16274 fprintf (f, "\t%s\t{", push ? "push" : "pop");
16275
16276 /* Look at the low registers first. */
16277 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
16278 {
16279 if (lo_mask & 1)
16280 {
16281 asm_fprintf (f, "%r", regno);
16282
16283 if ((lo_mask & ~1) != 0)
16284 fprintf (f, ", ");
16285
16286 pushed_words++;
16287 }
16288 }
16289
16290 if (push && (mask & (1 << LR_REGNUM)))
16291 {
16292 /* Catch pushing the LR. */
16293 if (mask & 0xFF)
16294 fprintf (f, ", ");
16295
16296 asm_fprintf (f, "%r", LR_REGNUM);
16297
16298 pushed_words++;
16299 }
16300 else if (!push && (mask & (1 << PC_REGNUM)))
16301 {
16302 /* Catch popping the PC. */
16303 if (TARGET_INTERWORK || TARGET_BACKTRACE
e3b5732b 16304 || crtl->calls_eh_return)
b279b20a
NC		 16305 {
16306 /* The PC is never poped directly, instead
16307 it is popped into r3 and then BX is used. */
16308 fprintf (f, "}\n");
16309
16310 thumb_exit (f, -1);
16311
16312 return;
16313 }
16314 else
16315 {
16316 if (mask & 0xFF)
16317 fprintf (f, ", ");
16318
16319 asm_fprintf (f, "%r", PC_REGNUM);
16320 }
16321 }
16322
16323 fprintf (f, "}\n");
16324
16325 if (push && pushed_words && dwarf2out_do_frame ())
16326 {
16327 char *l = dwarf2out_cfi_label ();
16328 int pushed_mask = real_regs;
16329
16330 *cfa_offset += pushed_words * 4;
16331 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
16332
16333 pushed_words = 0;
16334 pushed_mask = real_regs;
16335 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
16336 {
16337 if (pushed_mask & 1)
16338 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
16339 }
16340 }
16341}
16342
d5b7b3ae
RE		 16343/* Generate code to return from a thumb function.
16344 If 'reg_containing_return_addr' is -1, then the return address is
16345 actually on the stack, at the stack pointer. */
16346static void
c9ca9b88 16347thumb_exit (FILE *f, int reg_containing_return_addr)
d5b7b3ae
RE		 16348{
16349 unsigned regs_available_for_popping;
16350 unsigned regs_to_pop;
16351 int pops_needed;
16352 unsigned available;
16353 unsigned required;
16354 int mode;
16355 int size;
16356 int restore_a4 = FALSE;
16357
16358 /* Compute the registers we need to pop. */
16359 regs_to_pop = 0;
16360 pops_needed = 0;
16361
c9ca9b88 16362 if (reg_containing_return_addr == -1)
d5b7b3ae 16363 {
d5b7b3ae 16364 regs_to_pop |= 1 << LR_REGNUM;
5895f793 16365 ++pops_needed;
d5b7b3ae
RE		 16366 }
16367
16368 if (TARGET_BACKTRACE)
16369 {
16370 /* Restore the (ARM) frame pointer and stack pointer. */
16371 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
16372 pops_needed += 2;
16373 }
16374
16375 /* If there is nothing to pop then just emit the BX instruction and
16376 return. */
16377 if (pops_needed == 0)
16378 {
e3b5732b 16379 if (crtl->calls_eh_return)
c9ca9b88 16380 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
d5b7b3ae
RE		 16381
16382 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
16383 return;
16384 }
16385 /* Otherwise if we are not supporting interworking and we have not created
16386 a backtrace structure and the function was not entered in ARM mode then
16387 just pop the return address straight into the PC. */
5895f793
RE		 16388 else if (!TARGET_INTERWORK
16389 && !TARGET_BACKTRACE
c9ca9b88 16390 && !is_called_in_ARM_mode (current_function_decl)
e3b5732b 16391 && !crtl->calls_eh_return)
d5b7b3ae 16392 {
c9ca9b88 16393 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
d5b7b3ae
RE		 16394 return;
16395 }
16396
16397 /* Find out how many of the (return) argument registers we can corrupt. */
16398 regs_available_for_popping = 0;
16399
16400 /* If returning via __builtin_eh_return, the bottom three registers
16401 all contain information needed for the return. */
e3b5732b 16402 if (crtl->calls_eh_return)
d5b7b3ae
RE		 16403 size = 12;
16404 else
16405 {
d5b7b3ae
RE		 16406 /* If we can deduce the registers used from the function's
16407 return value. This is more reliable that examining
6fb5fa3c 16408 df_regs_ever_live_p () because that will be set if the register is
d5b7b3ae
RE		 16409 ever used in the function, not just if the register is used
16410 to hold a return value. */
16411
38173d38
JH		 16412 if (crtl->return_rtx != 0)
16413 mode = GET_MODE (crtl->return_rtx);
d5b7b3ae 16414 else
d5b7b3ae
RE		 16415 mode = DECL_MODE (DECL_RESULT (current_function_decl));
16416
16417 size = GET_MODE_SIZE (mode);
16418
16419 if (size == 0)
16420 {
16421 /* In a void function we can use any argument register.
16422 In a function that returns a structure on the stack
16423 we can use the second and third argument registers. */
16424 if (mode == VOIDmode)
16425 regs_available_for_popping =
16426 (1 << ARG_REGISTER (1))
16427 | (1 << ARG_REGISTER (2))
16428 | (1 << ARG_REGISTER (3));
16429 else
16430 regs_available_for_popping =
16431 (1 << ARG_REGISTER (2))
16432 | (1 << ARG_REGISTER (3));
16433 }
16434 else if (size <= 4)
16435 regs_available_for_popping =
16436 (1 << ARG_REGISTER (2))
16437 | (1 << ARG_REGISTER (3));
16438 else if (size <= 8)
16439 regs_available_for_popping =
16440 (1 << ARG_REGISTER (3));
16441 }
16442
16443 /* Match registers to be popped with registers into which we pop them. */
16444 for (available = regs_available_for_popping,
16445 required = regs_to_pop;
16446 required != 0 && available != 0;
16447 available &= ~(available & - available),
16448 required &= ~(required & - required))
16449 -- pops_needed;
16450
16451 /* If we have any popping registers left over, remove them. */
16452 if (available > 0)
5895f793 16453 regs_available_for_popping &= ~available;
f676971a 16454
d5b7b3ae
RE		 16455 /* Otherwise if we need another popping register we can use
16456 the fourth argument register. */
16457 else if (pops_needed)
16458 {
16459 /* If we have not found any free argument registers and
16460 reg a4 contains the return address, we must move it. */
16461 if (regs_available_for_popping == 0
16462 && reg_containing_return_addr == LAST_ARG_REGNUM)
16463 {
16464 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
16465 reg_containing_return_addr = LR_REGNUM;
16466 }
16467 else if (size > 12)
16468 {
16469 /* Register a4 is being used to hold part of the return value,
16470 but we have dire need of a free, low register. */
16471 restore_a4 = TRUE;
f676971a 16472
d5b7b3ae
RE		 16473 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
16474 }
f676971a 16475
d5b7b3ae
RE		 16476 if (reg_containing_return_addr != LAST_ARG_REGNUM)
16477 {
16478 /* The fourth argument register is available. */
16479 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
f676971a 16480
5895f793 16481 --pops_needed;
d5b7b3ae
RE		 16482 }
16483 }
16484
16485 /* Pop as many registers as we can. */
980e61bb
DJ		 16486 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16487 regs_available_for_popping);
d5b7b3ae
RE		 16488
16489 /* Process the registers we popped. */
16490 if (reg_containing_return_addr == -1)
16491 {
16492 /* The return address was popped into the lowest numbered register. */
5895f793 16493 regs_to_pop &= ~(1 << LR_REGNUM);
f676971a 16494
d5b7b3ae
RE		 16495 reg_containing_return_addr =
16496 number_of_first_bit_set (regs_available_for_popping);
16497
16498 /* Remove this register for the mask of available registers, so that
6bc82793 16499 the return address will not be corrupted by further pops. */
5895f793 16500 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
d5b7b3ae
RE		 16501 }
16502
16503 /* If we popped other registers then handle them here. */
16504 if (regs_available_for_popping)
16505 {
16506 int frame_pointer;
f676971a 16507
d5b7b3ae
RE		 16508 /* Work out which register currently contains the frame pointer. */
16509 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
16510
16511 /* Move it into the correct place. */
16512 asm_fprintf (f, "\tmov\t%r, %r\n",
16513 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
16514
16515 /* (Temporarily) remove it from the mask of popped registers. */
5895f793
RE		 16516 regs_available_for_popping &= ~(1 << frame_pointer);
16517 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
f676971a 16518
d5b7b3ae
RE		 16519 if (regs_available_for_popping)
16520 {
16521 int stack_pointer;
f676971a 16522
d5b7b3ae
RE		 16523 /* We popped the stack pointer as well,
16524 find the register that contains it. */
16525 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
16526
16527 /* Move it into the stack register. */
16528 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
f676971a 16529
d5b7b3ae
RE		 16530 /* At this point we have popped all necessary registers, so
16531 do not worry about restoring regs_available_for_popping
16532 to its correct value:
16533
16534 assert (pops_needed == 0)
16535 assert (regs_available_for_popping == (1 << frame_pointer))
16536 assert (regs_to_pop == (1 << STACK_POINTER)) */
16537 }
16538 else
16539 {
16540 /* Since we have just move the popped value into the frame
16541 pointer, the popping register is available for reuse, and
16542 we know that we still have the stack pointer left to pop. */
16543 regs_available_for_popping |= (1 << frame_pointer);
16544 }
16545 }
f676971a 16546
d5b7b3ae
RE		 16547 /* If we still have registers left on the stack, but we no longer have
16548 any registers into which we can pop them, then we must move the return
16549 address into the link register and make available the register that
16550 contained it. */
16551 if (regs_available_for_popping == 0 && pops_needed > 0)
16552 {
16553 regs_available_for_popping |= 1 << reg_containing_return_addr;
f676971a 16554
d5b7b3ae
RE		 16555 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
16556 reg_containing_return_addr);
f676971a 16557
d5b7b3ae
RE		 16558 reg_containing_return_addr = LR_REGNUM;
16559 }
16560
16561 /* If we have registers left on the stack then pop some more.
16562 We know that at most we will want to pop FP and SP. */
16563 if (pops_needed > 0)
16564 {
16565 int popped_into;
16566 int move_to;
f676971a 16567
980e61bb
DJ		 16568 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16569 regs_available_for_popping);
d5b7b3ae
RE		 16570
16571 /* We have popped either FP or SP.
16572 Move whichever one it is into the correct register. */
16573 popped_into = number_of_first_bit_set (regs_available_for_popping);
16574 move_to = number_of_first_bit_set (regs_to_pop);
16575
16576 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
16577
5895f793 16578 regs_to_pop &= ~(1 << move_to);
d5b7b3ae 16579
5895f793 16580 --pops_needed;
d5b7b3ae 16581 }
f676971a 16582
d5b7b3ae
RE		 16583 /* If we still have not popped everything then we must have only
16584 had one register available to us and we are now popping the SP. */
16585 if (pops_needed > 0)
16586 {
16587 int popped_into;
f676971a 16588
980e61bb
DJ		 16589 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
16590 regs_available_for_popping);
d5b7b3ae
RE		 16591
16592 popped_into = number_of_first_bit_set (regs_available_for_popping);
16593
16594 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
16595 /*
16596 assert (regs_to_pop == (1 << STACK_POINTER))
16597 assert (pops_needed == 1)
16598 */
16599 }
16600
16601 /* If necessary restore the a4 register. */
16602 if (restore_a4)
16603 {
16604 if (reg_containing_return_addr != LR_REGNUM)
16605 {
16606 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
16607 reg_containing_return_addr = LR_REGNUM;
16608 }
f676971a 16609
d5b7b3ae
RE		 16610 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
16611 }
16612
e3b5732b 16613 if (crtl->calls_eh_return)
c9ca9b88 16614 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
d5b7b3ae
RE		 16615
16616 /* Return to caller. */
16617 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
16618}
16619
d5b7b3ae
RE		 16620\f
16621void
5b3e6663 16622thumb1_final_prescan_insn (rtx insn)
d5b7b3ae 16623{
d5b7b3ae 16624 if (flag_print_asm_name)
9d98a694
AO		 16625 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
16626 INSN_ADDRESSES (INSN_UID (insn)));
d5b7b3ae
RE		 16627}
16628
16629int
e32bac5b 16630thumb_shiftable_const (unsigned HOST_WIDE_INT val)
d5b7b3ae
RE		 16631{
16632 unsigned HOST_WIDE_INT mask = 0xff;
16633 int i;
16634
16635 if (val == 0) /* XXX */
16636 return 0;
f676971a 16637
d5b7b3ae
RE		 16638 for (i = 0; i < 25; i++)
16639 if ((val & (mask << i)) == val)
16640 return 1;
16641
16642 return 0;
16643}
16644
825dda42 16645/* Returns nonzero if the current function contains,
d5b7b3ae 16646 or might contain a far jump. */
5848830f
PB		 16647static int
16648thumb_far_jump_used_p (void)
d5b7b3ae
RE		 16649{
16650 rtx insn;
16651
16652 /* This test is only important for leaf functions. */
5895f793 16653 /* assert (!leaf_function_p ()); */
f676971a 16654
d5b7b3ae
RE		 16655 /* If we have already decided that far jumps may be used,
16656 do not bother checking again, and always return true even if
16657 it turns out that they are not being used. Once we have made
16658 the decision that far jumps are present (and that hence the link
16659 register will be pushed onto the stack) we cannot go back on it. */
16660 if (cfun->machine->far_jump_used)
16661 return 1;
16662
16663 /* If this function is not being called from the prologue/epilogue
16664 generation code then it must be being called from the
16665 INITIAL_ELIMINATION_OFFSET macro. */
5848830f 16666 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
d5b7b3ae
RE		 16667 {
16668 /* In this case we know that we are being asked about the elimination
16669 of the arg pointer register. If that register is not being used,
16670 then there are no arguments on the stack, and we do not have to
16671 worry that a far jump might force the prologue to push the link
16672 register, changing the stack offsets. In this case we can just
16673 return false, since the presence of far jumps in the function will
16674 not affect stack offsets.
16675
16676 If the arg pointer is live (or if it was live, but has now been
16677 eliminated and so set to dead) then we do have to test to see if
16678 the function might contain a far jump. This test can lead to some
16679 false negatives, since before reload is completed, then length of
16680 branch instructions is not known, so gcc defaults to returning their
16681 longest length, which in turn sets the far jump attribute to true.
16682
16683 A false negative will not result in bad code being generated, but it
16684 will result in a needless push and pop of the link register. We
5848830f
PB		 16685 hope that this does not occur too often.
16686
16687 If we need doubleword stack alignment this could affect the other
16688 elimination offsets so we can't risk getting it wrong. */
6fb5fa3c 16689 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
d5b7b3ae 16690 cfun->machine->arg_pointer_live = 1;
5895f793 16691 else if (!cfun->machine->arg_pointer_live)
d5b7b3ae
RE		 16692 return 0;
16693 }
16694
16695 /* Check to see if the function contains a branch
16696 insn with the far jump attribute set. */
16697 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16698 {
16699 if (GET_CODE (insn) == JUMP_INSN
16700 /* Ignore tablejump patterns. */
16701 && GET_CODE (PATTERN (insn)) != ADDR_VEC
16702 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
16703 && get_attr_far_jump (insn) == FAR_JUMP_YES
16704 )
16705 {
9a9f7594 16706 /* Record the fact that we have decided that
d5b7b3ae
RE		 16707 the function does use far jumps. */
16708 cfun->machine->far_jump_used = 1;
16709 return 1;
16710 }
16711 }
f676971a 16712
d5b7b3ae
RE		 16713 return 0;
16714}
16715
825dda42 16716/* Return nonzero if FUNC must be entered in ARM mode. */
d5b7b3ae 16717int
e32bac5b 16718is_called_in_ARM_mode (tree func)
d5b7b3ae 16719{
e6d29d15 16720 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
d5b7b3ae 16721
696e78bf 16722 /* Ignore the problem about functions whose address is taken. */
d5b7b3ae
RE		 16723 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
16724 return TRUE;
16725
f676971a 16726#ifdef ARM_PE
91d231cb 16727 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
d5b7b3ae
RE		 16728#else
16729 return FALSE;
16730#endif
16731}
16732
d6b4baa4 16733/* The bits which aren't usefully expanded as rtl. */
cd2b33d0 16734const char *
e32bac5b 16735thumb_unexpanded_epilogue (void)
d5b7b3ae 16736{
954954d1 16737 arm_stack_offsets *offsets;
d5b7b3ae 16738 int regno;
b279b20a 16739 unsigned long live_regs_mask = 0;
d5b7b3ae 16740 int high_regs_pushed = 0;
d5b7b3ae 16741 int had_to_push_lr;
57934c39 16742 int size;
d5b7b3ae
RE		 16743
16744 if (return_used_this_function)
16745 return "";
16746
58e60158
AN		 16747 if (IS_NAKED (arm_current_func_type ()))
16748 return "";
16749
954954d1
PB		 16750 offsets = arm_get_frame_offsets ();
16751 live_regs_mask = offsets->saved_regs_mask;
57934c39
PB		 16752 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
16753
16754 /* If we can deduce the registers used from the function's return value.
6fb5fa3c 16755 This is more reliable that examining df_regs_ever_live_p () because that
57934c39
PB		 16756 will be set if the register is ever used in the function, not just if
16757 the register is used to hold a return value. */
4f5dfed0 16758 size = arm_size_return_regs ();
d5b7b3ae
RE		 16759
16760 /* The prolog may have pushed some high registers to use as
112cdef5 16761 work registers. e.g. the testsuite file:
d5b7b3ae
RE		 16762 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
16763 compiles to produce:
16764 push {r4, r5, r6, r7, lr}
16765 mov r7, r9
16766 mov r6, r8
16767 push {r6, r7}
16768 as part of the prolog. We have to undo that pushing here. */
f676971a 16769
d5b7b3ae
RE		 16770 if (high_regs_pushed)
16771 {
b279b20a 16772 unsigned long mask = live_regs_mask & 0xff;
d5b7b3ae 16773 int next_hi_reg;
d5b7b3ae 16774
57934c39
PB		 16775 /* The available low registers depend on the size of the value we are
16776 returning. */
16777 if (size <= 12)
d5b7b3ae 16778 mask |= 1 << 3;
57934c39
PB		 16779 if (size <= 8)
16780 mask |= 1 << 2;
d5b7b3ae
RE		 16781
16782 if (mask == 0)
16783 /* Oh dear! We have no low registers into which we can pop
16784 high registers! */
400500c4
RK		 16785 internal_error
16786 ("no low registers available for popping high registers");
f676971a 16787
d5b7b3ae 16788 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
57934c39 16789 if (live_regs_mask & (1 << next_hi_reg))
d5b7b3ae
RE		 16790 break;
16791
16792 while (high_regs_pushed)
16793 {
16794 /* Find lo register(s) into which the high register(s) can
16795 be popped. */
16796 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
16797 {
16798 if (mask & (1 << regno))
16799 high_regs_pushed--;
16800 if (high_regs_pushed == 0)
16801 break;
16802 }
16803
16804 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
16805
d6b4baa4 16806 /* Pop the values into the low register(s). */
980e61bb 16807 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
d5b7b3ae
RE		 16808
16809 /* Move the value(s) into the high registers. */
16810 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
16811 {
16812 if (mask & (1 << regno))
16813 {
16814 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
16815 regno);
f676971a 16816
d5b7b3ae 16817 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
57934c39 16818 if (live_regs_mask & (1 << next_hi_reg))
d5b7b3ae
RE		 16819 break;
16820 }
16821 }
16822 }
57934c39 16823 live_regs_mask &= ~0x0f00;
d5b7b3ae
RE		 16824 }
16825
57934c39
PB		 16826 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
16827 live_regs_mask &= 0xff;
16828
38173d38 16829 if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE)
d5b7b3ae 16830 {
f676971a 16831 /* Pop the return address into the PC. */
57934c39 16832 if (had_to_push_lr)
d5b7b3ae
RE		 16833 live_regs_mask |= 1 << PC_REGNUM;
16834
16835 /* Either no argument registers were pushed or a backtrace
16836 structure was created which includes an adjusted stack
16837 pointer, so just pop everything. */
16838 if (live_regs_mask)
980e61bb
DJ		 16839 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
16840 live_regs_mask);
57934c39 16841
d5b7b3ae 16842 /* We have either just popped the return address into the
57934c39
PB		 16843 PC or it is was kept in LR for the entire function. */
16844 if (!had_to_push_lr)
16845 thumb_exit (asm_out_file, LR_REGNUM);
d5b7b3ae
RE		 16846 }
16847 else
16848 {
16849 /* Pop everything but the return address. */
d5b7b3ae 16850 if (live_regs_mask)
980e61bb
DJ		 16851 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
16852 live_regs_mask);
d5b7b3ae
RE		 16853
16854 if (had_to_push_lr)
57934c39
PB		 16855 {
16856 if (size > 12)
16857 {
16858 /* We have no free low regs, so save one. */
16859 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
16860 LAST_ARG_REGNUM);
16861 }
16862
16863 /* Get the return address into a temporary register. */
16864 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
16865 1 << LAST_ARG_REGNUM);
16866
16867 if (size > 12)
16868 {
16869 /* Move the return address to lr. */
16870 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
16871 LAST_ARG_REGNUM);
16872 /* Restore the low register. */
16873 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
16874 IP_REGNUM);
16875 regno = LR_REGNUM;
16876 }
16877 else
16878 regno = LAST_ARG_REGNUM;
16879 }
16880 else
16881 regno = LR_REGNUM;
f676971a 16882
d5b7b3ae
RE		 16883 /* Remove the argument registers that were pushed onto the stack. */
16884 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
16885 SP_REGNUM, SP_REGNUM,
38173d38 16886 crtl->args.pretend_args_size);
f676971a 16887
57934c39 16888 thumb_exit (asm_out_file, regno);
d5b7b3ae
RE		 16889 }
16890
16891 return "";
16892}
16893
16894/* Functions to save and restore machine-specific function data. */
e2500fed 16895static struct machine_function *
e32bac5b 16896arm_init_machine_status (void)
d5b7b3ae 16897{
e2500fed
GK		 16898 struct machine_function *machine;
16899 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
6d3d9133 16900
f676971a 16901#if ARM_FT_UNKNOWN != 0
e2500fed 16902 machine->func_type = ARM_FT_UNKNOWN;
6d3d9133 16903#endif
e2500fed 16904 return machine;
f7a80099
NC		 16905}
16906
d5b7b3ae
RE		 16907/* Return an RTX indicating where the return address to the
16908 calling function can be found. */
16909rtx
e32bac5b 16910arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
d5b7b3ae 16911{
d5b7b3ae
RE		 16912 if (count != 0)
16913 return NULL_RTX;
16914
61f0ccff 16915 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
d5b7b3ae
RE		 16916}
16917
16918/* Do anything needed before RTL is emitted for each function. */
16919void
e32bac5b 16920arm_init_expanders (void)
d5b7b3ae
RE		 16921{
16922 /* Arrange to initialize and mark the machine per-function status. */
16923 init_machine_status = arm_init_machine_status;
3ac5ea7c
RH		 16924
16925 /* This is to stop the combine pass optimizing away the alignment
16926 adjustment of va_arg. */
16927 /* ??? It is claimed that this should not be necessary. */
16928 if (cfun)
16929 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
d5b7b3ae
RE		 16930}
16931
0977774b 16932
2591db65
RE		 16933/* Like arm_compute_initial_elimination offset. Simpler because there
16934 isn't an ABI specified frame pointer for Thumb. Instead, we set it
16935 to point at the base of the local variables after static stack
16936 space for a function has been allocated. */
0977774b 16937
5848830f
PB		 16938HOST_WIDE_INT
16939thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
16940{
16941 arm_stack_offsets *offsets;
0977774b 16942
5848830f 16943 offsets = arm_get_frame_offsets ();
0977774b 16944
5848830f 16945 switch (from)
0977774b 16946 {
5848830f
PB		 16947 case ARG_POINTER_REGNUM:
16948 switch (to)
16949 {
16950 case STACK_POINTER_REGNUM:
16951 return offsets->outgoing_args - offsets->saved_args;
0977774b 16952
5848830f
PB		 16953 case FRAME_POINTER_REGNUM:
16954 return offsets->soft_frame - offsets->saved_args;
0977774b 16955
5848830f
PB		 16956 case ARM_HARD_FRAME_POINTER_REGNUM:
16957 return offsets->saved_regs - offsets->saved_args;
0977774b 16958
2591db65
RE		 16959 case THUMB_HARD_FRAME_POINTER_REGNUM:
16960 return offsets->locals_base - offsets->saved_args;
16961
5848830f 16962 default:
e6d29d15 16963 gcc_unreachable ();
5848830f
PB		 16964 }
16965 break;
0977774b 16966
5848830f
PB		 16967 case FRAME_POINTER_REGNUM:
16968 switch (to)
16969 {
16970 case STACK_POINTER_REGNUM:
16971 return offsets->outgoing_args - offsets->soft_frame;
0977774b 16972
5848830f
PB		 16973 case ARM_HARD_FRAME_POINTER_REGNUM:
16974 return offsets->saved_regs - offsets->soft_frame;
0977774b 16975
2591db65
RE		 16976 case THUMB_HARD_FRAME_POINTER_REGNUM:
16977 return offsets->locals_base - offsets->soft_frame;
16978
5848830f 16979 default:
e6d29d15 16980 gcc_unreachable ();
5848830f
PB		 16981 }
16982 break;
0977774b 16983
5848830f 16984 default:
e6d29d15 16985 gcc_unreachable ();
5848830f 16986 }
0977774b
JT		 16987}
16988
d5b7b3ae
RE		 16989/* Generate the rest of a function's prologue. */
16990void
5b3e6663 16991thumb1_expand_prologue (void)
d5b7b3ae 16992{
980e61bb
DJ		 16993 rtx insn, dwarf;
16994
5848830f
PB		 16995 HOST_WIDE_INT amount;
16996 arm_stack_offsets *offsets;
6d3d9133 16997 unsigned long func_type;
3c7ad43e 16998 int regno;
57934c39 16999 unsigned long live_regs_mask;
6d3d9133
NC		 17000
17001 func_type = arm_current_func_type ();
f676971a 17002
d5b7b3ae 17003 /* Naked functions don't have prologues. */
6d3d9133 17004 if (IS_NAKED (func_type))
d5b7b3ae
RE		 17005 return;
17006
6d3d9133
NC		 17007 if (IS_INTERRUPT (func_type))
17008 {
c725bd79 17009 error ("interrupt Service Routines cannot be coded in Thumb mode");
6d3d9133
NC		 17010 return;
17011 }
17012
954954d1
PB		 17013 offsets = arm_get_frame_offsets ();
17014 live_regs_mask = offsets->saved_regs_mask;
b279b20a
NC		 17015 /* Load the pic register before setting the frame pointer,
17016 so we can use r7 as a temporary work register. */
020a4035 17017 if (flag_pic && arm_pic_register != INVALID_REGNUM)
e55ef7f4 17018 arm_load_pic_register (live_regs_mask);
876f13b0 17019
2591db65 17020 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
a2503645
RS		 17021 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
17022 stack_pointer_rtx);
d5b7b3ae 17023
5848830f 17024 amount = offsets->outgoing_args - offsets->saved_regs;
d5b7b3ae
RE		 17025 if (amount)
17026 {
d5b7b3ae 17027 if (amount < 512)
980e61bb
DJ		 17028 {
17029 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17030 GEN_INT (- amount)));
17031 RTX_FRAME_RELATED_P (insn) = 1;
17032 }
d5b7b3ae
RE		 17033 else
17034 {
d5b7b3ae
RE		 17035 rtx reg;
17036
17037 /* The stack decrement is too big for an immediate value in a single
17038 insn. In theory we could issue multiple subtracts, but after
17039 three of them it becomes more space efficient to place the full
17040 value in the constant pool and load into a register. (Also the
17041 ARM debugger really likes to see only one stack decrement per
17042 function). So instead we look for a scratch register into which
17043 we can load the decrement, and then we subtract this from the
17044 stack pointer. Unfortunately on the thumb the only available
17045 scratch registers are the argument registers, and we cannot use
17046 these as they may hold arguments to the function. Instead we
17047 attempt to locate a call preserved register which is used by this
17048 function. If we can find one, then we know that it will have
17049 been pushed at the start of the prologue and so we can corrupt
17050 it now. */
17051 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
35596784 17052 if (live_regs_mask & (1 << regno))
d5b7b3ae
RE		 17053 break;
17054
35596784 17055 gcc_assert(regno <= LAST_LO_REGNUM);
d5b7b3ae 17056
35596784 17057 reg = gen_rtx_REG (SImode, regno);
d5b7b3ae 17058
35596784 17059 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
980e61bb 17060
35596784
AJ		 17061 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
17062 stack_pointer_rtx, reg));
17063 RTX_FRAME_RELATED_P (insn) = 1;
17064 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
17065 plus_constant (stack_pointer_rtx,
17066 -amount));
17067 RTX_FRAME_RELATED_P (dwarf) = 1;
17068 REG_NOTES (insn)
17069 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
17070 REG_NOTES (insn));
d5b7b3ae 17071 }
2591db65
RE		 17072 }
17073
17074 if (frame_pointer_needed)
5b3e6663 17075 thumb_set_frame_pointer (offsets);
f676971a 17076
74d9c39f
DJ		 17077 /* If we are profiling, make sure no instructions are scheduled before
17078 the call to mcount. Similarly if the user has requested no
17079 scheduling in the prolog. Similarly if we want non-call exceptions
17080 using the EABI unwinder, to prevent faulting instructions from being
17081 swapped with a stack adjustment. */
e3b5732b 17082 if (crtl->profile || !TARGET_SCHED_PROLOG
74d9c39f 17083 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
d5b7b3ae 17084 emit_insn (gen_blockage ());
3c7ad43e
PB		 17085
17086 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
57934c39
PB		 17087 if (live_regs_mask & 0xff)
17088 cfun->machine->lr_save_eliminated = 0;
d5b7b3ae
RE		 17089}
17090
57934c39 17091
d5b7b3ae 17092void
5b3e6663 17093thumb1_expand_epilogue (void)
d5b7b3ae 17094{
5848830f
PB		 17095 HOST_WIDE_INT amount;
17096 arm_stack_offsets *offsets;
defc0463
RE		 17097 int regno;
17098
6d3d9133
NC		 17099 /* Naked functions don't have prologues. */
17100 if (IS_NAKED (arm_current_func_type ()))
d5b7b3ae
RE		 17101 return;
17102
5848830f
PB		 17103 offsets = arm_get_frame_offsets ();
17104 amount = offsets->outgoing_args - offsets->saved_regs;
17105
d5b7b3ae 17106 if (frame_pointer_needed)
2591db65
RE		 17107 {
17108 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
17109 amount = offsets->locals_base - offsets->saved_regs;
17110 }
e0b92319 17111
a3a531ec 17112 gcc_assert (amount >= 0);
2591db65 17113 if (amount)
d5b7b3ae 17114 {
d5b7b3ae
RE		 17115 if (amount < 512)
17116 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
17117 GEN_INT (amount)));
17118 else
17119 {
17120 /* r3 is always free in the epilogue. */
f1c25d3b 17121 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
d5b7b3ae
RE		 17122
17123 emit_insn (gen_movsi (reg, GEN_INT (amount)));
17124 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
17125 }
17126 }
f676971a 17127
d5b7b3ae
RE		 17128 /* Emit a USE (stack_pointer_rtx), so that
17129 the stack adjustment will not be deleted. */
6bacc7b0 17130 emit_insn (gen_prologue_use (stack_pointer_rtx));
d5b7b3ae 17131
e3b5732b 17132 if (crtl->profile || !TARGET_SCHED_PROLOG)
d5b7b3ae 17133 emit_insn (gen_blockage ());
defc0463
RE		 17134
17135 /* Emit a clobber for each insn that will be restored in the epilogue,
17136 so that flow2 will get register lifetimes correct. */
17137 for (regno = 0; regno < 13; regno++)
6fb5fa3c 17138 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
c41c1387 17139 emit_clobber (gen_rtx_REG (SImode, regno));
defc0463 17140
6fb5fa3c 17141 if (! df_regs_ever_live_p (LR_REGNUM))
c41c1387 17142 emit_use (gen_rtx_REG (SImode, LR_REGNUM));
d5b7b3ae
RE		 17143}
17144
08c148a8 17145static void
5b3e6663 17146thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
d5b7b3ae 17147{
954954d1 17148 arm_stack_offsets *offsets;
b279b20a
NC		 17149 unsigned long live_regs_mask = 0;
17150 unsigned long l_mask;
17151 unsigned high_regs_pushed = 0;
980e61bb 17152 int cfa_offset = 0;
d5b7b3ae
RE		 17153 int regno;
17154
6d3d9133 17155 if (IS_NAKED (arm_current_func_type ()))
d5b7b3ae
RE		 17156 return;
17157
17158 if (is_called_in_ARM_mode (current_function_decl))
17159 {
17160 const char * name;
17161
e6d29d15
NS		 17162 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
17163 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
17164 == SYMBOL_REF);
d5b7b3ae 17165 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
f676971a 17166
d5b7b3ae
RE		 17167 /* Generate code sequence to switch us into Thumb mode. */
17168 /* The .code 32 directive has already been emitted by
6d77b53e 17169 ASM_DECLARE_FUNCTION_NAME. */
d5b7b3ae
RE		 17170 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
17171 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
17172
17173 /* Generate a label, so that the debugger will notice the
17174 change in instruction sets. This label is also used by
17175 the assembler to bypass the ARM code when this function
17176 is called from a Thumb encoded function elsewhere in the
17177 same file. Hence the definition of STUB_NAME here must
d6b4baa4 17178 agree with the definition in gas/config/tc-arm.c. */
f676971a 17179
d5b7b3ae 17180#define STUB_NAME ".real_start_of"
f676971a 17181
761c70aa 17182 fprintf (f, "\t.code\t16\n");
d5b7b3ae
RE		 17183#ifdef ARM_PE
17184 if (arm_dllexport_name_p (name))
e5951263 17185 name = arm_strip_name_encoding (name);
f676971a 17186#endif
d5b7b3ae 17187 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
761c70aa 17188 fprintf (f, "\t.thumb_func\n");
d5b7b3ae
RE		 17189 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
17190 }
f676971a 17191
38173d38 17192 if (crtl->args.pretend_args_size)
d5b7b3ae 17193 {
617a1b71
PB		 17194 /* Output unwind directive for the stack adjustment. */
17195 if (ARM_EABI_UNWIND_TABLES)
17196 fprintf (f, "\t.pad #%d\n",
38173d38 17197 crtl->args.pretend_args_size);
617a1b71 17198
3cb66fd7 17199 if (cfun->machine->uses_anonymous_args)
d5b7b3ae
RE		 17200 {
17201 int num_pushes;
f676971a 17202
761c70aa 17203 fprintf (f, "\tpush\t{");
d5b7b3ae 17204
38173d38 17205 num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size);
f676971a 17206
d5b7b3ae
RE		 17207 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
17208 regno <= LAST_ARG_REGNUM;
5895f793 17209 regno++)
d5b7b3ae
RE		 17210 asm_fprintf (f, "%r%s", regno,
17211 regno == LAST_ARG_REGNUM ? "" : ", ");
17212
761c70aa 17213 fprintf (f, "}\n");
d5b7b3ae
RE		 17214 }
17215 else
f676971a 17216 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
d5b7b3ae 17217 SP_REGNUM, SP_REGNUM,
38173d38 17218 crtl->args.pretend_args_size);
980e61bb
DJ		 17219
17220 /* We don't need to record the stores for unwinding (would it
17221 help the debugger any if we did?), but record the change in
17222 the stack pointer. */
17223 if (dwarf2out_do_frame ())
17224 {
17225 char *l = dwarf2out_cfi_label ();
b279b20a 17226
38173d38 17227 cfa_offset = cfa_offset + crtl->args.pretend_args_size;
980e61bb
DJ		 17228 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
17229 }
d5b7b3ae
RE		 17230 }
17231
b279b20a 17232 /* Get the registers we are going to push. */
954954d1
PB		 17233 offsets = arm_get_frame_offsets ();
17234 live_regs_mask = offsets->saved_regs_mask;
b279b20a 17235 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
57934c39 17236 l_mask = live_regs_mask & 0x40ff;
b279b20a
NC		 17237 /* Then count how many other high registers will need to be pushed. */
17238 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
d5b7b3ae
RE		 17239
17240 if (TARGET_BACKTRACE)
17241 {
b279b20a
NC		 17242 unsigned offset;
17243 unsigned work_register;
f676971a 17244
d5b7b3ae
RE		 17245 /* We have been asked to create a stack backtrace structure.
17246 The code looks like this:
f676971a 17247
d5b7b3ae
RE		 17248 0 .align 2
17249 0 func:
17250 0 sub SP, #16 Reserve space for 4 registers.
57934c39 17251 2 push {R7} Push low registers.
d5b7b3ae
RE		 17252 4 add R7, SP, #20 Get the stack pointer before the push.
17253 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
17254 8 mov R7, PC Get hold of the start of this code plus 12.
17255 10 str R7, [SP, #16] Store it.
17256 12 mov R7, FP Get hold of the current frame pointer.
17257 14 str R7, [SP, #4] Store it.
17258 16 mov R7, LR Get hold of the current return address.
17259 18 str R7, [SP, #12] Store it.
17260 20 add R7, SP, #16 Point at the start of the backtrace structure.
17261 22 mov FP, R7 Put this value into the frame pointer. */
17262
57934c39 17263 work_register = thumb_find_work_register (live_regs_mask);
f676971a 17264
617a1b71
PB		 17265 if (ARM_EABI_UNWIND_TABLES)
17266 asm_fprintf (f, "\t.pad #16\n");
17267
d5b7b3ae
RE		 17268 asm_fprintf
17269 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
17270 SP_REGNUM, SP_REGNUM);
980e61bb
DJ		 17271
17272 if (dwarf2out_do_frame ())
17273 {
17274 char *l = dwarf2out_cfi_label ();
b279b20a 17275
980e61bb
DJ		 17276 cfa_offset = cfa_offset + 16;
17277 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
17278 }
17279
57934c39
PB		 17280 if (l_mask)
17281 {
17282 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
1a59548b 17283 offset = bit_count (l_mask) * UNITS_PER_WORD;
57934c39
PB		 17284 }
17285 else
17286 offset = 0;
f676971a 17287
d5b7b3ae 17288 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
38173d38 17289 offset + 16 + crtl->args.pretend_args_size);
f676971a 17290
d5b7b3ae
RE		 17291 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17292 offset + 4);
17293
17294 /* Make sure that the instruction fetching the PC is in the right place
17295 to calculate "start of backtrace creation code + 12". */
57934c39 17296 if (l_mask)
d5b7b3ae
RE		 17297 {
17298 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
17299 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17300 offset + 12);
17301 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
17302 ARM_HARD_FRAME_POINTER_REGNUM);
17303 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17304 offset);
17305 }
17306 else
17307 {
17308 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
17309 ARM_HARD_FRAME_POINTER_REGNUM);
17310 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17311 offset);
17312 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
17313 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17314 offset + 12);
17315 }
f676971a 17316
d5b7b3ae
RE		 17317 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
17318 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
17319 offset + 8);
17320 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
17321 offset + 12);
17322 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
17323 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
17324 }
0fa2e4df 17325 /* Optimization: If we are not pushing any low registers but we are going
b279b20a
NC		 17326 to push some high registers then delay our first push. This will just
17327 be a push of LR and we can combine it with the push of the first high
17328 register. */
17329 else if ((l_mask & 0xff) != 0
17330 || (high_regs_pushed == 0 && l_mask))
57934c39 17331 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
d5b7b3ae 17332
d5b7b3ae
RE		 17333 if (high_regs_pushed)
17334 {
b279b20a
NC		 17335 unsigned pushable_regs;
17336 unsigned next_hi_reg;
d5b7b3ae
RE		 17337
17338 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
57934c39 17339 if (live_regs_mask & (1 << next_hi_reg))
e26053d1 17340 break;
d5b7b3ae 17341
57934c39 17342 pushable_regs = l_mask & 0xff;
d5b7b3ae
RE		 17343
17344 if (pushable_regs == 0)
57934c39 17345 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
d5b7b3ae
RE		 17346
17347 while (high_regs_pushed > 0)
17348 {
b279b20a 17349 unsigned long real_regs_mask = 0;
980e61bb 17350
b279b20a 17351 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
d5b7b3ae 17352 {
57934c39 17353 if (pushable_regs & (1 << regno))
d5b7b3ae
RE		 17354 {
17355 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
f676971a 17356
b279b20a 17357 high_regs_pushed --;
980e61bb 17358 real_regs_mask |= (1 << next_hi_reg);
f676971a 17359
d5b7b3ae 17360 if (high_regs_pushed)
aeaf4d25 17361 {
b279b20a
NC		 17362 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
17363 next_hi_reg --)
57934c39 17364 if (live_regs_mask & (1 << next_hi_reg))
d5b7b3ae 17365 break;
aeaf4d25 17366 }
d5b7b3ae
RE		 17367 else
17368 {
57934c39 17369 pushable_regs &= ~((1 << regno) - 1);
d5b7b3ae
RE		 17370 break;
17371 }
17372 }
17373 }
980e61bb 17374
b279b20a
NC		 17375 /* If we had to find a work register and we have not yet
17376 saved the LR then add it to the list of regs to push. */
17377 if (l_mask == (1 << LR_REGNUM))
17378 {
17379 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
17380 1, &cfa_offset,
17381 real_regs_mask | (1 << LR_REGNUM));
17382 l_mask = 0;
17383 }
17384 else
17385 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
d5b7b3ae 17386 }
d5b7b3ae
RE		 17387 }
17388}
17389
17390/* Handle the case of a double word load into a low register from
17391 a computed memory address. The computed address may involve a
17392 register which is overwritten by the load. */
cd2b33d0 17393const char *
e32bac5b 17394thumb_load_double_from_address (rtx *operands)
d5b7b3ae
RE		 17395{
17396 rtx addr;
17397 rtx base;
17398 rtx offset;
17399 rtx arg1;
17400 rtx arg2;
f676971a 17401
e6d29d15
NS		 17402 gcc_assert (GET_CODE (operands[0]) == REG);
17403 gcc_assert (GET_CODE (operands[1]) == MEM);
d5b7b3ae
RE		 17404
17405 /* Get the memory address. */
17406 addr = XEXP (operands[1], 0);
f676971a 17407
d5b7b3ae
RE		 17408 /* Work out how the memory address is computed. */
17409 switch (GET_CODE (addr))
17410 {
17411 case REG:
31fa16b6 17412 operands[2] = adjust_address (operands[1], SImode, 4);
e0b92319 17413
d5b7b3ae
RE		 17414 if (REGNO (operands[0]) == REGNO (addr))
17415 {
17416 output_asm_insn ("ldr\t%H0, %2", operands);
17417 output_asm_insn ("ldr\t%0, %1", operands);
17418 }
17419 else
17420 {
17421 output_asm_insn ("ldr\t%0, %1", operands);
17422 output_asm_insn ("ldr\t%H0, %2", operands);
17423 }
17424 break;
f676971a 17425
d5b7b3ae
RE		 17426 case CONST:
17427 /* Compute <address> + 4 for the high order load. */
31fa16b6 17428 operands[2] = adjust_address (operands[1], SImode, 4);
e0b92319 17429
d5b7b3ae
RE		 17430 output_asm_insn ("ldr\t%0, %1", operands);
17431 output_asm_insn ("ldr\t%H0, %2", operands);
17432 break;
f676971a 17433
d5b7b3ae
RE		 17434 case PLUS:
17435 arg1 = XEXP (addr, 0);
17436 arg2 = XEXP (addr, 1);
f676971a 17437
d5b7b3ae
RE		 17438 if (CONSTANT_P (arg1))
17439 base = arg2, offset = arg1;
17440 else
17441 base = arg1, offset = arg2;
f676971a 17442
e6d29d15 17443 gcc_assert (GET_CODE (base) == REG);
d5b7b3ae
RE		 17444
17445 /* Catch the case of <address> = <reg> + <reg> */
17446 if (GET_CODE (offset) == REG)
17447 {
17448 int reg_offset = REGNO (offset);
17449 int reg_base = REGNO (base);
17450 int reg_dest = REGNO (operands[0]);
f676971a 17451
d5b7b3ae
RE		 17452 /* Add the base and offset registers together into the
17453 higher destination register. */
17454 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
17455 reg_dest + 1, reg_base, reg_offset);
f676971a 17456
d5b7b3ae
RE		 17457 /* Load the lower destination register from the address in
17458 the higher destination register. */
17459 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
17460 reg_dest, reg_dest + 1);
f676971a 17461
d5b7b3ae
RE		 17462 /* Load the higher destination register from its own address
17463 plus 4. */
17464 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
17465 reg_dest + 1, reg_dest + 1);
17466 }
17467 else
17468 {
17469 /* Compute <address> + 4 for the high order load. */
31fa16b6 17470 operands[2] = adjust_address (operands[1], SImode, 4);
f676971a 17471
d5b7b3ae
RE		 17472 /* If the computed address is held in the low order register
17473 then load the high order register first, otherwise always
17474 load the low order register first. */
17475 if (REGNO (operands[0]) == REGNO (base))
17476 {
17477 output_asm_insn ("ldr\t%H0, %2", operands);
17478 output_asm_insn ("ldr\t%0, %1", operands);
17479 }
17480 else
17481 {
17482 output_asm_insn ("ldr\t%0, %1", operands);
17483 output_asm_insn ("ldr\t%H0, %2", operands);
17484 }
17485 }
17486 break;
17487
17488 case LABEL_REF:
17489 /* With no registers to worry about we can just load the value
17490 directly. */
31fa16b6 17491 operands[2] = adjust_address (operands[1], SImode, 4);
f676971a 17492
d5b7b3ae
RE		 17493 output_asm_insn ("ldr\t%H0, %2", operands);
17494 output_asm_insn ("ldr\t%0, %1", operands);
17495 break;
f676971a 17496
d5b7b3ae 17497 default:
e6d29d15 17498 gcc_unreachable ();
d5b7b3ae 17499 }
f676971a 17500
d5b7b3ae
RE		 17501 return "";
17502}
17503
cd2b33d0 17504const char *
e32bac5b 17505thumb_output_move_mem_multiple (int n, rtx *operands)
d5b7b3ae
RE		 17506{
17507 rtx tmp;
17508
17509 switch (n)
17510 {
17511 case 2:
ca356f3a 17512 if (REGNO (operands[4]) > REGNO (operands[5]))
d5b7b3ae 17513 {
ca356f3a
RE		 17514 tmp = operands[4];
17515 operands[4] = operands[5];
17516 operands[5] = tmp;
d5b7b3ae 17517 }
ca356f3a
RE		 17518 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
17519 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
d5b7b3ae
RE		 17520 break;
17521
17522 case 3:
ca356f3a 17523 if (REGNO (operands[4]) > REGNO (operands[5]))
d5b7b3ae 17524 {
ca356f3a
RE		 17525 tmp = operands[4];
17526 operands[4] = operands[5];
17527 operands[5] = tmp;
d5b7b3ae 17528 }
ca356f3a 17529 if (REGNO (operands[5]) > REGNO (operands[6]))
d5b7b3ae 17530 {
ca356f3a
RE		 17531 tmp = operands[5];
17532 operands[5] = operands[6];
17533 operands[6] = tmp;
d5b7b3ae 17534 }
ca356f3a 17535 if (REGNO (operands[4]) > REGNO (operands[5]))
d5b7b3ae 17536 {
ca356f3a
RE		 17537 tmp = operands[4];
17538 operands[4] = operands[5];
17539 operands[5] = tmp;
d5b7b3ae 17540 }
f676971a 17541
ca356f3a
RE		 17542 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
17543 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
d5b7b3ae
RE		 17544 break;
17545
17546 default:
e6d29d15 17547 gcc_unreachable ();
d5b7b3ae
RE		 17548 }
17549
17550 return "";
17551}
17552
b12a00f1
RE		 17553/* Output a call-via instruction for thumb state. */
17554const char *
17555thumb_call_via_reg (rtx reg)
17556{
17557 int regno = REGNO (reg);
17558 rtx *labelp;
17559
57ecec57 17560 gcc_assert (regno < LR_REGNUM);
b12a00f1
RE		 17561
17562 /* If we are in the normal text section we can use a single instance
17563 per compilation unit. If we are doing function sections, then we need
17564 an entry per section, since we can't rely on reachability. */
d6b5193b 17565 if (in_section == text_section)
b12a00f1
RE		 17566 {
17567 thumb_call_reg_needed = 1;
17568
17569 if (thumb_call_via_label[regno] == NULL)
17570 thumb_call_via_label[regno] = gen_label_rtx ();
17571 labelp = thumb_call_via_label + regno;
17572 }
17573 else
17574 {
17575 if (cfun->machine->call_via[regno] == NULL)
17576 cfun->machine->call_via[regno] = gen_label_rtx ();
17577 labelp = cfun->machine->call_via + regno;
17578 }
17579
17580 output_asm_insn ("bl\t%a0", labelp);
17581 return "";
17582}
17583
1d6e90ac 17584/* Routines for generating rtl. */
d5b7b3ae 17585void
70128ad9 17586thumb_expand_movmemqi (rtx *operands)
d5b7b3ae
RE		 17587{
17588 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
17589 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
17590 HOST_WIDE_INT len = INTVAL (operands[2]);
17591 HOST_WIDE_INT offset = 0;
17592
17593 while (len >= 12)
17594 {
ca356f3a 17595 emit_insn (gen_movmem12b (out, in, out, in));
d5b7b3ae
RE		 17596 len -= 12;
17597 }
f676971a 17598
d5b7b3ae
RE		 17599 if (len >= 8)
17600 {
ca356f3a 17601 emit_insn (gen_movmem8b (out, in, out, in));
d5b7b3ae
RE		 17602 len -= 8;
17603 }
f676971a 17604
d5b7b3ae
RE		 17605 if (len >= 4)
17606 {
17607 rtx reg = gen_reg_rtx (SImode);
f1c25d3b
KH		 17608 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
17609 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
d5b7b3ae
RE		 17610 len -= 4;
17611 offset += 4;
17612 }
f676971a 17613
d5b7b3ae
RE		 17614 if (len >= 2)
17615 {
17616 rtx reg = gen_reg_rtx (HImode);
f676971a 17617 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
f1c25d3b
KH		 17618 plus_constant (in, offset))));
17619 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
d5b7b3ae
RE		 17620 reg));
17621 len -= 2;
17622 offset += 2;
17623 }
f676971a 17624
d5b7b3ae
RE		 17625 if (len)
17626 {
17627 rtx reg = gen_reg_rtx (QImode);
f1c25d3b
KH		 17628 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
17629 plus_constant (in, offset))));
17630 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
d5b7b3ae
RE		 17631 reg));
17632 }
17633}
17634
d5b7b3ae 17635void
e32bac5b 17636thumb_reload_out_hi (rtx *operands)
d5b7b3ae
RE		 17637{
17638 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
17639}
17640
f676971a 17641/* Handle reading a half-word from memory during reload. */
d5b7b3ae 17642void
e32bac5b 17643thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
d5b7b3ae 17644{
e6d29d15 17645 gcc_unreachable ();
d5b7b3ae
RE		 17646}
17647
c27ba912
DM		 17648/* Return the length of a function name prefix
17649 that starts with the character 'c'. */
17650static int
e32bac5b 17651arm_get_strip_length (int c)
c27ba912
DM		 17652{
17653 switch (c)
17654 {
17655 ARM_NAME_ENCODING_LENGTHS
f676971a 17656 default: return 0;
c27ba912
DM		 17657 }
17658}
17659
17660/* Return a pointer to a function's name with any
17661 and all prefix encodings stripped from it. */
17662const char *
e32bac5b 17663arm_strip_name_encoding (const char *name)
c27ba912
DM		 17664{
17665 int skip;
f676971a 17666
c27ba912
DM		 17667 while ((skip = arm_get_strip_length (* name)))
17668 name += skip;
17669
17670 return name;
17671}
17672
e1944073
KW		 17673/* If there is a '*' anywhere in the name's prefix, then
17674 emit the stripped name verbatim, otherwise prepend an
17675 underscore if leading underscores are being used. */
e1944073 17676void
e32bac5b 17677arm_asm_output_labelref (FILE *stream, const char *name)
e1944073
KW		 17678{
17679 int skip;
17680 int verbatim = 0;
17681
17682 while ((skip = arm_get_strip_length (* name)))
17683 {
17684 verbatim |= (*name == '*');
17685 name += skip;
17686 }
17687
17688 if (verbatim)
17689 fputs (name, stream);
17690 else
17691 asm_fprintf (stream, "%U%s", name);
17692}
17693
6c6aa1af
PB		 17694static void
17695arm_file_start (void)
17696{
17697 int val;
17698
5b3e6663
PB		 17699 if (TARGET_UNIFIED_ASM)
17700 asm_fprintf (asm_out_file, "\t.syntax unified\n");
17701
6c6aa1af
PB		 17702 if (TARGET_BPABI)
17703 {
17704 const char *fpu_name;
17705 if (arm_select[0].string)
17706 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
17707 else if (arm_select[1].string)
17708 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
17709 else
17710 asm_fprintf (asm_out_file, "\t.cpu %s\n",
17711 all_cores[arm_default_cpu].name);
17712
17713 if (TARGET_SOFT_FLOAT)
17714 {
17715 if (TARGET_VFP)
17716 fpu_name = "softvfp";
17717 else
17718 fpu_name = "softfpa";
17719 }
17720 else
17721 {
f1adb0a9 17722 int set_float_abi_attributes = 0;
6c6aa1af
PB		 17723 switch (arm_fpu_arch)
17724 {
17725 case FPUTYPE_FPA:
17726 fpu_name = "fpa";
17727 break;
17728 case FPUTYPE_FPA_EMU2:
17729 fpu_name = "fpe2";
17730 break;
17731 case FPUTYPE_FPA_EMU3:
17732 fpu_name = "fpe3";
17733 break;
17734 case FPUTYPE_MAVERICK:
17735 fpu_name = "maverick";
17736 break;
17737 case FPUTYPE_VFP:
6c6aa1af 17738 fpu_name = "vfp";
f1adb0a9
JB		 17739 set_float_abi_attributes = 1;
17740 break;
17741 case FPUTYPE_VFP3:
17742 fpu_name = "vfp3";
17743 set_float_abi_attributes = 1;
6c6aa1af 17744 break;
88f77cba
JB		 17745 case FPUTYPE_NEON:
17746 fpu_name = "neon";
17747 set_float_abi_attributes = 1;
17748 break;
6c6aa1af
PB		 17749 default:
17750 abort();
17751 }
f1adb0a9
JB		 17752 if (set_float_abi_attributes)
17753 {
17754 if (TARGET_HARD_FLOAT)
17755 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
17756 if (TARGET_HARD_FLOAT_ABI)
17757 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
17758 }
6c6aa1af
PB		 17759 }
17760 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
17761
17762 /* Some of these attributes only apply when the corresponding features
17763 are used. However we don't have any easy way of figuring this out.
17764 Conservatively record the setting that would have been used. */
17765
6c6aa1af
PB		 17766 /* Tag_ABI_FP_rounding. */
17767 if (flag_rounding_math)
17768 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
17769 if (!flag_unsafe_math_optimizations)
17770 {
17771 /* Tag_ABI_FP_denomal. */
17772 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
17773 /* Tag_ABI_FP_exceptions. */
17774 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
17775 }
17776 /* Tag_ABI_FP_user_exceptions. */
17777 if (flag_signaling_nans)
17778 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
17779 /* Tag_ABI_FP_number_model. */
17780 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
17781 flag_finite_math_only ? 1 : 3);
17782
17783 /* Tag_ABI_align8_needed. */
17784 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
17785 /* Tag_ABI_align8_preserved. */
17786 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
17787 /* Tag_ABI_enum_size. */
17788 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
17789 flag_short_enums ? 1 : 2);
17790
17791 /* Tag_ABI_optimization_goals. */
17792 if (optimize_size)
17793 val = 4;
17794 else if (optimize >= 2)
17795 val = 2;
17796 else if (optimize)
17797 val = 1;
17798 else
17799 val = 6;
17800 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
b76c3c4b
PB		 17801
17802 if (arm_lang_output_object_attributes_hook)
17803 arm_lang_output_object_attributes_hook();
6c6aa1af
PB		 17804 }
17805 default_file_start();
17806}
17807
b12a00f1
RE		 17808static void
17809arm_file_end (void)
17810{
17811 int regno;
17812
978e411f
CD		 17813 if (NEED_INDICATE_EXEC_STACK)
17814 /* Add .note.GNU-stack. */
17815 file_end_indicate_exec_stack ();
17816
b12a00f1
RE		 17817 if (! thumb_call_reg_needed)
17818 return;
17819
d6b5193b 17820 switch_to_section (text_section);
b12a00f1
RE		 17821 asm_fprintf (asm_out_file, "\t.code 16\n");
17822 ASM_OUTPUT_ALIGN (asm_out_file, 1);
17823
57ecec57 17824 for (regno = 0; regno < LR_REGNUM; regno++)
b12a00f1
RE		 17825 {
17826 rtx label = thumb_call_via_label[regno];
17827
17828 if (label != 0)
17829 {
17830 targetm.asm_out.internal_label (asm_out_file, "L",
17831 CODE_LABEL_NUMBER (label));
17832 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
17833 }
17834 }
17835}
17836
fb49053f
RH		 17837#ifndef ARM_PE
17838/* Symbols in the text segment can be accessed without indirecting via the
17839 constant pool; it may take an extra binary operation, but this is still
17840 faster than indirecting via memory. Don't do this when not optimizing,
17841 since we won't be calculating al of the offsets necessary to do this
17842 simplification. */
17843
17844static void
e32bac5b 17845arm_encode_section_info (tree decl, rtx rtl, int first)
fb49053f 17846{
3521b33c 17847 if (optimize > 0 && TREE_CONSTANT (decl))
c6a2438a 17848 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
fb49053f 17849
d3585b76 17850 default_encode_section_info (decl, rtl, first);
fb49053f
RH		 17851}
17852#endif /* !ARM_PE */
483ab821 17853
4977bab6 17854static void
e32bac5b 17855arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
4977bab6
ZW		 17856{
17857 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
17858 && !strcmp (prefix, "L"))
17859 {
17860 arm_ccfsm_state = 0;
17861 arm_target_insn = NULL;
17862 }
17863 default_internal_label (stream, prefix, labelno);
17864}
17865
c590b625
RH		 17866/* Output code to add DELTA to the first argument, and then jump
17867 to FUNCTION. Used for C++ multiple inheritance. */
c590b625 17868static void
e32bac5b
RE		 17869arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
17870 HOST_WIDE_INT delta,
17871 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
17872 tree function)
483ab821 17873{
9b66ebb1
PB		 17874 static int thunk_label = 0;
17875 char label[256];
54b9e939 17876 char labelpc[256];
483ab821
MM		 17877 int mi_delta = delta;
17878 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
17879 int shift = 0;
61f71b34 17880 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
483ab821
MM		 17881 ? 1 : 0);
17882 if (mi_delta < 0)
17883 mi_delta = - mi_delta;
bf98ec6c 17884
5b3e6663 17885 if (TARGET_THUMB1)
9b66ebb1
PB		 17886 {
17887 int labelno = thunk_label++;
17888 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
bf98ec6c
PB		 17889 /* Thunks are entered in arm mode when avaiable. */
17890 if (TARGET_THUMB1_ONLY)
17891 {
17892 /* push r3 so we can use it as a temporary. */
17893 /* TODO: Omit this save if r3 is not used. */
17894 fputs ("\tpush {r3}\n", file);
17895 fputs ("\tldr\tr3, ", file);
17896 }
17897 else
17898 {
17899 fputs ("\tldr\tr12, ", file);
17900 }
9b66ebb1
PB		 17901 assemble_name (file, label);
17902 fputc ('\n', file);
54b9e939
KH		 17903 if (flag_pic)
17904 {
17905 /* If we are generating PIC, the ldr instruction below loads
17906 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
17907 the address of the add + 8, so we have:
17908
17909 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
17910 = target + 1.
17911
17912 Note that we have "+ 1" because some versions of GNU ld
17913 don't set the low bit of the result for R_ARM_REL32
bf98ec6c
PB		 17914 relocations against thumb function symbols.
17915 On ARMv6M this is +4, not +8. */
54b9e939
KH		 17916 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
17917 assemble_name (file, labelpc);
17918 fputs (":\n", file);
bf98ec6c
PB		 17919 if (TARGET_THUMB1_ONLY)
17920 {
17921 /* This is 2 insns after the start of the thunk, so we know it
17922 is 4-byte aligned. */
17923 fputs ("\tadd\tr3, pc, r3\n", file);
17924 fputs ("\tmov r12, r3\n", file);
17925 }
17926 else
17927 fputs ("\tadd\tr12, pc, r12\n", file);
54b9e939 17928 }
bf98ec6c
PB		 17929 else if (TARGET_THUMB1_ONLY)
17930 fputs ("\tmov r12, r3\n", file);
9b66ebb1 17931 }
bf98ec6c 17932 if (TARGET_THUMB1_ONLY)
483ab821 17933 {
bf98ec6c
PB		 17934 if (mi_delta > 255)
17935 {
17936 fputs ("\tldr\tr3, ", file);
17937 assemble_name (file, label);
17938 fputs ("+4\n", file);
17939 asm_fprintf (file, "\t%s\t%r, %r, r3\n",
17940 mi_op, this_regno, this_regno);
17941 }
17942 else if (mi_delta != 0)
17943 {
17944 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
17945 mi_op, this_regno, this_regno,
17946 mi_delta);
17947 }
17948 }
17949 else
17950 {
17951 /* TODO: Use movw/movt for large constants when available. */
17952 while (mi_delta != 0)
17953 {
17954 if ((mi_delta & (3 << shift)) == 0)
17955 shift += 2;
17956 else
17957 {
17958 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
17959 mi_op, this_regno, this_regno,
17960 mi_delta & (0xff << shift));
17961 mi_delta &= ~(0xff << shift);
17962 shift += 8;
17963 }
17964 }
483ab821 17965 }
5b3e6663 17966 if (TARGET_THUMB1)
9b66ebb1 17967 {
bf98ec6c
PB		 17968 if (TARGET_THUMB1_ONLY)
17969 fputs ("\tpop\t{r3}\n", file);
17970
9b66ebb1
PB		 17971 fprintf (file, "\tbx\tr12\n");
17972 ASM_OUTPUT_ALIGN (file, 2);
17973 assemble_name (file, label);
17974 fputs (":\n", file);
54b9e939
KH		 17975 if (flag_pic)
17976 {
17977 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
17978 rtx tem = XEXP (DECL_RTL (function), 0);
17979 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
17980 tem = gen_rtx_MINUS (GET_MODE (tem),
17981 tem,
17982 gen_rtx_SYMBOL_REF (Pmode,
17983 ggc_strdup (labelpc)));
17984 assemble_integer (tem, 4, BITS_PER_WORD, 1);
17985 }
17986 else
17987 /* Output ".word .LTHUNKn". */
17988 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
bf98ec6c
PB		 17989
17990 if (TARGET_THUMB1_ONLY && mi_delta > 255)
17991 assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1);
9b66ebb1
PB		 17992 }
17993 else
17994 {
17995 fputs ("\tb\t", file);
17996 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
17997 if (NEED_PLT_RELOC)
17998 fputs ("(PLT)", file);
17999 fputc ('\n', file);
18000 }
483ab821 18001}
5a9335ef
NC		 18002
18003int
6f5f2481 18004arm_emit_vector_const (FILE *file, rtx x)
5a9335ef
NC		 18005{
18006 int i;
18007 const char * pattern;
18008
e6d29d15 18009 gcc_assert (GET_CODE (x) == CONST_VECTOR);
5a9335ef
NC		 18010
18011 switch (GET_MODE (x))
18012 {
18013 case V2SImode: pattern = "%08x"; break;
18014 case V4HImode: pattern = "%04x"; break;
18015 case V8QImode: pattern = "%02x"; break;
e6d29d15 18016 default: gcc_unreachable ();
5a9335ef
NC		 18017 }
18018
18019 fprintf (file, "0x");
18020 for (i = CONST_VECTOR_NUNITS (x); i--;)
18021 {
18022 rtx element;
18023
18024 element = CONST_VECTOR_ELT (x, i);
18025 fprintf (file, pattern, INTVAL (element));
18026 }
18027
18028 return 1;
18029}
18030
18031const char *
6f5f2481 18032arm_output_load_gr (rtx *operands)
5a9335ef
NC		 18033{
18034 rtx reg;
18035 rtx offset;
18036 rtx wcgr;
18037 rtx sum;
f676971a 18038
5a9335ef
NC		 18039 if (GET_CODE (operands [1]) != MEM
18040 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
18041 || GET_CODE (reg = XEXP (sum, 0)) != REG
18042 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
18043 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
18044 return "wldrw%?\t%0, %1";
f676971a
EC		 18045
18046 /* Fix up an out-of-range load of a GR register. */
5a9335ef
NC		 18047 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
18048 wcgr = operands[0];
18049 operands[0] = reg;
18050 output_asm_insn ("ldr%?\t%0, %1", operands);
18051
18052 operands[0] = wcgr;
18053 operands[1] = reg;
18054 output_asm_insn ("tmcr%?\t%0, %1", operands);
18055 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
18056
18057 return "";
18058}
f9ba5949 18059
1cc9f5f5
KH		 18060/* Worker function for TARGET_SETUP_INCOMING_VARARGS.
18061
18062 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
18063 named arg and all anonymous args onto the stack.
18064 XXX I know the prologue shouldn't be pushing registers, but it is faster
18065 that way. */
18066
18067static void
18068arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
22ccaaee
JJ		 18069 enum machine_mode mode,
18070 tree type,
1cc9f5f5
KH		 18071 int *pretend_size,
18072 int second_time ATTRIBUTE_UNUSED)
18073{
22ccaaee
JJ		 18074 int nregs = cum->nregs;
18075 if (nregs & 1
18076 && ARM_DOUBLEWORD_ALIGN
18077 && arm_needs_doubleword_align (mode, type))
18078 nregs++;
18079
1cc9f5f5 18080 cfun->machine->uses_anonymous_args = 1;
22ccaaee
JJ		 18081 if (nregs < NUM_ARG_REGS)
18082 *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
1cc9f5f5 18083}
9b66ebb1 18084
59b9a953 18085/* Return nonzero if the CONSUMER instruction (a store) does not need
9b66ebb1
PB		 18086 PRODUCER's value to calculate the address. */
18087
18088int
18089arm_no_early_store_addr_dep (rtx producer, rtx consumer)
18090{
18091 rtx value = PATTERN (producer);
18092 rtx addr = PATTERN (consumer);
18093
18094 if (GET_CODE (value) == COND_EXEC)
18095 value = COND_EXEC_CODE (value);
18096 if (GET_CODE (value) == PARALLEL)
18097 value = XVECEXP (value, 0, 0);
18098 value = XEXP (value, 0);
18099 if (GET_CODE (addr) == COND_EXEC)
18100 addr = COND_EXEC_CODE (addr);
18101 if (GET_CODE (addr) == PARALLEL)
18102 addr = XVECEXP (addr, 0, 0);
18103 addr = XEXP (addr, 0);
f676971a 18104
9b66ebb1
PB		 18105 return !reg_overlap_mentioned_p (value, addr);
18106}
18107
59b9a953 18108/* Return nonzero if the CONSUMER instruction (an ALU op) does not
9b66ebb1
PB		 18109 have an early register shift value or amount dependency on the
18110 result of PRODUCER. */
18111
18112int
18113arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
18114{
18115 rtx value = PATTERN (producer);
18116 rtx op = PATTERN (consumer);
18117 rtx early_op;
18118
18119 if (GET_CODE (value) == COND_EXEC)
18120 value = COND_EXEC_CODE (value);
18121 if (GET_CODE (value) == PARALLEL)
18122 value = XVECEXP (value, 0, 0);
18123 value = XEXP (value, 0);
18124 if (GET_CODE (op) == COND_EXEC)
18125 op = COND_EXEC_CODE (op);
18126 if (GET_CODE (op) == PARALLEL)
18127 op = XVECEXP (op, 0, 0);
18128 op = XEXP (op, 1);
f676971a 18129
9b66ebb1
PB		 18130 early_op = XEXP (op, 0);
18131 /* This is either an actual independent shift, or a shift applied to
18132 the first operand of another operation. We want the whole shift
18133 operation. */
18134 if (GET_CODE (early_op) == REG)
18135 early_op = op;
18136
18137 return !reg_overlap_mentioned_p (value, early_op);
18138}
18139
59b9a953 18140/* Return nonzero if the CONSUMER instruction (an ALU op) does not
9b66ebb1
PB		 18141 have an early register shift value dependency on the result of
18142 PRODUCER. */
18143
18144int
18145arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
18146{
18147 rtx value = PATTERN (producer);
18148 rtx op = PATTERN (consumer);
18149 rtx early_op;
18150
18151 if (GET_CODE (value) == COND_EXEC)
18152 value = COND_EXEC_CODE (value);
18153 if (GET_CODE (value) == PARALLEL)
18154 value = XVECEXP (value, 0, 0);
18155 value = XEXP (value, 0);
18156 if (GET_CODE (op) == COND_EXEC)
18157 op = COND_EXEC_CODE (op);
18158 if (GET_CODE (op) == PARALLEL)
18159 op = XVECEXP (op, 0, 0);
18160 op = XEXP (op, 1);
f676971a 18161
9b66ebb1
PB		 18162 early_op = XEXP (op, 0);
18163
18164 /* This is either an actual independent shift, or a shift applied to
18165 the first operand of another operation. We want the value being
18166 shifted, in either case. */
18167 if (GET_CODE (early_op) != REG)
18168 early_op = XEXP (early_op, 0);
f676971a 18169
9b66ebb1
PB		 18170 return !reg_overlap_mentioned_p (value, early_op);
18171}
18172
59b9a953 18173/* Return nonzero if the CONSUMER (a mul or mac op) does not
9b66ebb1
PB		 18174 have an early register mult dependency on the result of
18175 PRODUCER. */
18176
18177int
18178arm_no_early_mul_dep (rtx producer, rtx consumer)
18179{
18180 rtx value = PATTERN (producer);
18181 rtx op = PATTERN (consumer);
18182
18183 if (GET_CODE (value) == COND_EXEC)
18184 value = COND_EXEC_CODE (value);
18185 if (GET_CODE (value) == PARALLEL)
18186 value = XVECEXP (value, 0, 0);
18187 value = XEXP (value, 0);
18188 if (GET_CODE (op) == COND_EXEC)
18189 op = COND_EXEC_CODE (op);
18190 if (GET_CODE (op) == PARALLEL)
18191 op = XVECEXP (op, 0, 0);
18192 op = XEXP (op, 1);
f676971a 18193
9b66ebb1
PB		 18194 return (GET_CODE (op) == PLUS
18195 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
18196}
18197
70301b45
PB		 18198/* We can't rely on the caller doing the proper promotion when
18199 using APCS or ATPCS. */
18200
18201static bool
586de218 18202arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED)
70301b45 18203{
b6685939 18204 return !TARGET_AAPCS_BASED;
70301b45
PB		 18205}
18206
6b045785
PB		 18207
18208/* AAPCS based ABIs use short enums by default. */
18209
18210static bool
18211arm_default_short_enums (void)
18212{
077fc835 18213 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
6b045785 18214}
13c1cd82
PB		 18215
18216
18217/* AAPCS requires that anonymous bitfields affect structure alignment. */
18218
18219static bool
18220arm_align_anon_bitfield (void)
18221{
18222 return TARGET_AAPCS_BASED;
18223}
4185ae53
PB		 18224
18225
18226/* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
18227
18228static tree
18229arm_cxx_guard_type (void)
18230{
18231 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
18232}
18233
c956e102
MS		 18234/* Return non-zero if the consumer (a multiply-accumulate instruction)
18235 has an accumulator dependency on the result of the producer (a
18236 multiplication instruction) and no other dependency on that result. */
18237int
18238arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer)
18239{
18240 rtx mul = PATTERN (producer);
18241 rtx mac = PATTERN (consumer);
18242 rtx mul_result;
18243 rtx mac_op0, mac_op1, mac_acc;
18244
18245 if (GET_CODE (mul) == COND_EXEC)
18246 mul = COND_EXEC_CODE (mul);
18247 if (GET_CODE (mac) == COND_EXEC)
18248 mac = COND_EXEC_CODE (mac);
18249
18250 /* Check that mul is of the form (set (...) (mult ...))
18251 and mla is of the form (set (...) (plus (mult ...) (...))). */
18252 if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT)
18253 || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS
18254 || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT))
18255 return 0;
18256
18257 mul_result = XEXP (mul, 0);
18258 mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0);
18259 mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1);
18260 mac_acc = XEXP (XEXP (mac, 1), 1);
18261
18262 return (reg_overlap_mentioned_p (mul_result, mac_acc)
18263 && !reg_overlap_mentioned_p (mul_result, mac_op0)
18264 && !reg_overlap_mentioned_p (mul_result, mac_op1));
18265}
18266
4185ae53 18267
0fa2e4df 18268/* The EABI says test the least significant bit of a guard variable. */
4185ae53
PB		 18269
18270static bool
18271arm_cxx_guard_mask_bit (void)
18272{
18273 return TARGET_AAPCS_BASED;
18274}
46e995e0
PB		 18275
18276
18277/* The EABI specifies that all array cookies are 8 bytes long. */
18278
18279static tree
18280arm_get_cookie_size (tree type)
18281{
18282 tree size;
18283
18284 if (!TARGET_AAPCS_BASED)
18285 return default_cxx_get_cookie_size (type);
18286
7d60be94 18287 size = build_int_cst (sizetype, 8);
46e995e0
PB		 18288 return size;
18289}
18290
18291
18292/* The EABI says that array cookies should also contain the element size. */
18293
18294static bool
18295arm_cookie_has_size (void)
18296{
18297 return TARGET_AAPCS_BASED;
18298}
44d10c10
PB		 18299
18300
18301/* The EABI says constructors and destructors should return a pointer to
18302 the object constructed/destroyed. */
18303
18304static bool
18305arm_cxx_cdtor_returns_this (void)
18306{
18307 return TARGET_AAPCS_BASED;
18308}
c9ca9b88 18309
505970fc
MM		 18310/* The EABI says that an inline function may never be the key
18311 method. */
18312
18313static bool
18314arm_cxx_key_method_may_be_inline (void)
18315{
18316 return !TARGET_AAPCS_BASED;
18317}
18318
1e731102
MM		 18319static void
18320arm_cxx_determine_class_data_visibility (tree decl)
18321{
711b2998
JB		 18322 if (!TARGET_AAPCS_BASED
18323 || !TARGET_DLLIMPORT_DECL_ATTRIBUTES)
1e731102 18324 return;
505970fc 18325
1e731102
MM		 18326 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
18327 is exported. However, on systems without dynamic vague linkage,
18328 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
18329 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
18330 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
18331 else
18332 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
18333 DECL_VISIBILITY_SPECIFIED (decl) = 1;
18334}
e0b92319 18335
505970fc 18336static bool
1e731102 18337arm_cxx_class_data_always_comdat (void)
505970fc 18338{
1e731102
MM		 18339 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
18340 vague linkage if the class has no key function. */
18341 return !TARGET_AAPCS_BASED;
505970fc 18342}
c9ca9b88 18343
9f62c3e3
PB		 18344
18345/* The EABI says __aeabi_atexit should be used to register static
18346 destructors. */
18347
18348static bool
18349arm_cxx_use_aeabi_atexit (void)
18350{
18351 return TARGET_AAPCS_BASED;
18352}
18353
18354
c9ca9b88
PB		 18355void
18356arm_set_return_address (rtx source, rtx scratch)
18357{
18358 arm_stack_offsets *offsets;
18359 HOST_WIDE_INT delta;
18360 rtx addr;
18361 unsigned long saved_regs;
18362
954954d1
PB		 18363 offsets = arm_get_frame_offsets ();
18364 saved_regs = offsets->saved_regs_mask;
c9ca9b88
PB		 18365
18366 if ((saved_regs & (1 << LR_REGNUM)) == 0)
18367 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
18368 else
18369 {
18370 if (frame_pointer_needed)
18371 addr = plus_constant(hard_frame_pointer_rtx, -4);
18372 else
18373 {
18374 /* LR will be the first saved register. */
c9ca9b88
PB		 18375 delta = offsets->outgoing_args - (offsets->frame + 4);
18376
f676971a 18377
c9ca9b88
PB		 18378 if (delta >= 4096)
18379 {
18380 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
18381 GEN_INT (delta & ~4095)));
18382 addr = scratch;
18383 delta &= 4095;
18384 }
18385 else
18386 addr = stack_pointer_rtx;
18387
18388 addr = plus_constant (addr, delta);
18389 }
31fa16b6 18390 emit_move_insn (gen_frame_mem (Pmode, addr), source);
c9ca9b88
PB		 18391 }
18392}
18393
18394
18395void
18396thumb_set_return_address (rtx source, rtx scratch)
18397{
18398 arm_stack_offsets *offsets;
c9ca9b88 18399 HOST_WIDE_INT delta;
5b3e6663 18400 HOST_WIDE_INT limit;
c9ca9b88
PB		 18401 int reg;
18402 rtx addr;
57934c39 18403 unsigned long mask;
c9ca9b88 18404
c41c1387 18405 emit_use (source);
c9ca9b88 18406
954954d1
PB		 18407 offsets = arm_get_frame_offsets ();
18408 mask = offsets->saved_regs_mask;
57934c39 18409 if (mask & (1 << LR_REGNUM))
c9ca9b88 18410 {
5b3e6663 18411 limit = 1024;
c9ca9b88
PB		 18412 /* Find the saved regs. */
18413 if (frame_pointer_needed)
18414 {
18415 delta = offsets->soft_frame - offsets->saved_args;
18416 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
5b3e6663
PB		 18417 if (TARGET_THUMB1)
18418 limit = 128;
c9ca9b88
PB		 18419 }
18420 else
18421 {
18422 delta = offsets->outgoing_args - offsets->saved_args;
18423 reg = SP_REGNUM;
18424 }
18425 /* Allow for the stack frame. */
5b3e6663 18426 if (TARGET_THUMB1 && TARGET_BACKTRACE)
c9ca9b88
PB		 18427 delta -= 16;
18428 /* The link register is always the first saved register. */
18429 delta -= 4;
f676971a 18430
c9ca9b88
PB		 18431 /* Construct the address. */
18432 addr = gen_rtx_REG (SImode, reg);
5b3e6663 18433 if (delta > limit)
c9ca9b88
PB		 18434 {
18435 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
18436 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
18437 addr = scratch;
18438 }
18439 else
18440 addr = plus_constant (addr, delta);
18441
31fa16b6 18442 emit_move_insn (gen_frame_mem (Pmode, addr), source);
c9ca9b88
PB		 18443 }
18444 else
18445 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
18446}
18447
f676971a
EC		 18448/* Implements target hook vector_mode_supported_p. */
18449bool
18450arm_vector_mode_supported_p (enum machine_mode mode)
18451{
88f77cba
JB		 18452 /* Neon also supports V2SImode, etc. listed in the clause below. */
18453 if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode
18454 || mode == V16QImode || mode == V4SFmode || mode == V2DImode))
18455 return true;
18456
f676971a
EC		 18457 if ((mode == V2SImode)
18458 || (mode == V4HImode)
18459 || (mode == V8QImode))
18460 return true;
18461
18462 return false;
18463}
273a2526
RS		 18464
18465/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
18466 ARM insns and therefore guarantee that the shift count is modulo 256.
18467 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
18468 guarantee no particular behavior for out-of-range counts. */
18469
18470static unsigned HOST_WIDE_INT
18471arm_shift_truncation_mask (enum machine_mode mode)
18472{
18473 return mode == SImode ? 255 : 0;
18474}
2fa330b2
PB		 18475
18476
18477/* Map internal gcc register numbers to DWARF2 register numbers. */
18478
18479unsigned int
18480arm_dbx_register_number (unsigned int regno)
18481{
18482 if (regno < 16)
18483 return regno;
18484
18485 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
18486 compatibility. The EABI defines them as registers 96-103. */
18487 if (IS_FPA_REGNUM (regno))
18488 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
18489
f1adb0a9 18490 /* FIXME: VFPv3 register numbering. */
2fa330b2
PB		 18491 if (IS_VFP_REGNUM (regno))
18492 return 64 + regno - FIRST_VFP_REGNUM;
18493
18494 if (IS_IWMMXT_GR_REGNUM (regno))
18495 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
18496
18497 if (IS_IWMMXT_REGNUM (regno))
18498 return 112 + regno - FIRST_IWMMXT_REGNUM;
18499
e6d29d15 18500 gcc_unreachable ();
2fa330b2
PB		 18501}
18502
617a1b71
PB		 18503
18504#ifdef TARGET_UNWIND_INFO
5b3e6663
PB		 18505/* Emit unwind directives for a store-multiple instruction or stack pointer
18506 push during alignment.
18507 These should only ever be generated by the function prologue code, so
18508 expect them to have a particular form. */
617a1b71
PB		 18509
18510static void
5b3e6663 18511arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
617a1b71
PB		 18512{
18513 int i;
18514 HOST_WIDE_INT offset;
18515 HOST_WIDE_INT nregs;
18516 int reg_size;
18517 unsigned reg;
18518 unsigned lastreg;
18519 rtx e;
18520
617a1b71 18521 e = XVECEXP (p, 0, 0);
5b3e6663
PB		 18522 if (GET_CODE (e) != SET)
18523 abort ();
18524
18525 /* First insn will adjust the stack pointer. */
617a1b71
PB		 18526 if (GET_CODE (e) != SET
18527 || GET_CODE (XEXP (e, 0)) != REG
18528 || REGNO (XEXP (e, 0)) != SP_REGNUM
18529 || GET_CODE (XEXP (e, 1)) != PLUS)
18530 abort ();
18531
18532 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
18533 nregs = XVECLEN (p, 0) - 1;
18534
18535 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
18536 if (reg < 16)
18537 {
18538 /* The function prologue may also push pc, but not annotate it as it is
569b7f6a 18539 never restored. We turn this into a stack pointer adjustment. */
617a1b71
PB		 18540 if (nregs * 4 == offset - 4)
18541 {
18542 fprintf (asm_out_file, "\t.pad #4\n");
18543 offset -= 4;
18544 }
18545 reg_size = 4;
8edfc4cc 18546 fprintf (asm_out_file, "\t.save {");
617a1b71
PB		 18547 }
18548 else if (IS_VFP_REGNUM (reg))
18549 {
617a1b71 18550 reg_size = 8;
8edfc4cc 18551 fprintf (asm_out_file, "\t.vsave {");
617a1b71
PB		 18552 }
18553 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
18554 {
18555 /* FPA registers are done differently. */
ea40ba9c 18556 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
617a1b71
PB		 18557 return;
18558 }
18559 else
18560 /* Unknown register type. */
18561 abort ();
18562
18563 /* If the stack increment doesn't match the size of the saved registers,
18564 something has gone horribly wrong. */
18565 if (offset != nregs * reg_size)
18566 abort ();
18567
617a1b71
PB		 18568 offset = 0;
18569 lastreg = 0;
18570 /* The remaining insns will describe the stores. */
18571 for (i = 1; i <= nregs; i++)
18572 {
18573 /* Expect (set (mem <addr>) (reg)).
18574 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
18575 e = XVECEXP (p, 0, i);
18576 if (GET_CODE (e) != SET
18577 || GET_CODE (XEXP (e, 0)) != MEM
18578 || GET_CODE (XEXP (e, 1)) != REG)
18579 abort ();
e0b92319 18580
617a1b71
PB		 18581 reg = REGNO (XEXP (e, 1));
18582 if (reg < lastreg)
18583 abort ();
e0b92319 18584
617a1b71
PB		 18585 if (i != 1)
18586 fprintf (asm_out_file, ", ");
18587 /* We can't use %r for vfp because we need to use the
18588 double precision register names. */
18589 if (IS_VFP_REGNUM (reg))
18590 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
18591 else
18592 asm_fprintf (asm_out_file, "%r", reg);
18593
18594#ifdef ENABLE_CHECKING
18595 /* Check that the addresses are consecutive. */
18596 e = XEXP (XEXP (e, 0), 0);
18597 if (GET_CODE (e) == PLUS)
18598 {
18599 offset += reg_size;
18600 if (GET_CODE (XEXP (e, 0)) != REG
18601 || REGNO (XEXP (e, 0)) != SP_REGNUM
18602 || GET_CODE (XEXP (e, 1)) != CONST_INT
18603 || offset != INTVAL (XEXP (e, 1)))
18604 abort ();
18605 }
18606 else if (i != 1
18607 || GET_CODE (e) != REG
18608 || REGNO (e) != SP_REGNUM)
18609 abort ();
18610#endif
18611 }
18612 fprintf (asm_out_file, "}\n");
18613}
18614
18615/* Emit unwind directives for a SET. */
18616
18617static void
18618arm_unwind_emit_set (FILE * asm_out_file, rtx p)
18619{
18620 rtx e0;
18621 rtx e1;
5b3e6663 18622 unsigned reg;
617a1b71
PB		 18623
18624 e0 = XEXP (p, 0);
18625 e1 = XEXP (p, 1);
18626 switch (GET_CODE (e0))
18627 {
18628 case MEM:
18629 /* Pushing a single register. */
18630 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
18631 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
18632 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
18633 abort ();
18634
18635 asm_fprintf (asm_out_file, "\t.save ");
18636 if (IS_VFP_REGNUM (REGNO (e1)))
18637 asm_fprintf(asm_out_file, "{d%d}\n",
18638 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
18639 else
18640 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
18641 break;
18642
18643 case REG:
18644 if (REGNO (e0) == SP_REGNUM)
18645 {
18646 /* A stack increment. */
18647 if (GET_CODE (e1) != PLUS
18648 || GET_CODE (XEXP (e1, 0)) != REG
18649 || REGNO (XEXP (e1, 0)) != SP_REGNUM
18650 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
18651 abort ();
18652
ea40ba9c 18653 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
617a1b71
PB		 18654 -INTVAL (XEXP (e1, 1)));
18655 }
18656 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
18657 {
18658 HOST_WIDE_INT offset;
e0b92319 18659
617a1b71
PB		 18660 if (GET_CODE (e1) == PLUS)
18661 {
18662 if (GET_CODE (XEXP (e1, 0)) != REG
18663 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
18664 abort ();
18665 reg = REGNO (XEXP (e1, 0));
18666 offset = INTVAL (XEXP (e1, 1));
ea40ba9c 18667 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
617a1b71
PB		 18668 HARD_FRAME_POINTER_REGNUM, reg,
18669 INTVAL (XEXP (e1, 1)));
18670 }
18671 else if (GET_CODE (e1) == REG)
18672 {
18673 reg = REGNO (e1);
18674 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
18675 HARD_FRAME_POINTER_REGNUM, reg);
18676 }
18677 else
18678 abort ();
18679 }
18680 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
18681 {
18682 /* Move from sp to reg. */
18683 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
18684 }
758ed9b2
PB		 18685 else if (GET_CODE (e1) == PLUS
18686 && GET_CODE (XEXP (e1, 0)) == REG
18687 && REGNO (XEXP (e1, 0)) == SP_REGNUM
18688 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
18689 {
18690 /* Set reg to offset from sp. */
18691 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
18692 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
18693 }
5b3e6663
PB		 18694 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
18695 {
18696 /* Stack pointer save before alignment. */
18697 reg = REGNO (e0);
18698 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
18699 reg + 0x90, reg);
18700 }
617a1b71
PB		 18701 else
18702 abort ();
18703 break;
18704
18705 default:
18706 abort ();
18707 }
18708}
18709
18710
18711/* Emit unwind directives for the given insn. */
18712
18713static void
18714arm_unwind_emit (FILE * asm_out_file, rtx insn)
18715{
18716 rtx pat;
18717
18718 if (!ARM_EABI_UNWIND_TABLES)
18719 return;
18720
e3b5732b 18721 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
80efdb6a 18722 && (TREE_NOTHROW (current_function_decl)
ad516a74 18723 || crtl->all_throwers_are_sibcalls))
80efdb6a
PB		 18724 return;
18725
617a1b71
PB		 18726 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
18727 return;
18728
18729 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
18730 if (pat)
18731 pat = XEXP (pat, 0);
18732 else
18733 pat = PATTERN (insn);
18734
18735 switch (GET_CODE (pat))
18736 {
18737 case SET:
18738 arm_unwind_emit_set (asm_out_file, pat);
18739 break;
18740
18741 case SEQUENCE:
18742 /* Store multiple. */
5b3e6663 18743 arm_unwind_emit_sequence (asm_out_file, pat);
617a1b71
PB		 18744 break;
18745
18746 default:
18747 abort();
18748 }
18749}
18750
18751
18752/* Output a reference from a function exception table to the type_info
18753 object X. The EABI specifies that the symbol should be relocated by
18754 an R_ARM_TARGET2 relocation. */
18755
18756static bool
18757arm_output_ttype (rtx x)
18758{
18759 fputs ("\t.word\t", asm_out_file);
18760 output_addr_const (asm_out_file, x);
18761 /* Use special relocations for symbol references. */
18762 if (GET_CODE (x) != CONST_INT)
18763 fputs ("(TARGET2)", asm_out_file);
18764 fputc ('\n', asm_out_file);
18765
18766 return TRUE;
18767}
18768#endif /* TARGET_UNWIND_INFO */
18769
18770
5b3e6663
PB		 18771/* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
18772 stack alignment. */
18773
18774static void
18775arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
18776{
18777 rtx unspec = SET_SRC (pattern);
18778 gcc_assert (GET_CODE (unspec) == UNSPEC);
18779
18780 switch (index)
18781 {
18782 case UNSPEC_STACK_ALIGN:
18783 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
18784 put anything on the stack, so hopefully it won't matter.
18785 CFA = SP will be correct after alignment. */
18786 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
18787 SET_DEST (pattern));
18788 break;
18789 default:
18790 gcc_unreachable ();
18791 }
18792}
18793
18794
617a1b71
PB		 18795/* Output unwind directives for the start/end of a function. */
18796
18797void
18798arm_output_fn_unwind (FILE * f, bool prologue)
18799{
18800 if (!ARM_EABI_UNWIND_TABLES)
18801 return;
18802
18803 if (prologue)
18804 fputs ("\t.fnstart\n", f);
18805 else
80efdb6a
PB		 18806 {
18807 /* If this function will never be unwound, then mark it as such.
18808 The came condition is used in arm_unwind_emit to suppress
18809 the frame annotations. */
e3b5732b 18810 if (!(flag_unwind_tables || crtl->uses_eh_lsda)
80efdb6a 18811 && (TREE_NOTHROW (current_function_decl)
ad516a74 18812 || crtl->all_throwers_are_sibcalls))
80efdb6a
PB		 18813 fputs("\t.cantunwind\n", f);
18814
18815 fputs ("\t.fnend\n", f);
18816 }
617a1b71 18817}
d3585b76
DJ		 18818
18819static bool
18820arm_emit_tls_decoration (FILE *fp, rtx x)
18821{
18822 enum tls_reloc reloc;
18823 rtx val;
18824
18825 val = XVECEXP (x, 0, 0);
18826 reloc = INTVAL (XVECEXP (x, 0, 1));
18827
18828 output_addr_const (fp, val);
18829
18830 switch (reloc)
18831 {
18832 case TLS_GD32:
18833 fputs ("(tlsgd)", fp);
18834 break;
18835 case TLS_LDM32:
18836 fputs ("(tlsldm)", fp);
18837 break;
18838 case TLS_LDO32:
18839 fputs ("(tlsldo)", fp);
18840 break;
18841 case TLS_IE32:
18842 fputs ("(gottpoff)", fp);
18843 break;
18844 case TLS_LE32:
18845 fputs ("(tpoff)", fp);
18846 break;
18847 default:
18848 gcc_unreachable ();
18849 }
18850
18851 switch (reloc)
18852 {
18853 case TLS_GD32:
18854 case TLS_LDM32:
18855 case TLS_IE32:
18856 fputs (" + (. - ", fp);
18857 output_addr_const (fp, XVECEXP (x, 0, 2));
18858 fputs (" - ", fp);
18859 output_addr_const (fp, XVECEXP (x, 0, 3));
18860 fputc (')', fp);
18861 break;
18862 default:
18863 break;
18864 }
18865
18866 return TRUE;
18867}
18868
afcc986d
JM		 18869/* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
18870
18871static void
18872arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
18873{
18874 gcc_assert (size == 4);
18875 fputs ("\t.word\t", file);
18876 output_addr_const (file, x);
18877 fputs ("(tlsldo)", file);
18878}
18879
d3585b76
DJ		 18880bool
18881arm_output_addr_const_extra (FILE *fp, rtx x)
18882{
18883 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
18884 return arm_emit_tls_decoration (fp, x);
f16fe45f
DJ		 18885 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
18886 {
18887 char label[256];
18888 int labelno = INTVAL (XVECEXP (x, 0, 0));
18889
18890 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
18891 assemble_name_raw (fp, label);
18892
18893 return TRUE;
18894 }
d3585b76
DJ		 18895 else if (GET_CODE (x) == CONST_VECTOR)
18896 return arm_emit_vector_const (fp, x);
18897
18898 return FALSE;
18899}
18900
5b3e6663
PB		 18901/* Output assembly for a shift instruction.
18902 SET_FLAGS determines how the instruction modifies the condition codes.
7a085dce 18903 0 - Do not set condition codes.
5b3e6663
PB		 18904 1 - Set condition codes.
18905 2 - Use smallest instruction. */
18906const char *
18907arm_output_shift(rtx * operands, int set_flags)
18908{
18909 char pattern[100];
18910 static const char flag_chars[3] = {'?', '.', '!'};
18911 const char *shift;
18912 HOST_WIDE_INT val;
18913 char c;
18914
18915 c = flag_chars[set_flags];
18916 if (TARGET_UNIFIED_ASM)
18917 {
18918 shift = shift_op(operands[3], &val);
18919 if (shift)
18920 {
18921 if (val != -1)
18922 operands[2] = GEN_INT(val);
18923 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
18924 }
18925 else
18926 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
18927 }
18928 else
18929 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
18930 output_asm_insn (pattern, operands);
18931 return "";
18932}
18933
18934/* Output a Thumb-2 casesi instruction. */
18935const char *
18936thumb2_output_casesi (rtx *operands)
18937{
18938 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
18939
18940 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
18941
18942 output_asm_insn ("cmp\t%0, %1", operands);
18943 output_asm_insn ("bhi\t%l3", operands);
18944 switch (GET_MODE(diff_vec))
18945 {
18946 case QImode:
18947 return "tbb\t[%|pc, %0]";
18948 case HImode:
18949 return "tbh\t[%|pc, %0, lsl #1]";
18950 case SImode:
18951 if (flag_pic)
18952 {
18953 output_asm_insn ("adr\t%4, %l2", operands);
18954 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
18955 output_asm_insn ("add\t%4, %4, %5", operands);
18956 return "bx\t%4";
18957 }
18958 else
18959 {
18960 output_asm_insn ("adr\t%4, %l2", operands);
18961 return "ldr\t%|pc, [%4, %0, lsl #2]";
18962 }
18963 default:
18964 gcc_unreachable ();
18965 }
18966}
18967
bd4dc3cd
PB		 18968/* Most ARM cores are single issue, but some newer ones can dual issue.
18969 The scheduler descriptions rely on this being correct. */
18970static int
18971arm_issue_rate (void)
18972{
18973 switch (arm_tune)
18974 {
18975 case cortexr4:
18976 case cortexa8:
18977 return 2;
18978
18979 default:
18980 return 1;
18981 }
18982}
18983
608063c3
JB		 18984/* A table and a function to perform ARM-specific name mangling for
18985 NEON vector types in order to conform to the AAPCS (see "Procedure
18986 Call Standard for the ARM Architecture", Appendix A). To qualify
18987 for emission with the mangled names defined in that document, a
18988 vector type must not only be of the correct mode but also be
18989 composed of NEON vector element types (e.g. __builtin_neon_qi). */
18990typedef struct
18991{
18992 enum machine_mode mode;
18993 const char *element_type_name;
18994 const char *aapcs_name;
18995} arm_mangle_map_entry;
18996
18997static arm_mangle_map_entry arm_mangle_map[] = {
18998 /* 64-bit containerized types. */
18999 { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" },
19000 { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" },
19001 { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" },
19002 { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" },
19003 { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" },
19004 { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" },
19005 { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" },
19006 { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" },
19007 { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" },
19008 /* 128-bit containerized types. */
19009 { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" },
19010 { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" },
19011 { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" },
19012 { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" },
19013 { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" },
19014 { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" },
19015 { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" },
19016 { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" },
19017 { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" },
19018 { VOIDmode, NULL, NULL }
19019};
19020
19021const char *
3101faab 19022arm_mangle_type (const_tree type)
608063c3
JB		 19023{
19024 arm_mangle_map_entry *pos = arm_mangle_map;
19025
19026 if (TREE_CODE (type) != VECTOR_TYPE)
19027 return NULL;
19028
19029 /* Check the mode of the vector type, and the name of the vector
19030 element type, against the table. */
19031 while (pos->mode != VOIDmode)
19032 {
19033 tree elt_type = TREE_TYPE (type);
19034
19035 if (pos->mode == TYPE_MODE (type)
19036 && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL
19037 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))),
19038 pos->element_type_name))
19039 return pos->aapcs_name;
19040
19041 pos++;
19042 }
19043
19044 /* Use the default mangling for unrecognized (possibly user-defined)
19045 vector types. */
19046 return NULL;
19047}
19048
795dc4fc
PB		 19049/* Order of allocation of core registers for Thumb: this allocation is
19050 written over the corresponding initial entries of the array
19051 initialized with REG_ALLOC_ORDER. We allocate all low registers
19052 first. Saving and restoring a low register is usually cheaper than
19053 using a call-clobbered high register. */
19054
19055static const int thumb_core_reg_alloc_order[] =
19056{
19057 3, 2, 1, 0, 4, 5, 6, 7,
19058 14, 12, 8, 9, 10, 11, 13, 15
19059};
19060
19061/* Adjust register allocation order when compiling for Thumb. */
19062
19063void
19064arm_order_regs_for_local_alloc (void)
19065{
19066 const int arm_reg_alloc_order[] = REG_ALLOC_ORDER;
19067 memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order));
19068 if (TARGET_THUMB)
19069 memcpy (reg_alloc_order, thumb_core_reg_alloc_order,
19070 sizeof (thumb_core_reg_alloc_order));
19071}
19072
d3585b76 19073#include "gt-arm.h"
GNU Compiler Collection
This page took 5.932291 seconds and 5 git commands to generate.