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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
020a4035 | 3 | 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 7 | |
4f448245 | 8 | This file is part of GCC. |
cce8749e | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
12 | by the Free Software Foundation; either version 2, or (at your | |
13 | option) any later version. | |
cce8749e | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
cce8749e | 19 | |
4f448245 NC |
20 | You should have received a copy of the GNU General Public License |
21 | along with GCC; see the file COPYING. If not, write to | |
39d14dda KC |
22 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
23 | Boston, MA 02110-1301, USA. */ | |
f676971a | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
980e61bb | 53 | #include "debug.h" |
6e34d3a3 | 54 | #include "langhooks.h" |
cce8749e | 55 | |
d5b7b3ae RE |
56 | /* Forward definitions of types. */ |
57 | typedef struct minipool_node Mnode; | |
58 | typedef struct minipool_fixup Mfix; | |
59 | ||
1d6e90ac NC |
60 | const struct attribute_spec arm_attribute_table[]; |
61 | ||
d5b7b3ae | 62 | /* Forward function declarations. */ |
5848830f | 63 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 64 | static void arm_add_gc_roots (void); |
a406f566 MM |
65 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
66 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
67 | static unsigned bit_count (unsigned long); |
68 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 69 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
e32bac5b RE |
70 | static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); |
71 | inline static int thumb_index_register_rtx_p (rtx, int); | |
5848830f | 72 | static int thumb_far_jump_used_p (void); |
57934c39 | 73 | static bool thumb_force_lr_save (void); |
e32bac5b | 74 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 75 | static rtx emit_sfm (int, int); |
4f5dfed0 | 76 | static int arm_size_return_regs (void); |
301d03af | 77 | #ifndef AOF_ASSEMBLER |
e32bac5b | 78 | static bool arm_assemble_integer (rtx, unsigned int, int); |
301d03af | 79 | #endif |
e32bac5b RE |
80 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
81 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
82 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
83 | static rtx is_jump_table (rtx); | |
84 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
85 | int, HOST_WIDE_INT); | |
e32bac5b RE |
86 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
87 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 88 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
89 | static rtx is_jump_table (rtx); |
90 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
91 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
92 | static Mnode *add_minipool_forward_ref (Mfix *); | |
93 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
94 | static Mnode *add_minipool_backward_ref (Mfix *); | |
95 | static void assign_minipool_offsets (Mfix *); | |
96 | static void arm_print_value (FILE *, rtx); | |
97 | static void dump_minipool (rtx); | |
98 | static int arm_barrier_cost (rtx); | |
99 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
100 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
101 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
102 | rtx); | |
103 | static void arm_reorg (void); | |
104 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
105 | static int current_file_function_operand (rtx); | |
106 | static unsigned long arm_compute_save_reg0_reg12_mask (void); | |
107 | static unsigned long arm_compute_save_reg_mask (void); | |
108 | static unsigned long arm_isr_value (tree); | |
109 | static unsigned long arm_compute_func_type (void); | |
110 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
111 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
7bff66a7 | 112 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 113 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 114 | #endif |
e32bac5b RE |
115 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
116 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
117 | static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); | |
118 | static int arm_comp_type_attributes (tree, tree); | |
119 | static void arm_set_default_type_attributes (tree); | |
120 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
121 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
122 | static int arm_get_strip_length (int); | |
123 | static bool arm_function_ok_for_sibcall (tree, tree); | |
124 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
125 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
126 | tree); | |
127 | static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); | |
21b5653c | 128 | static bool arm_size_rtx_costs (rtx, int, int, int *); |
9b66ebb1 PB |
129 | static bool arm_slowmul_rtx_costs (rtx, int, int, int *); |
130 | static bool arm_fastmul_rtx_costs (rtx, int, int, int *); | |
131 | static bool arm_xscale_rtx_costs (rtx, int, int, int *); | |
132 | static bool arm_9e_rtx_costs (rtx, int, int, int *); | |
e32bac5b RE |
133 | static int arm_address_cost (rtx); |
134 | static bool arm_memory_load_p (rtx); | |
135 | static bool arm_cirrus_insn_p (rtx); | |
136 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
137 | static void arm_init_builtins (void); |
138 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
139 | static void arm_init_iwmmxt_builtins (void); | |
140 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
141 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
142 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
143 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 144 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 145 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
146 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
147 | tree, bool); | |
5a9335ef | 148 | |
7abc66b1 JB |
149 | #ifdef OBJECT_FORMAT_ELF |
150 | static void arm_elf_asm_constructor (rtx, int); | |
151 | #endif | |
fb49053f | 152 | #ifndef ARM_PE |
e32bac5b | 153 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 154 | #endif |
b12a00f1 RE |
155 | |
156 | static void arm_file_end (void); | |
157 | ||
5eb99654 | 158 | #ifdef AOF_ASSEMBLER |
e32bac5b RE |
159 | static void aof_globalize_label (FILE *, const char *); |
160 | static void aof_dump_imports (FILE *); | |
161 | static void aof_dump_pic_table (FILE *); | |
1bc7c5b6 | 162 | static void aof_file_start (void); |
e32bac5b | 163 | static void aof_file_end (void); |
d6b5193b | 164 | static void aof_asm_init_sections (void); |
5eb99654 | 165 | #endif |
f9ba5949 | 166 | static rtx arm_struct_value_rtx (tree, int); |
1cc9f5f5 KH |
167 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
168 | tree, int *, int); | |
8cd5a4e0 RH |
169 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
170 | enum machine_mode, tree, bool); | |
70301b45 | 171 | static bool arm_promote_prototypes (tree); |
6b045785 | 172 | static bool arm_default_short_enums (void); |
13c1cd82 | 173 | static bool arm_align_anon_bitfield (void); |
866af8a9 JB |
174 | static bool arm_return_in_msb (tree); |
175 | static bool arm_must_pass_in_stack (enum machine_mode, tree); | |
617a1b71 PB |
176 | #ifdef TARGET_UNWIND_INFO |
177 | static void arm_unwind_emit (FILE *, rtx); | |
178 | static bool arm_output_ttype (rtx); | |
179 | #endif | |
c237e94a | 180 | |
4185ae53 PB |
181 | static tree arm_cxx_guard_type (void); |
182 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
183 | static tree arm_get_cookie_size (tree); |
184 | static bool arm_cookie_has_size (void); | |
44d10c10 | 185 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 186 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
187 | static void arm_cxx_determine_class_data_visibility (tree); |
188 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 189 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 190 | static void arm_init_libfuncs (void); |
c54c7322 | 191 | static bool arm_handle_option (size_t, const char *, int); |
273a2526 | 192 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
193 | static bool arm_cannot_copy_insn_p (rtx); |
194 | static bool arm_tls_symbol_p (rtx x); | |
195 | ||
672a6f42 NB |
196 | \f |
197 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 198 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 199 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
200 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
201 | #endif | |
f3bb6135 | 202 | |
1d6e90ac | 203 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 204 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 205 | |
b12a00f1 RE |
206 | #undef TARGET_ASM_FILE_END |
207 | #define TARGET_ASM_FILE_END arm_file_end | |
208 | ||
301d03af | 209 | #ifdef AOF_ASSEMBLER |
1d6e90ac | 210 | #undef TARGET_ASM_BYTE_OP |
301d03af | 211 | #define TARGET_ASM_BYTE_OP "\tDCB\t" |
1d6e90ac | 212 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 213 | #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" |
1d6e90ac | 214 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 215 | #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" |
5eb99654 KG |
216 | #undef TARGET_ASM_GLOBALIZE_LABEL |
217 | #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label | |
1bc7c5b6 ZW |
218 | #undef TARGET_ASM_FILE_START |
219 | #define TARGET_ASM_FILE_START aof_file_start | |
a5fe455b ZW |
220 | #undef TARGET_ASM_FILE_END |
221 | #define TARGET_ASM_FILE_END aof_file_end | |
301d03af | 222 | #else |
1d6e90ac | 223 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 224 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 225 | #undef TARGET_ASM_INTEGER |
301d03af RS |
226 | #define TARGET_ASM_INTEGER arm_assemble_integer |
227 | #endif | |
228 | ||
1d6e90ac | 229 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
230 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
231 | ||
1d6e90ac | 232 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
233 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
234 | ||
c54c7322 RS |
235 | #undef TARGET_DEFAULT_TARGET_FLAGS |
236 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
237 | #undef TARGET_HANDLE_OPTION | |
238 | #define TARGET_HANDLE_OPTION arm_handle_option | |
239 | ||
1d6e90ac | 240 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
241 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
242 | ||
1d6e90ac | 243 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
244 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
245 | ||
1d6e90ac | 246 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
247 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
248 | ||
fb49053f RH |
249 | #undef TARGET_ENCODE_SECTION_INFO |
250 | #ifdef ARM_PE | |
251 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
252 | #else | |
253 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
254 | #endif | |
255 | ||
5a9335ef | 256 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
257 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
258 | ||
5a9335ef | 259 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
260 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
261 | ||
5a9335ef | 262 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
263 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
264 | ||
5a9335ef | 265 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 266 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 267 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 268 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 269 | |
9b66ebb1 | 270 | /* This will be overridden in arm_override_options. */ |
5a9335ef | 271 | #undef TARGET_RTX_COSTS |
9b66ebb1 | 272 | #define TARGET_RTX_COSTS arm_slowmul_rtx_costs |
5a9335ef | 273 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 274 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 275 | |
273a2526 RS |
276 | #undef TARGET_SHIFT_TRUNCATION_MASK |
277 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
278 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
279 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
280 | ||
5a9335ef | 281 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
282 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
283 | ||
5a9335ef NC |
284 | #undef TARGET_INIT_BUILTINS |
285 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
286 | #undef TARGET_EXPAND_BUILTIN | |
287 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
288 | ||
b3f8d95d MM |
289 | #undef TARGET_INIT_LIBFUNCS |
290 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
291 | ||
f9ba5949 KH |
292 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
293 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
d4453b7a PB |
294 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
295 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
f9ba5949 | 296 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 297 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
298 | #undef TARGET_PASS_BY_REFERENCE |
299 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
300 | #undef TARGET_ARG_PARTIAL_BYTES |
301 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
f9ba5949 KH |
302 | |
303 | #undef TARGET_STRUCT_VALUE_RTX | |
304 | #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx | |
305 | ||
1cc9f5f5 KH |
306 | #undef TARGET_SETUP_INCOMING_VARARGS |
307 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
308 | ||
6b045785 PB |
309 | #undef TARGET_DEFAULT_SHORT_ENUMS |
310 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
311 | ||
13c1cd82 PB |
312 | #undef TARGET_ALIGN_ANON_BITFIELD |
313 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
314 | ||
4185ae53 PB |
315 | #undef TARGET_CXX_GUARD_TYPE |
316 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
317 | ||
318 | #undef TARGET_CXX_GUARD_MASK_BIT | |
319 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
320 | ||
46e995e0 PB |
321 | #undef TARGET_CXX_GET_COOKIE_SIZE |
322 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
323 | ||
324 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
325 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
326 | ||
44d10c10 PB |
327 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
328 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
329 | ||
505970fc MM |
330 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
331 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
332 | ||
9f62c3e3 PB |
333 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
334 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
335 | ||
1e731102 MM |
336 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
337 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
338 | arm_cxx_determine_class_data_visibility | |
339 | ||
340 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
341 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 342 | |
866af8a9 JB |
343 | #undef TARGET_RETURN_IN_MSB |
344 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
345 | ||
346 | #undef TARGET_MUST_PASS_IN_STACK | |
347 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
348 | ||
617a1b71 PB |
349 | #ifdef TARGET_UNWIND_INFO |
350 | #undef TARGET_UNWIND_EMIT | |
351 | #define TARGET_UNWIND_EMIT arm_unwind_emit | |
352 | ||
353 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
354 | #undef TARGET_ASM_TTYPE | |
355 | #define TARGET_ASM_TTYPE arm_output_ttype | |
356 | ||
357 | #undef TARGET_ARM_EABI_UNWINDER | |
358 | #define TARGET_ARM_EABI_UNWINDER true | |
359 | #endif /* TARGET_UNWIND_INFO */ | |
360 | ||
d3585b76 DJ |
361 | #undef TARGET_CANNOT_COPY_INSN_P |
362 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
363 | ||
364 | #ifdef HAVE_AS_TLS | |
365 | #undef TARGET_HAVE_TLS | |
366 | #define TARGET_HAVE_TLS true | |
367 | #endif | |
368 | ||
369 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
370 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p | |
371 | ||
f6897b10 | 372 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 373 | \f |
c7319d87 RE |
374 | /* Obstack for minipool constant handling. */ |
375 | static struct obstack minipool_obstack; | |
1d6e90ac | 376 | static char * minipool_startobj; |
c7319d87 | 377 | |
1d6e90ac NC |
378 | /* The maximum number of insns skipped which |
379 | will be conditionalised if possible. */ | |
c27ba912 DM |
380 | static int max_insns_skipped = 5; |
381 | ||
382 | extern FILE * asm_out_file; | |
383 | ||
6354dc9b | 384 | /* True if we are currently building a constant table. */ |
13bd191d PB |
385 | int making_const_table; |
386 | ||
60d0536b | 387 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 388 | stored from the compare operation. */ |
ff9940b0 | 389 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 390 | |
9b66ebb1 PB |
391 | /* The processor for which instructions should be scheduled. */ |
392 | enum processor_type arm_tune = arm_none; | |
393 | ||
394 | /* Which floating point model to use. */ | |
395 | enum arm_fp_model arm_fp_model; | |
bee06f3d | 396 | |
9b66ebb1 | 397 | /* Which floating point hardware is available. */ |
29ad9694 | 398 | enum fputype arm_fpu_arch; |
b111229a | 399 | |
9b66ebb1 PB |
400 | /* Which floating point hardware to schedule for. */ |
401 | enum fputype arm_fpu_tune; | |
402 | ||
403 | /* Whether to use floating point hardware. */ | |
404 | enum float_abi_type arm_float_abi; | |
405 | ||
5848830f PB |
406 | /* Which ABI to use. */ |
407 | enum arm_abi_type arm_abi; | |
408 | ||
d3585b76 DJ |
409 | /* Which thread pointer model to use. */ |
410 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
411 | ||
b355a481 | 412 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 413 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 414 | |
b12a00f1 | 415 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 416 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
417 | static int thumb_call_reg_needed; |
418 | ||
aec3cfba | 419 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 420 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 421 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
422 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
423 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
424 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
425 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
426 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
427 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
428 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 429 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 430 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 431 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 432 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
433 | media instructions. */ |
434 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
435 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
436 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 437 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
aec3cfba | 438 | |
9b66ebb1 PB |
439 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
440 | ||
78011587 PB |
441 | #define FL_FOR_ARCH2 0 |
442 | #define FL_FOR_ARCH3 FL_MODE32 | |
443 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) | |
444 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
445 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
446 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
447 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
448 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
449 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
450 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
451 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
452 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 453 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 454 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 455 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
78011587 | 456 | |
1d6e90ac NC |
457 | /* The bits in this mask specify which |
458 | instructions we are allowed to generate. */ | |
0977774b | 459 | static unsigned long insn_flags = 0; |
d5b7b3ae | 460 | |
aec3cfba | 461 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 462 | be used. */ |
0977774b | 463 | static unsigned long tune_flags = 0; |
aec3cfba NC |
464 | |
465 | /* The following are used in the arm.md file as equivalents to bits | |
466 | in the above two flag variables. */ | |
467 | ||
9b66ebb1 PB |
468 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
469 | int arm_arch3m = 0; | |
2b835d68 | 470 | |
6354dc9b | 471 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
472 | int arm_arch4 = 0; |
473 | ||
68d560d4 RE |
474 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
475 | int arm_arch4t = 0; | |
476 | ||
6354dc9b | 477 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
478 | int arm_arch5 = 0; |
479 | ||
b15bca31 RE |
480 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
481 | int arm_arch5e = 0; | |
482 | ||
9b66ebb1 PB |
483 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
484 | int arm_arch6 = 0; | |
485 | ||
d3585b76 DJ |
486 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
487 | int arm_arch6k = 0; | |
488 | ||
aec3cfba | 489 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
490 | int arm_ld_sched = 0; |
491 | ||
492 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 493 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 494 | |
78011587 PB |
495 | /* Nonzero if this chip is a Cirrus variant. */ |
496 | int arm_arch_cirrus = 0; | |
497 | ||
5a9335ef NC |
498 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
499 | int arm_arch_iwmmxt = 0; | |
500 | ||
d19fb8e3 | 501 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
502 | int arm_arch_xscale = 0; |
503 | ||
504 | /* Nonzero if tuning for XScale */ | |
505 | int arm_tune_xscale = 0; | |
d19fb8e3 | 506 | |
e0b92319 | 507 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 508 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 509 | int arm_tune_wbuf = 0; |
b111229a | 510 | |
0616531f RE |
511 | /* Nonzero if generating Thumb instructions. */ |
512 | int thumb_code = 0; | |
513 | ||
2ad4dcf9 | 514 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 515 | preprocessor. |
2ad4dcf9 RE |
516 | XXX This is a bit of a hack, it's intended to help work around |
517 | problems in GLD which doesn't understand that armv5t code is | |
518 | interworking clean. */ | |
519 | int arm_cpp_interwork = 0; | |
520 | ||
cce8749e CH |
521 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
522 | must report the mode of the memory reference from PRINT_OPERAND to | |
523 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 524 | enum machine_mode output_memory_reference_mode; |
cce8749e | 525 | |
32de079a | 526 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 527 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 528 | |
ff9940b0 | 529 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 530 | is not needed. */ |
d5b7b3ae | 531 | int return_used_this_function; |
ff9940b0 | 532 | |
aec3cfba NC |
533 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
534 | the next function. */ | |
4b632bf1 RE |
535 | static int after_arm_reorg = 0; |
536 | ||
aec3cfba | 537 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
538 | static int arm_constant_limit = 3; |
539 | ||
cce8749e CH |
540 | /* For an explanation of these variables, see final_prescan_insn below. */ |
541 | int arm_ccfsm_state; | |
84ed5e79 | 542 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
543 | rtx arm_target_insn; |
544 | int arm_target_label; | |
9997d19d RE |
545 | |
546 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 547 | static const char * const arm_condition_codes[] = |
9997d19d RE |
548 | { |
549 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
550 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
551 | }; | |
552 | ||
f5a1b0d2 | 553 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
2b835d68 | 554 | \f |
6354dc9b | 555 | /* Initialization code. */ |
2b835d68 | 556 | |
2b835d68 RE |
557 | struct processors |
558 | { | |
8b60264b | 559 | const char *const name; |
9b66ebb1 | 560 | enum processor_type core; |
78011587 | 561 | const char *arch; |
0977774b | 562 | const unsigned long flags; |
9b66ebb1 | 563 | bool (* rtx_costs) (rtx, int, int, int *); |
2b835d68 RE |
564 | }; |
565 | ||
566 | /* Not all of these give usefully different compilation alternatives, | |
567 | but there is no simple way of generalizing them. */ | |
8b60264b | 568 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
569 | { |
570 | /* ARM Cores */ | |
d98a72fd RE |
571 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
572 | {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | |
9b66ebb1 PB |
573 | #include "arm-cores.def" |
574 | #undef ARM_CORE | |
78011587 | 575 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
576 | }; |
577 | ||
8b60264b | 578 | static const struct processors all_architectures[] = |
2b835d68 | 579 | { |
f5a1b0d2 | 580 | /* ARM Architectures */ |
9b66ebb1 PB |
581 | /* We don't specify rtx_costs here as it will be figured out |
582 | from the core. */ | |
f676971a | 583 | |
78011587 PB |
584 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
585 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
586 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
587 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
588 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
589 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
590 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
591 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
592 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
593 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
594 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
595 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
596 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
597 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
598 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
599 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
600 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
78011587 PB |
601 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
602 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
603 | {NULL, arm_none, NULL, 0 , NULL} | |
f5a1b0d2 NC |
604 | }; |
605 | ||
c54c7322 RS |
606 | struct arm_cpu_select |
607 | { | |
608 | const char * string; | |
609 | const char * name; | |
610 | const struct processors * processors; | |
611 | }; | |
612 | ||
9a9f7594 | 613 | /* This is a magic structure. The 'string' field is magically filled in |
f5a1b0d2 NC |
614 | with a pointer to the value specified by the user on the command line |
615 | assuming that the user has specified such a value. */ | |
616 | ||
c54c7322 | 617 | static struct arm_cpu_select arm_select[] = |
f5a1b0d2 | 618 | { |
f676971a | 619 | /* string name processors */ |
f5a1b0d2 NC |
620 | { NULL, "-mcpu=", all_cores }, |
621 | { NULL, "-march=", all_architectures }, | |
622 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
623 | }; |
624 | ||
e6fffade RE |
625 | /* Defines representing the indexes into the above table. */ |
626 | #define ARM_OPT_SET_CPU 0 | |
627 | #define ARM_OPT_SET_ARCH 1 | |
628 | #define ARM_OPT_SET_TUNE 2 | |
78011587 PB |
629 | |
630 | /* The name of the proprocessor macro to define for this architecture. */ | |
631 | ||
632 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
633 | ||
9b66ebb1 PB |
634 | struct fpu_desc |
635 | { | |
636 | const char * name; | |
637 | enum fputype fpu; | |
638 | }; | |
639 | ||
640 | ||
56f42830 | 641 | /* Available values for -mfpu=. */ |
9b66ebb1 PB |
642 | |
643 | static const struct fpu_desc all_fpus[] = | |
644 | { | |
645 | {"fpa", FPUTYPE_FPA}, | |
646 | {"fpe2", FPUTYPE_FPA_EMU2}, | |
647 | {"fpe3", FPUTYPE_FPA_EMU2}, | |
648 | {"maverick", FPUTYPE_MAVERICK}, | |
649 | {"vfp", FPUTYPE_VFP} | |
650 | }; | |
651 | ||
652 | ||
653 | /* Floating point models used by the different hardware. | |
654 | See fputype in arm.h. */ | |
655 | ||
656 | static const enum fputype fp_model_for_fpu[] = | |
657 | { | |
658 | /* No FP hardware. */ | |
659 | ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ | |
660 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ | |
661 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ | |
662 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ | |
663 | ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ | |
664 | ARM_FP_MODEL_VFP /* FPUTYPE_VFP */ | |
665 | }; | |
666 | ||
667 | ||
668 | struct float_abi | |
669 | { | |
670 | const char * name; | |
671 | enum float_abi_type abi_type; | |
672 | }; | |
673 | ||
674 | ||
675 | /* Available values for -mfloat-abi=. */ | |
676 | ||
677 | static const struct float_abi all_float_abis[] = | |
678 | { | |
679 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
680 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
681 | {"hard", ARM_FLOAT_ABI_HARD} | |
682 | }; | |
683 | ||
684 | ||
5848830f PB |
685 | struct abi_name |
686 | { | |
687 | const char *name; | |
688 | enum arm_abi_type abi_type; | |
689 | }; | |
690 | ||
691 | ||
692 | /* Available values for -mabi=. */ | |
693 | ||
694 | static const struct abi_name arm_all_abis[] = | |
695 | { | |
696 | {"apcs-gnu", ARM_ABI_APCS}, | |
697 | {"atpcs", ARM_ABI_ATPCS}, | |
698 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
699 | {"iwmmxt", ARM_ABI_IWMMXT}, |
700 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
701 | }; |
702 | ||
d3585b76 DJ |
703 | /* Supported TLS relocations. */ |
704 | ||
705 | enum tls_reloc { | |
706 | TLS_GD32, | |
707 | TLS_LDM32, | |
708 | TLS_LDO32, | |
709 | TLS_IE32, | |
710 | TLS_LE32 | |
711 | }; | |
712 | ||
d66437c5 RE |
713 | /* Emit an insn that's a simple single-set. Both the operands must be known |
714 | to be valid. */ | |
715 | inline static rtx | |
716 | emit_set_insn (rtx x, rtx y) | |
717 | { | |
718 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
719 | } | |
720 | ||
0977774b JT |
721 | /* Return the number of bits set in VALUE. */ |
722 | static unsigned | |
e32bac5b | 723 | bit_count (unsigned long value) |
aec3cfba | 724 | { |
d5b7b3ae | 725 | unsigned long count = 0; |
f676971a | 726 | |
aec3cfba NC |
727 | while (value) |
728 | { | |
0977774b JT |
729 | count++; |
730 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
731 | } |
732 | ||
733 | return count; | |
734 | } | |
735 | ||
c112cf2b | 736 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
737 | |
738 | static void | |
739 | arm_init_libfuncs (void) | |
740 | { | |
741 | /* There are no special library functions unless we are using the | |
742 | ARM BPABI. */ | |
743 | if (!TARGET_BPABI) | |
744 | return; | |
745 | ||
746 | /* The functions below are described in Section 4 of the "Run-Time | |
747 | ABI for the ARM architecture", Version 1.0. */ | |
748 | ||
749 | /* Double-precision floating-point arithmetic. Table 2. */ | |
750 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
751 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
752 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
753 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
754 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
755 | ||
c112cf2b | 756 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
757 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
758 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
759 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
760 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
761 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
762 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
763 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
764 | ||
765 | /* Single-precision floating-point arithmetic. Table 4. */ | |
766 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
767 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
768 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
769 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
770 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 771 | |
c112cf2b | 772 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
773 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
774 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
775 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
776 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
777 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
778 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
779 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
780 | ||
781 | /* Floating-point to integer conversions. Table 6. */ | |
782 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
783 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
784 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
785 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
786 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
787 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
788 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
789 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
790 | ||
791 | /* Conversions between floating types. Table 7. */ | |
792 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
793 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
794 | ||
c112cf2b | 795 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
796 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
797 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
798 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
799 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
800 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
801 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
802 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
803 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
804 | ||
805 | /* Long long. Table 9. */ | |
806 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
807 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
808 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
809 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
810 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
811 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
812 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
813 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
814 | ||
815 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
816 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
817 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
818 | ||
819 | /* The divmod functions are designed so that they can be used for | |
820 | plain division, even though they return both the quotient and the | |
821 | remainder. The quotient is returned in the usual location (i.e., | |
822 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
823 | for an ordinary division routine. Because the AAPCS calling | |
824 | conventions specify that all of { r0, r1, r2, r3 } are | |
825 | callee-saved registers, there is no need to tell the compiler | |
826 | explicitly that those registers are clobbered by these | |
827 | routines. */ | |
828 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
829 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
830 | |
831 | /* For SImode division the ABI provides div-without-mod routines, | |
832 | which are faster. */ | |
833 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
834 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
835 | |
836 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
837 | divmod libcalls instead. */ | |
838 | set_optab_libfunc (smod_optab, DImode, NULL); | |
839 | set_optab_libfunc (umod_optab, DImode, NULL); | |
840 | set_optab_libfunc (smod_optab, SImode, NULL); | |
841 | set_optab_libfunc (umod_optab, SImode, NULL); | |
b3f8d95d MM |
842 | } |
843 | ||
c54c7322 RS |
844 | /* Implement TARGET_HANDLE_OPTION. */ |
845 | ||
846 | static bool | |
847 | arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
848 | { | |
849 | switch (code) | |
850 | { | |
c54c7322 RS |
851 | case OPT_march_: |
852 | arm_select[1].string = arg; | |
853 | return true; | |
854 | ||
855 | case OPT_mcpu_: | |
856 | arm_select[0].string = arg; | |
857 | return true; | |
858 | ||
c54c7322 RS |
859 | case OPT_mhard_float: |
860 | target_float_abi_name = "hard"; | |
861 | return true; | |
862 | ||
c54c7322 RS |
863 | case OPT_msoft_float: |
864 | target_float_abi_name = "soft"; | |
865 | return true; | |
866 | ||
c54c7322 RS |
867 | case OPT_mtune_: |
868 | arm_select[2].string = arg; | |
869 | return true; | |
870 | ||
871 | default: | |
872 | return true; | |
873 | } | |
874 | } | |
875 | ||
2b835d68 RE |
876 | /* Fix up any incompatible options that the user has specified. |
877 | This has now turned into a maze. */ | |
878 | void | |
e32bac5b | 879 | arm_override_options (void) |
2b835d68 | 880 | { |
ed4c4348 | 881 | unsigned i; |
e6fffade | 882 | enum processor_type target_arch_cpu = arm_none; |
9b66ebb1 | 883 | |
f5a1b0d2 | 884 | /* Set up the flags based on the cpu/architecture selected by the user. */ |
b6a1cbae | 885 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 886 | { |
f5a1b0d2 | 887 | struct arm_cpu_select * ptr = arm_select + i; |
f676971a | 888 | |
f5a1b0d2 | 889 | if (ptr->string != NULL && ptr->string[0] != '\0') |
bd9c7e23 | 890 | { |
13bd191d | 891 | const struct processors * sel; |
bd9c7e23 | 892 | |
5895f793 | 893 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 894 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 895 | { |
78011587 | 896 | /* Set the architecture define. */ |
e6fffade | 897 | if (i != ARM_OPT_SET_TUNE) |
78011587 PB |
898 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
899 | ||
9b66ebb1 PB |
900 | /* Determine the processor core for which we should |
901 | tune code-generation. */ | |
902 | if (/* -mcpu= is a sensible default. */ | |
e6fffade | 903 | i == ARM_OPT_SET_CPU |
9b66ebb1 | 904 | /* -mtune= overrides -mcpu= and -march=. */ |
e6fffade | 905 | || i == ARM_OPT_SET_TUNE) |
9b66ebb1 PB |
906 | arm_tune = (enum processor_type) (sel - ptr->processors); |
907 | ||
e6fffade RE |
908 | /* Remember the CPU associated with this architecture. |
909 | If no other option is used to set the CPU type, | |
910 | we'll use this to guess the most suitable tuning | |
911 | options. */ | |
912 | if (i == ARM_OPT_SET_ARCH) | |
913 | target_arch_cpu = sel->core; | |
e0b92319 | 914 | |
e6fffade | 915 | if (i != ARM_OPT_SET_TUNE) |
b111229a | 916 | { |
aec3cfba NC |
917 | /* If we have been given an architecture and a processor |
918 | make sure that they are compatible. We only generate | |
919 | a warning though, and we prefer the CPU over the | |
6354dc9b | 920 | architecture. */ |
aec3cfba | 921 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
d4ee4d25 | 922 | warning (0, "switch -mcpu=%s conflicts with -march= switch", |
aec3cfba | 923 | ptr->string); |
f676971a | 924 | |
aec3cfba | 925 | insn_flags = sel->flags; |
b111229a | 926 | } |
f676971a | 927 | |
bd9c7e23 RE |
928 | break; |
929 | } | |
930 | ||
931 | if (sel->name == NULL) | |
932 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
933 | } | |
934 | } | |
f676971a | 935 | |
e6fffade RE |
936 | /* Guess the tuning options from the architecture if necessary. */ |
937 | if (arm_tune == arm_none) | |
938 | arm_tune = target_arch_cpu; | |
939 | ||
f5a1b0d2 | 940 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 941 | if (insn_flags == 0) |
f5a1b0d2 | 942 | { |
8b60264b | 943 | const struct processors * sel; |
aec3cfba | 944 | unsigned int sought; |
78011587 | 945 | enum processor_type cpu; |
aec3cfba | 946 | |
78011587 PB |
947 | cpu = TARGET_CPU_DEFAULT; |
948 | if (cpu == arm_none) | |
949 | { | |
950 | #ifdef SUBTARGET_CPU_DEFAULT | |
951 | /* Use the subtarget default CPU if none was specified by | |
952 | configure. */ | |
953 | cpu = SUBTARGET_CPU_DEFAULT; | |
954 | #endif | |
955 | /* Default to ARM6. */ | |
956 | if (cpu == arm_none) | |
957 | cpu = arm6; | |
958 | } | |
959 | sel = &all_cores[cpu]; | |
aec3cfba NC |
960 | |
961 | insn_flags = sel->flags; | |
9b66ebb1 | 962 | |
aec3cfba NC |
963 | /* Now check to see if the user has specified some command line |
964 | switch that require certain abilities from the cpu. */ | |
965 | sought = 0; | |
f676971a | 966 | |
d5b7b3ae | 967 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 968 | { |
aec3cfba | 969 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 970 | |
d5b7b3ae | 971 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
972 | interworking. Therefore we force FL_MODE26 to be removed |
973 | from insn_flags here (if it was set), so that the search | |
974 | below will always be able to find a compatible processor. */ | |
5895f793 | 975 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 976 | } |
f676971a | 977 | |
aec3cfba | 978 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 979 | { |
aec3cfba NC |
980 | /* Try to locate a CPU type that supports all of the abilities |
981 | of the default CPU, plus the extra abilities requested by | |
982 | the user. */ | |
5895f793 | 983 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 984 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
985 | break; |
986 | ||
987 | if (sel->name == NULL) | |
aec3cfba | 988 | { |
0977774b | 989 | unsigned current_bit_count = 0; |
8b60264b | 990 | const struct processors * best_fit = NULL; |
f676971a | 991 | |
aec3cfba NC |
992 | /* Ideally we would like to issue an error message here |
993 | saying that it was not possible to find a CPU compatible | |
994 | with the default CPU, but which also supports the command | |
995 | line options specified by the programmer, and so they | |
996 | ought to use the -mcpu=<name> command line option to | |
997 | override the default CPU type. | |
998 | ||
61f0ccff RE |
999 | If we cannot find a cpu that has both the |
1000 | characteristics of the default cpu and the given | |
1001 | command line options we scan the array again looking | |
1002 | for a best match. */ | |
5895f793 | 1003 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1004 | if ((sel->flags & sought) == sought) |
1005 | { | |
0977774b | 1006 | unsigned count; |
aec3cfba NC |
1007 | |
1008 | count = bit_count (sel->flags & insn_flags); | |
1009 | ||
1010 | if (count >= current_bit_count) | |
1011 | { | |
1012 | best_fit = sel; | |
1013 | current_bit_count = count; | |
1014 | } | |
1015 | } | |
f5a1b0d2 | 1016 | |
e6d29d15 NS |
1017 | gcc_assert (best_fit); |
1018 | sel = best_fit; | |
aec3cfba NC |
1019 | } |
1020 | ||
1021 | insn_flags = sel->flags; | |
f5a1b0d2 | 1022 | } |
78011587 | 1023 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
9b66ebb1 PB |
1024 | if (arm_tune == arm_none) |
1025 | arm_tune = (enum processor_type) (sel - all_cores); | |
f5a1b0d2 | 1026 | } |
f676971a | 1027 | |
9b66ebb1 PB |
1028 | /* The processor for which we should tune should now have been |
1029 | chosen. */ | |
e6d29d15 | 1030 | gcc_assert (arm_tune != arm_none); |
f676971a | 1031 | |
9b66ebb1 | 1032 | tune_flags = all_cores[(int)arm_tune].flags; |
21b5653c RE |
1033 | if (optimize_size) |
1034 | targetm.rtx_costs = arm_size_rtx_costs; | |
1035 | else | |
1036 | targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs; | |
e26053d1 | 1037 | |
f5a1b0d2 NC |
1038 | /* Make sure that the processor choice does not conflict with any of the |
1039 | other command line choices. */ | |
6cfc7210 | 1040 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 | 1041 | { |
d4ee4d25 | 1042 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1043 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1044 | } |
f676971a | 1045 | |
d5b7b3ae RE |
1046 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1047 | { | |
d4ee4d25 | 1048 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1049 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1050 | } |
1051 | ||
1052 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1053 | { | |
d4ee4d25 | 1054 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1055 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1056 | } |
d19fb8e3 | 1057 | |
da8ce8be RE |
1058 | /* Callee super interworking implies thumb interworking. Adding |
1059 | this to the flags here simplifies the logic elsewhere. */ | |
1060 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
1061 | target_flags |= MASK_INTERWORK; | |
1062 | ||
d5b7b3ae RE |
1063 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1064 | from here where no function is being compiled currently. */ | |
c54c7322 | 1065 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1066 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1067 | |
1068 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1069 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1070 | |
1071 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
d4ee4d25 | 1072 | warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1073 | |
5895f793 | 1074 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1075 | { |
d4ee4d25 | 1076 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1077 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1078 | } |
f676971a | 1079 | |
2b835d68 | 1080 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1081 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1082 | |
2b835d68 | 1083 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1084 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1085 | |
2b835d68 | 1086 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1087 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1088 | |
d5b7b3ae RE |
1089 | /* If this target is normally configured to use APCS frames, warn if they |
1090 | are turned off and debugging is turned on. */ | |
1091 | if (TARGET_ARM | |
1092 | && write_symbols != NO_DEBUG | |
5895f793 | 1093 | && !TARGET_APCS_FRAME |
c54c7322 | 1094 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1095 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1096 | |
32de079a RE |
1097 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1098 | which keeps r9 available. */ | |
020a4035 | 1099 | if (flag_pic && TARGET_SINGLE_PIC_BASE) |
5b43fed1 | 1100 | arm_pic_register = TARGET_APCS_STACK ? 9 : 10; |
f676971a | 1101 | |
2b835d68 | 1102 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1103 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1104 | |
4912a07c | 1105 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1106 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1107 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1108 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1109 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1110 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1111 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1112 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
9b66ebb1 | 1113 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1114 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1115 | |
1116 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1117 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
9b66ebb1 | 1118 | thumb_code = (TARGET_ARM == 0); |
abac3b49 | 1119 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1120 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1121 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5a9335ef | 1122 | |
68d560d4 RE |
1123 | /* V5 code we generate is completely interworking capable, so we turn off |
1124 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1125 | |
1126 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1127 | or GLD can get confused. This is a hack. */ | |
1128 | if (TARGET_INTERWORK) | |
1129 | arm_cpp_interwork = 1; | |
1130 | ||
68d560d4 | 1131 | if (arm_arch5) |
c54c7322 | 1132 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1133 | |
5848830f PB |
1134 | if (target_abi_name) |
1135 | { | |
1136 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1137 | { | |
1138 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1139 | { | |
1140 | arm_abi = arm_all_abis[i].abi_type; | |
1141 | break; | |
1142 | } | |
1143 | } | |
1144 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1145 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1146 | } | |
1147 | else | |
c805f22e | 1148 | arm_abi = ARM_DEFAULT_ABI; |
5848830f PB |
1149 | |
1150 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) | |
1151 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1152 | ||
1153 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1154 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1155 | |
9b66ebb1 PB |
1156 | arm_fp_model = ARM_FP_MODEL_UNKNOWN; |
1157 | if (target_fpu_name == NULL && target_fpe_name != NULL) | |
9b6b54e2 | 1158 | { |
9b66ebb1 PB |
1159 | if (streq (target_fpe_name, "2")) |
1160 | target_fpu_name = "fpe2"; | |
1161 | else if (streq (target_fpe_name, "3")) | |
1162 | target_fpu_name = "fpe3"; | |
1163 | else | |
1164 | error ("invalid floating point emulation option: -mfpe=%s", | |
1165 | target_fpe_name); | |
1166 | } | |
1167 | if (target_fpu_name != NULL) | |
1168 | { | |
1169 | /* The user specified a FPU. */ | |
1170 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1171 | { | |
1172 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1173 | { | |
1174 | arm_fpu_arch = all_fpus[i].fpu; | |
1175 | arm_fpu_tune = arm_fpu_arch; | |
1176 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
1177 | break; | |
1178 | } | |
1179 | } | |
1180 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
1181 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
9b6b54e2 NC |
1182 | } |
1183 | else | |
2b835d68 | 1184 | { |
9b66ebb1 | 1185 | #ifdef FPUTYPE_DEFAULT |
78011587 | 1186 | /* Use the default if it is specified for this platform. */ |
9b66ebb1 PB |
1187 | arm_fpu_arch = FPUTYPE_DEFAULT; |
1188 | arm_fpu_tune = FPUTYPE_DEFAULT; | |
1189 | #else | |
1190 | /* Pick one based on CPU type. */ | |
78011587 | 1191 | /* ??? Some targets assume FPA is the default. |
9b66ebb1 PB |
1192 | if ((insn_flags & FL_VFP) != 0) |
1193 | arm_fpu_arch = FPUTYPE_VFP; | |
78011587 PB |
1194 | else |
1195 | */ | |
1196 | if (arm_arch_cirrus) | |
9b66ebb1 PB |
1197 | arm_fpu_arch = FPUTYPE_MAVERICK; |
1198 | else | |
29ad9694 | 1199 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
9b66ebb1 PB |
1200 | #endif |
1201 | if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
1202 | arm_fpu_tune = FPUTYPE_FPA; | |
2b835d68 | 1203 | else |
9b66ebb1 PB |
1204 | arm_fpu_tune = arm_fpu_arch; |
1205 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
e6d29d15 | 1206 | gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); |
9b66ebb1 PB |
1207 | } |
1208 | ||
1209 | if (target_float_abi_name != NULL) | |
1210 | { | |
1211 | /* The user specified a FP ABI. */ | |
1212 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1213 | { | |
1214 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1215 | { | |
1216 | arm_float_abi = all_float_abis[i].abi_type; | |
1217 | break; | |
1218 | } | |
1219 | } | |
1220 | if (i == ARRAY_SIZE (all_float_abis)) | |
1221 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1222 | target_float_abi_name); | |
2b835d68 | 1223 | } |
3d8532aa PB |
1224 | else |
1225 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1226 | |
72cdc543 PB |
1227 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) |
1228 | sorry ("-mfloat-abi=hard and VFP"); | |
1229 | ||
9b66ebb1 PB |
1230 | /* If soft-float is specified then don't use FPU. */ |
1231 | if (TARGET_SOFT_FLOAT) | |
1232 | arm_fpu_arch = FPUTYPE_NONE; | |
f676971a | 1233 | |
f5a1b0d2 NC |
1234 | /* For arm2/3 there is no need to do any scheduling if there is only |
1235 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 PB |
1236 | if ((TARGET_SOFT_FLOAT |
1237 | || arm_fpu_tune == FPUTYPE_FPA_EMU2 | |
1238 | || arm_fpu_tune == FPUTYPE_FPA_EMU3) | |
ed0e6530 | 1239 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1240 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1241 | |
d3585b76 DJ |
1242 | if (target_thread_switch) |
1243 | { | |
1244 | if (strcmp (target_thread_switch, "soft") == 0) | |
1245 | target_thread_pointer = TP_SOFT; | |
1246 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1247 | target_thread_pointer = TP_AUTO; | |
1248 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1249 | target_thread_pointer = TP_CP15; | |
1250 | else | |
1251 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1252 | } | |
1253 | ||
1254 | /* Use the cp15 method if it is available. */ | |
1255 | if (target_thread_pointer == TP_AUTO) | |
1256 | { | |
1257 | if (arm_arch6k && !TARGET_THUMB) | |
1258 | target_thread_pointer = TP_CP15; | |
1259 | else | |
1260 | target_thread_pointer = TP_SOFT; | |
1261 | } | |
1262 | ||
1263 | if (TARGET_HARD_TP && TARGET_THUMB) | |
1264 | error ("can not use -mtp=cp15 with -mthumb"); | |
1265 | ||
5848830f | 1266 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1267 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1268 | arm_structure_size_boundary = 8; |
1269 | ||
b355a481 NC |
1270 | if (structure_size_string != NULL) |
1271 | { | |
1272 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1273 | |
1274 | if (size == 8 || size == 32 | |
1275 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1276 | arm_structure_size_boundary = size; |
1277 | else | |
d4ee4d25 | 1278 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1279 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1280 | } |
ed0e6530 PB |
1281 | |
1282 | if (arm_pic_register_string != NULL) | |
1283 | { | |
5b43fed1 | 1284 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1285 | |
5895f793 | 1286 | if (!flag_pic) |
d4ee4d25 | 1287 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1288 | |
ed0e6530 | 1289 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1290 | else if (pic_register < 0 || call_used_regs[pic_register] |
1291 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1292 | || pic_register == STACK_POINTER_REGNUM | |
1293 | || pic_register >= PC_REGNUM) | |
c725bd79 | 1294 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1295 | else |
1296 | arm_pic_register = pic_register; | |
1297 | } | |
d5b7b3ae RE |
1298 | |
1299 | if (TARGET_THUMB && flag_schedule_insns) | |
1300 | { | |
1301 | /* Don't warn since it's on by default in -O2. */ | |
1302 | flag_schedule_insns = 0; | |
1303 | } | |
1304 | ||
f5a1b0d2 | 1305 | if (optimize_size) |
be03ccc9 | 1306 | { |
577d6328 | 1307 | arm_constant_limit = 1; |
be03ccc9 NP |
1308 | |
1309 | /* If optimizing for size, bump the number of instructions that we | |
d6b4baa4 | 1310 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1311 | max_insns_skipped = 6; |
1312 | } | |
1313 | else | |
1314 | { | |
1315 | /* For processors with load scheduling, it never costs more than | |
1316 | 2 cycles to load a constant, and the load scheduler may well | |
1317 | reduce that to 1. */ | |
2075b05d | 1318 | if (arm_ld_sched) |
be03ccc9 NP |
1319 | arm_constant_limit = 1; |
1320 | ||
1321 | /* On XScale the longer latency of a load makes it more difficult | |
1322 | to achieve a good schedule, so it's faster to synthesize | |
d6b4baa4 | 1323 | constants that can be done in two insns. */ |
be03ccc9 NP |
1324 | if (arm_tune_xscale) |
1325 | arm_constant_limit = 2; | |
1326 | ||
1327 | /* StrongARM has early execution of branches, so a sequence | |
1328 | that is worth skipping is shorter. */ | |
abac3b49 | 1329 | if (arm_tune_strongarm) |
be03ccc9 NP |
1330 | max_insns_skipped = 3; |
1331 | } | |
92a432f4 RE |
1332 | |
1333 | /* Register global variables with the garbage collector. */ | |
1334 | arm_add_gc_roots (); | |
1335 | } | |
1336 | ||
1337 | static void | |
e32bac5b | 1338 | arm_add_gc_roots (void) |
92a432f4 | 1339 | { |
c7319d87 RE |
1340 | gcc_obstack_init(&minipool_obstack); |
1341 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1342 | } |
cce8749e | 1343 | \f |
6d3d9133 NC |
1344 | /* A table of known ARM exception types. |
1345 | For use with the interrupt function attribute. */ | |
1346 | ||
1347 | typedef struct | |
1348 | { | |
8b60264b KG |
1349 | const char *const arg; |
1350 | const unsigned long return_value; | |
6d3d9133 NC |
1351 | } |
1352 | isr_attribute_arg; | |
1353 | ||
8b60264b | 1354 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1355 | { |
1356 | { "IRQ", ARM_FT_ISR }, | |
1357 | { "irq", ARM_FT_ISR }, | |
1358 | { "FIQ", ARM_FT_FIQ }, | |
1359 | { "fiq", ARM_FT_FIQ }, | |
1360 | { "ABORT", ARM_FT_ISR }, | |
1361 | { "abort", ARM_FT_ISR }, | |
1362 | { "ABORT", ARM_FT_ISR }, | |
1363 | { "abort", ARM_FT_ISR }, | |
1364 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1365 | { "undef", ARM_FT_EXCEPTION }, | |
1366 | { "SWI", ARM_FT_EXCEPTION }, | |
1367 | { "swi", ARM_FT_EXCEPTION }, | |
1368 | { NULL, ARM_FT_NORMAL } | |
1369 | }; | |
1370 | ||
1371 | /* Returns the (interrupt) function type of the current | |
1372 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1373 | ||
1374 | static unsigned long | |
e32bac5b | 1375 | arm_isr_value (tree argument) |
6d3d9133 | 1376 | { |
8b60264b | 1377 | const isr_attribute_arg * ptr; |
1d6e90ac | 1378 | const char * arg; |
6d3d9133 NC |
1379 | |
1380 | /* No argument - default to IRQ. */ | |
1381 | if (argument == NULL_TREE) | |
1382 | return ARM_FT_ISR; | |
1383 | ||
1384 | /* Get the value of the argument. */ | |
1385 | if (TREE_VALUE (argument) == NULL_TREE | |
1386 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1387 | return ARM_FT_UNKNOWN; | |
1388 | ||
1389 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1390 | ||
1391 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1392 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1393 | if (streq (arg, ptr->arg)) |
1394 | return ptr->return_value; | |
6d3d9133 | 1395 | |
05713b80 | 1396 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1397 | return ARM_FT_UNKNOWN; |
1398 | } | |
1399 | ||
1400 | /* Computes the type of the current function. */ | |
1401 | ||
1402 | static unsigned long | |
e32bac5b | 1403 | arm_compute_func_type (void) |
6d3d9133 NC |
1404 | { |
1405 | unsigned long type = ARM_FT_UNKNOWN; | |
1406 | tree a; | |
1407 | tree attr; | |
f676971a | 1408 | |
e6d29d15 | 1409 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
1410 | |
1411 | /* Decide if the current function is volatile. Such functions | |
1412 | never return, and many memory cycles can be saved by not storing | |
1413 | register values that will never be needed again. This optimization | |
1414 | was added to speed up context switching in a kernel application. */ | |
1415 | if (optimize > 0 | |
cf1955dc PB |
1416 | && (TREE_NOTHROW (current_function_decl) |
1417 | || !(flag_unwind_tables | |
1418 | || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) | |
6d3d9133 NC |
1419 | && TREE_THIS_VOLATILE (current_function_decl)) |
1420 | type |= ARM_FT_VOLATILE; | |
f676971a | 1421 | |
6de9cd9a | 1422 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
1423 | type |= ARM_FT_NESTED; |
1424 | ||
91d231cb | 1425 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 1426 | |
6d3d9133 NC |
1427 | a = lookup_attribute ("naked", attr); |
1428 | if (a != NULL_TREE) | |
1429 | type |= ARM_FT_NAKED; | |
1430 | ||
c9ca9b88 PB |
1431 | a = lookup_attribute ("isr", attr); |
1432 | if (a == NULL_TREE) | |
1433 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 1434 | |
c9ca9b88 PB |
1435 | if (a == NULL_TREE) |
1436 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 1437 | else |
c9ca9b88 | 1438 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 1439 | |
6d3d9133 NC |
1440 | return type; |
1441 | } | |
1442 | ||
1443 | /* Returns the type of the current function. */ | |
1444 | ||
1445 | unsigned long | |
e32bac5b | 1446 | arm_current_func_type (void) |
6d3d9133 NC |
1447 | { |
1448 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
1449 | cfun->machine->func_type = arm_compute_func_type (); | |
1450 | ||
1451 | return cfun->machine->func_type; | |
1452 | } | |
1453 | \f | |
f676971a | 1454 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
1455 | If SIBLING is non-null, this is a test for a return before a sibling |
1456 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 1457 | |
ff9940b0 | 1458 | int |
a72d4945 | 1459 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
1460 | { |
1461 | int regno; | |
9b598fa0 | 1462 | unsigned int func_type; |
d5db54a1 | 1463 | unsigned long saved_int_regs; |
a72d4945 | 1464 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 1465 | arm_stack_offsets *offsets; |
ff9940b0 | 1466 | |
d5b7b3ae | 1467 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
1468 | if (!reload_completed) |
1469 | return 0; | |
efc2515b | 1470 | |
9b598fa0 RE |
1471 | func_type = arm_current_func_type (); |
1472 | ||
3a7731fd PB |
1473 | /* Naked functions and volatile functions need special |
1474 | consideration. */ | |
1475 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) | |
6d3d9133 | 1476 | return 0; |
06bea5aa NC |
1477 | |
1478 | /* So do interrupt functions that use the frame pointer. */ | |
1479 | if (IS_INTERRUPT (func_type) && frame_pointer_needed) | |
1480 | return 0; | |
a72d4945 | 1481 | |
5848830f PB |
1482 | offsets = arm_get_frame_offsets (); |
1483 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 1484 | |
6d3d9133 NC |
1485 | /* As do variadic functions. */ |
1486 | if (current_function_pretend_args_size | |
3cb66fd7 | 1487 | || cfun->machine->uses_anonymous_args |
699a4925 | 1488 | /* Or if the function calls __builtin_eh_return () */ |
c9ca9b88 | 1489 | || current_function_calls_eh_return |
699a4925 RE |
1490 | /* Or if the function calls alloca */ |
1491 | || current_function_calls_alloca | |
a72d4945 RE |
1492 | /* Or if there is a stack adjustment. However, if the stack pointer |
1493 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
1494 | || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4))) | |
ff9940b0 RE |
1495 | return 0; |
1496 | ||
d5db54a1 RE |
1497 | saved_int_regs = arm_compute_save_reg_mask (); |
1498 | ||
a72d4945 RE |
1499 | /* Unfortunately, the insn |
1500 | ||
1501 | ldmib sp, {..., sp, ...} | |
1502 | ||
1503 | triggers a bug on most SA-110 based devices, such that the stack | |
1504 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 1505 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 1506 | the other registers, since that is never slower than executing |
f676971a | 1507 | another instruction. |
a72d4945 RE |
1508 | |
1509 | We test for !arm_arch5 here, because code for any architecture | |
1510 | less than this could potentially be run on one of the buggy | |
1511 | chips. */ | |
1512 | if (stack_adjust == 4 && !arm_arch5) | |
1513 | { | |
1514 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 1515 | the default abi) ... */ |
a72d4945 RE |
1516 | if (!call_used_regs[3]) |
1517 | return 0; | |
1518 | ||
4f5dfed0 JC |
1519 | /* ... that it isn't being used for a return value ... */ |
1520 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
1521 | return 0; | |
1522 | ||
1523 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
1524 | if (sibling) |
1525 | { | |
e6d29d15 | 1526 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
1527 | |
1528 | if (find_regno_fusage (sibling, USE, 3)) | |
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | /* ... and that there are no call-saved registers in r0-r2 | |
1533 | (always true in the default ABI). */ | |
1534 | if (saved_int_regs & 0x7) | |
1535 | return 0; | |
1536 | } | |
1537 | ||
b111229a | 1538 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 RE |
1539 | stacked. */ |
1540 | if (TARGET_INTERWORK && saved_int_regs != 0) | |
b36ba79f | 1541 | return 0; |
d5db54a1 RE |
1542 | |
1543 | /* On StrongARM, conditional returns are expensive if they aren't | |
1544 | taken and multiple registers have been stacked. */ | |
abac3b49 | 1545 | if (iscond && arm_tune_strongarm) |
6ed30148 | 1546 | { |
f676971a | 1547 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
1548 | conditional-load instruction, that's not expensive. */ |
1549 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
1550 | return 0; | |
6ed30148 | 1551 | |
020a4035 RE |
1552 | if (flag_pic |
1553 | && arm_pic_register != INVALID_REGNUM | |
1554 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
b111229a | 1555 | return 0; |
6ed30148 | 1556 | } |
d5db54a1 RE |
1557 | |
1558 | /* If there are saved registers but the LR isn't saved, then we need | |
1559 | two instructions for the return. */ | |
1560 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1561 | return 0; | |
1562 | ||
3b684012 | 1563 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1564 | since this also requires an insn. */ |
9b66ebb1 PB |
1565 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
1566 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
1567 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
1568 | return 0; | |
1569 | ||
1570 | /* Likewise VFP regs. */ | |
1571 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
1572 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
5895f793 | 1573 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
d5b7b3ae | 1574 | return 0; |
ff9940b0 | 1575 | |
5a9335ef NC |
1576 | if (TARGET_REALLY_IWMMXT) |
1577 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
1578 | if (regs_ever_live[regno] && ! call_used_regs [regno]) | |
1579 | return 0; | |
1580 | ||
ff9940b0 RE |
1581 | return 1; |
1582 | } | |
1583 | ||
cce8749e CH |
1584 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1585 | ||
1586 | int | |
e32bac5b | 1587 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 1588 | { |
4642ccb1 | 1589 | int lowbit; |
e0b92319 | 1590 | |
f676971a | 1591 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 1592 | be all zero, or all one. */ |
30cf4896 KG |
1593 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1594 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1595 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1596 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 1597 | return FALSE; |
f676971a | 1598 | |
4642ccb1 | 1599 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 1600 | |
4642ccb1 RE |
1601 | /* Fast return for 0 and small values. We must do this for zero, since |
1602 | the code below can't handle that one case. */ | |
1603 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
1604 | return TRUE; |
1605 | ||
4642ccb1 RE |
1606 | /* Get the number of trailing zeros, rounded down to the nearest even |
1607 | number. */ | |
1608 | lowbit = (ffs ((int) i) - 1) & ~1; | |
1609 | ||
1610 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
1611 | return TRUE; | |
1612 | else if (lowbit <= 4 | |
1613 | && ((i & ~0xc000003f) == 0 | |
1614 | || (i & ~0xf000000f) == 0 | |
1615 | || (i & ~0xfc000003) == 0)) | |
1616 | return TRUE; | |
cce8749e | 1617 | |
f3bb6135 RE |
1618 | return FALSE; |
1619 | } | |
cce8749e | 1620 | |
6354dc9b | 1621 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 1622 | static int |
e32bac5b | 1623 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
1624 | { |
1625 | if (const_ok_for_arm (i)) | |
1626 | return 1; | |
1627 | ||
1628 | switch (code) | |
1629 | { | |
1630 | case PLUS: | |
1631 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
1632 | ||
1633 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
1634 | case XOR: | |
1635 | case IOR: | |
1636 | return 0; | |
1637 | ||
1638 | case AND: | |
1639 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
1640 | ||
1641 | default: | |
e6d29d15 | 1642 | gcc_unreachable (); |
e2c671ba RE |
1643 | } |
1644 | } | |
1645 | ||
1646 | /* Emit a sequence of insns to handle a large constant. | |
1647 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
1648 | IOR, AND, XOR, MINUS; | |
1649 | MODE is the mode in which the operation is being performed; | |
1650 | VAL is the integer to operate on; | |
1651 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
1652 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
1653 | either produce a simpler sequence, or we will want to cse the values. |
1654 | Return value is the number of insns emitted. */ | |
e2c671ba RE |
1655 | |
1656 | int | |
a406f566 | 1657 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 1658 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 1659 | { |
a406f566 MM |
1660 | rtx cond; |
1661 | ||
1662 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
1663 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
1664 | else | |
1665 | cond = NULL_RTX; | |
1666 | ||
2b835d68 RE |
1667 | if (subtargets || code == SET |
1668 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
1669 | && REGNO (target) != REGNO (source))) | |
1670 | { | |
4b632bf1 | 1671 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 1672 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
1673 | them in-line, regardless of the cost. This is only likely to |
1674 | be more costly on chips that have load delay slots and we are | |
1675 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1676 | occurred before the final instruction emission). |
1677 | ||
1678 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1679 | */ |
5895f793 | 1680 | if (!after_arm_reorg |
a406f566 | 1681 | && !cond |
f676971a | 1682 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 1683 | 1, 0) |
4b632bf1 | 1684 | > arm_constant_limit + (code != SET))) |
2b835d68 RE |
1685 | { |
1686 | if (code == SET) | |
1687 | { | |
1688 | /* Currently SET is the only monadic value for CODE, all | |
1689 | the rest are diadic. */ | |
d66437c5 | 1690 | emit_set_insn (target, GEN_INT (val)); |
2b835d68 RE |
1691 | return 1; |
1692 | } | |
1693 | else | |
1694 | { | |
1695 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1696 | ||
d66437c5 | 1697 | emit_set_insn (temp, GEN_INT (val)); |
2b835d68 RE |
1698 | /* For MINUS, the value is subtracted from, since we never |
1699 | have subtraction of a constant. */ | |
1700 | if (code == MINUS) | |
d66437c5 | 1701 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 1702 | else |
d66437c5 RE |
1703 | emit_set_insn (target, |
1704 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
1705 | return 2; |
1706 | } | |
1707 | } | |
1708 | } | |
1709 | ||
f676971a | 1710 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 1711 | 1); |
2b835d68 RE |
1712 | } |
1713 | ||
ceebdb09 | 1714 | static int |
e32bac5b | 1715 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
1716 | { |
1717 | HOST_WIDE_INT temp1; | |
1718 | int num_insns = 0; | |
1719 | do | |
1720 | { | |
1721 | int end; | |
f676971a | 1722 | |
ceebdb09 PB |
1723 | if (i <= 0) |
1724 | i += 32; | |
1725 | if (remainder & (3 << (i - 2))) | |
1726 | { | |
1727 | end = i - 8; | |
1728 | if (end < 0) | |
1729 | end += 32; | |
1730 | temp1 = remainder & ((0x0ff << end) | |
1731 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1732 | remainder &= ~temp1; | |
1733 | num_insns++; | |
1734 | i -= 6; | |
1735 | } | |
1736 | i -= 2; | |
1737 | } while (remainder); | |
1738 | return num_insns; | |
1739 | } | |
1740 | ||
a406f566 MM |
1741 | /* Emit an instruction with the indicated PATTERN. If COND is |
1742 | non-NULL, conditionalize the execution of the instruction on COND | |
1743 | being true. */ | |
1744 | ||
1745 | static void | |
1746 | emit_constant_insn (rtx cond, rtx pattern) | |
1747 | { | |
1748 | if (cond) | |
1749 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
1750 | emit_insn (pattern); | |
1751 | } | |
1752 | ||
2b835d68 RE |
1753 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1754 | RTL generation. */ | |
1d6e90ac | 1755 | |
d5b7b3ae | 1756 | static int |
a406f566 | 1757 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
1758 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
1759 | int generate) | |
e2c671ba | 1760 | { |
e2c671ba RE |
1761 | int can_invert = 0; |
1762 | int can_negate = 0; | |
1763 | int can_negate_initial = 0; | |
1764 | int can_shift = 0; | |
1765 | int i; | |
1766 | int num_bits_set = 0; | |
1767 | int set_sign_bit_copies = 0; | |
1768 | int clear_sign_bit_copies = 0; | |
1769 | int clear_zero_bit_copies = 0; | |
1770 | int set_zero_bit_copies = 0; | |
1771 | int insns = 0; | |
e2c671ba | 1772 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 1773 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 1774 | |
d5b7b3ae | 1775 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1776 | check for degenerate cases; these can occur when DImode operations |
1777 | are split. */ | |
1778 | switch (code) | |
1779 | { | |
1780 | case SET: | |
1781 | can_invert = 1; | |
1782 | can_shift = 1; | |
1783 | can_negate = 1; | |
1784 | break; | |
1785 | ||
1786 | case PLUS: | |
1787 | can_negate = 1; | |
1788 | can_negate_initial = 1; | |
1789 | break; | |
1790 | ||
1791 | case IOR: | |
30cf4896 | 1792 | if (remainder == 0xffffffff) |
e2c671ba | 1793 | { |
2b835d68 | 1794 | if (generate) |
a406f566 MM |
1795 | emit_constant_insn (cond, |
1796 | gen_rtx_SET (VOIDmode, target, | |
1797 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
1798 | return 1; |
1799 | } | |
1800 | if (remainder == 0) | |
1801 | { | |
1802 | if (reload_completed && rtx_equal_p (target, source)) | |
1803 | return 0; | |
2b835d68 | 1804 | if (generate) |
a406f566 MM |
1805 | emit_constant_insn (cond, |
1806 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1807 | return 1; |
1808 | } | |
1809 | break; | |
1810 | ||
1811 | case AND: | |
1812 | if (remainder == 0) | |
1813 | { | |
2b835d68 | 1814 | if (generate) |
a406f566 MM |
1815 | emit_constant_insn (cond, |
1816 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
1817 | return 1; |
1818 | } | |
30cf4896 | 1819 | if (remainder == 0xffffffff) |
e2c671ba RE |
1820 | { |
1821 | if (reload_completed && rtx_equal_p (target, source)) | |
1822 | return 0; | |
2b835d68 | 1823 | if (generate) |
a406f566 MM |
1824 | emit_constant_insn (cond, |
1825 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1826 | return 1; |
1827 | } | |
1828 | can_invert = 1; | |
1829 | break; | |
1830 | ||
1831 | case XOR: | |
1832 | if (remainder == 0) | |
1833 | { | |
1834 | if (reload_completed && rtx_equal_p (target, source)) | |
1835 | return 0; | |
2b835d68 | 1836 | if (generate) |
a406f566 MM |
1837 | emit_constant_insn (cond, |
1838 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1839 | return 1; |
1840 | } | |
e0b92319 | 1841 | |
e6d29d15 NS |
1842 | /* We don't know how to handle other cases yet. */ |
1843 | gcc_assert (remainder == 0xffffffff); | |
e0b92319 | 1844 | |
e6d29d15 NS |
1845 | if (generate) |
1846 | emit_constant_insn (cond, | |
1847 | gen_rtx_SET (VOIDmode, target, | |
1848 | gen_rtx_NOT (mode, source))); | |
1849 | return 1; | |
e2c671ba RE |
1850 | |
1851 | case MINUS: | |
1852 | /* We treat MINUS as (val - source), since (source - val) is always | |
1853 | passed as (source + (-val)). */ | |
1854 | if (remainder == 0) | |
1855 | { | |
2b835d68 | 1856 | if (generate) |
a406f566 MM |
1857 | emit_constant_insn (cond, |
1858 | gen_rtx_SET (VOIDmode, target, | |
1859 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
1860 | return 1; |
1861 | } | |
1862 | if (const_ok_for_arm (val)) | |
1863 | { | |
2b835d68 | 1864 | if (generate) |
a406f566 | 1865 | emit_constant_insn (cond, |
f676971a | 1866 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
1867 | gen_rtx_MINUS (mode, GEN_INT (val), |
1868 | source))); | |
e2c671ba RE |
1869 | return 1; |
1870 | } | |
1871 | can_negate = 1; | |
1872 | ||
1873 | break; | |
1874 | ||
1875 | default: | |
e6d29d15 | 1876 | gcc_unreachable (); |
e2c671ba RE |
1877 | } |
1878 | ||
6354dc9b | 1879 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
1880 | if (const_ok_for_arm (val) |
1881 | || (can_negate_initial && const_ok_for_arm (-val)) | |
1882 | || (can_invert && const_ok_for_arm (~val))) | |
1883 | { | |
2b835d68 | 1884 | if (generate) |
a406f566 MM |
1885 | emit_constant_insn (cond, |
1886 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 1887 | (source |
a406f566 MM |
1888 | ? gen_rtx_fmt_ee (code, mode, source, |
1889 | GEN_INT (val)) | |
1890 | : GEN_INT (val)))); | |
e2c671ba RE |
1891 | return 1; |
1892 | } | |
1893 | ||
e2c671ba | 1894 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 1895 | optimizations. */ |
e2c671ba RE |
1896 | for (i = 31; i >= 0; i--) |
1897 | { | |
1898 | if ((remainder & (1 << i)) == 0) | |
1899 | clear_sign_bit_copies++; | |
1900 | else | |
1901 | break; | |
1902 | } | |
1903 | ||
1904 | for (i = 31; i >= 0; i--) | |
1905 | { | |
1906 | if ((remainder & (1 << i)) != 0) | |
1907 | set_sign_bit_copies++; | |
1908 | else | |
1909 | break; | |
1910 | } | |
1911 | ||
1912 | for (i = 0; i <= 31; i++) | |
1913 | { | |
1914 | if ((remainder & (1 << i)) == 0) | |
1915 | clear_zero_bit_copies++; | |
1916 | else | |
1917 | break; | |
1918 | } | |
1919 | ||
1920 | for (i = 0; i <= 31; i++) | |
1921 | { | |
1922 | if ((remainder & (1 << i)) != 0) | |
1923 | set_zero_bit_copies++; | |
1924 | else | |
1925 | break; | |
1926 | } | |
1927 | ||
1928 | switch (code) | |
1929 | { | |
1930 | case SET: | |
1931 | /* See if we can do this by sign_extending a constant that is known | |
1932 | to be negative. This is a good, way of doing it, since the shift | |
1933 | may well merge into a subsequent insn. */ | |
1934 | if (set_sign_bit_copies > 1) | |
1935 | { | |
1936 | if (const_ok_for_arm | |
f676971a | 1937 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
1938 | << (set_sign_bit_copies - 1)))) |
1939 | { | |
2b835d68 RE |
1940 | if (generate) |
1941 | { | |
d499463f | 1942 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 1943 | emit_constant_insn (cond, |
f676971a | 1944 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
1945 | GEN_INT (temp1))); |
1946 | emit_constant_insn (cond, | |
f676971a | 1947 | gen_ashrsi3 (target, new_src, |
a406f566 | 1948 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 1949 | } |
e2c671ba RE |
1950 | return 2; |
1951 | } | |
1952 | /* For an inverted constant, we will need to set the low bits, | |
1953 | these will be shifted out of harm's way. */ | |
1954 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
1955 | if (const_ok_for_arm (~temp1)) | |
1956 | { | |
2b835d68 RE |
1957 | if (generate) |
1958 | { | |
d499463f | 1959 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
1960 | emit_constant_insn (cond, |
1961 | gen_rtx_SET (VOIDmode, new_src, | |
1962 | GEN_INT (temp1))); | |
1963 | emit_constant_insn (cond, | |
f676971a | 1964 | gen_ashrsi3 (target, new_src, |
a406f566 | 1965 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 1966 | } |
e2c671ba RE |
1967 | return 2; |
1968 | } | |
1969 | } | |
1970 | ||
c87e6352 RE |
1971 | /* See if we can calculate the value as the difference between two |
1972 | valid immediates. */ | |
1973 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
1974 | { | |
1975 | int topshift = clear_sign_bit_copies & ~1; | |
1976 | ||
fa2c88a0 RE |
1977 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
1978 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
1979 | |
1980 | /* If temp1 is zero, then that means the 9 most significant | |
1981 | bits of remainder were 1 and we've caused it to overflow. | |
1982 | When topshift is 0 we don't need to do anything since we | |
1983 | can borrow from 'bit 32'. */ | |
1984 | if (temp1 == 0 && topshift != 0) | |
1985 | temp1 = 0x80000000 >> (topshift - 1); | |
1986 | ||
fa2c88a0 | 1987 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 1988 | |
c87e6352 RE |
1989 | if (const_ok_for_arm (temp2)) |
1990 | { | |
1991 | if (generate) | |
1992 | { | |
1993 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
1994 | emit_constant_insn (cond, | |
1995 | gen_rtx_SET (VOIDmode, new_src, | |
1996 | GEN_INT (temp1))); | |
1997 | emit_constant_insn (cond, | |
1998 | gen_addsi3 (target, new_src, | |
1999 | GEN_INT (-temp2))); | |
2000 | } | |
2001 | ||
2002 | return 2; | |
2003 | } | |
2004 | } | |
2005 | ||
e2c671ba RE |
2006 | /* See if we can generate this by setting the bottom (or the top) |
2007 | 16 bits, and then shifting these into the other half of the | |
2008 | word. We only look for the simplest cases, to do more would cost | |
2009 | too much. Be careful, however, not to generate this when the | |
2010 | alternative would take fewer insns. */ | |
30cf4896 | 2011 | if (val & 0xffff0000) |
e2c671ba | 2012 | { |
30cf4896 | 2013 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2014 | temp2 = remainder & 0x0000ffff; |
2015 | ||
6354dc9b | 2016 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2017 | for (i = 9; i < 24; i++) |
2018 | { | |
30cf4896 | 2019 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2020 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2021 | { |
d499463f RE |
2022 | rtx new_src = (subtargets |
2023 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2024 | : target); | |
a406f566 | 2025 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2026 | source, subtargets, generate); |
e2c671ba | 2027 | source = new_src; |
2b835d68 | 2028 | if (generate) |
f676971a | 2029 | emit_constant_insn |
a406f566 MM |
2030 | (cond, |
2031 | gen_rtx_SET | |
2032 | (VOIDmode, target, | |
2033 | gen_rtx_IOR (mode, | |
2034 | gen_rtx_ASHIFT (mode, source, | |
2035 | GEN_INT (i)), | |
2036 | source))); | |
e2c671ba RE |
2037 | return insns + 1; |
2038 | } | |
2039 | } | |
2040 | ||
6354dc9b | 2041 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
2042 | for (i = 17; i < 24; i++) |
2043 | { | |
2044 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 2045 | && !const_ok_for_arm (temp1)) |
e2c671ba | 2046 | { |
d499463f RE |
2047 | rtx new_src = (subtargets |
2048 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2049 | : target); | |
a406f566 | 2050 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 2051 | source, subtargets, generate); |
e2c671ba | 2052 | source = new_src; |
2b835d68 | 2053 | if (generate) |
a406f566 MM |
2054 | emit_constant_insn |
2055 | (cond, | |
2056 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
2057 | gen_rtx_IOR |
2058 | (mode, | |
2059 | gen_rtx_LSHIFTRT (mode, source, | |
2060 | GEN_INT (i)), | |
2061 | source))); | |
e2c671ba RE |
2062 | return insns + 1; |
2063 | } | |
2064 | } | |
2065 | } | |
2066 | break; | |
2067 | ||
2068 | case IOR: | |
2069 | case XOR: | |
7b64da89 RE |
2070 | /* If we have IOR or XOR, and the constant can be loaded in a |
2071 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
2072 | then this can be done in two instructions instead of 3-4. */ |
2073 | if (subtargets | |
d499463f | 2074 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 2075 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 2076 | { |
5895f793 | 2077 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2078 | { |
2b835d68 RE |
2079 | if (generate) |
2080 | { | |
2081 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 2082 | |
a406f566 | 2083 | emit_constant_insn (cond, |
f676971a | 2084 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
2085 | GEN_INT (val))); |
2086 | emit_constant_insn (cond, | |
f676971a | 2087 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2088 | gen_rtx_fmt_ee (code, mode, |
2089 | source, sub))); | |
2b835d68 | 2090 | } |
e2c671ba RE |
2091 | return 2; |
2092 | } | |
2093 | } | |
2094 | ||
2095 | if (code == XOR) | |
2096 | break; | |
2097 | ||
2098 | if (set_sign_bit_copies > 8 | |
2099 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
2100 | { | |
2b835d68 RE |
2101 | if (generate) |
2102 | { | |
2103 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2104 | rtx shift = GEN_INT (set_sign_bit_copies); | |
2105 | ||
f676971a | 2106 | emit_constant_insn |
a406f566 MM |
2107 | (cond, |
2108 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2109 | gen_rtx_NOT (mode, |
a406f566 | 2110 | gen_rtx_ASHIFT (mode, |
f676971a | 2111 | source, |
a406f566 | 2112 | shift)))); |
f676971a | 2113 | emit_constant_insn |
a406f566 MM |
2114 | (cond, |
2115 | gen_rtx_SET (VOIDmode, target, | |
2116 | gen_rtx_NOT (mode, | |
2117 | gen_rtx_LSHIFTRT (mode, sub, | |
2118 | shift)))); | |
2b835d68 | 2119 | } |
e2c671ba RE |
2120 | return 2; |
2121 | } | |
2122 | ||
2123 | if (set_zero_bit_copies > 8 | |
2124 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
2125 | { | |
2b835d68 RE |
2126 | if (generate) |
2127 | { | |
2128 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2129 | rtx shift = GEN_INT (set_zero_bit_copies); | |
2130 | ||
a406f566 MM |
2131 | emit_constant_insn |
2132 | (cond, | |
2133 | gen_rtx_SET (VOIDmode, sub, | |
2134 | gen_rtx_NOT (mode, | |
2135 | gen_rtx_LSHIFTRT (mode, | |
2136 | source, | |
2137 | shift)))); | |
f676971a | 2138 | emit_constant_insn |
a406f566 MM |
2139 | (cond, |
2140 | gen_rtx_SET (VOIDmode, target, | |
2141 | gen_rtx_NOT (mode, | |
2142 | gen_rtx_ASHIFT (mode, sub, | |
2143 | shift)))); | |
2b835d68 | 2144 | } |
e2c671ba RE |
2145 | return 2; |
2146 | } | |
2147 | ||
5895f793 | 2148 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2149 | { |
2b835d68 RE |
2150 | if (generate) |
2151 | { | |
2152 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
2153 | emit_constant_insn (cond, |
2154 | gen_rtx_SET (VOIDmode, sub, | |
2155 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
2156 | source = sub; |
2157 | if (subtargets) | |
2158 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
2159 | emit_constant_insn (cond, |
2160 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2161 | gen_rtx_AND (mode, source, |
a406f566 MM |
2162 | GEN_INT (temp1)))); |
2163 | emit_constant_insn (cond, | |
2164 | gen_rtx_SET (VOIDmode, target, | |
2165 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 2166 | } |
e2c671ba RE |
2167 | return 3; |
2168 | } | |
2169 | break; | |
2170 | ||
2171 | case AND: | |
2172 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
2173 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
2174 | { | |
30cf4896 | 2175 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 2176 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 2177 | & 0xffffffff); |
e2c671ba | 2178 | |
30cf4896 | 2179 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2180 | { |
2b835d68 RE |
2181 | if (generate) |
2182 | { | |
d499463f | 2183 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 2184 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 2185 | remainder | shift_mask, |
d499463f RE |
2186 | new_src, source, subtargets, 1); |
2187 | source = new_src; | |
2b835d68 RE |
2188 | } |
2189 | else | |
d499463f RE |
2190 | { |
2191 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
2192 | insns = arm_gen_constant (AND, mode, cond, |
2193 | remainder | shift_mask, | |
d499463f RE |
2194 | targ, source, subtargets, 0); |
2195 | } | |
2b835d68 RE |
2196 | } |
2197 | ||
2198 | if (generate) | |
2199 | { | |
d499463f RE |
2200 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2201 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
2202 | ||
2203 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
2204 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
2205 | } |
2206 | ||
e2c671ba RE |
2207 | return insns + 2; |
2208 | } | |
2209 | ||
2210 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
2211 | { | |
2212 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 2213 | |
30cf4896 | 2214 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2215 | { |
2b835d68 RE |
2216 | if (generate) |
2217 | { | |
d499463f RE |
2218 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2219 | ||
a406f566 MM |
2220 | insns = arm_gen_constant (AND, mode, cond, |
2221 | remainder | shift_mask, | |
d499463f RE |
2222 | new_src, source, subtargets, 1); |
2223 | source = new_src; | |
2b835d68 RE |
2224 | } |
2225 | else | |
d499463f RE |
2226 | { |
2227 | rtx targ = subtargets ? NULL_RTX : target; | |
2228 | ||
a406f566 MM |
2229 | insns = arm_gen_constant (AND, mode, cond, |
2230 | remainder | shift_mask, | |
d499463f RE |
2231 | targ, source, subtargets, 0); |
2232 | } | |
2b835d68 RE |
2233 | } |
2234 | ||
2235 | if (generate) | |
2236 | { | |
d499463f RE |
2237 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2238 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
2239 | ||
2240 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
2241 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
2242 | } |
2243 | ||
e2c671ba RE |
2244 | return insns + 2; |
2245 | } | |
2246 | ||
2247 | break; | |
2248 | ||
2249 | default: | |
2250 | break; | |
2251 | } | |
2252 | ||
2253 | for (i = 0; i < 32; i++) | |
2254 | if (remainder & (1 << i)) | |
2255 | num_bits_set++; | |
2256 | ||
2257 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 2258 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 2259 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 2260 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
2261 | else |
2262 | { | |
2263 | can_invert = 0; | |
2264 | can_negate = 0; | |
2265 | } | |
2266 | ||
2267 | /* Now try and find a way of doing the job in either two or three | |
2268 | instructions. | |
2269 | We start by looking for the largest block of zeros that are aligned on | |
2270 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
2271 | top of the word when we drop off the bottom. | |
6354dc9b | 2272 | In the worst case this code should produce no more than four insns. */ |
e2c671ba RE |
2273 | { |
2274 | int best_start = 0; | |
2275 | int best_consecutive_zeros = 0; | |
2276 | ||
2277 | for (i = 0; i < 32; i += 2) | |
2278 | { | |
2279 | int consecutive_zeros = 0; | |
2280 | ||
5895f793 | 2281 | if (!(remainder & (3 << i))) |
e2c671ba | 2282 | { |
5895f793 | 2283 | while ((i < 32) && !(remainder & (3 << i))) |
e2c671ba RE |
2284 | { |
2285 | consecutive_zeros += 2; | |
2286 | i += 2; | |
2287 | } | |
2288 | if (consecutive_zeros > best_consecutive_zeros) | |
2289 | { | |
2290 | best_consecutive_zeros = consecutive_zeros; | |
2291 | best_start = i - consecutive_zeros; | |
2292 | } | |
2293 | i -= 2; | |
2294 | } | |
2295 | } | |
2296 | ||
ceebdb09 PB |
2297 | /* So long as it won't require any more insns to do so, it's |
2298 | desirable to emit a small constant (in bits 0...9) in the last | |
2299 | insn. This way there is more chance that it can be combined with | |
2300 | a later addressing insn to form a pre-indexed load or store | |
2301 | operation. Consider: | |
2302 | ||
2303 | *((volatile int *)0xe0000100) = 1; | |
2304 | *((volatile int *)0xe0000110) = 2; | |
2305 | ||
2306 | We want this to wind up as: | |
2307 | ||
2308 | mov rA, #0xe0000000 | |
2309 | mov rB, #1 | |
2310 | str rB, [rA, #0x100] | |
2311 | mov rB, #2 | |
2312 | str rB, [rA, #0x110] | |
2313 | ||
2314 | rather than having to synthesize both large constants from scratch. | |
2315 | ||
2316 | Therefore, we calculate how many insns would be required to emit | |
f676971a | 2317 | the constant starting from `best_start', and also starting from |
112cdef5 | 2318 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't |
ceebdb09 PB |
2319 | yield a shorter sequence, we may as well use zero. */ |
2320 | if (best_start != 0 | |
2321 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
f676971a | 2322 | && (count_insns_for_constant (remainder, 0) <= |
ceebdb09 PB |
2323 | count_insns_for_constant (remainder, best_start))) |
2324 | best_start = 0; | |
2325 | ||
2326 | /* Now start emitting the insns. */ | |
e2c671ba RE |
2327 | i = best_start; |
2328 | do | |
2329 | { | |
2330 | int end; | |
2331 | ||
2332 | if (i <= 0) | |
2333 | i += 32; | |
2334 | if (remainder & (3 << (i - 2))) | |
2335 | { | |
2336 | end = i - 8; | |
2337 | if (end < 0) | |
2338 | end += 32; | |
2339 | temp1 = remainder & ((0x0ff << end) | |
2340 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2341 | remainder &= ~temp1; | |
2342 | ||
d499463f | 2343 | if (generate) |
e2c671ba | 2344 | { |
9503f3d1 RH |
2345 | rtx new_src, temp1_rtx; |
2346 | ||
2347 | if (code == SET || code == MINUS) | |
2348 | { | |
2349 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 2350 | if (can_invert && code != MINUS) |
9503f3d1 RH |
2351 | temp1 = ~temp1; |
2352 | } | |
2353 | else | |
2354 | { | |
96ae8197 | 2355 | if (remainder && subtargets) |
9503f3d1 | 2356 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
2357 | else |
2358 | new_src = target; | |
9503f3d1 RH |
2359 | if (can_invert) |
2360 | temp1 = ~temp1; | |
2361 | else if (can_negate) | |
2362 | temp1 = -temp1; | |
2363 | } | |
2364 | ||
2365 | temp1 = trunc_int_for_mode (temp1, mode); | |
2366 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
2367 | |
2368 | if (code == SET) | |
9503f3d1 | 2369 | ; |
d499463f | 2370 | else if (code == MINUS) |
9503f3d1 | 2371 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 2372 | else |
9503f3d1 RH |
2373 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
2374 | ||
a406f566 | 2375 | emit_constant_insn (cond, |
f676971a | 2376 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 2377 | temp1_rtx)); |
d499463f | 2378 | source = new_src; |
e2c671ba RE |
2379 | } |
2380 | ||
d499463f RE |
2381 | if (code == SET) |
2382 | { | |
2383 | can_invert = 0; | |
2384 | code = PLUS; | |
2385 | } | |
2386 | else if (code == MINUS) | |
2387 | code = PLUS; | |
2388 | ||
e2c671ba | 2389 | insns++; |
e2c671ba RE |
2390 | i -= 6; |
2391 | } | |
2392 | i -= 2; | |
1d6e90ac NC |
2393 | } |
2394 | while (remainder); | |
e2c671ba | 2395 | } |
1d6e90ac | 2396 | |
e2c671ba RE |
2397 | return insns; |
2398 | } | |
2399 | ||
bd9c7e23 RE |
2400 | /* Canonicalize a comparison so that we are more likely to recognize it. |
2401 | This can be done for a few constant compares, where we can make the | |
2402 | immediate value easier to load. */ | |
1d6e90ac | 2403 | |
bd9c7e23 | 2404 | enum rtx_code |
a14b88bb PB |
2405 | arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, |
2406 | rtx * op1) | |
bd9c7e23 | 2407 | { |
ad076f4e | 2408 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
a14b88bb PB |
2409 | unsigned HOST_WIDE_INT maxval; |
2410 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; | |
bd9c7e23 RE |
2411 | |
2412 | switch (code) | |
2413 | { | |
2414 | case EQ: | |
2415 | case NE: | |
2416 | return code; | |
2417 | ||
2418 | case GT: | |
2419 | case LE: | |
a14b88bb | 2420 | if (i != maxval |
5895f793 | 2421 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 2422 | { |
5895f793 | 2423 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
2424 | return code == GT ? GE : LT; |
2425 | } | |
2426 | break; | |
2427 | ||
2428 | case GE: | |
2429 | case LT: | |
a14b88bb | 2430 | if (i != ~maxval |
5895f793 | 2431 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 2432 | { |
5895f793 | 2433 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
2434 | return code == GE ? GT : LE; |
2435 | } | |
2436 | break; | |
2437 | ||
2438 | case GTU: | |
2439 | case LEU: | |
30cf4896 | 2440 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 2441 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
2442 | { |
2443 | *op1 = GEN_INT (i + 1); | |
2444 | return code == GTU ? GEU : LTU; | |
2445 | } | |
2446 | break; | |
2447 | ||
2448 | case GEU: | |
2449 | case LTU: | |
2450 | if (i != 0 | |
5895f793 | 2451 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
2452 | { |
2453 | *op1 = GEN_INT (i - 1); | |
2454 | return code == GEU ? GTU : LEU; | |
2455 | } | |
2456 | break; | |
2457 | ||
2458 | default: | |
e6d29d15 | 2459 | gcc_unreachable (); |
bd9c7e23 RE |
2460 | } |
2461 | ||
2462 | return code; | |
2463 | } | |
bd9c7e23 | 2464 | |
d4453b7a PB |
2465 | |
2466 | /* Define how to find the value returned by a function. */ | |
2467 | ||
9f7bf991 RE |
2468 | rtx |
2469 | arm_function_value(tree type, tree func ATTRIBUTE_UNUSED) | |
d4453b7a PB |
2470 | { |
2471 | enum machine_mode mode; | |
2472 | int unsignedp ATTRIBUTE_UNUSED; | |
2473 | rtx r ATTRIBUTE_UNUSED; | |
2474 | ||
d4453b7a PB |
2475 | mode = TYPE_MODE (type); |
2476 | /* Promote integer types. */ | |
2477 | if (INTEGRAL_TYPE_P (type)) | |
2478 | PROMOTE_FUNCTION_MODE (mode, unsignedp, type); | |
866af8a9 JB |
2479 | |
2480 | /* Promotes small structs returned in a register to full-word size | |
2481 | for big-endian AAPCS. */ | |
2482 | if (arm_return_in_msb (type)) | |
2483 | { | |
2484 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2485 | if (size % UNITS_PER_WORD != 0) | |
2486 | { | |
2487 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
2488 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
2489 | } | |
2490 | } | |
e0b92319 | 2491 | |
d4453b7a PB |
2492 | return LIBCALL_VALUE(mode); |
2493 | } | |
2494 | ||
e0b92319 | 2495 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
2496 | registers of an untyped call. */ |
2497 | int | |
2498 | arm_apply_result_size (void) | |
2499 | { | |
2500 | int size = 16; | |
2501 | ||
2502 | if (TARGET_ARM) | |
2503 | { | |
2504 | if (TARGET_HARD_FLOAT_ABI) | |
2505 | { | |
2506 | if (TARGET_FPA) | |
2507 | size += 12; | |
2508 | if (TARGET_MAVERICK) | |
2509 | size += 8; | |
2510 | } | |
2511 | if (TARGET_IWMMXT_ABI) | |
2512 | size += 8; | |
2513 | } | |
2514 | ||
2515 | return size; | |
2516 | } | |
d4453b7a | 2517 | |
f5a1b0d2 NC |
2518 | /* Decide whether a type should be returned in memory (true) |
2519 | or in a register (false). This is called by the macro | |
2520 | RETURN_IN_MEMORY. */ | |
2b835d68 | 2521 | int |
e32bac5b | 2522 | arm_return_in_memory (tree type) |
2b835d68 | 2523 | { |
dc0ba55a JT |
2524 | HOST_WIDE_INT size; |
2525 | ||
3dd7ab65 | 2526 | if (!AGGREGATE_TYPE_P (type) && |
30e5a198 | 2527 | (TREE_CODE (type) != VECTOR_TYPE) && |
3dd7ab65 JB |
2528 | !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) |
2529 | /* All simple types are returned in registers. | |
2530 | For AAPCS, complex types are treated the same as aggregates. */ | |
d7d01975 | 2531 | return 0; |
dc0ba55a JT |
2532 | |
2533 | size = int_size_in_bytes (type); | |
2534 | ||
5848830f | 2535 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 2536 | { |
5848830f | 2537 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
2538 | larger than a word (or are variable size). */ |
2539 | return (size < 0 || size > UNITS_PER_WORD); | |
2540 | } | |
f676971a | 2541 | |
30e5a198 JC |
2542 | /* To maximize backwards compatibility with previous versions of gcc, |
2543 | return vectors up to 4 words in registers. */ | |
2544 | if (TREE_CODE (type) == VECTOR_TYPE) | |
2545 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
2546 | ||
6bc82793 | 2547 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
2548 | ARM and Thumb compilers, which always return aggregates in memory. */ |
2549 | #ifndef ARM_WINCE | |
e529bd42 NC |
2550 | /* All structures/unions bigger than one word are returned in memory. |
2551 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 2552 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 2553 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 2554 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 2555 | return 1; |
f676971a | 2556 | |
d7d01975 | 2557 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
2558 | { |
2559 | tree field; | |
2560 | ||
3a2ea258 RE |
2561 | /* For a struct the APCS says that we only return in a register |
2562 | if the type is 'integer like' and every addressable element | |
2563 | has an offset of zero. For practical purposes this means | |
2564 | that the structure can have at most one non bit-field element | |
2565 | and that this element must be the first one in the structure. */ | |
f676971a | 2566 | |
f5a1b0d2 NC |
2567 | /* Find the first field, ignoring non FIELD_DECL things which will |
2568 | have been created by C++. */ | |
2569 | for (field = TYPE_FIELDS (type); | |
2570 | field && TREE_CODE (field) != FIELD_DECL; | |
2571 | field = TREE_CHAIN (field)) | |
2572 | continue; | |
f676971a | 2573 | |
f5a1b0d2 | 2574 | if (field == NULL) |
9e291dbe | 2575 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 2576 | |
d5b7b3ae RE |
2577 | /* Check that the first field is valid for returning in a register. */ |
2578 | ||
2579 | /* ... Floats are not allowed */ | |
9e291dbe | 2580 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
2581 | return 1; |
2582 | ||
d5b7b3ae RE |
2583 | /* ... Aggregates that are not themselves valid for returning in |
2584 | a register are not allowed. */ | |
9e291dbe | 2585 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
3a2ea258 | 2586 | return 1; |
6f7ebcbb | 2587 | |
3a2ea258 RE |
2588 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
2589 | since they are not addressable. */ | |
f5a1b0d2 NC |
2590 | for (field = TREE_CHAIN (field); |
2591 | field; | |
2592 | field = TREE_CHAIN (field)) | |
2593 | { | |
2594 | if (TREE_CODE (field) != FIELD_DECL) | |
2595 | continue; | |
f676971a | 2596 | |
5895f793 | 2597 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
2598 | return 1; |
2599 | } | |
2b835d68 RE |
2600 | |
2601 | return 0; | |
2602 | } | |
f676971a | 2603 | |
d7d01975 | 2604 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
2605 | { |
2606 | tree field; | |
2607 | ||
2608 | /* Unions can be returned in registers if every element is | |
2609 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
2610 | for (field = TYPE_FIELDS (type); |
2611 | field; | |
2612 | field = TREE_CHAIN (field)) | |
2b835d68 | 2613 | { |
f5a1b0d2 NC |
2614 | if (TREE_CODE (field) != FIELD_DECL) |
2615 | continue; | |
2616 | ||
6cc8c0b3 NC |
2617 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
2618 | return 1; | |
f676971a | 2619 | |
f5a1b0d2 | 2620 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
2b835d68 RE |
2621 | return 1; |
2622 | } | |
f676971a | 2623 | |
2b835d68 RE |
2624 | return 0; |
2625 | } | |
f676971a EC |
2626 | #endif /* not ARM_WINCE */ |
2627 | ||
d5b7b3ae | 2628 | /* Return all other types in memory. */ |
2b835d68 RE |
2629 | return 1; |
2630 | } | |
2631 | ||
d6b4baa4 | 2632 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
2633 | |
2634 | int | |
e32bac5b | 2635 | arm_float_words_big_endian (void) |
3717da94 | 2636 | { |
9b66ebb1 | 2637 | if (TARGET_MAVERICK) |
9b6b54e2 | 2638 | return 0; |
3717da94 JT |
2639 | |
2640 | /* For FPA, float words are always big-endian. For VFP, floats words | |
2641 | follow the memory system mode. */ | |
2642 | ||
9b66ebb1 | 2643 | if (TARGET_FPA) |
3717da94 | 2644 | { |
3717da94 JT |
2645 | return 1; |
2646 | } | |
2647 | ||
2648 | if (TARGET_VFP) | |
2649 | return (TARGET_BIG_END ? 1 : 0); | |
2650 | ||
2651 | return 1; | |
2652 | } | |
2653 | ||
82e9d970 PB |
2654 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
2655 | for a call to a function whose data type is FNTYPE. | |
2656 | For a library call, FNTYPE is NULL. */ | |
2657 | void | |
f676971a | 2658 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
e32bac5b RE |
2659 | rtx libname ATTRIBUTE_UNUSED, |
2660 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
2661 | { |
2662 | /* On the ARM, the offset starts at 0. */ | |
61f71b34 | 2663 | pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0); |
5a9335ef | 2664 | pcum->iwmmxt_nregs = 0; |
5848830f | 2665 | pcum->can_split = true; |
f676971a | 2666 | |
82e9d970 PB |
2667 | pcum->call_cookie = CALL_NORMAL; |
2668 | ||
2669 | if (TARGET_LONG_CALLS) | |
2670 | pcum->call_cookie = CALL_LONG; | |
f676971a | 2671 | |
82e9d970 PB |
2672 | /* Check for long call/short call attributes. The attributes |
2673 | override any command line option. */ | |
2674 | if (fntype) | |
2675 | { | |
2676 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) | |
2677 | pcum->call_cookie = CALL_SHORT; | |
2678 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) | |
2679 | pcum->call_cookie = CALL_LONG; | |
2680 | } | |
5a9335ef NC |
2681 | |
2682 | /* Varargs vectors are treated the same as long long. | |
2683 | named_count avoids having to change the way arm handles 'named' */ | |
2684 | pcum->named_count = 0; | |
2685 | pcum->nargs = 0; | |
2686 | ||
2687 | if (TARGET_REALLY_IWMMXT && fntype) | |
2688 | { | |
2689 | tree fn_arg; | |
2690 | ||
2691 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
2692 | fn_arg; | |
2693 | fn_arg = TREE_CHAIN (fn_arg)) | |
2694 | pcum->named_count += 1; | |
2695 | ||
2696 | if (! pcum->named_count) | |
2697 | pcum->named_count = INT_MAX; | |
2698 | } | |
82e9d970 PB |
2699 | } |
2700 | ||
5848830f PB |
2701 | |
2702 | /* Return true if mode/type need doubleword alignment. */ | |
2703 | bool | |
2704 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
2705 | { | |
65a939f7 PB |
2706 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
2707 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
2708 | } |
2709 | ||
2710 | ||
82e9d970 PB |
2711 | /* Determine where to put an argument to a function. |
2712 | Value is zero to push the argument on the stack, | |
2713 | or a hard register in which to store the argument. | |
2714 | ||
2715 | MODE is the argument's machine mode. | |
2716 | TYPE is the data type of the argument (as a tree). | |
2717 | This is null for libcalls where that information may | |
2718 | not be available. | |
2719 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2720 | the preceding args and about the function being called. | |
2721 | NAMED is nonzero if this argument is a named parameter | |
2722 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 2723 | |
82e9d970 | 2724 | rtx |
e32bac5b | 2725 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 2726 | tree type, int named) |
82e9d970 | 2727 | { |
5848830f PB |
2728 | int nregs; |
2729 | ||
2730 | /* Varargs vectors are treated the same as long long. | |
2731 | named_count avoids having to change the way arm handles 'named' */ | |
2732 | if (TARGET_IWMMXT_ABI | |
f676971a | 2733 | && arm_vector_mode_supported_p (mode) |
5848830f | 2734 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 2735 | { |
5848830f PB |
2736 | if (pcum->iwmmxt_nregs <= 9) |
2737 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
2738 | else | |
5a9335ef | 2739 | { |
5848830f PB |
2740 | pcum->can_split = false; |
2741 | return NULL_RTX; | |
5a9335ef | 2742 | } |
5a9335ef NC |
2743 | } |
2744 | ||
5848830f PB |
2745 | /* Put doubleword aligned quantities in even register pairs. */ |
2746 | if (pcum->nregs & 1 | |
2747 | && ARM_DOUBLEWORD_ALIGN | |
2748 | && arm_needs_doubleword_align (mode, type)) | |
2749 | pcum->nregs++; | |
2750 | ||
82e9d970 PB |
2751 | if (mode == VOIDmode) |
2752 | /* Compute operand 2 of the call insn. */ | |
2753 | return GEN_INT (pcum->call_cookie); | |
5848830f | 2754 | |
666c27b9 | 2755 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
2756 | args were allocated to regs. For args passed by reference we only count |
2757 | the reference pointer. */ | |
2758 | if (pcum->can_split) | |
2759 | nregs = 1; | |
2760 | else | |
2761 | nregs = ARM_NUM_REGS2 (mode, type); | |
2762 | ||
2763 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 2764 | return NULL_RTX; |
f676971a | 2765 | |
82e9d970 PB |
2766 | return gen_rtx_REG (mode, pcum->nregs); |
2767 | } | |
1741620c | 2768 | |
78a52f11 RH |
2769 | static int |
2770 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
2771 | tree type, bool named ATTRIBUTE_UNUSED) | |
2772 | { | |
2773 | int nregs = pcum->nregs; | |
2774 | ||
2775 | if (arm_vector_mode_supported_p (mode)) | |
2776 | return 0; | |
2777 | ||
2778 | if (NUM_ARG_REGS > nregs | |
2779 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
2780 | && pcum->can_split) | |
2781 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
2782 | ||
2783 | return 0; | |
2784 | } | |
2785 | ||
1741620c JD |
2786 | /* Variable sized types are passed by reference. This is a GCC |
2787 | extension to the ARM ABI. */ | |
2788 | ||
8cd5a4e0 RH |
2789 | static bool |
2790 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
2791 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
2792 | tree type, bool named ATTRIBUTE_UNUSED) | |
1741620c JD |
2793 | { |
2794 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
2795 | } | |
82e9d970 | 2796 | \f |
c27ba912 DM |
2797 | /* Encode the current state of the #pragma [no_]long_calls. */ |
2798 | typedef enum | |
82e9d970 | 2799 | { |
c27ba912 DM |
2800 | OFF, /* No #pramgma [no_]long_calls is in effect. */ |
2801 | LONG, /* #pragma long_calls is in effect. */ | |
2802 | SHORT /* #pragma no_long_calls is in effect. */ | |
2803 | } arm_pragma_enum; | |
82e9d970 | 2804 | |
c27ba912 | 2805 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 2806 | |
8b97c5f8 | 2807 | void |
e32bac5b | 2808 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 2809 | { |
8b97c5f8 ZW |
2810 | arm_pragma_long_calls = LONG; |
2811 | } | |
2812 | ||
2813 | void | |
e32bac5b | 2814 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2815 | { |
2816 | arm_pragma_long_calls = SHORT; | |
2817 | } | |
2818 | ||
2819 | void | |
e32bac5b | 2820 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2821 | { |
2822 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
2823 | } |
2824 | \f | |
91d231cb JM |
2825 | /* Table of machine attributes. */ |
2826 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 2827 | { |
91d231cb | 2828 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
2829 | /* Function calls made to this symbol must be done indirectly, because |
2830 | it may lie outside of the 26 bit addressing range of a normal function | |
2831 | call. */ | |
91d231cb | 2832 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
2833 | /* Whereas these functions are always known to reside within the 26 bit |
2834 | addressing range. */ | |
91d231cb | 2835 | { "short_call", 0, 0, false, true, true, NULL }, |
f676971a | 2836 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
2837 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
2838 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
2839 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2840 | #ifdef ARM_PE | |
2841 | /* ARM/PE has three new attributes: | |
2842 | interfacearm - ? | |
2843 | dllexport - for exporting a function/variable that will live in a dll | |
2844 | dllimport - for importing a function/variable from a dll | |
2845 | ||
2846 | Microsoft allows multiple declspecs in one __declspec, separating | |
2847 | them with spaces. We do NOT support this. Instead, use __declspec | |
2848 | multiple times. | |
2849 | */ | |
2850 | { "dllimport", 0, 0, true, false, false, NULL }, | |
2851 | { "dllexport", 0, 0, true, false, false, NULL }, | |
2852 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
b2ca3702 MM |
2853 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES |
2854 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, | |
2855 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, | |
04fb56d5 | 2856 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, |
91d231cb JM |
2857 | #endif |
2858 | { NULL, 0, 0, false, false, false, NULL } | |
2859 | }; | |
6d3d9133 | 2860 | |
91d231cb JM |
2861 | /* Handle an attribute requiring a FUNCTION_DECL; |
2862 | arguments as in struct attribute_spec.handler. */ | |
2863 | static tree | |
e32bac5b RE |
2864 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
2865 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
2866 | { |
2867 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2868 | { | |
5c498b10 | 2869 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
2870 | IDENTIFIER_POINTER (name)); |
2871 | *no_add_attrs = true; | |
2872 | } | |
2873 | ||
2874 | return NULL_TREE; | |
2875 | } | |
2876 | ||
2877 | /* Handle an "interrupt" or "isr" attribute; | |
2878 | arguments as in struct attribute_spec.handler. */ | |
2879 | static tree | |
e32bac5b RE |
2880 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
2881 | bool *no_add_attrs) | |
91d231cb JM |
2882 | { |
2883 | if (DECL_P (*node)) | |
2884 | { | |
2885 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2886 | { | |
5c498b10 | 2887 | warning (OPT_Wattributes, "%qs attribute only applies to functions", |
91d231cb JM |
2888 | IDENTIFIER_POINTER (name)); |
2889 | *no_add_attrs = true; | |
2890 | } | |
2891 | /* FIXME: the argument if any is checked for type attributes; | |
2892 | should it be checked for decl ones? */ | |
2893 | } | |
2894 | else | |
2895 | { | |
2896 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
2897 | || TREE_CODE (*node) == METHOD_TYPE) | |
2898 | { | |
2899 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
2900 | { | |
5c498b10 DD |
2901 | warning (OPT_Wattributes, "%qs attribute ignored", |
2902 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
2903 | *no_add_attrs = true; |
2904 | } | |
2905 | } | |
2906 | else if (TREE_CODE (*node) == POINTER_TYPE | |
2907 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
2908 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
2909 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
2910 | { | |
8dd16ecc | 2911 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
2912 | TREE_TYPE (*node) = build_type_attribute_variant |
2913 | (TREE_TYPE (*node), | |
2914 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
2915 | *no_add_attrs = true; |
2916 | } | |
2917 | else | |
2918 | { | |
2919 | /* Possibly pass this attribute on from the type to a decl. */ | |
2920 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
2921 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
2922 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
2923 | { | |
2924 | *no_add_attrs = true; | |
2925 | return tree_cons (name, args, NULL_TREE); | |
2926 | } | |
2927 | else | |
2928 | { | |
5c498b10 DD |
2929 | warning (OPT_Wattributes, "%qs attribute ignored", |
2930 | IDENTIFIER_POINTER (name)); | |
91d231cb JM |
2931 | } |
2932 | } | |
2933 | } | |
2934 | ||
2935 | return NULL_TREE; | |
82e9d970 PB |
2936 | } |
2937 | ||
7bff66a7 | 2938 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
2939 | /* Handle the "notshared" attribute. This attribute is another way of |
2940 | requesting hidden visibility. ARM's compiler supports | |
2941 | "__declspec(notshared)"; we support the same thing via an | |
2942 | attribute. */ | |
2943 | ||
2944 | static tree | |
e0b92319 NC |
2945 | arm_handle_notshared_attribute (tree *node, |
2946 | tree name ATTRIBUTE_UNUSED, | |
2947 | tree args ATTRIBUTE_UNUSED, | |
2948 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
2949 | bool *no_add_attrs) |
2950 | { | |
2951 | tree decl = TYPE_NAME (*node); | |
2952 | ||
2953 | if (decl) | |
2954 | { | |
2955 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
2956 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
2957 | *no_add_attrs = false; | |
2958 | } | |
2959 | return NULL_TREE; | |
2960 | } | |
7bff66a7 | 2961 | #endif |
04fb56d5 | 2962 | |
82e9d970 PB |
2963 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
2964 | are compatible, and 2 if they are nearly compatible (which causes a | |
2965 | warning to be generated). */ | |
8d8e52be | 2966 | static int |
e32bac5b | 2967 | arm_comp_type_attributes (tree type1, tree type2) |
82e9d970 | 2968 | { |
1cb8d58a | 2969 | int l1, l2, s1, s2; |
f676971a | 2970 | |
82e9d970 PB |
2971 | /* Check for mismatch of non-default calling convention. */ |
2972 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
2973 | return 1; | |
2974 | ||
2975 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
2976 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
2977 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
2978 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
2979 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
2980 | |
2981 | /* Only bother to check if an attribute is defined. */ | |
2982 | if (l1 | l2 | s1 | s2) | |
2983 | { | |
2984 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 2985 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 2986 | return 0; |
82e9d970 | 2987 | |
bd7fc26f NC |
2988 | /* Disallow mixed attributes. */ |
2989 | if ((l1 & s2) || (l2 & s1)) | |
2990 | return 0; | |
2991 | } | |
f676971a | 2992 | |
6d3d9133 NC |
2993 | /* Check for mismatched ISR attribute. */ |
2994 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
2995 | if (! l1) | |
2996 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
2997 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
2998 | if (! l2) | |
2999 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
3000 | if (l1 != l2) | |
3001 | return 0; | |
3002 | ||
bd7fc26f | 3003 | return 1; |
82e9d970 PB |
3004 | } |
3005 | ||
c27ba912 DM |
3006 | /* Encode long_call or short_call attribute by prefixing |
3007 | symbol name in DECL with a special character FLAG. */ | |
3008 | void | |
e32bac5b | 3009 | arm_encode_call_attribute (tree decl, int flag) |
c27ba912 | 3010 | { |
3cce094d | 3011 | const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
6354dc9b | 3012 | int len = strlen (str); |
d19fb8e3 | 3013 | char * newstr; |
c27ba912 | 3014 | |
c27ba912 DM |
3015 | /* Do not allow weak functions to be treated as short call. */ |
3016 | if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) | |
3017 | return; | |
c27ba912 | 3018 | |
520a57c8 ZW |
3019 | newstr = alloca (len + 2); |
3020 | newstr[0] = flag; | |
3021 | strcpy (newstr + 1, str); | |
c27ba912 | 3022 | |
6d3d9133 | 3023 | newstr = (char *) ggc_alloc_string (newstr, len + 1); |
c27ba912 DM |
3024 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
3025 | } | |
3026 | ||
3027 | /* Assigns default attributes to newly defined type. This is used to | |
3028 | set short_call/long_call attributes for function types of | |
3029 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 3030 | static void |
e32bac5b | 3031 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
3032 | { |
3033 | /* Add __attribute__ ((long_call)) to all functions, when | |
3034 | inside #pragma long_calls or __attribute__ ((short_call)), | |
3035 | when inside #pragma no_long_calls. */ | |
3036 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
3037 | { | |
3038 | tree type_attr_list, attr_name; | |
3039 | type_attr_list = TYPE_ATTRIBUTES (type); | |
3040 | ||
3041 | if (arm_pragma_long_calls == LONG) | |
3042 | attr_name = get_identifier ("long_call"); | |
3043 | else if (arm_pragma_long_calls == SHORT) | |
3044 | attr_name = get_identifier ("short_call"); | |
3045 | else | |
3046 | return; | |
3047 | ||
3048 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
3049 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
3050 | } | |
3051 | } | |
3052 | \f | |
3053 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be | |
6bc82793 | 3054 | defined within the current compilation unit. If this cannot be |
c27ba912 DM |
3055 | determined, then 0 is returned. */ |
3056 | static int | |
e32bac5b | 3057 | current_file_function_operand (rtx sym_ref) |
c27ba912 DM |
3058 | { |
3059 | /* This is a bit of a fib. A function will have a short call flag | |
3060 | applied to its name if it has the short call attribute, or it has | |
3061 | already been defined within the current compilation unit. */ | |
3062 | if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) | |
3063 | return 1; | |
3064 | ||
6d77b53e | 3065 | /* The current function is always defined within the current compilation |
a77655b1 | 3066 | unit. If it s a weak definition however, then this may not be the real |
d6a7951f | 3067 | definition of the function, and so we have to say no. */ |
c27ba912 | 3068 | if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) |
5895f793 | 3069 | && !DECL_WEAK (current_function_decl)) |
c27ba912 DM |
3070 | return 1; |
3071 | ||
3072 | /* We cannot make the determination - default to returning 0. */ | |
3073 | return 0; | |
3074 | } | |
3075 | ||
825dda42 | 3076 | /* Return nonzero if a 32 bit "long_call" should be generated for |
c27ba912 DM |
3077 | this call. We generate a long_call if the function: |
3078 | ||
3079 | a. has an __attribute__((long call)) | |
3080 | or b. is within the scope of a #pragma long_calls | |
3081 | or c. the -mlong-calls command line switch has been specified | |
a77655b1 NC |
3082 | . and either: |
3083 | 1. -ffunction-sections is in effect | |
3084 | or 2. the current function has __attribute__ ((section)) | |
3085 | or 3. the target function has __attribute__ ((section)) | |
c27ba912 DM |
3086 | |
3087 | However we do not generate a long call if the function: | |
f676971a | 3088 | |
c27ba912 DM |
3089 | d. has an __attribute__ ((short_call)) |
3090 | or e. is inside the scope of a #pragma no_long_calls | |
a77655b1 | 3091 | or f. is defined within the current compilation unit. |
f676971a | 3092 | |
c27ba912 | 3093 | This function will be called by C fragments contained in the machine |
a77655b1 | 3094 | description file. SYM_REF and CALL_COOKIE correspond to the matched |
c27ba912 DM |
3095 | rtl operands. CALL_SYMBOL is used to distinguish between |
3096 | two different callers of the function. It is set to 1 in the | |
3097 | "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" | |
3098 | and "call_value" patterns. This is because of the difference in the | |
3099 | SYM_REFs passed by these patterns. */ | |
3100 | int | |
e32bac5b | 3101 | arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) |
c27ba912 | 3102 | { |
5895f793 | 3103 | if (!call_symbol) |
c27ba912 DM |
3104 | { |
3105 | if (GET_CODE (sym_ref) != MEM) | |
3106 | return 0; | |
3107 | ||
3108 | sym_ref = XEXP (sym_ref, 0); | |
3109 | } | |
3110 | ||
3111 | if (GET_CODE (sym_ref) != SYMBOL_REF) | |
3112 | return 0; | |
3113 | ||
3114 | if (call_cookie & CALL_SHORT) | |
3115 | return 0; | |
3116 | ||
a77655b1 NC |
3117 | if (TARGET_LONG_CALLS) |
3118 | { | |
3119 | if (flag_function_sections | |
3120 | || DECL_SECTION_NAME (current_function_decl)) | |
c112cf2b | 3121 | /* c.3 is handled by the definition of the |
a77655b1 NC |
3122 | ARM_DECLARE_FUNCTION_SIZE macro. */ |
3123 | return 1; | |
3124 | } | |
3125 | ||
87e27392 | 3126 | if (current_file_function_operand (sym_ref)) |
c27ba912 | 3127 | return 0; |
f676971a | 3128 | |
c27ba912 DM |
3129 | return (call_cookie & CALL_LONG) |
3130 | || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) | |
3131 | || TARGET_LONG_CALLS; | |
3132 | } | |
f99fce0c | 3133 | |
825dda42 | 3134 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 3135 | static bool |
e32bac5b | 3136 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c RE |
3137 | { |
3138 | int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; | |
3139 | ||
5a9335ef NC |
3140 | if (cfun->machine->sibcall_blocked) |
3141 | return false; | |
3142 | ||
f99fce0c RE |
3143 | /* Never tailcall something for which we have no decl, or if we |
3144 | are in Thumb mode. */ | |
3145 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 3146 | return false; |
f99fce0c RE |
3147 | |
3148 | /* Get the calling method. */ | |
3149 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
3150 | call_type = CALL_SHORT; | |
3151 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
3152 | call_type = CALL_LONG; | |
3153 | ||
3154 | /* Cannot tail-call to long calls, since these are out of range of | |
3155 | a branch instruction. However, if not compiling PIC, we know | |
3156 | we can reach the symbol if it is in this compilation unit. */ | |
5895f793 | 3157 | if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) |
4977bab6 | 3158 | return false; |
f99fce0c RE |
3159 | |
3160 | /* If we are interworking and the function is not declared static | |
f676971a | 3161 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 3162 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 3163 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 3164 | return false; |
f99fce0c | 3165 | |
6d3d9133 NC |
3166 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
3167 | if (IS_INTERRUPT (arm_current_func_type ())) | |
4977bab6 | 3168 | return false; |
6d3d9133 | 3169 | |
f99fce0c | 3170 | /* Everything else is ok. */ |
4977bab6 | 3171 | return true; |
f99fce0c RE |
3172 | } |
3173 | ||
82e9d970 | 3174 | \f |
6b990f6b RE |
3175 | /* Addressing mode support functions. */ |
3176 | ||
0b4be7de | 3177 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 3178 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 3179 | int |
e32bac5b | 3180 | legitimate_pic_operand_p (rtx x) |
32de079a | 3181 | { |
020a4035 RE |
3182 | if (GET_CODE (x) == SYMBOL_REF |
3183 | || (GET_CODE (x) == CONST | |
3184 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3185 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
3186 | return 0; |
3187 | ||
3188 | return 1; | |
3189 | } | |
3190 | ||
3191 | rtx | |
e32bac5b | 3192 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 3193 | { |
a3c48721 RE |
3194 | if (GET_CODE (orig) == SYMBOL_REF |
3195 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 3196 | { |
5f37d07c | 3197 | #ifndef AOF_ASSEMBLER |
32de079a | 3198 | rtx pic_ref, address; |
5f37d07c | 3199 | #endif |
32de079a RE |
3200 | rtx insn; |
3201 | int subregs = 0; | |
3202 | ||
020a4035 RE |
3203 | /* If this function doesn't have a pic register, create one now. |
3204 | A lot of the logic here is made obscure by the fact that this | |
3205 | routine gets called as part of the rtx cost estimation | |
3206 | process. We don't want those calls to affect any assumptions | |
3207 | about the real function; and further, we can't call | |
3208 | entry_of_function() until we start the real expansion | |
3209 | process. */ | |
3210 | if (!current_function_uses_pic_offset_table) | |
3211 | { | |
3212 | gcc_assert (!no_new_pseudos); | |
3213 | if (arm_pic_register != INVALID_REGNUM) | |
3214 | { | |
3215 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
3216 | ||
3217 | /* Play games to avoid marking the function as needing pic | |
3218 | if we are being called as part of the cost-estimation | |
3219 | process. */ | |
3220 | if (!ir_type()) | |
3221 | current_function_uses_pic_offset_table = 1; | |
3222 | } | |
3223 | else | |
3224 | { | |
3225 | rtx seq; | |
3226 | ||
3227 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
3228 | ||
3229 | /* Play games to avoid marking the function as needing pic | |
3230 | if we are being called as part of the cost-estimation | |
3231 | process. */ | |
3232 | if (!ir_type()) | |
3233 | { | |
3234 | current_function_uses_pic_offset_table = 1; | |
3235 | start_sequence (); | |
3236 | ||
3237 | arm_load_pic_register (0UL); | |
3238 | ||
3239 | seq = get_insns (); | |
3240 | end_sequence (); | |
3241 | emit_insn_after (seq, entry_of_function ()); | |
3242 | } | |
3243 | } | |
3244 | } | |
3245 | ||
32de079a RE |
3246 | if (reg == 0) |
3247 | { | |
e6d29d15 NS |
3248 | gcc_assert (!no_new_pseudos); |
3249 | reg = gen_reg_rtx (Pmode); | |
32de079a RE |
3250 | |
3251 | subregs = 1; | |
3252 | } | |
3253 | ||
3254 | #ifdef AOF_ASSEMBLER | |
3255 | /* The AOF assembler can generate relocations for these directly, and | |
6354dc9b | 3256 | understands that the PIC register has to be added into the offset. */ |
32de079a RE |
3257 | insn = emit_insn (gen_pic_load_addr_based (reg, orig)); |
3258 | #else | |
3259 | if (subregs) | |
3260 | address = gen_reg_rtx (Pmode); | |
3261 | else | |
3262 | address = reg; | |
3263 | ||
4bec9f7d NC |
3264 | if (TARGET_ARM) |
3265 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
3266 | else | |
3267 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
32de079a | 3268 | |
14f583b8 | 3269 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 3270 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 3271 | SYMBOL_REF_LOCAL_P (orig))) |
14f583b8 | 3272 | && NEED_GOT_RELOC) |
020a4035 | 3273 | pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); |
a3c48721 RE |
3274 | else |
3275 | { | |
542a8afa | 3276 | pic_ref = gen_const_mem (Pmode, |
020a4035 | 3277 | gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, |
542a8afa | 3278 | address)); |
a3c48721 RE |
3279 | } |
3280 | ||
32de079a RE |
3281 | insn = emit_move_insn (reg, pic_ref); |
3282 | #endif | |
32de079a RE |
3283 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
3284 | by loop. */ | |
43cffd11 RE |
3285 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, |
3286 | REG_NOTES (insn)); | |
32de079a RE |
3287 | return reg; |
3288 | } | |
3289 | else if (GET_CODE (orig) == CONST) | |
3290 | { | |
3291 | rtx base, offset; | |
3292 | ||
3293 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 3294 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
3295 | return orig; |
3296 | ||
d3585b76 DJ |
3297 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
3298 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
3299 | return orig; | |
3300 | ||
32de079a RE |
3301 | if (reg == 0) |
3302 | { | |
e6d29d15 NS |
3303 | gcc_assert (!no_new_pseudos); |
3304 | reg = gen_reg_rtx (Pmode); | |
32de079a RE |
3305 | } |
3306 | ||
e6d29d15 | 3307 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 3308 | |
e6d29d15 NS |
3309 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3310 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3311 | base == reg ? 0 : reg); | |
32de079a RE |
3312 | |
3313 | if (GET_CODE (offset) == CONST_INT) | |
3314 | { | |
3315 | /* The base register doesn't really matter, we only want to | |
3316 | test the index for the appropriate mode. */ | |
1e1ab407 | 3317 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 3318 | { |
c4db6655 | 3319 | gcc_assert (!no_new_pseudos); |
e6d29d15 | 3320 | offset = force_reg (Pmode, offset); |
6b990f6b | 3321 | } |
32de079a | 3322 | |
32de079a | 3323 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 3324 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
3325 | } |
3326 | ||
3327 | if (GET_MODE_SIZE (mode) > 4 | |
3328 | && (GET_MODE_CLASS (mode) == MODE_INT | |
3329 | || TARGET_SOFT_FLOAT)) | |
3330 | { | |
3331 | emit_insn (gen_addsi3 (reg, base, offset)); | |
3332 | return reg; | |
3333 | } | |
3334 | ||
43cffd11 | 3335 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 3336 | } |
32de079a RE |
3337 | |
3338 | return orig; | |
3339 | } | |
3340 | ||
57934c39 | 3341 | |
b279b20a | 3342 | /* Find a spare low register to use during the prolog of a function. */ |
57934c39 PB |
3343 | |
3344 | static int | |
b279b20a | 3345 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
3346 | { |
3347 | int reg; | |
3348 | ||
b279b20a NC |
3349 | /* Check the argument registers first as these are call-used. The |
3350 | register allocation order means that sometimes r3 might be used | |
3351 | but earlier argument registers might not, so check them all. */ | |
3352 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
3353 | if (!regs_ever_live[reg]) | |
3354 | return reg; | |
3355 | ||
3356 | /* Before going on to check the call-saved registers we can try a couple | |
3357 | more ways of deducing that r3 is available. The first is when we are | |
3358 | pushing anonymous arguments onto the stack and we have less than 4 | |
3359 | registers worth of fixed arguments(*). In this case r3 will be part of | |
3360 | the variable argument list and so we can be sure that it will be | |
3361 | pushed right at the start of the function. Hence it will be available | |
3362 | for the rest of the prologue. | |
3363 | (*): ie current_function_pretend_args_size is greater than 0. */ | |
3364 | if (cfun->machine->uses_anonymous_args | |
3365 | && current_function_pretend_args_size > 0) | |
57934c39 PB |
3366 | return LAST_ARG_REGNUM; |
3367 | ||
b279b20a NC |
3368 | /* The other case is when we have fixed arguments but less than 4 registers |
3369 | worth. In this case r3 might be used in the body of the function, but | |
3370 | it is not being used to convey an argument into the function. In theory | |
3371 | we could just check current_function_args_size to see how many bytes are | |
3372 | being passed in argument registers, but it seems that it is unreliable. | |
3373 | Sometimes it will have the value 0 when in fact arguments are being | |
3374 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
3375 | check the args_info.nregs field as well. The problem with this field is | |
3376 | that it makes no allowances for arguments that are passed to the | |
3377 | function but which are not used. Hence we could miss an opportunity | |
3378 | when a function has an unused argument in r3. But it is better to be | |
3379 | safe than to be sorry. */ | |
3380 | if (! cfun->machine->uses_anonymous_args | |
3381 | && current_function_args_size >= 0 | |
3382 | && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
3383 | && cfun->args_info.nregs < 4) | |
3384 | return LAST_ARG_REGNUM; | |
e0b92319 | 3385 | |
b279b20a NC |
3386 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
3387 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
3388 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
3389 | return reg; |
3390 | ||
b279b20a NC |
3391 | /* Something went wrong - thumb_compute_save_reg_mask() |
3392 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 3393 | gcc_unreachable (); |
57934c39 PB |
3394 | } |
3395 | ||
f16fe45f | 3396 | static GTY(()) int pic_labelno; |
876f13b0 | 3397 | |
fe013435 PB |
3398 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
3399 | low register. */ | |
876f13b0 | 3400 | |
32de079a | 3401 | void |
e55ef7f4 | 3402 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a RE |
3403 | { |
3404 | #ifndef AOF_ASSEMBLER | |
f16fe45f | 3405 | rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx; |
32de079a RE |
3406 | rtx global_offset_table; |
3407 | ||
ed0e6530 | 3408 | if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
3409 | return; |
3410 | ||
e6d29d15 | 3411 | gcc_assert (flag_pic); |
32de079a | 3412 | |
f16fe45f DJ |
3413 | /* We use an UNSPEC rather than a LABEL_REF because this label never appears |
3414 | in the code stream. */ | |
3415 | ||
3416 | labelno = GEN_INT (pic_labelno++); | |
3417 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3418 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
32de079a | 3419 | |
43cffd11 | 3420 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
dfa08768 | 3421 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
d5b7b3ae | 3422 | addition, on the Thumb it is 'dot + 4'. */ |
f16fe45f | 3423 | pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4); |
84306176 PB |
3424 | if (GOT_PCREL) |
3425 | pic_tmp2 = gen_rtx_CONST (VOIDmode, | |
43cffd11 | 3426 | gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); |
84306176 PB |
3427 | else |
3428 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); | |
43cffd11 RE |
3429 | |
3430 | pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); | |
f676971a | 3431 | |
d5b7b3ae | 3432 | if (TARGET_ARM) |
4bec9f7d | 3433 | { |
020a4035 RE |
3434 | emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx)); |
3435 | emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg, | |
3436 | cfun->machine->pic_reg, labelno)); | |
4bec9f7d | 3437 | } |
d5b7b3ae | 3438 | else |
4bec9f7d | 3439 | { |
020a4035 RE |
3440 | if (arm_pic_register != INVALID_REGNUM |
3441 | && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM) | |
876f13b0 | 3442 | { |
e55ef7f4 | 3443 | /* We will have pushed the pic register, so we should always be |
876f13b0 | 3444 | able to find a work register. */ |
e55ef7f4 RE |
3445 | pic_tmp = gen_rtx_REG (SImode, |
3446 | thumb_find_work_register (saved_regs)); | |
876f13b0 PB |
3447 | emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx)); |
3448 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
3449 | } | |
3450 | else | |
020a4035 RE |
3451 | emit_insn (gen_pic_load_addr_thumb (cfun->machine->pic_reg, pic_rtx)); |
3452 | emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg, | |
3453 | cfun->machine->pic_reg, labelno)); | |
4bec9f7d | 3454 | } |
32de079a | 3455 | |
32de079a RE |
3456 | /* Need to emit this whether or not we obey regdecls, |
3457 | since setjmp/longjmp can cause life info to screw up. */ | |
020a4035 | 3458 | emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg)); |
32de079a RE |
3459 | #endif /* AOF_ASSEMBLER */ |
3460 | } | |
3461 | ||
876f13b0 | 3462 | |
6b990f6b RE |
3463 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
3464 | static int | |
e32bac5b | 3465 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
3466 | { |
3467 | int regno; | |
3468 | ||
3469 | if (GET_CODE (x) != REG) | |
3470 | return 0; | |
3471 | ||
3472 | regno = REGNO (x); | |
3473 | ||
3474 | if (strict_p) | |
3475 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
3476 | ||
3477 | return (regno <= LAST_ARM_REGNUM | |
3478 | || regno >= FIRST_PSEUDO_REGISTER | |
3479 | || regno == FRAME_POINTER_REGNUM | |
3480 | || regno == ARG_POINTER_REGNUM); | |
3481 | } | |
3482 | ||
d3585b76 DJ |
3483 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
3484 | and will reduce to a PC-relative relocation in the object file. | |
3485 | Expressions like this can be left alone when generating PIC, rather | |
3486 | than forced through the GOT. */ | |
3487 | static int | |
3488 | pcrel_constant_p (rtx x) | |
3489 | { | |
3490 | if (GET_CODE (x) == MINUS) | |
3491 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
3492 | ||
3493 | return FALSE; | |
3494 | } | |
3495 | ||
6b990f6b RE |
3496 | /* Return nonzero if X is a valid ARM state address operand. */ |
3497 | int | |
1e1ab407 RE |
3498 | arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
3499 | int strict_p) | |
6b990f6b | 3500 | { |
fdd695fd PB |
3501 | bool use_ldrd; |
3502 | enum rtx_code code = GET_CODE (x); | |
f676971a | 3503 | |
6b990f6b RE |
3504 | if (arm_address_register_rtx_p (x, strict_p)) |
3505 | return 1; | |
3506 | ||
fdd695fd PB |
3507 | use_ldrd = (TARGET_LDRD |
3508 | && (mode == DImode | |
3509 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
3510 | ||
3511 | if (code == POST_INC || code == PRE_DEC | |
3512 | || ((code == PRE_INC || code == POST_DEC) | |
3513 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
3514 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
3515 | ||
fdd695fd | 3516 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
3517 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
3518 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 3519 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
3520 | { |
3521 | rtx addend = XEXP (XEXP (x, 1), 1); | |
3522 | ||
112cdef5 | 3523 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
3524 | to fixup invalid register choices. */ |
3525 | if (use_ldrd | |
3526 | && GET_CODE (x) == POST_MODIFY | |
3527 | && GET_CODE (addend) == REG) | |
3528 | return 0; | |
3529 | ||
3530 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
3531 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
3532 | } | |
6b990f6b RE |
3533 | |
3534 | /* After reload constants split into minipools will have addresses | |
3535 | from a LABEL_REF. */ | |
0bfb39ef | 3536 | else if (reload_completed |
fdd695fd PB |
3537 | && (code == LABEL_REF |
3538 | || (code == CONST | |
6b990f6b RE |
3539 | && GET_CODE (XEXP (x, 0)) == PLUS |
3540 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3541 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3542 | return 1; | |
3543 | ||
3544 | else if (mode == TImode) | |
3545 | return 0; | |
3546 | ||
fdd695fd | 3547 | else if (code == PLUS) |
6b990f6b RE |
3548 | { |
3549 | rtx xop0 = XEXP (x, 0); | |
3550 | rtx xop1 = XEXP (x, 1); | |
3551 | ||
3552 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3553 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
6b990f6b | 3554 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 3555 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
3556 | } |
3557 | ||
3558 | #if 0 | |
3559 | /* Reload currently can't handle MINUS, so disable this for now */ | |
3560 | else if (GET_CODE (x) == MINUS) | |
3561 | { | |
3562 | rtx xop0 = XEXP (x, 0); | |
3563 | rtx xop1 = XEXP (x, 1); | |
3564 | ||
3565 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3566 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
3567 | } |
3568 | #endif | |
3569 | ||
3570 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 3571 | && code == SYMBOL_REF |
6b990f6b RE |
3572 | && CONSTANT_POOL_ADDRESS_P (x) |
3573 | && ! (flag_pic | |
d3585b76 DJ |
3574 | && symbol_mentioned_p (get_pool_constant (x)) |
3575 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
3576 | return 1; |
3577 | ||
6b990f6b RE |
3578 | return 0; |
3579 | } | |
3580 | ||
3581 | /* Return nonzero if INDEX is valid for an address index operand in | |
3582 | ARM state. */ | |
3583 | static int | |
1e1ab407 RE |
3584 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
3585 | int strict_p) | |
6b990f6b RE |
3586 | { |
3587 | HOST_WIDE_INT range; | |
3588 | enum rtx_code code = GET_CODE (index); | |
3589 | ||
778ebdd9 PB |
3590 | /* Standard coprocessor addressing modes. */ |
3591 | if (TARGET_HARD_FLOAT | |
3592 | && (TARGET_FPA || TARGET_MAVERICK) | |
3593 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3594 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
3595 | return (code == CONST_INT && INTVAL (index) < 1024 |
3596 | && INTVAL (index) > -1024 | |
3597 | && (INTVAL (index) & 3) == 0); | |
3598 | ||
5a9335ef NC |
3599 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
3600 | return (code == CONST_INT | |
3657dc3e PB |
3601 | && INTVAL (index) < 1024 |
3602 | && INTVAL (index) > -1024 | |
3603 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 3604 | |
fdd695fd PB |
3605 | if (arm_address_register_rtx_p (index, strict_p) |
3606 | && (GET_MODE_SIZE (mode) <= 4)) | |
3607 | return 1; | |
3608 | ||
3609 | if (mode == DImode || mode == DFmode) | |
3610 | { | |
3611 | if (code == CONST_INT) | |
3612 | { | |
3613 | HOST_WIDE_INT val = INTVAL (index); | |
3614 | ||
3615 | if (TARGET_LDRD) | |
3616 | return val > -256 && val < 256; | |
3617 | else | |
f372c932 | 3618 | return val > -4096 && val < 4092; |
fdd695fd PB |
3619 | } |
3620 | ||
3621 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
3622 | } | |
3623 | ||
6b990f6b | 3624 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
3625 | && ! (arm_arch4 |
3626 | && (mode == HImode | |
3627 | || (mode == QImode && outer == SIGN_EXTEND)))) | |
6b990f6b | 3628 | { |
1e1ab407 RE |
3629 | if (code == MULT) |
3630 | { | |
3631 | rtx xiop0 = XEXP (index, 0); | |
3632 | rtx xiop1 = XEXP (index, 1); | |
3633 | ||
3634 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
3635 | && power_of_two_operand (xiop1, SImode)) | |
3636 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
3637 | && power_of_two_operand (xiop0, SImode))); | |
3638 | } | |
3639 | else if (code == LSHIFTRT || code == ASHIFTRT | |
3640 | || code == ASHIFT || code == ROTATERT) | |
3641 | { | |
3642 | rtx op = XEXP (index, 1); | |
6b990f6b | 3643 | |
1e1ab407 RE |
3644 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
3645 | && GET_CODE (op) == CONST_INT | |
3646 | && INTVAL (op) > 0 | |
3647 | && INTVAL (op) <= 31); | |
3648 | } | |
6b990f6b RE |
3649 | } |
3650 | ||
1e1ab407 RE |
3651 | /* For ARM v4 we may be doing a sign-extend operation during the |
3652 | load. */ | |
e1471c91 | 3653 | if (arm_arch4) |
1e1ab407 RE |
3654 | { |
3655 | if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) | |
3656 | range = 256; | |
3657 | else | |
3658 | range = 4096; | |
3659 | } | |
e1471c91 RE |
3660 | else |
3661 | range = (mode == HImode) ? 4095 : 4096; | |
6b990f6b RE |
3662 | |
3663 | return (code == CONST_INT | |
3664 | && INTVAL (index) < range | |
3665 | && INTVAL (index) > -range); | |
76a318e9 RE |
3666 | } |
3667 | ||
edf7cee8 | 3668 | /* Return nonzero if X is valid as a Thumb state base register. */ |
76a318e9 | 3669 | static int |
e32bac5b | 3670 | thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
3671 | { |
3672 | int regno; | |
3673 | ||
3674 | if (GET_CODE (x) != REG) | |
3675 | return 0; | |
3676 | ||
3677 | regno = REGNO (x); | |
3678 | ||
3679 | if (strict_p) | |
3680 | return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); | |
3681 | ||
3682 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 3683 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
3684 | || regno == FRAME_POINTER_REGNUM |
3685 | || (GET_MODE_SIZE (mode) >= 4 | |
3686 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 3687 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
3688 | || x == hard_frame_pointer_rtx |
3689 | || x == arg_pointer_rtx))); | |
3690 | } | |
3691 | ||
3692 | /* Return nonzero if x is a legitimate index register. This is the case | |
3693 | for any base register that can access a QImode object. */ | |
3694 | inline static int | |
e32bac5b | 3695 | thumb_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 RE |
3696 | { |
3697 | return thumb_base_register_rtx_p (x, QImode, strict_p); | |
3698 | } | |
3699 | ||
3700 | /* Return nonzero if x is a legitimate Thumb-state address. | |
f676971a | 3701 | |
76a318e9 RE |
3702 | The AP may be eliminated to either the SP or the FP, so we use the |
3703 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
3704 | ||
3705 | ??? Verify whether the above is the right approach. | |
3706 | ||
3707 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
3708 | needs special handling also. | |
3709 | ||
3710 | ??? Look at how the mips16 port solves this problem. It probably uses | |
3711 | better ways to solve some of these problems. | |
3712 | ||
3713 | Although it is not incorrect, we don't accept QImode and HImode | |
3714 | addresses based on the frame pointer or arg pointer until the | |
3715 | reload pass starts. This is so that eliminating such addresses | |
3716 | into stack based ones won't produce impossible code. */ | |
3717 | int | |
e32bac5b | 3718 | thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
3719 | { |
3720 | /* ??? Not clear if this is right. Experiment. */ | |
3721 | if (GET_MODE_SIZE (mode) < 4 | |
3722 | && !(reload_in_progress || reload_completed) | |
3723 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
3724 | || reg_mentioned_p (arg_pointer_rtx, x) | |
3725 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
3726 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
3727 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
3728 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
3729 | return 0; | |
3730 | ||
3731 | /* Accept any base register. SP only in SImode or larger. */ | |
3732 | else if (thumb_base_register_rtx_p (x, mode, strict_p)) | |
3733 | return 1; | |
3734 | ||
18dbd950 | 3735 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
3736 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
3737 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 3738 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
3739 | return 1; |
3740 | ||
18dbd950 | 3741 | /* This is PC relative data after arm_reorg runs. */ |
76a318e9 RE |
3742 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed |
3743 | && (GET_CODE (x) == LABEL_REF | |
3744 | || (GET_CODE (x) == CONST | |
3745 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3746 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3747 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3748 | return 1; | |
3749 | ||
3750 | /* Post-inc indexing only supported for SImode and larger. */ | |
3751 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
3752 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) | |
3753 | return 1; | |
3754 | ||
3755 | else if (GET_CODE (x) == PLUS) | |
3756 | { | |
3757 | /* REG+REG address can be any two index registers. */ | |
3758 | /* We disallow FRAME+REG addressing since we know that FRAME | |
3759 | will be replaced with STACK, and SP relative addressing only | |
3760 | permits SP+OFFSET. */ | |
3761 | if (GET_MODE_SIZE (mode) <= 4 | |
3762 | && XEXP (x, 0) != frame_pointer_rtx | |
3763 | && XEXP (x, 1) != frame_pointer_rtx | |
76a318e9 RE |
3764 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) |
3765 | && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
3766 | return 1; | |
3767 | ||
3768 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
3769 | else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
3770 | || XEXP (x, 0) == arg_pointer_rtx) | |
3771 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3772 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
3773 | return 1; | |
3774 | ||
3775 | /* REG+const has 10 bit offset for SP, but only SImode and | |
3776 | larger is supported. */ | |
3777 | /* ??? Should probably check for DI/DFmode overflow here | |
3778 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
3779 | else if (GET_CODE (XEXP (x, 0)) == REG | |
3780 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
3781 | && GET_MODE_SIZE (mode) >= 4 | |
3782 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3783 | && INTVAL (XEXP (x, 1)) >= 0 | |
3784 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
3785 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
3786 | return 1; | |
3787 | ||
3788 | else if (GET_CODE (XEXP (x, 0)) == REG | |
3789 | && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM | |
3790 | && GET_MODE_SIZE (mode) >= 4 | |
3791 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3792 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
3793 | return 1; | |
3794 | } | |
3795 | ||
3796 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 3797 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
3798 | && GET_CODE (x) == SYMBOL_REF |
3799 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
3800 | && ! (flag_pic |
3801 | && symbol_mentioned_p (get_pool_constant (x)) | |
3802 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
3803 | return 1; |
3804 | ||
3805 | return 0; | |
3806 | } | |
3807 | ||
3808 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
3809 | instruction of mode MODE. */ | |
3810 | int | |
e32bac5b | 3811 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
3812 | { |
3813 | switch (GET_MODE_SIZE (mode)) | |
3814 | { | |
3815 | case 1: | |
3816 | return val >= 0 && val < 32; | |
3817 | ||
3818 | case 2: | |
3819 | return val >= 0 && val < 64 && (val & 1) == 0; | |
3820 | ||
3821 | default: | |
3822 | return (val >= 0 | |
3823 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
3824 | && (val & 3) == 0); | |
3825 | } | |
3826 | } | |
3827 | ||
d3585b76 DJ |
3828 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
3829 | ||
3830 | static GTY(()) rtx tls_get_addr_libfunc; | |
3831 | ||
3832 | static rtx | |
3833 | get_tls_get_addr (void) | |
3834 | { | |
3835 | if (!tls_get_addr_libfunc) | |
3836 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
3837 | return tls_get_addr_libfunc; | |
3838 | } | |
3839 | ||
3840 | static rtx | |
3841 | arm_load_tp (rtx target) | |
3842 | { | |
3843 | if (!target) | |
3844 | target = gen_reg_rtx (SImode); | |
3845 | ||
3846 | if (TARGET_HARD_TP) | |
3847 | { | |
3848 | /* Can return in any reg. */ | |
3849 | emit_insn (gen_load_tp_hard (target)); | |
3850 | } | |
3851 | else | |
3852 | { | |
3853 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
3854 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
3855 | clobber the value. */ | |
3856 | ||
3857 | rtx tmp; | |
3858 | ||
3859 | emit_insn (gen_load_tp_soft ()); | |
3860 | ||
3861 | tmp = gen_rtx_REG (SImode, 0); | |
3862 | emit_move_insn (target, tmp); | |
3863 | } | |
3864 | return target; | |
3865 | } | |
3866 | ||
3867 | static rtx | |
3868 | load_tls_operand (rtx x, rtx reg) | |
3869 | { | |
3870 | rtx tmp; | |
3871 | ||
3872 | if (reg == NULL_RTX) | |
3873 | reg = gen_reg_rtx (SImode); | |
3874 | ||
3875 | tmp = gen_rtx_CONST (SImode, x); | |
3876 | ||
3877 | emit_move_insn (reg, tmp); | |
3878 | ||
3879 | return reg; | |
3880 | } | |
3881 | ||
3882 | static rtx | |
3883 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
3884 | { | |
f16fe45f | 3885 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
3886 | |
3887 | start_sequence (); | |
3888 | ||
f16fe45f DJ |
3889 | labelno = GEN_INT (pic_labelno++); |
3890 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3891 | label = gen_rtx_CONST (VOIDmode, label); | |
3892 | ||
d3585b76 | 3893 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 3894 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
3895 | GEN_INT (TARGET_ARM ? 8 : 4)), |
3896 | UNSPEC_TLS); | |
3897 | reg = load_tls_operand (sum, reg); | |
3898 | ||
3899 | if (TARGET_ARM) | |
f16fe45f | 3900 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
d3585b76 | 3901 | else |
f16fe45f | 3902 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
3903 | |
3904 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
3905 | Pmode, 1, reg, Pmode); | |
3906 | ||
3907 | insns = get_insns (); | |
3908 | end_sequence (); | |
3909 | ||
3910 | return insns; | |
3911 | } | |
3912 | ||
3913 | rtx | |
3914 | legitimize_tls_address (rtx x, rtx reg) | |
3915 | { | |
f16fe45f | 3916 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
3917 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
3918 | ||
3919 | switch (model) | |
3920 | { | |
3921 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3922 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
3923 | dest = gen_reg_rtx (Pmode); | |
3924 | emit_libcall_block (insns, dest, ret, x); | |
3925 | return dest; | |
3926 | ||
3927 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3928 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
3929 | ||
3930 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
3931 | share the LDM result with other LD model accesses. */ | |
3932 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
3933 | UNSPEC_TLS); | |
3934 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 3935 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
3936 | |
3937 | /* Load the addend. */ | |
3938 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
3939 | UNSPEC_TLS); | |
3940 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
3941 | return gen_rtx_PLUS (Pmode, dest, addend); | |
3942 | ||
3943 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
3944 | labelno = GEN_INT (pic_labelno++); |
3945 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3946 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 3947 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 3948 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
3949 | GEN_INT (TARGET_ARM ? 8 : 4)), |
3950 | UNSPEC_TLS); | |
3951 | reg = load_tls_operand (sum, reg); | |
3952 | ||
3953 | if (TARGET_ARM) | |
f16fe45f | 3954 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
d3585b76 DJ |
3955 | else |
3956 | { | |
f16fe45f | 3957 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
3958 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
3959 | } | |
3960 | ||
3961 | tp = arm_load_tp (NULL_RTX); | |
3962 | ||
3963 | return gen_rtx_PLUS (Pmode, tp, reg); | |
3964 | ||
3965 | case TLS_MODEL_LOCAL_EXEC: | |
3966 | tp = arm_load_tp (NULL_RTX); | |
3967 | ||
3968 | reg = gen_rtx_UNSPEC (Pmode, | |
3969 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
3970 | UNSPEC_TLS); | |
3971 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
3972 | ||
3973 | return gen_rtx_PLUS (Pmode, tp, reg); | |
3974 | ||
3975 | default: | |
3976 | abort (); | |
3977 | } | |
3978 | } | |
3979 | ||
ccf4d512 RE |
3980 | /* Try machine-dependent ways of modifying an illegitimate address |
3981 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 3982 | rtx |
e32bac5b | 3983 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 3984 | { |
d3585b76 DJ |
3985 | if (arm_tls_symbol_p (x)) |
3986 | return legitimize_tls_address (x, NULL_RTX); | |
3987 | ||
ccf4d512 RE |
3988 | if (GET_CODE (x) == PLUS) |
3989 | { | |
3990 | rtx xop0 = XEXP (x, 0); | |
3991 | rtx xop1 = XEXP (x, 1); | |
3992 | ||
3993 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
3994 | xop0 = force_reg (SImode, xop0); | |
3995 | ||
3996 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
3997 | xop1 = force_reg (SImode, xop1); | |
3998 | ||
3999 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
4000 | && GET_CODE (xop1) == CONST_INT) | |
4001 | { | |
4002 | HOST_WIDE_INT n, low_n; | |
4003 | rtx base_reg, val; | |
4004 | n = INTVAL (xop1); | |
4005 | ||
9b66ebb1 PB |
4006 | /* VFP addressing modes actually allow greater offsets, but for |
4007 | now we just stick with the lowest common denominator. */ | |
4008 | if (mode == DImode | |
4009 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
4010 | { |
4011 | low_n = n & 0x0f; | |
4012 | n &= ~0x0f; | |
4013 | if (low_n > 4) | |
4014 | { | |
4015 | n += 16; | |
4016 | low_n -= 16; | |
4017 | } | |
4018 | } | |
4019 | else | |
4020 | { | |
4021 | low_n = ((mode) == TImode ? 0 | |
4022 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
4023 | n -= low_n; | |
4024 | } | |
4025 | ||
4026 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 4027 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 4028 | emit_move_insn (base_reg, val); |
d66437c5 | 4029 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
4030 | } |
4031 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4032 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4033 | } | |
4034 | ||
4035 | /* XXX We don't allow MINUS any more -- see comment in | |
4036 | arm_legitimate_address_p (). */ | |
4037 | else if (GET_CODE (x) == MINUS) | |
4038 | { | |
4039 | rtx xop0 = XEXP (x, 0); | |
4040 | rtx xop1 = XEXP (x, 1); | |
4041 | ||
4042 | if (CONSTANT_P (xop0)) | |
4043 | xop0 = force_reg (SImode, xop0); | |
4044 | ||
4045 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
4046 | xop1 = force_reg (SImode, xop1); | |
4047 | ||
4048 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4049 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
4050 | } | |
4051 | ||
86805759 NP |
4052 | /* Make sure to take full advantage of the pre-indexed addressing mode |
4053 | with absolute addresses which often allows for the base register to | |
4054 | be factorized for multiple adjacent memory references, and it might | |
4055 | even allows for the mini pool to be avoided entirely. */ | |
4056 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
4057 | { | |
4058 | unsigned int bits; | |
4059 | HOST_WIDE_INT mask, base, index; | |
4060 | rtx base_reg; | |
4061 | ||
4062 | /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only | |
4063 | use a 8 bit index. So let's use a 12 bit index for SImode only and | |
4064 | hope that arm_gen_constant will enable ldrb to use more bits. */ | |
4065 | bits = (mode == SImode) ? 12 : 8; | |
4066 | mask = (1 << bits) - 1; | |
4067 | base = INTVAL (x) & ~mask; | |
4068 | index = INTVAL (x) & mask; | |
b107d743 | 4069 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
4070 | { |
4071 | /* It'll most probably be more efficient to generate the base | |
4072 | with more bits set and use a negative index instead. */ | |
4073 | base |= mask; | |
4074 | index -= mask; | |
4075 | } | |
4076 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 4077 | x = plus_constant (base_reg, index); |
86805759 NP |
4078 | } |
4079 | ||
ccf4d512 RE |
4080 | if (flag_pic) |
4081 | { | |
4082 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4083 | references; so go back to the original address expression. */ | |
4084 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4085 | ||
4086 | if (new_x != orig_x) | |
4087 | x = new_x; | |
4088 | } | |
4089 | ||
4090 | return x; | |
4091 | } | |
4092 | ||
6f5b4f3e RE |
4093 | |
4094 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
4095 | to be legitimate. If we find one, return the new, valid address. */ | |
4096 | rtx | |
4097 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
4098 | { | |
d3585b76 DJ |
4099 | if (arm_tls_symbol_p (x)) |
4100 | return legitimize_tls_address (x, NULL_RTX); | |
4101 | ||
6f5b4f3e RE |
4102 | if (GET_CODE (x) == PLUS |
4103 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4104 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
4105 | || INTVAL (XEXP (x, 1)) < 0)) | |
4106 | { | |
4107 | rtx xop0 = XEXP (x, 0); | |
4108 | rtx xop1 = XEXP (x, 1); | |
4109 | HOST_WIDE_INT offset = INTVAL (xop1); | |
4110 | ||
4111 | /* Try and fold the offset into a biasing of the base register and | |
4112 | then offsetting that. Don't do this when optimizing for space | |
4113 | since it can cause too many CSEs. */ | |
4114 | if (optimize_size && offset >= 0 | |
4115 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
4116 | { | |
4117 | HOST_WIDE_INT delta; | |
4118 | ||
4119 | if (offset >= 256) | |
4120 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
4121 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
4122 | delta = 31 * GET_MODE_SIZE (mode); | |
4123 | else | |
4124 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
4125 | ||
4126 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
4127 | NULL_RTX); | |
4128 | x = plus_constant (xop0, delta); | |
4129 | } | |
4130 | else if (offset < 0 && offset > -256) | |
4131 | /* Small negative offsets are best done with a subtract before the | |
4132 | dereference, forcing these into a register normally takes two | |
4133 | instructions. */ | |
4134 | x = force_operand (x, NULL_RTX); | |
4135 | else | |
4136 | { | |
4137 | /* For the remaining cases, force the constant into a register. */ | |
4138 | xop1 = force_reg (SImode, xop1); | |
4139 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4140 | } | |
4141 | } | |
4142 | else if (GET_CODE (x) == PLUS | |
4143 | && s_register_operand (XEXP (x, 1), SImode) | |
4144 | && !s_register_operand (XEXP (x, 0), SImode)) | |
4145 | { | |
4146 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
4147 | ||
4148 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
4149 | } | |
4150 | ||
4151 | if (flag_pic) | |
4152 | { | |
4153 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4154 | references; so go back to the original address expression. */ | |
4155 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4156 | ||
4157 | if (new_x != orig_x) | |
4158 | x = new_x; | |
4159 | } | |
4160 | ||
4161 | return x; | |
4162 | } | |
4163 | ||
a132dad6 | 4164 | rtx |
e0b92319 NC |
4165 | thumb_legitimize_reload_address (rtx *x_p, |
4166 | enum machine_mode mode, | |
4167 | int opnum, int type, | |
4168 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
4169 | { |
4170 | rtx x = *x_p; | |
e0b92319 | 4171 | |
a132dad6 RE |
4172 | if (GET_CODE (x) == PLUS |
4173 | && GET_MODE_SIZE (mode) < 4 | |
4174 | && REG_P (XEXP (x, 0)) | |
4175 | && XEXP (x, 0) == stack_pointer_rtx | |
4176 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4177 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4178 | { | |
4179 | rtx orig_x = x; | |
4180 | ||
4181 | x = copy_rtx (x); | |
4182 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4183 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4184 | return x; | |
4185 | } | |
4186 | ||
4187 | /* If both registers are hi-regs, then it's better to reload the | |
4188 | entire expression rather than each register individually. That | |
4189 | only requires one reload register rather than two. */ | |
4190 | if (GET_CODE (x) == PLUS | |
4191 | && REG_P (XEXP (x, 0)) | |
4192 | && REG_P (XEXP (x, 1)) | |
4193 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
4194 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
4195 | { | |
4196 | rtx orig_x = x; | |
4197 | ||
4198 | x = copy_rtx (x); | |
4199 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
4200 | Pmode, VOIDmode, 0, 0, opnum, type); | |
4201 | return x; | |
4202 | } | |
4203 | ||
4204 | return NULL; | |
4205 | } | |
d3585b76 DJ |
4206 | |
4207 | /* Test for various thread-local symbols. */ | |
4208 | ||
4209 | /* Return TRUE if X is a thread-local symbol. */ | |
4210 | ||
4211 | static bool | |
4212 | arm_tls_symbol_p (rtx x) | |
4213 | { | |
4214 | if (! TARGET_HAVE_TLS) | |
4215 | return false; | |
4216 | ||
4217 | if (GET_CODE (x) != SYMBOL_REF) | |
4218 | return false; | |
4219 | ||
4220 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
4221 | } | |
4222 | ||
4223 | /* Helper for arm_tls_referenced_p. */ | |
4224 | ||
4225 | static int | |
4226 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
4227 | { | |
4228 | if (GET_CODE (*x) == SYMBOL_REF) | |
4229 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
4230 | ||
4231 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
4232 | TLS offsets, not real symbol references. */ | |
4233 | if (GET_CODE (*x) == UNSPEC | |
4234 | && XINT (*x, 1) == UNSPEC_TLS) | |
4235 | return -1; | |
4236 | ||
4237 | return 0; | |
4238 | } | |
4239 | ||
4240 | /* Return TRUE if X contains any TLS symbol references. */ | |
4241 | ||
4242 | bool | |
4243 | arm_tls_referenced_p (rtx x) | |
4244 | { | |
4245 | if (! TARGET_HAVE_TLS) | |
4246 | return false; | |
4247 | ||
4248 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
4249 | } | |
6b990f6b | 4250 | \f |
e2c671ba RE |
4251 | #define REG_OR_SUBREG_REG(X) \ |
4252 | (GET_CODE (X) == REG \ | |
4253 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
4254 | ||
4255 | #define REG_OR_SUBREG_RTX(X) \ | |
4256 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
4257 | ||
d5b7b3ae RE |
4258 | #ifndef COSTS_N_INSNS |
4259 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
4260 | #endif | |
3c50106f | 4261 | static inline int |
9b66ebb1 | 4262 | thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
4263 | { |
4264 | enum machine_mode mode = GET_MODE (x); | |
e2c671ba | 4265 | |
9b66ebb1 | 4266 | switch (code) |
d5b7b3ae | 4267 | { |
9b66ebb1 PB |
4268 | case ASHIFT: |
4269 | case ASHIFTRT: | |
4270 | case LSHIFTRT: | |
f676971a | 4271 | case ROTATERT: |
9b66ebb1 PB |
4272 | case PLUS: |
4273 | case MINUS: | |
4274 | case COMPARE: | |
4275 | case NEG: | |
f676971a | 4276 | case NOT: |
9b66ebb1 | 4277 | return COSTS_N_INSNS (1); |
f676971a EC |
4278 | |
4279 | case MULT: | |
4280 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4281 | { | |
4282 | int cycles = 0; | |
9b66ebb1 | 4283 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
4284 | |
4285 | while (i) | |
4286 | { | |
4287 | i >>= 2; | |
4288 | cycles++; | |
4289 | } | |
4290 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
4291 | } |
4292 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
4293 | |
4294 | case SET: | |
4295 | return (COSTS_N_INSNS (1) | |
4296 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 4297 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
4298 | |
4299 | case CONST_INT: | |
4300 | if (outer == SET) | |
4301 | { | |
4302 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
4303 | return 0; | |
4304 | if (thumb_shiftable_const (INTVAL (x))) | |
4305 | return COSTS_N_INSNS (2); | |
4306 | return COSTS_N_INSNS (3); | |
4307 | } | |
9b66ebb1 | 4308 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 4309 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 PB |
4310 | return 0; |
4311 | else if (outer == AND | |
4312 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
4313 | return COSTS_N_INSNS (1); | |
f676971a EC |
4314 | else if (outer == ASHIFT || outer == ASHIFTRT |
4315 | || outer == LSHIFTRT) | |
4316 | return 0; | |
9b66ebb1 | 4317 | return COSTS_N_INSNS (2); |
f676971a EC |
4318 | |
4319 | case CONST: | |
4320 | case CONST_DOUBLE: | |
4321 | case LABEL_REF: | |
4322 | case SYMBOL_REF: | |
9b66ebb1 | 4323 | return COSTS_N_INSNS (3); |
f676971a | 4324 | |
9b66ebb1 PB |
4325 | case UDIV: |
4326 | case UMOD: | |
4327 | case DIV: | |
4328 | case MOD: | |
4329 | return 100; | |
d5b7b3ae | 4330 | |
9b66ebb1 PB |
4331 | case TRUNCATE: |
4332 | return 99; | |
d5b7b3ae | 4333 | |
9b66ebb1 PB |
4334 | case AND: |
4335 | case XOR: | |
f676971a | 4336 | case IOR: |
ff482c8d | 4337 | /* XXX guess. */ |
9b66ebb1 | 4338 | return 8; |
d5b7b3ae | 4339 | |
9b66ebb1 PB |
4340 | case MEM: |
4341 | /* XXX another guess. */ | |
4342 | /* Memory costs quite a lot for the first word, but subsequent words | |
4343 | load at the equivalent of a single insn each. */ | |
4344 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
4345 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
4346 | ? 4 : 0)); | |
4347 | ||
4348 | case IF_THEN_ELSE: | |
ff482c8d | 4349 | /* XXX a guess. */ |
9b66ebb1 PB |
4350 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
4351 | return 14; | |
4352 | return 2; | |
4353 | ||
4354 | case ZERO_EXTEND: | |
4355 | /* XXX still guessing. */ | |
4356 | switch (GET_MODE (XEXP (x, 0))) | |
4357 | { | |
4358 | case QImode: | |
4359 | return (1 + (mode == DImode ? 4 : 0) | |
4360 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4361 | |
9b66ebb1 PB |
4362 | case HImode: |
4363 | return (4 + (mode == DImode ? 4 : 0) | |
4364 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4365 | |
9b66ebb1 PB |
4366 | case SImode: |
4367 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 4368 | |
d5b7b3ae RE |
4369 | default: |
4370 | return 99; | |
d5b7b3ae | 4371 | } |
f676971a | 4372 | |
9b66ebb1 PB |
4373 | default: |
4374 | return 99; | |
d5b7b3ae | 4375 | } |
9b66ebb1 PB |
4376 | } |
4377 | ||
4378 | ||
4379 | /* Worker routine for arm_rtx_costs. */ | |
4380 | static inline int | |
4381 | arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) | |
4382 | { | |
4383 | enum machine_mode mode = GET_MODE (x); | |
4384 | enum rtx_code subcode; | |
4385 | int extra_cost; | |
4386 | ||
e2c671ba RE |
4387 | switch (code) |
4388 | { | |
4389 | case MEM: | |
4390 | /* Memory costs quite a lot for the first word, but subsequent words | |
4391 | load at the equivalent of a single insn each. */ | |
4392 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
4393 | + (GET_CODE (x) == SYMBOL_REF |
4394 | && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
e2c671ba RE |
4395 | |
4396 | case DIV: | |
4397 | case MOD: | |
b9c53150 RS |
4398 | case UDIV: |
4399 | case UMOD: | |
4400 | return optimize_size ? COSTS_N_INSNS (2) : 100; | |
e2c671ba RE |
4401 | |
4402 | case ROTATE: | |
4403 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
4404 | return 4; | |
4405 | /* Fall through */ | |
4406 | case ROTATERT: | |
4407 | if (mode != SImode) | |
4408 | return 8; | |
4409 | /* Fall through */ | |
4410 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
4411 | if (mode == DImode) | |
4412 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
f676971a | 4413 | + ((GET_CODE (XEXP (x, 0)) == REG |
e2c671ba RE |
4414 | || (GET_CODE (XEXP (x, 0)) == SUBREG |
4415 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
4416 | ? 0 : 8)); | |
4417 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
4418 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
4419 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
4420 | ? 0 : 4) | |
4421 | + ((GET_CODE (XEXP (x, 1)) == REG | |
4422 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
4423 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
4424 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
4425 | ? 0 : 4)); | |
4426 | ||
4427 | case MINUS: | |
4428 | if (mode == DImode) | |
4429 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
4430 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4431 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
4432 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
4433 | ? 0 : 8)); | |
4434 | ||
4435 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4436 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4437 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 4438 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
4439 | ? 0 : 8) |
4440 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4441 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
9b66ebb1 | 4442 | && arm_const_double_rtx (XEXP (x, 0)))) |
e2c671ba RE |
4443 | ? 0 : 8)); |
4444 | ||
4445 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
4446 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
4447 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
4448 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
4449 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
4450 | || subcode == ROTATE || subcode == ROTATERT | |
4451 | || (subcode == MULT | |
4452 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
4453 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
4454 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
4455 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
4456 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
4457 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
4458 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
4459 | return 1; | |
4460 | /* Fall through */ | |
4461 | ||
f676971a | 4462 | case PLUS: |
e2c671ba RE |
4463 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
4464 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
4465 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4466 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 4467 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
4468 | ? 0 : 8)); |
4469 | ||
4470 | /* Fall through */ | |
f676971a | 4471 | case AND: case XOR: case IOR: |
e2c671ba RE |
4472 | extra_cost = 0; |
4473 | ||
4474 | /* Normally the frame registers will be spilt into reg+const during | |
4475 | reload, so it is a bad idea to combine them with other instructions, | |
4476 | since then they might not be moved outside of loops. As a compromise | |
4477 | we allow integration with ops that have a constant as their second | |
4478 | operand. */ | |
4479 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4480 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
4481 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
4482 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
4483 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
4484 | extra_cost = 4; | |
4485 | ||
4486 | if (mode == DImode) | |
4487 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
4488 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4489 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 4490 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
4491 | ? 0 : 8)); |
4492 | ||
4493 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
4494 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
4495 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
4496 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 4497 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
4498 | ? 0 : 4)); |
4499 | ||
4500 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
4501 | return (1 + extra_cost | |
4502 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
4503 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
4504 | || subcode == ROTATE || subcode == ROTATERT | |
4505 | || (subcode == MULT | |
4506 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4507 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 4508 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
4509 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
4510 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 4511 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
4512 | ? 0 : 4)); |
4513 | ||
4514 | return 8; | |
4515 | ||
4516 | case MULT: | |
9b66ebb1 | 4517 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 4518 | gcc_unreachable (); |
e2c671ba | 4519 | |
56636818 | 4520 | case TRUNCATE: |
9b66ebb1 | 4521 | if (arm_arch3m && mode == SImode |
56636818 JL |
4522 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
4523 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
4524 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
4525 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
4526 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
4527 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
4528 | return 8; | |
4529 | return 99; | |
4530 | ||
e2c671ba RE |
4531 | case NEG: |
4532 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4533 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
4534 | /* Fall through */ | |
4535 | case NOT: | |
4536 | if (mode == DImode) | |
4537 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
4538 | ||
4539 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
4540 | ||
4541 | case IF_THEN_ELSE: | |
4542 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
4543 | return 14; | |
4544 | return 2; | |
4545 | ||
4546 | case COMPARE: | |
4547 | return 1; | |
4548 | ||
4549 | case ABS: | |
4550 | return 4 + (mode == DImode ? 4 : 0); | |
4551 | ||
4552 | case SIGN_EXTEND: | |
4553 | if (GET_MODE (XEXP (x, 0)) == QImode) | |
4554 | return (4 + (mode == DImode ? 4 : 0) | |
4555 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
4556 | /* Fall through */ | |
4557 | case ZERO_EXTEND: | |
4558 | switch (GET_MODE (XEXP (x, 0))) | |
4559 | { | |
4560 | case QImode: | |
4561 | return (1 + (mode == DImode ? 4 : 0) | |
4562 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
4563 | ||
4564 | case HImode: | |
4565 | return (4 + (mode == DImode ? 4 : 0) | |
4566 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
4567 | ||
4568 | case SImode: | |
4569 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e | 4570 | |
5a9335ef NC |
4571 | case V8QImode: |
4572 | case V4HImode: | |
4573 | case V2SImode: | |
4574 | case V4QImode: | |
4575 | case V2HImode: | |
4576 | return 1; | |
4577 | ||
ad076f4e | 4578 | default: |
e6d29d15 | 4579 | gcc_unreachable (); |
e2c671ba | 4580 | } |
e6d29d15 | 4581 | gcc_unreachable (); |
e2c671ba | 4582 | |
f676971a EC |
4583 | case CONST_INT: |
4584 | if (const_ok_for_arm (INTVAL (x))) | |
4585 | return outer == SET ? 2 : -1; | |
4586 | else if (outer == AND | |
4587 | && const_ok_for_arm (~INTVAL (x))) | |
4588 | return -1; | |
4589 | else if ((outer == COMPARE | |
4590 | || outer == PLUS || outer == MINUS) | |
4591 | && const_ok_for_arm (-INTVAL (x))) | |
4592 | return -1; | |
4593 | else | |
d5b7b3ae | 4594 | return 5; |
f676971a EC |
4595 | |
4596 | case CONST: | |
4597 | case LABEL_REF: | |
4598 | case SYMBOL_REF: | |
d5b7b3ae | 4599 | return 6; |
f676971a EC |
4600 | |
4601 | case CONST_DOUBLE: | |
9b66ebb1 | 4602 | if (arm_const_double_rtx (x)) |
f676971a EC |
4603 | return outer == SET ? 2 : -1; |
4604 | else if ((outer == COMPARE || outer == PLUS) | |
4605 | && neg_const_double_rtx_ok_for_fpa (x)) | |
4606 | return -1; | |
d5b7b3ae | 4607 | return 7; |
f676971a | 4608 | |
e2c671ba RE |
4609 | default: |
4610 | return 99; | |
4611 | } | |
4612 | } | |
32de079a | 4613 | |
21b5653c RE |
4614 | /* RTX costs when optimizing for size. */ |
4615 | static bool | |
4616 | arm_size_rtx_costs (rtx x, int code, int outer_code, int *total) | |
4617 | { | |
4618 | enum machine_mode mode = GET_MODE (x); | |
4619 | ||
4620 | if (TARGET_THUMB) | |
4621 | { | |
4622 | /* XXX TBD. For now, use the standard costs. */ | |
4623 | *total = thumb_rtx_costs (x, code, outer_code); | |
4624 | return true; | |
4625 | } | |
4626 | ||
4627 | switch (code) | |
4628 | { | |
4629 | case MEM: | |
f676971a | 4630 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
4631 | a single register, otherwise it costs one insn per word. */ |
4632 | if (REG_P (XEXP (x, 0))) | |
4633 | *total = COSTS_N_INSNS (1); | |
4634 | else | |
4635 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4636 | return true; | |
4637 | ||
4638 | case DIV: | |
4639 | case MOD: | |
4640 | case UDIV: | |
4641 | case UMOD: | |
4642 | /* Needs a libcall, so it costs about this. */ | |
4643 | *total = COSTS_N_INSNS (2); | |
4644 | return false; | |
4645 | ||
4646 | case ROTATE: | |
4647 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
4648 | { | |
4649 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code); | |
4650 | return true; | |
4651 | } | |
4652 | /* Fall through */ | |
4653 | case ROTATERT: | |
4654 | case ASHIFT: | |
4655 | case LSHIFTRT: | |
4656 | case ASHIFTRT: | |
4657 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4658 | { | |
4659 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code); | |
4660 | return true; | |
4661 | } | |
4662 | else if (mode == SImode) | |
4663 | { | |
4664 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code); | |
4665 | /* Slightly disparage register shifts, but not by much. */ | |
4666 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
4667 | *total += 1 + rtx_cost (XEXP (x, 1), code); | |
4668 | return true; | |
4669 | } | |
4670 | ||
4671 | /* Needs a libcall. */ | |
4672 | *total = COSTS_N_INSNS (2); | |
4673 | return false; | |
4674 | ||
4675 | case MINUS: | |
4676 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4677 | { | |
4678 | *total = COSTS_N_INSNS (1); | |
4679 | return false; | |
4680 | } | |
4681 | ||
4682 | if (mode == SImode) | |
4683 | { | |
4684 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
4685 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
4686 | ||
4687 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
4688 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
4689 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
4690 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
4691 | || subcode1 == ASHIFTRT) | |
4692 | { | |
4693 | /* It's just the cost of the two operands. */ | |
4694 | *total = 0; | |
4695 | return false; | |
4696 | } | |
4697 | ||
4698 | *total = COSTS_N_INSNS (1); | |
4699 | return false; | |
4700 | } | |
4701 | ||
4702 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4703 | return false; | |
4704 | ||
f676971a | 4705 | case PLUS: |
21b5653c RE |
4706 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
4707 | { | |
4708 | *total = COSTS_N_INSNS (1); | |
4709 | return false; | |
4710 | } | |
4711 | ||
4712 | /* Fall through */ | |
4713 | case AND: case XOR: case IOR: | |
4714 | if (mode == SImode) | |
4715 | { | |
4716 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
4717 | ||
4718 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
4719 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
4720 | || (code == AND && subcode == NOT)) | |
4721 | { | |
4722 | /* It's just the cost of the two operands. */ | |
4723 | *total = 0; | |
4724 | return false; | |
4725 | } | |
4726 | } | |
4727 | ||
4728 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4729 | return false; | |
4730 | ||
4731 | case MULT: | |
4732 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4733 | return false; | |
4734 | ||
4735 | case NEG: | |
4736 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4737 | *total = COSTS_N_INSNS (1); | |
4738 | /* Fall through */ | |
4739 | case NOT: | |
4740 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4741 | ||
4742 | return false; | |
4743 | ||
4744 | case IF_THEN_ELSE: | |
4745 | *total = 0; | |
4746 | return false; | |
4747 | ||
4748 | case COMPARE: | |
4749 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
4750 | * total = 0; | |
4751 | else | |
4752 | *total = COSTS_N_INSNS (1); | |
4753 | return false; | |
4754 | ||
4755 | case ABS: | |
4756 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4757 | *total = COSTS_N_INSNS (1); | |
4758 | else | |
4759 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
4760 | return false; | |
4761 | ||
4762 | case SIGN_EXTEND: | |
4763 | *total = 0; | |
4764 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) | |
4765 | { | |
4766 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
4767 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
4768 | } | |
4769 | if (mode == DImode) | |
4770 | *total += COSTS_N_INSNS (1); | |
4771 | return false; | |
4772 | ||
4773 | case ZERO_EXTEND: | |
4774 | *total = 0; | |
4775 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
4776 | { | |
4777 | switch (GET_MODE (XEXP (x, 0))) | |
4778 | { | |
4779 | case QImode: | |
4780 | *total += COSTS_N_INSNS (1); | |
4781 | break; | |
4782 | ||
4783 | case HImode: | |
4784 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
f676971a | 4785 | |
21b5653c RE |
4786 | case SImode: |
4787 | break; | |
4788 | ||
4789 | default: | |
4790 | *total += COSTS_N_INSNS (2); | |
4791 | } | |
4792 | } | |
4793 | ||
4794 | if (mode == DImode) | |
4795 | *total += COSTS_N_INSNS (1); | |
4796 | ||
4797 | return false; | |
4798 | ||
f676971a EC |
4799 | case CONST_INT: |
4800 | if (const_ok_for_arm (INTVAL (x))) | |
21b5653c RE |
4801 | *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0); |
4802 | else if (const_ok_for_arm (~INTVAL (x))) | |
4803 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
4804 | else if (const_ok_for_arm (-INTVAL (x))) | |
4805 | { | |
4806 | if (outer_code == COMPARE || outer_code == PLUS | |
4807 | || outer_code == MINUS) | |
4808 | *total = 0; | |
4809 | else | |
4810 | *total = COSTS_N_INSNS (1); | |
4811 | } | |
4812 | else | |
4813 | *total = COSTS_N_INSNS (2); | |
4814 | return true; | |
f676971a EC |
4815 | |
4816 | case CONST: | |
4817 | case LABEL_REF: | |
4818 | case SYMBOL_REF: | |
21b5653c RE |
4819 | *total = COSTS_N_INSNS (2); |
4820 | return true; | |
f676971a | 4821 | |
21b5653c RE |
4822 | case CONST_DOUBLE: |
4823 | *total = COSTS_N_INSNS (4); | |
4824 | return true; | |
4825 | ||
4826 | default: | |
4827 | if (mode != VOIDmode) | |
4828 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
4829 | else | |
4830 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
4831 | return false; | |
4832 | } | |
4833 | } | |
4834 | ||
59b9a953 | 4835 | /* RTX costs for cores with a slow MUL implementation. */ |
9b66ebb1 | 4836 | |
3c50106f | 4837 | static bool |
9b66ebb1 | 4838 | arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 4839 | { |
9b66ebb1 PB |
4840 | enum machine_mode mode = GET_MODE (x); |
4841 | ||
4842 | if (TARGET_THUMB) | |
4843 | { | |
4844 | *total = thumb_rtx_costs (x, code, outer_code); | |
4845 | return true; | |
4846 | } | |
f676971a | 4847 | |
9b66ebb1 PB |
4848 | switch (code) |
4849 | { | |
4850 | case MULT: | |
4851 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4852 | || mode == DImode) | |
4853 | { | |
4854 | *total = 30; | |
4855 | return true; | |
4856 | } | |
4857 | ||
4858 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4859 | { | |
4860 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
4861 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
4862 | int cost, const_ok = const_ok_for_arm (i); | |
4863 | int j, booth_unit_size; | |
4864 | ||
f676971a | 4865 | /* Tune as appropriate. */ |
9b66ebb1 PB |
4866 | cost = const_ok ? 4 : 8; |
4867 | booth_unit_size = 2; | |
4868 | for (j = 0; i && j < 32; j += booth_unit_size) | |
4869 | { | |
4870 | i >>= booth_unit_size; | |
4871 | cost += 2; | |
4872 | } | |
4873 | ||
4874 | *total = cost; | |
4875 | return true; | |
4876 | } | |
4877 | ||
4878 | *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
4879 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
4880 | return true; | |
f676971a | 4881 | |
9b66ebb1 PB |
4882 | default: |
4883 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
4884 | return true; | |
4885 | } | |
3c50106f RH |
4886 | } |
4887 | ||
9b66ebb1 PB |
4888 | |
4889 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
4890 | ||
4891 | static bool | |
4892 | arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total) | |
4893 | { | |
4894 | enum machine_mode mode = GET_MODE (x); | |
4895 | ||
4896 | if (TARGET_THUMB) | |
4897 | { | |
4898 | *total = thumb_rtx_costs (x, code, outer_code); | |
4899 | return true; | |
4900 | } | |
f676971a | 4901 | |
9b66ebb1 PB |
4902 | switch (code) |
4903 | { | |
4904 | case MULT: | |
4905 | /* There is no point basing this on the tuning, since it is always the | |
4906 | fast variant if it exists at all. */ | |
4907 | if (mode == DImode | |
4908 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
4909 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
4910 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
4911 | { | |
4912 | *total = 8; | |
4913 | return true; | |
4914 | } | |
f676971a | 4915 | |
9b66ebb1 PB |
4916 | |
4917 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4918 | || mode == DImode) | |
4919 | { | |
4920 | *total = 30; | |
4921 | return true; | |
4922 | } | |
4923 | ||
4924 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4925 | { | |
4926 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
4927 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
4928 | int cost, const_ok = const_ok_for_arm (i); | |
4929 | int j, booth_unit_size; | |
4930 | ||
f676971a | 4931 | /* Tune as appropriate. */ |
9b66ebb1 PB |
4932 | cost = const_ok ? 4 : 8; |
4933 | booth_unit_size = 8; | |
4934 | for (j = 0; i && j < 32; j += booth_unit_size) | |
4935 | { | |
4936 | i >>= booth_unit_size; | |
4937 | cost += 2; | |
4938 | } | |
4939 | ||
4940 | *total = cost; | |
4941 | return true; | |
4942 | } | |
4943 | ||
4944 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
4945 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
4946 | return true; | |
f676971a | 4947 | |
9b66ebb1 PB |
4948 | default: |
4949 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
4950 | return true; | |
4951 | } | |
4952 | } | |
4953 | ||
4954 | ||
4955 | /* RTX cost for XScale CPUs. */ | |
4956 | ||
4957 | static bool | |
4958 | arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total) | |
4959 | { | |
4960 | enum machine_mode mode = GET_MODE (x); | |
4961 | ||
4962 | if (TARGET_THUMB) | |
4963 | { | |
4964 | *total = thumb_rtx_costs (x, code, outer_code); | |
4965 | return true; | |
4966 | } | |
f676971a | 4967 | |
9b66ebb1 PB |
4968 | switch (code) |
4969 | { | |
4970 | case MULT: | |
4971 | /* There is no point basing this on the tuning, since it is always the | |
4972 | fast variant if it exists at all. */ | |
4973 | if (mode == DImode | |
4974 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
4975 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
4976 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
4977 | { | |
4978 | *total = 8; | |
4979 | return true; | |
4980 | } | |
f676971a | 4981 | |
9b66ebb1 PB |
4982 | |
4983 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4984 | || mode == DImode) | |
4985 | { | |
4986 | *total = 30; | |
4987 | return true; | |
4988 | } | |
4989 | ||
4990 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4991 | { | |
4992 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
4993 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
4994 | int cost, const_ok = const_ok_for_arm (i); | |
4995 | unsigned HOST_WIDE_INT masked_const; | |
4996 | ||
4997 | /* The cost will be related to two insns. | |
ff482c8d | 4998 | First a load of the constant (MOV or LDR), then a multiply. */ |
9b66ebb1 PB |
4999 | cost = 2; |
5000 | if (! const_ok) | |
5001 | cost += 1; /* LDR is probably more expensive because | |
ff482c8d | 5002 | of longer result latency. */ |
9b66ebb1 PB |
5003 | masked_const = i & 0xffff8000; |
5004 | if (masked_const != 0 && masked_const != 0xffff8000) | |
5005 | { | |
5006 | masked_const = i & 0xf8000000; | |
5007 | if (masked_const == 0 || masked_const == 0xf8000000) | |
5008 | cost += 1; | |
5009 | else | |
5010 | cost += 2; | |
5011 | } | |
5012 | *total = cost; | |
5013 | return true; | |
5014 | } | |
5015 | ||
5016 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
5017 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
5018 | return true; | |
f676971a | 5019 | |
06d5588c ILT |
5020 | case COMPARE: |
5021 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
5022 | will stall until the multiplication is complete. */ | |
5023 | if (GET_CODE (XEXP (x, 0)) == MULT) | |
5024 | *total = 4 + rtx_cost (XEXP (x, 0), code); | |
5025 | else | |
5026 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5027 | return true; | |
5028 | ||
9b66ebb1 PB |
5029 | default: |
5030 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5031 | return true; | |
5032 | } | |
5033 | } | |
5034 | ||
5035 | ||
5036 | /* RTX costs for 9e (and later) cores. */ | |
5037 | ||
5038 | static bool | |
5039 | arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total) | |
5040 | { | |
5041 | enum machine_mode mode = GET_MODE (x); | |
5042 | int nonreg_cost; | |
5043 | int cost; | |
f676971a | 5044 | |
9b66ebb1 PB |
5045 | if (TARGET_THUMB) |
5046 | { | |
5047 | switch (code) | |
5048 | { | |
5049 | case MULT: | |
5050 | *total = COSTS_N_INSNS (3); | |
5051 | return true; | |
f676971a | 5052 | |
9b66ebb1 PB |
5053 | default: |
5054 | *total = thumb_rtx_costs (x, code, outer_code); | |
5055 | return true; | |
5056 | } | |
5057 | } | |
f676971a | 5058 | |
9b66ebb1 PB |
5059 | switch (code) |
5060 | { | |
5061 | case MULT: | |
5062 | /* There is no point basing this on the tuning, since it is always the | |
5063 | fast variant if it exists at all. */ | |
5064 | if (mode == DImode | |
5065 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
5066 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
5067 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
5068 | { | |
5069 | *total = 3; | |
5070 | return true; | |
5071 | } | |
f676971a | 5072 | |
9b66ebb1 PB |
5073 | |
5074 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5075 | { | |
5076 | *total = 30; | |
5077 | return true; | |
5078 | } | |
5079 | if (mode == DImode) | |
5080 | { | |
5081 | cost = 7; | |
5082 | nonreg_cost = 8; | |
5083 | } | |
5084 | else | |
5085 | { | |
5086 | cost = 2; | |
5087 | nonreg_cost = 4; | |
5088 | } | |
5089 | ||
5090 | ||
5091 | *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost) | |
5092 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost); | |
5093 | return true; | |
f676971a | 5094 | |
9b66ebb1 PB |
5095 | default: |
5096 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
5097 | return true; | |
5098 | } | |
5099 | } | |
dcefdf67 RH |
5100 | /* All address computations that can be done are free, but rtx cost returns |
5101 | the same for practically all of them. So we weight the different types | |
5102 | of address here in the order (most pref first): | |
d6b4baa4 | 5103 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
5104 | static inline int |
5105 | arm_arm_address_cost (rtx x) | |
5106 | { | |
5107 | enum rtx_code c = GET_CODE (x); | |
5108 | ||
5109 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
5110 | return 0; | |
5111 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
5112 | return 10; | |
5113 | ||
5114 | if (c == PLUS || c == MINUS) | |
5115 | { | |
d2b6eb76 ZW |
5116 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
5117 | return 2; | |
5118 | ||
ec8e098d | 5119 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
5120 | return 3; |
5121 | ||
5122 | return 4; | |
5123 | } | |
5124 | ||
5125 | return 6; | |
5126 | } | |
5127 | ||
5128 | static inline int | |
5129 | arm_thumb_address_cost (rtx x) | |
5130 | { | |
5131 | enum rtx_code c = GET_CODE (x); | |
5132 | ||
5133 | if (c == REG) | |
5134 | return 1; | |
5135 | if (c == PLUS | |
5136 | && GET_CODE (XEXP (x, 0)) == REG | |
5137 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5138 | return 1; | |
5139 | ||
5140 | return 2; | |
5141 | } | |
5142 | ||
dcefdf67 | 5143 | static int |
e32bac5b | 5144 | arm_address_cost (rtx x) |
dcefdf67 | 5145 | { |
d2b6eb76 | 5146 | return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 RH |
5147 | } |
5148 | ||
c237e94a | 5149 | static int |
e32bac5b | 5150 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
5151 | { |
5152 | rtx i_pat, d_pat; | |
5153 | ||
d19fb8e3 NC |
5154 | /* Some true dependencies can have a higher cost depending |
5155 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 5156 | if (arm_tune_xscale |
d19fb8e3 | 5157 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
5158 | && recog_memoized (insn) >= 0 |
5159 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
5160 | { |
5161 | int shift_opnum = get_attr_shift (insn); | |
5162 | enum attr_type attr_type = get_attr_type (dep); | |
5163 | ||
5164 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
5165 | operand for INSN. If we have a shifted input operand and the | |
5166 | instruction we depend on is another ALU instruction, then we may | |
5167 | have to account for an additional stall. */ | |
9b66ebb1 PB |
5168 | if (shift_opnum != 0 |
5169 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
5170 | { |
5171 | rtx shifted_operand; | |
5172 | int opno; | |
f676971a | 5173 | |
d19fb8e3 NC |
5174 | /* Get the shifted operand. */ |
5175 | extract_insn (insn); | |
5176 | shifted_operand = recog_data.operand[shift_opnum]; | |
5177 | ||
5178 | /* Iterate over all the operands in DEP. If we write an operand | |
5179 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
5180 | cost of this dependency. */ | |
5181 | extract_insn (dep); | |
5182 | preprocess_constraints (); | |
5183 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
5184 | { | |
5185 | /* We can ignore strict inputs. */ | |
5186 | if (recog_data.operand_type[opno] == OP_IN) | |
5187 | continue; | |
5188 | ||
5189 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
5190 | shifted_operand)) | |
5191 | return 2; | |
5192 | } | |
5193 | } | |
5194 | } | |
5195 | ||
6354dc9b | 5196 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
5197 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
5198 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
5199 | return 0; |
5200 | ||
d5b7b3ae RE |
5201 | /* Call insns don't incur a stall, even if they follow a load. */ |
5202 | if (REG_NOTE_KIND (link) == 0 | |
5203 | && GET_CODE (insn) == CALL_INSN) | |
5204 | return 1; | |
5205 | ||
32de079a RE |
5206 | if ((i_pat = single_set (insn)) != NULL |
5207 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
5208 | && (d_pat = single_set (dep)) != NULL | |
5209 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
5210 | { | |
48f6efae | 5211 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
5212 | /* This is a load after a store, there is no conflict if the load reads |
5213 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 5214 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 5215 | hack. */ |
f676971a | 5216 | |
48f6efae NC |
5217 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
5218 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
5219 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
5220 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 5221 | return 1; |
32de079a RE |
5222 | } |
5223 | ||
5224 | return cost; | |
5225 | } | |
5226 | ||
9b66ebb1 | 5227 | static int fp_consts_inited = 0; |
ff9940b0 | 5228 | |
9b66ebb1 PB |
5229 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
5230 | static const char * const strings_fp[8] = | |
62b10bbc | 5231 | { |
2b835d68 RE |
5232 | "0", "1", "2", "3", |
5233 | "4", "5", "0.5", "10" | |
5234 | }; | |
ff9940b0 | 5235 | |
9b66ebb1 | 5236 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
5237 | |
5238 | static void | |
9b66ebb1 | 5239 | init_fp_table (void) |
ff9940b0 RE |
5240 | { |
5241 | int i; | |
5242 | REAL_VALUE_TYPE r; | |
5243 | ||
9b66ebb1 PB |
5244 | if (TARGET_VFP) |
5245 | fp_consts_inited = 1; | |
5246 | else | |
5247 | fp_consts_inited = 8; | |
5248 | ||
5249 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 5250 | { |
9b66ebb1 PB |
5251 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
5252 | values_fp[i] = r; | |
ff9940b0 | 5253 | } |
ff9940b0 RE |
5254 | } |
5255 | ||
9b66ebb1 | 5256 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 5257 | int |
9b66ebb1 | 5258 | arm_const_double_rtx (rtx x) |
cce8749e | 5259 | { |
ff9940b0 RE |
5260 | REAL_VALUE_TYPE r; |
5261 | int i; | |
f676971a | 5262 | |
9b66ebb1 PB |
5263 | if (!fp_consts_inited) |
5264 | init_fp_table (); | |
f676971a | 5265 | |
ff9940b0 RE |
5266 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
5267 | if (REAL_VALUE_MINUS_ZERO (r)) | |
5268 | return 0; | |
f3bb6135 | 5269 | |
9b66ebb1 PB |
5270 | for (i = 0; i < fp_consts_inited; i++) |
5271 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 5272 | return 1; |
f3bb6135 | 5273 | |
ff9940b0 | 5274 | return 0; |
f3bb6135 | 5275 | } |
ff9940b0 | 5276 | |
3b684012 | 5277 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 5278 | int |
e32bac5b | 5279 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
5280 | { |
5281 | REAL_VALUE_TYPE r; | |
5282 | int i; | |
f676971a | 5283 | |
9b66ebb1 PB |
5284 | if (!fp_consts_inited) |
5285 | init_fp_table (); | |
f676971a | 5286 | |
ff9940b0 RE |
5287 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
5288 | r = REAL_VALUE_NEGATE (r); | |
5289 | if (REAL_VALUE_MINUS_ZERO (r)) | |
5290 | return 0; | |
f3bb6135 | 5291 | |
ff9940b0 | 5292 | for (i = 0; i < 8; i++) |
9b66ebb1 | 5293 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 5294 | return 1; |
f3bb6135 | 5295 | |
ff9940b0 | 5296 | return 0; |
f3bb6135 | 5297 | } |
cce8749e CH |
5298 | \f |
5299 | /* Predicates for `match_operand' and `match_operator'. */ | |
5300 | ||
9b6b54e2 | 5301 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 5302 | int |
e32bac5b | 5303 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
5304 | { |
5305 | /* Reject eliminable registers. */ | |
5306 | if (! (reload_in_progress || reload_completed) | |
5307 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
5308 | || reg_mentioned_p (arg_pointer_rtx, op) | |
5309 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
5310 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
5311 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
5312 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
5313 | return 0; | |
5314 | ||
5315 | if (GET_CODE (op) == MEM) | |
5316 | { | |
5317 | rtx ind; | |
5318 | ||
5319 | ind = XEXP (op, 0); | |
5320 | ||
5321 | /* Match: (mem (reg)). */ | |
5322 | if (GET_CODE (ind) == REG) | |
5323 | return 1; | |
5324 | ||
5325 | /* Match: | |
5326 | (mem (plus (reg) | |
5327 | (const))). */ | |
5328 | if (GET_CODE (ind) == PLUS | |
5329 | && GET_CODE (XEXP (ind, 0)) == REG | |
5330 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
5331 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
5332 | return 1; | |
5333 | } | |
5334 | ||
5335 | return 0; | |
5336 | } | |
5337 | ||
f26b8ec9 | 5338 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
fdd695fd | 5339 | WB if true if writeback address modes are allowed. */ |
9b66ebb1 PB |
5340 | |
5341 | int | |
fdd695fd | 5342 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 5343 | { |
fdd695fd | 5344 | rtx ind; |
9b66ebb1 | 5345 | |
fdd695fd | 5346 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
5347 | if (! (reload_in_progress || reload_completed) |
5348 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
5349 | || reg_mentioned_p (arg_pointer_rtx, op) | |
5350 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
5351 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
5352 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
5353 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
5354 | return FALSE; | |
5355 | ||
59b9a953 | 5356 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
5357 | if (GET_CODE (op) != MEM) |
5358 | return FALSE; | |
9b66ebb1 | 5359 | |
fdd695fd | 5360 | ind = XEXP (op, 0); |
9b66ebb1 | 5361 | |
fdd695fd PB |
5362 | if (reload_completed |
5363 | && (GET_CODE (ind) == LABEL_REF | |
5364 | || (GET_CODE (ind) == CONST | |
5365 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
5366 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
5367 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
5368 | return TRUE; | |
9b66ebb1 | 5369 | |
fdd695fd PB |
5370 | /* Match: (mem (reg)). */ |
5371 | if (GET_CODE (ind) == REG) | |
5372 | return arm_address_register_rtx_p (ind, 0); | |
5373 | ||
5374 | /* Autoincremment addressing modes. */ | |
5375 | if (wb | |
5376 | && (GET_CODE (ind) == PRE_INC | |
5377 | || GET_CODE (ind) == POST_INC | |
5378 | || GET_CODE (ind) == PRE_DEC | |
5379 | || GET_CODE (ind) == POST_DEC)) | |
5380 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); | |
5381 | ||
5382 | if (wb | |
5383 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
5384 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
5385 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
5386 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
5387 | ind = XEXP (ind, 1); | |
5388 | ||
5389 | /* Match: | |
5390 | (plus (reg) | |
5391 | (const)). */ | |
5392 | if (GET_CODE (ind) == PLUS | |
5393 | && GET_CODE (XEXP (ind, 0)) == REG | |
5394 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
5395 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
5396 | && INTVAL (XEXP (ind, 1)) > -1024 | |
5397 | && INTVAL (XEXP (ind, 1)) < 1024 | |
5398 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
5399 | return TRUE; | |
9b66ebb1 PB |
5400 | |
5401 | return FALSE; | |
5402 | } | |
5403 | ||
6555b6bd RE |
5404 | /* Return true if X is a register that will be eliminated later on. */ |
5405 | int | |
5406 | arm_eliminable_register (rtx x) | |
5407 | { | |
5408 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
5409 | || REGNO (x) == ARG_POINTER_REGNUM | |
5410 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
5411 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
5412 | } | |
9b66ebb1 | 5413 | |
9b66ebb1 PB |
5414 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
5415 | VFP registers. Otherwise return NO_REGS. */ | |
5416 | ||
5417 | enum reg_class | |
5418 | vfp_secondary_reload_class (enum machine_mode mode, rtx x) | |
5419 | { | |
fdd695fd | 5420 | if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode)) |
9b66ebb1 PB |
5421 | return NO_REGS; |
5422 | ||
5423 | return GENERAL_REGS; | |
5424 | } | |
5425 | ||
866af8a9 JB |
5426 | /* Values which must be returned in the most-significant end of the return |
5427 | register. */ | |
5428 | ||
5429 | static bool | |
5430 | arm_return_in_msb (tree valtype) | |
5431 | { | |
5432 | return (TARGET_AAPCS_BASED | |
5433 | && BYTES_BIG_ENDIAN | |
5434 | && (AGGREGATE_TYPE_P (valtype) | |
5435 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
5436 | } | |
9b66ebb1 | 5437 | |
f0375c66 NC |
5438 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
5439 | Use by the Cirrus Maverick code which has to workaround | |
5440 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 5441 | static bool |
e32bac5b | 5442 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
5443 | { |
5444 | rtx body, lhs, rhs;; | |
5445 | ||
f0375c66 NC |
5446 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
5447 | return false; | |
9b6b54e2 NC |
5448 | |
5449 | body = PATTERN (insn); | |
5450 | ||
5451 | if (GET_CODE (body) != SET) | |
f0375c66 | 5452 | return false; |
9b6b54e2 NC |
5453 | |
5454 | lhs = XEXP (body, 0); | |
5455 | rhs = XEXP (body, 1); | |
5456 | ||
f0375c66 NC |
5457 | lhs = REG_OR_SUBREG_RTX (lhs); |
5458 | ||
5459 | /* If the destination is not a general purpose | |
5460 | register we do not have to worry. */ | |
5461 | if (GET_CODE (lhs) != REG | |
5462 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
5463 | return false; | |
5464 | ||
5465 | /* As well as loads from memory we also have to react | |
5466 | to loads of invalid constants which will be turned | |
5467 | into loads from the minipool. */ | |
5468 | return (GET_CODE (rhs) == MEM | |
5469 | || GET_CODE (rhs) == SYMBOL_REF | |
5470 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
5471 | } |
5472 | ||
f0375c66 | 5473 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 5474 | static bool |
e32bac5b | 5475 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
5476 | { |
5477 | enum attr_cirrus attr; | |
5478 | ||
e6d29d15 | 5479 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
5480 | if (!insn |
5481 | || GET_CODE (insn) != INSN | |
5482 | || GET_CODE (PATTERN (insn)) == USE | |
5483 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
5484 | return 0; | |
5485 | ||
5486 | attr = get_attr_cirrus (insn); | |
5487 | ||
f0375c66 | 5488 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
5489 | } |
5490 | ||
5491 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 5492 | static void |
e32bac5b | 5493 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
5494 | { |
5495 | enum attr_cirrus attr; | |
5496 | rtx body = PATTERN (first); | |
5497 | rtx t; | |
5498 | int nops; | |
5499 | ||
5500 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
5501 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
5502 | { | |
5503 | nops = 0; | |
5504 | t = next_nonnote_insn (first); | |
5505 | ||
f0375c66 | 5506 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
5507 | ++ nops; |
5508 | ||
f0375c66 | 5509 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
5510 | ++ nops; |
5511 | ||
5512 | while (nops --) | |
5513 | emit_insn_after (gen_nop (), first); | |
5514 | ||
5515 | return; | |
5516 | } | |
5517 | ||
5518 | /* (float (blah)) is in parallel with a clobber. */ | |
5519 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
5520 | body = XVECEXP (body, 0, 0); | |
5521 | ||
5522 | if (GET_CODE (body) == SET) | |
5523 | { | |
5524 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
5525 | ||
5526 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
5527 | be followed by a non Cirrus insn. */ | |
5528 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
5529 | { | |
f0375c66 | 5530 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
5531 | emit_insn_after (gen_nop (), first); |
5532 | ||
5533 | return; | |
5534 | } | |
f0375c66 | 5535 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
5536 | { |
5537 | unsigned int arm_regno; | |
5538 | ||
5539 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
5540 | ldr/cfmv64hr combination where the Rd field is the same | |
5541 | in both instructions must be split with a non Cirrus | |
5542 | insn. Example: | |
5543 | ||
5544 | ldr r0, blah | |
5545 | nop | |
5546 | cfmvsr mvf0, r0. */ | |
5547 | ||
5548 | /* Get Arm register number for ldr insn. */ | |
5549 | if (GET_CODE (lhs) == REG) | |
5550 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 5551 | else |
e6d29d15 NS |
5552 | { |
5553 | gcc_assert (GET_CODE (rhs) == REG); | |
5554 | arm_regno = REGNO (rhs); | |
5555 | } | |
9b6b54e2 NC |
5556 | |
5557 | /* Next insn. */ | |
5558 | first = next_nonnote_insn (first); | |
5559 | ||
f0375c66 | 5560 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
5561 | return; |
5562 | ||
5563 | body = PATTERN (first); | |
5564 | ||
5565 | /* (float (blah)) is in parallel with a clobber. */ | |
5566 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
5567 | body = XVECEXP (body, 0, 0); | |
5568 | ||
5569 | if (GET_CODE (body) == FLOAT) | |
5570 | body = XEXP (body, 0); | |
5571 | ||
5572 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
5573 | && GET_CODE (XEXP (body, 1)) == REG | |
5574 | && arm_regno == REGNO (XEXP (body, 1))) | |
5575 | emit_insn_after (gen_nop (), first); | |
5576 | ||
5577 | return; | |
5578 | } | |
5579 | } | |
5580 | ||
e6d29d15 | 5581 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
5582 | if (!first |
5583 | || GET_CODE (first) != INSN | |
5584 | || GET_CODE (PATTERN (first)) == USE | |
5585 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
5586 | return; | |
5587 | ||
5588 | attr = get_attr_cirrus (first); | |
5589 | ||
5590 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
5591 | must be followed by a non-coprocessor instruction. */ | |
5592 | if (attr == CIRRUS_COMPARE) | |
5593 | { | |
5594 | nops = 0; | |
5595 | ||
5596 | t = next_nonnote_insn (first); | |
5597 | ||
f0375c66 | 5598 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
5599 | ++ nops; |
5600 | ||
f0375c66 | 5601 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
5602 | ++ nops; |
5603 | ||
5604 | while (nops --) | |
5605 | emit_insn_after (gen_nop (), first); | |
5606 | ||
5607 | return; | |
5608 | } | |
5609 | } | |
5610 | ||
2b835d68 RE |
5611 | /* Return TRUE if X references a SYMBOL_REF. */ |
5612 | int | |
e32bac5b | 5613 | symbol_mentioned_p (rtx x) |
2b835d68 | 5614 | { |
1d6e90ac NC |
5615 | const char * fmt; |
5616 | int i; | |
2b835d68 RE |
5617 | |
5618 | if (GET_CODE (x) == SYMBOL_REF) | |
5619 | return 1; | |
5620 | ||
d3585b76 DJ |
5621 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
5622 | are constant offsets, not symbols. */ | |
5623 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
5624 | return 0; | |
5625 | ||
2b835d68 | 5626 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 5627 | |
2b835d68 RE |
5628 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
5629 | { | |
5630 | if (fmt[i] == 'E') | |
5631 | { | |
1d6e90ac | 5632 | int j; |
2b835d68 RE |
5633 | |
5634 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5635 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
5636 | return 1; | |
5637 | } | |
5638 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
5639 | return 1; | |
5640 | } | |
5641 | ||
5642 | return 0; | |
5643 | } | |
5644 | ||
5645 | /* Return TRUE if X references a LABEL_REF. */ | |
5646 | int | |
e32bac5b | 5647 | label_mentioned_p (rtx x) |
2b835d68 | 5648 | { |
1d6e90ac NC |
5649 | const char * fmt; |
5650 | int i; | |
2b835d68 RE |
5651 | |
5652 | if (GET_CODE (x) == LABEL_REF) | |
5653 | return 1; | |
5654 | ||
d3585b76 DJ |
5655 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
5656 | instruction, but they are constant offsets, not symbols. */ | |
5657 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
5658 | return 0; | |
5659 | ||
2b835d68 RE |
5660 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
5661 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5662 | { | |
5663 | if (fmt[i] == 'E') | |
5664 | { | |
1d6e90ac | 5665 | int j; |
2b835d68 RE |
5666 | |
5667 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5668 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
5669 | return 1; | |
5670 | } | |
5671 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
5672 | return 1; | |
5673 | } | |
5674 | ||
5675 | return 0; | |
5676 | } | |
5677 | ||
d3585b76 DJ |
5678 | int |
5679 | tls_mentioned_p (rtx x) | |
5680 | { | |
5681 | switch (GET_CODE (x)) | |
5682 | { | |
5683 | case CONST: | |
5684 | return tls_mentioned_p (XEXP (x, 0)); | |
5685 | ||
5686 | case UNSPEC: | |
5687 | if (XINT (x, 1) == UNSPEC_TLS) | |
5688 | return 1; | |
5689 | ||
5690 | default: | |
5691 | return 0; | |
5692 | } | |
5693 | } | |
5694 | ||
5695 | /* Must not copy a SET whose source operand is PC-relative. */ | |
5696 | ||
5697 | static bool | |
5698 | arm_cannot_copy_insn_p (rtx insn) | |
5699 | { | |
5700 | rtx pat = PATTERN (insn); | |
5701 | ||
5702 | if (GET_CODE (pat) == PARALLEL | |
5703 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET) | |
5704 | { | |
5705 | rtx rhs = SET_SRC (XVECEXP (pat, 0, 0)); | |
5706 | ||
5707 | if (GET_CODE (rhs) == UNSPEC | |
5708 | && XINT (rhs, 1) == UNSPEC_PIC_BASE) | |
5709 | return TRUE; | |
5710 | ||
5711 | if (GET_CODE (rhs) == MEM | |
5712 | && GET_CODE (XEXP (rhs, 0)) == UNSPEC | |
5713 | && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) | |
5714 | return TRUE; | |
5715 | } | |
5716 | ||
5717 | return FALSE; | |
5718 | } | |
5719 | ||
ff9940b0 | 5720 | enum rtx_code |
e32bac5b | 5721 | minmax_code (rtx x) |
ff9940b0 RE |
5722 | { |
5723 | enum rtx_code code = GET_CODE (x); | |
5724 | ||
e6d29d15 NS |
5725 | switch (code) |
5726 | { | |
5727 | case SMAX: | |
5728 | return GE; | |
5729 | case SMIN: | |
5730 | return LE; | |
5731 | case UMIN: | |
5732 | return LEU; | |
5733 | case UMAX: | |
5734 | return GEU; | |
5735 | default: | |
5736 | gcc_unreachable (); | |
5737 | } | |
ff9940b0 RE |
5738 | } |
5739 | ||
6354dc9b | 5740 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 5741 | int |
e32bac5b | 5742 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 5743 | { |
15b5c4c1 RE |
5744 | /* We don't guarantee to preserve the order of these memory refs. */ |
5745 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
5746 | return 0; | |
5747 | ||
ff9940b0 RE |
5748 | if ((GET_CODE (XEXP (a, 0)) == REG |
5749 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
5750 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
5751 | && (GET_CODE (XEXP (b, 0)) == REG | |
5752 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
5753 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
5754 | { | |
6555b6bd RE |
5755 | HOST_WIDE_INT val0 = 0, val1 = 0; |
5756 | rtx reg0, reg1; | |
5757 | int val_diff; | |
f676971a | 5758 | |
ff9940b0 RE |
5759 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
5760 | { | |
6555b6bd | 5761 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
5762 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
5763 | } | |
5764 | else | |
6555b6bd | 5765 | reg0 = XEXP (a, 0); |
1d6e90ac | 5766 | |
ff9940b0 RE |
5767 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
5768 | { | |
6555b6bd | 5769 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
5770 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
5771 | } | |
5772 | else | |
6555b6bd | 5773 | reg1 = XEXP (b, 0); |
1d6e90ac | 5774 | |
e32bac5b RE |
5775 | /* Don't accept any offset that will require multiple |
5776 | instructions to handle, since this would cause the | |
5777 | arith_adjacentmem pattern to output an overlong sequence. */ | |
c75a3ddc PB |
5778 | if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) |
5779 | return 0; | |
f676971a | 5780 | |
6555b6bd RE |
5781 | /* Don't allow an eliminable register: register elimination can make |
5782 | the offset too large. */ | |
5783 | if (arm_eliminable_register (reg0)) | |
5784 | return 0; | |
5785 | ||
5786 | val_diff = val1 - val0; | |
15b5c4c1 RE |
5787 | |
5788 | if (arm_ld_sched) | |
5789 | { | |
5790 | /* If the target has load delay slots, then there's no benefit | |
5791 | to using an ldm instruction unless the offset is zero and | |
5792 | we are optimizing for size. */ | |
5793 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
5794 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
5795 | && (val_diff == 4 || val_diff == -4)); | |
5796 | } | |
5797 | ||
6555b6bd RE |
5798 | return ((REGNO (reg0) == REGNO (reg1)) |
5799 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 5800 | } |
6555b6bd | 5801 | |
ff9940b0 RE |
5802 | return 0; |
5803 | } | |
5804 | ||
84ed5e79 | 5805 | int |
e32bac5b RE |
5806 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
5807 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
5808 | { |
5809 | int unsorted_regs[4]; | |
5810 | HOST_WIDE_INT unsorted_offsets[4]; | |
5811 | int order[4]; | |
ad076f4e | 5812 | int base_reg = -1; |
84ed5e79 RE |
5813 | int i; |
5814 | ||
1d6e90ac NC |
5815 | /* Can only handle 2, 3, or 4 insns at present, |
5816 | though could be easily extended if required. */ | |
e6d29d15 | 5817 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 RE |
5818 | |
5819 | /* Loop over the operands and check that the memory references are | |
112cdef5 | 5820 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
5821 | the same time, extract the target register, and the memory |
5822 | offsets. */ | |
5823 | for (i = 0; i < nops; i++) | |
5824 | { | |
5825 | rtx reg; | |
5826 | rtx offset; | |
5827 | ||
56636818 JL |
5828 | /* Convert a subreg of a mem into the mem itself. */ |
5829 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 5830 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 5831 | |
e6d29d15 | 5832 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
5833 | |
5834 | /* Don't reorder volatile memory references; it doesn't seem worth | |
5835 | looking for the case where the order is ok anyway. */ | |
5836 | if (MEM_VOLATILE_P (operands[nops + i])) | |
5837 | return 0; | |
5838 | ||
5839 | offset = const0_rtx; | |
5840 | ||
5841 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
5842 | || (GET_CODE (reg) == SUBREG | |
5843 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5844 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
5845 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
5846 | == REG) | |
5847 | || (GET_CODE (reg) == SUBREG | |
5848 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5849 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
5850 | == CONST_INT))) | |
5851 | { | |
5852 | if (i == 0) | |
5853 | { | |
d5b7b3ae | 5854 | base_reg = REGNO (reg); |
84ed5e79 RE |
5855 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
5856 | ? REGNO (operands[i]) | |
5857 | : REGNO (SUBREG_REG (operands[i]))); | |
5858 | order[0] = 0; | |
5859 | } | |
f676971a | 5860 | else |
84ed5e79 | 5861 | { |
6354dc9b | 5862 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
5863 | /* Not addressed from the same base register. */ |
5864 | return 0; | |
5865 | ||
5866 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
5867 | ? REGNO (operands[i]) | |
5868 | : REGNO (SUBREG_REG (operands[i]))); | |
5869 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
5870 | order[0] = i; | |
5871 | } | |
5872 | ||
5873 | /* If it isn't an integer register, or if it overwrites the | |
5874 | base register but isn't the last insn in the list, then | |
5875 | we can't do this. */ | |
5876 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
5877 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
5878 | return 0; | |
5879 | ||
5880 | unsorted_offsets[i] = INTVAL (offset); | |
5881 | } | |
5882 | else | |
5883 | /* Not a suitable memory address. */ | |
5884 | return 0; | |
5885 | } | |
5886 | ||
5887 | /* All the useful information has now been extracted from the | |
5888 | operands into unsorted_regs and unsorted_offsets; additionally, | |
5889 | order[0] has been set to the lowest numbered register in the | |
5890 | list. Sort the registers into order, and check that the memory | |
5891 | offsets are ascending and adjacent. */ | |
5892 | ||
5893 | for (i = 1; i < nops; i++) | |
5894 | { | |
5895 | int j; | |
5896 | ||
5897 | order[i] = order[i - 1]; | |
5898 | for (j = 0; j < nops; j++) | |
5899 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
5900 | && (order[i] == order[i - 1] | |
5901 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
5902 | order[i] = j; | |
5903 | ||
5904 | /* Have we found a suitable register? if not, one must be used more | |
5905 | than once. */ | |
5906 | if (order[i] == order[i - 1]) | |
5907 | return 0; | |
5908 | ||
5909 | /* Is the memory address adjacent and ascending? */ | |
5910 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
5911 | return 0; | |
5912 | } | |
5913 | ||
5914 | if (base) | |
5915 | { | |
5916 | *base = base_reg; | |
5917 | ||
5918 | for (i = 0; i < nops; i++) | |
5919 | regs[i] = unsorted_regs[order[i]]; | |
5920 | ||
5921 | *load_offset = unsorted_offsets[order[0]]; | |
5922 | } | |
5923 | ||
5924 | if (unsorted_offsets[order[0]] == 0) | |
5925 | return 1; /* ldmia */ | |
5926 | ||
5927 | if (unsorted_offsets[order[0]] == 4) | |
5928 | return 2; /* ldmib */ | |
5929 | ||
5930 | if (unsorted_offsets[order[nops - 1]] == 0) | |
5931 | return 3; /* ldmda */ | |
5932 | ||
5933 | if (unsorted_offsets[order[nops - 1]] == -4) | |
5934 | return 4; /* ldmdb */ | |
5935 | ||
949d79eb RE |
5936 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
5937 | if the offset isn't small enough. The reason 2 ldrs are faster | |
5938 | is because these ARMs are able to do more than one cache access | |
5939 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
5940 | whilst the ARM8 has a double bandwidth cache. This means that | |
5941 | these cores can do both an instruction fetch and a data fetch in | |
5942 | a single cycle, so the trick of calculating the address into a | |
5943 | scratch register (one of the result regs) and then doing a load | |
5944 | multiple actually becomes slower (and no smaller in code size). | |
5945 | That is the transformation | |
f676971a | 5946 | |
6cc8c0b3 NC |
5947 | ldr rd1, [rbase + offset] |
5948 | ldr rd2, [rbase + offset + 4] | |
f676971a | 5949 | |
6cc8c0b3 | 5950 | to |
f676971a | 5951 | |
6cc8c0b3 NC |
5952 | add rd1, rbase, offset |
5953 | ldmia rd1, {rd1, rd2} | |
f676971a | 5954 | |
949d79eb RE |
5955 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
5956 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
5957 | access per cycle, the first sequence could never complete in less | |
5958 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
5959 | would make better use of sequential accesses if not hitting the | |
5960 | cache. | |
5961 | ||
5962 | We cheat here and test 'arm_ld_sched' which we currently know to | |
5963 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
5964 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 5965 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
5966 | return 0; |
5967 | ||
84ed5e79 RE |
5968 | /* Can't do it without setting up the offset, only do this if it takes |
5969 | no more than one insn. */ | |
f676971a | 5970 | return (const_ok_for_arm (unsorted_offsets[order[0]]) |
84ed5e79 RE |
5971 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; |
5972 | } | |
5973 | ||
cd2b33d0 | 5974 | const char * |
e32bac5b | 5975 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
5976 | { |
5977 | int regs[4]; | |
5978 | int base_reg; | |
5979 | HOST_WIDE_INT offset; | |
5980 | char buf[100]; | |
5981 | int i; | |
5982 | ||
5983 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
5984 | { | |
5985 | case 1: | |
5986 | strcpy (buf, "ldm%?ia\t"); | |
5987 | break; | |
5988 | ||
5989 | case 2: | |
5990 | strcpy (buf, "ldm%?ib\t"); | |
5991 | break; | |
5992 | ||
5993 | case 3: | |
5994 | strcpy (buf, "ldm%?da\t"); | |
5995 | break; | |
5996 | ||
5997 | case 4: | |
5998 | strcpy (buf, "ldm%?db\t"); | |
5999 | break; | |
6000 | ||
6001 | case 5: | |
6002 | if (offset >= 0) | |
6003 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
6004 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
6005 | (long) offset); | |
6006 | else | |
6007 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
6008 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
6009 | (long) -offset); | |
6010 | output_asm_insn (buf, operands); | |
6011 | base_reg = regs[0]; | |
6012 | strcpy (buf, "ldm%?ia\t"); | |
6013 | break; | |
6014 | ||
6015 | default: | |
e6d29d15 | 6016 | gcc_unreachable (); |
84ed5e79 RE |
6017 | } |
6018 | ||
f676971a | 6019 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
6020 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
6021 | ||
6022 | for (i = 1; i < nops; i++) | |
6023 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
6024 | reg_names[regs[i]]); | |
6025 | ||
6026 | strcat (buf, "}\t%@ phole ldm"); | |
6027 | ||
6028 | output_asm_insn (buf, operands); | |
6029 | return ""; | |
6030 | } | |
6031 | ||
6032 | int | |
e32bac5b RE |
6033 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
6034 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
6035 | { |
6036 | int unsorted_regs[4]; | |
6037 | HOST_WIDE_INT unsorted_offsets[4]; | |
6038 | int order[4]; | |
ad076f4e | 6039 | int base_reg = -1; |
84ed5e79 RE |
6040 | int i; |
6041 | ||
6042 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
6043 | extended if required. */ | |
e6d29d15 | 6044 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 RE |
6045 | |
6046 | /* Loop over the operands and check that the memory references are | |
112cdef5 | 6047 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
6048 | the same time, extract the target register, and the memory |
6049 | offsets. */ | |
6050 | for (i = 0; i < nops; i++) | |
6051 | { | |
6052 | rtx reg; | |
6053 | rtx offset; | |
6054 | ||
56636818 JL |
6055 | /* Convert a subreg of a mem into the mem itself. */ |
6056 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 6057 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 6058 | |
e6d29d15 | 6059 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
6060 | |
6061 | /* Don't reorder volatile memory references; it doesn't seem worth | |
6062 | looking for the case where the order is ok anyway. */ | |
6063 | if (MEM_VOLATILE_P (operands[nops + i])) | |
6064 | return 0; | |
6065 | ||
6066 | offset = const0_rtx; | |
6067 | ||
6068 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
6069 | || (GET_CODE (reg) == SUBREG | |
6070 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
6071 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
6072 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
6073 | == REG) | |
6074 | || (GET_CODE (reg) == SUBREG | |
6075 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
6076 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
6077 | == CONST_INT))) | |
6078 | { | |
6079 | if (i == 0) | |
6080 | { | |
62b10bbc | 6081 | base_reg = REGNO (reg); |
84ed5e79 RE |
6082 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
6083 | ? REGNO (operands[i]) | |
6084 | : REGNO (SUBREG_REG (operands[i]))); | |
6085 | order[0] = 0; | |
6086 | } | |
f676971a | 6087 | else |
84ed5e79 | 6088 | { |
6354dc9b | 6089 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
6090 | /* Not addressed from the same base register. */ |
6091 | return 0; | |
6092 | ||
6093 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
6094 | ? REGNO (operands[i]) | |
6095 | : REGNO (SUBREG_REG (operands[i]))); | |
6096 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
6097 | order[0] = i; | |
6098 | } | |
6099 | ||
6100 | /* If it isn't an integer register, then we can't do this. */ | |
6101 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
6102 | return 0; | |
6103 | ||
6104 | unsorted_offsets[i] = INTVAL (offset); | |
6105 | } | |
6106 | else | |
6107 | /* Not a suitable memory address. */ | |
6108 | return 0; | |
6109 | } | |
6110 | ||
6111 | /* All the useful information has now been extracted from the | |
6112 | operands into unsorted_regs and unsorted_offsets; additionally, | |
6113 | order[0] has been set to the lowest numbered register in the | |
6114 | list. Sort the registers into order, and check that the memory | |
6115 | offsets are ascending and adjacent. */ | |
6116 | ||
6117 | for (i = 1; i < nops; i++) | |
6118 | { | |
6119 | int j; | |
6120 | ||
6121 | order[i] = order[i - 1]; | |
6122 | for (j = 0; j < nops; j++) | |
6123 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
6124 | && (order[i] == order[i - 1] | |
6125 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
6126 | order[i] = j; | |
6127 | ||
6128 | /* Have we found a suitable register? if not, one must be used more | |
6129 | than once. */ | |
6130 | if (order[i] == order[i - 1]) | |
6131 | return 0; | |
6132 | ||
6133 | /* Is the memory address adjacent and ascending? */ | |
6134 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
6135 | return 0; | |
6136 | } | |
6137 | ||
6138 | if (base) | |
6139 | { | |
6140 | *base = base_reg; | |
6141 | ||
6142 | for (i = 0; i < nops; i++) | |
6143 | regs[i] = unsorted_regs[order[i]]; | |
6144 | ||
6145 | *load_offset = unsorted_offsets[order[0]]; | |
6146 | } | |
6147 | ||
6148 | if (unsorted_offsets[order[0]] == 0) | |
6149 | return 1; /* stmia */ | |
6150 | ||
6151 | if (unsorted_offsets[order[0]] == 4) | |
6152 | return 2; /* stmib */ | |
6153 | ||
6154 | if (unsorted_offsets[order[nops - 1]] == 0) | |
6155 | return 3; /* stmda */ | |
6156 | ||
6157 | if (unsorted_offsets[order[nops - 1]] == -4) | |
6158 | return 4; /* stmdb */ | |
6159 | ||
6160 | return 0; | |
6161 | } | |
6162 | ||
cd2b33d0 | 6163 | const char * |
e32bac5b | 6164 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
6165 | { |
6166 | int regs[4]; | |
6167 | int base_reg; | |
6168 | HOST_WIDE_INT offset; | |
6169 | char buf[100]; | |
6170 | int i; | |
6171 | ||
6172 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
6173 | { | |
6174 | case 1: | |
6175 | strcpy (buf, "stm%?ia\t"); | |
6176 | break; | |
6177 | ||
6178 | case 2: | |
6179 | strcpy (buf, "stm%?ib\t"); | |
6180 | break; | |
6181 | ||
6182 | case 3: | |
6183 | strcpy (buf, "stm%?da\t"); | |
6184 | break; | |
6185 | ||
6186 | case 4: | |
6187 | strcpy (buf, "stm%?db\t"); | |
6188 | break; | |
6189 | ||
6190 | default: | |
e6d29d15 | 6191 | gcc_unreachable (); |
84ed5e79 RE |
6192 | } |
6193 | ||
f676971a | 6194 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
6195 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
6196 | ||
6197 | for (i = 1; i < nops; i++) | |
6198 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
6199 | reg_names[regs[i]]); | |
6200 | ||
6201 | strcat (buf, "}\t%@ phole stm"); | |
6202 | ||
6203 | output_asm_insn (buf, operands); | |
6204 | return ""; | |
6205 | } | |
ff9940b0 | 6206 | \f |
6354dc9b | 6207 | /* Routines for use in generating RTL. */ |
1d6e90ac | 6208 | |
f3bb6135 | 6209 | rtx |
e32bac5b | 6210 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
50ed9cea | 6211 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 6212 | { |
50ed9cea | 6213 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
6214 | int i = 0, j; |
6215 | rtx result; | |
6216 | int sign = up ? 1 : -1; | |
50ed9cea | 6217 | rtx mem, addr; |
ff9940b0 | 6218 | |
d19fb8e3 | 6219 | /* XScale has load-store double instructions, but they have stricter |
1e5f1716 | 6220 | alignment requirements than load-store multiple, so we cannot |
d19fb8e3 NC |
6221 | use them. |
6222 | ||
6223 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
6224 | the pipeline until completion. | |
6225 | ||
6226 | NREGS CYCLES | |
6227 | 1 3 | |
6228 | 2 4 | |
6229 | 3 5 | |
6230 | 4 6 | |
6231 | ||
6232 | An ldr instruction takes 1-3 cycles, but does not block the | |
6233 | pipeline. | |
6234 | ||
6235 | NREGS CYCLES | |
6236 | 1 1-3 | |
6237 | 2 2-6 | |
6238 | 3 3-9 | |
6239 | 4 4-12 | |
6240 | ||
6241 | Best case ldr will always win. However, the more ldr instructions | |
6242 | we issue, the less likely we are to be able to schedule them well. | |
6243 | Using ldr instructions also increases code size. | |
6244 | ||
6245 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
6246 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 6247 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
6248 | { |
6249 | rtx seq; | |
f676971a | 6250 | |
d19fb8e3 | 6251 | start_sequence (); |
f676971a | 6252 | |
d19fb8e3 NC |
6253 | for (i = 0; i < count; i++) |
6254 | { | |
50ed9cea RH |
6255 | addr = plus_constant (from, i * 4 * sign); |
6256 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 6257 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); |
50ed9cea | 6258 | offset += 4 * sign; |
d19fb8e3 NC |
6259 | } |
6260 | ||
6261 | if (write_back) | |
50ed9cea RH |
6262 | { |
6263 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
6264 | *offsetp = offset; | |
6265 | } | |
d19fb8e3 | 6266 | |
2f937369 | 6267 | seq = get_insns (); |
d19fb8e3 | 6268 | end_sequence (); |
f676971a | 6269 | |
d19fb8e3 NC |
6270 | return seq; |
6271 | } | |
6272 | ||
43cffd11 | 6273 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 6274 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 6275 | if (write_back) |
f3bb6135 | 6276 | { |
ff9940b0 | 6277 | XVECEXP (result, 0, 0) |
d66437c5 | 6278 | = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); |
ff9940b0 RE |
6279 | i = 1; |
6280 | count++; | |
f3bb6135 RE |
6281 | } |
6282 | ||
ff9940b0 | 6283 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 6284 | { |
50ed9cea RH |
6285 | addr = plus_constant (from, j * 4 * sign); |
6286 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
6287 | XVECEXP (result, 0, i) |
6288 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
50ed9cea | 6289 | offset += 4 * sign; |
f3bb6135 RE |
6290 | } |
6291 | ||
50ed9cea RH |
6292 | if (write_back) |
6293 | *offsetp = offset; | |
6294 | ||
ff9940b0 RE |
6295 | return result; |
6296 | } | |
6297 | ||
f3bb6135 | 6298 | rtx |
e32bac5b | 6299 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
50ed9cea | 6300 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 6301 | { |
50ed9cea | 6302 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
6303 | int i = 0, j; |
6304 | rtx result; | |
6305 | int sign = up ? 1 : -1; | |
50ed9cea | 6306 | rtx mem, addr; |
ff9940b0 | 6307 | |
d19fb8e3 NC |
6308 | /* See arm_gen_load_multiple for discussion of |
6309 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 6310 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
6311 | { |
6312 | rtx seq; | |
f676971a | 6313 | |
d19fb8e3 | 6314 | start_sequence (); |
f676971a | 6315 | |
d19fb8e3 NC |
6316 | for (i = 0; i < count; i++) |
6317 | { | |
50ed9cea RH |
6318 | addr = plus_constant (to, i * 4 * sign); |
6319 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 6320 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); |
50ed9cea | 6321 | offset += 4 * sign; |
d19fb8e3 NC |
6322 | } |
6323 | ||
6324 | if (write_back) | |
50ed9cea RH |
6325 | { |
6326 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
6327 | *offsetp = offset; | |
6328 | } | |
d19fb8e3 | 6329 | |
2f937369 | 6330 | seq = get_insns (); |
d19fb8e3 | 6331 | end_sequence (); |
f676971a | 6332 | |
d19fb8e3 NC |
6333 | return seq; |
6334 | } | |
6335 | ||
43cffd11 | 6336 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 6337 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 6338 | if (write_back) |
f3bb6135 | 6339 | { |
ff9940b0 | 6340 | XVECEXP (result, 0, 0) |
d66437c5 | 6341 | = gen_rtx_SET (VOIDmode, to, |
43cffd11 | 6342 | plus_constant (to, count * 4 * sign)); |
ff9940b0 RE |
6343 | i = 1; |
6344 | count++; | |
f3bb6135 RE |
6345 | } |
6346 | ||
ff9940b0 | 6347 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 6348 | { |
50ed9cea RH |
6349 | addr = plus_constant (to, j * 4 * sign); |
6350 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
6351 | XVECEXP (result, 0, i) |
6352 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
50ed9cea | 6353 | offset += 4 * sign; |
f3bb6135 RE |
6354 | } |
6355 | ||
50ed9cea RH |
6356 | if (write_back) |
6357 | *offsetp = offset; | |
6358 | ||
ff9940b0 RE |
6359 | return result; |
6360 | } | |
6361 | ||
880e2516 | 6362 | int |
70128ad9 | 6363 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
6364 | { |
6365 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 6366 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 6367 | int i; |
50ed9cea | 6368 | rtx src, dst, srcbase, dstbase; |
880e2516 | 6369 | rtx part_bytes_reg = NULL; |
56636818 | 6370 | rtx mem; |
880e2516 RE |
6371 | |
6372 | if (GET_CODE (operands[2]) != CONST_INT | |
6373 | || GET_CODE (operands[3]) != CONST_INT | |
6374 | || INTVAL (operands[2]) > 64 | |
6375 | || INTVAL (operands[3]) & 3) | |
6376 | return 0; | |
6377 | ||
50ed9cea RH |
6378 | dstbase = operands[0]; |
6379 | srcbase = operands[1]; | |
56636818 | 6380 | |
50ed9cea RH |
6381 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
6382 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 6383 | |
e9d7b180 | 6384 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
6385 | out_words_to_go = INTVAL (operands[2]) / 4; |
6386 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 6387 | dstoffset = srcoffset = 0; |
880e2516 RE |
6388 | |
6389 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 6390 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
6391 | |
6392 | for (i = 0; in_words_to_go >= 2; i+=4) | |
6393 | { | |
bd9c7e23 | 6394 | if (in_words_to_go > 4) |
56636818 | 6395 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
50ed9cea | 6396 | srcbase, &srcoffset)); |
bd9c7e23 | 6397 | else |
f676971a | 6398 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, |
50ed9cea | 6399 | FALSE, srcbase, &srcoffset)); |
bd9c7e23 | 6400 | |
880e2516 RE |
6401 | if (out_words_to_go) |
6402 | { | |
bd9c7e23 | 6403 | if (out_words_to_go > 4) |
56636818 | 6404 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
50ed9cea | 6405 | dstbase, &dstoffset)); |
bd9c7e23 RE |
6406 | else if (out_words_to_go != 1) |
6407 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
f676971a | 6408 | dst, TRUE, |
bd9c7e23 | 6409 | (last_bytes == 0 |
56636818 | 6410 | ? FALSE : TRUE), |
50ed9cea | 6411 | dstbase, &dstoffset)); |
880e2516 RE |
6412 | else |
6413 | { | |
50ed9cea | 6414 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 6415 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 6416 | if (last_bytes != 0) |
50ed9cea RH |
6417 | { |
6418 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
6419 | dstoffset += 4; | |
6420 | } | |
880e2516 RE |
6421 | } |
6422 | } | |
6423 | ||
6424 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
6425 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
6426 | } | |
6427 | ||
6428 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
6429 | if (out_words_to_go) | |
62b10bbc NC |
6430 | { |
6431 | rtx sreg; | |
f676971a | 6432 | |
50ed9cea RH |
6433 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
6434 | sreg = copy_to_reg (mem); | |
6435 | ||
6436 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 6437 | emit_move_insn (mem, sreg); |
62b10bbc | 6438 | in_words_to_go--; |
f676971a | 6439 | |
e6d29d15 | 6440 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 6441 | } |
880e2516 RE |
6442 | |
6443 | if (in_words_to_go) | |
6444 | { | |
e6d29d15 | 6445 | gcc_assert (in_words_to_go > 0); |
880e2516 | 6446 | |
50ed9cea | 6447 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 6448 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
6449 | } |
6450 | ||
e6d29d15 | 6451 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 6452 | |
880e2516 RE |
6453 | if (BYTES_BIG_ENDIAN && last_bytes) |
6454 | { | |
6455 | rtx tmp = gen_reg_rtx (SImode); | |
6456 | ||
6354dc9b | 6457 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
6458 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
6459 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 6460 | part_bytes_reg = tmp; |
f676971a | 6461 | |
880e2516 RE |
6462 | while (last_bytes) |
6463 | { | |
50ed9cea RH |
6464 | mem = adjust_automodify_address (dstbase, QImode, |
6465 | plus_constant (dst, last_bytes - 1), | |
6466 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
6467 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
6468 | ||
880e2516 RE |
6469 | if (--last_bytes) |
6470 | { | |
6471 | tmp = gen_reg_rtx (SImode); | |
6472 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
6473 | part_bytes_reg = tmp; | |
6474 | } | |
6475 | } | |
f676971a | 6476 | |
880e2516 RE |
6477 | } |
6478 | else | |
6479 | { | |
d5b7b3ae | 6480 | if (last_bytes > 1) |
880e2516 | 6481 | { |
50ed9cea | 6482 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 6483 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
6484 | last_bytes -= 2; |
6485 | if (last_bytes) | |
880e2516 RE |
6486 | { |
6487 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 6488 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 6489 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 6490 | part_bytes_reg = tmp; |
50ed9cea | 6491 | dstoffset += 2; |
880e2516 RE |
6492 | } |
6493 | } | |
f676971a | 6494 | |
d5b7b3ae RE |
6495 | if (last_bytes) |
6496 | { | |
50ed9cea | 6497 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 6498 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 6499 | } |
880e2516 RE |
6500 | } |
6501 | ||
6502 | return 1; | |
6503 | } | |
6504 | ||
03f1640c RE |
6505 | /* Select a dominance comparison mode if possible for a test of the general |
6506 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 6507 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 6508 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 6509 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 6510 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 6511 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
6512 | CC mode. This will then fail to match for the RTL expressions that |
6513 | generate this call. */ | |
03f1640c | 6514 | enum machine_mode |
e32bac5b | 6515 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
6516 | { |
6517 | enum rtx_code cond1, cond2; | |
6518 | int swapped = 0; | |
6519 | ||
6520 | /* Currently we will probably get the wrong result if the individual | |
6521 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 6522 | reverse a comparison if necessary. */ |
84ed5e79 RE |
6523 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
6524 | != CCmode) | |
6525 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
6526 | != CCmode)) | |
6527 | return CCmode; | |
6528 | ||
1646cf41 RE |
6529 | /* The if_then_else variant of this tests the second condition if the |
6530 | first passes, but is true if the first fails. Reverse the first | |
6531 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 6532 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
6533 | cond1 = reverse_condition (cond1); |
6534 | ||
6535 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
6536 | then we can't do this. */ | |
f676971a | 6537 | if (cond1 != cond2 |
5895f793 RE |
6538 | && !comparison_dominates_p (cond1, cond2) |
6539 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
6540 | return CCmode; |
6541 | ||
6542 | if (swapped) | |
6543 | { | |
6544 | enum rtx_code temp = cond1; | |
6545 | cond1 = cond2; | |
6546 | cond2 = temp; | |
6547 | } | |
6548 | ||
6549 | switch (cond1) | |
6550 | { | |
6551 | case EQ: | |
e6d29d15 | 6552 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6553 | return CC_DEQmode; |
6554 | ||
6555 | switch (cond2) | |
6556 | { | |
e6d29d15 | 6557 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
6558 | case LE: return CC_DLEmode; |
6559 | case LEU: return CC_DLEUmode; | |
6560 | case GE: return CC_DGEmode; | |
6561 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 6562 | default: gcc_unreachable (); |
84ed5e79 RE |
6563 | } |
6564 | ||
84ed5e79 | 6565 | case LT: |
e6d29d15 | 6566 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 6567 | return CC_DLTmode; |
e0b92319 | 6568 | |
e6d29d15 NS |
6569 | switch (cond2) |
6570 | { | |
6571 | case LT: | |
6572 | return CC_DLTmode; | |
6573 | case LE: | |
6574 | return CC_DLEmode; | |
6575 | case NE: | |
6576 | return CC_DNEmode; | |
6577 | default: | |
6578 | gcc_unreachable (); | |
6579 | } | |
84ed5e79 RE |
6580 | |
6581 | case GT: | |
e6d29d15 | 6582 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 6583 | return CC_DGTmode; |
e6d29d15 NS |
6584 | |
6585 | switch (cond2) | |
6586 | { | |
6587 | case GT: | |
6588 | return CC_DGTmode; | |
6589 | case GE: | |
6590 | return CC_DGEmode; | |
6591 | case NE: | |
6592 | return CC_DNEmode; | |
6593 | default: | |
6594 | gcc_unreachable (); | |
6595 | } | |
f676971a | 6596 | |
84ed5e79 | 6597 | case LTU: |
e6d29d15 | 6598 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 6599 | return CC_DLTUmode; |
e6d29d15 NS |
6600 | |
6601 | switch (cond2) | |
6602 | { | |
6603 | case LTU: | |
6604 | return CC_DLTUmode; | |
6605 | case LEU: | |
6606 | return CC_DLEUmode; | |
6607 | case NE: | |
6608 | return CC_DNEmode; | |
6609 | default: | |
6610 | gcc_unreachable (); | |
6611 | } | |
84ed5e79 RE |
6612 | |
6613 | case GTU: | |
e6d29d15 | 6614 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 6615 | return CC_DGTUmode; |
e0b92319 | 6616 | |
e6d29d15 NS |
6617 | switch (cond2) |
6618 | { | |
6619 | case GTU: | |
6620 | return CC_DGTUmode; | |
6621 | case GEU: | |
6622 | return CC_DGEUmode; | |
6623 | case NE: | |
6624 | return CC_DNEmode; | |
6625 | default: | |
6626 | gcc_unreachable (); | |
6627 | } | |
84ed5e79 RE |
6628 | |
6629 | /* The remaining cases only occur when both comparisons are the | |
6630 | same. */ | |
6631 | case NE: | |
e6d29d15 | 6632 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
6633 | return CC_DNEmode; |
6634 | ||
6635 | case LE: | |
e6d29d15 | 6636 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
6637 | return CC_DLEmode; |
6638 | ||
6639 | case GE: | |
e6d29d15 | 6640 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
6641 | return CC_DGEmode; |
6642 | ||
6643 | case LEU: | |
e6d29d15 | 6644 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
6645 | return CC_DLEUmode; |
6646 | ||
6647 | case GEU: | |
e6d29d15 | 6648 | gcc_assert (cond1 == cond2); |
84ed5e79 | 6649 | return CC_DGEUmode; |
ad076f4e RE |
6650 | |
6651 | default: | |
e6d29d15 | 6652 | gcc_unreachable (); |
84ed5e79 | 6653 | } |
84ed5e79 RE |
6654 | } |
6655 | ||
6656 | enum machine_mode | |
e32bac5b | 6657 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
6658 | { |
6659 | /* All floating point compares return CCFP if it is an equality | |
6660 | comparison, and CCFPE otherwise. */ | |
6661 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
6662 | { |
6663 | switch (op) | |
6664 | { | |
6665 | case EQ: | |
6666 | case NE: | |
6667 | case UNORDERED: | |
6668 | case ORDERED: | |
6669 | case UNLT: | |
6670 | case UNLE: | |
6671 | case UNGT: | |
6672 | case UNGE: | |
6673 | case UNEQ: | |
6674 | case LTGT: | |
6675 | return CCFPmode; | |
6676 | ||
6677 | case LT: | |
6678 | case LE: | |
6679 | case GT: | |
6680 | case GE: | |
9b66ebb1 | 6681 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 6682 | return CCFPmode; |
e45b72c4 RE |
6683 | return CCFPEmode; |
6684 | ||
6685 | default: | |
e6d29d15 | 6686 | gcc_unreachable (); |
e45b72c4 RE |
6687 | } |
6688 | } | |
f676971a | 6689 | |
84ed5e79 RE |
6690 | /* A compare with a shifted operand. Because of canonicalization, the |
6691 | comparison will have to be swapped when we emit the assembler. */ | |
6692 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
6693 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
6694 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
6695 | || GET_CODE (x) == ROTATERT)) | |
6696 | return CC_SWPmode; | |
6697 | ||
04d8b819 RE |
6698 | /* This operation is performed swapped, but since we only rely on the Z |
6699 | flag we don't need an additional mode. */ | |
6700 | if (GET_MODE (y) == SImode && REG_P (y) | |
6701 | && GET_CODE (x) == NEG | |
6702 | && (op == EQ || op == NE)) | |
6703 | return CC_Zmode; | |
6704 | ||
f676971a | 6705 | /* This is a special case that is used by combine to allow a |
956d6950 | 6706 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 6707 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 6708 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
6709 | if (GET_MODE (x) == SImode |
6710 | && GET_CODE (x) == ASHIFT | |
6711 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
6712 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
6713 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
6714 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
6715 | && (op == EQ || op == NE | |
6716 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
6717 | && GET_CODE (y) == CONST_INT) | |
6718 | return CC_Zmode; | |
6719 | ||
1646cf41 RE |
6720 | /* A construct for a conditional compare, if the false arm contains |
6721 | 0, then both conditions must be true, otherwise either condition | |
6722 | must be true. Not all conditions are possible, so CCmode is | |
6723 | returned if it can't be done. */ | |
6724 | if (GET_CODE (x) == IF_THEN_ELSE | |
6725 | && (XEXP (x, 2) == const0_rtx | |
6726 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
6727 | && COMPARISON_P (XEXP (x, 0)) |
6728 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 6729 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 6730 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
6731 | |
6732 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
6733 | if (GET_CODE (x) == AND | |
ec8e098d PB |
6734 | && COMPARISON_P (XEXP (x, 0)) |
6735 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
6736 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
6737 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
6738 | |
6739 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
6740 | && COMPARISON_P (XEXP (x, 0)) |
6741 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
6742 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
6743 | DOM_CC_X_OR_Y); | |
1646cf41 | 6744 | |
defc0463 RE |
6745 | /* An operation (on Thumb) where we want to test for a single bit. |
6746 | This is done by shifting that bit up into the top bit of a | |
6747 | scratch register; we can then branch on the sign bit. */ | |
6748 | if (TARGET_THUMB | |
6749 | && GET_MODE (x) == SImode | |
6750 | && (op == EQ || op == NE) | |
6751 | && (GET_CODE (x) == ZERO_EXTRACT)) | |
6752 | return CC_Nmode; | |
6753 | ||
84ed5e79 RE |
6754 | /* An operation that sets the condition codes as a side-effect, the |
6755 | V flag is not set correctly, so we can only use comparisons where | |
6756 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 6757 | instead.) */ |
84ed5e79 RE |
6758 | if (GET_MODE (x) == SImode |
6759 | && y == const0_rtx | |
6760 | && (op == EQ || op == NE || op == LT || op == GE) | |
6761 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
6762 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
6763 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
6764 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
6765 | || GET_CODE (x) == LSHIFTRT | |
6766 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 RE |
6767 | || GET_CODE (x) == ROTATERT |
6768 | || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT))) | |
84ed5e79 RE |
6769 | return CC_NOOVmode; |
6770 | ||
84ed5e79 RE |
6771 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
6772 | return CC_Zmode; | |
6773 | ||
bd9c7e23 RE |
6774 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
6775 | && GET_CODE (x) == PLUS | |
6776 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
6777 | return CC_Cmode; | |
6778 | ||
84ed5e79 RE |
6779 | return CCmode; |
6780 | } | |
6781 | ||
ff9940b0 RE |
6782 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
6783 | return the rtx for register 0 in the proper mode. FP means this is a | |
6784 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 6785 | rtx |
e32bac5b | 6786 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
6787 | { |
6788 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 6789 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 6790 | |
d66437c5 | 6791 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); |
ff9940b0 RE |
6792 | |
6793 | return cc_reg; | |
6794 | } | |
6795 | ||
fcd53748 JT |
6796 | /* Generate a sequence of insns that will generate the correct return |
6797 | address mask depending on the physical architecture that the program | |
6798 | is running on. */ | |
fcd53748 | 6799 | rtx |
e32bac5b | 6800 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
6801 | { |
6802 | rtx reg = gen_reg_rtx (Pmode); | |
6803 | ||
6804 | emit_insn (gen_return_addr_mask (reg)); | |
6805 | return reg; | |
6806 | } | |
6807 | ||
0a81f500 | 6808 | void |
e32bac5b | 6809 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 6810 | { |
f9cc092a RE |
6811 | rtx ref = operands[1]; |
6812 | rtx base, scratch; | |
6813 | HOST_WIDE_INT offset = 0; | |
6814 | ||
6815 | if (GET_CODE (ref) == SUBREG) | |
6816 | { | |
ddef6bc7 | 6817 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
6818 | ref = SUBREG_REG (ref); |
6819 | } | |
6820 | ||
6821 | if (GET_CODE (ref) == REG) | |
6822 | { | |
6823 | /* We have a pseudo which has been spilt onto the stack; there | |
6824 | are two cases here: the first where there is a simple | |
6825 | stack-slot replacement and a second where the stack-slot is | |
6826 | out of range, or is used as a subreg. */ | |
6827 | if (reg_equiv_mem[REGNO (ref)]) | |
6828 | { | |
6829 | ref = reg_equiv_mem[REGNO (ref)]; | |
6830 | base = find_replacement (&XEXP (ref, 0)); | |
6831 | } | |
6832 | else | |
6354dc9b | 6833 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
6834 | base = reg_equiv_address[REGNO (ref)]; |
6835 | } | |
6836 | else | |
6837 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 6838 | |
e5e809f4 JL |
6839 | /* Handle the case where the address is too complex to be offset by 1. */ |
6840 | if (GET_CODE (base) == MINUS | |
6841 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
6842 | { | |
f9cc092a | 6843 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 6844 | |
d66437c5 | 6845 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
6846 | base = base_plus; |
6847 | } | |
f9cc092a RE |
6848 | else if (GET_CODE (base) == PLUS) |
6849 | { | |
6354dc9b | 6850 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
6851 | HOST_WIDE_INT hi, lo; |
6852 | ||
6853 | offset += INTVAL (XEXP (base, 1)); | |
6854 | base = XEXP (base, 0); | |
6855 | ||
6354dc9b | 6856 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
6857 | /* Valid range for lo is -4095 -> 4095 */ |
6858 | lo = (offset >= 0 | |
6859 | ? (offset & 0xfff) | |
6860 | : -((-offset) & 0xfff)); | |
6861 | ||
6862 | /* Corner case, if lo is the max offset then we would be out of range | |
6863 | once we have added the additional 1 below, so bump the msb into the | |
6864 | pre-loading insn(s). */ | |
6865 | if (lo == 4095) | |
6866 | lo &= 0x7ff; | |
6867 | ||
30cf4896 KG |
6868 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
6869 | ^ (HOST_WIDE_INT) 0x80000000) | |
6870 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 6871 | |
e6d29d15 | 6872 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
6873 | |
6874 | if (hi != 0) | |
6875 | { | |
6876 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6877 | ||
6878 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 6879 | that require more than one insn. */ |
f9cc092a RE |
6880 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
6881 | base = base_plus; | |
6882 | offset = lo; | |
6883 | } | |
6884 | } | |
e5e809f4 | 6885 | |
3a1944a6 RE |
6886 | /* Operands[2] may overlap operands[0] (though it won't overlap |
6887 | operands[1]), that's why we asked for a DImode reg -- so we can | |
6888 | use the bit that does not overlap. */ | |
6889 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
6890 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6891 | else | |
6892 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
6893 | ||
f9cc092a RE |
6894 | emit_insn (gen_zero_extendqisi2 (scratch, |
6895 | gen_rtx_MEM (QImode, | |
6896 | plus_constant (base, | |
6897 | offset)))); | |
43cffd11 | 6898 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 6899 | gen_rtx_MEM (QImode, |
f9cc092a RE |
6900 | plus_constant (base, |
6901 | offset + 1)))); | |
5895f793 | 6902 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
6903 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
6904 | gen_rtx_IOR (SImode, | |
6905 | gen_rtx_ASHIFT | |
6906 | (SImode, | |
6907 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
6908 | GEN_INT (8)), | |
6909 | scratch)); | |
0a81f500 | 6910 | else |
d66437c5 RE |
6911 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
6912 | gen_rtx_IOR (SImode, | |
6913 | gen_rtx_ASHIFT (SImode, scratch, | |
6914 | GEN_INT (8)), | |
6915 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
6916 | } |
6917 | ||
72ac76be | 6918 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
6919 | byte stores. Take care not to clobber the input values until after we |
6920 | have moved them somewhere safe. This code assumes that if the DImode | |
6921 | scratch in operands[2] overlaps either the input value or output address | |
6922 | in some way, then that value must die in this insn (we absolutely need | |
6923 | two scratch registers for some corner cases). */ | |
f3bb6135 | 6924 | void |
e32bac5b | 6925 | arm_reload_out_hi (rtx *operands) |
af48348a | 6926 | { |
f9cc092a RE |
6927 | rtx ref = operands[0]; |
6928 | rtx outval = operands[1]; | |
6929 | rtx base, scratch; | |
6930 | HOST_WIDE_INT offset = 0; | |
6931 | ||
6932 | if (GET_CODE (ref) == SUBREG) | |
6933 | { | |
ddef6bc7 | 6934 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
6935 | ref = SUBREG_REG (ref); |
6936 | } | |
6937 | ||
f9cc092a RE |
6938 | if (GET_CODE (ref) == REG) |
6939 | { | |
6940 | /* We have a pseudo which has been spilt onto the stack; there | |
6941 | are two cases here: the first where there is a simple | |
6942 | stack-slot replacement and a second where the stack-slot is | |
6943 | out of range, or is used as a subreg. */ | |
6944 | if (reg_equiv_mem[REGNO (ref)]) | |
6945 | { | |
6946 | ref = reg_equiv_mem[REGNO (ref)]; | |
6947 | base = find_replacement (&XEXP (ref, 0)); | |
6948 | } | |
6949 | else | |
6354dc9b | 6950 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
6951 | base = reg_equiv_address[REGNO (ref)]; |
6952 | } | |
6953 | else | |
6954 | base = find_replacement (&XEXP (ref, 0)); | |
6955 | ||
6956 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
6957 | ||
6958 | /* Handle the case where the address is too complex to be offset by 1. */ | |
6959 | if (GET_CODE (base) == MINUS | |
6960 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
6961 | { | |
6962 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6963 | ||
6964 | /* Be careful not to destroy OUTVAL. */ | |
6965 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
6966 | { | |
6967 | /* Updating base_plus might destroy outval, see if we can | |
6968 | swap the scratch and base_plus. */ | |
5895f793 | 6969 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
6970 | { |
6971 | rtx tmp = scratch; | |
6972 | scratch = base_plus; | |
6973 | base_plus = tmp; | |
6974 | } | |
6975 | else | |
6976 | { | |
6977 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
6978 | ||
6979 | /* Be conservative and copy OUTVAL into the scratch now, | |
6980 | this should only be necessary if outval is a subreg | |
6981 | of something larger than a word. */ | |
6982 | /* XXX Might this clobber base? I can't see how it can, | |
6983 | since scratch is known to overlap with OUTVAL, and | |
6984 | must be wider than a word. */ | |
6985 | emit_insn (gen_movhi (scratch_hi, outval)); | |
6986 | outval = scratch_hi; | |
6987 | } | |
6988 | } | |
6989 | ||
d66437c5 | 6990 | emit_set_insn (base_plus, base); |
f9cc092a RE |
6991 | base = base_plus; |
6992 | } | |
6993 | else if (GET_CODE (base) == PLUS) | |
6994 | { | |
6354dc9b | 6995 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
6996 | HOST_WIDE_INT hi, lo; |
6997 | ||
6998 | offset += INTVAL (XEXP (base, 1)); | |
6999 | base = XEXP (base, 0); | |
7000 | ||
6354dc9b | 7001 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
7002 | /* Valid range for lo is -4095 -> 4095 */ |
7003 | lo = (offset >= 0 | |
7004 | ? (offset & 0xfff) | |
7005 | : -((-offset) & 0xfff)); | |
7006 | ||
7007 | /* Corner case, if lo is the max offset then we would be out of range | |
7008 | once we have added the additional 1 below, so bump the msb into the | |
7009 | pre-loading insn(s). */ | |
7010 | if (lo == 4095) | |
7011 | lo &= 0x7ff; | |
7012 | ||
30cf4896 KG |
7013 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
7014 | ^ (HOST_WIDE_INT) 0x80000000) | |
7015 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 7016 | |
e6d29d15 | 7017 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
7018 | |
7019 | if (hi != 0) | |
7020 | { | |
7021 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
7022 | ||
7023 | /* Be careful not to destroy OUTVAL. */ | |
7024 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
7025 | { | |
7026 | /* Updating base_plus might destroy outval, see if we | |
7027 | can swap the scratch and base_plus. */ | |
5895f793 | 7028 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
7029 | { |
7030 | rtx tmp = scratch; | |
7031 | scratch = base_plus; | |
7032 | base_plus = tmp; | |
7033 | } | |
7034 | else | |
7035 | { | |
7036 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
7037 | ||
7038 | /* Be conservative and copy outval into scratch now, | |
7039 | this should only be necessary if outval is a | |
7040 | subreg of something larger than a word. */ | |
7041 | /* XXX Might this clobber base? I can't see how it | |
7042 | can, since scratch is known to overlap with | |
7043 | outval. */ | |
7044 | emit_insn (gen_movhi (scratch_hi, outval)); | |
7045 | outval = scratch_hi; | |
7046 | } | |
7047 | } | |
7048 | ||
7049 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 7050 | that require more than one insn. */ |
f9cc092a RE |
7051 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
7052 | base = base_plus; | |
7053 | offset = lo; | |
7054 | } | |
7055 | } | |
af48348a | 7056 | |
b5cc037f RE |
7057 | if (BYTES_BIG_ENDIAN) |
7058 | { | |
f676971a | 7059 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 7060 | plus_constant (base, offset + 1)), |
5d5603e2 | 7061 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
7062 | emit_insn (gen_lshrsi3 (scratch, |
7063 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 7064 | GEN_INT (8))); |
f9cc092a | 7065 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 7066 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
7067 | } |
7068 | else | |
7069 | { | |
f9cc092a | 7070 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 7071 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
7072 | emit_insn (gen_lshrsi3 (scratch, |
7073 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 7074 | GEN_INT (8))); |
f9cc092a RE |
7075 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
7076 | plus_constant (base, offset + 1)), | |
5d5603e2 | 7077 | gen_lowpart (QImode, scratch))); |
b5cc037f | 7078 | } |
af48348a | 7079 | } |
866af8a9 JB |
7080 | |
7081 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
7082 | (padded to the size of a word) should be passed in a register. */ | |
7083 | ||
7084 | static bool | |
7085 | arm_must_pass_in_stack (enum machine_mode mode, tree type) | |
7086 | { | |
7087 | if (TARGET_AAPCS_BASED) | |
7088 | return must_pass_in_stack_var_size (mode, type); | |
7089 | else | |
7090 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
7091 | } | |
7092 | ||
7093 | ||
7094 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
7095 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
7096 | i.e. if the least-significant byte has useful data. |
7097 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
7098 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
7099 | |
7100 | bool | |
7101 | arm_pad_arg_upward (enum machine_mode mode, tree type) | |
7102 | { | |
7103 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 7104 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
7105 | |
7106 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
7107 | return false; | |
7108 | ||
7109 | return true; | |
7110 | } | |
7111 | ||
7112 | ||
7113 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
7114 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
7115 | byte of the register has useful data, and return the opposite if the | |
7116 | most significant byte does. | |
7117 | For AAPCS, small aggregates and small complex types are always padded | |
7118 | upwards. */ | |
7119 | ||
7120 | bool | |
7121 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
7122 | tree type, int first ATTRIBUTE_UNUSED) | |
7123 | { | |
7124 | if (TARGET_AAPCS_BASED | |
7125 | && BYTES_BIG_ENDIAN | |
7126 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
7127 | && int_size_in_bytes (type) <= 4) | |
7128 | return true; | |
7129 | ||
7130 | /* Otherwise, use default padding. */ | |
7131 | return !BYTES_BIG_ENDIAN; | |
7132 | } | |
7133 | ||
2b835d68 | 7134 | \f |
d5b7b3ae RE |
7135 | /* Print a symbolic form of X to the debug file, F. */ |
7136 | static void | |
e32bac5b | 7137 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
7138 | { |
7139 | switch (GET_CODE (x)) | |
7140 | { | |
7141 | case CONST_INT: | |
7142 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
7143 | return; | |
7144 | ||
7145 | case CONST_DOUBLE: | |
7146 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
7147 | return; | |
7148 | ||
5a9335ef NC |
7149 | case CONST_VECTOR: |
7150 | { | |
7151 | int i; | |
7152 | ||
7153 | fprintf (f, "<"); | |
7154 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
7155 | { | |
7156 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
7157 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
7158 | fputc (',', f); | |
7159 | } | |
7160 | fprintf (f, ">"); | |
7161 | } | |
7162 | return; | |
7163 | ||
d5b7b3ae RE |
7164 | case CONST_STRING: |
7165 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
7166 | return; | |
7167 | ||
7168 | case SYMBOL_REF: | |
7169 | fprintf (f, "`%s'", XSTR (x, 0)); | |
7170 | return; | |
7171 | ||
7172 | case LABEL_REF: | |
7173 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
7174 | return; | |
7175 | ||
7176 | case CONST: | |
7177 | arm_print_value (f, XEXP (x, 0)); | |
7178 | return; | |
7179 | ||
7180 | case PLUS: | |
7181 | arm_print_value (f, XEXP (x, 0)); | |
7182 | fprintf (f, "+"); | |
7183 | arm_print_value (f, XEXP (x, 1)); | |
7184 | return; | |
7185 | ||
7186 | case PC: | |
7187 | fprintf (f, "pc"); | |
7188 | return; | |
7189 | ||
7190 | default: | |
7191 | fprintf (f, "????"); | |
7192 | return; | |
7193 | } | |
7194 | } | |
7195 | \f | |
2b835d68 | 7196 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 7197 | |
949d79eb RE |
7198 | /* Arm instructions cannot load a large constant directly into a |
7199 | register; they have to come from a pc relative load. The constant | |
7200 | must therefore be placed in the addressable range of the pc | |
7201 | relative load. Depending on the precise pc relative load | |
7202 | instruction the range is somewhere between 256 bytes and 4k. This | |
7203 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
7204 | generate code to branch around it. |
7205 | ||
949d79eb RE |
7206 | It is important to minimize this, since the branches will slow |
7207 | things down and make the code larger. | |
2b835d68 | 7208 | |
949d79eb RE |
7209 | Normally we can hide the table after an existing unconditional |
7210 | branch so that there is no interruption of the flow, but in the | |
7211 | worst case the code looks like this: | |
2b835d68 RE |
7212 | |
7213 | ldr rn, L1 | |
949d79eb | 7214 | ... |
2b835d68 RE |
7215 | b L2 |
7216 | align | |
7217 | L1: .long value | |
7218 | L2: | |
949d79eb | 7219 | ... |
2b835d68 | 7220 | |
2b835d68 | 7221 | ldr rn, L3 |
949d79eb | 7222 | ... |
2b835d68 RE |
7223 | b L4 |
7224 | align | |
2b835d68 RE |
7225 | L3: .long value |
7226 | L4: | |
949d79eb RE |
7227 | ... |
7228 | ||
7229 | We fix this by performing a scan after scheduling, which notices | |
7230 | which instructions need to have their operands fetched from the | |
7231 | constant table and builds the table. | |
7232 | ||
7233 | The algorithm starts by building a table of all the constants that | |
7234 | need fixing up and all the natural barriers in the function (places | |
7235 | where a constant table can be dropped without breaking the flow). | |
7236 | For each fixup we note how far the pc-relative replacement will be | |
7237 | able to reach and the offset of the instruction into the function. | |
7238 | ||
7239 | Having built the table we then group the fixes together to form | |
7240 | tables that are as large as possible (subject to addressing | |
7241 | constraints) and emit each table of constants after the last | |
7242 | barrier that is within range of all the instructions in the group. | |
7243 | If a group does not contain a barrier, then we forcibly create one | |
7244 | by inserting a jump instruction into the flow. Once the table has | |
7245 | been inserted, the insns are then modified to reference the | |
7246 | relevant entry in the pool. | |
7247 | ||
6354dc9b | 7248 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 7249 | |
d5b7b3ae | 7250 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
7251 | aligning the pools to the start of cache lines; this alignment |
7252 | would need to be taken into account when calculating addressability | |
6354dc9b | 7253 | of a pool. */ |
2b835d68 | 7254 | |
d5b7b3ae RE |
7255 | /* These typedefs are located at the start of this file, so that |
7256 | they can be used in the prototypes there. This comment is to | |
7257 | remind readers of that fact so that the following structures | |
7258 | can be understood more easily. | |
7259 | ||
7260 | typedef struct minipool_node Mnode; | |
7261 | typedef struct minipool_fixup Mfix; */ | |
7262 | ||
7263 | struct minipool_node | |
7264 | { | |
7265 | /* Doubly linked chain of entries. */ | |
7266 | Mnode * next; | |
7267 | Mnode * prev; | |
7268 | /* The maximum offset into the code that this entry can be placed. While | |
7269 | pushing fixes for forward references, all entries are sorted in order | |
7270 | of increasing max_address. */ | |
7271 | HOST_WIDE_INT max_address; | |
5519a4f9 | 7272 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
7273 | HOST_WIDE_INT min_address; |
7274 | /* The number of fixes referencing this entry. This can become zero | |
7275 | if we "unpush" an entry. In this case we ignore the entry when we | |
7276 | come to emit the code. */ | |
7277 | int refcount; | |
7278 | /* The offset from the start of the minipool. */ | |
7279 | HOST_WIDE_INT offset; | |
7280 | /* The value in table. */ | |
7281 | rtx value; | |
7282 | /* The mode of value. */ | |
7283 | enum machine_mode mode; | |
5a9335ef NC |
7284 | /* The size of the value. With iWMMXt enabled |
7285 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
7286 | int fix_size; |
7287 | }; | |
7288 | ||
7289 | struct minipool_fixup | |
2b835d68 | 7290 | { |
d5b7b3ae RE |
7291 | Mfix * next; |
7292 | rtx insn; | |
7293 | HOST_WIDE_INT address; | |
7294 | rtx * loc; | |
7295 | enum machine_mode mode; | |
7296 | int fix_size; | |
7297 | rtx value; | |
7298 | Mnode * minipool; | |
7299 | HOST_WIDE_INT forwards; | |
7300 | HOST_WIDE_INT backwards; | |
7301 | }; | |
2b835d68 | 7302 | |
d5b7b3ae RE |
7303 | /* Fixes less than a word need padding out to a word boundary. */ |
7304 | #define MINIPOOL_FIX_SIZE(mode) \ | |
7305 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 7306 | |
d5b7b3ae RE |
7307 | static Mnode * minipool_vector_head; |
7308 | static Mnode * minipool_vector_tail; | |
7309 | static rtx minipool_vector_label; | |
332072db | 7310 | |
d5b7b3ae RE |
7311 | /* The linked list of all minipool fixes required for this function. */ |
7312 | Mfix * minipool_fix_head; | |
7313 | Mfix * minipool_fix_tail; | |
7314 | /* The fix entry for the current minipool, once it has been placed. */ | |
7315 | Mfix * minipool_barrier; | |
7316 | ||
7317 | /* Determines if INSN is the start of a jump table. Returns the end | |
7318 | of the TABLE or NULL_RTX. */ | |
7319 | static rtx | |
e32bac5b | 7320 | is_jump_table (rtx insn) |
2b835d68 | 7321 | { |
d5b7b3ae | 7322 | rtx table; |
f676971a | 7323 | |
d5b7b3ae RE |
7324 | if (GET_CODE (insn) == JUMP_INSN |
7325 | && JUMP_LABEL (insn) != NULL | |
7326 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
7327 | == next_real_insn (insn)) | |
7328 | && table != NULL | |
7329 | && GET_CODE (table) == JUMP_INSN | |
7330 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
7331 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
7332 | return table; | |
7333 | ||
7334 | return NULL_RTX; | |
2b835d68 RE |
7335 | } |
7336 | ||
657d9449 RE |
7337 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
7338 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
7339 | #endif | |
7340 | ||
d5b7b3ae | 7341 | static HOST_WIDE_INT |
e32bac5b | 7342 | get_jump_table_size (rtx insn) |
2b835d68 | 7343 | { |
657d9449 RE |
7344 | /* ADDR_VECs only take room if read-only data does into the text |
7345 | section. */ | |
d6b5193b | 7346 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
7347 | { |
7348 | rtx body = PATTERN (insn); | |
7349 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
2b835d68 | 7350 | |
657d9449 RE |
7351 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); |
7352 | } | |
7353 | ||
7354 | return 0; | |
d5b7b3ae | 7355 | } |
2b835d68 | 7356 | |
d5b7b3ae RE |
7357 | /* Move a minipool fix MP from its current location to before MAX_MP. |
7358 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 7359 | constraints may need updating. */ |
d5b7b3ae | 7360 | static Mnode * |
e32bac5b RE |
7361 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
7362 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 7363 | { |
e6d29d15 NS |
7364 | /* The code below assumes these are different. */ |
7365 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
7366 | |
7367 | if (max_mp == NULL) | |
7368 | { | |
7369 | if (max_address < mp->max_address) | |
7370 | mp->max_address = max_address; | |
7371 | } | |
7372 | else | |
2b835d68 | 7373 | { |
d5b7b3ae RE |
7374 | if (max_address > max_mp->max_address - mp->fix_size) |
7375 | mp->max_address = max_mp->max_address - mp->fix_size; | |
7376 | else | |
7377 | mp->max_address = max_address; | |
2b835d68 | 7378 | |
d5b7b3ae RE |
7379 | /* Unlink MP from its current position. Since max_mp is non-null, |
7380 | mp->prev must be non-null. */ | |
7381 | mp->prev->next = mp->next; | |
7382 | if (mp->next != NULL) | |
7383 | mp->next->prev = mp->prev; | |
7384 | else | |
7385 | minipool_vector_tail = mp->prev; | |
2b835d68 | 7386 | |
d5b7b3ae RE |
7387 | /* Re-insert it before MAX_MP. */ |
7388 | mp->next = max_mp; | |
7389 | mp->prev = max_mp->prev; | |
7390 | max_mp->prev = mp; | |
f676971a | 7391 | |
d5b7b3ae RE |
7392 | if (mp->prev != NULL) |
7393 | mp->prev->next = mp; | |
7394 | else | |
7395 | minipool_vector_head = mp; | |
7396 | } | |
2b835d68 | 7397 | |
d5b7b3ae RE |
7398 | /* Save the new entry. */ |
7399 | max_mp = mp; | |
7400 | ||
d6a7951f | 7401 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
7402 | required. */ |
7403 | while (mp->prev != NULL | |
7404 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
7405 | { | |
7406 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
7407 | mp = mp->prev; | |
2b835d68 RE |
7408 | } |
7409 | ||
d5b7b3ae | 7410 | return max_mp; |
2b835d68 RE |
7411 | } |
7412 | ||
d5b7b3ae RE |
7413 | /* Add a constant to the minipool for a forward reference. Returns the |
7414 | node added or NULL if the constant will not fit in this pool. */ | |
7415 | static Mnode * | |
e32bac5b | 7416 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
7417 | { |
7418 | /* If set, max_mp is the first pool_entry that has a lower | |
7419 | constraint than the one we are trying to add. */ | |
7420 | Mnode * max_mp = NULL; | |
7421 | HOST_WIDE_INT max_address = fix->address + fix->forwards; | |
7422 | Mnode * mp; | |
f676971a | 7423 | |
d5b7b3ae RE |
7424 | /* If this fix's address is greater than the address of the first |
7425 | entry, then we can't put the fix in this pool. We subtract the | |
7426 | size of the current fix to ensure that if the table is fully | |
0fa2e4df | 7427 | packed we still have enough room to insert this value by shuffling |
d5b7b3ae RE |
7428 | the other fixes forwards. */ |
7429 | if (minipool_vector_head && | |
7430 | fix->address >= minipool_vector_head->max_address - fix->fix_size) | |
7431 | return NULL; | |
2b835d68 | 7432 | |
d5b7b3ae RE |
7433 | /* Scan the pool to see if a constant with the same value has |
7434 | already been added. While we are doing this, also note the | |
7435 | location where we must insert the constant if it doesn't already | |
7436 | exist. */ | |
7437 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
7438 | { | |
7439 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
7440 | && fix->mode == mp->mode | |
7441 | && (GET_CODE (fix->value) != CODE_LABEL | |
7442 | || (CODE_LABEL_NUMBER (fix->value) | |
7443 | == CODE_LABEL_NUMBER (mp->value))) | |
7444 | && rtx_equal_p (fix->value, mp->value)) | |
7445 | { | |
7446 | /* More than one fix references this entry. */ | |
7447 | mp->refcount++; | |
7448 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
7449 | } | |
7450 | ||
7451 | /* Note the insertion point if necessary. */ | |
7452 | if (max_mp == NULL | |
7453 | && mp->max_address > max_address) | |
7454 | max_mp = mp; | |
5a9335ef NC |
7455 | |
7456 | /* If we are inserting an 8-bytes aligned quantity and | |
7457 | we have not already found an insertion point, then | |
7458 | make sure that all such 8-byte aligned quantities are | |
7459 | placed at the start of the pool. */ | |
5848830f | 7460 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef NC |
7461 | && max_mp == NULL |
7462 | && fix->fix_size == 8 | |
7463 | && mp->fix_size != 8) | |
7464 | { | |
7465 | max_mp = mp; | |
7466 | max_address = mp->max_address; | |
7467 | } | |
d5b7b3ae RE |
7468 | } |
7469 | ||
7470 | /* The value is not currently in the minipool, so we need to create | |
7471 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
7472 | the end of the list since the placement is less constrained than | |
7473 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 7474 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae RE |
7475 | entries. */ |
7476 | mp = xmalloc (sizeof (* mp)); | |
7477 | mp->fix_size = fix->fix_size; | |
7478 | mp->mode = fix->mode; | |
7479 | mp->value = fix->value; | |
7480 | mp->refcount = 1; | |
7481 | /* Not yet required for a backwards ref. */ | |
7482 | mp->min_address = -65536; | |
7483 | ||
7484 | if (max_mp == NULL) | |
7485 | { | |
7486 | mp->max_address = max_address; | |
7487 | mp->next = NULL; | |
7488 | mp->prev = minipool_vector_tail; | |
7489 | ||
7490 | if (mp->prev == NULL) | |
7491 | { | |
7492 | minipool_vector_head = mp; | |
7493 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 7494 | } |
2b835d68 | 7495 | else |
d5b7b3ae | 7496 | mp->prev->next = mp; |
2b835d68 | 7497 | |
d5b7b3ae RE |
7498 | minipool_vector_tail = mp; |
7499 | } | |
7500 | else | |
7501 | { | |
7502 | if (max_address > max_mp->max_address - mp->fix_size) | |
7503 | mp->max_address = max_mp->max_address - mp->fix_size; | |
7504 | else | |
7505 | mp->max_address = max_address; | |
7506 | ||
7507 | mp->next = max_mp; | |
7508 | mp->prev = max_mp->prev; | |
7509 | max_mp->prev = mp; | |
7510 | if (mp->prev != NULL) | |
7511 | mp->prev->next = mp; | |
7512 | else | |
7513 | minipool_vector_head = mp; | |
7514 | } | |
7515 | ||
7516 | /* Save the new entry. */ | |
7517 | max_mp = mp; | |
7518 | ||
d6a7951f | 7519 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
7520 | required. */ |
7521 | while (mp->prev != NULL | |
7522 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
7523 | { | |
7524 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
7525 | mp = mp->prev; | |
2b835d68 RE |
7526 | } |
7527 | ||
d5b7b3ae RE |
7528 | return max_mp; |
7529 | } | |
7530 | ||
7531 | static Mnode * | |
e32bac5b RE |
7532 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
7533 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
7534 | { |
7535 | HOST_WIDE_INT offset; | |
7536 | ||
e6d29d15 NS |
7537 | /* The code below assumes these are different. */ |
7538 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
7539 | |
7540 | if (min_mp == NULL) | |
2b835d68 | 7541 | { |
d5b7b3ae RE |
7542 | if (min_address > mp->min_address) |
7543 | mp->min_address = min_address; | |
7544 | } | |
7545 | else | |
7546 | { | |
7547 | /* We will adjust this below if it is too loose. */ | |
7548 | mp->min_address = min_address; | |
7549 | ||
7550 | /* Unlink MP from its current position. Since min_mp is non-null, | |
7551 | mp->next must be non-null. */ | |
7552 | mp->next->prev = mp->prev; | |
7553 | if (mp->prev != NULL) | |
7554 | mp->prev->next = mp->next; | |
7555 | else | |
7556 | minipool_vector_head = mp->next; | |
7557 | ||
7558 | /* Reinsert it after MIN_MP. */ | |
7559 | mp->prev = min_mp; | |
7560 | mp->next = min_mp->next; | |
7561 | min_mp->next = mp; | |
7562 | if (mp->next != NULL) | |
7563 | mp->next->prev = mp; | |
2b835d68 | 7564 | else |
d5b7b3ae RE |
7565 | minipool_vector_tail = mp; |
7566 | } | |
7567 | ||
7568 | min_mp = mp; | |
7569 | ||
7570 | offset = 0; | |
7571 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
7572 | { | |
7573 | mp->offset = offset; | |
7574 | if (mp->refcount > 0) | |
7575 | offset += mp->fix_size; | |
7576 | ||
7577 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
7578 | mp->next->min_address = mp->min_address + mp->fix_size; | |
7579 | } | |
7580 | ||
7581 | return min_mp; | |
f676971a | 7582 | } |
d5b7b3ae RE |
7583 | |
7584 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 7585 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
7586 | |
7587 | Note that the code for insertion for a backwards reference can be | |
7588 | somewhat confusing because the calculated offsets for each fix do | |
7589 | not take into account the size of the pool (which is still under | |
7590 | construction. */ | |
7591 | static Mnode * | |
e32bac5b | 7592 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
7593 | { |
7594 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
7595 | than the one we are trying to add. */ | |
e32bac5b | 7596 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
7597 | /* This can be negative, since it is only a constraint. */ |
7598 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 7599 | Mnode *mp; |
d5b7b3ae RE |
7600 | |
7601 | /* If we can't reach the current pool from this insn, or if we can't | |
7602 | insert this entry at the end of the pool without pushing other | |
7603 | fixes out of range, then we don't try. This ensures that we | |
7604 | can't fail later on. */ | |
7605 | if (min_address >= minipool_barrier->address | |
7606 | || (minipool_vector_tail->min_address + fix->fix_size | |
7607 | >= minipool_barrier->address)) | |
7608 | return NULL; | |
7609 | ||
7610 | /* Scan the pool to see if a constant with the same value has | |
7611 | already been added. While we are doing this, also note the | |
7612 | location where we must insert the constant if it doesn't already | |
7613 | exist. */ | |
7614 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
7615 | { | |
7616 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
7617 | && fix->mode == mp->mode | |
7618 | && (GET_CODE (fix->value) != CODE_LABEL | |
7619 | || (CODE_LABEL_NUMBER (fix->value) | |
7620 | == CODE_LABEL_NUMBER (mp->value))) | |
7621 | && rtx_equal_p (fix->value, mp->value) | |
7622 | /* Check that there is enough slack to move this entry to the | |
7623 | end of the table (this is conservative). */ | |
f676971a EC |
7624 | && (mp->max_address |
7625 | > (minipool_barrier->address | |
d5b7b3ae RE |
7626 | + minipool_vector_tail->offset |
7627 | + minipool_vector_tail->fix_size))) | |
7628 | { | |
7629 | mp->refcount++; | |
7630 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
7631 | } | |
7632 | ||
7633 | if (min_mp != NULL) | |
7634 | mp->min_address += fix->fix_size; | |
7635 | else | |
7636 | { | |
7637 | /* Note the insertion point if necessary. */ | |
7638 | if (mp->min_address < min_address) | |
5a9335ef NC |
7639 | { |
7640 | /* For now, we do not allow the insertion of 8-byte alignment | |
7641 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f PB |
7642 | if (ARM_DOUBLEWORD_ALIGN |
7643 | && fix->fix_size == 8 && mp->fix_size != 8) | |
5a9335ef NC |
7644 | return NULL; |
7645 | else | |
7646 | min_mp = mp; | |
7647 | } | |
d5b7b3ae RE |
7648 | else if (mp->max_address |
7649 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
7650 | { | |
7651 | /* Inserting before this entry would push the fix beyond | |
7652 | its maximum address (which can happen if we have | |
7653 | re-located a forwards fix); force the new fix to come | |
7654 | after it. */ | |
7655 | min_mp = mp; | |
7656 | min_address = mp->min_address + fix->fix_size; | |
7657 | } | |
5a9335ef NC |
7658 | /* If we are inserting an 8-bytes aligned quantity and |
7659 | we have not already found an insertion point, then | |
7660 | make sure that all such 8-byte aligned quantities are | |
7661 | placed at the start of the pool. */ | |
5848830f | 7662 | else if (ARM_DOUBLEWORD_ALIGN |
5a9335ef NC |
7663 | && min_mp == NULL |
7664 | && fix->fix_size == 8 | |
7665 | && mp->fix_size < 8) | |
7666 | { | |
7667 | min_mp = mp; | |
7668 | min_address = mp->min_address + fix->fix_size; | |
7669 | } | |
d5b7b3ae RE |
7670 | } |
7671 | } | |
7672 | ||
7673 | /* We need to create a new entry. */ | |
7674 | mp = xmalloc (sizeof (* mp)); | |
7675 | mp->fix_size = fix->fix_size; | |
7676 | mp->mode = fix->mode; | |
7677 | mp->value = fix->value; | |
7678 | mp->refcount = 1; | |
7679 | mp->max_address = minipool_barrier->address + 65536; | |
7680 | ||
7681 | mp->min_address = min_address; | |
7682 | ||
7683 | if (min_mp == NULL) | |
7684 | { | |
7685 | mp->prev = NULL; | |
7686 | mp->next = minipool_vector_head; | |
7687 | ||
7688 | if (mp->next == NULL) | |
7689 | { | |
7690 | minipool_vector_tail = mp; | |
7691 | minipool_vector_label = gen_label_rtx (); | |
7692 | } | |
7693 | else | |
7694 | mp->next->prev = mp; | |
7695 | ||
7696 | minipool_vector_head = mp; | |
7697 | } | |
7698 | else | |
7699 | { | |
7700 | mp->next = min_mp->next; | |
7701 | mp->prev = min_mp; | |
7702 | min_mp->next = mp; | |
f676971a | 7703 | |
d5b7b3ae RE |
7704 | if (mp->next != NULL) |
7705 | mp->next->prev = mp; | |
7706 | else | |
7707 | minipool_vector_tail = mp; | |
7708 | } | |
7709 | ||
7710 | /* Save the new entry. */ | |
7711 | min_mp = mp; | |
7712 | ||
7713 | if (mp->prev) | |
7714 | mp = mp->prev; | |
7715 | else | |
7716 | mp->offset = 0; | |
7717 | ||
7718 | /* Scan over the following entries and adjust their offsets. */ | |
7719 | while (mp->next != NULL) | |
7720 | { | |
7721 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
7722 | mp->next->min_address = mp->min_address + mp->fix_size; | |
7723 | ||
7724 | if (mp->refcount) | |
7725 | mp->next->offset = mp->offset + mp->fix_size; | |
7726 | else | |
7727 | mp->next->offset = mp->offset; | |
7728 | ||
7729 | mp = mp->next; | |
7730 | } | |
7731 | ||
7732 | return min_mp; | |
7733 | } | |
7734 | ||
7735 | static void | |
e32bac5b | 7736 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
7737 | { |
7738 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 7739 | Mnode *mp; |
d5b7b3ae RE |
7740 | |
7741 | minipool_barrier = barrier; | |
7742 | ||
7743 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
7744 | { | |
7745 | mp->offset = offset; | |
f676971a | 7746 | |
d5b7b3ae RE |
7747 | if (mp->refcount > 0) |
7748 | offset += mp->fix_size; | |
7749 | } | |
7750 | } | |
7751 | ||
7752 | /* Output the literal table */ | |
7753 | static void | |
e32bac5b | 7754 | dump_minipool (rtx scan) |
d5b7b3ae | 7755 | { |
5a9335ef NC |
7756 | Mnode * mp; |
7757 | Mnode * nmp; | |
7758 | int align64 = 0; | |
7759 | ||
5848830f | 7760 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef NC |
7761 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
7762 | if (mp->refcount > 0 && mp->fix_size == 8) | |
7763 | { | |
7764 | align64 = 1; | |
7765 | break; | |
7766 | } | |
d5b7b3ae | 7767 | |
c263766c RH |
7768 | if (dump_file) |
7769 | fprintf (dump_file, | |
5a9335ef NC |
7770 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
7771 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
7772 | |
7773 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 7774 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
7775 | scan = emit_label_after (minipool_vector_label, scan); |
7776 | ||
7777 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
7778 | { | |
7779 | if (mp->refcount > 0) | |
7780 | { | |
c263766c | 7781 | if (dump_file) |
d5b7b3ae | 7782 | { |
f676971a | 7783 | fprintf (dump_file, |
d5b7b3ae RE |
7784 | ";; Offset %u, min %ld, max %ld ", |
7785 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
7786 | (unsigned long) mp->max_address); | |
c263766c RH |
7787 | arm_print_value (dump_file, mp->value); |
7788 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
7789 | } |
7790 | ||
7791 | switch (mp->fix_size) | |
7792 | { | |
7793 | #ifdef HAVE_consttable_1 | |
7794 | case 1: | |
7795 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
7796 | break; | |
7797 | ||
7798 | #endif | |
7799 | #ifdef HAVE_consttable_2 | |
7800 | case 2: | |
7801 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
7802 | break; | |
7803 | ||
7804 | #endif | |
7805 | #ifdef HAVE_consttable_4 | |
7806 | case 4: | |
7807 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
7808 | break; | |
7809 | ||
7810 | #endif | |
7811 | #ifdef HAVE_consttable_8 | |
7812 | case 8: | |
7813 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
7814 | break; | |
7815 | ||
7816 | #endif | |
7817 | default: | |
e6d29d15 | 7818 | gcc_unreachable (); |
d5b7b3ae RE |
7819 | } |
7820 | } | |
7821 | ||
7822 | nmp = mp->next; | |
7823 | free (mp); | |
2b835d68 RE |
7824 | } |
7825 | ||
d5b7b3ae RE |
7826 | minipool_vector_head = minipool_vector_tail = NULL; |
7827 | scan = emit_insn_after (gen_consttable_end (), scan); | |
7828 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
7829 | } |
7830 | ||
d5b7b3ae RE |
7831 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
7832 | static int | |
e32bac5b | 7833 | arm_barrier_cost (rtx insn) |
949d79eb | 7834 | { |
d5b7b3ae RE |
7835 | /* Basing the location of the pool on the loop depth is preferable, |
7836 | but at the moment, the basic block information seems to be | |
7837 | corrupt by this stage of the compilation. */ | |
7838 | int base_cost = 50; | |
7839 | rtx next = next_nonnote_insn (insn); | |
7840 | ||
7841 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
7842 | base_cost -= 20; | |
7843 | ||
7844 | switch (GET_CODE (insn)) | |
7845 | { | |
7846 | case CODE_LABEL: | |
7847 | /* It will always be better to place the table before the label, rather | |
7848 | than after it. */ | |
f676971a | 7849 | return 50; |
949d79eb | 7850 | |
d5b7b3ae RE |
7851 | case INSN: |
7852 | case CALL_INSN: | |
7853 | return base_cost; | |
7854 | ||
7855 | case JUMP_INSN: | |
7856 | return base_cost - 10; | |
7857 | ||
7858 | default: | |
7859 | return base_cost + 10; | |
7860 | } | |
7861 | } | |
7862 | ||
7863 | /* Find the best place in the insn stream in the range | |
7864 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
7865 | Create the barrier by inserting a jump and add a new fix entry for | |
7866 | it. */ | |
7867 | static Mfix * | |
e32bac5b | 7868 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
7869 | { |
7870 | HOST_WIDE_INT count = 0; | |
7871 | rtx barrier; | |
7872 | rtx from = fix->insn; | |
7873 | rtx selected = from; | |
7874 | int selected_cost; | |
7875 | HOST_WIDE_INT selected_address; | |
7876 | Mfix * new_fix; | |
7877 | HOST_WIDE_INT max_count = max_address - fix->address; | |
7878 | rtx label = gen_label_rtx (); | |
7879 | ||
7880 | selected_cost = arm_barrier_cost (from); | |
7881 | selected_address = fix->address; | |
7882 | ||
7883 | while (from && count < max_count) | |
7884 | { | |
7885 | rtx tmp; | |
7886 | int new_cost; | |
7887 | ||
7888 | /* This code shouldn't have been called if there was a natural barrier | |
7889 | within range. */ | |
e6d29d15 | 7890 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
7891 | |
7892 | /* Count the length of this insn. */ | |
7893 | count += get_attr_length (from); | |
7894 | ||
7895 | /* If there is a jump table, add its length. */ | |
7896 | tmp = is_jump_table (from); | |
7897 | if (tmp != NULL) | |
7898 | { | |
7899 | count += get_jump_table_size (tmp); | |
7900 | ||
7901 | /* Jump tables aren't in a basic block, so base the cost on | |
7902 | the dispatch insn. If we select this location, we will | |
7903 | still put the pool after the table. */ | |
7904 | new_cost = arm_barrier_cost (from); | |
7905 | ||
7906 | if (count < max_count && new_cost <= selected_cost) | |
7907 | { | |
7908 | selected = tmp; | |
7909 | selected_cost = new_cost; | |
7910 | selected_address = fix->address + count; | |
7911 | } | |
7912 | ||
7913 | /* Continue after the dispatch table. */ | |
7914 | from = NEXT_INSN (tmp); | |
7915 | continue; | |
7916 | } | |
7917 | ||
7918 | new_cost = arm_barrier_cost (from); | |
f676971a | 7919 | |
d5b7b3ae RE |
7920 | if (count < max_count && new_cost <= selected_cost) |
7921 | { | |
7922 | selected = from; | |
7923 | selected_cost = new_cost; | |
7924 | selected_address = fix->address + count; | |
7925 | } | |
7926 | ||
7927 | from = NEXT_INSN (from); | |
7928 | } | |
7929 | ||
7930 | /* Create a new JUMP_INSN that branches around a barrier. */ | |
7931 | from = emit_jump_insn_after (gen_jump (label), selected); | |
7932 | JUMP_LABEL (from) = label; | |
7933 | barrier = emit_barrier_after (from); | |
7934 | emit_label_after (label, barrier); | |
7935 | ||
7936 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 7937 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
7938 | new_fix->insn = barrier; |
7939 | new_fix->address = selected_address; | |
7940 | new_fix->next = fix->next; | |
7941 | fix->next = new_fix; | |
7942 | ||
7943 | return new_fix; | |
7944 | } | |
7945 | ||
7946 | /* Record that there is a natural barrier in the insn stream at | |
7947 | ADDRESS. */ | |
949d79eb | 7948 | static void |
e32bac5b | 7949 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 7950 | { |
c7319d87 | 7951 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 7952 | |
949d79eb RE |
7953 | fix->insn = insn; |
7954 | fix->address = address; | |
2b835d68 | 7955 | |
949d79eb RE |
7956 | fix->next = NULL; |
7957 | if (minipool_fix_head != NULL) | |
7958 | minipool_fix_tail->next = fix; | |
7959 | else | |
7960 | minipool_fix_head = fix; | |
7961 | ||
7962 | minipool_fix_tail = fix; | |
7963 | } | |
2b835d68 | 7964 | |
d5b7b3ae RE |
7965 | /* Record INSN, which will need fixing up to load a value from the |
7966 | minipool. ADDRESS is the offset of the insn since the start of the | |
7967 | function; LOC is a pointer to the part of the insn which requires | |
7968 | fixing; VALUE is the constant that must be loaded, which is of type | |
7969 | MODE. */ | |
949d79eb | 7970 | static void |
e32bac5b RE |
7971 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
7972 | enum machine_mode mode, rtx value) | |
949d79eb | 7973 | { |
c7319d87 | 7974 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb RE |
7975 | |
7976 | #ifdef AOF_ASSEMBLER | |
093354e0 | 7977 | /* PIC symbol references need to be converted into offsets into the |
949d79eb | 7978 | based area. */ |
d5b7b3ae RE |
7979 | /* XXX This shouldn't be done here. */ |
7980 | if (flag_pic && GET_CODE (value) == SYMBOL_REF) | |
949d79eb RE |
7981 | value = aof_pic_entry (value); |
7982 | #endif /* AOF_ASSEMBLER */ | |
7983 | ||
7984 | fix->insn = insn; | |
7985 | fix->address = address; | |
7986 | fix->loc = loc; | |
7987 | fix->mode = mode; | |
d5b7b3ae | 7988 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 7989 | fix->value = value; |
d5b7b3ae RE |
7990 | fix->forwards = get_attr_pool_range (insn); |
7991 | fix->backwards = get_attr_neg_pool_range (insn); | |
7992 | fix->minipool = NULL; | |
949d79eb RE |
7993 | |
7994 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 7995 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 7996 | to generate duff assembly code. */ |
e6d29d15 | 7997 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 7998 | |
5848830f | 7999 | /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary. |
5a9335ef NC |
8000 | So there might be an empty word before the start of the pool. |
8001 | Hence we reduce the forward range by 4 to allow for this | |
8002 | possibility. */ | |
5848830f | 8003 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8) |
5a9335ef NC |
8004 | fix->forwards -= 4; |
8005 | ||
c263766c | 8006 | if (dump_file) |
d5b7b3ae | 8007 | { |
c263766c | 8008 | fprintf (dump_file, |
d5b7b3ae RE |
8009 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
8010 | GET_MODE_NAME (mode), | |
f676971a | 8011 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 8012 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
8013 | arm_print_value (dump_file, fix->value); |
8014 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
8015 | } |
8016 | ||
6354dc9b | 8017 | /* Add it to the chain of fixes. */ |
949d79eb | 8018 | fix->next = NULL; |
f676971a | 8019 | |
949d79eb RE |
8020 | if (minipool_fix_head != NULL) |
8021 | minipool_fix_tail->next = fix; | |
8022 | else | |
8023 | minipool_fix_head = fix; | |
8024 | ||
8025 | minipool_fix_tail = fix; | |
8026 | } | |
8027 | ||
9b901d50 | 8028 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
8029 | Returns the number of insns needed, or 99 if we don't know how to |
8030 | do it. */ | |
8031 | int | |
8032 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 8033 | { |
9b901d50 RE |
8034 | rtx lowpart, highpart; |
8035 | enum machine_mode mode; | |
e0b92319 | 8036 | |
9b901d50 | 8037 | mode = GET_MODE (val); |
b9e8bfda | 8038 | |
9b901d50 RE |
8039 | if (mode == VOIDmode) |
8040 | mode = DImode; | |
8041 | ||
8042 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 8043 | |
9b901d50 RE |
8044 | lowpart = gen_lowpart (SImode, val); |
8045 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 8046 | |
9b901d50 RE |
8047 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
8048 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
8049 | ||
8050 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 8051 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 8052 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
8053 | NULL_RTX, NULL_RTX, 0, 0)); |
8054 | } | |
8055 | ||
f3b569ca | 8056 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
8057 | 32-bit operations. This is the case if optimizing for size, or |
8058 | if we have load delay slots, or if one 32-bit part can be done with | |
8059 | a single data operation. */ | |
8060 | bool | |
8061 | arm_const_double_by_parts (rtx val) | |
8062 | { | |
8063 | enum machine_mode mode = GET_MODE (val); | |
8064 | rtx part; | |
8065 | ||
8066 | if (optimize_size || arm_ld_sched) | |
8067 | return true; | |
8068 | ||
8069 | if (mode == VOIDmode) | |
8070 | mode = DImode; | |
e0b92319 | 8071 | |
b4a58f80 | 8072 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 8073 | |
b4a58f80 | 8074 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 8075 | |
b4a58f80 RE |
8076 | if (const_ok_for_arm (INTVAL (part)) |
8077 | || const_ok_for_arm (~INTVAL (part))) | |
8078 | return true; | |
e0b92319 | 8079 | |
b4a58f80 | 8080 | part = gen_lowpart (SImode, val); |
e0b92319 | 8081 | |
b4a58f80 | 8082 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 8083 | |
b4a58f80 RE |
8084 | if (const_ok_for_arm (INTVAL (part)) |
8085 | || const_ok_for_arm (~INTVAL (part))) | |
8086 | return true; | |
e0b92319 | 8087 | |
b4a58f80 RE |
8088 | return false; |
8089 | } | |
8090 | ||
f0375c66 NC |
8091 | /* Scan INSN and note any of its operands that need fixing. |
8092 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 8093 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
8094 | This is used by arm_memory_load_p() which needs to know about loads |
8095 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 8096 | static bool |
e32bac5b | 8097 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 8098 | { |
f0375c66 | 8099 | bool result = false; |
949d79eb RE |
8100 | int opno; |
8101 | ||
d5b7b3ae | 8102 | extract_insn (insn); |
949d79eb | 8103 | |
5895f793 | 8104 | if (!constrain_operands (1)) |
949d79eb RE |
8105 | fatal_insn_not_found (insn); |
8106 | ||
8c2a5582 RE |
8107 | if (recog_data.n_alternatives == 0) |
8108 | return false; | |
8109 | ||
9b901d50 RE |
8110 | /* Fill in recog_op_alt with information about the constraints of |
8111 | this insn. */ | |
949d79eb RE |
8112 | preprocess_constraints (); |
8113 | ||
1ccbefce | 8114 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 8115 | { |
6354dc9b | 8116 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 8117 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
8118 | continue; |
8119 | ||
8120 | /* If this alternative is a memory reference, then any mention | |
8121 | of constants in this alternative is really to fool reload | |
8122 | into allowing us to accept one there. We need to fix them up | |
8123 | now so that we output the right code. */ | |
8124 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
8125 | { | |
1ccbefce | 8126 | rtx op = recog_data.operand[opno]; |
949d79eb | 8127 | |
9b901d50 | 8128 | if (CONSTANT_P (op)) |
f0375c66 NC |
8129 | { |
8130 | if (do_pushes) | |
8131 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
8132 | recog_data.operand_mode[opno], op); | |
8133 | result = true; | |
8134 | } | |
d5b7b3ae | 8135 | else if (GET_CODE (op) == MEM |
949d79eb RE |
8136 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
8137 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
8138 | { |
8139 | if (do_pushes) | |
244b1afb RE |
8140 | { |
8141 | rtx cop = avoid_constant_pool_reference (op); | |
8142 | ||
8143 | /* Casting the address of something to a mode narrower | |
8144 | than a word can cause avoid_constant_pool_reference() | |
8145 | to return the pool reference itself. That's no good to | |
f676971a | 8146 | us here. Lets just hope that we can use the |
244b1afb RE |
8147 | constant pool value directly. */ |
8148 | if (op == cop) | |
c769a35d | 8149 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
8150 | |
8151 | push_minipool_fix (insn, address, | |
8152 | recog_data.operand_loc[opno], | |
c769a35d | 8153 | recog_data.operand_mode[opno], cop); |
244b1afb | 8154 | } |
f0375c66 NC |
8155 | |
8156 | result = true; | |
8157 | } | |
949d79eb | 8158 | } |
2b835d68 | 8159 | } |
f0375c66 NC |
8160 | |
8161 | return result; | |
2b835d68 RE |
8162 | } |
8163 | ||
18dbd950 RS |
8164 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
8165 | load addresses a limited distance around the pc. We do some | |
8166 | special munging to move the constant pool values to the correct | |
8167 | point in the code. */ | |
18dbd950 | 8168 | static void |
e32bac5b | 8169 | arm_reorg (void) |
2b835d68 RE |
8170 | { |
8171 | rtx insn; | |
d5b7b3ae RE |
8172 | HOST_WIDE_INT address = 0; |
8173 | Mfix * fix; | |
ad076f4e | 8174 | |
949d79eb | 8175 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 8176 | |
949d79eb RE |
8177 | /* The first insn must always be a note, or the code below won't |
8178 | scan it properly. */ | |
18dbd950 | 8179 | insn = get_insns (); |
e6d29d15 | 8180 | gcc_assert (GET_CODE (insn) == NOTE); |
949d79eb RE |
8181 | |
8182 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 8183 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 8184 | { |
9b6b54e2 | 8185 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 8186 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 8187 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 8188 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
8189 | cirrus_reorg (insn); |
8190 | ||
949d79eb | 8191 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 8192 | push_minipool_barrier (insn, address); |
f0375c66 | 8193 | else if (INSN_P (insn)) |
949d79eb RE |
8194 | { |
8195 | rtx table; | |
8196 | ||
f0375c66 | 8197 | note_invalid_constants (insn, address, true); |
949d79eb | 8198 | address += get_attr_length (insn); |
d5b7b3ae | 8199 | |
949d79eb RE |
8200 | /* If the insn is a vector jump, add the size of the table |
8201 | and skip the table. */ | |
d5b7b3ae | 8202 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 8203 | { |
d5b7b3ae | 8204 | address += get_jump_table_size (table); |
949d79eb RE |
8205 | insn = table; |
8206 | } | |
8207 | } | |
8208 | } | |
332072db | 8209 | |
d5b7b3ae | 8210 | fix = minipool_fix_head; |
f676971a | 8211 | |
949d79eb | 8212 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 8213 | while (fix) |
949d79eb | 8214 | { |
d5b7b3ae RE |
8215 | Mfix * ftmp; |
8216 | Mfix * fdel; | |
8217 | Mfix * last_added_fix; | |
8218 | Mfix * last_barrier = NULL; | |
8219 | Mfix * this_fix; | |
949d79eb RE |
8220 | |
8221 | /* Skip any further barriers before the next fix. */ | |
8222 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
8223 | fix = fix->next; | |
8224 | ||
d5b7b3ae | 8225 | /* No more fixes. */ |
949d79eb RE |
8226 | if (fix == NULL) |
8227 | break; | |
332072db | 8228 | |
d5b7b3ae | 8229 | last_added_fix = NULL; |
2b835d68 | 8230 | |
d5b7b3ae | 8231 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 8232 | { |
949d79eb | 8233 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 8234 | { |
d5b7b3ae RE |
8235 | if (ftmp->address >= minipool_vector_head->max_address) |
8236 | break; | |
2b835d68 | 8237 | |
d5b7b3ae | 8238 | last_barrier = ftmp; |
2b835d68 | 8239 | } |
d5b7b3ae RE |
8240 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
8241 | break; | |
8242 | ||
8243 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 8244 | } |
949d79eb | 8245 | |
d5b7b3ae RE |
8246 | /* If we found a barrier, drop back to that; any fixes that we |
8247 | could have reached but come after the barrier will now go in | |
8248 | the next mini-pool. */ | |
949d79eb RE |
8249 | if (last_barrier != NULL) |
8250 | { | |
f676971a | 8251 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
8252 | pool after all. */ |
8253 | for (fdel = last_barrier->next; | |
8254 | fdel && fdel != ftmp; | |
8255 | fdel = fdel->next) | |
8256 | { | |
8257 | fdel->minipool->refcount--; | |
8258 | fdel->minipool = NULL; | |
8259 | } | |
8260 | ||
949d79eb RE |
8261 | ftmp = last_barrier; |
8262 | } | |
8263 | else | |
2bfa88dc | 8264 | { |
d5b7b3ae RE |
8265 | /* ftmp is first fix that we can't fit into this pool and |
8266 | there no natural barriers that we could use. Insert a | |
8267 | new barrier in the code somewhere between the previous | |
8268 | fix and this one, and arrange to jump around it. */ | |
8269 | HOST_WIDE_INT max_address; | |
8270 | ||
8271 | /* The last item on the list of fixes must be a barrier, so | |
8272 | we can never run off the end of the list of fixes without | |
8273 | last_barrier being set. */ | |
e6d29d15 | 8274 | gcc_assert (ftmp); |
d5b7b3ae RE |
8275 | |
8276 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
8277 | /* Check that there isn't another fix that is in range that |
8278 | we couldn't fit into this pool because the pool was | |
8279 | already too large: we need to put the pool before such an | |
8280 | instruction. */ | |
d5b7b3ae RE |
8281 | if (ftmp->address < max_address) |
8282 | max_address = ftmp->address; | |
8283 | ||
8284 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
8285 | } | |
8286 | ||
8287 | assign_minipool_offsets (last_barrier); | |
8288 | ||
8289 | while (ftmp) | |
8290 | { | |
8291 | if (GET_CODE (ftmp->insn) != BARRIER | |
8292 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
8293 | == NULL)) | |
8294 | break; | |
2bfa88dc | 8295 | |
d5b7b3ae | 8296 | ftmp = ftmp->next; |
2bfa88dc | 8297 | } |
949d79eb RE |
8298 | |
8299 | /* Scan over the fixes we have identified for this pool, fixing them | |
8300 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 8301 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
8302 | this_fix = this_fix->next) |
8303 | if (GET_CODE (this_fix->insn) != BARRIER) | |
8304 | { | |
949d79eb | 8305 | rtx addr |
f676971a | 8306 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 8307 | minipool_vector_label), |
d5b7b3ae | 8308 | this_fix->minipool->offset); |
949d79eb RE |
8309 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
8310 | } | |
8311 | ||
d5b7b3ae | 8312 | dump_minipool (last_barrier->insn); |
949d79eb | 8313 | fix = ftmp; |
2b835d68 | 8314 | } |
4b632bf1 | 8315 | |
949d79eb RE |
8316 | /* From now on we must synthesize any constants that we can't handle |
8317 | directly. This can happen if the RTL gets split during final | |
8318 | instruction generation. */ | |
4b632bf1 | 8319 | after_arm_reorg = 1; |
c7319d87 RE |
8320 | |
8321 | /* Free the minipool memory. */ | |
8322 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 8323 | } |
cce8749e CH |
8324 | \f |
8325 | /* Routines to output assembly language. */ | |
8326 | ||
f3bb6135 | 8327 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 8328 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 8329 | when cross compiling. */ |
cd2b33d0 | 8330 | const char * |
e32bac5b | 8331 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
8332 | { |
8333 | REAL_VALUE_TYPE r; | |
8334 | int i; | |
f676971a | 8335 | |
9b66ebb1 PB |
8336 | if (!fp_consts_inited) |
8337 | init_fp_table (); | |
f676971a | 8338 | |
ff9940b0 RE |
8339 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
8340 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
8341 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
8342 | return strings_fp[i]; | |
f3bb6135 | 8343 | |
e6d29d15 | 8344 | gcc_unreachable (); |
ff9940b0 RE |
8345 | } |
8346 | ||
9997d19d | 8347 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 8348 | static const char * |
e32bac5b | 8349 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
8350 | { |
8351 | int i; | |
8352 | ||
9b66ebb1 PB |
8353 | if (!fp_consts_inited) |
8354 | init_fp_table (); | |
9997d19d RE |
8355 | |
8356 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
8357 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
8358 | return strings_fp[i]; | |
9997d19d | 8359 | |
e6d29d15 | 8360 | gcc_unreachable (); |
9997d19d | 8361 | } |
ff9940b0 | 8362 | |
cce8749e CH |
8363 | /* Output the operands of a LDM/STM instruction to STREAM. |
8364 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 NC |
8365 | REG is the base register, either the frame pointer or the stack pointer, |
8366 | INSTR is the possibly suffixed load or store instruction. */ | |
b279b20a | 8367 | |
d5b7b3ae | 8368 | static void |
b279b20a NC |
8369 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
8370 | unsigned long mask) | |
cce8749e | 8371 | { |
b279b20a NC |
8372 | unsigned i; |
8373 | bool not_first = FALSE; | |
cce8749e | 8374 | |
1d5473cb | 8375 | fputc ('\t', stream); |
dd18ae56 | 8376 | asm_fprintf (stream, instr, reg); |
1d5473cb | 8377 | fputs (", {", stream); |
f676971a | 8378 | |
d5b7b3ae | 8379 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
8380 | if (mask & (1 << i)) |
8381 | { | |
8382 | if (not_first) | |
8383 | fprintf (stream, ", "); | |
f676971a | 8384 | |
dd18ae56 | 8385 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
8386 | not_first = TRUE; |
8387 | } | |
f3bb6135 | 8388 | |
61f0ccff | 8389 | fprintf (stream, "}\n"); |
f3bb6135 | 8390 | } |
cce8749e | 8391 | |
9b66ebb1 | 8392 | |
9728c9d1 PB |
8393 | /* Output a FLDMX instruction to STREAM. |
8394 | BASE if the register containing the address. | |
8395 | REG and COUNT specify the register range. | |
8396 | Extra registers may be added to avoid hardware bugs. */ | |
9b66ebb1 PB |
8397 | |
8398 | static void | |
9728c9d1 | 8399 | arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
8400 | { |
8401 | int i; | |
8402 | ||
9728c9d1 PB |
8403 | /* Workaround ARM10 VFPr1 bug. */ |
8404 | if (count == 2 && !arm_arch6) | |
8405 | { | |
8406 | if (reg == 15) | |
8407 | reg--; | |
8408 | count++; | |
8409 | } | |
8410 | ||
9b66ebb1 | 8411 | fputc ('\t', stream); |
9728c9d1 | 8412 | asm_fprintf (stream, "fldmfdx\t%r!, {", base); |
9b66ebb1 | 8413 | |
9728c9d1 | 8414 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 8415 | { |
9728c9d1 | 8416 | if (i > reg) |
9b66ebb1 | 8417 | fputs (", ", stream); |
9728c9d1 | 8418 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
8419 | } |
8420 | fputs ("}\n", stream); | |
9728c9d1 | 8421 | |
9b66ebb1 PB |
8422 | } |
8423 | ||
8424 | ||
8425 | /* Output the assembly for a store multiple. */ | |
8426 | ||
8427 | const char * | |
8428 | vfp_output_fstmx (rtx * operands) | |
8429 | { | |
8430 | char pattern[100]; | |
8431 | int p; | |
8432 | int base; | |
8433 | int i; | |
8434 | ||
8435 | strcpy (pattern, "fstmfdx\t%m0!, {%P1"); | |
8436 | p = strlen (pattern); | |
8437 | ||
e6d29d15 | 8438 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
8439 | |
8440 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
8441 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
8442 | { | |
8443 | p += sprintf (&pattern[p], ", d%d", base + i); | |
8444 | } | |
8445 | strcpy (&pattern[p], "}"); | |
8446 | ||
8447 | output_asm_insn (pattern, operands); | |
8448 | return ""; | |
8449 | } | |
8450 | ||
8451 | ||
9728c9d1 PB |
8452 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
8453 | number of bytes pushed. */ | |
9b66ebb1 | 8454 | |
9728c9d1 | 8455 | static int |
9b66ebb1 PB |
8456 | vfp_emit_fstmx (int base_reg, int count) |
8457 | { | |
8458 | rtx par; | |
8459 | rtx dwarf; | |
8460 | rtx tmp, reg; | |
8461 | int i; | |
8462 | ||
9728c9d1 PB |
8463 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
8464 | register pairs are stored by a store multiple insn. We avoid this | |
8465 | by pushing an extra pair. */ | |
8466 | if (count == 2 && !arm_arch6) | |
8467 | { | |
8468 | if (base_reg == LAST_VFP_REGNUM - 3) | |
8469 | base_reg -= 2; | |
8470 | count++; | |
8471 | } | |
8472 | ||
9b66ebb1 PB |
8473 | /* ??? The frame layout is implementation defined. We describe |
8474 | standard format 1 (equivalent to a FSTMD insn and unused pad word). | |
8475 | We really need some way of representing the whole block so that the | |
8476 | unwinder can figure it out at runtime. */ | |
8477 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
8478 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
8479 | ||
8480 | reg = gen_rtx_REG (DFmode, base_reg); | |
8481 | base_reg += 2; | |
8482 | ||
8483 | XVECEXP (par, 0, 0) | |
8484 | = gen_rtx_SET (VOIDmode, | |
31fa16b6 RE |
8485 | gen_frame_mem (BLKmode, |
8486 | gen_rtx_PRE_DEC (BLKmode, | |
8487 | stack_pointer_rtx)), | |
9b66ebb1 PB |
8488 | gen_rtx_UNSPEC (BLKmode, |
8489 | gen_rtvec (1, reg), | |
8490 | UNSPEC_PUSH_MULT)); | |
8491 | ||
8492 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 | 8493 | plus_constant (stack_pointer_rtx, -(count * 8 + 4))); |
9b66ebb1 PB |
8494 | RTX_FRAME_RELATED_P (tmp) = 1; |
8495 | XVECEXP (dwarf, 0, 0) = tmp; | |
8496 | ||
8497 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 8498 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
8499 | reg); |
8500 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8501 | XVECEXP (dwarf, 0, 1) = tmp; | |
8502 | ||
8503 | for (i = 1; i < count; i++) | |
8504 | { | |
8505 | reg = gen_rtx_REG (DFmode, base_reg); | |
8506 | base_reg += 2; | |
8507 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
8508 | ||
8509 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 8510 | gen_frame_mem (DFmode, |
d66437c5 RE |
8511 | plus_constant (stack_pointer_rtx, |
8512 | i * 8)), | |
9b66ebb1 PB |
8513 | reg); |
8514 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8515 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
8516 | } | |
8517 | ||
8518 | par = emit_insn (par); | |
8519 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
8520 | REG_NOTES (par)); | |
9728c9d1 PB |
8521 | RTX_FRAME_RELATED_P (par) = 1; |
8522 | ||
8523 | return count * 8 + 4; | |
9b66ebb1 PB |
8524 | } |
8525 | ||
8526 | ||
6354dc9b | 8527 | /* Output a 'call' insn. */ |
cd2b33d0 | 8528 | const char * |
e32bac5b | 8529 | output_call (rtx *operands) |
cce8749e | 8530 | { |
e6d29d15 | 8531 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 8532 | |
68d560d4 | 8533 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 8534 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 8535 | { |
62b10bbc | 8536 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 8537 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 8538 | } |
f676971a | 8539 | |
1d5473cb | 8540 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 8541 | |
68d560d4 | 8542 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
8543 | output_asm_insn ("bx%?\t%0", operands); |
8544 | else | |
8545 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 8546 | |
f3bb6135 RE |
8547 | return ""; |
8548 | } | |
cce8749e | 8549 | |
6354dc9b | 8550 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 8551 | const char * |
e32bac5b | 8552 | output_call_mem (rtx *operands) |
ff9940b0 | 8553 | { |
68d560d4 | 8554 | if (TARGET_INTERWORK && !arm_arch5) |
da6558fd NC |
8555 | { |
8556 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
8557 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8558 | output_asm_insn ("bx%?\t%|ip", operands); | |
8559 | } | |
6ab5da80 RE |
8560 | else if (regno_use_in (LR_REGNUM, operands[0])) |
8561 | { | |
8562 | /* LR is used in the memory address. We load the address in the | |
8563 | first instruction. It's safe to use IP as the target of the | |
8564 | load since the call will kill it anyway. */ | |
8565 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
68d560d4 | 8566 | if (arm_arch5) |
07ec3810 | 8567 | output_asm_insn ("blx%?\t%|ip", operands); |
68d560d4 RE |
8568 | else |
8569 | { | |
8570 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8571 | if (arm_arch4t) | |
8572 | output_asm_insn ("bx%?\t%|ip", operands); | |
8573 | else | |
8574 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
8575 | } | |
6ab5da80 | 8576 | } |
da6558fd NC |
8577 | else |
8578 | { | |
8579 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8580 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
8581 | } | |
8582 | ||
f3bb6135 RE |
8583 | return ""; |
8584 | } | |
ff9940b0 RE |
8585 | |
8586 | ||
3b684012 RE |
8587 | /* Output a move from arm registers to an fpa registers. |
8588 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 8589 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 8590 | const char * |
e32bac5b | 8591 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
8592 | { |
8593 | int arm_reg0 = REGNO (operands[1]); | |
8594 | rtx ops[3]; | |
8595 | ||
e6d29d15 | 8596 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 8597 | |
43cffd11 RE |
8598 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8599 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
8600 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 8601 | |
1d5473cb RE |
8602 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); |
8603 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); | |
f676971a | 8604 | |
f3bb6135 RE |
8605 | return ""; |
8606 | } | |
ff9940b0 | 8607 | |
3b684012 | 8608 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 8609 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 8610 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 8611 | const char * |
e32bac5b | 8612 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
8613 | { |
8614 | int arm_reg0 = REGNO (operands[0]); | |
8615 | rtx ops[3]; | |
8616 | ||
e6d29d15 | 8617 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 8618 | |
43cffd11 RE |
8619 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8620 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
8621 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 8622 | |
1d5473cb RE |
8623 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
8624 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); | |
f3bb6135 RE |
8625 | return ""; |
8626 | } | |
ff9940b0 RE |
8627 | |
8628 | /* Output a move from arm registers to arm registers of a long double | |
8629 | OPERANDS[0] is the destination. | |
8630 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 8631 | const char * |
e32bac5b | 8632 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 8633 | { |
6354dc9b | 8634 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
8635 | int dest_start = REGNO (operands[0]); |
8636 | int src_start = REGNO (operands[1]); | |
8637 | rtx ops[2]; | |
8638 | int i; | |
8639 | ||
8640 | if (dest_start < src_start) | |
8641 | { | |
8642 | for (i = 0; i < 3; i++) | |
8643 | { | |
43cffd11 RE |
8644 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
8645 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 8646 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
8647 | } |
8648 | } | |
8649 | else | |
8650 | { | |
8651 | for (i = 2; i >= 0; i--) | |
8652 | { | |
43cffd11 RE |
8653 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
8654 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 8655 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
8656 | } |
8657 | } | |
f3bb6135 | 8658 | |
ff9940b0 RE |
8659 | return ""; |
8660 | } | |
8661 | ||
8662 | ||
3b684012 RE |
8663 | /* Output a move from arm registers to an fpa registers. |
8664 | OPERANDS[0] is an fpa register. | |
cce8749e | 8665 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 8666 | const char * |
e32bac5b | 8667 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
8668 | { |
8669 | int arm_reg0 = REGNO (operands[1]); | |
8670 | rtx ops[2]; | |
8671 | ||
e6d29d15 | 8672 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 8673 | |
43cffd11 RE |
8674 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8675 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
8676 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); |
8677 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); | |
f3bb6135 RE |
8678 | return ""; |
8679 | } | |
cce8749e | 8680 | |
3b684012 | 8681 | /* Output a move from an fpa register to arm registers. |
cce8749e | 8682 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 8683 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 8684 | const char * |
e32bac5b | 8685 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
8686 | { |
8687 | int arm_reg0 = REGNO (operands[0]); | |
8688 | rtx ops[2]; | |
8689 | ||
e6d29d15 | 8690 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 8691 | |
43cffd11 RE |
8692 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8693 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
8694 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
8695 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); | |
f3bb6135 RE |
8696 | return ""; |
8697 | } | |
cce8749e CH |
8698 | |
8699 | /* Output a move between double words. | |
8700 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
8701 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 8702 | const char * |
e32bac5b | 8703 | output_move_double (rtx *operands) |
cce8749e CH |
8704 | { |
8705 | enum rtx_code code0 = GET_CODE (operands[0]); | |
8706 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 8707 | rtx otherops[3]; |
cce8749e CH |
8708 | |
8709 | if (code0 == REG) | |
8710 | { | |
8711 | int reg0 = REGNO (operands[0]); | |
8712 | ||
43cffd11 | 8713 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 8714 | |
e6d29d15 NS |
8715 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
8716 | ||
8717 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 8718 | { |
e6d29d15 NS |
8719 | case REG: |
8720 | output_asm_insn ("ldm%?ia\t%m1, %M0", operands); | |
8721 | break; | |
e0b92319 | 8722 | |
e6d29d15 NS |
8723 | case PRE_INC: |
8724 | gcc_assert (TARGET_LDRD); | |
8725 | output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands); | |
8726 | break; | |
e0b92319 | 8727 | |
e6d29d15 NS |
8728 | case PRE_DEC: |
8729 | output_asm_insn ("ldm%?db\t%m1!, %M0", operands); | |
8730 | break; | |
e0b92319 | 8731 | |
e6d29d15 NS |
8732 | case POST_INC: |
8733 | output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); | |
8734 | break; | |
e0b92319 | 8735 | |
e6d29d15 NS |
8736 | case POST_DEC: |
8737 | gcc_assert (TARGET_LDRD); | |
8738 | output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands); | |
8739 | break; | |
e0b92319 | 8740 | |
e6d29d15 NS |
8741 | case PRE_MODIFY: |
8742 | case POST_MODIFY: | |
8743 | otherops[0] = operands[0]; | |
8744 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
8745 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 8746 | |
e6d29d15 | 8747 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 8748 | { |
e6d29d15 | 8749 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 8750 | { |
e6d29d15 NS |
8751 | /* Registers overlap so split out the increment. */ |
8752 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
8753 | output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops); | |
fdd695fd PB |
8754 | } |
8755 | else | |
e6d29d15 NS |
8756 | output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops); |
8757 | } | |
8758 | else | |
8759 | { | |
8760 | /* We only allow constant increments, so this is safe. */ | |
8761 | output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops); | |
8762 | } | |
8763 | break; | |
e0b92319 | 8764 | |
e6d29d15 NS |
8765 | case LABEL_REF: |
8766 | case CONST: | |
8767 | output_asm_insn ("adr%?\t%0, %1", operands); | |
8768 | output_asm_insn ("ldm%?ia\t%0, %M0", operands); | |
8769 | break; | |
e0b92319 | 8770 | |
e6d29d15 NS |
8771 | default: |
8772 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
8773 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
8774 | { | |
8775 | otherops[0] = operands[0]; | |
8776 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
8777 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 8778 | |
e6d29d15 | 8779 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 8780 | { |
e6d29d15 | 8781 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 8782 | { |
e6d29d15 | 8783 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 8784 | { |
e6d29d15 NS |
8785 | case -8: |
8786 | output_asm_insn ("ldm%?db\t%1, %M0", otherops); | |
8787 | return ""; | |
8788 | case -4: | |
8789 | output_asm_insn ("ldm%?da\t%1, %M0", otherops); | |
8790 | return ""; | |
8791 | case 4: | |
8792 | output_asm_insn ("ldm%?ib\t%1, %M0", otherops); | |
8793 | return ""; | |
fdd695fd | 8794 | } |
e6d29d15 NS |
8795 | } |
8796 | if (TARGET_LDRD | |
8797 | && (GET_CODE (otherops[2]) == REG | |
8798 | || (GET_CODE (otherops[2]) == CONST_INT | |
8799 | && INTVAL (otherops[2]) > -256 | |
8800 | && INTVAL (otherops[2]) < 256))) | |
8801 | { | |
8802 | if (reg_overlap_mentioned_p (otherops[0], | |
8803 | otherops[2])) | |
fdd695fd | 8804 | { |
e6d29d15 NS |
8805 | /* Swap base and index registers over to |
8806 | avoid a conflict. */ | |
8807 | otherops[1] = XEXP (XEXP (operands[1], 0), 1); | |
8808 | otherops[2] = XEXP (XEXP (operands[1], 0), 0); | |
fdd695fd | 8809 | } |
e6d29d15 NS |
8810 | /* If both registers conflict, it will usually |
8811 | have been fixed by a splitter. */ | |
8812 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) | |
fdd695fd | 8813 | { |
e6d29d15 NS |
8814 | output_asm_insn ("add%?\t%1, %1, %2", otherops); |
8815 | output_asm_insn ("ldr%?d\t%0, [%1]", | |
8816 | otherops); | |
2b835d68 RE |
8817 | } |
8818 | else | |
e6d29d15 NS |
8819 | output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops); |
8820 | return ""; | |
2b835d68 | 8821 | } |
e0b92319 | 8822 | |
e6d29d15 | 8823 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 8824 | { |
e6d29d15 NS |
8825 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
8826 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
8827 | else | |
8828 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
8829 | } |
8830 | else | |
e6d29d15 NS |
8831 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
8832 | } | |
8833 | else | |
8834 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
8835 | ||
8836 | return "ldm%?ia\t%0, %M0"; | |
8837 | } | |
8838 | else | |
8839 | { | |
8840 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
8841 | /* Take care of overlapping base/data reg. */ | |
8842 | if (reg_mentioned_p (operands[0], operands[1])) | |
8843 | { | |
8844 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
8845 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
8846 | } | |
8847 | else | |
8848 | { | |
8849 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
8850 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
8851 | } |
8852 | } | |
8853 | } | |
cce8749e | 8854 | } |
e6d29d15 | 8855 | else |
cce8749e | 8856 | { |
e6d29d15 NS |
8857 | /* Constraints should ensure this. */ |
8858 | gcc_assert (code0 == MEM && code1 == REG); | |
8859 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 8860 | |
ff9940b0 RE |
8861 | switch (GET_CODE (XEXP (operands[0], 0))) |
8862 | { | |
8863 | case REG: | |
9997d19d | 8864 | output_asm_insn ("stm%?ia\t%m0, %M1", operands); |
ff9940b0 | 8865 | break; |
2b835d68 | 8866 | |
ff9940b0 | 8867 | case PRE_INC: |
e6d29d15 | 8868 | gcc_assert (TARGET_LDRD); |
fdd695fd | 8869 | output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands); |
ff9940b0 | 8870 | break; |
2b835d68 | 8871 | |
ff9940b0 | 8872 | case PRE_DEC: |
2b835d68 | 8873 | output_asm_insn ("stm%?db\t%m0!, %M1", operands); |
ff9940b0 | 8874 | break; |
2b835d68 | 8875 | |
ff9940b0 | 8876 | case POST_INC: |
9997d19d | 8877 | output_asm_insn ("stm%?ia\t%m0!, %M1", operands); |
ff9940b0 | 8878 | break; |
2b835d68 | 8879 | |
ff9940b0 | 8880 | case POST_DEC: |
e6d29d15 | 8881 | gcc_assert (TARGET_LDRD); |
fdd695fd PB |
8882 | output_asm_insn ("str%?d\t%1, [%m0], #-8", operands); |
8883 | break; | |
8884 | ||
8885 | case PRE_MODIFY: | |
8886 | case POST_MODIFY: | |
8887 | otherops[0] = operands[1]; | |
8888 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
8889 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
8890 | ||
8891 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
8892 | output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops); | |
8893 | else | |
8894 | output_asm_insn ("str%?d\t%0, [%1], %2", otherops); | |
ff9940b0 | 8895 | break; |
2b835d68 RE |
8896 | |
8897 | case PLUS: | |
fdd695fd PB |
8898 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
8899 | if (GET_CODE (otherops[2]) == CONST_INT) | |
2b835d68 | 8900 | { |
06bea5aa | 8901 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
8902 | { |
8903 | case -8: | |
8904 | output_asm_insn ("stm%?db\t%m0, %M1", operands); | |
8905 | return ""; | |
8906 | ||
8907 | case -4: | |
8908 | output_asm_insn ("stm%?da\t%m0, %M1", operands); | |
8909 | return ""; | |
8910 | ||
8911 | case 4: | |
8912 | output_asm_insn ("stm%?ib\t%m0, %M1", operands); | |
8913 | return ""; | |
8914 | } | |
8915 | } | |
fdd695fd PB |
8916 | if (TARGET_LDRD |
8917 | && (GET_CODE (otherops[2]) == REG | |
8918 | || (GET_CODE (otherops[2]) == CONST_INT | |
8919 | && INTVAL (otherops[2]) > -256 | |
8920 | && INTVAL (otherops[2]) < 256))) | |
8921 | { | |
8922 | otherops[0] = operands[1]; | |
8923 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
8924 | output_asm_insn ("str%?d\t%0, [%1, %2]", otherops); | |
8925 | return ""; | |
8926 | } | |
2b835d68 RE |
8927 | /* Fall through */ |
8928 | ||
ff9940b0 | 8929 | default: |
a4a37b30 | 8930 | otherops[0] = adjust_address (operands[0], SImode, 4); |
43cffd11 | 8931 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
8932 | output_asm_insn ("str%?\t%1, %0", operands); |
8933 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
8934 | } |
8935 | } | |
cce8749e | 8936 | |
9997d19d RE |
8937 | return ""; |
8938 | } | |
cce8749e | 8939 | |
1d6e90ac NC |
8940 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
8941 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 8942 | const char * |
e32bac5b | 8943 | output_add_immediate (rtx *operands) |
cce8749e | 8944 | { |
f3bb6135 | 8945 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
8946 | |
8947 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
8948 | { | |
8949 | if (n < 0) | |
8950 | output_multi_immediate (operands, | |
9997d19d RE |
8951 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
8952 | -n); | |
cce8749e CH |
8953 | else |
8954 | output_multi_immediate (operands, | |
9997d19d RE |
8955 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
8956 | n); | |
cce8749e | 8957 | } |
f3bb6135 RE |
8958 | |
8959 | return ""; | |
8960 | } | |
cce8749e | 8961 | |
cce8749e CH |
8962 | /* Output a multiple immediate operation. |
8963 | OPERANDS is the vector of operands referred to in the output patterns. | |
8964 | INSTR1 is the output pattern to use for the first constant. | |
8965 | INSTR2 is the output pattern to use for subsequent constants. | |
8966 | IMMED_OP is the index of the constant slot in OPERANDS. | |
8967 | N is the constant value. */ | |
cd2b33d0 | 8968 | static const char * |
e32bac5b RE |
8969 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
8970 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 8971 | { |
f3bb6135 | 8972 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 8973 | n &= 0xffffffff; |
f3bb6135 RE |
8974 | #endif |
8975 | ||
cce8749e CH |
8976 | if (n == 0) |
8977 | { | |
1d6e90ac | 8978 | /* Quick and easy output. */ |
cce8749e | 8979 | operands[immed_op] = const0_rtx; |
1d6e90ac | 8980 | output_asm_insn (instr1, operands); |
cce8749e CH |
8981 | } |
8982 | else | |
8983 | { | |
8984 | int i; | |
cd2b33d0 | 8985 | const char * instr = instr1; |
cce8749e | 8986 | |
6354dc9b | 8987 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
8988 | for (i = 0; i < 32; i += 2) |
8989 | { | |
8990 | if (n & (3 << i)) | |
8991 | { | |
f3bb6135 RE |
8992 | operands[immed_op] = GEN_INT (n & (255 << i)); |
8993 | output_asm_insn (instr, operands); | |
cce8749e CH |
8994 | instr = instr2; |
8995 | i += 6; | |
8996 | } | |
8997 | } | |
8998 | } | |
f676971a | 8999 | |
f3bb6135 | 9000 | return ""; |
9997d19d | 9001 | } |
cce8749e | 9002 | |
cce8749e CH |
9003 | /* Return the appropriate ARM instruction for the operation code. |
9004 | The returned result should not be overwritten. OP is the rtx of the | |
9005 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
9006 | was shifted. */ | |
cd2b33d0 | 9007 | const char * |
e32bac5b | 9008 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 9009 | { |
9997d19d | 9010 | switch (GET_CODE (op)) |
cce8749e CH |
9011 | { |
9012 | case PLUS: | |
f3bb6135 RE |
9013 | return "add"; |
9014 | ||
cce8749e | 9015 | case MINUS: |
f3bb6135 RE |
9016 | return shift_first_arg ? "rsb" : "sub"; |
9017 | ||
cce8749e | 9018 | case IOR: |
f3bb6135 RE |
9019 | return "orr"; |
9020 | ||
cce8749e | 9021 | case XOR: |
f3bb6135 RE |
9022 | return "eor"; |
9023 | ||
cce8749e | 9024 | case AND: |
f3bb6135 RE |
9025 | return "and"; |
9026 | ||
cce8749e | 9027 | default: |
e6d29d15 | 9028 | gcc_unreachable (); |
cce8749e | 9029 | } |
f3bb6135 | 9030 | } |
cce8749e | 9031 | |
cce8749e CH |
9032 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
9033 | for the operation code. The returned result should not be overwritten. | |
9034 | OP is the rtx code of the shift. | |
9997d19d | 9035 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 9036 | shift. */ |
cd2b33d0 | 9037 | static const char * |
e32bac5b | 9038 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 9039 | { |
cd2b33d0 | 9040 | const char * mnem; |
e2c671ba | 9041 | enum rtx_code code = GET_CODE (op); |
cce8749e | 9042 | |
e6d29d15 NS |
9043 | switch (GET_CODE (XEXP (op, 1))) |
9044 | { | |
9045 | case REG: | |
9046 | case SUBREG: | |
9047 | *amountp = -1; | |
9048 | break; | |
9049 | ||
9050 | case CONST_INT: | |
9051 | *amountp = INTVAL (XEXP (op, 1)); | |
9052 | break; | |
9053 | ||
9054 | default: | |
9055 | gcc_unreachable (); | |
9056 | } | |
9997d19d | 9057 | |
e2c671ba | 9058 | switch (code) |
cce8749e CH |
9059 | { |
9060 | case ASHIFT: | |
9061 | mnem = "asl"; | |
9062 | break; | |
f3bb6135 | 9063 | |
cce8749e CH |
9064 | case ASHIFTRT: |
9065 | mnem = "asr"; | |
cce8749e | 9066 | break; |
f3bb6135 | 9067 | |
cce8749e CH |
9068 | case LSHIFTRT: |
9069 | mnem = "lsr"; | |
cce8749e | 9070 | break; |
f3bb6135 | 9071 | |
a657c98a | 9072 | case ROTATE: |
e6d29d15 | 9073 | gcc_assert (*amountp != -1); |
a657c98a RE |
9074 | *amountp = 32 - *amountp; |
9075 | ||
9076 | /* Fall through. */ | |
9077 | ||
9997d19d RE |
9078 | case ROTATERT: |
9079 | mnem = "ror"; | |
9997d19d RE |
9080 | break; |
9081 | ||
ff9940b0 | 9082 | case MULT: |
e2c671ba RE |
9083 | /* We never have to worry about the amount being other than a |
9084 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
9085 | gcc_assert (*amountp != -1); |
9086 | *amountp = int_log2 (*amountp); | |
f3bb6135 RE |
9087 | return "asl"; |
9088 | ||
cce8749e | 9089 | default: |
e6d29d15 | 9090 | gcc_unreachable (); |
cce8749e CH |
9091 | } |
9092 | ||
e2c671ba RE |
9093 | if (*amountp != -1) |
9094 | { | |
9095 | /* This is not 100% correct, but follows from the desire to merge | |
9096 | multiplication by a power of 2 with the recognizer for a | |
9097 | shift. >=32 is not a valid shift for "asl", so we must try and | |
9098 | output a shift that produces the correct arithmetical result. | |
ddd5a7c1 | 9099 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 9100 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
9101 | carry bit from such an operation, so we can ignore that. */ |
9102 | if (code == ROTATERT) | |
1d6e90ac NC |
9103 | /* Rotate is just modulo 32. */ |
9104 | *amountp &= 31; | |
e2c671ba RE |
9105 | else if (*amountp != (*amountp & 31)) |
9106 | { | |
9107 | if (code == ASHIFT) | |
9108 | mnem = "lsr"; | |
9109 | *amountp = 32; | |
9110 | } | |
9111 | ||
9112 | /* Shifts of 0 are no-ops. */ | |
9113 | if (*amountp == 0) | |
9114 | return NULL; | |
f676971a | 9115 | } |
e2c671ba | 9116 | |
9997d19d RE |
9117 | return mnem; |
9118 | } | |
cce8749e | 9119 | |
6354dc9b | 9120 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 9121 | |
18af7313 | 9122 | static HOST_WIDE_INT |
e32bac5b | 9123 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 9124 | { |
f3bb6135 | 9125 | HOST_WIDE_INT shift = 0; |
cce8749e | 9126 | |
30cf4896 | 9127 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 9128 | { |
e6d29d15 | 9129 | gcc_assert (shift <= 31); |
e32bac5b | 9130 | shift++; |
cce8749e | 9131 | } |
f3bb6135 RE |
9132 | |
9133 | return shift; | |
9134 | } | |
cce8749e | 9135 | |
c5ff069d ZW |
9136 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
9137 | because /bin/as is horribly restrictive. The judgement about | |
9138 | whether or not each character is 'printable' (and can be output as | |
9139 | is) or not (and must be printed with an octal escape) must be made | |
9140 | with reference to the *host* character set -- the situation is | |
9141 | similar to that discussed in the comments above pp_c_char in | |
9142 | c-pretty-print.c. */ | |
9143 | ||
6cfc7210 | 9144 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
9145 | |
9146 | void | |
e32bac5b | 9147 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
9148 | { |
9149 | int i; | |
6cfc7210 | 9150 | int len_so_far = 0; |
cce8749e | 9151 | |
6cfc7210 | 9152 | fputs ("\t.ascii\t\"", stream); |
f676971a | 9153 | |
cce8749e CH |
9154 | for (i = 0; i < len; i++) |
9155 | { | |
1d6e90ac | 9156 | int c = p[i]; |
cce8749e | 9157 | |
6cfc7210 | 9158 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 9159 | { |
6cfc7210 | 9160 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 9161 | len_so_far = 0; |
cce8749e CH |
9162 | } |
9163 | ||
c5ff069d | 9164 | if (ISPRINT (c)) |
cce8749e | 9165 | { |
c5ff069d | 9166 | if (c == '\\' || c == '\"') |
6cfc7210 | 9167 | { |
c5ff069d | 9168 | putc ('\\', stream); |
5895f793 | 9169 | len_so_far++; |
6cfc7210 | 9170 | } |
c5ff069d ZW |
9171 | putc (c, stream); |
9172 | len_so_far++; | |
9173 | } | |
9174 | else | |
9175 | { | |
9176 | fprintf (stream, "\\%03o", c); | |
9177 | len_so_far += 4; | |
cce8749e | 9178 | } |
cce8749e | 9179 | } |
f3bb6135 | 9180 | |
cce8749e | 9181 | fputs ("\"\n", stream); |
f3bb6135 | 9182 | } |
cce8749e | 9183 | \f |
c9ca9b88 | 9184 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 9185 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 9186 | |
6d3d9133 | 9187 | static unsigned long |
e32bac5b | 9188 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 9189 | { |
121308d4 | 9190 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 9191 | unsigned long save_reg_mask = 0; |
6d3d9133 | 9192 | unsigned int reg; |
6d3d9133 | 9193 | |
7b8b8ade | 9194 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 9195 | { |
7b8b8ade | 9196 | unsigned int max_reg; |
7b8b8ade NC |
9197 | /* Interrupt functions must not corrupt any registers, |
9198 | even call clobbered ones. If this is a leaf function | |
9199 | we can just examine the registers used by the RTL, but | |
9200 | otherwise we have to assume that whatever function is | |
9201 | called might clobber anything, and so we have to save | |
9202 | all the call-clobbered registers as well. */ | |
9203 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
9204 | /* FIQ handlers have registers r8 - r12 banked, so | |
9205 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 9206 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
9207 | r13 is the stack pointer which is always preserved, |
9208 | so we do not need to consider it here. */ | |
9209 | max_reg = 7; | |
9210 | else | |
9211 | max_reg = 12; | |
f676971a | 9212 | |
7b8b8ade NC |
9213 | for (reg = 0; reg <= max_reg; reg++) |
9214 | if (regs_ever_live[reg] | |
9215 | || (! current_function_is_leaf && call_used_regs [reg])) | |
6d3d9133 | 9216 | save_reg_mask |= (1 << reg); |
cfa01aab | 9217 | |
286d28c3 | 9218 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
9219 | if (flag_pic |
9220 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 9221 | && arm_pic_register != INVALID_REGNUM |
cfa01aab PB |
9222 | && current_function_uses_pic_offset_table) |
9223 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
6d3d9133 NC |
9224 | } |
9225 | else | |
9226 | { | |
9227 | /* In the normal case we only need to save those registers | |
9228 | which are call saved and which are used by this function. */ | |
9229 | for (reg = 0; reg <= 10; reg++) | |
9230 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
9231 | save_reg_mask |= (1 << reg); | |
9232 | ||
9233 | /* Handle the frame pointer as a special case. */ | |
9234 | if (! TARGET_APCS_FRAME | |
9235 | && ! frame_pointer_needed | |
9236 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] | |
9237 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) | |
9238 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
9239 | ||
9240 | /* If we aren't loading the PIC register, | |
9241 | don't stack it even though it may be live. */ | |
9242 | if (flag_pic | |
e0b92319 | 9243 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 9244 | && arm_pic_register != INVALID_REGNUM |
cfa01aab PB |
9245 | && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] |
9246 | || current_function_uses_pic_offset_table)) | |
6d3d9133 NC |
9247 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
9248 | } | |
9249 | ||
c9ca9b88 PB |
9250 | /* Save registers so the exception handler can modify them. */ |
9251 | if (current_function_calls_eh_return) | |
9252 | { | |
9253 | unsigned int i; | |
f676971a | 9254 | |
c9ca9b88 PB |
9255 | for (i = 0; ; i++) |
9256 | { | |
9257 | reg = EH_RETURN_DATA_REGNO (i); | |
9258 | if (reg == INVALID_REGNUM) | |
9259 | break; | |
9260 | save_reg_mask |= 1 << reg; | |
9261 | } | |
9262 | } | |
9263 | ||
121308d4 NC |
9264 | return save_reg_mask; |
9265 | } | |
9266 | ||
9267 | /* Compute a bit mask of which registers need to be | |
9268 | saved on the stack for the current function. */ | |
9269 | ||
9270 | static unsigned long | |
e32bac5b | 9271 | arm_compute_save_reg_mask (void) |
121308d4 NC |
9272 | { |
9273 | unsigned int save_reg_mask = 0; | |
9274 | unsigned long func_type = arm_current_func_type (); | |
9275 | ||
9276 | if (IS_NAKED (func_type)) | |
9277 | /* This should never really happen. */ | |
9278 | return 0; | |
9279 | ||
9280 | /* If we are creating a stack frame, then we must save the frame pointer, | |
9281 | IP (which will hold the old stack pointer), LR and the PC. */ | |
9282 | if (frame_pointer_needed) | |
9283 | save_reg_mask |= | |
9284 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
9285 | | (1 << IP_REGNUM) | |
9286 | | (1 << LR_REGNUM) | |
9287 | | (1 << PC_REGNUM); | |
9288 | ||
9289 | /* Volatile functions do not return, so there | |
9290 | is no need to save any other registers. */ | |
9291 | if (IS_VOLATILE (func_type)) | |
9292 | return save_reg_mask; | |
9293 | ||
9294 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
9295 | ||
6d3d9133 NC |
9296 | /* Decide if we need to save the link register. |
9297 | Interrupt routines have their own banked link register, | |
9298 | so they never need to save it. | |
1768c26f | 9299 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
9300 | it. If we are pushing other registers onto the stack however, we |
9301 | can save an instruction in the epilogue by pushing the link register | |
9302 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 9303 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 9304 | if we know that we will not need a fancy return sequence. */ |
3a7731fd | 9305 | if (regs_ever_live [LR_REGNUM] |
6d3d9133 NC |
9306 | || (save_reg_mask |
9307 | && optimize_size | |
c9ca9b88 PB |
9308 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL |
9309 | && !current_function_calls_eh_return)) | |
6d3d9133 NC |
9310 | save_reg_mask |= 1 << LR_REGNUM; |
9311 | ||
6f7ebcbb NC |
9312 | if (cfun->machine->lr_save_eliminated) |
9313 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
9314 | ||
5a9335ef NC |
9315 | if (TARGET_REALLY_IWMMXT |
9316 | && ((bit_count (save_reg_mask) | |
9317 | + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0) | |
9318 | { | |
9319 | unsigned int reg; | |
9320 | ||
9321 | /* The total number of registers that are going to be pushed | |
9322 | onto the stack is odd. We need to ensure that the stack | |
9323 | is 64-bit aligned before we start to save iWMMXt registers, | |
9324 | and also before we start to create locals. (A local variable | |
9325 | might be a double or long long which we will load/store using | |
9326 | an iWMMXt instruction). Therefore we need to push another | |
9327 | ARM register, so that the stack will be 64-bit aligned. We | |
9328 | try to avoid using the arg registers (r0 -r3) as they might be | |
9329 | used to pass values in a tail call. */ | |
9330 | for (reg = 4; reg <= 12; reg++) | |
9331 | if ((save_reg_mask & (1 << reg)) == 0) | |
9332 | break; | |
9333 | ||
9334 | if (reg <= 12) | |
9335 | save_reg_mask |= (1 << reg); | |
9336 | else | |
9337 | { | |
9338 | cfun->machine->sibcall_blocked = 1; | |
9339 | save_reg_mask |= (1 << 3); | |
9340 | } | |
9341 | } | |
9342 | ||
6d3d9133 NC |
9343 | return save_reg_mask; |
9344 | } | |
9345 | ||
9728c9d1 | 9346 | |
57934c39 PB |
9347 | /* Compute a bit mask of which registers need to be |
9348 | saved on the stack for the current function. */ | |
9349 | static unsigned long | |
9350 | thumb_compute_save_reg_mask (void) | |
9351 | { | |
9352 | unsigned long mask; | |
b279b20a | 9353 | unsigned reg; |
57934c39 PB |
9354 | |
9355 | mask = 0; | |
9356 | for (reg = 0; reg < 12; reg ++) | |
b279b20a NC |
9357 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
9358 | mask |= 1 << reg; | |
57934c39 | 9359 | |
39c39be0 RE |
9360 | if (flag_pic |
9361 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 9362 | && arm_pic_register != INVALID_REGNUM |
39c39be0 RE |
9363 | && current_function_uses_pic_offset_table) |
9364 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
b279b20a | 9365 | |
a2503645 RS |
9366 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
9367 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
9368 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 9369 | |
b279b20a | 9370 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
9371 | if (mask & 0xff || thumb_force_lr_save ()) |
9372 | mask |= (1 << LR_REGNUM); | |
9373 | ||
b279b20a NC |
9374 | /* Make sure we have a low work register if we need one. |
9375 | We will need one if we are going to push a high register, | |
9376 | but we are not currently intending to push a low register. */ | |
9377 | if ((mask & 0xff) == 0 | |
57934c39 | 9378 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
9379 | { |
9380 | /* Use thumb_find_work_register to choose which register | |
9381 | we will use. If the register is live then we will | |
9382 | have to push it. Use LAST_LO_REGNUM as our fallback | |
9383 | choice for the register to select. */ | |
9384 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
9385 | ||
9386 | if (! call_used_regs[reg]) | |
9387 | mask |= 1 << reg; | |
9388 | } | |
57934c39 PB |
9389 | |
9390 | return mask; | |
9391 | } | |
9392 | ||
9393 | ||
9728c9d1 PB |
9394 | /* Return the number of bytes required to save VFP registers. */ |
9395 | static int | |
9396 | arm_get_vfp_saved_size (void) | |
9397 | { | |
9398 | unsigned int regno; | |
9399 | int count; | |
9400 | int saved; | |
9401 | ||
9402 | saved = 0; | |
9403 | /* Space for saved VFP registers. */ | |
9404 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9405 | { | |
9406 | count = 0; | |
9407 | for (regno = FIRST_VFP_REGNUM; | |
9408 | regno < LAST_VFP_REGNUM; | |
9409 | regno += 2) | |
9410 | { | |
9411 | if ((!regs_ever_live[regno] || call_used_regs[regno]) | |
9412 | && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1])) | |
9413 | { | |
9414 | if (count > 0) | |
9415 | { | |
9416 | /* Workaround ARM10 VFPr1 bug. */ | |
9417 | if (count == 2 && !arm_arch6) | |
9418 | count++; | |
9419 | saved += count * 8 + 4; | |
9420 | } | |
9421 | count = 0; | |
9422 | } | |
9423 | else | |
9424 | count++; | |
9425 | } | |
9426 | if (count > 0) | |
9427 | { | |
9428 | if (count == 2 && !arm_arch6) | |
9429 | count++; | |
9430 | saved += count * 8 + 4; | |
9431 | } | |
9432 | } | |
9433 | return saved; | |
9434 | } | |
9435 | ||
9436 | ||
699a4925 | 9437 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 9438 | everything bar the final return instruction. */ |
cd2b33d0 | 9439 | const char * |
e32bac5b | 9440 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 9441 | { |
6d3d9133 | 9442 | char conditional[10]; |
ff9940b0 | 9443 | char instr[100]; |
b279b20a | 9444 | unsigned reg; |
6d3d9133 NC |
9445 | unsigned long live_regs_mask; |
9446 | unsigned long func_type; | |
5848830f | 9447 | arm_stack_offsets *offsets; |
e26053d1 | 9448 | |
6d3d9133 | 9449 | func_type = arm_current_func_type (); |
e2c671ba | 9450 | |
6d3d9133 | 9451 | if (IS_NAKED (func_type)) |
d5b7b3ae | 9452 | return ""; |
6d3d9133 NC |
9453 | |
9454 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 9455 | { |
699a4925 RE |
9456 | /* If this function was declared non-returning, and we have |
9457 | found a tail call, then we have to trust that the called | |
9458 | function won't return. */ | |
3a5a4282 PB |
9459 | if (really_return) |
9460 | { | |
9461 | rtx ops[2]; | |
f676971a | 9462 | |
3a5a4282 PB |
9463 | /* Otherwise, trap an attempted return by aborting. */ |
9464 | ops[0] = operand; | |
f676971a | 9465 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
9466 | : "abort"); |
9467 | assemble_external_libcall (ops[1]); | |
9468 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
9469 | } | |
f676971a | 9470 | |
e2c671ba RE |
9471 | return ""; |
9472 | } | |
6d3d9133 | 9473 | |
e6d29d15 | 9474 | gcc_assert (!current_function_calls_alloca || really_return); |
ff9940b0 | 9475 | |
c414f8a9 | 9476 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 9477 | |
6d3d9133 | 9478 | return_used_this_function = 1; |
ff9940b0 | 9479 | |
6d3d9133 | 9480 | live_regs_mask = arm_compute_save_reg_mask (); |
ff9940b0 | 9481 | |
1768c26f | 9482 | if (live_regs_mask) |
6d3d9133 | 9483 | { |
1768c26f PB |
9484 | const char * return_reg; |
9485 | ||
f676971a | 9486 | /* If we do not have any special requirements for function exit |
112cdef5 | 9487 | (e.g. interworking, or ISR) then we can load the return address |
1768c26f PB |
9488 | directly into the PC. Otherwise we must load it into LR. */ |
9489 | if (really_return | |
1768c26f PB |
9490 | && ! TARGET_INTERWORK) |
9491 | return_reg = reg_names[PC_REGNUM]; | |
6d3d9133 | 9492 | else |
1768c26f PB |
9493 | return_reg = reg_names[LR_REGNUM]; |
9494 | ||
6d3d9133 | 9495 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
9496 | { |
9497 | /* There are three possible reasons for the IP register | |
9498 | being saved. 1) a stack frame was created, in which case | |
9499 | IP contains the old stack pointer, or 2) an ISR routine | |
9500 | corrupted it, or 3) it was saved to align the stack on | |
9501 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
9502 | restore IP. */ | |
9503 | if (frame_pointer_needed) | |
9504 | { | |
9505 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
9506 | live_regs_mask |= (1 << SP_REGNUM); | |
9507 | } | |
9508 | else | |
e6d29d15 | 9509 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 9510 | } |
f3bb6135 | 9511 | |
3a7731fd PB |
9512 | /* On some ARM architectures it is faster to use LDR rather than |
9513 | LDM to load a single register. On other architectures, the | |
9514 | cost is the same. In 26 bit mode, or for exception handlers, | |
9515 | we have to use LDM to load the PC so that the CPSR is also | |
9516 | restored. */ | |
9517 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
9518 | if (live_regs_mask == (1U << reg)) |
9519 | break; | |
9520 | ||
3a7731fd PB |
9521 | if (reg <= LAST_ARM_REGNUM |
9522 | && (reg != LR_REGNUM | |
f676971a | 9523 | || ! really_return |
61f0ccff | 9524 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 9525 | { |
f676971a | 9526 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 9527 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 9528 | } |
ff9940b0 | 9529 | else |
1d5473cb | 9530 | { |
1768c26f PB |
9531 | char *p; |
9532 | int first = 1; | |
6d3d9133 | 9533 | |
699a4925 RE |
9534 | /* Generate the load multiple instruction to restore the |
9535 | registers. Note we can get here, even if | |
9536 | frame_pointer_needed is true, but only if sp already | |
9537 | points to the base of the saved core registers. */ | |
9538 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 9539 | { |
5848830f PB |
9540 | unsigned HOST_WIDE_INT stack_adjust; |
9541 | ||
9542 | offsets = arm_get_frame_offsets (); | |
9543 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
e6d29d15 | 9544 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 RE |
9545 | |
9546 | if (stack_adjust && arm_arch5) | |
9547 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); | |
9548 | else | |
9549 | { | |
b279b20a NC |
9550 | /* If we can't use ldmib (SA110 bug), |
9551 | then try to pop r3 instead. */ | |
a72d4945 RE |
9552 | if (stack_adjust) |
9553 | live_regs_mask |= 1 << 3; | |
9554 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
9555 | } | |
9556 | } | |
da6558fd | 9557 | else |
1768c26f PB |
9558 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
9559 | ||
9560 | p = instr + strlen (instr); | |
6d3d9133 | 9561 | |
1768c26f PB |
9562 | for (reg = 0; reg <= SP_REGNUM; reg++) |
9563 | if (live_regs_mask & (1 << reg)) | |
9564 | { | |
9565 | int l = strlen (reg_names[reg]); | |
9566 | ||
9567 | if (first) | |
9568 | first = 0; | |
9569 | else | |
9570 | { | |
9571 | memcpy (p, ", ", 2); | |
9572 | p += 2; | |
9573 | } | |
9574 | ||
9575 | memcpy (p, "%|", 2); | |
9576 | memcpy (p + 2, reg_names[reg], l); | |
9577 | p += l + 2; | |
9578 | } | |
f676971a | 9579 | |
1768c26f PB |
9580 | if (live_regs_mask & (1 << LR_REGNUM)) |
9581 | { | |
b17fe233 | 9582 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
9583 | /* If returning from an interrupt, restore the CPSR. */ |
9584 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 9585 | strcat (p, "^"); |
1768c26f PB |
9586 | } |
9587 | else | |
9588 | strcpy (p, "}"); | |
1d5473cb | 9589 | } |
da6558fd | 9590 | |
1768c26f PB |
9591 | output_asm_insn (instr, & operand); |
9592 | ||
3a7731fd PB |
9593 | /* See if we need to generate an extra instruction to |
9594 | perform the actual function return. */ | |
9595 | if (really_return | |
9596 | && func_type != ARM_FT_INTERWORKED | |
9597 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 9598 | { |
3a7731fd PB |
9599 | /* The return has already been handled |
9600 | by loading the LR into the PC. */ | |
9601 | really_return = 0; | |
da6558fd | 9602 | } |
ff9940b0 | 9603 | } |
e26053d1 | 9604 | |
1768c26f | 9605 | if (really_return) |
ff9940b0 | 9606 | { |
6d3d9133 NC |
9607 | switch ((int) ARM_FUNC_TYPE (func_type)) |
9608 | { | |
9609 | case ARM_FT_ISR: | |
9610 | case ARM_FT_FIQ: | |
9611 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); | |
9612 | break; | |
9613 | ||
9614 | case ARM_FT_INTERWORKED: | |
9615 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
9616 | break; | |
9617 | ||
9618 | case ARM_FT_EXCEPTION: | |
9619 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); | |
9620 | break; | |
9621 | ||
9622 | default: | |
68d560d4 RE |
9623 | /* Use bx if it's available. */ |
9624 | if (arm_arch5 || arm_arch4t) | |
f676971a | 9625 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 9626 | else |
61f0ccff | 9627 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
9628 | break; |
9629 | } | |
1768c26f PB |
9630 | |
9631 | output_asm_insn (instr, & operand); | |
ff9940b0 | 9632 | } |
f3bb6135 | 9633 | |
ff9940b0 RE |
9634 | return ""; |
9635 | } | |
9636 | ||
ef179a26 NC |
9637 | /* Write the function name into the code section, directly preceding |
9638 | the function prologue. | |
9639 | ||
9640 | Code will be output similar to this: | |
9641 | t0 | |
9642 | .ascii "arm_poke_function_name", 0 | |
9643 | .align | |
9644 | t1 | |
9645 | .word 0xff000000 + (t1 - t0) | |
9646 | arm_poke_function_name | |
9647 | mov ip, sp | |
9648 | stmfd sp!, {fp, ip, lr, pc} | |
9649 | sub fp, ip, #4 | |
9650 | ||
9651 | When performing a stack backtrace, code can inspect the value | |
9652 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
9653 | at location pc - 12 and the top 8 bits are set, then we know | |
9654 | that there is a function name embedded immediately preceding this | |
9655 | location and has length ((pc[-3]) & 0xff000000). | |
9656 | ||
9657 | We assume that pc is declared as a pointer to an unsigned long. | |
9658 | ||
9659 | It is of no benefit to output the function name if we are assembling | |
9660 | a leaf function. These function types will not contain a stack | |
9661 | backtrace structure, therefore it is not possible to determine the | |
9662 | function name. */ | |
ef179a26 | 9663 | void |
e32bac5b | 9664 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
9665 | { |
9666 | unsigned long alignlength; | |
9667 | unsigned long length; | |
9668 | rtx x; | |
9669 | ||
d5b7b3ae | 9670 | length = strlen (name) + 1; |
0c2ca901 | 9671 | alignlength = ROUND_UP_WORD (length); |
f676971a | 9672 | |
949d79eb | 9673 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 9674 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 9675 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 9676 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
9677 | } |
9678 | ||
6d3d9133 NC |
9679 | /* Place some comments into the assembler stream |
9680 | describing the current function. */ | |
08c148a8 | 9681 | static void |
e32bac5b | 9682 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 9683 | { |
6d3d9133 | 9684 | unsigned long func_type; |
08c148a8 NB |
9685 | |
9686 | if (!TARGET_ARM) | |
9687 | { | |
9688 | thumb_output_function_prologue (f, frame_size); | |
9689 | return; | |
9690 | } | |
f676971a | 9691 | |
6d3d9133 | 9692 | /* Sanity check. */ |
e6d29d15 | 9693 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 9694 | |
6d3d9133 | 9695 | func_type = arm_current_func_type (); |
f676971a | 9696 | |
6d3d9133 NC |
9697 | switch ((int) ARM_FUNC_TYPE (func_type)) |
9698 | { | |
9699 | default: | |
9700 | case ARM_FT_NORMAL: | |
9701 | break; | |
9702 | case ARM_FT_INTERWORKED: | |
9703 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
9704 | break; | |
6d3d9133 NC |
9705 | case ARM_FT_ISR: |
9706 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
9707 | break; | |
9708 | case ARM_FT_FIQ: | |
9709 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
9710 | break; | |
9711 | case ARM_FT_EXCEPTION: | |
9712 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
9713 | break; | |
9714 | } | |
f676971a | 9715 | |
6d3d9133 NC |
9716 | if (IS_NAKED (func_type)) |
9717 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
9718 | ||
9719 | if (IS_VOLATILE (func_type)) | |
9720 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
9721 | ||
9722 | if (IS_NESTED (func_type)) | |
9723 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
f676971a | 9724 | |
c53dddc2 | 9725 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
dd18ae56 NC |
9726 | current_function_args_size, |
9727 | current_function_pretend_args_size, frame_size); | |
6d3d9133 | 9728 | |
3cb66fd7 | 9729 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 9730 | frame_pointer_needed, |
3cb66fd7 | 9731 | cfun->machine->uses_anonymous_args); |
cce8749e | 9732 | |
6f7ebcbb NC |
9733 | if (cfun->machine->lr_save_eliminated) |
9734 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
9735 | ||
c9ca9b88 PB |
9736 | if (current_function_calls_eh_return) |
9737 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); | |
9738 | ||
32de079a RE |
9739 | #ifdef AOF_ASSEMBLER |
9740 | if (flag_pic) | |
dd18ae56 | 9741 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); |
32de079a | 9742 | #endif |
6d3d9133 | 9743 | |
f676971a | 9744 | return_used_this_function = 0; |
f3bb6135 | 9745 | } |
cce8749e | 9746 | |
cd2b33d0 | 9747 | const char * |
a72d4945 | 9748 | arm_output_epilogue (rtx sibling) |
cce8749e | 9749 | { |
949d79eb | 9750 | int reg; |
6f7ebcbb | 9751 | unsigned long saved_regs_mask; |
6d3d9133 | 9752 | unsigned long func_type; |
f676971a | 9753 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
9754 | frame that is $fp + 4 for a non-variadic function. */ |
9755 | int floats_offset = 0; | |
cce8749e | 9756 | rtx operands[3]; |
d5b7b3ae | 9757 | FILE * f = asm_out_file; |
5a9335ef | 9758 | unsigned int lrm_count = 0; |
a72d4945 | 9759 | int really_return = (sibling == NULL); |
9b66ebb1 | 9760 | int start_reg; |
5848830f | 9761 | arm_stack_offsets *offsets; |
cce8749e | 9762 | |
6d3d9133 NC |
9763 | /* If we have already generated the return instruction |
9764 | then it is futile to generate anything else. */ | |
a72d4945 | 9765 | if (use_return_insn (FALSE, sibling) && return_used_this_function) |
949d79eb | 9766 | return ""; |
cce8749e | 9767 | |
6d3d9133 | 9768 | func_type = arm_current_func_type (); |
d5b7b3ae | 9769 | |
6d3d9133 NC |
9770 | if (IS_NAKED (func_type)) |
9771 | /* Naked functions don't have epilogues. */ | |
9772 | return ""; | |
0616531f | 9773 | |
6d3d9133 | 9774 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 9775 | { |
86efdc8e | 9776 | rtx op; |
f676971a | 9777 | |
6d3d9133 | 9778 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 9779 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 9780 | assemble_external_libcall (op); |
e2c671ba | 9781 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 9782 | |
949d79eb | 9783 | return ""; |
e2c671ba RE |
9784 | } |
9785 | ||
e6d29d15 NS |
9786 | /* If we are throwing an exception, then we really must be doing a |
9787 | return, so we can't tail-call. */ | |
9788 | gcc_assert (!current_function_calls_eh_return || really_return); | |
f676971a | 9789 | |
5848830f | 9790 | offsets = arm_get_frame_offsets (); |
6f7ebcbb | 9791 | saved_regs_mask = arm_compute_save_reg_mask (); |
5a9335ef NC |
9792 | |
9793 | if (TARGET_IWMMXT) | |
9794 | lrm_count = bit_count (saved_regs_mask); | |
9795 | ||
5848830f | 9796 | floats_offset = offsets->saved_args; |
6d3d9133 | 9797 | /* Compute how far away the floats will be. */ |
5a9335ef | 9798 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 9799 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 9800 | floats_offset += 4; |
f676971a | 9801 | |
ff9940b0 | 9802 | if (frame_pointer_needed) |
cce8749e | 9803 | { |
9b66ebb1 | 9804 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 9805 | int vfp_offset = offsets->frame; |
c882c7ac | 9806 | |
29ad9694 | 9807 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 9808 | { |
9b66ebb1 | 9809 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
5895f793 | 9810 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9811 | { |
9812 | floats_offset += 12; | |
f676971a | 9813 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 9814 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9815 | } |
9816 | } | |
9817 | else | |
9818 | { | |
9b66ebb1 | 9819 | start_reg = LAST_FPA_REGNUM; |
b111229a | 9820 | |
9b66ebb1 | 9821 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 9822 | { |
5895f793 | 9823 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9824 | { |
9825 | floats_offset += 12; | |
f676971a | 9826 | |
6354dc9b | 9827 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
9828 | if (start_reg - reg == 3) |
9829 | { | |
dd18ae56 | 9830 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 9831 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9832 | start_reg = reg - 1; |
9833 | } | |
9834 | } | |
9835 | else | |
9836 | { | |
9837 | if (reg != start_reg) | |
dd18ae56 NC |
9838 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
9839 | reg + 1, start_reg - reg, | |
c882c7ac | 9840 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9841 | start_reg = reg - 1; |
9842 | } | |
9843 | } | |
9844 | ||
9845 | /* Just in case the last register checked also needs unstacking. */ | |
9846 | if (reg != start_reg) | |
dd18ae56 NC |
9847 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
9848 | reg + 1, start_reg - reg, | |
c882c7ac | 9849 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 9850 | } |
6d3d9133 | 9851 | |
9b66ebb1 PB |
9852 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
9853 | { | |
9728c9d1 | 9854 | int saved_size; |
9b66ebb1 | 9855 | |
9728c9d1 PB |
9856 | /* The fldmx insn does not have base+offset addressing modes, |
9857 | so we use IP to hold the address. */ | |
9858 | saved_size = arm_get_vfp_saved_size (); | |
9b66ebb1 | 9859 | |
9728c9d1 | 9860 | if (saved_size > 0) |
9b66ebb1 | 9861 | { |
9728c9d1 | 9862 | floats_offset += saved_size; |
9b66ebb1 PB |
9863 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
9864 | FP_REGNUM, floats_offset - vfp_offset); | |
9865 | } | |
9866 | start_reg = FIRST_VFP_REGNUM; | |
9867 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
9868 | { | |
9869 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
9870 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
9871 | { | |
9872 | if (start_reg != reg) | |
9728c9d1 PB |
9873 | arm_output_fldmx (f, IP_REGNUM, |
9874 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9875 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
9876 | start_reg = reg + 2; |
9877 | } | |
9878 | } | |
9879 | if (start_reg != reg) | |
9728c9d1 PB |
9880 | arm_output_fldmx (f, IP_REGNUM, |
9881 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9882 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
9883 | } |
9884 | ||
5a9335ef NC |
9885 | if (TARGET_IWMMXT) |
9886 | { | |
9887 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
9888 | This is because it is set to (old_stack_pointer - 4) and the | |
9889 | old_stack_pointer was double word aligned. Thus the offset to | |
9890 | the iWMMXt registers to be loaded must also be non-double-word | |
9891 | sized, so that the resultant address *is* double-word aligned. | |
9892 | We can ignore floats_offset since that was already included in | |
9893 | the live_regs_mask. */ | |
9894 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 9895 | |
01d4c813 | 9896 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
5a9335ef NC |
9897 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
9898 | { | |
f676971a | 9899 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 9900 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 9901 | lrm_count += 2; |
5a9335ef NC |
9902 | } |
9903 | } | |
9904 | ||
6f7ebcbb | 9905 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
9906 | frame generation actually contains the old stack pointer. So a |
9907 | quick way to unwind the stack is just pop the IP register directly | |
9908 | into the stack pointer. */ | |
e6d29d15 | 9909 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
9910 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
9911 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 9912 | |
6f7ebcbb | 9913 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
9914 | only need to restore the LR register (the return address), but to |
9915 | save time we can load it directly into the PC, unless we need a | |
9916 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
9917 | if (really_return |
9918 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
9919 | && !current_function_calls_eh_return) | |
6d3d9133 NC |
9920 | /* Delete the LR from the register mask, so that the LR on |
9921 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 9922 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 9923 | else |
6f7ebcbb | 9924 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
9925 | |
9926 | /* We must use SP as the base register, because SP is one of the | |
9927 | registers being restored. If an interrupt or page fault | |
9928 | happens in the ldm instruction, the SP might or might not | |
9929 | have been restored. That would be bad, as then SP will no | |
9930 | longer indicate the safe area of stack, and we can get stack | |
9931 | corruption. Using SP as the base register means that it will | |
9932 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
9933 | occur. If the stack pointer already points at the right |
9934 | place, then omit the subtraction. */ | |
5848830f | 9935 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
699a4925 RE |
9936 | || current_function_calls_alloca) |
9937 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, | |
9938 | 4 * bit_count (saved_regs_mask)); | |
efc2515b | 9939 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); |
7b8b8ade NC |
9940 | |
9941 | if (IS_INTERRUPT (func_type)) | |
9942 | /* Interrupt handlers will have pushed the | |
9943 | IP onto the stack, so restore it now. */ | |
f55d7103 | 9944 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM); |
cce8749e CH |
9945 | } |
9946 | else | |
9947 | { | |
d2288d8d | 9948 | /* Restore stack pointer if necessary. */ |
5848830f | 9949 | if (offsets->outgoing_args != offsets->saved_regs) |
d2288d8d TG |
9950 | { |
9951 | operands[0] = operands[1] = stack_pointer_rtx; | |
5848830f | 9952 | operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs); |
d2288d8d TG |
9953 | output_add_immediate (operands); |
9954 | } | |
9955 | ||
29ad9694 | 9956 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 9957 | { |
9b66ebb1 | 9958 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
5895f793 | 9959 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
dd18ae56 NC |
9960 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
9961 | reg, SP_REGNUM); | |
b111229a RE |
9962 | } |
9963 | else | |
9964 | { | |
9b66ebb1 | 9965 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 9966 | |
9b66ebb1 | 9967 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 9968 | { |
5895f793 | 9969 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9970 | { |
9971 | if (reg - start_reg == 3) | |
9972 | { | |
dd18ae56 NC |
9973 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
9974 | start_reg, SP_REGNUM); | |
b111229a RE |
9975 | start_reg = reg + 1; |
9976 | } | |
9977 | } | |
9978 | else | |
9979 | { | |
9980 | if (reg != start_reg) | |
dd18ae56 NC |
9981 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
9982 | start_reg, reg - start_reg, | |
9983 | SP_REGNUM); | |
f676971a | 9984 | |
b111229a RE |
9985 | start_reg = reg + 1; |
9986 | } | |
9987 | } | |
9988 | ||
9989 | /* Just in case the last register checked also needs unstacking. */ | |
9990 | if (reg != start_reg) | |
dd18ae56 NC |
9991 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
9992 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
9993 | } |
9994 | ||
9b66ebb1 PB |
9995 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
9996 | { | |
9997 | start_reg = FIRST_VFP_REGNUM; | |
9998 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
9999 | { | |
10000 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
10001 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
10002 | { | |
10003 | if (start_reg != reg) | |
9728c9d1 PB |
10004 | arm_output_fldmx (f, SP_REGNUM, |
10005 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
10006 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
10007 | start_reg = reg + 2; |
10008 | } | |
10009 | } | |
10010 | if (start_reg != reg) | |
9728c9d1 PB |
10011 | arm_output_fldmx (f, SP_REGNUM, |
10012 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
10013 | (reg - start_reg) / 2); | |
9b66ebb1 | 10014 | } |
5a9335ef NC |
10015 | if (TARGET_IWMMXT) |
10016 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
10017 | if (regs_ever_live[reg] && !call_used_regs[reg]) | |
01d4c813 | 10018 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 10019 | |
6d3d9133 NC |
10020 | /* If we can, restore the LR into the PC. */ |
10021 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
10022 | && really_return | |
10023 | && current_function_pretend_args_size == 0 | |
c9ca9b88 PB |
10024 | && saved_regs_mask & (1 << LR_REGNUM) |
10025 | && !current_function_calls_eh_return) | |
cce8749e | 10026 | { |
6f7ebcbb NC |
10027 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
10028 | saved_regs_mask |= (1 << PC_REGNUM); | |
6d3d9133 | 10029 | } |
d5b7b3ae | 10030 | |
6d3d9133 NC |
10031 | /* Load the registers off the stack. If we only have one register |
10032 | to load use the LDR instruction - it is faster. */ | |
6f7ebcbb | 10033 | if (saved_regs_mask == (1 << LR_REGNUM)) |
6d3d9133 | 10034 | { |
c9ca9b88 | 10035 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 10036 | } |
6f7ebcbb | 10037 | else if (saved_regs_mask) |
f1acdf8b NC |
10038 | { |
10039 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
10040 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 10041 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
10042 | in the list of registers and if we add writeback the |
10043 | instruction becomes UNPREDICTABLE. */ | |
10044 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); | |
10045 | else | |
10046 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); | |
10047 | } | |
6d3d9133 NC |
10048 | |
10049 | if (current_function_pretend_args_size) | |
cce8749e | 10050 | { |
6d3d9133 NC |
10051 | /* Unwind the pre-pushed regs. */ |
10052 | operands[0] = operands[1] = stack_pointer_rtx; | |
10053 | operands[2] = GEN_INT (current_function_pretend_args_size); | |
10054 | output_add_immediate (operands); | |
10055 | } | |
10056 | } | |
32de079a | 10057 | |
2966b00e | 10058 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 10059 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 10060 | return ""; |
d5b7b3ae | 10061 | |
c9ca9b88 PB |
10062 | /* Stack adjustment for exception handler. */ |
10063 | if (current_function_calls_eh_return) | |
f676971a | 10064 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
10065 | ARM_EH_STACKADJ_REGNUM); |
10066 | ||
6d3d9133 NC |
10067 | /* Generate the return instruction. */ |
10068 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
10069 | { | |
6d3d9133 NC |
10070 | case ARM_FT_ISR: |
10071 | case ARM_FT_FIQ: | |
10072 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
10073 | break; | |
10074 | ||
10075 | case ARM_FT_EXCEPTION: | |
10076 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
10077 | break; | |
10078 | ||
10079 | case ARM_FT_INTERWORKED: | |
10080 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
10081 | break; | |
10082 | ||
10083 | default: | |
68d560d4 RE |
10084 | if (arm_arch5 || arm_arch4t) |
10085 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
10086 | else | |
10087 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 10088 | break; |
cce8749e | 10089 | } |
f3bb6135 | 10090 | |
949d79eb RE |
10091 | return ""; |
10092 | } | |
10093 | ||
08c148a8 | 10094 | static void |
e32bac5b | 10095 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 10096 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 10097 | { |
5848830f PB |
10098 | arm_stack_offsets *offsets; |
10099 | ||
d5b7b3ae RE |
10100 | if (TARGET_THUMB) |
10101 | { | |
b12a00f1 RE |
10102 | int regno; |
10103 | ||
10104 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
10105 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 10106 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
10107 | { |
10108 | rtx label = cfun->machine->call_via[regno]; | |
10109 | ||
10110 | if (label != NULL) | |
10111 | { | |
d6b5193b | 10112 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
10113 | targetm.asm_out.internal_label (asm_out_file, "L", |
10114 | CODE_LABEL_NUMBER (label)); | |
10115 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
10116 | } | |
10117 | } | |
10118 | ||
d5b7b3ae RE |
10119 | /* ??? Probably not safe to set this here, since it assumes that a |
10120 | function will be emitted as assembly immediately after we generate | |
10121 | RTL for it. This does not happen for inline functions. */ | |
10122 | return_used_this_function = 0; | |
10123 | } | |
10124 | else | |
10125 | { | |
0977774b | 10126 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 10127 | offsets = arm_get_frame_offsets (); |
0977774b | 10128 | |
e6d29d15 NS |
10129 | gcc_assert (!use_return_insn (FALSE, NULL) |
10130 | || !return_used_this_function | |
10131 | || offsets->saved_regs == offsets->outgoing_args | |
10132 | || frame_pointer_needed); | |
f3bb6135 | 10133 | |
d5b7b3ae | 10134 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
10135 | after_arm_reorg = 0; |
10136 | } | |
f3bb6135 | 10137 | } |
e2c671ba | 10138 | |
2c849145 JM |
10139 | /* Generate and emit an insn that we will recognize as a push_multi. |
10140 | Unfortunately, since this insn does not reflect very well the actual | |
10141 | semantics of the operation, we need to annotate the insn for the benefit | |
10142 | of DWARF2 frame unwind information. */ | |
2c849145 | 10143 | static rtx |
b279b20a | 10144 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
10145 | { |
10146 | int num_regs = 0; | |
9b598fa0 | 10147 | int num_dwarf_regs; |
e2c671ba RE |
10148 | int i, j; |
10149 | rtx par; | |
2c849145 | 10150 | rtx dwarf; |
87e27392 | 10151 | int dwarf_par_index; |
2c849145 | 10152 | rtx tmp, reg; |
e2c671ba | 10153 | |
d5b7b3ae | 10154 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 10155 | if (mask & (1 << i)) |
5895f793 | 10156 | num_regs++; |
e2c671ba | 10157 | |
e6d29d15 | 10158 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 10159 | |
9b598fa0 RE |
10160 | /* We don't record the PC in the dwarf frame information. */ |
10161 | num_dwarf_regs = num_regs; | |
10162 | if (mask & (1 << PC_REGNUM)) | |
10163 | num_dwarf_regs--; | |
10164 | ||
87e27392 | 10165 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 10166 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
10167 | by the push_multi pattern in the arm.md file. The insn looks |
10168 | something like this: | |
10169 | ||
f676971a | 10170 | (parallel [ |
b15bca31 RE |
10171 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
10172 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
10173 | (use (reg:SI 11 fp)) |
10174 | (use (reg:SI 12 ip)) | |
10175 | (use (reg:SI 14 lr)) | |
10176 | (use (reg:SI 15 pc)) | |
10177 | ]) | |
10178 | ||
10179 | For the frame note however, we try to be more explicit and actually | |
10180 | show each register being stored into the stack frame, plus a (single) | |
10181 | decrement of the stack pointer. We do it this way in order to be | |
10182 | friendly to the stack unwinding code, which only wants to see a single | |
10183 | stack decrement per instruction. The RTL we generate for the note looks | |
10184 | something like this: | |
10185 | ||
f676971a | 10186 | (sequence [ |
87e27392 NC |
10187 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
10188 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
10189 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
10190 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
10191 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
10192 | ]) |
10193 | ||
10194 | This sequence is used both by the code to support stack unwinding for | |
10195 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
f676971a | 10196 | |
43cffd11 | 10197 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 10198 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 10199 | dwarf_par_index = 1; |
e2c671ba | 10200 | |
d5b7b3ae | 10201 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
10202 | { |
10203 | if (mask & (1 << i)) | |
10204 | { | |
2c849145 JM |
10205 | reg = gen_rtx_REG (SImode, i); |
10206 | ||
e2c671ba | 10207 | XVECEXP (par, 0, 0) |
43cffd11 | 10208 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
10209 | gen_frame_mem (BLKmode, |
10210 | gen_rtx_PRE_DEC (BLKmode, | |
10211 | stack_pointer_rtx)), | |
43cffd11 | 10212 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 10213 | gen_rtvec (1, reg), |
9b598fa0 | 10214 | UNSPEC_PUSH_MULT)); |
2c849145 | 10215 | |
9b598fa0 RE |
10216 | if (i != PC_REGNUM) |
10217 | { | |
10218 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 10219 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
10220 | reg); |
10221 | RTX_FRAME_RELATED_P (tmp) = 1; | |
10222 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
10223 | dwarf_par_index++; | |
10224 | } | |
2c849145 | 10225 | |
e2c671ba RE |
10226 | break; |
10227 | } | |
10228 | } | |
10229 | ||
10230 | for (j = 1, i++; j < num_regs; i++) | |
10231 | { | |
10232 | if (mask & (1 << i)) | |
10233 | { | |
2c849145 JM |
10234 | reg = gen_rtx_REG (SImode, i); |
10235 | ||
10236 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
10237 | ||
9b598fa0 RE |
10238 | if (i != PC_REGNUM) |
10239 | { | |
31fa16b6 RE |
10240 | tmp |
10241 | = gen_rtx_SET (VOIDmode, | |
10242 | gen_frame_mem (SImode, | |
9b598fa0 RE |
10243 | plus_constant (stack_pointer_rtx, |
10244 | 4 * j)), | |
31fa16b6 | 10245 | reg); |
9b598fa0 RE |
10246 | RTX_FRAME_RELATED_P (tmp) = 1; |
10247 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
10248 | } | |
10249 | ||
e2c671ba RE |
10250 | j++; |
10251 | } | |
10252 | } | |
b111229a | 10253 | |
2c849145 | 10254 | par = emit_insn (par); |
f676971a | 10255 | |
d66437c5 | 10256 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 10257 | stack_pointer_rtx, |
d66437c5 | 10258 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
10259 | RTX_FRAME_RELATED_P (tmp) = 1; |
10260 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 10261 | |
2c849145 JM |
10262 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
10263 | REG_NOTES (par)); | |
10264 | return par; | |
b111229a RE |
10265 | } |
10266 | ||
4f5dfed0 JC |
10267 | /* Calculate the size of the return value that is passed in registers. */ |
10268 | static int | |
10269 | arm_size_return_regs (void) | |
10270 | { | |
10271 | enum machine_mode mode; | |
10272 | ||
10273 | if (current_function_return_rtx != 0) | |
10274 | mode = GET_MODE (current_function_return_rtx); | |
10275 | else | |
10276 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
10277 | ||
10278 | return GET_MODE_SIZE (mode); | |
10279 | } | |
10280 | ||
2c849145 | 10281 | static rtx |
e32bac5b | 10282 | emit_sfm (int base_reg, int count) |
b111229a RE |
10283 | { |
10284 | rtx par; | |
2c849145 JM |
10285 | rtx dwarf; |
10286 | rtx tmp, reg; | |
b111229a RE |
10287 | int i; |
10288 | ||
43cffd11 | 10289 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 10290 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
10291 | |
10292 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
10293 | |
10294 | XVECEXP (par, 0, 0) | |
f676971a | 10295 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
10296 | gen_frame_mem (BLKmode, |
10297 | gen_rtx_PRE_DEC (BLKmode, | |
10298 | stack_pointer_rtx)), | |
43cffd11 | 10299 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 10300 | gen_rtvec (1, reg), |
b15bca31 | 10301 | UNSPEC_PUSH_MULT)); |
f676971a | 10302 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 10303 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 10304 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
10305 | XVECEXP (dwarf, 0, 1) = tmp; |
10306 | ||
b111229a | 10307 | for (i = 1; i < count; i++) |
2c849145 JM |
10308 | { |
10309 | reg = gen_rtx_REG (XFmode, base_reg++); | |
10310 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
10311 | ||
f676971a | 10312 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
10313 | gen_frame_mem (XFmode, |
10314 | plus_constant (stack_pointer_rtx, | |
10315 | i * 12)), | |
2c849145 JM |
10316 | reg); |
10317 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 10318 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 10319 | } |
b111229a | 10320 | |
8ee6eb4e PB |
10321 | tmp = gen_rtx_SET (VOIDmode, |
10322 | stack_pointer_rtx, | |
d66437c5 RE |
10323 | plus_constant (stack_pointer_rtx, -12 * count)); |
10324 | ||
8ee6eb4e PB |
10325 | RTX_FRAME_RELATED_P (tmp) = 1; |
10326 | XVECEXP (dwarf, 0, 0) = tmp; | |
10327 | ||
2c849145 JM |
10328 | par = emit_insn (par); |
10329 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
10330 | REG_NOTES (par)); | |
10331 | return par; | |
e2c671ba RE |
10332 | } |
10333 | ||
9b66ebb1 | 10334 | |
3c7ad43e PB |
10335 | /* Return true if the current function needs to save/restore LR. */ |
10336 | ||
10337 | static bool | |
10338 | thumb_force_lr_save (void) | |
10339 | { | |
10340 | return !cfun->machine->lr_save_eliminated | |
10341 | && (!leaf_function_p () | |
10342 | || thumb_far_jump_used_p () | |
10343 | || regs_ever_live [LR_REGNUM]); | |
10344 | } | |
10345 | ||
10346 | ||
095bb276 NC |
10347 | /* Compute the distance from register FROM to register TO. |
10348 | These can be the arg pointer (26), the soft frame pointer (25), | |
10349 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 10350 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
10351 | Typical stack layout looks like this: |
10352 | ||
10353 | old stack pointer -> | | | |
10354 | ---- | |
10355 | | | \ | |
10356 | | | saved arguments for | |
10357 | | | vararg functions | |
10358 | | | / | |
10359 | -- | |
10360 | hard FP & arg pointer -> | | \ | |
10361 | | | stack | |
10362 | | | frame | |
10363 | | | / | |
10364 | -- | |
10365 | | | \ | |
10366 | | | call saved | |
10367 | | | registers | |
10368 | soft frame pointer -> | | / | |
10369 | -- | |
10370 | | | \ | |
10371 | | | local | |
10372 | | | variables | |
2591db65 | 10373 | locals base pointer -> | | / |
095bb276 NC |
10374 | -- |
10375 | | | \ | |
10376 | | | outgoing | |
10377 | | | arguments | |
10378 | current stack pointer -> | | / | |
10379 | -- | |
10380 | ||
43aa4e05 | 10381 | For a given function some or all of these stack components |
095bb276 NC |
10382 | may not be needed, giving rise to the possibility of |
10383 | eliminating some of the registers. | |
10384 | ||
825dda42 | 10385 | The values returned by this function must reflect the behavior |
095bb276 NC |
10386 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
10387 | ||
10388 | The sign of the number returned reflects the direction of stack | |
10389 | growth, so the values are positive for all eliminations except | |
5848830f PB |
10390 | from the soft frame pointer to the hard frame pointer. |
10391 | ||
10392 | SFP may point just inside the local variables block to ensure correct | |
10393 | alignment. */ | |
10394 | ||
10395 | ||
10396 | /* Calculate stack offsets. These are used to calculate register elimination | |
10397 | offsets and in prologue/epilogue code. */ | |
10398 | ||
10399 | static arm_stack_offsets * | |
10400 | arm_get_frame_offsets (void) | |
095bb276 | 10401 | { |
5848830f | 10402 | struct arm_stack_offsets *offsets; |
095bb276 | 10403 | unsigned long func_type; |
5848830f | 10404 | int leaf; |
5848830f PB |
10405 | int saved; |
10406 | HOST_WIDE_INT frame_size; | |
10407 | ||
10408 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 10409 | |
5848830f PB |
10410 | /* We need to know if we are a leaf function. Unfortunately, it |
10411 | is possible to be called after start_sequence has been called, | |
10412 | which causes get_insns to return the insns for the sequence, | |
10413 | not the function, which will cause leaf_function_p to return | |
10414 | the incorrect result. | |
095bb276 | 10415 | |
5848830f PB |
10416 | to know about leaf functions once reload has completed, and the |
10417 | frame size cannot be changed after that time, so we can safely | |
10418 | use the cached value. */ | |
10419 | ||
10420 | if (reload_completed) | |
10421 | return offsets; | |
10422 | ||
666c27b9 KH |
10423 | /* Initially this is the size of the local variables. It will translated |
10424 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
10425 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
10426 | ||
10427 | leaf = leaf_function_p (); | |
10428 | ||
10429 | /* Space for variadic functions. */ | |
10430 | offsets->saved_args = current_function_pretend_args_size; | |
10431 | ||
10432 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0); | |
10433 | ||
10434 | if (TARGET_ARM) | |
095bb276 | 10435 | { |
5848830f | 10436 | unsigned int regno; |
ef7112de | 10437 | |
5848830f | 10438 | saved = bit_count (arm_compute_save_reg_mask ()) * 4; |
5a9335ef | 10439 | |
5848830f PB |
10440 | /* We know that SP will be doubleword aligned on entry, and we must |
10441 | preserve that condition at any subroutine call. We also require the | |
10442 | soft frame pointer to be doubleword aligned. */ | |
10443 | ||
10444 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 10445 | { |
5848830f PB |
10446 | /* Check for the call-saved iWMMXt registers. */ |
10447 | for (regno = FIRST_IWMMXT_REGNUM; | |
10448 | regno <= LAST_IWMMXT_REGNUM; | |
10449 | regno++) | |
10450 | if (regs_ever_live [regno] && ! call_used_regs [regno]) | |
10451 | saved += 8; | |
10452 | } | |
10453 | ||
10454 | func_type = arm_current_func_type (); | |
10455 | if (! IS_VOLATILE (func_type)) | |
10456 | { | |
10457 | /* Space for saved FPA registers. */ | |
10458 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
10459 | if (regs_ever_live[regno] && ! call_used_regs[regno]) | |
10460 | saved += 12; | |
10461 | ||
10462 | /* Space for saved VFP registers. */ | |
10463 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 10464 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 10465 | } |
5848830f PB |
10466 | } |
10467 | else /* TARGET_THUMB */ | |
10468 | { | |
57934c39 | 10469 | saved = bit_count (thumb_compute_save_reg_mask ()) * 4; |
5848830f | 10470 | if (TARGET_BACKTRACE) |
57934c39 | 10471 | saved += 16; |
5848830f | 10472 | } |
9b66ebb1 | 10473 | |
5848830f PB |
10474 | /* Saved registers include the stack frame. */ |
10475 | offsets->saved_regs = offsets->saved_args + saved; | |
a2503645 | 10476 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
10477 | /* A leaf function does not need any stack alignment if it has nothing |
10478 | on the stack. */ | |
10479 | if (leaf && frame_size == 0) | |
10480 | { | |
10481 | offsets->outgoing_args = offsets->soft_frame; | |
10482 | return offsets; | |
10483 | } | |
10484 | ||
10485 | /* Ensure SFP has the correct alignment. */ | |
10486 | if (ARM_DOUBLEWORD_ALIGN | |
10487 | && (offsets->soft_frame & 7)) | |
10488 | offsets->soft_frame += 4; | |
10489 | ||
2591db65 RE |
10490 | offsets->locals_base = offsets->soft_frame + frame_size; |
10491 | offsets->outgoing_args = (offsets->locals_base | |
10492 | + current_function_outgoing_args_size); | |
5848830f PB |
10493 | |
10494 | if (ARM_DOUBLEWORD_ALIGN) | |
10495 | { | |
10496 | /* Ensure SP remains doubleword aligned. */ | |
10497 | if (offsets->outgoing_args & 7) | |
10498 | offsets->outgoing_args += 4; | |
e6d29d15 | 10499 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
10500 | } |
10501 | ||
5848830f PB |
10502 | return offsets; |
10503 | } | |
10504 | ||
10505 | ||
666c27b9 | 10506 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
10507 | offsets are in the direction of stack growth. */ |
10508 | ||
b3f8d95d | 10509 | HOST_WIDE_INT |
5848830f PB |
10510 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
10511 | { | |
10512 | arm_stack_offsets *offsets; | |
10513 | ||
10514 | offsets = arm_get_frame_offsets (); | |
095bb276 | 10515 | |
095bb276 NC |
10516 | /* OK, now we have enough information to compute the distances. |
10517 | There must be an entry in these switch tables for each pair | |
10518 | of registers in ELIMINABLE_REGS, even if some of the entries | |
10519 | seem to be redundant or useless. */ | |
10520 | switch (from) | |
10521 | { | |
10522 | case ARG_POINTER_REGNUM: | |
10523 | switch (to) | |
10524 | { | |
10525 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
10526 | return 0; | |
10527 | ||
10528 | case FRAME_POINTER_REGNUM: | |
10529 | /* This is the reverse of the soft frame pointer | |
10530 | to hard frame pointer elimination below. */ | |
5848830f | 10531 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
10532 | |
10533 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
10534 | /* If there is no stack frame then the hard | |
10535 | frame pointer and the arg pointer coincide. */ | |
5848830f | 10536 | if (offsets->frame == offsets->saved_regs) |
095bb276 | 10537 | return 0; |
6de9cd9a DN |
10538 | /* FIXME: Not sure about this. Maybe we should always return 0 ? */ |
10539 | return (frame_pointer_needed | |
10540 | && cfun->static_chain_decl != NULL | |
10541 | && ! cfun->machine->uses_anonymous_args) ? 4 : 0; | |
095bb276 NC |
10542 | |
10543 | case STACK_POINTER_REGNUM: | |
10544 | /* If nothing has been pushed on the stack at all | |
10545 | then this will return -4. This *is* correct! */ | |
5848830f | 10546 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
10547 | |
10548 | default: | |
e6d29d15 | 10549 | gcc_unreachable (); |
095bb276 | 10550 | } |
e6d29d15 | 10551 | gcc_unreachable (); |
095bb276 NC |
10552 | |
10553 | case FRAME_POINTER_REGNUM: | |
10554 | switch (to) | |
10555 | { | |
10556 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
10557 | return 0; | |
10558 | ||
10559 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
10560 | /* The hard frame pointer points to the top entry in the | |
10561 | stack frame. The soft frame pointer to the bottom entry | |
10562 | in the stack frame. If there is no stack frame at all, | |
10563 | then they are identical. */ | |
5848830f PB |
10564 | |
10565 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
10566 | |
10567 | case STACK_POINTER_REGNUM: | |
5848830f | 10568 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
10569 | |
10570 | default: | |
e6d29d15 | 10571 | gcc_unreachable (); |
095bb276 | 10572 | } |
e6d29d15 | 10573 | gcc_unreachable (); |
095bb276 NC |
10574 | |
10575 | default: | |
10576 | /* You cannot eliminate from the stack pointer. | |
10577 | In theory you could eliminate from the hard frame | |
10578 | pointer to the stack pointer, but this will never | |
10579 | happen, since if a stack frame is not needed the | |
10580 | hard frame pointer will never be used. */ | |
e6d29d15 | 10581 | gcc_unreachable (); |
095bb276 NC |
10582 | } |
10583 | } | |
10584 | ||
0977774b | 10585 | |
6d3d9133 | 10586 | /* Generate the prologue instructions for entry into an ARM function. */ |
e2c671ba | 10587 | void |
e32bac5b | 10588 | arm_expand_prologue (void) |
e2c671ba RE |
10589 | { |
10590 | int reg; | |
6d3d9133 | 10591 | rtx amount; |
2c849145 | 10592 | rtx insn; |
68dfd979 | 10593 | rtx ip_rtx; |
6d3d9133 NC |
10594 | unsigned long live_regs_mask; |
10595 | unsigned long func_type; | |
68dfd979 | 10596 | int fp_offset = 0; |
095bb276 | 10597 | int saved_pretend_args = 0; |
5848830f | 10598 | int saved_regs = 0; |
b9705a21 | 10599 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 10600 | arm_stack_offsets *offsets; |
d3236b4d | 10601 | |
6d3d9133 | 10602 | func_type = arm_current_func_type (); |
e2c671ba | 10603 | |
31fdb4d5 | 10604 | /* Naked functions don't have prologues. */ |
6d3d9133 | 10605 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
10606 | return; |
10607 | ||
095bb276 NC |
10608 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
10609 | args_to_push = current_function_pretend_args_size; | |
f676971a | 10610 | |
6d3d9133 NC |
10611 | /* Compute which register we will have to save onto the stack. */ |
10612 | live_regs_mask = arm_compute_save_reg_mask (); | |
e2c671ba | 10613 | |
68dfd979 | 10614 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 10615 | |
e2c671ba RE |
10616 | if (frame_pointer_needed) |
10617 | { | |
7b8b8ade NC |
10618 | if (IS_INTERRUPT (func_type)) |
10619 | { | |
10620 | /* Interrupt functions must not corrupt any registers. | |
10621 | Creating a frame pointer however, corrupts the IP | |
10622 | register, so we must push it first. */ | |
10623 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
10624 | |
10625 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
10626 | The dwarf stack unwinding code only wants to see one | |
10627 | stack decrement per function, and this is not it. If | |
10628 | this instruction is labeled as being part of the frame | |
10629 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 10630 | die when it encounters the assignment of IP to FP |
121308d4 NC |
10631 | later on, since the use of SP here establishes SP as |
10632 | the CFA register and not IP. | |
10633 | ||
10634 | Anyway this instruction is not really part of the stack | |
10635 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
10636 | } |
10637 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
10638 | { |
10639 | /* The Static chain register is the same as the IP register | |
10640 | used as a scratch register during stack frame creation. | |
10641 | To get around this need to find somewhere to store IP | |
10642 | whilst the frame is being created. We try the following | |
10643 | places in order: | |
f676971a | 10644 | |
6d3d9133 | 10645 | 1. The last argument register. |
68dfd979 NC |
10646 | 2. A slot on the stack above the frame. (This only |
10647 | works if the function is not a varargs function). | |
095bb276 NC |
10648 | 3. Register r3, after pushing the argument registers |
10649 | onto the stack. | |
6d3d9133 | 10650 | |
34ce3d7b JM |
10651 | Note - we only need to tell the dwarf2 backend about the SP |
10652 | adjustment in the second variant; the static chain register | |
10653 | doesn't need to be unwound, as it doesn't contain a value | |
10654 | inherited from the caller. */ | |
d3236b4d | 10655 | |
68dfd979 | 10656 | if (regs_ever_live[3] == 0) |
d66437c5 | 10657 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 10658 | else if (args_to_push == 0) |
68dfd979 | 10659 | { |
34ce3d7b | 10660 | rtx dwarf; |
34ce3d7b | 10661 | |
d66437c5 RE |
10662 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
10663 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 10664 | fp_offset = 4; |
34ce3d7b JM |
10665 | |
10666 | /* Just tell the dwarf backend that we adjusted SP. */ | |
10667 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
10668 | plus_constant (stack_pointer_rtx, |
10669 | -fp_offset)); | |
34ce3d7b JM |
10670 | RTX_FRAME_RELATED_P (insn) = 1; |
10671 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10672 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
10673 | } |
10674 | else | |
095bb276 NC |
10675 | { |
10676 | /* Store the args on the stack. */ | |
3cb66fd7 | 10677 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
10678 | insn = emit_multi_reg_push |
10679 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
10680 | else | |
10681 | insn = emit_insn | |
f676971a | 10682 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
10683 | GEN_INT (- args_to_push))); |
10684 | ||
10685 | RTX_FRAME_RELATED_P (insn) = 1; | |
10686 | ||
10687 | saved_pretend_args = 1; | |
10688 | fp_offset = args_to_push; | |
10689 | args_to_push = 0; | |
10690 | ||
10691 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 10692 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 10693 | } |
68dfd979 NC |
10694 | } |
10695 | ||
d66437c5 RE |
10696 | insn = emit_set_insn (ip_rtx, |
10697 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 10698 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
10699 | } |
10700 | ||
095bb276 | 10701 | if (args_to_push) |
e2c671ba | 10702 | { |
6d3d9133 | 10703 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 10704 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 10705 | insn = emit_multi_reg_push |
095bb276 | 10706 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 10707 | else |
2c849145 | 10708 | insn = emit_insn |
f676971a | 10709 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 10710 | GEN_INT (- args_to_push))); |
2c849145 | 10711 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
10712 | } |
10713 | ||
06bea5aa NC |
10714 | /* If this is an interrupt service routine, and the link register |
10715 | is going to be pushed, and we are not creating a stack frame, | |
10716 | (which would involve an extra push of IP and a pop in the epilogue) | |
10717 | subtracting four from LR now will mean that the function return | |
10718 | can be done with a single instruction. */ | |
3a7731fd | 10719 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa NC |
10720 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
10721 | && ! frame_pointer_needed) | |
d66437c5 RE |
10722 | { |
10723 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
10724 | ||
10725 | emit_set_insn (lr, plus_constant (lr, -4)); | |
10726 | } | |
3a7731fd | 10727 | |
e2c671ba RE |
10728 | if (live_regs_mask) |
10729 | { | |
2c849145 | 10730 | insn = emit_multi_reg_push (live_regs_mask); |
5848830f | 10731 | saved_regs += bit_count (live_regs_mask) * 4; |
2c849145 | 10732 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 10733 | } |
d5b7b3ae | 10734 | |
5a9335ef | 10735 | if (TARGET_IWMMXT) |
01d4c813 | 10736 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
5a9335ef NC |
10737 | if (regs_ever_live[reg] && ! call_used_regs [reg]) |
10738 | { | |
10739 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
31fa16b6 | 10740 | insn = gen_frame_mem (V2SImode, insn); |
d66437c5 | 10741 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); |
5a9335ef | 10742 | RTX_FRAME_RELATED_P (insn) = 1; |
5848830f | 10743 | saved_regs += 8; |
5a9335ef NC |
10744 | } |
10745 | ||
6d3d9133 | 10746 | if (! IS_VOLATILE (func_type)) |
b111229a | 10747 | { |
9b66ebb1 PB |
10748 | int start_reg; |
10749 | ||
29ad9694 RE |
10750 | /* Save any floating point call-saved registers used by this |
10751 | function. */ | |
10752 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
b111229a | 10753 | { |
9b66ebb1 | 10754 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
5895f793 | 10755 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
2c849145 JM |
10756 | { |
10757 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
31fa16b6 | 10758 | insn = gen_frame_mem (XFmode, insn); |
d66437c5 | 10759 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); |
2c849145 | 10760 | RTX_FRAME_RELATED_P (insn) = 1; |
5848830f | 10761 | saved_regs += 12; |
2c849145 | 10762 | } |
b111229a RE |
10763 | } |
10764 | else | |
10765 | { | |
9b66ebb1 | 10766 | start_reg = LAST_FPA_REGNUM; |
b111229a | 10767 | |
9b66ebb1 | 10768 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 10769 | { |
5895f793 | 10770 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
10771 | { |
10772 | if (start_reg - reg == 3) | |
10773 | { | |
2c849145 JM |
10774 | insn = emit_sfm (reg, 4); |
10775 | RTX_FRAME_RELATED_P (insn) = 1; | |
4b763d77 | 10776 | saved_regs += 48; |
b111229a RE |
10777 | start_reg = reg - 1; |
10778 | } | |
10779 | } | |
10780 | else | |
10781 | { | |
10782 | if (start_reg != reg) | |
2c849145 JM |
10783 | { |
10784 | insn = emit_sfm (reg + 1, start_reg - reg); | |
10785 | RTX_FRAME_RELATED_P (insn) = 1; | |
7aebacee | 10786 | saved_regs += (start_reg - reg) * 12; |
2c849145 | 10787 | } |
b111229a RE |
10788 | start_reg = reg - 1; |
10789 | } | |
10790 | } | |
10791 | ||
10792 | if (start_reg != reg) | |
2c849145 JM |
10793 | { |
10794 | insn = emit_sfm (reg + 1, start_reg - reg); | |
7aebacee | 10795 | saved_regs += (start_reg - reg) * 12; |
2c849145 JM |
10796 | RTX_FRAME_RELATED_P (insn) = 1; |
10797 | } | |
b111229a | 10798 | } |
9b66ebb1 PB |
10799 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
10800 | { | |
10801 | start_reg = FIRST_VFP_REGNUM; | |
10802 | ||
10803 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
10804 | { | |
10805 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
10806 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
10807 | { | |
10808 | if (start_reg != reg) | |
9728c9d1 PB |
10809 | saved_regs += vfp_emit_fstmx (start_reg, |
10810 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
10811 | start_reg = reg + 2; |
10812 | } | |
10813 | } | |
10814 | if (start_reg != reg) | |
9728c9d1 PB |
10815 | saved_regs += vfp_emit_fstmx (start_reg, |
10816 | (reg - start_reg) / 2); | |
9b66ebb1 | 10817 | } |
b111229a | 10818 | } |
e2c671ba RE |
10819 | |
10820 | if (frame_pointer_needed) | |
2c849145 | 10821 | { |
6d3d9133 | 10822 | /* Create the new frame pointer. */ |
095bb276 | 10823 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
68dfd979 | 10824 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); |
2c849145 | 10825 | RTX_FRAME_RELATED_P (insn) = 1; |
f676971a | 10826 | |
6d3d9133 | 10827 | if (IS_NESTED (func_type)) |
68dfd979 NC |
10828 | { |
10829 | /* Recover the static chain register. */ | |
095bb276 NC |
10830 | if (regs_ever_live [3] == 0 |
10831 | || saved_pretend_args) | |
1d6e90ac | 10832 | insn = gen_rtx_REG (SImode, 3); |
68dfd979 NC |
10833 | else /* if (current_function_pretend_args_size == 0) */ |
10834 | { | |
d66437c5 | 10835 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
31fa16b6 | 10836 | insn = gen_frame_mem (SImode, insn); |
68dfd979 | 10837 | } |
1d6e90ac | 10838 | |
d66437c5 | 10839 | emit_set_insn (ip_rtx, insn); |
c14a3a45 | 10840 | /* Add a USE to stop propagate_one_insn() from barfing. */ |
6bacc7b0 | 10841 | emit_insn (gen_prologue_use (ip_rtx)); |
68dfd979 | 10842 | } |
2c849145 | 10843 | } |
e2c671ba | 10844 | |
5848830f PB |
10845 | offsets = arm_get_frame_offsets (); |
10846 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) | |
e2c671ba | 10847 | { |
745b9093 JM |
10848 | /* This add can produce multiple insns for a large constant, so we |
10849 | need to get tricky. */ | |
10850 | rtx last = get_last_insn (); | |
5848830f PB |
10851 | |
10852 | amount = GEN_INT (offsets->saved_args + saved_regs | |
10853 | - offsets->outgoing_args); | |
10854 | ||
2c849145 JM |
10855 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
10856 | amount)); | |
745b9093 JM |
10857 | do |
10858 | { | |
10859 | last = last ? NEXT_INSN (last) : get_insns (); | |
10860 | RTX_FRAME_RELATED_P (last) = 1; | |
10861 | } | |
10862 | while (last != insn); | |
e04c2d6c RE |
10863 | |
10864 | /* If the frame pointer is needed, emit a special barrier that | |
10865 | will prevent the scheduler from moving stores to the frame | |
10866 | before the stack adjustment. */ | |
10867 | if (frame_pointer_needed) | |
3894f59e RE |
10868 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
10869 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
10870 | } |
10871 | ||
876f13b0 | 10872 | |
020a4035 | 10873 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 10874 | arm_load_pic_register (0UL); |
876f13b0 | 10875 | |
e2c671ba | 10876 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 10877 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
10878 | scheduling in the prolog. Similarly if we want non-call exceptions |
10879 | using the EABI unwinder, to prevent faulting instructions from being | |
10880 | swapped with a stack adjustment. */ | |
10881 | if (current_function_profile || !TARGET_SCHED_PROLOG | |
10882 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) | |
e2c671ba | 10883 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
10884 | |
10885 | /* If the link register is being kept alive, with the return address in it, | |
10886 | then make sure that it does not get reused by the ce2 pass. */ | |
10887 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
10888 | { | |
6bacc7b0 | 10889 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); |
6f7ebcbb NC |
10890 | cfun->machine->lr_save_eliminated = 1; |
10891 | } | |
e2c671ba | 10892 | } |
cce8749e | 10893 | \f |
9997d19d RE |
10894 | /* If CODE is 'd', then the X is a condition operand and the instruction |
10895 | should only be executed if the condition is true. | |
ddd5a7c1 | 10896 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
10897 | should only be executed if the condition is false: however, if the mode |
10898 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
10899 | do this because in these circumstances !GE does not necessarily imply LT; | |
10900 | in these cases the instruction pattern will take care to make sure that | |
10901 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 10902 | doing this instruction unconditionally. |
9997d19d RE |
10903 | If CODE is 'N' then X is a floating point operand that must be negated |
10904 | before output. | |
10905 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
10906 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 10907 | void |
e32bac5b | 10908 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
10909 | { |
10910 | switch (code) | |
10911 | { | |
10912 | case '@': | |
f3139301 | 10913 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
10914 | return; |
10915 | ||
d5b7b3ae RE |
10916 | case '_': |
10917 | fputs (user_label_prefix, stream); | |
10918 | return; | |
f676971a | 10919 | |
9997d19d | 10920 | case '|': |
f3139301 | 10921 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
10922 | return; |
10923 | ||
10924 | case '?': | |
10925 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
cca0a211 | 10926 | { |
22de4c3d RE |
10927 | if (TARGET_THUMB) |
10928 | { | |
10929 | output_operand_lossage ("predicated Thumb instruction"); | |
10930 | break; | |
10931 | } | |
10932 | if (current_insn_predicate != NULL) | |
10933 | { | |
10934 | output_operand_lossage | |
10935 | ("predicated instruction in conditional sequence"); | |
10936 | break; | |
10937 | } | |
cca0a211 RE |
10938 | |
10939 | fputs (arm_condition_codes[arm_current_cc], stream); | |
10940 | } | |
10941 | else if (current_insn_predicate) | |
10942 | { | |
10943 | enum arm_cond_code code; | |
10944 | ||
10945 | if (TARGET_THUMB) | |
22de4c3d RE |
10946 | { |
10947 | output_operand_lossage ("predicated Thumb instruction"); | |
10948 | break; | |
10949 | } | |
cca0a211 RE |
10950 | |
10951 | code = get_arm_condition_code (current_insn_predicate); | |
10952 | fputs (arm_condition_codes[code], stream); | |
10953 | } | |
9997d19d RE |
10954 | return; |
10955 | ||
10956 | case 'N': | |
10957 | { | |
10958 | REAL_VALUE_TYPE r; | |
10959 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
10960 | r = REAL_VALUE_NEGATE (r); | |
10961 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
10962 | } | |
10963 | return; | |
10964 | ||
10965 | case 'B': | |
10966 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
10967 | { |
10968 | HOST_WIDE_INT val; | |
5895f793 | 10969 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 10970 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 10971 | } |
9997d19d RE |
10972 | else |
10973 | { | |
10974 | putc ('~', stream); | |
10975 | output_addr_const (stream, x); | |
10976 | } | |
10977 | return; | |
10978 | ||
10979 | case 'i': | |
10980 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
10981 | return; | |
10982 | ||
9b6b54e2 NC |
10983 | /* Truncate Cirrus shift counts. */ |
10984 | case 's': | |
10985 | if (GET_CODE (x) == CONST_INT) | |
10986 | { | |
10987 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
10988 | return; | |
10989 | } | |
10990 | arm_print_operand (stream, x, 0); | |
10991 | return; | |
10992 | ||
9997d19d RE |
10993 | case 'I': |
10994 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
10995 | return; | |
10996 | ||
10997 | case 'S': | |
10998 | { | |
10999 | HOST_WIDE_INT val; | |
5895f793 | 11000 | const char * shift = shift_op (x, &val); |
9997d19d | 11001 | |
e2c671ba RE |
11002 | if (shift) |
11003 | { | |
5895f793 | 11004 | fprintf (stream, ", %s ", shift_op (x, &val)); |
e2c671ba RE |
11005 | if (val == -1) |
11006 | arm_print_operand (stream, XEXP (x, 1), 0); | |
11007 | else | |
4a0a75dd | 11008 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 11009 | } |
9997d19d RE |
11010 | } |
11011 | return; | |
11012 | ||
d5b7b3ae | 11013 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 11014 | |
d5b7b3ae RE |
11015 | In a pair of registers containing a DI or DF value the 'Q' |
11016 | operand returns the register number of the register containing | |
093354e0 | 11017 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
11018 | the register number of the register containing the most |
11019 | significant part of the value. | |
f676971a | 11020 | |
d5b7b3ae RE |
11021 | The 'H' operand returns the higher of the two register numbers. |
11022 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 11023 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
11024 | value is held in the lower number register. The reverse is true |
11025 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 11026 | |
d5b7b3ae RE |
11027 | The purpose of these operands is to distinguish between cases |
11028 | where the endian-ness of the values is important (for example | |
11029 | when they are added together), and cases where the endian-ness | |
11030 | is irrelevant, but the order of register operations is important. | |
11031 | For example when loading a value from memory into a register | |
11032 | pair, the endian-ness does not matter. Provided that the value | |
11033 | from the lower memory address is put into the lower numbered | |
11034 | register, and the value from the higher address is put into the | |
11035 | higher numbered register, the load will work regardless of whether | |
11036 | the value being loaded is big-wordian or little-wordian. The | |
11037 | order of the two register loads can matter however, if the address | |
11038 | of the memory location is actually held in one of the registers | |
11039 | being overwritten by the load. */ | |
c1c2bc04 | 11040 | case 'Q': |
22de4c3d RE |
11041 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
11042 | { | |
11043 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11044 | return; | |
11045 | } | |
11046 | ||
d5b7b3ae | 11047 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
11048 | return; |
11049 | ||
9997d19d | 11050 | case 'R': |
22de4c3d RE |
11051 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
11052 | { | |
11053 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11054 | return; | |
11055 | } | |
11056 | ||
d5b7b3ae RE |
11057 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
11058 | return; | |
11059 | ||
11060 | case 'H': | |
22de4c3d RE |
11061 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
11062 | { | |
11063 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11064 | return; | |
11065 | } | |
11066 | ||
d5b7b3ae | 11067 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
11068 | return; |
11069 | ||
11070 | case 'm': | |
f676971a | 11071 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
11072 | GET_CODE (XEXP (x, 0)) == REG |
11073 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
11074 | return; |
11075 | ||
11076 | case 'M': | |
dd18ae56 | 11077 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 11078 | REGNO (x), |
e9d7b180 | 11079 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
11080 | return; |
11081 | ||
11082 | case 'd': | |
64e92a26 RE |
11083 | /* CONST_TRUE_RTX means always -- that's the default. */ |
11084 | if (x == const_true_rtx) | |
d5b7b3ae | 11085 | return; |
f676971a | 11086 | |
22de4c3d RE |
11087 | if (!COMPARISON_P (x)) |
11088 | { | |
11089 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11090 | return; | |
11091 | } | |
11092 | ||
defc0463 RE |
11093 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
11094 | stream); | |
9997d19d RE |
11095 | return; |
11096 | ||
11097 | case 'D': | |
112cdef5 | 11098 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
11099 | want to do that. */ |
11100 | if (x == const_true_rtx) | |
22de4c3d RE |
11101 | { |
11102 | output_operand_lossage ("instruction never exectued"); | |
11103 | return; | |
11104 | } | |
11105 | if (!COMPARISON_P (x)) | |
11106 | { | |
11107 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11108 | return; | |
11109 | } | |
d5b7b3ae | 11110 | |
defc0463 RE |
11111 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
11112 | (get_arm_condition_code (x))], | |
11113 | stream); | |
9997d19d RE |
11114 | return; |
11115 | ||
9b6b54e2 NC |
11116 | /* Cirrus registers can be accessed in a variety of ways: |
11117 | single floating point (f) | |
11118 | double floating point (d) | |
11119 | 32bit integer (fx) | |
11120 | 64bit integer (dx). */ | |
11121 | case 'W': /* Cirrus register in F mode. */ | |
11122 | case 'X': /* Cirrus register in D mode. */ | |
11123 | case 'Y': /* Cirrus register in FX mode. */ | |
11124 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
11125 | gcc_assert (GET_CODE (x) == REG |
11126 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
11127 | |
11128 | fprintf (stream, "mv%s%s", | |
11129 | code == 'W' ? "f" | |
11130 | : code == 'X' ? "d" | |
11131 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
11132 | ||
11133 | return; | |
11134 | ||
11135 | /* Print cirrus register in the mode specified by the register's mode. */ | |
11136 | case 'V': | |
11137 | { | |
11138 | int mode = GET_MODE (x); | |
11139 | ||
11140 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
11141 | { |
11142 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11143 | return; | |
11144 | } | |
9b6b54e2 NC |
11145 | |
11146 | fprintf (stream, "mv%s%s", | |
11147 | mode == DFmode ? "d" | |
11148 | : mode == SImode ? "fx" | |
11149 | : mode == DImode ? "dx" | |
11150 | : "f", reg_names[REGNO (x)] + 2); | |
11151 | ||
11152 | return; | |
11153 | } | |
11154 | ||
5a9335ef NC |
11155 | case 'U': |
11156 | if (GET_CODE (x) != REG | |
11157 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
11158 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
11159 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
11160 | { |
11161 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11162 | return; | |
11163 | } | |
11164 | ||
5a9335ef NC |
11165 | else |
11166 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
11167 | return; | |
11168 | ||
11169 | /* Print an iWMMXt control register name. */ | |
11170 | case 'w': | |
11171 | if (GET_CODE (x) != CONST_INT | |
11172 | || INTVAL (x) < 0 | |
11173 | || INTVAL (x) >= 16) | |
11174 | /* Bad value for wC register number. */ | |
22de4c3d RE |
11175 | { |
11176 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11177 | return; | |
11178 | } | |
11179 | ||
5a9335ef NC |
11180 | else |
11181 | { | |
11182 | static const char * wc_reg_names [16] = | |
11183 | { | |
11184 | "wCID", "wCon", "wCSSF", "wCASF", | |
11185 | "wC4", "wC5", "wC6", "wC7", | |
11186 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
11187 | "wC12", "wC13", "wC14", "wC15" | |
11188 | }; | |
f676971a | 11189 | |
5a9335ef NC |
11190 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
11191 | } | |
11192 | return; | |
11193 | ||
9b66ebb1 PB |
11194 | /* Print a VFP double precision register name. */ |
11195 | case 'P': | |
11196 | { | |
11197 | int mode = GET_MODE (x); | |
11198 | int num; | |
11199 | ||
11200 | if (mode != DImode && mode != DFmode) | |
22de4c3d RE |
11201 | { |
11202 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11203 | return; | |
11204 | } | |
9b66ebb1 PB |
11205 | |
11206 | if (GET_CODE (x) != REG | |
11207 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
11208 | { |
11209 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11210 | return; | |
11211 | } | |
9b66ebb1 PB |
11212 | |
11213 | num = REGNO(x) - FIRST_VFP_REGNUM; | |
11214 | if (num & 1) | |
22de4c3d RE |
11215 | { |
11216 | output_operand_lossage ("invalid operand for code '%c'", code); | |
11217 | return; | |
11218 | } | |
9b66ebb1 PB |
11219 | |
11220 | fprintf (stream, "d%d", num >> 1); | |
11221 | } | |
11222 | return; | |
11223 | ||
9997d19d RE |
11224 | default: |
11225 | if (x == 0) | |
22de4c3d RE |
11226 | { |
11227 | output_operand_lossage ("missing operand"); | |
11228 | return; | |
11229 | } | |
9997d19d | 11230 | |
e6d29d15 | 11231 | switch (GET_CODE (x)) |
9997d19d | 11232 | { |
e6d29d15 NS |
11233 | case REG: |
11234 | asm_fprintf (stream, "%r", REGNO (x)); | |
11235 | break; | |
11236 | ||
11237 | case MEM: | |
9997d19d RE |
11238 | output_memory_reference_mode = GET_MODE (x); |
11239 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
11240 | break; |
11241 | ||
11242 | case CONST_DOUBLE: | |
11243 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
11244 | break; | |
11245 | ||
11246 | default: | |
11247 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d RE |
11248 | fputc ('#', stream); |
11249 | output_addr_const (stream, x); | |
e6d29d15 | 11250 | break; |
9997d19d RE |
11251 | } |
11252 | } | |
11253 | } | |
cce8749e | 11254 | \f |
301d03af RS |
11255 | #ifndef AOF_ASSEMBLER |
11256 | /* Target hook for assembling integer objects. The ARM version needs to | |
11257 | handle word-sized values specially. */ | |
301d03af | 11258 | static bool |
e32bac5b | 11259 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
11260 | { |
11261 | if (size == UNITS_PER_WORD && aligned_p) | |
11262 | { | |
11263 | fputs ("\t.word\t", asm_out_file); | |
11264 | output_addr_const (asm_out_file, x); | |
11265 | ||
11266 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 11267 | .text segment, not in the .data segment. */ |
301d03af RS |
11268 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
11269 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
11270 | { | |
e26053d1 | 11271 | if (GET_CODE (x) == SYMBOL_REF |
14f583b8 | 11272 | && (CONSTANT_POOL_ADDRESS_P (x) |
94428622 | 11273 | || SYMBOL_REF_LOCAL_P (x))) |
301d03af RS |
11274 | fputs ("(GOTOFF)", asm_out_file); |
11275 | else if (GET_CODE (x) == LABEL_REF) | |
11276 | fputs ("(GOTOFF)", asm_out_file); | |
11277 | else | |
11278 | fputs ("(GOT)", asm_out_file); | |
11279 | } | |
11280 | fputc ('\n', asm_out_file); | |
11281 | return true; | |
11282 | } | |
1d6e90ac | 11283 | |
f676971a | 11284 | if (arm_vector_mode_supported_p (GET_MODE (x))) |
5a9335ef NC |
11285 | { |
11286 | int i, units; | |
11287 | ||
e6d29d15 | 11288 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
11289 | |
11290 | units = CONST_VECTOR_NUNITS (x); | |
11291 | ||
11292 | switch (GET_MODE (x)) | |
11293 | { | |
11294 | case V2SImode: size = 4; break; | |
11295 | case V4HImode: size = 2; break; | |
11296 | case V8QImode: size = 1; break; | |
11297 | default: | |
e6d29d15 | 11298 | gcc_unreachable (); |
5a9335ef NC |
11299 | } |
11300 | ||
11301 | for (i = 0; i < units; i++) | |
11302 | { | |
11303 | rtx elt; | |
11304 | ||
11305 | elt = CONST_VECTOR_ELT (x, i); | |
11306 | assemble_integer | |
11307 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
11308 | } | |
11309 | ||
11310 | return true; | |
11311 | } | |
11312 | ||
301d03af RS |
11313 | return default_assemble_integer (x, size, aligned_p); |
11314 | } | |
7abc66b1 JB |
11315 | |
11316 | ||
11317 | /* Add a function to the list of static constructors. */ | |
11318 | ||
11319 | static void | |
11320 | arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) | |
11321 | { | |
11322 | if (!TARGET_AAPCS_BASED) | |
11323 | { | |
11324 | default_named_section_asm_out_constructor (symbol, priority); | |
11325 | return; | |
11326 | } | |
11327 | ||
11328 | /* Put these in the .init_array section, using a special relocation. */ | |
d6b5193b | 11329 | switch_to_section (ctors_section); |
7abc66b1 JB |
11330 | assemble_align (POINTER_SIZE); |
11331 | fputs ("\t.word\t", asm_out_file); | |
11332 | output_addr_const (asm_out_file, symbol); | |
11333 | fputs ("(target1)\n", asm_out_file); | |
11334 | } | |
301d03af RS |
11335 | #endif |
11336 | \f | |
cce8749e CH |
11337 | /* A finite state machine takes care of noticing whether or not instructions |
11338 | can be conditionally executed, and thus decrease execution time and code | |
11339 | size by deleting branch instructions. The fsm is controlled by | |
11340 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
11341 | ||
11342 | /* The state of the fsm controlling condition codes are: | |
11343 | 0: normal, do nothing special | |
11344 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
11345 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
11346 | 3: make instructions conditional | |
11347 | 4: make instructions conditional | |
11348 | ||
11349 | State transitions (state->state by whom under condition): | |
11350 | 0 -> 1 final_prescan_insn if the `target' is a label | |
11351 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
11352 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
11353 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 11354 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
11355 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
11356 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
11357 | (the target insn is arm_target_insn). | |
11358 | ||
ff9940b0 RE |
11359 | If the jump clobbers the conditions then we use states 2 and 4. |
11360 | ||
11361 | A similar thing can be done with conditional return insns. | |
11362 | ||
cce8749e CH |
11363 | XXX In case the `target' is an unconditional branch, this conditionalising |
11364 | of the instructions always reduces code size, but not always execution | |
11365 | time. But then, I want to reduce the code size to somewhere near what | |
11366 | /bin/cc produces. */ | |
11367 | ||
cce8749e CH |
11368 | /* Returns the index of the ARM condition code string in |
11369 | `arm_condition_codes'. COMPARISON should be an rtx like | |
11370 | `(eq (...) (...))'. */ | |
84ed5e79 | 11371 | static enum arm_cond_code |
e32bac5b | 11372 | get_arm_condition_code (rtx comparison) |
cce8749e | 11373 | { |
5165176d | 11374 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
11375 | int code; |
11376 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
11377 | |
11378 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 11379 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
11380 | XEXP (comparison, 1)); |
11381 | ||
11382 | switch (mode) | |
cce8749e | 11383 | { |
84ed5e79 RE |
11384 | case CC_DNEmode: code = ARM_NE; goto dominance; |
11385 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
11386 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
11387 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
11388 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
11389 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
11390 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
11391 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
11392 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
11393 | case CC_DLTUmode: code = ARM_CC; | |
11394 | ||
11395 | dominance: | |
e6d29d15 | 11396 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
11397 | |
11398 | if (comp_code == EQ) | |
11399 | return ARM_INVERSE_CONDITION_CODE (code); | |
11400 | return code; | |
11401 | ||
5165176d | 11402 | case CC_NOOVmode: |
84ed5e79 | 11403 | switch (comp_code) |
5165176d | 11404 | { |
84ed5e79 RE |
11405 | case NE: return ARM_NE; |
11406 | case EQ: return ARM_EQ; | |
11407 | case GE: return ARM_PL; | |
11408 | case LT: return ARM_MI; | |
e6d29d15 | 11409 | default: gcc_unreachable (); |
5165176d RE |
11410 | } |
11411 | ||
11412 | case CC_Zmode: | |
84ed5e79 | 11413 | switch (comp_code) |
5165176d | 11414 | { |
84ed5e79 RE |
11415 | case NE: return ARM_NE; |
11416 | case EQ: return ARM_EQ; | |
e6d29d15 | 11417 | default: gcc_unreachable (); |
5165176d RE |
11418 | } |
11419 | ||
defc0463 RE |
11420 | case CC_Nmode: |
11421 | switch (comp_code) | |
11422 | { | |
11423 | case NE: return ARM_MI; | |
11424 | case EQ: return ARM_PL; | |
e6d29d15 | 11425 | default: gcc_unreachable (); |
defc0463 RE |
11426 | } |
11427 | ||
5165176d | 11428 | case CCFPEmode: |
e45b72c4 RE |
11429 | case CCFPmode: |
11430 | /* These encodings assume that AC=1 in the FPA system control | |
11431 | byte. This allows us to handle all cases except UNEQ and | |
11432 | LTGT. */ | |
84ed5e79 RE |
11433 | switch (comp_code) |
11434 | { | |
11435 | case GE: return ARM_GE; | |
11436 | case GT: return ARM_GT; | |
11437 | case LE: return ARM_LS; | |
11438 | case LT: return ARM_MI; | |
e45b72c4 RE |
11439 | case NE: return ARM_NE; |
11440 | case EQ: return ARM_EQ; | |
11441 | case ORDERED: return ARM_VC; | |
11442 | case UNORDERED: return ARM_VS; | |
11443 | case UNLT: return ARM_LT; | |
11444 | case UNLE: return ARM_LE; | |
11445 | case UNGT: return ARM_HI; | |
11446 | case UNGE: return ARM_PL; | |
11447 | /* UNEQ and LTGT do not have a representation. */ | |
11448 | case UNEQ: /* Fall through. */ | |
11449 | case LTGT: /* Fall through. */ | |
e6d29d15 | 11450 | default: gcc_unreachable (); |
84ed5e79 RE |
11451 | } |
11452 | ||
11453 | case CC_SWPmode: | |
11454 | switch (comp_code) | |
11455 | { | |
11456 | case NE: return ARM_NE; | |
11457 | case EQ: return ARM_EQ; | |
11458 | case GE: return ARM_LE; | |
11459 | case GT: return ARM_LT; | |
11460 | case LE: return ARM_GE; | |
11461 | case LT: return ARM_GT; | |
11462 | case GEU: return ARM_LS; | |
11463 | case GTU: return ARM_CC; | |
11464 | case LEU: return ARM_CS; | |
11465 | case LTU: return ARM_HI; | |
e6d29d15 | 11466 | default: gcc_unreachable (); |
84ed5e79 RE |
11467 | } |
11468 | ||
bd9c7e23 RE |
11469 | case CC_Cmode: |
11470 | switch (comp_code) | |
11471 | { | |
11472 | case LTU: return ARM_CS; | |
11473 | case GEU: return ARM_CC; | |
e6d29d15 | 11474 | default: gcc_unreachable (); |
bd9c7e23 | 11475 | } |
f676971a | 11476 | |
5165176d | 11477 | case CCmode: |
84ed5e79 | 11478 | switch (comp_code) |
5165176d | 11479 | { |
84ed5e79 RE |
11480 | case NE: return ARM_NE; |
11481 | case EQ: return ARM_EQ; | |
11482 | case GE: return ARM_GE; | |
11483 | case GT: return ARM_GT; | |
11484 | case LE: return ARM_LE; | |
11485 | case LT: return ARM_LT; | |
11486 | case GEU: return ARM_CS; | |
11487 | case GTU: return ARM_HI; | |
11488 | case LEU: return ARM_LS; | |
11489 | case LTU: return ARM_CC; | |
e6d29d15 | 11490 | default: gcc_unreachable (); |
5165176d RE |
11491 | } |
11492 | ||
e6d29d15 | 11493 | default: gcc_unreachable (); |
cce8749e | 11494 | } |
f3bb6135 | 11495 | } |
cce8749e | 11496 | |
cce8749e | 11497 | void |
e32bac5b | 11498 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
11499 | { |
11500 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 11501 | rtx body = PATTERN (insn); |
cce8749e CH |
11502 | |
11503 | /* This will be 1 if trying to repeat the trick, and things need to be | |
11504 | reversed if it appears to fail. */ | |
11505 | int reverse = 0; | |
11506 | ||
ff9940b0 RE |
11507 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
11508 | taken are clobbered, even if the rtl suggests otherwise. It also | |
11509 | means that we have to grub around within the jump expression to find | |
11510 | out what the conditions are when the jump isn't taken. */ | |
11511 | int jump_clobbers = 0; | |
f676971a | 11512 | |
6354dc9b | 11513 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 11514 | int seeking_return = 0; |
f676971a | 11515 | |
cce8749e CH |
11516 | /* START_INSN will hold the insn from where we start looking. This is the |
11517 | first insn after the following code_label if REVERSE is true. */ | |
11518 | rtx start_insn = insn; | |
11519 | ||
11520 | /* If in state 4, check if the target branch is reached, in order to | |
11521 | change back to state 0. */ | |
11522 | if (arm_ccfsm_state == 4) | |
11523 | { | |
11524 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
11525 | { |
11526 | arm_target_insn = NULL; | |
11527 | arm_ccfsm_state = 0; | |
11528 | } | |
cce8749e CH |
11529 | return; |
11530 | } | |
11531 | ||
11532 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
11533 | unconditional branch to a label, and immediately following this branch | |
11534 | is the previous target label which is only used once, and the label this | |
11535 | branch jumps to is not too far off. */ | |
11536 | if (arm_ccfsm_state == 3) | |
11537 | { | |
11538 | if (simplejump_p (insn)) | |
11539 | { | |
11540 | start_insn = next_nonnote_insn (start_insn); | |
11541 | if (GET_CODE (start_insn) == BARRIER) | |
11542 | { | |
11543 | /* XXX Isn't this always a barrier? */ | |
11544 | start_insn = next_nonnote_insn (start_insn); | |
11545 | } | |
11546 | if (GET_CODE (start_insn) == CODE_LABEL | |
11547 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
11548 | && LABEL_NUSES (start_insn) == 1) | |
11549 | reverse = TRUE; | |
11550 | else | |
11551 | return; | |
11552 | } | |
ff9940b0 RE |
11553 | else if (GET_CODE (body) == RETURN) |
11554 | { | |
11555 | start_insn = next_nonnote_insn (start_insn); | |
11556 | if (GET_CODE (start_insn) == BARRIER) | |
11557 | start_insn = next_nonnote_insn (start_insn); | |
11558 | if (GET_CODE (start_insn) == CODE_LABEL | |
11559 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
11560 | && LABEL_NUSES (start_insn) == 1) | |
11561 | { | |
11562 | reverse = TRUE; | |
11563 | seeking_return = 1; | |
11564 | } | |
11565 | else | |
11566 | return; | |
11567 | } | |
cce8749e CH |
11568 | else |
11569 | return; | |
11570 | } | |
11571 | ||
e6d29d15 | 11572 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
11573 | if (GET_CODE (insn) != JUMP_INSN) |
11574 | return; | |
11575 | ||
f676971a | 11576 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
11577 | the jump should always come first */ |
11578 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
11579 | body = XVECEXP (body, 0, 0); | |
11580 | ||
cce8749e CH |
11581 | if (reverse |
11582 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
11583 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
11584 | { | |
bd9c7e23 RE |
11585 | int insns_skipped; |
11586 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
11587 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
11588 | int then_not_else = TRUE; | |
ff9940b0 | 11589 | rtx this_insn = start_insn, label = 0; |
cce8749e | 11590 | |
f676971a | 11591 | /* If the jump cannot be done with one instruction, we cannot |
e45b72c4 | 11592 | conditionally execute the instruction in the inverse case. */ |
ff9940b0 | 11593 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 11594 | { |
5bbe2d40 RE |
11595 | jump_clobbers = 1; |
11596 | return; | |
11597 | } | |
f676971a | 11598 | |
cce8749e CH |
11599 | /* Register the insn jumped to. */ |
11600 | if (reverse) | |
ff9940b0 RE |
11601 | { |
11602 | if (!seeking_return) | |
11603 | label = XEXP (SET_SRC (body), 0); | |
11604 | } | |
cce8749e CH |
11605 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
11606 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
11607 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
11608 | { | |
11609 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
11610 | then_not_else = FALSE; | |
11611 | } | |
ff9940b0 RE |
11612 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
11613 | seeking_return = 1; | |
11614 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
11615 | { | |
11616 | seeking_return = 1; | |
11617 | then_not_else = FALSE; | |
11618 | } | |
cce8749e | 11619 | else |
e6d29d15 | 11620 | gcc_unreachable (); |
cce8749e CH |
11621 | |
11622 | /* See how many insns this branch skips, and what kind of insns. If all | |
11623 | insns are okay, and the label or unconditional branch to the same | |
11624 | label is not too far away, succeed. */ | |
11625 | for (insns_skipped = 0; | |
b36ba79f | 11626 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
11627 | { |
11628 | rtx scanbody; | |
11629 | ||
11630 | this_insn = next_nonnote_insn (this_insn); | |
11631 | if (!this_insn) | |
11632 | break; | |
11633 | ||
cce8749e CH |
11634 | switch (GET_CODE (this_insn)) |
11635 | { | |
11636 | case CODE_LABEL: | |
11637 | /* Succeed if it is the target label, otherwise fail since | |
11638 | control falls in from somewhere else. */ | |
11639 | if (this_insn == label) | |
11640 | { | |
ff9940b0 RE |
11641 | if (jump_clobbers) |
11642 | { | |
11643 | arm_ccfsm_state = 2; | |
11644 | this_insn = next_nonnote_insn (this_insn); | |
11645 | } | |
11646 | else | |
11647 | arm_ccfsm_state = 1; | |
cce8749e CH |
11648 | succeed = TRUE; |
11649 | } | |
11650 | else | |
11651 | fail = TRUE; | |
11652 | break; | |
11653 | ||
ff9940b0 | 11654 | case BARRIER: |
cce8749e | 11655 | /* Succeed if the following insn is the target label. |
f676971a EC |
11656 | Otherwise fail. |
11657 | If return insns are used then the last insn in a function | |
6354dc9b | 11658 | will be a barrier. */ |
cce8749e | 11659 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 11660 | if (this_insn && this_insn == label) |
cce8749e | 11661 | { |
ff9940b0 RE |
11662 | if (jump_clobbers) |
11663 | { | |
11664 | arm_ccfsm_state = 2; | |
11665 | this_insn = next_nonnote_insn (this_insn); | |
11666 | } | |
11667 | else | |
11668 | arm_ccfsm_state = 1; | |
cce8749e CH |
11669 | succeed = TRUE; |
11670 | } | |
11671 | else | |
11672 | fail = TRUE; | |
11673 | break; | |
11674 | ||
ff9940b0 | 11675 | case CALL_INSN: |
68d560d4 RE |
11676 | /* The AAPCS says that conditional calls should not be |
11677 | used since they make interworking inefficient (the | |
11678 | linker can't transform BL<cond> into BLX). That's | |
11679 | only a problem if the machine has BLX. */ | |
11680 | if (arm_arch5) | |
11681 | { | |
11682 | fail = TRUE; | |
11683 | break; | |
11684 | } | |
11685 | ||
61f0ccff RE |
11686 | /* Succeed if the following insn is the target label, or |
11687 | if the following two insns are a barrier and the | |
11688 | target label. */ | |
11689 | this_insn = next_nonnote_insn (this_insn); | |
11690 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
11691 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 11692 | |
61f0ccff RE |
11693 | if (this_insn && this_insn == label |
11694 | && insns_skipped < max_insns_skipped) | |
11695 | { | |
11696 | if (jump_clobbers) | |
bd9c7e23 | 11697 | { |
61f0ccff RE |
11698 | arm_ccfsm_state = 2; |
11699 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 RE |
11700 | } |
11701 | else | |
61f0ccff RE |
11702 | arm_ccfsm_state = 1; |
11703 | succeed = TRUE; | |
bd9c7e23 | 11704 | } |
61f0ccff RE |
11705 | else |
11706 | fail = TRUE; | |
ff9940b0 | 11707 | break; |
2b835d68 | 11708 | |
cce8749e CH |
11709 | case JUMP_INSN: |
11710 | /* If this is an unconditional branch to the same label, succeed. | |
11711 | If it is to another label, do nothing. If it is conditional, | |
11712 | fail. */ | |
e32bac5b RE |
11713 | /* XXX Probably, the tests for SET and the PC are |
11714 | unnecessary. */ | |
cce8749e | 11715 | |
ed4c4348 | 11716 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
11717 | if (GET_CODE (scanbody) == SET |
11718 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
11719 | { |
11720 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
11721 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
11722 | { | |
11723 | arm_ccfsm_state = 2; | |
11724 | succeed = TRUE; | |
11725 | } | |
11726 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
11727 | fail = TRUE; | |
11728 | } | |
112cdef5 | 11729 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
11730 | StrongARM), but still allow this if optimizing for size. */ |
11731 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 11732 | && !use_return_insn (TRUE, NULL) |
5895f793 | 11733 | && !optimize_size) |
b36ba79f | 11734 | fail = TRUE; |
ff9940b0 RE |
11735 | else if (GET_CODE (scanbody) == RETURN |
11736 | && seeking_return) | |
11737 | { | |
11738 | arm_ccfsm_state = 2; | |
11739 | succeed = TRUE; | |
11740 | } | |
11741 | else if (GET_CODE (scanbody) == PARALLEL) | |
11742 | { | |
11743 | switch (get_attr_conds (this_insn)) | |
11744 | { | |
11745 | case CONDS_NOCOND: | |
11746 | break; | |
11747 | default: | |
11748 | fail = TRUE; | |
11749 | break; | |
11750 | } | |
11751 | } | |
4e67550b | 11752 | else |
112cdef5 | 11753 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 11754 | |
cce8749e CH |
11755 | break; |
11756 | ||
11757 | case INSN: | |
ff9940b0 RE |
11758 | /* Instructions using or affecting the condition codes make it |
11759 | fail. */ | |
ed4c4348 | 11760 | scanbody = PATTERN (this_insn); |
5895f793 RE |
11761 | if (!(GET_CODE (scanbody) == SET |
11762 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 11763 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 11764 | fail = TRUE; |
9b6b54e2 NC |
11765 | |
11766 | /* A conditional cirrus instruction must be followed by | |
11767 | a non Cirrus instruction. However, since we | |
11768 | conditionalize instructions in this function and by | |
11769 | the time we get here we can't add instructions | |
11770 | (nops), because shorten_branches() has already been | |
11771 | called, we will disable conditionalizing Cirrus | |
11772 | instructions to be safe. */ | |
11773 | if (GET_CODE (scanbody) != USE | |
11774 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 11775 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 11776 | fail = TRUE; |
cce8749e CH |
11777 | break; |
11778 | ||
11779 | default: | |
11780 | break; | |
11781 | } | |
11782 | } | |
11783 | if (succeed) | |
11784 | { | |
ff9940b0 | 11785 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 11786 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 11787 | else |
ff9940b0 | 11788 | { |
e6d29d15 | 11789 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 11790 | |
ff9940b0 RE |
11791 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
11792 | { | |
11793 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
11794 | gcc_assert (!this_insn |
11795 | || (GET_CODE (this_insn) != BARRIER | |
11796 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
11797 | } |
11798 | if (!this_insn) | |
11799 | { | |
d6b4baa4 | 11800 | /* Oh, dear! we ran off the end.. give up. */ |
df4ae160 | 11801 | recog (PATTERN (insn), insn, NULL); |
ff9940b0 | 11802 | arm_ccfsm_state = 0; |
abaa26e5 | 11803 | arm_target_insn = NULL; |
ff9940b0 RE |
11804 | return; |
11805 | } | |
11806 | arm_target_insn = this_insn; | |
11807 | } | |
ff9940b0 RE |
11808 | if (jump_clobbers) |
11809 | { | |
e6d29d15 | 11810 | gcc_assert (!reverse); |
f676971a | 11811 | arm_current_cc = |
ff9940b0 RE |
11812 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), |
11813 | 0), 0), 1)); | |
11814 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
11815 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11816 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
11817 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11818 | } | |
11819 | else | |
11820 | { | |
11821 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
11822 | what it was. */ | |
11823 | if (!reverse) | |
11824 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
11825 | 0)); | |
11826 | } | |
cce8749e | 11827 | |
cce8749e CH |
11828 | if (reverse || then_not_else) |
11829 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11830 | } | |
f676971a | 11831 | |
1ccbefce | 11832 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 11833 | destroy this array, but final.c assumes that it remains intact |
ddd5a7c1 | 11834 | across this call; since the insn has been recognized already we |
b020fd92 | 11835 | call recog direct). */ |
df4ae160 | 11836 | recog (PATTERN (insn), insn, NULL); |
cce8749e | 11837 | } |
f3bb6135 | 11838 | } |
cce8749e | 11839 | |
4b02997f | 11840 | /* Returns true if REGNO is a valid register |
21b5653c | 11841 | for holding a quantity of type MODE. */ |
4b02997f | 11842 | int |
e32bac5b | 11843 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
11844 | { |
11845 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
11846 | return (regno == CC_REGNUM |
11847 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
11848 | && regno == VFPCC_REGNUM)); | |
f676971a | 11849 | |
4b02997f NC |
11850 | if (TARGET_THUMB) |
11851 | /* For the Thumb we only allow values bigger than SImode in | |
11852 | registers 0 - 6, so that there is always a second low | |
11853 | register available to hold the upper part of the value. | |
11854 | We probably we ought to ensure that the register is the | |
11855 | start of an even numbered register pair. */ | |
e9d7b180 | 11856 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 11857 | |
a6a5de04 RE |
11858 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
11859 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
11860 | /* We have outlawed SI values in Cirrus registers because they |
11861 | reside in the lower 32 bits, but SF values reside in the | |
11862 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
11863 | even split the registers into pairs because Cirrus SI values | |
11864 | get sign extended to 64bits-- aldyh. */ | |
11865 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
11866 | ||
a6a5de04 RE |
11867 | if (TARGET_HARD_FLOAT && TARGET_VFP |
11868 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
11869 | { |
11870 | if (mode == SFmode || mode == SImode) | |
11871 | return TRUE; | |
11872 | ||
11873 | /* DFmode values are only valid in even register pairs. */ | |
11874 | if (mode == DFmode) | |
11875 | return ((regno - FIRST_VFP_REGNUM) & 1) == 0; | |
11876 | return FALSE; | |
11877 | } | |
11878 | ||
a6a5de04 RE |
11879 | if (TARGET_REALLY_IWMMXT) |
11880 | { | |
11881 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
11882 | return mode == SImode; | |
5a9335ef | 11883 | |
a6a5de04 RE |
11884 | if (IS_IWMMXT_REGNUM (regno)) |
11885 | return VALID_IWMMXT_REG_MODE (mode); | |
11886 | } | |
11887 | ||
fdd695fd PB |
11888 | /* We allow any value to be stored in the general registers. |
11889 | Restrict doubleword quantities to even register pairs so that we can | |
11890 | use ldrd. */ | |
4b02997f | 11891 | if (regno <= LAST_ARM_REGNUM) |
fdd695fd | 11892 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); |
4b02997f | 11893 | |
a6a5de04 | 11894 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
11895 | || regno == ARG_POINTER_REGNUM) |
11896 | /* We only allow integers in the fake hard registers. */ | |
11897 | return GET_MODE_CLASS (mode) == MODE_INT; | |
11898 | ||
3b684012 | 11899 | /* The only registers left are the FPA registers |
4b02997f | 11900 | which we only allow to hold FP values. */ |
a6a5de04 RE |
11901 | return (TARGET_HARD_FLOAT && TARGET_FPA |
11902 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
11903 | && regno >= FIRST_FPA_REGNUM | |
11904 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
11905 | } |
11906 | ||
d5b7b3ae | 11907 | int |
e32bac5b | 11908 | arm_regno_class (int regno) |
d5b7b3ae RE |
11909 | { |
11910 | if (TARGET_THUMB) | |
11911 | { | |
11912 | if (regno == STACK_POINTER_REGNUM) | |
11913 | return STACK_REG; | |
11914 | if (regno == CC_REGNUM) | |
11915 | return CC_REG; | |
11916 | if (regno < 8) | |
11917 | return LO_REGS; | |
11918 | return HI_REGS; | |
11919 | } | |
11920 | ||
11921 | if ( regno <= LAST_ARM_REGNUM | |
11922 | || regno == FRAME_POINTER_REGNUM | |
11923 | || regno == ARG_POINTER_REGNUM) | |
11924 | return GENERAL_REGS; | |
f676971a | 11925 | |
9b66ebb1 | 11926 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
d5b7b3ae RE |
11927 | return NO_REGS; |
11928 | ||
9b6b54e2 NC |
11929 | if (IS_CIRRUS_REGNUM (regno)) |
11930 | return CIRRUS_REGS; | |
11931 | ||
9b66ebb1 PB |
11932 | if (IS_VFP_REGNUM (regno)) |
11933 | return VFP_REGS; | |
11934 | ||
5a9335ef NC |
11935 | if (IS_IWMMXT_REGNUM (regno)) |
11936 | return IWMMXT_REGS; | |
11937 | ||
e99faaaa ILT |
11938 | if (IS_IWMMXT_GR_REGNUM (regno)) |
11939 | return IWMMXT_GR_REGS; | |
11940 | ||
3b684012 | 11941 | return FPA_REGS; |
d5b7b3ae RE |
11942 | } |
11943 | ||
11944 | /* Handle a special case when computing the offset | |
11945 | of an argument from the frame pointer. */ | |
11946 | int | |
e32bac5b | 11947 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
11948 | { |
11949 | rtx insn; | |
11950 | ||
11951 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
11952 | if (value != 0) | |
11953 | return 0; | |
11954 | ||
11955 | /* We can only cope with the case where the address is held in a register. */ | |
11956 | if (GET_CODE (addr) != REG) | |
11957 | return 0; | |
11958 | ||
11959 | /* If we are using the frame pointer to point at the argument, then | |
11960 | an offset of 0 is correct. */ | |
cd2b33d0 | 11961 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 11962 | return 0; |
f676971a | 11963 | |
d5b7b3ae RE |
11964 | /* If we are using the stack pointer to point at the |
11965 | argument, then an offset of 0 is correct. */ | |
5895f793 | 11966 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
11967 | && REGNO (addr) == SP_REGNUM) |
11968 | return 0; | |
f676971a | 11969 | |
d5b7b3ae RE |
11970 | /* Oh dear. The argument is pointed to by a register rather |
11971 | than being held in a register, or being stored at a known | |
11972 | offset from the frame pointer. Since GDB only understands | |
11973 | those two kinds of argument we must translate the address | |
11974 | held in the register into an offset from the frame pointer. | |
11975 | We do this by searching through the insns for the function | |
11976 | looking to see where this register gets its value. If the | |
4912a07c | 11977 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 11978 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 11979 | |
d5b7b3ae RE |
11980 | This code is exercised by producing debugging information |
11981 | for a function with arguments like this: | |
f676971a | 11982 | |
d5b7b3ae | 11983 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 11984 | |
d5b7b3ae RE |
11985 | Without this code the stab for parameter 'd' will be set to |
11986 | an offset of 0 from the frame pointer, rather than 8. */ | |
11987 | ||
11988 | /* The if() statement says: | |
11989 | ||
11990 | If the insn is a normal instruction | |
11991 | and if the insn is setting the value in a register | |
11992 | and if the register being set is the register holding the address of the argument | |
11993 | and if the address is computing by an addition | |
11994 | that involves adding to a register | |
11995 | which is the frame pointer | |
11996 | a constant integer | |
11997 | ||
d6b4baa4 | 11998 | then... */ |
f676971a | 11999 | |
d5b7b3ae RE |
12000 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
12001 | { | |
f676971a | 12002 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
12003 | && GET_CODE (PATTERN (insn)) == SET |
12004 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
12005 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
12006 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 12007 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
12008 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
12009 | ) | |
12010 | { | |
12011 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 12012 | |
d5b7b3ae RE |
12013 | break; |
12014 | } | |
12015 | } | |
f676971a | 12016 | |
d5b7b3ae RE |
12017 | if (value == 0) |
12018 | { | |
12019 | debug_rtx (addr); | |
d4ee4d25 | 12020 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
12021 | value = 8; /* XXX magic hack */ |
12022 | } | |
12023 | ||
12024 | return value; | |
12025 | } | |
d5b7b3ae | 12026 | \f |
5a9335ef NC |
12027 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
12028 | do \ | |
12029 | { \ | |
12030 | if ((MASK) & insn_flags) \ | |
6e34d3a3 JM |
12031 | lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \ |
12032 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
12033 | } \ |
12034 | while (0) | |
12035 | ||
12036 | struct builtin_description | |
12037 | { | |
12038 | const unsigned int mask; | |
12039 | const enum insn_code icode; | |
12040 | const char * const name; | |
12041 | const enum arm_builtins code; | |
12042 | const enum rtx_code comparison; | |
12043 | const unsigned int flag; | |
12044 | }; | |
12045 | ||
12046 | static const struct builtin_description bdesc_2arg[] = | |
12047 | { | |
12048 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
12049 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
12050 | ARM_BUILTIN_##builtin, 0, 0 }, | |
12051 | ||
12052 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
12053 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
12054 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
12055 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
12056 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
12057 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
12058 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
12059 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
12060 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
12061 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
12062 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
12063 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
12064 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
12065 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
12066 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
12067 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
12068 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
12069 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
12070 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
12071 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
12072 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
12073 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
12074 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
12075 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
12076 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
12077 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
12078 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
12079 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
12080 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
12081 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
12082 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
12083 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
12084 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
12085 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
12086 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
12087 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
12088 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
12089 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
12090 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
12091 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
12092 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
12093 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
12094 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
12095 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
12096 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
12097 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
12098 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
12099 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
12100 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
12101 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
12102 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
12103 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
12104 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
12105 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
12106 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
12107 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
12108 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
12109 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
12110 | ||
12111 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
12112 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, | |
f676971a | 12113 | |
5a9335ef NC |
12114 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
12115 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
12116 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
12117 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
12118 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
12119 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
12120 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
12121 | IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) | |
12122 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) | |
12123 | IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) | |
12124 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) | |
12125 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
12126 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
12127 | IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) | |
12128 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) | |
12129 | IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) | |
12130 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) | |
9b66ebb1 | 12131 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef NC |
12132 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
12133 | IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) | |
12134 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) | |
12135 | IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) | |
12136 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) | |
9b66ebb1 | 12137 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
12138 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
12139 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
12140 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
12141 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
12142 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
12143 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
12144 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
12145 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
12146 | }; | |
12147 | ||
12148 | static const struct builtin_description bdesc_1arg[] = | |
12149 | { | |
12150 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
12151 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
12152 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
12153 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
12154 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
12155 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
12156 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
12157 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
12158 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
12159 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
12160 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
12161 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
12162 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
12163 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
12164 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
12165 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
12166 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
12167 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
12168 | }; | |
12169 | ||
12170 | /* Set up all the iWMMXt builtins. This is | |
12171 | not called if TARGET_IWMMXT is zero. */ | |
12172 | ||
12173 | static void | |
12174 | arm_init_iwmmxt_builtins (void) | |
12175 | { | |
12176 | const struct builtin_description * d; | |
12177 | size_t i; | |
12178 | tree endlink = void_list_node; | |
12179 | ||
4a5eab38 PB |
12180 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
12181 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
12182 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
12183 | ||
5a9335ef NC |
12184 | tree int_ftype_int |
12185 | = build_function_type (integer_type_node, | |
12186 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
12187 | tree v8qi_ftype_v8qi_v8qi_int | |
12188 | = build_function_type (V8QI_type_node, | |
12189 | tree_cons (NULL_TREE, V8QI_type_node, | |
12190 | tree_cons (NULL_TREE, V8QI_type_node, | |
12191 | tree_cons (NULL_TREE, | |
12192 | integer_type_node, | |
12193 | endlink)))); | |
12194 | tree v4hi_ftype_v4hi_int | |
12195 | = build_function_type (V4HI_type_node, | |
12196 | tree_cons (NULL_TREE, V4HI_type_node, | |
12197 | tree_cons (NULL_TREE, integer_type_node, | |
12198 | endlink))); | |
12199 | tree v2si_ftype_v2si_int | |
12200 | = build_function_type (V2SI_type_node, | |
12201 | tree_cons (NULL_TREE, V2SI_type_node, | |
12202 | tree_cons (NULL_TREE, integer_type_node, | |
12203 | endlink))); | |
12204 | tree v2si_ftype_di_di | |
12205 | = build_function_type (V2SI_type_node, | |
12206 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
12207 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
12208 | endlink))); | |
12209 | tree di_ftype_di_int | |
12210 | = build_function_type (long_long_integer_type_node, | |
12211 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
12212 | tree_cons (NULL_TREE, integer_type_node, | |
12213 | endlink))); | |
12214 | tree di_ftype_di_int_int | |
12215 | = build_function_type (long_long_integer_type_node, | |
12216 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
12217 | tree_cons (NULL_TREE, integer_type_node, | |
12218 | tree_cons (NULL_TREE, | |
12219 | integer_type_node, | |
12220 | endlink)))); | |
12221 | tree int_ftype_v8qi | |
12222 | = build_function_type (integer_type_node, | |
12223 | tree_cons (NULL_TREE, V8QI_type_node, | |
12224 | endlink)); | |
12225 | tree int_ftype_v4hi | |
12226 | = build_function_type (integer_type_node, | |
12227 | tree_cons (NULL_TREE, V4HI_type_node, | |
12228 | endlink)); | |
12229 | tree int_ftype_v2si | |
12230 | = build_function_type (integer_type_node, | |
12231 | tree_cons (NULL_TREE, V2SI_type_node, | |
12232 | endlink)); | |
12233 | tree int_ftype_v8qi_int | |
12234 | = build_function_type (integer_type_node, | |
12235 | tree_cons (NULL_TREE, V8QI_type_node, | |
12236 | tree_cons (NULL_TREE, integer_type_node, | |
12237 | endlink))); | |
12238 | tree int_ftype_v4hi_int | |
12239 | = build_function_type (integer_type_node, | |
12240 | tree_cons (NULL_TREE, V4HI_type_node, | |
12241 | tree_cons (NULL_TREE, integer_type_node, | |
12242 | endlink))); | |
12243 | tree int_ftype_v2si_int | |
12244 | = build_function_type (integer_type_node, | |
12245 | tree_cons (NULL_TREE, V2SI_type_node, | |
12246 | tree_cons (NULL_TREE, integer_type_node, | |
12247 | endlink))); | |
12248 | tree v8qi_ftype_v8qi_int_int | |
12249 | = build_function_type (V8QI_type_node, | |
12250 | tree_cons (NULL_TREE, V8QI_type_node, | |
12251 | tree_cons (NULL_TREE, integer_type_node, | |
12252 | tree_cons (NULL_TREE, | |
12253 | integer_type_node, | |
12254 | endlink)))); | |
12255 | tree v4hi_ftype_v4hi_int_int | |
12256 | = build_function_type (V4HI_type_node, | |
12257 | tree_cons (NULL_TREE, V4HI_type_node, | |
12258 | tree_cons (NULL_TREE, integer_type_node, | |
12259 | tree_cons (NULL_TREE, | |
12260 | integer_type_node, | |
12261 | endlink)))); | |
12262 | tree v2si_ftype_v2si_int_int | |
12263 | = build_function_type (V2SI_type_node, | |
12264 | tree_cons (NULL_TREE, V2SI_type_node, | |
12265 | tree_cons (NULL_TREE, integer_type_node, | |
12266 | tree_cons (NULL_TREE, | |
12267 | integer_type_node, | |
12268 | endlink)))); | |
12269 | /* Miscellaneous. */ | |
12270 | tree v8qi_ftype_v4hi_v4hi | |
12271 | = build_function_type (V8QI_type_node, | |
12272 | tree_cons (NULL_TREE, V4HI_type_node, | |
12273 | tree_cons (NULL_TREE, V4HI_type_node, | |
12274 | endlink))); | |
12275 | tree v4hi_ftype_v2si_v2si | |
12276 | = build_function_type (V4HI_type_node, | |
12277 | tree_cons (NULL_TREE, V2SI_type_node, | |
12278 | tree_cons (NULL_TREE, V2SI_type_node, | |
12279 | endlink))); | |
12280 | tree v2si_ftype_v4hi_v4hi | |
12281 | = build_function_type (V2SI_type_node, | |
12282 | tree_cons (NULL_TREE, V4HI_type_node, | |
12283 | tree_cons (NULL_TREE, V4HI_type_node, | |
12284 | endlink))); | |
12285 | tree v2si_ftype_v8qi_v8qi | |
12286 | = build_function_type (V2SI_type_node, | |
12287 | tree_cons (NULL_TREE, V8QI_type_node, | |
12288 | tree_cons (NULL_TREE, V8QI_type_node, | |
12289 | endlink))); | |
12290 | tree v4hi_ftype_v4hi_di | |
12291 | = build_function_type (V4HI_type_node, | |
12292 | tree_cons (NULL_TREE, V4HI_type_node, | |
12293 | tree_cons (NULL_TREE, | |
12294 | long_long_integer_type_node, | |
12295 | endlink))); | |
12296 | tree v2si_ftype_v2si_di | |
12297 | = build_function_type (V2SI_type_node, | |
12298 | tree_cons (NULL_TREE, V2SI_type_node, | |
12299 | tree_cons (NULL_TREE, | |
12300 | long_long_integer_type_node, | |
12301 | endlink))); | |
12302 | tree void_ftype_int_int | |
12303 | = build_function_type (void_type_node, | |
12304 | tree_cons (NULL_TREE, integer_type_node, | |
12305 | tree_cons (NULL_TREE, integer_type_node, | |
12306 | endlink))); | |
12307 | tree di_ftype_void | |
12308 | = build_function_type (long_long_unsigned_type_node, endlink); | |
12309 | tree di_ftype_v8qi | |
12310 | = build_function_type (long_long_integer_type_node, | |
12311 | tree_cons (NULL_TREE, V8QI_type_node, | |
12312 | endlink)); | |
12313 | tree di_ftype_v4hi | |
12314 | = build_function_type (long_long_integer_type_node, | |
12315 | tree_cons (NULL_TREE, V4HI_type_node, | |
12316 | endlink)); | |
12317 | tree di_ftype_v2si | |
12318 | = build_function_type (long_long_integer_type_node, | |
12319 | tree_cons (NULL_TREE, V2SI_type_node, | |
12320 | endlink)); | |
12321 | tree v2si_ftype_v4hi | |
12322 | = build_function_type (V2SI_type_node, | |
12323 | tree_cons (NULL_TREE, V4HI_type_node, | |
12324 | endlink)); | |
12325 | tree v4hi_ftype_v8qi | |
12326 | = build_function_type (V4HI_type_node, | |
12327 | tree_cons (NULL_TREE, V8QI_type_node, | |
12328 | endlink)); | |
12329 | ||
12330 | tree di_ftype_di_v4hi_v4hi | |
12331 | = build_function_type (long_long_unsigned_type_node, | |
12332 | tree_cons (NULL_TREE, | |
12333 | long_long_unsigned_type_node, | |
12334 | tree_cons (NULL_TREE, V4HI_type_node, | |
12335 | tree_cons (NULL_TREE, | |
12336 | V4HI_type_node, | |
12337 | endlink)))); | |
12338 | ||
12339 | tree di_ftype_v4hi_v4hi | |
12340 | = build_function_type (long_long_unsigned_type_node, | |
12341 | tree_cons (NULL_TREE, V4HI_type_node, | |
12342 | tree_cons (NULL_TREE, V4HI_type_node, | |
12343 | endlink))); | |
12344 | ||
12345 | /* Normal vector binops. */ | |
12346 | tree v8qi_ftype_v8qi_v8qi | |
12347 | = build_function_type (V8QI_type_node, | |
12348 | tree_cons (NULL_TREE, V8QI_type_node, | |
12349 | tree_cons (NULL_TREE, V8QI_type_node, | |
12350 | endlink))); | |
12351 | tree v4hi_ftype_v4hi_v4hi | |
12352 | = build_function_type (V4HI_type_node, | |
12353 | tree_cons (NULL_TREE, V4HI_type_node, | |
12354 | tree_cons (NULL_TREE, V4HI_type_node, | |
12355 | endlink))); | |
12356 | tree v2si_ftype_v2si_v2si | |
12357 | = build_function_type (V2SI_type_node, | |
12358 | tree_cons (NULL_TREE, V2SI_type_node, | |
12359 | tree_cons (NULL_TREE, V2SI_type_node, | |
12360 | endlink))); | |
12361 | tree di_ftype_di_di | |
12362 | = build_function_type (long_long_unsigned_type_node, | |
12363 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
12364 | tree_cons (NULL_TREE, | |
12365 | long_long_unsigned_type_node, | |
12366 | endlink))); | |
12367 | ||
12368 | /* Add all builtins that are more or less simple operations on two | |
12369 | operands. */ | |
e97a46ce | 12370 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
12371 | { |
12372 | /* Use one of the operands; the target can have a different mode for | |
12373 | mask-generating compares. */ | |
12374 | enum machine_mode mode; | |
12375 | tree type; | |
12376 | ||
12377 | if (d->name == 0) | |
12378 | continue; | |
12379 | ||
12380 | mode = insn_data[d->icode].operand[1].mode; | |
12381 | ||
12382 | switch (mode) | |
12383 | { | |
12384 | case V8QImode: | |
12385 | type = v8qi_ftype_v8qi_v8qi; | |
12386 | break; | |
12387 | case V4HImode: | |
12388 | type = v4hi_ftype_v4hi_v4hi; | |
12389 | break; | |
12390 | case V2SImode: | |
12391 | type = v2si_ftype_v2si_v2si; | |
12392 | break; | |
12393 | case DImode: | |
12394 | type = di_ftype_di_di; | |
12395 | break; | |
12396 | ||
12397 | default: | |
e6d29d15 | 12398 | gcc_unreachable (); |
5a9335ef NC |
12399 | } |
12400 | ||
12401 | def_mbuiltin (d->mask, d->name, type, d->code); | |
12402 | } | |
12403 | ||
12404 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
12405 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
12406 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
12407 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
12408 | ||
12409 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
12410 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
12411 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
12412 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
12413 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
12414 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
12415 | ||
12416 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
12417 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
12418 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
12419 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
12420 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
12421 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
12422 | ||
12423 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
12424 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
12425 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
12426 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
12427 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
12428 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
12429 | ||
12430 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
12431 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
12432 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
12433 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
12434 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
12435 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
12436 | ||
12437 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
12438 | ||
12439 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
12440 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
12441 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
12442 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
12443 | ||
12444 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
12445 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
12446 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
12447 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
12448 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
12449 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
12450 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
12451 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
12452 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
12453 | ||
12454 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
12455 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
12456 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
12457 | ||
12458 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
12459 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
12460 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
12461 | ||
12462 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
12463 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
12464 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
12465 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
12466 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
12467 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
12468 | ||
12469 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
12470 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
12471 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
12472 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
12473 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
12474 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
12475 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
12476 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
12477 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
12478 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
12479 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
12480 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
12481 | ||
12482 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
12483 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
12484 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
12485 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
12486 | ||
12487 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
12488 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
12489 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
12490 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
12491 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
12492 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
12493 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
12494 | } | |
12495 | ||
d3585b76 DJ |
12496 | static void |
12497 | arm_init_tls_builtins (void) | |
12498 | { | |
12499 | tree ftype; | |
12500 | tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL); | |
12501 | tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow); | |
12502 | ||
12503 | ftype = build_function_type (ptr_type_node, void_list_node); | |
12504 | lang_hooks.builtin_function ("__builtin_thread_pointer", ftype, | |
12505 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
12506 | NULL, const_nothrow); | |
12507 | } | |
12508 | ||
5a9335ef NC |
12509 | static void |
12510 | arm_init_builtins (void) | |
12511 | { | |
d3585b76 DJ |
12512 | arm_init_tls_builtins (); |
12513 | ||
5a9335ef NC |
12514 | if (TARGET_REALLY_IWMMXT) |
12515 | arm_init_iwmmxt_builtins (); | |
12516 | } | |
12517 | ||
12518 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
12519 | where we expect a vector. To avoid crashing, use one of the vector | |
12520 | clear instructions. */ | |
12521 | ||
12522 | static rtx | |
12523 | safe_vector_operand (rtx x, enum machine_mode mode) | |
12524 | { | |
12525 | if (x != const0_rtx) | |
12526 | return x; | |
12527 | x = gen_reg_rtx (mode); | |
12528 | ||
12529 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
12530 | : gen_rtx_SUBREG (DImode, x, 0))); | |
12531 | return x; | |
12532 | } | |
12533 | ||
12534 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
12535 | ||
12536 | static rtx | |
12537 | arm_expand_binop_builtin (enum insn_code icode, | |
12538 | tree arglist, rtx target) | |
12539 | { | |
12540 | rtx pat; | |
12541 | tree arg0 = TREE_VALUE (arglist); | |
12542 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12543 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12544 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12545 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
12546 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
12547 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
12548 | ||
12549 | if (VECTOR_MODE_P (mode0)) | |
12550 | op0 = safe_vector_operand (op0, mode0); | |
12551 | if (VECTOR_MODE_P (mode1)) | |
12552 | op1 = safe_vector_operand (op1, mode1); | |
12553 | ||
12554 | if (! target | |
12555 | || GET_MODE (target) != tmode | |
12556 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12557 | target = gen_reg_rtx (tmode); | |
12558 | ||
e6d29d15 | 12559 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
12560 | |
12561 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12562 | op0 = copy_to_mode_reg (mode0, op0); | |
12563 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12564 | op1 = copy_to_mode_reg (mode1, op1); | |
12565 | ||
12566 | pat = GEN_FCN (icode) (target, op0, op1); | |
12567 | if (! pat) | |
12568 | return 0; | |
12569 | emit_insn (pat); | |
12570 | return target; | |
12571 | } | |
12572 | ||
12573 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
12574 | ||
12575 | static rtx | |
12576 | arm_expand_unop_builtin (enum insn_code icode, | |
12577 | tree arglist, rtx target, int do_load) | |
12578 | { | |
12579 | rtx pat; | |
12580 | tree arg0 = TREE_VALUE (arglist); | |
12581 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12582 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
12583 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
12584 | ||
12585 | if (! target | |
12586 | || GET_MODE (target) != tmode | |
12587 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12588 | target = gen_reg_rtx (tmode); | |
12589 | if (do_load) | |
12590 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
12591 | else | |
12592 | { | |
12593 | if (VECTOR_MODE_P (mode0)) | |
12594 | op0 = safe_vector_operand (op0, mode0); | |
12595 | ||
12596 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12597 | op0 = copy_to_mode_reg (mode0, op0); | |
12598 | } | |
12599 | ||
12600 | pat = GEN_FCN (icode) (target, op0); | |
12601 | if (! pat) | |
12602 | return 0; | |
12603 | emit_insn (pat); | |
12604 | return target; | |
12605 | } | |
12606 | ||
12607 | /* Expand an expression EXP that calls a built-in function, | |
12608 | with result going to TARGET if that's convenient | |
12609 | (and in mode MODE if that's convenient). | |
12610 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
12611 | IGNORE is nonzero if the value is to be ignored. */ | |
12612 | ||
12613 | static rtx | |
12614 | arm_expand_builtin (tree exp, | |
12615 | rtx target, | |
12616 | rtx subtarget ATTRIBUTE_UNUSED, | |
12617 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
12618 | int ignore ATTRIBUTE_UNUSED) | |
12619 | { | |
12620 | const struct builtin_description * d; | |
12621 | enum insn_code icode; | |
12622 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
12623 | tree arglist = TREE_OPERAND (exp, 1); | |
12624 | tree arg0; | |
12625 | tree arg1; | |
12626 | tree arg2; | |
12627 | rtx op0; | |
12628 | rtx op1; | |
12629 | rtx op2; | |
12630 | rtx pat; | |
12631 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
12632 | size_t i; | |
12633 | enum machine_mode tmode; | |
12634 | enum machine_mode mode0; | |
12635 | enum machine_mode mode1; | |
12636 | enum machine_mode mode2; | |
12637 | ||
12638 | switch (fcode) | |
12639 | { | |
12640 | case ARM_BUILTIN_TEXTRMSB: | |
12641 | case ARM_BUILTIN_TEXTRMUB: | |
12642 | case ARM_BUILTIN_TEXTRMSH: | |
12643 | case ARM_BUILTIN_TEXTRMUH: | |
12644 | case ARM_BUILTIN_TEXTRMSW: | |
12645 | case ARM_BUILTIN_TEXTRMUW: | |
12646 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
12647 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
12648 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
12649 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
12650 | : CODE_FOR_iwmmxt_textrmw); | |
12651 | ||
12652 | arg0 = TREE_VALUE (arglist); | |
12653 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12654 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12655 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12656 | tmode = insn_data[icode].operand[0].mode; | |
12657 | mode0 = insn_data[icode].operand[1].mode; | |
12658 | mode1 = insn_data[icode].operand[2].mode; | |
12659 | ||
12660 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12661 | op0 = copy_to_mode_reg (mode0, op0); | |
12662 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12663 | { | |
12664 | /* @@@ better error message */ | |
12665 | error ("selector must be an immediate"); | |
12666 | return gen_reg_rtx (tmode); | |
12667 | } | |
12668 | if (target == 0 | |
12669 | || GET_MODE (target) != tmode | |
12670 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12671 | target = gen_reg_rtx (tmode); | |
12672 | pat = GEN_FCN (icode) (target, op0, op1); | |
12673 | if (! pat) | |
12674 | return 0; | |
12675 | emit_insn (pat); | |
12676 | return target; | |
12677 | ||
12678 | case ARM_BUILTIN_TINSRB: | |
12679 | case ARM_BUILTIN_TINSRH: | |
12680 | case ARM_BUILTIN_TINSRW: | |
12681 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
12682 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
12683 | : CODE_FOR_iwmmxt_tinsrw); | |
12684 | arg0 = TREE_VALUE (arglist); | |
12685 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12686 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
12687 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12688 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12689 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
12690 | tmode = insn_data[icode].operand[0].mode; | |
12691 | mode0 = insn_data[icode].operand[1].mode; | |
12692 | mode1 = insn_data[icode].operand[2].mode; | |
12693 | mode2 = insn_data[icode].operand[3].mode; | |
12694 | ||
12695 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12696 | op0 = copy_to_mode_reg (mode0, op0); | |
12697 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12698 | op1 = copy_to_mode_reg (mode1, op1); | |
12699 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
12700 | { | |
12701 | /* @@@ better error message */ | |
12702 | error ("selector must be an immediate"); | |
12703 | return const0_rtx; | |
12704 | } | |
12705 | if (target == 0 | |
12706 | || GET_MODE (target) != tmode | |
12707 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12708 | target = gen_reg_rtx (tmode); | |
12709 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
12710 | if (! pat) | |
12711 | return 0; | |
12712 | emit_insn (pat); | |
12713 | return target; | |
12714 | ||
12715 | case ARM_BUILTIN_SETWCX: | |
12716 | arg0 = TREE_VALUE (arglist); | |
12717 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
f07a6b21 BE |
12718 | op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0)); |
12719 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12720 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); | |
5a9335ef NC |
12721 | return 0; |
12722 | ||
12723 | case ARM_BUILTIN_GETWCX: | |
12724 | arg0 = TREE_VALUE (arglist); | |
12725 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12726 | target = gen_reg_rtx (SImode); | |
12727 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
12728 | return target; | |
12729 | ||
12730 | case ARM_BUILTIN_WSHUFH: | |
12731 | icode = CODE_FOR_iwmmxt_wshufh; | |
12732 | arg0 = TREE_VALUE (arglist); | |
12733 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12734 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12735 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12736 | tmode = insn_data[icode].operand[0].mode; | |
12737 | mode1 = insn_data[icode].operand[1].mode; | |
12738 | mode2 = insn_data[icode].operand[2].mode; | |
12739 | ||
12740 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
12741 | op0 = copy_to_mode_reg (mode1, op0); | |
12742 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
12743 | { | |
12744 | /* @@@ better error message */ | |
12745 | error ("mask must be an immediate"); | |
12746 | return const0_rtx; | |
12747 | } | |
12748 | if (target == 0 | |
12749 | || GET_MODE (target) != tmode | |
12750 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12751 | target = gen_reg_rtx (tmode); | |
12752 | pat = GEN_FCN (icode) (target, op0, op1); | |
12753 | if (! pat) | |
12754 | return 0; | |
12755 | emit_insn (pat); | |
12756 | return target; | |
12757 | ||
12758 | case ARM_BUILTIN_WSADB: | |
12759 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target); | |
12760 | case ARM_BUILTIN_WSADH: | |
12761 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target); | |
12762 | case ARM_BUILTIN_WSADBZ: | |
12763 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target); | |
12764 | case ARM_BUILTIN_WSADHZ: | |
12765 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target); | |
12766 | ||
12767 | /* Several three-argument builtins. */ | |
12768 | case ARM_BUILTIN_WMACS: | |
12769 | case ARM_BUILTIN_WMACU: | |
12770 | case ARM_BUILTIN_WALIGN: | |
12771 | case ARM_BUILTIN_TMIA: | |
12772 | case ARM_BUILTIN_TMIAPH: | |
12773 | case ARM_BUILTIN_TMIATT: | |
12774 | case ARM_BUILTIN_TMIATB: | |
12775 | case ARM_BUILTIN_TMIABT: | |
12776 | case ARM_BUILTIN_TMIABB: | |
12777 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
12778 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
12779 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
12780 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
12781 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
12782 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
12783 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
12784 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
12785 | : CODE_FOR_iwmmxt_walign); | |
12786 | arg0 = TREE_VALUE (arglist); | |
12787 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12788 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
12789 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12790 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12791 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
12792 | tmode = insn_data[icode].operand[0].mode; | |
12793 | mode0 = insn_data[icode].operand[1].mode; | |
12794 | mode1 = insn_data[icode].operand[2].mode; | |
12795 | mode2 = insn_data[icode].operand[3].mode; | |
12796 | ||
12797 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12798 | op0 = copy_to_mode_reg (mode0, op0); | |
12799 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12800 | op1 = copy_to_mode_reg (mode1, op1); | |
12801 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
12802 | op2 = copy_to_mode_reg (mode2, op2); | |
12803 | if (target == 0 | |
12804 | || GET_MODE (target) != tmode | |
12805 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12806 | target = gen_reg_rtx (tmode); | |
12807 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
12808 | if (! pat) | |
12809 | return 0; | |
12810 | emit_insn (pat); | |
12811 | return target; | |
f676971a | 12812 | |
5a9335ef NC |
12813 | case ARM_BUILTIN_WZERO: |
12814 | target = gen_reg_rtx (DImode); | |
12815 | emit_insn (gen_iwmmxt_clrdi (target)); | |
12816 | return target; | |
12817 | ||
d3585b76 DJ |
12818 | case ARM_BUILTIN_THREAD_POINTER: |
12819 | return arm_load_tp (target); | |
12820 | ||
5a9335ef NC |
12821 | default: |
12822 | break; | |
12823 | } | |
12824 | ||
e97a46ce | 12825 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
12826 | if (d->code == (const enum arm_builtins) fcode) |
12827 | return arm_expand_binop_builtin (d->icode, arglist, target); | |
12828 | ||
e97a46ce | 12829 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef NC |
12830 | if (d->code == (const enum arm_builtins) fcode) |
12831 | return arm_expand_unop_builtin (d->icode, arglist, target, 0); | |
12832 | ||
12833 | /* @@@ Should really do something sensible here. */ | |
12834 | return NULL_RTX; | |
12835 | } | |
12836 | \f | |
1d6e90ac NC |
12837 | /* Return the number (counting from 0) of |
12838 | the least significant set bit in MASK. */ | |
12839 | ||
e32bac5b | 12840 | inline static int |
b279b20a | 12841 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
12842 | { |
12843 | int bit; | |
12844 | ||
12845 | for (bit = 0; | |
12846 | (mask & (1 << bit)) == 0; | |
5895f793 | 12847 | ++bit) |
d5b7b3ae RE |
12848 | continue; |
12849 | ||
12850 | return bit; | |
12851 | } | |
12852 | ||
b279b20a NC |
12853 | /* Emit code to push or pop registers to or from the stack. F is the |
12854 | assembly file. MASK is the registers to push or pop. PUSH is | |
12855 | nonzero if we should push, and zero if we should pop. For debugging | |
12856 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
12857 | to the stack. REAL_REGS should have the same number of bits set as | |
12858 | MASK, and will be used instead (in the same order) to describe which | |
12859 | registers were saved - this is used to mark the save slots when we | |
12860 | push high registers after moving them to low registers. */ | |
12861 | static void | |
12862 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
12863 | unsigned long real_regs) | |
12864 | { | |
12865 | int regno; | |
12866 | int lo_mask = mask & 0xFF; | |
12867 | int pushed_words = 0; | |
12868 | ||
e6d29d15 | 12869 | gcc_assert (mask); |
b279b20a NC |
12870 | |
12871 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
12872 | { | |
12873 | /* Special case. Do not generate a POP PC statement here, do it in | |
12874 | thumb_exit() */ | |
12875 | thumb_exit (f, -1); | |
12876 | return; | |
12877 | } | |
12878 | ||
617a1b71 PB |
12879 | if (ARM_EABI_UNWIND_TABLES && push) |
12880 | { | |
12881 | fprintf (f, "\t.save\t{"); | |
12882 | for (regno = 0; regno < 15; regno++) | |
12883 | { | |
12884 | if (real_regs & (1 << regno)) | |
12885 | { | |
12886 | if (real_regs & ((1 << regno) -1)) | |
12887 | fprintf (f, ", "); | |
12888 | asm_fprintf (f, "%r", regno); | |
12889 | } | |
12890 | } | |
12891 | fprintf (f, "}\n"); | |
12892 | } | |
12893 | ||
b279b20a NC |
12894 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
12895 | ||
12896 | /* Look at the low registers first. */ | |
12897 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
12898 | { | |
12899 | if (lo_mask & 1) | |
12900 | { | |
12901 | asm_fprintf (f, "%r", regno); | |
12902 | ||
12903 | if ((lo_mask & ~1) != 0) | |
12904 | fprintf (f, ", "); | |
12905 | ||
12906 | pushed_words++; | |
12907 | } | |
12908 | } | |
12909 | ||
12910 | if (push && (mask & (1 << LR_REGNUM))) | |
12911 | { | |
12912 | /* Catch pushing the LR. */ | |
12913 | if (mask & 0xFF) | |
12914 | fprintf (f, ", "); | |
12915 | ||
12916 | asm_fprintf (f, "%r", LR_REGNUM); | |
12917 | ||
12918 | pushed_words++; | |
12919 | } | |
12920 | else if (!push && (mask & (1 << PC_REGNUM))) | |
12921 | { | |
12922 | /* Catch popping the PC. */ | |
12923 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
12924 | || current_function_calls_eh_return) | |
12925 | { | |
12926 | /* The PC is never poped directly, instead | |
12927 | it is popped into r3 and then BX is used. */ | |
12928 | fprintf (f, "}\n"); | |
12929 | ||
12930 | thumb_exit (f, -1); | |
12931 | ||
12932 | return; | |
12933 | } | |
12934 | else | |
12935 | { | |
12936 | if (mask & 0xFF) | |
12937 | fprintf (f, ", "); | |
12938 | ||
12939 | asm_fprintf (f, "%r", PC_REGNUM); | |
12940 | } | |
12941 | } | |
12942 | ||
12943 | fprintf (f, "}\n"); | |
12944 | ||
12945 | if (push && pushed_words && dwarf2out_do_frame ()) | |
12946 | { | |
12947 | char *l = dwarf2out_cfi_label (); | |
12948 | int pushed_mask = real_regs; | |
12949 | ||
12950 | *cfa_offset += pushed_words * 4; | |
12951 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
12952 | ||
12953 | pushed_words = 0; | |
12954 | pushed_mask = real_regs; | |
12955 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
12956 | { | |
12957 | if (pushed_mask & 1) | |
12958 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
12959 | } | |
12960 | } | |
12961 | } | |
12962 | ||
d5b7b3ae RE |
12963 | /* Generate code to return from a thumb function. |
12964 | If 'reg_containing_return_addr' is -1, then the return address is | |
12965 | actually on the stack, at the stack pointer. */ | |
12966 | static void | |
c9ca9b88 | 12967 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
12968 | { |
12969 | unsigned regs_available_for_popping; | |
12970 | unsigned regs_to_pop; | |
12971 | int pops_needed; | |
12972 | unsigned available; | |
12973 | unsigned required; | |
12974 | int mode; | |
12975 | int size; | |
12976 | int restore_a4 = FALSE; | |
12977 | ||
12978 | /* Compute the registers we need to pop. */ | |
12979 | regs_to_pop = 0; | |
12980 | pops_needed = 0; | |
12981 | ||
c9ca9b88 | 12982 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 12983 | { |
d5b7b3ae | 12984 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 12985 | ++pops_needed; |
d5b7b3ae RE |
12986 | } |
12987 | ||
12988 | if (TARGET_BACKTRACE) | |
12989 | { | |
12990 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
12991 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
12992 | pops_needed += 2; | |
12993 | } | |
12994 | ||
12995 | /* If there is nothing to pop then just emit the BX instruction and | |
12996 | return. */ | |
12997 | if (pops_needed == 0) | |
12998 | { | |
c9ca9b88 PB |
12999 | if (current_function_calls_eh_return) |
13000 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); | |
d5b7b3ae RE |
13001 | |
13002 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
13003 | return; | |
13004 | } | |
13005 | /* Otherwise if we are not supporting interworking and we have not created | |
13006 | a backtrace structure and the function was not entered in ARM mode then | |
13007 | just pop the return address straight into the PC. */ | |
5895f793 RE |
13008 | else if (!TARGET_INTERWORK |
13009 | && !TARGET_BACKTRACE | |
c9ca9b88 PB |
13010 | && !is_called_in_ARM_mode (current_function_decl) |
13011 | && !current_function_calls_eh_return) | |
d5b7b3ae | 13012 | { |
c9ca9b88 | 13013 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
13014 | return; |
13015 | } | |
13016 | ||
13017 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
13018 | regs_available_for_popping = 0; | |
13019 | ||
13020 | /* If returning via __builtin_eh_return, the bottom three registers | |
13021 | all contain information needed for the return. */ | |
c9ca9b88 | 13022 | if (current_function_calls_eh_return) |
d5b7b3ae RE |
13023 | size = 12; |
13024 | else | |
13025 | { | |
d5b7b3ae RE |
13026 | /* If we can deduce the registers used from the function's |
13027 | return value. This is more reliable that examining | |
13028 | regs_ever_live[] because that will be set if the register is | |
13029 | ever used in the function, not just if the register is used | |
13030 | to hold a return value. */ | |
13031 | ||
13032 | if (current_function_return_rtx != 0) | |
13033 | mode = GET_MODE (current_function_return_rtx); | |
13034 | else | |
d5b7b3ae RE |
13035 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
13036 | ||
13037 | size = GET_MODE_SIZE (mode); | |
13038 | ||
13039 | if (size == 0) | |
13040 | { | |
13041 | /* In a void function we can use any argument register. | |
13042 | In a function that returns a structure on the stack | |
13043 | we can use the second and third argument registers. */ | |
13044 | if (mode == VOIDmode) | |
13045 | regs_available_for_popping = | |
13046 | (1 << ARG_REGISTER (1)) | |
13047 | | (1 << ARG_REGISTER (2)) | |
13048 | | (1 << ARG_REGISTER (3)); | |
13049 | else | |
13050 | regs_available_for_popping = | |
13051 | (1 << ARG_REGISTER (2)) | |
13052 | | (1 << ARG_REGISTER (3)); | |
13053 | } | |
13054 | else if (size <= 4) | |
13055 | regs_available_for_popping = | |
13056 | (1 << ARG_REGISTER (2)) | |
13057 | | (1 << ARG_REGISTER (3)); | |
13058 | else if (size <= 8) | |
13059 | regs_available_for_popping = | |
13060 | (1 << ARG_REGISTER (3)); | |
13061 | } | |
13062 | ||
13063 | /* Match registers to be popped with registers into which we pop them. */ | |
13064 | for (available = regs_available_for_popping, | |
13065 | required = regs_to_pop; | |
13066 | required != 0 && available != 0; | |
13067 | available &= ~(available & - available), | |
13068 | required &= ~(required & - required)) | |
13069 | -- pops_needed; | |
13070 | ||
13071 | /* If we have any popping registers left over, remove them. */ | |
13072 | if (available > 0) | |
5895f793 | 13073 | regs_available_for_popping &= ~available; |
f676971a | 13074 | |
d5b7b3ae RE |
13075 | /* Otherwise if we need another popping register we can use |
13076 | the fourth argument register. */ | |
13077 | else if (pops_needed) | |
13078 | { | |
13079 | /* If we have not found any free argument registers and | |
13080 | reg a4 contains the return address, we must move it. */ | |
13081 | if (regs_available_for_popping == 0 | |
13082 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
13083 | { | |
13084 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
13085 | reg_containing_return_addr = LR_REGNUM; | |
13086 | } | |
13087 | else if (size > 12) | |
13088 | { | |
13089 | /* Register a4 is being used to hold part of the return value, | |
13090 | but we have dire need of a free, low register. */ | |
13091 | restore_a4 = TRUE; | |
f676971a | 13092 | |
d5b7b3ae RE |
13093 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
13094 | } | |
f676971a | 13095 | |
d5b7b3ae RE |
13096 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
13097 | { | |
13098 | /* The fourth argument register is available. */ | |
13099 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 13100 | |
5895f793 | 13101 | --pops_needed; |
d5b7b3ae RE |
13102 | } |
13103 | } | |
13104 | ||
13105 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
13106 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
13107 | regs_available_for_popping); | |
d5b7b3ae RE |
13108 | |
13109 | /* Process the registers we popped. */ | |
13110 | if (reg_containing_return_addr == -1) | |
13111 | { | |
13112 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 13113 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 13114 | |
d5b7b3ae RE |
13115 | reg_containing_return_addr = |
13116 | number_of_first_bit_set (regs_available_for_popping); | |
13117 | ||
13118 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 13119 | the return address will not be corrupted by further pops. */ |
5895f793 | 13120 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
13121 | } |
13122 | ||
13123 | /* If we popped other registers then handle them here. */ | |
13124 | if (regs_available_for_popping) | |
13125 | { | |
13126 | int frame_pointer; | |
f676971a | 13127 | |
d5b7b3ae RE |
13128 | /* Work out which register currently contains the frame pointer. */ |
13129 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
13130 | ||
13131 | /* Move it into the correct place. */ | |
13132 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
13133 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
13134 | ||
13135 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
13136 | regs_available_for_popping &= ~(1 << frame_pointer); |
13137 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 13138 | |
d5b7b3ae RE |
13139 | if (regs_available_for_popping) |
13140 | { | |
13141 | int stack_pointer; | |
f676971a | 13142 | |
d5b7b3ae RE |
13143 | /* We popped the stack pointer as well, |
13144 | find the register that contains it. */ | |
13145 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
13146 | ||
13147 | /* Move it into the stack register. */ | |
13148 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 13149 | |
d5b7b3ae RE |
13150 | /* At this point we have popped all necessary registers, so |
13151 | do not worry about restoring regs_available_for_popping | |
13152 | to its correct value: | |
13153 | ||
13154 | assert (pops_needed == 0) | |
13155 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
13156 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
13157 | } | |
13158 | else | |
13159 | { | |
13160 | /* Since we have just move the popped value into the frame | |
13161 | pointer, the popping register is available for reuse, and | |
13162 | we know that we still have the stack pointer left to pop. */ | |
13163 | regs_available_for_popping |= (1 << frame_pointer); | |
13164 | } | |
13165 | } | |
f676971a | 13166 | |
d5b7b3ae RE |
13167 | /* If we still have registers left on the stack, but we no longer have |
13168 | any registers into which we can pop them, then we must move the return | |
13169 | address into the link register and make available the register that | |
13170 | contained it. */ | |
13171 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
13172 | { | |
13173 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 13174 | |
d5b7b3ae RE |
13175 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
13176 | reg_containing_return_addr); | |
f676971a | 13177 | |
d5b7b3ae RE |
13178 | reg_containing_return_addr = LR_REGNUM; |
13179 | } | |
13180 | ||
13181 | /* If we have registers left on the stack then pop some more. | |
13182 | We know that at most we will want to pop FP and SP. */ | |
13183 | if (pops_needed > 0) | |
13184 | { | |
13185 | int popped_into; | |
13186 | int move_to; | |
f676971a | 13187 | |
980e61bb DJ |
13188 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
13189 | regs_available_for_popping); | |
d5b7b3ae RE |
13190 | |
13191 | /* We have popped either FP or SP. | |
13192 | Move whichever one it is into the correct register. */ | |
13193 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
13194 | move_to = number_of_first_bit_set (regs_to_pop); | |
13195 | ||
13196 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
13197 | ||
5895f793 | 13198 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 13199 | |
5895f793 | 13200 | --pops_needed; |
d5b7b3ae | 13201 | } |
f676971a | 13202 | |
d5b7b3ae RE |
13203 | /* If we still have not popped everything then we must have only |
13204 | had one register available to us and we are now popping the SP. */ | |
13205 | if (pops_needed > 0) | |
13206 | { | |
13207 | int popped_into; | |
f676971a | 13208 | |
980e61bb DJ |
13209 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
13210 | regs_available_for_popping); | |
d5b7b3ae RE |
13211 | |
13212 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
13213 | ||
13214 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
13215 | /* | |
13216 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
13217 | assert (pops_needed == 1) | |
13218 | */ | |
13219 | } | |
13220 | ||
13221 | /* If necessary restore the a4 register. */ | |
13222 | if (restore_a4) | |
13223 | { | |
13224 | if (reg_containing_return_addr != LR_REGNUM) | |
13225 | { | |
13226 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
13227 | reg_containing_return_addr = LR_REGNUM; | |
13228 | } | |
f676971a | 13229 | |
d5b7b3ae RE |
13230 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
13231 | } | |
13232 | ||
c9ca9b88 PB |
13233 | if (current_function_calls_eh_return) |
13234 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); | |
d5b7b3ae RE |
13235 | |
13236 | /* Return to caller. */ | |
13237 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
13238 | } | |
13239 | ||
d5b7b3ae RE |
13240 | \f |
13241 | void | |
e32bac5b | 13242 | thumb_final_prescan_insn (rtx insn) |
d5b7b3ae | 13243 | { |
d5b7b3ae | 13244 | if (flag_print_asm_name) |
9d98a694 AO |
13245 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
13246 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
13247 | } |
13248 | ||
13249 | int | |
e32bac5b | 13250 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
13251 | { |
13252 | unsigned HOST_WIDE_INT mask = 0xff; | |
13253 | int i; | |
13254 | ||
13255 | if (val == 0) /* XXX */ | |
13256 | return 0; | |
f676971a | 13257 | |
d5b7b3ae RE |
13258 | for (i = 0; i < 25; i++) |
13259 | if ((val & (mask << i)) == val) | |
13260 | return 1; | |
13261 | ||
13262 | return 0; | |
13263 | } | |
13264 | ||
825dda42 | 13265 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 13266 | or might contain a far jump. */ |
5848830f PB |
13267 | static int |
13268 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
13269 | { |
13270 | rtx insn; | |
13271 | ||
13272 | /* This test is only important for leaf functions. */ | |
5895f793 | 13273 | /* assert (!leaf_function_p ()); */ |
f676971a | 13274 | |
d5b7b3ae RE |
13275 | /* If we have already decided that far jumps may be used, |
13276 | do not bother checking again, and always return true even if | |
13277 | it turns out that they are not being used. Once we have made | |
13278 | the decision that far jumps are present (and that hence the link | |
13279 | register will be pushed onto the stack) we cannot go back on it. */ | |
13280 | if (cfun->machine->far_jump_used) | |
13281 | return 1; | |
13282 | ||
13283 | /* If this function is not being called from the prologue/epilogue | |
13284 | generation code then it must be being called from the | |
13285 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 13286 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
13287 | { |
13288 | /* In this case we know that we are being asked about the elimination | |
13289 | of the arg pointer register. If that register is not being used, | |
13290 | then there are no arguments on the stack, and we do not have to | |
13291 | worry that a far jump might force the prologue to push the link | |
13292 | register, changing the stack offsets. In this case we can just | |
13293 | return false, since the presence of far jumps in the function will | |
13294 | not affect stack offsets. | |
13295 | ||
13296 | If the arg pointer is live (or if it was live, but has now been | |
13297 | eliminated and so set to dead) then we do have to test to see if | |
13298 | the function might contain a far jump. This test can lead to some | |
13299 | false negatives, since before reload is completed, then length of | |
13300 | branch instructions is not known, so gcc defaults to returning their | |
13301 | longest length, which in turn sets the far jump attribute to true. | |
13302 | ||
13303 | A false negative will not result in bad code being generated, but it | |
13304 | will result in a needless push and pop of the link register. We | |
5848830f PB |
13305 | hope that this does not occur too often. |
13306 | ||
13307 | If we need doubleword stack alignment this could affect the other | |
13308 | elimination offsets so we can't risk getting it wrong. */ | |
d5b7b3ae RE |
13309 | if (regs_ever_live [ARG_POINTER_REGNUM]) |
13310 | cfun->machine->arg_pointer_live = 1; | |
5895f793 | 13311 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
13312 | return 0; |
13313 | } | |
13314 | ||
13315 | /* Check to see if the function contains a branch | |
13316 | insn with the far jump attribute set. */ | |
13317 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
13318 | { | |
13319 | if (GET_CODE (insn) == JUMP_INSN | |
13320 | /* Ignore tablejump patterns. */ | |
13321 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
13322 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
13323 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
13324 | ) | |
13325 | { | |
9a9f7594 | 13326 | /* Record the fact that we have decided that |
d5b7b3ae RE |
13327 | the function does use far jumps. */ |
13328 | cfun->machine->far_jump_used = 1; | |
13329 | return 1; | |
13330 | } | |
13331 | } | |
f676971a | 13332 | |
d5b7b3ae RE |
13333 | return 0; |
13334 | } | |
13335 | ||
825dda42 | 13336 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 13337 | int |
e32bac5b | 13338 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 13339 | { |
e6d29d15 | 13340 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 13341 | |
696e78bf | 13342 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
13343 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
13344 | return TRUE; | |
13345 | ||
f676971a | 13346 | #ifdef ARM_PE |
91d231cb | 13347 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
13348 | #else |
13349 | return FALSE; | |
13350 | #endif | |
13351 | } | |
13352 | ||
d6b4baa4 | 13353 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 13354 | const char * |
e32bac5b | 13355 | thumb_unexpanded_epilogue (void) |
d5b7b3ae RE |
13356 | { |
13357 | int regno; | |
b279b20a | 13358 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 13359 | int high_regs_pushed = 0; |
d5b7b3ae | 13360 | int had_to_push_lr; |
57934c39 | 13361 | int size; |
d5b7b3ae RE |
13362 | |
13363 | if (return_used_this_function) | |
13364 | return ""; | |
13365 | ||
58e60158 AN |
13366 | if (IS_NAKED (arm_current_func_type ())) |
13367 | return ""; | |
13368 | ||
57934c39 PB |
13369 | live_regs_mask = thumb_compute_save_reg_mask (); |
13370 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
13371 | ||
13372 | /* If we can deduce the registers used from the function's return value. | |
13373 | This is more reliable that examining regs_ever_live[] because that | |
13374 | will be set if the register is ever used in the function, not just if | |
13375 | the register is used to hold a return value. */ | |
4f5dfed0 | 13376 | size = arm_size_return_regs (); |
d5b7b3ae RE |
13377 | |
13378 | /* The prolog may have pushed some high registers to use as | |
112cdef5 | 13379 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
13380 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
13381 | compiles to produce: | |
13382 | push {r4, r5, r6, r7, lr} | |
13383 | mov r7, r9 | |
13384 | mov r6, r8 | |
13385 | push {r6, r7} | |
13386 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 13387 | |
d5b7b3ae RE |
13388 | if (high_regs_pushed) |
13389 | { | |
b279b20a | 13390 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 13391 | int next_hi_reg; |
d5b7b3ae | 13392 | |
57934c39 PB |
13393 | /* The available low registers depend on the size of the value we are |
13394 | returning. */ | |
13395 | if (size <= 12) | |
d5b7b3ae | 13396 | mask |= 1 << 3; |
57934c39 PB |
13397 | if (size <= 8) |
13398 | mask |= 1 << 2; | |
d5b7b3ae RE |
13399 | |
13400 | if (mask == 0) | |
13401 | /* Oh dear! We have no low registers into which we can pop | |
13402 | high registers! */ | |
400500c4 RK |
13403 | internal_error |
13404 | ("no low registers available for popping high registers"); | |
f676971a | 13405 | |
d5b7b3ae | 13406 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 13407 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
13408 | break; |
13409 | ||
13410 | while (high_regs_pushed) | |
13411 | { | |
13412 | /* Find lo register(s) into which the high register(s) can | |
13413 | be popped. */ | |
13414 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
13415 | { | |
13416 | if (mask & (1 << regno)) | |
13417 | high_regs_pushed--; | |
13418 | if (high_regs_pushed == 0) | |
13419 | break; | |
13420 | } | |
13421 | ||
13422 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
13423 | ||
d6b4baa4 | 13424 | /* Pop the values into the low register(s). */ |
980e61bb | 13425 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
13426 | |
13427 | /* Move the value(s) into the high registers. */ | |
13428 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
13429 | { | |
13430 | if (mask & (1 << regno)) | |
13431 | { | |
13432 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
13433 | regno); | |
f676971a | 13434 | |
d5b7b3ae | 13435 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 13436 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
13437 | break; |
13438 | } | |
13439 | } | |
13440 | } | |
57934c39 | 13441 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
13442 | } |
13443 | ||
57934c39 PB |
13444 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
13445 | live_regs_mask &= 0xff; | |
13446 | ||
d5b7b3ae RE |
13447 | if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) |
13448 | { | |
f676971a | 13449 | /* Pop the return address into the PC. */ |
57934c39 | 13450 | if (had_to_push_lr) |
d5b7b3ae RE |
13451 | live_regs_mask |= 1 << PC_REGNUM; |
13452 | ||
13453 | /* Either no argument registers were pushed or a backtrace | |
13454 | structure was created which includes an adjusted stack | |
13455 | pointer, so just pop everything. */ | |
13456 | if (live_regs_mask) | |
980e61bb DJ |
13457 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
13458 | live_regs_mask); | |
57934c39 | 13459 | |
d5b7b3ae | 13460 | /* We have either just popped the return address into the |
57934c39 PB |
13461 | PC or it is was kept in LR for the entire function. */ |
13462 | if (!had_to_push_lr) | |
13463 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
13464 | } |
13465 | else | |
13466 | { | |
13467 | /* Pop everything but the return address. */ | |
d5b7b3ae | 13468 | if (live_regs_mask) |
980e61bb DJ |
13469 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
13470 | live_regs_mask); | |
d5b7b3ae RE |
13471 | |
13472 | if (had_to_push_lr) | |
57934c39 PB |
13473 | { |
13474 | if (size > 12) | |
13475 | { | |
13476 | /* We have no free low regs, so save one. */ | |
13477 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
13478 | LAST_ARG_REGNUM); | |
13479 | } | |
13480 | ||
13481 | /* Get the return address into a temporary register. */ | |
13482 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
13483 | 1 << LAST_ARG_REGNUM); | |
13484 | ||
13485 | if (size > 12) | |
13486 | { | |
13487 | /* Move the return address to lr. */ | |
13488 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
13489 | LAST_ARG_REGNUM); | |
13490 | /* Restore the low register. */ | |
13491 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
13492 | IP_REGNUM); | |
13493 | regno = LR_REGNUM; | |
13494 | } | |
13495 | else | |
13496 | regno = LAST_ARG_REGNUM; | |
13497 | } | |
13498 | else | |
13499 | regno = LR_REGNUM; | |
f676971a | 13500 | |
d5b7b3ae RE |
13501 | /* Remove the argument registers that were pushed onto the stack. */ |
13502 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
13503 | SP_REGNUM, SP_REGNUM, | |
13504 | current_function_pretend_args_size); | |
f676971a | 13505 | |
57934c39 | 13506 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
13507 | } |
13508 | ||
13509 | return ""; | |
13510 | } | |
13511 | ||
13512 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 13513 | static struct machine_function * |
e32bac5b | 13514 | arm_init_machine_status (void) |
d5b7b3ae | 13515 | { |
e2500fed GK |
13516 | struct machine_function *machine; |
13517 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 13518 | |
f676971a | 13519 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 13520 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 13521 | #endif |
e2500fed | 13522 | return machine; |
f7a80099 NC |
13523 | } |
13524 | ||
d5b7b3ae RE |
13525 | /* Return an RTX indicating where the return address to the |
13526 | calling function can be found. */ | |
13527 | rtx | |
e32bac5b | 13528 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 13529 | { |
d5b7b3ae RE |
13530 | if (count != 0) |
13531 | return NULL_RTX; | |
13532 | ||
61f0ccff | 13533 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
13534 | } |
13535 | ||
13536 | /* Do anything needed before RTL is emitted for each function. */ | |
13537 | void | |
e32bac5b | 13538 | arm_init_expanders (void) |
d5b7b3ae RE |
13539 | { |
13540 | /* Arrange to initialize and mark the machine per-function status. */ | |
13541 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
13542 | |
13543 | /* This is to stop the combine pass optimizing away the alignment | |
13544 | adjustment of va_arg. */ | |
13545 | /* ??? It is claimed that this should not be necessary. */ | |
13546 | if (cfun) | |
13547 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
13548 | } |
13549 | ||
0977774b | 13550 | |
2591db65 RE |
13551 | /* Like arm_compute_initial_elimination offset. Simpler because there |
13552 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
13553 | to point at the base of the local variables after static stack | |
13554 | space for a function has been allocated. */ | |
0977774b | 13555 | |
5848830f PB |
13556 | HOST_WIDE_INT |
13557 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
13558 | { | |
13559 | arm_stack_offsets *offsets; | |
0977774b | 13560 | |
5848830f | 13561 | offsets = arm_get_frame_offsets (); |
0977774b | 13562 | |
5848830f | 13563 | switch (from) |
0977774b | 13564 | { |
5848830f PB |
13565 | case ARG_POINTER_REGNUM: |
13566 | switch (to) | |
13567 | { | |
13568 | case STACK_POINTER_REGNUM: | |
13569 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 13570 | |
5848830f PB |
13571 | case FRAME_POINTER_REGNUM: |
13572 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 13573 | |
5848830f PB |
13574 | case ARM_HARD_FRAME_POINTER_REGNUM: |
13575 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 13576 | |
2591db65 RE |
13577 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
13578 | return offsets->locals_base - offsets->saved_args; | |
13579 | ||
5848830f | 13580 | default: |
e6d29d15 | 13581 | gcc_unreachable (); |
5848830f PB |
13582 | } |
13583 | break; | |
0977774b | 13584 | |
5848830f PB |
13585 | case FRAME_POINTER_REGNUM: |
13586 | switch (to) | |
13587 | { | |
13588 | case STACK_POINTER_REGNUM: | |
13589 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 13590 | |
5848830f PB |
13591 | case ARM_HARD_FRAME_POINTER_REGNUM: |
13592 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 13593 | |
2591db65 RE |
13594 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
13595 | return offsets->locals_base - offsets->soft_frame; | |
13596 | ||
5848830f | 13597 | default: |
e6d29d15 | 13598 | gcc_unreachable (); |
5848830f PB |
13599 | } |
13600 | break; | |
0977774b | 13601 | |
5848830f | 13602 | default: |
e6d29d15 | 13603 | gcc_unreachable (); |
5848830f | 13604 | } |
0977774b JT |
13605 | } |
13606 | ||
5848830f | 13607 | |
d5b7b3ae RE |
13608 | /* Generate the rest of a function's prologue. */ |
13609 | void | |
e32bac5b | 13610 | thumb_expand_prologue (void) |
d5b7b3ae | 13611 | { |
980e61bb DJ |
13612 | rtx insn, dwarf; |
13613 | ||
5848830f PB |
13614 | HOST_WIDE_INT amount; |
13615 | arm_stack_offsets *offsets; | |
6d3d9133 | 13616 | unsigned long func_type; |
3c7ad43e | 13617 | int regno; |
57934c39 | 13618 | unsigned long live_regs_mask; |
6d3d9133 NC |
13619 | |
13620 | func_type = arm_current_func_type (); | |
f676971a | 13621 | |
d5b7b3ae | 13622 | /* Naked functions don't have prologues. */ |
6d3d9133 | 13623 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
13624 | return; |
13625 | ||
6d3d9133 NC |
13626 | if (IS_INTERRUPT (func_type)) |
13627 | { | |
c725bd79 | 13628 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
13629 | return; |
13630 | } | |
13631 | ||
fe013435 | 13632 | live_regs_mask = thumb_compute_save_reg_mask (); |
b279b20a NC |
13633 | /* Load the pic register before setting the frame pointer, |
13634 | so we can use r7 as a temporary work register. */ | |
020a4035 | 13635 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 13636 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 13637 | |
2591db65 | 13638 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
13639 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
13640 | stack_pointer_rtx); | |
d5b7b3ae | 13641 | |
2591db65 | 13642 | offsets = arm_get_frame_offsets (); |
5848830f | 13643 | amount = offsets->outgoing_args - offsets->saved_regs; |
d5b7b3ae RE |
13644 | if (amount) |
13645 | { | |
d5b7b3ae | 13646 | if (amount < 512) |
980e61bb DJ |
13647 | { |
13648 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
13649 | GEN_INT (- amount))); | |
13650 | RTX_FRAME_RELATED_P (insn) = 1; | |
13651 | } | |
d5b7b3ae RE |
13652 | else |
13653 | { | |
d5b7b3ae RE |
13654 | rtx reg; |
13655 | ||
13656 | /* The stack decrement is too big for an immediate value in a single | |
13657 | insn. In theory we could issue multiple subtracts, but after | |
13658 | three of them it becomes more space efficient to place the full | |
13659 | value in the constant pool and load into a register. (Also the | |
13660 | ARM debugger really likes to see only one stack decrement per | |
13661 | function). So instead we look for a scratch register into which | |
13662 | we can load the decrement, and then we subtract this from the | |
13663 | stack pointer. Unfortunately on the thumb the only available | |
13664 | scratch registers are the argument registers, and we cannot use | |
13665 | these as they may hold arguments to the function. Instead we | |
13666 | attempt to locate a call preserved register which is used by this | |
13667 | function. If we can find one, then we know that it will have | |
13668 | been pushed at the start of the prologue and so we can corrupt | |
13669 | it now. */ | |
13670 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
57934c39 | 13671 | if (live_regs_mask & (1 << regno) |
5895f793 RE |
13672 | && !(frame_pointer_needed |
13673 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
13674 | break; |
13675 | ||
aeaf4d25 | 13676 | if (regno > LAST_LO_REGNUM) /* Very unlikely. */ |
d5b7b3ae | 13677 | { |
f1c25d3b | 13678 | rtx spare = gen_rtx_REG (SImode, IP_REGNUM); |
d5b7b3ae | 13679 | |
6bc82793 | 13680 | /* Choose an arbitrary, non-argument low register. */ |
f1c25d3b | 13681 | reg = gen_rtx_REG (SImode, LAST_LO_REGNUM); |
d5b7b3ae RE |
13682 | |
13683 | /* Save it by copying it into a high, scratch register. */ | |
c14a3a45 NC |
13684 | emit_insn (gen_movsi (spare, reg)); |
13685 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 13686 | emit_insn (gen_prologue_use (spare)); |
d5b7b3ae RE |
13687 | |
13688 | /* Decrement the stack. */ | |
1d6e90ac | 13689 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
13690 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
13691 | stack_pointer_rtx, reg)); | |
13692 | RTX_FRAME_RELATED_P (insn) = 1; | |
d66437c5 | 13693 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, |
980e61bb | 13694 | plus_constant (stack_pointer_rtx, |
78773322 | 13695 | -amount)); |
980e61bb DJ |
13696 | RTX_FRAME_RELATED_P (dwarf) = 1; |
13697 | REG_NOTES (insn) | |
13698 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
13699 | REG_NOTES (insn)); | |
d5b7b3ae RE |
13700 | |
13701 | /* Restore the low register's original value. */ | |
13702 | emit_insn (gen_movsi (reg, spare)); | |
f676971a | 13703 | |
d5b7b3ae RE |
13704 | /* Emit a USE of the restored scratch register, so that flow |
13705 | analysis will not consider the restore redundant. The | |
13706 | register won't be used again in this function and isn't | |
13707 | restored by the epilogue. */ | |
6bacc7b0 | 13708 | emit_insn (gen_prologue_use (reg)); |
d5b7b3ae RE |
13709 | } |
13710 | else | |
13711 | { | |
f1c25d3b | 13712 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 13713 | |
1d6e90ac | 13714 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
13715 | |
13716 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, | |
13717 | stack_pointer_rtx, reg)); | |
13718 | RTX_FRAME_RELATED_P (insn) = 1; | |
d66437c5 | 13719 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, |
980e61bb | 13720 | plus_constant (stack_pointer_rtx, |
78773322 | 13721 | -amount)); |
980e61bb DJ |
13722 | RTX_FRAME_RELATED_P (dwarf) = 1; |
13723 | REG_NOTES (insn) | |
13724 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
13725 | REG_NOTES (insn)); | |
d5b7b3ae RE |
13726 | } |
13727 | } | |
2591db65 RE |
13728 | } |
13729 | ||
13730 | if (frame_pointer_needed) | |
13731 | { | |
13732 | amount = offsets->outgoing_args - offsets->locals_base; | |
e0b92319 | 13733 | |
2591db65 RE |
13734 | if (amount < 1024) |
13735 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13736 | stack_pointer_rtx, GEN_INT (amount))); | |
13737 | else | |
13738 | { | |
13739 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
13740 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13741 | hard_frame_pointer_rtx, | |
13742 | stack_pointer_rtx)); | |
d66437c5 | 13743 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
2591db65 RE |
13744 | plus_constant (stack_pointer_rtx, amount)); |
13745 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
13746 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
13747 | REG_NOTES (insn)); | |
13748 | } | |
13749 | ||
13750 | RTX_FRAME_RELATED_P (insn) = 1; | |
d5b7b3ae | 13751 | } |
f676971a | 13752 | |
74d9c39f DJ |
13753 | /* If we are profiling, make sure no instructions are scheduled before |
13754 | the call to mcount. Similarly if the user has requested no | |
13755 | scheduling in the prolog. Similarly if we want non-call exceptions | |
13756 | using the EABI unwinder, to prevent faulting instructions from being | |
13757 | swapped with a stack adjustment. */ | |
13758 | if (current_function_profile || !TARGET_SCHED_PROLOG | |
13759 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) | |
d5b7b3ae | 13760 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
13761 | |
13762 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
13763 | if (live_regs_mask & 0xff) |
13764 | cfun->machine->lr_save_eliminated = 0; | |
3c7ad43e PB |
13765 | |
13766 | /* If the link register is being kept alive, with the return address in it, | |
13767 | then make sure that it does not get reused by the ce2 pass. */ | |
13768 | if (cfun->machine->lr_save_eliminated) | |
13769 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); | |
d5b7b3ae RE |
13770 | } |
13771 | ||
57934c39 | 13772 | |
d5b7b3ae | 13773 | void |
e32bac5b | 13774 | thumb_expand_epilogue (void) |
d5b7b3ae | 13775 | { |
5848830f PB |
13776 | HOST_WIDE_INT amount; |
13777 | arm_stack_offsets *offsets; | |
defc0463 RE |
13778 | int regno; |
13779 | ||
6d3d9133 NC |
13780 | /* Naked functions don't have prologues. */ |
13781 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
13782 | return; |
13783 | ||
5848830f PB |
13784 | offsets = arm_get_frame_offsets (); |
13785 | amount = offsets->outgoing_args - offsets->saved_regs; | |
13786 | ||
d5b7b3ae | 13787 | if (frame_pointer_needed) |
2591db65 RE |
13788 | { |
13789 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
13790 | amount = offsets->locals_base - offsets->saved_regs; | |
13791 | } | |
e0b92319 | 13792 | |
2591db65 | 13793 | if (amount) |
d5b7b3ae | 13794 | { |
d5b7b3ae RE |
13795 | if (amount < 512) |
13796 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
13797 | GEN_INT (amount))); | |
13798 | else | |
13799 | { | |
13800 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 13801 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
13802 | |
13803 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
13804 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
13805 | } | |
13806 | } | |
f676971a | 13807 | |
d5b7b3ae RE |
13808 | /* Emit a USE (stack_pointer_rtx), so that |
13809 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 13810 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 13811 | |
c54c7322 | 13812 | if (current_function_profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 13813 | emit_insn (gen_blockage ()); |
defc0463 RE |
13814 | |
13815 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
13816 | so that flow2 will get register lifetimes correct. */ | |
13817 | for (regno = 0; regno < 13; regno++) | |
13818 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
13819 | emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno))); | |
13820 | ||
13821 | if (! regs_ever_live[LR_REGNUM]) | |
13822 | emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))); | |
d5b7b3ae RE |
13823 | } |
13824 | ||
08c148a8 | 13825 | static void |
e32bac5b | 13826 | thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 13827 | { |
b279b20a NC |
13828 | unsigned long live_regs_mask = 0; |
13829 | unsigned long l_mask; | |
13830 | unsigned high_regs_pushed = 0; | |
980e61bb | 13831 | int cfa_offset = 0; |
d5b7b3ae RE |
13832 | int regno; |
13833 | ||
6d3d9133 | 13834 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
13835 | return; |
13836 | ||
13837 | if (is_called_in_ARM_mode (current_function_decl)) | |
13838 | { | |
13839 | const char * name; | |
13840 | ||
e6d29d15 NS |
13841 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
13842 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
13843 | == SYMBOL_REF); | |
d5b7b3ae | 13844 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 13845 | |
d5b7b3ae RE |
13846 | /* Generate code sequence to switch us into Thumb mode. */ |
13847 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 13848 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
13849 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
13850 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
13851 | ||
13852 | /* Generate a label, so that the debugger will notice the | |
13853 | change in instruction sets. This label is also used by | |
13854 | the assembler to bypass the ARM code when this function | |
13855 | is called from a Thumb encoded function elsewhere in the | |
13856 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 13857 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 13858 | |
d5b7b3ae | 13859 | #define STUB_NAME ".real_start_of" |
f676971a | 13860 | |
761c70aa | 13861 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
13862 | #ifdef ARM_PE |
13863 | if (arm_dllexport_name_p (name)) | |
e5951263 | 13864 | name = arm_strip_name_encoding (name); |
f676971a | 13865 | #endif |
d5b7b3ae | 13866 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 13867 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
13868 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
13869 | } | |
f676971a | 13870 | |
d5b7b3ae RE |
13871 | if (current_function_pretend_args_size) |
13872 | { | |
617a1b71 PB |
13873 | /* Output unwind directive for the stack adjustment. */ |
13874 | if (ARM_EABI_UNWIND_TABLES) | |
13875 | fprintf (f, "\t.pad #%d\n", | |
13876 | current_function_pretend_args_size); | |
13877 | ||
3cb66fd7 | 13878 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
13879 | { |
13880 | int num_pushes; | |
f676971a | 13881 | |
761c70aa | 13882 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 13883 | |
e9d7b180 | 13884 | num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); |
f676971a | 13885 | |
d5b7b3ae RE |
13886 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
13887 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 13888 | regno++) |
d5b7b3ae RE |
13889 | asm_fprintf (f, "%r%s", regno, |
13890 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
13891 | ||
761c70aa | 13892 | fprintf (f, "}\n"); |
d5b7b3ae RE |
13893 | } |
13894 | else | |
f676971a | 13895 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae RE |
13896 | SP_REGNUM, SP_REGNUM, |
13897 | current_function_pretend_args_size); | |
980e61bb DJ |
13898 | |
13899 | /* We don't need to record the stores for unwinding (would it | |
13900 | help the debugger any if we did?), but record the change in | |
13901 | the stack pointer. */ | |
13902 | if (dwarf2out_do_frame ()) | |
13903 | { | |
13904 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 13905 | |
980e61bb DJ |
13906 | cfa_offset = cfa_offset + current_function_pretend_args_size; |
13907 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
13908 | } | |
d5b7b3ae RE |
13909 | } |
13910 | ||
b279b20a | 13911 | /* Get the registers we are going to push. */ |
57934c39 | 13912 | live_regs_mask = thumb_compute_save_reg_mask (); |
b279b20a | 13913 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 13914 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
13915 | /* Then count how many other high registers will need to be pushed. */ |
13916 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
13917 | |
13918 | if (TARGET_BACKTRACE) | |
13919 | { | |
b279b20a NC |
13920 | unsigned offset; |
13921 | unsigned work_register; | |
f676971a | 13922 | |
d5b7b3ae RE |
13923 | /* We have been asked to create a stack backtrace structure. |
13924 | The code looks like this: | |
f676971a | 13925 | |
d5b7b3ae RE |
13926 | 0 .align 2 |
13927 | 0 func: | |
13928 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 13929 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
13930 | 4 add R7, SP, #20 Get the stack pointer before the push. |
13931 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
13932 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
13933 | 10 str R7, [SP, #16] Store it. | |
13934 | 12 mov R7, FP Get hold of the current frame pointer. | |
13935 | 14 str R7, [SP, #4] Store it. | |
13936 | 16 mov R7, LR Get hold of the current return address. | |
13937 | 18 str R7, [SP, #12] Store it. | |
13938 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
13939 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
13940 | ||
57934c39 | 13941 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 13942 | |
617a1b71 PB |
13943 | if (ARM_EABI_UNWIND_TABLES) |
13944 | asm_fprintf (f, "\t.pad #16\n"); | |
13945 | ||
d5b7b3ae RE |
13946 | asm_fprintf |
13947 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
13948 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
13949 | |
13950 | if (dwarf2out_do_frame ()) | |
13951 | { | |
13952 | char *l = dwarf2out_cfi_label (); | |
b279b20a | 13953 | |
980e61bb DJ |
13954 | cfa_offset = cfa_offset + 16; |
13955 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
13956 | } | |
13957 | ||
57934c39 PB |
13958 | if (l_mask) |
13959 | { | |
13960 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 13961 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
13962 | } |
13963 | else | |
13964 | offset = 0; | |
f676971a | 13965 | |
d5b7b3ae RE |
13966 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
13967 | offset + 16 + current_function_pretend_args_size); | |
f676971a | 13968 | |
d5b7b3ae RE |
13969 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
13970 | offset + 4); | |
13971 | ||
13972 | /* Make sure that the instruction fetching the PC is in the right place | |
13973 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 13974 | if (l_mask) |
d5b7b3ae RE |
13975 | { |
13976 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
13977 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13978 | offset + 12); | |
13979 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
13980 | ARM_HARD_FRAME_POINTER_REGNUM); | |
13981 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13982 | offset); | |
13983 | } | |
13984 | else | |
13985 | { | |
13986 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
13987 | ARM_HARD_FRAME_POINTER_REGNUM); | |
13988 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13989 | offset); | |
13990 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
13991 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13992 | offset + 12); | |
13993 | } | |
f676971a | 13994 | |
d5b7b3ae RE |
13995 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
13996 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13997 | offset + 8); | |
13998 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
13999 | offset + 12); | |
14000 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
14001 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
14002 | } | |
0fa2e4df | 14003 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
14004 | to push some high registers then delay our first push. This will just |
14005 | be a push of LR and we can combine it with the push of the first high | |
14006 | register. */ | |
14007 | else if ((l_mask & 0xff) != 0 | |
14008 | || (high_regs_pushed == 0 && l_mask)) | |
57934c39 | 14009 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); |
d5b7b3ae | 14010 | |
d5b7b3ae RE |
14011 | if (high_regs_pushed) |
14012 | { | |
b279b20a NC |
14013 | unsigned pushable_regs; |
14014 | unsigned next_hi_reg; | |
d5b7b3ae RE |
14015 | |
14016 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 14017 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 14018 | break; |
d5b7b3ae | 14019 | |
57934c39 | 14020 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
14021 | |
14022 | if (pushable_regs == 0) | |
57934c39 | 14023 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
14024 | |
14025 | while (high_regs_pushed > 0) | |
14026 | { | |
b279b20a | 14027 | unsigned long real_regs_mask = 0; |
980e61bb | 14028 | |
b279b20a | 14029 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 14030 | { |
57934c39 | 14031 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
14032 | { |
14033 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 14034 | |
b279b20a | 14035 | high_regs_pushed --; |
980e61bb | 14036 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 14037 | |
d5b7b3ae | 14038 | if (high_regs_pushed) |
aeaf4d25 | 14039 | { |
b279b20a NC |
14040 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
14041 | next_hi_reg --) | |
57934c39 | 14042 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 14043 | break; |
aeaf4d25 | 14044 | } |
d5b7b3ae RE |
14045 | else |
14046 | { | |
57934c39 | 14047 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
14048 | break; |
14049 | } | |
14050 | } | |
14051 | } | |
980e61bb | 14052 | |
b279b20a NC |
14053 | /* If we had to find a work register and we have not yet |
14054 | saved the LR then add it to the list of regs to push. */ | |
14055 | if (l_mask == (1 << LR_REGNUM)) | |
14056 | { | |
14057 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
14058 | 1, &cfa_offset, | |
14059 | real_regs_mask | (1 << LR_REGNUM)); | |
14060 | l_mask = 0; | |
14061 | } | |
14062 | else | |
14063 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 14064 | } |
d5b7b3ae RE |
14065 | } |
14066 | } | |
14067 | ||
14068 | /* Handle the case of a double word load into a low register from | |
14069 | a computed memory address. The computed address may involve a | |
14070 | register which is overwritten by the load. */ | |
cd2b33d0 | 14071 | const char * |
e32bac5b | 14072 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
14073 | { |
14074 | rtx addr; | |
14075 | rtx base; | |
14076 | rtx offset; | |
14077 | rtx arg1; | |
14078 | rtx arg2; | |
f676971a | 14079 | |
e6d29d15 NS |
14080 | gcc_assert (GET_CODE (operands[0]) == REG); |
14081 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
14082 | |
14083 | /* Get the memory address. */ | |
14084 | addr = XEXP (operands[1], 0); | |
f676971a | 14085 | |
d5b7b3ae RE |
14086 | /* Work out how the memory address is computed. */ |
14087 | switch (GET_CODE (addr)) | |
14088 | { | |
14089 | case REG: | |
31fa16b6 | 14090 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 14091 | |
d5b7b3ae RE |
14092 | if (REGNO (operands[0]) == REGNO (addr)) |
14093 | { | |
14094 | output_asm_insn ("ldr\t%H0, %2", operands); | |
14095 | output_asm_insn ("ldr\t%0, %1", operands); | |
14096 | } | |
14097 | else | |
14098 | { | |
14099 | output_asm_insn ("ldr\t%0, %1", operands); | |
14100 | output_asm_insn ("ldr\t%H0, %2", operands); | |
14101 | } | |
14102 | break; | |
f676971a | 14103 | |
d5b7b3ae RE |
14104 | case CONST: |
14105 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 14106 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 14107 | |
d5b7b3ae RE |
14108 | output_asm_insn ("ldr\t%0, %1", operands); |
14109 | output_asm_insn ("ldr\t%H0, %2", operands); | |
14110 | break; | |
f676971a | 14111 | |
d5b7b3ae RE |
14112 | case PLUS: |
14113 | arg1 = XEXP (addr, 0); | |
14114 | arg2 = XEXP (addr, 1); | |
f676971a | 14115 | |
d5b7b3ae RE |
14116 | if (CONSTANT_P (arg1)) |
14117 | base = arg2, offset = arg1; | |
14118 | else | |
14119 | base = arg1, offset = arg2; | |
f676971a | 14120 | |
e6d29d15 | 14121 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
14122 | |
14123 | /* Catch the case of <address> = <reg> + <reg> */ | |
14124 | if (GET_CODE (offset) == REG) | |
14125 | { | |
14126 | int reg_offset = REGNO (offset); | |
14127 | int reg_base = REGNO (base); | |
14128 | int reg_dest = REGNO (operands[0]); | |
f676971a | 14129 | |
d5b7b3ae RE |
14130 | /* Add the base and offset registers together into the |
14131 | higher destination register. */ | |
14132 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
14133 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 14134 | |
d5b7b3ae RE |
14135 | /* Load the lower destination register from the address in |
14136 | the higher destination register. */ | |
14137 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
14138 | reg_dest, reg_dest + 1); | |
f676971a | 14139 | |
d5b7b3ae RE |
14140 | /* Load the higher destination register from its own address |
14141 | plus 4. */ | |
14142 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
14143 | reg_dest + 1, reg_dest + 1); | |
14144 | } | |
14145 | else | |
14146 | { | |
14147 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 14148 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 14149 | |
d5b7b3ae RE |
14150 | /* If the computed address is held in the low order register |
14151 | then load the high order register first, otherwise always | |
14152 | load the low order register first. */ | |
14153 | if (REGNO (operands[0]) == REGNO (base)) | |
14154 | { | |
14155 | output_asm_insn ("ldr\t%H0, %2", operands); | |
14156 | output_asm_insn ("ldr\t%0, %1", operands); | |
14157 | } | |
14158 | else | |
14159 | { | |
14160 | output_asm_insn ("ldr\t%0, %1", operands); | |
14161 | output_asm_insn ("ldr\t%H0, %2", operands); | |
14162 | } | |
14163 | } | |
14164 | break; | |
14165 | ||
14166 | case LABEL_REF: | |
14167 | /* With no registers to worry about we can just load the value | |
14168 | directly. */ | |
31fa16b6 | 14169 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 14170 | |
d5b7b3ae RE |
14171 | output_asm_insn ("ldr\t%H0, %2", operands); |
14172 | output_asm_insn ("ldr\t%0, %1", operands); | |
14173 | break; | |
f676971a | 14174 | |
d5b7b3ae | 14175 | default: |
e6d29d15 | 14176 | gcc_unreachable (); |
d5b7b3ae | 14177 | } |
f676971a | 14178 | |
d5b7b3ae RE |
14179 | return ""; |
14180 | } | |
14181 | ||
cd2b33d0 | 14182 | const char * |
e32bac5b | 14183 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
14184 | { |
14185 | rtx tmp; | |
14186 | ||
14187 | switch (n) | |
14188 | { | |
14189 | case 2: | |
ca356f3a | 14190 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 14191 | { |
ca356f3a RE |
14192 | tmp = operands[4]; |
14193 | operands[4] = operands[5]; | |
14194 | operands[5] = tmp; | |
d5b7b3ae | 14195 | } |
ca356f3a RE |
14196 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
14197 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
14198 | break; |
14199 | ||
14200 | case 3: | |
ca356f3a | 14201 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 14202 | { |
ca356f3a RE |
14203 | tmp = operands[4]; |
14204 | operands[4] = operands[5]; | |
14205 | operands[5] = tmp; | |
d5b7b3ae | 14206 | } |
ca356f3a | 14207 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 14208 | { |
ca356f3a RE |
14209 | tmp = operands[5]; |
14210 | operands[5] = operands[6]; | |
14211 | operands[6] = tmp; | |
d5b7b3ae | 14212 | } |
ca356f3a | 14213 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 14214 | { |
ca356f3a RE |
14215 | tmp = operands[4]; |
14216 | operands[4] = operands[5]; | |
14217 | operands[5] = tmp; | |
d5b7b3ae | 14218 | } |
f676971a | 14219 | |
ca356f3a RE |
14220 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
14221 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
14222 | break; |
14223 | ||
14224 | default: | |
e6d29d15 | 14225 | gcc_unreachable (); |
d5b7b3ae RE |
14226 | } |
14227 | ||
14228 | return ""; | |
14229 | } | |
14230 | ||
b12a00f1 RE |
14231 | /* Output a call-via instruction for thumb state. */ |
14232 | const char * | |
14233 | thumb_call_via_reg (rtx reg) | |
14234 | { | |
14235 | int regno = REGNO (reg); | |
14236 | rtx *labelp; | |
14237 | ||
57ecec57 | 14238 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
14239 | |
14240 | /* If we are in the normal text section we can use a single instance | |
14241 | per compilation unit. If we are doing function sections, then we need | |
14242 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 14243 | if (in_section == text_section) |
b12a00f1 RE |
14244 | { |
14245 | thumb_call_reg_needed = 1; | |
14246 | ||
14247 | if (thumb_call_via_label[regno] == NULL) | |
14248 | thumb_call_via_label[regno] = gen_label_rtx (); | |
14249 | labelp = thumb_call_via_label + regno; | |
14250 | } | |
14251 | else | |
14252 | { | |
14253 | if (cfun->machine->call_via[regno] == NULL) | |
14254 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
14255 | labelp = cfun->machine->call_via + regno; | |
14256 | } | |
14257 | ||
14258 | output_asm_insn ("bl\t%a0", labelp); | |
14259 | return ""; | |
14260 | } | |
14261 | ||
1d6e90ac | 14262 | /* Routines for generating rtl. */ |
d5b7b3ae | 14263 | void |
70128ad9 | 14264 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
14265 | { |
14266 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
14267 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
14268 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
14269 | HOST_WIDE_INT offset = 0; | |
14270 | ||
14271 | while (len >= 12) | |
14272 | { | |
ca356f3a | 14273 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
14274 | len -= 12; |
14275 | } | |
f676971a | 14276 | |
d5b7b3ae RE |
14277 | if (len >= 8) |
14278 | { | |
ca356f3a | 14279 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
14280 | len -= 8; |
14281 | } | |
f676971a | 14282 | |
d5b7b3ae RE |
14283 | if (len >= 4) |
14284 | { | |
14285 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
14286 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
14287 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
14288 | len -= 4; |
14289 | offset += 4; | |
14290 | } | |
f676971a | 14291 | |
d5b7b3ae RE |
14292 | if (len >= 2) |
14293 | { | |
14294 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 14295 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
14296 | plus_constant (in, offset)))); |
14297 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
14298 | reg)); |
14299 | len -= 2; | |
14300 | offset += 2; | |
14301 | } | |
f676971a | 14302 | |
d5b7b3ae RE |
14303 | if (len) |
14304 | { | |
14305 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
14306 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
14307 | plus_constant (in, offset)))); | |
14308 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
14309 | reg)); |
14310 | } | |
14311 | } | |
14312 | ||
d5b7b3ae | 14313 | void |
e32bac5b | 14314 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
14315 | { |
14316 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
14317 | } | |
14318 | ||
f676971a | 14319 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 14320 | void |
e32bac5b | 14321 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 14322 | { |
e6d29d15 | 14323 | gcc_unreachable (); |
d5b7b3ae RE |
14324 | } |
14325 | ||
c27ba912 DM |
14326 | /* Return the length of a function name prefix |
14327 | that starts with the character 'c'. */ | |
14328 | static int | |
e32bac5b | 14329 | arm_get_strip_length (int c) |
c27ba912 DM |
14330 | { |
14331 | switch (c) | |
14332 | { | |
14333 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 14334 | default: return 0; |
c27ba912 DM |
14335 | } |
14336 | } | |
14337 | ||
14338 | /* Return a pointer to a function's name with any | |
14339 | and all prefix encodings stripped from it. */ | |
14340 | const char * | |
e32bac5b | 14341 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
14342 | { |
14343 | int skip; | |
f676971a | 14344 | |
c27ba912 DM |
14345 | while ((skip = arm_get_strip_length (* name))) |
14346 | name += skip; | |
14347 | ||
14348 | return name; | |
14349 | } | |
14350 | ||
e1944073 KW |
14351 | /* If there is a '*' anywhere in the name's prefix, then |
14352 | emit the stripped name verbatim, otherwise prepend an | |
14353 | underscore if leading underscores are being used. */ | |
e1944073 | 14354 | void |
e32bac5b | 14355 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
14356 | { |
14357 | int skip; | |
14358 | int verbatim = 0; | |
14359 | ||
14360 | while ((skip = arm_get_strip_length (* name))) | |
14361 | { | |
14362 | verbatim |= (*name == '*'); | |
14363 | name += skip; | |
14364 | } | |
14365 | ||
14366 | if (verbatim) | |
14367 | fputs (name, stream); | |
14368 | else | |
14369 | asm_fprintf (stream, "%U%s", name); | |
14370 | } | |
14371 | ||
b12a00f1 RE |
14372 | static void |
14373 | arm_file_end (void) | |
14374 | { | |
14375 | int regno; | |
14376 | ||
14377 | if (! thumb_call_reg_needed) | |
14378 | return; | |
14379 | ||
d6b5193b | 14380 | switch_to_section (text_section); |
b12a00f1 RE |
14381 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
14382 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
14383 | ||
57ecec57 | 14384 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
14385 | { |
14386 | rtx label = thumb_call_via_label[regno]; | |
14387 | ||
14388 | if (label != 0) | |
14389 | { | |
14390 | targetm.asm_out.internal_label (asm_out_file, "L", | |
14391 | CODE_LABEL_NUMBER (label)); | |
14392 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
14393 | } | |
14394 | } | |
14395 | } | |
14396 | ||
e2500fed GK |
14397 | rtx aof_pic_label; |
14398 | ||
2b835d68 | 14399 | #ifdef AOF_ASSEMBLER |
6354dc9b | 14400 | /* Special functions only needed when producing AOF syntax assembler. */ |
2b835d68 | 14401 | |
32de079a RE |
14402 | struct pic_chain |
14403 | { | |
62b10bbc | 14404 | struct pic_chain * next; |
5f37d07c | 14405 | const char * symname; |
32de079a RE |
14406 | }; |
14407 | ||
62b10bbc | 14408 | static struct pic_chain * aof_pic_chain = NULL; |
32de079a RE |
14409 | |
14410 | rtx | |
e32bac5b | 14411 | aof_pic_entry (rtx x) |
32de079a | 14412 | { |
62b10bbc | 14413 | struct pic_chain ** chainp; |
32de079a RE |
14414 | int offset; |
14415 | ||
14416 | if (aof_pic_label == NULL_RTX) | |
14417 | { | |
43cffd11 | 14418 | aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); |
32de079a RE |
14419 | } |
14420 | ||
14421 | for (offset = 0, chainp = &aof_pic_chain; *chainp; | |
14422 | offset += 4, chainp = &(*chainp)->next) | |
14423 | if ((*chainp)->symname == XSTR (x, 0)) | |
14424 | return plus_constant (aof_pic_label, offset); | |
14425 | ||
14426 | *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); | |
14427 | (*chainp)->next = NULL; | |
14428 | (*chainp)->symname = XSTR (x, 0); | |
14429 | return plus_constant (aof_pic_label, offset); | |
14430 | } | |
14431 | ||
14432 | void | |
e32bac5b | 14433 | aof_dump_pic_table (FILE *f) |
32de079a | 14434 | { |
62b10bbc | 14435 | struct pic_chain * chain; |
32de079a RE |
14436 | |
14437 | if (aof_pic_chain == NULL) | |
14438 | return; | |
14439 | ||
dd18ae56 NC |
14440 | asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", |
14441 | PIC_OFFSET_TABLE_REGNUM, | |
14442 | PIC_OFFSET_TABLE_REGNUM); | |
32de079a | 14443 | fputs ("|x$adcons|\n", f); |
f676971a | 14444 | |
32de079a RE |
14445 | for (chain = aof_pic_chain; chain; chain = chain->next) |
14446 | { | |
14447 | fputs ("\tDCD\t", f); | |
14448 | assemble_name (f, chain->symname); | |
14449 | fputs ("\n", f); | |
14450 | } | |
14451 | } | |
14452 | ||
2b835d68 RE |
14453 | int arm_text_section_count = 1; |
14454 | ||
d6b5193b RS |
14455 | /* A get_unnamed_section callback for switching to the text section. */ |
14456 | ||
14457 | static void | |
14458 | aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
2b835d68 | 14459 | { |
d6b5193b | 14460 | fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY", |
2b835d68 RE |
14461 | arm_text_section_count++); |
14462 | if (flag_pic) | |
d6b5193b RS |
14463 | fprintf (asm_out_file, ", PIC, REENTRANT"); |
14464 | fprintf (asm_out_file, "\n"); | |
2b835d68 RE |
14465 | } |
14466 | ||
14467 | static int arm_data_section_count = 1; | |
14468 | ||
d6b5193b RS |
14469 | /* A get_unnamed_section callback for switching to the data section. */ |
14470 | ||
14471 | static void | |
14472 | aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
14473 | { | |
14474 | fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n", | |
14475 | arm_data_section_count++); | |
14476 | } | |
14477 | ||
14478 | /* Implement TARGET_ASM_INIT_SECTIONS. | |
14479 | ||
14480 | AOF Assembler syntax is a nightmare when it comes to areas, since once | |
14481 | we change from one area to another, we can't go back again. Instead, | |
14482 | we must create a new area with the same attributes and add the new output | |
14483 | to that. Unfortunately, there is nothing we can do here to guarantee that | |
14484 | two areas with the same attributes will be linked adjacently in the | |
14485 | resulting executable, so we have to be careful not to do pc-relative | |
14486 | addressing across such boundaries. */ | |
14487 | ||
14488 | static void | |
14489 | aof_asm_init_sections (void) | |
14490 | { | |
14491 | text_section = get_unnamed_section (SECTION_CODE, | |
14492 | aof_output_text_section_asm_op, NULL); | |
14493 | data_section = get_unnamed_section (SECTION_WRITE, | |
14494 | aof_output_data_section_asm_op, NULL); | |
14495 | readonly_data_section = text_section; | |
14496 | } | |
14497 | ||
14498 | void | |
14499 | zero_init_section (void) | |
2b835d68 | 14500 | { |
d6b5193b RS |
14501 | static int zero_init_count = 1; |
14502 | ||
14503 | fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++); | |
14504 | in_section = NULL; | |
2b835d68 RE |
14505 | } |
14506 | ||
14507 | /* The AOF assembler is religiously strict about declarations of | |
14508 | imported and exported symbols, so that it is impossible to declare | |
956d6950 | 14509 | a function as imported near the beginning of the file, and then to |
2b835d68 RE |
14510 | export it later on. It is, however, possible to delay the decision |
14511 | until all the functions in the file have been compiled. To get | |
14512 | around this, we maintain a list of the imports and exports, and | |
14513 | delete from it any that are subsequently defined. At the end of | |
14514 | compilation we spit the remainder of the list out before the END | |
14515 | directive. */ | |
14516 | ||
14517 | struct import | |
14518 | { | |
62b10bbc | 14519 | struct import * next; |
5f37d07c | 14520 | const char * name; |
2b835d68 RE |
14521 | }; |
14522 | ||
62b10bbc | 14523 | static struct import * imports_list = NULL; |
2b835d68 RE |
14524 | |
14525 | void | |
e32bac5b | 14526 | aof_add_import (const char *name) |
2b835d68 | 14527 | { |
62b10bbc | 14528 | struct import * new; |
2b835d68 RE |
14529 | |
14530 | for (new = imports_list; new; new = new->next) | |
14531 | if (new->name == name) | |
14532 | return; | |
14533 | ||
14534 | new = (struct import *) xmalloc (sizeof (struct import)); | |
14535 | new->next = imports_list; | |
14536 | imports_list = new; | |
14537 | new->name = name; | |
14538 | } | |
14539 | ||
14540 | void | |
e32bac5b | 14541 | aof_delete_import (const char *name) |
2b835d68 | 14542 | { |
62b10bbc | 14543 | struct import ** old; |
2b835d68 RE |
14544 | |
14545 | for (old = &imports_list; *old; old = & (*old)->next) | |
14546 | { | |
14547 | if ((*old)->name == name) | |
14548 | { | |
14549 | *old = (*old)->next; | |
14550 | return; | |
14551 | } | |
14552 | } | |
14553 | } | |
14554 | ||
14555 | int arm_main_function = 0; | |
14556 | ||
a5fe455b | 14557 | static void |
e32bac5b | 14558 | aof_dump_imports (FILE *f) |
2b835d68 RE |
14559 | { |
14560 | /* The AOF assembler needs this to cause the startup code to be extracted | |
14561 | from the library. Brining in __main causes the whole thing to work | |
14562 | automagically. */ | |
14563 | if (arm_main_function) | |
14564 | { | |
d6b5193b | 14565 | switch_to_section (text_section); |
2b835d68 RE |
14566 | fputs ("\tIMPORT __main\n", f); |
14567 | fputs ("\tDCD __main\n", f); | |
14568 | } | |
14569 | ||
14570 | /* Now dump the remaining imports. */ | |
14571 | while (imports_list) | |
14572 | { | |
14573 | fprintf (f, "\tIMPORT\t"); | |
14574 | assemble_name (f, imports_list->name); | |
14575 | fputc ('\n', f); | |
14576 | imports_list = imports_list->next; | |
14577 | } | |
14578 | } | |
5eb99654 KG |
14579 | |
14580 | static void | |
e32bac5b | 14581 | aof_globalize_label (FILE *stream, const char *name) |
5eb99654 KG |
14582 | { |
14583 | default_globalize_label (stream, name); | |
14584 | if (! strcmp (name, "main")) | |
14585 | arm_main_function = 1; | |
14586 | } | |
a5fe455b | 14587 | |
1bc7c5b6 | 14588 | static void |
f1777882 | 14589 | aof_file_start (void) |
1bc7c5b6 ZW |
14590 | { |
14591 | fputs ("__r0\tRN\t0\n", asm_out_file); | |
14592 | fputs ("__a1\tRN\t0\n", asm_out_file); | |
14593 | fputs ("__a2\tRN\t1\n", asm_out_file); | |
14594 | fputs ("__a3\tRN\t2\n", asm_out_file); | |
14595 | fputs ("__a4\tRN\t3\n", asm_out_file); | |
14596 | fputs ("__v1\tRN\t4\n", asm_out_file); | |
14597 | fputs ("__v2\tRN\t5\n", asm_out_file); | |
14598 | fputs ("__v3\tRN\t6\n", asm_out_file); | |
14599 | fputs ("__v4\tRN\t7\n", asm_out_file); | |
14600 | fputs ("__v5\tRN\t8\n", asm_out_file); | |
14601 | fputs ("__v6\tRN\t9\n", asm_out_file); | |
14602 | fputs ("__sl\tRN\t10\n", asm_out_file); | |
14603 | fputs ("__fp\tRN\t11\n", asm_out_file); | |
14604 | fputs ("__ip\tRN\t12\n", asm_out_file); | |
14605 | fputs ("__sp\tRN\t13\n", asm_out_file); | |
14606 | fputs ("__lr\tRN\t14\n", asm_out_file); | |
14607 | fputs ("__pc\tRN\t15\n", asm_out_file); | |
14608 | fputs ("__f0\tFN\t0\n", asm_out_file); | |
14609 | fputs ("__f1\tFN\t1\n", asm_out_file); | |
14610 | fputs ("__f2\tFN\t2\n", asm_out_file); | |
14611 | fputs ("__f3\tFN\t3\n", asm_out_file); | |
14612 | fputs ("__f4\tFN\t4\n", asm_out_file); | |
14613 | fputs ("__f5\tFN\t5\n", asm_out_file); | |
14614 | fputs ("__f6\tFN\t6\n", asm_out_file); | |
14615 | fputs ("__f7\tFN\t7\n", asm_out_file); | |
d6b5193b | 14616 | switch_to_section (text_section); |
1bc7c5b6 ZW |
14617 | } |
14618 | ||
a5fe455b | 14619 | static void |
e32bac5b | 14620 | aof_file_end (void) |
a5fe455b ZW |
14621 | { |
14622 | if (flag_pic) | |
14623 | aof_dump_pic_table (asm_out_file); | |
b12a00f1 | 14624 | arm_file_end (); |
a5fe455b ZW |
14625 | aof_dump_imports (asm_out_file); |
14626 | fputs ("\tEND\n", asm_out_file); | |
14627 | } | |
2b835d68 | 14628 | #endif /* AOF_ASSEMBLER */ |
7c262518 | 14629 | |
fb49053f RH |
14630 | #ifndef ARM_PE |
14631 | /* Symbols in the text segment can be accessed without indirecting via the | |
14632 | constant pool; it may take an extra binary operation, but this is still | |
14633 | faster than indirecting via memory. Don't do this when not optimizing, | |
14634 | since we won't be calculating al of the offsets necessary to do this | |
14635 | simplification. */ | |
14636 | ||
14637 | static void | |
e32bac5b | 14638 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f RH |
14639 | { |
14640 | /* This doesn't work with AOF syntax, since the string table may be in | |
14641 | a different AREA. */ | |
14642 | #ifndef AOF_ASSEMBLER | |
3521b33c | 14643 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 14644 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f RH |
14645 | #endif |
14646 | ||
14647 | /* If we are referencing a function that is weak then encode a long call | |
14648 | flag in the function name, otherwise if the function is static or | |
14649 | or known to be defined in this file then encode a short call flag. */ | |
6615c446 | 14650 | if (first && DECL_P (decl)) |
fb49053f RH |
14651 | { |
14652 | if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) | |
14653 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); | |
14654 | else if (! TREE_PUBLIC (decl)) | |
14655 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); | |
14656 | } | |
d3585b76 DJ |
14657 | |
14658 | default_encode_section_info (decl, rtl, first); | |
fb49053f RH |
14659 | } |
14660 | #endif /* !ARM_PE */ | |
483ab821 | 14661 | |
4977bab6 | 14662 | static void |
e32bac5b | 14663 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
14664 | { |
14665 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
14666 | && !strcmp (prefix, "L")) | |
14667 | { | |
14668 | arm_ccfsm_state = 0; | |
14669 | arm_target_insn = NULL; | |
14670 | } | |
14671 | default_internal_label (stream, prefix, labelno); | |
14672 | } | |
14673 | ||
c590b625 RH |
14674 | /* Output code to add DELTA to the first argument, and then jump |
14675 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 14676 | static void |
e32bac5b RE |
14677 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
14678 | HOST_WIDE_INT delta, | |
14679 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
14680 | tree function) | |
483ab821 | 14681 | { |
9b66ebb1 PB |
14682 | static int thunk_label = 0; |
14683 | char label[256]; | |
483ab821 MM |
14684 | int mi_delta = delta; |
14685 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
14686 | int shift = 0; | |
61f71b34 | 14687 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
14688 | ? 1 : 0); |
14689 | if (mi_delta < 0) | |
14690 | mi_delta = - mi_delta; | |
9b66ebb1 PB |
14691 | if (TARGET_THUMB) |
14692 | { | |
14693 | int labelno = thunk_label++; | |
14694 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
14695 | fputs ("\tldr\tr12, ", file); | |
14696 | assemble_name (file, label); | |
14697 | fputc ('\n', file); | |
14698 | } | |
483ab821 MM |
14699 | while (mi_delta != 0) |
14700 | { | |
14701 | if ((mi_delta & (3 << shift)) == 0) | |
14702 | shift += 2; | |
14703 | else | |
14704 | { | |
14705 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
14706 | mi_op, this_regno, this_regno, | |
14707 | mi_delta & (0xff << shift)); | |
14708 | mi_delta &= ~(0xff << shift); | |
14709 | shift += 8; | |
14710 | } | |
14711 | } | |
9b66ebb1 PB |
14712 | if (TARGET_THUMB) |
14713 | { | |
14714 | fprintf (file, "\tbx\tr12\n"); | |
14715 | ASM_OUTPUT_ALIGN (file, 2); | |
14716 | assemble_name (file, label); | |
14717 | fputs (":\n", file); | |
14718 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
14719 | } | |
14720 | else | |
14721 | { | |
14722 | fputs ("\tb\t", file); | |
14723 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
14724 | if (NEED_PLT_RELOC) | |
14725 | fputs ("(PLT)", file); | |
14726 | fputc ('\n', file); | |
14727 | } | |
483ab821 | 14728 | } |
5a9335ef NC |
14729 | |
14730 | int | |
6f5f2481 | 14731 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
14732 | { |
14733 | int i; | |
14734 | const char * pattern; | |
14735 | ||
e6d29d15 | 14736 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
14737 | |
14738 | switch (GET_MODE (x)) | |
14739 | { | |
14740 | case V2SImode: pattern = "%08x"; break; | |
14741 | case V4HImode: pattern = "%04x"; break; | |
14742 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 14743 | default: gcc_unreachable (); |
5a9335ef NC |
14744 | } |
14745 | ||
14746 | fprintf (file, "0x"); | |
14747 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
14748 | { | |
14749 | rtx element; | |
14750 | ||
14751 | element = CONST_VECTOR_ELT (x, i); | |
14752 | fprintf (file, pattern, INTVAL (element)); | |
14753 | } | |
14754 | ||
14755 | return 1; | |
14756 | } | |
14757 | ||
14758 | const char * | |
6f5f2481 | 14759 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
14760 | { |
14761 | rtx reg; | |
14762 | rtx offset; | |
14763 | rtx wcgr; | |
14764 | rtx sum; | |
f676971a | 14765 | |
5a9335ef NC |
14766 | if (GET_CODE (operands [1]) != MEM |
14767 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
14768 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
14769 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
14770 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
14771 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
14772 | |
14773 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
14774 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
14775 | wcgr = operands[0]; | |
14776 | operands[0] = reg; | |
14777 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
14778 | ||
14779 | operands[0] = wcgr; | |
14780 | operands[1] = reg; | |
14781 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
14782 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
14783 | ||
14784 | return ""; | |
14785 | } | |
f9ba5949 KH |
14786 | |
14787 | static rtx | |
14788 | arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
14789 | int incoming ATTRIBUTE_UNUSED) | |
14790 | { | |
14791 | #if 0 | |
14792 | /* FIXME: The ARM backend has special code to handle structure | |
14793 | returns, and will reserve its own hidden first argument. So | |
14794 | if this macro is enabled a *second* hidden argument will be | |
14795 | reserved, which will break binary compatibility with old | |
14796 | toolchains and also thunk handling. One day this should be | |
14797 | fixed. */ | |
14798 | return 0; | |
14799 | #else | |
14800 | /* Register in which address to store a structure value | |
14801 | is passed to a function. */ | |
14802 | return gen_rtx_REG (Pmode, ARG_REGISTER (1)); | |
14803 | #endif | |
14804 | } | |
1cc9f5f5 KH |
14805 | |
14806 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. | |
14807 | ||
14808 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
14809 | named arg and all anonymous args onto the stack. | |
14810 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
14811 | that way. */ | |
14812 | ||
14813 | static void | |
14814 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
14815 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
14816 | tree type ATTRIBUTE_UNUSED, | |
14817 | int *pretend_size, | |
14818 | int second_time ATTRIBUTE_UNUSED) | |
14819 | { | |
14820 | cfun->machine->uses_anonymous_args = 1; | |
14821 | if (cum->nregs < NUM_ARG_REGS) | |
14822 | *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD; | |
14823 | } | |
9b66ebb1 | 14824 | |
59b9a953 | 14825 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
14826 | PRODUCER's value to calculate the address. */ |
14827 | ||
14828 | int | |
14829 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
14830 | { | |
14831 | rtx value = PATTERN (producer); | |
14832 | rtx addr = PATTERN (consumer); | |
14833 | ||
14834 | if (GET_CODE (value) == COND_EXEC) | |
14835 | value = COND_EXEC_CODE (value); | |
14836 | if (GET_CODE (value) == PARALLEL) | |
14837 | value = XVECEXP (value, 0, 0); | |
14838 | value = XEXP (value, 0); | |
14839 | if (GET_CODE (addr) == COND_EXEC) | |
14840 | addr = COND_EXEC_CODE (addr); | |
14841 | if (GET_CODE (addr) == PARALLEL) | |
14842 | addr = XVECEXP (addr, 0, 0); | |
14843 | addr = XEXP (addr, 0); | |
f676971a | 14844 | |
9b66ebb1 PB |
14845 | return !reg_overlap_mentioned_p (value, addr); |
14846 | } | |
14847 | ||
59b9a953 | 14848 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
14849 | have an early register shift value or amount dependency on the |
14850 | result of PRODUCER. */ | |
14851 | ||
14852 | int | |
14853 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
14854 | { | |
14855 | rtx value = PATTERN (producer); | |
14856 | rtx op = PATTERN (consumer); | |
14857 | rtx early_op; | |
14858 | ||
14859 | if (GET_CODE (value) == COND_EXEC) | |
14860 | value = COND_EXEC_CODE (value); | |
14861 | if (GET_CODE (value) == PARALLEL) | |
14862 | value = XVECEXP (value, 0, 0); | |
14863 | value = XEXP (value, 0); | |
14864 | if (GET_CODE (op) == COND_EXEC) | |
14865 | op = COND_EXEC_CODE (op); | |
14866 | if (GET_CODE (op) == PARALLEL) | |
14867 | op = XVECEXP (op, 0, 0); | |
14868 | op = XEXP (op, 1); | |
f676971a | 14869 | |
9b66ebb1 PB |
14870 | early_op = XEXP (op, 0); |
14871 | /* This is either an actual independent shift, or a shift applied to | |
14872 | the first operand of another operation. We want the whole shift | |
14873 | operation. */ | |
14874 | if (GET_CODE (early_op) == REG) | |
14875 | early_op = op; | |
14876 | ||
14877 | return !reg_overlap_mentioned_p (value, early_op); | |
14878 | } | |
14879 | ||
59b9a953 | 14880 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
14881 | have an early register shift value dependency on the result of |
14882 | PRODUCER. */ | |
14883 | ||
14884 | int | |
14885 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
14886 | { | |
14887 | rtx value = PATTERN (producer); | |
14888 | rtx op = PATTERN (consumer); | |
14889 | rtx early_op; | |
14890 | ||
14891 | if (GET_CODE (value) == COND_EXEC) | |
14892 | value = COND_EXEC_CODE (value); | |
14893 | if (GET_CODE (value) == PARALLEL) | |
14894 | value = XVECEXP (value, 0, 0); | |
14895 | value = XEXP (value, 0); | |
14896 | if (GET_CODE (op) == COND_EXEC) | |
14897 | op = COND_EXEC_CODE (op); | |
14898 | if (GET_CODE (op) == PARALLEL) | |
14899 | op = XVECEXP (op, 0, 0); | |
14900 | op = XEXP (op, 1); | |
f676971a | 14901 | |
9b66ebb1 PB |
14902 | early_op = XEXP (op, 0); |
14903 | ||
14904 | /* This is either an actual independent shift, or a shift applied to | |
14905 | the first operand of another operation. We want the value being | |
14906 | shifted, in either case. */ | |
14907 | if (GET_CODE (early_op) != REG) | |
14908 | early_op = XEXP (early_op, 0); | |
f676971a | 14909 | |
9b66ebb1 PB |
14910 | return !reg_overlap_mentioned_p (value, early_op); |
14911 | } | |
14912 | ||
59b9a953 | 14913 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
14914 | have an early register mult dependency on the result of |
14915 | PRODUCER. */ | |
14916 | ||
14917 | int | |
14918 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
14919 | { | |
14920 | rtx value = PATTERN (producer); | |
14921 | rtx op = PATTERN (consumer); | |
14922 | ||
14923 | if (GET_CODE (value) == COND_EXEC) | |
14924 | value = COND_EXEC_CODE (value); | |
14925 | if (GET_CODE (value) == PARALLEL) | |
14926 | value = XVECEXP (value, 0, 0); | |
14927 | value = XEXP (value, 0); | |
14928 | if (GET_CODE (op) == COND_EXEC) | |
14929 | op = COND_EXEC_CODE (op); | |
14930 | if (GET_CODE (op) == PARALLEL) | |
14931 | op = XVECEXP (op, 0, 0); | |
14932 | op = XEXP (op, 1); | |
f676971a | 14933 | |
9b66ebb1 PB |
14934 | return (GET_CODE (op) == PLUS |
14935 | && !reg_overlap_mentioned_p (value, XEXP (op, 0))); | |
14936 | } | |
14937 | ||
70301b45 PB |
14938 | |
14939 | /* We can't rely on the caller doing the proper promotion when | |
14940 | using APCS or ATPCS. */ | |
14941 | ||
14942 | static bool | |
14943 | arm_promote_prototypes (tree t ATTRIBUTE_UNUSED) | |
14944 | { | |
b6685939 | 14945 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
14946 | } |
14947 | ||
6b045785 PB |
14948 | |
14949 | /* AAPCS based ABIs use short enums by default. */ | |
14950 | ||
14951 | static bool | |
14952 | arm_default_short_enums (void) | |
14953 | { | |
077fc835 | 14954 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 14955 | } |
13c1cd82 PB |
14956 | |
14957 | ||
14958 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
14959 | ||
14960 | static bool | |
14961 | arm_align_anon_bitfield (void) | |
14962 | { | |
14963 | return TARGET_AAPCS_BASED; | |
14964 | } | |
4185ae53 PB |
14965 | |
14966 | ||
14967 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
14968 | ||
14969 | static tree | |
14970 | arm_cxx_guard_type (void) | |
14971 | { | |
14972 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
14973 | } | |
14974 | ||
14975 | ||
0fa2e4df | 14976 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
14977 | |
14978 | static bool | |
14979 | arm_cxx_guard_mask_bit (void) | |
14980 | { | |
14981 | return TARGET_AAPCS_BASED; | |
14982 | } | |
46e995e0 PB |
14983 | |
14984 | ||
14985 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
14986 | ||
14987 | static tree | |
14988 | arm_get_cookie_size (tree type) | |
14989 | { | |
14990 | tree size; | |
14991 | ||
14992 | if (!TARGET_AAPCS_BASED) | |
14993 | return default_cxx_get_cookie_size (type); | |
14994 | ||
7d60be94 | 14995 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
14996 | return size; |
14997 | } | |
14998 | ||
14999 | ||
15000 | /* The EABI says that array cookies should also contain the element size. */ | |
15001 | ||
15002 | static bool | |
15003 | arm_cookie_has_size (void) | |
15004 | { | |
15005 | return TARGET_AAPCS_BASED; | |
15006 | } | |
44d10c10 PB |
15007 | |
15008 | ||
15009 | /* The EABI says constructors and destructors should return a pointer to | |
15010 | the object constructed/destroyed. */ | |
15011 | ||
15012 | static bool | |
15013 | arm_cxx_cdtor_returns_this (void) | |
15014 | { | |
15015 | return TARGET_AAPCS_BASED; | |
15016 | } | |
c9ca9b88 | 15017 | |
505970fc MM |
15018 | /* The EABI says that an inline function may never be the key |
15019 | method. */ | |
15020 | ||
15021 | static bool | |
15022 | arm_cxx_key_method_may_be_inline (void) | |
15023 | { | |
15024 | return !TARGET_AAPCS_BASED; | |
15025 | } | |
15026 | ||
1e731102 MM |
15027 | static void |
15028 | arm_cxx_determine_class_data_visibility (tree decl) | |
15029 | { | |
15030 | if (!TARGET_AAPCS_BASED) | |
15031 | return; | |
505970fc | 15032 | |
1e731102 MM |
15033 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
15034 | is exported. However, on systems without dynamic vague linkage, | |
15035 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
15036 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
15037 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
15038 | else | |
15039 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
15040 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
15041 | } | |
e0b92319 | 15042 | |
505970fc | 15043 | static bool |
1e731102 | 15044 | arm_cxx_class_data_always_comdat (void) |
505970fc | 15045 | { |
1e731102 MM |
15046 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
15047 | vague linkage if the class has no key function. */ | |
15048 | return !TARGET_AAPCS_BASED; | |
505970fc | 15049 | } |
c9ca9b88 | 15050 | |
9f62c3e3 PB |
15051 | |
15052 | /* The EABI says __aeabi_atexit should be used to register static | |
15053 | destructors. */ | |
15054 | ||
15055 | static bool | |
15056 | arm_cxx_use_aeabi_atexit (void) | |
15057 | { | |
15058 | return TARGET_AAPCS_BASED; | |
15059 | } | |
15060 | ||
15061 | ||
c9ca9b88 PB |
15062 | void |
15063 | arm_set_return_address (rtx source, rtx scratch) | |
15064 | { | |
15065 | arm_stack_offsets *offsets; | |
15066 | HOST_WIDE_INT delta; | |
15067 | rtx addr; | |
15068 | unsigned long saved_regs; | |
15069 | ||
15070 | saved_regs = arm_compute_save_reg_mask (); | |
15071 | ||
15072 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
15073 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
15074 | else | |
15075 | { | |
15076 | if (frame_pointer_needed) | |
15077 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
15078 | else | |
15079 | { | |
15080 | /* LR will be the first saved register. */ | |
15081 | offsets = arm_get_frame_offsets (); | |
15082 | delta = offsets->outgoing_args - (offsets->frame + 4); | |
15083 | ||
f676971a | 15084 | |
c9ca9b88 PB |
15085 | if (delta >= 4096) |
15086 | { | |
15087 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
15088 | GEN_INT (delta & ~4095))); | |
15089 | addr = scratch; | |
15090 | delta &= 4095; | |
15091 | } | |
15092 | else | |
15093 | addr = stack_pointer_rtx; | |
15094 | ||
15095 | addr = plus_constant (addr, delta); | |
15096 | } | |
31fa16b6 | 15097 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
15098 | } |
15099 | } | |
15100 | ||
15101 | ||
15102 | void | |
15103 | thumb_set_return_address (rtx source, rtx scratch) | |
15104 | { | |
15105 | arm_stack_offsets *offsets; | |
c9ca9b88 PB |
15106 | HOST_WIDE_INT delta; |
15107 | int reg; | |
15108 | rtx addr; | |
57934c39 | 15109 | unsigned long mask; |
c9ca9b88 PB |
15110 | |
15111 | emit_insn (gen_rtx_USE (VOIDmode, source)); | |
c9ca9b88 | 15112 | |
57934c39 PB |
15113 | mask = thumb_compute_save_reg_mask (); |
15114 | if (mask & (1 << LR_REGNUM)) | |
c9ca9b88 PB |
15115 | { |
15116 | offsets = arm_get_frame_offsets (); | |
15117 | ||
15118 | /* Find the saved regs. */ | |
15119 | if (frame_pointer_needed) | |
15120 | { | |
15121 | delta = offsets->soft_frame - offsets->saved_args; | |
15122 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
15123 | } | |
15124 | else | |
15125 | { | |
15126 | delta = offsets->outgoing_args - offsets->saved_args; | |
15127 | reg = SP_REGNUM; | |
15128 | } | |
15129 | /* Allow for the stack frame. */ | |
15130 | if (TARGET_BACKTRACE) | |
15131 | delta -= 16; | |
15132 | /* The link register is always the first saved register. */ | |
15133 | delta -= 4; | |
f676971a | 15134 | |
c9ca9b88 PB |
15135 | /* Construct the address. */ |
15136 | addr = gen_rtx_REG (SImode, reg); | |
15137 | if ((reg != SP_REGNUM && delta >= 128) | |
15138 | || delta >= 1024) | |
15139 | { | |
15140 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
15141 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
15142 | addr = scratch; | |
15143 | } | |
15144 | else | |
15145 | addr = plus_constant (addr, delta); | |
15146 | ||
31fa16b6 | 15147 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
15148 | } |
15149 | else | |
15150 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
15151 | } | |
15152 | ||
f676971a EC |
15153 | /* Implements target hook vector_mode_supported_p. */ |
15154 | bool | |
15155 | arm_vector_mode_supported_p (enum machine_mode mode) | |
15156 | { | |
15157 | if ((mode == V2SImode) | |
15158 | || (mode == V4HImode) | |
15159 | || (mode == V8QImode)) | |
15160 | return true; | |
15161 | ||
15162 | return false; | |
15163 | } | |
273a2526 RS |
15164 | |
15165 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal | |
15166 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
15167 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
15168 | guarantee no particular behavior for out-of-range counts. */ | |
15169 | ||
15170 | static unsigned HOST_WIDE_INT | |
15171 | arm_shift_truncation_mask (enum machine_mode mode) | |
15172 | { | |
15173 | return mode == SImode ? 255 : 0; | |
15174 | } | |
2fa330b2 PB |
15175 | |
15176 | ||
15177 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
15178 | ||
15179 | unsigned int | |
15180 | arm_dbx_register_number (unsigned int regno) | |
15181 | { | |
15182 | if (regno < 16) | |
15183 | return regno; | |
15184 | ||
15185 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
15186 | compatibility. The EABI defines them as registers 96-103. */ | |
15187 | if (IS_FPA_REGNUM (regno)) | |
15188 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
15189 | ||
15190 | if (IS_VFP_REGNUM (regno)) | |
15191 | return 64 + regno - FIRST_VFP_REGNUM; | |
15192 | ||
15193 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
15194 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
15195 | ||
15196 | if (IS_IWMMXT_REGNUM (regno)) | |
15197 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
15198 | ||
e6d29d15 | 15199 | gcc_unreachable (); |
2fa330b2 PB |
15200 | } |
15201 | ||
617a1b71 PB |
15202 | |
15203 | #ifdef TARGET_UNWIND_INFO | |
15204 | /* Emit unwind directives for a store-multiple instruction. This should | |
15205 | only ever be generated by the function prologue code, so we expect it | |
15206 | to have a particular form. */ | |
15207 | ||
15208 | static void | |
15209 | arm_unwind_emit_stm (FILE * asm_out_file, rtx p) | |
15210 | { | |
15211 | int i; | |
15212 | HOST_WIDE_INT offset; | |
15213 | HOST_WIDE_INT nregs; | |
15214 | int reg_size; | |
15215 | unsigned reg; | |
15216 | unsigned lastreg; | |
15217 | rtx e; | |
15218 | ||
15219 | /* First insn will adjust the stack pointer. */ | |
15220 | e = XVECEXP (p, 0, 0); | |
15221 | if (GET_CODE (e) != SET | |
15222 | || GET_CODE (XEXP (e, 0)) != REG | |
15223 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
15224 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
15225 | abort (); | |
15226 | ||
15227 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
15228 | nregs = XVECLEN (p, 0) - 1; | |
15229 | ||
15230 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
15231 | if (reg < 16) | |
15232 | { | |
15233 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 15234 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
15235 | if (nregs * 4 == offset - 4) |
15236 | { | |
15237 | fprintf (asm_out_file, "\t.pad #4\n"); | |
15238 | offset -= 4; | |
15239 | } | |
15240 | reg_size = 4; | |
15241 | } | |
15242 | else if (IS_VFP_REGNUM (reg)) | |
15243 | { | |
15244 | /* FPA register saves use an additional word. */ | |
15245 | offset -= 4; | |
15246 | reg_size = 8; | |
15247 | } | |
15248 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
15249 | { | |
15250 | /* FPA registers are done differently. */ | |
ea40ba9c | 15251 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
15252 | return; |
15253 | } | |
15254 | else | |
15255 | /* Unknown register type. */ | |
15256 | abort (); | |
15257 | ||
15258 | /* If the stack increment doesn't match the size of the saved registers, | |
15259 | something has gone horribly wrong. */ | |
15260 | if (offset != nregs * reg_size) | |
15261 | abort (); | |
15262 | ||
15263 | fprintf (asm_out_file, "\t.save {"); | |
15264 | ||
15265 | offset = 0; | |
15266 | lastreg = 0; | |
15267 | /* The remaining insns will describe the stores. */ | |
15268 | for (i = 1; i <= nregs; i++) | |
15269 | { | |
15270 | /* Expect (set (mem <addr>) (reg)). | |
15271 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
15272 | e = XVECEXP (p, 0, i); | |
15273 | if (GET_CODE (e) != SET | |
15274 | || GET_CODE (XEXP (e, 0)) != MEM | |
15275 | || GET_CODE (XEXP (e, 1)) != REG) | |
15276 | abort (); | |
e0b92319 | 15277 | |
617a1b71 PB |
15278 | reg = REGNO (XEXP (e, 1)); |
15279 | if (reg < lastreg) | |
15280 | abort (); | |
e0b92319 | 15281 | |
617a1b71 PB |
15282 | if (i != 1) |
15283 | fprintf (asm_out_file, ", "); | |
15284 | /* We can't use %r for vfp because we need to use the | |
15285 | double precision register names. */ | |
15286 | if (IS_VFP_REGNUM (reg)) | |
15287 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
15288 | else | |
15289 | asm_fprintf (asm_out_file, "%r", reg); | |
15290 | ||
15291 | #ifdef ENABLE_CHECKING | |
15292 | /* Check that the addresses are consecutive. */ | |
15293 | e = XEXP (XEXP (e, 0), 0); | |
15294 | if (GET_CODE (e) == PLUS) | |
15295 | { | |
15296 | offset += reg_size; | |
15297 | if (GET_CODE (XEXP (e, 0)) != REG | |
15298 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
15299 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
15300 | || offset != INTVAL (XEXP (e, 1))) | |
15301 | abort (); | |
15302 | } | |
15303 | else if (i != 1 | |
15304 | || GET_CODE (e) != REG | |
15305 | || REGNO (e) != SP_REGNUM) | |
15306 | abort (); | |
15307 | #endif | |
15308 | } | |
15309 | fprintf (asm_out_file, "}\n"); | |
15310 | } | |
15311 | ||
15312 | /* Emit unwind directives for a SET. */ | |
15313 | ||
15314 | static void | |
15315 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
15316 | { | |
15317 | rtx e0; | |
15318 | rtx e1; | |
15319 | ||
15320 | e0 = XEXP (p, 0); | |
15321 | e1 = XEXP (p, 1); | |
15322 | switch (GET_CODE (e0)) | |
15323 | { | |
15324 | case MEM: | |
15325 | /* Pushing a single register. */ | |
15326 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
15327 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
15328 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
15329 | abort (); | |
15330 | ||
15331 | asm_fprintf (asm_out_file, "\t.save "); | |
15332 | if (IS_VFP_REGNUM (REGNO (e1))) | |
15333 | asm_fprintf(asm_out_file, "{d%d}\n", | |
15334 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
15335 | else | |
15336 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
15337 | break; | |
15338 | ||
15339 | case REG: | |
15340 | if (REGNO (e0) == SP_REGNUM) | |
15341 | { | |
15342 | /* A stack increment. */ | |
15343 | if (GET_CODE (e1) != PLUS | |
15344 | || GET_CODE (XEXP (e1, 0)) != REG | |
15345 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
15346 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
15347 | abort (); | |
15348 | ||
ea40ba9c | 15349 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
15350 | -INTVAL (XEXP (e1, 1))); |
15351 | } | |
15352 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
15353 | { | |
15354 | HOST_WIDE_INT offset; | |
15355 | unsigned reg; | |
e0b92319 | 15356 | |
617a1b71 PB |
15357 | if (GET_CODE (e1) == PLUS) |
15358 | { | |
15359 | if (GET_CODE (XEXP (e1, 0)) != REG | |
15360 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
15361 | abort (); | |
15362 | reg = REGNO (XEXP (e1, 0)); | |
15363 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 15364 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 PB |
15365 | HARD_FRAME_POINTER_REGNUM, reg, |
15366 | INTVAL (XEXP (e1, 1))); | |
15367 | } | |
15368 | else if (GET_CODE (e1) == REG) | |
15369 | { | |
15370 | reg = REGNO (e1); | |
15371 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
15372 | HARD_FRAME_POINTER_REGNUM, reg); | |
15373 | } | |
15374 | else | |
15375 | abort (); | |
15376 | } | |
15377 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
15378 | { | |
15379 | /* Move from sp to reg. */ | |
15380 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
15381 | } | |
15382 | else | |
15383 | abort (); | |
15384 | break; | |
15385 | ||
15386 | default: | |
15387 | abort (); | |
15388 | } | |
15389 | } | |
15390 | ||
15391 | ||
15392 | /* Emit unwind directives for the given insn. */ | |
15393 | ||
15394 | static void | |
15395 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
15396 | { | |
15397 | rtx pat; | |
15398 | ||
15399 | if (!ARM_EABI_UNWIND_TABLES) | |
15400 | return; | |
15401 | ||
15402 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) | |
15403 | return; | |
15404 | ||
15405 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
15406 | if (pat) | |
15407 | pat = XEXP (pat, 0); | |
15408 | else | |
15409 | pat = PATTERN (insn); | |
15410 | ||
15411 | switch (GET_CODE (pat)) | |
15412 | { | |
15413 | case SET: | |
15414 | arm_unwind_emit_set (asm_out_file, pat); | |
15415 | break; | |
15416 | ||
15417 | case SEQUENCE: | |
15418 | /* Store multiple. */ | |
15419 | arm_unwind_emit_stm (asm_out_file, pat); | |
15420 | break; | |
15421 | ||
15422 | default: | |
15423 | abort(); | |
15424 | } | |
15425 | } | |
15426 | ||
15427 | ||
15428 | /* Output a reference from a function exception table to the type_info | |
15429 | object X. The EABI specifies that the symbol should be relocated by | |
15430 | an R_ARM_TARGET2 relocation. */ | |
15431 | ||
15432 | static bool | |
15433 | arm_output_ttype (rtx x) | |
15434 | { | |
15435 | fputs ("\t.word\t", asm_out_file); | |
15436 | output_addr_const (asm_out_file, x); | |
15437 | /* Use special relocations for symbol references. */ | |
15438 | if (GET_CODE (x) != CONST_INT) | |
15439 | fputs ("(TARGET2)", asm_out_file); | |
15440 | fputc ('\n', asm_out_file); | |
15441 | ||
15442 | return TRUE; | |
15443 | } | |
15444 | #endif /* TARGET_UNWIND_INFO */ | |
15445 | ||
15446 | ||
15447 | /* Output unwind directives for the start/end of a function. */ | |
15448 | ||
15449 | void | |
15450 | arm_output_fn_unwind (FILE * f, bool prologue) | |
15451 | { | |
15452 | if (!ARM_EABI_UNWIND_TABLES) | |
15453 | return; | |
15454 | ||
15455 | if (prologue) | |
15456 | fputs ("\t.fnstart\n", f); | |
15457 | else | |
15458 | fputs ("\t.fnend\n", f); | |
15459 | } | |
d3585b76 DJ |
15460 | |
15461 | static bool | |
15462 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
15463 | { | |
15464 | enum tls_reloc reloc; | |
15465 | rtx val; | |
15466 | ||
15467 | val = XVECEXP (x, 0, 0); | |
15468 | reloc = INTVAL (XVECEXP (x, 0, 1)); | |
15469 | ||
15470 | output_addr_const (fp, val); | |
15471 | ||
15472 | switch (reloc) | |
15473 | { | |
15474 | case TLS_GD32: | |
15475 | fputs ("(tlsgd)", fp); | |
15476 | break; | |
15477 | case TLS_LDM32: | |
15478 | fputs ("(tlsldm)", fp); | |
15479 | break; | |
15480 | case TLS_LDO32: | |
15481 | fputs ("(tlsldo)", fp); | |
15482 | break; | |
15483 | case TLS_IE32: | |
15484 | fputs ("(gottpoff)", fp); | |
15485 | break; | |
15486 | case TLS_LE32: | |
15487 | fputs ("(tpoff)", fp); | |
15488 | break; | |
15489 | default: | |
15490 | gcc_unreachable (); | |
15491 | } | |
15492 | ||
15493 | switch (reloc) | |
15494 | { | |
15495 | case TLS_GD32: | |
15496 | case TLS_LDM32: | |
15497 | case TLS_IE32: | |
15498 | fputs (" + (. - ", fp); | |
15499 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
15500 | fputs (" - ", fp); | |
15501 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
15502 | fputc (')', fp); | |
15503 | break; | |
15504 | default: | |
15505 | break; | |
15506 | } | |
15507 | ||
15508 | return TRUE; | |
15509 | } | |
15510 | ||
15511 | bool | |
15512 | arm_output_addr_const_extra (FILE *fp, rtx x) | |
15513 | { | |
15514 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
15515 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
15516 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
15517 | { | |
15518 | char label[256]; | |
15519 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
15520 | ||
15521 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
15522 | assemble_name_raw (fp, label); | |
15523 | ||
15524 | return TRUE; | |
15525 | } | |
d3585b76 DJ |
15526 | else if (GET_CODE (x) == CONST_VECTOR) |
15527 | return arm_emit_vector_const (fp, x); | |
15528 | ||
15529 | return FALSE; | |
15530 | } | |
15531 | ||
15532 | #include "gt-arm.h" |