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b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e RE |
2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
3 | 2002, 2003, 2004 Free Software Foundation, Inc. | |
cce8749e | 4 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 5 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 6 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 7 | |
4f448245 | 8 | This file is part of GCC. |
cce8749e | 9 | |
4f448245 NC |
10 | GCC is free software; you can redistribute it and/or modify it |
11 | under the terms of the GNU General Public License as published | |
12 | by the Free Software Foundation; either version 2, or (at your | |
13 | option) any later version. | |
cce8749e | 14 | |
4f448245 NC |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT |
16 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
17 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
18 | License for more details. | |
cce8749e | 19 | |
4f448245 NC |
20 | You should have received a copy of the GNU General Public License |
21 | along with GCC; see the file COPYING. If not, write to | |
22 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
23 | Boston, MA 02111-1307, USA. */ | |
ff9940b0 | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
980e61bb | 53 | #include "debug.h" |
cce8749e | 54 | |
d5b7b3ae RE |
55 | /* Forward definitions of types. */ |
56 | typedef struct minipool_node Mnode; | |
57 | typedef struct minipool_fixup Mfix; | |
58 | ||
1d6e90ac NC |
59 | const struct attribute_spec arm_attribute_table[]; |
60 | ||
d5b7b3ae | 61 | /* Forward function declarations. */ |
5848830f | 62 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 63 | static void arm_add_gc_roots (void); |
a406f566 MM |
64 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
65 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
66 | static unsigned bit_count (unsigned long); |
67 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 68 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
e32bac5b RE |
69 | static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); |
70 | inline static int thumb_index_register_rtx_p (rtx, int); | |
5848830f | 71 | static int thumb_far_jump_used_p (void); |
e32bac5b | 72 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b RE |
73 | static rtx emit_multi_reg_push (int); |
74 | static rtx emit_sfm (int, int); | |
301d03af | 75 | #ifndef AOF_ASSEMBLER |
e32bac5b | 76 | static bool arm_assemble_integer (rtx, unsigned int, int); |
301d03af | 77 | #endif |
e32bac5b RE |
78 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
79 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
80 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
81 | static rtx is_jump_table (rtx); | |
82 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
83 | int, HOST_WIDE_INT); | |
84 | static void print_multi_reg (FILE *, const char *, int, int); | |
85 | static const char *shift_op (rtx, HOST_WIDE_INT *); | |
86 | static struct machine_function *arm_init_machine_status (void); | |
87 | static int number_of_first_bit_set (int); | |
88 | static void replace_symbols_in_block (tree, rtx, rtx); | |
89 | static void thumb_exit (FILE *, int, rtx); | |
980e61bb | 90 | static void thumb_pushpop (FILE *, int, int, int *, int); |
e32bac5b RE |
91 | static rtx is_jump_table (rtx); |
92 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
93 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
94 | static Mnode *add_minipool_forward_ref (Mfix *); | |
95 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
96 | static Mnode *add_minipool_backward_ref (Mfix *); | |
97 | static void assign_minipool_offsets (Mfix *); | |
98 | static void arm_print_value (FILE *, rtx); | |
99 | static void dump_minipool (rtx); | |
100 | static int arm_barrier_cost (rtx); | |
101 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
102 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
103 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
104 | rtx); | |
105 | static void arm_reorg (void); | |
106 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
107 | static int current_file_function_operand (rtx); | |
108 | static unsigned long arm_compute_save_reg0_reg12_mask (void); | |
109 | static unsigned long arm_compute_save_reg_mask (void); | |
110 | static unsigned long arm_isr_value (tree); | |
111 | static unsigned long arm_compute_func_type (void); | |
112 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
113 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
114 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
115 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
116 | static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); | |
117 | static int arm_comp_type_attributes (tree, tree); | |
118 | static void arm_set_default_type_attributes (tree); | |
119 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
120 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
121 | static int arm_get_strip_length (int); | |
122 | static bool arm_function_ok_for_sibcall (tree, tree); | |
123 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
124 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
125 | tree); | |
126 | static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); | |
9b66ebb1 PB |
127 | static bool arm_slowmul_rtx_costs (rtx, int, int, int *); |
128 | static bool arm_fastmul_rtx_costs (rtx, int, int, int *); | |
129 | static bool arm_xscale_rtx_costs (rtx, int, int, int *); | |
130 | static bool arm_9e_rtx_costs (rtx, int, int, int *); | |
e32bac5b RE |
131 | static int arm_address_cost (rtx); |
132 | static bool arm_memory_load_p (rtx); | |
133 | static bool arm_cirrus_insn_p (rtx); | |
134 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
135 | static void arm_init_builtins (void); |
136 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
137 | static void arm_init_iwmmxt_builtins (void); | |
138 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
139 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
140 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
141 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 142 | static void emit_constant_insn (rtx cond, rtx pattern); |
5a9335ef | 143 | |
ebe413e5 | 144 | #ifdef OBJECT_FORMAT_ELF |
e32bac5b | 145 | static void arm_elf_asm_named_section (const char *, unsigned int); |
ebe413e5 | 146 | #endif |
fb49053f | 147 | #ifndef ARM_PE |
e32bac5b | 148 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 149 | #endif |
5eb99654 | 150 | #ifdef AOF_ASSEMBLER |
e32bac5b RE |
151 | static void aof_globalize_label (FILE *, const char *); |
152 | static void aof_dump_imports (FILE *); | |
153 | static void aof_dump_pic_table (FILE *); | |
1bc7c5b6 | 154 | static void aof_file_start (void); |
e32bac5b | 155 | static void aof_file_end (void); |
5eb99654 | 156 | #endif |
f9ba5949 | 157 | static rtx arm_struct_value_rtx (tree, int); |
1cc9f5f5 KH |
158 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
159 | tree, int *, int); | |
70301b45 | 160 | static bool arm_promote_prototypes (tree); |
6b045785 | 161 | static bool arm_default_short_enums (void); |
13c1cd82 | 162 | static bool arm_align_anon_bitfield (void); |
c237e94a | 163 | |
4185ae53 PB |
164 | static tree arm_cxx_guard_type (void); |
165 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
166 | static tree arm_get_cookie_size (tree); |
167 | static bool arm_cookie_has_size (void); | |
4185ae53 | 168 | |
672a6f42 NB |
169 | \f |
170 | /* Initialize the GCC target structure. */ | |
171 | #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES | |
1d6e90ac | 172 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
173 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
174 | #endif | |
f3bb6135 | 175 | |
1d6e90ac | 176 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 177 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 178 | |
301d03af | 179 | #ifdef AOF_ASSEMBLER |
1d6e90ac | 180 | #undef TARGET_ASM_BYTE_OP |
301d03af | 181 | #define TARGET_ASM_BYTE_OP "\tDCB\t" |
1d6e90ac | 182 | #undef TARGET_ASM_ALIGNED_HI_OP |
301d03af | 183 | #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" |
1d6e90ac | 184 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 185 | #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" |
5eb99654 KG |
186 | #undef TARGET_ASM_GLOBALIZE_LABEL |
187 | #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label | |
1bc7c5b6 ZW |
188 | #undef TARGET_ASM_FILE_START |
189 | #define TARGET_ASM_FILE_START aof_file_start | |
a5fe455b ZW |
190 | #undef TARGET_ASM_FILE_END |
191 | #define TARGET_ASM_FILE_END aof_file_end | |
301d03af | 192 | #else |
1d6e90ac | 193 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 194 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 195 | #undef TARGET_ASM_INTEGER |
301d03af RS |
196 | #define TARGET_ASM_INTEGER arm_assemble_integer |
197 | #endif | |
198 | ||
1d6e90ac | 199 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
200 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
201 | ||
1d6e90ac | 202 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
203 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
204 | ||
1d6e90ac | 205 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
206 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
207 | ||
1d6e90ac | 208 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
209 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
210 | ||
1d6e90ac | 211 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
212 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
213 | ||
103fc15d | 214 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
ca4f3d13 | 215 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1 |
103fc15d | 216 | |
fb49053f RH |
217 | #undef TARGET_ENCODE_SECTION_INFO |
218 | #ifdef ARM_PE | |
219 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
220 | #else | |
221 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
222 | #endif | |
223 | ||
5a9335ef | 224 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
225 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
226 | ||
5a9335ef | 227 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
228 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
229 | ||
5a9335ef | 230 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
231 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
232 | ||
5a9335ef | 233 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 234 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 235 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 236 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 237 | |
9b66ebb1 | 238 | /* This will be overridden in arm_override_options. */ |
5a9335ef | 239 | #undef TARGET_RTX_COSTS |
9b66ebb1 | 240 | #define TARGET_RTX_COSTS arm_slowmul_rtx_costs |
5a9335ef | 241 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 242 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 243 | |
5a9335ef | 244 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
245 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
246 | ||
5a9335ef NC |
247 | #undef TARGET_INIT_BUILTINS |
248 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
249 | #undef TARGET_EXPAND_BUILTIN | |
250 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
251 | ||
f9ba5949 KH |
252 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
253 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true | |
d4453b7a PB |
254 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
255 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
f9ba5949 | 256 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 257 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
f9ba5949 KH |
258 | |
259 | #undef TARGET_STRUCT_VALUE_RTX | |
260 | #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx | |
261 | ||
1cc9f5f5 KH |
262 | #undef TARGET_SETUP_INCOMING_VARARGS |
263 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
264 | ||
6b045785 PB |
265 | #undef TARGET_DEFAULT_SHORT_ENUMS |
266 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
267 | ||
13c1cd82 PB |
268 | #undef TARGET_ALIGN_ANON_BITFIELD |
269 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
270 | ||
4185ae53 PB |
271 | #undef TARGET_CXX_GUARD_TYPE |
272 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
273 | ||
274 | #undef TARGET_CXX_GUARD_MASK_BIT | |
275 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
276 | ||
46e995e0 PB |
277 | #undef TARGET_CXX_GET_COOKIE_SIZE |
278 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
279 | ||
280 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
281 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
282 | ||
f6897b10 | 283 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 284 | \f |
c7319d87 RE |
285 | /* Obstack for minipool constant handling. */ |
286 | static struct obstack minipool_obstack; | |
1d6e90ac | 287 | static char * minipool_startobj; |
c7319d87 | 288 | |
1d6e90ac NC |
289 | /* The maximum number of insns skipped which |
290 | will be conditionalised if possible. */ | |
c27ba912 DM |
291 | static int max_insns_skipped = 5; |
292 | ||
293 | extern FILE * asm_out_file; | |
294 | ||
6354dc9b | 295 | /* True if we are currently building a constant table. */ |
13bd191d PB |
296 | int making_const_table; |
297 | ||
60d0536b | 298 | /* Define the information needed to generate branch insns. This is |
6354dc9b | 299 | stored from the compare operation. */ |
ff9940b0 | 300 | rtx arm_compare_op0, arm_compare_op1; |
ff9940b0 | 301 | |
9b66ebb1 PB |
302 | /* The processor for which instructions should be scheduled. */ |
303 | enum processor_type arm_tune = arm_none; | |
304 | ||
305 | /* Which floating point model to use. */ | |
306 | enum arm_fp_model arm_fp_model; | |
bee06f3d | 307 | |
9b66ebb1 | 308 | /* Which floating point hardware is available. */ |
29ad9694 | 309 | enum fputype arm_fpu_arch; |
b111229a | 310 | |
9b66ebb1 PB |
311 | /* Which floating point hardware to schedule for. */ |
312 | enum fputype arm_fpu_tune; | |
313 | ||
314 | /* Whether to use floating point hardware. */ | |
315 | enum float_abi_type arm_float_abi; | |
316 | ||
5848830f PB |
317 | /* Which ABI to use. */ |
318 | enum arm_abi_type arm_abi; | |
319 | ||
9b66ebb1 PB |
320 | /* Set by the -mfpu=... option. */ |
321 | const char * target_fpu_name = NULL; | |
322 | ||
323 | /* Set by the -mfpe=... option. */ | |
324 | const char * target_fpe_name = NULL; | |
325 | ||
326 | /* Set by the -mfloat-abi=... option. */ | |
327 | const char * target_float_abi_name = NULL; | |
2b835d68 | 328 | |
5848830f PB |
329 | /* Set by the -mabi=... option. */ |
330 | const char * target_abi_name = NULL; | |
331 | ||
b355a481 | 332 | /* Used to parse -mstructure_size_boundary command line option. */ |
f9cc092a | 333 | const char * structure_size_string = NULL; |
723ae7c1 | 334 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 335 | |
aec3cfba | 336 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 337 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 338 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
339 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
340 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
341 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
342 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
343 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
344 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
345 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 346 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 347 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 348 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 349 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
350 | media instructions. */ |
351 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
aec3cfba | 352 | |
9b66ebb1 PB |
353 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
354 | ||
78011587 PB |
355 | #define FL_FOR_ARCH2 0 |
356 | #define FL_FOR_ARCH3 FL_MODE32 | |
357 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) | |
358 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
359 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
360 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
361 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
362 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
363 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
364 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
365 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
366 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
367 | ||
1d6e90ac NC |
368 | /* The bits in this mask specify which |
369 | instructions we are allowed to generate. */ | |
0977774b | 370 | static unsigned long insn_flags = 0; |
d5b7b3ae | 371 | |
aec3cfba | 372 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 373 | be used. */ |
0977774b | 374 | static unsigned long tune_flags = 0; |
aec3cfba NC |
375 | |
376 | /* The following are used in the arm.md file as equivalents to bits | |
377 | in the above two flag variables. */ | |
378 | ||
9b66ebb1 PB |
379 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
380 | int arm_arch3m = 0; | |
2b835d68 | 381 | |
6354dc9b | 382 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
383 | int arm_arch4 = 0; |
384 | ||
68d560d4 RE |
385 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
386 | int arm_arch4t = 0; | |
387 | ||
6354dc9b | 388 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
389 | int arm_arch5 = 0; |
390 | ||
b15bca31 RE |
391 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
392 | int arm_arch5e = 0; | |
393 | ||
9b66ebb1 PB |
394 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
395 | int arm_arch6 = 0; | |
396 | ||
aec3cfba | 397 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
398 | int arm_ld_sched = 0; |
399 | ||
400 | /* Nonzero if this chip is a StrongARM. */ | |
401 | int arm_is_strong = 0; | |
402 | ||
78011587 PB |
403 | /* Nonzero if this chip is a Cirrus variant. */ |
404 | int arm_arch_cirrus = 0; | |
405 | ||
5a9335ef NC |
406 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
407 | int arm_arch_iwmmxt = 0; | |
408 | ||
d19fb8e3 | 409 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
410 | int arm_arch_xscale = 0; |
411 | ||
412 | /* Nonzero if tuning for XScale */ | |
413 | int arm_tune_xscale = 0; | |
d19fb8e3 | 414 | |
3569057d | 415 | /* Nonzero if this chip is an ARM6 or an ARM7. */ |
f5a1b0d2 | 416 | int arm_is_6_or_7 = 0; |
b111229a | 417 | |
0616531f RE |
418 | /* Nonzero if generating Thumb instructions. */ |
419 | int thumb_code = 0; | |
420 | ||
2ad4dcf9 RE |
421 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
422 | preprocessor. | |
423 | XXX This is a bit of a hack, it's intended to help work around | |
424 | problems in GLD which doesn't understand that armv5t code is | |
425 | interworking clean. */ | |
426 | int arm_cpp_interwork = 0; | |
427 | ||
cce8749e CH |
428 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
429 | must report the mode of the memory reference from PRINT_OPERAND to | |
430 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 431 | enum machine_mode output_memory_reference_mode; |
cce8749e | 432 | |
32de079a | 433 | /* The register number to be used for the PIC offset register. */ |
ed0e6530 | 434 | const char * arm_pic_register_string = NULL; |
5b43fed1 | 435 | int arm_pic_register = INVALID_REGNUM; |
32de079a | 436 | |
ff9940b0 | 437 | /* Set to 1 when a return insn is output, this means that the epilogue |
6354dc9b | 438 | is not needed. */ |
d5b7b3ae | 439 | int return_used_this_function; |
ff9940b0 | 440 | |
aec3cfba NC |
441 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
442 | the next function. */ | |
4b632bf1 RE |
443 | static int after_arm_reorg = 0; |
444 | ||
aec3cfba | 445 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
446 | static int arm_constant_limit = 3; |
447 | ||
cce8749e CH |
448 | /* For an explanation of these variables, see final_prescan_insn below. */ |
449 | int arm_ccfsm_state; | |
84ed5e79 | 450 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
451 | rtx arm_target_insn; |
452 | int arm_target_label; | |
9997d19d RE |
453 | |
454 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 455 | static const char * const arm_condition_codes[] = |
9997d19d RE |
456 | { |
457 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
458 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
459 | }; | |
460 | ||
f5a1b0d2 | 461 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
2b835d68 | 462 | \f |
6354dc9b | 463 | /* Initialization code. */ |
2b835d68 | 464 | |
2b835d68 RE |
465 | struct processors |
466 | { | |
8b60264b | 467 | const char *const name; |
9b66ebb1 | 468 | enum processor_type core; |
78011587 | 469 | const char *arch; |
0977774b | 470 | const unsigned long flags; |
9b66ebb1 | 471 | bool (* rtx_costs) (rtx, int, int, int *); |
2b835d68 RE |
472 | }; |
473 | ||
474 | /* Not all of these give usefully different compilation alternatives, | |
475 | but there is no simple way of generalizing them. */ | |
8b60264b | 476 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
477 | { |
478 | /* ARM Cores */ | |
78011587 PB |
479 | #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \ |
480 | {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | |
9b66ebb1 PB |
481 | #include "arm-cores.def" |
482 | #undef ARM_CORE | |
78011587 | 483 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
484 | }; |
485 | ||
8b60264b | 486 | static const struct processors all_architectures[] = |
2b835d68 | 487 | { |
f5a1b0d2 | 488 | /* ARM Architectures */ |
9b66ebb1 PB |
489 | /* We don't specify rtx_costs here as it will be figured out |
490 | from the core. */ | |
f5a1b0d2 | 491 | |
78011587 PB |
492 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
493 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
494 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
495 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
496 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
497 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
498 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
499 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
500 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
501 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
502 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
503 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
504 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
505 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
506 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, | |
507 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
508 | {NULL, arm_none, NULL, 0 , NULL} | |
f5a1b0d2 NC |
509 | }; |
510 | ||
9a9f7594 | 511 | /* This is a magic structure. The 'string' field is magically filled in |
f5a1b0d2 NC |
512 | with a pointer to the value specified by the user on the command line |
513 | assuming that the user has specified such a value. */ | |
514 | ||
515 | struct arm_cpu_select arm_select[] = | |
516 | { | |
517 | /* string name processors */ | |
518 | { NULL, "-mcpu=", all_cores }, | |
519 | { NULL, "-march=", all_architectures }, | |
520 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
521 | }; |
522 | ||
78011587 PB |
523 | |
524 | /* The name of the proprocessor macro to define for this architecture. */ | |
525 | ||
526 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
527 | ||
9b66ebb1 PB |
528 | struct fpu_desc |
529 | { | |
530 | const char * name; | |
531 | enum fputype fpu; | |
532 | }; | |
533 | ||
534 | ||
535 | /* Available values for for -mfpu=. */ | |
536 | ||
537 | static const struct fpu_desc all_fpus[] = | |
538 | { | |
539 | {"fpa", FPUTYPE_FPA}, | |
540 | {"fpe2", FPUTYPE_FPA_EMU2}, | |
541 | {"fpe3", FPUTYPE_FPA_EMU2}, | |
542 | {"maverick", FPUTYPE_MAVERICK}, | |
543 | {"vfp", FPUTYPE_VFP} | |
544 | }; | |
545 | ||
546 | ||
547 | /* Floating point models used by the different hardware. | |
548 | See fputype in arm.h. */ | |
549 | ||
550 | static const enum fputype fp_model_for_fpu[] = | |
551 | { | |
552 | /* No FP hardware. */ | |
553 | ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ | |
554 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ | |
555 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ | |
556 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ | |
557 | ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ | |
558 | ARM_FP_MODEL_VFP /* FPUTYPE_VFP */ | |
559 | }; | |
560 | ||
561 | ||
562 | struct float_abi | |
563 | { | |
564 | const char * name; | |
565 | enum float_abi_type abi_type; | |
566 | }; | |
567 | ||
568 | ||
569 | /* Available values for -mfloat-abi=. */ | |
570 | ||
571 | static const struct float_abi all_float_abis[] = | |
572 | { | |
573 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
574 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
575 | {"hard", ARM_FLOAT_ABI_HARD} | |
576 | }; | |
577 | ||
578 | ||
5848830f PB |
579 | struct abi_name |
580 | { | |
581 | const char *name; | |
582 | enum arm_abi_type abi_type; | |
583 | }; | |
584 | ||
585 | ||
586 | /* Available values for -mabi=. */ | |
587 | ||
588 | static const struct abi_name arm_all_abis[] = | |
589 | { | |
590 | {"apcs-gnu", ARM_ABI_APCS}, | |
591 | {"atpcs", ARM_ABI_ATPCS}, | |
592 | {"aapcs", ARM_ABI_AAPCS}, | |
593 | {"iwmmxt", ARM_ABI_IWMMXT} | |
594 | }; | |
595 | ||
0977774b JT |
596 | /* Return the number of bits set in VALUE. */ |
597 | static unsigned | |
e32bac5b | 598 | bit_count (unsigned long value) |
aec3cfba | 599 | { |
d5b7b3ae | 600 | unsigned long count = 0; |
aec3cfba NC |
601 | |
602 | while (value) | |
603 | { | |
0977774b JT |
604 | count++; |
605 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
606 | } |
607 | ||
608 | return count; | |
609 | } | |
610 | ||
2b835d68 RE |
611 | /* Fix up any incompatible options that the user has specified. |
612 | This has now turned into a maze. */ | |
613 | void | |
e32bac5b | 614 | arm_override_options (void) |
2b835d68 | 615 | { |
ed4c4348 | 616 | unsigned i; |
9b66ebb1 | 617 | |
f5a1b0d2 | 618 | /* Set up the flags based on the cpu/architecture selected by the user. */ |
b6a1cbae | 619 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 620 | { |
f5a1b0d2 NC |
621 | struct arm_cpu_select * ptr = arm_select + i; |
622 | ||
623 | if (ptr->string != NULL && ptr->string[0] != '\0') | |
bd9c7e23 | 624 | { |
13bd191d | 625 | const struct processors * sel; |
bd9c7e23 | 626 | |
5895f793 | 627 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 628 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 629 | { |
78011587 PB |
630 | /* Set the architecture define. */ |
631 | if (i != 2) | |
632 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); | |
633 | ||
9b66ebb1 PB |
634 | /* Determine the processor core for which we should |
635 | tune code-generation. */ | |
636 | if (/* -mcpu= is a sensible default. */ | |
637 | i == 0 | |
638 | /* If -march= is used, and -mcpu= has not been used, | |
639 | assume that we should tune for a representative | |
640 | CPU from that architecture. */ | |
641 | || i == 1 | |
642 | /* -mtune= overrides -mcpu= and -march=. */ | |
643 | || i == 2) | |
644 | arm_tune = (enum processor_type) (sel - ptr->processors); | |
645 | ||
646 | if (i != 2) | |
b111229a | 647 | { |
aec3cfba NC |
648 | /* If we have been given an architecture and a processor |
649 | make sure that they are compatible. We only generate | |
650 | a warning though, and we prefer the CPU over the | |
6354dc9b | 651 | architecture. */ |
aec3cfba | 652 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
6cf32035 | 653 | warning ("switch -mcpu=%s conflicts with -march= switch", |
aec3cfba NC |
654 | ptr->string); |
655 | ||
656 | insn_flags = sel->flags; | |
b111229a | 657 | } |
f5a1b0d2 | 658 | |
bd9c7e23 RE |
659 | break; |
660 | } | |
661 | ||
662 | if (sel->name == NULL) | |
663 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
664 | } | |
665 | } | |
aec3cfba | 666 | |
f5a1b0d2 | 667 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 668 | if (insn_flags == 0) |
f5a1b0d2 | 669 | { |
8b60264b | 670 | const struct processors * sel; |
aec3cfba | 671 | unsigned int sought; |
78011587 | 672 | enum processor_type cpu; |
aec3cfba | 673 | |
78011587 PB |
674 | cpu = TARGET_CPU_DEFAULT; |
675 | if (cpu == arm_none) | |
676 | { | |
677 | #ifdef SUBTARGET_CPU_DEFAULT | |
678 | /* Use the subtarget default CPU if none was specified by | |
679 | configure. */ | |
680 | cpu = SUBTARGET_CPU_DEFAULT; | |
681 | #endif | |
682 | /* Default to ARM6. */ | |
683 | if (cpu == arm_none) | |
684 | cpu = arm6; | |
685 | } | |
686 | sel = &all_cores[cpu]; | |
aec3cfba NC |
687 | |
688 | insn_flags = sel->flags; | |
9b66ebb1 | 689 | |
aec3cfba NC |
690 | /* Now check to see if the user has specified some command line |
691 | switch that require certain abilities from the cpu. */ | |
692 | sought = 0; | |
f5a1b0d2 | 693 | |
d5b7b3ae | 694 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 695 | { |
aec3cfba NC |
696 | sought |= (FL_THUMB | FL_MODE32); |
697 | ||
d5b7b3ae | 698 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
699 | interworking. Therefore we force FL_MODE26 to be removed |
700 | from insn_flags here (if it was set), so that the search | |
701 | below will always be able to find a compatible processor. */ | |
5895f793 | 702 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 703 | } |
d5b7b3ae | 704 | |
aec3cfba | 705 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 706 | { |
aec3cfba NC |
707 | /* Try to locate a CPU type that supports all of the abilities |
708 | of the default CPU, plus the extra abilities requested by | |
709 | the user. */ | |
5895f793 | 710 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 711 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
712 | break; |
713 | ||
714 | if (sel->name == NULL) | |
aec3cfba | 715 | { |
0977774b | 716 | unsigned current_bit_count = 0; |
8b60264b | 717 | const struct processors * best_fit = NULL; |
aec3cfba NC |
718 | |
719 | /* Ideally we would like to issue an error message here | |
720 | saying that it was not possible to find a CPU compatible | |
721 | with the default CPU, but which also supports the command | |
722 | line options specified by the programmer, and so they | |
723 | ought to use the -mcpu=<name> command line option to | |
724 | override the default CPU type. | |
725 | ||
61f0ccff RE |
726 | If we cannot find a cpu that has both the |
727 | characteristics of the default cpu and the given | |
728 | command line options we scan the array again looking | |
729 | for a best match. */ | |
5895f793 | 730 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
731 | if ((sel->flags & sought) == sought) |
732 | { | |
0977774b | 733 | unsigned count; |
aec3cfba NC |
734 | |
735 | count = bit_count (sel->flags & insn_flags); | |
736 | ||
737 | if (count >= current_bit_count) | |
738 | { | |
739 | best_fit = sel; | |
740 | current_bit_count = count; | |
741 | } | |
742 | } | |
f5a1b0d2 | 743 | |
aec3cfba NC |
744 | if (best_fit == NULL) |
745 | abort (); | |
746 | else | |
747 | sel = best_fit; | |
748 | } | |
749 | ||
750 | insn_flags = sel->flags; | |
f5a1b0d2 | 751 | } |
78011587 | 752 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
9b66ebb1 PB |
753 | if (arm_tune == arm_none) |
754 | arm_tune = (enum processor_type) (sel - all_cores); | |
f5a1b0d2 | 755 | } |
aec3cfba | 756 | |
9b66ebb1 PB |
757 | /* The processor for which we should tune should now have been |
758 | chosen. */ | |
759 | if (arm_tune == arm_none) | |
760 | abort (); | |
761 | ||
762 | tune_flags = all_cores[(int)arm_tune].flags; | |
763 | targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs; | |
e26053d1 | 764 | |
f5a1b0d2 NC |
765 | /* Make sure that the processor choice does not conflict with any of the |
766 | other command line choices. */ | |
6cfc7210 | 767 | if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) |
f5a1b0d2 NC |
768 | { |
769 | warning ("target CPU does not support interworking" ); | |
6cfc7210 | 770 | target_flags &= ~ARM_FLAG_INTERWORK; |
f5a1b0d2 NC |
771 | } |
772 | ||
d5b7b3ae RE |
773 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
774 | { | |
c725bd79 | 775 | warning ("target CPU does not support THUMB instructions"); |
d5b7b3ae RE |
776 | target_flags &= ~ARM_FLAG_THUMB; |
777 | } | |
778 | ||
779 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
780 | { | |
c725bd79 | 781 | /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ |
d5b7b3ae RE |
782 | target_flags &= ~ARM_FLAG_APCS_FRAME; |
783 | } | |
d19fb8e3 | 784 | |
d5b7b3ae RE |
785 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
786 | from here where no function is being compiled currently. */ | |
787 | if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) | |
788 | && TARGET_ARM) | |
c725bd79 | 789 | warning ("enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
790 | |
791 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
c725bd79 | 792 | warning ("enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
793 | |
794 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
c725bd79 | 795 | warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 796 | |
5895f793 | 797 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 NC |
798 | { |
799 | warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); | |
800 | target_flags |= ARM_FLAG_APCS_FRAME; | |
801 | } | |
aec3cfba | 802 | |
2b835d68 RE |
803 | if (TARGET_POKE_FUNCTION_NAME) |
804 | target_flags |= ARM_FLAG_APCS_FRAME; | |
aec3cfba | 805 | |
2b835d68 | 806 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 807 | error ("-fpic and -mapcs-reent are incompatible"); |
aec3cfba | 808 | |
2b835d68 | 809 | if (TARGET_APCS_REENT) |
f5a1b0d2 | 810 | warning ("APCS reentrant code not supported. Ignored"); |
aec3cfba | 811 | |
d5b7b3ae RE |
812 | /* If this target is normally configured to use APCS frames, warn if they |
813 | are turned off and debugging is turned on. */ | |
814 | if (TARGET_ARM | |
815 | && write_symbols != NO_DEBUG | |
5895f793 | 816 | && !TARGET_APCS_FRAME |
d5b7b3ae RE |
817 | && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) |
818 | warning ("-g with -mno-apcs-frame may not give sensible debugging"); | |
6cfc7210 | 819 | |
32de079a RE |
820 | /* If stack checking is disabled, we can use r10 as the PIC register, |
821 | which keeps r9 available. */ | |
5b43fed1 RH |
822 | if (flag_pic) |
823 | arm_pic_register = TARGET_APCS_STACK ? 9 : 10; | |
aec3cfba | 824 | |
2b835d68 | 825 | if (TARGET_APCS_FLOAT) |
c725bd79 | 826 | warning ("passing floating point arguments in fp regs not yet supported"); |
f5a1b0d2 | 827 | |
4912a07c | 828 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
829 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
830 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 831 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
832 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
833 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
834 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
835 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; | |
78011587 | 836 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
837 | |
838 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
839 | arm_is_strong = (tune_flags & FL_STRONG) != 0; | |
840 | thumb_code = (TARGET_ARM == 0); | |
841 | arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) | |
842 | && !(tune_flags & FL_ARCH4))) != 0; | |
843 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; | |
844 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5a9335ef | 845 | |
68d560d4 RE |
846 | /* V5 code we generate is completely interworking capable, so we turn off |
847 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
848 | |
849 | /* XXX However, we must pass the right pre-processor defines to CPP | |
850 | or GLD can get confused. This is a hack. */ | |
851 | if (TARGET_INTERWORK) | |
852 | arm_cpp_interwork = 1; | |
853 | ||
68d560d4 RE |
854 | if (arm_arch5) |
855 | target_flags &= ~ARM_FLAG_INTERWORK; | |
856 | ||
5848830f PB |
857 | if (target_abi_name) |
858 | { | |
859 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
860 | { | |
861 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
862 | { | |
863 | arm_abi = arm_all_abis[i].abi_type; | |
864 | break; | |
865 | } | |
866 | } | |
867 | if (i == ARRAY_SIZE (arm_all_abis)) | |
868 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
869 | } | |
870 | else | |
c805f22e | 871 | arm_abi = ARM_DEFAULT_ABI; |
5848830f PB |
872 | |
873 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) | |
874 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
875 | ||
876 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
877 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 878 | |
9b66ebb1 PB |
879 | arm_fp_model = ARM_FP_MODEL_UNKNOWN; |
880 | if (target_fpu_name == NULL && target_fpe_name != NULL) | |
9b6b54e2 | 881 | { |
9b66ebb1 PB |
882 | if (streq (target_fpe_name, "2")) |
883 | target_fpu_name = "fpe2"; | |
884 | else if (streq (target_fpe_name, "3")) | |
885 | target_fpu_name = "fpe3"; | |
886 | else | |
887 | error ("invalid floating point emulation option: -mfpe=%s", | |
888 | target_fpe_name); | |
889 | } | |
890 | if (target_fpu_name != NULL) | |
891 | { | |
892 | /* The user specified a FPU. */ | |
893 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
894 | { | |
895 | if (streq (all_fpus[i].name, target_fpu_name)) | |
896 | { | |
897 | arm_fpu_arch = all_fpus[i].fpu; | |
898 | arm_fpu_tune = arm_fpu_arch; | |
899 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
900 | break; | |
901 | } | |
902 | } | |
903 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
904 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
9b6b54e2 NC |
905 | } |
906 | else | |
2b835d68 | 907 | { |
9b66ebb1 | 908 | #ifdef FPUTYPE_DEFAULT |
78011587 | 909 | /* Use the default if it is specified for this platform. */ |
9b66ebb1 PB |
910 | arm_fpu_arch = FPUTYPE_DEFAULT; |
911 | arm_fpu_tune = FPUTYPE_DEFAULT; | |
912 | #else | |
913 | /* Pick one based on CPU type. */ | |
78011587 | 914 | /* ??? Some targets assume FPA is the default. |
9b66ebb1 PB |
915 | if ((insn_flags & FL_VFP) != 0) |
916 | arm_fpu_arch = FPUTYPE_VFP; | |
78011587 PB |
917 | else |
918 | */ | |
919 | if (arm_arch_cirrus) | |
9b66ebb1 PB |
920 | arm_fpu_arch = FPUTYPE_MAVERICK; |
921 | else | |
29ad9694 | 922 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
9b66ebb1 PB |
923 | #endif |
924 | if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
925 | arm_fpu_tune = FPUTYPE_FPA; | |
2b835d68 | 926 | else |
9b66ebb1 PB |
927 | arm_fpu_tune = arm_fpu_arch; |
928 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
929 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
930 | abort (); | |
931 | } | |
932 | ||
933 | if (target_float_abi_name != NULL) | |
934 | { | |
935 | /* The user specified a FP ABI. */ | |
936 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
937 | { | |
938 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
939 | { | |
940 | arm_float_abi = all_float_abis[i].abi_type; | |
941 | break; | |
942 | } | |
943 | } | |
944 | if (i == ARRAY_SIZE (all_float_abis)) | |
945 | error ("invalid floating point abi: -mfloat-abi=%s", | |
946 | target_float_abi_name); | |
2b835d68 | 947 | } |
b111229a | 948 | else |
9b6b54e2 | 949 | { |
9b66ebb1 PB |
950 | /* Use soft-float target flag. */ |
951 | if (target_flags & ARM_FLAG_SOFT_FLOAT) | |
952 | arm_float_abi = ARM_FLOAT_ABI_SOFT; | |
953 | else | |
954 | arm_float_abi = ARM_FLOAT_ABI_HARD; | |
9b6b54e2 | 955 | } |
9b66ebb1 PB |
956 | |
957 | if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP) | |
958 | sorry ("-mfloat-abi=softfp"); | |
959 | /* If soft-float is specified then don't use FPU. */ | |
960 | if (TARGET_SOFT_FLOAT) | |
961 | arm_fpu_arch = FPUTYPE_NONE; | |
aec3cfba | 962 | |
f5a1b0d2 NC |
963 | /* For arm2/3 there is no need to do any scheduling if there is only |
964 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 PB |
965 | if ((TARGET_SOFT_FLOAT |
966 | || arm_fpu_tune == FPUTYPE_FPA_EMU2 | |
967 | || arm_fpu_tune == FPUTYPE_FPA_EMU3) | |
ed0e6530 | 968 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 969 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
aec3cfba | 970 | |
5848830f PB |
971 | /* Override the default structure alignment for AAPCS ABI. */ |
972 | if (arm_abi == ARM_ABI_AAPCS) | |
973 | arm_structure_size_boundary = 8; | |
974 | ||
b355a481 NC |
975 | if (structure_size_string != NULL) |
976 | { | |
977 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
978 | |
979 | if (size == 8 || size == 32 | |
980 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
981 | arm_structure_size_boundary = size; |
982 | else | |
5848830f PB |
983 | warning ("structure size boundary can only be set to %s", |
984 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); | |
b355a481 | 985 | } |
ed0e6530 PB |
986 | |
987 | if (arm_pic_register_string != NULL) | |
988 | { | |
5b43fed1 | 989 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 990 | |
5895f793 | 991 | if (!flag_pic) |
ed0e6530 PB |
992 | warning ("-mpic-register= is useless without -fpic"); |
993 | ||
ed0e6530 | 994 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
995 | else if (pic_register < 0 || call_used_regs[pic_register] |
996 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
997 | || pic_register == STACK_POINTER_REGNUM | |
998 | || pic_register >= PC_REGNUM) | |
c725bd79 | 999 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1000 | else |
1001 | arm_pic_register = pic_register; | |
1002 | } | |
d5b7b3ae RE |
1003 | |
1004 | if (TARGET_THUMB && flag_schedule_insns) | |
1005 | { | |
1006 | /* Don't warn since it's on by default in -O2. */ | |
1007 | flag_schedule_insns = 0; | |
1008 | } | |
1009 | ||
f5a1b0d2 | 1010 | if (optimize_size) |
be03ccc9 | 1011 | { |
577d6328 RE |
1012 | /* There's some dispute as to whether this should be 1 or 2. However, |
1013 | experiments seem to show that in pathological cases a setting of | |
839a4992 | 1014 | 1 degrades less severely than a setting of 2. This could change if |
577d6328 RE |
1015 | other parts of the compiler change their behavior. */ |
1016 | arm_constant_limit = 1; | |
be03ccc9 NP |
1017 | |
1018 | /* If optimizing for size, bump the number of instructions that we | |
d6b4baa4 | 1019 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1020 | max_insns_skipped = 6; |
1021 | } | |
1022 | else | |
1023 | { | |
1024 | /* For processors with load scheduling, it never costs more than | |
1025 | 2 cycles to load a constant, and the load scheduler may well | |
1026 | reduce that to 1. */ | |
1027 | if (tune_flags & FL_LDSCHED) | |
1028 | arm_constant_limit = 1; | |
1029 | ||
1030 | /* On XScale the longer latency of a load makes it more difficult | |
1031 | to achieve a good schedule, so it's faster to synthesize | |
d6b4baa4 | 1032 | constants that can be done in two insns. */ |
be03ccc9 NP |
1033 | if (arm_tune_xscale) |
1034 | arm_constant_limit = 2; | |
1035 | ||
1036 | /* StrongARM has early execution of branches, so a sequence | |
1037 | that is worth skipping is shorter. */ | |
1038 | if (arm_is_strong) | |
1039 | max_insns_skipped = 3; | |
1040 | } | |
92a432f4 RE |
1041 | |
1042 | /* Register global variables with the garbage collector. */ | |
1043 | arm_add_gc_roots (); | |
1044 | } | |
1045 | ||
1046 | static void | |
e32bac5b | 1047 | arm_add_gc_roots (void) |
92a432f4 | 1048 | { |
c7319d87 RE |
1049 | gcc_obstack_init(&minipool_obstack); |
1050 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1051 | } |
cce8749e | 1052 | \f |
6d3d9133 NC |
1053 | /* A table of known ARM exception types. |
1054 | For use with the interrupt function attribute. */ | |
1055 | ||
1056 | typedef struct | |
1057 | { | |
8b60264b KG |
1058 | const char *const arg; |
1059 | const unsigned long return_value; | |
6d3d9133 NC |
1060 | } |
1061 | isr_attribute_arg; | |
1062 | ||
8b60264b | 1063 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1064 | { |
1065 | { "IRQ", ARM_FT_ISR }, | |
1066 | { "irq", ARM_FT_ISR }, | |
1067 | { "FIQ", ARM_FT_FIQ }, | |
1068 | { "fiq", ARM_FT_FIQ }, | |
1069 | { "ABORT", ARM_FT_ISR }, | |
1070 | { "abort", ARM_FT_ISR }, | |
1071 | { "ABORT", ARM_FT_ISR }, | |
1072 | { "abort", ARM_FT_ISR }, | |
1073 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1074 | { "undef", ARM_FT_EXCEPTION }, | |
1075 | { "SWI", ARM_FT_EXCEPTION }, | |
1076 | { "swi", ARM_FT_EXCEPTION }, | |
1077 | { NULL, ARM_FT_NORMAL } | |
1078 | }; | |
1079 | ||
1080 | /* Returns the (interrupt) function type of the current | |
1081 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1082 | ||
1083 | static unsigned long | |
e32bac5b | 1084 | arm_isr_value (tree argument) |
6d3d9133 | 1085 | { |
8b60264b | 1086 | const isr_attribute_arg * ptr; |
1d6e90ac | 1087 | const char * arg; |
6d3d9133 NC |
1088 | |
1089 | /* No argument - default to IRQ. */ | |
1090 | if (argument == NULL_TREE) | |
1091 | return ARM_FT_ISR; | |
1092 | ||
1093 | /* Get the value of the argument. */ | |
1094 | if (TREE_VALUE (argument) == NULL_TREE | |
1095 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1096 | return ARM_FT_UNKNOWN; | |
1097 | ||
1098 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1099 | ||
1100 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1101 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1102 | if (streq (arg, ptr->arg)) |
1103 | return ptr->return_value; | |
6d3d9133 | 1104 | |
05713b80 | 1105 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1106 | return ARM_FT_UNKNOWN; |
1107 | } | |
1108 | ||
1109 | /* Computes the type of the current function. */ | |
1110 | ||
1111 | static unsigned long | |
e32bac5b | 1112 | arm_compute_func_type (void) |
6d3d9133 NC |
1113 | { |
1114 | unsigned long type = ARM_FT_UNKNOWN; | |
1115 | tree a; | |
1116 | tree attr; | |
1117 | ||
1118 | if (TREE_CODE (current_function_decl) != FUNCTION_DECL) | |
1119 | abort (); | |
1120 | ||
1121 | /* Decide if the current function is volatile. Such functions | |
1122 | never return, and many memory cycles can be saved by not storing | |
1123 | register values that will never be needed again. This optimization | |
1124 | was added to speed up context switching in a kernel application. */ | |
1125 | if (optimize > 0 | |
97b0ade3 | 1126 | && TREE_NOTHROW (current_function_decl) |
6d3d9133 NC |
1127 | && TREE_THIS_VOLATILE (current_function_decl)) |
1128 | type |= ARM_FT_VOLATILE; | |
1129 | ||
6de9cd9a | 1130 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
1131 | type |= ARM_FT_NESTED; |
1132 | ||
91d231cb | 1133 | attr = DECL_ATTRIBUTES (current_function_decl); |
6d3d9133 NC |
1134 | |
1135 | a = lookup_attribute ("naked", attr); | |
1136 | if (a != NULL_TREE) | |
1137 | type |= ARM_FT_NAKED; | |
1138 | ||
1139 | if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) | |
1140 | type |= ARM_FT_EXCEPTION_HANDLER; | |
1141 | else | |
1142 | { | |
1143 | a = lookup_attribute ("isr", attr); | |
1144 | if (a == NULL_TREE) | |
1145 | a = lookup_attribute ("interrupt", attr); | |
1146 | ||
1147 | if (a == NULL_TREE) | |
1148 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
1149 | else | |
1150 | type |= arm_isr_value (TREE_VALUE (a)); | |
1151 | } | |
1152 | ||
1153 | return type; | |
1154 | } | |
1155 | ||
1156 | /* Returns the type of the current function. */ | |
1157 | ||
1158 | unsigned long | |
e32bac5b | 1159 | arm_current_func_type (void) |
6d3d9133 NC |
1160 | { |
1161 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
1162 | cfun->machine->func_type = arm_compute_func_type (); | |
1163 | ||
1164 | return cfun->machine->func_type; | |
1165 | } | |
1166 | \f | |
a72d4945 RE |
1167 | /* Return 1 if it is possible to return using a single instruction. |
1168 | If SIBLING is non-null, this is a test for a return before a sibling | |
1169 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 1170 | |
ff9940b0 | 1171 | int |
a72d4945 | 1172 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
1173 | { |
1174 | int regno; | |
9b598fa0 | 1175 | unsigned int func_type; |
d5db54a1 | 1176 | unsigned long saved_int_regs; |
a72d4945 | 1177 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 1178 | arm_stack_offsets *offsets; |
ff9940b0 | 1179 | |
d5b7b3ae | 1180 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
1181 | if (!reload_completed) |
1182 | return 0; | |
efc2515b | 1183 | |
9b598fa0 RE |
1184 | func_type = arm_current_func_type (); |
1185 | ||
3a7731fd PB |
1186 | /* Naked functions and volatile functions need special |
1187 | consideration. */ | |
1188 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) | |
6d3d9133 | 1189 | return 0; |
06bea5aa NC |
1190 | |
1191 | /* So do interrupt functions that use the frame pointer. */ | |
1192 | if (IS_INTERRUPT (func_type) && frame_pointer_needed) | |
1193 | return 0; | |
a72d4945 | 1194 | |
5848830f PB |
1195 | offsets = arm_get_frame_offsets (); |
1196 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 1197 | |
6d3d9133 NC |
1198 | /* As do variadic functions. */ |
1199 | if (current_function_pretend_args_size | |
3cb66fd7 | 1200 | || cfun->machine->uses_anonymous_args |
699a4925 | 1201 | /* Or if the function calls __builtin_eh_return () */ |
6d3d9133 | 1202 | || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
699a4925 RE |
1203 | /* Or if the function calls alloca */ |
1204 | || current_function_calls_alloca | |
a72d4945 RE |
1205 | /* Or if there is a stack adjustment. However, if the stack pointer |
1206 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
1207 | || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4))) | |
ff9940b0 RE |
1208 | return 0; |
1209 | ||
d5db54a1 RE |
1210 | saved_int_regs = arm_compute_save_reg_mask (); |
1211 | ||
a72d4945 RE |
1212 | /* Unfortunately, the insn |
1213 | ||
1214 | ldmib sp, {..., sp, ...} | |
1215 | ||
1216 | triggers a bug on most SA-110 based devices, such that the stack | |
1217 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 1218 | page fault. We work around this problem by popping r3 along with |
a72d4945 RE |
1219 | the other registers, since that is never slower than executing |
1220 | another instruction. | |
1221 | ||
1222 | We test for !arm_arch5 here, because code for any architecture | |
1223 | less than this could potentially be run on one of the buggy | |
1224 | chips. */ | |
1225 | if (stack_adjust == 4 && !arm_arch5) | |
1226 | { | |
1227 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 1228 | the default abi) ... */ |
a72d4945 RE |
1229 | if (!call_used_regs[3]) |
1230 | return 0; | |
1231 | ||
1232 | /* ... that it isn't being used for a return value (always true | |
1233 | until we implement return-in-regs), or for a tail-call | |
d6b4baa4 | 1234 | argument ... */ |
a72d4945 RE |
1235 | if (sibling) |
1236 | { | |
1237 | if (GET_CODE (sibling) != CALL_INSN) | |
1238 | abort (); | |
1239 | ||
1240 | if (find_regno_fusage (sibling, USE, 3)) | |
1241 | return 0; | |
1242 | } | |
1243 | ||
1244 | /* ... and that there are no call-saved registers in r0-r2 | |
1245 | (always true in the default ABI). */ | |
1246 | if (saved_int_regs & 0x7) | |
1247 | return 0; | |
1248 | } | |
1249 | ||
b111229a | 1250 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 RE |
1251 | stacked. */ |
1252 | if (TARGET_INTERWORK && saved_int_regs != 0) | |
b36ba79f | 1253 | return 0; |
d5db54a1 RE |
1254 | |
1255 | /* On StrongARM, conditional returns are expensive if they aren't | |
1256 | taken and multiple registers have been stacked. */ | |
1257 | if (iscond && arm_is_strong) | |
6ed30148 | 1258 | { |
d5db54a1 RE |
1259 | /* Conditional return when just the LR is stored is a simple |
1260 | conditional-load instruction, that's not expensive. */ | |
1261 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
1262 | return 0; | |
6ed30148 RE |
1263 | |
1264 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
b111229a | 1265 | return 0; |
6ed30148 | 1266 | } |
d5db54a1 RE |
1267 | |
1268 | /* If there are saved registers but the LR isn't saved, then we need | |
1269 | two instructions for the return. */ | |
1270 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
1271 | return 0; | |
1272 | ||
3b684012 | 1273 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 1274 | since this also requires an insn. */ |
9b66ebb1 PB |
1275 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
1276 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
1277 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
1278 | return 0; | |
1279 | ||
1280 | /* Likewise VFP regs. */ | |
1281 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
1282 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
5895f793 | 1283 | if (regs_ever_live[regno] && !call_used_regs[regno]) |
d5b7b3ae | 1284 | return 0; |
ff9940b0 | 1285 | |
5a9335ef NC |
1286 | if (TARGET_REALLY_IWMMXT) |
1287 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
1288 | if (regs_ever_live[regno] && ! call_used_regs [regno]) | |
1289 | return 0; | |
1290 | ||
ff9940b0 RE |
1291 | return 1; |
1292 | } | |
1293 | ||
cce8749e CH |
1294 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
1295 | ||
1296 | int | |
e32bac5b | 1297 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 1298 | { |
30cf4896 | 1299 | unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; |
cce8749e | 1300 | |
56636818 JL |
1301 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
1302 | be all zero, or all one. */ | |
30cf4896 KG |
1303 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
1304 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
1305 | != ((~(unsigned HOST_WIDE_INT) 0) | |
1306 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 JL |
1307 | return FALSE; |
1308 | ||
e2c671ba RE |
1309 | /* Fast return for 0 and powers of 2 */ |
1310 | if ((i & (i - 1)) == 0) | |
1311 | return TRUE; | |
1312 | ||
cce8749e CH |
1313 | do |
1314 | { | |
30cf4896 | 1315 | if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) |
f3bb6135 | 1316 | return TRUE; |
abaa26e5 | 1317 | mask = |
30cf4896 KG |
1318 | (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) |
1319 | >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff; | |
ebe413e5 NC |
1320 | } |
1321 | while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); | |
cce8749e | 1322 | |
f3bb6135 RE |
1323 | return FALSE; |
1324 | } | |
cce8749e | 1325 | |
6354dc9b | 1326 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 1327 | static int |
e32bac5b | 1328 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
1329 | { |
1330 | if (const_ok_for_arm (i)) | |
1331 | return 1; | |
1332 | ||
1333 | switch (code) | |
1334 | { | |
1335 | case PLUS: | |
1336 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); | |
1337 | ||
1338 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
1339 | case XOR: | |
1340 | case IOR: | |
1341 | return 0; | |
1342 | ||
1343 | case AND: | |
1344 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
1345 | ||
1346 | default: | |
1347 | abort (); | |
1348 | } | |
1349 | } | |
1350 | ||
1351 | /* Emit a sequence of insns to handle a large constant. | |
1352 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
1353 | IOR, AND, XOR, MINUS; | |
1354 | MODE is the mode in which the operation is being performed; | |
1355 | VAL is the integer to operate on; | |
1356 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
1357 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
1358 | either produce a simpler sequence, or we will want to cse the values. |
1359 | Return value is the number of insns emitted. */ | |
e2c671ba RE |
1360 | |
1361 | int | |
a406f566 | 1362 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 1363 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 1364 | { |
a406f566 MM |
1365 | rtx cond; |
1366 | ||
1367 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
1368 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
1369 | else | |
1370 | cond = NULL_RTX; | |
1371 | ||
2b835d68 RE |
1372 | if (subtargets || code == SET |
1373 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
1374 | && REGNO (target) != REGNO (source))) | |
1375 | { | |
4b632bf1 | 1376 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 1377 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
1378 | them in-line, regardless of the cost. This is only likely to |
1379 | be more costly on chips that have load delay slots and we are | |
1380 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
1381 | occurred before the final instruction emission). |
1382 | ||
1383 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 1384 | */ |
5895f793 | 1385 | if (!after_arm_reorg |
a406f566 MM |
1386 | && !cond |
1387 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, | |
1388 | 1, 0) | |
4b632bf1 | 1389 | > arm_constant_limit + (code != SET))) |
2b835d68 RE |
1390 | { |
1391 | if (code == SET) | |
1392 | { | |
1393 | /* Currently SET is the only monadic value for CODE, all | |
1394 | the rest are diadic. */ | |
43cffd11 | 1395 | emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); |
2b835d68 RE |
1396 | return 1; |
1397 | } | |
1398 | else | |
1399 | { | |
1400 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
1401 | ||
43cffd11 | 1402 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); |
2b835d68 RE |
1403 | /* For MINUS, the value is subtracted from, since we never |
1404 | have subtraction of a constant. */ | |
1405 | if (code == MINUS) | |
43cffd11 | 1406 | emit_insn (gen_rtx_SET (VOIDmode, target, |
d5b7b3ae | 1407 | gen_rtx_MINUS (mode, temp, source))); |
2b835d68 | 1408 | else |
43cffd11 | 1409 | emit_insn (gen_rtx_SET (VOIDmode, target, |
1c563bed | 1410 | gen_rtx_fmt_ee (code, mode, source, temp))); |
2b835d68 RE |
1411 | return 2; |
1412 | } | |
1413 | } | |
1414 | } | |
1415 | ||
a406f566 MM |
1416 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
1417 | 1); | |
2b835d68 RE |
1418 | } |
1419 | ||
ceebdb09 | 1420 | static int |
e32bac5b | 1421 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
1422 | { |
1423 | HOST_WIDE_INT temp1; | |
1424 | int num_insns = 0; | |
1425 | do | |
1426 | { | |
1427 | int end; | |
1428 | ||
1429 | if (i <= 0) | |
1430 | i += 32; | |
1431 | if (remainder & (3 << (i - 2))) | |
1432 | { | |
1433 | end = i - 8; | |
1434 | if (end < 0) | |
1435 | end += 32; | |
1436 | temp1 = remainder & ((0x0ff << end) | |
1437 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
1438 | remainder &= ~temp1; | |
1439 | num_insns++; | |
1440 | i -= 6; | |
1441 | } | |
1442 | i -= 2; | |
1443 | } while (remainder); | |
1444 | return num_insns; | |
1445 | } | |
1446 | ||
a406f566 MM |
1447 | /* Emit an instruction with the indicated PATTERN. If COND is |
1448 | non-NULL, conditionalize the execution of the instruction on COND | |
1449 | being true. */ | |
1450 | ||
1451 | static void | |
1452 | emit_constant_insn (rtx cond, rtx pattern) | |
1453 | { | |
1454 | if (cond) | |
1455 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
1456 | emit_insn (pattern); | |
1457 | } | |
1458 | ||
2b835d68 RE |
1459 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
1460 | RTL generation. */ | |
1d6e90ac | 1461 | |
d5b7b3ae | 1462 | static int |
a406f566 | 1463 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
1464 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
1465 | int generate) | |
e2c671ba | 1466 | { |
e2c671ba RE |
1467 | int can_invert = 0; |
1468 | int can_negate = 0; | |
1469 | int can_negate_initial = 0; | |
1470 | int can_shift = 0; | |
1471 | int i; | |
1472 | int num_bits_set = 0; | |
1473 | int set_sign_bit_copies = 0; | |
1474 | int clear_sign_bit_copies = 0; | |
1475 | int clear_zero_bit_copies = 0; | |
1476 | int set_zero_bit_copies = 0; | |
1477 | int insns = 0; | |
e2c671ba | 1478 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 1479 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 1480 | |
d5b7b3ae | 1481 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
1482 | check for degenerate cases; these can occur when DImode operations |
1483 | are split. */ | |
1484 | switch (code) | |
1485 | { | |
1486 | case SET: | |
1487 | can_invert = 1; | |
1488 | can_shift = 1; | |
1489 | can_negate = 1; | |
1490 | break; | |
1491 | ||
1492 | case PLUS: | |
1493 | can_negate = 1; | |
1494 | can_negate_initial = 1; | |
1495 | break; | |
1496 | ||
1497 | case IOR: | |
30cf4896 | 1498 | if (remainder == 0xffffffff) |
e2c671ba | 1499 | { |
2b835d68 | 1500 | if (generate) |
a406f566 MM |
1501 | emit_constant_insn (cond, |
1502 | gen_rtx_SET (VOIDmode, target, | |
1503 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
1504 | return 1; |
1505 | } | |
1506 | if (remainder == 0) | |
1507 | { | |
1508 | if (reload_completed && rtx_equal_p (target, source)) | |
1509 | return 0; | |
2b835d68 | 1510 | if (generate) |
a406f566 MM |
1511 | emit_constant_insn (cond, |
1512 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1513 | return 1; |
1514 | } | |
1515 | break; | |
1516 | ||
1517 | case AND: | |
1518 | if (remainder == 0) | |
1519 | { | |
2b835d68 | 1520 | if (generate) |
a406f566 MM |
1521 | emit_constant_insn (cond, |
1522 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
1523 | return 1; |
1524 | } | |
30cf4896 | 1525 | if (remainder == 0xffffffff) |
e2c671ba RE |
1526 | { |
1527 | if (reload_completed && rtx_equal_p (target, source)) | |
1528 | return 0; | |
2b835d68 | 1529 | if (generate) |
a406f566 MM |
1530 | emit_constant_insn (cond, |
1531 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1532 | return 1; |
1533 | } | |
1534 | can_invert = 1; | |
1535 | break; | |
1536 | ||
1537 | case XOR: | |
1538 | if (remainder == 0) | |
1539 | { | |
1540 | if (reload_completed && rtx_equal_p (target, source)) | |
1541 | return 0; | |
2b835d68 | 1542 | if (generate) |
a406f566 MM |
1543 | emit_constant_insn (cond, |
1544 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
1545 | return 1; |
1546 | } | |
30cf4896 | 1547 | if (remainder == 0xffffffff) |
e2c671ba | 1548 | { |
2b835d68 | 1549 | if (generate) |
a406f566 MM |
1550 | emit_constant_insn (cond, |
1551 | gen_rtx_SET (VOIDmode, target, | |
1552 | gen_rtx_NOT (mode, source))); | |
e2c671ba RE |
1553 | return 1; |
1554 | } | |
1555 | ||
1556 | /* We don't know how to handle this yet below. */ | |
1557 | abort (); | |
1558 | ||
1559 | case MINUS: | |
1560 | /* We treat MINUS as (val - source), since (source - val) is always | |
1561 | passed as (source + (-val)). */ | |
1562 | if (remainder == 0) | |
1563 | { | |
2b835d68 | 1564 | if (generate) |
a406f566 MM |
1565 | emit_constant_insn (cond, |
1566 | gen_rtx_SET (VOIDmode, target, | |
1567 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
1568 | return 1; |
1569 | } | |
1570 | if (const_ok_for_arm (val)) | |
1571 | { | |
2b835d68 | 1572 | if (generate) |
a406f566 MM |
1573 | emit_constant_insn (cond, |
1574 | gen_rtx_SET (VOIDmode, target, | |
1575 | gen_rtx_MINUS (mode, GEN_INT (val), | |
1576 | source))); | |
e2c671ba RE |
1577 | return 1; |
1578 | } | |
1579 | can_negate = 1; | |
1580 | ||
1581 | break; | |
1582 | ||
1583 | default: | |
1584 | abort (); | |
1585 | } | |
1586 | ||
6354dc9b | 1587 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
1588 | if (const_ok_for_arm (val) |
1589 | || (can_negate_initial && const_ok_for_arm (-val)) | |
1590 | || (can_invert && const_ok_for_arm (~val))) | |
1591 | { | |
2b835d68 | 1592 | if (generate) |
a406f566 MM |
1593 | emit_constant_insn (cond, |
1594 | gen_rtx_SET (VOIDmode, target, | |
1595 | (source | |
1596 | ? gen_rtx_fmt_ee (code, mode, source, | |
1597 | GEN_INT (val)) | |
1598 | : GEN_INT (val)))); | |
e2c671ba RE |
1599 | return 1; |
1600 | } | |
1601 | ||
e2c671ba | 1602 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 1603 | optimizations. */ |
e2c671ba RE |
1604 | for (i = 31; i >= 0; i--) |
1605 | { | |
1606 | if ((remainder & (1 << i)) == 0) | |
1607 | clear_sign_bit_copies++; | |
1608 | else | |
1609 | break; | |
1610 | } | |
1611 | ||
1612 | for (i = 31; i >= 0; i--) | |
1613 | { | |
1614 | if ((remainder & (1 << i)) != 0) | |
1615 | set_sign_bit_copies++; | |
1616 | else | |
1617 | break; | |
1618 | } | |
1619 | ||
1620 | for (i = 0; i <= 31; i++) | |
1621 | { | |
1622 | if ((remainder & (1 << i)) == 0) | |
1623 | clear_zero_bit_copies++; | |
1624 | else | |
1625 | break; | |
1626 | } | |
1627 | ||
1628 | for (i = 0; i <= 31; i++) | |
1629 | { | |
1630 | if ((remainder & (1 << i)) != 0) | |
1631 | set_zero_bit_copies++; | |
1632 | else | |
1633 | break; | |
1634 | } | |
1635 | ||
1636 | switch (code) | |
1637 | { | |
1638 | case SET: | |
1639 | /* See if we can do this by sign_extending a constant that is known | |
1640 | to be negative. This is a good, way of doing it, since the shift | |
1641 | may well merge into a subsequent insn. */ | |
1642 | if (set_sign_bit_copies > 1) | |
1643 | { | |
1644 | if (const_ok_for_arm | |
1645 | (temp1 = ARM_SIGN_EXTEND (remainder | |
1646 | << (set_sign_bit_copies - 1)))) | |
1647 | { | |
2b835d68 RE |
1648 | if (generate) |
1649 | { | |
d499463f | 1650 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
1651 | emit_constant_insn (cond, |
1652 | gen_rtx_SET (VOIDmode, new_src, | |
1653 | GEN_INT (temp1))); | |
1654 | emit_constant_insn (cond, | |
1655 | gen_ashrsi3 (target, new_src, | |
1656 | GEN_INT (set_sign_bit_copies - 1))); | |
2b835d68 | 1657 | } |
e2c671ba RE |
1658 | return 2; |
1659 | } | |
1660 | /* For an inverted constant, we will need to set the low bits, | |
1661 | these will be shifted out of harm's way. */ | |
1662 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
1663 | if (const_ok_for_arm (~temp1)) | |
1664 | { | |
2b835d68 RE |
1665 | if (generate) |
1666 | { | |
d499463f | 1667 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
1668 | emit_constant_insn (cond, |
1669 | gen_rtx_SET (VOIDmode, new_src, | |
1670 | GEN_INT (temp1))); | |
1671 | emit_constant_insn (cond, | |
1672 | gen_ashrsi3 (target, new_src, | |
1673 | GEN_INT (set_sign_bit_copies - 1))); | |
2b835d68 | 1674 | } |
e2c671ba RE |
1675 | return 2; |
1676 | } | |
1677 | } | |
1678 | ||
1679 | /* See if we can generate this by setting the bottom (or the top) | |
1680 | 16 bits, and then shifting these into the other half of the | |
1681 | word. We only look for the simplest cases, to do more would cost | |
1682 | too much. Be careful, however, not to generate this when the | |
1683 | alternative would take fewer insns. */ | |
30cf4896 | 1684 | if (val & 0xffff0000) |
e2c671ba | 1685 | { |
30cf4896 | 1686 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
1687 | temp2 = remainder & 0x0000ffff; |
1688 | ||
6354dc9b | 1689 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
1690 | for (i = 9; i < 24; i++) |
1691 | { | |
30cf4896 | 1692 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 1693 | && !const_ok_for_arm (temp2)) |
e2c671ba | 1694 | { |
d499463f RE |
1695 | rtx new_src = (subtargets |
1696 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1697 | : target); | |
a406f566 | 1698 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 1699 | source, subtargets, generate); |
e2c671ba | 1700 | source = new_src; |
2b835d68 | 1701 | if (generate) |
a406f566 MM |
1702 | emit_constant_insn |
1703 | (cond, | |
1704 | gen_rtx_SET | |
1705 | (VOIDmode, target, | |
1706 | gen_rtx_IOR (mode, | |
1707 | gen_rtx_ASHIFT (mode, source, | |
1708 | GEN_INT (i)), | |
1709 | source))); | |
e2c671ba RE |
1710 | return insns + 1; |
1711 | } | |
1712 | } | |
1713 | ||
6354dc9b | 1714 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
1715 | for (i = 17; i < 24; i++) |
1716 | { | |
1717 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 1718 | && !const_ok_for_arm (temp1)) |
e2c671ba | 1719 | { |
d499463f RE |
1720 | rtx new_src = (subtargets |
1721 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
1722 | : target); | |
a406f566 | 1723 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 1724 | source, subtargets, generate); |
e2c671ba | 1725 | source = new_src; |
2b835d68 | 1726 | if (generate) |
a406f566 MM |
1727 | emit_constant_insn |
1728 | (cond, | |
1729 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
1730 | gen_rtx_IOR |
1731 | (mode, | |
1732 | gen_rtx_LSHIFTRT (mode, source, | |
1733 | GEN_INT (i)), | |
1734 | source))); | |
e2c671ba RE |
1735 | return insns + 1; |
1736 | } | |
1737 | } | |
1738 | } | |
1739 | break; | |
1740 | ||
1741 | case IOR: | |
1742 | case XOR: | |
7b64da89 RE |
1743 | /* If we have IOR or XOR, and the constant can be loaded in a |
1744 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
1745 | then this can be done in two instructions instead of 3-4. */ |
1746 | if (subtargets | |
d499463f | 1747 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 1748 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 1749 | { |
5895f793 | 1750 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1751 | { |
2b835d68 RE |
1752 | if (generate) |
1753 | { | |
1754 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 1755 | |
a406f566 MM |
1756 | emit_constant_insn (cond, |
1757 | gen_rtx_SET (VOIDmode, sub, | |
1758 | GEN_INT (val))); | |
1759 | emit_constant_insn (cond, | |
1760 | gen_rtx_SET (VOIDmode, target, | |
1761 | gen_rtx_fmt_ee (code, mode, | |
1762 | source, sub))); | |
2b835d68 | 1763 | } |
e2c671ba RE |
1764 | return 2; |
1765 | } | |
1766 | } | |
1767 | ||
1768 | if (code == XOR) | |
1769 | break; | |
1770 | ||
1771 | if (set_sign_bit_copies > 8 | |
1772 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
1773 | { | |
2b835d68 RE |
1774 | if (generate) |
1775 | { | |
1776 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1777 | rtx shift = GEN_INT (set_sign_bit_copies); | |
1778 | ||
a406f566 MM |
1779 | emit_constant_insn |
1780 | (cond, | |
1781 | gen_rtx_SET (VOIDmode, sub, | |
1782 | gen_rtx_NOT (mode, | |
1783 | gen_rtx_ASHIFT (mode, | |
1784 | source, | |
1785 | shift)))); | |
1786 | emit_constant_insn | |
1787 | (cond, | |
1788 | gen_rtx_SET (VOIDmode, target, | |
1789 | gen_rtx_NOT (mode, | |
1790 | gen_rtx_LSHIFTRT (mode, sub, | |
1791 | shift)))); | |
2b835d68 | 1792 | } |
e2c671ba RE |
1793 | return 2; |
1794 | } | |
1795 | ||
1796 | if (set_zero_bit_copies > 8 | |
1797 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
1798 | { | |
2b835d68 RE |
1799 | if (generate) |
1800 | { | |
1801 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
1802 | rtx shift = GEN_INT (set_zero_bit_copies); | |
1803 | ||
a406f566 MM |
1804 | emit_constant_insn |
1805 | (cond, | |
1806 | gen_rtx_SET (VOIDmode, sub, | |
1807 | gen_rtx_NOT (mode, | |
1808 | gen_rtx_LSHIFTRT (mode, | |
1809 | source, | |
1810 | shift)))); | |
1811 | emit_constant_insn | |
1812 | (cond, | |
1813 | gen_rtx_SET (VOIDmode, target, | |
1814 | gen_rtx_NOT (mode, | |
1815 | gen_rtx_ASHIFT (mode, sub, | |
1816 | shift)))); | |
2b835d68 | 1817 | } |
e2c671ba RE |
1818 | return 2; |
1819 | } | |
1820 | ||
5895f793 | 1821 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 1822 | { |
2b835d68 RE |
1823 | if (generate) |
1824 | { | |
1825 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
1826 | emit_constant_insn (cond, |
1827 | gen_rtx_SET (VOIDmode, sub, | |
1828 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
1829 | source = sub; |
1830 | if (subtargets) | |
1831 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
1832 | emit_constant_insn (cond, |
1833 | gen_rtx_SET (VOIDmode, sub, | |
1834 | gen_rtx_AND (mode, source, | |
1835 | GEN_INT (temp1)))); | |
1836 | emit_constant_insn (cond, | |
1837 | gen_rtx_SET (VOIDmode, target, | |
1838 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 1839 | } |
e2c671ba RE |
1840 | return 3; |
1841 | } | |
1842 | break; | |
1843 | ||
1844 | case AND: | |
1845 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
1846 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
1847 | { | |
30cf4896 | 1848 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 1849 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 1850 | & 0xffffffff); |
e2c671ba | 1851 | |
30cf4896 | 1852 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1853 | { |
2b835d68 RE |
1854 | if (generate) |
1855 | { | |
d499463f | 1856 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
1857 | insns = arm_gen_constant (AND, mode, cond, |
1858 | remainder | shift_mask, | |
d499463f RE |
1859 | new_src, source, subtargets, 1); |
1860 | source = new_src; | |
2b835d68 RE |
1861 | } |
1862 | else | |
d499463f RE |
1863 | { |
1864 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
1865 | insns = arm_gen_constant (AND, mode, cond, |
1866 | remainder | shift_mask, | |
d499463f RE |
1867 | targ, source, subtargets, 0); |
1868 | } | |
2b835d68 RE |
1869 | } |
1870 | ||
1871 | if (generate) | |
1872 | { | |
d499463f RE |
1873 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1874 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
1875 | ||
1876 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
1877 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
1878 | } |
1879 | ||
e2c671ba RE |
1880 | return insns + 2; |
1881 | } | |
1882 | ||
1883 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
1884 | { | |
1885 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
e2c671ba | 1886 | |
30cf4896 | 1887 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 1888 | { |
2b835d68 RE |
1889 | if (generate) |
1890 | { | |
d499463f RE |
1891 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1892 | ||
a406f566 MM |
1893 | insns = arm_gen_constant (AND, mode, cond, |
1894 | remainder | shift_mask, | |
d499463f RE |
1895 | new_src, source, subtargets, 1); |
1896 | source = new_src; | |
2b835d68 RE |
1897 | } |
1898 | else | |
d499463f RE |
1899 | { |
1900 | rtx targ = subtargets ? NULL_RTX : target; | |
1901 | ||
a406f566 MM |
1902 | insns = arm_gen_constant (AND, mode, cond, |
1903 | remainder | shift_mask, | |
d499463f RE |
1904 | targ, source, subtargets, 0); |
1905 | } | |
2b835d68 RE |
1906 | } |
1907 | ||
1908 | if (generate) | |
1909 | { | |
d499463f RE |
1910 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
1911 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
1912 | ||
1913 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
1914 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
1915 | } |
1916 | ||
e2c671ba RE |
1917 | return insns + 2; |
1918 | } | |
1919 | ||
1920 | break; | |
1921 | ||
1922 | default: | |
1923 | break; | |
1924 | } | |
1925 | ||
1926 | for (i = 0; i < 32; i++) | |
1927 | if (remainder & (1 << i)) | |
1928 | num_bits_set++; | |
1929 | ||
1930 | if (code == AND || (can_invert && num_bits_set > 16)) | |
30cf4896 | 1931 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 1932 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 1933 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
1934 | else |
1935 | { | |
1936 | can_invert = 0; | |
1937 | can_negate = 0; | |
1938 | } | |
1939 | ||
1940 | /* Now try and find a way of doing the job in either two or three | |
1941 | instructions. | |
1942 | We start by looking for the largest block of zeros that are aligned on | |
1943 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
1944 | top of the word when we drop off the bottom. | |
6354dc9b | 1945 | In the worst case this code should produce no more than four insns. */ |
e2c671ba RE |
1946 | { |
1947 | int best_start = 0; | |
1948 | int best_consecutive_zeros = 0; | |
1949 | ||
1950 | for (i = 0; i < 32; i += 2) | |
1951 | { | |
1952 | int consecutive_zeros = 0; | |
1953 | ||
5895f793 | 1954 | if (!(remainder & (3 << i))) |
e2c671ba | 1955 | { |
5895f793 | 1956 | while ((i < 32) && !(remainder & (3 << i))) |
e2c671ba RE |
1957 | { |
1958 | consecutive_zeros += 2; | |
1959 | i += 2; | |
1960 | } | |
1961 | if (consecutive_zeros > best_consecutive_zeros) | |
1962 | { | |
1963 | best_consecutive_zeros = consecutive_zeros; | |
1964 | best_start = i - consecutive_zeros; | |
1965 | } | |
1966 | i -= 2; | |
1967 | } | |
1968 | } | |
1969 | ||
ceebdb09 PB |
1970 | /* So long as it won't require any more insns to do so, it's |
1971 | desirable to emit a small constant (in bits 0...9) in the last | |
1972 | insn. This way there is more chance that it can be combined with | |
1973 | a later addressing insn to form a pre-indexed load or store | |
1974 | operation. Consider: | |
1975 | ||
1976 | *((volatile int *)0xe0000100) = 1; | |
1977 | *((volatile int *)0xe0000110) = 2; | |
1978 | ||
1979 | We want this to wind up as: | |
1980 | ||
1981 | mov rA, #0xe0000000 | |
1982 | mov rB, #1 | |
1983 | str rB, [rA, #0x100] | |
1984 | mov rB, #2 | |
1985 | str rB, [rA, #0x110] | |
1986 | ||
1987 | rather than having to synthesize both large constants from scratch. | |
1988 | ||
1989 | Therefore, we calculate how many insns would be required to emit | |
1990 | the constant starting from `best_start', and also starting from | |
1991 | zero (ie with bit 31 first to be output). If `best_start' doesn't | |
1992 | yield a shorter sequence, we may as well use zero. */ | |
1993 | if (best_start != 0 | |
1994 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
1995 | && (count_insns_for_constant (remainder, 0) <= | |
1996 | count_insns_for_constant (remainder, best_start))) | |
1997 | best_start = 0; | |
1998 | ||
1999 | /* Now start emitting the insns. */ | |
e2c671ba RE |
2000 | i = best_start; |
2001 | do | |
2002 | { | |
2003 | int end; | |
2004 | ||
2005 | if (i <= 0) | |
2006 | i += 32; | |
2007 | if (remainder & (3 << (i - 2))) | |
2008 | { | |
2009 | end = i - 8; | |
2010 | if (end < 0) | |
2011 | end += 32; | |
2012 | temp1 = remainder & ((0x0ff << end) | |
2013 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2014 | remainder &= ~temp1; | |
2015 | ||
d499463f | 2016 | if (generate) |
e2c671ba | 2017 | { |
9503f3d1 RH |
2018 | rtx new_src, temp1_rtx; |
2019 | ||
2020 | if (code == SET || code == MINUS) | |
2021 | { | |
2022 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 2023 | if (can_invert && code != MINUS) |
9503f3d1 RH |
2024 | temp1 = ~temp1; |
2025 | } | |
2026 | else | |
2027 | { | |
96ae8197 | 2028 | if (remainder && subtargets) |
9503f3d1 | 2029 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
2030 | else |
2031 | new_src = target; | |
9503f3d1 RH |
2032 | if (can_invert) |
2033 | temp1 = ~temp1; | |
2034 | else if (can_negate) | |
2035 | temp1 = -temp1; | |
2036 | } | |
2037 | ||
2038 | temp1 = trunc_int_for_mode (temp1, mode); | |
2039 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
2040 | |
2041 | if (code == SET) | |
9503f3d1 | 2042 | ; |
d499463f | 2043 | else if (code == MINUS) |
9503f3d1 | 2044 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 2045 | else |
9503f3d1 RH |
2046 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
2047 | ||
a406f566 MM |
2048 | emit_constant_insn (cond, |
2049 | gen_rtx_SET (VOIDmode, new_src, | |
2050 | temp1_rtx)); | |
d499463f | 2051 | source = new_src; |
e2c671ba RE |
2052 | } |
2053 | ||
d499463f RE |
2054 | if (code == SET) |
2055 | { | |
2056 | can_invert = 0; | |
2057 | code = PLUS; | |
2058 | } | |
2059 | else if (code == MINUS) | |
2060 | code = PLUS; | |
2061 | ||
e2c671ba | 2062 | insns++; |
e2c671ba RE |
2063 | i -= 6; |
2064 | } | |
2065 | i -= 2; | |
1d6e90ac NC |
2066 | } |
2067 | while (remainder); | |
e2c671ba | 2068 | } |
1d6e90ac | 2069 | |
e2c671ba RE |
2070 | return insns; |
2071 | } | |
2072 | ||
bd9c7e23 RE |
2073 | /* Canonicalize a comparison so that we are more likely to recognize it. |
2074 | This can be done for a few constant compares, where we can make the | |
2075 | immediate value easier to load. */ | |
1d6e90ac | 2076 | |
bd9c7e23 | 2077 | enum rtx_code |
e32bac5b | 2078 | arm_canonicalize_comparison (enum rtx_code code, rtx * op1) |
bd9c7e23 | 2079 | { |
ad076f4e | 2080 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
bd9c7e23 RE |
2081 | |
2082 | switch (code) | |
2083 | { | |
2084 | case EQ: | |
2085 | case NE: | |
2086 | return code; | |
2087 | ||
2088 | case GT: | |
2089 | case LE: | |
30cf4896 | 2090 | if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) |
5895f793 | 2091 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 2092 | { |
5895f793 | 2093 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
2094 | return code == GT ? GE : LT; |
2095 | } | |
2096 | break; | |
2097 | ||
2098 | case GE: | |
2099 | case LT: | |
30cf4896 | 2100 | if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) |
5895f793 | 2101 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 2102 | { |
5895f793 | 2103 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
2104 | return code == GE ? GT : LE; |
2105 | } | |
2106 | break; | |
2107 | ||
2108 | case GTU: | |
2109 | case LEU: | |
30cf4896 | 2110 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 2111 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
2112 | { |
2113 | *op1 = GEN_INT (i + 1); | |
2114 | return code == GTU ? GEU : LTU; | |
2115 | } | |
2116 | break; | |
2117 | ||
2118 | case GEU: | |
2119 | case LTU: | |
2120 | if (i != 0 | |
5895f793 | 2121 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
2122 | { |
2123 | *op1 = GEN_INT (i - 1); | |
2124 | return code == GEU ? GTU : LEU; | |
2125 | } | |
2126 | break; | |
2127 | ||
2128 | default: | |
2129 | abort (); | |
2130 | } | |
2131 | ||
2132 | return code; | |
2133 | } | |
bd9c7e23 | 2134 | |
d4453b7a PB |
2135 | |
2136 | /* Define how to find the value returned by a function. */ | |
2137 | ||
2138 | rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED) | |
2139 | { | |
2140 | enum machine_mode mode; | |
2141 | int unsignedp ATTRIBUTE_UNUSED; | |
2142 | rtx r ATTRIBUTE_UNUSED; | |
2143 | ||
2144 | ||
2145 | mode = TYPE_MODE (type); | |
2146 | /* Promote integer types. */ | |
2147 | if (INTEGRAL_TYPE_P (type)) | |
2148 | PROMOTE_FUNCTION_MODE (mode, unsignedp, type); | |
2149 | return LIBCALL_VALUE(mode); | |
2150 | } | |
2151 | ||
2152 | ||
f5a1b0d2 NC |
2153 | /* Decide whether a type should be returned in memory (true) |
2154 | or in a register (false). This is called by the macro | |
2155 | RETURN_IN_MEMORY. */ | |
2b835d68 | 2156 | int |
e32bac5b | 2157 | arm_return_in_memory (tree type) |
2b835d68 | 2158 | { |
dc0ba55a JT |
2159 | HOST_WIDE_INT size; |
2160 | ||
5895f793 | 2161 | if (!AGGREGATE_TYPE_P (type)) |
9e291dbe | 2162 | /* All simple types are returned in registers. */ |
d7d01975 | 2163 | return 0; |
dc0ba55a JT |
2164 | |
2165 | size = int_size_in_bytes (type); | |
2166 | ||
5848830f | 2167 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 2168 | { |
5848830f | 2169 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
2170 | larger than a word (or are variable size). */ |
2171 | return (size < 0 || size > UNITS_PER_WORD); | |
2172 | } | |
d5b7b3ae | 2173 | |
6bc82793 | 2174 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
2175 | ARM and Thumb compilers, which always return aggregates in memory. */ |
2176 | #ifndef ARM_WINCE | |
e529bd42 NC |
2177 | /* All structures/unions bigger than one word are returned in memory. |
2178 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 2179 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 2180 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 2181 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 2182 | return 1; |
d5b7b3ae | 2183 | |
d7d01975 | 2184 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
2185 | { |
2186 | tree field; | |
2187 | ||
3a2ea258 RE |
2188 | /* For a struct the APCS says that we only return in a register |
2189 | if the type is 'integer like' and every addressable element | |
2190 | has an offset of zero. For practical purposes this means | |
2191 | that the structure can have at most one non bit-field element | |
2192 | and that this element must be the first one in the structure. */ | |
2193 | ||
f5a1b0d2 NC |
2194 | /* Find the first field, ignoring non FIELD_DECL things which will |
2195 | have been created by C++. */ | |
2196 | for (field = TYPE_FIELDS (type); | |
2197 | field && TREE_CODE (field) != FIELD_DECL; | |
2198 | field = TREE_CHAIN (field)) | |
2199 | continue; | |
2200 | ||
2201 | if (field == NULL) | |
9e291dbe | 2202 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 2203 | |
d5b7b3ae RE |
2204 | /* Check that the first field is valid for returning in a register. */ |
2205 | ||
2206 | /* ... Floats are not allowed */ | |
9e291dbe | 2207 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
2208 | return 1; |
2209 | ||
d5b7b3ae RE |
2210 | /* ... Aggregates that are not themselves valid for returning in |
2211 | a register are not allowed. */ | |
9e291dbe | 2212 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
3a2ea258 | 2213 | return 1; |
6f7ebcbb | 2214 | |
3a2ea258 RE |
2215 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
2216 | since they are not addressable. */ | |
f5a1b0d2 NC |
2217 | for (field = TREE_CHAIN (field); |
2218 | field; | |
2219 | field = TREE_CHAIN (field)) | |
2220 | { | |
2221 | if (TREE_CODE (field) != FIELD_DECL) | |
2222 | continue; | |
2223 | ||
5895f793 | 2224 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
2225 | return 1; |
2226 | } | |
2b835d68 RE |
2227 | |
2228 | return 0; | |
2229 | } | |
d7d01975 NC |
2230 | |
2231 | if (TREE_CODE (type) == UNION_TYPE) | |
2b835d68 RE |
2232 | { |
2233 | tree field; | |
2234 | ||
2235 | /* Unions can be returned in registers if every element is | |
2236 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
2237 | for (field = TYPE_FIELDS (type); |
2238 | field; | |
2239 | field = TREE_CHAIN (field)) | |
2b835d68 | 2240 | { |
f5a1b0d2 NC |
2241 | if (TREE_CODE (field) != FIELD_DECL) |
2242 | continue; | |
2243 | ||
6cc8c0b3 NC |
2244 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
2245 | return 1; | |
2246 | ||
f5a1b0d2 | 2247 | if (RETURN_IN_MEMORY (TREE_TYPE (field))) |
2b835d68 RE |
2248 | return 1; |
2249 | } | |
f5a1b0d2 | 2250 | |
2b835d68 RE |
2251 | return 0; |
2252 | } | |
d5b7b3ae | 2253 | #endif /* not ARM_WINCE */ |
f5a1b0d2 | 2254 | |
d5b7b3ae | 2255 | /* Return all other types in memory. */ |
2b835d68 RE |
2256 | return 1; |
2257 | } | |
2258 | ||
d6b4baa4 | 2259 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
2260 | |
2261 | int | |
e32bac5b | 2262 | arm_float_words_big_endian (void) |
3717da94 | 2263 | { |
9b66ebb1 | 2264 | if (TARGET_MAVERICK) |
9b6b54e2 | 2265 | return 0; |
3717da94 JT |
2266 | |
2267 | /* For FPA, float words are always big-endian. For VFP, floats words | |
2268 | follow the memory system mode. */ | |
2269 | ||
9b66ebb1 | 2270 | if (TARGET_FPA) |
3717da94 | 2271 | { |
3717da94 JT |
2272 | return 1; |
2273 | } | |
2274 | ||
2275 | if (TARGET_VFP) | |
2276 | return (TARGET_BIG_END ? 1 : 0); | |
2277 | ||
2278 | return 1; | |
2279 | } | |
2280 | ||
82e9d970 PB |
2281 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
2282 | for a call to a function whose data type is FNTYPE. | |
2283 | For a library call, FNTYPE is NULL. */ | |
2284 | void | |
e32bac5b RE |
2285 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
2286 | rtx libname ATTRIBUTE_UNUSED, | |
2287 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
2288 | { |
2289 | /* On the ARM, the offset starts at 0. */ | |
61f71b34 | 2290 | pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0); |
5a9335ef | 2291 | pcum->iwmmxt_nregs = 0; |
5848830f | 2292 | pcum->can_split = true; |
c27ba912 | 2293 | |
82e9d970 PB |
2294 | pcum->call_cookie = CALL_NORMAL; |
2295 | ||
2296 | if (TARGET_LONG_CALLS) | |
2297 | pcum->call_cookie = CALL_LONG; | |
2298 | ||
2299 | /* Check for long call/short call attributes. The attributes | |
2300 | override any command line option. */ | |
2301 | if (fntype) | |
2302 | { | |
2303 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) | |
2304 | pcum->call_cookie = CALL_SHORT; | |
2305 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) | |
2306 | pcum->call_cookie = CALL_LONG; | |
2307 | } | |
5a9335ef NC |
2308 | |
2309 | /* Varargs vectors are treated the same as long long. | |
2310 | named_count avoids having to change the way arm handles 'named' */ | |
2311 | pcum->named_count = 0; | |
2312 | pcum->nargs = 0; | |
2313 | ||
2314 | if (TARGET_REALLY_IWMMXT && fntype) | |
2315 | { | |
2316 | tree fn_arg; | |
2317 | ||
2318 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
2319 | fn_arg; | |
2320 | fn_arg = TREE_CHAIN (fn_arg)) | |
2321 | pcum->named_count += 1; | |
2322 | ||
2323 | if (! pcum->named_count) | |
2324 | pcum->named_count = INT_MAX; | |
2325 | } | |
82e9d970 PB |
2326 | } |
2327 | ||
5848830f PB |
2328 | |
2329 | /* Return true if mode/type need doubleword alignment. */ | |
2330 | bool | |
2331 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
2332 | { | |
65a939f7 PB |
2333 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
2334 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
2335 | } |
2336 | ||
2337 | ||
82e9d970 PB |
2338 | /* Determine where to put an argument to a function. |
2339 | Value is zero to push the argument on the stack, | |
2340 | or a hard register in which to store the argument. | |
2341 | ||
2342 | MODE is the argument's machine mode. | |
2343 | TYPE is the data type of the argument (as a tree). | |
2344 | This is null for libcalls where that information may | |
2345 | not be available. | |
2346 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
2347 | the preceding args and about the function being called. | |
2348 | NAMED is nonzero if this argument is a named parameter | |
2349 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 2350 | |
82e9d970 | 2351 | rtx |
e32bac5b | 2352 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 2353 | tree type, int named) |
82e9d970 | 2354 | { |
5848830f PB |
2355 | int nregs; |
2356 | ||
2357 | /* Varargs vectors are treated the same as long long. | |
2358 | named_count avoids having to change the way arm handles 'named' */ | |
2359 | if (TARGET_IWMMXT_ABI | |
2360 | && VECTOR_MODE_SUPPORTED_P (mode) | |
2361 | && pcum->named_count > pcum->nargs + 1) | |
5a9335ef | 2362 | { |
5848830f PB |
2363 | if (pcum->iwmmxt_nregs <= 9) |
2364 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
2365 | else | |
5a9335ef | 2366 | { |
5848830f PB |
2367 | pcum->can_split = false; |
2368 | return NULL_RTX; | |
5a9335ef | 2369 | } |
5a9335ef NC |
2370 | } |
2371 | ||
5848830f PB |
2372 | /* Put doubleword aligned quantities in even register pairs. */ |
2373 | if (pcum->nregs & 1 | |
2374 | && ARM_DOUBLEWORD_ALIGN | |
2375 | && arm_needs_doubleword_align (mode, type)) | |
2376 | pcum->nregs++; | |
2377 | ||
82e9d970 PB |
2378 | if (mode == VOIDmode) |
2379 | /* Compute operand 2 of the call insn. */ | |
2380 | return GEN_INT (pcum->call_cookie); | |
5848830f | 2381 | |
666c27b9 | 2382 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
2383 | args were allocated to regs. For args passed by reference we only count |
2384 | the reference pointer. */ | |
2385 | if (pcum->can_split) | |
2386 | nregs = 1; | |
2387 | else | |
2388 | nregs = ARM_NUM_REGS2 (mode, type); | |
2389 | ||
2390 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 PB |
2391 | return NULL_RTX; |
2392 | ||
2393 | return gen_rtx_REG (mode, pcum->nregs); | |
2394 | } | |
1741620c JD |
2395 | |
2396 | /* Variable sized types are passed by reference. This is a GCC | |
2397 | extension to the ARM ABI. */ | |
2398 | ||
2399 | int | |
e32bac5b RE |
2400 | arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, |
2401 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
2402 | tree type, int named ATTRIBUTE_UNUSED) | |
1741620c JD |
2403 | { |
2404 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
2405 | } | |
2406 | ||
2407 | /* Implement va_arg. */ | |
2408 | ||
2409 | rtx | |
e32bac5b | 2410 | arm_va_arg (tree valist, tree type) |
1741620c | 2411 | { |
5848830f PB |
2412 | int align; |
2413 | ||
1741620c JD |
2414 | /* Variable sized types are passed by reference. */ |
2415 | if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) | |
2416 | { | |
2417 | rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type)); | |
2418 | return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr)); | |
2419 | } | |
2420 | ||
5848830f PB |
2421 | align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type); |
2422 | if (align > PARM_BOUNDARY) | |
5a9335ef | 2423 | { |
5848830f | 2424 | tree mask; |
5a9335ef NC |
2425 | tree t; |
2426 | ||
2427 | /* Maintain 64-bit alignment of the valist pointer by | |
093354e0 | 2428 | constructing: valist = ((valist + (8 - 1)) & -8). */ |
5848830f PB |
2429 | mask = build_int_2 (- (align / BITS_PER_UNIT), -1); |
2430 | t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0); | |
5a9335ef | 2431 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t); |
5848830f | 2432 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask); |
5a9335ef NC |
2433 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); |
2434 | TREE_SIDE_EFFECTS (t) = 1; | |
2435 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
2436 | ||
f1ba665b | 2437 | /* This is to stop the combine pass optimizing |
5a9335ef NC |
2438 | away the alignment adjustment. */ |
2439 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
2440 | } | |
2441 | ||
1741620c JD |
2442 | return std_expand_builtin_va_arg (valist, type); |
2443 | } | |
82e9d970 | 2444 | \f |
c27ba912 DM |
2445 | /* Encode the current state of the #pragma [no_]long_calls. */ |
2446 | typedef enum | |
82e9d970 | 2447 | { |
c27ba912 DM |
2448 | OFF, /* No #pramgma [no_]long_calls is in effect. */ |
2449 | LONG, /* #pragma long_calls is in effect. */ | |
2450 | SHORT /* #pragma no_long_calls is in effect. */ | |
2451 | } arm_pragma_enum; | |
82e9d970 | 2452 | |
c27ba912 | 2453 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 2454 | |
8b97c5f8 | 2455 | void |
e32bac5b | 2456 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 2457 | { |
8b97c5f8 ZW |
2458 | arm_pragma_long_calls = LONG; |
2459 | } | |
2460 | ||
2461 | void | |
e32bac5b | 2462 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2463 | { |
2464 | arm_pragma_long_calls = SHORT; | |
2465 | } | |
2466 | ||
2467 | void | |
e32bac5b | 2468 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
2469 | { |
2470 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
2471 | } |
2472 | \f | |
91d231cb JM |
2473 | /* Table of machine attributes. */ |
2474 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 2475 | { |
91d231cb | 2476 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
2477 | /* Function calls made to this symbol must be done indirectly, because |
2478 | it may lie outside of the 26 bit addressing range of a normal function | |
2479 | call. */ | |
91d231cb | 2480 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
2481 | /* Whereas these functions are always known to reside within the 26 bit |
2482 | addressing range. */ | |
91d231cb | 2483 | { "short_call", 0, 0, false, true, true, NULL }, |
6d3d9133 | 2484 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
2485 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
2486 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
2487 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2488 | #ifdef ARM_PE | |
2489 | /* ARM/PE has three new attributes: | |
2490 | interfacearm - ? | |
2491 | dllexport - for exporting a function/variable that will live in a dll | |
2492 | dllimport - for importing a function/variable from a dll | |
2493 | ||
2494 | Microsoft allows multiple declspecs in one __declspec, separating | |
2495 | them with spaces. We do NOT support this. Instead, use __declspec | |
2496 | multiple times. | |
2497 | */ | |
2498 | { "dllimport", 0, 0, true, false, false, NULL }, | |
2499 | { "dllexport", 0, 0, true, false, false, NULL }, | |
2500 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
2501 | #endif | |
2502 | { NULL, 0, 0, false, false, false, NULL } | |
2503 | }; | |
6d3d9133 | 2504 | |
91d231cb JM |
2505 | /* Handle an attribute requiring a FUNCTION_DECL; |
2506 | arguments as in struct attribute_spec.handler. */ | |
2507 | static tree | |
e32bac5b RE |
2508 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
2509 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
2510 | { |
2511 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2512 | { | |
2513 | warning ("`%s' attribute only applies to functions", | |
2514 | IDENTIFIER_POINTER (name)); | |
2515 | *no_add_attrs = true; | |
2516 | } | |
2517 | ||
2518 | return NULL_TREE; | |
2519 | } | |
2520 | ||
2521 | /* Handle an "interrupt" or "isr" attribute; | |
2522 | arguments as in struct attribute_spec.handler. */ | |
2523 | static tree | |
e32bac5b RE |
2524 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
2525 | bool *no_add_attrs) | |
91d231cb JM |
2526 | { |
2527 | if (DECL_P (*node)) | |
2528 | { | |
2529 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
2530 | { | |
2531 | warning ("`%s' attribute only applies to functions", | |
2532 | IDENTIFIER_POINTER (name)); | |
2533 | *no_add_attrs = true; | |
2534 | } | |
2535 | /* FIXME: the argument if any is checked for type attributes; | |
2536 | should it be checked for decl ones? */ | |
2537 | } | |
2538 | else | |
2539 | { | |
2540 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
2541 | || TREE_CODE (*node) == METHOD_TYPE) | |
2542 | { | |
2543 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
2544 | { | |
2545 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2546 | *no_add_attrs = true; | |
2547 | } | |
2548 | } | |
2549 | else if (TREE_CODE (*node) == POINTER_TYPE | |
2550 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
2551 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
2552 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
2553 | { | |
2554 | *node = build_type_copy (*node); | |
1d6e90ac NC |
2555 | TREE_TYPE (*node) = build_type_attribute_variant |
2556 | (TREE_TYPE (*node), | |
2557 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
2558 | *no_add_attrs = true; |
2559 | } | |
2560 | else | |
2561 | { | |
2562 | /* Possibly pass this attribute on from the type to a decl. */ | |
2563 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
2564 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
2565 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
2566 | { | |
2567 | *no_add_attrs = true; | |
2568 | return tree_cons (name, args, NULL_TREE); | |
2569 | } | |
2570 | else | |
2571 | { | |
2572 | warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); | |
2573 | } | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | return NULL_TREE; | |
82e9d970 PB |
2578 | } |
2579 | ||
2580 | /* Return 0 if the attributes for two types are incompatible, 1 if they | |
2581 | are compatible, and 2 if they are nearly compatible (which causes a | |
2582 | warning to be generated). */ | |
8d8e52be | 2583 | static int |
e32bac5b | 2584 | arm_comp_type_attributes (tree type1, tree type2) |
82e9d970 | 2585 | { |
1cb8d58a | 2586 | int l1, l2, s1, s2; |
bd7fc26f | 2587 | |
82e9d970 PB |
2588 | /* Check for mismatch of non-default calling convention. */ |
2589 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
2590 | return 1; | |
2591 | ||
2592 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
2593 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
2594 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
2595 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
2596 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
2597 | |
2598 | /* Only bother to check if an attribute is defined. */ | |
2599 | if (l1 | l2 | s1 | s2) | |
2600 | { | |
2601 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 2602 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 2603 | return 0; |
82e9d970 | 2604 | |
bd7fc26f NC |
2605 | /* Disallow mixed attributes. */ |
2606 | if ((l1 & s2) || (l2 & s1)) | |
2607 | return 0; | |
2608 | } | |
2609 | ||
6d3d9133 NC |
2610 | /* Check for mismatched ISR attribute. */ |
2611 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
2612 | if (! l1) | |
2613 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
2614 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
2615 | if (! l2) | |
2616 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
2617 | if (l1 != l2) | |
2618 | return 0; | |
2619 | ||
bd7fc26f | 2620 | return 1; |
82e9d970 PB |
2621 | } |
2622 | ||
c27ba912 DM |
2623 | /* Encode long_call or short_call attribute by prefixing |
2624 | symbol name in DECL with a special character FLAG. */ | |
2625 | void | |
e32bac5b | 2626 | arm_encode_call_attribute (tree decl, int flag) |
c27ba912 | 2627 | { |
3cce094d | 2628 | const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); |
6354dc9b | 2629 | int len = strlen (str); |
d19fb8e3 | 2630 | char * newstr; |
c27ba912 | 2631 | |
c27ba912 DM |
2632 | /* Do not allow weak functions to be treated as short call. */ |
2633 | if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) | |
2634 | return; | |
c27ba912 | 2635 | |
520a57c8 ZW |
2636 | newstr = alloca (len + 2); |
2637 | newstr[0] = flag; | |
2638 | strcpy (newstr + 1, str); | |
c27ba912 | 2639 | |
6d3d9133 | 2640 | newstr = (char *) ggc_alloc_string (newstr, len + 1); |
c27ba912 DM |
2641 | XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; |
2642 | } | |
2643 | ||
2644 | /* Assigns default attributes to newly defined type. This is used to | |
2645 | set short_call/long_call attributes for function types of | |
2646 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 2647 | static void |
e32bac5b | 2648 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
2649 | { |
2650 | /* Add __attribute__ ((long_call)) to all functions, when | |
2651 | inside #pragma long_calls or __attribute__ ((short_call)), | |
2652 | when inside #pragma no_long_calls. */ | |
2653 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
2654 | { | |
2655 | tree type_attr_list, attr_name; | |
2656 | type_attr_list = TYPE_ATTRIBUTES (type); | |
2657 | ||
2658 | if (arm_pragma_long_calls == LONG) | |
2659 | attr_name = get_identifier ("long_call"); | |
2660 | else if (arm_pragma_long_calls == SHORT) | |
2661 | attr_name = get_identifier ("short_call"); | |
2662 | else | |
2663 | return; | |
2664 | ||
2665 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
2666 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
2667 | } | |
2668 | } | |
2669 | \f | |
2670 | /* Return 1 if the operand is a SYMBOL_REF for a function known to be | |
6bc82793 | 2671 | defined within the current compilation unit. If this cannot be |
c27ba912 DM |
2672 | determined, then 0 is returned. */ |
2673 | static int | |
e32bac5b | 2674 | current_file_function_operand (rtx sym_ref) |
c27ba912 DM |
2675 | { |
2676 | /* This is a bit of a fib. A function will have a short call flag | |
2677 | applied to its name if it has the short call attribute, or it has | |
2678 | already been defined within the current compilation unit. */ | |
2679 | if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) | |
2680 | return 1; | |
2681 | ||
6d77b53e | 2682 | /* The current function is always defined within the current compilation |
d6a7951f JM |
2683 | unit. if it s a weak definition however, then this may not be the real |
2684 | definition of the function, and so we have to say no. */ | |
c27ba912 | 2685 | if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) |
5895f793 | 2686 | && !DECL_WEAK (current_function_decl)) |
c27ba912 DM |
2687 | return 1; |
2688 | ||
2689 | /* We cannot make the determination - default to returning 0. */ | |
2690 | return 0; | |
2691 | } | |
2692 | ||
825dda42 | 2693 | /* Return nonzero if a 32 bit "long_call" should be generated for |
c27ba912 DM |
2694 | this call. We generate a long_call if the function: |
2695 | ||
2696 | a. has an __attribute__((long call)) | |
2697 | or b. is within the scope of a #pragma long_calls | |
2698 | or c. the -mlong-calls command line switch has been specified | |
2699 | ||
2700 | However we do not generate a long call if the function: | |
2701 | ||
2702 | d. has an __attribute__ ((short_call)) | |
2703 | or e. is inside the scope of a #pragma no_long_calls | |
2704 | or f. has an __attribute__ ((section)) | |
2705 | or g. is defined within the current compilation unit. | |
2706 | ||
2707 | This function will be called by C fragments contained in the machine | |
2708 | description file. CALL_REF and CALL_COOKIE correspond to the matched | |
2709 | rtl operands. CALL_SYMBOL is used to distinguish between | |
2710 | two different callers of the function. It is set to 1 in the | |
2711 | "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" | |
2712 | and "call_value" patterns. This is because of the difference in the | |
2713 | SYM_REFs passed by these patterns. */ | |
2714 | int | |
e32bac5b | 2715 | arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) |
c27ba912 | 2716 | { |
5895f793 | 2717 | if (!call_symbol) |
c27ba912 DM |
2718 | { |
2719 | if (GET_CODE (sym_ref) != MEM) | |
2720 | return 0; | |
2721 | ||
2722 | sym_ref = XEXP (sym_ref, 0); | |
2723 | } | |
2724 | ||
2725 | if (GET_CODE (sym_ref) != SYMBOL_REF) | |
2726 | return 0; | |
2727 | ||
2728 | if (call_cookie & CALL_SHORT) | |
2729 | return 0; | |
2730 | ||
2731 | if (TARGET_LONG_CALLS && flag_function_sections) | |
2732 | return 1; | |
2733 | ||
87e27392 | 2734 | if (current_file_function_operand (sym_ref)) |
c27ba912 DM |
2735 | return 0; |
2736 | ||
2737 | return (call_cookie & CALL_LONG) | |
2738 | || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) | |
2739 | || TARGET_LONG_CALLS; | |
2740 | } | |
f99fce0c | 2741 | |
825dda42 | 2742 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 2743 | static bool |
e32bac5b | 2744 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c RE |
2745 | { |
2746 | int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; | |
2747 | ||
5a9335ef NC |
2748 | if (cfun->machine->sibcall_blocked) |
2749 | return false; | |
2750 | ||
f99fce0c RE |
2751 | /* Never tailcall something for which we have no decl, or if we |
2752 | are in Thumb mode. */ | |
2753 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 2754 | return false; |
f99fce0c RE |
2755 | |
2756 | /* Get the calling method. */ | |
2757 | if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2758 | call_type = CALL_SHORT; | |
2759 | else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) | |
2760 | call_type = CALL_LONG; | |
2761 | ||
2762 | /* Cannot tail-call to long calls, since these are out of range of | |
2763 | a branch instruction. However, if not compiling PIC, we know | |
2764 | we can reach the symbol if it is in this compilation unit. */ | |
5895f793 | 2765 | if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) |
4977bab6 | 2766 | return false; |
f99fce0c RE |
2767 | |
2768 | /* If we are interworking and the function is not declared static | |
2769 | then we can't tail-call it unless we know that it exists in this | |
2770 | compilation unit (since it might be a Thumb routine). */ | |
5895f793 | 2771 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 2772 | return false; |
f99fce0c | 2773 | |
6d3d9133 NC |
2774 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
2775 | if (IS_INTERRUPT (arm_current_func_type ())) | |
4977bab6 | 2776 | return false; |
6d3d9133 | 2777 | |
f99fce0c | 2778 | /* Everything else is ok. */ |
4977bab6 | 2779 | return true; |
f99fce0c RE |
2780 | } |
2781 | ||
82e9d970 | 2782 | \f |
6b990f6b RE |
2783 | /* Addressing mode support functions. */ |
2784 | ||
0b4be7de | 2785 | /* Return nonzero if X is a legitimate immediate operand when compiling |
6b990f6b | 2786 | for PIC. */ |
32de079a | 2787 | int |
e32bac5b | 2788 | legitimate_pic_operand_p (rtx x) |
32de079a | 2789 | { |
d5b7b3ae RE |
2790 | if (CONSTANT_P (x) |
2791 | && flag_pic | |
32de079a RE |
2792 | && (GET_CODE (x) == SYMBOL_REF |
2793 | || (GET_CODE (x) == CONST | |
2794 | && GET_CODE (XEXP (x, 0)) == PLUS | |
2795 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) | |
2796 | return 0; | |
2797 | ||
2798 | return 1; | |
2799 | } | |
2800 | ||
2801 | rtx | |
e32bac5b | 2802 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 2803 | { |
a3c48721 RE |
2804 | if (GET_CODE (orig) == SYMBOL_REF |
2805 | || GET_CODE (orig) == LABEL_REF) | |
32de079a | 2806 | { |
5f37d07c | 2807 | #ifndef AOF_ASSEMBLER |
32de079a | 2808 | rtx pic_ref, address; |
5f37d07c | 2809 | #endif |
32de079a RE |
2810 | rtx insn; |
2811 | int subregs = 0; | |
2812 | ||
2813 | if (reg == 0) | |
2814 | { | |
893f3d5b | 2815 | if (no_new_pseudos) |
32de079a RE |
2816 | abort (); |
2817 | else | |
2818 | reg = gen_reg_rtx (Pmode); | |
2819 | ||
2820 | subregs = 1; | |
2821 | } | |
2822 | ||
2823 | #ifdef AOF_ASSEMBLER | |
2824 | /* The AOF assembler can generate relocations for these directly, and | |
6354dc9b | 2825 | understands that the PIC register has to be added into the offset. */ |
32de079a RE |
2826 | insn = emit_insn (gen_pic_load_addr_based (reg, orig)); |
2827 | #else | |
2828 | if (subregs) | |
2829 | address = gen_reg_rtx (Pmode); | |
2830 | else | |
2831 | address = reg; | |
2832 | ||
4bec9f7d NC |
2833 | if (TARGET_ARM) |
2834 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
2835 | else | |
2836 | emit_insn (gen_pic_load_addr_thumb (address, orig)); | |
32de079a | 2837 | |
14f583b8 PB |
2838 | if ((GET_CODE (orig) == LABEL_REF |
2839 | || (GET_CODE (orig) == SYMBOL_REF && | |
94428622 | 2840 | SYMBOL_REF_LOCAL_P (orig))) |
14f583b8 | 2841 | && NEED_GOT_RELOC) |
a3c48721 RE |
2842 | pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); |
2843 | else | |
2844 | { | |
2845 | pic_ref = gen_rtx_MEM (Pmode, | |
2846 | gen_rtx_PLUS (Pmode, pic_offset_table_rtx, | |
2847 | address)); | |
2848 | RTX_UNCHANGING_P (pic_ref) = 1; | |
2849 | } | |
2850 | ||
32de079a RE |
2851 | insn = emit_move_insn (reg, pic_ref); |
2852 | #endif | |
2853 | current_function_uses_pic_offset_table = 1; | |
2854 | /* Put a REG_EQUAL note on this insn, so that it can be optimized | |
2855 | by loop. */ | |
43cffd11 RE |
2856 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, |
2857 | REG_NOTES (insn)); | |
32de079a RE |
2858 | return reg; |
2859 | } | |
2860 | else if (GET_CODE (orig) == CONST) | |
2861 | { | |
2862 | rtx base, offset; | |
2863 | ||
2864 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
2865 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
2866 | return orig; | |
2867 | ||
2868 | if (reg == 0) | |
2869 | { | |
893f3d5b | 2870 | if (no_new_pseudos) |
32de079a RE |
2871 | abort (); |
2872 | else | |
2873 | reg = gen_reg_rtx (Pmode); | |
2874 | } | |
2875 | ||
2876 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
2877 | { | |
2878 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
2879 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
2880 | base == reg ? 0 : reg); | |
2881 | } | |
2882 | else | |
2883 | abort (); | |
2884 | ||
2885 | if (GET_CODE (offset) == CONST_INT) | |
2886 | { | |
2887 | /* The base register doesn't really matter, we only want to | |
2888 | test the index for the appropriate mode. */ | |
1e1ab407 | 2889 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b RE |
2890 | { |
2891 | if (!no_new_pseudos) | |
2892 | offset = force_reg (Pmode, offset); | |
2893 | else | |
2894 | abort (); | |
2895 | } | |
32de079a | 2896 | |
32de079a | 2897 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 2898 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
2899 | } |
2900 | ||
2901 | if (GET_MODE_SIZE (mode) > 4 | |
2902 | && (GET_MODE_CLASS (mode) == MODE_INT | |
2903 | || TARGET_SOFT_FLOAT)) | |
2904 | { | |
2905 | emit_insn (gen_addsi3 (reg, base, offset)); | |
2906 | return reg; | |
2907 | } | |
2908 | ||
43cffd11 | 2909 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 2910 | } |
32de079a RE |
2911 | |
2912 | return orig; | |
2913 | } | |
2914 | ||
c1163e75 PB |
2915 | /* Generate code to load the PIC register. PROLOGUE is true if |
2916 | called from arm_expand_prologue (in which case we want the | |
2917 | generated insns at the start of the function); false if called | |
2918 | by an exception receiver that needs the PIC register reloaded | |
2919 | (in which case the insns are just dumped at the current location). */ | |
32de079a | 2920 | void |
e32bac5b | 2921 | arm_finalize_pic (int prologue ATTRIBUTE_UNUSED) |
32de079a RE |
2922 | { |
2923 | #ifndef AOF_ASSEMBLER | |
c1163e75 | 2924 | rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; |
32de079a RE |
2925 | rtx global_offset_table; |
2926 | ||
ed0e6530 | 2927 | if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
2928 | return; |
2929 | ||
5895f793 | 2930 | if (!flag_pic) |
32de079a RE |
2931 | abort (); |
2932 | ||
2933 | start_sequence (); | |
2934 | l1 = gen_label_rtx (); | |
2935 | ||
43cffd11 | 2936 | global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); |
dfa08768 | 2937 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
d5b7b3ae RE |
2938 | addition, on the Thumb it is 'dot + 4'. */ |
2939 | pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); | |
84306176 PB |
2940 | if (GOT_PCREL) |
2941 | pic_tmp2 = gen_rtx_CONST (VOIDmode, | |
43cffd11 | 2942 | gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); |
84306176 PB |
2943 | else |
2944 | pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); | |
43cffd11 RE |
2945 | |
2946 | pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); | |
f5a1b0d2 | 2947 | |
d5b7b3ae | 2948 | if (TARGET_ARM) |
4bec9f7d NC |
2949 | { |
2950 | emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); | |
2951 | emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); | |
2952 | } | |
d5b7b3ae | 2953 | else |
4bec9f7d NC |
2954 | { |
2955 | emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); | |
2956 | emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); | |
2957 | } | |
32de079a | 2958 | |
2f937369 | 2959 | seq = get_insns (); |
32de079a | 2960 | end_sequence (); |
c1163e75 PB |
2961 | if (prologue) |
2962 | emit_insn_after (seq, get_insns ()); | |
2963 | else | |
2964 | emit_insn (seq); | |
32de079a RE |
2965 | |
2966 | /* Need to emit this whether or not we obey regdecls, | |
2967 | since setjmp/longjmp can cause life info to screw up. */ | |
43cffd11 | 2968 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
32de079a RE |
2969 | #endif /* AOF_ASSEMBLER */ |
2970 | } | |
2971 | ||
6b990f6b RE |
2972 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
2973 | static int | |
e32bac5b | 2974 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
2975 | { |
2976 | int regno; | |
2977 | ||
2978 | if (GET_CODE (x) != REG) | |
2979 | return 0; | |
2980 | ||
2981 | regno = REGNO (x); | |
2982 | ||
2983 | if (strict_p) | |
2984 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
2985 | ||
2986 | return (regno <= LAST_ARM_REGNUM | |
2987 | || regno >= FIRST_PSEUDO_REGISTER | |
2988 | || regno == FRAME_POINTER_REGNUM | |
2989 | || regno == ARG_POINTER_REGNUM); | |
2990 | } | |
2991 | ||
2992 | /* Return nonzero if X is a valid ARM state address operand. */ | |
2993 | int | |
1e1ab407 RE |
2994 | arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
2995 | int strict_p) | |
6b990f6b | 2996 | { |
fdd695fd PB |
2997 | bool use_ldrd; |
2998 | enum rtx_code code = GET_CODE (x); | |
2999 | ||
6b990f6b RE |
3000 | if (arm_address_register_rtx_p (x, strict_p)) |
3001 | return 1; | |
3002 | ||
fdd695fd PB |
3003 | use_ldrd = (TARGET_LDRD |
3004 | && (mode == DImode | |
3005 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
3006 | ||
3007 | if (code == POST_INC || code == PRE_DEC | |
3008 | || ((code == PRE_INC || code == POST_DEC) | |
3009 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
3010 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
3011 | ||
fdd695fd | 3012 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
3013 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
3014 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 3015 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
3016 | { |
3017 | rtx addend = XEXP (XEXP (x, 1), 1); | |
3018 | ||
3019 | /* Don't allow ldrd post increment by register becuase it's hard | |
3020 | to fixup invalid register choices. */ | |
3021 | if (use_ldrd | |
3022 | && GET_CODE (x) == POST_MODIFY | |
3023 | && GET_CODE (addend) == REG) | |
3024 | return 0; | |
3025 | ||
3026 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
3027 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
3028 | } | |
6b990f6b RE |
3029 | |
3030 | /* After reload constants split into minipools will have addresses | |
3031 | from a LABEL_REF. */ | |
0bfb39ef | 3032 | else if (reload_completed |
fdd695fd PB |
3033 | && (code == LABEL_REF |
3034 | || (code == CONST | |
6b990f6b RE |
3035 | && GET_CODE (XEXP (x, 0)) == PLUS |
3036 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3037 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3038 | return 1; | |
3039 | ||
3040 | else if (mode == TImode) | |
3041 | return 0; | |
3042 | ||
fdd695fd | 3043 | else if (code == PLUS) |
6b990f6b RE |
3044 | { |
3045 | rtx xop0 = XEXP (x, 0); | |
3046 | rtx xop1 = XEXP (x, 1); | |
3047 | ||
3048 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3049 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
6b990f6b | 3050 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 3051 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
3052 | } |
3053 | ||
3054 | #if 0 | |
3055 | /* Reload currently can't handle MINUS, so disable this for now */ | |
3056 | else if (GET_CODE (x) == MINUS) | |
3057 | { | |
3058 | rtx xop0 = XEXP (x, 0); | |
3059 | rtx xop1 = XEXP (x, 1); | |
3060 | ||
3061 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 3062 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
3063 | } |
3064 | #endif | |
3065 | ||
3066 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 3067 | && code == SYMBOL_REF |
6b990f6b RE |
3068 | && CONSTANT_POOL_ADDRESS_P (x) |
3069 | && ! (flag_pic | |
3070 | && symbol_mentioned_p (get_pool_constant (x)))) | |
3071 | return 1; | |
3072 | ||
6b990f6b RE |
3073 | return 0; |
3074 | } | |
3075 | ||
3076 | /* Return nonzero if INDEX is valid for an address index operand in | |
3077 | ARM state. */ | |
3078 | static int | |
1e1ab407 RE |
3079 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
3080 | int strict_p) | |
6b990f6b RE |
3081 | { |
3082 | HOST_WIDE_INT range; | |
3083 | enum rtx_code code = GET_CODE (index); | |
3084 | ||
778ebdd9 PB |
3085 | /* Standard coprocessor addressing modes. */ |
3086 | if (TARGET_HARD_FLOAT | |
3087 | && (TARGET_FPA || TARGET_MAVERICK) | |
3088 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3089 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
3090 | return (code == CONST_INT && INTVAL (index) < 1024 |
3091 | && INTVAL (index) > -1024 | |
3092 | && (INTVAL (index) & 3) == 0); | |
3093 | ||
5a9335ef NC |
3094 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
3095 | return (code == CONST_INT | |
3657dc3e PB |
3096 | && INTVAL (index) < 1024 |
3097 | && INTVAL (index) > -1024 | |
3098 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 3099 | |
fdd695fd PB |
3100 | if (arm_address_register_rtx_p (index, strict_p) |
3101 | && (GET_MODE_SIZE (mode) <= 4)) | |
3102 | return 1; | |
3103 | ||
3104 | if (mode == DImode || mode == DFmode) | |
3105 | { | |
3106 | if (code == CONST_INT) | |
3107 | { | |
3108 | HOST_WIDE_INT val = INTVAL (index); | |
3109 | ||
3110 | if (TARGET_LDRD) | |
3111 | return val > -256 && val < 256; | |
3112 | else | |
3113 | return val == 4 || val == -4 || val == -8; | |
3114 | } | |
3115 | ||
3116 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
3117 | } | |
3118 | ||
6b990f6b | 3119 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
3120 | && ! (arm_arch4 |
3121 | && (mode == HImode | |
3122 | || (mode == QImode && outer == SIGN_EXTEND)))) | |
6b990f6b | 3123 | { |
1e1ab407 RE |
3124 | if (code == MULT) |
3125 | { | |
3126 | rtx xiop0 = XEXP (index, 0); | |
3127 | rtx xiop1 = XEXP (index, 1); | |
3128 | ||
3129 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
3130 | && power_of_two_operand (xiop1, SImode)) | |
3131 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
3132 | && power_of_two_operand (xiop0, SImode))); | |
3133 | } | |
3134 | else if (code == LSHIFTRT || code == ASHIFTRT | |
3135 | || code == ASHIFT || code == ROTATERT) | |
3136 | { | |
3137 | rtx op = XEXP (index, 1); | |
6b990f6b | 3138 | |
1e1ab407 RE |
3139 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
3140 | && GET_CODE (op) == CONST_INT | |
3141 | && INTVAL (op) > 0 | |
3142 | && INTVAL (op) <= 31); | |
3143 | } | |
6b990f6b RE |
3144 | } |
3145 | ||
1e1ab407 RE |
3146 | /* For ARM v4 we may be doing a sign-extend operation during the |
3147 | load. */ | |
e1471c91 | 3148 | if (arm_arch4) |
1e1ab407 RE |
3149 | { |
3150 | if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) | |
3151 | range = 256; | |
3152 | else | |
3153 | range = 4096; | |
3154 | } | |
e1471c91 RE |
3155 | else |
3156 | range = (mode == HImode) ? 4095 : 4096; | |
6b990f6b RE |
3157 | |
3158 | return (code == CONST_INT | |
3159 | && INTVAL (index) < range | |
3160 | && INTVAL (index) > -range); | |
76a318e9 RE |
3161 | } |
3162 | ||
edf7cee8 | 3163 | /* Return nonzero if X is valid as a Thumb state base register. */ |
76a318e9 | 3164 | static int |
e32bac5b | 3165 | thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
3166 | { |
3167 | int regno; | |
3168 | ||
3169 | if (GET_CODE (x) != REG) | |
3170 | return 0; | |
3171 | ||
3172 | regno = REGNO (x); | |
3173 | ||
3174 | if (strict_p) | |
3175 | return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); | |
3176 | ||
3177 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 3178 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
3179 | || regno == FRAME_POINTER_REGNUM |
3180 | || (GET_MODE_SIZE (mode) >= 4 | |
3181 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 3182 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
3183 | || x == hard_frame_pointer_rtx |
3184 | || x == arg_pointer_rtx))); | |
3185 | } | |
3186 | ||
3187 | /* Return nonzero if x is a legitimate index register. This is the case | |
3188 | for any base register that can access a QImode object. */ | |
3189 | inline static int | |
e32bac5b | 3190 | thumb_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 RE |
3191 | { |
3192 | return thumb_base_register_rtx_p (x, QImode, strict_p); | |
3193 | } | |
3194 | ||
3195 | /* Return nonzero if x is a legitimate Thumb-state address. | |
3196 | ||
3197 | The AP may be eliminated to either the SP or the FP, so we use the | |
3198 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
3199 | ||
3200 | ??? Verify whether the above is the right approach. | |
3201 | ||
3202 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
3203 | needs special handling also. | |
3204 | ||
3205 | ??? Look at how the mips16 port solves this problem. It probably uses | |
3206 | better ways to solve some of these problems. | |
3207 | ||
3208 | Although it is not incorrect, we don't accept QImode and HImode | |
3209 | addresses based on the frame pointer or arg pointer until the | |
3210 | reload pass starts. This is so that eliminating such addresses | |
3211 | into stack based ones won't produce impossible code. */ | |
3212 | int | |
e32bac5b | 3213 | thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
3214 | { |
3215 | /* ??? Not clear if this is right. Experiment. */ | |
3216 | if (GET_MODE_SIZE (mode) < 4 | |
3217 | && !(reload_in_progress || reload_completed) | |
3218 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
3219 | || reg_mentioned_p (arg_pointer_rtx, x) | |
3220 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
3221 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
3222 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
3223 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
3224 | return 0; | |
3225 | ||
3226 | /* Accept any base register. SP only in SImode or larger. */ | |
3227 | else if (thumb_base_register_rtx_p (x, mode, strict_p)) | |
3228 | return 1; | |
3229 | ||
18dbd950 | 3230 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
3231 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
3232 | && GET_CODE (x) == SYMBOL_REF | |
3233 | && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic) | |
3234 | return 1; | |
3235 | ||
18dbd950 | 3236 | /* This is PC relative data after arm_reorg runs. */ |
76a318e9 RE |
3237 | else if (GET_MODE_SIZE (mode) >= 4 && reload_completed |
3238 | && (GET_CODE (x) == LABEL_REF | |
3239 | || (GET_CODE (x) == CONST | |
3240 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3241 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
3242 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
3243 | return 1; | |
3244 | ||
3245 | /* Post-inc indexing only supported for SImode and larger. */ | |
3246 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
3247 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) | |
3248 | return 1; | |
3249 | ||
3250 | else if (GET_CODE (x) == PLUS) | |
3251 | { | |
3252 | /* REG+REG address can be any two index registers. */ | |
3253 | /* We disallow FRAME+REG addressing since we know that FRAME | |
3254 | will be replaced with STACK, and SP relative addressing only | |
3255 | permits SP+OFFSET. */ | |
3256 | if (GET_MODE_SIZE (mode) <= 4 | |
3257 | && XEXP (x, 0) != frame_pointer_rtx | |
3258 | && XEXP (x, 1) != frame_pointer_rtx | |
76a318e9 RE |
3259 | && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) |
3260 | && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
3261 | return 1; | |
3262 | ||
3263 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
3264 | else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) | |
3265 | || XEXP (x, 0) == arg_pointer_rtx) | |
3266 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3267 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
3268 | return 1; | |
3269 | ||
3270 | /* REG+const has 10 bit offset for SP, but only SImode and | |
3271 | larger is supported. */ | |
3272 | /* ??? Should probably check for DI/DFmode overflow here | |
3273 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
3274 | else if (GET_CODE (XEXP (x, 0)) == REG | |
3275 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
3276 | && GET_MODE_SIZE (mode) >= 4 | |
3277 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3278 | && INTVAL (XEXP (x, 1)) >= 0 | |
3279 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
3280 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
3281 | return 1; | |
3282 | ||
3283 | else if (GET_CODE (XEXP (x, 0)) == REG | |
3284 | && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM | |
3285 | && GET_MODE_SIZE (mode) >= 4 | |
3286 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3287 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
3288 | return 1; | |
3289 | } | |
3290 | ||
3291 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 3292 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
3293 | && GET_CODE (x) == SYMBOL_REF |
3294 | && CONSTANT_POOL_ADDRESS_P (x) | |
3295 | && !(flag_pic | |
3296 | && symbol_mentioned_p (get_pool_constant (x)))) | |
3297 | return 1; | |
3298 | ||
3299 | return 0; | |
3300 | } | |
3301 | ||
3302 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
3303 | instruction of mode MODE. */ | |
3304 | int | |
e32bac5b | 3305 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
3306 | { |
3307 | switch (GET_MODE_SIZE (mode)) | |
3308 | { | |
3309 | case 1: | |
3310 | return val >= 0 && val < 32; | |
3311 | ||
3312 | case 2: | |
3313 | return val >= 0 && val < 64 && (val & 1) == 0; | |
3314 | ||
3315 | default: | |
3316 | return (val >= 0 | |
3317 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
3318 | && (val & 3) == 0); | |
3319 | } | |
3320 | } | |
3321 | ||
ccf4d512 RE |
3322 | /* Try machine-dependent ways of modifying an illegitimate address |
3323 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 3324 | rtx |
e32bac5b | 3325 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 RE |
3326 | { |
3327 | if (GET_CODE (x) == PLUS) | |
3328 | { | |
3329 | rtx xop0 = XEXP (x, 0); | |
3330 | rtx xop1 = XEXP (x, 1); | |
3331 | ||
3332 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
3333 | xop0 = force_reg (SImode, xop0); | |
3334 | ||
3335 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
3336 | xop1 = force_reg (SImode, xop1); | |
3337 | ||
3338 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
3339 | && GET_CODE (xop1) == CONST_INT) | |
3340 | { | |
3341 | HOST_WIDE_INT n, low_n; | |
3342 | rtx base_reg, val; | |
3343 | n = INTVAL (xop1); | |
3344 | ||
9b66ebb1 PB |
3345 | /* VFP addressing modes actually allow greater offsets, but for |
3346 | now we just stick with the lowest common denominator. */ | |
3347 | if (mode == DImode | |
3348 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
3349 | { |
3350 | low_n = n & 0x0f; | |
3351 | n &= ~0x0f; | |
3352 | if (low_n > 4) | |
3353 | { | |
3354 | n += 16; | |
3355 | low_n -= 16; | |
3356 | } | |
3357 | } | |
3358 | else | |
3359 | { | |
3360 | low_n = ((mode) == TImode ? 0 | |
3361 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
3362 | n -= low_n; | |
3363 | } | |
3364 | ||
3365 | base_reg = gen_reg_rtx (SImode); | |
3366 | val = force_operand (gen_rtx_PLUS (SImode, xop0, | |
3367 | GEN_INT (n)), NULL_RTX); | |
3368 | emit_move_insn (base_reg, val); | |
3369 | x = (low_n == 0 ? base_reg | |
3370 | : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); | |
3371 | } | |
3372 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
3373 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
3374 | } | |
3375 | ||
3376 | /* XXX We don't allow MINUS any more -- see comment in | |
3377 | arm_legitimate_address_p (). */ | |
3378 | else if (GET_CODE (x) == MINUS) | |
3379 | { | |
3380 | rtx xop0 = XEXP (x, 0); | |
3381 | rtx xop1 = XEXP (x, 1); | |
3382 | ||
3383 | if (CONSTANT_P (xop0)) | |
3384 | xop0 = force_reg (SImode, xop0); | |
3385 | ||
3386 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
3387 | xop1 = force_reg (SImode, xop1); | |
3388 | ||
3389 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
3390 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
3391 | } | |
3392 | ||
3393 | if (flag_pic) | |
3394 | { | |
3395 | /* We need to find and carefully transform any SYMBOL and LABEL | |
3396 | references; so go back to the original address expression. */ | |
3397 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
3398 | ||
3399 | if (new_x != orig_x) | |
3400 | x = new_x; | |
3401 | } | |
3402 | ||
3403 | return x; | |
3404 | } | |
3405 | ||
6f5b4f3e RE |
3406 | |
3407 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
3408 | to be legitimate. If we find one, return the new, valid address. */ | |
3409 | rtx | |
3410 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
3411 | { | |
3412 | if (GET_CODE (x) == PLUS | |
3413 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3414 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
3415 | || INTVAL (XEXP (x, 1)) < 0)) | |
3416 | { | |
3417 | rtx xop0 = XEXP (x, 0); | |
3418 | rtx xop1 = XEXP (x, 1); | |
3419 | HOST_WIDE_INT offset = INTVAL (xop1); | |
3420 | ||
3421 | /* Try and fold the offset into a biasing of the base register and | |
3422 | then offsetting that. Don't do this when optimizing for space | |
3423 | since it can cause too many CSEs. */ | |
3424 | if (optimize_size && offset >= 0 | |
3425 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
3426 | { | |
3427 | HOST_WIDE_INT delta; | |
3428 | ||
3429 | if (offset >= 256) | |
3430 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
3431 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
3432 | delta = 31 * GET_MODE_SIZE (mode); | |
3433 | else | |
3434 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
3435 | ||
3436 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
3437 | NULL_RTX); | |
3438 | x = plus_constant (xop0, delta); | |
3439 | } | |
3440 | else if (offset < 0 && offset > -256) | |
3441 | /* Small negative offsets are best done with a subtract before the | |
3442 | dereference, forcing these into a register normally takes two | |
3443 | instructions. */ | |
3444 | x = force_operand (x, NULL_RTX); | |
3445 | else | |
3446 | { | |
3447 | /* For the remaining cases, force the constant into a register. */ | |
3448 | xop1 = force_reg (SImode, xop1); | |
3449 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
3450 | } | |
3451 | } | |
3452 | else if (GET_CODE (x) == PLUS | |
3453 | && s_register_operand (XEXP (x, 1), SImode) | |
3454 | && !s_register_operand (XEXP (x, 0), SImode)) | |
3455 | { | |
3456 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
3457 | ||
3458 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
3459 | } | |
3460 | ||
3461 | if (flag_pic) | |
3462 | { | |
3463 | /* We need to find and carefully transform any SYMBOL and LABEL | |
3464 | references; so go back to the original address expression. */ | |
3465 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
3466 | ||
3467 | if (new_x != orig_x) | |
3468 | x = new_x; | |
3469 | } | |
3470 | ||
3471 | return x; | |
3472 | } | |
3473 | ||
6b990f6b RE |
3474 | \f |
3475 | ||
e2c671ba RE |
3476 | #define REG_OR_SUBREG_REG(X) \ |
3477 | (GET_CODE (X) == REG \ | |
3478 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
3479 | ||
3480 | #define REG_OR_SUBREG_RTX(X) \ | |
3481 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
3482 | ||
d5b7b3ae RE |
3483 | #ifndef COSTS_N_INSNS |
3484 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
3485 | #endif | |
3c50106f | 3486 | static inline int |
9b66ebb1 | 3487 | thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
3488 | { |
3489 | enum machine_mode mode = GET_MODE (x); | |
e2c671ba | 3490 | |
9b66ebb1 | 3491 | switch (code) |
d5b7b3ae | 3492 | { |
9b66ebb1 PB |
3493 | case ASHIFT: |
3494 | case ASHIFTRT: | |
3495 | case LSHIFTRT: | |
3496 | case ROTATERT: | |
3497 | case PLUS: | |
3498 | case MINUS: | |
3499 | case COMPARE: | |
3500 | case NEG: | |
3501 | case NOT: | |
3502 | return COSTS_N_INSNS (1); | |
3503 | ||
3504 | case MULT: | |
3505 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3506 | { | |
3507 | int cycles = 0; | |
3508 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
d5b7b3ae | 3509 | |
9b66ebb1 | 3510 | while (i) |
d5b7b3ae | 3511 | { |
9b66ebb1 PB |
3512 | i >>= 2; |
3513 | cycles++; | |
3514 | } | |
3515 | return COSTS_N_INSNS (2) + cycles; | |
3516 | } | |
3517 | return COSTS_N_INSNS (1) + 16; | |
3518 | ||
3519 | case SET: | |
3520 | return (COSTS_N_INSNS (1) | |
3521 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
3522 | + GET_CODE (SET_DEST (x)) == MEM)); | |
3523 | ||
3524 | case CONST_INT: | |
3525 | if (outer == SET) | |
3526 | { | |
3527 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
3528 | return 0; | |
3529 | if (thumb_shiftable_const (INTVAL (x))) | |
3530 | return COSTS_N_INSNS (2); | |
3531 | return COSTS_N_INSNS (3); | |
3532 | } | |
3533 | else if ((outer == PLUS || outer == COMPARE) | |
3534 | && INTVAL (x) < 256 && INTVAL (x) > -256) | |
3535 | return 0; | |
3536 | else if (outer == AND | |
3537 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
3538 | return COSTS_N_INSNS (1); | |
3539 | else if (outer == ASHIFT || outer == ASHIFTRT | |
3540 | || outer == LSHIFTRT) | |
3541 | return 0; | |
3542 | return COSTS_N_INSNS (2); | |
3543 | ||
3544 | case CONST: | |
3545 | case CONST_DOUBLE: | |
3546 | case LABEL_REF: | |
3547 | case SYMBOL_REF: | |
3548 | return COSTS_N_INSNS (3); | |
3549 | ||
3550 | case UDIV: | |
3551 | case UMOD: | |
3552 | case DIV: | |
3553 | case MOD: | |
3554 | return 100; | |
d5b7b3ae | 3555 | |
9b66ebb1 PB |
3556 | case TRUNCATE: |
3557 | return 99; | |
d5b7b3ae | 3558 | |
9b66ebb1 PB |
3559 | case AND: |
3560 | case XOR: | |
3561 | case IOR: | |
ff482c8d | 3562 | /* XXX guess. */ |
9b66ebb1 | 3563 | return 8; |
d5b7b3ae | 3564 | |
9b66ebb1 PB |
3565 | case MEM: |
3566 | /* XXX another guess. */ | |
3567 | /* Memory costs quite a lot for the first word, but subsequent words | |
3568 | load at the equivalent of a single insn each. */ | |
3569 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
3570 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
3571 | ? 4 : 0)); | |
3572 | ||
3573 | case IF_THEN_ELSE: | |
ff482c8d | 3574 | /* XXX a guess. */ |
9b66ebb1 PB |
3575 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
3576 | return 14; | |
3577 | return 2; | |
3578 | ||
3579 | case ZERO_EXTEND: | |
3580 | /* XXX still guessing. */ | |
3581 | switch (GET_MODE (XEXP (x, 0))) | |
3582 | { | |
3583 | case QImode: | |
3584 | return (1 + (mode == DImode ? 4 : 0) | |
3585 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
d5b7b3ae | 3586 | |
9b66ebb1 PB |
3587 | case HImode: |
3588 | return (4 + (mode == DImode ? 4 : 0) | |
3589 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
d5b7b3ae | 3590 | |
9b66ebb1 PB |
3591 | case SImode: |
3592 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3593 | ||
d5b7b3ae RE |
3594 | default: |
3595 | return 99; | |
d5b7b3ae | 3596 | } |
9b66ebb1 PB |
3597 | |
3598 | default: | |
3599 | return 99; | |
d5b7b3ae | 3600 | } |
9b66ebb1 PB |
3601 | } |
3602 | ||
3603 | ||
3604 | /* Worker routine for arm_rtx_costs. */ | |
3605 | static inline int | |
3606 | arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) | |
3607 | { | |
3608 | enum machine_mode mode = GET_MODE (x); | |
3609 | enum rtx_code subcode; | |
3610 | int extra_cost; | |
3611 | ||
e2c671ba RE |
3612 | switch (code) |
3613 | { | |
3614 | case MEM: | |
3615 | /* Memory costs quite a lot for the first word, but subsequent words | |
3616 | load at the equivalent of a single insn each. */ | |
3617 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
48f6efae NC |
3618 | + (GET_CODE (x) == SYMBOL_REF |
3619 | && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); | |
e2c671ba RE |
3620 | |
3621 | case DIV: | |
3622 | case MOD: | |
b9c53150 RS |
3623 | case UDIV: |
3624 | case UMOD: | |
3625 | return optimize_size ? COSTS_N_INSNS (2) : 100; | |
e2c671ba RE |
3626 | |
3627 | case ROTATE: | |
3628 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
3629 | return 4; | |
3630 | /* Fall through */ | |
3631 | case ROTATERT: | |
3632 | if (mode != SImode) | |
3633 | return 8; | |
3634 | /* Fall through */ | |
3635 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
3636 | if (mode == DImode) | |
3637 | return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) | |
3638 | + ((GET_CODE (XEXP (x, 0)) == REG | |
3639 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3640 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3641 | ? 0 : 8)); | |
3642 | return (1 + ((GET_CODE (XEXP (x, 0)) == REG | |
3643 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
3644 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) | |
3645 | ? 0 : 4) | |
3646 | + ((GET_CODE (XEXP (x, 1)) == REG | |
3647 | || (GET_CODE (XEXP (x, 1)) == SUBREG | |
3648 | && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) | |
3649 | || (GET_CODE (XEXP (x, 1)) == CONST_INT)) | |
3650 | ? 0 : 4)); | |
3651 | ||
3652 | case MINUS: | |
3653 | if (mode == DImode) | |
3654 | return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) | |
3655 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3656 | || (GET_CODE (XEXP (x, 0)) == CONST_INT | |
3657 | && const_ok_for_arm (INTVAL (XEXP (x, 0))))) | |
3658 | ? 0 : 8)); | |
3659 | ||
3660 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3661 | return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3662 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 3663 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
3664 | ? 0 : 8) |
3665 | + ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3666 | || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
9b66ebb1 | 3667 | && arm_const_double_rtx (XEXP (x, 0)))) |
e2c671ba RE |
3668 | ? 0 : 8)); |
3669 | ||
3670 | if (((GET_CODE (XEXP (x, 0)) == CONST_INT | |
3671 | && const_ok_for_arm (INTVAL (XEXP (x, 0))) | |
3672 | && REG_OR_SUBREG_REG (XEXP (x, 1)))) | |
3673 | || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT | |
3674 | || subcode == ASHIFTRT || subcode == LSHIFTRT | |
3675 | || subcode == ROTATE || subcode == ROTATERT | |
3676 | || (subcode == MULT | |
3677 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
3678 | && ((INTVAL (XEXP (XEXP (x, 1), 1)) & | |
3679 | (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) | |
3680 | && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) | |
3681 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) | |
3682 | || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) | |
3683 | && REG_OR_SUBREG_REG (XEXP (x, 0)))) | |
3684 | return 1; | |
3685 | /* Fall through */ | |
3686 | ||
3687 | case PLUS: | |
3688 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3689 | return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3690 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3691 | || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
9b66ebb1 | 3692 | && arm_const_double_rtx (XEXP (x, 1)))) |
e2c671ba RE |
3693 | ? 0 : 8)); |
3694 | ||
3695 | /* Fall through */ | |
3696 | case AND: case XOR: case IOR: | |
3697 | extra_cost = 0; | |
3698 | ||
3699 | /* Normally the frame registers will be spilt into reg+const during | |
3700 | reload, so it is a bad idea to combine them with other instructions, | |
3701 | since then they might not be moved outside of loops. As a compromise | |
3702 | we allow integration with ops that have a constant as their second | |
3703 | operand. */ | |
3704 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3705 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
3706 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
3707 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
3708 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
3709 | extra_cost = 4; | |
3710 | ||
3711 | if (mode == DImode) | |
3712 | return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) | |
3713 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3714 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3715 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3716 | ? 0 : 8)); |
3717 | ||
3718 | if (REG_OR_SUBREG_REG (XEXP (x, 0))) | |
3719 | return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) | |
3720 | + ((REG_OR_SUBREG_REG (XEXP (x, 1)) | |
3721 | || (GET_CODE (XEXP (x, 1)) == CONST_INT | |
74bbc178 | 3722 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) |
e2c671ba RE |
3723 | ? 0 : 4)); |
3724 | ||
3725 | else if (REG_OR_SUBREG_REG (XEXP (x, 1))) | |
3726 | return (1 + extra_cost | |
3727 | + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT | |
3728 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
3729 | || subcode == ROTATE || subcode == ROTATERT | |
3730 | || (subcode == MULT | |
3731 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3732 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) & | |
ad076f4e | 3733 | (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) |
e2c671ba RE |
3734 | && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) |
3735 | && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) | |
ad076f4e | 3736 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) |
e2c671ba RE |
3737 | ? 0 : 4)); |
3738 | ||
3739 | return 8; | |
3740 | ||
3741 | case MULT: | |
9b66ebb1 PB |
3742 | /* This should have been handled by the CPU specific routines. */ |
3743 | abort (); | |
e2c671ba | 3744 | |
56636818 | 3745 | case TRUNCATE: |
9b66ebb1 | 3746 | if (arm_arch3m && mode == SImode |
56636818 JL |
3747 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
3748 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
3749 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
3750 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
3751 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
3752 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
3753 | return 8; | |
3754 | return 99; | |
3755 | ||
e2c671ba RE |
3756 | case NEG: |
3757 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
3758 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); | |
3759 | /* Fall through */ | |
3760 | case NOT: | |
3761 | if (mode == DImode) | |
3762 | return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3763 | ||
3764 | return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); | |
3765 | ||
3766 | case IF_THEN_ELSE: | |
3767 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
3768 | return 14; | |
3769 | return 2; | |
3770 | ||
3771 | case COMPARE: | |
3772 | return 1; | |
3773 | ||
3774 | case ABS: | |
3775 | return 4 + (mode == DImode ? 4 : 0); | |
3776 | ||
3777 | case SIGN_EXTEND: | |
3778 | if (GET_MODE (XEXP (x, 0)) == QImode) | |
3779 | return (4 + (mode == DImode ? 4 : 0) | |
3780 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3781 | /* Fall through */ | |
3782 | case ZERO_EXTEND: | |
3783 | switch (GET_MODE (XEXP (x, 0))) | |
3784 | { | |
3785 | case QImode: | |
3786 | return (1 + (mode == DImode ? 4 : 0) | |
3787 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3788 | ||
3789 | case HImode: | |
3790 | return (4 + (mode == DImode ? 4 : 0) | |
3791 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
3792 | ||
3793 | case SImode: | |
3794 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
ad076f4e | 3795 | |
5a9335ef NC |
3796 | case V8QImode: |
3797 | case V4HImode: | |
3798 | case V2SImode: | |
3799 | case V4QImode: | |
3800 | case V2HImode: | |
3801 | return 1; | |
3802 | ||
ad076f4e RE |
3803 | default: |
3804 | break; | |
e2c671ba RE |
3805 | } |
3806 | abort (); | |
3807 | ||
d5b7b3ae RE |
3808 | case CONST_INT: |
3809 | if (const_ok_for_arm (INTVAL (x))) | |
3810 | return outer == SET ? 2 : -1; | |
3811 | else if (outer == AND | |
5895f793 | 3812 | && const_ok_for_arm (~INTVAL (x))) |
d5b7b3ae RE |
3813 | return -1; |
3814 | else if ((outer == COMPARE | |
3815 | || outer == PLUS || outer == MINUS) | |
5895f793 | 3816 | && const_ok_for_arm (-INTVAL (x))) |
d5b7b3ae RE |
3817 | return -1; |
3818 | else | |
3819 | return 5; | |
3820 | ||
3821 | case CONST: | |
3822 | case LABEL_REF: | |
3823 | case SYMBOL_REF: | |
3824 | return 6; | |
3825 | ||
3826 | case CONST_DOUBLE: | |
9b66ebb1 | 3827 | if (arm_const_double_rtx (x)) |
d5b7b3ae RE |
3828 | return outer == SET ? 2 : -1; |
3829 | else if ((outer == COMPARE || outer == PLUS) | |
3b684012 | 3830 | && neg_const_double_rtx_ok_for_fpa (x)) |
d5b7b3ae RE |
3831 | return -1; |
3832 | return 7; | |
3833 | ||
e2c671ba RE |
3834 | default: |
3835 | return 99; | |
3836 | } | |
3837 | } | |
32de079a | 3838 | |
59b9a953 | 3839 | /* RTX costs for cores with a slow MUL implementation. */ |
9b66ebb1 | 3840 | |
3c50106f | 3841 | static bool |
9b66ebb1 | 3842 | arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f | 3843 | { |
9b66ebb1 PB |
3844 | enum machine_mode mode = GET_MODE (x); |
3845 | ||
3846 | if (TARGET_THUMB) | |
3847 | { | |
3848 | *total = thumb_rtx_costs (x, code, outer_code); | |
3849 | return true; | |
3850 | } | |
3851 | ||
3852 | switch (code) | |
3853 | { | |
3854 | case MULT: | |
3855 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3856 | || mode == DImode) | |
3857 | { | |
3858 | *total = 30; | |
3859 | return true; | |
3860 | } | |
3861 | ||
3862 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3863 | { | |
3864 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
3865 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
3866 | int cost, const_ok = const_ok_for_arm (i); | |
3867 | int j, booth_unit_size; | |
3868 | ||
3869 | /* Tune as appropriate. */ | |
3870 | cost = const_ok ? 4 : 8; | |
3871 | booth_unit_size = 2; | |
3872 | for (j = 0; i && j < 32; j += booth_unit_size) | |
3873 | { | |
3874 | i >>= booth_unit_size; | |
3875 | cost += 2; | |
3876 | } | |
3877 | ||
3878 | *total = cost; | |
3879 | return true; | |
3880 | } | |
3881 | ||
3882 | *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
3883 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
3884 | return true; | |
3885 | ||
3886 | default: | |
3887 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
3888 | return true; | |
3889 | } | |
3c50106f RH |
3890 | } |
3891 | ||
9b66ebb1 PB |
3892 | |
3893 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
3894 | ||
3895 | static bool | |
3896 | arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total) | |
3897 | { | |
3898 | enum machine_mode mode = GET_MODE (x); | |
3899 | ||
3900 | if (TARGET_THUMB) | |
3901 | { | |
3902 | *total = thumb_rtx_costs (x, code, outer_code); | |
3903 | return true; | |
3904 | } | |
3905 | ||
3906 | switch (code) | |
3907 | { | |
3908 | case MULT: | |
3909 | /* There is no point basing this on the tuning, since it is always the | |
3910 | fast variant if it exists at all. */ | |
3911 | if (mode == DImode | |
3912 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
3913 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
3914 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
3915 | { | |
3916 | *total = 8; | |
3917 | return true; | |
3918 | } | |
3919 | ||
3920 | ||
3921 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3922 | || mode == DImode) | |
3923 | { | |
3924 | *total = 30; | |
3925 | return true; | |
3926 | } | |
3927 | ||
3928 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3929 | { | |
3930 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
3931 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
3932 | int cost, const_ok = const_ok_for_arm (i); | |
3933 | int j, booth_unit_size; | |
3934 | ||
3935 | /* Tune as appropriate. */ | |
3936 | cost = const_ok ? 4 : 8; | |
3937 | booth_unit_size = 8; | |
3938 | for (j = 0; i && j < 32; j += booth_unit_size) | |
3939 | { | |
3940 | i >>= booth_unit_size; | |
3941 | cost += 2; | |
3942 | } | |
3943 | ||
3944 | *total = cost; | |
3945 | return true; | |
3946 | } | |
3947 | ||
3948 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
3949 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
3950 | return true; | |
3951 | ||
3952 | default: | |
3953 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
3954 | return true; | |
3955 | } | |
3956 | } | |
3957 | ||
3958 | ||
3959 | /* RTX cost for XScale CPUs. */ | |
3960 | ||
3961 | static bool | |
3962 | arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total) | |
3963 | { | |
3964 | enum machine_mode mode = GET_MODE (x); | |
3965 | ||
3966 | if (TARGET_THUMB) | |
3967 | { | |
3968 | *total = thumb_rtx_costs (x, code, outer_code); | |
3969 | return true; | |
3970 | } | |
3971 | ||
3972 | switch (code) | |
3973 | { | |
3974 | case MULT: | |
3975 | /* There is no point basing this on the tuning, since it is always the | |
3976 | fast variant if it exists at all. */ | |
3977 | if (mode == DImode | |
3978 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
3979 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
3980 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
3981 | { | |
3982 | *total = 8; | |
3983 | return true; | |
3984 | } | |
3985 | ||
3986 | ||
3987 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
3988 | || mode == DImode) | |
3989 | { | |
3990 | *total = 30; | |
3991 | return true; | |
3992 | } | |
3993 | ||
3994 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3995 | { | |
3996 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
3997 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
3998 | int cost, const_ok = const_ok_for_arm (i); | |
3999 | unsigned HOST_WIDE_INT masked_const; | |
4000 | ||
4001 | /* The cost will be related to two insns. | |
ff482c8d | 4002 | First a load of the constant (MOV or LDR), then a multiply. */ |
9b66ebb1 PB |
4003 | cost = 2; |
4004 | if (! const_ok) | |
4005 | cost += 1; /* LDR is probably more expensive because | |
ff482c8d | 4006 | of longer result latency. */ |
9b66ebb1 PB |
4007 | masked_const = i & 0xffff8000; |
4008 | if (masked_const != 0 && masked_const != 0xffff8000) | |
4009 | { | |
4010 | masked_const = i & 0xf8000000; | |
4011 | if (masked_const == 0 || masked_const == 0xf8000000) | |
4012 | cost += 1; | |
4013 | else | |
4014 | cost += 2; | |
4015 | } | |
4016 | *total = cost; | |
4017 | return true; | |
4018 | } | |
4019 | ||
4020 | *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) | |
4021 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); | |
4022 | return true; | |
4023 | ||
4024 | default: | |
4025 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
4026 | return true; | |
4027 | } | |
4028 | } | |
4029 | ||
4030 | ||
4031 | /* RTX costs for 9e (and later) cores. */ | |
4032 | ||
4033 | static bool | |
4034 | arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total) | |
4035 | { | |
4036 | enum machine_mode mode = GET_MODE (x); | |
4037 | int nonreg_cost; | |
4038 | int cost; | |
4039 | ||
4040 | if (TARGET_THUMB) | |
4041 | { | |
4042 | switch (code) | |
4043 | { | |
4044 | case MULT: | |
4045 | *total = COSTS_N_INSNS (3); | |
4046 | return true; | |
4047 | ||
4048 | default: | |
4049 | *total = thumb_rtx_costs (x, code, outer_code); | |
4050 | return true; | |
4051 | } | |
4052 | } | |
4053 | ||
4054 | switch (code) | |
4055 | { | |
4056 | case MULT: | |
4057 | /* There is no point basing this on the tuning, since it is always the | |
4058 | fast variant if it exists at all. */ | |
4059 | if (mode == DImode | |
4060 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
4061 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
4062 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
4063 | { | |
4064 | *total = 3; | |
4065 | return true; | |
4066 | } | |
4067 | ||
4068 | ||
4069 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
4070 | { | |
4071 | *total = 30; | |
4072 | return true; | |
4073 | } | |
4074 | if (mode == DImode) | |
4075 | { | |
4076 | cost = 7; | |
4077 | nonreg_cost = 8; | |
4078 | } | |
4079 | else | |
4080 | { | |
4081 | cost = 2; | |
4082 | nonreg_cost = 4; | |
4083 | } | |
4084 | ||
4085 | ||
4086 | *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost) | |
4087 | + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost); | |
4088 | return true; | |
4089 | ||
4090 | default: | |
4091 | *total = arm_rtx_costs_1 (x, code, outer_code); | |
4092 | return true; | |
4093 | } | |
4094 | } | |
dcefdf67 RH |
4095 | /* All address computations that can be done are free, but rtx cost returns |
4096 | the same for practically all of them. So we weight the different types | |
4097 | of address here in the order (most pref first): | |
d6b4baa4 | 4098 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
4099 | static inline int |
4100 | arm_arm_address_cost (rtx x) | |
4101 | { | |
4102 | enum rtx_code c = GET_CODE (x); | |
4103 | ||
4104 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
4105 | return 0; | |
4106 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
4107 | return 10; | |
4108 | ||
4109 | if (c == PLUS || c == MINUS) | |
4110 | { | |
d2b6eb76 ZW |
4111 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
4112 | return 2; | |
4113 | ||
ec8e098d | 4114 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
4115 | return 3; |
4116 | ||
4117 | return 4; | |
4118 | } | |
4119 | ||
4120 | return 6; | |
4121 | } | |
4122 | ||
4123 | static inline int | |
4124 | arm_thumb_address_cost (rtx x) | |
4125 | { | |
4126 | enum rtx_code c = GET_CODE (x); | |
4127 | ||
4128 | if (c == REG) | |
4129 | return 1; | |
4130 | if (c == PLUS | |
4131 | && GET_CODE (XEXP (x, 0)) == REG | |
4132 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4133 | return 1; | |
4134 | ||
4135 | return 2; | |
4136 | } | |
4137 | ||
dcefdf67 | 4138 | static int |
e32bac5b | 4139 | arm_address_cost (rtx x) |
dcefdf67 | 4140 | { |
d2b6eb76 | 4141 | return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 RH |
4142 | } |
4143 | ||
c237e94a | 4144 | static int |
e32bac5b | 4145 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
4146 | { |
4147 | rtx i_pat, d_pat; | |
4148 | ||
d19fb8e3 NC |
4149 | /* Some true dependencies can have a higher cost depending |
4150 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 4151 | if (arm_tune_xscale |
d19fb8e3 | 4152 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
4153 | && recog_memoized (insn) >= 0 |
4154 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
4155 | { |
4156 | int shift_opnum = get_attr_shift (insn); | |
4157 | enum attr_type attr_type = get_attr_type (dep); | |
4158 | ||
4159 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
4160 | operand for INSN. If we have a shifted input operand and the | |
4161 | instruction we depend on is another ALU instruction, then we may | |
4162 | have to account for an additional stall. */ | |
9b66ebb1 PB |
4163 | if (shift_opnum != 0 |
4164 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
4165 | { |
4166 | rtx shifted_operand; | |
4167 | int opno; | |
4168 | ||
4169 | /* Get the shifted operand. */ | |
4170 | extract_insn (insn); | |
4171 | shifted_operand = recog_data.operand[shift_opnum]; | |
4172 | ||
4173 | /* Iterate over all the operands in DEP. If we write an operand | |
4174 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
4175 | cost of this dependency. */ | |
4176 | extract_insn (dep); | |
4177 | preprocess_constraints (); | |
4178 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
4179 | { | |
4180 | /* We can ignore strict inputs. */ | |
4181 | if (recog_data.operand_type[opno] == OP_IN) | |
4182 | continue; | |
4183 | ||
4184 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
4185 | shifted_operand)) | |
4186 | return 2; | |
4187 | } | |
4188 | } | |
4189 | } | |
4190 | ||
6354dc9b | 4191 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
4192 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
4193 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
4194 | return 0; |
4195 | ||
d5b7b3ae RE |
4196 | /* Call insns don't incur a stall, even if they follow a load. */ |
4197 | if (REG_NOTE_KIND (link) == 0 | |
4198 | && GET_CODE (insn) == CALL_INSN) | |
4199 | return 1; | |
4200 | ||
32de079a RE |
4201 | if ((i_pat = single_set (insn)) != NULL |
4202 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
4203 | && (d_pat = single_set (dep)) != NULL | |
4204 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
4205 | { | |
48f6efae | 4206 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
4207 | /* This is a load after a store, there is no conflict if the load reads |
4208 | from a cached area. Assume that loads from the stack, and from the | |
4209 | constant pool are cached, and that others will miss. This is a | |
6354dc9b | 4210 | hack. */ |
32de079a | 4211 | |
48f6efae NC |
4212 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
4213 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
4214 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
4215 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 4216 | return 1; |
32de079a RE |
4217 | } |
4218 | ||
4219 | return cost; | |
4220 | } | |
4221 | ||
9b66ebb1 | 4222 | static int fp_consts_inited = 0; |
ff9940b0 | 4223 | |
9b66ebb1 PB |
4224 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
4225 | static const char * const strings_fp[8] = | |
62b10bbc | 4226 | { |
2b835d68 RE |
4227 | "0", "1", "2", "3", |
4228 | "4", "5", "0.5", "10" | |
4229 | }; | |
ff9940b0 | 4230 | |
9b66ebb1 | 4231 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
4232 | |
4233 | static void | |
9b66ebb1 | 4234 | init_fp_table (void) |
ff9940b0 RE |
4235 | { |
4236 | int i; | |
4237 | REAL_VALUE_TYPE r; | |
4238 | ||
9b66ebb1 PB |
4239 | if (TARGET_VFP) |
4240 | fp_consts_inited = 1; | |
4241 | else | |
4242 | fp_consts_inited = 8; | |
4243 | ||
4244 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 4245 | { |
9b66ebb1 PB |
4246 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
4247 | values_fp[i] = r; | |
ff9940b0 | 4248 | } |
ff9940b0 RE |
4249 | } |
4250 | ||
9b66ebb1 | 4251 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 4252 | int |
9b66ebb1 | 4253 | arm_const_double_rtx (rtx x) |
cce8749e | 4254 | { |
ff9940b0 RE |
4255 | REAL_VALUE_TYPE r; |
4256 | int i; | |
4257 | ||
9b66ebb1 PB |
4258 | if (!fp_consts_inited) |
4259 | init_fp_table (); | |
ff9940b0 RE |
4260 | |
4261 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
4262 | if (REAL_VALUE_MINUS_ZERO (r)) | |
4263 | return 0; | |
f3bb6135 | 4264 | |
9b66ebb1 PB |
4265 | for (i = 0; i < fp_consts_inited; i++) |
4266 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 4267 | return 1; |
f3bb6135 | 4268 | |
ff9940b0 | 4269 | return 0; |
f3bb6135 | 4270 | } |
ff9940b0 | 4271 | |
3b684012 | 4272 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 4273 | int |
e32bac5b | 4274 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
4275 | { |
4276 | REAL_VALUE_TYPE r; | |
4277 | int i; | |
4278 | ||
9b66ebb1 PB |
4279 | if (!fp_consts_inited) |
4280 | init_fp_table (); | |
ff9940b0 RE |
4281 | |
4282 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
4283 | r = REAL_VALUE_NEGATE (r); | |
4284 | if (REAL_VALUE_MINUS_ZERO (r)) | |
4285 | return 0; | |
f3bb6135 | 4286 | |
ff9940b0 | 4287 | for (i = 0; i < 8; i++) |
9b66ebb1 | 4288 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 4289 | return 1; |
f3bb6135 | 4290 | |
ff9940b0 | 4291 | return 0; |
f3bb6135 | 4292 | } |
cce8749e CH |
4293 | \f |
4294 | /* Predicates for `match_operand' and `match_operator'. */ | |
4295 | ||
ff9940b0 | 4296 | /* s_register_operand is the same as register_operand, but it doesn't accept |
56a38cec DE |
4297 | (SUBREG (MEM)...). |
4298 | ||
4299 | This function exists because at the time it was put in it led to better | |
4300 | code. SUBREG(MEM) always needs a reload in the places where | |
4301 | s_register_operand is used, and this seemed to lead to excessive | |
4302 | reloading. */ | |
ff9940b0 | 4303 | int |
e32bac5b | 4304 | s_register_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
4305 | { |
4306 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4307 | return 0; | |
4308 | ||
4309 | if (GET_CODE (op) == SUBREG) | |
f3bb6135 | 4310 | op = SUBREG_REG (op); |
ff9940b0 RE |
4311 | |
4312 | /* We don't consider registers whose class is NO_REGS | |
4313 | to be a register operand. */ | |
d5b7b3ae | 4314 | /* XXX might have to check for lo regs only for thumb ??? */ |
ff9940b0 RE |
4315 | return (GET_CODE (op) == REG |
4316 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
4317 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
4318 | } | |
4319 | ||
b0888988 RE |
4320 | /* A hard register operand (even before reload. */ |
4321 | int | |
e32bac5b | 4322 | arm_hard_register_operand (rtx op, enum machine_mode mode) |
b0888988 RE |
4323 | { |
4324 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4325 | return 0; | |
4326 | ||
4327 | return (GET_CODE (op) == REG | |
4328 | && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
4329 | } | |
4330 | ||
9b66ebb1 PB |
4331 | /* An arm register operand. */ |
4332 | int | |
4333 | arm_general_register_operand (rtx op, enum machine_mode mode) | |
4334 | { | |
4335 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4336 | return 0; | |
4337 | ||
4338 | if (GET_CODE (op) == SUBREG) | |
4339 | op = SUBREG_REG (op); | |
4340 | ||
4341 | return (GET_CODE (op) == REG | |
4342 | && (REGNO (op) <= LAST_ARM_REGNUM | |
4343 | || REGNO (op) >= FIRST_PSEUDO_REGISTER)); | |
4344 | } | |
4345 | ||
e2c671ba | 4346 | /* Only accept reg, subreg(reg), const_int. */ |
e2c671ba | 4347 | int |
e32bac5b | 4348 | reg_or_int_operand (rtx op, enum machine_mode mode) |
e2c671ba RE |
4349 | { |
4350 | if (GET_CODE (op) == CONST_INT) | |
4351 | return 1; | |
4352 | ||
4353 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4354 | return 0; | |
4355 | ||
4356 | if (GET_CODE (op) == SUBREG) | |
4357 | op = SUBREG_REG (op); | |
4358 | ||
4359 | /* We don't consider registers whose class is NO_REGS | |
4360 | to be a register operand. */ | |
4361 | return (GET_CODE (op) == REG | |
4362 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
4363 | || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); | |
4364 | } | |
4365 | ||
ff9940b0 | 4366 | /* Return 1 if OP is an item in memory, given that we are in reload. */ |
ff9940b0 | 4367 | int |
e32bac5b | 4368 | arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 RE |
4369 | { |
4370 | int regno = true_regnum (op); | |
4371 | ||
5895f793 | 4372 | return (!CONSTANT_P (op) |
ff9940b0 RE |
4373 | && (regno == -1 |
4374 | || (GET_CODE (op) == REG | |
4375 | && REGNO (op) >= FIRST_PSEUDO_REGISTER))); | |
4376 | } | |
4377 | ||
cce8749e | 4378 | /* Return TRUE for valid operands for the rhs of an ARM instruction. */ |
cce8749e | 4379 | int |
e32bac5b | 4380 | arm_rhs_operand (rtx op, enum machine_mode mode) |
cce8749e | 4381 | { |
ff9940b0 | 4382 | return (s_register_operand (op, mode) |
cce8749e | 4383 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); |
f3bb6135 | 4384 | } |
cce8749e | 4385 | |
1d6e90ac NC |
4386 | /* Return TRUE for valid operands for the |
4387 | rhs of an ARM instruction, or a load. */ | |
ff9940b0 | 4388 | int |
e32bac5b | 4389 | arm_rhsm_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
4390 | { |
4391 | return (s_register_operand (op, mode) | |
4392 | || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) | |
4393 | || memory_operand (op, mode)); | |
f3bb6135 | 4394 | } |
ff9940b0 RE |
4395 | |
4396 | /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a | |
4397 | constant that is valid when negated. */ | |
ff9940b0 | 4398 | int |
e32bac5b | 4399 | arm_add_operand (rtx op, enum machine_mode mode) |
ff9940b0 | 4400 | { |
d5b7b3ae RE |
4401 | if (TARGET_THUMB) |
4402 | return thumb_cmp_operand (op, mode); | |
4403 | ||
ff9940b0 RE |
4404 | return (s_register_operand (op, mode) |
4405 | || (GET_CODE (op) == CONST_INT | |
4406 | && (const_ok_for_arm (INTVAL (op)) | |
4407 | || const_ok_for_arm (-INTVAL (op))))); | |
f3bb6135 | 4408 | } |
ff9940b0 | 4409 | |
f9b9980e RE |
4410 | /* Return TRUE for valid ARM constants (or when valid if negated). */ |
4411 | int | |
91de08c3 | 4412 | arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f9b9980e RE |
4413 | { |
4414 | return (GET_CODE (op) == CONST_INT | |
4415 | && (const_ok_for_arm (INTVAL (op)) | |
4416 | || const_ok_for_arm (-INTVAL (op)))); | |
4417 | } | |
4418 | ||
ff9940b0 | 4419 | int |
e32bac5b | 4420 | arm_not_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
4421 | { |
4422 | return (s_register_operand (op, mode) | |
4423 | || (GET_CODE (op) == CONST_INT | |
4424 | && (const_ok_for_arm (INTVAL (op)) | |
4425 | || const_ok_for_arm (~INTVAL (op))))); | |
f3bb6135 | 4426 | } |
ff9940b0 | 4427 | |
5165176d RE |
4428 | /* Return TRUE if the operand is a memory reference which contains an |
4429 | offsettable address. */ | |
4430 | int | |
e32bac5b | 4431 | offsettable_memory_operand (rtx op, enum machine_mode mode) |
5165176d RE |
4432 | { |
4433 | if (mode == VOIDmode) | |
4434 | mode = GET_MODE (op); | |
4435 | ||
4436 | return (mode == GET_MODE (op) | |
4437 | && GET_CODE (op) == MEM | |
4438 | && offsettable_address_p (reload_completed | reload_in_progress, | |
4439 | mode, XEXP (op, 0))); | |
4440 | } | |
4441 | ||
4442 | /* Return TRUE if the operand is a memory reference which is, or can be | |
4443 | made word aligned by adjusting the offset. */ | |
4444 | int | |
e32bac5b | 4445 | alignable_memory_operand (rtx op, enum machine_mode mode) |
5165176d RE |
4446 | { |
4447 | rtx reg; | |
4448 | ||
4449 | if (mode == VOIDmode) | |
4450 | mode = GET_MODE (op); | |
4451 | ||
4452 | if (mode != GET_MODE (op) || GET_CODE (op) != MEM) | |
4453 | return 0; | |
4454 | ||
4455 | op = XEXP (op, 0); | |
4456 | ||
4457 | return ((GET_CODE (reg = op) == REG | |
4458 | || (GET_CODE (op) == SUBREG | |
4459 | && GET_CODE (reg = SUBREG_REG (op)) == REG) | |
4460 | || (GET_CODE (op) == PLUS | |
4461 | && GET_CODE (XEXP (op, 1)) == CONST_INT | |
4462 | && (GET_CODE (reg = XEXP (op, 0)) == REG | |
4463 | || (GET_CODE (XEXP (op, 0)) == SUBREG | |
4464 | && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) | |
bdb429a5 | 4465 | && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); |
5165176d RE |
4466 | } |
4467 | ||
b111229a RE |
4468 | /* Similar to s_register_operand, but does not allow hard integer |
4469 | registers. */ | |
4470 | int | |
e32bac5b | 4471 | f_register_operand (rtx op, enum machine_mode mode) |
b111229a RE |
4472 | { |
4473 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4474 | return 0; | |
4475 | ||
4476 | if (GET_CODE (op) == SUBREG) | |
4477 | op = SUBREG_REG (op); | |
4478 | ||
4479 | /* We don't consider registers whose class is NO_REGS | |
4480 | to be a register operand. */ | |
4481 | return (GET_CODE (op) == REG | |
4482 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
3b684012 | 4483 | || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); |
b111229a RE |
4484 | } |
4485 | ||
9b66ebb1 PB |
4486 | /* Return TRUE for valid operands for the rhs of an floating point insns. |
4487 | Allows regs or certain consts on FPA, just regs for everything else. */ | |
cce8749e | 4488 | int |
9b66ebb1 | 4489 | arm_float_rhs_operand (rtx op, enum machine_mode mode) |
cce8749e | 4490 | { |
ff9940b0 | 4491 | if (s_register_operand (op, mode)) |
f3bb6135 | 4492 | return TRUE; |
9ce71c6f BS |
4493 | |
4494 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4495 | return FALSE; | |
4496 | ||
9b66ebb1 PB |
4497 | if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE) |
4498 | return arm_const_double_rtx (op); | |
f3bb6135 RE |
4499 | |
4500 | return FALSE; | |
4501 | } | |
cce8749e | 4502 | |
ff9940b0 | 4503 | int |
9b66ebb1 | 4504 | arm_float_add_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
4505 | { |
4506 | if (s_register_operand (op, mode)) | |
f3bb6135 | 4507 | return TRUE; |
9ce71c6f BS |
4508 | |
4509 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4510 | return FALSE; | |
4511 | ||
9b66ebb1 PB |
4512 | if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE) |
4513 | return (arm_const_double_rtx (op) | |
3b684012 | 4514 | || neg_const_double_rtx_ok_for_fpa (op)); |
f3bb6135 RE |
4515 | |
4516 | return FALSE; | |
ff9940b0 RE |
4517 | } |
4518 | ||
9b66ebb1 PB |
4519 | |
4520 | /* Return TRUE if OP is suitable for the rhs of a floating point comparison. | |
4521 | Depends which fpu we are targeting. */ | |
4522 | ||
4523 | int | |
4524 | arm_float_compare_operand (rtx op, enum machine_mode mode) | |
4525 | { | |
4526 | if (TARGET_VFP) | |
4527 | return vfp_compare_operand (op, mode); | |
4528 | else | |
4529 | return arm_float_rhs_operand (op, mode); | |
4530 | } | |
4531 | ||
4532 | ||
9b6b54e2 | 4533 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 4534 | int |
e32bac5b | 4535 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
4536 | { |
4537 | /* Reject eliminable registers. */ | |
4538 | if (! (reload_in_progress || reload_completed) | |
4539 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
4540 | || reg_mentioned_p (arg_pointer_rtx, op) | |
4541 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
4542 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
4543 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
4544 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
4545 | return 0; | |
4546 | ||
4547 | if (GET_CODE (op) == MEM) | |
4548 | { | |
4549 | rtx ind; | |
4550 | ||
4551 | ind = XEXP (op, 0); | |
4552 | ||
4553 | /* Match: (mem (reg)). */ | |
4554 | if (GET_CODE (ind) == REG) | |
4555 | return 1; | |
4556 | ||
4557 | /* Match: | |
4558 | (mem (plus (reg) | |
4559 | (const))). */ | |
4560 | if (GET_CODE (ind) == PLUS | |
4561 | && GET_CODE (XEXP (ind, 0)) == REG | |
4562 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
4563 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
4564 | return 1; | |
4565 | } | |
4566 | ||
4567 | return 0; | |
4568 | } | |
4569 | ||
1e1ab407 RE |
4570 | int |
4571 | arm_extendqisi_mem_op (rtx op, enum machine_mode mode) | |
4572 | { | |
4573 | if (!memory_operand (op, mode)) | |
4574 | return 0; | |
4575 | ||
4576 | return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0); | |
4577 | } | |
4578 | ||
9b6b54e2 | 4579 | /* Return nonzero if OP is a Cirrus or general register. */ |
9b6b54e2 | 4580 | int |
e32bac5b | 4581 | cirrus_register_operand (rtx op, enum machine_mode mode) |
9b6b54e2 NC |
4582 | { |
4583 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4584 | return FALSE; | |
4585 | ||
4586 | if (GET_CODE (op) == SUBREG) | |
4587 | op = SUBREG_REG (op); | |
4588 | ||
4589 | return (GET_CODE (op) == REG | |
4590 | && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS | |
4591 | || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); | |
4592 | } | |
4593 | ||
4594 | /* Return nonzero if OP is a cirrus FP register. */ | |
9b6b54e2 | 4595 | int |
e32bac5b | 4596 | cirrus_fp_register (rtx op, enum machine_mode mode) |
9b6b54e2 NC |
4597 | { |
4598 | if (GET_MODE (op) != mode && mode != VOIDmode) | |
4599 | return FALSE; | |
4600 | ||
4601 | if (GET_CODE (op) == SUBREG) | |
4602 | op = SUBREG_REG (op); | |
4603 | ||
4604 | return (GET_CODE (op) == REG | |
4605 | && (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
4606 | || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); | |
4607 | } | |
4608 | ||
4609 | /* Return nonzero if OP is a 6bit constant (0..63). */ | |
9b6b54e2 | 4610 | int |
e32bac5b | 4611 | cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9b6b54e2 NC |
4612 | { |
4613 | return (GET_CODE (op) == CONST_INT | |
4614 | && INTVAL (op) >= 0 | |
4615 | && INTVAL (op) < 64); | |
4616 | } | |
4617 | ||
9b66ebb1 | 4618 | |
fdd695fd PB |
4619 | /* Return TRUE if OP is a valid VFP memory address pattern. |
4620 | WB if true if writeback address modes are allowed. */ | |
9b66ebb1 PB |
4621 | |
4622 | int | |
fdd695fd | 4623 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 4624 | { |
fdd695fd | 4625 | rtx ind; |
9b66ebb1 | 4626 | |
fdd695fd | 4627 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
4628 | if (! (reload_in_progress || reload_completed) |
4629 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
4630 | || reg_mentioned_p (arg_pointer_rtx, op) | |
4631 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
4632 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
4633 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
4634 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
4635 | return FALSE; | |
4636 | ||
59b9a953 | 4637 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
4638 | if (GET_CODE (op) != MEM) |
4639 | return FALSE; | |
9b66ebb1 | 4640 | |
fdd695fd | 4641 | ind = XEXP (op, 0); |
9b66ebb1 | 4642 | |
fdd695fd PB |
4643 | if (reload_completed |
4644 | && (GET_CODE (ind) == LABEL_REF | |
4645 | || (GET_CODE (ind) == CONST | |
4646 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
4647 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
4648 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
4649 | return TRUE; | |
9b66ebb1 | 4650 | |
fdd695fd PB |
4651 | /* Match: (mem (reg)). */ |
4652 | if (GET_CODE (ind) == REG) | |
4653 | return arm_address_register_rtx_p (ind, 0); | |
4654 | ||
4655 | /* Autoincremment addressing modes. */ | |
4656 | if (wb | |
4657 | && (GET_CODE (ind) == PRE_INC | |
4658 | || GET_CODE (ind) == POST_INC | |
4659 | || GET_CODE (ind) == PRE_DEC | |
4660 | || GET_CODE (ind) == POST_DEC)) | |
4661 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); | |
4662 | ||
4663 | if (wb | |
4664 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
4665 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
4666 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
4667 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
4668 | ind = XEXP (ind, 1); | |
4669 | ||
4670 | /* Match: | |
4671 | (plus (reg) | |
4672 | (const)). */ | |
4673 | if (GET_CODE (ind) == PLUS | |
4674 | && GET_CODE (XEXP (ind, 0)) == REG | |
4675 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
4676 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
4677 | && INTVAL (XEXP (ind, 1)) > -1024 | |
4678 | && INTVAL (XEXP (ind, 1)) < 1024 | |
4679 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
4680 | return TRUE; | |
9b66ebb1 PB |
4681 | |
4682 | return FALSE; | |
4683 | } | |
4684 | ||
4685 | ||
4686 | /* Return TRUE if OP is a REG or constant zero. */ | |
4687 | int | |
4688 | vfp_compare_operand (rtx op, enum machine_mode mode) | |
4689 | { | |
4690 | if (s_register_operand (op, mode)) | |
4691 | return TRUE; | |
4692 | ||
4693 | return (GET_CODE (op) == CONST_DOUBLE | |
4694 | && arm_const_double_rtx (op)); | |
4695 | } | |
4696 | ||
4697 | ||
4698 | /* Return GENERAL_REGS if a scratch register required to reload x to/from | |
4699 | VFP registers. Otherwise return NO_REGS. */ | |
4700 | ||
4701 | enum reg_class | |
4702 | vfp_secondary_reload_class (enum machine_mode mode, rtx x) | |
4703 | { | |
fdd695fd | 4704 | if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode)) |
9b66ebb1 PB |
4705 | return NO_REGS; |
4706 | ||
4707 | return GENERAL_REGS; | |
4708 | } | |
4709 | ||
4710 | ||
f0375c66 NC |
4711 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
4712 | Use by the Cirrus Maverick code which has to workaround | |
4713 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 4714 | static bool |
e32bac5b | 4715 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
4716 | { |
4717 | rtx body, lhs, rhs;; | |
4718 | ||
f0375c66 NC |
4719 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
4720 | return false; | |
9b6b54e2 NC |
4721 | |
4722 | body = PATTERN (insn); | |
4723 | ||
4724 | if (GET_CODE (body) != SET) | |
f0375c66 | 4725 | return false; |
9b6b54e2 NC |
4726 | |
4727 | lhs = XEXP (body, 0); | |
4728 | rhs = XEXP (body, 1); | |
4729 | ||
f0375c66 NC |
4730 | lhs = REG_OR_SUBREG_RTX (lhs); |
4731 | ||
4732 | /* If the destination is not a general purpose | |
4733 | register we do not have to worry. */ | |
4734 | if (GET_CODE (lhs) != REG | |
4735 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
4736 | return false; | |
4737 | ||
4738 | /* As well as loads from memory we also have to react | |
4739 | to loads of invalid constants which will be turned | |
4740 | into loads from the minipool. */ | |
4741 | return (GET_CODE (rhs) == MEM | |
4742 | || GET_CODE (rhs) == SYMBOL_REF | |
4743 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
4744 | } |
4745 | ||
f0375c66 | 4746 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 4747 | static bool |
e32bac5b | 4748 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
4749 | { |
4750 | enum attr_cirrus attr; | |
4751 | ||
4752 | /* get_attr aborts on USE and CLOBBER. */ | |
4753 | if (!insn | |
4754 | || GET_CODE (insn) != INSN | |
4755 | || GET_CODE (PATTERN (insn)) == USE | |
4756 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
4757 | return 0; | |
4758 | ||
4759 | attr = get_attr_cirrus (insn); | |
4760 | ||
f0375c66 | 4761 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
4762 | } |
4763 | ||
4764 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 4765 | static void |
e32bac5b | 4766 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
4767 | { |
4768 | enum attr_cirrus attr; | |
4769 | rtx body = PATTERN (first); | |
4770 | rtx t; | |
4771 | int nops; | |
4772 | ||
4773 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
4774 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
4775 | { | |
4776 | nops = 0; | |
4777 | t = next_nonnote_insn (first); | |
4778 | ||
f0375c66 | 4779 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4780 | ++ nops; |
4781 | ||
f0375c66 | 4782 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4783 | ++ nops; |
4784 | ||
4785 | while (nops --) | |
4786 | emit_insn_after (gen_nop (), first); | |
4787 | ||
4788 | return; | |
4789 | } | |
4790 | ||
4791 | /* (float (blah)) is in parallel with a clobber. */ | |
4792 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
4793 | body = XVECEXP (body, 0, 0); | |
4794 | ||
4795 | if (GET_CODE (body) == SET) | |
4796 | { | |
4797 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
4798 | ||
4799 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
4800 | be followed by a non Cirrus insn. */ | |
4801 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
4802 | { | |
f0375c66 | 4803 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
4804 | emit_insn_after (gen_nop (), first); |
4805 | ||
4806 | return; | |
4807 | } | |
f0375c66 | 4808 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
4809 | { |
4810 | unsigned int arm_regno; | |
4811 | ||
4812 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
4813 | ldr/cfmv64hr combination where the Rd field is the same | |
4814 | in both instructions must be split with a non Cirrus | |
4815 | insn. Example: | |
4816 | ||
4817 | ldr r0, blah | |
4818 | nop | |
4819 | cfmvsr mvf0, r0. */ | |
4820 | ||
4821 | /* Get Arm register number for ldr insn. */ | |
4822 | if (GET_CODE (lhs) == REG) | |
4823 | arm_regno = REGNO (lhs); | |
4824 | else if (GET_CODE (rhs) == REG) | |
4825 | arm_regno = REGNO (rhs); | |
4826 | else | |
4827 | abort (); | |
4828 | ||
4829 | /* Next insn. */ | |
4830 | first = next_nonnote_insn (first); | |
4831 | ||
f0375c66 | 4832 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
4833 | return; |
4834 | ||
4835 | body = PATTERN (first); | |
4836 | ||
4837 | /* (float (blah)) is in parallel with a clobber. */ | |
4838 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
4839 | body = XVECEXP (body, 0, 0); | |
4840 | ||
4841 | if (GET_CODE (body) == FLOAT) | |
4842 | body = XEXP (body, 0); | |
4843 | ||
4844 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
4845 | && GET_CODE (XEXP (body, 1)) == REG | |
4846 | && arm_regno == REGNO (XEXP (body, 1))) | |
4847 | emit_insn_after (gen_nop (), first); | |
4848 | ||
4849 | return; | |
4850 | } | |
4851 | } | |
4852 | ||
4853 | /* get_attr aborts on USE and CLOBBER. */ | |
4854 | if (!first | |
4855 | || GET_CODE (first) != INSN | |
4856 | || GET_CODE (PATTERN (first)) == USE | |
4857 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
4858 | return; | |
4859 | ||
4860 | attr = get_attr_cirrus (first); | |
4861 | ||
4862 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
4863 | must be followed by a non-coprocessor instruction. */ | |
4864 | if (attr == CIRRUS_COMPARE) | |
4865 | { | |
4866 | nops = 0; | |
4867 | ||
4868 | t = next_nonnote_insn (first); | |
4869 | ||
f0375c66 | 4870 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
4871 | ++ nops; |
4872 | ||
f0375c66 | 4873 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
4874 | ++ nops; |
4875 | ||
4876 | while (nops --) | |
4877 | emit_insn_after (gen_nop (), first); | |
4878 | ||
4879 | return; | |
4880 | } | |
4881 | } | |
4882 | ||
cce8749e | 4883 | /* Return nonzero if OP is a constant power of two. */ |
cce8749e | 4884 | int |
e32bac5b | 4885 | power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
cce8749e CH |
4886 | { |
4887 | if (GET_CODE (op) == CONST_INT) | |
4888 | { | |
d5b7b3ae | 4889 | HOST_WIDE_INT value = INTVAL (op); |
1d6e90ac | 4890 | |
f3bb6135 | 4891 | return value != 0 && (value & (value - 1)) == 0; |
cce8749e | 4892 | } |
1d6e90ac | 4893 | |
f3bb6135 RE |
4894 | return FALSE; |
4895 | } | |
cce8749e CH |
4896 | |
4897 | /* Return TRUE for a valid operand of a DImode operation. | |
e9c6b69b | 4898 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
ff9940b0 RE |
4899 | Note that this disallows MEM(REG+REG), but allows |
4900 | MEM(PRE/POST_INC/DEC(REG)). */ | |
cce8749e | 4901 | int |
e32bac5b | 4902 | di_operand (rtx op, enum machine_mode mode) |
cce8749e | 4903 | { |
ff9940b0 | 4904 | if (s_register_operand (op, mode)) |
f3bb6135 | 4905 | return TRUE; |
cce8749e | 4906 | |
9ce71c6f BS |
4907 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) |
4908 | return FALSE; | |
4909 | ||
e9c6b69b NC |
4910 | if (GET_CODE (op) == SUBREG) |
4911 | op = SUBREG_REG (op); | |
4912 | ||
cce8749e CH |
4913 | switch (GET_CODE (op)) |
4914 | { | |
4915 | case CONST_DOUBLE: | |
4916 | case CONST_INT: | |
f3bb6135 RE |
4917 | return TRUE; |
4918 | ||
cce8749e | 4919 | case MEM: |
f3bb6135 RE |
4920 | return memory_address_p (DImode, XEXP (op, 0)); |
4921 | ||
cce8749e | 4922 | default: |
f3bb6135 | 4923 | return FALSE; |
cce8749e | 4924 | } |
f3bb6135 | 4925 | } |
cce8749e | 4926 | |
d5b7b3ae RE |
4927 | /* Like di_operand, but don't accept constants. */ |
4928 | int | |
e32bac5b | 4929 | nonimmediate_di_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
4930 | { |
4931 | if (s_register_operand (op, mode)) | |
4932 | return TRUE; | |
4933 | ||
4934 | if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) | |
4935 | return FALSE; | |
4936 | ||
4937 | if (GET_CODE (op) == SUBREG) | |
4938 | op = SUBREG_REG (op); | |
4939 | ||
4940 | if (GET_CODE (op) == MEM) | |
4941 | return memory_address_p (DImode, XEXP (op, 0)); | |
4942 | ||
4943 | return FALSE; | |
4944 | } | |
4945 | ||
9b66ebb1 | 4946 | /* Return TRUE for a valid operand of a DFmode operation when soft-float. |
e9c6b69b | 4947 | Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). |
f3139301 DE |
4948 | Note that this disallows MEM(REG+REG), but allows |
4949 | MEM(PRE/POST_INC/DEC(REG)). */ | |
f3139301 | 4950 | int |
e32bac5b | 4951 | soft_df_operand (rtx op, enum machine_mode mode) |
f3139301 DE |
4952 | { |
4953 | if (s_register_operand (op, mode)) | |
4b02997f | 4954 | return TRUE; |
f3139301 | 4955 | |
9ce71c6f BS |
4956 | if (mode != VOIDmode && GET_MODE (op) != mode) |
4957 | return FALSE; | |
4958 | ||
37b80d2e BS |
4959 | if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) |
4960 | return FALSE; | |
4961 | ||
e9c6b69b NC |
4962 | if (GET_CODE (op) == SUBREG) |
4963 | op = SUBREG_REG (op); | |
9ce71c6f | 4964 | |
f3139301 DE |
4965 | switch (GET_CODE (op)) |
4966 | { | |
4967 | case CONST_DOUBLE: | |
4968 | return TRUE; | |
4969 | ||
4970 | case MEM: | |
4971 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4972 | ||
4973 | default: | |
4974 | return FALSE; | |
4975 | } | |
4976 | } | |
4977 | ||
d5b7b3ae RE |
4978 | /* Like soft_df_operand, but don't accept constants. */ |
4979 | int | |
e32bac5b | 4980 | nonimmediate_soft_df_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
4981 | { |
4982 | if (s_register_operand (op, mode)) | |
4b02997f | 4983 | return TRUE; |
d5b7b3ae RE |
4984 | |
4985 | if (mode != VOIDmode && GET_MODE (op) != mode) | |
4986 | return FALSE; | |
4987 | ||
4988 | if (GET_CODE (op) == SUBREG) | |
4989 | op = SUBREG_REG (op); | |
4990 | ||
4991 | if (GET_CODE (op) == MEM) | |
4992 | return memory_address_p (DFmode, XEXP (op, 0)); | |
4993 | return FALSE; | |
4994 | } | |
cce8749e | 4995 | |
d5b7b3ae | 4996 | /* Return TRUE for valid index operands. */ |
cce8749e | 4997 | int |
e32bac5b | 4998 | index_operand (rtx op, enum machine_mode mode) |
cce8749e | 4999 | { |
d5b7b3ae | 5000 | return (s_register_operand (op, mode) |
ff9940b0 | 5001 | || (immediate_operand (op, mode) |
d5b7b3ae RE |
5002 | && (GET_CODE (op) != CONST_INT |
5003 | || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); | |
f3bb6135 | 5004 | } |
cce8749e | 5005 | |
ff9940b0 RE |
5006 | /* Return TRUE for valid shifts by a constant. This also accepts any |
5007 | power of two on the (somewhat overly relaxed) assumption that the | |
6354dc9b | 5008 | shift operator in this case was a mult. */ |
ff9940b0 | 5009 | int |
e32bac5b | 5010 | const_shift_operand (rtx op, enum machine_mode mode) |
ff9940b0 RE |
5011 | { |
5012 | return (power_of_two_operand (op, mode) | |
5013 | || (immediate_operand (op, mode) | |
d5b7b3ae RE |
5014 | && (GET_CODE (op) != CONST_INT |
5015 | || (INTVAL (op) < 32 && INTVAL (op) > 0)))); | |
f3bb6135 | 5016 | } |
ff9940b0 | 5017 | |
cce8749e CH |
5018 | /* Return TRUE for arithmetic operators which can be combined with a multiply |
5019 | (shift). */ | |
cce8749e | 5020 | int |
e32bac5b | 5021 | shiftable_operator (rtx x, enum machine_mode mode) |
cce8749e | 5022 | { |
1d6e90ac NC |
5023 | enum rtx_code code; |
5024 | ||
cce8749e CH |
5025 | if (GET_MODE (x) != mode) |
5026 | return FALSE; | |
cce8749e | 5027 | |
1d6e90ac NC |
5028 | code = GET_CODE (x); |
5029 | ||
5030 | return (code == PLUS || code == MINUS | |
5031 | || code == IOR || code == XOR || code == AND); | |
f3bb6135 | 5032 | } |
cce8749e | 5033 | |
6ab589e0 | 5034 | /* Return TRUE for binary logical operators. */ |
6ab589e0 | 5035 | int |
e32bac5b | 5036 | logical_binary_operator (rtx x, enum machine_mode mode) |
6ab589e0 | 5037 | { |
1d6e90ac NC |
5038 | enum rtx_code code; |
5039 | ||
6ab589e0 JL |
5040 | if (GET_MODE (x) != mode) |
5041 | return FALSE; | |
6ab589e0 | 5042 | |
1d6e90ac NC |
5043 | code = GET_CODE (x); |
5044 | ||
5045 | return (code == IOR || code == XOR || code == AND); | |
6ab589e0 JL |
5046 | } |
5047 | ||
6354dc9b | 5048 | /* Return TRUE for shift operators. */ |
cce8749e | 5049 | int |
e32bac5b | 5050 | shift_operator (rtx x,enum machine_mode mode) |
cce8749e | 5051 | { |
1d6e90ac NC |
5052 | enum rtx_code code; |
5053 | ||
cce8749e CH |
5054 | if (GET_MODE (x) != mode) |
5055 | return FALSE; | |
cce8749e | 5056 | |
1d6e90ac | 5057 | code = GET_CODE (x); |
f3bb6135 | 5058 | |
1d6e90ac NC |
5059 | if (code == MULT) |
5060 | return power_of_two_operand (XEXP (x, 1), mode); | |
5061 | ||
5062 | return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT | |
5063 | || code == ROTATERT); | |
f3bb6135 | 5064 | } |
ff9940b0 | 5065 | |
6354dc9b NC |
5066 | /* Return TRUE if x is EQ or NE. */ |
5067 | int | |
e32bac5b | 5068 | equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 5069 | { |
f3bb6135 | 5070 | return GET_CODE (x) == EQ || GET_CODE (x) == NE; |
ff9940b0 RE |
5071 | } |
5072 | ||
e45b72c4 RE |
5073 | /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ |
5074 | int | |
e32bac5b | 5075 | arm_comparison_operator (rtx x, enum machine_mode mode) |
e45b72c4 RE |
5076 | { |
5077 | return (comparison_operator (x, mode) | |
5078 | && GET_CODE (x) != LTGT | |
5079 | && GET_CODE (x) != UNEQ); | |
5080 | } | |
5081 | ||
6354dc9b | 5082 | /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ |
ff9940b0 | 5083 | int |
e32bac5b | 5084 | minmax_operator (rtx x, enum machine_mode mode) |
ff9940b0 RE |
5085 | { |
5086 | enum rtx_code code = GET_CODE (x); | |
5087 | ||
5088 | if (GET_MODE (x) != mode) | |
5089 | return FALSE; | |
f3bb6135 | 5090 | |
ff9940b0 | 5091 | return code == SMIN || code == SMAX || code == UMIN || code == UMAX; |
f3bb6135 | 5092 | } |
ff9940b0 | 5093 | |
ff9940b0 | 5094 | /* Return TRUE if this is the condition code register, if we aren't given |
6354dc9b | 5095 | a mode, accept any class CCmode register. */ |
ff9940b0 | 5096 | int |
e32bac5b | 5097 | cc_register (rtx x, enum machine_mode mode) |
ff9940b0 RE |
5098 | { |
5099 | if (mode == VOIDmode) | |
5100 | { | |
5101 | mode = GET_MODE (x); | |
d5b7b3ae | 5102 | |
ff9940b0 RE |
5103 | if (GET_MODE_CLASS (mode) != MODE_CC) |
5104 | return FALSE; | |
5105 | } | |
f3bb6135 | 5106 | |
d5b7b3ae RE |
5107 | if ( GET_MODE (x) == mode |
5108 | && GET_CODE (x) == REG | |
5109 | && REGNO (x) == CC_REGNUM) | |
ff9940b0 | 5110 | return TRUE; |
f3bb6135 | 5111 | |
ff9940b0 RE |
5112 | return FALSE; |
5113 | } | |
5bbe2d40 RE |
5114 | |
5115 | /* Return TRUE if this is the condition code register, if we aren't given | |
84ed5e79 RE |
5116 | a mode, accept any class CCmode register which indicates a dominance |
5117 | expression. */ | |
5bbe2d40 | 5118 | int |
e32bac5b | 5119 | dominant_cc_register (rtx x, enum machine_mode mode) |
5bbe2d40 RE |
5120 | { |
5121 | if (mode == VOIDmode) | |
5122 | { | |
5123 | mode = GET_MODE (x); | |
d5b7b3ae | 5124 | |
84ed5e79 | 5125 | if (GET_MODE_CLASS (mode) != MODE_CC) |
5bbe2d40 RE |
5126 | return FALSE; |
5127 | } | |
5128 | ||
e32bac5b | 5129 | if (mode != CC_DNEmode && mode != CC_DEQmode |
84ed5e79 RE |
5130 | && mode != CC_DLEmode && mode != CC_DLTmode |
5131 | && mode != CC_DGEmode && mode != CC_DGTmode | |
5132 | && mode != CC_DLEUmode && mode != CC_DLTUmode | |
5133 | && mode != CC_DGEUmode && mode != CC_DGTUmode) | |
5134 | return FALSE; | |
5135 | ||
d5b7b3ae | 5136 | return cc_register (x, mode); |
5bbe2d40 RE |
5137 | } |
5138 | ||
2b835d68 RE |
5139 | /* Return TRUE if X references a SYMBOL_REF. */ |
5140 | int | |
e32bac5b | 5141 | symbol_mentioned_p (rtx x) |
2b835d68 | 5142 | { |
1d6e90ac NC |
5143 | const char * fmt; |
5144 | int i; | |
2b835d68 RE |
5145 | |
5146 | if (GET_CODE (x) == SYMBOL_REF) | |
5147 | return 1; | |
5148 | ||
5149 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
d5b7b3ae | 5150 | |
2b835d68 RE |
5151 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
5152 | { | |
5153 | if (fmt[i] == 'E') | |
5154 | { | |
1d6e90ac | 5155 | int j; |
2b835d68 RE |
5156 | |
5157 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5158 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
5159 | return 1; | |
5160 | } | |
5161 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
5162 | return 1; | |
5163 | } | |
5164 | ||
5165 | return 0; | |
5166 | } | |
5167 | ||
5168 | /* Return TRUE if X references a LABEL_REF. */ | |
5169 | int | |
e32bac5b | 5170 | label_mentioned_p (rtx x) |
2b835d68 | 5171 | { |
1d6e90ac NC |
5172 | const char * fmt; |
5173 | int i; | |
2b835d68 RE |
5174 | |
5175 | if (GET_CODE (x) == LABEL_REF) | |
5176 | return 1; | |
5177 | ||
5178 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
5179 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5180 | { | |
5181 | if (fmt[i] == 'E') | |
5182 | { | |
1d6e90ac | 5183 | int j; |
2b835d68 RE |
5184 | |
5185 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
5186 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
5187 | return 1; | |
5188 | } | |
5189 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
5190 | return 1; | |
5191 | } | |
5192 | ||
5193 | return 0; | |
5194 | } | |
5195 | ||
ff9940b0 | 5196 | enum rtx_code |
e32bac5b | 5197 | minmax_code (rtx x) |
ff9940b0 RE |
5198 | { |
5199 | enum rtx_code code = GET_CODE (x); | |
5200 | ||
5201 | if (code == SMAX) | |
5202 | return GE; | |
f3bb6135 | 5203 | else if (code == SMIN) |
ff9940b0 | 5204 | return LE; |
f3bb6135 | 5205 | else if (code == UMIN) |
ff9940b0 | 5206 | return LEU; |
f3bb6135 | 5207 | else if (code == UMAX) |
ff9940b0 | 5208 | return GEU; |
f3bb6135 | 5209 | |
ff9940b0 RE |
5210 | abort (); |
5211 | } | |
5212 | ||
6354dc9b | 5213 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 5214 | int |
e32bac5b | 5215 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 5216 | { |
ff9940b0 RE |
5217 | if ((GET_CODE (XEXP (a, 0)) == REG |
5218 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
5219 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
5220 | && (GET_CODE (XEXP (b, 0)) == REG | |
5221 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
5222 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
5223 | { | |
1d6e90ac NC |
5224 | int val0 = 0, val1 = 0; |
5225 | int reg0, reg1; | |
5226 | ||
ff9940b0 RE |
5227 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
5228 | { | |
1d6e90ac | 5229 | reg0 = REGNO (XEXP (XEXP (a, 0), 0)); |
ff9940b0 RE |
5230 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
5231 | } | |
5232 | else | |
5233 | reg0 = REGNO (XEXP (a, 0)); | |
1d6e90ac | 5234 | |
ff9940b0 RE |
5235 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
5236 | { | |
1d6e90ac | 5237 | reg1 = REGNO (XEXP (XEXP (b, 0), 0)); |
ff9940b0 RE |
5238 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
5239 | } | |
5240 | else | |
5241 | reg1 = REGNO (XEXP (b, 0)); | |
1d6e90ac | 5242 | |
e32bac5b RE |
5243 | /* Don't accept any offset that will require multiple |
5244 | instructions to handle, since this would cause the | |
5245 | arith_adjacentmem pattern to output an overlong sequence. */ | |
c75a3ddc PB |
5246 | if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) |
5247 | return 0; | |
5248 | ||
ff9940b0 RE |
5249 | return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); |
5250 | } | |
5251 | return 0; | |
5252 | } | |
5253 | ||
5254 | /* Return 1 if OP is a load multiple operation. It is known to be | |
6354dc9b | 5255 | parallel and the first section will be tested. */ |
f3bb6135 | 5256 | int |
e32bac5b | 5257 | load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 5258 | { |
f3bb6135 | 5259 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
5260 | int dest_regno; |
5261 | rtx src_addr; | |
f3bb6135 | 5262 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
5263 | rtx elt; |
5264 | ||
5265 | if (count <= 1 | |
5266 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
5267 | return 0; | |
5268 | ||
6354dc9b | 5269 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
5270 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
5271 | { | |
5272 | i++; | |
5273 | base = 1; | |
5274 | ||
6354dc9b | 5275 | /* Now check it more carefully. */ |
ff9940b0 RE |
5276 | if (GET_CODE (SET_DEST (elt)) != REG |
5277 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
ff9940b0 | 5278 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT |
41e3f998 | 5279 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 5280 | return 0; |
ff9940b0 RE |
5281 | } |
5282 | ||
5283 | /* Perform a quick check so we don't blow up below. */ | |
5284 | if (count <= i | |
5285 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
5286 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG | |
5287 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) | |
5288 | return 0; | |
5289 | ||
5290 | dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); | |
5291 | src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); | |
5292 | ||
5293 | for (; i < count; i++) | |
5294 | { | |
ed4c4348 | 5295 | elt = XVECEXP (op, 0, i); |
ff9940b0 RE |
5296 | |
5297 | if (GET_CODE (elt) != SET | |
5298 | || GET_CODE (SET_DEST (elt)) != REG | |
5299 | || GET_MODE (SET_DEST (elt)) != SImode | |
6354dc9b | 5300 | || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) |
ff9940b0 RE |
5301 | || GET_CODE (SET_SRC (elt)) != MEM |
5302 | || GET_MODE (SET_SRC (elt)) != SImode | |
5303 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS | |
5895f793 | 5304 | || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) |
ff9940b0 RE |
5305 | || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT |
5306 | || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) | |
5307 | return 0; | |
5308 | } | |
5309 | ||
5310 | return 1; | |
5311 | } | |
5312 | ||
5313 | /* Return 1 if OP is a store multiple operation. It is known to be | |
6354dc9b | 5314 | parallel and the first section will be tested. */ |
f3bb6135 | 5315 | int |
e32bac5b | 5316 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ff9940b0 | 5317 | { |
f3bb6135 | 5318 | HOST_WIDE_INT count = XVECLEN (op, 0); |
ff9940b0 RE |
5319 | int src_regno; |
5320 | rtx dest_addr; | |
f3bb6135 | 5321 | HOST_WIDE_INT i = 1, base = 0; |
ff9940b0 RE |
5322 | rtx elt; |
5323 | ||
5324 | if (count <= 1 | |
5325 | || GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
5326 | return 0; | |
5327 | ||
6354dc9b | 5328 | /* Check to see if this might be a write-back. */ |
ff9940b0 RE |
5329 | if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) |
5330 | { | |
5331 | i++; | |
5332 | base = 1; | |
5333 | ||
6354dc9b | 5334 | /* Now check it more carefully. */ |
ff9940b0 RE |
5335 | if (GET_CODE (SET_DEST (elt)) != REG |
5336 | || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG | |
ff9940b0 | 5337 | || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT |
41e3f998 | 5338 | || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) |
ff9940b0 | 5339 | return 0; |
ff9940b0 RE |
5340 | } |
5341 | ||
5342 | /* Perform a quick check so we don't blow up below. */ | |
5343 | if (count <= i | |
5344 | || GET_CODE (XVECEXP (op, 0, i - 1)) != SET | |
5345 | || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM | |
5346 | || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) | |
5347 | return 0; | |
5348 | ||
5349 | src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); | |
5350 | dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); | |
5351 | ||
5352 | for (; i < count; i++) | |
5353 | { | |
5354 | elt = XVECEXP (op, 0, i); | |
5355 | ||
5356 | if (GET_CODE (elt) != SET | |
5357 | || GET_CODE (SET_SRC (elt)) != REG | |
5358 | || GET_MODE (SET_SRC (elt)) != SImode | |
6354dc9b | 5359 | || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) |
ff9940b0 RE |
5360 | || GET_CODE (SET_DEST (elt)) != MEM |
5361 | || GET_MODE (SET_DEST (elt)) != SImode | |
5362 | || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS | |
5895f793 | 5363 | || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) |
ff9940b0 RE |
5364 | || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT |
5365 | || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) | |
5366 | return 0; | |
5367 | } | |
5368 | ||
5369 | return 1; | |
5370 | } | |
e2c671ba | 5371 | |
84ed5e79 | 5372 | int |
e32bac5b RE |
5373 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
5374 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
5375 | { |
5376 | int unsorted_regs[4]; | |
5377 | HOST_WIDE_INT unsorted_offsets[4]; | |
5378 | int order[4]; | |
ad076f4e | 5379 | int base_reg = -1; |
84ed5e79 RE |
5380 | int i; |
5381 | ||
1d6e90ac NC |
5382 | /* Can only handle 2, 3, or 4 insns at present, |
5383 | though could be easily extended if required. */ | |
84ed5e79 RE |
5384 | if (nops < 2 || nops > 4) |
5385 | abort (); | |
5386 | ||
5387 | /* Loop over the operands and check that the memory references are | |
5388 | suitable (ie immediate offsets from the same base register). At | |
5389 | the same time, extract the target register, and the memory | |
5390 | offsets. */ | |
5391 | for (i = 0; i < nops; i++) | |
5392 | { | |
5393 | rtx reg; | |
5394 | rtx offset; | |
5395 | ||
56636818 JL |
5396 | /* Convert a subreg of a mem into the mem itself. */ |
5397 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 5398 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 5399 | |
84ed5e79 RE |
5400 | if (GET_CODE (operands[nops + i]) != MEM) |
5401 | abort (); | |
5402 | ||
5403 | /* Don't reorder volatile memory references; it doesn't seem worth | |
5404 | looking for the case where the order is ok anyway. */ | |
5405 | if (MEM_VOLATILE_P (operands[nops + i])) | |
5406 | return 0; | |
5407 | ||
5408 | offset = const0_rtx; | |
5409 | ||
5410 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
5411 | || (GET_CODE (reg) == SUBREG | |
5412 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5413 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
5414 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
5415 | == REG) | |
5416 | || (GET_CODE (reg) == SUBREG | |
5417 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5418 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
5419 | == CONST_INT))) | |
5420 | { | |
5421 | if (i == 0) | |
5422 | { | |
d5b7b3ae | 5423 | base_reg = REGNO (reg); |
84ed5e79 RE |
5424 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
5425 | ? REGNO (operands[i]) | |
5426 | : REGNO (SUBREG_REG (operands[i]))); | |
5427 | order[0] = 0; | |
5428 | } | |
5429 | else | |
5430 | { | |
6354dc9b | 5431 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
5432 | /* Not addressed from the same base register. */ |
5433 | return 0; | |
5434 | ||
5435 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
5436 | ? REGNO (operands[i]) | |
5437 | : REGNO (SUBREG_REG (operands[i]))); | |
5438 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
5439 | order[0] = i; | |
5440 | } | |
5441 | ||
5442 | /* If it isn't an integer register, or if it overwrites the | |
5443 | base register but isn't the last insn in the list, then | |
5444 | we can't do this. */ | |
5445 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
5446 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
5447 | return 0; | |
5448 | ||
5449 | unsorted_offsets[i] = INTVAL (offset); | |
5450 | } | |
5451 | else | |
5452 | /* Not a suitable memory address. */ | |
5453 | return 0; | |
5454 | } | |
5455 | ||
5456 | /* All the useful information has now been extracted from the | |
5457 | operands into unsorted_regs and unsorted_offsets; additionally, | |
5458 | order[0] has been set to the lowest numbered register in the | |
5459 | list. Sort the registers into order, and check that the memory | |
5460 | offsets are ascending and adjacent. */ | |
5461 | ||
5462 | for (i = 1; i < nops; i++) | |
5463 | { | |
5464 | int j; | |
5465 | ||
5466 | order[i] = order[i - 1]; | |
5467 | for (j = 0; j < nops; j++) | |
5468 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
5469 | && (order[i] == order[i - 1] | |
5470 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
5471 | order[i] = j; | |
5472 | ||
5473 | /* Have we found a suitable register? if not, one must be used more | |
5474 | than once. */ | |
5475 | if (order[i] == order[i - 1]) | |
5476 | return 0; | |
5477 | ||
5478 | /* Is the memory address adjacent and ascending? */ | |
5479 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
5480 | return 0; | |
5481 | } | |
5482 | ||
5483 | if (base) | |
5484 | { | |
5485 | *base = base_reg; | |
5486 | ||
5487 | for (i = 0; i < nops; i++) | |
5488 | regs[i] = unsorted_regs[order[i]]; | |
5489 | ||
5490 | *load_offset = unsorted_offsets[order[0]]; | |
5491 | } | |
5492 | ||
5493 | if (unsorted_offsets[order[0]] == 0) | |
5494 | return 1; /* ldmia */ | |
5495 | ||
5496 | if (unsorted_offsets[order[0]] == 4) | |
5497 | return 2; /* ldmib */ | |
5498 | ||
5499 | if (unsorted_offsets[order[nops - 1]] == 0) | |
5500 | return 3; /* ldmda */ | |
5501 | ||
5502 | if (unsorted_offsets[order[nops - 1]] == -4) | |
5503 | return 4; /* ldmdb */ | |
5504 | ||
949d79eb RE |
5505 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
5506 | if the offset isn't small enough. The reason 2 ldrs are faster | |
5507 | is because these ARMs are able to do more than one cache access | |
5508 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
5509 | whilst the ARM8 has a double bandwidth cache. This means that | |
5510 | these cores can do both an instruction fetch and a data fetch in | |
5511 | a single cycle, so the trick of calculating the address into a | |
5512 | scratch register (one of the result regs) and then doing a load | |
5513 | multiple actually becomes slower (and no smaller in code size). | |
5514 | That is the transformation | |
6cc8c0b3 NC |
5515 | |
5516 | ldr rd1, [rbase + offset] | |
5517 | ldr rd2, [rbase + offset + 4] | |
5518 | ||
5519 | to | |
5520 | ||
5521 | add rd1, rbase, offset | |
5522 | ldmia rd1, {rd1, rd2} | |
5523 | ||
949d79eb RE |
5524 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
5525 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
5526 | access per cycle, the first sequence could never complete in less | |
5527 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
5528 | would make better use of sequential accesses if not hitting the | |
5529 | cache. | |
5530 | ||
5531 | We cheat here and test 'arm_ld_sched' which we currently know to | |
5532 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
5533 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 5534 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
5535 | return 0; |
5536 | ||
84ed5e79 RE |
5537 | /* Can't do it without setting up the offset, only do this if it takes |
5538 | no more than one insn. */ | |
5539 | return (const_ok_for_arm (unsorted_offsets[order[0]]) | |
5540 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; | |
5541 | } | |
5542 | ||
cd2b33d0 | 5543 | const char * |
e32bac5b | 5544 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
5545 | { |
5546 | int regs[4]; | |
5547 | int base_reg; | |
5548 | HOST_WIDE_INT offset; | |
5549 | char buf[100]; | |
5550 | int i; | |
5551 | ||
5552 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
5553 | { | |
5554 | case 1: | |
5555 | strcpy (buf, "ldm%?ia\t"); | |
5556 | break; | |
5557 | ||
5558 | case 2: | |
5559 | strcpy (buf, "ldm%?ib\t"); | |
5560 | break; | |
5561 | ||
5562 | case 3: | |
5563 | strcpy (buf, "ldm%?da\t"); | |
5564 | break; | |
5565 | ||
5566 | case 4: | |
5567 | strcpy (buf, "ldm%?db\t"); | |
5568 | break; | |
5569 | ||
5570 | case 5: | |
5571 | if (offset >= 0) | |
5572 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
5573 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
5574 | (long) offset); | |
5575 | else | |
5576 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
5577 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
5578 | (long) -offset); | |
5579 | output_asm_insn (buf, operands); | |
5580 | base_reg = regs[0]; | |
5581 | strcpy (buf, "ldm%?ia\t"); | |
5582 | break; | |
5583 | ||
5584 | default: | |
5585 | abort (); | |
5586 | } | |
5587 | ||
5588 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
5589 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
5590 | ||
5591 | for (i = 1; i < nops; i++) | |
5592 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
5593 | reg_names[regs[i]]); | |
5594 | ||
5595 | strcat (buf, "}\t%@ phole ldm"); | |
5596 | ||
5597 | output_asm_insn (buf, operands); | |
5598 | return ""; | |
5599 | } | |
5600 | ||
5601 | int | |
e32bac5b RE |
5602 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
5603 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
5604 | { |
5605 | int unsorted_regs[4]; | |
5606 | HOST_WIDE_INT unsorted_offsets[4]; | |
5607 | int order[4]; | |
ad076f4e | 5608 | int base_reg = -1; |
84ed5e79 RE |
5609 | int i; |
5610 | ||
5611 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
5612 | extended if required. */ | |
5613 | if (nops < 2 || nops > 4) | |
5614 | abort (); | |
5615 | ||
5616 | /* Loop over the operands and check that the memory references are | |
5617 | suitable (ie immediate offsets from the same base register). At | |
5618 | the same time, extract the target register, and the memory | |
5619 | offsets. */ | |
5620 | for (i = 0; i < nops; i++) | |
5621 | { | |
5622 | rtx reg; | |
5623 | rtx offset; | |
5624 | ||
56636818 JL |
5625 | /* Convert a subreg of a mem into the mem itself. */ |
5626 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 5627 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 5628 | |
84ed5e79 RE |
5629 | if (GET_CODE (operands[nops + i]) != MEM) |
5630 | abort (); | |
5631 | ||
5632 | /* Don't reorder volatile memory references; it doesn't seem worth | |
5633 | looking for the case where the order is ok anyway. */ | |
5634 | if (MEM_VOLATILE_P (operands[nops + i])) | |
5635 | return 0; | |
5636 | ||
5637 | offset = const0_rtx; | |
5638 | ||
5639 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
5640 | || (GET_CODE (reg) == SUBREG | |
5641 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5642 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
5643 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
5644 | == REG) | |
5645 | || (GET_CODE (reg) == SUBREG | |
5646 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
5647 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
5648 | == CONST_INT))) | |
5649 | { | |
5650 | if (i == 0) | |
5651 | { | |
62b10bbc | 5652 | base_reg = REGNO (reg); |
84ed5e79 RE |
5653 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
5654 | ? REGNO (operands[i]) | |
5655 | : REGNO (SUBREG_REG (operands[i]))); | |
5656 | order[0] = 0; | |
5657 | } | |
5658 | else | |
5659 | { | |
6354dc9b | 5660 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
5661 | /* Not addressed from the same base register. */ |
5662 | return 0; | |
5663 | ||
5664 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
5665 | ? REGNO (operands[i]) | |
5666 | : REGNO (SUBREG_REG (operands[i]))); | |
5667 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
5668 | order[0] = i; | |
5669 | } | |
5670 | ||
5671 | /* If it isn't an integer register, then we can't do this. */ | |
5672 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
5673 | return 0; | |
5674 | ||
5675 | unsorted_offsets[i] = INTVAL (offset); | |
5676 | } | |
5677 | else | |
5678 | /* Not a suitable memory address. */ | |
5679 | return 0; | |
5680 | } | |
5681 | ||
5682 | /* All the useful information has now been extracted from the | |
5683 | operands into unsorted_regs and unsorted_offsets; additionally, | |
5684 | order[0] has been set to the lowest numbered register in the | |
5685 | list. Sort the registers into order, and check that the memory | |
5686 | offsets are ascending and adjacent. */ | |
5687 | ||
5688 | for (i = 1; i < nops; i++) | |
5689 | { | |
5690 | int j; | |
5691 | ||
5692 | order[i] = order[i - 1]; | |
5693 | for (j = 0; j < nops; j++) | |
5694 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
5695 | && (order[i] == order[i - 1] | |
5696 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
5697 | order[i] = j; | |
5698 | ||
5699 | /* Have we found a suitable register? if not, one must be used more | |
5700 | than once. */ | |
5701 | if (order[i] == order[i - 1]) | |
5702 | return 0; | |
5703 | ||
5704 | /* Is the memory address adjacent and ascending? */ | |
5705 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
5706 | return 0; | |
5707 | } | |
5708 | ||
5709 | if (base) | |
5710 | { | |
5711 | *base = base_reg; | |
5712 | ||
5713 | for (i = 0; i < nops; i++) | |
5714 | regs[i] = unsorted_regs[order[i]]; | |
5715 | ||
5716 | *load_offset = unsorted_offsets[order[0]]; | |
5717 | } | |
5718 | ||
5719 | if (unsorted_offsets[order[0]] == 0) | |
5720 | return 1; /* stmia */ | |
5721 | ||
5722 | if (unsorted_offsets[order[0]] == 4) | |
5723 | return 2; /* stmib */ | |
5724 | ||
5725 | if (unsorted_offsets[order[nops - 1]] == 0) | |
5726 | return 3; /* stmda */ | |
5727 | ||
5728 | if (unsorted_offsets[order[nops - 1]] == -4) | |
5729 | return 4; /* stmdb */ | |
5730 | ||
5731 | return 0; | |
5732 | } | |
5733 | ||
cd2b33d0 | 5734 | const char * |
e32bac5b | 5735 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
5736 | { |
5737 | int regs[4]; | |
5738 | int base_reg; | |
5739 | HOST_WIDE_INT offset; | |
5740 | char buf[100]; | |
5741 | int i; | |
5742 | ||
5743 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
5744 | { | |
5745 | case 1: | |
5746 | strcpy (buf, "stm%?ia\t"); | |
5747 | break; | |
5748 | ||
5749 | case 2: | |
5750 | strcpy (buf, "stm%?ib\t"); | |
5751 | break; | |
5752 | ||
5753 | case 3: | |
5754 | strcpy (buf, "stm%?da\t"); | |
5755 | break; | |
5756 | ||
5757 | case 4: | |
5758 | strcpy (buf, "stm%?db\t"); | |
5759 | break; | |
5760 | ||
5761 | default: | |
5762 | abort (); | |
5763 | } | |
5764 | ||
5765 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, | |
5766 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); | |
5767 | ||
5768 | for (i = 1; i < nops; i++) | |
5769 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
5770 | reg_names[regs[i]]); | |
5771 | ||
5772 | strcat (buf, "}\t%@ phole stm"); | |
5773 | ||
5774 | output_asm_insn (buf, operands); | |
5775 | return ""; | |
5776 | } | |
5777 | ||
e2c671ba | 5778 | int |
e32bac5b | 5779 | multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e2c671ba RE |
5780 | { |
5781 | if (GET_CODE (op) != PARALLEL | |
5782 | || (GET_CODE (XVECEXP (op, 0, 0)) != SET) | |
5783 | || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) | |
b15bca31 | 5784 | || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) |
e2c671ba RE |
5785 | return 0; |
5786 | ||
5787 | return 1; | |
5788 | } | |
ff9940b0 | 5789 | \f |
6354dc9b | 5790 | /* Routines for use in generating RTL. */ |
1d6e90ac | 5791 | |
f3bb6135 | 5792 | rtx |
e32bac5b RE |
5793 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
5794 | int write_back, int unchanging_p, int in_struct_p, | |
5795 | int scalar_p) | |
ff9940b0 RE |
5796 | { |
5797 | int i = 0, j; | |
5798 | rtx result; | |
5799 | int sign = up ? 1 : -1; | |
56636818 | 5800 | rtx mem; |
ff9940b0 | 5801 | |
d19fb8e3 NC |
5802 | /* XScale has load-store double instructions, but they have stricter |
5803 | alignment requirements than load-store multiple, so we can not | |
5804 | use them. | |
5805 | ||
5806 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
5807 | the pipeline until completion. | |
5808 | ||
5809 | NREGS CYCLES | |
5810 | 1 3 | |
5811 | 2 4 | |
5812 | 3 5 | |
5813 | 4 6 | |
5814 | ||
5815 | An ldr instruction takes 1-3 cycles, but does not block the | |
5816 | pipeline. | |
5817 | ||
5818 | NREGS CYCLES | |
5819 | 1 1-3 | |
5820 | 2 2-6 | |
5821 | 3 3-9 | |
5822 | 4 4-12 | |
5823 | ||
5824 | Best case ldr will always win. However, the more ldr instructions | |
5825 | we issue, the less likely we are to be able to schedule them well. | |
5826 | Using ldr instructions also increases code size. | |
5827 | ||
5828 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
5829 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 5830 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
5831 | { |
5832 | rtx seq; | |
5833 | ||
5834 | start_sequence (); | |
5835 | ||
5836 | for (i = 0; i < count; i++) | |
5837 | { | |
5838 | mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign)); | |
5839 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5840 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5841 | MEM_SCALAR_P (mem) = scalar_p; | |
5842 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); | |
5843 | } | |
5844 | ||
5845 | if (write_back) | |
5846 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
5847 | ||
2f937369 | 5848 | seq = get_insns (); |
d19fb8e3 NC |
5849 | end_sequence (); |
5850 | ||
5851 | return seq; | |
5852 | } | |
5853 | ||
43cffd11 | 5854 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5855 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5856 | if (write_back) |
f3bb6135 | 5857 | { |
ff9940b0 | 5858 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5859 | = gen_rtx_SET (GET_MODE (from), from, |
5860 | plus_constant (from, count * 4 * sign)); | |
ff9940b0 RE |
5861 | i = 1; |
5862 | count++; | |
f3bb6135 RE |
5863 | } |
5864 | ||
ff9940b0 | 5865 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5866 | { |
43cffd11 | 5867 | mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); |
56636818 JL |
5868 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5869 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5870 | MEM_SCALAR_P (mem) = scalar_p; |
43cffd11 RE |
5871 | XVECEXP (result, 0, i) |
5872 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
f3bb6135 RE |
5873 | } |
5874 | ||
ff9940b0 RE |
5875 | return result; |
5876 | } | |
5877 | ||
f3bb6135 | 5878 | rtx |
e32bac5b RE |
5879 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
5880 | int write_back, int unchanging_p, int in_struct_p, | |
5881 | int scalar_p) | |
ff9940b0 RE |
5882 | { |
5883 | int i = 0, j; | |
5884 | rtx result; | |
5885 | int sign = up ? 1 : -1; | |
56636818 | 5886 | rtx mem; |
ff9940b0 | 5887 | |
d19fb8e3 NC |
5888 | /* See arm_gen_load_multiple for discussion of |
5889 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 5890 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
5891 | { |
5892 | rtx seq; | |
5893 | ||
5894 | start_sequence (); | |
5895 | ||
5896 | for (i = 0; i < count; i++) | |
5897 | { | |
5898 | mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign)); | |
5899 | RTX_UNCHANGING_P (mem) = unchanging_p; | |
5900 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
5901 | MEM_SCALAR_P (mem) = scalar_p; | |
5902 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); | |
5903 | } | |
5904 | ||
5905 | if (write_back) | |
5906 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
5907 | ||
2f937369 | 5908 | seq = get_insns (); |
d19fb8e3 NC |
5909 | end_sequence (); |
5910 | ||
5911 | return seq; | |
5912 | } | |
5913 | ||
43cffd11 | 5914 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 5915 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 5916 | if (write_back) |
f3bb6135 | 5917 | { |
ff9940b0 | 5918 | XVECEXP (result, 0, 0) |
43cffd11 RE |
5919 | = gen_rtx_SET (GET_MODE (to), to, |
5920 | plus_constant (to, count * 4 * sign)); | |
ff9940b0 RE |
5921 | i = 1; |
5922 | count++; | |
f3bb6135 RE |
5923 | } |
5924 | ||
ff9940b0 | 5925 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 5926 | { |
43cffd11 | 5927 | mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); |
56636818 JL |
5928 | RTX_UNCHANGING_P (mem) = unchanging_p; |
5929 | MEM_IN_STRUCT_P (mem) = in_struct_p; | |
c6df88cb | 5930 | MEM_SCALAR_P (mem) = scalar_p; |
56636818 | 5931 | |
43cffd11 RE |
5932 | XVECEXP (result, 0, i) |
5933 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
f3bb6135 RE |
5934 | } |
5935 | ||
ff9940b0 RE |
5936 | return result; |
5937 | } | |
5938 | ||
880e2516 | 5939 | int |
70128ad9 | 5940 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
5941 | { |
5942 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
ad076f4e | 5943 | int i; |
880e2516 | 5944 | rtx src, dst; |
ad076f4e | 5945 | rtx st_src, st_dst, fin_src, fin_dst; |
880e2516 | 5946 | rtx part_bytes_reg = NULL; |
56636818 JL |
5947 | rtx mem; |
5948 | int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; | |
c6df88cb | 5949 | int dst_scalar_p, src_scalar_p; |
880e2516 RE |
5950 | |
5951 | if (GET_CODE (operands[2]) != CONST_INT | |
5952 | || GET_CODE (operands[3]) != CONST_INT | |
5953 | || INTVAL (operands[2]) > 64 | |
5954 | || INTVAL (operands[3]) & 3) | |
5955 | return 0; | |
5956 | ||
5957 | st_dst = XEXP (operands[0], 0); | |
5958 | st_src = XEXP (operands[1], 0); | |
56636818 JL |
5959 | |
5960 | dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); | |
5961 | dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); | |
c6df88cb | 5962 | dst_scalar_p = MEM_SCALAR_P (operands[0]); |
56636818 JL |
5963 | src_unchanging_p = RTX_UNCHANGING_P (operands[1]); |
5964 | src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); | |
c6df88cb | 5965 | src_scalar_p = MEM_SCALAR_P (operands[1]); |
56636818 | 5966 | |
880e2516 RE |
5967 | fin_dst = dst = copy_to_mode_reg (SImode, st_dst); |
5968 | fin_src = src = copy_to_mode_reg (SImode, st_src); | |
5969 | ||
e9d7b180 | 5970 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
5971 | out_words_to_go = INTVAL (operands[2]) / 4; |
5972 | last_bytes = INTVAL (operands[2]) & 3; | |
5973 | ||
5974 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 5975 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
5976 | |
5977 | for (i = 0; in_words_to_go >= 2; i+=4) | |
5978 | { | |
bd9c7e23 | 5979 | if (in_words_to_go > 4) |
56636818 | 5980 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
c6df88cb MM |
5981 | src_unchanging_p, |
5982 | src_in_struct_p, | |
5983 | src_scalar_p)); | |
bd9c7e23 RE |
5984 | else |
5985 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, | |
56636818 | 5986 | FALSE, src_unchanging_p, |
c6df88cb | 5987 | src_in_struct_p, src_scalar_p)); |
bd9c7e23 | 5988 | |
880e2516 RE |
5989 | if (out_words_to_go) |
5990 | { | |
bd9c7e23 | 5991 | if (out_words_to_go > 4) |
56636818 JL |
5992 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
5993 | dst_unchanging_p, | |
c6df88cb MM |
5994 | dst_in_struct_p, |
5995 | dst_scalar_p)); | |
bd9c7e23 RE |
5996 | else if (out_words_to_go != 1) |
5997 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
5998 | dst, TRUE, | |
5999 | (last_bytes == 0 | |
56636818 JL |
6000 | ? FALSE : TRUE), |
6001 | dst_unchanging_p, | |
c6df88cb MM |
6002 | dst_in_struct_p, |
6003 | dst_scalar_p)); | |
880e2516 RE |
6004 | else |
6005 | { | |
43cffd11 | 6006 | mem = gen_rtx_MEM (SImode, dst); |
56636818 JL |
6007 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
6008 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 6009 | MEM_SCALAR_P (mem) = dst_scalar_p; |
43cffd11 | 6010 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 RE |
6011 | if (last_bytes != 0) |
6012 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
880e2516 RE |
6013 | } |
6014 | } | |
6015 | ||
6016 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
6017 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
6018 | } | |
6019 | ||
6020 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
6021 | if (out_words_to_go) | |
62b10bbc NC |
6022 | { |
6023 | rtx sreg; | |
6024 | ||
6025 | mem = gen_rtx_MEM (SImode, src); | |
6026 | RTX_UNCHANGING_P (mem) = src_unchanging_p; | |
6027 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
6028 | MEM_SCALAR_P (mem) = src_scalar_p; | |
6029 | emit_move_insn (sreg = gen_reg_rtx (SImode), mem); | |
6030 | emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); | |
6031 | ||
6032 | mem = gen_rtx_MEM (SImode, dst); | |
6033 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
6034 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
6035 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
6036 | emit_move_insn (mem, sreg); | |
6037 | emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); | |
6038 | in_words_to_go--; | |
6039 | ||
6040 | if (in_words_to_go) /* Sanity check */ | |
6041 | abort (); | |
6042 | } | |
880e2516 RE |
6043 | |
6044 | if (in_words_to_go) | |
6045 | { | |
6046 | if (in_words_to_go < 0) | |
6047 | abort (); | |
6048 | ||
43cffd11 | 6049 | mem = gen_rtx_MEM (SImode, src); |
56636818 JL |
6050 | RTX_UNCHANGING_P (mem) = src_unchanging_p; |
6051 | MEM_IN_STRUCT_P (mem) = src_in_struct_p; | |
c6df88cb | 6052 | MEM_SCALAR_P (mem) = src_scalar_p; |
56636818 | 6053 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
6054 | } |
6055 | ||
d5b7b3ae RE |
6056 | if (last_bytes && part_bytes_reg == NULL) |
6057 | abort (); | |
6058 | ||
880e2516 RE |
6059 | if (BYTES_BIG_ENDIAN && last_bytes) |
6060 | { | |
6061 | rtx tmp = gen_reg_rtx (SImode); | |
6062 | ||
6354dc9b | 6063 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
6064 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
6065 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 RE |
6066 | part_bytes_reg = tmp; |
6067 | ||
6068 | while (last_bytes) | |
6069 | { | |
43cffd11 | 6070 | mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); |
56636818 JL |
6071 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
6072 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 6073 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 BS |
6074 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
6075 | ||
880e2516 RE |
6076 | if (--last_bytes) |
6077 | { | |
6078 | tmp = gen_reg_rtx (SImode); | |
6079 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
6080 | part_bytes_reg = tmp; | |
6081 | } | |
6082 | } | |
6083 | ||
6084 | } | |
6085 | else | |
6086 | { | |
d5b7b3ae | 6087 | if (last_bytes > 1) |
880e2516 | 6088 | { |
d5b7b3ae | 6089 | mem = gen_rtx_MEM (HImode, dst); |
56636818 JL |
6090 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; |
6091 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
c6df88cb | 6092 | MEM_SCALAR_P (mem) = dst_scalar_p; |
5d5603e2 | 6093 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
6094 | last_bytes -= 2; |
6095 | if (last_bytes) | |
880e2516 RE |
6096 | { |
6097 | rtx tmp = gen_reg_rtx (SImode); | |
bd9c7e23 | 6098 | |
a556fd39 | 6099 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 6100 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 RE |
6101 | part_bytes_reg = tmp; |
6102 | } | |
6103 | } | |
d5b7b3ae RE |
6104 | |
6105 | if (last_bytes) | |
6106 | { | |
6107 | mem = gen_rtx_MEM (QImode, dst); | |
6108 | RTX_UNCHANGING_P (mem) = dst_unchanging_p; | |
6109 | MEM_IN_STRUCT_P (mem) = dst_in_struct_p; | |
6110 | MEM_SCALAR_P (mem) = dst_scalar_p; | |
5d5603e2 | 6111 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 6112 | } |
880e2516 RE |
6113 | } |
6114 | ||
6115 | return 1; | |
6116 | } | |
6117 | ||
5165176d RE |
6118 | /* Generate a memory reference for a half word, such that it will be loaded |
6119 | into the top 16 bits of the word. We can assume that the address is | |
6120 | known to be alignable and of the form reg, or plus (reg, const). */ | |
1d6e90ac | 6121 | |
5165176d | 6122 | rtx |
e32bac5b | 6123 | arm_gen_rotated_half_load (rtx memref) |
5165176d RE |
6124 | { |
6125 | HOST_WIDE_INT offset = 0; | |
6126 | rtx base = XEXP (memref, 0); | |
6127 | ||
6128 | if (GET_CODE (base) == PLUS) | |
6129 | { | |
6130 | offset = INTVAL (XEXP (base, 1)); | |
6131 | base = XEXP (base, 0); | |
6132 | } | |
6133 | ||
956d6950 | 6134 | /* If we aren't allowed to generate unaligned addresses, then fail. */ |
61f0ccff | 6135 | if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)) |
5165176d RE |
6136 | return NULL; |
6137 | ||
43cffd11 | 6138 | base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); |
5165176d RE |
6139 | |
6140 | if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) | |
6141 | return base; | |
6142 | ||
43cffd11 | 6143 | return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); |
5165176d RE |
6144 | } |
6145 | ||
03f1640c RE |
6146 | /* Select a dominance comparison mode if possible for a test of the general |
6147 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
6148 | COND_OR == DOM_CC_X_AND_Y => (X && Y) | |
6149 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) | |
6150 | COND_OR == DOM_CC_X_OR_Y => (X || Y) | |
6151 | In all cases OP will be either EQ or NE, but we don't need to know which | |
6152 | here. If we are unable to support a dominance comparison we return | |
6153 | CC mode. This will then fail to match for the RTL expressions that | |
6154 | generate this call. */ | |
03f1640c | 6155 | enum machine_mode |
e32bac5b | 6156 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
6157 | { |
6158 | enum rtx_code cond1, cond2; | |
6159 | int swapped = 0; | |
6160 | ||
6161 | /* Currently we will probably get the wrong result if the individual | |
6162 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 6163 | reverse a comparison if necessary. */ |
84ed5e79 RE |
6164 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
6165 | != CCmode) | |
6166 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
6167 | != CCmode)) | |
6168 | return CCmode; | |
6169 | ||
1646cf41 RE |
6170 | /* The if_then_else variant of this tests the second condition if the |
6171 | first passes, but is true if the first fails. Reverse the first | |
6172 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 6173 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
6174 | cond1 = reverse_condition (cond1); |
6175 | ||
6176 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
6177 | then we can't do this. */ | |
6178 | if (cond1 != cond2 | |
5895f793 RE |
6179 | && !comparison_dominates_p (cond1, cond2) |
6180 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
6181 | return CCmode; |
6182 | ||
6183 | if (swapped) | |
6184 | { | |
6185 | enum rtx_code temp = cond1; | |
6186 | cond1 = cond2; | |
6187 | cond2 = temp; | |
6188 | } | |
6189 | ||
6190 | switch (cond1) | |
6191 | { | |
6192 | case EQ: | |
03f1640c | 6193 | if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6194 | return CC_DEQmode; |
6195 | ||
6196 | switch (cond2) | |
6197 | { | |
6198 | case LE: return CC_DLEmode; | |
6199 | case LEU: return CC_DLEUmode; | |
6200 | case GE: return CC_DGEmode; | |
6201 | case GEU: return CC_DGEUmode; | |
ad076f4e | 6202 | default: break; |
84ed5e79 RE |
6203 | } |
6204 | ||
6205 | break; | |
6206 | ||
6207 | case LT: | |
03f1640c | 6208 | if (cond2 == LT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6209 | return CC_DLTmode; |
6210 | if (cond2 == LE) | |
6211 | return CC_DLEmode; | |
6212 | if (cond2 == NE) | |
6213 | return CC_DNEmode; | |
6214 | break; | |
6215 | ||
6216 | case GT: | |
03f1640c | 6217 | if (cond2 == GT || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6218 | return CC_DGTmode; |
6219 | if (cond2 == GE) | |
6220 | return CC_DGEmode; | |
6221 | if (cond2 == NE) | |
6222 | return CC_DNEmode; | |
6223 | break; | |
6224 | ||
6225 | case LTU: | |
03f1640c | 6226 | if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6227 | return CC_DLTUmode; |
6228 | if (cond2 == LEU) | |
6229 | return CC_DLEUmode; | |
6230 | if (cond2 == NE) | |
6231 | return CC_DNEmode; | |
6232 | break; | |
6233 | ||
6234 | case GTU: | |
03f1640c | 6235 | if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
6236 | return CC_DGTUmode; |
6237 | if (cond2 == GEU) | |
6238 | return CC_DGEUmode; | |
6239 | if (cond2 == NE) | |
6240 | return CC_DNEmode; | |
6241 | break; | |
6242 | ||
6243 | /* The remaining cases only occur when both comparisons are the | |
6244 | same. */ | |
6245 | case NE: | |
6246 | return CC_DNEmode; | |
6247 | ||
6248 | case LE: | |
6249 | return CC_DLEmode; | |
6250 | ||
6251 | case GE: | |
6252 | return CC_DGEmode; | |
6253 | ||
6254 | case LEU: | |
6255 | return CC_DLEUmode; | |
6256 | ||
6257 | case GEU: | |
6258 | return CC_DGEUmode; | |
ad076f4e RE |
6259 | |
6260 | default: | |
6261 | break; | |
84ed5e79 RE |
6262 | } |
6263 | ||
6264 | abort (); | |
6265 | } | |
6266 | ||
6267 | enum machine_mode | |
e32bac5b | 6268 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
6269 | { |
6270 | /* All floating point compares return CCFP if it is an equality | |
6271 | comparison, and CCFPE otherwise. */ | |
6272 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
6273 | { |
6274 | switch (op) | |
6275 | { | |
6276 | case EQ: | |
6277 | case NE: | |
6278 | case UNORDERED: | |
6279 | case ORDERED: | |
6280 | case UNLT: | |
6281 | case UNLE: | |
6282 | case UNGT: | |
6283 | case UNGE: | |
6284 | case UNEQ: | |
6285 | case LTGT: | |
6286 | return CCFPmode; | |
6287 | ||
6288 | case LT: | |
6289 | case LE: | |
6290 | case GT: | |
6291 | case GE: | |
9b66ebb1 | 6292 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 6293 | return CCFPmode; |
e45b72c4 RE |
6294 | return CCFPEmode; |
6295 | ||
6296 | default: | |
6297 | abort (); | |
6298 | } | |
6299 | } | |
84ed5e79 RE |
6300 | |
6301 | /* A compare with a shifted operand. Because of canonicalization, the | |
6302 | comparison will have to be swapped when we emit the assembler. */ | |
6303 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
6304 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
6305 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
6306 | || GET_CODE (x) == ROTATERT)) | |
6307 | return CC_SWPmode; | |
6308 | ||
956d6950 JL |
6309 | /* This is a special case that is used by combine to allow a |
6310 | comparison of a shifted byte load to be split into a zero-extend | |
84ed5e79 | 6311 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 6312 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
6313 | if (GET_MODE (x) == SImode |
6314 | && GET_CODE (x) == ASHIFT | |
6315 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
6316 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
6317 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
6318 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
6319 | && (op == EQ || op == NE | |
6320 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
6321 | && GET_CODE (y) == CONST_INT) | |
6322 | return CC_Zmode; | |
6323 | ||
1646cf41 RE |
6324 | /* A construct for a conditional compare, if the false arm contains |
6325 | 0, then both conditions must be true, otherwise either condition | |
6326 | must be true. Not all conditions are possible, so CCmode is | |
6327 | returned if it can't be done. */ | |
6328 | if (GET_CODE (x) == IF_THEN_ELSE | |
6329 | && (XEXP (x, 2) == const0_rtx | |
6330 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
6331 | && COMPARISON_P (XEXP (x, 0)) |
6332 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
6333 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
6334 | INTVAL (XEXP (x, 2))); | |
1646cf41 RE |
6335 | |
6336 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
6337 | if (GET_CODE (x) == AND | |
ec8e098d PB |
6338 | && COMPARISON_P (XEXP (x, 0)) |
6339 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
6340 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
6341 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
6342 | |
6343 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
6344 | && COMPARISON_P (XEXP (x, 0)) |
6345 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
6346 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
6347 | DOM_CC_X_OR_Y); | |
1646cf41 | 6348 | |
defc0463 RE |
6349 | /* An operation (on Thumb) where we want to test for a single bit. |
6350 | This is done by shifting that bit up into the top bit of a | |
6351 | scratch register; we can then branch on the sign bit. */ | |
6352 | if (TARGET_THUMB | |
6353 | && GET_MODE (x) == SImode | |
6354 | && (op == EQ || op == NE) | |
6355 | && (GET_CODE (x) == ZERO_EXTRACT)) | |
6356 | return CC_Nmode; | |
6357 | ||
84ed5e79 RE |
6358 | /* An operation that sets the condition codes as a side-effect, the |
6359 | V flag is not set correctly, so we can only use comparisons where | |
6360 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 6361 | instead.) */ |
84ed5e79 RE |
6362 | if (GET_MODE (x) == SImode |
6363 | && y == const0_rtx | |
6364 | && (op == EQ || op == NE || op == LT || op == GE) | |
6365 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
6366 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
6367 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
6368 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
6369 | || GET_CODE (x) == LSHIFTRT | |
6370 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 RE |
6371 | || GET_CODE (x) == ROTATERT |
6372 | || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT))) | |
84ed5e79 RE |
6373 | return CC_NOOVmode; |
6374 | ||
84ed5e79 RE |
6375 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
6376 | return CC_Zmode; | |
6377 | ||
bd9c7e23 RE |
6378 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
6379 | && GET_CODE (x) == PLUS | |
6380 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
6381 | return CC_Cmode; | |
6382 | ||
84ed5e79 RE |
6383 | return CCmode; |
6384 | } | |
6385 | ||
ff9940b0 RE |
6386 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
6387 | return the rtx for register 0 in the proper mode. FP means this is a | |
6388 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 6389 | rtx |
e32bac5b | 6390 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
6391 | { |
6392 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 6393 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 6394 | |
43cffd11 RE |
6395 | emit_insn (gen_rtx_SET (VOIDmode, cc_reg, |
6396 | gen_rtx_COMPARE (mode, x, y))); | |
ff9940b0 RE |
6397 | |
6398 | return cc_reg; | |
6399 | } | |
6400 | ||
fcd53748 JT |
6401 | /* Generate a sequence of insns that will generate the correct return |
6402 | address mask depending on the physical architecture that the program | |
6403 | is running on. */ | |
fcd53748 | 6404 | rtx |
e32bac5b | 6405 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
6406 | { |
6407 | rtx reg = gen_reg_rtx (Pmode); | |
6408 | ||
6409 | emit_insn (gen_return_addr_mask (reg)); | |
6410 | return reg; | |
6411 | } | |
6412 | ||
0a81f500 | 6413 | void |
e32bac5b | 6414 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 6415 | { |
f9cc092a RE |
6416 | rtx ref = operands[1]; |
6417 | rtx base, scratch; | |
6418 | HOST_WIDE_INT offset = 0; | |
6419 | ||
6420 | if (GET_CODE (ref) == SUBREG) | |
6421 | { | |
ddef6bc7 | 6422 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
6423 | ref = SUBREG_REG (ref); |
6424 | } | |
6425 | ||
6426 | if (GET_CODE (ref) == REG) | |
6427 | { | |
6428 | /* We have a pseudo which has been spilt onto the stack; there | |
6429 | are two cases here: the first where there is a simple | |
6430 | stack-slot replacement and a second where the stack-slot is | |
6431 | out of range, or is used as a subreg. */ | |
6432 | if (reg_equiv_mem[REGNO (ref)]) | |
6433 | { | |
6434 | ref = reg_equiv_mem[REGNO (ref)]; | |
6435 | base = find_replacement (&XEXP (ref, 0)); | |
6436 | } | |
6437 | else | |
6354dc9b | 6438 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
6439 | base = reg_equiv_address[REGNO (ref)]; |
6440 | } | |
6441 | else | |
6442 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 6443 | |
e5e809f4 JL |
6444 | /* Handle the case where the address is too complex to be offset by 1. */ |
6445 | if (GET_CODE (base) == MINUS | |
6446 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
6447 | { | |
f9cc092a | 6448 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 6449 | |
43cffd11 | 6450 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); |
e5e809f4 JL |
6451 | base = base_plus; |
6452 | } | |
f9cc092a RE |
6453 | else if (GET_CODE (base) == PLUS) |
6454 | { | |
6354dc9b | 6455 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
6456 | HOST_WIDE_INT hi, lo; |
6457 | ||
6458 | offset += INTVAL (XEXP (base, 1)); | |
6459 | base = XEXP (base, 0); | |
6460 | ||
6354dc9b | 6461 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
6462 | /* Valid range for lo is -4095 -> 4095 */ |
6463 | lo = (offset >= 0 | |
6464 | ? (offset & 0xfff) | |
6465 | : -((-offset) & 0xfff)); | |
6466 | ||
6467 | /* Corner case, if lo is the max offset then we would be out of range | |
6468 | once we have added the additional 1 below, so bump the msb into the | |
6469 | pre-loading insn(s). */ | |
6470 | if (lo == 4095) | |
6471 | lo &= 0x7ff; | |
6472 | ||
30cf4896 KG |
6473 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
6474 | ^ (HOST_WIDE_INT) 0x80000000) | |
6475 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
6476 | |
6477 | if (hi + lo != offset) | |
6478 | abort (); | |
6479 | ||
6480 | if (hi != 0) | |
6481 | { | |
6482 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6483 | ||
6484 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 6485 | that require more than one insn. */ |
f9cc092a RE |
6486 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
6487 | base = base_plus; | |
6488 | offset = lo; | |
6489 | } | |
6490 | } | |
e5e809f4 | 6491 | |
3a1944a6 RE |
6492 | /* Operands[2] may overlap operands[0] (though it won't overlap |
6493 | operands[1]), that's why we asked for a DImode reg -- so we can | |
6494 | use the bit that does not overlap. */ | |
6495 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
6496 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6497 | else | |
6498 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
6499 | ||
f9cc092a RE |
6500 | emit_insn (gen_zero_extendqisi2 (scratch, |
6501 | gen_rtx_MEM (QImode, | |
6502 | plus_constant (base, | |
6503 | offset)))); | |
43cffd11 RE |
6504 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
6505 | gen_rtx_MEM (QImode, | |
f9cc092a RE |
6506 | plus_constant (base, |
6507 | offset + 1)))); | |
5895f793 | 6508 | if (!BYTES_BIG_ENDIAN) |
43cffd11 RE |
6509 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
6510 | gen_rtx_IOR (SImode, | |
6511 | gen_rtx_ASHIFT | |
6512 | (SImode, | |
6513 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
6514 | GEN_INT (8)), | |
f9cc092a | 6515 | scratch))); |
0a81f500 | 6516 | else |
43cffd11 RE |
6517 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), |
6518 | gen_rtx_IOR (SImode, | |
f9cc092a | 6519 | gen_rtx_ASHIFT (SImode, scratch, |
43cffd11 RE |
6520 | GEN_INT (8)), |
6521 | gen_rtx_SUBREG (SImode, operands[0], | |
6522 | 0)))); | |
0a81f500 RE |
6523 | } |
6524 | ||
72ac76be | 6525 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
6526 | byte stores. Take care not to clobber the input values until after we |
6527 | have moved them somewhere safe. This code assumes that if the DImode | |
6528 | scratch in operands[2] overlaps either the input value or output address | |
6529 | in some way, then that value must die in this insn (we absolutely need | |
6530 | two scratch registers for some corner cases). */ | |
f3bb6135 | 6531 | void |
e32bac5b | 6532 | arm_reload_out_hi (rtx *operands) |
af48348a | 6533 | { |
f9cc092a RE |
6534 | rtx ref = operands[0]; |
6535 | rtx outval = operands[1]; | |
6536 | rtx base, scratch; | |
6537 | HOST_WIDE_INT offset = 0; | |
6538 | ||
6539 | if (GET_CODE (ref) == SUBREG) | |
6540 | { | |
ddef6bc7 | 6541 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
6542 | ref = SUBREG_REG (ref); |
6543 | } | |
6544 | ||
f9cc092a RE |
6545 | if (GET_CODE (ref) == REG) |
6546 | { | |
6547 | /* We have a pseudo which has been spilt onto the stack; there | |
6548 | are two cases here: the first where there is a simple | |
6549 | stack-slot replacement and a second where the stack-slot is | |
6550 | out of range, or is used as a subreg. */ | |
6551 | if (reg_equiv_mem[REGNO (ref)]) | |
6552 | { | |
6553 | ref = reg_equiv_mem[REGNO (ref)]; | |
6554 | base = find_replacement (&XEXP (ref, 0)); | |
6555 | } | |
6556 | else | |
6354dc9b | 6557 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
6558 | base = reg_equiv_address[REGNO (ref)]; |
6559 | } | |
6560 | else | |
6561 | base = find_replacement (&XEXP (ref, 0)); | |
6562 | ||
6563 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
6564 | ||
6565 | /* Handle the case where the address is too complex to be offset by 1. */ | |
6566 | if (GET_CODE (base) == MINUS | |
6567 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
6568 | { | |
6569 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6570 | ||
6571 | /* Be careful not to destroy OUTVAL. */ | |
6572 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
6573 | { | |
6574 | /* Updating base_plus might destroy outval, see if we can | |
6575 | swap the scratch and base_plus. */ | |
5895f793 | 6576 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
6577 | { |
6578 | rtx tmp = scratch; | |
6579 | scratch = base_plus; | |
6580 | base_plus = tmp; | |
6581 | } | |
6582 | else | |
6583 | { | |
6584 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
6585 | ||
6586 | /* Be conservative and copy OUTVAL into the scratch now, | |
6587 | this should only be necessary if outval is a subreg | |
6588 | of something larger than a word. */ | |
6589 | /* XXX Might this clobber base? I can't see how it can, | |
6590 | since scratch is known to overlap with OUTVAL, and | |
6591 | must be wider than a word. */ | |
6592 | emit_insn (gen_movhi (scratch_hi, outval)); | |
6593 | outval = scratch_hi; | |
6594 | } | |
6595 | } | |
6596 | ||
6597 | emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); | |
6598 | base = base_plus; | |
6599 | } | |
6600 | else if (GET_CODE (base) == PLUS) | |
6601 | { | |
6354dc9b | 6602 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
6603 | HOST_WIDE_INT hi, lo; |
6604 | ||
6605 | offset += INTVAL (XEXP (base, 1)); | |
6606 | base = XEXP (base, 0); | |
6607 | ||
6354dc9b | 6608 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
6609 | /* Valid range for lo is -4095 -> 4095 */ |
6610 | lo = (offset >= 0 | |
6611 | ? (offset & 0xfff) | |
6612 | : -((-offset) & 0xfff)); | |
6613 | ||
6614 | /* Corner case, if lo is the max offset then we would be out of range | |
6615 | once we have added the additional 1 below, so bump the msb into the | |
6616 | pre-loading insn(s). */ | |
6617 | if (lo == 4095) | |
6618 | lo &= 0x7ff; | |
6619 | ||
30cf4896 KG |
6620 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
6621 | ^ (HOST_WIDE_INT) 0x80000000) | |
6622 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a RE |
6623 | |
6624 | if (hi + lo != offset) | |
6625 | abort (); | |
6626 | ||
6627 | if (hi != 0) | |
6628 | { | |
6629 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
6630 | ||
6631 | /* Be careful not to destroy OUTVAL. */ | |
6632 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
6633 | { | |
6634 | /* Updating base_plus might destroy outval, see if we | |
6635 | can swap the scratch and base_plus. */ | |
5895f793 | 6636 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
6637 | { |
6638 | rtx tmp = scratch; | |
6639 | scratch = base_plus; | |
6640 | base_plus = tmp; | |
6641 | } | |
6642 | else | |
6643 | { | |
6644 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
6645 | ||
6646 | /* Be conservative and copy outval into scratch now, | |
6647 | this should only be necessary if outval is a | |
6648 | subreg of something larger than a word. */ | |
6649 | /* XXX Might this clobber base? I can't see how it | |
6650 | can, since scratch is known to overlap with | |
6651 | outval. */ | |
6652 | emit_insn (gen_movhi (scratch_hi, outval)); | |
6653 | outval = scratch_hi; | |
6654 | } | |
6655 | } | |
6656 | ||
6657 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 6658 | that require more than one insn. */ |
f9cc092a RE |
6659 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
6660 | base = base_plus; | |
6661 | offset = lo; | |
6662 | } | |
6663 | } | |
af48348a | 6664 | |
b5cc037f RE |
6665 | if (BYTES_BIG_ENDIAN) |
6666 | { | |
f9cc092a RE |
6667 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
6668 | plus_constant (base, offset + 1)), | |
5d5603e2 | 6669 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
6670 | emit_insn (gen_lshrsi3 (scratch, |
6671 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 6672 | GEN_INT (8))); |
f9cc092a | 6673 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 6674 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
6675 | } |
6676 | else | |
6677 | { | |
f9cc092a | 6678 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 6679 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
6680 | emit_insn (gen_lshrsi3 (scratch, |
6681 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 6682 | GEN_INT (8))); |
f9cc092a RE |
6683 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
6684 | plus_constant (base, offset + 1)), | |
5d5603e2 | 6685 | gen_lowpart (QImode, scratch))); |
b5cc037f | 6686 | } |
af48348a | 6687 | } |
2b835d68 | 6688 | \f |
d5b7b3ae RE |
6689 | /* Print a symbolic form of X to the debug file, F. */ |
6690 | static void | |
e32bac5b | 6691 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
6692 | { |
6693 | switch (GET_CODE (x)) | |
6694 | { | |
6695 | case CONST_INT: | |
6696 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
6697 | return; | |
6698 | ||
6699 | case CONST_DOUBLE: | |
6700 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
6701 | return; | |
6702 | ||
5a9335ef NC |
6703 | case CONST_VECTOR: |
6704 | { | |
6705 | int i; | |
6706 | ||
6707 | fprintf (f, "<"); | |
6708 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
6709 | { | |
6710 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
6711 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
6712 | fputc (',', f); | |
6713 | } | |
6714 | fprintf (f, ">"); | |
6715 | } | |
6716 | return; | |
6717 | ||
d5b7b3ae RE |
6718 | case CONST_STRING: |
6719 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
6720 | return; | |
6721 | ||
6722 | case SYMBOL_REF: | |
6723 | fprintf (f, "`%s'", XSTR (x, 0)); | |
6724 | return; | |
6725 | ||
6726 | case LABEL_REF: | |
6727 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
6728 | return; | |
6729 | ||
6730 | case CONST: | |
6731 | arm_print_value (f, XEXP (x, 0)); | |
6732 | return; | |
6733 | ||
6734 | case PLUS: | |
6735 | arm_print_value (f, XEXP (x, 0)); | |
6736 | fprintf (f, "+"); | |
6737 | arm_print_value (f, XEXP (x, 1)); | |
6738 | return; | |
6739 | ||
6740 | case PC: | |
6741 | fprintf (f, "pc"); | |
6742 | return; | |
6743 | ||
6744 | default: | |
6745 | fprintf (f, "????"); | |
6746 | return; | |
6747 | } | |
6748 | } | |
6749 | \f | |
2b835d68 | 6750 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 6751 | |
949d79eb RE |
6752 | /* Arm instructions cannot load a large constant directly into a |
6753 | register; they have to come from a pc relative load. The constant | |
6754 | must therefore be placed in the addressable range of the pc | |
6755 | relative load. Depending on the precise pc relative load | |
6756 | instruction the range is somewhere between 256 bytes and 4k. This | |
6757 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
6758 | generate code to branch around it. |
6759 | ||
949d79eb RE |
6760 | It is important to minimize this, since the branches will slow |
6761 | things down and make the code larger. | |
2b835d68 | 6762 | |
949d79eb RE |
6763 | Normally we can hide the table after an existing unconditional |
6764 | branch so that there is no interruption of the flow, but in the | |
6765 | worst case the code looks like this: | |
2b835d68 RE |
6766 | |
6767 | ldr rn, L1 | |
949d79eb | 6768 | ... |
2b835d68 RE |
6769 | b L2 |
6770 | align | |
6771 | L1: .long value | |
6772 | L2: | |
949d79eb | 6773 | ... |
2b835d68 | 6774 | |
2b835d68 | 6775 | ldr rn, L3 |
949d79eb | 6776 | ... |
2b835d68 RE |
6777 | b L4 |
6778 | align | |
2b835d68 RE |
6779 | L3: .long value |
6780 | L4: | |
949d79eb RE |
6781 | ... |
6782 | ||
6783 | We fix this by performing a scan after scheduling, which notices | |
6784 | which instructions need to have their operands fetched from the | |
6785 | constant table and builds the table. | |
6786 | ||
6787 | The algorithm starts by building a table of all the constants that | |
6788 | need fixing up and all the natural barriers in the function (places | |
6789 | where a constant table can be dropped without breaking the flow). | |
6790 | For each fixup we note how far the pc-relative replacement will be | |
6791 | able to reach and the offset of the instruction into the function. | |
6792 | ||
6793 | Having built the table we then group the fixes together to form | |
6794 | tables that are as large as possible (subject to addressing | |
6795 | constraints) and emit each table of constants after the last | |
6796 | barrier that is within range of all the instructions in the group. | |
6797 | If a group does not contain a barrier, then we forcibly create one | |
6798 | by inserting a jump instruction into the flow. Once the table has | |
6799 | been inserted, the insns are then modified to reference the | |
6800 | relevant entry in the pool. | |
6801 | ||
6354dc9b | 6802 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 6803 | |
d5b7b3ae | 6804 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
6805 | aligning the pools to the start of cache lines; this alignment |
6806 | would need to be taken into account when calculating addressability | |
6354dc9b | 6807 | of a pool. */ |
2b835d68 | 6808 | |
d5b7b3ae RE |
6809 | /* These typedefs are located at the start of this file, so that |
6810 | they can be used in the prototypes there. This comment is to | |
6811 | remind readers of that fact so that the following structures | |
6812 | can be understood more easily. | |
6813 | ||
6814 | typedef struct minipool_node Mnode; | |
6815 | typedef struct minipool_fixup Mfix; */ | |
6816 | ||
6817 | struct minipool_node | |
6818 | { | |
6819 | /* Doubly linked chain of entries. */ | |
6820 | Mnode * next; | |
6821 | Mnode * prev; | |
6822 | /* The maximum offset into the code that this entry can be placed. While | |
6823 | pushing fixes for forward references, all entries are sorted in order | |
6824 | of increasing max_address. */ | |
6825 | HOST_WIDE_INT max_address; | |
5519a4f9 | 6826 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
6827 | HOST_WIDE_INT min_address; |
6828 | /* The number of fixes referencing this entry. This can become zero | |
6829 | if we "unpush" an entry. In this case we ignore the entry when we | |
6830 | come to emit the code. */ | |
6831 | int refcount; | |
6832 | /* The offset from the start of the minipool. */ | |
6833 | HOST_WIDE_INT offset; | |
6834 | /* The value in table. */ | |
6835 | rtx value; | |
6836 | /* The mode of value. */ | |
6837 | enum machine_mode mode; | |
5a9335ef NC |
6838 | /* The size of the value. With iWMMXt enabled |
6839 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
6840 | int fix_size; |
6841 | }; | |
6842 | ||
6843 | struct minipool_fixup | |
2b835d68 | 6844 | { |
d5b7b3ae RE |
6845 | Mfix * next; |
6846 | rtx insn; | |
6847 | HOST_WIDE_INT address; | |
6848 | rtx * loc; | |
6849 | enum machine_mode mode; | |
6850 | int fix_size; | |
6851 | rtx value; | |
6852 | Mnode * minipool; | |
6853 | HOST_WIDE_INT forwards; | |
6854 | HOST_WIDE_INT backwards; | |
6855 | }; | |
2b835d68 | 6856 | |
d5b7b3ae RE |
6857 | /* Fixes less than a word need padding out to a word boundary. */ |
6858 | #define MINIPOOL_FIX_SIZE(mode) \ | |
6859 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 6860 | |
d5b7b3ae RE |
6861 | static Mnode * minipool_vector_head; |
6862 | static Mnode * minipool_vector_tail; | |
6863 | static rtx minipool_vector_label; | |
332072db | 6864 | |
d5b7b3ae RE |
6865 | /* The linked list of all minipool fixes required for this function. */ |
6866 | Mfix * minipool_fix_head; | |
6867 | Mfix * minipool_fix_tail; | |
6868 | /* The fix entry for the current minipool, once it has been placed. */ | |
6869 | Mfix * minipool_barrier; | |
6870 | ||
6871 | /* Determines if INSN is the start of a jump table. Returns the end | |
6872 | of the TABLE or NULL_RTX. */ | |
6873 | static rtx | |
e32bac5b | 6874 | is_jump_table (rtx insn) |
2b835d68 | 6875 | { |
d5b7b3ae | 6876 | rtx table; |
da6558fd | 6877 | |
d5b7b3ae RE |
6878 | if (GET_CODE (insn) == JUMP_INSN |
6879 | && JUMP_LABEL (insn) != NULL | |
6880 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
6881 | == next_real_insn (insn)) | |
6882 | && table != NULL | |
6883 | && GET_CODE (table) == JUMP_INSN | |
6884 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
6885 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
6886 | return table; | |
6887 | ||
6888 | return NULL_RTX; | |
2b835d68 RE |
6889 | } |
6890 | ||
657d9449 RE |
6891 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
6892 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
6893 | #endif | |
6894 | ||
d5b7b3ae | 6895 | static HOST_WIDE_INT |
e32bac5b | 6896 | get_jump_table_size (rtx insn) |
2b835d68 | 6897 | { |
657d9449 RE |
6898 | /* ADDR_VECs only take room if read-only data does into the text |
6899 | section. */ | |
6900 | if (JUMP_TABLES_IN_TEXT_SECTION | |
d48bc59a | 6901 | #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP) |
657d9449 RE |
6902 | || 1 |
6903 | #endif | |
6904 | ) | |
6905 | { | |
6906 | rtx body = PATTERN (insn); | |
6907 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
2b835d68 | 6908 | |
657d9449 RE |
6909 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); |
6910 | } | |
6911 | ||
6912 | return 0; | |
d5b7b3ae | 6913 | } |
2b835d68 | 6914 | |
d5b7b3ae RE |
6915 | /* Move a minipool fix MP from its current location to before MAX_MP. |
6916 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 6917 | constraints may need updating. */ |
d5b7b3ae | 6918 | static Mnode * |
e32bac5b RE |
6919 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
6920 | HOST_WIDE_INT max_address) | |
d5b7b3ae RE |
6921 | { |
6922 | /* This should never be true and the code below assumes these are | |
6923 | different. */ | |
6924 | if (mp == max_mp) | |
6925 | abort (); | |
6926 | ||
6927 | if (max_mp == NULL) | |
6928 | { | |
6929 | if (max_address < mp->max_address) | |
6930 | mp->max_address = max_address; | |
6931 | } | |
6932 | else | |
2b835d68 | 6933 | { |
d5b7b3ae RE |
6934 | if (max_address > max_mp->max_address - mp->fix_size) |
6935 | mp->max_address = max_mp->max_address - mp->fix_size; | |
6936 | else | |
6937 | mp->max_address = max_address; | |
2b835d68 | 6938 | |
d5b7b3ae RE |
6939 | /* Unlink MP from its current position. Since max_mp is non-null, |
6940 | mp->prev must be non-null. */ | |
6941 | mp->prev->next = mp->next; | |
6942 | if (mp->next != NULL) | |
6943 | mp->next->prev = mp->prev; | |
6944 | else | |
6945 | minipool_vector_tail = mp->prev; | |
2b835d68 | 6946 | |
d5b7b3ae RE |
6947 | /* Re-insert it before MAX_MP. */ |
6948 | mp->next = max_mp; | |
6949 | mp->prev = max_mp->prev; | |
6950 | max_mp->prev = mp; | |
6951 | ||
6952 | if (mp->prev != NULL) | |
6953 | mp->prev->next = mp; | |
6954 | else | |
6955 | minipool_vector_head = mp; | |
6956 | } | |
2b835d68 | 6957 | |
d5b7b3ae RE |
6958 | /* Save the new entry. */ |
6959 | max_mp = mp; | |
6960 | ||
d6a7951f | 6961 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
6962 | required. */ |
6963 | while (mp->prev != NULL | |
6964 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
6965 | { | |
6966 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
6967 | mp = mp->prev; | |
2b835d68 RE |
6968 | } |
6969 | ||
d5b7b3ae | 6970 | return max_mp; |
2b835d68 RE |
6971 | } |
6972 | ||
d5b7b3ae RE |
6973 | /* Add a constant to the minipool for a forward reference. Returns the |
6974 | node added or NULL if the constant will not fit in this pool. */ | |
6975 | static Mnode * | |
e32bac5b | 6976 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
6977 | { |
6978 | /* If set, max_mp is the first pool_entry that has a lower | |
6979 | constraint than the one we are trying to add. */ | |
6980 | Mnode * max_mp = NULL; | |
6981 | HOST_WIDE_INT max_address = fix->address + fix->forwards; | |
6982 | Mnode * mp; | |
6983 | ||
6984 | /* If this fix's address is greater than the address of the first | |
6985 | entry, then we can't put the fix in this pool. We subtract the | |
6986 | size of the current fix to ensure that if the table is fully | |
6987 | packed we still have enough room to insert this value by suffling | |
6988 | the other fixes forwards. */ | |
6989 | if (minipool_vector_head && | |
6990 | fix->address >= minipool_vector_head->max_address - fix->fix_size) | |
6991 | return NULL; | |
2b835d68 | 6992 | |
d5b7b3ae RE |
6993 | /* Scan the pool to see if a constant with the same value has |
6994 | already been added. While we are doing this, also note the | |
6995 | location where we must insert the constant if it doesn't already | |
6996 | exist. */ | |
6997 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
6998 | { | |
6999 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
7000 | && fix->mode == mp->mode | |
7001 | && (GET_CODE (fix->value) != CODE_LABEL | |
7002 | || (CODE_LABEL_NUMBER (fix->value) | |
7003 | == CODE_LABEL_NUMBER (mp->value))) | |
7004 | && rtx_equal_p (fix->value, mp->value)) | |
7005 | { | |
7006 | /* More than one fix references this entry. */ | |
7007 | mp->refcount++; | |
7008 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
7009 | } | |
7010 | ||
7011 | /* Note the insertion point if necessary. */ | |
7012 | if (max_mp == NULL | |
7013 | && mp->max_address > max_address) | |
7014 | max_mp = mp; | |
5a9335ef NC |
7015 | |
7016 | /* If we are inserting an 8-bytes aligned quantity and | |
7017 | we have not already found an insertion point, then | |
7018 | make sure that all such 8-byte aligned quantities are | |
7019 | placed at the start of the pool. */ | |
5848830f | 7020 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef NC |
7021 | && max_mp == NULL |
7022 | && fix->fix_size == 8 | |
7023 | && mp->fix_size != 8) | |
7024 | { | |
7025 | max_mp = mp; | |
7026 | max_address = mp->max_address; | |
7027 | } | |
d5b7b3ae RE |
7028 | } |
7029 | ||
7030 | /* The value is not currently in the minipool, so we need to create | |
7031 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
7032 | the end of the list since the placement is less constrained than | |
7033 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 7034 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae RE |
7035 | entries. */ |
7036 | mp = xmalloc (sizeof (* mp)); | |
7037 | mp->fix_size = fix->fix_size; | |
7038 | mp->mode = fix->mode; | |
7039 | mp->value = fix->value; | |
7040 | mp->refcount = 1; | |
7041 | /* Not yet required for a backwards ref. */ | |
7042 | mp->min_address = -65536; | |
7043 | ||
7044 | if (max_mp == NULL) | |
7045 | { | |
7046 | mp->max_address = max_address; | |
7047 | mp->next = NULL; | |
7048 | mp->prev = minipool_vector_tail; | |
7049 | ||
7050 | if (mp->prev == NULL) | |
7051 | { | |
7052 | minipool_vector_head = mp; | |
7053 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 7054 | } |
2b835d68 | 7055 | else |
d5b7b3ae | 7056 | mp->prev->next = mp; |
2b835d68 | 7057 | |
d5b7b3ae RE |
7058 | minipool_vector_tail = mp; |
7059 | } | |
7060 | else | |
7061 | { | |
7062 | if (max_address > max_mp->max_address - mp->fix_size) | |
7063 | mp->max_address = max_mp->max_address - mp->fix_size; | |
7064 | else | |
7065 | mp->max_address = max_address; | |
7066 | ||
7067 | mp->next = max_mp; | |
7068 | mp->prev = max_mp->prev; | |
7069 | max_mp->prev = mp; | |
7070 | if (mp->prev != NULL) | |
7071 | mp->prev->next = mp; | |
7072 | else | |
7073 | minipool_vector_head = mp; | |
7074 | } | |
7075 | ||
7076 | /* Save the new entry. */ | |
7077 | max_mp = mp; | |
7078 | ||
d6a7951f | 7079 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
7080 | required. */ |
7081 | while (mp->prev != NULL | |
7082 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
7083 | { | |
7084 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
7085 | mp = mp->prev; | |
2b835d68 RE |
7086 | } |
7087 | ||
d5b7b3ae RE |
7088 | return max_mp; |
7089 | } | |
7090 | ||
7091 | static Mnode * | |
e32bac5b RE |
7092 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
7093 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
7094 | { |
7095 | HOST_WIDE_INT offset; | |
7096 | ||
7097 | /* This should never be true, and the code below assumes these are | |
7098 | different. */ | |
7099 | if (mp == min_mp) | |
7100 | abort (); | |
7101 | ||
7102 | if (min_mp == NULL) | |
2b835d68 | 7103 | { |
d5b7b3ae RE |
7104 | if (min_address > mp->min_address) |
7105 | mp->min_address = min_address; | |
7106 | } | |
7107 | else | |
7108 | { | |
7109 | /* We will adjust this below if it is too loose. */ | |
7110 | mp->min_address = min_address; | |
7111 | ||
7112 | /* Unlink MP from its current position. Since min_mp is non-null, | |
7113 | mp->next must be non-null. */ | |
7114 | mp->next->prev = mp->prev; | |
7115 | if (mp->prev != NULL) | |
7116 | mp->prev->next = mp->next; | |
7117 | else | |
7118 | minipool_vector_head = mp->next; | |
7119 | ||
7120 | /* Reinsert it after MIN_MP. */ | |
7121 | mp->prev = min_mp; | |
7122 | mp->next = min_mp->next; | |
7123 | min_mp->next = mp; | |
7124 | if (mp->next != NULL) | |
7125 | mp->next->prev = mp; | |
2b835d68 | 7126 | else |
d5b7b3ae RE |
7127 | minipool_vector_tail = mp; |
7128 | } | |
7129 | ||
7130 | min_mp = mp; | |
7131 | ||
7132 | offset = 0; | |
7133 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
7134 | { | |
7135 | mp->offset = offset; | |
7136 | if (mp->refcount > 0) | |
7137 | offset += mp->fix_size; | |
7138 | ||
7139 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
7140 | mp->next->min_address = mp->min_address + mp->fix_size; | |
7141 | } | |
7142 | ||
7143 | return min_mp; | |
7144 | } | |
7145 | ||
7146 | /* Add a constant to the minipool for a backward reference. Returns the | |
7147 | node added or NULL if the constant will not fit in this pool. | |
7148 | ||
7149 | Note that the code for insertion for a backwards reference can be | |
7150 | somewhat confusing because the calculated offsets for each fix do | |
7151 | not take into account the size of the pool (which is still under | |
7152 | construction. */ | |
7153 | static Mnode * | |
e32bac5b | 7154 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
7155 | { |
7156 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
7157 | than the one we are trying to add. */ | |
e32bac5b | 7158 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
7159 | /* This can be negative, since it is only a constraint. */ |
7160 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 7161 | Mnode *mp; |
d5b7b3ae RE |
7162 | |
7163 | /* If we can't reach the current pool from this insn, or if we can't | |
7164 | insert this entry at the end of the pool without pushing other | |
7165 | fixes out of range, then we don't try. This ensures that we | |
7166 | can't fail later on. */ | |
7167 | if (min_address >= minipool_barrier->address | |
7168 | || (minipool_vector_tail->min_address + fix->fix_size | |
7169 | >= minipool_barrier->address)) | |
7170 | return NULL; | |
7171 | ||
7172 | /* Scan the pool to see if a constant with the same value has | |
7173 | already been added. While we are doing this, also note the | |
7174 | location where we must insert the constant if it doesn't already | |
7175 | exist. */ | |
7176 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
7177 | { | |
7178 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
7179 | && fix->mode == mp->mode | |
7180 | && (GET_CODE (fix->value) != CODE_LABEL | |
7181 | || (CODE_LABEL_NUMBER (fix->value) | |
7182 | == CODE_LABEL_NUMBER (mp->value))) | |
7183 | && rtx_equal_p (fix->value, mp->value) | |
7184 | /* Check that there is enough slack to move this entry to the | |
7185 | end of the table (this is conservative). */ | |
7186 | && (mp->max_address | |
7187 | > (minipool_barrier->address | |
7188 | + minipool_vector_tail->offset | |
7189 | + minipool_vector_tail->fix_size))) | |
7190 | { | |
7191 | mp->refcount++; | |
7192 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
7193 | } | |
7194 | ||
7195 | if (min_mp != NULL) | |
7196 | mp->min_address += fix->fix_size; | |
7197 | else | |
7198 | { | |
7199 | /* Note the insertion point if necessary. */ | |
7200 | if (mp->min_address < min_address) | |
5a9335ef NC |
7201 | { |
7202 | /* For now, we do not allow the insertion of 8-byte alignment | |
7203 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f PB |
7204 | if (ARM_DOUBLEWORD_ALIGN |
7205 | && fix->fix_size == 8 && mp->fix_size != 8) | |
5a9335ef NC |
7206 | return NULL; |
7207 | else | |
7208 | min_mp = mp; | |
7209 | } | |
d5b7b3ae RE |
7210 | else if (mp->max_address |
7211 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
7212 | { | |
7213 | /* Inserting before this entry would push the fix beyond | |
7214 | its maximum address (which can happen if we have | |
7215 | re-located a forwards fix); force the new fix to come | |
7216 | after it. */ | |
7217 | min_mp = mp; | |
7218 | min_address = mp->min_address + fix->fix_size; | |
7219 | } | |
5a9335ef NC |
7220 | /* If we are inserting an 8-bytes aligned quantity and |
7221 | we have not already found an insertion point, then | |
7222 | make sure that all such 8-byte aligned quantities are | |
7223 | placed at the start of the pool. */ | |
5848830f | 7224 | else if (ARM_DOUBLEWORD_ALIGN |
5a9335ef NC |
7225 | && min_mp == NULL |
7226 | && fix->fix_size == 8 | |
7227 | && mp->fix_size < 8) | |
7228 | { | |
7229 | min_mp = mp; | |
7230 | min_address = mp->min_address + fix->fix_size; | |
7231 | } | |
d5b7b3ae RE |
7232 | } |
7233 | } | |
7234 | ||
7235 | /* We need to create a new entry. */ | |
7236 | mp = xmalloc (sizeof (* mp)); | |
7237 | mp->fix_size = fix->fix_size; | |
7238 | mp->mode = fix->mode; | |
7239 | mp->value = fix->value; | |
7240 | mp->refcount = 1; | |
7241 | mp->max_address = minipool_barrier->address + 65536; | |
7242 | ||
7243 | mp->min_address = min_address; | |
7244 | ||
7245 | if (min_mp == NULL) | |
7246 | { | |
7247 | mp->prev = NULL; | |
7248 | mp->next = minipool_vector_head; | |
7249 | ||
7250 | if (mp->next == NULL) | |
7251 | { | |
7252 | minipool_vector_tail = mp; | |
7253 | minipool_vector_label = gen_label_rtx (); | |
7254 | } | |
7255 | else | |
7256 | mp->next->prev = mp; | |
7257 | ||
7258 | minipool_vector_head = mp; | |
7259 | } | |
7260 | else | |
7261 | { | |
7262 | mp->next = min_mp->next; | |
7263 | mp->prev = min_mp; | |
7264 | min_mp->next = mp; | |
da6558fd | 7265 | |
d5b7b3ae RE |
7266 | if (mp->next != NULL) |
7267 | mp->next->prev = mp; | |
7268 | else | |
7269 | minipool_vector_tail = mp; | |
7270 | } | |
7271 | ||
7272 | /* Save the new entry. */ | |
7273 | min_mp = mp; | |
7274 | ||
7275 | if (mp->prev) | |
7276 | mp = mp->prev; | |
7277 | else | |
7278 | mp->offset = 0; | |
7279 | ||
7280 | /* Scan over the following entries and adjust their offsets. */ | |
7281 | while (mp->next != NULL) | |
7282 | { | |
7283 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
7284 | mp->next->min_address = mp->min_address + mp->fix_size; | |
7285 | ||
7286 | if (mp->refcount) | |
7287 | mp->next->offset = mp->offset + mp->fix_size; | |
7288 | else | |
7289 | mp->next->offset = mp->offset; | |
7290 | ||
7291 | mp = mp->next; | |
7292 | } | |
7293 | ||
7294 | return min_mp; | |
7295 | } | |
7296 | ||
7297 | static void | |
e32bac5b | 7298 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
7299 | { |
7300 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 7301 | Mnode *mp; |
d5b7b3ae RE |
7302 | |
7303 | minipool_barrier = barrier; | |
7304 | ||
7305 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
7306 | { | |
7307 | mp->offset = offset; | |
da6558fd | 7308 | |
d5b7b3ae RE |
7309 | if (mp->refcount > 0) |
7310 | offset += mp->fix_size; | |
7311 | } | |
7312 | } | |
7313 | ||
7314 | /* Output the literal table */ | |
7315 | static void | |
e32bac5b | 7316 | dump_minipool (rtx scan) |
d5b7b3ae | 7317 | { |
5a9335ef NC |
7318 | Mnode * mp; |
7319 | Mnode * nmp; | |
7320 | int align64 = 0; | |
7321 | ||
5848830f | 7322 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef NC |
7323 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
7324 | if (mp->refcount > 0 && mp->fix_size == 8) | |
7325 | { | |
7326 | align64 = 1; | |
7327 | break; | |
7328 | } | |
d5b7b3ae | 7329 | |
c263766c RH |
7330 | if (dump_file) |
7331 | fprintf (dump_file, | |
5a9335ef NC |
7332 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
7333 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
7334 | |
7335 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 7336 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
7337 | scan = emit_label_after (minipool_vector_label, scan); |
7338 | ||
7339 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
7340 | { | |
7341 | if (mp->refcount > 0) | |
7342 | { | |
c263766c | 7343 | if (dump_file) |
d5b7b3ae | 7344 | { |
c263766c | 7345 | fprintf (dump_file, |
d5b7b3ae RE |
7346 | ";; Offset %u, min %ld, max %ld ", |
7347 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
7348 | (unsigned long) mp->max_address); | |
c263766c RH |
7349 | arm_print_value (dump_file, mp->value); |
7350 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
7351 | } |
7352 | ||
7353 | switch (mp->fix_size) | |
7354 | { | |
7355 | #ifdef HAVE_consttable_1 | |
7356 | case 1: | |
7357 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
7358 | break; | |
7359 | ||
7360 | #endif | |
7361 | #ifdef HAVE_consttable_2 | |
7362 | case 2: | |
7363 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
7364 | break; | |
7365 | ||
7366 | #endif | |
7367 | #ifdef HAVE_consttable_4 | |
7368 | case 4: | |
7369 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
7370 | break; | |
7371 | ||
7372 | #endif | |
7373 | #ifdef HAVE_consttable_8 | |
7374 | case 8: | |
7375 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
7376 | break; | |
7377 | ||
7378 | #endif | |
7379 | default: | |
7380 | abort (); | |
7381 | break; | |
7382 | } | |
7383 | } | |
7384 | ||
7385 | nmp = mp->next; | |
7386 | free (mp); | |
2b835d68 RE |
7387 | } |
7388 | ||
d5b7b3ae RE |
7389 | minipool_vector_head = minipool_vector_tail = NULL; |
7390 | scan = emit_insn_after (gen_consttable_end (), scan); | |
7391 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
7392 | } |
7393 | ||
d5b7b3ae RE |
7394 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
7395 | static int | |
e32bac5b | 7396 | arm_barrier_cost (rtx insn) |
949d79eb | 7397 | { |
d5b7b3ae RE |
7398 | /* Basing the location of the pool on the loop depth is preferable, |
7399 | but at the moment, the basic block information seems to be | |
7400 | corrupt by this stage of the compilation. */ | |
7401 | int base_cost = 50; | |
7402 | rtx next = next_nonnote_insn (insn); | |
7403 | ||
7404 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
7405 | base_cost -= 20; | |
7406 | ||
7407 | switch (GET_CODE (insn)) | |
7408 | { | |
7409 | case CODE_LABEL: | |
7410 | /* It will always be better to place the table before the label, rather | |
7411 | than after it. */ | |
7412 | return 50; | |
949d79eb | 7413 | |
d5b7b3ae RE |
7414 | case INSN: |
7415 | case CALL_INSN: | |
7416 | return base_cost; | |
7417 | ||
7418 | case JUMP_INSN: | |
7419 | return base_cost - 10; | |
7420 | ||
7421 | default: | |
7422 | return base_cost + 10; | |
7423 | } | |
7424 | } | |
7425 | ||
7426 | /* Find the best place in the insn stream in the range | |
7427 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
7428 | Create the barrier by inserting a jump and add a new fix entry for | |
7429 | it. */ | |
7430 | static Mfix * | |
e32bac5b | 7431 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
7432 | { |
7433 | HOST_WIDE_INT count = 0; | |
7434 | rtx barrier; | |
7435 | rtx from = fix->insn; | |
7436 | rtx selected = from; | |
7437 | int selected_cost; | |
7438 | HOST_WIDE_INT selected_address; | |
7439 | Mfix * new_fix; | |
7440 | HOST_WIDE_INT max_count = max_address - fix->address; | |
7441 | rtx label = gen_label_rtx (); | |
7442 | ||
7443 | selected_cost = arm_barrier_cost (from); | |
7444 | selected_address = fix->address; | |
7445 | ||
7446 | while (from && count < max_count) | |
7447 | { | |
7448 | rtx tmp; | |
7449 | int new_cost; | |
7450 | ||
7451 | /* This code shouldn't have been called if there was a natural barrier | |
7452 | within range. */ | |
7453 | if (GET_CODE (from) == BARRIER) | |
7454 | abort (); | |
7455 | ||
7456 | /* Count the length of this insn. */ | |
7457 | count += get_attr_length (from); | |
7458 | ||
7459 | /* If there is a jump table, add its length. */ | |
7460 | tmp = is_jump_table (from); | |
7461 | if (tmp != NULL) | |
7462 | { | |
7463 | count += get_jump_table_size (tmp); | |
7464 | ||
7465 | /* Jump tables aren't in a basic block, so base the cost on | |
7466 | the dispatch insn. If we select this location, we will | |
7467 | still put the pool after the table. */ | |
7468 | new_cost = arm_barrier_cost (from); | |
7469 | ||
7470 | if (count < max_count && new_cost <= selected_cost) | |
7471 | { | |
7472 | selected = tmp; | |
7473 | selected_cost = new_cost; | |
7474 | selected_address = fix->address + count; | |
7475 | } | |
7476 | ||
7477 | /* Continue after the dispatch table. */ | |
7478 | from = NEXT_INSN (tmp); | |
7479 | continue; | |
7480 | } | |
7481 | ||
7482 | new_cost = arm_barrier_cost (from); | |
7483 | ||
7484 | if (count < max_count && new_cost <= selected_cost) | |
7485 | { | |
7486 | selected = from; | |
7487 | selected_cost = new_cost; | |
7488 | selected_address = fix->address + count; | |
7489 | } | |
7490 | ||
7491 | from = NEXT_INSN (from); | |
7492 | } | |
7493 | ||
7494 | /* Create a new JUMP_INSN that branches around a barrier. */ | |
7495 | from = emit_jump_insn_after (gen_jump (label), selected); | |
7496 | JUMP_LABEL (from) = label; | |
7497 | barrier = emit_barrier_after (from); | |
7498 | emit_label_after (label, barrier); | |
7499 | ||
7500 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 7501 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
7502 | new_fix->insn = barrier; |
7503 | new_fix->address = selected_address; | |
7504 | new_fix->next = fix->next; | |
7505 | fix->next = new_fix; | |
7506 | ||
7507 | return new_fix; | |
7508 | } | |
7509 | ||
7510 | /* Record that there is a natural barrier in the insn stream at | |
7511 | ADDRESS. */ | |
949d79eb | 7512 | static void |
e32bac5b | 7513 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 7514 | { |
c7319d87 | 7515 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 7516 | |
949d79eb RE |
7517 | fix->insn = insn; |
7518 | fix->address = address; | |
2b835d68 | 7519 | |
949d79eb RE |
7520 | fix->next = NULL; |
7521 | if (minipool_fix_head != NULL) | |
7522 | minipool_fix_tail->next = fix; | |
7523 | else | |
7524 | minipool_fix_head = fix; | |
7525 | ||
7526 | minipool_fix_tail = fix; | |
7527 | } | |
2b835d68 | 7528 | |
d5b7b3ae RE |
7529 | /* Record INSN, which will need fixing up to load a value from the |
7530 | minipool. ADDRESS is the offset of the insn since the start of the | |
7531 | function; LOC is a pointer to the part of the insn which requires | |
7532 | fixing; VALUE is the constant that must be loaded, which is of type | |
7533 | MODE. */ | |
949d79eb | 7534 | static void |
e32bac5b RE |
7535 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
7536 | enum machine_mode mode, rtx value) | |
949d79eb | 7537 | { |
c7319d87 | 7538 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb RE |
7539 | |
7540 | #ifdef AOF_ASSEMBLER | |
093354e0 | 7541 | /* PIC symbol references need to be converted into offsets into the |
949d79eb | 7542 | based area. */ |
d5b7b3ae RE |
7543 | /* XXX This shouldn't be done here. */ |
7544 | if (flag_pic && GET_CODE (value) == SYMBOL_REF) | |
949d79eb RE |
7545 | value = aof_pic_entry (value); |
7546 | #endif /* AOF_ASSEMBLER */ | |
7547 | ||
7548 | fix->insn = insn; | |
7549 | fix->address = address; | |
7550 | fix->loc = loc; | |
7551 | fix->mode = mode; | |
d5b7b3ae | 7552 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 7553 | fix->value = value; |
d5b7b3ae RE |
7554 | fix->forwards = get_attr_pool_range (insn); |
7555 | fix->backwards = get_attr_neg_pool_range (insn); | |
7556 | fix->minipool = NULL; | |
949d79eb RE |
7557 | |
7558 | /* If an insn doesn't have a range defined for it, then it isn't | |
7559 | expecting to be reworked by this code. Better to abort now than | |
7560 | to generate duff assembly code. */ | |
d5b7b3ae | 7561 | if (fix->forwards == 0 && fix->backwards == 0) |
949d79eb RE |
7562 | abort (); |
7563 | ||
5848830f | 7564 | /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary. |
5a9335ef NC |
7565 | So there might be an empty word before the start of the pool. |
7566 | Hence we reduce the forward range by 4 to allow for this | |
7567 | possibility. */ | |
5848830f | 7568 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8) |
5a9335ef NC |
7569 | fix->forwards -= 4; |
7570 | ||
c263766c | 7571 | if (dump_file) |
d5b7b3ae | 7572 | { |
c263766c | 7573 | fprintf (dump_file, |
d5b7b3ae RE |
7574 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
7575 | GET_MODE_NAME (mode), | |
7576 | INSN_UID (insn), (unsigned long) address, | |
7577 | -1 * (long)fix->backwards, (long)fix->forwards); | |
c263766c RH |
7578 | arm_print_value (dump_file, fix->value); |
7579 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
7580 | } |
7581 | ||
6354dc9b | 7582 | /* Add it to the chain of fixes. */ |
949d79eb | 7583 | fix->next = NULL; |
d5b7b3ae | 7584 | |
949d79eb RE |
7585 | if (minipool_fix_head != NULL) |
7586 | minipool_fix_tail->next = fix; | |
7587 | else | |
7588 | minipool_fix_head = fix; | |
7589 | ||
7590 | minipool_fix_tail = fix; | |
7591 | } | |
7592 | ||
f0375c66 NC |
7593 | /* Scan INSN and note any of its operands that need fixing. |
7594 | If DO_PUSHES is false we do not actually push any of the fixups | |
7595 | needed. The function returns TRUE is any fixups were needed/pushed. | |
7596 | This is used by arm_memory_load_p() which needs to know about loads | |
7597 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 7598 | static bool |
e32bac5b | 7599 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 7600 | { |
f0375c66 | 7601 | bool result = false; |
949d79eb RE |
7602 | int opno; |
7603 | ||
d5b7b3ae | 7604 | extract_insn (insn); |
949d79eb | 7605 | |
5895f793 | 7606 | if (!constrain_operands (1)) |
949d79eb RE |
7607 | fatal_insn_not_found (insn); |
7608 | ||
8c2a5582 RE |
7609 | if (recog_data.n_alternatives == 0) |
7610 | return false; | |
7611 | ||
f0375c66 | 7612 | /* Fill in recog_op_alt with information about the constraints of this insn. */ |
949d79eb RE |
7613 | preprocess_constraints (); |
7614 | ||
1ccbefce | 7615 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 7616 | { |
6354dc9b | 7617 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 7618 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
7619 | continue; |
7620 | ||
7621 | /* If this alternative is a memory reference, then any mention | |
7622 | of constants in this alternative is really to fool reload | |
7623 | into allowing us to accept one there. We need to fix them up | |
7624 | now so that we output the right code. */ | |
7625 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
7626 | { | |
1ccbefce | 7627 | rtx op = recog_data.operand[opno]; |
949d79eb RE |
7628 | |
7629 | if (CONSTANT_P (op)) | |
f0375c66 NC |
7630 | { |
7631 | if (do_pushes) | |
7632 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
7633 | recog_data.operand_mode[opno], op); | |
7634 | result = true; | |
7635 | } | |
d5b7b3ae | 7636 | else if (GET_CODE (op) == MEM |
949d79eb RE |
7637 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
7638 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
7639 | { |
7640 | if (do_pushes) | |
244b1afb RE |
7641 | { |
7642 | rtx cop = avoid_constant_pool_reference (op); | |
7643 | ||
7644 | /* Casting the address of something to a mode narrower | |
7645 | than a word can cause avoid_constant_pool_reference() | |
7646 | to return the pool reference itself. That's no good to | |
7647 | us here. Lets just hope that we can use the | |
7648 | constant pool value directly. */ | |
7649 | if (op == cop) | |
c769a35d | 7650 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
7651 | |
7652 | push_minipool_fix (insn, address, | |
7653 | recog_data.operand_loc[opno], | |
c769a35d | 7654 | recog_data.operand_mode[opno], cop); |
244b1afb | 7655 | } |
f0375c66 NC |
7656 | |
7657 | result = true; | |
7658 | } | |
949d79eb | 7659 | } |
2b835d68 | 7660 | } |
f0375c66 NC |
7661 | |
7662 | return result; | |
2b835d68 RE |
7663 | } |
7664 | ||
18dbd950 RS |
7665 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
7666 | load addresses a limited distance around the pc. We do some | |
7667 | special munging to move the constant pool values to the correct | |
7668 | point in the code. */ | |
18dbd950 | 7669 | static void |
e32bac5b | 7670 | arm_reorg (void) |
2b835d68 RE |
7671 | { |
7672 | rtx insn; | |
d5b7b3ae RE |
7673 | HOST_WIDE_INT address = 0; |
7674 | Mfix * fix; | |
ad076f4e | 7675 | |
949d79eb | 7676 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 7677 | |
949d79eb RE |
7678 | /* The first insn must always be a note, or the code below won't |
7679 | scan it properly. */ | |
18dbd950 RS |
7680 | insn = get_insns (); |
7681 | if (GET_CODE (insn) != NOTE) | |
949d79eb RE |
7682 | abort (); |
7683 | ||
7684 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 7685 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 7686 | { |
9b6b54e2 | 7687 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 7688 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 7689 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 7690 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
7691 | cirrus_reorg (insn); |
7692 | ||
949d79eb | 7693 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 7694 | push_minipool_barrier (insn, address); |
f0375c66 | 7695 | else if (INSN_P (insn)) |
949d79eb RE |
7696 | { |
7697 | rtx table; | |
7698 | ||
f0375c66 | 7699 | note_invalid_constants (insn, address, true); |
949d79eb | 7700 | address += get_attr_length (insn); |
d5b7b3ae | 7701 | |
949d79eb RE |
7702 | /* If the insn is a vector jump, add the size of the table |
7703 | and skip the table. */ | |
d5b7b3ae | 7704 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 7705 | { |
d5b7b3ae | 7706 | address += get_jump_table_size (table); |
949d79eb RE |
7707 | insn = table; |
7708 | } | |
7709 | } | |
7710 | } | |
332072db | 7711 | |
d5b7b3ae RE |
7712 | fix = minipool_fix_head; |
7713 | ||
949d79eb | 7714 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 7715 | while (fix) |
949d79eb | 7716 | { |
d5b7b3ae RE |
7717 | Mfix * ftmp; |
7718 | Mfix * fdel; | |
7719 | Mfix * last_added_fix; | |
7720 | Mfix * last_barrier = NULL; | |
7721 | Mfix * this_fix; | |
949d79eb RE |
7722 | |
7723 | /* Skip any further barriers before the next fix. */ | |
7724 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
7725 | fix = fix->next; | |
7726 | ||
d5b7b3ae | 7727 | /* No more fixes. */ |
949d79eb RE |
7728 | if (fix == NULL) |
7729 | break; | |
332072db | 7730 | |
d5b7b3ae | 7731 | last_added_fix = NULL; |
2b835d68 | 7732 | |
d5b7b3ae | 7733 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 7734 | { |
949d79eb | 7735 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 7736 | { |
d5b7b3ae RE |
7737 | if (ftmp->address >= minipool_vector_head->max_address) |
7738 | break; | |
2b835d68 | 7739 | |
d5b7b3ae | 7740 | last_barrier = ftmp; |
2b835d68 | 7741 | } |
d5b7b3ae RE |
7742 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
7743 | break; | |
7744 | ||
7745 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 7746 | } |
949d79eb | 7747 | |
d5b7b3ae RE |
7748 | /* If we found a barrier, drop back to that; any fixes that we |
7749 | could have reached but come after the barrier will now go in | |
7750 | the next mini-pool. */ | |
949d79eb RE |
7751 | if (last_barrier != NULL) |
7752 | { | |
d5b7b3ae RE |
7753 | /* Reduce the refcount for those fixes that won't go into this |
7754 | pool after all. */ | |
7755 | for (fdel = last_barrier->next; | |
7756 | fdel && fdel != ftmp; | |
7757 | fdel = fdel->next) | |
7758 | { | |
7759 | fdel->minipool->refcount--; | |
7760 | fdel->minipool = NULL; | |
7761 | } | |
7762 | ||
949d79eb RE |
7763 | ftmp = last_barrier; |
7764 | } | |
7765 | else | |
2bfa88dc | 7766 | { |
d5b7b3ae RE |
7767 | /* ftmp is first fix that we can't fit into this pool and |
7768 | there no natural barriers that we could use. Insert a | |
7769 | new barrier in the code somewhere between the previous | |
7770 | fix and this one, and arrange to jump around it. */ | |
7771 | HOST_WIDE_INT max_address; | |
7772 | ||
7773 | /* The last item on the list of fixes must be a barrier, so | |
7774 | we can never run off the end of the list of fixes without | |
7775 | last_barrier being set. */ | |
7776 | if (ftmp == NULL) | |
7777 | abort (); | |
7778 | ||
7779 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
7780 | /* Check that there isn't another fix that is in range that |
7781 | we couldn't fit into this pool because the pool was | |
7782 | already too large: we need to put the pool before such an | |
7783 | instruction. */ | |
d5b7b3ae RE |
7784 | if (ftmp->address < max_address) |
7785 | max_address = ftmp->address; | |
7786 | ||
7787 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
7788 | } | |
7789 | ||
7790 | assign_minipool_offsets (last_barrier); | |
7791 | ||
7792 | while (ftmp) | |
7793 | { | |
7794 | if (GET_CODE (ftmp->insn) != BARRIER | |
7795 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
7796 | == NULL)) | |
7797 | break; | |
2bfa88dc | 7798 | |
d5b7b3ae | 7799 | ftmp = ftmp->next; |
2bfa88dc | 7800 | } |
949d79eb RE |
7801 | |
7802 | /* Scan over the fixes we have identified for this pool, fixing them | |
7803 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 7804 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
7805 | this_fix = this_fix->next) |
7806 | if (GET_CODE (this_fix->insn) != BARRIER) | |
7807 | { | |
949d79eb RE |
7808 | rtx addr |
7809 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, | |
7810 | minipool_vector_label), | |
d5b7b3ae | 7811 | this_fix->minipool->offset); |
949d79eb RE |
7812 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
7813 | } | |
7814 | ||
d5b7b3ae | 7815 | dump_minipool (last_barrier->insn); |
949d79eb | 7816 | fix = ftmp; |
2b835d68 | 7817 | } |
4b632bf1 | 7818 | |
949d79eb RE |
7819 | /* From now on we must synthesize any constants that we can't handle |
7820 | directly. This can happen if the RTL gets split during final | |
7821 | instruction generation. */ | |
4b632bf1 | 7822 | after_arm_reorg = 1; |
c7319d87 RE |
7823 | |
7824 | /* Free the minipool memory. */ | |
7825 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 7826 | } |
cce8749e CH |
7827 | \f |
7828 | /* Routines to output assembly language. */ | |
7829 | ||
f3bb6135 | 7830 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 7831 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 7832 | when cross compiling. */ |
cd2b33d0 | 7833 | const char * |
e32bac5b | 7834 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
7835 | { |
7836 | REAL_VALUE_TYPE r; | |
7837 | int i; | |
7838 | ||
9b66ebb1 PB |
7839 | if (!fp_consts_inited) |
7840 | init_fp_table (); | |
ff9940b0 RE |
7841 | |
7842 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
7843 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
7844 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
7845 | return strings_fp[i]; | |
f3bb6135 | 7846 | |
ff9940b0 RE |
7847 | abort (); |
7848 | } | |
7849 | ||
9997d19d | 7850 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 7851 | static const char * |
e32bac5b | 7852 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
7853 | { |
7854 | int i; | |
7855 | ||
9b66ebb1 PB |
7856 | if (!fp_consts_inited) |
7857 | init_fp_table (); | |
9997d19d RE |
7858 | |
7859 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
7860 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
7861 | return strings_fp[i]; | |
9997d19d RE |
7862 | |
7863 | abort (); | |
7864 | } | |
ff9940b0 | 7865 | |
cce8749e CH |
7866 | /* Output the operands of a LDM/STM instruction to STREAM. |
7867 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 NC |
7868 | REG is the base register, either the frame pointer or the stack pointer, |
7869 | INSTR is the possibly suffixed load or store instruction. */ | |
d5b7b3ae | 7870 | static void |
e32bac5b | 7871 | print_multi_reg (FILE *stream, const char *instr, int reg, int mask) |
cce8749e CH |
7872 | { |
7873 | int i; | |
7874 | int not_first = FALSE; | |
7875 | ||
1d5473cb | 7876 | fputc ('\t', stream); |
dd18ae56 | 7877 | asm_fprintf (stream, instr, reg); |
1d5473cb | 7878 | fputs (", {", stream); |
62b10bbc | 7879 | |
d5b7b3ae | 7880 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
7881 | if (mask & (1 << i)) |
7882 | { | |
7883 | if (not_first) | |
7884 | fprintf (stream, ", "); | |
62b10bbc | 7885 | |
dd18ae56 | 7886 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
7887 | not_first = TRUE; |
7888 | } | |
f3bb6135 | 7889 | |
61f0ccff | 7890 | fprintf (stream, "}\n"); |
f3bb6135 | 7891 | } |
cce8749e | 7892 | |
9b66ebb1 | 7893 | |
9728c9d1 PB |
7894 | /* Output a FLDMX instruction to STREAM. |
7895 | BASE if the register containing the address. | |
7896 | REG and COUNT specify the register range. | |
7897 | Extra registers may be added to avoid hardware bugs. */ | |
9b66ebb1 PB |
7898 | |
7899 | static void | |
9728c9d1 | 7900 | arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
7901 | { |
7902 | int i; | |
7903 | ||
9728c9d1 PB |
7904 | /* Workaround ARM10 VFPr1 bug. */ |
7905 | if (count == 2 && !arm_arch6) | |
7906 | { | |
7907 | if (reg == 15) | |
7908 | reg--; | |
7909 | count++; | |
7910 | } | |
7911 | ||
9b66ebb1 | 7912 | fputc ('\t', stream); |
9728c9d1 | 7913 | asm_fprintf (stream, "fldmfdx\t%r!, {", base); |
9b66ebb1 | 7914 | |
9728c9d1 | 7915 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 7916 | { |
9728c9d1 | 7917 | if (i > reg) |
9b66ebb1 | 7918 | fputs (", ", stream); |
9728c9d1 | 7919 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
7920 | } |
7921 | fputs ("}\n", stream); | |
9728c9d1 | 7922 | |
9b66ebb1 PB |
7923 | } |
7924 | ||
7925 | ||
7926 | /* Output the assembly for a store multiple. */ | |
7927 | ||
7928 | const char * | |
7929 | vfp_output_fstmx (rtx * operands) | |
7930 | { | |
7931 | char pattern[100]; | |
7932 | int p; | |
7933 | int base; | |
7934 | int i; | |
7935 | ||
7936 | strcpy (pattern, "fstmfdx\t%m0!, {%P1"); | |
7937 | p = strlen (pattern); | |
7938 | ||
7939 | if (GET_CODE (operands[1]) != REG) | |
7940 | abort (); | |
7941 | ||
7942 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
7943 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
7944 | { | |
7945 | p += sprintf (&pattern[p], ", d%d", base + i); | |
7946 | } | |
7947 | strcpy (&pattern[p], "}"); | |
7948 | ||
7949 | output_asm_insn (pattern, operands); | |
7950 | return ""; | |
7951 | } | |
7952 | ||
7953 | ||
9728c9d1 PB |
7954 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
7955 | number of bytes pushed. */ | |
9b66ebb1 | 7956 | |
9728c9d1 | 7957 | static int |
9b66ebb1 PB |
7958 | vfp_emit_fstmx (int base_reg, int count) |
7959 | { | |
7960 | rtx par; | |
7961 | rtx dwarf; | |
7962 | rtx tmp, reg; | |
7963 | int i; | |
7964 | ||
9728c9d1 PB |
7965 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
7966 | register pairs are stored by a store multiple insn. We avoid this | |
7967 | by pushing an extra pair. */ | |
7968 | if (count == 2 && !arm_arch6) | |
7969 | { | |
7970 | if (base_reg == LAST_VFP_REGNUM - 3) | |
7971 | base_reg -= 2; | |
7972 | count++; | |
7973 | } | |
7974 | ||
9b66ebb1 PB |
7975 | /* ??? The frame layout is implementation defined. We describe |
7976 | standard format 1 (equivalent to a FSTMD insn and unused pad word). | |
7977 | We really need some way of representing the whole block so that the | |
7978 | unwinder can figure it out at runtime. */ | |
7979 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
7980 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
7981 | ||
7982 | reg = gen_rtx_REG (DFmode, base_reg); | |
7983 | base_reg += 2; | |
7984 | ||
7985 | XVECEXP (par, 0, 0) | |
7986 | = gen_rtx_SET (VOIDmode, | |
7987 | gen_rtx_MEM (BLKmode, | |
7988 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
7989 | gen_rtx_UNSPEC (BLKmode, | |
7990 | gen_rtvec (1, reg), | |
7991 | UNSPEC_PUSH_MULT)); | |
7992 | ||
7993 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
7994 | gen_rtx_PLUS (SImode, stack_pointer_rtx, | |
7995 | GEN_INT (-(count * 8 + 4)))); | |
7996 | RTX_FRAME_RELATED_P (tmp) = 1; | |
7997 | XVECEXP (dwarf, 0, 0) = tmp; | |
7998 | ||
7999 | tmp = gen_rtx_SET (VOIDmode, | |
8000 | gen_rtx_MEM (DFmode, stack_pointer_rtx), | |
8001 | reg); | |
8002 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8003 | XVECEXP (dwarf, 0, 1) = tmp; | |
8004 | ||
8005 | for (i = 1; i < count; i++) | |
8006 | { | |
8007 | reg = gen_rtx_REG (DFmode, base_reg); | |
8008 | base_reg += 2; | |
8009 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
8010 | ||
8011 | tmp = gen_rtx_SET (VOIDmode, | |
8012 | gen_rtx_MEM (DFmode, | |
8013 | gen_rtx_PLUS (SImode, | |
8014 | stack_pointer_rtx, | |
8015 | GEN_INT (i * 8))), | |
8016 | reg); | |
8017 | RTX_FRAME_RELATED_P (tmp) = 1; | |
8018 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
8019 | } | |
8020 | ||
8021 | par = emit_insn (par); | |
8022 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
8023 | REG_NOTES (par)); | |
9728c9d1 PB |
8024 | RTX_FRAME_RELATED_P (par) = 1; |
8025 | ||
8026 | return count * 8 + 4; | |
9b66ebb1 PB |
8027 | } |
8028 | ||
8029 | ||
6354dc9b | 8030 | /* Output a 'call' insn. */ |
cd2b33d0 | 8031 | const char * |
e32bac5b | 8032 | output_call (rtx *operands) |
cce8749e | 8033 | { |
68d560d4 RE |
8034 | if (arm_arch5) |
8035 | abort (); /* Patterns should call blx <reg> directly. */ | |
cce8749e | 8036 | |
68d560d4 | 8037 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 8038 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 8039 | { |
62b10bbc | 8040 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 8041 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 8042 | } |
62b10bbc | 8043 | |
1d5473cb | 8044 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
da6558fd | 8045 | |
68d560d4 | 8046 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
8047 | output_asm_insn ("bx%?\t%0", operands); |
8048 | else | |
8049 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
8050 | ||
f3bb6135 RE |
8051 | return ""; |
8052 | } | |
cce8749e | 8053 | |
6354dc9b | 8054 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 8055 | const char * |
e32bac5b | 8056 | output_call_mem (rtx *operands) |
ff9940b0 | 8057 | { |
68d560d4 | 8058 | if (TARGET_INTERWORK && !arm_arch5) |
da6558fd NC |
8059 | { |
8060 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
8061 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8062 | output_asm_insn ("bx%?\t%|ip", operands); | |
8063 | } | |
6ab5da80 RE |
8064 | else if (regno_use_in (LR_REGNUM, operands[0])) |
8065 | { | |
8066 | /* LR is used in the memory address. We load the address in the | |
8067 | first instruction. It's safe to use IP as the target of the | |
8068 | load since the call will kill it anyway. */ | |
8069 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
68d560d4 RE |
8070 | if (arm_arch5) |
8071 | output_asm_insn ("blx%?%|ip", operands); | |
8072 | else | |
8073 | { | |
8074 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8075 | if (arm_arch4t) | |
8076 | output_asm_insn ("bx%?\t%|ip", operands); | |
8077 | else | |
8078 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
8079 | } | |
6ab5da80 | 8080 | } |
da6558fd NC |
8081 | else |
8082 | { | |
8083 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
8084 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
8085 | } | |
8086 | ||
f3bb6135 RE |
8087 | return ""; |
8088 | } | |
ff9940b0 RE |
8089 | |
8090 | ||
3b684012 RE |
8091 | /* Output a move from arm registers to an fpa registers. |
8092 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 8093 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 8094 | const char * |
e32bac5b | 8095 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
8096 | { |
8097 | int arm_reg0 = REGNO (operands[1]); | |
8098 | rtx ops[3]; | |
8099 | ||
62b10bbc NC |
8100 | if (arm_reg0 == IP_REGNUM) |
8101 | abort (); | |
f3bb6135 | 8102 | |
43cffd11 RE |
8103 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8104 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
8105 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 8106 | |
1d5473cb RE |
8107 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); |
8108 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); | |
62b10bbc | 8109 | |
f3bb6135 RE |
8110 | return ""; |
8111 | } | |
ff9940b0 | 8112 | |
3b684012 | 8113 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 8114 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 8115 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 8116 | const char * |
e32bac5b | 8117 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
8118 | { |
8119 | int arm_reg0 = REGNO (operands[0]); | |
8120 | rtx ops[3]; | |
8121 | ||
62b10bbc NC |
8122 | if (arm_reg0 == IP_REGNUM) |
8123 | abort (); | |
f3bb6135 | 8124 | |
43cffd11 RE |
8125 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8126 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
8127 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 8128 | |
1d5473cb RE |
8129 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
8130 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); | |
f3bb6135 RE |
8131 | return ""; |
8132 | } | |
ff9940b0 RE |
8133 | |
8134 | /* Output a move from arm registers to arm registers of a long double | |
8135 | OPERANDS[0] is the destination. | |
8136 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 8137 | const char * |
e32bac5b | 8138 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 8139 | { |
6354dc9b | 8140 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
8141 | int dest_start = REGNO (operands[0]); |
8142 | int src_start = REGNO (operands[1]); | |
8143 | rtx ops[2]; | |
8144 | int i; | |
8145 | ||
8146 | if (dest_start < src_start) | |
8147 | { | |
8148 | for (i = 0; i < 3; i++) | |
8149 | { | |
43cffd11 RE |
8150 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
8151 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 8152 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
8153 | } |
8154 | } | |
8155 | else | |
8156 | { | |
8157 | for (i = 2; i >= 0; i--) | |
8158 | { | |
43cffd11 RE |
8159 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
8160 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 8161 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
8162 | } |
8163 | } | |
f3bb6135 | 8164 | |
ff9940b0 RE |
8165 | return ""; |
8166 | } | |
8167 | ||
8168 | ||
3b684012 RE |
8169 | /* Output a move from arm registers to an fpa registers. |
8170 | OPERANDS[0] is an fpa register. | |
cce8749e | 8171 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 8172 | const char * |
e32bac5b | 8173 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
8174 | { |
8175 | int arm_reg0 = REGNO (operands[1]); | |
8176 | rtx ops[2]; | |
8177 | ||
62b10bbc NC |
8178 | if (arm_reg0 == IP_REGNUM) |
8179 | abort (); | |
8180 | ||
43cffd11 RE |
8181 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8182 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
8183 | output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); |
8184 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); | |
f3bb6135 RE |
8185 | return ""; |
8186 | } | |
cce8749e | 8187 | |
3b684012 | 8188 | /* Output a move from an fpa register to arm registers. |
cce8749e | 8189 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 8190 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 8191 | const char * |
e32bac5b | 8192 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
8193 | { |
8194 | int arm_reg0 = REGNO (operands[0]); | |
8195 | rtx ops[2]; | |
8196 | ||
62b10bbc NC |
8197 | if (arm_reg0 == IP_REGNUM) |
8198 | abort (); | |
f3bb6135 | 8199 | |
43cffd11 RE |
8200 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
8201 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb RE |
8202 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
8203 | output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); | |
f3bb6135 RE |
8204 | return ""; |
8205 | } | |
cce8749e CH |
8206 | |
8207 | /* Output a move between double words. | |
8208 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
8209 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 8210 | const char * |
e32bac5b | 8211 | output_move_double (rtx *operands) |
cce8749e CH |
8212 | { |
8213 | enum rtx_code code0 = GET_CODE (operands[0]); | |
8214 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 8215 | rtx otherops[3]; |
cce8749e CH |
8216 | |
8217 | if (code0 == REG) | |
8218 | { | |
8219 | int reg0 = REGNO (operands[0]); | |
8220 | ||
43cffd11 | 8221 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
aec3cfba | 8222 | |
cce8749e CH |
8223 | if (code1 == REG) |
8224 | { | |
8225 | int reg1 = REGNO (operands[1]); | |
62b10bbc NC |
8226 | if (reg1 == IP_REGNUM) |
8227 | abort (); | |
f3bb6135 | 8228 | |
6354dc9b | 8229 | /* Ensure the second source is not overwritten. */ |
c1c2bc04 | 8230 | if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) |
6cfc7210 | 8231 | output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); |
cce8749e | 8232 | else |
6cfc7210 | 8233 | output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); |
cce8749e | 8234 | } |
5a9335ef NC |
8235 | else if (code1 == CONST_VECTOR) |
8236 | { | |
8237 | HOST_WIDE_INT hint = 0; | |
8238 | ||
8239 | switch (GET_MODE (operands[1])) | |
8240 | { | |
8241 | case V2SImode: | |
8242 | otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1))); | |
8243 | operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0))); | |
8244 | break; | |
8245 | ||
8246 | case V4HImode: | |
8247 | if (BYTES_BIG_ENDIAN) | |
8248 | { | |
8249 | hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
8250 | hint <<= 16; | |
8251 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
8252 | } | |
8253 | else | |
8254 | { | |
8255 | hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
8256 | hint <<= 16; | |
8257 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
8258 | } | |
8259 | ||
8260 | otherops[1] = GEN_INT (hint); | |
8261 | hint = 0; | |
8262 | ||
8263 | if (BYTES_BIG_ENDIAN) | |
8264 | { | |
8265 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
8266 | hint <<= 16; | |
8267 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
8268 | } | |
8269 | else | |
8270 | { | |
8271 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
8272 | hint <<= 16; | |
8273 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
8274 | } | |
8275 | ||
8276 | operands[1] = GEN_INT (hint); | |
8277 | break; | |
8278 | ||
8279 | case V8QImode: | |
8280 | if (BYTES_BIG_ENDIAN) | |
8281 | { | |
8282 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); | |
8283 | hint <<= 8; | |
8284 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); | |
8285 | hint <<= 8; | |
8286 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); | |
8287 | hint <<= 8; | |
8288 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); | |
8289 | } | |
8290 | else | |
8291 | { | |
8292 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); | |
8293 | hint <<= 8; | |
8294 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); | |
8295 | hint <<= 8; | |
8296 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); | |
8297 | hint <<= 8; | |
8298 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); | |
8299 | } | |
8300 | ||
8301 | otherops[1] = GEN_INT (hint); | |
8302 | hint = 0; | |
8303 | ||
8304 | if (BYTES_BIG_ENDIAN) | |
8305 | { | |
8306 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
8307 | hint <<= 8; | |
8308 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
8309 | hint <<= 8; | |
8310 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
8311 | hint <<= 8; | |
8312 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
8313 | } | |
8314 | else | |
8315 | { | |
8316 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); | |
8317 | hint <<= 8; | |
8318 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); | |
8319 | hint <<= 8; | |
8320 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); | |
8321 | hint <<= 8; | |
8322 | hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); | |
8323 | } | |
8324 | ||
8325 | operands[1] = GEN_INT (hint); | |
8326 | break; | |
8327 | ||
8328 | default: | |
8329 | abort (); | |
8330 | } | |
8331 | output_mov_immediate (operands); | |
8332 | output_mov_immediate (otherops); | |
8333 | } | |
cce8749e CH |
8334 | else if (code1 == CONST_DOUBLE) |
8335 | { | |
226a5051 RE |
8336 | if (GET_MODE (operands[1]) == DFmode) |
8337 | { | |
b216cd4a | 8338 | REAL_VALUE_TYPE r; |
226a5051 | 8339 | long l[2]; |
226a5051 | 8340 | |
b216cd4a ZW |
8341 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); |
8342 | REAL_VALUE_TO_TARGET_DOUBLE (r, l); | |
d5b7b3ae RE |
8343 | otherops[1] = GEN_INT (l[1]); |
8344 | operands[1] = GEN_INT (l[0]); | |
226a5051 | 8345 | } |
c1c2bc04 RE |
8346 | else if (GET_MODE (operands[1]) != VOIDmode) |
8347 | abort (); | |
8348 | else if (WORDS_BIG_ENDIAN) | |
8349 | { | |
c1c2bc04 RE |
8350 | otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); |
8351 | operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8352 | } | |
226a5051 RE |
8353 | else |
8354 | { | |
8355 | otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8356 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8357 | } | |
6cfc7210 | 8358 | |
c1c2bc04 RE |
8359 | output_mov_immediate (operands); |
8360 | output_mov_immediate (otherops); | |
cce8749e CH |
8361 | } |
8362 | else if (code1 == CONST_INT) | |
8363 | { | |
56636818 JL |
8364 | #if HOST_BITS_PER_WIDE_INT > 32 |
8365 | /* If HOST_WIDE_INT is more than 32 bits, the intval tells us | |
8366 | what the upper word is. */ | |
8367 | if (WORDS_BIG_ENDIAN) | |
8368 | { | |
8369 | otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
8370 | operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
8371 | } | |
8372 | else | |
8373 | { | |
8374 | otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); | |
8375 | operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); | |
8376 | } | |
8377 | #else | |
6354dc9b | 8378 | /* Sign extend the intval into the high-order word. */ |
c1c2bc04 RE |
8379 | if (WORDS_BIG_ENDIAN) |
8380 | { | |
8381 | otherops[1] = operands[1]; | |
8382 | operands[1] = (INTVAL (operands[1]) < 0 | |
8383 | ? constm1_rtx : const0_rtx); | |
8384 | } | |
ff9940b0 | 8385 | else |
c1c2bc04 | 8386 | otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; |
56636818 | 8387 | #endif |
c1c2bc04 RE |
8388 | output_mov_immediate (otherops); |
8389 | output_mov_immediate (operands); | |
cce8749e CH |
8390 | } |
8391 | else if (code1 == MEM) | |
8392 | { | |
ff9940b0 | 8393 | switch (GET_CODE (XEXP (operands[1], 0))) |
cce8749e | 8394 | { |
ff9940b0 | 8395 | case REG: |
9997d19d | 8396 | output_asm_insn ("ldm%?ia\t%m1, %M0", operands); |
ff9940b0 | 8397 | break; |
2b835d68 | 8398 | |
ff9940b0 | 8399 | case PRE_INC: |
fdd695fd PB |
8400 | if (!TARGET_LDRD) |
8401 | abort (); /* Should never happen now. */ | |
8402 | output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands); | |
ff9940b0 | 8403 | break; |
2b835d68 | 8404 | |
ff9940b0 | 8405 | case PRE_DEC: |
2b835d68 | 8406 | output_asm_insn ("ldm%?db\t%m1!, %M0", operands); |
ff9940b0 | 8407 | break; |
2b835d68 | 8408 | |
ff9940b0 | 8409 | case POST_INC: |
9997d19d | 8410 | output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); |
ff9940b0 | 8411 | break; |
2b835d68 | 8412 | |
ff9940b0 | 8413 | case POST_DEC: |
fdd695fd PB |
8414 | if (!TARGET_LDRD) |
8415 | abort (); /* Should never happen now. */ | |
8416 | output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands); | |
8417 | break; | |
8418 | ||
8419 | case PRE_MODIFY: | |
8420 | case POST_MODIFY: | |
8421 | otherops[0] = operands[0]; | |
8422 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
8423 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
8424 | ||
8425 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) | |
8426 | { | |
8427 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) | |
8428 | { | |
8429 | /* Registers overlap so split out the increment. */ | |
8430 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
8431 | output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops); | |
8432 | } | |
8433 | else | |
8434 | output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops); | |
8435 | } | |
8436 | else | |
8437 | { | |
8438 | /* We only allow constant increments, so this is safe. */ | |
8439 | output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops); | |
8440 | } | |
ff9940b0 | 8441 | break; |
2b835d68 RE |
8442 | |
8443 | case LABEL_REF: | |
8444 | case CONST: | |
8445 | output_asm_insn ("adr%?\t%0, %1", operands); | |
8446 | output_asm_insn ("ldm%?ia\t%0, %M0", operands); | |
8447 | break; | |
8448 | ||
ff9940b0 | 8449 | default: |
aec3cfba NC |
8450 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), |
8451 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
cce8749e | 8452 | { |
2b835d68 RE |
8453 | otherops[0] = operands[0]; |
8454 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
8455 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
1d6e90ac | 8456 | |
2b835d68 RE |
8457 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
8458 | { | |
8459 | if (GET_CODE (otherops[2]) == CONST_INT) | |
8460 | { | |
06bea5aa | 8461 | switch ((int) INTVAL (otherops[2])) |
2b835d68 RE |
8462 | { |
8463 | case -8: | |
8464 | output_asm_insn ("ldm%?db\t%1, %M0", otherops); | |
8465 | return ""; | |
8466 | case -4: | |
8467 | output_asm_insn ("ldm%?da\t%1, %M0", otherops); | |
8468 | return ""; | |
8469 | case 4: | |
8470 | output_asm_insn ("ldm%?ib\t%1, %M0", otherops); | |
8471 | return ""; | |
8472 | } | |
fdd695fd PB |
8473 | } |
8474 | if (TARGET_LDRD | |
8475 | && (GET_CODE (otherops[2]) == REG | |
8476 | || (GET_CODE (otherops[2]) == CONST_INT | |
8477 | && INTVAL (otherops[2]) > -256 | |
8478 | && INTVAL (otherops[2]) < 256))) | |
8479 | { | |
8480 | if (reg_overlap_mentioned_p (otherops[0], | |
8481 | otherops[2])) | |
8482 | { | |
8483 | /* Swap base and index registers over to | |
8484 | avoid a conflict. */ | |
8485 | otherops[1] = XEXP (XEXP (operands[1], 0), 1); | |
8486 | otherops[2] = XEXP (XEXP (operands[1], 0), 0); | |
8487 | ||
8488 | } | |
8489 | /* If both registers conflict, it will usually | |
8490 | have been fixed by a splitter. */ | |
8491 | if (reg_overlap_mentioned_p (otherops[0], | |
8492 | otherops[2])) | |
8493 | { | |
8494 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
8495 | output_asm_insn ("ldr%?d\t%0, [%1]", | |
8496 | otherops); | |
8497 | return ""; | |
8498 | } | |
8499 | else | |
8500 | { | |
8501 | output_asm_insn ("ldr%?d\t%0, [%1, %2]", | |
8502 | otherops); | |
8503 | return ""; | |
8504 | } | |
8505 | } | |
8506 | if (GET_CODE (otherops[2]) == CONST_INT) | |
8507 | { | |
2b835d68 RE |
8508 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
8509 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
8510 | else | |
8511 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
8512 | } | |
8513 | else | |
8514 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
8515 | } | |
8516 | else | |
8517 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
6cfc7210 | 8518 | |
2b835d68 RE |
8519 | return "ldm%?ia\t%0, %M0"; |
8520 | } | |
8521 | else | |
8522 | { | |
a4a37b30 | 8523 | otherops[1] = adjust_address (operands[1], SImode, 4); |
2b835d68 RE |
8524 | /* Take care of overlapping base/data reg. */ |
8525 | if (reg_mentioned_p (operands[0], operands[1])) | |
8526 | { | |
8527 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
8528 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
8529 | } | |
8530 | else | |
8531 | { | |
8532 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
8533 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
8534 | } | |
cce8749e CH |
8535 | } |
8536 | } | |
8537 | } | |
2b835d68 | 8538 | else |
6354dc9b | 8539 | abort (); /* Constraints should prevent this. */ |
cce8749e CH |
8540 | } |
8541 | else if (code0 == MEM && code1 == REG) | |
8542 | { | |
62b10bbc NC |
8543 | if (REGNO (operands[1]) == IP_REGNUM) |
8544 | abort (); | |
2b835d68 | 8545 | |
ff9940b0 RE |
8546 | switch (GET_CODE (XEXP (operands[0], 0))) |
8547 | { | |
8548 | case REG: | |
9997d19d | 8549 | output_asm_insn ("stm%?ia\t%m0, %M1", operands); |
ff9940b0 | 8550 | break; |
2b835d68 | 8551 | |
ff9940b0 | 8552 | case PRE_INC: |
fdd695fd PB |
8553 | if (!TARGET_LDRD) |
8554 | abort (); /* Should never happen now. */ | |
8555 | output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands); | |
ff9940b0 | 8556 | break; |
2b835d68 | 8557 | |
ff9940b0 | 8558 | case PRE_DEC: |
2b835d68 | 8559 | output_asm_insn ("stm%?db\t%m0!, %M1", operands); |
ff9940b0 | 8560 | break; |
2b835d68 | 8561 | |
ff9940b0 | 8562 | case POST_INC: |
9997d19d | 8563 | output_asm_insn ("stm%?ia\t%m0!, %M1", operands); |
ff9940b0 | 8564 | break; |
2b835d68 | 8565 | |
ff9940b0 | 8566 | case POST_DEC: |
fdd695fd PB |
8567 | if (!TARGET_LDRD) |
8568 | abort (); /* Should never happen now. */ | |
8569 | output_asm_insn ("str%?d\t%1, [%m0], #-8", operands); | |
8570 | break; | |
8571 | ||
8572 | case PRE_MODIFY: | |
8573 | case POST_MODIFY: | |
8574 | otherops[0] = operands[1]; | |
8575 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
8576 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
8577 | ||
8578 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
8579 | output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops); | |
8580 | else | |
8581 | output_asm_insn ("str%?d\t%0, [%1], %2", otherops); | |
ff9940b0 | 8582 | break; |
2b835d68 RE |
8583 | |
8584 | case PLUS: | |
fdd695fd PB |
8585 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
8586 | if (GET_CODE (otherops[2]) == CONST_INT) | |
2b835d68 | 8587 | { |
06bea5aa | 8588 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
8589 | { |
8590 | case -8: | |
8591 | output_asm_insn ("stm%?db\t%m0, %M1", operands); | |
8592 | return ""; | |
8593 | ||
8594 | case -4: | |
8595 | output_asm_insn ("stm%?da\t%m0, %M1", operands); | |
8596 | return ""; | |
8597 | ||
8598 | case 4: | |
8599 | output_asm_insn ("stm%?ib\t%m0, %M1", operands); | |
8600 | return ""; | |
8601 | } | |
8602 | } | |
fdd695fd PB |
8603 | if (TARGET_LDRD |
8604 | && (GET_CODE (otherops[2]) == REG | |
8605 | || (GET_CODE (otherops[2]) == CONST_INT | |
8606 | && INTVAL (otherops[2]) > -256 | |
8607 | && INTVAL (otherops[2]) < 256))) | |
8608 | { | |
8609 | otherops[0] = operands[1]; | |
8610 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
8611 | output_asm_insn ("str%?d\t%0, [%1, %2]", otherops); | |
8612 | return ""; | |
8613 | } | |
2b835d68 RE |
8614 | /* Fall through */ |
8615 | ||
ff9940b0 | 8616 | default: |
a4a37b30 | 8617 | otherops[0] = adjust_address (operands[0], SImode, 4); |
43cffd11 | 8618 | otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); |
9997d19d RE |
8619 | output_asm_insn ("str%?\t%1, %0", operands); |
8620 | output_asm_insn ("str%?\t%1, %0", otherops); | |
cce8749e CH |
8621 | } |
8622 | } | |
2b835d68 | 8623 | else |
1d6e90ac NC |
8624 | /* Constraints should prevent this. */ |
8625 | abort (); | |
cce8749e | 8626 | |
9997d19d RE |
8627 | return ""; |
8628 | } | |
cce8749e CH |
8629 | |
8630 | ||
8631 | /* Output an arbitrary MOV reg, #n. | |
8632 | OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ | |
cd2b33d0 | 8633 | const char * |
e32bac5b | 8634 | output_mov_immediate (rtx *operands) |
cce8749e | 8635 | { |
f3bb6135 | 8636 | HOST_WIDE_INT n = INTVAL (operands[1]); |
cce8749e | 8637 | |
1d6e90ac | 8638 | /* Try to use one MOV. */ |
cce8749e | 8639 | if (const_ok_for_arm (n)) |
1d6e90ac | 8640 | output_asm_insn ("mov%?\t%0, %1", operands); |
cce8749e | 8641 | |
1d6e90ac NC |
8642 | /* Try to use one MVN. */ |
8643 | else if (const_ok_for_arm (~n)) | |
cce8749e | 8644 | { |
f3bb6135 | 8645 | operands[1] = GEN_INT (~n); |
9997d19d | 8646 | output_asm_insn ("mvn%?\t%0, %1", operands); |
cce8749e | 8647 | } |
1d6e90ac NC |
8648 | else |
8649 | { | |
8650 | int n_ones = 0; | |
8651 | int i; | |
cce8749e | 8652 | |
1d6e90ac | 8653 | /* If all else fails, make it out of ORRs or BICs as appropriate. */ |
5a9335ef | 8654 | for (i = 0; i < 32; i++) |
1d6e90ac | 8655 | if (n & 1 << i) |
5a9335ef | 8656 | n_ones++; |
cce8749e | 8657 | |
1d6e90ac NC |
8658 | if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ |
8659 | output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); | |
8660 | else | |
8661 | output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); | |
8662 | } | |
f3bb6135 RE |
8663 | |
8664 | return ""; | |
8665 | } | |
cce8749e | 8666 | |
1d6e90ac NC |
8667 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
8668 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 8669 | const char * |
e32bac5b | 8670 | output_add_immediate (rtx *operands) |
cce8749e | 8671 | { |
f3bb6135 | 8672 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
8673 | |
8674 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
8675 | { | |
8676 | if (n < 0) | |
8677 | output_multi_immediate (operands, | |
9997d19d RE |
8678 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
8679 | -n); | |
cce8749e CH |
8680 | else |
8681 | output_multi_immediate (operands, | |
9997d19d RE |
8682 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
8683 | n); | |
cce8749e | 8684 | } |
f3bb6135 RE |
8685 | |
8686 | return ""; | |
8687 | } | |
cce8749e | 8688 | |
cce8749e CH |
8689 | /* Output a multiple immediate operation. |
8690 | OPERANDS is the vector of operands referred to in the output patterns. | |
8691 | INSTR1 is the output pattern to use for the first constant. | |
8692 | INSTR2 is the output pattern to use for subsequent constants. | |
8693 | IMMED_OP is the index of the constant slot in OPERANDS. | |
8694 | N is the constant value. */ | |
cd2b33d0 | 8695 | static const char * |
e32bac5b RE |
8696 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
8697 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 8698 | { |
f3bb6135 | 8699 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 8700 | n &= 0xffffffff; |
f3bb6135 RE |
8701 | #endif |
8702 | ||
cce8749e CH |
8703 | if (n == 0) |
8704 | { | |
1d6e90ac | 8705 | /* Quick and easy output. */ |
cce8749e | 8706 | operands[immed_op] = const0_rtx; |
1d6e90ac | 8707 | output_asm_insn (instr1, operands); |
cce8749e CH |
8708 | } |
8709 | else | |
8710 | { | |
8711 | int i; | |
cd2b33d0 | 8712 | const char * instr = instr1; |
cce8749e | 8713 | |
6354dc9b | 8714 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
8715 | for (i = 0; i < 32; i += 2) |
8716 | { | |
8717 | if (n & (3 << i)) | |
8718 | { | |
f3bb6135 RE |
8719 | operands[immed_op] = GEN_INT (n & (255 << i)); |
8720 | output_asm_insn (instr, operands); | |
cce8749e CH |
8721 | instr = instr2; |
8722 | i += 6; | |
8723 | } | |
8724 | } | |
8725 | } | |
cd2b33d0 | 8726 | |
f3bb6135 | 8727 | return ""; |
9997d19d | 8728 | } |
cce8749e | 8729 | |
cce8749e CH |
8730 | /* Return the appropriate ARM instruction for the operation code. |
8731 | The returned result should not be overwritten. OP is the rtx of the | |
8732 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
8733 | was shifted. */ | |
cd2b33d0 | 8734 | const char * |
e32bac5b | 8735 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 8736 | { |
9997d19d | 8737 | switch (GET_CODE (op)) |
cce8749e CH |
8738 | { |
8739 | case PLUS: | |
f3bb6135 RE |
8740 | return "add"; |
8741 | ||
cce8749e | 8742 | case MINUS: |
f3bb6135 RE |
8743 | return shift_first_arg ? "rsb" : "sub"; |
8744 | ||
cce8749e | 8745 | case IOR: |
f3bb6135 RE |
8746 | return "orr"; |
8747 | ||
cce8749e | 8748 | case XOR: |
f3bb6135 RE |
8749 | return "eor"; |
8750 | ||
cce8749e | 8751 | case AND: |
f3bb6135 RE |
8752 | return "and"; |
8753 | ||
cce8749e | 8754 | default: |
f3bb6135 | 8755 | abort (); |
cce8749e | 8756 | } |
f3bb6135 | 8757 | } |
cce8749e | 8758 | |
cce8749e CH |
8759 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
8760 | for the operation code. The returned result should not be overwritten. | |
8761 | OP is the rtx code of the shift. | |
9997d19d | 8762 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 8763 | shift. */ |
cd2b33d0 | 8764 | static const char * |
e32bac5b | 8765 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 8766 | { |
cd2b33d0 | 8767 | const char * mnem; |
e2c671ba | 8768 | enum rtx_code code = GET_CODE (op); |
cce8749e | 8769 | |
9997d19d RE |
8770 | if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) |
8771 | *amountp = -1; | |
8772 | else if (GET_CODE (XEXP (op, 1)) == CONST_INT) | |
8773 | *amountp = INTVAL (XEXP (op, 1)); | |
8774 | else | |
8775 | abort (); | |
8776 | ||
e2c671ba | 8777 | switch (code) |
cce8749e CH |
8778 | { |
8779 | case ASHIFT: | |
8780 | mnem = "asl"; | |
8781 | break; | |
f3bb6135 | 8782 | |
cce8749e CH |
8783 | case ASHIFTRT: |
8784 | mnem = "asr"; | |
cce8749e | 8785 | break; |
f3bb6135 | 8786 | |
cce8749e CH |
8787 | case LSHIFTRT: |
8788 | mnem = "lsr"; | |
cce8749e | 8789 | break; |
f3bb6135 | 8790 | |
9997d19d RE |
8791 | case ROTATERT: |
8792 | mnem = "ror"; | |
9997d19d RE |
8793 | break; |
8794 | ||
ff9940b0 | 8795 | case MULT: |
e2c671ba RE |
8796 | /* We never have to worry about the amount being other than a |
8797 | power of 2, since this case can never be reloaded from a reg. */ | |
9997d19d RE |
8798 | if (*amountp != -1) |
8799 | *amountp = int_log2 (*amountp); | |
8800 | else | |
8801 | abort (); | |
f3bb6135 RE |
8802 | return "asl"; |
8803 | ||
cce8749e | 8804 | default: |
f3bb6135 | 8805 | abort (); |
cce8749e CH |
8806 | } |
8807 | ||
e2c671ba RE |
8808 | if (*amountp != -1) |
8809 | { | |
8810 | /* This is not 100% correct, but follows from the desire to merge | |
8811 | multiplication by a power of 2 with the recognizer for a | |
8812 | shift. >=32 is not a valid shift for "asl", so we must try and | |
8813 | output a shift that produces the correct arithmetical result. | |
ddd5a7c1 | 8814 | Using lsr #32 is identical except for the fact that the carry bit |
e2c671ba RE |
8815 | is not set correctly if we set the flags; but we never use the |
8816 | carry bit from such an operation, so we can ignore that. */ | |
8817 | if (code == ROTATERT) | |
1d6e90ac NC |
8818 | /* Rotate is just modulo 32. */ |
8819 | *amountp &= 31; | |
e2c671ba RE |
8820 | else if (*amountp != (*amountp & 31)) |
8821 | { | |
8822 | if (code == ASHIFT) | |
8823 | mnem = "lsr"; | |
8824 | *amountp = 32; | |
8825 | } | |
8826 | ||
8827 | /* Shifts of 0 are no-ops. */ | |
8828 | if (*amountp == 0) | |
8829 | return NULL; | |
8830 | } | |
8831 | ||
9997d19d RE |
8832 | return mnem; |
8833 | } | |
cce8749e | 8834 | |
6354dc9b | 8835 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 8836 | |
18af7313 | 8837 | static HOST_WIDE_INT |
e32bac5b | 8838 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 8839 | { |
f3bb6135 | 8840 | HOST_WIDE_INT shift = 0; |
cce8749e | 8841 | |
30cf4896 | 8842 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e CH |
8843 | { |
8844 | if (shift > 31) | |
f3bb6135 | 8845 | abort (); |
e32bac5b | 8846 | shift++; |
cce8749e | 8847 | } |
f3bb6135 RE |
8848 | |
8849 | return shift; | |
8850 | } | |
cce8749e | 8851 | |
cce8749e CH |
8852 | /* Output a .ascii pseudo-op, keeping track of lengths. This is because |
8853 | /bin/as is horribly restrictive. */ | |
6cfc7210 | 8854 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
8855 | |
8856 | void | |
e32bac5b | 8857 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
8858 | { |
8859 | int i; | |
6cfc7210 | 8860 | int len_so_far = 0; |
cce8749e | 8861 | |
6cfc7210 NC |
8862 | fputs ("\t.ascii\t\"", stream); |
8863 | ||
cce8749e CH |
8864 | for (i = 0; i < len; i++) |
8865 | { | |
1d6e90ac | 8866 | int c = p[i]; |
cce8749e | 8867 | |
6cfc7210 | 8868 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 8869 | { |
6cfc7210 | 8870 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 8871 | len_so_far = 0; |
cce8749e CH |
8872 | } |
8873 | ||
6cfc7210 | 8874 | switch (c) |
cce8749e | 8875 | { |
6cfc7210 NC |
8876 | case TARGET_TAB: |
8877 | fputs ("\\t", stream); | |
8878 | len_so_far += 2; | |
8879 | break; | |
8880 | ||
8881 | case TARGET_FF: | |
8882 | fputs ("\\f", stream); | |
8883 | len_so_far += 2; | |
8884 | break; | |
8885 | ||
8886 | case TARGET_BS: | |
8887 | fputs ("\\b", stream); | |
8888 | len_so_far += 2; | |
8889 | break; | |
8890 | ||
8891 | case TARGET_CR: | |
8892 | fputs ("\\r", stream); | |
8893 | len_so_far += 2; | |
8894 | break; | |
8895 | ||
8896 | case TARGET_NEWLINE: | |
8897 | fputs ("\\n", stream); | |
8898 | c = p [i + 1]; | |
8899 | if ((c >= ' ' && c <= '~') | |
8900 | || c == TARGET_TAB) | |
8901 | /* This is a good place for a line break. */ | |
8902 | len_so_far = MAX_ASCII_LEN; | |
8903 | else | |
8904 | len_so_far += 2; | |
8905 | break; | |
8906 | ||
8907 | case '\"': | |
8908 | case '\\': | |
8909 | putc ('\\', stream); | |
5895f793 | 8910 | len_so_far++; |
d6b4baa4 | 8911 | /* Drop through. */ |
f3bb6135 | 8912 | |
6cfc7210 NC |
8913 | default: |
8914 | if (c >= ' ' && c <= '~') | |
8915 | { | |
8916 | putc (c, stream); | |
5895f793 | 8917 | len_so_far++; |
6cfc7210 NC |
8918 | } |
8919 | else | |
8920 | { | |
8921 | fprintf (stream, "\\%03o", c); | |
8922 | len_so_far += 4; | |
8923 | } | |
8924 | break; | |
cce8749e | 8925 | } |
cce8749e | 8926 | } |
f3bb6135 | 8927 | |
cce8749e | 8928 | fputs ("\"\n", stream); |
f3bb6135 | 8929 | } |
cce8749e | 8930 | \f |
121308d4 | 8931 | /* Compute the register sabe mask for registers 0 through 12 |
5848830f | 8932 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
6d3d9133 | 8933 | static unsigned long |
e32bac5b | 8934 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 8935 | { |
121308d4 | 8936 | unsigned long func_type = arm_current_func_type (); |
6d3d9133 NC |
8937 | unsigned int save_reg_mask = 0; |
8938 | unsigned int reg; | |
6d3d9133 | 8939 | |
7b8b8ade | 8940 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 8941 | { |
7b8b8ade | 8942 | unsigned int max_reg; |
7b8b8ade NC |
8943 | /* Interrupt functions must not corrupt any registers, |
8944 | even call clobbered ones. If this is a leaf function | |
8945 | we can just examine the registers used by the RTL, but | |
8946 | otherwise we have to assume that whatever function is | |
8947 | called might clobber anything, and so we have to save | |
8948 | all the call-clobbered registers as well. */ | |
8949 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
8950 | /* FIQ handlers have registers r8 - r12 banked, so | |
8951 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 8952 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
8953 | r13 is the stack pointer which is always preserved, |
8954 | so we do not need to consider it here. */ | |
8955 | max_reg = 7; | |
8956 | else | |
8957 | max_reg = 12; | |
8958 | ||
8959 | for (reg = 0; reg <= max_reg; reg++) | |
8960 | if (regs_ever_live[reg] | |
8961 | || (! current_function_is_leaf && call_used_regs [reg])) | |
6d3d9133 NC |
8962 | save_reg_mask |= (1 << reg); |
8963 | } | |
8964 | else | |
8965 | { | |
8966 | /* In the normal case we only need to save those registers | |
8967 | which are call saved and which are used by this function. */ | |
8968 | for (reg = 0; reg <= 10; reg++) | |
8969 | if (regs_ever_live[reg] && ! call_used_regs [reg]) | |
8970 | save_reg_mask |= (1 << reg); | |
8971 | ||
8972 | /* Handle the frame pointer as a special case. */ | |
8973 | if (! TARGET_APCS_FRAME | |
8974 | && ! frame_pointer_needed | |
8975 | && regs_ever_live[HARD_FRAME_POINTER_REGNUM] | |
8976 | && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) | |
8977 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; | |
8978 | ||
8979 | /* If we aren't loading the PIC register, | |
8980 | don't stack it even though it may be live. */ | |
8981 | if (flag_pic | |
8982 | && ! TARGET_SINGLE_PIC_BASE | |
8983 | && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) | |
8984 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; | |
8985 | } | |
8986 | ||
121308d4 NC |
8987 | return save_reg_mask; |
8988 | } | |
8989 | ||
8990 | /* Compute a bit mask of which registers need to be | |
8991 | saved on the stack for the current function. */ | |
8992 | ||
8993 | static unsigned long | |
e32bac5b | 8994 | arm_compute_save_reg_mask (void) |
121308d4 NC |
8995 | { |
8996 | unsigned int save_reg_mask = 0; | |
8997 | unsigned long func_type = arm_current_func_type (); | |
8998 | ||
8999 | if (IS_NAKED (func_type)) | |
9000 | /* This should never really happen. */ | |
9001 | return 0; | |
9002 | ||
9003 | /* If we are creating a stack frame, then we must save the frame pointer, | |
9004 | IP (which will hold the old stack pointer), LR and the PC. */ | |
9005 | if (frame_pointer_needed) | |
9006 | save_reg_mask |= | |
9007 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
9008 | | (1 << IP_REGNUM) | |
9009 | | (1 << LR_REGNUM) | |
9010 | | (1 << PC_REGNUM); | |
9011 | ||
9012 | /* Volatile functions do not return, so there | |
9013 | is no need to save any other registers. */ | |
9014 | if (IS_VOLATILE (func_type)) | |
9015 | return save_reg_mask; | |
9016 | ||
9017 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
9018 | ||
6d3d9133 NC |
9019 | /* Decide if we need to save the link register. |
9020 | Interrupt routines have their own banked link register, | |
9021 | so they never need to save it. | |
1768c26f | 9022 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
9023 | it. If we are pushing other registers onto the stack however, we |
9024 | can save an instruction in the epilogue by pushing the link register | |
9025 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 9026 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 9027 | if we know that we will not need a fancy return sequence. */ |
3a7731fd | 9028 | if (regs_ever_live [LR_REGNUM] |
6d3d9133 NC |
9029 | || (save_reg_mask |
9030 | && optimize_size | |
3a7731fd | 9031 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)) |
6d3d9133 NC |
9032 | save_reg_mask |= 1 << LR_REGNUM; |
9033 | ||
6f7ebcbb NC |
9034 | if (cfun->machine->lr_save_eliminated) |
9035 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
9036 | ||
5a9335ef NC |
9037 | if (TARGET_REALLY_IWMMXT |
9038 | && ((bit_count (save_reg_mask) | |
9039 | + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0) | |
9040 | { | |
9041 | unsigned int reg; | |
9042 | ||
9043 | /* The total number of registers that are going to be pushed | |
9044 | onto the stack is odd. We need to ensure that the stack | |
9045 | is 64-bit aligned before we start to save iWMMXt registers, | |
9046 | and also before we start to create locals. (A local variable | |
9047 | might be a double or long long which we will load/store using | |
9048 | an iWMMXt instruction). Therefore we need to push another | |
9049 | ARM register, so that the stack will be 64-bit aligned. We | |
9050 | try to avoid using the arg registers (r0 -r3) as they might be | |
9051 | used to pass values in a tail call. */ | |
9052 | for (reg = 4; reg <= 12; reg++) | |
9053 | if ((save_reg_mask & (1 << reg)) == 0) | |
9054 | break; | |
9055 | ||
9056 | if (reg <= 12) | |
9057 | save_reg_mask |= (1 << reg); | |
9058 | else | |
9059 | { | |
9060 | cfun->machine->sibcall_blocked = 1; | |
9061 | save_reg_mask |= (1 << 3); | |
9062 | } | |
9063 | } | |
9064 | ||
6d3d9133 NC |
9065 | return save_reg_mask; |
9066 | } | |
9067 | ||
9728c9d1 PB |
9068 | |
9069 | /* Return the number of bytes required to save VFP registers. */ | |
9070 | static int | |
9071 | arm_get_vfp_saved_size (void) | |
9072 | { | |
9073 | unsigned int regno; | |
9074 | int count; | |
9075 | int saved; | |
9076 | ||
9077 | saved = 0; | |
9078 | /* Space for saved VFP registers. */ | |
9079 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9080 | { | |
9081 | count = 0; | |
9082 | for (regno = FIRST_VFP_REGNUM; | |
9083 | regno < LAST_VFP_REGNUM; | |
9084 | regno += 2) | |
9085 | { | |
9086 | if ((!regs_ever_live[regno] || call_used_regs[regno]) | |
9087 | && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1])) | |
9088 | { | |
9089 | if (count > 0) | |
9090 | { | |
9091 | /* Workaround ARM10 VFPr1 bug. */ | |
9092 | if (count == 2 && !arm_arch6) | |
9093 | count++; | |
9094 | saved += count * 8 + 4; | |
9095 | } | |
9096 | count = 0; | |
9097 | } | |
9098 | else | |
9099 | count++; | |
9100 | } | |
9101 | if (count > 0) | |
9102 | { | |
9103 | if (count == 2 && !arm_arch6) | |
9104 | count++; | |
9105 | saved += count * 8 + 4; | |
9106 | } | |
9107 | } | |
9108 | return saved; | |
9109 | } | |
9110 | ||
9111 | ||
699a4925 | 9112 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 9113 | everything bar the final return instruction. */ |
cd2b33d0 | 9114 | const char * |
e32bac5b | 9115 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 9116 | { |
6d3d9133 | 9117 | char conditional[10]; |
ff9940b0 | 9118 | char instr[100]; |
6d3d9133 NC |
9119 | int reg; |
9120 | unsigned long live_regs_mask; | |
9121 | unsigned long func_type; | |
5848830f | 9122 | arm_stack_offsets *offsets; |
e26053d1 | 9123 | |
6d3d9133 | 9124 | func_type = arm_current_func_type (); |
e2c671ba | 9125 | |
6d3d9133 | 9126 | if (IS_NAKED (func_type)) |
d5b7b3ae | 9127 | return ""; |
6d3d9133 NC |
9128 | |
9129 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 9130 | { |
699a4925 RE |
9131 | /* If this function was declared non-returning, and we have |
9132 | found a tail call, then we have to trust that the called | |
9133 | function won't return. */ | |
3a5a4282 PB |
9134 | if (really_return) |
9135 | { | |
9136 | rtx ops[2]; | |
9137 | ||
9138 | /* Otherwise, trap an attempted return by aborting. */ | |
9139 | ops[0] = operand; | |
9140 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" | |
9141 | : "abort"); | |
9142 | assemble_external_libcall (ops[1]); | |
9143 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
9144 | } | |
9145 | ||
e2c671ba RE |
9146 | return ""; |
9147 | } | |
6d3d9133 | 9148 | |
5895f793 | 9149 | if (current_function_calls_alloca && !really_return) |
62b10bbc | 9150 | abort (); |
ff9940b0 | 9151 | |
c414f8a9 | 9152 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 9153 | |
6d3d9133 | 9154 | return_used_this_function = 1; |
ff9940b0 | 9155 | |
6d3d9133 | 9156 | live_regs_mask = arm_compute_save_reg_mask (); |
ff9940b0 | 9157 | |
1768c26f | 9158 | if (live_regs_mask) |
6d3d9133 | 9159 | { |
1768c26f PB |
9160 | const char * return_reg; |
9161 | ||
9162 | /* If we do not have any special requirements for function exit | |
9163 | (eg interworking, or ISR) then we can load the return address | |
9164 | directly into the PC. Otherwise we must load it into LR. */ | |
9165 | if (really_return | |
1768c26f PB |
9166 | && ! TARGET_INTERWORK) |
9167 | return_reg = reg_names[PC_REGNUM]; | |
6d3d9133 | 9168 | else |
1768c26f PB |
9169 | return_reg = reg_names[LR_REGNUM]; |
9170 | ||
6d3d9133 | 9171 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
9172 | { |
9173 | /* There are three possible reasons for the IP register | |
9174 | being saved. 1) a stack frame was created, in which case | |
9175 | IP contains the old stack pointer, or 2) an ISR routine | |
9176 | corrupted it, or 3) it was saved to align the stack on | |
9177 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
9178 | restore IP. */ | |
9179 | if (frame_pointer_needed) | |
9180 | { | |
9181 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
9182 | live_regs_mask |= (1 << SP_REGNUM); | |
9183 | } | |
9184 | else | |
9185 | { | |
9186 | if (! IS_INTERRUPT (func_type) | |
9187 | && ! TARGET_REALLY_IWMMXT) | |
9188 | abort (); | |
9189 | } | |
9190 | } | |
f3bb6135 | 9191 | |
3a7731fd PB |
9192 | /* On some ARM architectures it is faster to use LDR rather than |
9193 | LDM to load a single register. On other architectures, the | |
9194 | cost is the same. In 26 bit mode, or for exception handlers, | |
9195 | we have to use LDM to load the PC so that the CPSR is also | |
9196 | restored. */ | |
9197 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
6d3d9133 | 9198 | { |
3a7731fd PB |
9199 | if (live_regs_mask == (unsigned int)(1 << reg)) |
9200 | break; | |
9201 | } | |
9202 | if (reg <= LAST_ARM_REGNUM | |
9203 | && (reg != LR_REGNUM | |
9204 | || ! really_return | |
61f0ccff | 9205 | || ! IS_INTERRUPT (func_type))) |
3a7731fd PB |
9206 | { |
9207 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, | |
9208 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); | |
6d3d9133 | 9209 | } |
ff9940b0 | 9210 | else |
1d5473cb | 9211 | { |
1768c26f PB |
9212 | char *p; |
9213 | int first = 1; | |
6d3d9133 | 9214 | |
699a4925 RE |
9215 | /* Generate the load multiple instruction to restore the |
9216 | registers. Note we can get here, even if | |
9217 | frame_pointer_needed is true, but only if sp already | |
9218 | points to the base of the saved core registers. */ | |
9219 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 9220 | { |
5848830f PB |
9221 | unsigned HOST_WIDE_INT stack_adjust; |
9222 | ||
9223 | offsets = arm_get_frame_offsets (); | |
9224 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 RE |
9225 | if (stack_adjust != 0 && stack_adjust != 4) |
9226 | abort (); | |
9227 | ||
9228 | if (stack_adjust && arm_arch5) | |
9229 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); | |
9230 | else | |
9231 | { | |
9232 | /* If we can't use ldmib (SA110 bug), then try to pop r3 | |
9233 | instead. */ | |
9234 | if (stack_adjust) | |
9235 | live_regs_mask |= 1 << 3; | |
9236 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
9237 | } | |
9238 | } | |
da6558fd | 9239 | else |
1768c26f PB |
9240 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
9241 | ||
9242 | p = instr + strlen (instr); | |
6d3d9133 | 9243 | |
1768c26f PB |
9244 | for (reg = 0; reg <= SP_REGNUM; reg++) |
9245 | if (live_regs_mask & (1 << reg)) | |
9246 | { | |
9247 | int l = strlen (reg_names[reg]); | |
9248 | ||
9249 | if (first) | |
9250 | first = 0; | |
9251 | else | |
9252 | { | |
9253 | memcpy (p, ", ", 2); | |
9254 | p += 2; | |
9255 | } | |
9256 | ||
9257 | memcpy (p, "%|", 2); | |
9258 | memcpy (p + 2, reg_names[reg], l); | |
9259 | p += l + 2; | |
9260 | } | |
9261 | ||
9262 | if (live_regs_mask & (1 << LR_REGNUM)) | |
9263 | { | |
b17fe233 | 9264 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
9265 | /* If returning from an interrupt, restore the CPSR. */ |
9266 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 9267 | strcat (p, "^"); |
1768c26f PB |
9268 | } |
9269 | else | |
9270 | strcpy (p, "}"); | |
1d5473cb | 9271 | } |
da6558fd | 9272 | |
1768c26f PB |
9273 | output_asm_insn (instr, & operand); |
9274 | ||
3a7731fd PB |
9275 | /* See if we need to generate an extra instruction to |
9276 | perform the actual function return. */ | |
9277 | if (really_return | |
9278 | && func_type != ARM_FT_INTERWORKED | |
9279 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 9280 | { |
3a7731fd PB |
9281 | /* The return has already been handled |
9282 | by loading the LR into the PC. */ | |
9283 | really_return = 0; | |
da6558fd | 9284 | } |
ff9940b0 | 9285 | } |
e26053d1 | 9286 | |
1768c26f | 9287 | if (really_return) |
ff9940b0 | 9288 | { |
6d3d9133 NC |
9289 | switch ((int) ARM_FUNC_TYPE (func_type)) |
9290 | { | |
9291 | case ARM_FT_ISR: | |
9292 | case ARM_FT_FIQ: | |
9293 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); | |
9294 | break; | |
9295 | ||
9296 | case ARM_FT_INTERWORKED: | |
9297 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
9298 | break; | |
9299 | ||
9300 | case ARM_FT_EXCEPTION: | |
9301 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); | |
9302 | break; | |
9303 | ||
9304 | default: | |
68d560d4 RE |
9305 | /* Use bx if it's available. */ |
9306 | if (arm_arch5 || arm_arch4t) | |
1768c26f PB |
9307 | sprintf (instr, "bx%s\t%%|lr", conditional); |
9308 | else | |
61f0ccff | 9309 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
9310 | break; |
9311 | } | |
1768c26f PB |
9312 | |
9313 | output_asm_insn (instr, & operand); | |
ff9940b0 | 9314 | } |
f3bb6135 | 9315 | |
ff9940b0 RE |
9316 | return ""; |
9317 | } | |
9318 | ||
ef179a26 NC |
9319 | /* Write the function name into the code section, directly preceding |
9320 | the function prologue. | |
9321 | ||
9322 | Code will be output similar to this: | |
9323 | t0 | |
9324 | .ascii "arm_poke_function_name", 0 | |
9325 | .align | |
9326 | t1 | |
9327 | .word 0xff000000 + (t1 - t0) | |
9328 | arm_poke_function_name | |
9329 | mov ip, sp | |
9330 | stmfd sp!, {fp, ip, lr, pc} | |
9331 | sub fp, ip, #4 | |
9332 | ||
9333 | When performing a stack backtrace, code can inspect the value | |
9334 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
9335 | at location pc - 12 and the top 8 bits are set, then we know | |
9336 | that there is a function name embedded immediately preceding this | |
9337 | location and has length ((pc[-3]) & 0xff000000). | |
9338 | ||
9339 | We assume that pc is declared as a pointer to an unsigned long. | |
9340 | ||
9341 | It is of no benefit to output the function name if we are assembling | |
9342 | a leaf function. These function types will not contain a stack | |
9343 | backtrace structure, therefore it is not possible to determine the | |
9344 | function name. */ | |
ef179a26 | 9345 | void |
e32bac5b | 9346 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
9347 | { |
9348 | unsigned long alignlength; | |
9349 | unsigned long length; | |
9350 | rtx x; | |
9351 | ||
d5b7b3ae | 9352 | length = strlen (name) + 1; |
0c2ca901 | 9353 | alignlength = ROUND_UP_WORD (length); |
ef179a26 | 9354 | |
949d79eb | 9355 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 9356 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 9357 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 9358 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
9359 | } |
9360 | ||
6d3d9133 NC |
9361 | /* Place some comments into the assembler stream |
9362 | describing the current function. */ | |
08c148a8 | 9363 | static void |
e32bac5b | 9364 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 9365 | { |
6d3d9133 | 9366 | unsigned long func_type; |
08c148a8 NB |
9367 | |
9368 | if (!TARGET_ARM) | |
9369 | { | |
9370 | thumb_output_function_prologue (f, frame_size); | |
9371 | return; | |
9372 | } | |
6d3d9133 NC |
9373 | |
9374 | /* Sanity check. */ | |
abaa26e5 | 9375 | if (arm_ccfsm_state || arm_target_insn) |
6d3d9133 | 9376 | abort (); |
31fdb4d5 | 9377 | |
6d3d9133 NC |
9378 | func_type = arm_current_func_type (); |
9379 | ||
9380 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
9381 | { | |
9382 | default: | |
9383 | case ARM_FT_NORMAL: | |
9384 | break; | |
9385 | case ARM_FT_INTERWORKED: | |
9386 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
9387 | break; | |
9388 | case ARM_FT_EXCEPTION_HANDLER: | |
9389 | asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); | |
9390 | break; | |
9391 | case ARM_FT_ISR: | |
9392 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
9393 | break; | |
9394 | case ARM_FT_FIQ: | |
9395 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
9396 | break; | |
9397 | case ARM_FT_EXCEPTION: | |
9398 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
9399 | break; | |
9400 | } | |
ff9940b0 | 9401 | |
6d3d9133 NC |
9402 | if (IS_NAKED (func_type)) |
9403 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
9404 | ||
9405 | if (IS_VOLATILE (func_type)) | |
9406 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
9407 | ||
9408 | if (IS_NESTED (func_type)) | |
9409 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
9410 | ||
c53dddc2 | 9411 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
dd18ae56 NC |
9412 | current_function_args_size, |
9413 | current_function_pretend_args_size, frame_size); | |
6d3d9133 | 9414 | |
3cb66fd7 | 9415 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 9416 | frame_pointer_needed, |
3cb66fd7 | 9417 | cfun->machine->uses_anonymous_args); |
cce8749e | 9418 | |
6f7ebcbb NC |
9419 | if (cfun->machine->lr_save_eliminated) |
9420 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
9421 | ||
32de079a RE |
9422 | #ifdef AOF_ASSEMBLER |
9423 | if (flag_pic) | |
dd18ae56 | 9424 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); |
32de079a | 9425 | #endif |
6d3d9133 NC |
9426 | |
9427 | return_used_this_function = 0; | |
f3bb6135 | 9428 | } |
cce8749e | 9429 | |
cd2b33d0 | 9430 | const char * |
a72d4945 | 9431 | arm_output_epilogue (rtx sibling) |
cce8749e | 9432 | { |
949d79eb | 9433 | int reg; |
6f7ebcbb | 9434 | unsigned long saved_regs_mask; |
6d3d9133 | 9435 | unsigned long func_type; |
c882c7ac RE |
9436 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
9437 | frame that is $fp + 4 for a non-variadic function. */ | |
9438 | int floats_offset = 0; | |
cce8749e | 9439 | rtx operands[3]; |
d5b7b3ae | 9440 | FILE * f = asm_out_file; |
6d3d9133 | 9441 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; |
5a9335ef | 9442 | unsigned int lrm_count = 0; |
a72d4945 | 9443 | int really_return = (sibling == NULL); |
9b66ebb1 | 9444 | int start_reg; |
5848830f | 9445 | arm_stack_offsets *offsets; |
cce8749e | 9446 | |
6d3d9133 NC |
9447 | /* If we have already generated the return instruction |
9448 | then it is futile to generate anything else. */ | |
a72d4945 | 9449 | if (use_return_insn (FALSE, sibling) && return_used_this_function) |
949d79eb | 9450 | return ""; |
cce8749e | 9451 | |
6d3d9133 | 9452 | func_type = arm_current_func_type (); |
d5b7b3ae | 9453 | |
6d3d9133 NC |
9454 | if (IS_NAKED (func_type)) |
9455 | /* Naked functions don't have epilogues. */ | |
9456 | return ""; | |
0616531f | 9457 | |
6d3d9133 | 9458 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 9459 | { |
86efdc8e | 9460 | rtx op; |
6d3d9133 NC |
9461 | |
9462 | /* A volatile function should never return. Call abort. */ | |
ed0e6530 | 9463 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 9464 | assemble_external_libcall (op); |
e2c671ba | 9465 | output_asm_insn ("bl\t%a0", &op); |
6d3d9133 | 9466 | |
949d79eb | 9467 | return ""; |
e2c671ba RE |
9468 | } |
9469 | ||
6d3d9133 NC |
9470 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER |
9471 | && ! really_return) | |
9472 | /* If we are throwing an exception, then we really must | |
9473 | be doing a return, so we can't tail-call. */ | |
9474 | abort (); | |
9475 | ||
5848830f | 9476 | offsets = arm_get_frame_offsets (); |
6f7ebcbb | 9477 | saved_regs_mask = arm_compute_save_reg_mask (); |
5a9335ef NC |
9478 | |
9479 | if (TARGET_IWMMXT) | |
9480 | lrm_count = bit_count (saved_regs_mask); | |
9481 | ||
5848830f | 9482 | floats_offset = offsets->saved_args; |
6d3d9133 | 9483 | /* Compute how far away the floats will be. */ |
5a9335ef | 9484 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 9485 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 9486 | floats_offset += 4; |
6d3d9133 | 9487 | |
ff9940b0 | 9488 | if (frame_pointer_needed) |
cce8749e | 9489 | { |
9b66ebb1 | 9490 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 9491 | int vfp_offset = offsets->frame; |
c882c7ac | 9492 | |
29ad9694 | 9493 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 9494 | { |
9b66ebb1 | 9495 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
5895f793 | 9496 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9497 | { |
9498 | floats_offset += 12; | |
dd18ae56 | 9499 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 9500 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9501 | } |
9502 | } | |
9503 | else | |
9504 | { | |
9b66ebb1 | 9505 | start_reg = LAST_FPA_REGNUM; |
b111229a | 9506 | |
9b66ebb1 | 9507 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 9508 | { |
5895f793 | 9509 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9510 | { |
9511 | floats_offset += 12; | |
6cfc7210 | 9512 | |
6354dc9b | 9513 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
9514 | if (start_reg - reg == 3) |
9515 | { | |
dd18ae56 | 9516 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 9517 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9518 | start_reg = reg - 1; |
9519 | } | |
9520 | } | |
9521 | else | |
9522 | { | |
9523 | if (reg != start_reg) | |
dd18ae56 NC |
9524 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
9525 | reg + 1, start_reg - reg, | |
c882c7ac | 9526 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
9527 | start_reg = reg - 1; |
9528 | } | |
9529 | } | |
9530 | ||
9531 | /* Just in case the last register checked also needs unstacking. */ | |
9532 | if (reg != start_reg) | |
dd18ae56 NC |
9533 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
9534 | reg + 1, start_reg - reg, | |
c882c7ac | 9535 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 9536 | } |
6d3d9133 | 9537 | |
9b66ebb1 PB |
9538 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
9539 | { | |
9728c9d1 | 9540 | int saved_size; |
9b66ebb1 | 9541 | |
9728c9d1 PB |
9542 | /* The fldmx insn does not have base+offset addressing modes, |
9543 | so we use IP to hold the address. */ | |
9544 | saved_size = arm_get_vfp_saved_size (); | |
9b66ebb1 | 9545 | |
9728c9d1 | 9546 | if (saved_size > 0) |
9b66ebb1 | 9547 | { |
9728c9d1 | 9548 | floats_offset += saved_size; |
9b66ebb1 PB |
9549 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
9550 | FP_REGNUM, floats_offset - vfp_offset); | |
9551 | } | |
9552 | start_reg = FIRST_VFP_REGNUM; | |
9553 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
9554 | { | |
9555 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
9556 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
9557 | { | |
9558 | if (start_reg != reg) | |
9728c9d1 PB |
9559 | arm_output_fldmx (f, IP_REGNUM, |
9560 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9561 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
9562 | start_reg = reg + 2; |
9563 | } | |
9564 | } | |
9565 | if (start_reg != reg) | |
9728c9d1 PB |
9566 | arm_output_fldmx (f, IP_REGNUM, |
9567 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9568 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
9569 | } |
9570 | ||
5a9335ef NC |
9571 | if (TARGET_IWMMXT) |
9572 | { | |
9573 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
9574 | This is because it is set to (old_stack_pointer - 4) and the | |
9575 | old_stack_pointer was double word aligned. Thus the offset to | |
9576 | the iWMMXt registers to be loaded must also be non-double-word | |
9577 | sized, so that the resultant address *is* double-word aligned. | |
9578 | We can ignore floats_offset since that was already included in | |
9579 | the live_regs_mask. */ | |
9580 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
9581 | ||
01d4c813 | 9582 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
5a9335ef NC |
9583 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
9584 | { | |
9585 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", | |
9586 | reg, FP_REGNUM, lrm_count * 4); | |
9587 | lrm_count += 2; | |
9588 | } | |
9589 | } | |
9590 | ||
6f7ebcbb | 9591 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
9592 | frame generation actually contains the old stack pointer. So a |
9593 | quick way to unwind the stack is just pop the IP register directly | |
9594 | into the stack pointer. */ | |
6f7ebcbb | 9595 | if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) |
6d3d9133 | 9596 | abort (); |
6f7ebcbb NC |
9597 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
9598 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 9599 | |
6f7ebcbb | 9600 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
9601 | only need to restore the LR register (the return address), but to |
9602 | save time we can load it directly into the PC, unless we need a | |
9603 | special function exit sequence, or we are not really returning. */ | |
9604 | if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
9605 | /* Delete the LR from the register mask, so that the LR on | |
9606 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 9607 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 9608 | else |
6f7ebcbb | 9609 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
9610 | |
9611 | /* We must use SP as the base register, because SP is one of the | |
9612 | registers being restored. If an interrupt or page fault | |
9613 | happens in the ldm instruction, the SP might or might not | |
9614 | have been restored. That would be bad, as then SP will no | |
9615 | longer indicate the safe area of stack, and we can get stack | |
9616 | corruption. Using SP as the base register means that it will | |
9617 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
9618 | occur. If the stack pointer already points at the right |
9619 | place, then omit the subtraction. */ | |
5848830f | 9620 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
699a4925 RE |
9621 | || current_function_calls_alloca) |
9622 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, | |
9623 | 4 * bit_count (saved_regs_mask)); | |
efc2515b | 9624 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); |
7b8b8ade NC |
9625 | |
9626 | if (IS_INTERRUPT (func_type)) | |
9627 | /* Interrupt handlers will have pushed the | |
9628 | IP onto the stack, so restore it now. */ | |
f55d7103 | 9629 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM); |
cce8749e CH |
9630 | } |
9631 | else | |
9632 | { | |
d2288d8d | 9633 | /* Restore stack pointer if necessary. */ |
5848830f | 9634 | if (offsets->outgoing_args != offsets->saved_regs) |
d2288d8d TG |
9635 | { |
9636 | operands[0] = operands[1] = stack_pointer_rtx; | |
5848830f | 9637 | operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs); |
d2288d8d TG |
9638 | output_add_immediate (operands); |
9639 | } | |
9640 | ||
29ad9694 | 9641 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 9642 | { |
9b66ebb1 | 9643 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
5895f793 | 9644 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
dd18ae56 NC |
9645 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
9646 | reg, SP_REGNUM); | |
b111229a RE |
9647 | } |
9648 | else | |
9649 | { | |
9b66ebb1 | 9650 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 9651 | |
9b66ebb1 | 9652 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 9653 | { |
5895f793 | 9654 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
9655 | { |
9656 | if (reg - start_reg == 3) | |
9657 | { | |
dd18ae56 NC |
9658 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
9659 | start_reg, SP_REGNUM); | |
b111229a RE |
9660 | start_reg = reg + 1; |
9661 | } | |
9662 | } | |
9663 | else | |
9664 | { | |
9665 | if (reg != start_reg) | |
dd18ae56 NC |
9666 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
9667 | start_reg, reg - start_reg, | |
9668 | SP_REGNUM); | |
6cfc7210 | 9669 | |
b111229a RE |
9670 | start_reg = reg + 1; |
9671 | } | |
9672 | } | |
9673 | ||
9674 | /* Just in case the last register checked also needs unstacking. */ | |
9675 | if (reg != start_reg) | |
dd18ae56 NC |
9676 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
9677 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
9678 | } |
9679 | ||
9b66ebb1 PB |
9680 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
9681 | { | |
9682 | start_reg = FIRST_VFP_REGNUM; | |
9683 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
9684 | { | |
9685 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
9686 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
9687 | { | |
9688 | if (start_reg != reg) | |
9728c9d1 PB |
9689 | arm_output_fldmx (f, SP_REGNUM, |
9690 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9691 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
9692 | start_reg = reg + 2; |
9693 | } | |
9694 | } | |
9695 | if (start_reg != reg) | |
9728c9d1 PB |
9696 | arm_output_fldmx (f, SP_REGNUM, |
9697 | (start_reg - FIRST_VFP_REGNUM) / 2, | |
9698 | (reg - start_reg) / 2); | |
9b66ebb1 | 9699 | } |
5a9335ef NC |
9700 | if (TARGET_IWMMXT) |
9701 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
9702 | if (regs_ever_live[reg] && !call_used_regs[reg]) | |
01d4c813 | 9703 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 9704 | |
6d3d9133 NC |
9705 | /* If we can, restore the LR into the PC. */ |
9706 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
9707 | && really_return | |
9708 | && current_function_pretend_args_size == 0 | |
6f7ebcbb | 9709 | && saved_regs_mask & (1 << LR_REGNUM)) |
cce8749e | 9710 | { |
6f7ebcbb NC |
9711 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
9712 | saved_regs_mask |= (1 << PC_REGNUM); | |
6d3d9133 | 9713 | } |
d5b7b3ae | 9714 | |
6d3d9133 NC |
9715 | /* Load the registers off the stack. If we only have one register |
9716 | to load use the LDR instruction - it is faster. */ | |
6f7ebcbb | 9717 | if (saved_regs_mask == (1 << LR_REGNUM)) |
6d3d9133 | 9718 | { |
f4864588 | 9719 | /* The exception handler ignores the LR, so we do |
6d3d9133 NC |
9720 | not really need to load it off the stack. */ |
9721 | if (eh_ofs) | |
9722 | asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); | |
32de079a | 9723 | else |
6d3d9133 | 9724 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 9725 | } |
6f7ebcbb | 9726 | else if (saved_regs_mask) |
f1acdf8b NC |
9727 | { |
9728 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
9729 | /* Note - write back to the stack register is not enabled | |
9730 | (ie "ldmfd sp!..."). We know that the stack pointer is | |
9731 | in the list of registers and if we add writeback the | |
9732 | instruction becomes UNPREDICTABLE. */ | |
9733 | print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); | |
9734 | else | |
9735 | print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); | |
9736 | } | |
6d3d9133 NC |
9737 | |
9738 | if (current_function_pretend_args_size) | |
cce8749e | 9739 | { |
6d3d9133 NC |
9740 | /* Unwind the pre-pushed regs. */ |
9741 | operands[0] = operands[1] = stack_pointer_rtx; | |
9742 | operands[2] = GEN_INT (current_function_pretend_args_size); | |
9743 | output_add_immediate (operands); | |
9744 | } | |
9745 | } | |
32de079a | 9746 | |
2966b00e | 9747 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 9748 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 9749 | return ""; |
d5b7b3ae | 9750 | |
6d3d9133 NC |
9751 | /* Generate the return instruction. */ |
9752 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
9753 | { | |
9754 | case ARM_FT_EXCEPTION_HANDLER: | |
6d3d9133 NC |
9755 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); |
9756 | break; | |
0616531f | 9757 | |
6d3d9133 NC |
9758 | case ARM_FT_ISR: |
9759 | case ARM_FT_FIQ: | |
9760 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
9761 | break; | |
9762 | ||
9763 | case ARM_FT_EXCEPTION: | |
9764 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
9765 | break; | |
9766 | ||
9767 | case ARM_FT_INTERWORKED: | |
9768 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
9769 | break; | |
9770 | ||
9771 | default: | |
68d560d4 RE |
9772 | if (arm_arch5 || arm_arch4t) |
9773 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
9774 | else | |
9775 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 9776 | break; |
cce8749e | 9777 | } |
f3bb6135 | 9778 | |
949d79eb RE |
9779 | return ""; |
9780 | } | |
9781 | ||
08c148a8 | 9782 | static void |
e32bac5b | 9783 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 9784 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 9785 | { |
5848830f PB |
9786 | arm_stack_offsets *offsets; |
9787 | ||
d5b7b3ae RE |
9788 | if (TARGET_THUMB) |
9789 | { | |
9790 | /* ??? Probably not safe to set this here, since it assumes that a | |
9791 | function will be emitted as assembly immediately after we generate | |
9792 | RTL for it. This does not happen for inline functions. */ | |
9793 | return_used_this_function = 0; | |
9794 | } | |
9795 | else | |
9796 | { | |
0977774b | 9797 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 9798 | offsets = arm_get_frame_offsets (); |
0977774b | 9799 | |
a72d4945 | 9800 | if (use_return_insn (FALSE, NULL) |
d5b7b3ae | 9801 | && return_used_this_function |
5848830f | 9802 | && offsets->saved_regs != offsets->outgoing_args |
5895f793 | 9803 | && !frame_pointer_needed) |
d5b7b3ae | 9804 | abort (); |
f3bb6135 | 9805 | |
d5b7b3ae | 9806 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
9807 | after_arm_reorg = 0; |
9808 | } | |
f3bb6135 | 9809 | } |
e2c671ba | 9810 | |
2c849145 JM |
9811 | /* Generate and emit an insn that we will recognize as a push_multi. |
9812 | Unfortunately, since this insn does not reflect very well the actual | |
9813 | semantics of the operation, we need to annotate the insn for the benefit | |
9814 | of DWARF2 frame unwind information. */ | |
2c849145 | 9815 | static rtx |
e32bac5b | 9816 | emit_multi_reg_push (int mask) |
e2c671ba RE |
9817 | { |
9818 | int num_regs = 0; | |
9b598fa0 | 9819 | int num_dwarf_regs; |
e2c671ba RE |
9820 | int i, j; |
9821 | rtx par; | |
2c849145 | 9822 | rtx dwarf; |
87e27392 | 9823 | int dwarf_par_index; |
2c849145 | 9824 | rtx tmp, reg; |
e2c671ba | 9825 | |
d5b7b3ae | 9826 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 9827 | if (mask & (1 << i)) |
5895f793 | 9828 | num_regs++; |
e2c671ba RE |
9829 | |
9830 | if (num_regs == 0 || num_regs > 16) | |
9831 | abort (); | |
9832 | ||
9b598fa0 RE |
9833 | /* We don't record the PC in the dwarf frame information. */ |
9834 | num_dwarf_regs = num_regs; | |
9835 | if (mask & (1 << PC_REGNUM)) | |
9836 | num_dwarf_regs--; | |
9837 | ||
87e27392 | 9838 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 9839 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
9840 | by the push_multi pattern in the arm.md file. The insn looks |
9841 | something like this: | |
9842 | ||
9843 | (parallel [ | |
b15bca31 RE |
9844 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
9845 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
9846 | (use (reg:SI 11 fp)) |
9847 | (use (reg:SI 12 ip)) | |
9848 | (use (reg:SI 14 lr)) | |
9849 | (use (reg:SI 15 pc)) | |
9850 | ]) | |
9851 | ||
9852 | For the frame note however, we try to be more explicit and actually | |
9853 | show each register being stored into the stack frame, plus a (single) | |
9854 | decrement of the stack pointer. We do it this way in order to be | |
9855 | friendly to the stack unwinding code, which only wants to see a single | |
9856 | stack decrement per instruction. The RTL we generate for the note looks | |
9857 | something like this: | |
9858 | ||
9859 | (sequence [ | |
9860 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) | |
9861 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
9862 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
9863 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
9864 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
9865 | ]) |
9866 | ||
9867 | This sequence is used both by the code to support stack unwinding for | |
9868 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
9869 | ||
43cffd11 | 9870 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 9871 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 9872 | dwarf_par_index = 1; |
e2c671ba | 9873 | |
d5b7b3ae | 9874 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
9875 | { |
9876 | if (mask & (1 << i)) | |
9877 | { | |
2c849145 JM |
9878 | reg = gen_rtx_REG (SImode, i); |
9879 | ||
e2c671ba | 9880 | XVECEXP (par, 0, 0) |
43cffd11 RE |
9881 | = gen_rtx_SET (VOIDmode, |
9882 | gen_rtx_MEM (BLKmode, | |
9883 | gen_rtx_PRE_DEC (BLKmode, | |
9884 | stack_pointer_rtx)), | |
9885 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 9886 | gen_rtvec (1, reg), |
9b598fa0 | 9887 | UNSPEC_PUSH_MULT)); |
2c849145 | 9888 | |
9b598fa0 RE |
9889 | if (i != PC_REGNUM) |
9890 | { | |
9891 | tmp = gen_rtx_SET (VOIDmode, | |
9892 | gen_rtx_MEM (SImode, stack_pointer_rtx), | |
9893 | reg); | |
9894 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9895 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
9896 | dwarf_par_index++; | |
9897 | } | |
2c849145 | 9898 | |
e2c671ba RE |
9899 | break; |
9900 | } | |
9901 | } | |
9902 | ||
9903 | for (j = 1, i++; j < num_regs; i++) | |
9904 | { | |
9905 | if (mask & (1 << i)) | |
9906 | { | |
2c849145 JM |
9907 | reg = gen_rtx_REG (SImode, i); |
9908 | ||
9909 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
9910 | ||
9b598fa0 RE |
9911 | if (i != PC_REGNUM) |
9912 | { | |
9913 | tmp = gen_rtx_SET (VOIDmode, | |
9914 | gen_rtx_MEM (SImode, | |
9915 | plus_constant (stack_pointer_rtx, | |
9916 | 4 * j)), | |
9917 | reg); | |
9918 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9919 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
9920 | } | |
9921 | ||
e2c671ba RE |
9922 | j++; |
9923 | } | |
9924 | } | |
b111229a | 9925 | |
2c849145 | 9926 | par = emit_insn (par); |
87e27392 NC |
9927 | |
9928 | tmp = gen_rtx_SET (SImode, | |
9929 | stack_pointer_rtx, | |
9930 | gen_rtx_PLUS (SImode, | |
9931 | stack_pointer_rtx, | |
9932 | GEN_INT (-4 * num_regs))); | |
9933 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9934 | XVECEXP (dwarf, 0, 0) = tmp; | |
9935 | ||
2c849145 JM |
9936 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, |
9937 | REG_NOTES (par)); | |
9938 | return par; | |
b111229a RE |
9939 | } |
9940 | ||
2c849145 | 9941 | static rtx |
e32bac5b | 9942 | emit_sfm (int base_reg, int count) |
b111229a RE |
9943 | { |
9944 | rtx par; | |
2c849145 JM |
9945 | rtx dwarf; |
9946 | rtx tmp, reg; | |
b111229a RE |
9947 | int i; |
9948 | ||
43cffd11 | 9949 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 | 9950 | dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
2c849145 JM |
9951 | |
9952 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
9953 | |
9954 | XVECEXP (par, 0, 0) | |
9955 | = gen_rtx_SET (VOIDmode, | |
9956 | gen_rtx_MEM (BLKmode, | |
9957 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
9958 | gen_rtx_UNSPEC (BLKmode, | |
2c849145 | 9959 | gen_rtvec (1, reg), |
b15bca31 | 9960 | UNSPEC_PUSH_MULT)); |
2c849145 JM |
9961 | tmp |
9962 | = gen_rtx_SET (VOIDmode, | |
9963 | gen_rtx_MEM (XFmode, | |
9964 | gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), | |
9965 | reg); | |
9966 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9967 | XVECEXP (dwarf, 0, count - 1) = tmp; | |
9968 | ||
b111229a | 9969 | for (i = 1; i < count; i++) |
2c849145 JM |
9970 | { |
9971 | reg = gen_rtx_REG (XFmode, base_reg++); | |
9972 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
9973 | ||
9974 | tmp = gen_rtx_SET (VOIDmode, | |
9975 | gen_rtx_MEM (XFmode, | |
9976 | gen_rtx_PRE_DEC (BLKmode, | |
9977 | stack_pointer_rtx)), | |
9978 | reg); | |
9979 | RTX_FRAME_RELATED_P (tmp) = 1; | |
9980 | XVECEXP (dwarf, 0, count - i - 1) = tmp; | |
9981 | } | |
b111229a | 9982 | |
2c849145 JM |
9983 | par = emit_insn (par); |
9984 | REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
9985 | REG_NOTES (par)); | |
9986 | return par; | |
e2c671ba RE |
9987 | } |
9988 | ||
9b66ebb1 | 9989 | |
3c7ad43e PB |
9990 | /* Return true if the current function needs to save/restore LR. */ |
9991 | ||
9992 | static bool | |
9993 | thumb_force_lr_save (void) | |
9994 | { | |
9995 | return !cfun->machine->lr_save_eliminated | |
9996 | && (!leaf_function_p () | |
9997 | || thumb_far_jump_used_p () | |
9998 | || regs_ever_live [LR_REGNUM]); | |
9999 | } | |
10000 | ||
10001 | ||
095bb276 NC |
10002 | /* Compute the distance from register FROM to register TO. |
10003 | These can be the arg pointer (26), the soft frame pointer (25), | |
10004 | the stack pointer (13) or the hard frame pointer (11). | |
10005 | Typical stack layout looks like this: | |
10006 | ||
10007 | old stack pointer -> | | | |
10008 | ---- | |
10009 | | | \ | |
10010 | | | saved arguments for | |
10011 | | | vararg functions | |
10012 | | | / | |
10013 | -- | |
10014 | hard FP & arg pointer -> | | \ | |
10015 | | | stack | |
10016 | | | frame | |
10017 | | | / | |
10018 | -- | |
10019 | | | \ | |
10020 | | | call saved | |
10021 | | | registers | |
10022 | soft frame pointer -> | | / | |
10023 | -- | |
10024 | | | \ | |
10025 | | | local | |
10026 | | | variables | |
10027 | | | / | |
10028 | -- | |
10029 | | | \ | |
10030 | | | outgoing | |
10031 | | | arguments | |
10032 | current stack pointer -> | | / | |
10033 | -- | |
10034 | ||
43aa4e05 | 10035 | For a given function some or all of these stack components |
095bb276 NC |
10036 | may not be needed, giving rise to the possibility of |
10037 | eliminating some of the registers. | |
10038 | ||
825dda42 | 10039 | The values returned by this function must reflect the behavior |
095bb276 NC |
10040 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
10041 | ||
10042 | The sign of the number returned reflects the direction of stack | |
10043 | growth, so the values are positive for all eliminations except | |
5848830f PB |
10044 | from the soft frame pointer to the hard frame pointer. |
10045 | ||
10046 | SFP may point just inside the local variables block to ensure correct | |
10047 | alignment. */ | |
10048 | ||
10049 | ||
10050 | /* Calculate stack offsets. These are used to calculate register elimination | |
10051 | offsets and in prologue/epilogue code. */ | |
10052 | ||
10053 | static arm_stack_offsets * | |
10054 | arm_get_frame_offsets (void) | |
095bb276 | 10055 | { |
5848830f | 10056 | struct arm_stack_offsets *offsets; |
095bb276 | 10057 | unsigned long func_type; |
5848830f | 10058 | int leaf; |
5848830f PB |
10059 | int saved; |
10060 | HOST_WIDE_INT frame_size; | |
10061 | ||
10062 | offsets = &cfun->machine->stack_offsets; | |
095bb276 | 10063 | |
5848830f PB |
10064 | /* We need to know if we are a leaf function. Unfortunately, it |
10065 | is possible to be called after start_sequence has been called, | |
10066 | which causes get_insns to return the insns for the sequence, | |
10067 | not the function, which will cause leaf_function_p to return | |
10068 | the incorrect result. | |
095bb276 | 10069 | |
5848830f PB |
10070 | to know about leaf functions once reload has completed, and the |
10071 | frame size cannot be changed after that time, so we can safely | |
10072 | use the cached value. */ | |
10073 | ||
10074 | if (reload_completed) | |
10075 | return offsets; | |
10076 | ||
666c27b9 KH |
10077 | /* Initially this is the size of the local variables. It will translated |
10078 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
10079 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
10080 | ||
10081 | leaf = leaf_function_p (); | |
10082 | ||
10083 | /* Space for variadic functions. */ | |
10084 | offsets->saved_args = current_function_pretend_args_size; | |
10085 | ||
10086 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0); | |
10087 | ||
10088 | if (TARGET_ARM) | |
095bb276 | 10089 | { |
5848830f | 10090 | unsigned int regno; |
ef7112de | 10091 | |
5848830f | 10092 | saved = bit_count (arm_compute_save_reg_mask ()) * 4; |
5a9335ef | 10093 | |
5848830f PB |
10094 | /* We know that SP will be doubleword aligned on entry, and we must |
10095 | preserve that condition at any subroutine call. We also require the | |
10096 | soft frame pointer to be doubleword aligned. */ | |
10097 | ||
10098 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 10099 | { |
5848830f PB |
10100 | /* Check for the call-saved iWMMXt registers. */ |
10101 | for (regno = FIRST_IWMMXT_REGNUM; | |
10102 | regno <= LAST_IWMMXT_REGNUM; | |
10103 | regno++) | |
10104 | if (regs_ever_live [regno] && ! call_used_regs [regno]) | |
10105 | saved += 8; | |
10106 | } | |
10107 | ||
10108 | func_type = arm_current_func_type (); | |
10109 | if (! IS_VOLATILE (func_type)) | |
10110 | { | |
10111 | /* Space for saved FPA registers. */ | |
10112 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
10113 | if (regs_ever_live[regno] && ! call_used_regs[regno]) | |
10114 | saved += 12; | |
10115 | ||
10116 | /* Space for saved VFP registers. */ | |
10117 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 10118 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 10119 | } |
5848830f PB |
10120 | } |
10121 | else /* TARGET_THUMB */ | |
10122 | { | |
10123 | int reg; | |
10124 | int count_regs; | |
10125 | ||
10126 | saved = 0; | |
10127 | count_regs = 0; | |
10128 | for (reg = 8; reg < 13; reg ++) | |
10129 | if (THUMB_REG_PUSHED_P (reg)) | |
10130 | count_regs ++; | |
10131 | if (count_regs) | |
10132 | saved += 4 * count_regs; | |
10133 | count_regs = 0; | |
10134 | for (reg = 0; reg <= LAST_LO_REGNUM; reg ++) | |
10135 | if (THUMB_REG_PUSHED_P (reg)) | |
10136 | count_regs ++; | |
3c7ad43e | 10137 | if (count_regs || thumb_force_lr_save ()) |
5848830f PB |
10138 | saved += 4 * (count_regs + 1); |
10139 | if (TARGET_BACKTRACE) | |
10140 | { | |
10141 | if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) | |
10142 | saved += 20; | |
10143 | else | |
10144 | saved += 16; | |
10145 | } | |
10146 | } | |
9b66ebb1 | 10147 | |
5848830f PB |
10148 | /* Saved registers include the stack frame. */ |
10149 | offsets->saved_regs = offsets->saved_args + saved; | |
10150 | offsets->soft_frame = offsets->saved_regs; | |
10151 | /* A leaf function does not need any stack alignment if it has nothing | |
10152 | on the stack. */ | |
10153 | if (leaf && frame_size == 0) | |
10154 | { | |
10155 | offsets->outgoing_args = offsets->soft_frame; | |
10156 | return offsets; | |
10157 | } | |
10158 | ||
10159 | /* Ensure SFP has the correct alignment. */ | |
10160 | if (ARM_DOUBLEWORD_ALIGN | |
10161 | && (offsets->soft_frame & 7)) | |
10162 | offsets->soft_frame += 4; | |
10163 | ||
10164 | offsets->outgoing_args = offsets->soft_frame + frame_size | |
10165 | + current_function_outgoing_args_size; | |
10166 | ||
10167 | if (ARM_DOUBLEWORD_ALIGN) | |
10168 | { | |
10169 | /* Ensure SP remains doubleword aligned. */ | |
10170 | if (offsets->outgoing_args & 7) | |
10171 | offsets->outgoing_args += 4; | |
10172 | if (offsets->outgoing_args & 7) | |
10173 | abort (); | |
095bb276 NC |
10174 | } |
10175 | ||
5848830f PB |
10176 | return offsets; |
10177 | } | |
10178 | ||
10179 | ||
666c27b9 | 10180 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
10181 | offsets are in the direction of stack growth. */ |
10182 | ||
10183 | unsigned int | |
10184 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
10185 | { | |
10186 | arm_stack_offsets *offsets; | |
10187 | ||
10188 | offsets = arm_get_frame_offsets (); | |
095bb276 | 10189 | |
095bb276 NC |
10190 | /* OK, now we have enough information to compute the distances. |
10191 | There must be an entry in these switch tables for each pair | |
10192 | of registers in ELIMINABLE_REGS, even if some of the entries | |
10193 | seem to be redundant or useless. */ | |
10194 | switch (from) | |
10195 | { | |
10196 | case ARG_POINTER_REGNUM: | |
10197 | switch (to) | |
10198 | { | |
10199 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
10200 | return 0; | |
10201 | ||
10202 | case FRAME_POINTER_REGNUM: | |
10203 | /* This is the reverse of the soft frame pointer | |
10204 | to hard frame pointer elimination below. */ | |
5848830f | 10205 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
10206 | |
10207 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
10208 | /* If there is no stack frame then the hard | |
10209 | frame pointer and the arg pointer coincide. */ | |
5848830f | 10210 | if (offsets->frame == offsets->saved_regs) |
095bb276 | 10211 | return 0; |
6de9cd9a DN |
10212 | /* FIXME: Not sure about this. Maybe we should always return 0 ? */ |
10213 | return (frame_pointer_needed | |
10214 | && cfun->static_chain_decl != NULL | |
10215 | && ! cfun->machine->uses_anonymous_args) ? 4 : 0; | |
095bb276 NC |
10216 | |
10217 | case STACK_POINTER_REGNUM: | |
10218 | /* If nothing has been pushed on the stack at all | |
10219 | then this will return -4. This *is* correct! */ | |
5848830f | 10220 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
10221 | |
10222 | default: | |
10223 | abort (); | |
10224 | } | |
10225 | break; | |
10226 | ||
10227 | case FRAME_POINTER_REGNUM: | |
10228 | switch (to) | |
10229 | { | |
10230 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
10231 | return 0; | |
10232 | ||
10233 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
10234 | /* The hard frame pointer points to the top entry in the | |
10235 | stack frame. The soft frame pointer to the bottom entry | |
10236 | in the stack frame. If there is no stack frame at all, | |
10237 | then they are identical. */ | |
5848830f PB |
10238 | |
10239 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
10240 | |
10241 | case STACK_POINTER_REGNUM: | |
5848830f | 10242 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
10243 | |
10244 | default: | |
10245 | abort (); | |
10246 | } | |
10247 | break; | |
10248 | ||
10249 | default: | |
10250 | /* You cannot eliminate from the stack pointer. | |
10251 | In theory you could eliminate from the hard frame | |
10252 | pointer to the stack pointer, but this will never | |
10253 | happen, since if a stack frame is not needed the | |
10254 | hard frame pointer will never be used. */ | |
10255 | abort (); | |
10256 | } | |
10257 | } | |
10258 | ||
0977774b | 10259 | |
6d3d9133 | 10260 | /* Generate the prologue instructions for entry into an ARM function. */ |
e2c671ba | 10261 | void |
e32bac5b | 10262 | arm_expand_prologue (void) |
e2c671ba RE |
10263 | { |
10264 | int reg; | |
6d3d9133 | 10265 | rtx amount; |
2c849145 | 10266 | rtx insn; |
68dfd979 | 10267 | rtx ip_rtx; |
6d3d9133 NC |
10268 | unsigned long live_regs_mask; |
10269 | unsigned long func_type; | |
68dfd979 | 10270 | int fp_offset = 0; |
095bb276 | 10271 | int saved_pretend_args = 0; |
5848830f | 10272 | int saved_regs = 0; |
095bb276 | 10273 | unsigned int args_to_push; |
5848830f | 10274 | arm_stack_offsets *offsets; |
d3236b4d | 10275 | |
6d3d9133 | 10276 | func_type = arm_current_func_type (); |
e2c671ba | 10277 | |
31fdb4d5 | 10278 | /* Naked functions don't have prologues. */ |
6d3d9133 | 10279 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
10280 | return; |
10281 | ||
095bb276 NC |
10282 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
10283 | args_to_push = current_function_pretend_args_size; | |
10284 | ||
6d3d9133 NC |
10285 | /* Compute which register we will have to save onto the stack. */ |
10286 | live_regs_mask = arm_compute_save_reg_mask (); | |
e2c671ba | 10287 | |
68dfd979 | 10288 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 10289 | |
e2c671ba RE |
10290 | if (frame_pointer_needed) |
10291 | { | |
7b8b8ade NC |
10292 | if (IS_INTERRUPT (func_type)) |
10293 | { | |
10294 | /* Interrupt functions must not corrupt any registers. | |
10295 | Creating a frame pointer however, corrupts the IP | |
10296 | register, so we must push it first. */ | |
10297 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
10298 | |
10299 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
10300 | The dwarf stack unwinding code only wants to see one | |
10301 | stack decrement per function, and this is not it. If | |
10302 | this instruction is labeled as being part of the frame | |
10303 | creation sequence then dwarf2out_frame_debug_expr will | |
10304 | abort when it encounters the assignment of IP to FP | |
10305 | later on, since the use of SP here establishes SP as | |
10306 | the CFA register and not IP. | |
10307 | ||
10308 | Anyway this instruction is not really part of the stack | |
10309 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
10310 | } |
10311 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
10312 | { |
10313 | /* The Static chain register is the same as the IP register | |
10314 | used as a scratch register during stack frame creation. | |
10315 | To get around this need to find somewhere to store IP | |
10316 | whilst the frame is being created. We try the following | |
10317 | places in order: | |
10318 | ||
6d3d9133 | 10319 | 1. The last argument register. |
68dfd979 NC |
10320 | 2. A slot on the stack above the frame. (This only |
10321 | works if the function is not a varargs function). | |
095bb276 NC |
10322 | 3. Register r3, after pushing the argument registers |
10323 | onto the stack. | |
6d3d9133 | 10324 | |
34ce3d7b JM |
10325 | Note - we only need to tell the dwarf2 backend about the SP |
10326 | adjustment in the second variant; the static chain register | |
10327 | doesn't need to be unwound, as it doesn't contain a value | |
10328 | inherited from the caller. */ | |
d3236b4d | 10329 | |
68dfd979 NC |
10330 | if (regs_ever_live[3] == 0) |
10331 | { | |
10332 | insn = gen_rtx_REG (SImode, 3); | |
10333 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
d3236b4d | 10334 | insn = emit_insn (insn); |
68dfd979 | 10335 | } |
095bb276 | 10336 | else if (args_to_push == 0) |
68dfd979 | 10337 | { |
34ce3d7b | 10338 | rtx dwarf; |
68dfd979 NC |
10339 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
10340 | insn = gen_rtx_MEM (SImode, insn); | |
10341 | insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); | |
10342 | insn = emit_insn (insn); | |
34ce3d7b | 10343 | |
68dfd979 | 10344 | fp_offset = 4; |
34ce3d7b JM |
10345 | |
10346 | /* Just tell the dwarf backend that we adjusted SP. */ | |
10347 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
10348 | gen_rtx_PLUS (SImode, stack_pointer_rtx, | |
10349 | GEN_INT (-fp_offset))); | |
10350 | RTX_FRAME_RELATED_P (insn) = 1; | |
10351 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
10352 | dwarf, REG_NOTES (insn)); | |
68dfd979 NC |
10353 | } |
10354 | else | |
095bb276 NC |
10355 | { |
10356 | /* Store the args on the stack. */ | |
3cb66fd7 | 10357 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
10358 | insn = emit_multi_reg_push |
10359 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
10360 | else | |
10361 | insn = emit_insn | |
10362 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
10363 | GEN_INT (- args_to_push))); | |
10364 | ||
10365 | RTX_FRAME_RELATED_P (insn) = 1; | |
10366 | ||
10367 | saved_pretend_args = 1; | |
10368 | fp_offset = args_to_push; | |
10369 | args_to_push = 0; | |
10370 | ||
10371 | /* Now reuse r3 to preserve IP. */ | |
10372 | insn = gen_rtx_REG (SImode, 3); | |
10373 | insn = gen_rtx_SET (SImode, insn, ip_rtx); | |
10374 | (void) emit_insn (insn); | |
10375 | } | |
68dfd979 NC |
10376 | } |
10377 | ||
68dfd979 NC |
10378 | if (fp_offset) |
10379 | { | |
10380 | insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); | |
10381 | insn = gen_rtx_SET (SImode, ip_rtx, insn); | |
10382 | } | |
10383 | else | |
10384 | insn = gen_movsi (ip_rtx, stack_pointer_rtx); | |
10385 | ||
6d3d9133 | 10386 | insn = emit_insn (insn); |
8e56560e | 10387 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
10388 | } |
10389 | ||
095bb276 | 10390 | if (args_to_push) |
e2c671ba | 10391 | { |
6d3d9133 | 10392 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 10393 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 10394 | insn = emit_multi_reg_push |
095bb276 | 10395 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 10396 | else |
2c849145 JM |
10397 | insn = emit_insn |
10398 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
095bb276 | 10399 | GEN_INT (- args_to_push))); |
2c849145 | 10400 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
10401 | } |
10402 | ||
06bea5aa NC |
10403 | /* If this is an interrupt service routine, and the link register |
10404 | is going to be pushed, and we are not creating a stack frame, | |
10405 | (which would involve an extra push of IP and a pop in the epilogue) | |
10406 | subtracting four from LR now will mean that the function return | |
10407 | can be done with a single instruction. */ | |
3a7731fd | 10408 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa NC |
10409 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
10410 | && ! frame_pointer_needed) | |
10411 | emit_insn (gen_rtx_SET (SImode, | |
10412 | gen_rtx_REG (SImode, LR_REGNUM), | |
10413 | gen_rtx_PLUS (SImode, | |
10414 | gen_rtx_REG (SImode, LR_REGNUM), | |
10415 | GEN_INT (-4)))); | |
3a7731fd | 10416 | |
e2c671ba RE |
10417 | if (live_regs_mask) |
10418 | { | |
2c849145 | 10419 | insn = emit_multi_reg_push (live_regs_mask); |
5848830f | 10420 | saved_regs += bit_count (live_regs_mask) * 4; |
2c849145 | 10421 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 10422 | } |
d5b7b3ae | 10423 | |
5a9335ef | 10424 | if (TARGET_IWMMXT) |
01d4c813 | 10425 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
5a9335ef NC |
10426 | if (regs_ever_live[reg] && ! call_used_regs [reg]) |
10427 | { | |
10428 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
10429 | insn = gen_rtx_MEM (V2SImode, insn); | |
10430 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
10431 | gen_rtx_REG (V2SImode, reg))); | |
10432 | RTX_FRAME_RELATED_P (insn) = 1; | |
5848830f | 10433 | saved_regs += 8; |
5a9335ef NC |
10434 | } |
10435 | ||
6d3d9133 | 10436 | if (! IS_VOLATILE (func_type)) |
b111229a | 10437 | { |
9b66ebb1 PB |
10438 | int start_reg; |
10439 | ||
29ad9694 RE |
10440 | /* Save any floating point call-saved registers used by this |
10441 | function. */ | |
10442 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
b111229a | 10443 | { |
9b66ebb1 | 10444 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
5895f793 | 10445 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
2c849145 JM |
10446 | { |
10447 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
10448 | insn = gen_rtx_MEM (XFmode, insn); | |
10449 | insn = emit_insn (gen_rtx_SET (VOIDmode, insn, | |
10450 | gen_rtx_REG (XFmode, reg))); | |
10451 | RTX_FRAME_RELATED_P (insn) = 1; | |
5848830f | 10452 | saved_regs += 12; |
2c849145 | 10453 | } |
b111229a RE |
10454 | } |
10455 | else | |
10456 | { | |
9b66ebb1 | 10457 | start_reg = LAST_FPA_REGNUM; |
b111229a | 10458 | |
9b66ebb1 | 10459 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 10460 | { |
5895f793 | 10461 | if (regs_ever_live[reg] && !call_used_regs[reg]) |
b111229a RE |
10462 | { |
10463 | if (start_reg - reg == 3) | |
10464 | { | |
2c849145 JM |
10465 | insn = emit_sfm (reg, 4); |
10466 | RTX_FRAME_RELATED_P (insn) = 1; | |
4b763d77 | 10467 | saved_regs += 48; |
b111229a RE |
10468 | start_reg = reg - 1; |
10469 | } | |
10470 | } | |
10471 | else | |
10472 | { | |
10473 | if (start_reg != reg) | |
2c849145 JM |
10474 | { |
10475 | insn = emit_sfm (reg + 1, start_reg - reg); | |
10476 | RTX_FRAME_RELATED_P (insn) = 1; | |
7aebacee | 10477 | saved_regs += (start_reg - reg) * 12; |
2c849145 | 10478 | } |
b111229a RE |
10479 | start_reg = reg - 1; |
10480 | } | |
10481 | } | |
10482 | ||
10483 | if (start_reg != reg) | |
2c849145 JM |
10484 | { |
10485 | insn = emit_sfm (reg + 1, start_reg - reg); | |
7aebacee | 10486 | saved_regs += (start_reg - reg) * 12; |
2c849145 JM |
10487 | RTX_FRAME_RELATED_P (insn) = 1; |
10488 | } | |
b111229a | 10489 | } |
9b66ebb1 PB |
10490 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
10491 | { | |
10492 | start_reg = FIRST_VFP_REGNUM; | |
10493 | ||
10494 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
10495 | { | |
10496 | if ((!regs_ever_live[reg] || call_used_regs[reg]) | |
10497 | && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) | |
10498 | { | |
10499 | if (start_reg != reg) | |
9728c9d1 PB |
10500 | saved_regs += vfp_emit_fstmx (start_reg, |
10501 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
10502 | start_reg = reg + 2; |
10503 | } | |
10504 | } | |
10505 | if (start_reg != reg) | |
9728c9d1 PB |
10506 | saved_regs += vfp_emit_fstmx (start_reg, |
10507 | (reg - start_reg) / 2); | |
9b66ebb1 | 10508 | } |
b111229a | 10509 | } |
e2c671ba RE |
10510 | |
10511 | if (frame_pointer_needed) | |
2c849145 | 10512 | { |
6d3d9133 | 10513 | /* Create the new frame pointer. */ |
095bb276 | 10514 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
68dfd979 | 10515 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); |
2c849145 | 10516 | RTX_FRAME_RELATED_P (insn) = 1; |
68dfd979 | 10517 | |
6d3d9133 | 10518 | if (IS_NESTED (func_type)) |
68dfd979 NC |
10519 | { |
10520 | /* Recover the static chain register. */ | |
095bb276 NC |
10521 | if (regs_ever_live [3] == 0 |
10522 | || saved_pretend_args) | |
1d6e90ac | 10523 | insn = gen_rtx_REG (SImode, 3); |
68dfd979 NC |
10524 | else /* if (current_function_pretend_args_size == 0) */ |
10525 | { | |
29ad9694 RE |
10526 | insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, |
10527 | GEN_INT (4)); | |
68dfd979 | 10528 | insn = gen_rtx_MEM (SImode, insn); |
68dfd979 | 10529 | } |
1d6e90ac | 10530 | |
c14a3a45 NC |
10531 | emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); |
10532 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 10533 | emit_insn (gen_prologue_use (ip_rtx)); |
68dfd979 | 10534 | } |
2c849145 | 10535 | } |
e2c671ba | 10536 | |
5848830f PB |
10537 | offsets = arm_get_frame_offsets (); |
10538 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) | |
e2c671ba | 10539 | { |
745b9093 JM |
10540 | /* This add can produce multiple insns for a large constant, so we |
10541 | need to get tricky. */ | |
10542 | rtx last = get_last_insn (); | |
5848830f PB |
10543 | |
10544 | amount = GEN_INT (offsets->saved_args + saved_regs | |
10545 | - offsets->outgoing_args); | |
10546 | ||
2c849145 JM |
10547 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
10548 | amount)); | |
745b9093 JM |
10549 | do |
10550 | { | |
10551 | last = last ? NEXT_INSN (last) : get_insns (); | |
10552 | RTX_FRAME_RELATED_P (last) = 1; | |
10553 | } | |
10554 | while (last != insn); | |
e04c2d6c RE |
10555 | |
10556 | /* If the frame pointer is needed, emit a special barrier that | |
10557 | will prevent the scheduler from moving stores to the frame | |
10558 | before the stack adjustment. */ | |
10559 | if (frame_pointer_needed) | |
3894f59e RE |
10560 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
10561 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
10562 | } |
10563 | ||
10564 | /* If we are profiling, make sure no instructions are scheduled before | |
f5a1b0d2 NC |
10565 | the call to mcount. Similarly if the user has requested no |
10566 | scheduling in the prolog. */ | |
70f4f91c | 10567 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
e2c671ba | 10568 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
10569 | |
10570 | /* If the link register is being kept alive, with the return address in it, | |
10571 | then make sure that it does not get reused by the ce2 pass. */ | |
10572 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
10573 | { | |
6bacc7b0 | 10574 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); |
6f7ebcbb NC |
10575 | cfun->machine->lr_save_eliminated = 1; |
10576 | } | |
e2c671ba | 10577 | } |
cce8749e | 10578 | \f |
9997d19d RE |
10579 | /* If CODE is 'd', then the X is a condition operand and the instruction |
10580 | should only be executed if the condition is true. | |
ddd5a7c1 | 10581 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
10582 | should only be executed if the condition is false: however, if the mode |
10583 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
10584 | do this because in these circumstances !GE does not necessarily imply LT; | |
10585 | in these cases the instruction pattern will take care to make sure that | |
10586 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 10587 | doing this instruction unconditionally. |
9997d19d RE |
10588 | If CODE is 'N' then X is a floating point operand that must be negated |
10589 | before output. | |
10590 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
10591 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 10592 | void |
e32bac5b | 10593 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
10594 | { |
10595 | switch (code) | |
10596 | { | |
10597 | case '@': | |
f3139301 | 10598 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
10599 | return; |
10600 | ||
d5b7b3ae RE |
10601 | case '_': |
10602 | fputs (user_label_prefix, stream); | |
10603 | return; | |
10604 | ||
9997d19d | 10605 | case '|': |
f3139301 | 10606 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
10607 | return; |
10608 | ||
10609 | case '?': | |
10610 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
cca0a211 RE |
10611 | { |
10612 | if (TARGET_THUMB || current_insn_predicate != NULL) | |
10613 | abort (); | |
10614 | ||
10615 | fputs (arm_condition_codes[arm_current_cc], stream); | |
10616 | } | |
10617 | else if (current_insn_predicate) | |
10618 | { | |
10619 | enum arm_cond_code code; | |
10620 | ||
10621 | if (TARGET_THUMB) | |
10622 | abort (); | |
10623 | ||
10624 | code = get_arm_condition_code (current_insn_predicate); | |
10625 | fputs (arm_condition_codes[code], stream); | |
10626 | } | |
9997d19d RE |
10627 | return; |
10628 | ||
10629 | case 'N': | |
10630 | { | |
10631 | REAL_VALUE_TYPE r; | |
10632 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
10633 | r = REAL_VALUE_NEGATE (r); | |
10634 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
10635 | } | |
10636 | return; | |
10637 | ||
10638 | case 'B': | |
10639 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
10640 | { |
10641 | HOST_WIDE_INT val; | |
5895f793 | 10642 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 10643 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 10644 | } |
9997d19d RE |
10645 | else |
10646 | { | |
10647 | putc ('~', stream); | |
10648 | output_addr_const (stream, x); | |
10649 | } | |
10650 | return; | |
10651 | ||
10652 | case 'i': | |
10653 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
10654 | return; | |
10655 | ||
9b6b54e2 NC |
10656 | /* Truncate Cirrus shift counts. */ |
10657 | case 's': | |
10658 | if (GET_CODE (x) == CONST_INT) | |
10659 | { | |
10660 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
10661 | return; | |
10662 | } | |
10663 | arm_print_operand (stream, x, 0); | |
10664 | return; | |
10665 | ||
9997d19d RE |
10666 | case 'I': |
10667 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
10668 | return; | |
10669 | ||
10670 | case 'S': | |
10671 | { | |
10672 | HOST_WIDE_INT val; | |
5895f793 | 10673 | const char * shift = shift_op (x, &val); |
9997d19d | 10674 | |
e2c671ba RE |
10675 | if (shift) |
10676 | { | |
5895f793 | 10677 | fprintf (stream, ", %s ", shift_op (x, &val)); |
e2c671ba RE |
10678 | if (val == -1) |
10679 | arm_print_operand (stream, XEXP (x, 1), 0); | |
10680 | else | |
4a0a75dd | 10681 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 10682 | } |
9997d19d RE |
10683 | } |
10684 | return; | |
10685 | ||
d5b7b3ae RE |
10686 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
10687 | ||
10688 | In a pair of registers containing a DI or DF value the 'Q' | |
10689 | operand returns the register number of the register containing | |
093354e0 | 10690 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
10691 | the register number of the register containing the most |
10692 | significant part of the value. | |
10693 | ||
10694 | The 'H' operand returns the higher of the two register numbers. | |
10695 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 10696 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
10697 | value is held in the lower number register. The reverse is true |
10698 | on systems where WORDS_BIG_ENDIAN is false. | |
10699 | ||
10700 | The purpose of these operands is to distinguish between cases | |
10701 | where the endian-ness of the values is important (for example | |
10702 | when they are added together), and cases where the endian-ness | |
10703 | is irrelevant, but the order of register operations is important. | |
10704 | For example when loading a value from memory into a register | |
10705 | pair, the endian-ness does not matter. Provided that the value | |
10706 | from the lower memory address is put into the lower numbered | |
10707 | register, and the value from the higher address is put into the | |
10708 | higher numbered register, the load will work regardless of whether | |
10709 | the value being loaded is big-wordian or little-wordian. The | |
10710 | order of the two register loads can matter however, if the address | |
10711 | of the memory location is actually held in one of the registers | |
10712 | being overwritten by the load. */ | |
c1c2bc04 | 10713 | case 'Q': |
d5b7b3ae | 10714 | if (REGNO (x) > LAST_ARM_REGNUM) |
c1c2bc04 | 10715 | abort (); |
d5b7b3ae | 10716 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
10717 | return; |
10718 | ||
9997d19d | 10719 | case 'R': |
d5b7b3ae | 10720 | if (REGNO (x) > LAST_ARM_REGNUM) |
9997d19d | 10721 | abort (); |
d5b7b3ae RE |
10722 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
10723 | return; | |
10724 | ||
10725 | case 'H': | |
10726 | if (REGNO (x) > LAST_ARM_REGNUM) | |
10727 | abort (); | |
10728 | asm_fprintf (stream, "%r", REGNO (x) + 1); | |
9997d19d RE |
10729 | return; |
10730 | ||
10731 | case 'm': | |
d5b7b3ae RE |
10732 | asm_fprintf (stream, "%r", |
10733 | GET_CODE (XEXP (x, 0)) == REG | |
10734 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
10735 | return; |
10736 | ||
10737 | case 'M': | |
dd18ae56 | 10738 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 10739 | REGNO (x), |
e9d7b180 | 10740 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
10741 | return; |
10742 | ||
10743 | case 'd': | |
64e92a26 RE |
10744 | /* CONST_TRUE_RTX means always -- that's the default. */ |
10745 | if (x == const_true_rtx) | |
d5b7b3ae RE |
10746 | return; |
10747 | ||
defc0463 RE |
10748 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
10749 | stream); | |
9997d19d RE |
10750 | return; |
10751 | ||
10752 | case 'D': | |
64e92a26 RE |
10753 | /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever |
10754 | want to do that. */ | |
10755 | if (x == const_true_rtx) | |
10756 | abort (); | |
d5b7b3ae | 10757 | |
defc0463 RE |
10758 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
10759 | (get_arm_condition_code (x))], | |
10760 | stream); | |
9997d19d RE |
10761 | return; |
10762 | ||
9b6b54e2 NC |
10763 | /* Cirrus registers can be accessed in a variety of ways: |
10764 | single floating point (f) | |
10765 | double floating point (d) | |
10766 | 32bit integer (fx) | |
10767 | 64bit integer (dx). */ | |
10768 | case 'W': /* Cirrus register in F mode. */ | |
10769 | case 'X': /* Cirrus register in D mode. */ | |
10770 | case 'Y': /* Cirrus register in FX mode. */ | |
10771 | case 'Z': /* Cirrus register in DX mode. */ | |
10772 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
10773 | abort (); | |
10774 | ||
10775 | fprintf (stream, "mv%s%s", | |
10776 | code == 'W' ? "f" | |
10777 | : code == 'X' ? "d" | |
10778 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
10779 | ||
10780 | return; | |
10781 | ||
10782 | /* Print cirrus register in the mode specified by the register's mode. */ | |
10783 | case 'V': | |
10784 | { | |
10785 | int mode = GET_MODE (x); | |
10786 | ||
10787 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
10788 | abort (); | |
10789 | ||
10790 | fprintf (stream, "mv%s%s", | |
10791 | mode == DFmode ? "d" | |
10792 | : mode == SImode ? "fx" | |
10793 | : mode == DImode ? "dx" | |
10794 | : "f", reg_names[REGNO (x)] + 2); | |
10795 | ||
10796 | return; | |
10797 | } | |
10798 | ||
5a9335ef NC |
10799 | case 'U': |
10800 | if (GET_CODE (x) != REG | |
10801 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
10802 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
10803 | /* Bad value for wCG register number. */ | |
10804 | abort (); | |
10805 | else | |
10806 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
10807 | return; | |
10808 | ||
10809 | /* Print an iWMMXt control register name. */ | |
10810 | case 'w': | |
10811 | if (GET_CODE (x) != CONST_INT | |
10812 | || INTVAL (x) < 0 | |
10813 | || INTVAL (x) >= 16) | |
10814 | /* Bad value for wC register number. */ | |
10815 | abort (); | |
10816 | else | |
10817 | { | |
10818 | static const char * wc_reg_names [16] = | |
10819 | { | |
10820 | "wCID", "wCon", "wCSSF", "wCASF", | |
10821 | "wC4", "wC5", "wC6", "wC7", | |
10822 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
10823 | "wC12", "wC13", "wC14", "wC15" | |
10824 | }; | |
10825 | ||
10826 | fprintf (stream, wc_reg_names [INTVAL (x)]); | |
10827 | } | |
10828 | return; | |
10829 | ||
9b66ebb1 PB |
10830 | /* Print a VFP double precision register name. */ |
10831 | case 'P': | |
10832 | { | |
10833 | int mode = GET_MODE (x); | |
10834 | int num; | |
10835 | ||
10836 | if (mode != DImode && mode != DFmode) | |
10837 | abort (); | |
10838 | ||
10839 | if (GET_CODE (x) != REG | |
10840 | || !IS_VFP_REGNUM (REGNO (x))) | |
10841 | abort (); | |
10842 | ||
10843 | num = REGNO(x) - FIRST_VFP_REGNUM; | |
10844 | if (num & 1) | |
10845 | abort (); | |
10846 | ||
10847 | fprintf (stream, "d%d", num >> 1); | |
10848 | } | |
10849 | return; | |
10850 | ||
9997d19d RE |
10851 | default: |
10852 | if (x == 0) | |
10853 | abort (); | |
10854 | ||
10855 | if (GET_CODE (x) == REG) | |
d5b7b3ae | 10856 | asm_fprintf (stream, "%r", REGNO (x)); |
9997d19d RE |
10857 | else if (GET_CODE (x) == MEM) |
10858 | { | |
10859 | output_memory_reference_mode = GET_MODE (x); | |
10860 | output_address (XEXP (x, 0)); | |
10861 | } | |
10862 | else if (GET_CODE (x) == CONST_DOUBLE) | |
10863 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
10864 | else if (GET_CODE (x) == NEG) | |
6354dc9b | 10865 | abort (); /* This should never happen now. */ |
9997d19d RE |
10866 | else |
10867 | { | |
10868 | fputc ('#', stream); | |
10869 | output_addr_const (stream, x); | |
10870 | } | |
10871 | } | |
10872 | } | |
cce8749e | 10873 | \f |
301d03af RS |
10874 | #ifndef AOF_ASSEMBLER |
10875 | /* Target hook for assembling integer objects. The ARM version needs to | |
10876 | handle word-sized values specially. */ | |
301d03af | 10877 | static bool |
e32bac5b | 10878 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
10879 | { |
10880 | if (size == UNITS_PER_WORD && aligned_p) | |
10881 | { | |
10882 | fputs ("\t.word\t", asm_out_file); | |
10883 | output_addr_const (asm_out_file, x); | |
10884 | ||
10885 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 10886 | .text segment, not in the .data segment. */ |
301d03af RS |
10887 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
10888 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
10889 | { | |
e26053d1 | 10890 | if (GET_CODE (x) == SYMBOL_REF |
14f583b8 | 10891 | && (CONSTANT_POOL_ADDRESS_P (x) |
94428622 | 10892 | || SYMBOL_REF_LOCAL_P (x))) |
301d03af RS |
10893 | fputs ("(GOTOFF)", asm_out_file); |
10894 | else if (GET_CODE (x) == LABEL_REF) | |
10895 | fputs ("(GOTOFF)", asm_out_file); | |
10896 | else | |
10897 | fputs ("(GOT)", asm_out_file); | |
10898 | } | |
10899 | fputc ('\n', asm_out_file); | |
10900 | return true; | |
10901 | } | |
1d6e90ac | 10902 | |
5a9335ef NC |
10903 | if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x))) |
10904 | { | |
10905 | int i, units; | |
10906 | ||
10907 | if (GET_CODE (x) != CONST_VECTOR) | |
10908 | abort (); | |
10909 | ||
10910 | units = CONST_VECTOR_NUNITS (x); | |
10911 | ||
10912 | switch (GET_MODE (x)) | |
10913 | { | |
10914 | case V2SImode: size = 4; break; | |
10915 | case V4HImode: size = 2; break; | |
10916 | case V8QImode: size = 1; break; | |
10917 | default: | |
10918 | abort (); | |
10919 | } | |
10920 | ||
10921 | for (i = 0; i < units; i++) | |
10922 | { | |
10923 | rtx elt; | |
10924 | ||
10925 | elt = CONST_VECTOR_ELT (x, i); | |
10926 | assemble_integer | |
10927 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
10928 | } | |
10929 | ||
10930 | return true; | |
10931 | } | |
10932 | ||
301d03af RS |
10933 | return default_assemble_integer (x, size, aligned_p); |
10934 | } | |
10935 | #endif | |
10936 | \f | |
cce8749e CH |
10937 | /* A finite state machine takes care of noticing whether or not instructions |
10938 | can be conditionally executed, and thus decrease execution time and code | |
10939 | size by deleting branch instructions. The fsm is controlled by | |
10940 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
10941 | ||
10942 | /* The state of the fsm controlling condition codes are: | |
10943 | 0: normal, do nothing special | |
10944 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
10945 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
10946 | 3: make instructions conditional | |
10947 | 4: make instructions conditional | |
10948 | ||
10949 | State transitions (state->state by whom under condition): | |
10950 | 0 -> 1 final_prescan_insn if the `target' is a label | |
10951 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
10952 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
10953 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 10954 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
10955 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
10956 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
10957 | (the target insn is arm_target_insn). | |
10958 | ||
ff9940b0 RE |
10959 | If the jump clobbers the conditions then we use states 2 and 4. |
10960 | ||
10961 | A similar thing can be done with conditional return insns. | |
10962 | ||
cce8749e CH |
10963 | XXX In case the `target' is an unconditional branch, this conditionalising |
10964 | of the instructions always reduces code size, but not always execution | |
10965 | time. But then, I want to reduce the code size to somewhere near what | |
10966 | /bin/cc produces. */ | |
10967 | ||
cce8749e CH |
10968 | /* Returns the index of the ARM condition code string in |
10969 | `arm_condition_codes'. COMPARISON should be an rtx like | |
10970 | `(eq (...) (...))'. */ | |
84ed5e79 | 10971 | static enum arm_cond_code |
e32bac5b | 10972 | get_arm_condition_code (rtx comparison) |
cce8749e | 10973 | { |
5165176d | 10974 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
1d6e90ac NC |
10975 | int code; |
10976 | enum rtx_code comp_code = GET_CODE (comparison); | |
5165176d RE |
10977 | |
10978 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 10979 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
10980 | XEXP (comparison, 1)); |
10981 | ||
10982 | switch (mode) | |
cce8749e | 10983 | { |
84ed5e79 RE |
10984 | case CC_DNEmode: code = ARM_NE; goto dominance; |
10985 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
10986 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
10987 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
10988 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
10989 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
10990 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
10991 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
10992 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
10993 | case CC_DLTUmode: code = ARM_CC; | |
10994 | ||
10995 | dominance: | |
10996 | if (comp_code != EQ && comp_code != NE) | |
10997 | abort (); | |
10998 | ||
10999 | if (comp_code == EQ) | |
11000 | return ARM_INVERSE_CONDITION_CODE (code); | |
11001 | return code; | |
11002 | ||
5165176d | 11003 | case CC_NOOVmode: |
84ed5e79 | 11004 | switch (comp_code) |
5165176d | 11005 | { |
84ed5e79 RE |
11006 | case NE: return ARM_NE; |
11007 | case EQ: return ARM_EQ; | |
11008 | case GE: return ARM_PL; | |
11009 | case LT: return ARM_MI; | |
5165176d RE |
11010 | default: abort (); |
11011 | } | |
11012 | ||
11013 | case CC_Zmode: | |
84ed5e79 | 11014 | switch (comp_code) |
5165176d | 11015 | { |
84ed5e79 RE |
11016 | case NE: return ARM_NE; |
11017 | case EQ: return ARM_EQ; | |
5165176d RE |
11018 | default: abort (); |
11019 | } | |
11020 | ||
defc0463 RE |
11021 | case CC_Nmode: |
11022 | switch (comp_code) | |
11023 | { | |
11024 | case NE: return ARM_MI; | |
11025 | case EQ: return ARM_PL; | |
11026 | default: abort (); | |
11027 | } | |
11028 | ||
5165176d | 11029 | case CCFPEmode: |
e45b72c4 RE |
11030 | case CCFPmode: |
11031 | /* These encodings assume that AC=1 in the FPA system control | |
11032 | byte. This allows us to handle all cases except UNEQ and | |
11033 | LTGT. */ | |
84ed5e79 RE |
11034 | switch (comp_code) |
11035 | { | |
11036 | case GE: return ARM_GE; | |
11037 | case GT: return ARM_GT; | |
11038 | case LE: return ARM_LS; | |
11039 | case LT: return ARM_MI; | |
e45b72c4 RE |
11040 | case NE: return ARM_NE; |
11041 | case EQ: return ARM_EQ; | |
11042 | case ORDERED: return ARM_VC; | |
11043 | case UNORDERED: return ARM_VS; | |
11044 | case UNLT: return ARM_LT; | |
11045 | case UNLE: return ARM_LE; | |
11046 | case UNGT: return ARM_HI; | |
11047 | case UNGE: return ARM_PL; | |
11048 | /* UNEQ and LTGT do not have a representation. */ | |
11049 | case UNEQ: /* Fall through. */ | |
11050 | case LTGT: /* Fall through. */ | |
84ed5e79 RE |
11051 | default: abort (); |
11052 | } | |
11053 | ||
11054 | case CC_SWPmode: | |
11055 | switch (comp_code) | |
11056 | { | |
11057 | case NE: return ARM_NE; | |
11058 | case EQ: return ARM_EQ; | |
11059 | case GE: return ARM_LE; | |
11060 | case GT: return ARM_LT; | |
11061 | case LE: return ARM_GE; | |
11062 | case LT: return ARM_GT; | |
11063 | case GEU: return ARM_LS; | |
11064 | case GTU: return ARM_CC; | |
11065 | case LEU: return ARM_CS; | |
11066 | case LTU: return ARM_HI; | |
11067 | default: abort (); | |
11068 | } | |
11069 | ||
bd9c7e23 RE |
11070 | case CC_Cmode: |
11071 | switch (comp_code) | |
11072 | { | |
11073 | case LTU: return ARM_CS; | |
11074 | case GEU: return ARM_CC; | |
11075 | default: abort (); | |
11076 | } | |
11077 | ||
5165176d | 11078 | case CCmode: |
84ed5e79 | 11079 | switch (comp_code) |
5165176d | 11080 | { |
84ed5e79 RE |
11081 | case NE: return ARM_NE; |
11082 | case EQ: return ARM_EQ; | |
11083 | case GE: return ARM_GE; | |
11084 | case GT: return ARM_GT; | |
11085 | case LE: return ARM_LE; | |
11086 | case LT: return ARM_LT; | |
11087 | case GEU: return ARM_CS; | |
11088 | case GTU: return ARM_HI; | |
11089 | case LEU: return ARM_LS; | |
11090 | case LTU: return ARM_CC; | |
5165176d RE |
11091 | default: abort (); |
11092 | } | |
11093 | ||
cce8749e CH |
11094 | default: abort (); |
11095 | } | |
84ed5e79 RE |
11096 | |
11097 | abort (); | |
f3bb6135 | 11098 | } |
cce8749e | 11099 | |
cce8749e | 11100 | void |
e32bac5b | 11101 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
11102 | { |
11103 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 11104 | rtx body = PATTERN (insn); |
cce8749e CH |
11105 | |
11106 | /* This will be 1 if trying to repeat the trick, and things need to be | |
11107 | reversed if it appears to fail. */ | |
11108 | int reverse = 0; | |
11109 | ||
ff9940b0 RE |
11110 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
11111 | taken are clobbered, even if the rtl suggests otherwise. It also | |
11112 | means that we have to grub around within the jump expression to find | |
11113 | out what the conditions are when the jump isn't taken. */ | |
11114 | int jump_clobbers = 0; | |
11115 | ||
6354dc9b | 11116 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 RE |
11117 | int seeking_return = 0; |
11118 | ||
cce8749e CH |
11119 | /* START_INSN will hold the insn from where we start looking. This is the |
11120 | first insn after the following code_label if REVERSE is true. */ | |
11121 | rtx start_insn = insn; | |
11122 | ||
11123 | /* If in state 4, check if the target branch is reached, in order to | |
11124 | change back to state 0. */ | |
11125 | if (arm_ccfsm_state == 4) | |
11126 | { | |
11127 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
11128 | { |
11129 | arm_target_insn = NULL; | |
11130 | arm_ccfsm_state = 0; | |
11131 | } | |
cce8749e CH |
11132 | return; |
11133 | } | |
11134 | ||
11135 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
11136 | unconditional branch to a label, and immediately following this branch | |
11137 | is the previous target label which is only used once, and the label this | |
11138 | branch jumps to is not too far off. */ | |
11139 | if (arm_ccfsm_state == 3) | |
11140 | { | |
11141 | if (simplejump_p (insn)) | |
11142 | { | |
11143 | start_insn = next_nonnote_insn (start_insn); | |
11144 | if (GET_CODE (start_insn) == BARRIER) | |
11145 | { | |
11146 | /* XXX Isn't this always a barrier? */ | |
11147 | start_insn = next_nonnote_insn (start_insn); | |
11148 | } | |
11149 | if (GET_CODE (start_insn) == CODE_LABEL | |
11150 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
11151 | && LABEL_NUSES (start_insn) == 1) | |
11152 | reverse = TRUE; | |
11153 | else | |
11154 | return; | |
11155 | } | |
ff9940b0 RE |
11156 | else if (GET_CODE (body) == RETURN) |
11157 | { | |
11158 | start_insn = next_nonnote_insn (start_insn); | |
11159 | if (GET_CODE (start_insn) == BARRIER) | |
11160 | start_insn = next_nonnote_insn (start_insn); | |
11161 | if (GET_CODE (start_insn) == CODE_LABEL | |
11162 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
11163 | && LABEL_NUSES (start_insn) == 1) | |
11164 | { | |
11165 | reverse = TRUE; | |
11166 | seeking_return = 1; | |
11167 | } | |
11168 | else | |
11169 | return; | |
11170 | } | |
cce8749e CH |
11171 | else |
11172 | return; | |
11173 | } | |
11174 | ||
11175 | if (arm_ccfsm_state != 0 && !reverse) | |
11176 | abort (); | |
11177 | if (GET_CODE (insn) != JUMP_INSN) | |
11178 | return; | |
11179 | ||
ddd5a7c1 | 11180 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
11181 | the jump should always come first */ |
11182 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
11183 | body = XVECEXP (body, 0, 0); | |
11184 | ||
cce8749e CH |
11185 | if (reverse |
11186 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
11187 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
11188 | { | |
bd9c7e23 RE |
11189 | int insns_skipped; |
11190 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
11191 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
11192 | int then_not_else = TRUE; | |
ff9940b0 | 11193 | rtx this_insn = start_insn, label = 0; |
cce8749e | 11194 | |
e45b72c4 RE |
11195 | /* If the jump cannot be done with one instruction, we cannot |
11196 | conditionally execute the instruction in the inverse case. */ | |
ff9940b0 | 11197 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 11198 | { |
5bbe2d40 RE |
11199 | jump_clobbers = 1; |
11200 | return; | |
11201 | } | |
ff9940b0 | 11202 | |
cce8749e CH |
11203 | /* Register the insn jumped to. */ |
11204 | if (reverse) | |
ff9940b0 RE |
11205 | { |
11206 | if (!seeking_return) | |
11207 | label = XEXP (SET_SRC (body), 0); | |
11208 | } | |
cce8749e CH |
11209 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
11210 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
11211 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
11212 | { | |
11213 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
11214 | then_not_else = FALSE; | |
11215 | } | |
ff9940b0 RE |
11216 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
11217 | seeking_return = 1; | |
11218 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
11219 | { | |
11220 | seeking_return = 1; | |
11221 | then_not_else = FALSE; | |
11222 | } | |
cce8749e CH |
11223 | else |
11224 | abort (); | |
11225 | ||
11226 | /* See how many insns this branch skips, and what kind of insns. If all | |
11227 | insns are okay, and the label or unconditional branch to the same | |
11228 | label is not too far away, succeed. */ | |
11229 | for (insns_skipped = 0; | |
b36ba79f | 11230 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
11231 | { |
11232 | rtx scanbody; | |
11233 | ||
11234 | this_insn = next_nonnote_insn (this_insn); | |
11235 | if (!this_insn) | |
11236 | break; | |
11237 | ||
cce8749e CH |
11238 | switch (GET_CODE (this_insn)) |
11239 | { | |
11240 | case CODE_LABEL: | |
11241 | /* Succeed if it is the target label, otherwise fail since | |
11242 | control falls in from somewhere else. */ | |
11243 | if (this_insn == label) | |
11244 | { | |
ff9940b0 RE |
11245 | if (jump_clobbers) |
11246 | { | |
11247 | arm_ccfsm_state = 2; | |
11248 | this_insn = next_nonnote_insn (this_insn); | |
11249 | } | |
11250 | else | |
11251 | arm_ccfsm_state = 1; | |
cce8749e CH |
11252 | succeed = TRUE; |
11253 | } | |
11254 | else | |
11255 | fail = TRUE; | |
11256 | break; | |
11257 | ||
ff9940b0 | 11258 | case BARRIER: |
cce8749e | 11259 | /* Succeed if the following insn is the target label. |
ff9940b0 RE |
11260 | Otherwise fail. |
11261 | If return insns are used then the last insn in a function | |
6354dc9b | 11262 | will be a barrier. */ |
cce8749e | 11263 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 11264 | if (this_insn && this_insn == label) |
cce8749e | 11265 | { |
ff9940b0 RE |
11266 | if (jump_clobbers) |
11267 | { | |
11268 | arm_ccfsm_state = 2; | |
11269 | this_insn = next_nonnote_insn (this_insn); | |
11270 | } | |
11271 | else | |
11272 | arm_ccfsm_state = 1; | |
cce8749e CH |
11273 | succeed = TRUE; |
11274 | } | |
11275 | else | |
11276 | fail = TRUE; | |
11277 | break; | |
11278 | ||
ff9940b0 | 11279 | case CALL_INSN: |
68d560d4 RE |
11280 | /* The AAPCS says that conditional calls should not be |
11281 | used since they make interworking inefficient (the | |
11282 | linker can't transform BL<cond> into BLX). That's | |
11283 | only a problem if the machine has BLX. */ | |
11284 | if (arm_arch5) | |
11285 | { | |
11286 | fail = TRUE; | |
11287 | break; | |
11288 | } | |
11289 | ||
61f0ccff RE |
11290 | /* Succeed if the following insn is the target label, or |
11291 | if the following two insns are a barrier and the | |
11292 | target label. */ | |
11293 | this_insn = next_nonnote_insn (this_insn); | |
11294 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
11295 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 11296 | |
61f0ccff RE |
11297 | if (this_insn && this_insn == label |
11298 | && insns_skipped < max_insns_skipped) | |
11299 | { | |
11300 | if (jump_clobbers) | |
bd9c7e23 | 11301 | { |
61f0ccff RE |
11302 | arm_ccfsm_state = 2; |
11303 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 RE |
11304 | } |
11305 | else | |
61f0ccff RE |
11306 | arm_ccfsm_state = 1; |
11307 | succeed = TRUE; | |
bd9c7e23 | 11308 | } |
61f0ccff RE |
11309 | else |
11310 | fail = TRUE; | |
ff9940b0 | 11311 | break; |
2b835d68 | 11312 | |
cce8749e CH |
11313 | case JUMP_INSN: |
11314 | /* If this is an unconditional branch to the same label, succeed. | |
11315 | If it is to another label, do nothing. If it is conditional, | |
11316 | fail. */ | |
e32bac5b RE |
11317 | /* XXX Probably, the tests for SET and the PC are |
11318 | unnecessary. */ | |
cce8749e | 11319 | |
ed4c4348 | 11320 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
11321 | if (GET_CODE (scanbody) == SET |
11322 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
11323 | { |
11324 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
11325 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
11326 | { | |
11327 | arm_ccfsm_state = 2; | |
11328 | succeed = TRUE; | |
11329 | } | |
11330 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
11331 | fail = TRUE; | |
11332 | } | |
b36ba79f RE |
11333 | /* Fail if a conditional return is undesirable (eg on a |
11334 | StrongARM), but still allow this if optimizing for size. */ | |
11335 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 11336 | && !use_return_insn (TRUE, NULL) |
5895f793 | 11337 | && !optimize_size) |
b36ba79f | 11338 | fail = TRUE; |
ff9940b0 RE |
11339 | else if (GET_CODE (scanbody) == RETURN |
11340 | && seeking_return) | |
11341 | { | |
11342 | arm_ccfsm_state = 2; | |
11343 | succeed = TRUE; | |
11344 | } | |
11345 | else if (GET_CODE (scanbody) == PARALLEL) | |
11346 | { | |
11347 | switch (get_attr_conds (this_insn)) | |
11348 | { | |
11349 | case CONDS_NOCOND: | |
11350 | break; | |
11351 | default: | |
11352 | fail = TRUE; | |
11353 | break; | |
11354 | } | |
11355 | } | |
4e67550b RE |
11356 | else |
11357 | fail = TRUE; /* Unrecognized jump (eg epilogue). */ | |
11358 | ||
cce8749e CH |
11359 | break; |
11360 | ||
11361 | case INSN: | |
ff9940b0 RE |
11362 | /* Instructions using or affecting the condition codes make it |
11363 | fail. */ | |
ed4c4348 | 11364 | scanbody = PATTERN (this_insn); |
5895f793 RE |
11365 | if (!(GET_CODE (scanbody) == SET |
11366 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 11367 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 11368 | fail = TRUE; |
9b6b54e2 NC |
11369 | |
11370 | /* A conditional cirrus instruction must be followed by | |
11371 | a non Cirrus instruction. However, since we | |
11372 | conditionalize instructions in this function and by | |
11373 | the time we get here we can't add instructions | |
11374 | (nops), because shorten_branches() has already been | |
11375 | called, we will disable conditionalizing Cirrus | |
11376 | instructions to be safe. */ | |
11377 | if (GET_CODE (scanbody) != USE | |
11378 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 11379 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 11380 | fail = TRUE; |
cce8749e CH |
11381 | break; |
11382 | ||
11383 | default: | |
11384 | break; | |
11385 | } | |
11386 | } | |
11387 | if (succeed) | |
11388 | { | |
ff9940b0 | 11389 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 11390 | arm_target_label = CODE_LABEL_NUMBER (label); |
ff9940b0 RE |
11391 | else if (seeking_return || arm_ccfsm_state == 2) |
11392 | { | |
11393 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) | |
11394 | { | |
11395 | this_insn = next_nonnote_insn (this_insn); | |
11396 | if (this_insn && (GET_CODE (this_insn) == BARRIER | |
11397 | || GET_CODE (this_insn) == CODE_LABEL)) | |
11398 | abort (); | |
11399 | } | |
11400 | if (!this_insn) | |
11401 | { | |
d6b4baa4 | 11402 | /* Oh, dear! we ran off the end.. give up. */ |
df4ae160 | 11403 | recog (PATTERN (insn), insn, NULL); |
ff9940b0 | 11404 | arm_ccfsm_state = 0; |
abaa26e5 | 11405 | arm_target_insn = NULL; |
ff9940b0 RE |
11406 | return; |
11407 | } | |
11408 | arm_target_insn = this_insn; | |
11409 | } | |
cce8749e CH |
11410 | else |
11411 | abort (); | |
ff9940b0 RE |
11412 | if (jump_clobbers) |
11413 | { | |
11414 | if (reverse) | |
11415 | abort (); | |
11416 | arm_current_cc = | |
11417 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), | |
11418 | 0), 0), 1)); | |
11419 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
11420 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11421 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
11422 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11423 | } | |
11424 | else | |
11425 | { | |
11426 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
11427 | what it was. */ | |
11428 | if (!reverse) | |
11429 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
11430 | 0)); | |
11431 | } | |
cce8749e | 11432 | |
cce8749e CH |
11433 | if (reverse || then_not_else) |
11434 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
11435 | } | |
d5b7b3ae | 11436 | |
1ccbefce | 11437 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 11438 | destroy this array, but final.c assumes that it remains intact |
ddd5a7c1 | 11439 | across this call; since the insn has been recognized already we |
b020fd92 | 11440 | call recog direct). */ |
df4ae160 | 11441 | recog (PATTERN (insn), insn, NULL); |
cce8749e | 11442 | } |
f3bb6135 | 11443 | } |
cce8749e | 11444 | |
4b02997f NC |
11445 | /* Returns true if REGNO is a valid register |
11446 | for holding a quantity of tyoe MODE. */ | |
4b02997f | 11447 | int |
e32bac5b | 11448 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
11449 | { |
11450 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
9b66ebb1 | 11451 | return regno == CC_REGNUM || regno == VFPCC_REGNUM; |
4b02997f NC |
11452 | |
11453 | if (TARGET_THUMB) | |
11454 | /* For the Thumb we only allow values bigger than SImode in | |
11455 | registers 0 - 6, so that there is always a second low | |
11456 | register available to hold the upper part of the value. | |
11457 | We probably we ought to ensure that the register is the | |
11458 | start of an even numbered register pair. */ | |
e9d7b180 | 11459 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 11460 | |
9b6b54e2 NC |
11461 | if (IS_CIRRUS_REGNUM (regno)) |
11462 | /* We have outlawed SI values in Cirrus registers because they | |
11463 | reside in the lower 32 bits, but SF values reside in the | |
11464 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
11465 | even split the registers into pairs because Cirrus SI values | |
11466 | get sign extended to 64bits-- aldyh. */ | |
11467 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
11468 | ||
9b66ebb1 PB |
11469 | if (IS_VFP_REGNUM (regno)) |
11470 | { | |
11471 | if (mode == SFmode || mode == SImode) | |
11472 | return TRUE; | |
11473 | ||
11474 | /* DFmode values are only valid in even register pairs. */ | |
11475 | if (mode == DFmode) | |
11476 | return ((regno - FIRST_VFP_REGNUM) & 1) == 0; | |
11477 | return FALSE; | |
11478 | } | |
11479 | ||
5a9335ef NC |
11480 | if (IS_IWMMXT_GR_REGNUM (regno)) |
11481 | return mode == SImode; | |
11482 | ||
11483 | if (IS_IWMMXT_REGNUM (regno)) | |
11484 | return VALID_IWMMXT_REG_MODE (mode); | |
11485 | ||
fdd695fd PB |
11486 | /* We allow any value to be stored in the general registers. |
11487 | Restrict doubleword quantities to even register pairs so that we can | |
11488 | use ldrd. */ | |
4b02997f | 11489 | if (regno <= LAST_ARM_REGNUM) |
fdd695fd | 11490 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); |
4b02997f NC |
11491 | |
11492 | if ( regno == FRAME_POINTER_REGNUM | |
11493 | || regno == ARG_POINTER_REGNUM) | |
11494 | /* We only allow integers in the fake hard registers. */ | |
11495 | return GET_MODE_CLASS (mode) == MODE_INT; | |
11496 | ||
3b684012 | 11497 | /* The only registers left are the FPA registers |
4b02997f NC |
11498 | which we only allow to hold FP values. */ |
11499 | return GET_MODE_CLASS (mode) == MODE_FLOAT | |
9b66ebb1 PB |
11500 | && regno >= FIRST_FPA_REGNUM |
11501 | && regno <= LAST_FPA_REGNUM; | |
4b02997f NC |
11502 | } |
11503 | ||
d5b7b3ae | 11504 | int |
e32bac5b | 11505 | arm_regno_class (int regno) |
d5b7b3ae RE |
11506 | { |
11507 | if (TARGET_THUMB) | |
11508 | { | |
11509 | if (regno == STACK_POINTER_REGNUM) | |
11510 | return STACK_REG; | |
11511 | if (regno == CC_REGNUM) | |
11512 | return CC_REG; | |
11513 | if (regno < 8) | |
11514 | return LO_REGS; | |
11515 | return HI_REGS; | |
11516 | } | |
11517 | ||
11518 | if ( regno <= LAST_ARM_REGNUM | |
11519 | || regno == FRAME_POINTER_REGNUM | |
11520 | || regno == ARG_POINTER_REGNUM) | |
11521 | return GENERAL_REGS; | |
11522 | ||
9b66ebb1 | 11523 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
d5b7b3ae RE |
11524 | return NO_REGS; |
11525 | ||
9b6b54e2 NC |
11526 | if (IS_CIRRUS_REGNUM (regno)) |
11527 | return CIRRUS_REGS; | |
11528 | ||
9b66ebb1 PB |
11529 | if (IS_VFP_REGNUM (regno)) |
11530 | return VFP_REGS; | |
11531 | ||
5a9335ef NC |
11532 | if (IS_IWMMXT_REGNUM (regno)) |
11533 | return IWMMXT_REGS; | |
11534 | ||
e99faaaa ILT |
11535 | if (IS_IWMMXT_GR_REGNUM (regno)) |
11536 | return IWMMXT_GR_REGS; | |
11537 | ||
3b684012 | 11538 | return FPA_REGS; |
d5b7b3ae RE |
11539 | } |
11540 | ||
11541 | /* Handle a special case when computing the offset | |
11542 | of an argument from the frame pointer. */ | |
11543 | int | |
e32bac5b | 11544 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
11545 | { |
11546 | rtx insn; | |
11547 | ||
11548 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
11549 | if (value != 0) | |
11550 | return 0; | |
11551 | ||
11552 | /* We can only cope with the case where the address is held in a register. */ | |
11553 | if (GET_CODE (addr) != REG) | |
11554 | return 0; | |
11555 | ||
11556 | /* If we are using the frame pointer to point at the argument, then | |
11557 | an offset of 0 is correct. */ | |
cd2b33d0 | 11558 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae RE |
11559 | return 0; |
11560 | ||
11561 | /* If we are using the stack pointer to point at the | |
11562 | argument, then an offset of 0 is correct. */ | |
5895f793 | 11563 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
11564 | && REGNO (addr) == SP_REGNUM) |
11565 | return 0; | |
11566 | ||
11567 | /* Oh dear. The argument is pointed to by a register rather | |
11568 | than being held in a register, or being stored at a known | |
11569 | offset from the frame pointer. Since GDB only understands | |
11570 | those two kinds of argument we must translate the address | |
11571 | held in the register into an offset from the frame pointer. | |
11572 | We do this by searching through the insns for the function | |
11573 | looking to see where this register gets its value. If the | |
4912a07c | 11574 | register is initialized from the frame pointer plus an offset |
d5b7b3ae RE |
11575 | then we are in luck and we can continue, otherwise we give up. |
11576 | ||
11577 | This code is exercised by producing debugging information | |
11578 | for a function with arguments like this: | |
11579 | ||
11580 | double func (double a, double b, int c, double d) {return d;} | |
11581 | ||
11582 | Without this code the stab for parameter 'd' will be set to | |
11583 | an offset of 0 from the frame pointer, rather than 8. */ | |
11584 | ||
11585 | /* The if() statement says: | |
11586 | ||
11587 | If the insn is a normal instruction | |
11588 | and if the insn is setting the value in a register | |
11589 | and if the register being set is the register holding the address of the argument | |
11590 | and if the address is computing by an addition | |
11591 | that involves adding to a register | |
11592 | which is the frame pointer | |
11593 | a constant integer | |
11594 | ||
d6b4baa4 | 11595 | then... */ |
d5b7b3ae RE |
11596 | |
11597 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
11598 | { | |
11599 | if ( GET_CODE (insn) == INSN | |
11600 | && GET_CODE (PATTERN (insn)) == SET | |
11601 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
11602 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
11603 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 11604 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
11605 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
11606 | ) | |
11607 | { | |
11608 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
11609 | ||
11610 | break; | |
11611 | } | |
11612 | } | |
11613 | ||
11614 | if (value == 0) | |
11615 | { | |
11616 | debug_rtx (addr); | |
c725bd79 | 11617 | warning ("unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
11618 | value = 8; /* XXX magic hack */ |
11619 | } | |
11620 | ||
11621 | return value; | |
11622 | } | |
d5b7b3ae | 11623 | \f |
5a9335ef NC |
11624 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
11625 | do \ | |
11626 | { \ | |
11627 | if ((MASK) & insn_flags) \ | |
11628 | builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \ | |
11629 | } \ | |
11630 | while (0) | |
11631 | ||
11632 | struct builtin_description | |
11633 | { | |
11634 | const unsigned int mask; | |
11635 | const enum insn_code icode; | |
11636 | const char * const name; | |
11637 | const enum arm_builtins code; | |
11638 | const enum rtx_code comparison; | |
11639 | const unsigned int flag; | |
11640 | }; | |
11641 | ||
11642 | static const struct builtin_description bdesc_2arg[] = | |
11643 | { | |
11644 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
11645 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
11646 | ARM_BUILTIN_##builtin, 0, 0 }, | |
11647 | ||
11648 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
11649 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
11650 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
11651 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
11652 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
11653 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
11654 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
11655 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
11656 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
11657 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
11658 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
11659 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
11660 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
11661 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
11662 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
11663 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
11664 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
11665 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
11666 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
11667 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
11668 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
11669 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
11670 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
11671 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
11672 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
11673 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
11674 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
11675 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
11676 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
11677 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
11678 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
11679 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
11680 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
11681 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
11682 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
11683 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
11684 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
11685 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
11686 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
11687 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
11688 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
11689 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
11690 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
11691 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
11692 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
11693 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
11694 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
11695 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
11696 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
11697 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
11698 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
11699 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
11700 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
11701 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
11702 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
11703 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
11704 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
11705 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
11706 | ||
11707 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
11708 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, | |
11709 | ||
11710 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) | |
11711 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
11712 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
11713 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
11714 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
11715 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
11716 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
11717 | IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) | |
11718 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) | |
11719 | IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) | |
11720 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) | |
11721 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
11722 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
11723 | IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) | |
11724 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) | |
11725 | IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) | |
11726 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) | |
9b66ebb1 | 11727 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef NC |
11728 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
11729 | IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) | |
11730 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) | |
11731 | IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) | |
11732 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) | |
9b66ebb1 | 11733 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
11734 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
11735 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
11736 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
11737 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
11738 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
11739 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
11740 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
11741 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
11742 | }; | |
11743 | ||
11744 | static const struct builtin_description bdesc_1arg[] = | |
11745 | { | |
11746 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
11747 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
11748 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
11749 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
11750 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
11751 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
11752 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
11753 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
11754 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
11755 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
11756 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
11757 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
11758 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
11759 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
11760 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
11761 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
11762 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
11763 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
11764 | }; | |
11765 | ||
11766 | /* Set up all the iWMMXt builtins. This is | |
11767 | not called if TARGET_IWMMXT is zero. */ | |
11768 | ||
11769 | static void | |
11770 | arm_init_iwmmxt_builtins (void) | |
11771 | { | |
11772 | const struct builtin_description * d; | |
11773 | size_t i; | |
11774 | tree endlink = void_list_node; | |
11775 | ||
4a5eab38 PB |
11776 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
11777 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
11778 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
11779 | ||
5a9335ef NC |
11780 | tree int_ftype_int |
11781 | = build_function_type (integer_type_node, | |
11782 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
11783 | tree v8qi_ftype_v8qi_v8qi_int | |
11784 | = build_function_type (V8QI_type_node, | |
11785 | tree_cons (NULL_TREE, V8QI_type_node, | |
11786 | tree_cons (NULL_TREE, V8QI_type_node, | |
11787 | tree_cons (NULL_TREE, | |
11788 | integer_type_node, | |
11789 | endlink)))); | |
11790 | tree v4hi_ftype_v4hi_int | |
11791 | = build_function_type (V4HI_type_node, | |
11792 | tree_cons (NULL_TREE, V4HI_type_node, | |
11793 | tree_cons (NULL_TREE, integer_type_node, | |
11794 | endlink))); | |
11795 | tree v2si_ftype_v2si_int | |
11796 | = build_function_type (V2SI_type_node, | |
11797 | tree_cons (NULL_TREE, V2SI_type_node, | |
11798 | tree_cons (NULL_TREE, integer_type_node, | |
11799 | endlink))); | |
11800 | tree v2si_ftype_di_di | |
11801 | = build_function_type (V2SI_type_node, | |
11802 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
11803 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
11804 | endlink))); | |
11805 | tree di_ftype_di_int | |
11806 | = build_function_type (long_long_integer_type_node, | |
11807 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
11808 | tree_cons (NULL_TREE, integer_type_node, | |
11809 | endlink))); | |
11810 | tree di_ftype_di_int_int | |
11811 | = build_function_type (long_long_integer_type_node, | |
11812 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
11813 | tree_cons (NULL_TREE, integer_type_node, | |
11814 | tree_cons (NULL_TREE, | |
11815 | integer_type_node, | |
11816 | endlink)))); | |
11817 | tree int_ftype_v8qi | |
11818 | = build_function_type (integer_type_node, | |
11819 | tree_cons (NULL_TREE, V8QI_type_node, | |
11820 | endlink)); | |
11821 | tree int_ftype_v4hi | |
11822 | = build_function_type (integer_type_node, | |
11823 | tree_cons (NULL_TREE, V4HI_type_node, | |
11824 | endlink)); | |
11825 | tree int_ftype_v2si | |
11826 | = build_function_type (integer_type_node, | |
11827 | tree_cons (NULL_TREE, V2SI_type_node, | |
11828 | endlink)); | |
11829 | tree int_ftype_v8qi_int | |
11830 | = build_function_type (integer_type_node, | |
11831 | tree_cons (NULL_TREE, V8QI_type_node, | |
11832 | tree_cons (NULL_TREE, integer_type_node, | |
11833 | endlink))); | |
11834 | tree int_ftype_v4hi_int | |
11835 | = build_function_type (integer_type_node, | |
11836 | tree_cons (NULL_TREE, V4HI_type_node, | |
11837 | tree_cons (NULL_TREE, integer_type_node, | |
11838 | endlink))); | |
11839 | tree int_ftype_v2si_int | |
11840 | = build_function_type (integer_type_node, | |
11841 | tree_cons (NULL_TREE, V2SI_type_node, | |
11842 | tree_cons (NULL_TREE, integer_type_node, | |
11843 | endlink))); | |
11844 | tree v8qi_ftype_v8qi_int_int | |
11845 | = build_function_type (V8QI_type_node, | |
11846 | tree_cons (NULL_TREE, V8QI_type_node, | |
11847 | tree_cons (NULL_TREE, integer_type_node, | |
11848 | tree_cons (NULL_TREE, | |
11849 | integer_type_node, | |
11850 | endlink)))); | |
11851 | tree v4hi_ftype_v4hi_int_int | |
11852 | = build_function_type (V4HI_type_node, | |
11853 | tree_cons (NULL_TREE, V4HI_type_node, | |
11854 | tree_cons (NULL_TREE, integer_type_node, | |
11855 | tree_cons (NULL_TREE, | |
11856 | integer_type_node, | |
11857 | endlink)))); | |
11858 | tree v2si_ftype_v2si_int_int | |
11859 | = build_function_type (V2SI_type_node, | |
11860 | tree_cons (NULL_TREE, V2SI_type_node, | |
11861 | tree_cons (NULL_TREE, integer_type_node, | |
11862 | tree_cons (NULL_TREE, | |
11863 | integer_type_node, | |
11864 | endlink)))); | |
11865 | /* Miscellaneous. */ | |
11866 | tree v8qi_ftype_v4hi_v4hi | |
11867 | = build_function_type (V8QI_type_node, | |
11868 | tree_cons (NULL_TREE, V4HI_type_node, | |
11869 | tree_cons (NULL_TREE, V4HI_type_node, | |
11870 | endlink))); | |
11871 | tree v4hi_ftype_v2si_v2si | |
11872 | = build_function_type (V4HI_type_node, | |
11873 | tree_cons (NULL_TREE, V2SI_type_node, | |
11874 | tree_cons (NULL_TREE, V2SI_type_node, | |
11875 | endlink))); | |
11876 | tree v2si_ftype_v4hi_v4hi | |
11877 | = build_function_type (V2SI_type_node, | |
11878 | tree_cons (NULL_TREE, V4HI_type_node, | |
11879 | tree_cons (NULL_TREE, V4HI_type_node, | |
11880 | endlink))); | |
11881 | tree v2si_ftype_v8qi_v8qi | |
11882 | = build_function_type (V2SI_type_node, | |
11883 | tree_cons (NULL_TREE, V8QI_type_node, | |
11884 | tree_cons (NULL_TREE, V8QI_type_node, | |
11885 | endlink))); | |
11886 | tree v4hi_ftype_v4hi_di | |
11887 | = build_function_type (V4HI_type_node, | |
11888 | tree_cons (NULL_TREE, V4HI_type_node, | |
11889 | tree_cons (NULL_TREE, | |
11890 | long_long_integer_type_node, | |
11891 | endlink))); | |
11892 | tree v2si_ftype_v2si_di | |
11893 | = build_function_type (V2SI_type_node, | |
11894 | tree_cons (NULL_TREE, V2SI_type_node, | |
11895 | tree_cons (NULL_TREE, | |
11896 | long_long_integer_type_node, | |
11897 | endlink))); | |
11898 | tree void_ftype_int_int | |
11899 | = build_function_type (void_type_node, | |
11900 | tree_cons (NULL_TREE, integer_type_node, | |
11901 | tree_cons (NULL_TREE, integer_type_node, | |
11902 | endlink))); | |
11903 | tree di_ftype_void | |
11904 | = build_function_type (long_long_unsigned_type_node, endlink); | |
11905 | tree di_ftype_v8qi | |
11906 | = build_function_type (long_long_integer_type_node, | |
11907 | tree_cons (NULL_TREE, V8QI_type_node, | |
11908 | endlink)); | |
11909 | tree di_ftype_v4hi | |
11910 | = build_function_type (long_long_integer_type_node, | |
11911 | tree_cons (NULL_TREE, V4HI_type_node, | |
11912 | endlink)); | |
11913 | tree di_ftype_v2si | |
11914 | = build_function_type (long_long_integer_type_node, | |
11915 | tree_cons (NULL_TREE, V2SI_type_node, | |
11916 | endlink)); | |
11917 | tree v2si_ftype_v4hi | |
11918 | = build_function_type (V2SI_type_node, | |
11919 | tree_cons (NULL_TREE, V4HI_type_node, | |
11920 | endlink)); | |
11921 | tree v4hi_ftype_v8qi | |
11922 | = build_function_type (V4HI_type_node, | |
11923 | tree_cons (NULL_TREE, V8QI_type_node, | |
11924 | endlink)); | |
11925 | ||
11926 | tree di_ftype_di_v4hi_v4hi | |
11927 | = build_function_type (long_long_unsigned_type_node, | |
11928 | tree_cons (NULL_TREE, | |
11929 | long_long_unsigned_type_node, | |
11930 | tree_cons (NULL_TREE, V4HI_type_node, | |
11931 | tree_cons (NULL_TREE, | |
11932 | V4HI_type_node, | |
11933 | endlink)))); | |
11934 | ||
11935 | tree di_ftype_v4hi_v4hi | |
11936 | = build_function_type (long_long_unsigned_type_node, | |
11937 | tree_cons (NULL_TREE, V4HI_type_node, | |
11938 | tree_cons (NULL_TREE, V4HI_type_node, | |
11939 | endlink))); | |
11940 | ||
11941 | /* Normal vector binops. */ | |
11942 | tree v8qi_ftype_v8qi_v8qi | |
11943 | = build_function_type (V8QI_type_node, | |
11944 | tree_cons (NULL_TREE, V8QI_type_node, | |
11945 | tree_cons (NULL_TREE, V8QI_type_node, | |
11946 | endlink))); | |
11947 | tree v4hi_ftype_v4hi_v4hi | |
11948 | = build_function_type (V4HI_type_node, | |
11949 | tree_cons (NULL_TREE, V4HI_type_node, | |
11950 | tree_cons (NULL_TREE, V4HI_type_node, | |
11951 | endlink))); | |
11952 | tree v2si_ftype_v2si_v2si | |
11953 | = build_function_type (V2SI_type_node, | |
11954 | tree_cons (NULL_TREE, V2SI_type_node, | |
11955 | tree_cons (NULL_TREE, V2SI_type_node, | |
11956 | endlink))); | |
11957 | tree di_ftype_di_di | |
11958 | = build_function_type (long_long_unsigned_type_node, | |
11959 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
11960 | tree_cons (NULL_TREE, | |
11961 | long_long_unsigned_type_node, | |
11962 | endlink))); | |
11963 | ||
11964 | /* Add all builtins that are more or less simple operations on two | |
11965 | operands. */ | |
e97a46ce | 11966 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
11967 | { |
11968 | /* Use one of the operands; the target can have a different mode for | |
11969 | mask-generating compares. */ | |
11970 | enum machine_mode mode; | |
11971 | tree type; | |
11972 | ||
11973 | if (d->name == 0) | |
11974 | continue; | |
11975 | ||
11976 | mode = insn_data[d->icode].operand[1].mode; | |
11977 | ||
11978 | switch (mode) | |
11979 | { | |
11980 | case V8QImode: | |
11981 | type = v8qi_ftype_v8qi_v8qi; | |
11982 | break; | |
11983 | case V4HImode: | |
11984 | type = v4hi_ftype_v4hi_v4hi; | |
11985 | break; | |
11986 | case V2SImode: | |
11987 | type = v2si_ftype_v2si_v2si; | |
11988 | break; | |
11989 | case DImode: | |
11990 | type = di_ftype_di_di; | |
11991 | break; | |
11992 | ||
11993 | default: | |
11994 | abort (); | |
11995 | } | |
11996 | ||
11997 | def_mbuiltin (d->mask, d->name, type, d->code); | |
11998 | } | |
11999 | ||
12000 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
12001 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
12002 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
12003 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
12004 | ||
12005 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
12006 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
12007 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
12008 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
12009 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
12010 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
12011 | ||
12012 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
12013 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
12014 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
12015 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
12016 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
12017 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
12018 | ||
12019 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
12020 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
12021 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
12022 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
12023 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
12024 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
12025 | ||
12026 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
12027 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
12028 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
12029 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
12030 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
12031 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
12032 | ||
12033 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
12034 | ||
12035 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
12036 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
12037 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
12038 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
12039 | ||
12040 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
12041 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
12042 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
12043 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
12044 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
12045 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
12046 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
12047 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
12048 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
12049 | ||
12050 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
12051 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
12052 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
12053 | ||
12054 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
12055 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
12056 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
12057 | ||
12058 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
12059 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
12060 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
12061 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
12062 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
12063 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
12064 | ||
12065 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
12066 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
12067 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
12068 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
12069 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
12070 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
12071 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
12072 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
12073 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
12074 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
12075 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
12076 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
12077 | ||
12078 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
12079 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
12080 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
12081 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
12082 | ||
12083 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
12084 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
12085 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
12086 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
12087 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
12088 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
12089 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
12090 | } | |
12091 | ||
12092 | static void | |
12093 | arm_init_builtins (void) | |
12094 | { | |
12095 | if (TARGET_REALLY_IWMMXT) | |
12096 | arm_init_iwmmxt_builtins (); | |
12097 | } | |
12098 | ||
12099 | /* Errors in the source file can cause expand_expr to return const0_rtx | |
12100 | where we expect a vector. To avoid crashing, use one of the vector | |
12101 | clear instructions. */ | |
12102 | ||
12103 | static rtx | |
12104 | safe_vector_operand (rtx x, enum machine_mode mode) | |
12105 | { | |
12106 | if (x != const0_rtx) | |
12107 | return x; | |
12108 | x = gen_reg_rtx (mode); | |
12109 | ||
12110 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
12111 | : gen_rtx_SUBREG (DImode, x, 0))); | |
12112 | return x; | |
12113 | } | |
12114 | ||
12115 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
12116 | ||
12117 | static rtx | |
12118 | arm_expand_binop_builtin (enum insn_code icode, | |
12119 | tree arglist, rtx target) | |
12120 | { | |
12121 | rtx pat; | |
12122 | tree arg0 = TREE_VALUE (arglist); | |
12123 | tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12124 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12125 | rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12126 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
12127 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
12128 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
12129 | ||
12130 | if (VECTOR_MODE_P (mode0)) | |
12131 | op0 = safe_vector_operand (op0, mode0); | |
12132 | if (VECTOR_MODE_P (mode1)) | |
12133 | op1 = safe_vector_operand (op1, mode1); | |
12134 | ||
12135 | if (! target | |
12136 | || GET_MODE (target) != tmode | |
12137 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12138 | target = gen_reg_rtx (tmode); | |
12139 | ||
12140 | /* In case the insn wants input operands in modes different from | |
12141 | the result, abort. */ | |
12142 | if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1) | |
12143 | abort (); | |
12144 | ||
12145 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12146 | op0 = copy_to_mode_reg (mode0, op0); | |
12147 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12148 | op1 = copy_to_mode_reg (mode1, op1); | |
12149 | ||
12150 | pat = GEN_FCN (icode) (target, op0, op1); | |
12151 | if (! pat) | |
12152 | return 0; | |
12153 | emit_insn (pat); | |
12154 | return target; | |
12155 | } | |
12156 | ||
12157 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
12158 | ||
12159 | static rtx | |
12160 | arm_expand_unop_builtin (enum insn_code icode, | |
12161 | tree arglist, rtx target, int do_load) | |
12162 | { | |
12163 | rtx pat; | |
12164 | tree arg0 = TREE_VALUE (arglist); | |
12165 | rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12166 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
12167 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
12168 | ||
12169 | if (! target | |
12170 | || GET_MODE (target) != tmode | |
12171 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12172 | target = gen_reg_rtx (tmode); | |
12173 | if (do_load) | |
12174 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
12175 | else | |
12176 | { | |
12177 | if (VECTOR_MODE_P (mode0)) | |
12178 | op0 = safe_vector_operand (op0, mode0); | |
12179 | ||
12180 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12181 | op0 = copy_to_mode_reg (mode0, op0); | |
12182 | } | |
12183 | ||
12184 | pat = GEN_FCN (icode) (target, op0); | |
12185 | if (! pat) | |
12186 | return 0; | |
12187 | emit_insn (pat); | |
12188 | return target; | |
12189 | } | |
12190 | ||
12191 | /* Expand an expression EXP that calls a built-in function, | |
12192 | with result going to TARGET if that's convenient | |
12193 | (and in mode MODE if that's convenient). | |
12194 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
12195 | IGNORE is nonzero if the value is to be ignored. */ | |
12196 | ||
12197 | static rtx | |
12198 | arm_expand_builtin (tree exp, | |
12199 | rtx target, | |
12200 | rtx subtarget ATTRIBUTE_UNUSED, | |
12201 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
12202 | int ignore ATTRIBUTE_UNUSED) | |
12203 | { | |
12204 | const struct builtin_description * d; | |
12205 | enum insn_code icode; | |
12206 | tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); | |
12207 | tree arglist = TREE_OPERAND (exp, 1); | |
12208 | tree arg0; | |
12209 | tree arg1; | |
12210 | tree arg2; | |
12211 | rtx op0; | |
12212 | rtx op1; | |
12213 | rtx op2; | |
12214 | rtx pat; | |
12215 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
12216 | size_t i; | |
12217 | enum machine_mode tmode; | |
12218 | enum machine_mode mode0; | |
12219 | enum machine_mode mode1; | |
12220 | enum machine_mode mode2; | |
12221 | ||
12222 | switch (fcode) | |
12223 | { | |
12224 | case ARM_BUILTIN_TEXTRMSB: | |
12225 | case ARM_BUILTIN_TEXTRMUB: | |
12226 | case ARM_BUILTIN_TEXTRMSH: | |
12227 | case ARM_BUILTIN_TEXTRMUH: | |
12228 | case ARM_BUILTIN_TEXTRMSW: | |
12229 | case ARM_BUILTIN_TEXTRMUW: | |
12230 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
12231 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
12232 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
12233 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
12234 | : CODE_FOR_iwmmxt_textrmw); | |
12235 | ||
12236 | arg0 = TREE_VALUE (arglist); | |
12237 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12238 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12239 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12240 | tmode = insn_data[icode].operand[0].mode; | |
12241 | mode0 = insn_data[icode].operand[1].mode; | |
12242 | mode1 = insn_data[icode].operand[2].mode; | |
12243 | ||
12244 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12245 | op0 = copy_to_mode_reg (mode0, op0); | |
12246 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12247 | { | |
12248 | /* @@@ better error message */ | |
12249 | error ("selector must be an immediate"); | |
12250 | return gen_reg_rtx (tmode); | |
12251 | } | |
12252 | if (target == 0 | |
12253 | || GET_MODE (target) != tmode | |
12254 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12255 | target = gen_reg_rtx (tmode); | |
12256 | pat = GEN_FCN (icode) (target, op0, op1); | |
12257 | if (! pat) | |
12258 | return 0; | |
12259 | emit_insn (pat); | |
12260 | return target; | |
12261 | ||
12262 | case ARM_BUILTIN_TINSRB: | |
12263 | case ARM_BUILTIN_TINSRH: | |
12264 | case ARM_BUILTIN_TINSRW: | |
12265 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
12266 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
12267 | : CODE_FOR_iwmmxt_tinsrw); | |
12268 | arg0 = TREE_VALUE (arglist); | |
12269 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12270 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
12271 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12272 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12273 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
12274 | tmode = insn_data[icode].operand[0].mode; | |
12275 | mode0 = insn_data[icode].operand[1].mode; | |
12276 | mode1 = insn_data[icode].operand[2].mode; | |
12277 | mode2 = insn_data[icode].operand[3].mode; | |
12278 | ||
12279 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12280 | op0 = copy_to_mode_reg (mode0, op0); | |
12281 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12282 | op1 = copy_to_mode_reg (mode1, op1); | |
12283 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
12284 | { | |
12285 | /* @@@ better error message */ | |
12286 | error ("selector must be an immediate"); | |
12287 | return const0_rtx; | |
12288 | } | |
12289 | if (target == 0 | |
12290 | || GET_MODE (target) != tmode | |
12291 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12292 | target = gen_reg_rtx (tmode); | |
12293 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
12294 | if (! pat) | |
12295 | return 0; | |
12296 | emit_insn (pat); | |
12297 | return target; | |
12298 | ||
12299 | case ARM_BUILTIN_SETWCX: | |
12300 | arg0 = TREE_VALUE (arglist); | |
12301 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
f07a6b21 BE |
12302 | op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0)); |
12303 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12304 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); | |
5a9335ef NC |
12305 | return 0; |
12306 | ||
12307 | case ARM_BUILTIN_GETWCX: | |
12308 | arg0 = TREE_VALUE (arglist); | |
12309 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12310 | target = gen_reg_rtx (SImode); | |
12311 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
12312 | return target; | |
12313 | ||
12314 | case ARM_BUILTIN_WSHUFH: | |
12315 | icode = CODE_FOR_iwmmxt_wshufh; | |
12316 | arg0 = TREE_VALUE (arglist); | |
12317 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12318 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12319 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12320 | tmode = insn_data[icode].operand[0].mode; | |
12321 | mode1 = insn_data[icode].operand[1].mode; | |
12322 | mode2 = insn_data[icode].operand[2].mode; | |
12323 | ||
12324 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
12325 | op0 = copy_to_mode_reg (mode1, op0); | |
12326 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
12327 | { | |
12328 | /* @@@ better error message */ | |
12329 | error ("mask must be an immediate"); | |
12330 | return const0_rtx; | |
12331 | } | |
12332 | if (target == 0 | |
12333 | || GET_MODE (target) != tmode | |
12334 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12335 | target = gen_reg_rtx (tmode); | |
12336 | pat = GEN_FCN (icode) (target, op0, op1); | |
12337 | if (! pat) | |
12338 | return 0; | |
12339 | emit_insn (pat); | |
12340 | return target; | |
12341 | ||
12342 | case ARM_BUILTIN_WSADB: | |
12343 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target); | |
12344 | case ARM_BUILTIN_WSADH: | |
12345 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target); | |
12346 | case ARM_BUILTIN_WSADBZ: | |
12347 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target); | |
12348 | case ARM_BUILTIN_WSADHZ: | |
12349 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target); | |
12350 | ||
12351 | /* Several three-argument builtins. */ | |
12352 | case ARM_BUILTIN_WMACS: | |
12353 | case ARM_BUILTIN_WMACU: | |
12354 | case ARM_BUILTIN_WALIGN: | |
12355 | case ARM_BUILTIN_TMIA: | |
12356 | case ARM_BUILTIN_TMIAPH: | |
12357 | case ARM_BUILTIN_TMIATT: | |
12358 | case ARM_BUILTIN_TMIATB: | |
12359 | case ARM_BUILTIN_TMIABT: | |
12360 | case ARM_BUILTIN_TMIABB: | |
12361 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
12362 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
12363 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
12364 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
12365 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
12366 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
12367 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
12368 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
12369 | : CODE_FOR_iwmmxt_walign); | |
12370 | arg0 = TREE_VALUE (arglist); | |
12371 | arg1 = TREE_VALUE (TREE_CHAIN (arglist)); | |
12372 | arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); | |
12373 | op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); | |
12374 | op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); | |
12375 | op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); | |
12376 | tmode = insn_data[icode].operand[0].mode; | |
12377 | mode0 = insn_data[icode].operand[1].mode; | |
12378 | mode1 = insn_data[icode].operand[2].mode; | |
12379 | mode2 = insn_data[icode].operand[3].mode; | |
12380 | ||
12381 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
12382 | op0 = copy_to_mode_reg (mode0, op0); | |
12383 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
12384 | op1 = copy_to_mode_reg (mode1, op1); | |
12385 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
12386 | op2 = copy_to_mode_reg (mode2, op2); | |
12387 | if (target == 0 | |
12388 | || GET_MODE (target) != tmode | |
12389 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
12390 | target = gen_reg_rtx (tmode); | |
12391 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
12392 | if (! pat) | |
12393 | return 0; | |
12394 | emit_insn (pat); | |
12395 | return target; | |
12396 | ||
12397 | case ARM_BUILTIN_WZERO: | |
12398 | target = gen_reg_rtx (DImode); | |
12399 | emit_insn (gen_iwmmxt_clrdi (target)); | |
12400 | return target; | |
12401 | ||
12402 | default: | |
12403 | break; | |
12404 | } | |
12405 | ||
e97a46ce | 12406 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
12407 | if (d->code == (const enum arm_builtins) fcode) |
12408 | return arm_expand_binop_builtin (d->icode, arglist, target); | |
12409 | ||
e97a46ce | 12410 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef NC |
12411 | if (d->code == (const enum arm_builtins) fcode) |
12412 | return arm_expand_unop_builtin (d->icode, arglist, target, 0); | |
12413 | ||
12414 | /* @@@ Should really do something sensible here. */ | |
12415 | return NULL_RTX; | |
12416 | } | |
12417 | \f | |
d5b7b3ae RE |
12418 | /* Recursively search through all of the blocks in a function |
12419 | checking to see if any of the variables created in that | |
12420 | function match the RTX called 'orig'. If they do then | |
12421 | replace them with the RTX called 'new'. */ | |
d5b7b3ae | 12422 | static void |
e32bac5b | 12423 | replace_symbols_in_block (tree block, rtx orig, rtx new) |
d5b7b3ae RE |
12424 | { |
12425 | for (; block; block = BLOCK_CHAIN (block)) | |
12426 | { | |
12427 | tree sym; | |
12428 | ||
5895f793 | 12429 | if (!TREE_USED (block)) |
d5b7b3ae RE |
12430 | continue; |
12431 | ||
12432 | for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) | |
12433 | { | |
12434 | if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) | |
12435 | || DECL_IGNORED_P (sym) | |
12436 | || TREE_CODE (sym) != VAR_DECL | |
12437 | || DECL_EXTERNAL (sym) | |
5895f793 | 12438 | || !rtx_equal_p (DECL_RTL (sym), orig) |
d5b7b3ae RE |
12439 | ) |
12440 | continue; | |
12441 | ||
7b8b8ade | 12442 | SET_DECL_RTL (sym, new); |
d5b7b3ae RE |
12443 | } |
12444 | ||
12445 | replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); | |
12446 | } | |
12447 | } | |
12448 | ||
1d6e90ac NC |
12449 | /* Return the number (counting from 0) of |
12450 | the least significant set bit in MASK. */ | |
12451 | ||
e32bac5b RE |
12452 | inline static int |
12453 | number_of_first_bit_set (int mask) | |
d5b7b3ae RE |
12454 | { |
12455 | int bit; | |
12456 | ||
12457 | for (bit = 0; | |
12458 | (mask & (1 << bit)) == 0; | |
5895f793 | 12459 | ++bit) |
d5b7b3ae RE |
12460 | continue; |
12461 | ||
12462 | return bit; | |
12463 | } | |
12464 | ||
12465 | /* Generate code to return from a thumb function. | |
12466 | If 'reg_containing_return_addr' is -1, then the return address is | |
12467 | actually on the stack, at the stack pointer. */ | |
12468 | static void | |
e32bac5b | 12469 | thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) |
d5b7b3ae RE |
12470 | { |
12471 | unsigned regs_available_for_popping; | |
12472 | unsigned regs_to_pop; | |
12473 | int pops_needed; | |
12474 | unsigned available; | |
12475 | unsigned required; | |
12476 | int mode; | |
12477 | int size; | |
12478 | int restore_a4 = FALSE; | |
12479 | ||
12480 | /* Compute the registers we need to pop. */ | |
12481 | regs_to_pop = 0; | |
12482 | pops_needed = 0; | |
12483 | ||
12484 | /* There is an assumption here, that if eh_ofs is not NULL, the | |
12485 | normal return address will have been pushed. */ | |
12486 | if (reg_containing_return_addr == -1 || eh_ofs) | |
12487 | { | |
12488 | /* When we are generating a return for __builtin_eh_return, | |
12489 | reg_containing_return_addr must specify the return regno. */ | |
12490 | if (eh_ofs && reg_containing_return_addr == -1) | |
12491 | abort (); | |
12492 | ||
12493 | regs_to_pop |= 1 << LR_REGNUM; | |
5895f793 | 12494 | ++pops_needed; |
d5b7b3ae RE |
12495 | } |
12496 | ||
12497 | if (TARGET_BACKTRACE) | |
12498 | { | |
12499 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
12500 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
12501 | pops_needed += 2; | |
12502 | } | |
12503 | ||
12504 | /* If there is nothing to pop then just emit the BX instruction and | |
12505 | return. */ | |
12506 | if (pops_needed == 0) | |
12507 | { | |
12508 | if (eh_ofs) | |
12509 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
12510 | ||
12511 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
12512 | return; | |
12513 | } | |
12514 | /* Otherwise if we are not supporting interworking and we have not created | |
12515 | a backtrace structure and the function was not entered in ARM mode then | |
12516 | just pop the return address straight into the PC. */ | |
5895f793 RE |
12517 | else if (!TARGET_INTERWORK |
12518 | && !TARGET_BACKTRACE | |
12519 | && !is_called_in_ARM_mode (current_function_decl)) | |
d5b7b3ae RE |
12520 | { |
12521 | if (eh_ofs) | |
12522 | { | |
12523 | asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); | |
12524 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
12525 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
12526 | } | |
12527 | else | |
12528 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); | |
12529 | ||
12530 | return; | |
12531 | } | |
12532 | ||
12533 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
12534 | regs_available_for_popping = 0; | |
12535 | ||
12536 | /* If returning via __builtin_eh_return, the bottom three registers | |
12537 | all contain information needed for the return. */ | |
12538 | if (eh_ofs) | |
12539 | size = 12; | |
12540 | else | |
12541 | { | |
d5b7b3ae RE |
12542 | /* If we can deduce the registers used from the function's |
12543 | return value. This is more reliable that examining | |
12544 | regs_ever_live[] because that will be set if the register is | |
12545 | ever used in the function, not just if the register is used | |
12546 | to hold a return value. */ | |
12547 | ||
12548 | if (current_function_return_rtx != 0) | |
12549 | mode = GET_MODE (current_function_return_rtx); | |
12550 | else | |
d5b7b3ae RE |
12551 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
12552 | ||
12553 | size = GET_MODE_SIZE (mode); | |
12554 | ||
12555 | if (size == 0) | |
12556 | { | |
12557 | /* In a void function we can use any argument register. | |
12558 | In a function that returns a structure on the stack | |
12559 | we can use the second and third argument registers. */ | |
12560 | if (mode == VOIDmode) | |
12561 | regs_available_for_popping = | |
12562 | (1 << ARG_REGISTER (1)) | |
12563 | | (1 << ARG_REGISTER (2)) | |
12564 | | (1 << ARG_REGISTER (3)); | |
12565 | else | |
12566 | regs_available_for_popping = | |
12567 | (1 << ARG_REGISTER (2)) | |
12568 | | (1 << ARG_REGISTER (3)); | |
12569 | } | |
12570 | else if (size <= 4) | |
12571 | regs_available_for_popping = | |
12572 | (1 << ARG_REGISTER (2)) | |
12573 | | (1 << ARG_REGISTER (3)); | |
12574 | else if (size <= 8) | |
12575 | regs_available_for_popping = | |
12576 | (1 << ARG_REGISTER (3)); | |
12577 | } | |
12578 | ||
12579 | /* Match registers to be popped with registers into which we pop them. */ | |
12580 | for (available = regs_available_for_popping, | |
12581 | required = regs_to_pop; | |
12582 | required != 0 && available != 0; | |
12583 | available &= ~(available & - available), | |
12584 | required &= ~(required & - required)) | |
12585 | -- pops_needed; | |
12586 | ||
12587 | /* If we have any popping registers left over, remove them. */ | |
12588 | if (available > 0) | |
5895f793 | 12589 | regs_available_for_popping &= ~available; |
d5b7b3ae RE |
12590 | |
12591 | /* Otherwise if we need another popping register we can use | |
12592 | the fourth argument register. */ | |
12593 | else if (pops_needed) | |
12594 | { | |
12595 | /* If we have not found any free argument registers and | |
12596 | reg a4 contains the return address, we must move it. */ | |
12597 | if (regs_available_for_popping == 0 | |
12598 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
12599 | { | |
12600 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
12601 | reg_containing_return_addr = LR_REGNUM; | |
12602 | } | |
12603 | else if (size > 12) | |
12604 | { | |
12605 | /* Register a4 is being used to hold part of the return value, | |
12606 | but we have dire need of a free, low register. */ | |
12607 | restore_a4 = TRUE; | |
12608 | ||
12609 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); | |
12610 | } | |
12611 | ||
12612 | if (reg_containing_return_addr != LAST_ARG_REGNUM) | |
12613 | { | |
12614 | /* The fourth argument register is available. */ | |
12615 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
12616 | ||
5895f793 | 12617 | --pops_needed; |
d5b7b3ae RE |
12618 | } |
12619 | } | |
12620 | ||
12621 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
12622 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
12623 | regs_available_for_popping); | |
d5b7b3ae RE |
12624 | |
12625 | /* Process the registers we popped. */ | |
12626 | if (reg_containing_return_addr == -1) | |
12627 | { | |
12628 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 12629 | regs_to_pop &= ~(1 << LR_REGNUM); |
d5b7b3ae RE |
12630 | |
12631 | reg_containing_return_addr = | |
12632 | number_of_first_bit_set (regs_available_for_popping); | |
12633 | ||
12634 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 12635 | the return address will not be corrupted by further pops. */ |
5895f793 | 12636 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
12637 | } |
12638 | ||
12639 | /* If we popped other registers then handle them here. */ | |
12640 | if (regs_available_for_popping) | |
12641 | { | |
12642 | int frame_pointer; | |
12643 | ||
12644 | /* Work out which register currently contains the frame pointer. */ | |
12645 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
12646 | ||
12647 | /* Move it into the correct place. */ | |
12648 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
12649 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
12650 | ||
12651 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
12652 | regs_available_for_popping &= ~(1 << frame_pointer); |
12653 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
d5b7b3ae RE |
12654 | |
12655 | if (regs_available_for_popping) | |
12656 | { | |
12657 | int stack_pointer; | |
12658 | ||
12659 | /* We popped the stack pointer as well, | |
12660 | find the register that contains it. */ | |
12661 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
12662 | ||
12663 | /* Move it into the stack register. */ | |
12664 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
12665 | ||
12666 | /* At this point we have popped all necessary registers, so | |
12667 | do not worry about restoring regs_available_for_popping | |
12668 | to its correct value: | |
12669 | ||
12670 | assert (pops_needed == 0) | |
12671 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
12672 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
12673 | } | |
12674 | else | |
12675 | { | |
12676 | /* Since we have just move the popped value into the frame | |
12677 | pointer, the popping register is available for reuse, and | |
12678 | we know that we still have the stack pointer left to pop. */ | |
12679 | regs_available_for_popping |= (1 << frame_pointer); | |
12680 | } | |
12681 | } | |
12682 | ||
12683 | /* If we still have registers left on the stack, but we no longer have | |
12684 | any registers into which we can pop them, then we must move the return | |
12685 | address into the link register and make available the register that | |
12686 | contained it. */ | |
12687 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
12688 | { | |
12689 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
12690 | ||
12691 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, | |
12692 | reg_containing_return_addr); | |
12693 | ||
12694 | reg_containing_return_addr = LR_REGNUM; | |
12695 | } | |
12696 | ||
12697 | /* If we have registers left on the stack then pop some more. | |
12698 | We know that at most we will want to pop FP and SP. */ | |
12699 | if (pops_needed > 0) | |
12700 | { | |
12701 | int popped_into; | |
12702 | int move_to; | |
12703 | ||
980e61bb DJ |
12704 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
12705 | regs_available_for_popping); | |
d5b7b3ae RE |
12706 | |
12707 | /* We have popped either FP or SP. | |
12708 | Move whichever one it is into the correct register. */ | |
12709 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
12710 | move_to = number_of_first_bit_set (regs_to_pop); | |
12711 | ||
12712 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
12713 | ||
5895f793 | 12714 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 12715 | |
5895f793 | 12716 | --pops_needed; |
d5b7b3ae RE |
12717 | } |
12718 | ||
12719 | /* If we still have not popped everything then we must have only | |
12720 | had one register available to us and we are now popping the SP. */ | |
12721 | if (pops_needed > 0) | |
12722 | { | |
12723 | int popped_into; | |
12724 | ||
980e61bb DJ |
12725 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
12726 | regs_available_for_popping); | |
d5b7b3ae RE |
12727 | |
12728 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
12729 | ||
12730 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
12731 | /* | |
12732 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
12733 | assert (pops_needed == 1) | |
12734 | */ | |
12735 | } | |
12736 | ||
12737 | /* If necessary restore the a4 register. */ | |
12738 | if (restore_a4) | |
12739 | { | |
12740 | if (reg_containing_return_addr != LR_REGNUM) | |
12741 | { | |
12742 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
12743 | reg_containing_return_addr = LR_REGNUM; | |
12744 | } | |
12745 | ||
12746 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); | |
12747 | } | |
12748 | ||
12749 | if (eh_ofs) | |
12750 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); | |
12751 | ||
12752 | /* Return to caller. */ | |
12753 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
12754 | } | |
12755 | ||
980e61bb DJ |
12756 | /* Emit code to push or pop registers to or from the stack. F is the |
12757 | assembly file. MASK is the registers to push or pop. PUSH is | |
59b9a953 | 12758 | nonzero if we should push, and zero if we should pop. For debugging |
980e61bb DJ |
12759 | output, if pushing, adjust CFA_OFFSET by the amount of space added |
12760 | to the stack. REAL_REGS should have the same number of bits set as | |
12761 | MASK, and will be used instead (in the same order) to describe which | |
12762 | registers were saved - this is used to mark the save slots when we | |
12763 | push high registers after moving them to low registers. */ | |
d5b7b3ae | 12764 | static void |
980e61bb | 12765 | thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs) |
d5b7b3ae RE |
12766 | { |
12767 | int regno; | |
12768 | int lo_mask = mask & 0xFF; | |
980e61bb | 12769 | int pushed_words = 0; |
d5b7b3ae | 12770 | |
5895f793 | 12771 | if (lo_mask == 0 && !push && (mask & (1 << 15))) |
d5b7b3ae RE |
12772 | { |
12773 | /* Special case. Do not generate a POP PC statement here, do it in | |
12774 | thumb_exit() */ | |
12775 | thumb_exit (f, -1, NULL_RTX); | |
12776 | return; | |
12777 | } | |
12778 | ||
12779 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); | |
12780 | ||
12781 | /* Look at the low registers first. */ | |
5895f793 | 12782 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) |
d5b7b3ae RE |
12783 | { |
12784 | if (lo_mask & 1) | |
12785 | { | |
12786 | asm_fprintf (f, "%r", regno); | |
12787 | ||
12788 | if ((lo_mask & ~1) != 0) | |
12789 | fprintf (f, ", "); | |
980e61bb DJ |
12790 | |
12791 | pushed_words++; | |
d5b7b3ae RE |
12792 | } |
12793 | } | |
12794 | ||
12795 | if (push && (mask & (1 << LR_REGNUM))) | |
12796 | { | |
12797 | /* Catch pushing the LR. */ | |
12798 | if (mask & 0xFF) | |
12799 | fprintf (f, ", "); | |
12800 | ||
12801 | asm_fprintf (f, "%r", LR_REGNUM); | |
980e61bb DJ |
12802 | |
12803 | pushed_words++; | |
d5b7b3ae RE |
12804 | } |
12805 | else if (!push && (mask & (1 << PC_REGNUM))) | |
12806 | { | |
12807 | /* Catch popping the PC. */ | |
12808 | if (TARGET_INTERWORK || TARGET_BACKTRACE) | |
12809 | { | |
12810 | /* The PC is never poped directly, instead | |
12811 | it is popped into r3 and then BX is used. */ | |
12812 | fprintf (f, "}\n"); | |
12813 | ||
12814 | thumb_exit (f, -1, NULL_RTX); | |
12815 | ||
12816 | return; | |
12817 | } | |
12818 | else | |
12819 | { | |
12820 | if (mask & 0xFF) | |
12821 | fprintf (f, ", "); | |
12822 | ||
12823 | asm_fprintf (f, "%r", PC_REGNUM); | |
12824 | } | |
12825 | } | |
12826 | ||
12827 | fprintf (f, "}\n"); | |
980e61bb DJ |
12828 | |
12829 | if (push && pushed_words && dwarf2out_do_frame ()) | |
12830 | { | |
12831 | char *l = dwarf2out_cfi_label (); | |
12832 | int pushed_mask = real_regs; | |
12833 | ||
12834 | *cfa_offset += pushed_words * 4; | |
12835 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
12836 | ||
12837 | pushed_words = 0; | |
12838 | pushed_mask = real_regs; | |
12839 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
12840 | { | |
12841 | if (pushed_mask & 1) | |
12842 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
12843 | } | |
12844 | } | |
d5b7b3ae RE |
12845 | } |
12846 | \f | |
12847 | void | |
e32bac5b | 12848 | thumb_final_prescan_insn (rtx insn) |
d5b7b3ae | 12849 | { |
d5b7b3ae | 12850 | if (flag_print_asm_name) |
9d98a694 AO |
12851 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
12852 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
12853 | } |
12854 | ||
12855 | int | |
e32bac5b | 12856 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
12857 | { |
12858 | unsigned HOST_WIDE_INT mask = 0xff; | |
12859 | int i; | |
12860 | ||
12861 | if (val == 0) /* XXX */ | |
12862 | return 0; | |
12863 | ||
12864 | for (i = 0; i < 25; i++) | |
12865 | if ((val & (mask << i)) == val) | |
12866 | return 1; | |
12867 | ||
12868 | return 0; | |
12869 | } | |
12870 | ||
825dda42 | 12871 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 12872 | or might contain a far jump. */ |
5848830f PB |
12873 | static int |
12874 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
12875 | { |
12876 | rtx insn; | |
12877 | ||
12878 | /* This test is only important for leaf functions. */ | |
5895f793 | 12879 | /* assert (!leaf_function_p ()); */ |
d5b7b3ae RE |
12880 | |
12881 | /* If we have already decided that far jumps may be used, | |
12882 | do not bother checking again, and always return true even if | |
12883 | it turns out that they are not being used. Once we have made | |
12884 | the decision that far jumps are present (and that hence the link | |
12885 | register will be pushed onto the stack) we cannot go back on it. */ | |
12886 | if (cfun->machine->far_jump_used) | |
12887 | return 1; | |
12888 | ||
12889 | /* If this function is not being called from the prologue/epilogue | |
12890 | generation code then it must be being called from the | |
12891 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 12892 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
12893 | { |
12894 | /* In this case we know that we are being asked about the elimination | |
12895 | of the arg pointer register. If that register is not being used, | |
12896 | then there are no arguments on the stack, and we do not have to | |
12897 | worry that a far jump might force the prologue to push the link | |
12898 | register, changing the stack offsets. In this case we can just | |
12899 | return false, since the presence of far jumps in the function will | |
12900 | not affect stack offsets. | |
12901 | ||
12902 | If the arg pointer is live (or if it was live, but has now been | |
12903 | eliminated and so set to dead) then we do have to test to see if | |
12904 | the function might contain a far jump. This test can lead to some | |
12905 | false negatives, since before reload is completed, then length of | |
12906 | branch instructions is not known, so gcc defaults to returning their | |
12907 | longest length, which in turn sets the far jump attribute to true. | |
12908 | ||
12909 | A false negative will not result in bad code being generated, but it | |
12910 | will result in a needless push and pop of the link register. We | |
5848830f PB |
12911 | hope that this does not occur too often. |
12912 | ||
12913 | If we need doubleword stack alignment this could affect the other | |
12914 | elimination offsets so we can't risk getting it wrong. */ | |
d5b7b3ae RE |
12915 | if (regs_ever_live [ARG_POINTER_REGNUM]) |
12916 | cfun->machine->arg_pointer_live = 1; | |
5895f793 | 12917 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
12918 | return 0; |
12919 | } | |
12920 | ||
12921 | /* Check to see if the function contains a branch | |
12922 | insn with the far jump attribute set. */ | |
12923 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
12924 | { | |
12925 | if (GET_CODE (insn) == JUMP_INSN | |
12926 | /* Ignore tablejump patterns. */ | |
12927 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
12928 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
12929 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
12930 | ) | |
12931 | { | |
9a9f7594 | 12932 | /* Record the fact that we have decided that |
d5b7b3ae RE |
12933 | the function does use far jumps. */ |
12934 | cfun->machine->far_jump_used = 1; | |
12935 | return 1; | |
12936 | } | |
12937 | } | |
12938 | ||
12939 | return 0; | |
12940 | } | |
12941 | ||
825dda42 | 12942 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 12943 | int |
e32bac5b | 12944 | is_called_in_ARM_mode (tree func) |
d5b7b3ae RE |
12945 | { |
12946 | if (TREE_CODE (func) != FUNCTION_DECL) | |
12947 | abort (); | |
12948 | ||
12949 | /* Ignore the problem about functions whoes address is taken. */ | |
12950 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) | |
12951 | return TRUE; | |
12952 | ||
12953 | #ifdef ARM_PE | |
91d231cb | 12954 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
12955 | #else |
12956 | return FALSE; | |
12957 | #endif | |
12958 | } | |
12959 | ||
d6b4baa4 | 12960 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 12961 | const char * |
e32bac5b | 12962 | thumb_unexpanded_epilogue (void) |
d5b7b3ae RE |
12963 | { |
12964 | int regno; | |
12965 | int live_regs_mask = 0; | |
12966 | int high_regs_pushed = 0; | |
d5b7b3ae RE |
12967 | int had_to_push_lr; |
12968 | rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; | |
12969 | ||
12970 | if (return_used_this_function) | |
12971 | return ""; | |
12972 | ||
58e60158 AN |
12973 | if (IS_NAKED (arm_current_func_type ())) |
12974 | return ""; | |
12975 | ||
d5b7b3ae | 12976 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 12977 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
12978 | live_regs_mask |= 1 << regno; |
12979 | ||
12980 | for (regno = 8; regno < 13; regno++) | |
aeaf4d25 AN |
12981 | if (THUMB_REG_PUSHED_P (regno)) |
12982 | high_regs_pushed++; | |
d5b7b3ae RE |
12983 | |
12984 | /* The prolog may have pushed some high registers to use as | |
093354e0 | 12985 | work registers. eg the testsuite file: |
d5b7b3ae RE |
12986 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
12987 | compiles to produce: | |
12988 | push {r4, r5, r6, r7, lr} | |
12989 | mov r7, r9 | |
12990 | mov r6, r8 | |
12991 | push {r6, r7} | |
12992 | as part of the prolog. We have to undo that pushing here. */ | |
12993 | ||
12994 | if (high_regs_pushed) | |
12995 | { | |
12996 | int mask = live_regs_mask; | |
12997 | int next_hi_reg; | |
12998 | int size; | |
12999 | int mode; | |
13000 | ||
d5b7b3ae RE |
13001 | /* If we can deduce the registers used from the function's return value. |
13002 | This is more reliable that examining regs_ever_live[] because that | |
13003 | will be set if the register is ever used in the function, not just if | |
13004 | the register is used to hold a return value. */ | |
13005 | ||
13006 | if (current_function_return_rtx != 0) | |
13007 | mode = GET_MODE (current_function_return_rtx); | |
13008 | else | |
d5b7b3ae RE |
13009 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
13010 | ||
13011 | size = GET_MODE_SIZE (mode); | |
13012 | ||
13013 | /* Unless we are returning a type of size > 12 register r3 is | |
13014 | available. */ | |
13015 | if (size < 13) | |
13016 | mask |= 1 << 3; | |
13017 | ||
13018 | if (mask == 0) | |
13019 | /* Oh dear! We have no low registers into which we can pop | |
13020 | high registers! */ | |
400500c4 RK |
13021 | internal_error |
13022 | ("no low registers available for popping high registers"); | |
d5b7b3ae RE |
13023 | |
13024 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 13025 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
13026 | break; |
13027 | ||
13028 | while (high_regs_pushed) | |
13029 | { | |
13030 | /* Find lo register(s) into which the high register(s) can | |
13031 | be popped. */ | |
13032 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
13033 | { | |
13034 | if (mask & (1 << regno)) | |
13035 | high_regs_pushed--; | |
13036 | if (high_regs_pushed == 0) | |
13037 | break; | |
13038 | } | |
13039 | ||
13040 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
13041 | ||
d6b4baa4 | 13042 | /* Pop the values into the low register(s). */ |
980e61bb | 13043 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
13044 | |
13045 | /* Move the value(s) into the high registers. */ | |
13046 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
13047 | { | |
13048 | if (mask & (1 << regno)) | |
13049 | { | |
13050 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
13051 | regno); | |
13052 | ||
13053 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) | |
aeaf4d25 | 13054 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
d5b7b3ae RE |
13055 | break; |
13056 | } | |
13057 | } | |
13058 | } | |
13059 | } | |
13060 | ||
3c7ad43e | 13061 | had_to_push_lr = (live_regs_mask || thumb_force_lr_save ()); |
d5b7b3ae RE |
13062 | |
13063 | if (TARGET_BACKTRACE | |
13064 | && ((live_regs_mask & 0xFF) == 0) | |
13065 | && regs_ever_live [LAST_ARG_REGNUM] != 0) | |
13066 | { | |
13067 | /* The stack backtrace structure creation code had to | |
13068 | push R7 in order to get a work register, so we pop | |
d6b4baa4 | 13069 | it now. */ |
d5b7b3ae RE |
13070 | live_regs_mask |= (1 << LAST_LO_REGNUM); |
13071 | } | |
13072 | ||
13073 | if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) | |
13074 | { | |
13075 | if (had_to_push_lr | |
5895f793 RE |
13076 | && !is_called_in_ARM_mode (current_function_decl) |
13077 | && !eh_ofs) | |
d5b7b3ae RE |
13078 | live_regs_mask |= 1 << PC_REGNUM; |
13079 | ||
13080 | /* Either no argument registers were pushed or a backtrace | |
13081 | structure was created which includes an adjusted stack | |
13082 | pointer, so just pop everything. */ | |
13083 | if (live_regs_mask) | |
980e61bb DJ |
13084 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
13085 | live_regs_mask); | |
d5b7b3ae RE |
13086 | |
13087 | if (eh_ofs) | |
13088 | thumb_exit (asm_out_file, 2, eh_ofs); | |
13089 | /* We have either just popped the return address into the | |
13090 | PC or it is was kept in LR for the entire function or | |
13091 | it is still on the stack because we do not want to | |
13092 | return by doing a pop {pc}. */ | |
13093 | else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) | |
13094 | thumb_exit (asm_out_file, | |
13095 | (had_to_push_lr | |
13096 | && is_called_in_ARM_mode (current_function_decl)) ? | |
13097 | -1 : LR_REGNUM, NULL_RTX); | |
13098 | } | |
13099 | else | |
13100 | { | |
13101 | /* Pop everything but the return address. */ | |
5895f793 | 13102 | live_regs_mask &= ~(1 << PC_REGNUM); |
d5b7b3ae RE |
13103 | |
13104 | if (live_regs_mask) | |
980e61bb DJ |
13105 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
13106 | live_regs_mask); | |
d5b7b3ae RE |
13107 | |
13108 | if (had_to_push_lr) | |
13109 | /* Get the return address into a temporary register. */ | |
980e61bb DJ |
13110 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, |
13111 | 1 << LAST_ARG_REGNUM); | |
d5b7b3ae RE |
13112 | |
13113 | /* Remove the argument registers that were pushed onto the stack. */ | |
13114 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
13115 | SP_REGNUM, SP_REGNUM, | |
13116 | current_function_pretend_args_size); | |
13117 | ||
13118 | if (eh_ofs) | |
13119 | thumb_exit (asm_out_file, 2, eh_ofs); | |
13120 | else | |
13121 | thumb_exit (asm_out_file, | |
13122 | had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); | |
13123 | } | |
13124 | ||
13125 | return ""; | |
13126 | } | |
13127 | ||
13128 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 13129 | static struct machine_function * |
e32bac5b | 13130 | arm_init_machine_status (void) |
d5b7b3ae | 13131 | { |
e2500fed GK |
13132 | struct machine_function *machine; |
13133 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 13134 | |
e2500fed GK |
13135 | #if ARM_FT_UNKNOWN != 0 |
13136 | machine->func_type = ARM_FT_UNKNOWN; | |
6d3d9133 | 13137 | #endif |
e2500fed | 13138 | return machine; |
f7a80099 NC |
13139 | } |
13140 | ||
d5b7b3ae RE |
13141 | /* Return an RTX indicating where the return address to the |
13142 | calling function can be found. */ | |
13143 | rtx | |
e32bac5b | 13144 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 13145 | { |
d5b7b3ae RE |
13146 | if (count != 0) |
13147 | return NULL_RTX; | |
13148 | ||
61f0ccff | 13149 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
13150 | } |
13151 | ||
13152 | /* Do anything needed before RTL is emitted for each function. */ | |
13153 | void | |
e32bac5b | 13154 | arm_init_expanders (void) |
d5b7b3ae RE |
13155 | { |
13156 | /* Arrange to initialize and mark the machine per-function status. */ | |
13157 | init_machine_status = arm_init_machine_status; | |
d5b7b3ae RE |
13158 | } |
13159 | ||
0977774b | 13160 | |
5848830f PB |
13161 | /* Like arm_compute_initial_elimination offset. Simpler because |
13162 | THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */ | |
0977774b | 13163 | |
5848830f PB |
13164 | HOST_WIDE_INT |
13165 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
13166 | { | |
13167 | arm_stack_offsets *offsets; | |
0977774b | 13168 | |
5848830f | 13169 | offsets = arm_get_frame_offsets (); |
0977774b | 13170 | |
5848830f | 13171 | switch (from) |
0977774b | 13172 | { |
5848830f PB |
13173 | case ARG_POINTER_REGNUM: |
13174 | switch (to) | |
13175 | { | |
13176 | case STACK_POINTER_REGNUM: | |
13177 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 13178 | |
5848830f PB |
13179 | case FRAME_POINTER_REGNUM: |
13180 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 13181 | |
5848830f PB |
13182 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
13183 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
13184 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 13185 | |
5848830f PB |
13186 | default: |
13187 | abort(); | |
13188 | } | |
13189 | break; | |
0977774b | 13190 | |
5848830f PB |
13191 | case FRAME_POINTER_REGNUM: |
13192 | switch (to) | |
13193 | { | |
13194 | case STACK_POINTER_REGNUM: | |
13195 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 13196 | |
5848830f PB |
13197 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
13198 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
13199 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 13200 | |
5848830f PB |
13201 | default: |
13202 | abort(); | |
13203 | } | |
13204 | break; | |
0977774b | 13205 | |
5848830f PB |
13206 | default: |
13207 | abort (); | |
13208 | } | |
0977774b JT |
13209 | } |
13210 | ||
5848830f | 13211 | |
d5b7b3ae RE |
13212 | /* Generate the rest of a function's prologue. */ |
13213 | void | |
e32bac5b | 13214 | thumb_expand_prologue (void) |
d5b7b3ae | 13215 | { |
980e61bb DJ |
13216 | rtx insn, dwarf; |
13217 | ||
5848830f PB |
13218 | HOST_WIDE_INT amount; |
13219 | arm_stack_offsets *offsets; | |
6d3d9133 | 13220 | unsigned long func_type; |
3c7ad43e | 13221 | int regno; |
6d3d9133 NC |
13222 | |
13223 | func_type = arm_current_func_type (); | |
d5b7b3ae RE |
13224 | |
13225 | /* Naked functions don't have prologues. */ | |
6d3d9133 | 13226 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
13227 | return; |
13228 | ||
6d3d9133 NC |
13229 | if (IS_INTERRUPT (func_type)) |
13230 | { | |
c725bd79 | 13231 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
13232 | return; |
13233 | } | |
13234 | ||
5848830f PB |
13235 | offsets = arm_get_frame_offsets (); |
13236 | ||
d5b7b3ae | 13237 | if (frame_pointer_needed) |
980e61bb | 13238 | { |
5848830f PB |
13239 | insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, |
13240 | stack_pointer_rtx)); | |
980e61bb DJ |
13241 | RTX_FRAME_RELATED_P (insn) = 1; |
13242 | } | |
d5b7b3ae | 13243 | |
5848830f | 13244 | amount = offsets->outgoing_args - offsets->saved_regs; |
d5b7b3ae RE |
13245 | if (amount) |
13246 | { | |
d5b7b3ae | 13247 | if (amount < 512) |
980e61bb DJ |
13248 | { |
13249 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
13250 | GEN_INT (- amount))); | |
13251 | RTX_FRAME_RELATED_P (insn) = 1; | |
13252 | } | |
d5b7b3ae RE |
13253 | else |
13254 | { | |
d5b7b3ae RE |
13255 | rtx reg; |
13256 | ||
13257 | /* The stack decrement is too big for an immediate value in a single | |
13258 | insn. In theory we could issue multiple subtracts, but after | |
13259 | three of them it becomes more space efficient to place the full | |
13260 | value in the constant pool and load into a register. (Also the | |
13261 | ARM debugger really likes to see only one stack decrement per | |
13262 | function). So instead we look for a scratch register into which | |
13263 | we can load the decrement, and then we subtract this from the | |
13264 | stack pointer. Unfortunately on the thumb the only available | |
13265 | scratch registers are the argument registers, and we cannot use | |
13266 | these as they may hold arguments to the function. Instead we | |
13267 | attempt to locate a call preserved register which is used by this | |
13268 | function. If we can find one, then we know that it will have | |
13269 | been pushed at the start of the prologue and so we can corrupt | |
13270 | it now. */ | |
13271 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
aeaf4d25 | 13272 | if (THUMB_REG_PUSHED_P (regno) |
5895f793 RE |
13273 | && !(frame_pointer_needed |
13274 | && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) | |
d5b7b3ae RE |
13275 | break; |
13276 | ||
aeaf4d25 | 13277 | if (regno > LAST_LO_REGNUM) /* Very unlikely. */ |
d5b7b3ae | 13278 | { |
f1c25d3b | 13279 | rtx spare = gen_rtx_REG (SImode, IP_REGNUM); |
d5b7b3ae | 13280 | |
6bc82793 | 13281 | /* Choose an arbitrary, non-argument low register. */ |
f1c25d3b | 13282 | reg = gen_rtx_REG (SImode, LAST_LO_REGNUM); |
d5b7b3ae RE |
13283 | |
13284 | /* Save it by copying it into a high, scratch register. */ | |
c14a3a45 NC |
13285 | emit_insn (gen_movsi (spare, reg)); |
13286 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
6bacc7b0 | 13287 | emit_insn (gen_prologue_use (spare)); |
d5b7b3ae RE |
13288 | |
13289 | /* Decrement the stack. */ | |
1d6e90ac | 13290 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
13291 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
13292 | stack_pointer_rtx, reg)); | |
13293 | RTX_FRAME_RELATED_P (insn) = 1; | |
13294 | dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, | |
13295 | plus_constant (stack_pointer_rtx, | |
13296 | GEN_INT (- amount))); | |
13297 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
13298 | REG_NOTES (insn) | |
13299 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
13300 | REG_NOTES (insn)); | |
d5b7b3ae RE |
13301 | |
13302 | /* Restore the low register's original value. */ | |
13303 | emit_insn (gen_movsi (reg, spare)); | |
13304 | ||
13305 | /* Emit a USE of the restored scratch register, so that flow | |
13306 | analysis will not consider the restore redundant. The | |
13307 | register won't be used again in this function and isn't | |
13308 | restored by the epilogue. */ | |
6bacc7b0 | 13309 | emit_insn (gen_prologue_use (reg)); |
d5b7b3ae RE |
13310 | } |
13311 | else | |
13312 | { | |
f1c25d3b | 13313 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 13314 | |
1d6e90ac | 13315 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb DJ |
13316 | |
13317 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, | |
13318 | stack_pointer_rtx, reg)); | |
13319 | RTX_FRAME_RELATED_P (insn) = 1; | |
13320 | dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, | |
13321 | plus_constant (stack_pointer_rtx, | |
13322 | GEN_INT (- amount))); | |
13323 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
13324 | REG_NOTES (insn) | |
13325 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, | |
13326 | REG_NOTES (insn)); | |
d5b7b3ae RE |
13327 | } |
13328 | } | |
983e6484 PB |
13329 | /* If the frame pointer is needed, emit a special barrier that |
13330 | will prevent the scheduler from moving stores to the frame | |
13331 | before the stack adjustment. */ | |
13332 | if (frame_pointer_needed) | |
13333 | emit_insn (gen_stack_tie (stack_pointer_rtx, | |
13334 | hard_frame_pointer_rtx)); | |
d5b7b3ae RE |
13335 | } |
13336 | ||
70f4f91c | 13337 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae | 13338 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
13339 | |
13340 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
13341 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
13342 | { | |
13343 | if (THUMB_REG_PUSHED_P (regno)) | |
13344 | { | |
13345 | cfun->machine->lr_save_eliminated = 0; | |
13346 | break; | |
13347 | } | |
13348 | } | |
13349 | ||
13350 | /* If the link register is being kept alive, with the return address in it, | |
13351 | then make sure that it does not get reused by the ce2 pass. */ | |
13352 | if (cfun->machine->lr_save_eliminated) | |
13353 | emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); | |
d5b7b3ae RE |
13354 | } |
13355 | ||
13356 | void | |
e32bac5b | 13357 | thumb_expand_epilogue (void) |
d5b7b3ae | 13358 | { |
5848830f PB |
13359 | HOST_WIDE_INT amount; |
13360 | arm_stack_offsets *offsets; | |
defc0463 RE |
13361 | int regno; |
13362 | ||
6d3d9133 NC |
13363 | /* Naked functions don't have prologues. */ |
13364 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
13365 | return; |
13366 | ||
5848830f PB |
13367 | offsets = arm_get_frame_offsets (); |
13368 | amount = offsets->outgoing_args - offsets->saved_regs; | |
13369 | ||
d5b7b3ae RE |
13370 | if (frame_pointer_needed) |
13371 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
13372 | else if (amount) | |
13373 | { | |
d5b7b3ae RE |
13374 | if (amount < 512) |
13375 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
13376 | GEN_INT (amount))); | |
13377 | else | |
13378 | { | |
13379 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 13380 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
13381 | |
13382 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
13383 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
13384 | } | |
13385 | } | |
13386 | ||
13387 | /* Emit a USE (stack_pointer_rtx), so that | |
13388 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 13389 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 13390 | |
70f4f91c | 13391 | if (current_function_profile || TARGET_NO_SCHED_PRO) |
d5b7b3ae | 13392 | emit_insn (gen_blockage ()); |
defc0463 RE |
13393 | |
13394 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
13395 | so that flow2 will get register lifetimes correct. */ | |
13396 | for (regno = 0; regno < 13; regno++) | |
13397 | if (regs_ever_live[regno] && !call_used_regs[regno]) | |
13398 | emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno))); | |
13399 | ||
13400 | if (! regs_ever_live[LR_REGNUM]) | |
13401 | emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))); | |
d5b7b3ae RE |
13402 | } |
13403 | ||
08c148a8 | 13404 | static void |
e32bac5b | 13405 | thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae RE |
13406 | { |
13407 | int live_regs_mask = 0; | |
13408 | int high_regs_pushed = 0; | |
980e61bb | 13409 | int cfa_offset = 0; |
d5b7b3ae RE |
13410 | int regno; |
13411 | ||
6d3d9133 | 13412 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
13413 | return; |
13414 | ||
13415 | if (is_called_in_ARM_mode (current_function_decl)) | |
13416 | { | |
13417 | const char * name; | |
13418 | ||
13419 | if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) | |
13420 | abort (); | |
13421 | if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) | |
13422 | abort (); | |
13423 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
13424 | ||
13425 | /* Generate code sequence to switch us into Thumb mode. */ | |
13426 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 13427 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
13428 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
13429 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
13430 | ||
13431 | /* Generate a label, so that the debugger will notice the | |
13432 | change in instruction sets. This label is also used by | |
13433 | the assembler to bypass the ARM code when this function | |
13434 | is called from a Thumb encoded function elsewhere in the | |
13435 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 13436 | agree with the definition in gas/config/tc-arm.c. */ |
d5b7b3ae RE |
13437 | |
13438 | #define STUB_NAME ".real_start_of" | |
13439 | ||
761c70aa | 13440 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
13441 | #ifdef ARM_PE |
13442 | if (arm_dllexport_name_p (name)) | |
e5951263 | 13443 | name = arm_strip_name_encoding (name); |
d5b7b3ae RE |
13444 | #endif |
13445 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); | |
761c70aa | 13446 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
13447 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
13448 | } | |
13449 | ||
d5b7b3ae RE |
13450 | if (current_function_pretend_args_size) |
13451 | { | |
3cb66fd7 | 13452 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
13453 | { |
13454 | int num_pushes; | |
13455 | ||
761c70aa | 13456 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 13457 | |
e9d7b180 | 13458 | num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); |
d5b7b3ae RE |
13459 | |
13460 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; | |
13461 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 13462 | regno++) |
d5b7b3ae RE |
13463 | asm_fprintf (f, "%r%s", regno, |
13464 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
13465 | ||
761c70aa | 13466 | fprintf (f, "}\n"); |
d5b7b3ae RE |
13467 | } |
13468 | else | |
13469 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", | |
13470 | SP_REGNUM, SP_REGNUM, | |
13471 | current_function_pretend_args_size); | |
980e61bb DJ |
13472 | |
13473 | /* We don't need to record the stores for unwinding (would it | |
13474 | help the debugger any if we did?), but record the change in | |
13475 | the stack pointer. */ | |
13476 | if (dwarf2out_do_frame ()) | |
13477 | { | |
13478 | char *l = dwarf2out_cfi_label (); | |
13479 | cfa_offset = cfa_offset + current_function_pretend_args_size; | |
13480 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
13481 | } | |
d5b7b3ae RE |
13482 | } |
13483 | ||
5895f793 | 13484 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) |
aeaf4d25 | 13485 | if (THUMB_REG_PUSHED_P (regno)) |
d5b7b3ae RE |
13486 | live_regs_mask |= 1 << regno; |
13487 | ||
3c7ad43e | 13488 | if (live_regs_mask || thumb_force_lr_save ()) |
d5b7b3ae RE |
13489 | live_regs_mask |= 1 << LR_REGNUM; |
13490 | ||
13491 | if (TARGET_BACKTRACE) | |
13492 | { | |
13493 | int offset; | |
13494 | int work_register = 0; | |
13495 | int wr; | |
13496 | ||
13497 | /* We have been asked to create a stack backtrace structure. | |
13498 | The code looks like this: | |
13499 | ||
13500 | 0 .align 2 | |
13501 | 0 func: | |
13502 | 0 sub SP, #16 Reserve space for 4 registers. | |
13503 | 2 push {R7} Get a work register. | |
13504 | 4 add R7, SP, #20 Get the stack pointer before the push. | |
13505 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
13506 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
13507 | 10 str R7, [SP, #16] Store it. | |
13508 | 12 mov R7, FP Get hold of the current frame pointer. | |
13509 | 14 str R7, [SP, #4] Store it. | |
13510 | 16 mov R7, LR Get hold of the current return address. | |
13511 | 18 str R7, [SP, #12] Store it. | |
13512 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
13513 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
13514 | ||
13515 | if ((live_regs_mask & 0xFF) == 0) | |
13516 | { | |
13517 | /* See if the a4 register is free. */ | |
13518 | ||
13519 | if (regs_ever_live [LAST_ARG_REGNUM] == 0) | |
13520 | work_register = LAST_ARG_REGNUM; | |
d6b4baa4 | 13521 | else /* We must push a register of our own. */ |
d5b7b3ae RE |
13522 | live_regs_mask |= (1 << LAST_LO_REGNUM); |
13523 | } | |
13524 | ||
13525 | if (work_register == 0) | |
13526 | { | |
13527 | /* Select a register from the list that will be pushed to | |
13528 | use as our work register. */ | |
13529 | for (work_register = (LAST_LO_REGNUM + 1); work_register--;) | |
13530 | if ((1 << work_register) & live_regs_mask) | |
13531 | break; | |
13532 | } | |
13533 | ||
13534 | asm_fprintf | |
13535 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
13536 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
13537 | |
13538 | if (dwarf2out_do_frame ()) | |
13539 | { | |
13540 | char *l = dwarf2out_cfi_label (); | |
13541 | cfa_offset = cfa_offset + 16; | |
13542 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
13543 | } | |
13544 | ||
d5b7b3ae | 13545 | if (live_regs_mask) |
980e61bb | 13546 | thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); |
d5b7b3ae RE |
13547 | |
13548 | for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) | |
13549 | if (wr & live_regs_mask) | |
13550 | offset += 4; | |
13551 | ||
13552 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
13553 | offset + 16 + current_function_pretend_args_size); | |
13554 | ||
13555 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13556 | offset + 4); | |
13557 | ||
13558 | /* Make sure that the instruction fetching the PC is in the right place | |
13559 | to calculate "start of backtrace creation code + 12". */ | |
13560 | if (live_regs_mask) | |
13561 | { | |
13562 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
13563 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13564 | offset + 12); | |
13565 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
13566 | ARM_HARD_FRAME_POINTER_REGNUM); | |
13567 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13568 | offset); | |
13569 | } | |
13570 | else | |
13571 | { | |
13572 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
13573 | ARM_HARD_FRAME_POINTER_REGNUM); | |
13574 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13575 | offset); | |
13576 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
13577 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13578 | offset + 12); | |
13579 | } | |
13580 | ||
13581 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); | |
13582 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
13583 | offset + 8); | |
13584 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
13585 | offset + 12); | |
13586 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
13587 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
13588 | } | |
13589 | else if (live_regs_mask) | |
980e61bb | 13590 | thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); |
d5b7b3ae RE |
13591 | |
13592 | for (regno = 8; regno < 13; regno++) | |
e26053d1 NC |
13593 | if (THUMB_REG_PUSHED_P (regno)) |
13594 | high_regs_pushed++; | |
d5b7b3ae RE |
13595 | |
13596 | if (high_regs_pushed) | |
13597 | { | |
13598 | int pushable_regs = 0; | |
13599 | int mask = live_regs_mask & 0xff; | |
13600 | int next_hi_reg; | |
13601 | ||
13602 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
e26053d1 NC |
13603 | if (THUMB_REG_PUSHED_P (next_hi_reg)) |
13604 | break; | |
d5b7b3ae RE |
13605 | |
13606 | pushable_regs = mask; | |
13607 | ||
13608 | if (pushable_regs == 0) | |
13609 | { | |
13610 | /* Desperation time -- this probably will never happen. */ | |
aeaf4d25 | 13611 | if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)) |
d5b7b3ae RE |
13612 | asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); |
13613 | mask = 1 << LAST_ARG_REGNUM; | |
13614 | } | |
13615 | ||
13616 | while (high_regs_pushed > 0) | |
13617 | { | |
980e61bb DJ |
13618 | int real_regs_mask = 0; |
13619 | ||
d5b7b3ae RE |
13620 | for (regno = LAST_LO_REGNUM; regno >= 0; regno--) |
13621 | { | |
13622 | if (mask & (1 << regno)) | |
13623 | { | |
13624 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
13625 | ||
5895f793 | 13626 | high_regs_pushed--; |
980e61bb | 13627 | real_regs_mask |= (1 << next_hi_reg); |
d5b7b3ae RE |
13628 | |
13629 | if (high_regs_pushed) | |
aeaf4d25 AN |
13630 | { |
13631 | for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; | |
13632 | next_hi_reg--) | |
13633 | if (THUMB_REG_PUSHED_P (next_hi_reg)) | |
d5b7b3ae | 13634 | break; |
aeaf4d25 | 13635 | } |
d5b7b3ae RE |
13636 | else |
13637 | { | |
5895f793 | 13638 | mask &= ~((1 << regno) - 1); |
d5b7b3ae RE |
13639 | break; |
13640 | } | |
13641 | } | |
13642 | } | |
980e61bb DJ |
13643 | |
13644 | thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae RE |
13645 | } |
13646 | ||
13647 | if (pushable_regs == 0 | |
aeaf4d25 | 13648 | && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))) |
d5b7b3ae RE |
13649 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
13650 | } | |
13651 | } | |
13652 | ||
13653 | /* Handle the case of a double word load into a low register from | |
13654 | a computed memory address. The computed address may involve a | |
13655 | register which is overwritten by the load. */ | |
cd2b33d0 | 13656 | const char * |
e32bac5b | 13657 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
13658 | { |
13659 | rtx addr; | |
13660 | rtx base; | |
13661 | rtx offset; | |
13662 | rtx arg1; | |
13663 | rtx arg2; | |
13664 | ||
13665 | if (GET_CODE (operands[0]) != REG) | |
400500c4 | 13666 | abort (); |
d5b7b3ae RE |
13667 | |
13668 | if (GET_CODE (operands[1]) != MEM) | |
400500c4 | 13669 | abort (); |
d5b7b3ae RE |
13670 | |
13671 | /* Get the memory address. */ | |
13672 | addr = XEXP (operands[1], 0); | |
13673 | ||
13674 | /* Work out how the memory address is computed. */ | |
13675 | switch (GET_CODE (addr)) | |
13676 | { | |
13677 | case REG: | |
f1c25d3b KH |
13678 | operands[2] = gen_rtx_MEM (SImode, |
13679 | plus_constant (XEXP (operands[1], 0), 4)); | |
d5b7b3ae RE |
13680 | |
13681 | if (REGNO (operands[0]) == REGNO (addr)) | |
13682 | { | |
13683 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13684 | output_asm_insn ("ldr\t%0, %1", operands); | |
13685 | } | |
13686 | else | |
13687 | { | |
13688 | output_asm_insn ("ldr\t%0, %1", operands); | |
13689 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13690 | } | |
13691 | break; | |
13692 | ||
13693 | case CONST: | |
13694 | /* Compute <address> + 4 for the high order load. */ | |
f1c25d3b KH |
13695 | operands[2] = gen_rtx_MEM (SImode, |
13696 | plus_constant (XEXP (operands[1], 0), 4)); | |
d5b7b3ae RE |
13697 | |
13698 | output_asm_insn ("ldr\t%0, %1", operands); | |
13699 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13700 | break; | |
13701 | ||
13702 | case PLUS: | |
13703 | arg1 = XEXP (addr, 0); | |
13704 | arg2 = XEXP (addr, 1); | |
13705 | ||
13706 | if (CONSTANT_P (arg1)) | |
13707 | base = arg2, offset = arg1; | |
13708 | else | |
13709 | base = arg1, offset = arg2; | |
13710 | ||
13711 | if (GET_CODE (base) != REG) | |
400500c4 | 13712 | abort (); |
d5b7b3ae RE |
13713 | |
13714 | /* Catch the case of <address> = <reg> + <reg> */ | |
13715 | if (GET_CODE (offset) == REG) | |
13716 | { | |
13717 | int reg_offset = REGNO (offset); | |
13718 | int reg_base = REGNO (base); | |
13719 | int reg_dest = REGNO (operands[0]); | |
13720 | ||
13721 | /* Add the base and offset registers together into the | |
13722 | higher destination register. */ | |
13723 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
13724 | reg_dest + 1, reg_base, reg_offset); | |
13725 | ||
13726 | /* Load the lower destination register from the address in | |
13727 | the higher destination register. */ | |
13728 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
13729 | reg_dest, reg_dest + 1); | |
13730 | ||
13731 | /* Load the higher destination register from its own address | |
13732 | plus 4. */ | |
13733 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
13734 | reg_dest + 1, reg_dest + 1); | |
13735 | } | |
13736 | else | |
13737 | { | |
13738 | /* Compute <address> + 4 for the high order load. */ | |
f1c25d3b KH |
13739 | operands[2] = gen_rtx_MEM (SImode, |
13740 | plus_constant (XEXP (operands[1], 0), 4)); | |
d5b7b3ae RE |
13741 | |
13742 | /* If the computed address is held in the low order register | |
13743 | then load the high order register first, otherwise always | |
13744 | load the low order register first. */ | |
13745 | if (REGNO (operands[0]) == REGNO (base)) | |
13746 | { | |
13747 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13748 | output_asm_insn ("ldr\t%0, %1", operands); | |
13749 | } | |
13750 | else | |
13751 | { | |
13752 | output_asm_insn ("ldr\t%0, %1", operands); | |
13753 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13754 | } | |
13755 | } | |
13756 | break; | |
13757 | ||
13758 | case LABEL_REF: | |
13759 | /* With no registers to worry about we can just load the value | |
13760 | directly. */ | |
f1c25d3b KH |
13761 | operands[2] = gen_rtx_MEM (SImode, |
13762 | plus_constant (XEXP (operands[1], 0), 4)); | |
d5b7b3ae RE |
13763 | |
13764 | output_asm_insn ("ldr\t%H0, %2", operands); | |
13765 | output_asm_insn ("ldr\t%0, %1", operands); | |
13766 | break; | |
13767 | ||
13768 | default: | |
400500c4 | 13769 | abort (); |
d5b7b3ae RE |
13770 | break; |
13771 | } | |
13772 | ||
13773 | return ""; | |
13774 | } | |
13775 | ||
cd2b33d0 | 13776 | const char * |
e32bac5b | 13777 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
13778 | { |
13779 | rtx tmp; | |
13780 | ||
13781 | switch (n) | |
13782 | { | |
13783 | case 2: | |
ca356f3a | 13784 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 13785 | { |
ca356f3a RE |
13786 | tmp = operands[4]; |
13787 | operands[4] = operands[5]; | |
13788 | operands[5] = tmp; | |
d5b7b3ae | 13789 | } |
ca356f3a RE |
13790 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
13791 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
13792 | break; |
13793 | ||
13794 | case 3: | |
ca356f3a | 13795 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 13796 | { |
ca356f3a RE |
13797 | tmp = operands[4]; |
13798 | operands[4] = operands[5]; | |
13799 | operands[5] = tmp; | |
d5b7b3ae | 13800 | } |
ca356f3a | 13801 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 13802 | { |
ca356f3a RE |
13803 | tmp = operands[5]; |
13804 | operands[5] = operands[6]; | |
13805 | operands[6] = tmp; | |
d5b7b3ae | 13806 | } |
ca356f3a | 13807 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 13808 | { |
ca356f3a RE |
13809 | tmp = operands[4]; |
13810 | operands[4] = operands[5]; | |
13811 | operands[5] = tmp; | |
d5b7b3ae RE |
13812 | } |
13813 | ||
ca356f3a RE |
13814 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
13815 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
13816 | break; |
13817 | ||
13818 | default: | |
13819 | abort (); | |
13820 | } | |
13821 | ||
13822 | return ""; | |
13823 | } | |
13824 | ||
1d6e90ac | 13825 | /* Routines for generating rtl. */ |
d5b7b3ae | 13826 | void |
70128ad9 | 13827 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
13828 | { |
13829 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
13830 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
13831 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
13832 | HOST_WIDE_INT offset = 0; | |
13833 | ||
13834 | while (len >= 12) | |
13835 | { | |
ca356f3a | 13836 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
13837 | len -= 12; |
13838 | } | |
13839 | ||
13840 | if (len >= 8) | |
13841 | { | |
ca356f3a | 13842 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
13843 | len -= 8; |
13844 | } | |
13845 | ||
13846 | if (len >= 4) | |
13847 | { | |
13848 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
13849 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
13850 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
13851 | len -= 4; |
13852 | offset += 4; | |
13853 | } | |
13854 | ||
13855 | if (len >= 2) | |
13856 | { | |
13857 | rtx reg = gen_reg_rtx (HImode); | |
f1c25d3b KH |
13858 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
13859 | plus_constant (in, offset)))); | |
13860 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
13861 | reg)); |
13862 | len -= 2; | |
13863 | offset += 2; | |
13864 | } | |
13865 | ||
13866 | if (len) | |
13867 | { | |
13868 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
13869 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
13870 | plus_constant (in, offset)))); | |
13871 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
13872 | reg)); |
13873 | } | |
13874 | } | |
13875 | ||
13876 | int | |
e32bac5b | 13877 | thumb_cmp_operand (rtx op, enum machine_mode mode) |
d5b7b3ae RE |
13878 | { |
13879 | return ((GET_CODE (op) == CONST_INT | |
c769a35d RE |
13880 | && INTVAL (op) < 256 |
13881 | && INTVAL (op) >= 0) | |
defc0463 | 13882 | || s_register_operand (op, mode)); |
d5b7b3ae RE |
13883 | } |
13884 | ||
c769a35d RE |
13885 | int |
13886 | thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) | |
13887 | { | |
13888 | return (GET_CODE (op) == CONST_INT | |
13889 | && INTVAL (op) < 0 | |
13890 | && INTVAL (op) > -256); | |
13891 | } | |
13892 | ||
defc0463 RE |
13893 | /* Return TRUE if a result can be stored in OP without clobbering the |
13894 | condition code register. Prior to reload we only accept a | |
13895 | register. After reload we have to be able to handle memory as | |
13896 | well, since a pseudo may not get a hard reg and reload cannot | |
13897 | handle output-reloads on jump insns. | |
d5b7b3ae | 13898 | |
defc0463 RE |
13899 | We could possibly handle mem before reload as well, but that might |
13900 | complicate things with the need to handle increment | |
13901 | side-effects. */ | |
d5b7b3ae | 13902 | |
defc0463 RE |
13903 | int |
13904 | thumb_cbrch_target_operand (rtx op, enum machine_mode mode) | |
13905 | { | |
13906 | return (s_register_operand (op, mode) | |
13907 | || ((reload_in_progress || reload_completed) | |
13908 | && memory_operand (op, mode))); | |
d5b7b3ae RE |
13909 | } |
13910 | ||
13911 | /* Handle storing a half-word to memory during reload. */ | |
13912 | void | |
e32bac5b | 13913 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
13914 | { |
13915 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
13916 | } | |
13917 | ||
e32bac5b | 13918 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 13919 | void |
e32bac5b | 13920 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae RE |
13921 | { |
13922 | abort (); | |
13923 | } | |
13924 | ||
c27ba912 DM |
13925 | /* Return the length of a function name prefix |
13926 | that starts with the character 'c'. */ | |
13927 | static int | |
e32bac5b | 13928 | arm_get_strip_length (int c) |
c27ba912 DM |
13929 | { |
13930 | switch (c) | |
13931 | { | |
13932 | ARM_NAME_ENCODING_LENGTHS | |
13933 | default: return 0; | |
13934 | } | |
13935 | } | |
13936 | ||
13937 | /* Return a pointer to a function's name with any | |
13938 | and all prefix encodings stripped from it. */ | |
13939 | const char * | |
e32bac5b | 13940 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
13941 | { |
13942 | int skip; | |
13943 | ||
13944 | while ((skip = arm_get_strip_length (* name))) | |
13945 | name += skip; | |
13946 | ||
13947 | return name; | |
13948 | } | |
13949 | ||
e1944073 KW |
13950 | /* If there is a '*' anywhere in the name's prefix, then |
13951 | emit the stripped name verbatim, otherwise prepend an | |
13952 | underscore if leading underscores are being used. */ | |
e1944073 | 13953 | void |
e32bac5b | 13954 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
13955 | { |
13956 | int skip; | |
13957 | int verbatim = 0; | |
13958 | ||
13959 | while ((skip = arm_get_strip_length (* name))) | |
13960 | { | |
13961 | verbatim |= (*name == '*'); | |
13962 | name += skip; | |
13963 | } | |
13964 | ||
13965 | if (verbatim) | |
13966 | fputs (name, stream); | |
13967 | else | |
13968 | asm_fprintf (stream, "%U%s", name); | |
13969 | } | |
13970 | ||
e2500fed GK |
13971 | rtx aof_pic_label; |
13972 | ||
2b835d68 | 13973 | #ifdef AOF_ASSEMBLER |
6354dc9b | 13974 | /* Special functions only needed when producing AOF syntax assembler. */ |
2b835d68 | 13975 | |
32de079a RE |
13976 | struct pic_chain |
13977 | { | |
62b10bbc | 13978 | struct pic_chain * next; |
5f37d07c | 13979 | const char * symname; |
32de079a RE |
13980 | }; |
13981 | ||
62b10bbc | 13982 | static struct pic_chain * aof_pic_chain = NULL; |
32de079a RE |
13983 | |
13984 | rtx | |
e32bac5b | 13985 | aof_pic_entry (rtx x) |
32de079a | 13986 | { |
62b10bbc | 13987 | struct pic_chain ** chainp; |
32de079a RE |
13988 | int offset; |
13989 | ||
13990 | if (aof_pic_label == NULL_RTX) | |
13991 | { | |
43cffd11 | 13992 | aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); |
32de079a RE |
13993 | } |
13994 | ||
13995 | for (offset = 0, chainp = &aof_pic_chain; *chainp; | |
13996 | offset += 4, chainp = &(*chainp)->next) | |
13997 | if ((*chainp)->symname == XSTR (x, 0)) | |
13998 | return plus_constant (aof_pic_label, offset); | |
13999 | ||
14000 | *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); | |
14001 | (*chainp)->next = NULL; | |
14002 | (*chainp)->symname = XSTR (x, 0); | |
14003 | return plus_constant (aof_pic_label, offset); | |
14004 | } | |
14005 | ||
14006 | void | |
e32bac5b | 14007 | aof_dump_pic_table (FILE *f) |
32de079a | 14008 | { |
62b10bbc | 14009 | struct pic_chain * chain; |
32de079a RE |
14010 | |
14011 | if (aof_pic_chain == NULL) | |
14012 | return; | |
14013 | ||
dd18ae56 NC |
14014 | asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", |
14015 | PIC_OFFSET_TABLE_REGNUM, | |
14016 | PIC_OFFSET_TABLE_REGNUM); | |
32de079a RE |
14017 | fputs ("|x$adcons|\n", f); |
14018 | ||
14019 | for (chain = aof_pic_chain; chain; chain = chain->next) | |
14020 | { | |
14021 | fputs ("\tDCD\t", f); | |
14022 | assemble_name (f, chain->symname); | |
14023 | fputs ("\n", f); | |
14024 | } | |
14025 | } | |
14026 | ||
2b835d68 RE |
14027 | int arm_text_section_count = 1; |
14028 | ||
14029 | char * | |
e32bac5b | 14030 | aof_text_section (void ) |
2b835d68 RE |
14031 | { |
14032 | static char buf[100]; | |
2b835d68 RE |
14033 | sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", |
14034 | arm_text_section_count++); | |
14035 | if (flag_pic) | |
14036 | strcat (buf, ", PIC, REENTRANT"); | |
14037 | return buf; | |
14038 | } | |
14039 | ||
14040 | static int arm_data_section_count = 1; | |
14041 | ||
14042 | char * | |
e32bac5b | 14043 | aof_data_section (void) |
2b835d68 RE |
14044 | { |
14045 | static char buf[100]; | |
14046 | sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); | |
14047 | return buf; | |
14048 | } | |
14049 | ||
14050 | /* The AOF assembler is religiously strict about declarations of | |
14051 | imported and exported symbols, so that it is impossible to declare | |
956d6950 | 14052 | a function as imported near the beginning of the file, and then to |
2b835d68 RE |
14053 | export it later on. It is, however, possible to delay the decision |
14054 | until all the functions in the file have been compiled. To get | |
14055 | around this, we maintain a list of the imports and exports, and | |
14056 | delete from it any that are subsequently defined. At the end of | |
14057 | compilation we spit the remainder of the list out before the END | |
14058 | directive. */ | |
14059 | ||
14060 | struct import | |
14061 | { | |
62b10bbc | 14062 | struct import * next; |
5f37d07c | 14063 | const char * name; |
2b835d68 RE |
14064 | }; |
14065 | ||
62b10bbc | 14066 | static struct import * imports_list = NULL; |
2b835d68 RE |
14067 | |
14068 | void | |
e32bac5b | 14069 | aof_add_import (const char *name) |
2b835d68 | 14070 | { |
62b10bbc | 14071 | struct import * new; |
2b835d68 RE |
14072 | |
14073 | for (new = imports_list; new; new = new->next) | |
14074 | if (new->name == name) | |
14075 | return; | |
14076 | ||
14077 | new = (struct import *) xmalloc (sizeof (struct import)); | |
14078 | new->next = imports_list; | |
14079 | imports_list = new; | |
14080 | new->name = name; | |
14081 | } | |
14082 | ||
14083 | void | |
e32bac5b | 14084 | aof_delete_import (const char *name) |
2b835d68 | 14085 | { |
62b10bbc | 14086 | struct import ** old; |
2b835d68 RE |
14087 | |
14088 | for (old = &imports_list; *old; old = & (*old)->next) | |
14089 | { | |
14090 | if ((*old)->name == name) | |
14091 | { | |
14092 | *old = (*old)->next; | |
14093 | return; | |
14094 | } | |
14095 | } | |
14096 | } | |
14097 | ||
14098 | int arm_main_function = 0; | |
14099 | ||
a5fe455b | 14100 | static void |
e32bac5b | 14101 | aof_dump_imports (FILE *f) |
2b835d68 RE |
14102 | { |
14103 | /* The AOF assembler needs this to cause the startup code to be extracted | |
14104 | from the library. Brining in __main causes the whole thing to work | |
14105 | automagically. */ | |
14106 | if (arm_main_function) | |
14107 | { | |
14108 | text_section (); | |
14109 | fputs ("\tIMPORT __main\n", f); | |
14110 | fputs ("\tDCD __main\n", f); | |
14111 | } | |
14112 | ||
14113 | /* Now dump the remaining imports. */ | |
14114 | while (imports_list) | |
14115 | { | |
14116 | fprintf (f, "\tIMPORT\t"); | |
14117 | assemble_name (f, imports_list->name); | |
14118 | fputc ('\n', f); | |
14119 | imports_list = imports_list->next; | |
14120 | } | |
14121 | } | |
5eb99654 KG |
14122 | |
14123 | static void | |
e32bac5b | 14124 | aof_globalize_label (FILE *stream, const char *name) |
5eb99654 KG |
14125 | { |
14126 | default_globalize_label (stream, name); | |
14127 | if (! strcmp (name, "main")) | |
14128 | arm_main_function = 1; | |
14129 | } | |
a5fe455b | 14130 | |
1bc7c5b6 | 14131 | static void |
f1777882 | 14132 | aof_file_start (void) |
1bc7c5b6 ZW |
14133 | { |
14134 | fputs ("__r0\tRN\t0\n", asm_out_file); | |
14135 | fputs ("__a1\tRN\t0\n", asm_out_file); | |
14136 | fputs ("__a2\tRN\t1\n", asm_out_file); | |
14137 | fputs ("__a3\tRN\t2\n", asm_out_file); | |
14138 | fputs ("__a4\tRN\t3\n", asm_out_file); | |
14139 | fputs ("__v1\tRN\t4\n", asm_out_file); | |
14140 | fputs ("__v2\tRN\t5\n", asm_out_file); | |
14141 | fputs ("__v3\tRN\t6\n", asm_out_file); | |
14142 | fputs ("__v4\tRN\t7\n", asm_out_file); | |
14143 | fputs ("__v5\tRN\t8\n", asm_out_file); | |
14144 | fputs ("__v6\tRN\t9\n", asm_out_file); | |
14145 | fputs ("__sl\tRN\t10\n", asm_out_file); | |
14146 | fputs ("__fp\tRN\t11\n", asm_out_file); | |
14147 | fputs ("__ip\tRN\t12\n", asm_out_file); | |
14148 | fputs ("__sp\tRN\t13\n", asm_out_file); | |
14149 | fputs ("__lr\tRN\t14\n", asm_out_file); | |
14150 | fputs ("__pc\tRN\t15\n", asm_out_file); | |
14151 | fputs ("__f0\tFN\t0\n", asm_out_file); | |
14152 | fputs ("__f1\tFN\t1\n", asm_out_file); | |
14153 | fputs ("__f2\tFN\t2\n", asm_out_file); | |
14154 | fputs ("__f3\tFN\t3\n", asm_out_file); | |
14155 | fputs ("__f4\tFN\t4\n", asm_out_file); | |
14156 | fputs ("__f5\tFN\t5\n", asm_out_file); | |
14157 | fputs ("__f6\tFN\t6\n", asm_out_file); | |
14158 | fputs ("__f7\tFN\t7\n", asm_out_file); | |
14159 | text_section (); | |
14160 | } | |
14161 | ||
a5fe455b | 14162 | static void |
e32bac5b | 14163 | aof_file_end (void) |
a5fe455b ZW |
14164 | { |
14165 | if (flag_pic) | |
14166 | aof_dump_pic_table (asm_out_file); | |
14167 | aof_dump_imports (asm_out_file); | |
14168 | fputs ("\tEND\n", asm_out_file); | |
14169 | } | |
2b835d68 | 14170 | #endif /* AOF_ASSEMBLER */ |
7c262518 | 14171 | |
ebe413e5 | 14172 | #ifdef OBJECT_FORMAT_ELF |
7c262518 RH |
14173 | /* Switch to an arbitrary section NAME with attributes as specified |
14174 | by FLAGS. ALIGN specifies any known alignment requirements for | |
14175 | the section; 0 if the default should be used. | |
14176 | ||
14177 | Differs from the default elf version only in the prefix character | |
14178 | used before the section type. */ | |
14179 | ||
14180 | static void | |
e32bac5b | 14181 | arm_elf_asm_named_section (const char *name, unsigned int flags) |
7c262518 | 14182 | { |
6a0a6ac4 AM |
14183 | char flagchars[10], *f = flagchars; |
14184 | ||
14185 | if (! named_section_first_declaration (name)) | |
14186 | { | |
14187 | fprintf (asm_out_file, "\t.section\t%s\n", name); | |
14188 | return; | |
14189 | } | |
7c262518 RH |
14190 | |
14191 | if (!(flags & SECTION_DEBUG)) | |
14192 | *f++ = 'a'; | |
14193 | if (flags & SECTION_WRITE) | |
14194 | *f++ = 'w'; | |
14195 | if (flags & SECTION_CODE) | |
14196 | *f++ = 'x'; | |
14197 | if (flags & SECTION_SMALL) | |
14198 | *f++ = 's'; | |
201556f0 JJ |
14199 | if (flags & SECTION_MERGE) |
14200 | *f++ = 'M'; | |
14201 | if (flags & SECTION_STRINGS) | |
14202 | *f++ = 'S'; | |
6a0a6ac4 AM |
14203 | if (flags & SECTION_TLS) |
14204 | *f++ = 'T'; | |
7c262518 RH |
14205 | *f = '\0'; |
14206 | ||
6a0a6ac4 | 14207 | fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars); |
7c262518 | 14208 | |
6a0a6ac4 AM |
14209 | if (!(flags & SECTION_NOTYPE)) |
14210 | { | |
14211 | const char *type; | |
14212 | ||
14213 | if (flags & SECTION_BSS) | |
14214 | type = "nobits"; | |
14215 | else | |
14216 | type = "progbits"; | |
14217 | ||
14218 | fprintf (asm_out_file, ",%%%s", type); | |
14219 | ||
14220 | if (flags & SECTION_ENTSIZE) | |
14221 | fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE); | |
14222 | } | |
14223 | ||
14224 | putc ('\n', asm_out_file); | |
7c262518 | 14225 | } |
ebe413e5 | 14226 | #endif |
fb49053f RH |
14227 | |
14228 | #ifndef ARM_PE | |
14229 | /* Symbols in the text segment can be accessed without indirecting via the | |
14230 | constant pool; it may take an extra binary operation, but this is still | |
14231 | faster than indirecting via memory. Don't do this when not optimizing, | |
14232 | since we won't be calculating al of the offsets necessary to do this | |
14233 | simplification. */ | |
14234 | ||
14235 | static void | |
e32bac5b | 14236 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f RH |
14237 | { |
14238 | /* This doesn't work with AOF syntax, since the string table may be in | |
14239 | a different AREA. */ | |
14240 | #ifndef AOF_ASSEMBLER | |
3521b33c | 14241 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 14242 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f RH |
14243 | #endif |
14244 | ||
14245 | /* If we are referencing a function that is weak then encode a long call | |
14246 | flag in the function name, otherwise if the function is static or | |
14247 | or known to be defined in this file then encode a short call flag. */ | |
14248 | if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd') | |
14249 | { | |
14250 | if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) | |
14251 | arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); | |
14252 | else if (! TREE_PUBLIC (decl)) | |
14253 | arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); | |
14254 | } | |
14255 | } | |
14256 | #endif /* !ARM_PE */ | |
483ab821 | 14257 | |
4977bab6 | 14258 | static void |
e32bac5b | 14259 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
14260 | { |
14261 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
14262 | && !strcmp (prefix, "L")) | |
14263 | { | |
14264 | arm_ccfsm_state = 0; | |
14265 | arm_target_insn = NULL; | |
14266 | } | |
14267 | default_internal_label (stream, prefix, labelno); | |
14268 | } | |
14269 | ||
c590b625 RH |
14270 | /* Output code to add DELTA to the first argument, and then jump |
14271 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 14272 | static void |
e32bac5b RE |
14273 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
14274 | HOST_WIDE_INT delta, | |
14275 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
14276 | tree function) | |
483ab821 | 14277 | { |
9b66ebb1 PB |
14278 | static int thunk_label = 0; |
14279 | char label[256]; | |
483ab821 MM |
14280 | int mi_delta = delta; |
14281 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
14282 | int shift = 0; | |
61f71b34 | 14283 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
14284 | ? 1 : 0); |
14285 | if (mi_delta < 0) | |
14286 | mi_delta = - mi_delta; | |
9b66ebb1 PB |
14287 | if (TARGET_THUMB) |
14288 | { | |
14289 | int labelno = thunk_label++; | |
14290 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
14291 | fputs ("\tldr\tr12, ", file); | |
14292 | assemble_name (file, label); | |
14293 | fputc ('\n', file); | |
14294 | } | |
483ab821 MM |
14295 | while (mi_delta != 0) |
14296 | { | |
14297 | if ((mi_delta & (3 << shift)) == 0) | |
14298 | shift += 2; | |
14299 | else | |
14300 | { | |
14301 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
14302 | mi_op, this_regno, this_regno, | |
14303 | mi_delta & (0xff << shift)); | |
14304 | mi_delta &= ~(0xff << shift); | |
14305 | shift += 8; | |
14306 | } | |
14307 | } | |
9b66ebb1 PB |
14308 | if (TARGET_THUMB) |
14309 | { | |
14310 | fprintf (file, "\tbx\tr12\n"); | |
14311 | ASM_OUTPUT_ALIGN (file, 2); | |
14312 | assemble_name (file, label); | |
14313 | fputs (":\n", file); | |
14314 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
14315 | } | |
14316 | else | |
14317 | { | |
14318 | fputs ("\tb\t", file); | |
14319 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
14320 | if (NEED_PLT_RELOC) | |
14321 | fputs ("(PLT)", file); | |
14322 | fputc ('\n', file); | |
14323 | } | |
483ab821 | 14324 | } |
5a9335ef NC |
14325 | |
14326 | int | |
6f5f2481 | 14327 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
14328 | { |
14329 | int i; | |
14330 | const char * pattern; | |
14331 | ||
14332 | if (GET_CODE (x) != CONST_VECTOR) | |
14333 | abort (); | |
14334 | ||
14335 | switch (GET_MODE (x)) | |
14336 | { | |
14337 | case V2SImode: pattern = "%08x"; break; | |
14338 | case V4HImode: pattern = "%04x"; break; | |
14339 | case V8QImode: pattern = "%02x"; break; | |
14340 | default: abort (); | |
14341 | } | |
14342 | ||
14343 | fprintf (file, "0x"); | |
14344 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
14345 | { | |
14346 | rtx element; | |
14347 | ||
14348 | element = CONST_VECTOR_ELT (x, i); | |
14349 | fprintf (file, pattern, INTVAL (element)); | |
14350 | } | |
14351 | ||
14352 | return 1; | |
14353 | } | |
14354 | ||
14355 | const char * | |
6f5f2481 | 14356 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
14357 | { |
14358 | rtx reg; | |
14359 | rtx offset; | |
14360 | rtx wcgr; | |
14361 | rtx sum; | |
14362 | ||
14363 | if (GET_CODE (operands [1]) != MEM | |
14364 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
14365 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
14366 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
14367 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
14368 | return "wldrw%?\t%0, %1"; | |
14369 | ||
14370 | /* Fix up an out-of-range load of a GR register. */ | |
14371 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); | |
14372 | wcgr = operands[0]; | |
14373 | operands[0] = reg; | |
14374 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
14375 | ||
14376 | operands[0] = wcgr; | |
14377 | operands[1] = reg; | |
14378 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
14379 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
14380 | ||
14381 | return ""; | |
14382 | } | |
f9ba5949 KH |
14383 | |
14384 | static rtx | |
14385 | arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
14386 | int incoming ATTRIBUTE_UNUSED) | |
14387 | { | |
14388 | #if 0 | |
14389 | /* FIXME: The ARM backend has special code to handle structure | |
14390 | returns, and will reserve its own hidden first argument. So | |
14391 | if this macro is enabled a *second* hidden argument will be | |
14392 | reserved, which will break binary compatibility with old | |
14393 | toolchains and also thunk handling. One day this should be | |
14394 | fixed. */ | |
14395 | return 0; | |
14396 | #else | |
14397 | /* Register in which address to store a structure value | |
14398 | is passed to a function. */ | |
14399 | return gen_rtx_REG (Pmode, ARG_REGISTER (1)); | |
14400 | #endif | |
14401 | } | |
1cc9f5f5 KH |
14402 | |
14403 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. | |
14404 | ||
14405 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
14406 | named arg and all anonymous args onto the stack. | |
14407 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
14408 | that way. */ | |
14409 | ||
14410 | static void | |
14411 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
14412 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
14413 | tree type ATTRIBUTE_UNUSED, | |
14414 | int *pretend_size, | |
14415 | int second_time ATTRIBUTE_UNUSED) | |
14416 | { | |
14417 | cfun->machine->uses_anonymous_args = 1; | |
14418 | if (cum->nregs < NUM_ARG_REGS) | |
14419 | *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD; | |
14420 | } | |
9b66ebb1 | 14421 | |
59b9a953 | 14422 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
14423 | PRODUCER's value to calculate the address. */ |
14424 | ||
14425 | int | |
14426 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
14427 | { | |
14428 | rtx value = PATTERN (producer); | |
14429 | rtx addr = PATTERN (consumer); | |
14430 | ||
14431 | if (GET_CODE (value) == COND_EXEC) | |
14432 | value = COND_EXEC_CODE (value); | |
14433 | if (GET_CODE (value) == PARALLEL) | |
14434 | value = XVECEXP (value, 0, 0); | |
14435 | value = XEXP (value, 0); | |
14436 | if (GET_CODE (addr) == COND_EXEC) | |
14437 | addr = COND_EXEC_CODE (addr); | |
14438 | if (GET_CODE (addr) == PARALLEL) | |
14439 | addr = XVECEXP (addr, 0, 0); | |
14440 | addr = XEXP (addr, 0); | |
14441 | ||
14442 | return !reg_overlap_mentioned_p (value, addr); | |
14443 | } | |
14444 | ||
59b9a953 | 14445 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
14446 | have an early register shift value or amount dependency on the |
14447 | result of PRODUCER. */ | |
14448 | ||
14449 | int | |
14450 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
14451 | { | |
14452 | rtx value = PATTERN (producer); | |
14453 | rtx op = PATTERN (consumer); | |
14454 | rtx early_op; | |
14455 | ||
14456 | if (GET_CODE (value) == COND_EXEC) | |
14457 | value = COND_EXEC_CODE (value); | |
14458 | if (GET_CODE (value) == PARALLEL) | |
14459 | value = XVECEXP (value, 0, 0); | |
14460 | value = XEXP (value, 0); | |
14461 | if (GET_CODE (op) == COND_EXEC) | |
14462 | op = COND_EXEC_CODE (op); | |
14463 | if (GET_CODE (op) == PARALLEL) | |
14464 | op = XVECEXP (op, 0, 0); | |
14465 | op = XEXP (op, 1); | |
14466 | ||
14467 | early_op = XEXP (op, 0); | |
14468 | /* This is either an actual independent shift, or a shift applied to | |
14469 | the first operand of another operation. We want the whole shift | |
14470 | operation. */ | |
14471 | if (GET_CODE (early_op) == REG) | |
14472 | early_op = op; | |
14473 | ||
14474 | return !reg_overlap_mentioned_p (value, early_op); | |
14475 | } | |
14476 | ||
59b9a953 | 14477 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
14478 | have an early register shift value dependency on the result of |
14479 | PRODUCER. */ | |
14480 | ||
14481 | int | |
14482 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
14483 | { | |
14484 | rtx value = PATTERN (producer); | |
14485 | rtx op = PATTERN (consumer); | |
14486 | rtx early_op; | |
14487 | ||
14488 | if (GET_CODE (value) == COND_EXEC) | |
14489 | value = COND_EXEC_CODE (value); | |
14490 | if (GET_CODE (value) == PARALLEL) | |
14491 | value = XVECEXP (value, 0, 0); | |
14492 | value = XEXP (value, 0); | |
14493 | if (GET_CODE (op) == COND_EXEC) | |
14494 | op = COND_EXEC_CODE (op); | |
14495 | if (GET_CODE (op) == PARALLEL) | |
14496 | op = XVECEXP (op, 0, 0); | |
14497 | op = XEXP (op, 1); | |
14498 | ||
14499 | early_op = XEXP (op, 0); | |
14500 | ||
14501 | /* This is either an actual independent shift, or a shift applied to | |
14502 | the first operand of another operation. We want the value being | |
14503 | shifted, in either case. */ | |
14504 | if (GET_CODE (early_op) != REG) | |
14505 | early_op = XEXP (early_op, 0); | |
14506 | ||
14507 | return !reg_overlap_mentioned_p (value, early_op); | |
14508 | } | |
14509 | ||
59b9a953 | 14510 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
14511 | have an early register mult dependency on the result of |
14512 | PRODUCER. */ | |
14513 | ||
14514 | int | |
14515 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
14516 | { | |
14517 | rtx value = PATTERN (producer); | |
14518 | rtx op = PATTERN (consumer); | |
14519 | ||
14520 | if (GET_CODE (value) == COND_EXEC) | |
14521 | value = COND_EXEC_CODE (value); | |
14522 | if (GET_CODE (value) == PARALLEL) | |
14523 | value = XVECEXP (value, 0, 0); | |
14524 | value = XEXP (value, 0); | |
14525 | if (GET_CODE (op) == COND_EXEC) | |
14526 | op = COND_EXEC_CODE (op); | |
14527 | if (GET_CODE (op) == PARALLEL) | |
14528 | op = XVECEXP (op, 0, 0); | |
14529 | op = XEXP (op, 1); | |
14530 | ||
14531 | return (GET_CODE (op) == PLUS | |
14532 | && !reg_overlap_mentioned_p (value, XEXP (op, 0))); | |
14533 | } | |
14534 | ||
70301b45 PB |
14535 | |
14536 | /* We can't rely on the caller doing the proper promotion when | |
14537 | using APCS or ATPCS. */ | |
14538 | ||
14539 | static bool | |
14540 | arm_promote_prototypes (tree t ATTRIBUTE_UNUSED) | |
14541 | { | |
b6685939 | 14542 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
14543 | } |
14544 | ||
6b045785 PB |
14545 | |
14546 | /* AAPCS based ABIs use short enums by default. */ | |
14547 | ||
14548 | static bool | |
14549 | arm_default_short_enums (void) | |
14550 | { | |
14551 | return TARGET_AAPCS_BASED; | |
14552 | } | |
13c1cd82 PB |
14553 | |
14554 | ||
14555 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
14556 | ||
14557 | static bool | |
14558 | arm_align_anon_bitfield (void) | |
14559 | { | |
14560 | return TARGET_AAPCS_BASED; | |
14561 | } | |
4185ae53 PB |
14562 | |
14563 | ||
14564 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
14565 | ||
14566 | static tree | |
14567 | arm_cxx_guard_type (void) | |
14568 | { | |
14569 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
14570 | } | |
14571 | ||
14572 | ||
14573 | /* The EABI says test the least significan bit of a guard variable. */ | |
14574 | ||
14575 | static bool | |
14576 | arm_cxx_guard_mask_bit (void) | |
14577 | { | |
14578 | return TARGET_AAPCS_BASED; | |
14579 | } | |
46e995e0 PB |
14580 | |
14581 | ||
14582 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
14583 | ||
14584 | static tree | |
14585 | arm_get_cookie_size (tree type) | |
14586 | { | |
14587 | tree size; | |
14588 | ||
14589 | if (!TARGET_AAPCS_BASED) | |
14590 | return default_cxx_get_cookie_size (type); | |
14591 | ||
14592 | size = build_int_2 (8, 0); | |
14593 | TREE_TYPE (size) = sizetype; | |
14594 | return size; | |
14595 | } | |
14596 | ||
14597 | ||
14598 | /* The EABI says that array cookies should also contain the element size. */ | |
14599 | ||
14600 | static bool | |
14601 | arm_cookie_has_size (void) | |
14602 | { | |
14603 | return TARGET_AAPCS_BASED; | |
14604 | } |