]>
Commit | Line | Data |
---|---|---|
b36ba79f | 1 | /* Output routines for GCC for ARM. |
f954388e | 2 | Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
b3a796bc JJ |
3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
cce8749e | 5 | Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) |
956d6950 | 6 | and Martin Simmons (@harleqn.co.uk). |
b36ba79f | 7 | More major hacks by Richard Earnshaw (rearnsha@arm.com). |
cce8749e | 8 | |
4f448245 | 9 | This file is part of GCC. |
cce8749e | 10 | |
4f448245 NC |
11 | GCC is free software; you can redistribute it and/or modify it |
12 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 13 | by the Free Software Foundation; either version 3, or (at your |
4f448245 | 14 | option) any later version. |
cce8749e | 15 | |
4f448245 NC |
16 | GCC is distributed in the hope that it will be useful, but WITHOUT |
17 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
18 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
19 | License for more details. | |
cce8749e | 20 | |
4f448245 | 21 | You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
f676971a | 24 | |
56636818 | 25 | #include "config.h" |
43cffd11 | 26 | #include "system.h" |
4977bab6 ZW |
27 | #include "coretypes.h" |
28 | #include "tm.h" | |
cce8749e | 29 | #include "rtl.h" |
d5b7b3ae | 30 | #include "tree.h" |
c7319d87 | 31 | #include "obstack.h" |
cce8749e CH |
32 | #include "regs.h" |
33 | #include "hard-reg-set.h" | |
34 | #include "real.h" | |
35 | #include "insn-config.h" | |
36 | #include "conditions.h" | |
cce8749e CH |
37 | #include "output.h" |
38 | #include "insn-attr.h" | |
39 | #include "flags.h" | |
af48348a | 40 | #include "reload.h" |
49ad7cfa | 41 | #include "function.h" |
bee06f3d | 42 | #include "expr.h" |
e78d8e51 | 43 | #include "optabs.h" |
ad076f4e | 44 | #include "toplev.h" |
aec3cfba | 45 | #include "recog.h" |
92a432f4 | 46 | #include "ggc.h" |
d5b7b3ae | 47 | #include "except.h" |
8b97c5f8 | 48 | #include "c-pragma.h" |
7b8b8ade | 49 | #include "integrate.h" |
c27ba912 | 50 | #include "tm_p.h" |
672a6f42 NB |
51 | #include "target.h" |
52 | #include "target-def.h" | |
980e61bb | 53 | #include "debug.h" |
6e34d3a3 | 54 | #include "langhooks.h" |
6fb5fa3c | 55 | #include "df.h" |
0fd8c3ad | 56 | #include "intl.h" |
cce8749e | 57 | |
d5b7b3ae RE |
58 | /* Forward definitions of types. */ |
59 | typedef struct minipool_node Mnode; | |
60 | typedef struct minipool_fixup Mfix; | |
61 | ||
6bc7bc14 | 62 | EXPORTED_CONST struct attribute_spec arm_attribute_table[]; |
1d6e90ac | 63 | |
b76c3c4b PB |
64 | void (*arm_lang_output_object_attributes_hook)(void); |
65 | ||
d5b7b3ae | 66 | /* Forward function declarations. */ |
35596784 | 67 | static int arm_compute_static_chain_stack_bytes (void); |
5848830f | 68 | static arm_stack_offsets *arm_get_frame_offsets (void); |
e32bac5b | 69 | static void arm_add_gc_roots (void); |
a406f566 MM |
70 | static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, |
71 | HOST_WIDE_INT, rtx, rtx, int, int); | |
e32bac5b RE |
72 | static unsigned bit_count (unsigned long); |
73 | static int arm_address_register_rtx_p (rtx, int); | |
1e1ab407 | 74 | static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); |
5b3e6663 PB |
75 | static int thumb2_legitimate_index_p (enum machine_mode, rtx, int); |
76 | static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int); | |
506d7b68 PB |
77 | static rtx arm_legitimize_address (rtx, rtx, enum machine_mode); |
78 | static rtx thumb_legitimize_address (rtx, rtx, enum machine_mode); | |
5b3e6663 | 79 | inline static int thumb1_index_register_rtx_p (rtx, int); |
c6c3dba9 | 80 | static bool arm_legitimate_address_p (enum machine_mode, rtx, bool); |
5848830f | 81 | static int thumb_far_jump_used_p (void); |
57934c39 | 82 | static bool thumb_force_lr_save (void); |
e32bac5b | 83 | static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); |
e32bac5b | 84 | static rtx emit_sfm (int, int); |
466e4b7a | 85 | static unsigned arm_size_return_regs (void); |
e32bac5b | 86 | static bool arm_assemble_integer (rtx, unsigned int, int); |
e32bac5b RE |
87 | static const char *fp_const_from_val (REAL_VALUE_TYPE *); |
88 | static arm_cc get_arm_condition_code (rtx); | |
e32bac5b RE |
89 | static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); |
90 | static rtx is_jump_table (rtx); | |
91 | static const char *output_multi_immediate (rtx *, const char *, const char *, | |
92 | int, HOST_WIDE_INT); | |
e32bac5b RE |
93 | static const char *shift_op (rtx, HOST_WIDE_INT *); |
94 | static struct machine_function *arm_init_machine_status (void); | |
c9ca9b88 | 95 | static void thumb_exit (FILE *, int); |
e32bac5b RE |
96 | static rtx is_jump_table (rtx); |
97 | static HOST_WIDE_INT get_jump_table_size (rtx); | |
98 | static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
99 | static Mnode *add_minipool_forward_ref (Mfix *); | |
100 | static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); | |
101 | static Mnode *add_minipool_backward_ref (Mfix *); | |
102 | static void assign_minipool_offsets (Mfix *); | |
103 | static void arm_print_value (FILE *, rtx); | |
104 | static void dump_minipool (rtx); | |
105 | static int arm_barrier_cost (rtx); | |
106 | static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); | |
107 | static void push_minipool_barrier (rtx, HOST_WIDE_INT); | |
108 | static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, | |
109 | rtx); | |
110 | static void arm_reorg (void); | |
111 | static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); | |
e32bac5b RE |
112 | static unsigned long arm_compute_save_reg0_reg12_mask (void); |
113 | static unsigned long arm_compute_save_reg_mask (void); | |
114 | static unsigned long arm_isr_value (tree); | |
115 | static unsigned long arm_compute_func_type (void); | |
116 | static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); | |
117 | static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); | |
7bff66a7 | 118 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 | 119 | static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); |
7bff66a7 | 120 | #endif |
e32bac5b RE |
121 | static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); |
122 | static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); | |
5b3e6663 | 123 | static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT); |
3101faab | 124 | static int arm_comp_type_attributes (const_tree, const_tree); |
e32bac5b RE |
125 | static void arm_set_default_type_attributes (tree); |
126 | static int arm_adjust_cost (rtx, rtx, rtx, int); | |
e32bac5b RE |
127 | static int count_insns_for_constant (HOST_WIDE_INT, int); |
128 | static int arm_get_strip_length (int); | |
129 | static bool arm_function_ok_for_sibcall (tree, tree); | |
130 | static void arm_internal_label (FILE *, const char *, unsigned long); | |
131 | static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, | |
132 | tree); | |
d5a0a47b RE |
133 | static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool); |
134 | static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *); | |
135 | static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
136 | static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
137 | static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
138 | static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); | |
f40751dd JH |
139 | static bool arm_rtx_costs (rtx, int, int, int *, bool); |
140 | static int arm_address_cost (rtx, bool); | |
e32bac5b RE |
141 | static bool arm_memory_load_p (rtx); |
142 | static bool arm_cirrus_insn_p (rtx); | |
143 | static void cirrus_reorg (rtx); | |
5a9335ef NC |
144 | static void arm_init_builtins (void); |
145 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
146 | static void arm_init_iwmmxt_builtins (void); | |
147 | static rtx safe_vector_operand (rtx, enum machine_mode); | |
148 | static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); | |
149 | static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); | |
150 | static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); | |
a406f566 | 151 | static void emit_constant_insn (rtx cond, rtx pattern); |
d66437c5 | 152 | static rtx emit_set_insn (rtx, rtx); |
78a52f11 RH |
153 | static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
154 | tree, bool); | |
5a9335ef | 155 | |
7abc66b1 | 156 | #ifdef OBJECT_FORMAT_ELF |
9403b7f7 RS |
157 | static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED; |
158 | static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; | |
7abc66b1 | 159 | #endif |
fb49053f | 160 | #ifndef ARM_PE |
e32bac5b | 161 | static void arm_encode_section_info (tree, rtx, int); |
fb49053f | 162 | #endif |
b12a00f1 RE |
163 | |
164 | static void arm_file_end (void); | |
6c6aa1af | 165 | static void arm_file_start (void); |
b12a00f1 | 166 | |
1cc9f5f5 KH |
167 | static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, |
168 | tree, int *, int); | |
8cd5a4e0 | 169 | static bool arm_pass_by_reference (CUMULATIVE_ARGS *, |
586de218 KG |
170 | enum machine_mode, const_tree, bool); |
171 | static bool arm_promote_prototypes (const_tree); | |
6b045785 | 172 | static bool arm_default_short_enums (void); |
13c1cd82 | 173 | static bool arm_align_anon_bitfield (void); |
586de218 KG |
174 | static bool arm_return_in_msb (const_tree); |
175 | static bool arm_must_pass_in_stack (enum machine_mode, const_tree); | |
23668cf7 | 176 | static bool arm_return_in_memory (const_tree, const_tree); |
617a1b71 PB |
177 | #ifdef TARGET_UNWIND_INFO |
178 | static void arm_unwind_emit (FILE *, rtx); | |
179 | static bool arm_output_ttype (rtx); | |
180 | #endif | |
5b3e6663 | 181 | static void arm_dwarf_handle_frame_unspec (const char *, rtx, int); |
c237e94a | 182 | |
4185ae53 PB |
183 | static tree arm_cxx_guard_type (void); |
184 | static bool arm_cxx_guard_mask_bit (void); | |
46e995e0 PB |
185 | static tree arm_get_cookie_size (tree); |
186 | static bool arm_cookie_has_size (void); | |
44d10c10 | 187 | static bool arm_cxx_cdtor_returns_this (void); |
505970fc | 188 | static bool arm_cxx_key_method_may_be_inline (void); |
1e731102 MM |
189 | static void arm_cxx_determine_class_data_visibility (tree); |
190 | static bool arm_cxx_class_data_always_comdat (void); | |
9f62c3e3 | 191 | static bool arm_cxx_use_aeabi_atexit (void); |
b3f8d95d | 192 | static void arm_init_libfuncs (void); |
07d8efe3 MM |
193 | static tree arm_build_builtin_va_list (void); |
194 | static void arm_expand_builtin_va_start (tree, rtx); | |
ae46a823 | 195 | static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
c54c7322 | 196 | static bool arm_handle_option (size_t, const char *, int); |
67e6ba46 | 197 | static void arm_target_help (void); |
273a2526 | 198 | static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); |
d3585b76 DJ |
199 | static bool arm_cannot_copy_insn_p (rtx); |
200 | static bool arm_tls_symbol_p (rtx x); | |
bd4dc3cd | 201 | static int arm_issue_rate (void); |
afcc986d | 202 | static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
007e61c2 | 203 | static bool arm_allocate_stack_slots_for_args (void); |
0fd8c3ad SL |
204 | static const char *arm_invalid_parameter_type (const_tree t); |
205 | static const char *arm_invalid_return_type (const_tree t); | |
206 | static tree arm_promoted_type (const_tree t); | |
207 | static tree arm_convert_to_type (tree type, tree expr); | |
bdc4827b | 208 | static bool arm_scalar_mode_supported_p (enum machine_mode); |
d3585b76 | 209 | |
672a6f42 NB |
210 | \f |
211 | /* Initialize the GCC target structure. */ | |
b2ca3702 | 212 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
1d6e90ac | 213 | #undef TARGET_MERGE_DECL_ATTRIBUTES |
672a6f42 NB |
214 | #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes |
215 | #endif | |
f3bb6135 | 216 | |
506d7b68 PB |
217 | #undef TARGET_LEGITIMIZE_ADDRESS |
218 | #define TARGET_LEGITIMIZE_ADDRESS arm_legitimize_address | |
219 | ||
1d6e90ac | 220 | #undef TARGET_ATTRIBUTE_TABLE |
91d231cb | 221 | #define TARGET_ATTRIBUTE_TABLE arm_attribute_table |
672a6f42 | 222 | |
6c6aa1af PB |
223 | #undef TARGET_ASM_FILE_START |
224 | #define TARGET_ASM_FILE_START arm_file_start | |
b12a00f1 RE |
225 | #undef TARGET_ASM_FILE_END |
226 | #define TARGET_ASM_FILE_END arm_file_end | |
227 | ||
1d6e90ac | 228 | #undef TARGET_ASM_ALIGNED_SI_OP |
301d03af | 229 | #define TARGET_ASM_ALIGNED_SI_OP NULL |
1d6e90ac | 230 | #undef TARGET_ASM_INTEGER |
301d03af | 231 | #define TARGET_ASM_INTEGER arm_assemble_integer |
301d03af | 232 | |
1d6e90ac | 233 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
08c148a8 NB |
234 | #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue |
235 | ||
1d6e90ac | 236 | #undef TARGET_ASM_FUNCTION_EPILOGUE |
08c148a8 NB |
237 | #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue |
238 | ||
c54c7322 RS |
239 | #undef TARGET_DEFAULT_TARGET_FLAGS |
240 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) | |
241 | #undef TARGET_HANDLE_OPTION | |
242 | #define TARGET_HANDLE_OPTION arm_handle_option | |
67e6ba46 NC |
243 | #undef TARGET_HELP |
244 | #define TARGET_HELP arm_target_help | |
c54c7322 | 245 | |
1d6e90ac | 246 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
8d8e52be JM |
247 | #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes |
248 | ||
1d6e90ac | 249 | #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES |
8d8e52be JM |
250 | #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes |
251 | ||
1d6e90ac | 252 | #undef TARGET_SCHED_ADJUST_COST |
c237e94a ZW |
253 | #define TARGET_SCHED_ADJUST_COST arm_adjust_cost |
254 | ||
fb49053f RH |
255 | #undef TARGET_ENCODE_SECTION_INFO |
256 | #ifdef ARM_PE | |
257 | #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info | |
258 | #else | |
259 | #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info | |
260 | #endif | |
261 | ||
5a9335ef | 262 | #undef TARGET_STRIP_NAME_ENCODING |
772c5265 RH |
263 | #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding |
264 | ||
5a9335ef | 265 | #undef TARGET_ASM_INTERNAL_LABEL |
4977bab6 ZW |
266 | #define TARGET_ASM_INTERNAL_LABEL arm_internal_label |
267 | ||
5a9335ef | 268 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
4977bab6 ZW |
269 | #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall |
270 | ||
5a9335ef | 271 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
c590b625 | 272 | #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk |
5a9335ef | 273 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
3961e8fe | 274 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall |
c590b625 | 275 | |
5a9335ef | 276 | #undef TARGET_RTX_COSTS |
f40751dd | 277 | #define TARGET_RTX_COSTS arm_rtx_costs |
5a9335ef | 278 | #undef TARGET_ADDRESS_COST |
dcefdf67 | 279 | #define TARGET_ADDRESS_COST arm_address_cost |
3c50106f | 280 | |
273a2526 RS |
281 | #undef TARGET_SHIFT_TRUNCATION_MASK |
282 | #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask | |
f676971a EC |
283 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
284 | #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p | |
285 | ||
5a9335ef | 286 | #undef TARGET_MACHINE_DEPENDENT_REORG |
18dbd950 RS |
287 | #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg |
288 | ||
5a9335ef NC |
289 | #undef TARGET_INIT_BUILTINS |
290 | #define TARGET_INIT_BUILTINS arm_init_builtins | |
291 | #undef TARGET_EXPAND_BUILTIN | |
292 | #define TARGET_EXPAND_BUILTIN arm_expand_builtin | |
293 | ||
b3f8d95d MM |
294 | #undef TARGET_INIT_LIBFUNCS |
295 | #define TARGET_INIT_LIBFUNCS arm_init_libfuncs | |
296 | ||
f9ba5949 | 297 | #undef TARGET_PROMOTE_FUNCTION_ARGS |
586de218 | 298 | #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true |
d4453b7a | 299 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
586de218 | 300 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
f9ba5949 | 301 | #undef TARGET_PROMOTE_PROTOTYPES |
70301b45 | 302 | #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes |
8cd5a4e0 RH |
303 | #undef TARGET_PASS_BY_REFERENCE |
304 | #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference | |
78a52f11 RH |
305 | #undef TARGET_ARG_PARTIAL_BYTES |
306 | #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes | |
f9ba5949 | 307 | |
1cc9f5f5 KH |
308 | #undef TARGET_SETUP_INCOMING_VARARGS |
309 | #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs | |
310 | ||
007e61c2 PB |
311 | #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS |
312 | #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args | |
313 | ||
6b045785 PB |
314 | #undef TARGET_DEFAULT_SHORT_ENUMS |
315 | #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums | |
316 | ||
13c1cd82 PB |
317 | #undef TARGET_ALIGN_ANON_BITFIELD |
318 | #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield | |
319 | ||
c2a64439 PB |
320 | #undef TARGET_NARROW_VOLATILE_BITFIELD |
321 | #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false | |
322 | ||
4185ae53 PB |
323 | #undef TARGET_CXX_GUARD_TYPE |
324 | #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type | |
325 | ||
326 | #undef TARGET_CXX_GUARD_MASK_BIT | |
327 | #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit | |
328 | ||
46e995e0 PB |
329 | #undef TARGET_CXX_GET_COOKIE_SIZE |
330 | #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size | |
331 | ||
332 | #undef TARGET_CXX_COOKIE_HAS_SIZE | |
333 | #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size | |
334 | ||
44d10c10 PB |
335 | #undef TARGET_CXX_CDTOR_RETURNS_THIS |
336 | #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this | |
337 | ||
505970fc MM |
338 | #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE |
339 | #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline | |
340 | ||
9f62c3e3 PB |
341 | #undef TARGET_CXX_USE_AEABI_ATEXIT |
342 | #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit | |
343 | ||
1e731102 MM |
344 | #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY |
345 | #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ | |
346 | arm_cxx_determine_class_data_visibility | |
347 | ||
348 | #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT | |
349 | #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat | |
505970fc | 350 | |
866af8a9 JB |
351 | #undef TARGET_RETURN_IN_MSB |
352 | #define TARGET_RETURN_IN_MSB arm_return_in_msb | |
353 | ||
23668cf7 CLT |
354 | #undef TARGET_RETURN_IN_MEMORY |
355 | #define TARGET_RETURN_IN_MEMORY arm_return_in_memory | |
356 | ||
866af8a9 JB |
357 | #undef TARGET_MUST_PASS_IN_STACK |
358 | #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack | |
359 | ||
617a1b71 PB |
360 | #ifdef TARGET_UNWIND_INFO |
361 | #undef TARGET_UNWIND_EMIT | |
362 | #define TARGET_UNWIND_EMIT arm_unwind_emit | |
363 | ||
364 | /* EABI unwinding tables use a different format for the typeinfo tables. */ | |
365 | #undef TARGET_ASM_TTYPE | |
366 | #define TARGET_ASM_TTYPE arm_output_ttype | |
367 | ||
368 | #undef TARGET_ARM_EABI_UNWINDER | |
369 | #define TARGET_ARM_EABI_UNWINDER true | |
370 | #endif /* TARGET_UNWIND_INFO */ | |
371 | ||
5b3e6663 PB |
372 | #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC |
373 | #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec | |
374 | ||
d3585b76 DJ |
375 | #undef TARGET_CANNOT_COPY_INSN_P |
376 | #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p | |
377 | ||
378 | #ifdef HAVE_AS_TLS | |
379 | #undef TARGET_HAVE_TLS | |
380 | #define TARGET_HAVE_TLS true | |
381 | #endif | |
382 | ||
383 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
8426b956 | 384 | #define TARGET_CANNOT_FORCE_CONST_MEM arm_cannot_force_const_mem |
d3585b76 | 385 | |
f67358da PB |
386 | #undef TARGET_MAX_ANCHOR_OFFSET |
387 | #define TARGET_MAX_ANCHOR_OFFSET 4095 | |
388 | ||
389 | /* The minimum is set such that the total size of the block | |
390 | for a particular anchor is -4088 + 1 + 4095 bytes, which is | |
391 | divisible by eight, ensuring natural spacing of anchors. */ | |
392 | #undef TARGET_MIN_ANCHOR_OFFSET | |
393 | #define TARGET_MIN_ANCHOR_OFFSET -4088 | |
394 | ||
bd4dc3cd PB |
395 | #undef TARGET_SCHED_ISSUE_RATE |
396 | #define TARGET_SCHED_ISSUE_RATE arm_issue_rate | |
397 | ||
608063c3 JB |
398 | #undef TARGET_MANGLE_TYPE |
399 | #define TARGET_MANGLE_TYPE arm_mangle_type | |
400 | ||
07d8efe3 MM |
401 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
402 | #define TARGET_BUILD_BUILTIN_VA_LIST arm_build_builtin_va_list | |
403 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
404 | #define TARGET_EXPAND_BUILTIN_VA_START arm_expand_builtin_va_start | |
405 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR | |
406 | #define TARGET_GIMPLIFY_VA_ARG_EXPR arm_gimplify_va_arg_expr | |
407 | ||
afcc986d JM |
408 | #ifdef HAVE_AS_TLS |
409 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
410 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel | |
411 | #endif | |
412 | ||
c6c3dba9 PB |
413 | #undef TARGET_LEGITIMATE_ADDRESS_P |
414 | #define TARGET_LEGITIMATE_ADDRESS_P arm_legitimate_address_p | |
415 | ||
0fd8c3ad SL |
416 | #undef TARGET_INVALID_PARAMETER_TYPE |
417 | #define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type | |
418 | ||
419 | #undef TARGET_INVALID_RETURN_TYPE | |
420 | #define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type | |
421 | ||
422 | #undef TARGET_PROMOTED_TYPE | |
423 | #define TARGET_PROMOTED_TYPE arm_promoted_type | |
424 | ||
425 | #undef TARGET_CONVERT_TO_TYPE | |
426 | #define TARGET_CONVERT_TO_TYPE arm_convert_to_type | |
427 | ||
bdc4827b SL |
428 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
429 | #define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p | |
430 | ||
f6897b10 | 431 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 432 | \f |
c7319d87 RE |
433 | /* Obstack for minipool constant handling. */ |
434 | static struct obstack minipool_obstack; | |
1d6e90ac | 435 | static char * minipool_startobj; |
c7319d87 | 436 | |
1d6e90ac NC |
437 | /* The maximum number of insns skipped which |
438 | will be conditionalised if possible. */ | |
c27ba912 DM |
439 | static int max_insns_skipped = 5; |
440 | ||
441 | extern FILE * asm_out_file; | |
442 | ||
6354dc9b | 443 | /* True if we are currently building a constant table. */ |
13bd191d PB |
444 | int making_const_table; |
445 | ||
9b66ebb1 PB |
446 | /* The processor for which instructions should be scheduled. */ |
447 | enum processor_type arm_tune = arm_none; | |
448 | ||
2f8e468b | 449 | /* The default processor used if not overridden by commandline. */ |
6c6aa1af PB |
450 | static enum processor_type arm_default_cpu = arm_none; |
451 | ||
9b66ebb1 PB |
452 | /* Which floating point model to use. */ |
453 | enum arm_fp_model arm_fp_model; | |
bee06f3d | 454 | |
9b66ebb1 | 455 | /* Which floating point hardware is available. */ |
29ad9694 | 456 | enum fputype arm_fpu_arch; |
b111229a | 457 | |
9b66ebb1 PB |
458 | /* Which floating point hardware to schedule for. */ |
459 | enum fputype arm_fpu_tune; | |
460 | ||
461 | /* Whether to use floating point hardware. */ | |
462 | enum float_abi_type arm_float_abi; | |
463 | ||
0fd8c3ad SL |
464 | /* Which __fp16 format to use. */ |
465 | enum arm_fp16_format_type arm_fp16_format; | |
466 | ||
5848830f PB |
467 | /* Which ABI to use. */ |
468 | enum arm_abi_type arm_abi; | |
469 | ||
d3585b76 DJ |
470 | /* Which thread pointer model to use. */ |
471 | enum arm_tp_type target_thread_pointer = TP_AUTO; | |
472 | ||
b355a481 | 473 | /* Used to parse -mstructure_size_boundary command line option. */ |
723ae7c1 | 474 | int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; |
b355a481 | 475 | |
b12a00f1 | 476 | /* Used for Thumb call_via trampolines. */ |
57ecec57 | 477 | rtx thumb_call_via_label[14]; |
b12a00f1 RE |
478 | static int thumb_call_reg_needed; |
479 | ||
aec3cfba | 480 | /* Bit values used to identify processor capabilities. */ |
62b10bbc | 481 | #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ |
9b66ebb1 | 482 | #define FL_ARCH3M (1 << 1) /* Extended multiply */ |
62b10bbc NC |
483 | #define FL_MODE26 (1 << 2) /* 26-bit mode support */ |
484 | #define FL_MODE32 (1 << 3) /* 32-bit mode support */ | |
485 | #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ | |
486 | #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ | |
487 | #define FL_THUMB (1 << 6) /* Thumb aware */ | |
488 | #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ | |
489 | #define FL_STRONG (1 << 8) /* StrongARM */ | |
6bc82793 | 490 | #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ |
d19fb8e3 | 491 | #define FL_XSCALE (1 << 10) /* XScale */ |
9b6b54e2 | 492 | #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ |
9b66ebb1 | 493 | #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds |
81f9037c MM |
494 | media instructions. */ |
495 | #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ | |
abac3b49 RE |
496 | #define FL_WBUF (1 << 14) /* Schedule for write buffer ops. |
497 | Note: ARM6 & 7 derivatives only. */ | |
d3585b76 | 498 | #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ |
5b3e6663 PB |
499 | #define FL_THUMB2 (1 << 16) /* Thumb-2. */ |
500 | #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' | |
501 | profile. */ | |
7a085dce | 502 | #define FL_DIV (1 << 18) /* Hardware divide. */ |
f1adb0a9 | 503 | #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ |
88f77cba | 504 | #define FL_NEON (1 << 20) /* Neon instructions. */ |
aec3cfba | 505 | |
9b66ebb1 PB |
506 | #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ |
507 | ||
5b3e6663 PB |
508 | #define FL_FOR_ARCH2 FL_NOTM |
509 | #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32) | |
78011587 PB |
510 | #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) |
511 | #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) | |
512 | #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) | |
513 | #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) | |
514 | #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) | |
515 | #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) | |
516 | #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) | |
517 | #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE | |
518 | #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) | |
519 | #define FL_FOR_ARCH6J FL_FOR_ARCH6 | |
d3585b76 | 520 | #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) |
fa91adc6 | 521 | #define FL_FOR_ARCH6Z FL_FOR_ARCH6 |
d3585b76 | 522 | #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K |
5b3e6663 | 523 | #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2) |
bf98ec6c | 524 | #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) |
5b3e6663 PB |
525 | #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM) |
526 | #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM) | |
527 | #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) | |
528 | #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) | |
78011587 | 529 | |
1d6e90ac NC |
530 | /* The bits in this mask specify which |
531 | instructions we are allowed to generate. */ | |
0977774b | 532 | static unsigned long insn_flags = 0; |
d5b7b3ae | 533 | |
aec3cfba | 534 | /* The bits in this mask specify which instruction scheduling options should |
9b66ebb1 | 535 | be used. */ |
0977774b | 536 | static unsigned long tune_flags = 0; |
aec3cfba NC |
537 | |
538 | /* The following are used in the arm.md file as equivalents to bits | |
539 | in the above two flag variables. */ | |
540 | ||
9b66ebb1 PB |
541 | /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ |
542 | int arm_arch3m = 0; | |
2b835d68 | 543 | |
6354dc9b | 544 | /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ |
2b835d68 RE |
545 | int arm_arch4 = 0; |
546 | ||
68d560d4 RE |
547 | /* Nonzero if this chip supports the ARM Architecture 4t extensions. */ |
548 | int arm_arch4t = 0; | |
549 | ||
6354dc9b | 550 | /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ |
62b10bbc NC |
551 | int arm_arch5 = 0; |
552 | ||
b15bca31 RE |
553 | /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ |
554 | int arm_arch5e = 0; | |
555 | ||
9b66ebb1 PB |
556 | /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ |
557 | int arm_arch6 = 0; | |
558 | ||
d3585b76 DJ |
559 | /* Nonzero if this chip supports the ARM 6K extensions. */ |
560 | int arm_arch6k = 0; | |
561 | ||
5b3e6663 PB |
562 | /* Nonzero if instructions not present in the 'M' profile can be used. */ |
563 | int arm_arch_notm = 0; | |
564 | ||
aec3cfba | 565 | /* Nonzero if this chip can benefit from load scheduling. */ |
f5a1b0d2 NC |
566 | int arm_ld_sched = 0; |
567 | ||
568 | /* Nonzero if this chip is a StrongARM. */ | |
abac3b49 | 569 | int arm_tune_strongarm = 0; |
f5a1b0d2 | 570 | |
78011587 PB |
571 | /* Nonzero if this chip is a Cirrus variant. */ |
572 | int arm_arch_cirrus = 0; | |
573 | ||
5a9335ef NC |
574 | /* Nonzero if this chip supports Intel Wireless MMX technology. */ |
575 | int arm_arch_iwmmxt = 0; | |
576 | ||
d19fb8e3 | 577 | /* Nonzero if this chip is an XScale. */ |
4b3c2e48 PB |
578 | int arm_arch_xscale = 0; |
579 | ||
580 | /* Nonzero if tuning for XScale */ | |
581 | int arm_tune_xscale = 0; | |
d19fb8e3 | 582 | |
e0b92319 | 583 | /* Nonzero if we want to tune for stores that access the write-buffer. |
c5d34bb2 | 584 | This typically means an ARM6 or ARM7 with MMU or MPU. */ |
abac3b49 | 585 | int arm_tune_wbuf = 0; |
b111229a | 586 | |
7612f14d PB |
587 | /* Nonzero if tuning for Cortex-A9. */ |
588 | int arm_tune_cortex_a9 = 0; | |
589 | ||
0616531f RE |
590 | /* Nonzero if generating Thumb instructions. */ |
591 | int thumb_code = 0; | |
592 | ||
2ad4dcf9 | 593 | /* Nonzero if we should define __THUMB_INTERWORK__ in the |
f676971a | 594 | preprocessor. |
2ad4dcf9 RE |
595 | XXX This is a bit of a hack, it's intended to help work around |
596 | problems in GLD which doesn't understand that armv5t code is | |
597 | interworking clean. */ | |
598 | int arm_cpp_interwork = 0; | |
599 | ||
5b3e6663 PB |
600 | /* Nonzero if chip supports Thumb 2. */ |
601 | int arm_arch_thumb2; | |
602 | ||
603 | /* Nonzero if chip supports integer division instruction. */ | |
604 | int arm_arch_hwdiv; | |
605 | ||
cce8749e CH |
606 | /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we |
607 | must report the mode of the memory reference from PRINT_OPERAND to | |
608 | PRINT_OPERAND_ADDRESS. */ | |
f3bb6135 | 609 | enum machine_mode output_memory_reference_mode; |
cce8749e | 610 | |
32de079a | 611 | /* The register number to be used for the PIC offset register. */ |
020a4035 | 612 | unsigned arm_pic_register = INVALID_REGNUM; |
32de079a | 613 | |
aec3cfba NC |
614 | /* Set to 1 after arm_reorg has started. Reset to start at the start of |
615 | the next function. */ | |
4b632bf1 RE |
616 | static int after_arm_reorg = 0; |
617 | ||
aec3cfba | 618 | /* The maximum number of insns to be used when loading a constant. */ |
2b835d68 RE |
619 | static int arm_constant_limit = 3; |
620 | ||
cce8749e CH |
621 | /* For an explanation of these variables, see final_prescan_insn below. */ |
622 | int arm_ccfsm_state; | |
5b3e6663 | 623 | /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */ |
84ed5e79 | 624 | enum arm_cond_code arm_current_cc; |
cce8749e CH |
625 | rtx arm_target_insn; |
626 | int arm_target_label; | |
5b3e6663 PB |
627 | /* The number of conditionally executed insns, including the current insn. */ |
628 | int arm_condexec_count = 0; | |
629 | /* A bitmask specifying the patterns for the IT block. | |
630 | Zero means do not output an IT block before this insn. */ | |
631 | int arm_condexec_mask = 0; | |
632 | /* The number of bits used in arm_condexec_mask. */ | |
633 | int arm_condexec_masklen = 0; | |
9997d19d RE |
634 | |
635 | /* The condition codes of the ARM, and the inverse function. */ | |
1d6e90ac | 636 | static const char * const arm_condition_codes[] = |
9997d19d RE |
637 | { |
638 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", | |
639 | "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" | |
640 | }; | |
641 | ||
5b3e6663 | 642 | #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl") |
f5a1b0d2 | 643 | #define streq(string1, string2) (strcmp (string1, string2) == 0) |
5b3e6663 PB |
644 | |
645 | #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \ | |
646 | | (1 << SP_REGNUM) | (1 << PC_REGNUM) \ | |
647 | | (1 << PIC_OFFSET_TABLE_REGNUM))) | |
2b835d68 | 648 | \f |
6354dc9b | 649 | /* Initialization code. */ |
2b835d68 | 650 | |
2b835d68 RE |
651 | struct processors |
652 | { | |
8b60264b | 653 | const char *const name; |
9b66ebb1 | 654 | enum processor_type core; |
78011587 | 655 | const char *arch; |
0977774b | 656 | const unsigned long flags; |
d5a0a47b | 657 | bool (* rtx_costs) (rtx, enum rtx_code, enum rtx_code, int *, bool); |
2b835d68 RE |
658 | }; |
659 | ||
660 | /* Not all of these give usefully different compilation alternatives, | |
661 | but there is no simple way of generalizing them. */ | |
8b60264b | 662 | static const struct processors all_cores[] = |
f5a1b0d2 NC |
663 | { |
664 | /* ARM Cores */ | |
d98a72fd RE |
665 | #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ |
666 | {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, | |
9b66ebb1 PB |
667 | #include "arm-cores.def" |
668 | #undef ARM_CORE | |
78011587 | 669 | {NULL, arm_none, NULL, 0, NULL} |
f5a1b0d2 NC |
670 | }; |
671 | ||
8b60264b | 672 | static const struct processors all_architectures[] = |
2b835d68 | 673 | { |
f5a1b0d2 | 674 | /* ARM Architectures */ |
9b66ebb1 PB |
675 | /* We don't specify rtx_costs here as it will be figured out |
676 | from the core. */ | |
f676971a | 677 | |
78011587 PB |
678 | {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, |
679 | {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, | |
680 | {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, | |
681 | {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, | |
682 | {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, | |
b111229a RE |
683 | /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no |
684 | implementations that support it, so we will leave it out for now. */ | |
78011587 PB |
685 | {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, |
686 | {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, | |
687 | {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, | |
688 | {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, | |
689 | {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, | |
690 | {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, | |
691 | {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, | |
fa91adc6 PB |
692 | {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, |
693 | {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, | |
694 | {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, | |
5b3e6663 | 695 | {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL}, |
bf98ec6c | 696 | {"armv6-m", cortexm1, "6M", FL_FOR_ARCH6M, NULL}, |
5b3e6663 PB |
697 | {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL}, |
698 | {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL}, | |
699 | {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL}, | |
700 | {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL}, | |
78011587 PB |
701 | {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, |
702 | {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, | |
442dc742 | 703 | {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, |
78011587 | 704 | {NULL, arm_none, NULL, 0 , NULL} |
f5a1b0d2 NC |
705 | }; |
706 | ||
c54c7322 RS |
707 | struct arm_cpu_select |
708 | { | |
709 | const char * string; | |
710 | const char * name; | |
711 | const struct processors * processors; | |
712 | }; | |
713 | ||
9a9f7594 | 714 | /* This is a magic structure. The 'string' field is magically filled in |
f5a1b0d2 NC |
715 | with a pointer to the value specified by the user on the command line |
716 | assuming that the user has specified such a value. */ | |
717 | ||
c54c7322 | 718 | static struct arm_cpu_select arm_select[] = |
f5a1b0d2 | 719 | { |
f676971a | 720 | /* string name processors */ |
f5a1b0d2 NC |
721 | { NULL, "-mcpu=", all_cores }, |
722 | { NULL, "-march=", all_architectures }, | |
723 | { NULL, "-mtune=", all_cores } | |
2b835d68 RE |
724 | }; |
725 | ||
e6fffade RE |
726 | /* Defines representing the indexes into the above table. */ |
727 | #define ARM_OPT_SET_CPU 0 | |
728 | #define ARM_OPT_SET_ARCH 1 | |
729 | #define ARM_OPT_SET_TUNE 2 | |
78011587 | 730 | |
afc0a4ba | 731 | /* The name of the preprocessor macro to define for this architecture. */ |
78011587 PB |
732 | |
733 | char arm_arch_name[] = "__ARM_ARCH_0UNK__"; | |
734 | ||
9b66ebb1 PB |
735 | struct fpu_desc |
736 | { | |
737 | const char * name; | |
738 | enum fputype fpu; | |
739 | }; | |
740 | ||
741 | ||
56f42830 | 742 | /* Available values for -mfpu=. */ |
9b66ebb1 PB |
743 | |
744 | static const struct fpu_desc all_fpus[] = | |
745 | { | |
0fd8c3ad SL |
746 | {"fpa", FPUTYPE_FPA}, |
747 | {"fpe2", FPUTYPE_FPA_EMU2}, | |
748 | {"fpe3", FPUTYPE_FPA_EMU2}, | |
749 | {"maverick", FPUTYPE_MAVERICK}, | |
750 | {"vfp", FPUTYPE_VFP}, | |
751 | {"vfp3", FPUTYPE_VFP3}, | |
752 | {"vfpv3", FPUTYPE_VFP3}, | |
753 | {"vfpv3-d16", FPUTYPE_VFP3D16}, | |
754 | {"neon", FPUTYPE_NEON}, | |
755 | {"neon-fp16", FPUTYPE_NEON_FP16} | |
9b66ebb1 PB |
756 | }; |
757 | ||
758 | ||
759 | /* Floating point models used by the different hardware. | |
760 | See fputype in arm.h. */ | |
761 | ||
32e8bb8e | 762 | static const enum arm_fp_model fp_model_for_fpu[] = |
9b66ebb1 PB |
763 | { |
764 | /* No FP hardware. */ | |
765 | ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ | |
766 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ | |
767 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ | |
768 | ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ | |
769 | ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ | |
f1adb0a9 | 770 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */ |
302c3d8e | 771 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3D16 */ |
88f77cba | 772 | ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */ |
0fd8c3ad SL |
773 | ARM_FP_MODEL_VFP, /* FPUTYPE_NEON */ |
774 | ARM_FP_MODEL_VFP /* FPUTYPE_NEON_FP16 */ | |
9b66ebb1 PB |
775 | }; |
776 | ||
777 | ||
778 | struct float_abi | |
779 | { | |
780 | const char * name; | |
781 | enum float_abi_type abi_type; | |
782 | }; | |
783 | ||
784 | ||
785 | /* Available values for -mfloat-abi=. */ | |
786 | ||
787 | static const struct float_abi all_float_abis[] = | |
788 | { | |
789 | {"soft", ARM_FLOAT_ABI_SOFT}, | |
790 | {"softfp", ARM_FLOAT_ABI_SOFTFP}, | |
791 | {"hard", ARM_FLOAT_ABI_HARD} | |
792 | }; | |
793 | ||
794 | ||
0fd8c3ad SL |
795 | struct fp16_format |
796 | { | |
797 | const char *name; | |
798 | enum arm_fp16_format_type fp16_format_type; | |
799 | }; | |
800 | ||
801 | ||
802 | /* Available values for -mfp16-format=. */ | |
803 | ||
804 | static const struct fp16_format all_fp16_formats[] = | |
805 | { | |
806 | {"none", ARM_FP16_FORMAT_NONE}, | |
807 | {"ieee", ARM_FP16_FORMAT_IEEE}, | |
808 | {"alternative", ARM_FP16_FORMAT_ALTERNATIVE} | |
809 | }; | |
810 | ||
811 | ||
5848830f PB |
812 | struct abi_name |
813 | { | |
814 | const char *name; | |
815 | enum arm_abi_type abi_type; | |
816 | }; | |
817 | ||
818 | ||
819 | /* Available values for -mabi=. */ | |
820 | ||
821 | static const struct abi_name arm_all_abis[] = | |
822 | { | |
823 | {"apcs-gnu", ARM_ABI_APCS}, | |
824 | {"atpcs", ARM_ABI_ATPCS}, | |
825 | {"aapcs", ARM_ABI_AAPCS}, | |
077fc835 KH |
826 | {"iwmmxt", ARM_ABI_IWMMXT}, |
827 | {"aapcs-linux", ARM_ABI_AAPCS_LINUX} | |
5848830f PB |
828 | }; |
829 | ||
d3585b76 DJ |
830 | /* Supported TLS relocations. */ |
831 | ||
832 | enum tls_reloc { | |
833 | TLS_GD32, | |
834 | TLS_LDM32, | |
835 | TLS_LDO32, | |
836 | TLS_IE32, | |
837 | TLS_LE32 | |
838 | }; | |
839 | ||
d66437c5 RE |
840 | /* Emit an insn that's a simple single-set. Both the operands must be known |
841 | to be valid. */ | |
842 | inline static rtx | |
843 | emit_set_insn (rtx x, rtx y) | |
844 | { | |
845 | return emit_insn (gen_rtx_SET (VOIDmode, x, y)); | |
846 | } | |
847 | ||
0977774b JT |
848 | /* Return the number of bits set in VALUE. */ |
849 | static unsigned | |
e32bac5b | 850 | bit_count (unsigned long value) |
aec3cfba | 851 | { |
d5b7b3ae | 852 | unsigned long count = 0; |
f676971a | 853 | |
aec3cfba NC |
854 | while (value) |
855 | { | |
0977774b JT |
856 | count++; |
857 | value &= value - 1; /* Clear the least-significant set bit. */ | |
aec3cfba NC |
858 | } |
859 | ||
860 | return count; | |
861 | } | |
862 | ||
c112cf2b | 863 | /* Set up library functions unique to ARM. */ |
b3f8d95d MM |
864 | |
865 | static void | |
866 | arm_init_libfuncs (void) | |
867 | { | |
868 | /* There are no special library functions unless we are using the | |
869 | ARM BPABI. */ | |
870 | if (!TARGET_BPABI) | |
871 | return; | |
872 | ||
873 | /* The functions below are described in Section 4 of the "Run-Time | |
874 | ABI for the ARM architecture", Version 1.0. */ | |
875 | ||
876 | /* Double-precision floating-point arithmetic. Table 2. */ | |
877 | set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); | |
878 | set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); | |
879 | set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); | |
880 | set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); | |
881 | set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); | |
882 | ||
c112cf2b | 883 | /* Double-precision comparisons. Table 3. */ |
b3f8d95d MM |
884 | set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); |
885 | set_optab_libfunc (ne_optab, DFmode, NULL); | |
886 | set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); | |
887 | set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); | |
888 | set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); | |
889 | set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); | |
890 | set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); | |
891 | ||
892 | /* Single-precision floating-point arithmetic. Table 4. */ | |
893 | set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); | |
894 | set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); | |
895 | set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); | |
896 | set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); | |
897 | set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); | |
f676971a | 898 | |
c112cf2b | 899 | /* Single-precision comparisons. Table 5. */ |
b3f8d95d MM |
900 | set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); |
901 | set_optab_libfunc (ne_optab, SFmode, NULL); | |
902 | set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); | |
903 | set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); | |
904 | set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); | |
905 | set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); | |
906 | set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); | |
907 | ||
908 | /* Floating-point to integer conversions. Table 6. */ | |
909 | set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); | |
910 | set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); | |
911 | set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); | |
912 | set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); | |
913 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); | |
914 | set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); | |
915 | set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); | |
916 | set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); | |
917 | ||
918 | /* Conversions between floating types. Table 7. */ | |
919 | set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); | |
920 | set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); | |
921 | ||
c112cf2b | 922 | /* Integer to floating-point conversions. Table 8. */ |
b3f8d95d MM |
923 | set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); |
924 | set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); | |
925 | set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); | |
926 | set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); | |
927 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); | |
928 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); | |
929 | set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); | |
930 | set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); | |
931 | ||
932 | /* Long long. Table 9. */ | |
933 | set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); | |
934 | set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); | |
935 | set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); | |
936 | set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); | |
937 | set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); | |
938 | set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); | |
939 | set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); | |
940 | set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); | |
941 | ||
942 | /* Integer (32/32->32) division. \S 4.3.1. */ | |
943 | set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); | |
944 | set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); | |
945 | ||
946 | /* The divmod functions are designed so that they can be used for | |
947 | plain division, even though they return both the quotient and the | |
948 | remainder. The quotient is returned in the usual location (i.e., | |
949 | r0 for SImode, {r0, r1} for DImode), just as would be expected | |
950 | for an ordinary division routine. Because the AAPCS calling | |
951 | conventions specify that all of { r0, r1, r2, r3 } are | |
952 | callee-saved registers, there is no need to tell the compiler | |
953 | explicitly that those registers are clobbered by these | |
954 | routines. */ | |
955 | set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); | |
956 | set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); | |
e993ba8f DJ |
957 | |
958 | /* For SImode division the ABI provides div-without-mod routines, | |
959 | which are faster. */ | |
960 | set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); | |
961 | set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); | |
01c19d47 PB |
962 | |
963 | /* We don't have mod libcalls. Fortunately gcc knows how to use the | |
964 | divmod libcalls instead. */ | |
965 | set_optab_libfunc (smod_optab, DImode, NULL); | |
966 | set_optab_libfunc (umod_optab, DImode, NULL); | |
967 | set_optab_libfunc (smod_optab, SImode, NULL); | |
968 | set_optab_libfunc (umod_optab, SImode, NULL); | |
0fd8c3ad SL |
969 | |
970 | /* Half-precision float operations. The compiler handles all operations | |
971 | with NULL libfuncs by converting the SFmode. */ | |
972 | switch (arm_fp16_format) | |
973 | { | |
974 | case ARM_FP16_FORMAT_IEEE: | |
975 | case ARM_FP16_FORMAT_ALTERNATIVE: | |
976 | ||
977 | /* Conversions. */ | |
978 | set_conv_libfunc (trunc_optab, HFmode, SFmode, | |
979 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
980 | ? "__gnu_f2h_ieee" | |
981 | : "__gnu_f2h_alternative")); | |
982 | set_conv_libfunc (sext_optab, SFmode, HFmode, | |
983 | (arm_fp16_format == ARM_FP16_FORMAT_IEEE | |
984 | ? "__gnu_h2f_ieee" | |
985 | : "__gnu_h2f_alternative")); | |
986 | ||
987 | /* Arithmetic. */ | |
988 | set_optab_libfunc (add_optab, HFmode, NULL); | |
989 | set_optab_libfunc (sdiv_optab, HFmode, NULL); | |
990 | set_optab_libfunc (smul_optab, HFmode, NULL); | |
991 | set_optab_libfunc (neg_optab, HFmode, NULL); | |
992 | set_optab_libfunc (sub_optab, HFmode, NULL); | |
993 | ||
994 | /* Comparisons. */ | |
995 | set_optab_libfunc (eq_optab, HFmode, NULL); | |
996 | set_optab_libfunc (ne_optab, HFmode, NULL); | |
997 | set_optab_libfunc (lt_optab, HFmode, NULL); | |
998 | set_optab_libfunc (le_optab, HFmode, NULL); | |
999 | set_optab_libfunc (ge_optab, HFmode, NULL); | |
1000 | set_optab_libfunc (gt_optab, HFmode, NULL); | |
1001 | set_optab_libfunc (unord_optab, HFmode, NULL); | |
1002 | break; | |
1003 | ||
1004 | default: | |
1005 | break; | |
1006 | } | |
b3f8d95d MM |
1007 | } |
1008 | ||
07d8efe3 MM |
1009 | /* On AAPCS systems, this is the "struct __va_list". */ |
1010 | static GTY(()) tree va_list_type; | |
1011 | ||
1012 | /* Return the type to use as __builtin_va_list. */ | |
1013 | static tree | |
1014 | arm_build_builtin_va_list (void) | |
1015 | { | |
1016 | tree va_list_name; | |
1017 | tree ap_field; | |
1018 | ||
1019 | if (!TARGET_AAPCS_BASED) | |
1020 | return std_build_builtin_va_list (); | |
1021 | ||
1022 | /* AAPCS \S 7.1.4 requires that va_list be a typedef for a type | |
1023 | defined as: | |
1024 | ||
1025 | struct __va_list | |
1026 | { | |
1027 | void *__ap; | |
1028 | }; | |
1029 | ||
1030 | The C Library ABI further reinforces this definition in \S | |
1031 | 4.1. | |
1032 | ||
1033 | We must follow this definition exactly. The structure tag | |
1034 | name is visible in C++ mangled names, and thus forms a part | |
1035 | of the ABI. The field name may be used by people who | |
1036 | #include <stdarg.h>. */ | |
1037 | /* Create the type. */ | |
1038 | va_list_type = lang_hooks.types.make_type (RECORD_TYPE); | |
1039 | /* Give it the required name. */ | |
4c4bde29 AH |
1040 | va_list_name = build_decl (BUILTINS_LOCATION, |
1041 | TYPE_DECL, | |
07d8efe3 MM |
1042 | get_identifier ("__va_list"), |
1043 | va_list_type); | |
1044 | DECL_ARTIFICIAL (va_list_name) = 1; | |
1045 | TYPE_NAME (va_list_type) = va_list_name; | |
1046 | /* Create the __ap field. */ | |
4c4bde29 AH |
1047 | ap_field = build_decl (BUILTINS_LOCATION, |
1048 | FIELD_DECL, | |
07d8efe3 MM |
1049 | get_identifier ("__ap"), |
1050 | ptr_type_node); | |
1051 | DECL_ARTIFICIAL (ap_field) = 1; | |
1052 | DECL_FIELD_CONTEXT (ap_field) = va_list_type; | |
1053 | TYPE_FIELDS (va_list_type) = ap_field; | |
1054 | /* Compute its layout. */ | |
1055 | layout_type (va_list_type); | |
1056 | ||
1057 | return va_list_type; | |
1058 | } | |
1059 | ||
1060 | /* Return an expression of type "void *" pointing to the next | |
1061 | available argument in a variable-argument list. VALIST is the | |
1062 | user-level va_list object, of type __builtin_va_list. */ | |
1063 | static tree | |
1064 | arm_extract_valist_ptr (tree valist) | |
1065 | { | |
1066 | if (TREE_TYPE (valist) == error_mark_node) | |
1067 | return error_mark_node; | |
1068 | ||
1069 | /* On an AAPCS target, the pointer is stored within "struct | |
1070 | va_list". */ | |
1071 | if (TARGET_AAPCS_BASED) | |
1072 | { | |
1073 | tree ap_field = TYPE_FIELDS (TREE_TYPE (valist)); | |
1074 | valist = build3 (COMPONENT_REF, TREE_TYPE (ap_field), | |
1075 | valist, ap_field, NULL_TREE); | |
1076 | } | |
1077 | ||
1078 | return valist; | |
1079 | } | |
1080 | ||
1081 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ | |
1082 | static void | |
1083 | arm_expand_builtin_va_start (tree valist, rtx nextarg) | |
1084 | { | |
1085 | valist = arm_extract_valist_ptr (valist); | |
1086 | std_expand_builtin_va_start (valist, nextarg); | |
1087 | } | |
1088 | ||
1089 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
1090 | static tree | |
ae46a823 JM |
1091 | arm_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
1092 | gimple_seq *post_p) | |
07d8efe3 MM |
1093 | { |
1094 | valist = arm_extract_valist_ptr (valist); | |
1095 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); | |
1096 | } | |
1097 | ||
c54c7322 RS |
1098 | /* Implement TARGET_HANDLE_OPTION. */ |
1099 | ||
1100 | static bool | |
1101 | arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
1102 | { | |
1103 | switch (code) | |
1104 | { | |
c54c7322 RS |
1105 | case OPT_march_: |
1106 | arm_select[1].string = arg; | |
1107 | return true; | |
1108 | ||
1109 | case OPT_mcpu_: | |
1110 | arm_select[0].string = arg; | |
1111 | return true; | |
1112 | ||
c54c7322 RS |
1113 | case OPT_mhard_float: |
1114 | target_float_abi_name = "hard"; | |
1115 | return true; | |
1116 | ||
c54c7322 RS |
1117 | case OPT_msoft_float: |
1118 | target_float_abi_name = "soft"; | |
1119 | return true; | |
1120 | ||
c54c7322 RS |
1121 | case OPT_mtune_: |
1122 | arm_select[2].string = arg; | |
1123 | return true; | |
1124 | ||
1125 | default: | |
1126 | return true; | |
1127 | } | |
1128 | } | |
1129 | ||
67e6ba46 NC |
1130 | static void |
1131 | arm_target_help (void) | |
1132 | { | |
1133 | int i; | |
1134 | static int columns = 0; | |
1135 | int remaining; | |
1136 | ||
1137 | /* If we have not done so already, obtain the desired maximum width of | |
1138 | the output. Note - this is a duplication of the code at the start of | |
1139 | gcc/opts.c:print_specific_help() - the two copies should probably be | |
1140 | replaced by a single function. */ | |
1141 | if (columns == 0) | |
1142 | { | |
1143 | const char *p; | |
1144 | ||
1145 | GET_ENVIRONMENT (p, "COLUMNS"); | |
1146 | if (p != NULL) | |
1147 | { | |
1148 | int value = atoi (p); | |
1149 | ||
1150 | if (value > 0) | |
1151 | columns = value; | |
1152 | } | |
1153 | ||
1154 | if (columns == 0) | |
1155 | /* Use a reasonable default. */ | |
1156 | columns = 80; | |
1157 | } | |
1158 | ||
1159 | printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"); | |
1160 | ||
1161 | /* The - 2 is because we know that the last entry in the array is NULL. */ | |
1162 | i = ARRAY_SIZE (all_cores) - 2; | |
1163 | gcc_assert (i > 0); | |
1164 | printf (" %s", all_cores[i].name); | |
1165 | remaining = columns - (strlen (all_cores[i].name) + 4); | |
1166 | gcc_assert (remaining >= 0); | |
1167 | ||
1168 | while (i--) | |
1169 | { | |
1170 | int len = strlen (all_cores[i].name); | |
1171 | ||
1172 | if (remaining > len + 2) | |
1173 | { | |
1174 | printf (", %s", all_cores[i].name); | |
1175 | remaining -= len + 2; | |
1176 | } | |
1177 | else | |
1178 | { | |
1179 | if (remaining > 0) | |
1180 | printf (","); | |
1181 | printf ("\n %s", all_cores[i].name); | |
1182 | remaining = columns - (len + 4); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | printf ("\n\n Known ARM architectures (for use with the -march= option):\n"); | |
1187 | ||
1188 | i = ARRAY_SIZE (all_architectures) - 2; | |
1189 | gcc_assert (i > 0); | |
1190 | ||
1191 | printf (" %s", all_architectures[i].name); | |
1192 | remaining = columns - (strlen (all_architectures[i].name) + 4); | |
1193 | gcc_assert (remaining >= 0); | |
1194 | ||
1195 | while (i--) | |
1196 | { | |
1197 | int len = strlen (all_architectures[i].name); | |
1198 | ||
1199 | if (remaining > len + 2) | |
1200 | { | |
1201 | printf (", %s", all_architectures[i].name); | |
1202 | remaining -= len + 2; | |
1203 | } | |
1204 | else | |
1205 | { | |
1206 | if (remaining > 0) | |
1207 | printf (","); | |
1208 | printf ("\n %s", all_architectures[i].name); | |
1209 | remaining = columns - (len + 4); | |
1210 | } | |
1211 | } | |
1212 | printf ("\n"); | |
1213 | ||
1214 | } | |
1215 | ||
2b835d68 RE |
1216 | /* Fix up any incompatible options that the user has specified. |
1217 | This has now turned into a maze. */ | |
1218 | void | |
e32bac5b | 1219 | arm_override_options (void) |
2b835d68 | 1220 | { |
ed4c4348 | 1221 | unsigned i; |
e6fffade | 1222 | enum processor_type target_arch_cpu = arm_none; |
5fd42423 | 1223 | enum processor_type selected_cpu = arm_none; |
9b66ebb1 | 1224 | |
f5a1b0d2 | 1225 | /* Set up the flags based on the cpu/architecture selected by the user. */ |
b6a1cbae | 1226 | for (i = ARRAY_SIZE (arm_select); i--;) |
bd9c7e23 | 1227 | { |
f5a1b0d2 | 1228 | struct arm_cpu_select * ptr = arm_select + i; |
f676971a | 1229 | |
f5a1b0d2 | 1230 | if (ptr->string != NULL && ptr->string[0] != '\0') |
bd9c7e23 | 1231 | { |
13bd191d | 1232 | const struct processors * sel; |
bd9c7e23 | 1233 | |
5895f793 | 1234 | for (sel = ptr->processors; sel->name != NULL; sel++) |
f5a1b0d2 | 1235 | if (streq (ptr->string, sel->name)) |
bd9c7e23 | 1236 | { |
78011587 | 1237 | /* Set the architecture define. */ |
e6fffade | 1238 | if (i != ARM_OPT_SET_TUNE) |
78011587 PB |
1239 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
1240 | ||
9b66ebb1 PB |
1241 | /* Determine the processor core for which we should |
1242 | tune code-generation. */ | |
1243 | if (/* -mcpu= is a sensible default. */ | |
e6fffade | 1244 | i == ARM_OPT_SET_CPU |
9b66ebb1 | 1245 | /* -mtune= overrides -mcpu= and -march=. */ |
e6fffade | 1246 | || i == ARM_OPT_SET_TUNE) |
9b66ebb1 PB |
1247 | arm_tune = (enum processor_type) (sel - ptr->processors); |
1248 | ||
e6fffade RE |
1249 | /* Remember the CPU associated with this architecture. |
1250 | If no other option is used to set the CPU type, | |
1251 | we'll use this to guess the most suitable tuning | |
1252 | options. */ | |
1253 | if (i == ARM_OPT_SET_ARCH) | |
1254 | target_arch_cpu = sel->core; | |
e0b92319 | 1255 | |
5fd42423 PB |
1256 | if (i == ARM_OPT_SET_CPU) |
1257 | selected_cpu = (enum processor_type) (sel - ptr->processors); | |
1258 | ||
e6fffade | 1259 | if (i != ARM_OPT_SET_TUNE) |
b111229a | 1260 | { |
aec3cfba NC |
1261 | /* If we have been given an architecture and a processor |
1262 | make sure that they are compatible. We only generate | |
1263 | a warning though, and we prefer the CPU over the | |
6354dc9b | 1264 | architecture. */ |
aec3cfba | 1265 | if (insn_flags != 0 && (insn_flags ^ sel->flags)) |
d4ee4d25 | 1266 | warning (0, "switch -mcpu=%s conflicts with -march= switch", |
aec3cfba | 1267 | ptr->string); |
f676971a | 1268 | |
aec3cfba | 1269 | insn_flags = sel->flags; |
b111229a | 1270 | } |
f676971a | 1271 | |
bd9c7e23 RE |
1272 | break; |
1273 | } | |
1274 | ||
1275 | if (sel->name == NULL) | |
1276 | error ("bad value (%s) for %s switch", ptr->string, ptr->name); | |
1277 | } | |
1278 | } | |
f676971a | 1279 | |
e6fffade RE |
1280 | /* Guess the tuning options from the architecture if necessary. */ |
1281 | if (arm_tune == arm_none) | |
1282 | arm_tune = target_arch_cpu; | |
1283 | ||
f5a1b0d2 | 1284 | /* If the user did not specify a processor, choose one for them. */ |
aec3cfba | 1285 | if (insn_flags == 0) |
f5a1b0d2 | 1286 | { |
8b60264b | 1287 | const struct processors * sel; |
aec3cfba | 1288 | unsigned int sought; |
aec3cfba | 1289 | |
32e8bb8e | 1290 | selected_cpu = (enum processor_type) TARGET_CPU_DEFAULT; |
5fd42423 | 1291 | if (selected_cpu == arm_none) |
78011587 PB |
1292 | { |
1293 | #ifdef SUBTARGET_CPU_DEFAULT | |
1294 | /* Use the subtarget default CPU if none was specified by | |
1295 | configure. */ | |
32e8bb8e | 1296 | selected_cpu = (enum processor_type) SUBTARGET_CPU_DEFAULT; |
78011587 PB |
1297 | #endif |
1298 | /* Default to ARM6. */ | |
5fd42423 PB |
1299 | if (selected_cpu == arm_none) |
1300 | selected_cpu = arm6; | |
78011587 | 1301 | } |
5fd42423 | 1302 | sel = &all_cores[selected_cpu]; |
aec3cfba NC |
1303 | |
1304 | insn_flags = sel->flags; | |
9b66ebb1 | 1305 | |
aec3cfba NC |
1306 | /* Now check to see if the user has specified some command line |
1307 | switch that require certain abilities from the cpu. */ | |
1308 | sought = 0; | |
f676971a | 1309 | |
d5b7b3ae | 1310 | if (TARGET_INTERWORK || TARGET_THUMB) |
f5a1b0d2 | 1311 | { |
aec3cfba | 1312 | sought |= (FL_THUMB | FL_MODE32); |
f676971a | 1313 | |
d5b7b3ae | 1314 | /* There are no ARM processors that support both APCS-26 and |
aec3cfba NC |
1315 | interworking. Therefore we force FL_MODE26 to be removed |
1316 | from insn_flags here (if it was set), so that the search | |
1317 | below will always be able to find a compatible processor. */ | |
5895f793 | 1318 | insn_flags &= ~FL_MODE26; |
f5a1b0d2 | 1319 | } |
f676971a | 1320 | |
aec3cfba | 1321 | if (sought != 0 && ((sought & insn_flags) != sought)) |
f5a1b0d2 | 1322 | { |
aec3cfba NC |
1323 | /* Try to locate a CPU type that supports all of the abilities |
1324 | of the default CPU, plus the extra abilities requested by | |
1325 | the user. */ | |
5895f793 | 1326 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba | 1327 | if ((sel->flags & sought) == (sought | insn_flags)) |
f5a1b0d2 NC |
1328 | break; |
1329 | ||
1330 | if (sel->name == NULL) | |
aec3cfba | 1331 | { |
0977774b | 1332 | unsigned current_bit_count = 0; |
8b60264b | 1333 | const struct processors * best_fit = NULL; |
f676971a | 1334 | |
aec3cfba NC |
1335 | /* Ideally we would like to issue an error message here |
1336 | saying that it was not possible to find a CPU compatible | |
1337 | with the default CPU, but which also supports the command | |
1338 | line options specified by the programmer, and so they | |
1339 | ought to use the -mcpu=<name> command line option to | |
1340 | override the default CPU type. | |
1341 | ||
61f0ccff RE |
1342 | If we cannot find a cpu that has both the |
1343 | characteristics of the default cpu and the given | |
1344 | command line options we scan the array again looking | |
1345 | for a best match. */ | |
5895f793 | 1346 | for (sel = all_cores; sel->name != NULL; sel++) |
aec3cfba NC |
1347 | if ((sel->flags & sought) == sought) |
1348 | { | |
0977774b | 1349 | unsigned count; |
aec3cfba NC |
1350 | |
1351 | count = bit_count (sel->flags & insn_flags); | |
1352 | ||
1353 | if (count >= current_bit_count) | |
1354 | { | |
1355 | best_fit = sel; | |
1356 | current_bit_count = count; | |
1357 | } | |
1358 | } | |
f5a1b0d2 | 1359 | |
e6d29d15 NS |
1360 | gcc_assert (best_fit); |
1361 | sel = best_fit; | |
aec3cfba NC |
1362 | } |
1363 | ||
1364 | insn_flags = sel->flags; | |
f5a1b0d2 | 1365 | } |
78011587 | 1366 | sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); |
6c6aa1af | 1367 | arm_default_cpu = (enum processor_type) (sel - all_cores); |
9b66ebb1 | 1368 | if (arm_tune == arm_none) |
6c6aa1af | 1369 | arm_tune = arm_default_cpu; |
f5a1b0d2 | 1370 | } |
f676971a | 1371 | |
9b66ebb1 PB |
1372 | /* The processor for which we should tune should now have been |
1373 | chosen. */ | |
e6d29d15 | 1374 | gcc_assert (arm_tune != arm_none); |
f676971a | 1375 | |
9b66ebb1 | 1376 | tune_flags = all_cores[(int)arm_tune].flags; |
e26053d1 | 1377 | |
0fd8c3ad SL |
1378 | if (target_fp16_format_name) |
1379 | { | |
1380 | for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++) | |
1381 | { | |
1382 | if (streq (all_fp16_formats[i].name, target_fp16_format_name)) | |
1383 | { | |
1384 | arm_fp16_format = all_fp16_formats[i].fp16_format_type; | |
1385 | break; | |
1386 | } | |
1387 | } | |
1388 | if (i == ARRAY_SIZE (all_fp16_formats)) | |
1389 | error ("invalid __fp16 format option: -mfp16-format=%s", | |
1390 | target_fp16_format_name); | |
1391 | } | |
1392 | else | |
1393 | arm_fp16_format = ARM_FP16_FORMAT_NONE; | |
1394 | ||
26272ba2 PB |
1395 | if (target_abi_name) |
1396 | { | |
1397 | for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) | |
1398 | { | |
1399 | if (streq (arm_all_abis[i].name, target_abi_name)) | |
1400 | { | |
1401 | arm_abi = arm_all_abis[i].abi_type; | |
1402 | break; | |
1403 | } | |
1404 | } | |
1405 | if (i == ARRAY_SIZE (arm_all_abis)) | |
1406 | error ("invalid ABI option: -mabi=%s", target_abi_name); | |
1407 | } | |
1408 | else | |
1409 | arm_abi = ARM_DEFAULT_ABI; | |
1410 | ||
f5a1b0d2 NC |
1411 | /* Make sure that the processor choice does not conflict with any of the |
1412 | other command line choices. */ | |
5b3e6663 PB |
1413 | if (TARGET_ARM && !(insn_flags & FL_NOTM)) |
1414 | error ("target CPU does not support ARM mode"); | |
1415 | ||
26272ba2 PB |
1416 | /* BPABI targets use linker tricks to allow interworking on cores |
1417 | without thumb support. */ | |
1418 | if (TARGET_INTERWORK && !((insn_flags & FL_THUMB) || TARGET_BPABI)) | |
f5a1b0d2 | 1419 | { |
d4ee4d25 | 1420 | warning (0, "target CPU does not support interworking" ); |
c54c7322 | 1421 | target_flags &= ~MASK_INTERWORK; |
f5a1b0d2 | 1422 | } |
f676971a | 1423 | |
d5b7b3ae RE |
1424 | if (TARGET_THUMB && !(insn_flags & FL_THUMB)) |
1425 | { | |
d4ee4d25 | 1426 | warning (0, "target CPU does not support THUMB instructions"); |
c54c7322 | 1427 | target_flags &= ~MASK_THUMB; |
d5b7b3ae RE |
1428 | } |
1429 | ||
1430 | if (TARGET_APCS_FRAME && TARGET_THUMB) | |
1431 | { | |
d4ee4d25 | 1432 | /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ |
c54c7322 | 1433 | target_flags &= ~MASK_APCS_FRAME; |
d5b7b3ae | 1434 | } |
d19fb8e3 | 1435 | |
da8ce8be RE |
1436 | /* Callee super interworking implies thumb interworking. Adding |
1437 | this to the flags here simplifies the logic elsewhere. */ | |
1438 | if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) | |
1439 | target_flags |= MASK_INTERWORK; | |
1440 | ||
d5b7b3ae RE |
1441 | /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done |
1442 | from here where no function is being compiled currently. */ | |
c54c7322 | 1443 | if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) |
d4ee4d25 | 1444 | warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1445 | |
1446 | if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) | |
d4ee4d25 | 1447 | warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae RE |
1448 | |
1449 | if (TARGET_ARM && TARGET_CALLER_INTERWORKING) | |
d4ee4d25 | 1450 | warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); |
d5b7b3ae | 1451 | |
5895f793 | 1452 | if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) |
f5a1b0d2 | 1453 | { |
d4ee4d25 | 1454 | warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); |
c54c7322 | 1455 | target_flags |= MASK_APCS_FRAME; |
f5a1b0d2 | 1456 | } |
f676971a | 1457 | |
2b835d68 | 1458 | if (TARGET_POKE_FUNCTION_NAME) |
c54c7322 | 1459 | target_flags |= MASK_APCS_FRAME; |
f676971a | 1460 | |
2b835d68 | 1461 | if (TARGET_APCS_REENT && flag_pic) |
400500c4 | 1462 | error ("-fpic and -mapcs-reent are incompatible"); |
f676971a | 1463 | |
2b835d68 | 1464 | if (TARGET_APCS_REENT) |
d4ee4d25 | 1465 | warning (0, "APCS reentrant code not supported. Ignored"); |
f676971a | 1466 | |
d5b7b3ae RE |
1467 | /* If this target is normally configured to use APCS frames, warn if they |
1468 | are turned off and debugging is turned on. */ | |
1469 | if (TARGET_ARM | |
1470 | && write_symbols != NO_DEBUG | |
5895f793 | 1471 | && !TARGET_APCS_FRAME |
c54c7322 | 1472 | && (TARGET_DEFAULT & MASK_APCS_FRAME)) |
d4ee4d25 | 1473 | warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); |
f676971a | 1474 | |
2b835d68 | 1475 | if (TARGET_APCS_FLOAT) |
d4ee4d25 | 1476 | warning (0, "passing floating point arguments in fp regs not yet supported"); |
f676971a | 1477 | |
4912a07c | 1478 | /* Initialize boolean versions of the flags, for use in the arm.md file. */ |
9b66ebb1 PB |
1479 | arm_arch3m = (insn_flags & FL_ARCH3M) != 0; |
1480 | arm_arch4 = (insn_flags & FL_ARCH4) != 0; | |
68d560d4 | 1481 | arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); |
9b66ebb1 PB |
1482 | arm_arch5 = (insn_flags & FL_ARCH5) != 0; |
1483 | arm_arch5e = (insn_flags & FL_ARCH5E) != 0; | |
1484 | arm_arch6 = (insn_flags & FL_ARCH6) != 0; | |
d3585b76 | 1485 | arm_arch6k = (insn_flags & FL_ARCH6K) != 0; |
5b3e6663 PB |
1486 | arm_arch_notm = (insn_flags & FL_NOTM) != 0; |
1487 | arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; | |
9b66ebb1 | 1488 | arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; |
78011587 | 1489 | arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; |
9b66ebb1 PB |
1490 | |
1491 | arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; | |
abac3b49 | 1492 | arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; |
9b66ebb1 | 1493 | thumb_code = (TARGET_ARM == 0); |
abac3b49 | 1494 | arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; |
9b66ebb1 PB |
1495 | arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; |
1496 | arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; | |
5b3e6663 | 1497 | arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; |
7612f14d | 1498 | arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; |
5a9335ef | 1499 | |
f67358da PB |
1500 | /* If we are not using the default (ARM mode) section anchor offset |
1501 | ranges, then set the correct ranges now. */ | |
1502 | if (TARGET_THUMB1) | |
1503 | { | |
1504 | /* Thumb-1 LDR instructions cannot have negative offsets. | |
1505 | Permissible positive offset ranges are 5-bit (for byte loads), | |
1506 | 6-bit (for halfword loads), or 7-bit (for word loads). | |
1507 | Empirical results suggest a 7-bit anchor range gives the best | |
1508 | overall code size. */ | |
1509 | targetm.min_anchor_offset = 0; | |
1510 | targetm.max_anchor_offset = 127; | |
1511 | } | |
1512 | else if (TARGET_THUMB2) | |
1513 | { | |
1514 | /* The minimum is set such that the total size of the block | |
1515 | for a particular anchor is 248 + 1 + 4095 bytes, which is | |
1516 | divisible by eight, ensuring natural spacing of anchors. */ | |
1517 | targetm.min_anchor_offset = -248; | |
1518 | targetm.max_anchor_offset = 4095; | |
1519 | } | |
1520 | ||
68d560d4 RE |
1521 | /* V5 code we generate is completely interworking capable, so we turn off |
1522 | TARGET_INTERWORK here to avoid many tests later on. */ | |
2ad4dcf9 RE |
1523 | |
1524 | /* XXX However, we must pass the right pre-processor defines to CPP | |
1525 | or GLD can get confused. This is a hack. */ | |
1526 | if (TARGET_INTERWORK) | |
1527 | arm_cpp_interwork = 1; | |
1528 | ||
68d560d4 | 1529 | if (arm_arch5) |
c54c7322 | 1530 | target_flags &= ~MASK_INTERWORK; |
68d560d4 | 1531 | |
5848830f PB |
1532 | if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) |
1533 | error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); | |
1534 | ||
1535 | if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) | |
1536 | error ("iwmmxt abi requires an iwmmxt capable cpu"); | |
6f7ebcbb | 1537 | |
9b66ebb1 PB |
1538 | arm_fp_model = ARM_FP_MODEL_UNKNOWN; |
1539 | if (target_fpu_name == NULL && target_fpe_name != NULL) | |
9b6b54e2 | 1540 | { |
9b66ebb1 PB |
1541 | if (streq (target_fpe_name, "2")) |
1542 | target_fpu_name = "fpe2"; | |
1543 | else if (streq (target_fpe_name, "3")) | |
1544 | target_fpu_name = "fpe3"; | |
1545 | else | |
1546 | error ("invalid floating point emulation option: -mfpe=%s", | |
1547 | target_fpe_name); | |
1548 | } | |
1549 | if (target_fpu_name != NULL) | |
1550 | { | |
1551 | /* The user specified a FPU. */ | |
1552 | for (i = 0; i < ARRAY_SIZE (all_fpus); i++) | |
1553 | { | |
1554 | if (streq (all_fpus[i].name, target_fpu_name)) | |
1555 | { | |
1556 | arm_fpu_arch = all_fpus[i].fpu; | |
1557 | arm_fpu_tune = arm_fpu_arch; | |
1558 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
1559 | break; | |
1560 | } | |
1561 | } | |
1562 | if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) | |
1563 | error ("invalid floating point option: -mfpu=%s", target_fpu_name); | |
9b6b54e2 NC |
1564 | } |
1565 | else | |
2b835d68 | 1566 | { |
9b66ebb1 | 1567 | #ifdef FPUTYPE_DEFAULT |
78011587 | 1568 | /* Use the default if it is specified for this platform. */ |
9b66ebb1 PB |
1569 | arm_fpu_arch = FPUTYPE_DEFAULT; |
1570 | arm_fpu_tune = FPUTYPE_DEFAULT; | |
1571 | #else | |
1572 | /* Pick one based on CPU type. */ | |
78011587 | 1573 | /* ??? Some targets assume FPA is the default. |
9b66ebb1 PB |
1574 | if ((insn_flags & FL_VFP) != 0) |
1575 | arm_fpu_arch = FPUTYPE_VFP; | |
78011587 PB |
1576 | else |
1577 | */ | |
1578 | if (arm_arch_cirrus) | |
9b66ebb1 PB |
1579 | arm_fpu_arch = FPUTYPE_MAVERICK; |
1580 | else | |
29ad9694 | 1581 | arm_fpu_arch = FPUTYPE_FPA_EMU2; |
9b66ebb1 PB |
1582 | #endif |
1583 | if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
1584 | arm_fpu_tune = FPUTYPE_FPA; | |
2b835d68 | 1585 | else |
9b66ebb1 PB |
1586 | arm_fpu_tune = arm_fpu_arch; |
1587 | arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; | |
e6d29d15 | 1588 | gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); |
9b66ebb1 PB |
1589 | } |
1590 | ||
1591 | if (target_float_abi_name != NULL) | |
1592 | { | |
1593 | /* The user specified a FP ABI. */ | |
1594 | for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) | |
1595 | { | |
1596 | if (streq (all_float_abis[i].name, target_float_abi_name)) | |
1597 | { | |
1598 | arm_float_abi = all_float_abis[i].abi_type; | |
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | if (i == ARRAY_SIZE (all_float_abis)) | |
1603 | error ("invalid floating point abi: -mfloat-abi=%s", | |
1604 | target_float_abi_name); | |
2b835d68 | 1605 | } |
3d8532aa PB |
1606 | else |
1607 | arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; | |
9b66ebb1 | 1608 | |
72cdc543 PB |
1609 | if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) |
1610 | sorry ("-mfloat-abi=hard and VFP"); | |
1611 | ||
0c48a567 RR |
1612 | if (TARGET_AAPCS_BASED |
1613 | && (arm_fp_model == ARM_FP_MODEL_FPA)) | |
1614 | error ("FPA is unsupported in the AAPCS"); | |
1615 | ||
3ce14752 RR |
1616 | if (TARGET_AAPCS_BASED) |
1617 | if (TARGET_CALLER_INTERWORKING) | |
1618 | error ("AAPCS doesn't support -mcaller-super-interworking"); | |
1619 | else | |
1620 | if (TARGET_CALLEE_INTERWORKING) | |
1621 | error ("AAPCS doesn't support -mcallee-super-interworking"); | |
1622 | ||
1623 | ||
87b24aaf PB |
1624 | /* FPA and iWMMXt are incompatible because the insn encodings overlap. |
1625 | VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon | |
1626 | will ever exist. GCC makes no attempt to support this combination. */ | |
1627 | if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) | |
1628 | sorry ("iWMMXt and hardware floating point"); | |
1629 | ||
5b3e6663 PB |
1630 | /* ??? iWMMXt insn patterns need auditing for Thumb-2. */ |
1631 | if (TARGET_THUMB2 && TARGET_IWMMXT) | |
1632 | sorry ("Thumb-2 iWMMXt"); | |
1633 | ||
0fd8c3ad SL |
1634 | /* __fp16 support currently assumes the core has ldrh. */ |
1635 | if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) | |
1636 | sorry ("__fp16 and no ldrh"); | |
1637 | ||
9b66ebb1 PB |
1638 | /* If soft-float is specified then don't use FPU. */ |
1639 | if (TARGET_SOFT_FLOAT) | |
1640 | arm_fpu_arch = FPUTYPE_NONE; | |
f676971a | 1641 | |
f5a1b0d2 NC |
1642 | /* For arm2/3 there is no need to do any scheduling if there is only |
1643 | a floating point emulator, or we are doing software floating-point. */ | |
9b66ebb1 PB |
1644 | if ((TARGET_SOFT_FLOAT |
1645 | || arm_fpu_tune == FPUTYPE_FPA_EMU2 | |
1646 | || arm_fpu_tune == FPUTYPE_FPA_EMU3) | |
ed0e6530 | 1647 | && (tune_flags & FL_MODE32) == 0) |
f5a1b0d2 | 1648 | flag_schedule_insns = flag_schedule_insns_after_reload = 0; |
f676971a | 1649 | |
d3585b76 DJ |
1650 | if (target_thread_switch) |
1651 | { | |
1652 | if (strcmp (target_thread_switch, "soft") == 0) | |
1653 | target_thread_pointer = TP_SOFT; | |
1654 | else if (strcmp (target_thread_switch, "auto") == 0) | |
1655 | target_thread_pointer = TP_AUTO; | |
1656 | else if (strcmp (target_thread_switch, "cp15") == 0) | |
1657 | target_thread_pointer = TP_CP15; | |
1658 | else | |
1659 | error ("invalid thread pointer option: -mtp=%s", target_thread_switch); | |
1660 | } | |
1661 | ||
1662 | /* Use the cp15 method if it is available. */ | |
1663 | if (target_thread_pointer == TP_AUTO) | |
1664 | { | |
1665 | if (arm_arch6k && !TARGET_THUMB) | |
1666 | target_thread_pointer = TP_CP15; | |
1667 | else | |
1668 | target_thread_pointer = TP_SOFT; | |
1669 | } | |
1670 | ||
5b3e6663 PB |
1671 | if (TARGET_HARD_TP && TARGET_THUMB1) |
1672 | error ("can not use -mtp=cp15 with 16-bit Thumb"); | |
d3585b76 | 1673 | |
5848830f | 1674 | /* Override the default structure alignment for AAPCS ABI. */ |
077fc835 | 1675 | if (TARGET_AAPCS_BASED) |
5848830f PB |
1676 | arm_structure_size_boundary = 8; |
1677 | ||
b355a481 NC |
1678 | if (structure_size_string != NULL) |
1679 | { | |
1680 | int size = strtol (structure_size_string, NULL, 0); | |
5848830f PB |
1681 | |
1682 | if (size == 8 || size == 32 | |
1683 | || (ARM_DOUBLEWORD_ALIGN && size == 64)) | |
b355a481 NC |
1684 | arm_structure_size_boundary = size; |
1685 | else | |
d4ee4d25 | 1686 | warning (0, "structure size boundary can only be set to %s", |
5848830f | 1687 | ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); |
b355a481 | 1688 | } |
ed0e6530 | 1689 | |
9403b7f7 RS |
1690 | if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic) |
1691 | { | |
1692 | error ("RTP PIC is incompatible with Thumb"); | |
1693 | flag_pic = 0; | |
1694 | } | |
1695 | ||
c147eacb PB |
1696 | /* If stack checking is disabled, we can use r10 as the PIC register, |
1697 | which keeps r9 available. The EABI specifies r9 as the PIC register. */ | |
1698 | if (flag_pic && TARGET_SINGLE_PIC_BASE) | |
9403b7f7 RS |
1699 | { |
1700 | if (TARGET_VXWORKS_RTP) | |
1701 | warning (0, "RTP PIC is incompatible with -msingle-pic-base"); | |
1702 | arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10; | |
1703 | } | |
1704 | ||
1705 | if (flag_pic && TARGET_VXWORKS_RTP) | |
1706 | arm_pic_register = 9; | |
c147eacb | 1707 | |
ed0e6530 PB |
1708 | if (arm_pic_register_string != NULL) |
1709 | { | |
5b43fed1 | 1710 | int pic_register = decode_reg_name (arm_pic_register_string); |
e26053d1 | 1711 | |
5895f793 | 1712 | if (!flag_pic) |
d4ee4d25 | 1713 | warning (0, "-mpic-register= is useless without -fpic"); |
ed0e6530 | 1714 | |
ed0e6530 | 1715 | /* Prevent the user from choosing an obviously stupid PIC register. */ |
5b43fed1 RH |
1716 | else if (pic_register < 0 || call_used_regs[pic_register] |
1717 | || pic_register == HARD_FRAME_POINTER_REGNUM | |
1718 | || pic_register == STACK_POINTER_REGNUM | |
9403b7f7 RS |
1719 | || pic_register >= PC_REGNUM |
1720 | || (TARGET_VXWORKS_RTP | |
1721 | && (unsigned int) pic_register != arm_pic_register)) | |
c725bd79 | 1722 | error ("unable to use '%s' for PIC register", arm_pic_register_string); |
ed0e6530 PB |
1723 | else |
1724 | arm_pic_register = pic_register; | |
1725 | } | |
d5b7b3ae | 1726 | |
5fd42423 PB |
1727 | /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ |
1728 | if (fix_cm3_ldrd == 2) | |
1729 | { | |
1730 | if (selected_cpu == cortexm3) | |
1731 | fix_cm3_ldrd = 1; | |
1732 | else | |
1733 | fix_cm3_ldrd = 0; | |
1734 | } | |
1735 | ||
5b3e6663 | 1736 | /* ??? We might want scheduling for thumb2. */ |
d5b7b3ae RE |
1737 | if (TARGET_THUMB && flag_schedule_insns) |
1738 | { | |
1739 | /* Don't warn since it's on by default in -O2. */ | |
1740 | flag_schedule_insns = 0; | |
1741 | } | |
1742 | ||
f5a1b0d2 | 1743 | if (optimize_size) |
be03ccc9 | 1744 | { |
577d6328 | 1745 | arm_constant_limit = 1; |
be03ccc9 NP |
1746 | |
1747 | /* If optimizing for size, bump the number of instructions that we | |
d6b4baa4 | 1748 | are prepared to conditionally execute (even on a StrongARM). */ |
be03ccc9 NP |
1749 | max_insns_skipped = 6; |
1750 | } | |
1751 | else | |
1752 | { | |
1753 | /* For processors with load scheduling, it never costs more than | |
1754 | 2 cycles to load a constant, and the load scheduler may well | |
1755 | reduce that to 1. */ | |
2075b05d | 1756 | if (arm_ld_sched) |
be03ccc9 NP |
1757 | arm_constant_limit = 1; |
1758 | ||
1759 | /* On XScale the longer latency of a load makes it more difficult | |
1760 | to achieve a good schedule, so it's faster to synthesize | |
d6b4baa4 | 1761 | constants that can be done in two insns. */ |
be03ccc9 NP |
1762 | if (arm_tune_xscale) |
1763 | arm_constant_limit = 2; | |
1764 | ||
1765 | /* StrongARM has early execution of branches, so a sequence | |
1766 | that is worth skipping is shorter. */ | |
abac3b49 | 1767 | if (arm_tune_strongarm) |
be03ccc9 NP |
1768 | max_insns_skipped = 3; |
1769 | } | |
92a432f4 RE |
1770 | |
1771 | /* Register global variables with the garbage collector. */ | |
1772 | arm_add_gc_roots (); | |
1773 | } | |
1774 | ||
1775 | static void | |
e32bac5b | 1776 | arm_add_gc_roots (void) |
92a432f4 | 1777 | { |
c7319d87 RE |
1778 | gcc_obstack_init(&minipool_obstack); |
1779 | minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); | |
2b835d68 | 1780 | } |
cce8749e | 1781 | \f |
6d3d9133 NC |
1782 | /* A table of known ARM exception types. |
1783 | For use with the interrupt function attribute. */ | |
1784 | ||
1785 | typedef struct | |
1786 | { | |
8b60264b KG |
1787 | const char *const arg; |
1788 | const unsigned long return_value; | |
6d3d9133 NC |
1789 | } |
1790 | isr_attribute_arg; | |
1791 | ||
8b60264b | 1792 | static const isr_attribute_arg isr_attribute_args [] = |
6d3d9133 NC |
1793 | { |
1794 | { "IRQ", ARM_FT_ISR }, | |
1795 | { "irq", ARM_FT_ISR }, | |
1796 | { "FIQ", ARM_FT_FIQ }, | |
1797 | { "fiq", ARM_FT_FIQ }, | |
1798 | { "ABORT", ARM_FT_ISR }, | |
1799 | { "abort", ARM_FT_ISR }, | |
1800 | { "ABORT", ARM_FT_ISR }, | |
1801 | { "abort", ARM_FT_ISR }, | |
1802 | { "UNDEF", ARM_FT_EXCEPTION }, | |
1803 | { "undef", ARM_FT_EXCEPTION }, | |
1804 | { "SWI", ARM_FT_EXCEPTION }, | |
1805 | { "swi", ARM_FT_EXCEPTION }, | |
1806 | { NULL, ARM_FT_NORMAL } | |
1807 | }; | |
1808 | ||
1809 | /* Returns the (interrupt) function type of the current | |
1810 | function, or ARM_FT_UNKNOWN if the type cannot be determined. */ | |
1811 | ||
1812 | static unsigned long | |
e32bac5b | 1813 | arm_isr_value (tree argument) |
6d3d9133 | 1814 | { |
8b60264b | 1815 | const isr_attribute_arg * ptr; |
1d6e90ac | 1816 | const char * arg; |
6d3d9133 | 1817 | |
5b3e6663 PB |
1818 | if (!arm_arch_notm) |
1819 | return ARM_FT_NORMAL | ARM_FT_STACKALIGN; | |
1820 | ||
6d3d9133 NC |
1821 | /* No argument - default to IRQ. */ |
1822 | if (argument == NULL_TREE) | |
1823 | return ARM_FT_ISR; | |
1824 | ||
1825 | /* Get the value of the argument. */ | |
1826 | if (TREE_VALUE (argument) == NULL_TREE | |
1827 | || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) | |
1828 | return ARM_FT_UNKNOWN; | |
1829 | ||
1830 | arg = TREE_STRING_POINTER (TREE_VALUE (argument)); | |
1831 | ||
1832 | /* Check it against the list of known arguments. */ | |
5a9335ef | 1833 | for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) |
1d6e90ac NC |
1834 | if (streq (arg, ptr->arg)) |
1835 | return ptr->return_value; | |
6d3d9133 | 1836 | |
05713b80 | 1837 | /* An unrecognized interrupt type. */ |
6d3d9133 NC |
1838 | return ARM_FT_UNKNOWN; |
1839 | } | |
1840 | ||
1841 | /* Computes the type of the current function. */ | |
1842 | ||
1843 | static unsigned long | |
e32bac5b | 1844 | arm_compute_func_type (void) |
6d3d9133 NC |
1845 | { |
1846 | unsigned long type = ARM_FT_UNKNOWN; | |
1847 | tree a; | |
1848 | tree attr; | |
f676971a | 1849 | |
e6d29d15 | 1850 | gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); |
6d3d9133 NC |
1851 | |
1852 | /* Decide if the current function is volatile. Such functions | |
1853 | never return, and many memory cycles can be saved by not storing | |
1854 | register values that will never be needed again. This optimization | |
1855 | was added to speed up context switching in a kernel application. */ | |
1856 | if (optimize > 0 | |
cf1955dc PB |
1857 | && (TREE_NOTHROW (current_function_decl) |
1858 | || !(flag_unwind_tables | |
1859 | || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) | |
6d3d9133 NC |
1860 | && TREE_THIS_VOLATILE (current_function_decl)) |
1861 | type |= ARM_FT_VOLATILE; | |
f676971a | 1862 | |
6de9cd9a | 1863 | if (cfun->static_chain_decl != NULL) |
6d3d9133 NC |
1864 | type |= ARM_FT_NESTED; |
1865 | ||
91d231cb | 1866 | attr = DECL_ATTRIBUTES (current_function_decl); |
f676971a | 1867 | |
6d3d9133 NC |
1868 | a = lookup_attribute ("naked", attr); |
1869 | if (a != NULL_TREE) | |
1870 | type |= ARM_FT_NAKED; | |
1871 | ||
c9ca9b88 PB |
1872 | a = lookup_attribute ("isr", attr); |
1873 | if (a == NULL_TREE) | |
1874 | a = lookup_attribute ("interrupt", attr); | |
f676971a | 1875 | |
c9ca9b88 PB |
1876 | if (a == NULL_TREE) |
1877 | type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; | |
6d3d9133 | 1878 | else |
c9ca9b88 | 1879 | type |= arm_isr_value (TREE_VALUE (a)); |
f676971a | 1880 | |
6d3d9133 NC |
1881 | return type; |
1882 | } | |
1883 | ||
1884 | /* Returns the type of the current function. */ | |
1885 | ||
1886 | unsigned long | |
e32bac5b | 1887 | arm_current_func_type (void) |
6d3d9133 NC |
1888 | { |
1889 | if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) | |
1890 | cfun->machine->func_type = arm_compute_func_type (); | |
1891 | ||
1892 | return cfun->machine->func_type; | |
1893 | } | |
007e61c2 PB |
1894 | |
1895 | bool | |
1896 | arm_allocate_stack_slots_for_args (void) | |
1897 | { | |
1898 | /* Naked functions should not allocate stack slots for arguments. */ | |
1899 | return !IS_NAKED (arm_current_func_type ()); | |
1900 | } | |
1901 | ||
6d3d9133 | 1902 | \f |
f676971a | 1903 | /* Return 1 if it is possible to return using a single instruction. |
a72d4945 RE |
1904 | If SIBLING is non-null, this is a test for a return before a sibling |
1905 | call. SIBLING is the call insn, so we can examine its register usage. */ | |
6d3d9133 | 1906 | |
ff9940b0 | 1907 | int |
a72d4945 | 1908 | use_return_insn (int iscond, rtx sibling) |
ff9940b0 RE |
1909 | { |
1910 | int regno; | |
9b598fa0 | 1911 | unsigned int func_type; |
d5db54a1 | 1912 | unsigned long saved_int_regs; |
a72d4945 | 1913 | unsigned HOST_WIDE_INT stack_adjust; |
5848830f | 1914 | arm_stack_offsets *offsets; |
ff9940b0 | 1915 | |
d5b7b3ae | 1916 | /* Never use a return instruction before reload has run. */ |
6d3d9133 NC |
1917 | if (!reload_completed) |
1918 | return 0; | |
efc2515b | 1919 | |
9b598fa0 RE |
1920 | func_type = arm_current_func_type (); |
1921 | ||
5b3e6663 | 1922 | /* Naked, volatile and stack alignment functions need special |
3a7731fd | 1923 | consideration. */ |
5b3e6663 | 1924 | if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN)) |
6d3d9133 | 1925 | return 0; |
06bea5aa | 1926 | |
a15908a4 PB |
1927 | /* So do interrupt functions that use the frame pointer and Thumb |
1928 | interrupt functions. */ | |
1929 | if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB)) | |
06bea5aa | 1930 | return 0; |
a72d4945 | 1931 | |
5848830f PB |
1932 | offsets = arm_get_frame_offsets (); |
1933 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; | |
a72d4945 | 1934 | |
6d3d9133 | 1935 | /* As do variadic functions. */ |
38173d38 | 1936 | if (crtl->args.pretend_args_size |
3cb66fd7 | 1937 | || cfun->machine->uses_anonymous_args |
699a4925 | 1938 | /* Or if the function calls __builtin_eh_return () */ |
e3b5732b | 1939 | || crtl->calls_eh_return |
699a4925 | 1940 | /* Or if the function calls alloca */ |
e3b5732b | 1941 | || cfun->calls_alloca |
a72d4945 RE |
1942 | /* Or if there is a stack adjustment. However, if the stack pointer |
1943 | is saved on the stack, we can use a pre-incrementing stack load. */ | |
ec6237e4 PB |
1944 | || !(stack_adjust == 0 || (TARGET_APCS_FRAME && frame_pointer_needed |
1945 | && stack_adjust == 4))) | |
ff9940b0 RE |
1946 | return 0; |
1947 | ||
954954d1 | 1948 | saved_int_regs = offsets->saved_regs_mask; |
d5db54a1 | 1949 | |
a72d4945 RE |
1950 | /* Unfortunately, the insn |
1951 | ||
1952 | ldmib sp, {..., sp, ...} | |
1953 | ||
1954 | triggers a bug on most SA-110 based devices, such that the stack | |
1955 | pointer won't be correctly restored if the instruction takes a | |
839a4992 | 1956 | page fault. We work around this problem by popping r3 along with |
a72d4945 | 1957 | the other registers, since that is never slower than executing |
f676971a | 1958 | another instruction. |
a72d4945 RE |
1959 | |
1960 | We test for !arm_arch5 here, because code for any architecture | |
1961 | less than this could potentially be run on one of the buggy | |
1962 | chips. */ | |
5b3e6663 | 1963 | if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM) |
a72d4945 RE |
1964 | { |
1965 | /* Validate that r3 is a call-clobbered register (always true in | |
d6b4baa4 | 1966 | the default abi) ... */ |
a72d4945 RE |
1967 | if (!call_used_regs[3]) |
1968 | return 0; | |
1969 | ||
4f5dfed0 JC |
1970 | /* ... that it isn't being used for a return value ... */ |
1971 | if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) | |
1972 | return 0; | |
1973 | ||
1974 | /* ... or for a tail-call argument ... */ | |
a72d4945 RE |
1975 | if (sibling) |
1976 | { | |
e6d29d15 | 1977 | gcc_assert (GET_CODE (sibling) == CALL_INSN); |
a72d4945 RE |
1978 | |
1979 | if (find_regno_fusage (sibling, USE, 3)) | |
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | /* ... and that there are no call-saved registers in r0-r2 | |
1984 | (always true in the default ABI). */ | |
1985 | if (saved_int_regs & 0x7) | |
1986 | return 0; | |
1987 | } | |
1988 | ||
b111229a | 1989 | /* Can't be done if interworking with Thumb, and any registers have been |
d5db54a1 | 1990 | stacked. */ |
a15908a4 | 1991 | if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type)) |
b36ba79f | 1992 | return 0; |
d5db54a1 RE |
1993 | |
1994 | /* On StrongARM, conditional returns are expensive if they aren't | |
1995 | taken and multiple registers have been stacked. */ | |
abac3b49 | 1996 | if (iscond && arm_tune_strongarm) |
6ed30148 | 1997 | { |
f676971a | 1998 | /* Conditional return when just the LR is stored is a simple |
d5db54a1 RE |
1999 | conditional-load instruction, that's not expensive. */ |
2000 | if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) | |
2001 | return 0; | |
6ed30148 | 2002 | |
020a4035 RE |
2003 | if (flag_pic |
2004 | && arm_pic_register != INVALID_REGNUM | |
6fb5fa3c | 2005 | && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
b111229a | 2006 | return 0; |
6ed30148 | 2007 | } |
d5db54a1 RE |
2008 | |
2009 | /* If there are saved registers but the LR isn't saved, then we need | |
2010 | two instructions for the return. */ | |
2011 | if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) | |
2012 | return 0; | |
2013 | ||
3b684012 | 2014 | /* Can't be done if any of the FPA regs are pushed, |
6d3d9133 | 2015 | since this also requires an insn. */ |
9b66ebb1 PB |
2016 | if (TARGET_HARD_FLOAT && TARGET_FPA) |
2017 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 2018 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
9b66ebb1 PB |
2019 | return 0; |
2020 | ||
2021 | /* Likewise VFP regs. */ | |
2022 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
2023 | for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) | |
6fb5fa3c | 2024 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
d5b7b3ae | 2025 | return 0; |
ff9940b0 | 2026 | |
5a9335ef NC |
2027 | if (TARGET_REALLY_IWMMXT) |
2028 | for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) | |
6fb5fa3c | 2029 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5a9335ef NC |
2030 | return 0; |
2031 | ||
ff9940b0 RE |
2032 | return 1; |
2033 | } | |
2034 | ||
cce8749e CH |
2035 | /* Return TRUE if int I is a valid immediate ARM constant. */ |
2036 | ||
2037 | int | |
e32bac5b | 2038 | const_ok_for_arm (HOST_WIDE_INT i) |
cce8749e | 2039 | { |
4642ccb1 | 2040 | int lowbit; |
e0b92319 | 2041 | |
f676971a | 2042 | /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must |
56636818 | 2043 | be all zero, or all one. */ |
30cf4896 KG |
2044 | if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 |
2045 | && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) | |
2046 | != ((~(unsigned HOST_WIDE_INT) 0) | |
2047 | & ~(unsigned HOST_WIDE_INT) 0xffffffff))) | |
56636818 | 2048 | return FALSE; |
f676971a | 2049 | |
4642ccb1 | 2050 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; |
e0b92319 | 2051 | |
4642ccb1 RE |
2052 | /* Fast return for 0 and small values. We must do this for zero, since |
2053 | the code below can't handle that one case. */ | |
2054 | if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) | |
e2c671ba RE |
2055 | return TRUE; |
2056 | ||
5b3e6663 PB |
2057 | /* Get the number of trailing zeros. */ |
2058 | lowbit = ffs((int) i) - 1; | |
2059 | ||
2060 | /* Only even shifts are allowed in ARM mode so round down to the | |
2061 | nearest even number. */ | |
2062 | if (TARGET_ARM) | |
2063 | lowbit &= ~1; | |
4642ccb1 RE |
2064 | |
2065 | if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) | |
2066 | return TRUE; | |
5b3e6663 PB |
2067 | |
2068 | if (TARGET_ARM) | |
2069 | { | |
2070 | /* Allow rotated constants in ARM mode. */ | |
2071 | if (lowbit <= 4 | |
4642ccb1 RE |
2072 | && ((i & ~0xc000003f) == 0 |
2073 | || (i & ~0xf000000f) == 0 | |
2074 | || (i & ~0xfc000003) == 0)) | |
5b3e6663 PB |
2075 | return TRUE; |
2076 | } | |
2077 | else | |
2078 | { | |
2079 | HOST_WIDE_INT v; | |
2080 | ||
2081 | /* Allow repeated pattern. */ | |
2082 | v = i & 0xff; | |
2083 | v |= v << 16; | |
2084 | if (i == v || i == (v | (v << 8))) | |
2085 | return TRUE; | |
2086 | } | |
cce8749e | 2087 | |
f3bb6135 RE |
2088 | return FALSE; |
2089 | } | |
cce8749e | 2090 | |
6354dc9b | 2091 | /* Return true if I is a valid constant for the operation CODE. */ |
74bbc178 | 2092 | static int |
e32bac5b | 2093 | const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) |
e2c671ba RE |
2094 | { |
2095 | if (const_ok_for_arm (i)) | |
2096 | return 1; | |
2097 | ||
2098 | switch (code) | |
2099 | { | |
2100 | case PLUS: | |
d5a0a47b RE |
2101 | case COMPARE: |
2102 | case EQ: | |
2103 | case NE: | |
2104 | case GT: | |
2105 | case LE: | |
2106 | case LT: | |
2107 | case GE: | |
2108 | case GEU: | |
2109 | case LTU: | |
2110 | case GTU: | |
2111 | case LEU: | |
2112 | case UNORDERED: | |
2113 | case ORDERED: | |
2114 | case UNEQ: | |
2115 | case UNGE: | |
2116 | case UNLT: | |
2117 | case UNGT: | |
2118 | case UNLE: | |
e2c671ba RE |
2119 | return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); |
2120 | ||
2121 | case MINUS: /* Should only occur with (MINUS I reg) => rsb */ | |
2122 | case XOR: | |
a7994a57 RR |
2123 | return 0; |
2124 | ||
e2c671ba | 2125 | case IOR: |
a7994a57 RR |
2126 | if (TARGET_THUMB2) |
2127 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
e2c671ba RE |
2128 | return 0; |
2129 | ||
2130 | case AND: | |
2131 | return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); | |
2132 | ||
2133 | default: | |
e6d29d15 | 2134 | gcc_unreachable (); |
e2c671ba RE |
2135 | } |
2136 | } | |
2137 | ||
2138 | /* Emit a sequence of insns to handle a large constant. | |
2139 | CODE is the code of the operation required, it can be any of SET, PLUS, | |
2140 | IOR, AND, XOR, MINUS; | |
2141 | MODE is the mode in which the operation is being performed; | |
2142 | VAL is the integer to operate on; | |
2143 | SOURCE is the other operand (a register, or a null-pointer for SET); | |
2144 | SUBTARGETS means it is safe to create scratch registers if that will | |
2b835d68 RE |
2145 | either produce a simpler sequence, or we will want to cse the values. |
2146 | Return value is the number of insns emitted. */ | |
e2c671ba | 2147 | |
5b3e6663 | 2148 | /* ??? Tweak this for thumb2. */ |
e2c671ba | 2149 | int |
a406f566 | 2150 | arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, |
e32bac5b | 2151 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets) |
2b835d68 | 2152 | { |
a406f566 MM |
2153 | rtx cond; |
2154 | ||
2155 | if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) | |
2156 | cond = COND_EXEC_TEST (PATTERN (insn)); | |
2157 | else | |
2158 | cond = NULL_RTX; | |
2159 | ||
2b835d68 RE |
2160 | if (subtargets || code == SET |
2161 | || (GET_CODE (target) == REG && GET_CODE (source) == REG | |
2162 | && REGNO (target) != REGNO (source))) | |
2163 | { | |
4b632bf1 | 2164 | /* After arm_reorg has been called, we can't fix up expensive |
05713b80 | 2165 | constants by pushing them into memory so we must synthesize |
4b632bf1 RE |
2166 | them in-line, regardless of the cost. This is only likely to |
2167 | be more costly on chips that have load delay slots and we are | |
2168 | compiling without running the scheduler (so no splitting | |
aec3cfba NC |
2169 | occurred before the final instruction emission). |
2170 | ||
2171 | Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c | |
aec3cfba | 2172 | */ |
5895f793 | 2173 | if (!after_arm_reorg |
a406f566 | 2174 | && !cond |
f676971a | 2175 | && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, |
a406f566 | 2176 | 1, 0) |
4b632bf1 | 2177 | > arm_constant_limit + (code != SET))) |
2b835d68 RE |
2178 | { |
2179 | if (code == SET) | |
2180 | { | |
2181 | /* Currently SET is the only monadic value for CODE, all | |
2182 | the rest are diadic. */ | |
571191af PB |
2183 | if (TARGET_USE_MOVT) |
2184 | arm_emit_movpair (target, GEN_INT (val)); | |
2185 | else | |
2186 | emit_set_insn (target, GEN_INT (val)); | |
2187 | ||
2b835d68 RE |
2188 | return 1; |
2189 | } | |
2190 | else | |
2191 | { | |
2192 | rtx temp = subtargets ? gen_reg_rtx (mode) : target; | |
2193 | ||
571191af PB |
2194 | if (TARGET_USE_MOVT) |
2195 | arm_emit_movpair (temp, GEN_INT (val)); | |
2196 | else | |
2197 | emit_set_insn (temp, GEN_INT (val)); | |
2198 | ||
2b835d68 RE |
2199 | /* For MINUS, the value is subtracted from, since we never |
2200 | have subtraction of a constant. */ | |
2201 | if (code == MINUS) | |
d66437c5 | 2202 | emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); |
2b835d68 | 2203 | else |
d66437c5 RE |
2204 | emit_set_insn (target, |
2205 | gen_rtx_fmt_ee (code, mode, source, temp)); | |
2b835d68 RE |
2206 | return 2; |
2207 | } | |
2208 | } | |
2209 | } | |
2210 | ||
f676971a | 2211 | return arm_gen_constant (code, mode, cond, val, target, source, subtargets, |
a406f566 | 2212 | 1); |
2b835d68 RE |
2213 | } |
2214 | ||
5b3e6663 PB |
2215 | /* Return the number of ARM instructions required to synthesize the given |
2216 | constant. */ | |
ceebdb09 | 2217 | static int |
e32bac5b | 2218 | count_insns_for_constant (HOST_WIDE_INT remainder, int i) |
ceebdb09 PB |
2219 | { |
2220 | HOST_WIDE_INT temp1; | |
2221 | int num_insns = 0; | |
2222 | do | |
2223 | { | |
2224 | int end; | |
f676971a | 2225 | |
ceebdb09 PB |
2226 | if (i <= 0) |
2227 | i += 32; | |
2228 | if (remainder & (3 << (i - 2))) | |
2229 | { | |
2230 | end = i - 8; | |
2231 | if (end < 0) | |
2232 | end += 32; | |
2233 | temp1 = remainder & ((0x0ff << end) | |
2234 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2235 | remainder &= ~temp1; | |
2236 | num_insns++; | |
2237 | i -= 6; | |
2238 | } | |
2239 | i -= 2; | |
2240 | } while (remainder); | |
2241 | return num_insns; | |
2242 | } | |
2243 | ||
a406f566 MM |
2244 | /* Emit an instruction with the indicated PATTERN. If COND is |
2245 | non-NULL, conditionalize the execution of the instruction on COND | |
2246 | being true. */ | |
2247 | ||
2248 | static void | |
2249 | emit_constant_insn (rtx cond, rtx pattern) | |
2250 | { | |
2251 | if (cond) | |
2252 | pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); | |
2253 | emit_insn (pattern); | |
2254 | } | |
2255 | ||
2b835d68 RE |
2256 | /* As above, but extra parameter GENERATE which, if clear, suppresses |
2257 | RTL generation. */ | |
5b3e6663 | 2258 | /* ??? This needs more work for thumb2. */ |
1d6e90ac | 2259 | |
d5b7b3ae | 2260 | static int |
a406f566 | 2261 | arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, |
e32bac5b RE |
2262 | HOST_WIDE_INT val, rtx target, rtx source, int subtargets, |
2263 | int generate) | |
e2c671ba | 2264 | { |
e2c671ba RE |
2265 | int can_invert = 0; |
2266 | int can_negate = 0; | |
2267 | int can_negate_initial = 0; | |
2268 | int can_shift = 0; | |
2269 | int i; | |
2270 | int num_bits_set = 0; | |
2271 | int set_sign_bit_copies = 0; | |
2272 | int clear_sign_bit_copies = 0; | |
2273 | int clear_zero_bit_copies = 0; | |
2274 | int set_zero_bit_copies = 0; | |
2275 | int insns = 0; | |
e2c671ba | 2276 | unsigned HOST_WIDE_INT temp1, temp2; |
30cf4896 | 2277 | unsigned HOST_WIDE_INT remainder = val & 0xffffffff; |
e2c671ba | 2278 | |
d5b7b3ae | 2279 | /* Find out which operations are safe for a given CODE. Also do a quick |
e2c671ba RE |
2280 | check for degenerate cases; these can occur when DImode operations |
2281 | are split. */ | |
2282 | switch (code) | |
2283 | { | |
2284 | case SET: | |
2285 | can_invert = 1; | |
2286 | can_shift = 1; | |
2287 | can_negate = 1; | |
2288 | break; | |
2289 | ||
2290 | case PLUS: | |
2291 | can_negate = 1; | |
2292 | can_negate_initial = 1; | |
2293 | break; | |
2294 | ||
2295 | case IOR: | |
30cf4896 | 2296 | if (remainder == 0xffffffff) |
e2c671ba | 2297 | { |
2b835d68 | 2298 | if (generate) |
a406f566 MM |
2299 | emit_constant_insn (cond, |
2300 | gen_rtx_SET (VOIDmode, target, | |
2301 | GEN_INT (ARM_SIGN_EXTEND (val)))); | |
e2c671ba RE |
2302 | return 1; |
2303 | } | |
a7994a57 | 2304 | |
e2c671ba RE |
2305 | if (remainder == 0) |
2306 | { | |
2307 | if (reload_completed && rtx_equal_p (target, source)) | |
2308 | return 0; | |
a7994a57 | 2309 | |
2b835d68 | 2310 | if (generate) |
a406f566 MM |
2311 | emit_constant_insn (cond, |
2312 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2313 | return 1; |
2314 | } | |
a7994a57 RR |
2315 | |
2316 | if (TARGET_THUMB2) | |
2317 | can_invert = 1; | |
e2c671ba RE |
2318 | break; |
2319 | ||
2320 | case AND: | |
2321 | if (remainder == 0) | |
2322 | { | |
2b835d68 | 2323 | if (generate) |
a406f566 MM |
2324 | emit_constant_insn (cond, |
2325 | gen_rtx_SET (VOIDmode, target, const0_rtx)); | |
e2c671ba RE |
2326 | return 1; |
2327 | } | |
30cf4896 | 2328 | if (remainder == 0xffffffff) |
e2c671ba RE |
2329 | { |
2330 | if (reload_completed && rtx_equal_p (target, source)) | |
2331 | return 0; | |
2b835d68 | 2332 | if (generate) |
a406f566 MM |
2333 | emit_constant_insn (cond, |
2334 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2335 | return 1; |
2336 | } | |
2337 | can_invert = 1; | |
2338 | break; | |
2339 | ||
2340 | case XOR: | |
2341 | if (remainder == 0) | |
2342 | { | |
2343 | if (reload_completed && rtx_equal_p (target, source)) | |
2344 | return 0; | |
2b835d68 | 2345 | if (generate) |
a406f566 MM |
2346 | emit_constant_insn (cond, |
2347 | gen_rtx_SET (VOIDmode, target, source)); | |
e2c671ba RE |
2348 | return 1; |
2349 | } | |
e0b92319 | 2350 | |
e6d29d15 NS |
2351 | /* We don't know how to handle other cases yet. */ |
2352 | gcc_assert (remainder == 0xffffffff); | |
e0b92319 | 2353 | |
e6d29d15 NS |
2354 | if (generate) |
2355 | emit_constant_insn (cond, | |
2356 | gen_rtx_SET (VOIDmode, target, | |
2357 | gen_rtx_NOT (mode, source))); | |
2358 | return 1; | |
e2c671ba RE |
2359 | |
2360 | case MINUS: | |
2361 | /* We treat MINUS as (val - source), since (source - val) is always | |
2362 | passed as (source + (-val)). */ | |
2363 | if (remainder == 0) | |
2364 | { | |
2b835d68 | 2365 | if (generate) |
a406f566 MM |
2366 | emit_constant_insn (cond, |
2367 | gen_rtx_SET (VOIDmode, target, | |
2368 | gen_rtx_NEG (mode, source))); | |
e2c671ba RE |
2369 | return 1; |
2370 | } | |
2371 | if (const_ok_for_arm (val)) | |
2372 | { | |
2b835d68 | 2373 | if (generate) |
a406f566 | 2374 | emit_constant_insn (cond, |
f676971a | 2375 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2376 | gen_rtx_MINUS (mode, GEN_INT (val), |
2377 | source))); | |
e2c671ba RE |
2378 | return 1; |
2379 | } | |
2380 | can_negate = 1; | |
2381 | ||
2382 | break; | |
2383 | ||
2384 | default: | |
e6d29d15 | 2385 | gcc_unreachable (); |
e2c671ba RE |
2386 | } |
2387 | ||
6354dc9b | 2388 | /* If we can do it in one insn get out quickly. */ |
e2c671ba RE |
2389 | if (const_ok_for_arm (val) |
2390 | || (can_negate_initial && const_ok_for_arm (-val)) | |
2391 | || (can_invert && const_ok_for_arm (~val))) | |
2392 | { | |
2b835d68 | 2393 | if (generate) |
a406f566 MM |
2394 | emit_constant_insn (cond, |
2395 | gen_rtx_SET (VOIDmode, target, | |
f676971a | 2396 | (source |
a406f566 MM |
2397 | ? gen_rtx_fmt_ee (code, mode, source, |
2398 | GEN_INT (val)) | |
2399 | : GEN_INT (val)))); | |
e2c671ba RE |
2400 | return 1; |
2401 | } | |
2402 | ||
e2c671ba | 2403 | /* Calculate a few attributes that may be useful for specific |
6354dc9b | 2404 | optimizations. */ |
a7994a57 | 2405 | /* Count number of leading zeros. */ |
e2c671ba RE |
2406 | for (i = 31; i >= 0; i--) |
2407 | { | |
2408 | if ((remainder & (1 << i)) == 0) | |
2409 | clear_sign_bit_copies++; | |
2410 | else | |
2411 | break; | |
2412 | } | |
2413 | ||
a7994a57 | 2414 | /* Count number of leading 1's. */ |
e2c671ba RE |
2415 | for (i = 31; i >= 0; i--) |
2416 | { | |
2417 | if ((remainder & (1 << i)) != 0) | |
2418 | set_sign_bit_copies++; | |
2419 | else | |
2420 | break; | |
2421 | } | |
2422 | ||
a7994a57 | 2423 | /* Count number of trailing zero's. */ |
e2c671ba RE |
2424 | for (i = 0; i <= 31; i++) |
2425 | { | |
2426 | if ((remainder & (1 << i)) == 0) | |
2427 | clear_zero_bit_copies++; | |
2428 | else | |
2429 | break; | |
2430 | } | |
2431 | ||
a7994a57 | 2432 | /* Count number of trailing 1's. */ |
e2c671ba RE |
2433 | for (i = 0; i <= 31; i++) |
2434 | { | |
2435 | if ((remainder & (1 << i)) != 0) | |
2436 | set_zero_bit_copies++; | |
2437 | else | |
2438 | break; | |
2439 | } | |
2440 | ||
2441 | switch (code) | |
2442 | { | |
2443 | case SET: | |
5b3e6663 PB |
2444 | /* See if we can use movw. */ |
2445 | if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0) | |
2446 | { | |
2447 | if (generate) | |
2448 | emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target, | |
2449 | GEN_INT (val))); | |
2450 | return 1; | |
2451 | } | |
2452 | ||
e2c671ba RE |
2453 | /* See if we can do this by sign_extending a constant that is known |
2454 | to be negative. This is a good, way of doing it, since the shift | |
2455 | may well merge into a subsequent insn. */ | |
2456 | if (set_sign_bit_copies > 1) | |
2457 | { | |
2458 | if (const_ok_for_arm | |
f676971a | 2459 | (temp1 = ARM_SIGN_EXTEND (remainder |
e2c671ba RE |
2460 | << (set_sign_bit_copies - 1)))) |
2461 | { | |
2b835d68 RE |
2462 | if (generate) |
2463 | { | |
d499463f | 2464 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 | 2465 | emit_constant_insn (cond, |
f676971a | 2466 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 MM |
2467 | GEN_INT (temp1))); |
2468 | emit_constant_insn (cond, | |
f676971a | 2469 | gen_ashrsi3 (target, new_src, |
a406f566 | 2470 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2471 | } |
e2c671ba RE |
2472 | return 2; |
2473 | } | |
2474 | /* For an inverted constant, we will need to set the low bits, | |
2475 | these will be shifted out of harm's way. */ | |
2476 | temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; | |
2477 | if (const_ok_for_arm (~temp1)) | |
2478 | { | |
2b835d68 RE |
2479 | if (generate) |
2480 | { | |
d499463f | 2481 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
a406f566 MM |
2482 | emit_constant_insn (cond, |
2483 | gen_rtx_SET (VOIDmode, new_src, | |
2484 | GEN_INT (temp1))); | |
2485 | emit_constant_insn (cond, | |
f676971a | 2486 | gen_ashrsi3 (target, new_src, |
a406f566 | 2487 | GEN_INT (set_sign_bit_copies - 1))); |
2b835d68 | 2488 | } |
e2c671ba RE |
2489 | return 2; |
2490 | } | |
2491 | } | |
2492 | ||
c87e6352 RE |
2493 | /* See if we can calculate the value as the difference between two |
2494 | valid immediates. */ | |
2495 | if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) | |
2496 | { | |
2497 | int topshift = clear_sign_bit_copies & ~1; | |
2498 | ||
fa2c88a0 RE |
2499 | temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) |
2500 | & (0xff000000 >> topshift)); | |
c87e6352 RE |
2501 | |
2502 | /* If temp1 is zero, then that means the 9 most significant | |
2503 | bits of remainder were 1 and we've caused it to overflow. | |
2504 | When topshift is 0 we don't need to do anything since we | |
2505 | can borrow from 'bit 32'. */ | |
2506 | if (temp1 == 0 && topshift != 0) | |
2507 | temp1 = 0x80000000 >> (topshift - 1); | |
2508 | ||
fa2c88a0 | 2509 | temp2 = ARM_SIGN_EXTEND (temp1 - remainder); |
e0b92319 | 2510 | |
c87e6352 RE |
2511 | if (const_ok_for_arm (temp2)) |
2512 | { | |
2513 | if (generate) | |
2514 | { | |
2515 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; | |
2516 | emit_constant_insn (cond, | |
2517 | gen_rtx_SET (VOIDmode, new_src, | |
2518 | GEN_INT (temp1))); | |
2519 | emit_constant_insn (cond, | |
2520 | gen_addsi3 (target, new_src, | |
2521 | GEN_INT (-temp2))); | |
2522 | } | |
2523 | ||
2524 | return 2; | |
2525 | } | |
2526 | } | |
2527 | ||
e2c671ba RE |
2528 | /* See if we can generate this by setting the bottom (or the top) |
2529 | 16 bits, and then shifting these into the other half of the | |
2530 | word. We only look for the simplest cases, to do more would cost | |
2531 | too much. Be careful, however, not to generate this when the | |
2532 | alternative would take fewer insns. */ | |
30cf4896 | 2533 | if (val & 0xffff0000) |
e2c671ba | 2534 | { |
30cf4896 | 2535 | temp1 = remainder & 0xffff0000; |
e2c671ba RE |
2536 | temp2 = remainder & 0x0000ffff; |
2537 | ||
6354dc9b | 2538 | /* Overlaps outside this range are best done using other methods. */ |
e2c671ba RE |
2539 | for (i = 9; i < 24; i++) |
2540 | { | |
30cf4896 | 2541 | if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) |
5895f793 | 2542 | && !const_ok_for_arm (temp2)) |
e2c671ba | 2543 | { |
d499463f RE |
2544 | rtx new_src = (subtargets |
2545 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2546 | : target); | |
a406f566 | 2547 | insns = arm_gen_constant (code, mode, cond, temp2, new_src, |
2b835d68 | 2548 | source, subtargets, generate); |
e2c671ba | 2549 | source = new_src; |
2b835d68 | 2550 | if (generate) |
f676971a | 2551 | emit_constant_insn |
a406f566 MM |
2552 | (cond, |
2553 | gen_rtx_SET | |
2554 | (VOIDmode, target, | |
2555 | gen_rtx_IOR (mode, | |
2556 | gen_rtx_ASHIFT (mode, source, | |
2557 | GEN_INT (i)), | |
2558 | source))); | |
e2c671ba RE |
2559 | return insns + 1; |
2560 | } | |
2561 | } | |
2562 | ||
6354dc9b | 2563 | /* Don't duplicate cases already considered. */ |
e2c671ba RE |
2564 | for (i = 17; i < 24; i++) |
2565 | { | |
2566 | if (((temp1 | (temp1 >> i)) == remainder) | |
5895f793 | 2567 | && !const_ok_for_arm (temp1)) |
e2c671ba | 2568 | { |
d499463f RE |
2569 | rtx new_src = (subtargets |
2570 | ? (generate ? gen_reg_rtx (mode) : NULL_RTX) | |
2571 | : target); | |
a406f566 | 2572 | insns = arm_gen_constant (code, mode, cond, temp1, new_src, |
2b835d68 | 2573 | source, subtargets, generate); |
e2c671ba | 2574 | source = new_src; |
2b835d68 | 2575 | if (generate) |
a406f566 MM |
2576 | emit_constant_insn |
2577 | (cond, | |
2578 | gen_rtx_SET (VOIDmode, target, | |
43cffd11 RE |
2579 | gen_rtx_IOR |
2580 | (mode, | |
2581 | gen_rtx_LSHIFTRT (mode, source, | |
2582 | GEN_INT (i)), | |
2583 | source))); | |
e2c671ba RE |
2584 | return insns + 1; |
2585 | } | |
2586 | } | |
2587 | } | |
2588 | break; | |
2589 | ||
2590 | case IOR: | |
2591 | case XOR: | |
7b64da89 RE |
2592 | /* If we have IOR or XOR, and the constant can be loaded in a |
2593 | single instruction, and we can find a temporary to put it in, | |
e2c671ba RE |
2594 | then this can be done in two instructions instead of 3-4. */ |
2595 | if (subtargets | |
d499463f | 2596 | /* TARGET can't be NULL if SUBTARGETS is 0 */ |
5895f793 | 2597 | || (reload_completed && !reg_mentioned_p (target, source))) |
e2c671ba | 2598 | { |
5895f793 | 2599 | if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2600 | { |
2b835d68 RE |
2601 | if (generate) |
2602 | { | |
2603 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
e2c671ba | 2604 | |
a406f566 | 2605 | emit_constant_insn (cond, |
f676971a | 2606 | gen_rtx_SET (VOIDmode, sub, |
a406f566 MM |
2607 | GEN_INT (val))); |
2608 | emit_constant_insn (cond, | |
f676971a | 2609 | gen_rtx_SET (VOIDmode, target, |
a406f566 MM |
2610 | gen_rtx_fmt_ee (code, mode, |
2611 | source, sub))); | |
2b835d68 | 2612 | } |
e2c671ba RE |
2613 | return 2; |
2614 | } | |
2615 | } | |
2616 | ||
2617 | if (code == XOR) | |
2618 | break; | |
2619 | ||
a7994a57 RR |
2620 | /* Convert. |
2621 | x = y | constant ( which is composed of set_sign_bit_copies of leading 1s | |
2622 | and the remainder 0s for e.g. 0xfff00000) | |
2623 | x = ~(~(y ashift set_sign_bit_copies) lshiftrt set_sign_bit_copies) | |
2624 | ||
2625 | This can be done in 2 instructions by using shifts with mov or mvn. | |
2626 | e.g. for | |
2627 | x = x | 0xfff00000; | |
2628 | we generate. | |
2629 | mvn r0, r0, asl #12 | |
2630 | mvn r0, r0, lsr #12 */ | |
e2c671ba RE |
2631 | if (set_sign_bit_copies > 8 |
2632 | && (val & (-1 << (32 - set_sign_bit_copies))) == val) | |
2633 | { | |
2b835d68 RE |
2634 | if (generate) |
2635 | { | |
2636 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2637 | rtx shift = GEN_INT (set_sign_bit_copies); | |
2638 | ||
f676971a | 2639 | emit_constant_insn |
a406f566 MM |
2640 | (cond, |
2641 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2642 | gen_rtx_NOT (mode, |
a406f566 | 2643 | gen_rtx_ASHIFT (mode, |
f676971a | 2644 | source, |
a406f566 | 2645 | shift)))); |
f676971a | 2646 | emit_constant_insn |
a406f566 MM |
2647 | (cond, |
2648 | gen_rtx_SET (VOIDmode, target, | |
2649 | gen_rtx_NOT (mode, | |
2650 | gen_rtx_LSHIFTRT (mode, sub, | |
2651 | shift)))); | |
2b835d68 | 2652 | } |
e2c671ba RE |
2653 | return 2; |
2654 | } | |
2655 | ||
a7994a57 RR |
2656 | /* Convert |
2657 | x = y | constant (which has set_zero_bit_copies number of trailing ones). | |
2658 | to | |
2659 | x = ~((~y lshiftrt set_zero_bit_copies) ashift set_zero_bit_copies). | |
2660 | ||
2661 | For eg. r0 = r0 | 0xfff | |
2662 | mvn r0, r0, lsr #12 | |
2663 | mvn r0, r0, asl #12 | |
2664 | ||
2665 | */ | |
e2c671ba RE |
2666 | if (set_zero_bit_copies > 8 |
2667 | && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) | |
2668 | { | |
2b835d68 RE |
2669 | if (generate) |
2670 | { | |
2671 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
2672 | rtx shift = GEN_INT (set_zero_bit_copies); | |
2673 | ||
a406f566 MM |
2674 | emit_constant_insn |
2675 | (cond, | |
2676 | gen_rtx_SET (VOIDmode, sub, | |
2677 | gen_rtx_NOT (mode, | |
2678 | gen_rtx_LSHIFTRT (mode, | |
2679 | source, | |
2680 | shift)))); | |
f676971a | 2681 | emit_constant_insn |
a406f566 MM |
2682 | (cond, |
2683 | gen_rtx_SET (VOIDmode, target, | |
2684 | gen_rtx_NOT (mode, | |
2685 | gen_rtx_ASHIFT (mode, sub, | |
2686 | shift)))); | |
2b835d68 | 2687 | } |
e2c671ba RE |
2688 | return 2; |
2689 | } | |
2690 | ||
a7994a57 RR |
2691 | /* This will never be reached for Thumb2 because orn is a valid |
2692 | instruction. This is for Thumb1 and the ARM 32 bit cases. | |
2693 | ||
2694 | x = y | constant (such that ~constant is a valid constant) | |
2695 | Transform this to | |
2696 | x = ~(~y & ~constant). | |
2697 | */ | |
5895f793 | 2698 | if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) |
e2c671ba | 2699 | { |
2b835d68 RE |
2700 | if (generate) |
2701 | { | |
2702 | rtx sub = subtargets ? gen_reg_rtx (mode) : target; | |
a406f566 MM |
2703 | emit_constant_insn (cond, |
2704 | gen_rtx_SET (VOIDmode, sub, | |
2705 | gen_rtx_NOT (mode, source))); | |
2b835d68 RE |
2706 | source = sub; |
2707 | if (subtargets) | |
2708 | sub = gen_reg_rtx (mode); | |
a406f566 MM |
2709 | emit_constant_insn (cond, |
2710 | gen_rtx_SET (VOIDmode, sub, | |
f676971a | 2711 | gen_rtx_AND (mode, source, |
a406f566 MM |
2712 | GEN_INT (temp1)))); |
2713 | emit_constant_insn (cond, | |
2714 | gen_rtx_SET (VOIDmode, target, | |
2715 | gen_rtx_NOT (mode, sub))); | |
2b835d68 | 2716 | } |
e2c671ba RE |
2717 | return 3; |
2718 | } | |
2719 | break; | |
2720 | ||
2721 | case AND: | |
2722 | /* See if two shifts will do 2 or more insn's worth of work. */ | |
2723 | if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) | |
2724 | { | |
30cf4896 | 2725 | HOST_WIDE_INT shift_mask = ((0xffffffff |
e2c671ba | 2726 | << (32 - clear_sign_bit_copies)) |
30cf4896 | 2727 | & 0xffffffff); |
e2c671ba | 2728 | |
30cf4896 | 2729 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2730 | { |
2b835d68 RE |
2731 | if (generate) |
2732 | { | |
d499463f | 2733 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
f676971a | 2734 | insns = arm_gen_constant (AND, mode, cond, |
a406f566 | 2735 | remainder | shift_mask, |
d499463f RE |
2736 | new_src, source, subtargets, 1); |
2737 | source = new_src; | |
2b835d68 RE |
2738 | } |
2739 | else | |
d499463f RE |
2740 | { |
2741 | rtx targ = subtargets ? NULL_RTX : target; | |
a406f566 MM |
2742 | insns = arm_gen_constant (AND, mode, cond, |
2743 | remainder | shift_mask, | |
d499463f RE |
2744 | targ, source, subtargets, 0); |
2745 | } | |
2b835d68 RE |
2746 | } |
2747 | ||
2748 | if (generate) | |
2749 | { | |
d499463f RE |
2750 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2751 | rtx shift = GEN_INT (clear_sign_bit_copies); | |
2752 | ||
2753 | emit_insn (gen_ashlsi3 (new_src, source, shift)); | |
2754 | emit_insn (gen_lshrsi3 (target, new_src, shift)); | |
e2c671ba RE |
2755 | } |
2756 | ||
e2c671ba RE |
2757 | return insns + 2; |
2758 | } | |
2759 | ||
2760 | if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) | |
2761 | { | |
2762 | HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; | |
f676971a | 2763 | |
30cf4896 | 2764 | if ((remainder | shift_mask) != 0xffffffff) |
e2c671ba | 2765 | { |
2b835d68 RE |
2766 | if (generate) |
2767 | { | |
d499463f RE |
2768 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2769 | ||
a406f566 MM |
2770 | insns = arm_gen_constant (AND, mode, cond, |
2771 | remainder | shift_mask, | |
d499463f RE |
2772 | new_src, source, subtargets, 1); |
2773 | source = new_src; | |
2b835d68 RE |
2774 | } |
2775 | else | |
d499463f RE |
2776 | { |
2777 | rtx targ = subtargets ? NULL_RTX : target; | |
2778 | ||
a406f566 MM |
2779 | insns = arm_gen_constant (AND, mode, cond, |
2780 | remainder | shift_mask, | |
d499463f RE |
2781 | targ, source, subtargets, 0); |
2782 | } | |
2b835d68 RE |
2783 | } |
2784 | ||
2785 | if (generate) | |
2786 | { | |
d499463f RE |
2787 | rtx new_src = subtargets ? gen_reg_rtx (mode) : target; |
2788 | rtx shift = GEN_INT (clear_zero_bit_copies); | |
2789 | ||
2790 | emit_insn (gen_lshrsi3 (new_src, source, shift)); | |
2791 | emit_insn (gen_ashlsi3 (target, new_src, shift)); | |
e2c671ba RE |
2792 | } |
2793 | ||
e2c671ba RE |
2794 | return insns + 2; |
2795 | } | |
2796 | ||
2797 | break; | |
2798 | ||
2799 | default: | |
2800 | break; | |
2801 | } | |
2802 | ||
2803 | for (i = 0; i < 32; i++) | |
2804 | if (remainder & (1 << i)) | |
2805 | num_bits_set++; | |
2806 | ||
a7994a57 RR |
2807 | if ((code == AND) |
2808 | || (code != IOR && can_invert && num_bits_set > 16)) | |
30cf4896 | 2809 | remainder = (~remainder) & 0xffffffff; |
e2c671ba | 2810 | else if (code == PLUS && num_bits_set > 16) |
30cf4896 | 2811 | remainder = (-remainder) & 0xffffffff; |
e2c671ba RE |
2812 | else |
2813 | { | |
2814 | can_invert = 0; | |
2815 | can_negate = 0; | |
2816 | } | |
2817 | ||
2818 | /* Now try and find a way of doing the job in either two or three | |
2819 | instructions. | |
2820 | We start by looking for the largest block of zeros that are aligned on | |
2821 | a 2-bit boundary, we then fill up the temps, wrapping around to the | |
2822 | top of the word when we drop off the bottom. | |
5b3e6663 PB |
2823 | In the worst case this code should produce no more than four insns. |
2824 | Thumb-2 constants are shifted, not rotated, so the MSB is always the | |
2825 | best place to start. */ | |
2826 | ||
2827 | /* ??? Use thumb2 replicated constants when the high and low halfwords are | |
2828 | the same. */ | |
e2c671ba RE |
2829 | { |
2830 | int best_start = 0; | |
5b3e6663 | 2831 | if (!TARGET_THUMB2) |
e2c671ba | 2832 | { |
5b3e6663 | 2833 | int best_consecutive_zeros = 0; |
e2c671ba | 2834 | |
5b3e6663 | 2835 | for (i = 0; i < 32; i += 2) |
e2c671ba | 2836 | { |
5b3e6663 PB |
2837 | int consecutive_zeros = 0; |
2838 | ||
2839 | if (!(remainder & (3 << i))) | |
e2c671ba | 2840 | { |
5b3e6663 PB |
2841 | while ((i < 32) && !(remainder & (3 << i))) |
2842 | { | |
2843 | consecutive_zeros += 2; | |
2844 | i += 2; | |
2845 | } | |
2846 | if (consecutive_zeros > best_consecutive_zeros) | |
2847 | { | |
2848 | best_consecutive_zeros = consecutive_zeros; | |
2849 | best_start = i - consecutive_zeros; | |
2850 | } | |
2851 | i -= 2; | |
e2c671ba | 2852 | } |
e2c671ba | 2853 | } |
ceebdb09 | 2854 | |
5b3e6663 PB |
2855 | /* So long as it won't require any more insns to do so, it's |
2856 | desirable to emit a small constant (in bits 0...9) in the last | |
2857 | insn. This way there is more chance that it can be combined with | |
2858 | a later addressing insn to form a pre-indexed load or store | |
2859 | operation. Consider: | |
2860 | ||
2861 | *((volatile int *)0xe0000100) = 1; | |
2862 | *((volatile int *)0xe0000110) = 2; | |
2863 | ||
2864 | We want this to wind up as: | |
2865 | ||
2866 | mov rA, #0xe0000000 | |
2867 | mov rB, #1 | |
2868 | str rB, [rA, #0x100] | |
2869 | mov rB, #2 | |
2870 | str rB, [rA, #0x110] | |
2871 | ||
2872 | rather than having to synthesize both large constants from scratch. | |
2873 | ||
2874 | Therefore, we calculate how many insns would be required to emit | |
2875 | the constant starting from `best_start', and also starting from | |
2876 | zero (i.e. with bit 31 first to be output). If `best_start' doesn't | |
2877 | yield a shorter sequence, we may as well use zero. */ | |
2878 | if (best_start != 0 | |
2879 | && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) | |
2880 | && (count_insns_for_constant (remainder, 0) <= | |
2881 | count_insns_for_constant (remainder, best_start))) | |
2882 | best_start = 0; | |
2883 | } | |
ceebdb09 PB |
2884 | |
2885 | /* Now start emitting the insns. */ | |
e2c671ba RE |
2886 | i = best_start; |
2887 | do | |
2888 | { | |
2889 | int end; | |
2890 | ||
2891 | if (i <= 0) | |
2892 | i += 32; | |
2893 | if (remainder & (3 << (i - 2))) | |
2894 | { | |
2895 | end = i - 8; | |
2896 | if (end < 0) | |
2897 | end += 32; | |
2898 | temp1 = remainder & ((0x0ff << end) | |
2899 | | ((i < end) ? (0xff >> (32 - end)) : 0)); | |
2900 | remainder &= ~temp1; | |
2901 | ||
d499463f | 2902 | if (generate) |
e2c671ba | 2903 | { |
9503f3d1 RH |
2904 | rtx new_src, temp1_rtx; |
2905 | ||
2906 | if (code == SET || code == MINUS) | |
2907 | { | |
2908 | new_src = (subtargets ? gen_reg_rtx (mode) : target); | |
96ae8197 | 2909 | if (can_invert && code != MINUS) |
9503f3d1 RH |
2910 | temp1 = ~temp1; |
2911 | } | |
2912 | else | |
2913 | { | |
96ae8197 | 2914 | if (remainder && subtargets) |
9503f3d1 | 2915 | new_src = gen_reg_rtx (mode); |
96ae8197 NC |
2916 | else |
2917 | new_src = target; | |
9503f3d1 RH |
2918 | if (can_invert) |
2919 | temp1 = ~temp1; | |
2920 | else if (can_negate) | |
2921 | temp1 = -temp1; | |
2922 | } | |
2923 | ||
2924 | temp1 = trunc_int_for_mode (temp1, mode); | |
2925 | temp1_rtx = GEN_INT (temp1); | |
d499463f RE |
2926 | |
2927 | if (code == SET) | |
9503f3d1 | 2928 | ; |
d499463f | 2929 | else if (code == MINUS) |
9503f3d1 | 2930 | temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); |
d499463f | 2931 | else |
9503f3d1 RH |
2932 | temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); |
2933 | ||
a406f566 | 2934 | emit_constant_insn (cond, |
f676971a | 2935 | gen_rtx_SET (VOIDmode, new_src, |
a406f566 | 2936 | temp1_rtx)); |
d499463f | 2937 | source = new_src; |
e2c671ba RE |
2938 | } |
2939 | ||
d499463f RE |
2940 | if (code == SET) |
2941 | { | |
2942 | can_invert = 0; | |
2943 | code = PLUS; | |
2944 | } | |
2945 | else if (code == MINUS) | |
2946 | code = PLUS; | |
2947 | ||
e2c671ba | 2948 | insns++; |
5b3e6663 PB |
2949 | if (TARGET_ARM) |
2950 | i -= 6; | |
2951 | else | |
2952 | i -= 7; | |
e2c671ba | 2953 | } |
7a085dce | 2954 | /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary |
5b3e6663 PB |
2955 | shifts. */ |
2956 | if (TARGET_ARM) | |
2957 | i -= 2; | |
2958 | else | |
2959 | i--; | |
1d6e90ac NC |
2960 | } |
2961 | while (remainder); | |
e2c671ba | 2962 | } |
1d6e90ac | 2963 | |
e2c671ba RE |
2964 | return insns; |
2965 | } | |
2966 | ||
bd9c7e23 RE |
2967 | /* Canonicalize a comparison so that we are more likely to recognize it. |
2968 | This can be done for a few constant compares, where we can make the | |
2969 | immediate value easier to load. */ | |
1d6e90ac | 2970 | |
bd9c7e23 | 2971 | enum rtx_code |
a14b88bb PB |
2972 | arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, |
2973 | rtx * op1) | |
bd9c7e23 | 2974 | { |
ad076f4e | 2975 | unsigned HOST_WIDE_INT i = INTVAL (*op1); |
a14b88bb PB |
2976 | unsigned HOST_WIDE_INT maxval; |
2977 | maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; | |
bd9c7e23 RE |
2978 | |
2979 | switch (code) | |
2980 | { | |
2981 | case EQ: | |
2982 | case NE: | |
2983 | return code; | |
2984 | ||
2985 | case GT: | |
2986 | case LE: | |
a14b88bb | 2987 | if (i != maxval |
5895f793 | 2988 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 | 2989 | { |
5895f793 | 2990 | *op1 = GEN_INT (i + 1); |
bd9c7e23 RE |
2991 | return code == GT ? GE : LT; |
2992 | } | |
2993 | break; | |
2994 | ||
2995 | case GE: | |
2996 | case LT: | |
a14b88bb | 2997 | if (i != ~maxval |
5895f793 | 2998 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 | 2999 | { |
5895f793 | 3000 | *op1 = GEN_INT (i - 1); |
bd9c7e23 RE |
3001 | return code == GE ? GT : LE; |
3002 | } | |
3003 | break; | |
3004 | ||
3005 | case GTU: | |
3006 | case LEU: | |
30cf4896 | 3007 | if (i != ~((unsigned HOST_WIDE_INT) 0) |
5895f793 | 3008 | && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) |
bd9c7e23 RE |
3009 | { |
3010 | *op1 = GEN_INT (i + 1); | |
3011 | return code == GTU ? GEU : LTU; | |
3012 | } | |
3013 | break; | |
3014 | ||
3015 | case GEU: | |
3016 | case LTU: | |
3017 | if (i != 0 | |
5895f793 | 3018 | && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) |
bd9c7e23 RE |
3019 | { |
3020 | *op1 = GEN_INT (i - 1); | |
3021 | return code == GEU ? GTU : LEU; | |
3022 | } | |
3023 | break; | |
3024 | ||
3025 | default: | |
e6d29d15 | 3026 | gcc_unreachable (); |
bd9c7e23 RE |
3027 | } |
3028 | ||
3029 | return code; | |
3030 | } | |
bd9c7e23 | 3031 | |
d4453b7a PB |
3032 | |
3033 | /* Define how to find the value returned by a function. */ | |
3034 | ||
9f7bf991 | 3035 | rtx |
586de218 | 3036 | arm_function_value(const_tree type, const_tree func ATTRIBUTE_UNUSED) |
d4453b7a PB |
3037 | { |
3038 | enum machine_mode mode; | |
3039 | int unsignedp ATTRIBUTE_UNUSED; | |
3040 | rtx r ATTRIBUTE_UNUSED; | |
3041 | ||
d4453b7a PB |
3042 | mode = TYPE_MODE (type); |
3043 | /* Promote integer types. */ | |
3044 | if (INTEGRAL_TYPE_P (type)) | |
3045 | PROMOTE_FUNCTION_MODE (mode, unsignedp, type); | |
866af8a9 JB |
3046 | |
3047 | /* Promotes small structs returned in a register to full-word size | |
3048 | for big-endian AAPCS. */ | |
3049 | if (arm_return_in_msb (type)) | |
3050 | { | |
3051 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
3052 | if (size % UNITS_PER_WORD != 0) | |
3053 | { | |
3054 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; | |
3055 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
3056 | } | |
3057 | } | |
e0b92319 | 3058 | |
d4453b7a PB |
3059 | return LIBCALL_VALUE(mode); |
3060 | } | |
3061 | ||
e0b92319 | 3062 | /* Determine the amount of memory needed to store the possible return |
9f7bf991 RE |
3063 | registers of an untyped call. */ |
3064 | int | |
3065 | arm_apply_result_size (void) | |
3066 | { | |
3067 | int size = 16; | |
3068 | ||
3069 | if (TARGET_ARM) | |
3070 | { | |
3071 | if (TARGET_HARD_FLOAT_ABI) | |
3072 | { | |
3073 | if (TARGET_FPA) | |
3074 | size += 12; | |
3075 | if (TARGET_MAVERICK) | |
3076 | size += 8; | |
3077 | } | |
3078 | if (TARGET_IWMMXT_ABI) | |
3079 | size += 8; | |
3080 | } | |
3081 | ||
3082 | return size; | |
3083 | } | |
d4453b7a | 3084 | |
f5a1b0d2 | 3085 | /* Decide whether a type should be returned in memory (true) |
23668cf7 | 3086 | or in a register (false). This is called as the target hook |
81464b2c | 3087 | TARGET_RETURN_IN_MEMORY. */ |
23668cf7 | 3088 | static bool |
81464b2c | 3089 | arm_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
2b835d68 | 3090 | { |
dc0ba55a JT |
3091 | HOST_WIDE_INT size; |
3092 | ||
88f77cba JB |
3093 | size = int_size_in_bytes (type); |
3094 | ||
3095 | /* Vector values should be returned using ARM registers, not memory (unless | |
3096 | they're over 16 bytes, which will break since we only have four | |
3097 | call-clobbered registers to play with). */ | |
3098 | if (TREE_CODE (type) == VECTOR_TYPE) | |
3099 | return (size < 0 || size > (4 * UNITS_PER_WORD)); | |
3100 | ||
3dd7ab65 JB |
3101 | if (!AGGREGATE_TYPE_P (type) && |
3102 | !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) | |
3103 | /* All simple types are returned in registers. | |
3104 | For AAPCS, complex types are treated the same as aggregates. */ | |
d7d01975 | 3105 | return 0; |
dc0ba55a | 3106 | |
5848830f | 3107 | if (arm_abi != ARM_ABI_APCS) |
dc0ba55a | 3108 | { |
5848830f | 3109 | /* ATPCS and later return aggregate types in memory only if they are |
dc0ba55a JT |
3110 | larger than a word (or are variable size). */ |
3111 | return (size < 0 || size > UNITS_PER_WORD); | |
3112 | } | |
f676971a | 3113 | |
6bc82793 | 3114 | /* For the arm-wince targets we choose to be compatible with Microsoft's |
d5b7b3ae RE |
3115 | ARM and Thumb compilers, which always return aggregates in memory. */ |
3116 | #ifndef ARM_WINCE | |
e529bd42 NC |
3117 | /* All structures/unions bigger than one word are returned in memory. |
3118 | Also catch the case where int_size_in_bytes returns -1. In this case | |
6bc82793 | 3119 | the aggregate is either huge or of variable size, and in either case |
e529bd42 | 3120 | we will want to return it via memory and not in a register. */ |
dc0ba55a | 3121 | if (size < 0 || size > UNITS_PER_WORD) |
d7d01975 | 3122 | return 1; |
f676971a | 3123 | |
d7d01975 | 3124 | if (TREE_CODE (type) == RECORD_TYPE) |
2b835d68 RE |
3125 | { |
3126 | tree field; | |
3127 | ||
3a2ea258 RE |
3128 | /* For a struct the APCS says that we only return in a register |
3129 | if the type is 'integer like' and every addressable element | |
3130 | has an offset of zero. For practical purposes this means | |
3131 | that the structure can have at most one non bit-field element | |
3132 | and that this element must be the first one in the structure. */ | |
f676971a | 3133 | |
f5a1b0d2 NC |
3134 | /* Find the first field, ignoring non FIELD_DECL things which will |
3135 | have been created by C++. */ | |
3136 | for (field = TYPE_FIELDS (type); | |
3137 | field && TREE_CODE (field) != FIELD_DECL; | |
3138 | field = TREE_CHAIN (field)) | |
3139 | continue; | |
f676971a | 3140 | |
f5a1b0d2 | 3141 | if (field == NULL) |
9e291dbe | 3142 | return 0; /* An empty structure. Allowed by an extension to ANSI C. */ |
f5a1b0d2 | 3143 | |
d5b7b3ae RE |
3144 | /* Check that the first field is valid for returning in a register. */ |
3145 | ||
3146 | /* ... Floats are not allowed */ | |
9e291dbe | 3147 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3a2ea258 RE |
3148 | return 1; |
3149 | ||
d5b7b3ae RE |
3150 | /* ... Aggregates that are not themselves valid for returning in |
3151 | a register are not allowed. */ | |
81464b2c | 3152 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
3a2ea258 | 3153 | return 1; |
6f7ebcbb | 3154 | |
3a2ea258 RE |
3155 | /* Now check the remaining fields, if any. Only bitfields are allowed, |
3156 | since they are not addressable. */ | |
f5a1b0d2 NC |
3157 | for (field = TREE_CHAIN (field); |
3158 | field; | |
3159 | field = TREE_CHAIN (field)) | |
3160 | { | |
3161 | if (TREE_CODE (field) != FIELD_DECL) | |
3162 | continue; | |
f676971a | 3163 | |
5895f793 | 3164 | if (!DECL_BIT_FIELD_TYPE (field)) |
f5a1b0d2 NC |
3165 | return 1; |
3166 | } | |
2b835d68 RE |
3167 | |
3168 | return 0; | |
3169 | } | |
f676971a | 3170 | |
d7d01975 | 3171 | if (TREE_CODE (type) == UNION_TYPE) |
2b835d68 RE |
3172 | { |
3173 | tree field; | |
3174 | ||
3175 | /* Unions can be returned in registers if every element is | |
3176 | integral, or can be returned in an integer register. */ | |
f5a1b0d2 NC |
3177 | for (field = TYPE_FIELDS (type); |
3178 | field; | |
3179 | field = TREE_CHAIN (field)) | |
2b835d68 | 3180 | { |
f5a1b0d2 NC |
3181 | if (TREE_CODE (field) != FIELD_DECL) |
3182 | continue; | |
3183 | ||
6cc8c0b3 NC |
3184 | if (FLOAT_TYPE_P (TREE_TYPE (field))) |
3185 | return 1; | |
f676971a | 3186 | |
81464b2c | 3187 | if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE)) |
2b835d68 RE |
3188 | return 1; |
3189 | } | |
f676971a | 3190 | |
2b835d68 RE |
3191 | return 0; |
3192 | } | |
f676971a EC |
3193 | #endif /* not ARM_WINCE */ |
3194 | ||
d5b7b3ae | 3195 | /* Return all other types in memory. */ |
2b835d68 RE |
3196 | return 1; |
3197 | } | |
3198 | ||
d6b4baa4 | 3199 | /* Indicate whether or not words of a double are in big-endian order. */ |
3717da94 JT |
3200 | |
3201 | int | |
e32bac5b | 3202 | arm_float_words_big_endian (void) |
3717da94 | 3203 | { |
9b66ebb1 | 3204 | if (TARGET_MAVERICK) |
9b6b54e2 | 3205 | return 0; |
3717da94 JT |
3206 | |
3207 | /* For FPA, float words are always big-endian. For VFP, floats words | |
3208 | follow the memory system mode. */ | |
3209 | ||
9b66ebb1 | 3210 | if (TARGET_FPA) |
3717da94 | 3211 | { |
3717da94 JT |
3212 | return 1; |
3213 | } | |
3214 | ||
3215 | if (TARGET_VFP) | |
3216 | return (TARGET_BIG_END ? 1 : 0); | |
3217 | ||
3218 | return 1; | |
3219 | } | |
3220 | ||
82e9d970 PB |
3221 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
3222 | for a call to a function whose data type is FNTYPE. | |
3223 | For a library call, FNTYPE is NULL. */ | |
3224 | void | |
f676971a | 3225 | arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, |
e32bac5b RE |
3226 | rtx libname ATTRIBUTE_UNUSED, |
3227 | tree fndecl ATTRIBUTE_UNUSED) | |
82e9d970 PB |
3228 | { |
3229 | /* On the ARM, the offset starts at 0. */ | |
29e339b9 | 3230 | pcum->nregs = 0; |
5a9335ef | 3231 | pcum->iwmmxt_nregs = 0; |
5848830f | 3232 | pcum->can_split = true; |
f676971a | 3233 | |
5a9335ef NC |
3234 | /* Varargs vectors are treated the same as long long. |
3235 | named_count avoids having to change the way arm handles 'named' */ | |
3236 | pcum->named_count = 0; | |
3237 | pcum->nargs = 0; | |
3238 | ||
3239 | if (TARGET_REALLY_IWMMXT && fntype) | |
3240 | { | |
3241 | tree fn_arg; | |
3242 | ||
3243 | for (fn_arg = TYPE_ARG_TYPES (fntype); | |
3244 | fn_arg; | |
3245 | fn_arg = TREE_CHAIN (fn_arg)) | |
3246 | pcum->named_count += 1; | |
3247 | ||
3248 | if (! pcum->named_count) | |
3249 | pcum->named_count = INT_MAX; | |
3250 | } | |
82e9d970 PB |
3251 | } |
3252 | ||
5848830f PB |
3253 | |
3254 | /* Return true if mode/type need doubleword alignment. */ | |
3255 | bool | |
3256 | arm_needs_doubleword_align (enum machine_mode mode, tree type) | |
3257 | { | |
65a939f7 PB |
3258 | return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY |
3259 | || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); | |
5848830f PB |
3260 | } |
3261 | ||
3262 | ||
82e9d970 PB |
3263 | /* Determine where to put an argument to a function. |
3264 | Value is zero to push the argument on the stack, | |
3265 | or a hard register in which to store the argument. | |
3266 | ||
3267 | MODE is the argument's machine mode. | |
3268 | TYPE is the data type of the argument (as a tree). | |
3269 | This is null for libcalls where that information may | |
3270 | not be available. | |
3271 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
3272 | the preceding args and about the function being called. | |
3273 | NAMED is nonzero if this argument is a named parameter | |
3274 | (otherwise it is an extra parameter matching an ellipsis). */ | |
1d6e90ac | 3275 | |
82e9d970 | 3276 | rtx |
e32bac5b | 3277 | arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, |
5848830f | 3278 | tree type, int named) |
82e9d970 | 3279 | { |
5848830f PB |
3280 | int nregs; |
3281 | ||
3282 | /* Varargs vectors are treated the same as long long. | |
3283 | named_count avoids having to change the way arm handles 'named' */ | |
3284 | if (TARGET_IWMMXT_ABI | |
f676971a | 3285 | && arm_vector_mode_supported_p (mode) |
5848830f | 3286 | && pcum->named_count > pcum->nargs + 1) |
5a9335ef | 3287 | { |
5848830f PB |
3288 | if (pcum->iwmmxt_nregs <= 9) |
3289 | return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); | |
3290 | else | |
5a9335ef | 3291 | { |
5848830f PB |
3292 | pcum->can_split = false; |
3293 | return NULL_RTX; | |
5a9335ef | 3294 | } |
5a9335ef NC |
3295 | } |
3296 | ||
5848830f PB |
3297 | /* Put doubleword aligned quantities in even register pairs. */ |
3298 | if (pcum->nregs & 1 | |
3299 | && ARM_DOUBLEWORD_ALIGN | |
3300 | && arm_needs_doubleword_align (mode, type)) | |
3301 | pcum->nregs++; | |
3302 | ||
82e9d970 | 3303 | if (mode == VOIDmode) |
25a65198 RS |
3304 | /* Pick an arbitrary value for operand 2 of the call insn. */ |
3305 | return const0_rtx; | |
5848830f | 3306 | |
666c27b9 | 3307 | /* Only allow splitting an arg between regs and memory if all preceding |
5848830f PB |
3308 | args were allocated to regs. For args passed by reference we only count |
3309 | the reference pointer. */ | |
3310 | if (pcum->can_split) | |
3311 | nregs = 1; | |
3312 | else | |
3313 | nregs = ARM_NUM_REGS2 (mode, type); | |
3314 | ||
3315 | if (!named || pcum->nregs + nregs > NUM_ARG_REGS) | |
82e9d970 | 3316 | return NULL_RTX; |
f676971a | 3317 | |
82e9d970 PB |
3318 | return gen_rtx_REG (mode, pcum->nregs); |
3319 | } | |
1741620c | 3320 | |
78a52f11 RH |
3321 | static int |
3322 | arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, | |
3323 | tree type, bool named ATTRIBUTE_UNUSED) | |
3324 | { | |
3325 | int nregs = pcum->nregs; | |
3326 | ||
88f77cba | 3327 | if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode)) |
78a52f11 RH |
3328 | return 0; |
3329 | ||
3330 | if (NUM_ARG_REGS > nregs | |
3331 | && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) | |
3332 | && pcum->can_split) | |
3333 | return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
1741620c JD |
3338 | /* Variable sized types are passed by reference. This is a GCC |
3339 | extension to the ARM ABI. */ | |
3340 | ||
8cd5a4e0 RH |
3341 | static bool |
3342 | arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
3343 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
586de218 | 3344 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1741620c JD |
3345 | { |
3346 | return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; | |
3347 | } | |
82e9d970 | 3348 | \f |
c27ba912 DM |
3349 | /* Encode the current state of the #pragma [no_]long_calls. */ |
3350 | typedef enum | |
82e9d970 | 3351 | { |
6fc0bb99 | 3352 | OFF, /* No #pragma [no_]long_calls is in effect. */ |
c27ba912 DM |
3353 | LONG, /* #pragma long_calls is in effect. */ |
3354 | SHORT /* #pragma no_long_calls is in effect. */ | |
3355 | } arm_pragma_enum; | |
82e9d970 | 3356 | |
c27ba912 | 3357 | static arm_pragma_enum arm_pragma_long_calls = OFF; |
82e9d970 | 3358 | |
8b97c5f8 | 3359 | void |
e32bac5b | 3360 | arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
82e9d970 | 3361 | { |
8b97c5f8 ZW |
3362 | arm_pragma_long_calls = LONG; |
3363 | } | |
3364 | ||
3365 | void | |
e32bac5b | 3366 | arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3367 | { |
3368 | arm_pragma_long_calls = SHORT; | |
3369 | } | |
3370 | ||
3371 | void | |
e32bac5b | 3372 | arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) |
8b97c5f8 ZW |
3373 | { |
3374 | arm_pragma_long_calls = OFF; | |
82e9d970 PB |
3375 | } |
3376 | \f | |
91d231cb JM |
3377 | /* Table of machine attributes. */ |
3378 | const struct attribute_spec arm_attribute_table[] = | |
82e9d970 | 3379 | { |
91d231cb | 3380 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
82e9d970 PB |
3381 | /* Function calls made to this symbol must be done indirectly, because |
3382 | it may lie outside of the 26 bit addressing range of a normal function | |
3383 | call. */ | |
91d231cb | 3384 | { "long_call", 0, 0, false, true, true, NULL }, |
82e9d970 PB |
3385 | /* Whereas these functions are always known to reside within the 26 bit |
3386 | addressing range. */ | |
91d231cb | 3387 | { "short_call", 0, 0, false, true, true, NULL }, |
f676971a | 3388 | /* Interrupt Service Routines have special prologue and epilogue requirements. */ |
91d231cb JM |
3389 | { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, |
3390 | { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, | |
3391 | { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
3392 | #ifdef ARM_PE | |
3393 | /* ARM/PE has three new attributes: | |
3394 | interfacearm - ? | |
3395 | dllexport - for exporting a function/variable that will live in a dll | |
3396 | dllimport - for importing a function/variable from a dll | |
3397 | ||
3398 | Microsoft allows multiple declspecs in one __declspec, separating | |
3399 | them with spaces. We do NOT support this. Instead, use __declspec | |
3400 | multiple times. | |
3401 | */ | |
3402 | { "dllimport", 0, 0, true, false, false, NULL }, | |
3403 | { "dllexport", 0, 0, true, false, false, NULL }, | |
3404 | { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, | |
b2ca3702 MM |
3405 | #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES |
3406 | { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, | |
3407 | { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, | |
04fb56d5 | 3408 | { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, |
91d231cb JM |
3409 | #endif |
3410 | { NULL, 0, 0, false, false, false, NULL } | |
3411 | }; | |
6d3d9133 | 3412 | |
91d231cb JM |
3413 | /* Handle an attribute requiring a FUNCTION_DECL; |
3414 | arguments as in struct attribute_spec.handler. */ | |
3415 | static tree | |
e32bac5b RE |
3416 | arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, |
3417 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
91d231cb JM |
3418 | { |
3419 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3420 | { | |
29d08eba JM |
3421 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
3422 | name); | |
91d231cb JM |
3423 | *no_add_attrs = true; |
3424 | } | |
3425 | ||
3426 | return NULL_TREE; | |
3427 | } | |
3428 | ||
3429 | /* Handle an "interrupt" or "isr" attribute; | |
3430 | arguments as in struct attribute_spec.handler. */ | |
3431 | static tree | |
e32bac5b RE |
3432 | arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, |
3433 | bool *no_add_attrs) | |
91d231cb JM |
3434 | { |
3435 | if (DECL_P (*node)) | |
3436 | { | |
3437 | if (TREE_CODE (*node) != FUNCTION_DECL) | |
3438 | { | |
29d08eba JM |
3439 | warning (OPT_Wattributes, "%qE attribute only applies to functions", |
3440 | name); | |
91d231cb JM |
3441 | *no_add_attrs = true; |
3442 | } | |
3443 | /* FIXME: the argument if any is checked for type attributes; | |
3444 | should it be checked for decl ones? */ | |
3445 | } | |
3446 | else | |
3447 | { | |
3448 | if (TREE_CODE (*node) == FUNCTION_TYPE | |
3449 | || TREE_CODE (*node) == METHOD_TYPE) | |
3450 | { | |
3451 | if (arm_isr_value (args) == ARM_FT_UNKNOWN) | |
3452 | { | |
29d08eba JM |
3453 | warning (OPT_Wattributes, "%qE attribute ignored", |
3454 | name); | |
91d231cb JM |
3455 | *no_add_attrs = true; |
3456 | } | |
3457 | } | |
3458 | else if (TREE_CODE (*node) == POINTER_TYPE | |
3459 | && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE | |
3460 | || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) | |
3461 | && arm_isr_value (args) != ARM_FT_UNKNOWN) | |
3462 | { | |
8dd16ecc | 3463 | *node = build_variant_type_copy (*node); |
1d6e90ac NC |
3464 | TREE_TYPE (*node) = build_type_attribute_variant |
3465 | (TREE_TYPE (*node), | |
3466 | tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); | |
91d231cb JM |
3467 | *no_add_attrs = true; |
3468 | } | |
3469 | else | |
3470 | { | |
3471 | /* Possibly pass this attribute on from the type to a decl. */ | |
3472 | if (flags & ((int) ATTR_FLAG_DECL_NEXT | |
3473 | | (int) ATTR_FLAG_FUNCTION_NEXT | |
3474 | | (int) ATTR_FLAG_ARRAY_NEXT)) | |
3475 | { | |
3476 | *no_add_attrs = true; | |
3477 | return tree_cons (name, args, NULL_TREE); | |
3478 | } | |
3479 | else | |
3480 | { | |
29d08eba JM |
3481 | warning (OPT_Wattributes, "%qE attribute ignored", |
3482 | name); | |
91d231cb JM |
3483 | } |
3484 | } | |
3485 | } | |
3486 | ||
3487 | return NULL_TREE; | |
82e9d970 PB |
3488 | } |
3489 | ||
7bff66a7 | 3490 | #if TARGET_DLLIMPORT_DECL_ATTRIBUTES |
04fb56d5 MM |
3491 | /* Handle the "notshared" attribute. This attribute is another way of |
3492 | requesting hidden visibility. ARM's compiler supports | |
3493 | "__declspec(notshared)"; we support the same thing via an | |
3494 | attribute. */ | |
3495 | ||
3496 | static tree | |
e0b92319 NC |
3497 | arm_handle_notshared_attribute (tree *node, |
3498 | tree name ATTRIBUTE_UNUSED, | |
3499 | tree args ATTRIBUTE_UNUSED, | |
3500 | int flags ATTRIBUTE_UNUSED, | |
04fb56d5 MM |
3501 | bool *no_add_attrs) |
3502 | { | |
3503 | tree decl = TYPE_NAME (*node); | |
3504 | ||
3505 | if (decl) | |
3506 | { | |
3507 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
3508 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
3509 | *no_add_attrs = false; | |
3510 | } | |
3511 | return NULL_TREE; | |
3512 | } | |
7bff66a7 | 3513 | #endif |
04fb56d5 | 3514 | |
82e9d970 PB |
3515 | /* Return 0 if the attributes for two types are incompatible, 1 if they |
3516 | are compatible, and 2 if they are nearly compatible (which causes a | |
3517 | warning to be generated). */ | |
8d8e52be | 3518 | static int |
3101faab | 3519 | arm_comp_type_attributes (const_tree type1, const_tree type2) |
82e9d970 | 3520 | { |
1cb8d58a | 3521 | int l1, l2, s1, s2; |
f676971a | 3522 | |
82e9d970 PB |
3523 | /* Check for mismatch of non-default calling convention. */ |
3524 | if (TREE_CODE (type1) != FUNCTION_TYPE) | |
3525 | return 1; | |
3526 | ||
3527 | /* Check for mismatched call attributes. */ | |
1cb8d58a NC |
3528 | l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; |
3529 | l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
3530 | s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; | |
3531 | s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; | |
bd7fc26f NC |
3532 | |
3533 | /* Only bother to check if an attribute is defined. */ | |
3534 | if (l1 | l2 | s1 | s2) | |
3535 | { | |
3536 | /* If one type has an attribute, the other must have the same attribute. */ | |
1cb8d58a | 3537 | if ((l1 != l2) || (s1 != s2)) |
bd7fc26f | 3538 | return 0; |
82e9d970 | 3539 | |
bd7fc26f NC |
3540 | /* Disallow mixed attributes. */ |
3541 | if ((l1 & s2) || (l2 & s1)) | |
3542 | return 0; | |
3543 | } | |
f676971a | 3544 | |
6d3d9133 NC |
3545 | /* Check for mismatched ISR attribute. */ |
3546 | l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; | |
3547 | if (! l1) | |
3548 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; | |
3549 | l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; | |
3550 | if (! l2) | |
3551 | l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; | |
3552 | if (l1 != l2) | |
3553 | return 0; | |
3554 | ||
bd7fc26f | 3555 | return 1; |
82e9d970 PB |
3556 | } |
3557 | ||
c27ba912 DM |
3558 | /* Assigns default attributes to newly defined type. This is used to |
3559 | set short_call/long_call attributes for function types of | |
3560 | functions defined inside corresponding #pragma scopes. */ | |
8d8e52be | 3561 | static void |
e32bac5b | 3562 | arm_set_default_type_attributes (tree type) |
c27ba912 DM |
3563 | { |
3564 | /* Add __attribute__ ((long_call)) to all functions, when | |
3565 | inside #pragma long_calls or __attribute__ ((short_call)), | |
3566 | when inside #pragma no_long_calls. */ | |
3567 | if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
3568 | { | |
3569 | tree type_attr_list, attr_name; | |
3570 | type_attr_list = TYPE_ATTRIBUTES (type); | |
3571 | ||
3572 | if (arm_pragma_long_calls == LONG) | |
3573 | attr_name = get_identifier ("long_call"); | |
3574 | else if (arm_pragma_long_calls == SHORT) | |
3575 | attr_name = get_identifier ("short_call"); | |
3576 | else | |
3577 | return; | |
3578 | ||
3579 | type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); | |
3580 | TYPE_ATTRIBUTES (type) = type_attr_list; | |
3581 | } | |
3582 | } | |
3583 | \f | |
25a65198 RS |
3584 | /* Return true if DECL is known to be linked into section SECTION. */ |
3585 | ||
3586 | static bool | |
3587 | arm_function_in_section_p (tree decl, section *section) | |
c27ba912 | 3588 | { |
25a65198 RS |
3589 | /* We can only be certain about functions defined in the same |
3590 | compilation unit. */ | |
3591 | if (!TREE_STATIC (decl)) | |
3592 | return false; | |
c27ba912 | 3593 | |
25a65198 RS |
3594 | /* Make sure that SYMBOL always binds to the definition in this |
3595 | compilation unit. */ | |
3596 | if (!targetm.binds_local_p (decl)) | |
3597 | return false; | |
c27ba912 | 3598 | |
25a65198 RS |
3599 | /* If DECL_SECTION_NAME is set, assume it is trustworthy. */ |
3600 | if (!DECL_SECTION_NAME (decl)) | |
3601 | { | |
25a65198 RS |
3602 | /* Make sure that we will not create a unique section for DECL. */ |
3603 | if (flag_function_sections || DECL_ONE_ONLY (decl)) | |
3604 | return false; | |
3605 | } | |
3606 | ||
3607 | return function_section (decl) == section; | |
c27ba912 DM |
3608 | } |
3609 | ||
a50aa827 | 3610 | /* Return nonzero if a 32-bit "long_call" should be generated for |
25a65198 RS |
3611 | a call from the current function to DECL. We generate a long_call |
3612 | if the function: | |
c27ba912 DM |
3613 | |
3614 | a. has an __attribute__((long call)) | |
3615 | or b. is within the scope of a #pragma long_calls | |
3616 | or c. the -mlong-calls command line switch has been specified | |
3617 | ||
3618 | However we do not generate a long call if the function: | |
f676971a | 3619 | |
c27ba912 DM |
3620 | d. has an __attribute__ ((short_call)) |
3621 | or e. is inside the scope of a #pragma no_long_calls | |
25a65198 | 3622 | or f. is defined in the same section as the current function. */ |
c27ba912 | 3623 | |
25a65198 RS |
3624 | bool |
3625 | arm_is_long_call_p (tree decl) | |
3626 | { | |
3627 | tree attrs; | |
c27ba912 | 3628 | |
25a65198 RS |
3629 | if (!decl) |
3630 | return TARGET_LONG_CALLS; | |
c27ba912 | 3631 | |
25a65198 RS |
3632 | attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl)); |
3633 | if (lookup_attribute ("short_call", attrs)) | |
3634 | return false; | |
c27ba912 | 3635 | |
25a65198 RS |
3636 | /* For "f", be conservative, and only cater for cases in which the |
3637 | whole of the current function is placed in the same section. */ | |
3638 | if (!flag_reorder_blocks_and_partition | |
b3a796bc | 3639 | && TREE_CODE (decl) == FUNCTION_DECL |
25a65198 RS |
3640 | && arm_function_in_section_p (decl, current_function_section ())) |
3641 | return false; | |
a77655b1 | 3642 | |
25a65198 RS |
3643 | if (lookup_attribute ("long_call", attrs)) |
3644 | return true; | |
f676971a | 3645 | |
25a65198 | 3646 | return TARGET_LONG_CALLS; |
c27ba912 | 3647 | } |
f99fce0c | 3648 | |
825dda42 | 3649 | /* Return nonzero if it is ok to make a tail-call to DECL. */ |
4977bab6 | 3650 | static bool |
e32bac5b | 3651 | arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
f99fce0c | 3652 | { |
5b3e6663 | 3653 | unsigned long func_type; |
f99fce0c | 3654 | |
5a9335ef NC |
3655 | if (cfun->machine->sibcall_blocked) |
3656 | return false; | |
3657 | ||
f99fce0c RE |
3658 | /* Never tailcall something for which we have no decl, or if we |
3659 | are in Thumb mode. */ | |
3660 | if (decl == NULL || TARGET_THUMB) | |
4977bab6 | 3661 | return false; |
f99fce0c | 3662 | |
9403b7f7 RS |
3663 | /* The PIC register is live on entry to VxWorks PLT entries, so we |
3664 | must make the call before restoring the PIC register. */ | |
3665 | if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl)) | |
3666 | return false; | |
3667 | ||
f99fce0c | 3668 | /* Cannot tail-call to long calls, since these are out of range of |
25a65198 RS |
3669 | a branch instruction. */ |
3670 | if (arm_is_long_call_p (decl)) | |
4977bab6 | 3671 | return false; |
f99fce0c RE |
3672 | |
3673 | /* If we are interworking and the function is not declared static | |
f676971a | 3674 | then we can't tail-call it unless we know that it exists in this |
f99fce0c | 3675 | compilation unit (since it might be a Thumb routine). */ |
5895f793 | 3676 | if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) |
4977bab6 | 3677 | return false; |
f99fce0c | 3678 | |
5b3e6663 | 3679 | func_type = arm_current_func_type (); |
6d3d9133 | 3680 | /* Never tailcall from an ISR routine - it needs a special exit sequence. */ |
5b3e6663 PB |
3681 | if (IS_INTERRUPT (func_type)) |
3682 | return false; | |
3683 | ||
3684 | /* Never tailcall if function may be called with a misaligned SP. */ | |
3685 | if (IS_STACKALIGN (func_type)) | |
4977bab6 | 3686 | return false; |
6d3d9133 | 3687 | |
f99fce0c | 3688 | /* Everything else is ok. */ |
4977bab6 | 3689 | return true; |
f99fce0c RE |
3690 | } |
3691 | ||
82e9d970 | 3692 | \f |
6b990f6b RE |
3693 | /* Addressing mode support functions. */ |
3694 | ||
0b4be7de | 3695 | /* Return nonzero if X is a legitimate immediate operand when compiling |
020a4035 | 3696 | for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ |
32de079a | 3697 | int |
e32bac5b | 3698 | legitimate_pic_operand_p (rtx x) |
32de079a | 3699 | { |
020a4035 RE |
3700 | if (GET_CODE (x) == SYMBOL_REF |
3701 | || (GET_CODE (x) == CONST | |
3702 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3703 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
32de079a RE |
3704 | return 0; |
3705 | ||
3706 | return 1; | |
3707 | } | |
3708 | ||
9403b7f7 RS |
3709 | /* Record that the current function needs a PIC register. Initialize |
3710 | cfun->machine->pic_reg if we have not already done so. */ | |
3711 | ||
3712 | static void | |
3713 | require_pic_register (void) | |
3714 | { | |
3715 | /* A lot of the logic here is made obscure by the fact that this | |
3716 | routine gets called as part of the rtx cost estimation process. | |
3717 | We don't want those calls to affect any assumptions about the real | |
3718 | function; and further, we can't call entry_of_function() until we | |
3719 | start the real expansion process. */ | |
e3b5732b | 3720 | if (!crtl->uses_pic_offset_table) |
9403b7f7 | 3721 | { |
b3a13419 | 3722 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
3723 | if (arm_pic_register != INVALID_REGNUM) |
3724 | { | |
6d2538f5 JB |
3725 | if (!cfun->machine->pic_reg) |
3726 | cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); | |
9403b7f7 RS |
3727 | |
3728 | /* Play games to avoid marking the function as needing pic | |
3729 | if we are being called as part of the cost-estimation | |
3730 | process. */ | |
04ef80ce | 3731 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
e3b5732b | 3732 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3733 | } |
3734 | else | |
3735 | { | |
3736 | rtx seq; | |
3737 | ||
6d2538f5 JB |
3738 | if (!cfun->machine->pic_reg) |
3739 | cfun->machine->pic_reg = gen_reg_rtx (Pmode); | |
9403b7f7 RS |
3740 | |
3741 | /* Play games to avoid marking the function as needing pic | |
3742 | if we are being called as part of the cost-estimation | |
3743 | process. */ | |
04ef80ce | 3744 | if (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl) |
9403b7f7 | 3745 | { |
e3b5732b | 3746 | crtl->uses_pic_offset_table = 1; |
9403b7f7 RS |
3747 | start_sequence (); |
3748 | ||
3749 | arm_load_pic_register (0UL); | |
3750 | ||
3751 | seq = get_insns (); | |
3752 | end_sequence (); | |
af618949 MM |
3753 | /* We can be called during expansion of PHI nodes, where |
3754 | we can't yet emit instructions directly in the final | |
3755 | insn stream. Queue the insns on the entry edge, they will | |
3756 | be committed after everything else is expanded. */ | |
3757 | insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR)); | |
9403b7f7 RS |
3758 | } |
3759 | } | |
3760 | } | |
3761 | } | |
3762 | ||
32de079a | 3763 | rtx |
e32bac5b | 3764 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
32de079a | 3765 | { |
a3c48721 RE |
3766 | if (GET_CODE (orig) == SYMBOL_REF |
3767 | || GET_CODE (orig) == LABEL_REF) | |
32de079a RE |
3768 | { |
3769 | rtx pic_ref, address; | |
3770 | rtx insn; | |
3771 | int subregs = 0; | |
3772 | ||
9403b7f7 RS |
3773 | /* If this function doesn't have a pic register, create one now. */ |
3774 | require_pic_register (); | |
020a4035 | 3775 | |
32de079a RE |
3776 | if (reg == 0) |
3777 | { | |
b3a13419 | 3778 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3779 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3780 | |
3781 | subregs = 1; | |
3782 | } | |
3783 | ||
32de079a RE |
3784 | if (subregs) |
3785 | address = gen_reg_rtx (Pmode); | |
3786 | else | |
3787 | address = reg; | |
3788 | ||
4bec9f7d NC |
3789 | if (TARGET_ARM) |
3790 | emit_insn (gen_pic_load_addr_arm (address, orig)); | |
5b3e6663 PB |
3791 | else if (TARGET_THUMB2) |
3792 | emit_insn (gen_pic_load_addr_thumb2 (address, orig)); | |
3793 | else /* TARGET_THUMB1 */ | |
3794 | emit_insn (gen_pic_load_addr_thumb1 (address, orig)); | |
32de079a | 3795 | |
9403b7f7 RS |
3796 | /* VxWorks does not impose a fixed gap between segments; the run-time |
3797 | gap can be different from the object-file gap. We therefore can't | |
3798 | use GOTOFF unless we are absolutely sure that the symbol is in the | |
3799 | same segment as the GOT. Unfortunately, the flexibility of linker | |
3800 | scripts means that we can't be sure of that in general, so assume | |
3801 | that GOTOFF is never valid on VxWorks. */ | |
14f583b8 | 3802 | if ((GET_CODE (orig) == LABEL_REF |
f676971a | 3803 | || (GET_CODE (orig) == SYMBOL_REF && |
94428622 | 3804 | SYMBOL_REF_LOCAL_P (orig))) |
9403b7f7 RS |
3805 | && NEED_GOT_RELOC |
3806 | && !TARGET_VXWORKS_RTP) | |
020a4035 | 3807 | pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); |
a3c48721 RE |
3808 | else |
3809 | { | |
542a8afa | 3810 | pic_ref = gen_const_mem (Pmode, |
020a4035 | 3811 | gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, |
542a8afa | 3812 | address)); |
a3c48721 RE |
3813 | } |
3814 | ||
32de079a | 3815 | insn = emit_move_insn (reg, pic_ref); |
96a3900d | 3816 | |
32de079a RE |
3817 | /* Put a REG_EQUAL note on this insn, so that it can be optimized |
3818 | by loop. */ | |
bd94cb6e SB |
3819 | set_unique_reg_note (insn, REG_EQUAL, orig); |
3820 | ||
32de079a RE |
3821 | return reg; |
3822 | } | |
3823 | else if (GET_CODE (orig) == CONST) | |
3824 | { | |
3825 | rtx base, offset; | |
3826 | ||
3827 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
020a4035 | 3828 | && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) |
32de079a RE |
3829 | return orig; |
3830 | ||
f67358da | 3831 | /* Handle the case where we have: const (UNSPEC_TLS). */ |
d3585b76 DJ |
3832 | if (GET_CODE (XEXP (orig, 0)) == UNSPEC |
3833 | && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) | |
3834 | return orig; | |
3835 | ||
f67358da PB |
3836 | /* Handle the case where we have: |
3837 | const (plus (UNSPEC_TLS) (ADDEND)). The ADDEND must be a | |
3838 | CONST_INT. */ | |
3839 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
3840 | && GET_CODE (XEXP (XEXP (orig, 0), 0)) == UNSPEC | |
3841 | && XINT (XEXP (XEXP (orig, 0), 0), 1) == UNSPEC_TLS) | |
3842 | { | |
3843 | gcc_assert (GET_CODE (XEXP (XEXP (orig, 0), 1)) == CONST_INT); | |
3844 | return orig; | |
3845 | } | |
3846 | ||
32de079a RE |
3847 | if (reg == 0) |
3848 | { | |
b3a13419 | 3849 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3850 | reg = gen_reg_rtx (Pmode); |
32de079a RE |
3851 | } |
3852 | ||
e6d29d15 | 3853 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); |
e0b92319 | 3854 | |
e6d29d15 NS |
3855 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); |
3856 | offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
3857 | base == reg ? 0 : reg); | |
32de079a RE |
3858 | |
3859 | if (GET_CODE (offset) == CONST_INT) | |
3860 | { | |
3861 | /* The base register doesn't really matter, we only want to | |
3862 | test the index for the appropriate mode. */ | |
1e1ab407 | 3863 | if (!arm_legitimate_index_p (mode, offset, SET, 0)) |
6b990f6b | 3864 | { |
b3a13419 | 3865 | gcc_assert (can_create_pseudo_p ()); |
e6d29d15 | 3866 | offset = force_reg (Pmode, offset); |
6b990f6b | 3867 | } |
32de079a | 3868 | |
32de079a | 3869 | if (GET_CODE (offset) == CONST_INT) |
ed8908e7 | 3870 | return plus_constant (base, INTVAL (offset)); |
32de079a RE |
3871 | } |
3872 | ||
3873 | if (GET_MODE_SIZE (mode) > 4 | |
3874 | && (GET_MODE_CLASS (mode) == MODE_INT | |
3875 | || TARGET_SOFT_FLOAT)) | |
3876 | { | |
3877 | emit_insn (gen_addsi3 (reg, base, offset)); | |
3878 | return reg; | |
3879 | } | |
3880 | ||
43cffd11 | 3881 | return gen_rtx_PLUS (Pmode, base, offset); |
32de079a | 3882 | } |
32de079a RE |
3883 | |
3884 | return orig; | |
3885 | } | |
3886 | ||
57934c39 | 3887 | |
5b3e6663 | 3888 | /* Find a spare register to use during the prolog of a function. */ |
57934c39 PB |
3889 | |
3890 | static int | |
b279b20a | 3891 | thumb_find_work_register (unsigned long pushed_regs_mask) |
57934c39 PB |
3892 | { |
3893 | int reg; | |
3894 | ||
b279b20a NC |
3895 | /* Check the argument registers first as these are call-used. The |
3896 | register allocation order means that sometimes r3 might be used | |
3897 | but earlier argument registers might not, so check them all. */ | |
3898 | for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) | |
6fb5fa3c | 3899 | if (!df_regs_ever_live_p (reg)) |
b279b20a NC |
3900 | return reg; |
3901 | ||
3902 | /* Before going on to check the call-saved registers we can try a couple | |
3903 | more ways of deducing that r3 is available. The first is when we are | |
3904 | pushing anonymous arguments onto the stack and we have less than 4 | |
3905 | registers worth of fixed arguments(*). In this case r3 will be part of | |
3906 | the variable argument list and so we can be sure that it will be | |
3907 | pushed right at the start of the function. Hence it will be available | |
3908 | for the rest of the prologue. | |
38173d38 | 3909 | (*): ie crtl->args.pretend_args_size is greater than 0. */ |
b279b20a | 3910 | if (cfun->machine->uses_anonymous_args |
38173d38 | 3911 | && crtl->args.pretend_args_size > 0) |
57934c39 PB |
3912 | return LAST_ARG_REGNUM; |
3913 | ||
b279b20a NC |
3914 | /* The other case is when we have fixed arguments but less than 4 registers |
3915 | worth. In this case r3 might be used in the body of the function, but | |
3916 | it is not being used to convey an argument into the function. In theory | |
38173d38 | 3917 | we could just check crtl->args.size to see how many bytes are |
b279b20a NC |
3918 | being passed in argument registers, but it seems that it is unreliable. |
3919 | Sometimes it will have the value 0 when in fact arguments are being | |
3920 | passed. (See testcase execute/20021111-1.c for an example). So we also | |
3921 | check the args_info.nregs field as well. The problem with this field is | |
3922 | that it makes no allowances for arguments that are passed to the | |
3923 | function but which are not used. Hence we could miss an opportunity | |
3924 | when a function has an unused argument in r3. But it is better to be | |
3925 | safe than to be sorry. */ | |
3926 | if (! cfun->machine->uses_anonymous_args | |
38173d38 JH |
3927 | && crtl->args.size >= 0 |
3928 | && crtl->args.size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) | |
f6d2671e | 3929 | && crtl->args.info.nregs < 4) |
b279b20a | 3930 | return LAST_ARG_REGNUM; |
e0b92319 | 3931 | |
b279b20a NC |
3932 | /* Otherwise look for a call-saved register that is going to be pushed. */ |
3933 | for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) | |
3934 | if (pushed_regs_mask & (1 << reg)) | |
57934c39 PB |
3935 | return reg; |
3936 | ||
5b3e6663 PB |
3937 | if (TARGET_THUMB2) |
3938 | { | |
3939 | /* Thumb-2 can use high regs. */ | |
3940 | for (reg = FIRST_HI_REGNUM; reg < 15; reg ++) | |
3941 | if (pushed_regs_mask & (1 << reg)) | |
3942 | return reg; | |
3943 | } | |
b279b20a NC |
3944 | /* Something went wrong - thumb_compute_save_reg_mask() |
3945 | should have arranged for a suitable register to be pushed. */ | |
e6d29d15 | 3946 | gcc_unreachable (); |
57934c39 PB |
3947 | } |
3948 | ||
f16fe45f | 3949 | static GTY(()) int pic_labelno; |
876f13b0 | 3950 | |
fe013435 PB |
3951 | /* Generate code to load the PIC register. In thumb mode SCRATCH is a |
3952 | low register. */ | |
876f13b0 | 3953 | |
32de079a | 3954 | void |
e55ef7f4 | 3955 | arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) |
32de079a | 3956 | { |
f9bd1a89 | 3957 | rtx l1, labelno, pic_tmp, pic_rtx, pic_reg; |
32de079a | 3958 | |
e3b5732b | 3959 | if (crtl->uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) |
32de079a RE |
3960 | return; |
3961 | ||
e6d29d15 | 3962 | gcc_assert (flag_pic); |
32de079a | 3963 | |
9403b7f7 RS |
3964 | pic_reg = cfun->machine->pic_reg; |
3965 | if (TARGET_VXWORKS_RTP) | |
3966 | { | |
3967 | pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); | |
3968 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); | |
3969 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); | |
43cffd11 | 3970 | |
9403b7f7 | 3971 | emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg))); |
f676971a | 3972 | |
9403b7f7 RS |
3973 | pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); |
3974 | emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp)); | |
4bec9f7d | 3975 | } |
9403b7f7 | 3976 | else |
5b3e6663 | 3977 | { |
9403b7f7 RS |
3978 | /* We use an UNSPEC rather than a LABEL_REF because this label |
3979 | never appears in the code stream. */ | |
3980 | ||
3981 | labelno = GEN_INT (pic_labelno++); | |
3982 | l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
3983 | l1 = gen_rtx_CONST (VOIDmode, l1); | |
3984 | ||
9403b7f7 RS |
3985 | /* On the ARM the PC register contains 'dot + 8' at the time of the |
3986 | addition, on the Thumb it is 'dot + 4'. */ | |
f9bd1a89 RS |
3987 | pic_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4); |
3988 | pic_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, pic_rtx), | |
3989 | UNSPEC_GOTSYM_OFF); | |
9403b7f7 RS |
3990 | pic_rtx = gen_rtx_CONST (Pmode, pic_rtx); |
3991 | ||
3992 | if (TARGET_ARM) | |
5b3e6663 | 3993 | { |
9403b7f7 RS |
3994 | emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx)); |
3995 | emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno)); | |
5b3e6663 | 3996 | } |
9403b7f7 RS |
3997 | else if (TARGET_THUMB2) |
3998 | { | |
3999 | /* Thumb-2 only allows very limited access to the PC. Calculate the | |
4000 | address in a temporary register. */ | |
4001 | if (arm_pic_register != INVALID_REGNUM) | |
4002 | { | |
4003 | pic_tmp = gen_rtx_REG (SImode, | |
4004 | thumb_find_work_register (saved_regs)); | |
4005 | } | |
4006 | else | |
4007 | { | |
b3a13419 | 4008 | gcc_assert (can_create_pseudo_p ()); |
9403b7f7 RS |
4009 | pic_tmp = gen_reg_rtx (Pmode); |
4010 | } | |
5b3e6663 | 4011 | |
9403b7f7 RS |
4012 | emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx)); |
4013 | emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno)); | |
4014 | emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp)); | |
4015 | } | |
4016 | else /* TARGET_THUMB1 */ | |
876f13b0 | 4017 | { |
9403b7f7 RS |
4018 | if (arm_pic_register != INVALID_REGNUM |
4019 | && REGNO (pic_reg) > LAST_LO_REGNUM) | |
4020 | { | |
4021 | /* We will have pushed the pic register, so we should always be | |
4022 | able to find a work register. */ | |
4023 | pic_tmp = gen_rtx_REG (SImode, | |
4024 | thumb_find_work_register (saved_regs)); | |
4025 | emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx)); | |
4026 | emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); | |
4027 | } | |
4028 | else | |
4029 | emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx)); | |
4030 | emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno)); | |
876f13b0 | 4031 | } |
4bec9f7d | 4032 | } |
32de079a | 4033 | |
32de079a RE |
4034 | /* Need to emit this whether or not we obey regdecls, |
4035 | since setjmp/longjmp can cause life info to screw up. */ | |
c41c1387 | 4036 | emit_use (pic_reg); |
32de079a RE |
4037 | } |
4038 | ||
876f13b0 | 4039 | |
6b990f6b RE |
4040 | /* Return nonzero if X is valid as an ARM state addressing register. */ |
4041 | static int | |
e32bac5b | 4042 | arm_address_register_rtx_p (rtx x, int strict_p) |
6b990f6b RE |
4043 | { |
4044 | int regno; | |
4045 | ||
4046 | if (GET_CODE (x) != REG) | |
4047 | return 0; | |
4048 | ||
4049 | regno = REGNO (x); | |
4050 | ||
4051 | if (strict_p) | |
4052 | return ARM_REGNO_OK_FOR_BASE_P (regno); | |
4053 | ||
4054 | return (regno <= LAST_ARM_REGNUM | |
4055 | || regno >= FIRST_PSEUDO_REGISTER | |
4056 | || regno == FRAME_POINTER_REGNUM | |
4057 | || regno == ARG_POINTER_REGNUM); | |
4058 | } | |
4059 | ||
d3585b76 DJ |
4060 | /* Return TRUE if this rtx is the difference of a symbol and a label, |
4061 | and will reduce to a PC-relative relocation in the object file. | |
4062 | Expressions like this can be left alone when generating PIC, rather | |
4063 | than forced through the GOT. */ | |
4064 | static int | |
4065 | pcrel_constant_p (rtx x) | |
4066 | { | |
4067 | if (GET_CODE (x) == MINUS) | |
4068 | return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); | |
4069 | ||
4070 | return FALSE; | |
4071 | } | |
4072 | ||
6b990f6b RE |
4073 | /* Return nonzero if X is a valid ARM state address operand. */ |
4074 | int | |
c6c3dba9 PB |
4075 | arm_legitimate_address_outer_p (enum machine_mode mode, rtx x, RTX_CODE outer, |
4076 | int strict_p) | |
6b990f6b | 4077 | { |
fdd695fd PB |
4078 | bool use_ldrd; |
4079 | enum rtx_code code = GET_CODE (x); | |
f676971a | 4080 | |
6b990f6b RE |
4081 | if (arm_address_register_rtx_p (x, strict_p)) |
4082 | return 1; | |
4083 | ||
fdd695fd PB |
4084 | use_ldrd = (TARGET_LDRD |
4085 | && (mode == DImode | |
4086 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
4087 | ||
4088 | if (code == POST_INC || code == PRE_DEC | |
4089 | || ((code == PRE_INC || code == POST_DEC) | |
4090 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
6b990f6b RE |
4091 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); |
4092 | ||
fdd695fd | 4093 | else if ((code == POST_MODIFY || code == PRE_MODIFY) |
6b990f6b RE |
4094 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) |
4095 | && GET_CODE (XEXP (x, 1)) == PLUS | |
386d3a16 | 4096 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
fdd695fd PB |
4097 | { |
4098 | rtx addend = XEXP (XEXP (x, 1), 1); | |
4099 | ||
112cdef5 | 4100 | /* Don't allow ldrd post increment by register because it's hard |
fdd695fd PB |
4101 | to fixup invalid register choices. */ |
4102 | if (use_ldrd | |
4103 | && GET_CODE (x) == POST_MODIFY | |
4104 | && GET_CODE (addend) == REG) | |
4105 | return 0; | |
4106 | ||
4107 | return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) | |
4108 | && arm_legitimate_index_p (mode, addend, outer, strict_p)); | |
4109 | } | |
6b990f6b RE |
4110 | |
4111 | /* After reload constants split into minipools will have addresses | |
4112 | from a LABEL_REF. */ | |
0bfb39ef | 4113 | else if (reload_completed |
fdd695fd PB |
4114 | && (code == LABEL_REF |
4115 | || (code == CONST | |
6b990f6b RE |
4116 | && GET_CODE (XEXP (x, 0)) == PLUS |
4117 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4118 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4119 | return 1; | |
4120 | ||
88f77cba | 4121 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
6b990f6b RE |
4122 | return 0; |
4123 | ||
fdd695fd | 4124 | else if (code == PLUS) |
6b990f6b RE |
4125 | { |
4126 | rtx xop0 = XEXP (x, 0); | |
4127 | rtx xop1 = XEXP (x, 1); | |
4128 | ||
4129 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
01577df7 | 4130 | && GET_CODE(xop1) == CONST_INT |
1e1ab407 | 4131 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)) |
6b990f6b | 4132 | || (arm_address_register_rtx_p (xop1, strict_p) |
1e1ab407 | 4133 | && arm_legitimate_index_p (mode, xop0, outer, strict_p))); |
6b990f6b RE |
4134 | } |
4135 | ||
4136 | #if 0 | |
4137 | /* Reload currently can't handle MINUS, so disable this for now */ | |
4138 | else if (GET_CODE (x) == MINUS) | |
4139 | { | |
4140 | rtx xop0 = XEXP (x, 0); | |
4141 | rtx xop1 = XEXP (x, 1); | |
4142 | ||
4143 | return (arm_address_register_rtx_p (xop0, strict_p) | |
1e1ab407 | 4144 | && arm_legitimate_index_p (mode, xop1, outer, strict_p)); |
6b990f6b RE |
4145 | } |
4146 | #endif | |
4147 | ||
4148 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
fdd695fd | 4149 | && code == SYMBOL_REF |
6b990f6b RE |
4150 | && CONSTANT_POOL_ADDRESS_P (x) |
4151 | && ! (flag_pic | |
d3585b76 DJ |
4152 | && symbol_mentioned_p (get_pool_constant (x)) |
4153 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
6b990f6b RE |
4154 | return 1; |
4155 | ||
6b990f6b RE |
4156 | return 0; |
4157 | } | |
4158 | ||
5b3e6663 | 4159 | /* Return nonzero if X is a valid Thumb-2 address operand. */ |
c6c3dba9 | 4160 | static int |
5b3e6663 PB |
4161 | thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
4162 | { | |
4163 | bool use_ldrd; | |
4164 | enum rtx_code code = GET_CODE (x); | |
4165 | ||
4166 | if (arm_address_register_rtx_p (x, strict_p)) | |
4167 | return 1; | |
4168 | ||
4169 | use_ldrd = (TARGET_LDRD | |
4170 | && (mode == DImode | |
4171 | || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); | |
4172 | ||
4173 | if (code == POST_INC || code == PRE_DEC | |
4174 | || ((code == PRE_INC || code == POST_DEC) | |
4175 | && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) | |
4176 | return arm_address_register_rtx_p (XEXP (x, 0), strict_p); | |
4177 | ||
4178 | else if ((code == POST_MODIFY || code == PRE_MODIFY) | |
4179 | && arm_address_register_rtx_p (XEXP (x, 0), strict_p) | |
4180 | && GET_CODE (XEXP (x, 1)) == PLUS | |
4181 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
4182 | { | |
4183 | /* Thumb-2 only has autoincrement by constant. */ | |
4184 | rtx addend = XEXP (XEXP (x, 1), 1); | |
4185 | HOST_WIDE_INT offset; | |
4186 | ||
4187 | if (GET_CODE (addend) != CONST_INT) | |
4188 | return 0; | |
4189 | ||
4190 | offset = INTVAL(addend); | |
4191 | if (GET_MODE_SIZE (mode) <= 4) | |
4192 | return (offset > -256 && offset < 256); | |
4193 | ||
4194 | return (use_ldrd && offset > -1024 && offset < 1024 | |
4195 | && (offset & 3) == 0); | |
4196 | } | |
4197 | ||
4198 | /* After reload constants split into minipools will have addresses | |
4199 | from a LABEL_REF. */ | |
4200 | else if (reload_completed | |
4201 | && (code == LABEL_REF | |
4202 | || (code == CONST | |
4203 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4204 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4205 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4206 | return 1; | |
4207 | ||
88f77cba | 4208 | else if (mode == TImode || (TARGET_NEON && VALID_NEON_STRUCT_MODE (mode))) |
5b3e6663 PB |
4209 | return 0; |
4210 | ||
4211 | else if (code == PLUS) | |
4212 | { | |
4213 | rtx xop0 = XEXP (x, 0); | |
4214 | rtx xop1 = XEXP (x, 1); | |
4215 | ||
4216 | return ((arm_address_register_rtx_p (xop0, strict_p) | |
4217 | && thumb2_legitimate_index_p (mode, xop1, strict_p)) | |
4218 | || (arm_address_register_rtx_p (xop1, strict_p) | |
4219 | && thumb2_legitimate_index_p (mode, xop0, strict_p))); | |
4220 | } | |
4221 | ||
4222 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
4223 | && code == SYMBOL_REF | |
4224 | && CONSTANT_POOL_ADDRESS_P (x) | |
4225 | && ! (flag_pic | |
4226 | && symbol_mentioned_p (get_pool_constant (x)) | |
4227 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
4228 | return 1; | |
4229 | ||
4230 | return 0; | |
4231 | } | |
4232 | ||
6b990f6b RE |
4233 | /* Return nonzero if INDEX is valid for an address index operand in |
4234 | ARM state. */ | |
4235 | static int | |
1e1ab407 RE |
4236 | arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, |
4237 | int strict_p) | |
6b990f6b RE |
4238 | { |
4239 | HOST_WIDE_INT range; | |
4240 | enum rtx_code code = GET_CODE (index); | |
4241 | ||
778ebdd9 PB |
4242 | /* Standard coprocessor addressing modes. */ |
4243 | if (TARGET_HARD_FLOAT | |
4244 | && (TARGET_FPA || TARGET_MAVERICK) | |
4245 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4246 | || (TARGET_MAVERICK && mode == DImode))) | |
6b990f6b RE |
4247 | return (code == CONST_INT && INTVAL (index) < 1024 |
4248 | && INTVAL (index) > -1024 | |
4249 | && (INTVAL (index) & 3) == 0); | |
4250 | ||
88f77cba JB |
4251 | if (TARGET_NEON |
4252 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
4253 | return (code == CONST_INT | |
4254 | && INTVAL (index) < 1016 | |
4255 | && INTVAL (index) > -1024 | |
4256 | && (INTVAL (index) & 3) == 0); | |
4257 | ||
5a9335ef NC |
4258 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) |
4259 | return (code == CONST_INT | |
3657dc3e PB |
4260 | && INTVAL (index) < 1024 |
4261 | && INTVAL (index) > -1024 | |
4262 | && (INTVAL (index) & 3) == 0); | |
5a9335ef | 4263 | |
fdd695fd PB |
4264 | if (arm_address_register_rtx_p (index, strict_p) |
4265 | && (GET_MODE_SIZE (mode) <= 4)) | |
4266 | return 1; | |
4267 | ||
4268 | if (mode == DImode || mode == DFmode) | |
4269 | { | |
4270 | if (code == CONST_INT) | |
4271 | { | |
4272 | HOST_WIDE_INT val = INTVAL (index); | |
4273 | ||
4274 | if (TARGET_LDRD) | |
4275 | return val > -256 && val < 256; | |
4276 | else | |
f372c932 | 4277 | return val > -4096 && val < 4092; |
fdd695fd PB |
4278 | } |
4279 | ||
4280 | return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); | |
4281 | } | |
4282 | ||
6b990f6b | 4283 | if (GET_MODE_SIZE (mode) <= 4 |
1e1ab407 RE |
4284 | && ! (arm_arch4 |
4285 | && (mode == HImode | |
0fd8c3ad | 4286 | || mode == HFmode |
1e1ab407 | 4287 | || (mode == QImode && outer == SIGN_EXTEND)))) |
6b990f6b | 4288 | { |
1e1ab407 RE |
4289 | if (code == MULT) |
4290 | { | |
4291 | rtx xiop0 = XEXP (index, 0); | |
4292 | rtx xiop1 = XEXP (index, 1); | |
4293 | ||
4294 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
4295 | && power_of_two_operand (xiop1, SImode)) | |
4296 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
4297 | && power_of_two_operand (xiop0, SImode))); | |
4298 | } | |
4299 | else if (code == LSHIFTRT || code == ASHIFTRT | |
4300 | || code == ASHIFT || code == ROTATERT) | |
4301 | { | |
4302 | rtx op = XEXP (index, 1); | |
6b990f6b | 4303 | |
1e1ab407 RE |
4304 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) |
4305 | && GET_CODE (op) == CONST_INT | |
4306 | && INTVAL (op) > 0 | |
4307 | && INTVAL (op) <= 31); | |
4308 | } | |
6b990f6b RE |
4309 | } |
4310 | ||
1e1ab407 RE |
4311 | /* For ARM v4 we may be doing a sign-extend operation during the |
4312 | load. */ | |
e1471c91 | 4313 | if (arm_arch4) |
1e1ab407 | 4314 | { |
0fd8c3ad SL |
4315 | if (mode == HImode |
4316 | || mode == HFmode | |
4317 | || (outer == SIGN_EXTEND && mode == QImode)) | |
1e1ab407 RE |
4318 | range = 256; |
4319 | else | |
4320 | range = 4096; | |
4321 | } | |
e1471c91 | 4322 | else |
0fd8c3ad | 4323 | range = (mode == HImode || mode == HFmode) ? 4095 : 4096; |
6b990f6b RE |
4324 | |
4325 | return (code == CONST_INT | |
4326 | && INTVAL (index) < range | |
4327 | && INTVAL (index) > -range); | |
76a318e9 RE |
4328 | } |
4329 | ||
5b3e6663 PB |
4330 | /* Return true if OP is a valid index scaling factor for Thumb-2 address |
4331 | index operand. i.e. 1, 2, 4 or 8. */ | |
4332 | static bool | |
4333 | thumb2_index_mul_operand (rtx op) | |
4334 | { | |
4335 | HOST_WIDE_INT val; | |
4336 | ||
4337 | if (GET_CODE(op) != CONST_INT) | |
4338 | return false; | |
4339 | ||
4340 | val = INTVAL(op); | |
4341 | return (val == 1 || val == 2 || val == 4 || val == 8); | |
4342 | } | |
4343 | ||
4344 | /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */ | |
4345 | static int | |
4346 | thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) | |
4347 | { | |
4348 | enum rtx_code code = GET_CODE (index); | |
4349 | ||
4350 | /* ??? Combine arm and thumb2 coprocessor addressing modes. */ | |
4351 | /* Standard coprocessor addressing modes. */ | |
4352 | if (TARGET_HARD_FLOAT | |
4353 | && (TARGET_FPA || TARGET_MAVERICK) | |
4354 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4355 | || (TARGET_MAVERICK && mode == DImode))) | |
4356 | return (code == CONST_INT && INTVAL (index) < 1024 | |
4357 | && INTVAL (index) > -1024 | |
4358 | && (INTVAL (index) & 3) == 0); | |
4359 | ||
4360 | if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) | |
fe2d934b PB |
4361 | { |
4362 | /* For DImode assume values will usually live in core regs | |
4363 | and only allow LDRD addressing modes. */ | |
4364 | if (!TARGET_LDRD || mode != DImode) | |
4365 | return (code == CONST_INT | |
4366 | && INTVAL (index) < 1024 | |
4367 | && INTVAL (index) > -1024 | |
4368 | && (INTVAL (index) & 3) == 0); | |
4369 | } | |
5b3e6663 | 4370 | |
88f77cba JB |
4371 | if (TARGET_NEON |
4372 | && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))) | |
4373 | return (code == CONST_INT | |
4374 | && INTVAL (index) < 1016 | |
4375 | && INTVAL (index) > -1024 | |
4376 | && (INTVAL (index) & 3) == 0); | |
4377 | ||
5b3e6663 PB |
4378 | if (arm_address_register_rtx_p (index, strict_p) |
4379 | && (GET_MODE_SIZE (mode) <= 4)) | |
4380 | return 1; | |
4381 | ||
4382 | if (mode == DImode || mode == DFmode) | |
4383 | { | |
e07e020b RR |
4384 | if (code == CONST_INT) |
4385 | { | |
4386 | HOST_WIDE_INT val = INTVAL (index); | |
4387 | /* ??? Can we assume ldrd for thumb2? */ | |
4388 | /* Thumb-2 ldrd only has reg+const addressing modes. */ | |
4389 | /* ldrd supports offsets of +-1020. | |
4390 | However the ldr fallback does not. */ | |
4391 | return val > -256 && val < 256 && (val & 3) == 0; | |
4392 | } | |
4393 | else | |
5b3e6663 | 4394 | return 0; |
5b3e6663 PB |
4395 | } |
4396 | ||
4397 | if (code == MULT) | |
4398 | { | |
4399 | rtx xiop0 = XEXP (index, 0); | |
4400 | rtx xiop1 = XEXP (index, 1); | |
4401 | ||
4402 | return ((arm_address_register_rtx_p (xiop0, strict_p) | |
4403 | && thumb2_index_mul_operand (xiop1)) | |
4404 | || (arm_address_register_rtx_p (xiop1, strict_p) | |
4405 | && thumb2_index_mul_operand (xiop0))); | |
4406 | } | |
4407 | else if (code == ASHIFT) | |
4408 | { | |
4409 | rtx op = XEXP (index, 1); | |
4410 | ||
4411 | return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) | |
4412 | && GET_CODE (op) == CONST_INT | |
4413 | && INTVAL (op) > 0 | |
4414 | && INTVAL (op) <= 3); | |
4415 | } | |
4416 | ||
4417 | return (code == CONST_INT | |
4418 | && INTVAL (index) < 4096 | |
4419 | && INTVAL (index) > -256); | |
4420 | } | |
4421 | ||
4422 | /* Return nonzero if X is valid as a 16-bit Thumb state base register. */ | |
76a318e9 | 4423 | static int |
5b3e6663 | 4424 | thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) |
76a318e9 RE |
4425 | { |
4426 | int regno; | |
4427 | ||
4428 | if (GET_CODE (x) != REG) | |
4429 | return 0; | |
4430 | ||
4431 | regno = REGNO (x); | |
4432 | ||
4433 | if (strict_p) | |
5b3e6663 | 4434 | return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode); |
76a318e9 RE |
4435 | |
4436 | return (regno <= LAST_LO_REGNUM | |
07e58265 | 4437 | || regno > LAST_VIRTUAL_REGISTER |
76a318e9 RE |
4438 | || regno == FRAME_POINTER_REGNUM |
4439 | || (GET_MODE_SIZE (mode) >= 4 | |
4440 | && (regno == STACK_POINTER_REGNUM | |
edf7cee8 | 4441 | || regno >= FIRST_PSEUDO_REGISTER |
76a318e9 RE |
4442 | || x == hard_frame_pointer_rtx |
4443 | || x == arg_pointer_rtx))); | |
4444 | } | |
4445 | ||
4446 | /* Return nonzero if x is a legitimate index register. This is the case | |
4447 | for any base register that can access a QImode object. */ | |
4448 | inline static int | |
5b3e6663 | 4449 | thumb1_index_register_rtx_p (rtx x, int strict_p) |
76a318e9 | 4450 | { |
5b3e6663 | 4451 | return thumb1_base_register_rtx_p (x, QImode, strict_p); |
76a318e9 RE |
4452 | } |
4453 | ||
5b3e6663 | 4454 | /* Return nonzero if x is a legitimate 16-bit Thumb-state address. |
f676971a | 4455 | |
76a318e9 RE |
4456 | The AP may be eliminated to either the SP or the FP, so we use the |
4457 | least common denominator, e.g. SImode, and offsets from 0 to 64. | |
4458 | ||
4459 | ??? Verify whether the above is the right approach. | |
4460 | ||
4461 | ??? Also, the FP may be eliminated to the SP, so perhaps that | |
4462 | needs special handling also. | |
4463 | ||
4464 | ??? Look at how the mips16 port solves this problem. It probably uses | |
4465 | better ways to solve some of these problems. | |
4466 | ||
4467 | Although it is not incorrect, we don't accept QImode and HImode | |
4468 | addresses based on the frame pointer or arg pointer until the | |
4469 | reload pass starts. This is so that eliminating such addresses | |
4470 | into stack based ones won't produce impossible code. */ | |
c6c3dba9 | 4471 | static int |
5b3e6663 | 4472 | thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) |
76a318e9 RE |
4473 | { |
4474 | /* ??? Not clear if this is right. Experiment. */ | |
4475 | if (GET_MODE_SIZE (mode) < 4 | |
4476 | && !(reload_in_progress || reload_completed) | |
4477 | && (reg_mentioned_p (frame_pointer_rtx, x) | |
4478 | || reg_mentioned_p (arg_pointer_rtx, x) | |
4479 | || reg_mentioned_p (virtual_incoming_args_rtx, x) | |
4480 | || reg_mentioned_p (virtual_outgoing_args_rtx, x) | |
4481 | || reg_mentioned_p (virtual_stack_dynamic_rtx, x) | |
4482 | || reg_mentioned_p (virtual_stack_vars_rtx, x))) | |
4483 | return 0; | |
4484 | ||
4485 | /* Accept any base register. SP only in SImode or larger. */ | |
5b3e6663 | 4486 | else if (thumb1_base_register_rtx_p (x, mode, strict_p)) |
76a318e9 RE |
4487 | return 1; |
4488 | ||
18dbd950 | 4489 | /* This is PC relative data before arm_reorg runs. */ |
76a318e9 RE |
4490 | else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) |
4491 | && GET_CODE (x) == SYMBOL_REF | |
020a4035 | 4492 | && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) |
76a318e9 RE |
4493 | return 1; |
4494 | ||
18dbd950 | 4495 | /* This is PC relative data after arm_reorg runs. */ |
0fd8c3ad SL |
4496 | else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode) |
4497 | && reload_completed | |
76a318e9 RE |
4498 | && (GET_CODE (x) == LABEL_REF |
4499 | || (GET_CODE (x) == CONST | |
4500 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4501 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF | |
4502 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) | |
4503 | return 1; | |
4504 | ||
4505 | /* Post-inc indexing only supported for SImode and larger. */ | |
4506 | else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 | |
5b3e6663 | 4507 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)) |
76a318e9 RE |
4508 | return 1; |
4509 | ||
4510 | else if (GET_CODE (x) == PLUS) | |
4511 | { | |
4512 | /* REG+REG address can be any two index registers. */ | |
4513 | /* We disallow FRAME+REG addressing since we know that FRAME | |
4514 | will be replaced with STACK, and SP relative addressing only | |
4515 | permits SP+OFFSET. */ | |
4516 | if (GET_MODE_SIZE (mode) <= 4 | |
4517 | && XEXP (x, 0) != frame_pointer_rtx | |
4518 | && XEXP (x, 1) != frame_pointer_rtx | |
5b3e6663 PB |
4519 | && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
4520 | && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p)) | |
76a318e9 RE |
4521 | return 1; |
4522 | ||
4523 | /* REG+const has 5-7 bit offset for non-SP registers. */ | |
5b3e6663 | 4524 | else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p) |
76a318e9 RE |
4525 | || XEXP (x, 0) == arg_pointer_rtx) |
4526 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4527 | && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4528 | return 1; | |
4529 | ||
a50aa827 | 4530 | /* REG+const has 10-bit offset for SP, but only SImode and |
76a318e9 RE |
4531 | larger is supported. */ |
4532 | /* ??? Should probably check for DI/DFmode overflow here | |
4533 | just like GO_IF_LEGITIMATE_OFFSET does. */ | |
4534 | else if (GET_CODE (XEXP (x, 0)) == REG | |
4535 | && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM | |
4536 | && GET_MODE_SIZE (mode) >= 4 | |
4537 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4538 | && INTVAL (XEXP (x, 1)) >= 0 | |
4539 | && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 | |
4540 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4541 | return 1; | |
4542 | ||
4543 | else if (GET_CODE (XEXP (x, 0)) == REG | |
c5289e45 RE |
4544 | && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM |
4545 | || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM | |
4546 | || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER | |
4547 | && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER)) | |
76a318e9 RE |
4548 | && GET_MODE_SIZE (mode) >= 4 |
4549 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4550 | && (INTVAL (XEXP (x, 1)) & 3) == 0) | |
4551 | return 1; | |
4552 | } | |
4553 | ||
4554 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
f954388e | 4555 | && GET_MODE_SIZE (mode) == 4 |
76a318e9 RE |
4556 | && GET_CODE (x) == SYMBOL_REF |
4557 | && CONSTANT_POOL_ADDRESS_P (x) | |
d3585b76 DJ |
4558 | && ! (flag_pic |
4559 | && symbol_mentioned_p (get_pool_constant (x)) | |
4560 | && ! pcrel_constant_p (get_pool_constant (x)))) | |
76a318e9 RE |
4561 | return 1; |
4562 | ||
4563 | return 0; | |
4564 | } | |
4565 | ||
4566 | /* Return nonzero if VAL can be used as an offset in a Thumb-state address | |
4567 | instruction of mode MODE. */ | |
4568 | int | |
e32bac5b | 4569 | thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) |
76a318e9 RE |
4570 | { |
4571 | switch (GET_MODE_SIZE (mode)) | |
4572 | { | |
4573 | case 1: | |
4574 | return val >= 0 && val < 32; | |
4575 | ||
4576 | case 2: | |
4577 | return val >= 0 && val < 64 && (val & 1) == 0; | |
4578 | ||
4579 | default: | |
4580 | return (val >= 0 | |
4581 | && (val + GET_MODE_SIZE (mode)) <= 128 | |
4582 | && (val & 3) == 0); | |
4583 | } | |
4584 | } | |
4585 | ||
c6c3dba9 PB |
4586 | bool |
4587 | arm_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) | |
4588 | { | |
4589 | if (TARGET_ARM) | |
4590 | return arm_legitimate_address_outer_p (mode, x, SET, strict_p); | |
4591 | else if (TARGET_THUMB2) | |
4592 | return thumb2_legitimate_address_p (mode, x, strict_p); | |
4593 | else /* if (TARGET_THUMB1) */ | |
4594 | return thumb1_legitimate_address_p (mode, x, strict_p); | |
4595 | } | |
4596 | ||
d3585b76 DJ |
4597 | /* Build the SYMBOL_REF for __tls_get_addr. */ |
4598 | ||
4599 | static GTY(()) rtx tls_get_addr_libfunc; | |
4600 | ||
4601 | static rtx | |
4602 | get_tls_get_addr (void) | |
4603 | { | |
4604 | if (!tls_get_addr_libfunc) | |
4605 | tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); | |
4606 | return tls_get_addr_libfunc; | |
4607 | } | |
4608 | ||
4609 | static rtx | |
4610 | arm_load_tp (rtx target) | |
4611 | { | |
4612 | if (!target) | |
4613 | target = gen_reg_rtx (SImode); | |
4614 | ||
4615 | if (TARGET_HARD_TP) | |
4616 | { | |
4617 | /* Can return in any reg. */ | |
4618 | emit_insn (gen_load_tp_hard (target)); | |
4619 | } | |
4620 | else | |
4621 | { | |
4622 | /* Always returned in r0. Immediately copy the result into a pseudo, | |
4623 | otherwise other uses of r0 (e.g. setting up function arguments) may | |
4624 | clobber the value. */ | |
4625 | ||
4626 | rtx tmp; | |
4627 | ||
4628 | emit_insn (gen_load_tp_soft ()); | |
4629 | ||
4630 | tmp = gen_rtx_REG (SImode, 0); | |
4631 | emit_move_insn (target, tmp); | |
4632 | } | |
4633 | return target; | |
4634 | } | |
4635 | ||
4636 | static rtx | |
4637 | load_tls_operand (rtx x, rtx reg) | |
4638 | { | |
4639 | rtx tmp; | |
4640 | ||
4641 | if (reg == NULL_RTX) | |
4642 | reg = gen_reg_rtx (SImode); | |
4643 | ||
4644 | tmp = gen_rtx_CONST (SImode, x); | |
4645 | ||
4646 | emit_move_insn (reg, tmp); | |
4647 | ||
4648 | return reg; | |
4649 | } | |
4650 | ||
4651 | static rtx | |
4652 | arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) | |
4653 | { | |
f16fe45f | 4654 | rtx insns, label, labelno, sum; |
d3585b76 DJ |
4655 | |
4656 | start_sequence (); | |
4657 | ||
f16fe45f DJ |
4658 | labelno = GEN_INT (pic_labelno++); |
4659 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4660 | label = gen_rtx_CONST (VOIDmode, label); | |
4661 | ||
d3585b76 | 4662 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4663 | gen_rtvec (4, x, GEN_INT (reloc), label, |
d3585b76 DJ |
4664 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4665 | UNSPEC_TLS); | |
4666 | reg = load_tls_operand (sum, reg); | |
4667 | ||
4668 | if (TARGET_ARM) | |
f16fe45f | 4669 | emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4670 | else if (TARGET_THUMB2) |
4671 | { | |
4672 | rtx tmp; | |
4673 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4674 | the address in a temporary register. */ | |
4675 | tmp = gen_reg_rtx (SImode); | |
4676 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4677 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4678 | } | |
4679 | else /* TARGET_THUMB1 */ | |
f16fe45f | 4680 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4681 | |
4682 | *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ | |
4683 | Pmode, 1, reg, Pmode); | |
4684 | ||
4685 | insns = get_insns (); | |
4686 | end_sequence (); | |
4687 | ||
4688 | return insns; | |
4689 | } | |
4690 | ||
4691 | rtx | |
4692 | legitimize_tls_address (rtx x, rtx reg) | |
4693 | { | |
f16fe45f | 4694 | rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; |
d3585b76 DJ |
4695 | unsigned int model = SYMBOL_REF_TLS_MODEL (x); |
4696 | ||
4697 | switch (model) | |
4698 | { | |
4699 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
4700 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); | |
4701 | dest = gen_reg_rtx (Pmode); | |
4702 | emit_libcall_block (insns, dest, ret, x); | |
4703 | return dest; | |
4704 | ||
4705 | case TLS_MODEL_LOCAL_DYNAMIC: | |
4706 | insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); | |
4707 | ||
4708 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
4709 | share the LDM result with other LD model accesses. */ | |
4710 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), | |
4711 | UNSPEC_TLS); | |
4712 | dest = gen_reg_rtx (Pmode); | |
e66e1c68 | 4713 | emit_libcall_block (insns, dest, ret, eqv); |
d3585b76 DJ |
4714 | |
4715 | /* Load the addend. */ | |
4716 | addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), | |
4717 | UNSPEC_TLS); | |
4718 | addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); | |
4719 | return gen_rtx_PLUS (Pmode, dest, addend); | |
4720 | ||
4721 | case TLS_MODEL_INITIAL_EXEC: | |
f16fe45f DJ |
4722 | labelno = GEN_INT (pic_labelno++); |
4723 | label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); | |
4724 | label = gen_rtx_CONST (VOIDmode, label); | |
d3585b76 | 4725 | sum = gen_rtx_UNSPEC (Pmode, |
f16fe45f | 4726 | gen_rtvec (4, x, GEN_INT (TLS_IE32), label, |
d3585b76 DJ |
4727 | GEN_INT (TARGET_ARM ? 8 : 4)), |
4728 | UNSPEC_TLS); | |
4729 | reg = load_tls_operand (sum, reg); | |
4730 | ||
4731 | if (TARGET_ARM) | |
f16fe45f | 4732 | emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); |
5b3e6663 PB |
4733 | else if (TARGET_THUMB2) |
4734 | { | |
4735 | rtx tmp; | |
4736 | /* Thumb-2 only allows very limited access to the PC. Calculate | |
4737 | the address in a temporary register. */ | |
4738 | tmp = gen_reg_rtx (SImode); | |
4739 | emit_insn (gen_pic_load_dot_plus_four (tmp, labelno)); | |
4740 | emit_insn (gen_addsi3(reg, reg, tmp)); | |
4741 | emit_move_insn (reg, gen_const_mem (SImode, reg)); | |
4742 | } | |
d3585b76 DJ |
4743 | else |
4744 | { | |
f16fe45f | 4745 | emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); |
d3585b76 DJ |
4746 | emit_move_insn (reg, gen_const_mem (SImode, reg)); |
4747 | } | |
4748 | ||
4749 | tp = arm_load_tp (NULL_RTX); | |
4750 | ||
4751 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4752 | ||
4753 | case TLS_MODEL_LOCAL_EXEC: | |
4754 | tp = arm_load_tp (NULL_RTX); | |
4755 | ||
4756 | reg = gen_rtx_UNSPEC (Pmode, | |
4757 | gen_rtvec (2, x, GEN_INT (TLS_LE32)), | |
4758 | UNSPEC_TLS); | |
4759 | reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); | |
4760 | ||
4761 | return gen_rtx_PLUS (Pmode, tp, reg); | |
4762 | ||
4763 | default: | |
4764 | abort (); | |
4765 | } | |
4766 | } | |
4767 | ||
ccf4d512 RE |
4768 | /* Try machine-dependent ways of modifying an illegitimate address |
4769 | to be legitimate. If we find one, return the new, valid address. */ | |
ccf4d512 | 4770 | rtx |
e32bac5b | 4771 | arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) |
ccf4d512 | 4772 | { |
506d7b68 PB |
4773 | if (!TARGET_ARM) |
4774 | { | |
4775 | /* TODO: legitimize_address for Thumb2. */ | |
4776 | if (TARGET_THUMB2) | |
4777 | return x; | |
4778 | return thumb_legitimize_address (x, orig_x, mode); | |
4779 | } | |
4780 | ||
d3585b76 DJ |
4781 | if (arm_tls_symbol_p (x)) |
4782 | return legitimize_tls_address (x, NULL_RTX); | |
4783 | ||
ccf4d512 RE |
4784 | if (GET_CODE (x) == PLUS) |
4785 | { | |
4786 | rtx xop0 = XEXP (x, 0); | |
4787 | rtx xop1 = XEXP (x, 1); | |
4788 | ||
4789 | if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) | |
4790 | xop0 = force_reg (SImode, xop0); | |
4791 | ||
4792 | if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) | |
4793 | xop1 = force_reg (SImode, xop1); | |
4794 | ||
4795 | if (ARM_BASE_REGISTER_RTX_P (xop0) | |
4796 | && GET_CODE (xop1) == CONST_INT) | |
4797 | { | |
4798 | HOST_WIDE_INT n, low_n; | |
4799 | rtx base_reg, val; | |
4800 | n = INTVAL (xop1); | |
4801 | ||
9b66ebb1 PB |
4802 | /* VFP addressing modes actually allow greater offsets, but for |
4803 | now we just stick with the lowest common denominator. */ | |
4804 | if (mode == DImode | |
4805 | || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) | |
ccf4d512 RE |
4806 | { |
4807 | low_n = n & 0x0f; | |
4808 | n &= ~0x0f; | |
4809 | if (low_n > 4) | |
4810 | { | |
4811 | n += 16; | |
4812 | low_n -= 16; | |
4813 | } | |
4814 | } | |
4815 | else | |
4816 | { | |
4817 | low_n = ((mode) == TImode ? 0 | |
4818 | : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); | |
4819 | n -= low_n; | |
4820 | } | |
4821 | ||
4822 | base_reg = gen_reg_rtx (SImode); | |
d66437c5 | 4823 | val = force_operand (plus_constant (xop0, n), NULL_RTX); |
ccf4d512 | 4824 | emit_move_insn (base_reg, val); |
d66437c5 | 4825 | x = plus_constant (base_reg, low_n); |
ccf4d512 RE |
4826 | } |
4827 | else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4828 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4829 | } | |
4830 | ||
4831 | /* XXX We don't allow MINUS any more -- see comment in | |
c6c3dba9 | 4832 | arm_legitimate_address_outer_p (). */ |
ccf4d512 RE |
4833 | else if (GET_CODE (x) == MINUS) |
4834 | { | |
4835 | rtx xop0 = XEXP (x, 0); | |
4836 | rtx xop1 = XEXP (x, 1); | |
4837 | ||
4838 | if (CONSTANT_P (xop0)) | |
4839 | xop0 = force_reg (SImode, xop0); | |
4840 | ||
4841 | if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) | |
4842 | xop1 = force_reg (SImode, xop1); | |
4843 | ||
4844 | if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) | |
4845 | x = gen_rtx_MINUS (SImode, xop0, xop1); | |
4846 | } | |
4847 | ||
86805759 NP |
4848 | /* Make sure to take full advantage of the pre-indexed addressing mode |
4849 | with absolute addresses which often allows for the base register to | |
4850 | be factorized for multiple adjacent memory references, and it might | |
4851 | even allows for the mini pool to be avoided entirely. */ | |
4852 | else if (GET_CODE (x) == CONST_INT && optimize > 0) | |
4853 | { | |
4854 | unsigned int bits; | |
4855 | HOST_WIDE_INT mask, base, index; | |
4856 | rtx base_reg; | |
4857 | ||
a50aa827 KH |
4858 | /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only |
4859 | use a 8-bit index. So let's use a 12-bit index for SImode only and | |
86805759 NP |
4860 | hope that arm_gen_constant will enable ldrb to use more bits. */ |
4861 | bits = (mode == SImode) ? 12 : 8; | |
4862 | mask = (1 << bits) - 1; | |
4863 | base = INTVAL (x) & ~mask; | |
4864 | index = INTVAL (x) & mask; | |
b107d743 | 4865 | if (bit_count (base & 0xffffffff) > (32 - bits)/2) |
86805759 NP |
4866 | { |
4867 | /* It'll most probably be more efficient to generate the base | |
4868 | with more bits set and use a negative index instead. */ | |
4869 | base |= mask; | |
4870 | index -= mask; | |
4871 | } | |
4872 | base_reg = force_reg (SImode, GEN_INT (base)); | |
d66437c5 | 4873 | x = plus_constant (base_reg, index); |
86805759 NP |
4874 | } |
4875 | ||
ccf4d512 RE |
4876 | if (flag_pic) |
4877 | { | |
4878 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4879 | references; so go back to the original address expression. */ | |
4880 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4881 | ||
4882 | if (new_x != orig_x) | |
4883 | x = new_x; | |
4884 | } | |
4885 | ||
4886 | return x; | |
4887 | } | |
4888 | ||
6f5b4f3e RE |
4889 | |
4890 | /* Try machine-dependent ways of modifying an illegitimate Thumb address | |
4891 | to be legitimate. If we find one, return the new, valid address. */ | |
4892 | rtx | |
4893 | thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) | |
4894 | { | |
d3585b76 DJ |
4895 | if (arm_tls_symbol_p (x)) |
4896 | return legitimize_tls_address (x, NULL_RTX); | |
4897 | ||
6f5b4f3e RE |
4898 | if (GET_CODE (x) == PLUS |
4899 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4900 | && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) | |
4901 | || INTVAL (XEXP (x, 1)) < 0)) | |
4902 | { | |
4903 | rtx xop0 = XEXP (x, 0); | |
4904 | rtx xop1 = XEXP (x, 1); | |
4905 | HOST_WIDE_INT offset = INTVAL (xop1); | |
4906 | ||
4907 | /* Try and fold the offset into a biasing of the base register and | |
4908 | then offsetting that. Don't do this when optimizing for space | |
4909 | since it can cause too many CSEs. */ | |
4910 | if (optimize_size && offset >= 0 | |
4911 | && offset < 256 + 31 * GET_MODE_SIZE (mode)) | |
4912 | { | |
4913 | HOST_WIDE_INT delta; | |
4914 | ||
4915 | if (offset >= 256) | |
4916 | delta = offset - (256 - GET_MODE_SIZE (mode)); | |
4917 | else if (offset < 32 * GET_MODE_SIZE (mode) + 8) | |
4918 | delta = 31 * GET_MODE_SIZE (mode); | |
4919 | else | |
4920 | delta = offset & (~31 * GET_MODE_SIZE (mode)); | |
4921 | ||
4922 | xop0 = force_operand (plus_constant (xop0, offset - delta), | |
4923 | NULL_RTX); | |
4924 | x = plus_constant (xop0, delta); | |
4925 | } | |
4926 | else if (offset < 0 && offset > -256) | |
4927 | /* Small negative offsets are best done with a subtract before the | |
4928 | dereference, forcing these into a register normally takes two | |
4929 | instructions. */ | |
4930 | x = force_operand (x, NULL_RTX); | |
4931 | else | |
4932 | { | |
4933 | /* For the remaining cases, force the constant into a register. */ | |
4934 | xop1 = force_reg (SImode, xop1); | |
4935 | x = gen_rtx_PLUS (SImode, xop0, xop1); | |
4936 | } | |
4937 | } | |
4938 | else if (GET_CODE (x) == PLUS | |
4939 | && s_register_operand (XEXP (x, 1), SImode) | |
4940 | && !s_register_operand (XEXP (x, 0), SImode)) | |
4941 | { | |
4942 | rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); | |
4943 | ||
4944 | x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); | |
4945 | } | |
4946 | ||
4947 | if (flag_pic) | |
4948 | { | |
4949 | /* We need to find and carefully transform any SYMBOL and LABEL | |
4950 | references; so go back to the original address expression. */ | |
4951 | rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); | |
4952 | ||
4953 | if (new_x != orig_x) | |
4954 | x = new_x; | |
4955 | } | |
4956 | ||
4957 | return x; | |
4958 | } | |
4959 | ||
a132dad6 | 4960 | rtx |
e0b92319 NC |
4961 | thumb_legitimize_reload_address (rtx *x_p, |
4962 | enum machine_mode mode, | |
4963 | int opnum, int type, | |
4964 | int ind_levels ATTRIBUTE_UNUSED) | |
a132dad6 RE |
4965 | { |
4966 | rtx x = *x_p; | |
e0b92319 | 4967 | |
a132dad6 RE |
4968 | if (GET_CODE (x) == PLUS |
4969 | && GET_MODE_SIZE (mode) < 4 | |
4970 | && REG_P (XEXP (x, 0)) | |
4971 | && XEXP (x, 0) == stack_pointer_rtx | |
4972 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4973 | && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) | |
4974 | { | |
4975 | rtx orig_x = x; | |
4976 | ||
4977 | x = copy_rtx (x); | |
4978 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 4979 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
4980 | return x; |
4981 | } | |
4982 | ||
4983 | /* If both registers are hi-regs, then it's better to reload the | |
4984 | entire expression rather than each register individually. That | |
4985 | only requires one reload register rather than two. */ | |
4986 | if (GET_CODE (x) == PLUS | |
4987 | && REG_P (XEXP (x, 0)) | |
4988 | && REG_P (XEXP (x, 1)) | |
4989 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) | |
4990 | && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) | |
4991 | { | |
4992 | rtx orig_x = x; | |
4993 | ||
4994 | x = copy_rtx (x); | |
4995 | push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), | |
bbbbb16a | 4996 | Pmode, VOIDmode, 0, 0, opnum, (enum reload_type) type); |
a132dad6 RE |
4997 | return x; |
4998 | } | |
4999 | ||
5000 | return NULL; | |
5001 | } | |
d3585b76 DJ |
5002 | |
5003 | /* Test for various thread-local symbols. */ | |
5004 | ||
5005 | /* Return TRUE if X is a thread-local symbol. */ | |
5006 | ||
5007 | static bool | |
5008 | arm_tls_symbol_p (rtx x) | |
5009 | { | |
5010 | if (! TARGET_HAVE_TLS) | |
5011 | return false; | |
5012 | ||
5013 | if (GET_CODE (x) != SYMBOL_REF) | |
5014 | return false; | |
5015 | ||
5016 | return SYMBOL_REF_TLS_MODEL (x) != 0; | |
5017 | } | |
5018 | ||
5019 | /* Helper for arm_tls_referenced_p. */ | |
5020 | ||
5021 | static int | |
5022 | arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
5023 | { | |
5024 | if (GET_CODE (*x) == SYMBOL_REF) | |
5025 | return SYMBOL_REF_TLS_MODEL (*x) != 0; | |
5026 | ||
5027 | /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are | |
5028 | TLS offsets, not real symbol references. */ | |
5029 | if (GET_CODE (*x) == UNSPEC | |
5030 | && XINT (*x, 1) == UNSPEC_TLS) | |
5031 | return -1; | |
5032 | ||
5033 | return 0; | |
5034 | } | |
5035 | ||
5036 | /* Return TRUE if X contains any TLS symbol references. */ | |
5037 | ||
5038 | bool | |
5039 | arm_tls_referenced_p (rtx x) | |
5040 | { | |
5041 | if (! TARGET_HAVE_TLS) | |
5042 | return false; | |
5043 | ||
5044 | return for_each_rtx (&x, arm_tls_operand_p_1, NULL); | |
5045 | } | |
8426b956 RS |
5046 | |
5047 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ | |
5048 | ||
5049 | bool | |
5050 | arm_cannot_force_const_mem (rtx x) | |
5051 | { | |
5052 | rtx base, offset; | |
5053 | ||
5054 | if (ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) | |
5055 | { | |
5056 | split_const (x, &base, &offset); | |
5057 | if (GET_CODE (base) == SYMBOL_REF | |
5058 | && !offset_within_block_p (base, INTVAL (offset))) | |
5059 | return true; | |
5060 | } | |
5061 | return arm_tls_referenced_p (x); | |
5062 | } | |
6b990f6b | 5063 | \f |
e2c671ba RE |
5064 | #define REG_OR_SUBREG_REG(X) \ |
5065 | (GET_CODE (X) == REG \ | |
5066 | || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) | |
5067 | ||
5068 | #define REG_OR_SUBREG_RTX(X) \ | |
5069 | (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) | |
5070 | ||
d5b7b3ae RE |
5071 | #ifndef COSTS_N_INSNS |
5072 | #define COSTS_N_INSNS(N) ((N) * 4 - 2) | |
5073 | #endif | |
3c50106f | 5074 | static inline int |
5b3e6663 | 5075 | thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) |
e2c671ba RE |
5076 | { |
5077 | enum machine_mode mode = GET_MODE (x); | |
e2c671ba | 5078 | |
9b66ebb1 | 5079 | switch (code) |
d5b7b3ae | 5080 | { |
9b66ebb1 PB |
5081 | case ASHIFT: |
5082 | case ASHIFTRT: | |
5083 | case LSHIFTRT: | |
f676971a | 5084 | case ROTATERT: |
9b66ebb1 PB |
5085 | case PLUS: |
5086 | case MINUS: | |
5087 | case COMPARE: | |
5088 | case NEG: | |
f676971a | 5089 | case NOT: |
9b66ebb1 | 5090 | return COSTS_N_INSNS (1); |
f676971a EC |
5091 | |
5092 | case MULT: | |
5093 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5094 | { | |
5095 | int cycles = 0; | |
9b66ebb1 | 5096 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); |
f676971a EC |
5097 | |
5098 | while (i) | |
5099 | { | |
5100 | i >>= 2; | |
5101 | cycles++; | |
5102 | } | |
5103 | return COSTS_N_INSNS (2) + cycles; | |
9b66ebb1 PB |
5104 | } |
5105 | return COSTS_N_INSNS (1) + 16; | |
f676971a EC |
5106 | |
5107 | case SET: | |
5108 | return (COSTS_N_INSNS (1) | |
5109 | + 4 * ((GET_CODE (SET_SRC (x)) == MEM) | |
9b66ebb1 | 5110 | + GET_CODE (SET_DEST (x)) == MEM)); |
f676971a EC |
5111 | |
5112 | case CONST_INT: | |
5113 | if (outer == SET) | |
5114 | { | |
5115 | if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) | |
5116 | return 0; | |
5117 | if (thumb_shiftable_const (INTVAL (x))) | |
5118 | return COSTS_N_INSNS (2); | |
5119 | return COSTS_N_INSNS (3); | |
5120 | } | |
9b66ebb1 | 5121 | else if ((outer == PLUS || outer == COMPARE) |
f676971a | 5122 | && INTVAL (x) < 256 && INTVAL (x) > -256) |
9b66ebb1 PB |
5123 | return 0; |
5124 | else if (outer == AND | |
5125 | && INTVAL (x) < 256 && INTVAL (x) >= -256) | |
5126 | return COSTS_N_INSNS (1); | |
f676971a EC |
5127 | else if (outer == ASHIFT || outer == ASHIFTRT |
5128 | || outer == LSHIFTRT) | |
5129 | return 0; | |
9b66ebb1 | 5130 | return COSTS_N_INSNS (2); |
f676971a EC |
5131 | |
5132 | case CONST: | |
5133 | case CONST_DOUBLE: | |
5134 | case LABEL_REF: | |
5135 | case SYMBOL_REF: | |
9b66ebb1 | 5136 | return COSTS_N_INSNS (3); |
f676971a | 5137 | |
9b66ebb1 PB |
5138 | case UDIV: |
5139 | case UMOD: | |
5140 | case DIV: | |
5141 | case MOD: | |
5142 | return 100; | |
d5b7b3ae | 5143 | |
9b66ebb1 PB |
5144 | case TRUNCATE: |
5145 | return 99; | |
d5b7b3ae | 5146 | |
9b66ebb1 PB |
5147 | case AND: |
5148 | case XOR: | |
f676971a | 5149 | case IOR: |
ff482c8d | 5150 | /* XXX guess. */ |
9b66ebb1 | 5151 | return 8; |
d5b7b3ae | 5152 | |
9b66ebb1 PB |
5153 | case MEM: |
5154 | /* XXX another guess. */ | |
5155 | /* Memory costs quite a lot for the first word, but subsequent words | |
5156 | load at the equivalent of a single insn each. */ | |
5157 | return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) | |
5158 | + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
5159 | ? 4 : 0)); | |
5160 | ||
5161 | case IF_THEN_ELSE: | |
ff482c8d | 5162 | /* XXX a guess. */ |
9b66ebb1 PB |
5163 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) |
5164 | return 14; | |
5165 | return 2; | |
5166 | ||
5167 | case ZERO_EXTEND: | |
5168 | /* XXX still guessing. */ | |
5169 | switch (GET_MODE (XEXP (x, 0))) | |
5170 | { | |
5171 | case QImode: | |
5172 | return (1 + (mode == DImode ? 4 : 0) | |
5173 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 5174 | |
9b66ebb1 PB |
5175 | case HImode: |
5176 | return (4 + (mode == DImode ? 4 : 0) | |
5177 | + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 5178 | |
9b66ebb1 PB |
5179 | case SImode: |
5180 | return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); | |
f676971a | 5181 | |
d5b7b3ae RE |
5182 | default: |
5183 | return 99; | |
d5b7b3ae | 5184 | } |
f676971a | 5185 | |
9b66ebb1 PB |
5186 | default: |
5187 | return 99; | |
d5b7b3ae | 5188 | } |
9b66ebb1 PB |
5189 | } |
5190 | ||
d5a0a47b RE |
5191 | static inline bool |
5192 | arm_rtx_costs_1 (rtx x, enum rtx_code outer, int* total, bool speed) | |
9b66ebb1 PB |
5193 | { |
5194 | enum machine_mode mode = GET_MODE (x); | |
5195 | enum rtx_code subcode; | |
d5a0a47b RE |
5196 | rtx operand; |
5197 | enum rtx_code code = GET_CODE (x); | |
9b66ebb1 | 5198 | int extra_cost; |
d5a0a47b | 5199 | *total = 0; |
9b66ebb1 | 5200 | |
e2c671ba RE |
5201 | switch (code) |
5202 | { | |
5203 | case MEM: | |
5204 | /* Memory costs quite a lot for the first word, but subsequent words | |
5205 | load at the equivalent of a single insn each. */ | |
d5a0a47b RE |
5206 | *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode)); |
5207 | return true; | |
e2c671ba RE |
5208 | |
5209 | case DIV: | |
5210 | case MOD: | |
b9c53150 RS |
5211 | case UDIV: |
5212 | case UMOD: | |
d5a0a47b RE |
5213 | if (TARGET_HARD_FLOAT && mode == SFmode) |
5214 | *total = COSTS_N_INSNS (2); | |
5215 | else if (TARGET_HARD_FLOAT && mode == DFmode) | |
5216 | *total = COSTS_N_INSNS (4); | |
5217 | else | |
5218 | *total = COSTS_N_INSNS (20); | |
5219 | return false; | |
e2c671ba RE |
5220 | |
5221 | case ROTATE: | |
d5a0a47b RE |
5222 | if (GET_CODE (XEXP (x, 1)) == REG) |
5223 | *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */ | |
5224 | else if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5225 | *total = rtx_cost (XEXP (x, 1), code, speed); | |
5226 | ||
e2c671ba RE |
5227 | /* Fall through */ |
5228 | case ROTATERT: | |
5229 | if (mode != SImode) | |
d5a0a47b RE |
5230 | { |
5231 | *total += COSTS_N_INSNS (4); | |
5232 | return true; | |
5233 | } | |
5234 | ||
e2c671ba RE |
5235 | /* Fall through */ |
5236 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: | |
d5a0a47b | 5237 | *total += rtx_cost (XEXP (x, 0), code, speed); |
e2c671ba | 5238 | if (mode == DImode) |
d5a0a47b RE |
5239 | { |
5240 | *total += COSTS_N_INSNS (3); | |
5241 | return true; | |
5242 | } | |
7612f14d | 5243 | |
d5a0a47b | 5244 | *total += COSTS_N_INSNS (1); |
7612f14d PB |
5245 | /* Increase the cost of complex shifts because they aren't any faster, |
5246 | and reduce dual issue opportunities. */ | |
5247 | if (arm_tune_cortex_a9 | |
5248 | && outer != SET && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
d5a0a47b RE |
5249 | ++*total; |
5250 | ||
5251 | return true; | |
e2c671ba RE |
5252 | |
5253 | case MINUS: | |
d5a0a47b | 5254 | if (TARGET_THUMB2) |
26b53f80 | 5255 | { |
d5a0a47b RE |
5256 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5257 | { | |
5258 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5259 | *total = COSTS_N_INSNS (1); | |
5260 | else | |
5261 | *total = COSTS_N_INSNS (20); | |
5262 | } | |
5263 | else | |
5264 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5265 | /* Thumb2 does not have RSB, so all arguments must be | |
5266 | registers (subtracting a constant is canonicalized as | |
5267 | addition of the negated constant). */ | |
5268 | return false; | |
26b53f80 PB |
5269 | } |
5270 | ||
e2c671ba | 5271 | if (mode == DImode) |
d5a0a47b RE |
5272 | { |
5273 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5274 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
5275 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
5276 | { | |
5277 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5278 | return true; | |
5279 | } | |
5280 | ||
5281 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5282 | && const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
5283 | { | |
5284 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5285 | return true; | |
5286 | } | |
5287 | ||
5288 | return false; | |
5289 | } | |
e2c671ba RE |
5290 | |
5291 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b RE |
5292 | { |
5293 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5294 | { | |
5295 | *total = COSTS_N_INSNS (1); | |
5296 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE | |
5297 | && arm_const_double_rtx (XEXP (x, 0))) | |
5298 | { | |
5299 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5300 | return true; | |
5301 | } | |
5302 | ||
5303 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
5304 | && arm_const_double_rtx (XEXP (x, 1))) | |
5305 | { | |
5306 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5307 | return true; | |
5308 | } | |
5309 | ||
5310 | return false; | |
5311 | } | |
5312 | *total = COSTS_N_INSNS (20); | |
5313 | return false; | |
5314 | } | |
5315 | ||
5316 | *total = COSTS_N_INSNS (1); | |
5317 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
5318 | && const_ok_for_arm (INTVAL (XEXP (x, 0)))) | |
5319 | { | |
5320 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5321 | return true; | |
5322 | } | |
5323 | ||
5324 | subcode = GET_CODE (XEXP (x, 1)); | |
5325 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5326 | || subcode == LSHIFTRT | |
5327 | || subcode == ROTATE || subcode == ROTATERT) | |
5328 | { | |
5329 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5330 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
5331 | return true; | |
5332 | } | |
5333 | ||
b32f6fff KH |
5334 | /* A shift as a part of RSB costs no more than RSB itself. */ |
5335 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 5336 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
b32f6fff KH |
5337 | { |
5338 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, speed); | |
5339 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5340 | return true; | |
5341 | } | |
5342 | ||
d5a0a47b | 5343 | if (subcode == MULT |
4c7c486a | 5344 | && power_of_two_operand (XEXP (XEXP (x, 1), 1), SImode)) |
d5a0a47b RE |
5345 | { |
5346 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5347 | *total += rtx_cost (XEXP (XEXP (x, 1), 0), subcode, speed); | |
5348 | return true; | |
5349 | } | |
5350 | ||
5351 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMPARE | |
5352 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == RTX_COMM_COMPARE) | |
5353 | { | |
5354 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5355 | if (GET_CODE (XEXP (XEXP (x, 1), 0)) == REG | |
5356 | && REGNO (XEXP (XEXP (x, 1), 0)) != CC_REGNUM) | |
5357 | *total += COSTS_N_INSNS (1); | |
5358 | ||
5359 | return true; | |
5360 | } | |
5361 | ||
e2c671ba RE |
5362 | /* Fall through */ |
5363 | ||
f676971a | 5364 | case PLUS: |
d5a0a47b | 5365 | if (code == PLUS && arm_arch6 && mode == SImode |
ff069900 PB |
5366 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND |
5367 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
5368 | { |
5369 | *total = COSTS_N_INSNS (1); | |
5370 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), GET_CODE (XEXP (x, 0)), | |
5371 | speed); | |
5372 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5373 | return true; | |
5374 | } | |
ff069900 | 5375 | |
d5a0a47b RE |
5376 | /* MLA: All arguments must be registers. We filter out |
5377 | multiplication by a power of two, so that we fall down into | |
5378 | the code below. */ | |
5379 | if (GET_CODE (XEXP (x, 0)) == MULT | |
4c7c486a | 5380 | && !power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
26da58dd | 5381 | { |
d5a0a47b RE |
5382 | /* The cost comes from the cost of the multiply. */ |
5383 | return false; | |
26da58dd PB |
5384 | } |
5385 | ||
e2c671ba | 5386 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b RE |
5387 | { |
5388 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5389 | { | |
5390 | *total = COSTS_N_INSNS (1); | |
5391 | if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE | |
5392 | && arm_const_double_rtx (XEXP (x, 1))) | |
5393 | { | |
5394 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5395 | return true; | |
5396 | } | |
5397 | ||
5398 | return false; | |
5399 | } | |
5400 | ||
5401 | *total = COSTS_N_INSNS (20); | |
5402 | return false; | |
5403 | } | |
5404 | ||
5405 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMPARE | |
5406 | || GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == RTX_COMM_COMPARE) | |
5407 | { | |
5408 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 1), code, speed); | |
5409 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG | |
5410 | && REGNO (XEXP (XEXP (x, 0), 0)) != CC_REGNUM) | |
5411 | *total += COSTS_N_INSNS (1); | |
5412 | return true; | |
5413 | } | |
e2c671ba RE |
5414 | |
5415 | /* Fall through */ | |
d5a0a47b | 5416 | |
f676971a | 5417 | case AND: case XOR: case IOR: |
e2c671ba RE |
5418 | extra_cost = 0; |
5419 | ||
5420 | /* Normally the frame registers will be spilt into reg+const during | |
5421 | reload, so it is a bad idea to combine them with other instructions, | |
5422 | since then they might not be moved outside of loops. As a compromise | |
5423 | we allow integration with ops that have a constant as their second | |
5424 | operand. */ | |
5425 | if ((REG_OR_SUBREG_REG (XEXP (x, 0)) | |
5426 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) | |
5427 | && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
5428 | || (REG_OR_SUBREG_REG (XEXP (x, 0)) | |
5429 | && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) | |
d5a0a47b | 5430 | *total = 4; |
e2c671ba RE |
5431 | |
5432 | if (mode == DImode) | |
d5a0a47b RE |
5433 | { |
5434 | *total += COSTS_N_INSNS (2); | |
5435 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5436 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5437 | { | |
5438 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5439 | return true; | |
5440 | } | |
e2c671ba | 5441 | |
d5a0a47b RE |
5442 | return false; |
5443 | } | |
5444 | ||
5445 | *total += COSTS_N_INSNS (1); | |
5446 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5447 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5448 | { | |
5449 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5450 | return true; | |
5451 | } | |
5452 | subcode = GET_CODE (XEXP (x, 0)); | |
5453 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5454 | || subcode == LSHIFTRT | |
5455 | || subcode == ROTATE || subcode == ROTATERT) | |
5456 | { | |
5457 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5458 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5459 | return true; | |
5460 | } | |
5461 | ||
5462 | if (subcode == MULT | |
4c7c486a | 5463 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
5464 | { |
5465 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5466 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5467 | return true; | |
5468 | } | |
5469 | ||
5470 | if (subcode == UMIN || subcode == UMAX | |
5471 | || subcode == SMIN || subcode == SMAX) | |
5472 | { | |
5473 | *total = COSTS_N_INSNS (3); | |
5474 | return true; | |
5475 | } | |
5476 | ||
5477 | return false; | |
e2c671ba RE |
5478 | |
5479 | case MULT: | |
9b66ebb1 | 5480 | /* This should have been handled by the CPU specific routines. */ |
e6d29d15 | 5481 | gcc_unreachable (); |
e2c671ba | 5482 | |
56636818 | 5483 | case TRUNCATE: |
9b66ebb1 | 5484 | if (arm_arch3m && mode == SImode |
56636818 JL |
5485 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT |
5486 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5487 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) | |
5488 | == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) | |
5489 | && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND | |
5490 | || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) | |
d5a0a47b RE |
5491 | { |
5492 | *total = rtx_cost (XEXP (XEXP (x, 0), 0), LSHIFTRT, speed); | |
5493 | return true; | |
5494 | } | |
5495 | *total = COSTS_N_INSNS (2); /* Plus the cost of the MULT */ | |
5496 | return false; | |
56636818 | 5497 | |
e2c671ba RE |
5498 | case NEG: |
5499 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
d5a0a47b RE |
5500 | { |
5501 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5502 | { | |
5503 | *total = COSTS_N_INSNS (1); | |
5504 | return false; | |
5505 | } | |
5506 | *total = COSTS_N_INSNS (2); | |
5507 | return false; | |
5508 | } | |
5509 | ||
e2c671ba RE |
5510 | /* Fall through */ |
5511 | case NOT: | |
d5a0a47b RE |
5512 | *total = COSTS_N_INSNS (ARM_NUM_REGS(mode)); |
5513 | if (mode == SImode && code == NOT) | |
5514 | { | |
5515 | subcode = GET_CODE (XEXP (x, 0)); | |
5516 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5517 | || subcode == LSHIFTRT | |
5518 | || subcode == ROTATE || subcode == ROTATERT | |
5519 | || (subcode == MULT | |
4c7c486a | 5520 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode))) |
d5a0a47b RE |
5521 | { |
5522 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5523 | /* Register shifts cost an extra cycle. */ | |
5524 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) | |
5525 | *total += COSTS_N_INSNS (1) + rtx_cost (XEXP (XEXP (x, 0), 1), | |
5526 | subcode, speed); | |
5527 | return true; | |
5528 | } | |
5529 | } | |
e2c671ba | 5530 | |
d5a0a47b | 5531 | return false; |
e2c671ba RE |
5532 | |
5533 | case IF_THEN_ELSE: | |
5534 | if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) | |
d5a0a47b RE |
5535 | { |
5536 | *total = COSTS_N_INSNS (4); | |
5537 | return true; | |
5538 | } | |
5539 | ||
5540 | operand = XEXP (x, 0); | |
5541 | ||
5542 | if (!((GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMPARE | |
5543 | || GET_RTX_CLASS (GET_CODE (operand)) == RTX_COMM_COMPARE) | |
5544 | && GET_CODE (XEXP (operand, 0)) == REG | |
5545 | && REGNO (XEXP (operand, 0)) == CC_REGNUM)) | |
5546 | *total += COSTS_N_INSNS (1); | |
5547 | *total += (rtx_cost (XEXP (x, 1), code, speed) | |
5548 | + rtx_cost (XEXP (x, 2), code, speed)); | |
5549 | return true; | |
5550 | ||
5551 | case NE: | |
5552 | if (mode == SImode && XEXP (x, 1) == const0_rtx) | |
5553 | { | |
5554 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5555 | return true; | |
5556 | } | |
5557 | goto scc_insn; | |
5558 | ||
5559 | case GE: | |
5560 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
5561 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
5562 | { | |
5563 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5564 | return true; | |
5565 | } | |
5566 | goto scc_insn; | |
5567 | ||
5568 | case LT: | |
5569 | if ((GET_CODE (XEXP (x, 0)) != REG || REGNO (XEXP (x, 0)) != CC_REGNUM) | |
5570 | && mode == SImode && XEXP (x, 1) == const0_rtx) | |
5571 | { | |
5572 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5573 | return true; | |
5574 | } | |
5575 | goto scc_insn; | |
5576 | ||
5577 | case EQ: | |
5578 | case GT: | |
5579 | case LE: | |
5580 | case GEU: | |
5581 | case LTU: | |
5582 | case GTU: | |
5583 | case LEU: | |
5584 | case UNORDERED: | |
5585 | case ORDERED: | |
5586 | case UNEQ: | |
5587 | case UNGE: | |
5588 | case UNLT: | |
5589 | case UNGT: | |
5590 | case UNLE: | |
5591 | scc_insn: | |
5592 | /* SCC insns. In the case where the comparison has already been | |
5593 | performed, then they cost 2 instructions. Otherwise they need | |
5594 | an additional comparison before them. */ | |
5595 | *total = COSTS_N_INSNS (2); | |
5596 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) | |
5597 | { | |
5598 | return true; | |
5599 | } | |
e2c671ba | 5600 | |
d5a0a47b | 5601 | /* Fall through */ |
e2c671ba | 5602 | case COMPARE: |
d5a0a47b RE |
5603 | if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == CC_REGNUM) |
5604 | { | |
5605 | *total = 0; | |
5606 | return true; | |
5607 | } | |
5608 | ||
5609 | *total += COSTS_N_INSNS (1); | |
5610 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5611 | && const_ok_for_op (INTVAL (XEXP (x, 1)), code)) | |
5612 | { | |
5613 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5614 | return true; | |
5615 | } | |
5616 | ||
5617 | subcode = GET_CODE (XEXP (x, 0)); | |
5618 | if (subcode == ASHIFT || subcode == ASHIFTRT | |
5619 | || subcode == LSHIFTRT | |
5620 | || subcode == ROTATE || subcode == ROTATERT) | |
5621 | { | |
5622 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5623 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5624 | return true; | |
5625 | } | |
5626 | ||
5627 | if (subcode == MULT | |
4c7c486a | 5628 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) |
d5a0a47b RE |
5629 | { |
5630 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5631 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), subcode, speed); | |
5632 | return true; | |
5633 | } | |
5634 | ||
5635 | return false; | |
5636 | ||
5637 | case UMIN: | |
5638 | case UMAX: | |
5639 | case SMIN: | |
5640 | case SMAX: | |
5641 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, speed); | |
5642 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5643 | || !const_ok_for_arm (INTVAL (XEXP (x, 1)))) | |
5644 | *total += rtx_cost (XEXP (x, 1), code, speed); | |
5645 | return true; | |
e2c671ba RE |
5646 | |
5647 | case ABS: | |
bbbbb16a | 5648 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
d5a0a47b RE |
5649 | { |
5650 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
5651 | { | |
5652 | *total = COSTS_N_INSNS (1); | |
5653 | return false; | |
5654 | } | |
5655 | *total = COSTS_N_INSNS (20); | |
5656 | return false; | |
5657 | } | |
5658 | *total = COSTS_N_INSNS (1); | |
5659 | if (mode == DImode) | |
5660 | *total += COSTS_N_INSNS (3); | |
5661 | return false; | |
e2c671ba RE |
5662 | |
5663 | case SIGN_EXTEND: | |
d5a0a47b RE |
5664 | if (GET_MODE_CLASS (mode) == MODE_INT) |
5665 | { | |
5666 | *total = 0; | |
5667 | if (mode == DImode) | |
5668 | *total += COSTS_N_INSNS (1); | |
5669 | ||
5670 | if (GET_MODE (XEXP (x, 0)) != SImode) | |
5671 | { | |
5672 | if (arm_arch6) | |
5673 | { | |
5674 | if (GET_CODE (XEXP (x, 0)) != MEM) | |
5675 | *total += COSTS_N_INSNS (1); | |
5676 | } | |
5677 | else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | |
5678 | *total += COSTS_N_INSNS (2); | |
5679 | } | |
5680 | ||
5681 | return false; | |
5682 | } | |
ff069900 | 5683 | |
e2c671ba RE |
5684 | /* Fall through */ |
5685 | case ZERO_EXTEND: | |
d5a0a47b RE |
5686 | *total = 0; |
5687 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
e2c671ba | 5688 | { |
d5a0a47b RE |
5689 | if (mode == DImode) |
5690 | *total += COSTS_N_INSNS (1); | |
e2c671ba | 5691 | |
d5a0a47b RE |
5692 | if (GET_MODE (XEXP (x, 0)) != SImode) |
5693 | { | |
5694 | if (arm_arch6) | |
5695 | { | |
5696 | if (GET_CODE (XEXP (x, 0)) != MEM) | |
5697 | *total += COSTS_N_INSNS (1); | |
5698 | } | |
5699 | else if (!arm_arch4 || GET_CODE (XEXP (x, 0)) != MEM) | |
5700 | *total += COSTS_N_INSNS (GET_MODE (XEXP (x, 0)) == QImode ? | |
5701 | 1 : 2); | |
5702 | } | |
e2c671ba | 5703 | |
d5a0a47b RE |
5704 | return false; |
5705 | } | |
ad076f4e | 5706 | |
d5a0a47b RE |
5707 | switch (GET_MODE (XEXP (x, 0))) |
5708 | { | |
5a9335ef NC |
5709 | case V8QImode: |
5710 | case V4HImode: | |
5711 | case V2SImode: | |
5712 | case V4QImode: | |
5713 | case V2HImode: | |
d5a0a47b RE |
5714 | *total = COSTS_N_INSNS (1); |
5715 | return false; | |
5a9335ef | 5716 | |
ad076f4e | 5717 | default: |
e6d29d15 | 5718 | gcc_unreachable (); |
e2c671ba | 5719 | } |
e6d29d15 | 5720 | gcc_unreachable (); |
e2c671ba | 5721 | |
d5a0a47b RE |
5722 | case ZERO_EXTRACT: |
5723 | case SIGN_EXTRACT: | |
5724 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, speed); | |
5725 | return true; | |
5726 | ||
f676971a | 5727 | case CONST_INT: |
d5a0a47b RE |
5728 | if (const_ok_for_arm (INTVAL (x)) |
5729 | || const_ok_for_arm (~INTVAL (x))) | |
5730 | *total = COSTS_N_INSNS (1); | |
f676971a | 5731 | else |
d5a0a47b RE |
5732 | *total = COSTS_N_INSNS (arm_gen_constant (SET, mode, NULL_RTX, |
5733 | INTVAL (x), NULL_RTX, | |
5734 | NULL_RTX, 0, 0)); | |
5735 | return true; | |
f676971a EC |
5736 | |
5737 | case CONST: | |
5738 | case LABEL_REF: | |
5739 | case SYMBOL_REF: | |
d5a0a47b RE |
5740 | *total = COSTS_N_INSNS (3); |
5741 | return true; | |
f676971a | 5742 | |
571191af | 5743 | case HIGH: |
d5a0a47b RE |
5744 | *total = COSTS_N_INSNS (1); |
5745 | return true; | |
5746 | ||
571191af | 5747 | case LO_SUM: |
d5a0a47b RE |
5748 | *total = COSTS_N_INSNS (1); |
5749 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
5750 | return true; | |
571191af | 5751 | |
f676971a | 5752 | case CONST_DOUBLE: |
d5a0a47b RE |
5753 | if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)) |
5754 | *total = COSTS_N_INSNS (1); | |
5755 | else | |
5756 | *total = COSTS_N_INSNS (4); | |
5757 | return true; | |
f676971a | 5758 | |
e2c671ba | 5759 | default: |
d5a0a47b RE |
5760 | *total = COSTS_N_INSNS (4); |
5761 | return false; | |
e2c671ba RE |
5762 | } |
5763 | } | |
32de079a | 5764 | |
21b5653c RE |
5765 | /* RTX costs when optimizing for size. */ |
5766 | static bool | |
d5a0a47b RE |
5767 | arm_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
5768 | int *total) | |
21b5653c RE |
5769 | { |
5770 | enum machine_mode mode = GET_MODE (x); | |
09754904 | 5771 | if (TARGET_THUMB1) |
21b5653c RE |
5772 | { |
5773 | /* XXX TBD. For now, use the standard costs. */ | |
5b3e6663 | 5774 | *total = thumb1_rtx_costs (x, code, outer_code); |
21b5653c RE |
5775 | return true; |
5776 | } | |
5777 | ||
09754904 | 5778 | /* FIXME: This makes no attempt to prefer narrow Thumb-2 instructions. */ |
21b5653c RE |
5779 | switch (code) |
5780 | { | |
5781 | case MEM: | |
f676971a | 5782 | /* A memory access costs 1 insn if the mode is small, or the address is |
21b5653c RE |
5783 | a single register, otherwise it costs one insn per word. */ |
5784 | if (REG_P (XEXP (x, 0))) | |
5785 | *total = COSTS_N_INSNS (1); | |
5786 | else | |
5787 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5788 | return true; | |
5789 | ||
5790 | case DIV: | |
5791 | case MOD: | |
5792 | case UDIV: | |
5793 | case UMOD: | |
5794 | /* Needs a libcall, so it costs about this. */ | |
5795 | *total = COSTS_N_INSNS (2); | |
5796 | return false; | |
5797 | ||
5798 | case ROTATE: | |
5799 | if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) | |
5800 | { | |
f40751dd | 5801 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5802 | return true; |
5803 | } | |
5804 | /* Fall through */ | |
5805 | case ROTATERT: | |
5806 | case ASHIFT: | |
5807 | case LSHIFTRT: | |
5808 | case ASHIFTRT: | |
5809 | if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
5810 | { | |
f40751dd | 5811 | *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5812 | return true; |
5813 | } | |
5814 | else if (mode == SImode) | |
5815 | { | |
f40751dd | 5816 | *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code, false); |
21b5653c RE |
5817 | /* Slightly disparage register shifts, but not by much. */ |
5818 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
f40751dd | 5819 | *total += 1 + rtx_cost (XEXP (x, 1), code, false); |
21b5653c RE |
5820 | return true; |
5821 | } | |
5822 | ||
5823 | /* Needs a libcall. */ | |
5824 | *total = COSTS_N_INSNS (2); | |
5825 | return false; | |
5826 | ||
5827 | case MINUS: | |
5828 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5829 | { | |
5830 | *total = COSTS_N_INSNS (1); | |
5831 | return false; | |
5832 | } | |
5833 | ||
5834 | if (mode == SImode) | |
5835 | { | |
5836 | enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); | |
5837 | enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); | |
5838 | ||
5839 | if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT | |
5840 | || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT | |
5841 | || subcode1 == ROTATE || subcode1 == ROTATERT | |
5842 | || subcode1 == ASHIFT || subcode1 == LSHIFTRT | |
5843 | || subcode1 == ASHIFTRT) | |
5844 | { | |
5845 | /* It's just the cost of the two operands. */ | |
5846 | *total = 0; | |
5847 | return false; | |
5848 | } | |
5849 | ||
5850 | *total = COSTS_N_INSNS (1); | |
5851 | return false; | |
5852 | } | |
5853 | ||
5854 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5855 | return false; | |
5856 | ||
f676971a | 5857 | case PLUS: |
21b5653c RE |
5858 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
5859 | { | |
5860 | *total = COSTS_N_INSNS (1); | |
5861 | return false; | |
5862 | } | |
5863 | ||
6e782a29 KH |
5864 | /* A shift as a part of ADD costs nothing. */ |
5865 | if (GET_CODE (XEXP (x, 0)) == MULT | |
5866 | && power_of_two_operand (XEXP (XEXP (x, 0), 1), SImode)) | |
5867 | { | |
5868 | *total = COSTS_N_INSNS (TARGET_THUMB2 ? 2 : 1); | |
5869 | *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, false); | |
5870 | *total += rtx_cost (XEXP (x, 1), code, false); | |
5871 | return true; | |
5872 | } | |
5873 | ||
21b5653c RE |
5874 | /* Fall through */ |
5875 | case AND: case XOR: case IOR: | |
5876 | if (mode == SImode) | |
5877 | { | |
5878 | enum rtx_code subcode = GET_CODE (XEXP (x, 0)); | |
5879 | ||
5880 | if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT | |
5881 | || subcode == LSHIFTRT || subcode == ASHIFTRT | |
5882 | || (code == AND && subcode == NOT)) | |
5883 | { | |
5884 | /* It's just the cost of the two operands. */ | |
5885 | *total = 0; | |
5886 | return false; | |
5887 | } | |
5888 | } | |
5889 | ||
5890 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5891 | return false; | |
5892 | ||
5893 | case MULT: | |
5894 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5895 | return false; | |
5896 | ||
5897 | case NEG: | |
5898 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
7ce8451d MG |
5899 | { |
5900 | *total = COSTS_N_INSNS (1); | |
5901 | return false; | |
5902 | } | |
5903 | ||
21b5653c RE |
5904 | /* Fall through */ |
5905 | case NOT: | |
5906 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
5907 | ||
5908 | return false; | |
5909 | ||
5910 | case IF_THEN_ELSE: | |
5911 | *total = 0; | |
5912 | return false; | |
5913 | ||
5914 | case COMPARE: | |
5915 | if (cc_register (XEXP (x, 0), VOIDmode)) | |
5916 | * total = 0; | |
5917 | else | |
5918 | *total = COSTS_N_INSNS (1); | |
5919 | return false; | |
5920 | ||
5921 | case ABS: | |
5922 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5923 | *total = COSTS_N_INSNS (1); | |
5924 | else | |
5925 | *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); | |
5926 | return false; | |
5927 | ||
5928 | case SIGN_EXTEND: | |
5929 | *total = 0; | |
5930 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) | |
5931 | { | |
5932 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5933 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
5934 | } | |
5935 | if (mode == DImode) | |
5936 | *total += COSTS_N_INSNS (1); | |
5937 | return false; | |
5938 | ||
5939 | case ZERO_EXTEND: | |
5940 | *total = 0; | |
5941 | if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) | |
5942 | { | |
5943 | switch (GET_MODE (XEXP (x, 0))) | |
5944 | { | |
5945 | case QImode: | |
5946 | *total += COSTS_N_INSNS (1); | |
5947 | break; | |
5948 | ||
5949 | case HImode: | |
5950 | *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); | |
f676971a | 5951 | |
21b5653c RE |
5952 | case SImode: |
5953 | break; | |
5954 | ||
5955 | default: | |
5956 | *total += COSTS_N_INSNS (2); | |
5957 | } | |
5958 | } | |
5959 | ||
5960 | if (mode == DImode) | |
5961 | *total += COSTS_N_INSNS (1); | |
5962 | ||
5963 | return false; | |
5964 | ||
f676971a EC |
5965 | case CONST_INT: |
5966 | if (const_ok_for_arm (INTVAL (x))) | |
6e782a29 KH |
5967 | /* A multiplication by a constant requires another instruction |
5968 | to load the constant to a register. */ | |
5969 | *total = COSTS_N_INSNS ((outer_code == SET || outer_code == MULT) | |
5970 | ? 1 : 0); | |
21b5653c RE |
5971 | else if (const_ok_for_arm (~INTVAL (x))) |
5972 | *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); | |
5973 | else if (const_ok_for_arm (-INTVAL (x))) | |
5974 | { | |
5975 | if (outer_code == COMPARE || outer_code == PLUS | |
5976 | || outer_code == MINUS) | |
5977 | *total = 0; | |
5978 | else | |
5979 | *total = COSTS_N_INSNS (1); | |
5980 | } | |
5981 | else | |
5982 | *total = COSTS_N_INSNS (2); | |
5983 | return true; | |
f676971a EC |
5984 | |
5985 | case CONST: | |
5986 | case LABEL_REF: | |
5987 | case SYMBOL_REF: | |
21b5653c RE |
5988 | *total = COSTS_N_INSNS (2); |
5989 | return true; | |
f676971a | 5990 | |
21b5653c RE |
5991 | case CONST_DOUBLE: |
5992 | *total = COSTS_N_INSNS (4); | |
5993 | return true; | |
5994 | ||
571191af PB |
5995 | case HIGH: |
5996 | case LO_SUM: | |
5997 | /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the | |
5998 | cost of these slightly. */ | |
5999 | *total = COSTS_N_INSNS (1) + 1; | |
6000 | return true; | |
6001 | ||
21b5653c RE |
6002 | default: |
6003 | if (mode != VOIDmode) | |
6004 | *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); | |
6005 | else | |
6006 | *total = COSTS_N_INSNS (4); /* How knows? */ | |
6007 | return false; | |
6008 | } | |
6009 | } | |
6010 | ||
f40751dd JH |
6011 | /* RTX costs when optimizing for size. */ |
6012 | static bool | |
d5a0a47b RE |
6013 | arm_rtx_costs (rtx x, int code, int outer_code, int *total, |
6014 | bool speed) | |
f40751dd JH |
6015 | { |
6016 | if (!speed) | |
bbbbb16a ILT |
6017 | return arm_size_rtx_costs (x, (enum rtx_code) code, |
6018 | (enum rtx_code) outer_code, total); | |
f40751dd | 6019 | else |
bbbbb16a ILT |
6020 | return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code, |
6021 | (enum rtx_code) outer_code, | |
6022 | total, speed); | |
f40751dd JH |
6023 | } |
6024 | ||
5b3e6663 PB |
6025 | /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not |
6026 | supported on any "slowmul" cores, so it can be ignored. */ | |
9b66ebb1 | 6027 | |
3c50106f | 6028 | static bool |
d5a0a47b RE |
6029 | arm_slowmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
6030 | int *total, bool speed) | |
3c50106f | 6031 | { |
9b66ebb1 PB |
6032 | enum machine_mode mode = GET_MODE (x); |
6033 | ||
6034 | if (TARGET_THUMB) | |
6035 | { | |
5b3e6663 | 6036 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
6037 | return true; |
6038 | } | |
f676971a | 6039 | |
9b66ebb1 PB |
6040 | switch (code) |
6041 | { | |
6042 | case MULT: | |
6043 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
6044 | || mode == DImode) | |
6045 | { | |
d5a0a47b RE |
6046 | *total = COSTS_N_INSNS (20); |
6047 | return false; | |
9b66ebb1 PB |
6048 | } |
6049 | ||
6050 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6051 | { | |
6052 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
6053 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
6054 | int cost, const_ok = const_ok_for_arm (i); | |
6055 | int j, booth_unit_size; | |
6056 | ||
f676971a | 6057 | /* Tune as appropriate. */ |
9b66ebb1 PB |
6058 | cost = const_ok ? 4 : 8; |
6059 | booth_unit_size = 2; | |
6060 | for (j = 0; i && j < 32; j += booth_unit_size) | |
6061 | { | |
6062 | i >>= booth_unit_size; | |
d5a0a47b | 6063 | cost++; |
9b66ebb1 PB |
6064 | } |
6065 | ||
d5a0a47b RE |
6066 | *total = COSTS_N_INSNS (cost); |
6067 | *total += rtx_cost (XEXP (x, 0), code, speed); | |
9b66ebb1 PB |
6068 | return true; |
6069 | } | |
6070 | ||
d5a0a47b RE |
6071 | *total = COSTS_N_INSNS (20); |
6072 | return false; | |
f676971a | 6073 | |
9b66ebb1 | 6074 | default: |
d5a0a47b | 6075 | return arm_rtx_costs_1 (x, outer_code, total, speed);; |
9b66ebb1 | 6076 | } |
3c50106f RH |
6077 | } |
6078 | ||
9b66ebb1 PB |
6079 | |
6080 | /* RTX cost for cores with a fast multiply unit (M variants). */ | |
6081 | ||
6082 | static bool | |
d5a0a47b RE |
6083 | arm_fastmul_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
6084 | int *total, bool speed) | |
9b66ebb1 PB |
6085 | { |
6086 | enum machine_mode mode = GET_MODE (x); | |
6087 | ||
5b3e6663 | 6088 | if (TARGET_THUMB1) |
9b66ebb1 | 6089 | { |
5b3e6663 | 6090 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
6091 | return true; |
6092 | } | |
f676971a | 6093 | |
5b3e6663 | 6094 | /* ??? should thumb2 use different costs? */ |
9b66ebb1 PB |
6095 | switch (code) |
6096 | { | |
6097 | case MULT: | |
6098 | /* There is no point basing this on the tuning, since it is always the | |
6099 | fast variant if it exists at all. */ | |
6100 | if (mode == DImode | |
6101 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
6102 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
6103 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
6104 | { | |
d5a0a47b RE |
6105 | *total = COSTS_N_INSNS(2); |
6106 | return false; | |
9b66ebb1 | 6107 | } |
f676971a | 6108 | |
9b66ebb1 | 6109 | |
d5a0a47b | 6110 | if (mode == DImode) |
9b66ebb1 | 6111 | { |
d5a0a47b RE |
6112 | *total = COSTS_N_INSNS (5); |
6113 | return false; | |
9b66ebb1 PB |
6114 | } |
6115 | ||
6116 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6117 | { | |
6118 | unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) | |
6119 | & (unsigned HOST_WIDE_INT) 0xffffffff); | |
6120 | int cost, const_ok = const_ok_for_arm (i); | |
6121 | int j, booth_unit_size; | |
6122 | ||
f676971a | 6123 | /* Tune as appropriate. */ |
9b66ebb1 PB |
6124 | cost = const_ok ? 4 : 8; |
6125 | booth_unit_size = 8; | |
6126 | for (j = 0; i && j < 32; j += booth_unit_size) | |
6127 | { | |
6128 | i >>= booth_unit_size; | |
d5a0a47b | 6129 | cost++; |
9b66ebb1 PB |
6130 | } |
6131 | ||
d5a0a47b RE |
6132 | *total = COSTS_N_INSNS(cost); |
6133 | return false; | |
9b66ebb1 PB |
6134 | } |
6135 | ||
d5a0a47b RE |
6136 | if (mode == SImode) |
6137 | { | |
6138 | *total = COSTS_N_INSNS (4); | |
6139 | return false; | |
6140 | } | |
6141 | ||
6142 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) | |
6143 | { | |
6144 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
6145 | { | |
6146 | *total = COSTS_N_INSNS (1); | |
6147 | return false; | |
6148 | } | |
6149 | } | |
6150 | ||
6151 | /* Requires a lib call */ | |
6152 | *total = COSTS_N_INSNS (20); | |
6153 | return false; | |
f676971a | 6154 | |
9b66ebb1 | 6155 | default: |
d5a0a47b | 6156 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
6157 | } |
6158 | } | |
6159 | ||
6160 | ||
5b3e6663 PB |
6161 | /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores, |
6162 | so it can be ignored. */ | |
9b66ebb1 PB |
6163 | |
6164 | static bool | |
d5a0a47b | 6165 | arm_xscale_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, int *total, bool speed) |
9b66ebb1 PB |
6166 | { |
6167 | enum machine_mode mode = GET_MODE (x); | |
6168 | ||
6169 | if (TARGET_THUMB) | |
6170 | { | |
5b3e6663 | 6171 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
6172 | return true; |
6173 | } | |
f676971a | 6174 | |
9b66ebb1 PB |
6175 | switch (code) |
6176 | { | |
d5a0a47b RE |
6177 | case COMPARE: |
6178 | if (GET_CODE (XEXP (x, 0)) != MULT) | |
6179 | return arm_rtx_costs_1 (x, outer_code, total, speed); | |
6180 | ||
6181 | /* A COMPARE of a MULT is slow on XScale; the muls instruction | |
6182 | will stall until the multiplication is complete. */ | |
6183 | *total = COSTS_N_INSNS (3); | |
6184 | return false; | |
6185 | ||
9b66ebb1 PB |
6186 | case MULT: |
6187 | /* There is no point basing this on the tuning, since it is always the | |
6188 | fast variant if it exists at all. */ | |
6189 | if (mode == DImode | |
6190 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
6191 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
6192 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
6193 | { | |
d5a0a47b RE |
6194 | *total = COSTS_N_INSNS (2); |
6195 | return false; | |
9b66ebb1 | 6196 | } |
f676971a | 6197 | |
9b66ebb1 | 6198 | |
d5a0a47b | 6199 | if (mode == DImode) |
9b66ebb1 | 6200 | { |
d5a0a47b RE |
6201 | *total = COSTS_N_INSNS (5); |
6202 | return false; | |
9b66ebb1 PB |
6203 | } |
6204 | ||
6205 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6206 | { | |
d5a0a47b RE |
6207 | /* If operand 1 is a constant we can more accurately |
6208 | calculate the cost of the multiply. The multiplier can | |
6209 | retire 15 bits on the first cycle and a further 12 on the | |
6210 | second. We do, of course, have to load the constant into | |
6211 | a register first. */ | |
6212 | unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); | |
6213 | /* There's a general overhead of one cycle. */ | |
6214 | int cost = 1; | |
9b66ebb1 PB |
6215 | unsigned HOST_WIDE_INT masked_const; |
6216 | ||
d5a0a47b RE |
6217 | if (i & 0x80000000) |
6218 | i = ~i; | |
6219 | ||
6220 | i &= (unsigned HOST_WIDE_INT) 0xffffffff; | |
6221 | ||
9b66ebb1 | 6222 | masked_const = i & 0xffff8000; |
d5a0a47b | 6223 | if (masked_const != 0) |
9b66ebb1 | 6224 | { |
d5a0a47b | 6225 | cost++; |
9b66ebb1 | 6226 | masked_const = i & 0xf8000000; |
d5a0a47b RE |
6227 | if (masked_const != 0) |
6228 | cost++; | |
9b66ebb1 | 6229 | } |
d5a0a47b RE |
6230 | *total = COSTS_N_INSNS (cost); |
6231 | return false; | |
9b66ebb1 PB |
6232 | } |
6233 | ||
d5a0a47b RE |
6234 | if (mode == SImode) |
6235 | { | |
6236 | *total = COSTS_N_INSNS (3); | |
6237 | return false; | |
6238 | } | |
f676971a | 6239 | |
d5a0a47b RE |
6240 | /* Requires a lib call */ |
6241 | *total = COSTS_N_INSNS (20); | |
6242 | return false; | |
06d5588c | 6243 | |
9b66ebb1 | 6244 | default: |
d5a0a47b | 6245 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
6246 | } |
6247 | } | |
6248 | ||
6249 | ||
6250 | /* RTX costs for 9e (and later) cores. */ | |
6251 | ||
6252 | static bool | |
d5a0a47b RE |
6253 | arm_9e_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, |
6254 | int *total, bool speed) | |
9b66ebb1 PB |
6255 | { |
6256 | enum machine_mode mode = GET_MODE (x); | |
f676971a | 6257 | |
5b3e6663 | 6258 | if (TARGET_THUMB1) |
9b66ebb1 PB |
6259 | { |
6260 | switch (code) | |
6261 | { | |
6262 | case MULT: | |
6263 | *total = COSTS_N_INSNS (3); | |
6264 | return true; | |
f676971a | 6265 | |
9b66ebb1 | 6266 | default: |
5b3e6663 | 6267 | *total = thumb1_rtx_costs (x, code, outer_code); |
9b66ebb1 PB |
6268 | return true; |
6269 | } | |
6270 | } | |
f676971a | 6271 | |
9b66ebb1 PB |
6272 | switch (code) |
6273 | { | |
6274 | case MULT: | |
6275 | /* There is no point basing this on the tuning, since it is always the | |
6276 | fast variant if it exists at all. */ | |
6277 | if (mode == DImode | |
6278 | && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) | |
6279 | && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND | |
6280 | || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) | |
6281 | { | |
d5a0a47b RE |
6282 | *total = COSTS_N_INSNS (2); |
6283 | return false; | |
9b66ebb1 | 6284 | } |
f676971a | 6285 | |
9b66ebb1 | 6286 | |
9b66ebb1 PB |
6287 | if (mode == DImode) |
6288 | { | |
d5a0a47b RE |
6289 | *total = COSTS_N_INSNS (5); |
6290 | return false; | |
9b66ebb1 | 6291 | } |
d5a0a47b RE |
6292 | |
6293 | if (mode == SImode) | |
9b66ebb1 | 6294 | { |
d5a0a47b RE |
6295 | *total = COSTS_N_INSNS (2); |
6296 | return false; | |
9b66ebb1 PB |
6297 | } |
6298 | ||
d5a0a47b RE |
6299 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
6300 | { | |
6301 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) | |
6302 | { | |
6303 | *total = COSTS_N_INSNS (1); | |
6304 | return false; | |
6305 | } | |
6306 | } | |
9b66ebb1 | 6307 | |
d5a0a47b RE |
6308 | *total = COSTS_N_INSNS (20); |
6309 | return false; | |
f676971a | 6310 | |
9b66ebb1 | 6311 | default: |
d5a0a47b | 6312 | return arm_rtx_costs_1 (x, outer_code, total, speed); |
9b66ebb1 PB |
6313 | } |
6314 | } | |
dcefdf67 RH |
6315 | /* All address computations that can be done are free, but rtx cost returns |
6316 | the same for practically all of them. So we weight the different types | |
6317 | of address here in the order (most pref first): | |
d6b4baa4 | 6318 | PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ |
d2b6eb76 ZW |
6319 | static inline int |
6320 | arm_arm_address_cost (rtx x) | |
6321 | { | |
6322 | enum rtx_code c = GET_CODE (x); | |
6323 | ||
6324 | if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) | |
6325 | return 0; | |
6326 | if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) | |
6327 | return 10; | |
6328 | ||
6329 | if (c == PLUS || c == MINUS) | |
6330 | { | |
d2b6eb76 ZW |
6331 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
6332 | return 2; | |
6333 | ||
ec8e098d | 6334 | if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) |
d2b6eb76 ZW |
6335 | return 3; |
6336 | ||
6337 | return 4; | |
6338 | } | |
6339 | ||
6340 | return 6; | |
6341 | } | |
6342 | ||
6343 | static inline int | |
6344 | arm_thumb_address_cost (rtx x) | |
6345 | { | |
6346 | enum rtx_code c = GET_CODE (x); | |
6347 | ||
6348 | if (c == REG) | |
6349 | return 1; | |
6350 | if (c == PLUS | |
6351 | && GET_CODE (XEXP (x, 0)) == REG | |
6352 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
6353 | return 1; | |
6354 | ||
6355 | return 2; | |
6356 | } | |
6357 | ||
dcefdf67 | 6358 | static int |
f40751dd | 6359 | arm_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
dcefdf67 | 6360 | { |
5b3e6663 | 6361 | return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); |
dcefdf67 RH |
6362 | } |
6363 | ||
c237e94a | 6364 | static int |
e32bac5b | 6365 | arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) |
32de079a RE |
6366 | { |
6367 | rtx i_pat, d_pat; | |
6368 | ||
d19fb8e3 NC |
6369 | /* Some true dependencies can have a higher cost depending |
6370 | on precisely how certain input operands are used. */ | |
4b3c2e48 | 6371 | if (arm_tune_xscale |
d19fb8e3 | 6372 | && REG_NOTE_KIND (link) == 0 |
eda833e3 BE |
6373 | && recog_memoized (insn) >= 0 |
6374 | && recog_memoized (dep) >= 0) | |
d19fb8e3 NC |
6375 | { |
6376 | int shift_opnum = get_attr_shift (insn); | |
6377 | enum attr_type attr_type = get_attr_type (dep); | |
6378 | ||
6379 | /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted | |
6380 | operand for INSN. If we have a shifted input operand and the | |
6381 | instruction we depend on is another ALU instruction, then we may | |
6382 | have to account for an additional stall. */ | |
9b66ebb1 PB |
6383 | if (shift_opnum != 0 |
6384 | && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) | |
d19fb8e3 NC |
6385 | { |
6386 | rtx shifted_operand; | |
6387 | int opno; | |
f676971a | 6388 | |
d19fb8e3 NC |
6389 | /* Get the shifted operand. */ |
6390 | extract_insn (insn); | |
6391 | shifted_operand = recog_data.operand[shift_opnum]; | |
6392 | ||
6393 | /* Iterate over all the operands in DEP. If we write an operand | |
6394 | that overlaps with SHIFTED_OPERAND, then we have increase the | |
6395 | cost of this dependency. */ | |
6396 | extract_insn (dep); | |
6397 | preprocess_constraints (); | |
6398 | for (opno = 0; opno < recog_data.n_operands; opno++) | |
6399 | { | |
6400 | /* We can ignore strict inputs. */ | |
6401 | if (recog_data.operand_type[opno] == OP_IN) | |
6402 | continue; | |
6403 | ||
6404 | if (reg_overlap_mentioned_p (recog_data.operand[opno], | |
6405 | shifted_operand)) | |
6406 | return 2; | |
6407 | } | |
6408 | } | |
6409 | } | |
6410 | ||
6354dc9b | 6411 | /* XXX This is not strictly true for the FPA. */ |
d5b7b3ae RE |
6412 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI |
6413 | || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) | |
b36ba79f RE |
6414 | return 0; |
6415 | ||
d5b7b3ae RE |
6416 | /* Call insns don't incur a stall, even if they follow a load. */ |
6417 | if (REG_NOTE_KIND (link) == 0 | |
6418 | && GET_CODE (insn) == CALL_INSN) | |
6419 | return 1; | |
6420 | ||
32de079a RE |
6421 | if ((i_pat = single_set (insn)) != NULL |
6422 | && GET_CODE (SET_SRC (i_pat)) == MEM | |
6423 | && (d_pat = single_set (dep)) != NULL | |
6424 | && GET_CODE (SET_DEST (d_pat)) == MEM) | |
6425 | { | |
48f6efae | 6426 | rtx src_mem = XEXP (SET_SRC (i_pat), 0); |
32de079a RE |
6427 | /* This is a load after a store, there is no conflict if the load reads |
6428 | from a cached area. Assume that loads from the stack, and from the | |
f676971a | 6429 | constant pool are cached, and that others will miss. This is a |
6354dc9b | 6430 | hack. */ |
f676971a | 6431 | |
48f6efae NC |
6432 | if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) |
6433 | || reg_mentioned_p (stack_pointer_rtx, src_mem) | |
6434 | || reg_mentioned_p (frame_pointer_rtx, src_mem) | |
6435 | || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) | |
949d79eb | 6436 | return 1; |
32de079a RE |
6437 | } |
6438 | ||
6439 | return cost; | |
6440 | } | |
6441 | ||
9b66ebb1 | 6442 | static int fp_consts_inited = 0; |
ff9940b0 | 6443 | |
9b66ebb1 PB |
6444 | /* Only zero is valid for VFP. Other values are also valid for FPA. */ |
6445 | static const char * const strings_fp[8] = | |
62b10bbc | 6446 | { |
2b835d68 RE |
6447 | "0", "1", "2", "3", |
6448 | "4", "5", "0.5", "10" | |
6449 | }; | |
ff9940b0 | 6450 | |
9b66ebb1 | 6451 | static REAL_VALUE_TYPE values_fp[8]; |
ff9940b0 RE |
6452 | |
6453 | static void | |
9b66ebb1 | 6454 | init_fp_table (void) |
ff9940b0 RE |
6455 | { |
6456 | int i; | |
6457 | REAL_VALUE_TYPE r; | |
6458 | ||
9b66ebb1 PB |
6459 | if (TARGET_VFP) |
6460 | fp_consts_inited = 1; | |
6461 | else | |
6462 | fp_consts_inited = 8; | |
6463 | ||
6464 | for (i = 0; i < fp_consts_inited; i++) | |
ff9940b0 | 6465 | { |
9b66ebb1 PB |
6466 | r = REAL_VALUE_ATOF (strings_fp[i], DFmode); |
6467 | values_fp[i] = r; | |
ff9940b0 | 6468 | } |
ff9940b0 RE |
6469 | } |
6470 | ||
9b66ebb1 | 6471 | /* Return TRUE if rtx X is a valid immediate FP constant. */ |
cce8749e | 6472 | int |
9b66ebb1 | 6473 | arm_const_double_rtx (rtx x) |
cce8749e | 6474 | { |
ff9940b0 RE |
6475 | REAL_VALUE_TYPE r; |
6476 | int i; | |
f676971a | 6477 | |
9b66ebb1 PB |
6478 | if (!fp_consts_inited) |
6479 | init_fp_table (); | |
f676971a | 6480 | |
ff9940b0 RE |
6481 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
6482 | if (REAL_VALUE_MINUS_ZERO (r)) | |
6483 | return 0; | |
f3bb6135 | 6484 | |
9b66ebb1 PB |
6485 | for (i = 0; i < fp_consts_inited; i++) |
6486 | if (REAL_VALUES_EQUAL (r, values_fp[i])) | |
ff9940b0 | 6487 | return 1; |
f3bb6135 | 6488 | |
ff9940b0 | 6489 | return 0; |
f3bb6135 | 6490 | } |
ff9940b0 | 6491 | |
3b684012 | 6492 | /* Return TRUE if rtx X is a valid immediate FPA constant. */ |
ff9940b0 | 6493 | int |
e32bac5b | 6494 | neg_const_double_rtx_ok_for_fpa (rtx x) |
ff9940b0 RE |
6495 | { |
6496 | REAL_VALUE_TYPE r; | |
6497 | int i; | |
f676971a | 6498 | |
9b66ebb1 PB |
6499 | if (!fp_consts_inited) |
6500 | init_fp_table (); | |
f676971a | 6501 | |
ff9940b0 RE |
6502 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
6503 | r = REAL_VALUE_NEGATE (r); | |
6504 | if (REAL_VALUE_MINUS_ZERO (r)) | |
6505 | return 0; | |
f3bb6135 | 6506 | |
ff9940b0 | 6507 | for (i = 0; i < 8; i++) |
9b66ebb1 | 6508 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
ff9940b0 | 6509 | return 1; |
f3bb6135 | 6510 | |
ff9940b0 | 6511 | return 0; |
f3bb6135 | 6512 | } |
f1adb0a9 JB |
6513 | |
6514 | ||
6515 | /* VFPv3 has a fairly wide range of representable immediates, formed from | |
6516 | "quarter-precision" floating-point values. These can be evaluated using this | |
6517 | formula (with ^ for exponentiation): | |
6518 | ||
6519 | -1^s * n * 2^-r | |
6520 | ||
6521 | Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that | |
6522 | 16 <= n <= 31 and 0 <= r <= 7. | |
6523 | ||
6524 | These values are mapped onto an 8-bit integer ABCDEFGH s.t. | |
6525 | ||
6526 | - A (most-significant) is the sign bit. | |
6527 | - BCD are the exponent (encoded as r XOR 3). | |
6528 | - EFGH are the mantissa (encoded as n - 16). | |
6529 | */ | |
6530 | ||
6531 | /* Return an integer index for a VFPv3 immediate operand X suitable for the | |
6532 | fconst[sd] instruction, or -1 if X isn't suitable. */ | |
6533 | static int | |
6534 | vfp3_const_double_index (rtx x) | |
6535 | { | |
6536 | REAL_VALUE_TYPE r, m; | |
6537 | int sign, exponent; | |
6538 | unsigned HOST_WIDE_INT mantissa, mant_hi; | |
6539 | unsigned HOST_WIDE_INT mask; | |
8e39e9af | 6540 | HOST_WIDE_INT m1, m2; |
f1adb0a9 JB |
6541 | int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1; |
6542 | ||
6543 | if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE) | |
6544 | return -1; | |
6545 | ||
6546 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
6547 | ||
6548 | /* We can't represent these things, so detect them first. */ | |
6549 | if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r)) | |
6550 | return -1; | |
6551 | ||
6552 | /* Extract sign, exponent and mantissa. */ | |
6553 | sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0; | |
6554 | r = REAL_VALUE_ABS (r); | |
6555 | exponent = REAL_EXP (&r); | |
6556 | /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the | |
6557 | highest (sign) bit, with a fixed binary point at bit point_pos. | |
6558 | WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1 | |
6559 | bits for the mantissa, this may fail (low bits would be lost). */ | |
6560 | real_ldexp (&m, &r, point_pos - exponent); | |
8e39e9af RE |
6561 | REAL_VALUE_TO_INT (&m1, &m2, m); |
6562 | mantissa = m1; | |
6563 | mant_hi = m2; | |
f1adb0a9 JB |
6564 | |
6565 | /* If there are bits set in the low part of the mantissa, we can't | |
6566 | represent this value. */ | |
6567 | if (mantissa != 0) | |
6568 | return -1; | |
6569 | ||
6570 | /* Now make it so that mantissa contains the most-significant bits, and move | |
6571 | the point_pos to indicate that the least-significant bits have been | |
6572 | discarded. */ | |
6573 | point_pos -= HOST_BITS_PER_WIDE_INT; | |
6574 | mantissa = mant_hi; | |
6575 | ||
6576 | /* We can permit four significant bits of mantissa only, plus a high bit | |
6577 | which is always 1. */ | |
6578 | mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1; | |
6579 | if ((mantissa & mask) != 0) | |
6580 | return -1; | |
6581 | ||
6582 | /* Now we know the mantissa is in range, chop off the unneeded bits. */ | |
6583 | mantissa >>= point_pos - 5; | |
6584 | ||
6585 | /* The mantissa may be zero. Disallow that case. (It's possible to load the | |
6586 | floating-point immediate zero with Neon using an integer-zero load, but | |
6587 | that case is handled elsewhere.) */ | |
6588 | if (mantissa == 0) | |
6589 | return -1; | |
6590 | ||
6591 | gcc_assert (mantissa >= 16 && mantissa <= 31); | |
6592 | ||
6593 | /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where | |
6ed3da00 KH |
6594 | normalized significands are in the range [1, 2). (Our mantissa is shifted |
6595 | left 4 places at this point relative to normalized IEEE754 values). GCC | |
f1adb0a9 JB |
6596 | internally uses [0.5, 1) (see real.c), so the exponent returned from |
6597 | REAL_EXP must be altered. */ | |
6598 | exponent = 5 - exponent; | |
6599 | ||
6600 | if (exponent < 0 || exponent > 7) | |
6601 | return -1; | |
6602 | ||
6603 | /* Sign, mantissa and exponent are now in the correct form to plug into the | |
15dc95cb | 6604 | formula described in the comment above. */ |
f1adb0a9 JB |
6605 | return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16); |
6606 | } | |
6607 | ||
6608 | /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */ | |
6609 | int | |
6610 | vfp3_const_double_rtx (rtx x) | |
6611 | { | |
6612 | if (!TARGET_VFP3) | |
6613 | return 0; | |
6614 | ||
6615 | return vfp3_const_double_index (x) != -1; | |
6616 | } | |
6617 | ||
88f77cba JB |
6618 | /* Recognize immediates which can be used in various Neon instructions. Legal |
6619 | immediates are described by the following table (for VMVN variants, the | |
6620 | bitwise inverse of the constant shown is recognized. In either case, VMOV | |
6621 | is output and the correct instruction to use for a given constant is chosen | |
6622 | by the assembler). The constant shown is replicated across all elements of | |
6623 | the destination vector. | |
6624 | ||
6625 | insn elems variant constant (binary) | |
6626 | ---- ----- ------- ----------------- | |
6627 | vmov i32 0 00000000 00000000 00000000 abcdefgh | |
6628 | vmov i32 1 00000000 00000000 abcdefgh 00000000 | |
6629 | vmov i32 2 00000000 abcdefgh 00000000 00000000 | |
6630 | vmov i32 3 abcdefgh 00000000 00000000 00000000 | |
6631 | vmov i16 4 00000000 abcdefgh | |
6632 | vmov i16 5 abcdefgh 00000000 | |
6633 | vmvn i32 6 00000000 00000000 00000000 abcdefgh | |
6634 | vmvn i32 7 00000000 00000000 abcdefgh 00000000 | |
6635 | vmvn i32 8 00000000 abcdefgh 00000000 00000000 | |
6636 | vmvn i32 9 abcdefgh 00000000 00000000 00000000 | |
6637 | vmvn i16 10 00000000 abcdefgh | |
6638 | vmvn i16 11 abcdefgh 00000000 | |
6639 | vmov i32 12 00000000 00000000 abcdefgh 11111111 | |
6640 | vmvn i32 13 00000000 00000000 abcdefgh 11111111 | |
6641 | vmov i32 14 00000000 abcdefgh 11111111 11111111 | |
6642 | vmvn i32 15 00000000 abcdefgh 11111111 11111111 | |
6643 | vmov i8 16 abcdefgh | |
6644 | vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd | |
6645 | eeeeeeee ffffffff gggggggg hhhhhhhh | |
6646 | vmov f32 18 aBbbbbbc defgh000 00000000 00000000 | |
6647 | ||
6648 | For case 18, B = !b. Representable values are exactly those accepted by | |
6649 | vfp3_const_double_index, but are output as floating-point numbers rather | |
6650 | than indices. | |
6651 | ||
6652 | Variants 0-5 (inclusive) may also be used as immediates for the second | |
6653 | operand of VORR/VBIC instructions. | |
6654 | ||
6655 | The INVERSE argument causes the bitwise inverse of the given operand to be | |
6656 | recognized instead (used for recognizing legal immediates for the VAND/VORN | |
6657 | pseudo-instructions). If INVERSE is true, the value placed in *MODCONST is | |
6658 | *not* inverted (i.e. the pseudo-instruction forms vand/vorn should still be | |
6659 | output, rather than the real insns vbic/vorr). | |
6660 | ||
6661 | INVERSE makes no difference to the recognition of float vectors. | |
6662 | ||
6663 | The return value is the variant of immediate as shown in the above table, or | |
6664 | -1 if the given value doesn't match any of the listed patterns. | |
6665 | */ | |
6666 | static int | |
6667 | neon_valid_immediate (rtx op, enum machine_mode mode, int inverse, | |
6668 | rtx *modconst, int *elementwidth) | |
6669 | { | |
6670 | #define CHECK(STRIDE, ELSIZE, CLASS, TEST) \ | |
6671 | matches = 1; \ | |
6672 | for (i = 0; i < idx; i += (STRIDE)) \ | |
6673 | if (!(TEST)) \ | |
6674 | matches = 0; \ | |
6675 | if (matches) \ | |
6676 | { \ | |
6677 | immtype = (CLASS); \ | |
6678 | elsize = (ELSIZE); \ | |
6679 | break; \ | |
6680 | } | |
6681 | ||
ff128632 | 6682 | unsigned int i, elsize = 0, idx = 0, n_elts = CONST_VECTOR_NUNITS (op); |
88f77cba JB |
6683 | unsigned int innersize = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
6684 | unsigned char bytes[16]; | |
6685 | int immtype = -1, matches; | |
6686 | unsigned int invmask = inverse ? 0xff : 0; | |
6687 | ||
6688 | /* Vectors of float constants. */ | |
6689 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
6690 | { | |
6691 | rtx el0 = CONST_VECTOR_ELT (op, 0); | |
6692 | REAL_VALUE_TYPE r0; | |
6693 | ||
6694 | if (!vfp3_const_double_rtx (el0)) | |
6695 | return -1; | |
6696 | ||
6697 | REAL_VALUE_FROM_CONST_DOUBLE (r0, el0); | |
6698 | ||
6699 | for (i = 1; i < n_elts; i++) | |
6700 | { | |
6701 | rtx elt = CONST_VECTOR_ELT (op, i); | |
6702 | REAL_VALUE_TYPE re; | |
6703 | ||
6704 | REAL_VALUE_FROM_CONST_DOUBLE (re, elt); | |
6705 | ||
6706 | if (!REAL_VALUES_EQUAL (r0, re)) | |
6707 | return -1; | |
6708 | } | |
6709 | ||
6710 | if (modconst) | |
6711 | *modconst = CONST_VECTOR_ELT (op, 0); | |
6712 | ||
6713 | if (elementwidth) | |
6714 | *elementwidth = 0; | |
6715 | ||
6716 | return 18; | |
6717 | } | |
6718 | ||
6719 | /* Splat vector constant out into a byte vector. */ | |
6720 | for (i = 0; i < n_elts; i++) | |
6721 | { | |
6722 | rtx el = CONST_VECTOR_ELT (op, i); | |
6723 | unsigned HOST_WIDE_INT elpart; | |
6724 | unsigned int part, parts; | |
6725 | ||
6726 | if (GET_CODE (el) == CONST_INT) | |
6727 | { | |
6728 | elpart = INTVAL (el); | |
6729 | parts = 1; | |
6730 | } | |
6731 | else if (GET_CODE (el) == CONST_DOUBLE) | |
6732 | { | |
6733 | elpart = CONST_DOUBLE_LOW (el); | |
6734 | parts = 2; | |
6735 | } | |
6736 | else | |
6737 | gcc_unreachable (); | |
6738 | ||
6739 | for (part = 0; part < parts; part++) | |
6740 | { | |
6741 | unsigned int byte; | |
6742 | for (byte = 0; byte < innersize; byte++) | |
6743 | { | |
6744 | bytes[idx++] = (elpart & 0xff) ^ invmask; | |
6745 | elpart >>= BITS_PER_UNIT; | |
6746 | } | |
6747 | if (GET_CODE (el) == CONST_DOUBLE) | |
6748 | elpart = CONST_DOUBLE_HIGH (el); | |
6749 | } | |
6750 | } | |
6751 | ||
6752 | /* Sanity check. */ | |
6753 | gcc_assert (idx == GET_MODE_SIZE (mode)); | |
6754 | ||
6755 | do | |
6756 | { | |
6757 | CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0 | |
6758 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6759 | ||
6760 | CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6761 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6762 | ||
6763 | CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0 | |
6764 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6765 | ||
6766 | CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0 | |
6767 | && bytes[i + 2] == 0 && bytes[i + 3] == bytes[3]); | |
6768 | ||
6769 | CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0); | |
6770 | ||
6771 | CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1]); | |
6772 | ||
6773 | CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff | |
6774 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6775 | ||
6776 | CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6777 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6778 | ||
6779 | CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6780 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6781 | ||
6782 | CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6783 | && bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3]); | |
6784 | ||
6785 | CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff); | |
6786 | ||
6787 | CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1]); | |
6788 | ||
6789 | CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1] | |
6790 | && bytes[i + 2] == 0 && bytes[i + 3] == 0); | |
6791 | ||
6792 | CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1] | |
6793 | && bytes[i + 2] == 0xff && bytes[i + 3] == 0xff); | |
6794 | ||
6795 | CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff | |
6796 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0); | |
6797 | ||
6798 | CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0 | |
6799 | && bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff); | |
6800 | ||
6801 | CHECK (1, 8, 16, bytes[i] == bytes[0]); | |
6802 | ||
6803 | CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff) | |
6804 | && bytes[i] == bytes[(i + 8) % idx]); | |
6805 | } | |
6806 | while (0); | |
6807 | ||
6808 | if (immtype == -1) | |
6809 | return -1; | |
6810 | ||
6811 | if (elementwidth) | |
6812 | *elementwidth = elsize; | |
6813 | ||
6814 | if (modconst) | |
6815 | { | |
6816 | unsigned HOST_WIDE_INT imm = 0; | |
6817 | ||
cea618ac | 6818 | /* Un-invert bytes of recognized vector, if necessary. */ |
88f77cba JB |
6819 | if (invmask != 0) |
6820 | for (i = 0; i < idx; i++) | |
6821 | bytes[i] ^= invmask; | |
6822 | ||
6823 | if (immtype == 17) | |
6824 | { | |
6825 | /* FIXME: Broken on 32-bit H_W_I hosts. */ | |
6826 | gcc_assert (sizeof (HOST_WIDE_INT) == 8); | |
6827 | ||
6828 | for (i = 0; i < 8; i++) | |
6829 | imm |= (unsigned HOST_WIDE_INT) (bytes[i] ? 0xff : 0) | |
6830 | << (i * BITS_PER_UNIT); | |
6831 | ||
6832 | *modconst = GEN_INT (imm); | |
6833 | } | |
6834 | else | |
6835 | { | |
6836 | unsigned HOST_WIDE_INT imm = 0; | |
6837 | ||
6838 | for (i = 0; i < elsize / BITS_PER_UNIT; i++) | |
6839 | imm |= (unsigned HOST_WIDE_INT) bytes[i] << (i * BITS_PER_UNIT); | |
6840 | ||
6841 | *modconst = GEN_INT (imm); | |
6842 | } | |
6843 | } | |
6844 | ||
6845 | return immtype; | |
6846 | #undef CHECK | |
6847 | } | |
6848 | ||
6849 | /* Return TRUE if rtx X is legal for use as either a Neon VMOV (or, implicitly, | |
6850 | VMVN) immediate. Write back width per element to *ELEMENTWIDTH (or zero for | |
6851 | float elements), and a modified constant (whatever should be output for a | |
6852 | VMOV) in *MODCONST. */ | |
6853 | ||
6854 | int | |
6855 | neon_immediate_valid_for_move (rtx op, enum machine_mode mode, | |
6856 | rtx *modconst, int *elementwidth) | |
6857 | { | |
6858 | rtx tmpconst; | |
6859 | int tmpwidth; | |
6860 | int retval = neon_valid_immediate (op, mode, 0, &tmpconst, &tmpwidth); | |
6861 | ||
6862 | if (retval == -1) | |
6863 | return 0; | |
6864 | ||
6865 | if (modconst) | |
6866 | *modconst = tmpconst; | |
6867 | ||
6868 | if (elementwidth) | |
6869 | *elementwidth = tmpwidth; | |
6870 | ||
6871 | return 1; | |
6872 | } | |
6873 | ||
6874 | /* Return TRUE if rtx X is legal for use in a VORR or VBIC instruction. If | |
6875 | the immediate is valid, write a constant suitable for using as an operand | |
6876 | to VORR/VBIC/VAND/VORN to *MODCONST and the corresponding element width to | |
6877 | *ELEMENTWIDTH. See neon_valid_immediate for description of INVERSE. */ | |
6878 | ||
6879 | int | |
6880 | neon_immediate_valid_for_logic (rtx op, enum machine_mode mode, int inverse, | |
6881 | rtx *modconst, int *elementwidth) | |
6882 | { | |
6883 | rtx tmpconst; | |
6884 | int tmpwidth; | |
6885 | int retval = neon_valid_immediate (op, mode, inverse, &tmpconst, &tmpwidth); | |
6886 | ||
6887 | if (retval < 0 || retval > 5) | |
6888 | return 0; | |
6889 | ||
6890 | if (modconst) | |
6891 | *modconst = tmpconst; | |
6892 | ||
6893 | if (elementwidth) | |
6894 | *elementwidth = tmpwidth; | |
6895 | ||
6896 | return 1; | |
6897 | } | |
6898 | ||
6899 | /* Return a string suitable for output of Neon immediate logic operation | |
6900 | MNEM. */ | |
6901 | ||
6902 | char * | |
6903 | neon_output_logic_immediate (const char *mnem, rtx *op2, enum machine_mode mode, | |
6904 | int inverse, int quad) | |
6905 | { | |
6906 | int width, is_valid; | |
6907 | static char templ[40]; | |
6908 | ||
6909 | is_valid = neon_immediate_valid_for_logic (*op2, mode, inverse, op2, &width); | |
6910 | ||
6911 | gcc_assert (is_valid != 0); | |
6912 | ||
6913 | if (quad) | |
6914 | sprintf (templ, "%s.i%d\t%%q0, %%2", mnem, width); | |
6915 | else | |
6916 | sprintf (templ, "%s.i%d\t%%P0, %%2", mnem, width); | |
6917 | ||
6918 | return templ; | |
6919 | } | |
6920 | ||
6921 | /* Output a sequence of pairwise operations to implement a reduction. | |
6922 | NOTE: We do "too much work" here, because pairwise operations work on two | |
6923 | registers-worth of operands in one go. Unfortunately we can't exploit those | |
6924 | extra calculations to do the full operation in fewer steps, I don't think. | |
6925 | Although all vector elements of the result but the first are ignored, we | |
6926 | actually calculate the same result in each of the elements. An alternative | |
6927 | such as initially loading a vector with zero to use as each of the second | |
6928 | operands would use up an additional register and take an extra instruction, | |
6929 | for no particular gain. */ | |
6930 | ||
6931 | void | |
6932 | neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode, | |
6933 | rtx (*reduc) (rtx, rtx, rtx)) | |
6934 | { | |
6935 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6936 | unsigned int i, parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (inner); | |
6937 | rtx tmpsum = op1; | |
6938 | ||
6939 | for (i = parts / 2; i >= 1; i /= 2) | |
6940 | { | |
6941 | rtx dest = (i == 1) ? op0 : gen_reg_rtx (mode); | |
6942 | emit_insn (reduc (dest, tmpsum, tmpsum)); | |
6943 | tmpsum = dest; | |
6944 | } | |
6945 | } | |
6946 | ||
cea618ac | 6947 | /* Initialize a vector with non-constant elements. FIXME: We can do better |
88f77cba JB |
6948 | than the current implementation (building a vector on the stack and then |
6949 | loading it) in many cases. See rs6000.c. */ | |
6950 | ||
6951 | void | |
6952 | neon_expand_vector_init (rtx target, rtx vals) | |
6953 | { | |
6954 | enum machine_mode mode = GET_MODE (target); | |
6955 | enum machine_mode inner = GET_MODE_INNER (mode); | |
6956 | unsigned int i, n_elts = GET_MODE_NUNITS (mode); | |
6957 | rtx mem; | |
6958 | ||
6959 | gcc_assert (VECTOR_MODE_P (mode)); | |
6960 | ||
6961 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
6962 | for (i = 0; i < n_elts; i++) | |
6963 | emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), | |
6964 | XVECEXP (vals, 0, i)); | |
6965 | ||
6966 | emit_move_insn (target, mem); | |
6967 | } | |
6968 | ||
b617fc71 JB |
6969 | /* Ensure OPERAND lies between LOW (inclusive) and HIGH (exclusive). Raise |
6970 | ERR if it doesn't. FIXME: NEON bounds checks occur late in compilation, so | |
6971 | reported source locations are bogus. */ | |
6972 | ||
6973 | static void | |
6974 | bounds_check (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high, | |
6975 | const char *err) | |
6976 | { | |
6977 | HOST_WIDE_INT lane; | |
6978 | ||
6979 | gcc_assert (GET_CODE (operand) == CONST_INT); | |
6980 | ||
6981 | lane = INTVAL (operand); | |
6982 | ||
6983 | if (lane < low || lane >= high) | |
6984 | error (err); | |
6985 | } | |
6986 | ||
6987 | /* Bounds-check lanes. */ | |
6988 | ||
6989 | void | |
6990 | neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6991 | { | |
6992 | bounds_check (operand, low, high, "lane out of range"); | |
6993 | } | |
6994 | ||
6995 | /* Bounds-check constants. */ | |
6996 | ||
6997 | void | |
6998 | neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) | |
6999 | { | |
7000 | bounds_check (operand, low, high, "constant out of range"); | |
7001 | } | |
7002 | ||
7003 | HOST_WIDE_INT | |
7004 | neon_element_bits (enum machine_mode mode) | |
7005 | { | |
7006 | if (mode == DImode) | |
7007 | return GET_MODE_BITSIZE (mode); | |
7008 | else | |
7009 | return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); | |
7010 | } | |
7011 | ||
cce8749e CH |
7012 | \f |
7013 | /* Predicates for `match_operand' and `match_operator'. */ | |
7014 | ||
9b6b54e2 | 7015 | /* Return nonzero if OP is a valid Cirrus memory address pattern. */ |
9b6b54e2 | 7016 | int |
e32bac5b | 7017 | cirrus_memory_offset (rtx op) |
9b6b54e2 NC |
7018 | { |
7019 | /* Reject eliminable registers. */ | |
7020 | if (! (reload_in_progress || reload_completed) | |
7021 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
7022 | || reg_mentioned_p (arg_pointer_rtx, op) | |
7023 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
7024 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
7025 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
7026 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
7027 | return 0; | |
7028 | ||
7029 | if (GET_CODE (op) == MEM) | |
7030 | { | |
7031 | rtx ind; | |
7032 | ||
7033 | ind = XEXP (op, 0); | |
7034 | ||
7035 | /* Match: (mem (reg)). */ | |
7036 | if (GET_CODE (ind) == REG) | |
7037 | return 1; | |
7038 | ||
7039 | /* Match: | |
7040 | (mem (plus (reg) | |
7041 | (const))). */ | |
7042 | if (GET_CODE (ind) == PLUS | |
7043 | && GET_CODE (XEXP (ind, 0)) == REG | |
7044 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
7045 | && GET_CODE (XEXP (ind, 1)) == CONST_INT) | |
7046 | return 1; | |
7047 | } | |
7048 | ||
7049 | return 0; | |
7050 | } | |
7051 | ||
f26b8ec9 | 7052 | /* Return TRUE if OP is a valid coprocessor memory address pattern. |
5b3e6663 PB |
7053 | WB is true if full writeback address modes are allowed and is false |
7054 | if limited writeback address modes (POST_INC and PRE_DEC) are | |
7055 | allowed. */ | |
9b66ebb1 PB |
7056 | |
7057 | int | |
fdd695fd | 7058 | arm_coproc_mem_operand (rtx op, bool wb) |
9b66ebb1 | 7059 | { |
fdd695fd | 7060 | rtx ind; |
9b66ebb1 | 7061 | |
fdd695fd | 7062 | /* Reject eliminable registers. */ |
9b66ebb1 PB |
7063 | if (! (reload_in_progress || reload_completed) |
7064 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
7065 | || reg_mentioned_p (arg_pointer_rtx, op) | |
7066 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
7067 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
7068 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
7069 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
7070 | return FALSE; | |
7071 | ||
59b9a953 | 7072 | /* Constants are converted into offsets from labels. */ |
fdd695fd PB |
7073 | if (GET_CODE (op) != MEM) |
7074 | return FALSE; | |
9b66ebb1 | 7075 | |
fdd695fd | 7076 | ind = XEXP (op, 0); |
9b66ebb1 | 7077 | |
fdd695fd PB |
7078 | if (reload_completed |
7079 | && (GET_CODE (ind) == LABEL_REF | |
7080 | || (GET_CODE (ind) == CONST | |
7081 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
7082 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
7083 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
7084 | return TRUE; | |
9b66ebb1 | 7085 | |
fdd695fd PB |
7086 | /* Match: (mem (reg)). */ |
7087 | if (GET_CODE (ind) == REG) | |
7088 | return arm_address_register_rtx_p (ind, 0); | |
7089 | ||
5b3e6663 PB |
7090 | /* Autoincremment addressing modes. POST_INC and PRE_DEC are |
7091 | acceptable in any case (subject to verification by | |
7092 | arm_address_register_rtx_p). We need WB to be true to accept | |
7093 | PRE_INC and POST_DEC. */ | |
7094 | if (GET_CODE (ind) == POST_INC | |
7095 | || GET_CODE (ind) == PRE_DEC | |
7096 | || (wb | |
7097 | && (GET_CODE (ind) == PRE_INC | |
7098 | || GET_CODE (ind) == POST_DEC))) | |
fdd695fd PB |
7099 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
7100 | ||
7101 | if (wb | |
7102 | && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) | |
7103 | && arm_address_register_rtx_p (XEXP (ind, 0), 0) | |
7104 | && GET_CODE (XEXP (ind, 1)) == PLUS | |
7105 | && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) | |
7106 | ind = XEXP (ind, 1); | |
7107 | ||
7108 | /* Match: | |
7109 | (plus (reg) | |
7110 | (const)). */ | |
7111 | if (GET_CODE (ind) == PLUS | |
7112 | && GET_CODE (XEXP (ind, 0)) == REG | |
7113 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
7114 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
7115 | && INTVAL (XEXP (ind, 1)) > -1024 | |
7116 | && INTVAL (XEXP (ind, 1)) < 1024 | |
7117 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
7118 | return TRUE; | |
9b66ebb1 PB |
7119 | |
7120 | return FALSE; | |
7121 | } | |
7122 | ||
88f77cba | 7123 | /* Return TRUE if OP is a memory operand which we can load or store a vector |
dc34db56 PB |
7124 | to/from. TYPE is one of the following values: |
7125 | 0 - Vector load/stor (vldr) | |
7126 | 1 - Core registers (ldm) | |
7127 | 2 - Element/structure loads (vld1) | |
7128 | */ | |
88f77cba | 7129 | int |
dc34db56 | 7130 | neon_vector_mem_operand (rtx op, int type) |
88f77cba JB |
7131 | { |
7132 | rtx ind; | |
7133 | ||
7134 | /* Reject eliminable registers. */ | |
7135 | if (! (reload_in_progress || reload_completed) | |
7136 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
7137 | || reg_mentioned_p (arg_pointer_rtx, op) | |
7138 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
7139 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
7140 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
7141 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
7142 | return FALSE; | |
7143 | ||
7144 | /* Constants are converted into offsets from labels. */ | |
7145 | if (GET_CODE (op) != MEM) | |
7146 | return FALSE; | |
7147 | ||
7148 | ind = XEXP (op, 0); | |
7149 | ||
7150 | if (reload_completed | |
7151 | && (GET_CODE (ind) == LABEL_REF | |
7152 | || (GET_CODE (ind) == CONST | |
7153 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
7154 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
7155 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
7156 | return TRUE; | |
7157 | ||
7158 | /* Match: (mem (reg)). */ | |
7159 | if (GET_CODE (ind) == REG) | |
7160 | return arm_address_register_rtx_p (ind, 0); | |
7161 | ||
7162 | /* Allow post-increment with Neon registers. */ | |
dc34db56 | 7163 | if (type != 1 && (GET_CODE (ind) == POST_INC || GET_CODE (ind) == PRE_DEC)) |
88f77cba JB |
7164 | return arm_address_register_rtx_p (XEXP (ind, 0), 0); |
7165 | ||
dc34db56 | 7166 | /* FIXME: vld1 allows register post-modify. */ |
88f77cba JB |
7167 | |
7168 | /* Match: | |
7169 | (plus (reg) | |
7170 | (const)). */ | |
dc34db56 | 7171 | if (type == 0 |
88f77cba JB |
7172 | && GET_CODE (ind) == PLUS |
7173 | && GET_CODE (XEXP (ind, 0)) == REG | |
7174 | && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) | |
7175 | && GET_CODE (XEXP (ind, 1)) == CONST_INT | |
7176 | && INTVAL (XEXP (ind, 1)) > -1024 | |
7177 | && INTVAL (XEXP (ind, 1)) < 1016 | |
7178 | && (INTVAL (XEXP (ind, 1)) & 3) == 0) | |
7179 | return TRUE; | |
7180 | ||
7181 | return FALSE; | |
7182 | } | |
7183 | ||
7184 | /* Return TRUE if OP is a mem suitable for loading/storing a Neon struct | |
7185 | type. */ | |
7186 | int | |
7187 | neon_struct_mem_operand (rtx op) | |
7188 | { | |
7189 | rtx ind; | |
7190 | ||
7191 | /* Reject eliminable registers. */ | |
7192 | if (! (reload_in_progress || reload_completed) | |
7193 | && ( reg_mentioned_p (frame_pointer_rtx, op) | |
7194 | || reg_mentioned_p (arg_pointer_rtx, op) | |
7195 | || reg_mentioned_p (virtual_incoming_args_rtx, op) | |
7196 | || reg_mentioned_p (virtual_outgoing_args_rtx, op) | |
7197 | || reg_mentioned_p (virtual_stack_dynamic_rtx, op) | |
7198 | || reg_mentioned_p (virtual_stack_vars_rtx, op))) | |
7199 | return FALSE; | |
7200 | ||
7201 | /* Constants are converted into offsets from labels. */ | |
7202 | if (GET_CODE (op) != MEM) | |
7203 | return FALSE; | |
7204 | ||
7205 | ind = XEXP (op, 0); | |
7206 | ||
7207 | if (reload_completed | |
7208 | && (GET_CODE (ind) == LABEL_REF | |
7209 | || (GET_CODE (ind) == CONST | |
7210 | && GET_CODE (XEXP (ind, 0)) == PLUS | |
7211 | && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF | |
7212 | && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) | |
7213 | return TRUE; | |
7214 | ||
7215 | /* Match: (mem (reg)). */ | |
7216 | if (GET_CODE (ind) == REG) | |
7217 | return arm_address_register_rtx_p (ind, 0); | |
7218 | ||
7219 | return FALSE; | |
7220 | } | |
7221 | ||
6555b6bd RE |
7222 | /* Return true if X is a register that will be eliminated later on. */ |
7223 | int | |
7224 | arm_eliminable_register (rtx x) | |
7225 | { | |
7226 | return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM | |
7227 | || REGNO (x) == ARG_POINTER_REGNUM | |
7228 | || (REGNO (x) >= FIRST_VIRTUAL_REGISTER | |
7229 | && REGNO (x) <= LAST_VIRTUAL_REGISTER)); | |
7230 | } | |
9b66ebb1 | 7231 | |
9b66ebb1 | 7232 | /* Return GENERAL_REGS if a scratch register required to reload x to/from |
fe2d934b | 7233 | coprocessor registers. Otherwise return NO_REGS. */ |
9b66ebb1 PB |
7234 | |
7235 | enum reg_class | |
fe2d934b | 7236 | coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) |
9b66ebb1 | 7237 | { |
0fd8c3ad SL |
7238 | if (mode == HFmode) |
7239 | { | |
7240 | if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2)) | |
7241 | return NO_REGS; | |
7242 | return GENERAL_REGS; | |
7243 | } | |
7244 | ||
88f77cba JB |
7245 | if (TARGET_NEON |
7246 | && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT | |
7247 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
dc34db56 | 7248 | && neon_vector_mem_operand (x, 0)) |
88f77cba JB |
7249 | return NO_REGS; |
7250 | ||
fe2d934b | 7251 | if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) |
9b66ebb1 PB |
7252 | return NO_REGS; |
7253 | ||
7254 | return GENERAL_REGS; | |
7255 | } | |
7256 | ||
866af8a9 JB |
7257 | /* Values which must be returned in the most-significant end of the return |
7258 | register. */ | |
7259 | ||
7260 | static bool | |
586de218 | 7261 | arm_return_in_msb (const_tree valtype) |
866af8a9 JB |
7262 | { |
7263 | return (TARGET_AAPCS_BASED | |
7264 | && BYTES_BIG_ENDIAN | |
7265 | && (AGGREGATE_TYPE_P (valtype) | |
7266 | || TREE_CODE (valtype) == COMPLEX_TYPE)); | |
7267 | } | |
9b66ebb1 | 7268 | |
f0375c66 NC |
7269 | /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. |
7270 | Use by the Cirrus Maverick code which has to workaround | |
7271 | a hardware bug triggered by such instructions. */ | |
f0375c66 | 7272 | static bool |
e32bac5b | 7273 | arm_memory_load_p (rtx insn) |
9b6b54e2 NC |
7274 | { |
7275 | rtx body, lhs, rhs;; | |
7276 | ||
f0375c66 NC |
7277 | if (insn == NULL_RTX || GET_CODE (insn) != INSN) |
7278 | return false; | |
9b6b54e2 NC |
7279 | |
7280 | body = PATTERN (insn); | |
7281 | ||
7282 | if (GET_CODE (body) != SET) | |
f0375c66 | 7283 | return false; |
9b6b54e2 NC |
7284 | |
7285 | lhs = XEXP (body, 0); | |
7286 | rhs = XEXP (body, 1); | |
7287 | ||
f0375c66 NC |
7288 | lhs = REG_OR_SUBREG_RTX (lhs); |
7289 | ||
7290 | /* If the destination is not a general purpose | |
7291 | register we do not have to worry. */ | |
7292 | if (GET_CODE (lhs) != REG | |
7293 | || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) | |
7294 | return false; | |
7295 | ||
7296 | /* As well as loads from memory we also have to react | |
7297 | to loads of invalid constants which will be turned | |
7298 | into loads from the minipool. */ | |
7299 | return (GET_CODE (rhs) == MEM | |
7300 | || GET_CODE (rhs) == SYMBOL_REF | |
7301 | || note_invalid_constants (insn, -1, false)); | |
9b6b54e2 NC |
7302 | } |
7303 | ||
f0375c66 | 7304 | /* Return TRUE if INSN is a Cirrus instruction. */ |
f0375c66 | 7305 | static bool |
e32bac5b | 7306 | arm_cirrus_insn_p (rtx insn) |
9b6b54e2 NC |
7307 | { |
7308 | enum attr_cirrus attr; | |
7309 | ||
e6d29d15 | 7310 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
7311 | if (!insn |
7312 | || GET_CODE (insn) != INSN | |
7313 | || GET_CODE (PATTERN (insn)) == USE | |
7314 | || GET_CODE (PATTERN (insn)) == CLOBBER) | |
7315 | return 0; | |
7316 | ||
7317 | attr = get_attr_cirrus (insn); | |
7318 | ||
f0375c66 | 7319 | return attr != CIRRUS_NOT; |
9b6b54e2 NC |
7320 | } |
7321 | ||
7322 | /* Cirrus reorg for invalid instruction combinations. */ | |
9b6b54e2 | 7323 | static void |
e32bac5b | 7324 | cirrus_reorg (rtx first) |
9b6b54e2 NC |
7325 | { |
7326 | enum attr_cirrus attr; | |
7327 | rtx body = PATTERN (first); | |
7328 | rtx t; | |
7329 | int nops; | |
7330 | ||
7331 | /* Any branch must be followed by 2 non Cirrus instructions. */ | |
7332 | if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) | |
7333 | { | |
7334 | nops = 0; | |
7335 | t = next_nonnote_insn (first); | |
7336 | ||
f0375c66 | 7337 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
7338 | ++ nops; |
7339 | ||
f0375c66 | 7340 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
7341 | ++ nops; |
7342 | ||
7343 | while (nops --) | |
7344 | emit_insn_after (gen_nop (), first); | |
7345 | ||
7346 | return; | |
7347 | } | |
7348 | ||
7349 | /* (float (blah)) is in parallel with a clobber. */ | |
7350 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
7351 | body = XVECEXP (body, 0, 0); | |
7352 | ||
7353 | if (GET_CODE (body) == SET) | |
7354 | { | |
7355 | rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); | |
7356 | ||
7357 | /* cfldrd, cfldr64, cfstrd, cfstr64 must | |
7358 | be followed by a non Cirrus insn. */ | |
7359 | if (get_attr_cirrus (first) == CIRRUS_DOUBLE) | |
7360 | { | |
f0375c66 | 7361 | if (arm_cirrus_insn_p (next_nonnote_insn (first))) |
9b6b54e2 NC |
7362 | emit_insn_after (gen_nop (), first); |
7363 | ||
7364 | return; | |
7365 | } | |
f0375c66 | 7366 | else if (arm_memory_load_p (first)) |
9b6b54e2 NC |
7367 | { |
7368 | unsigned int arm_regno; | |
7369 | ||
7370 | /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, | |
7371 | ldr/cfmv64hr combination where the Rd field is the same | |
7372 | in both instructions must be split with a non Cirrus | |
7373 | insn. Example: | |
7374 | ||
7375 | ldr r0, blah | |
7376 | nop | |
7377 | cfmvsr mvf0, r0. */ | |
7378 | ||
7379 | /* Get Arm register number for ldr insn. */ | |
7380 | if (GET_CODE (lhs) == REG) | |
7381 | arm_regno = REGNO (lhs); | |
9b6b54e2 | 7382 | else |
e6d29d15 NS |
7383 | { |
7384 | gcc_assert (GET_CODE (rhs) == REG); | |
7385 | arm_regno = REGNO (rhs); | |
7386 | } | |
9b6b54e2 NC |
7387 | |
7388 | /* Next insn. */ | |
7389 | first = next_nonnote_insn (first); | |
7390 | ||
f0375c66 | 7391 | if (! arm_cirrus_insn_p (first)) |
9b6b54e2 NC |
7392 | return; |
7393 | ||
7394 | body = PATTERN (first); | |
7395 | ||
7396 | /* (float (blah)) is in parallel with a clobber. */ | |
7397 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) | |
7398 | body = XVECEXP (body, 0, 0); | |
7399 | ||
7400 | if (GET_CODE (body) == FLOAT) | |
7401 | body = XEXP (body, 0); | |
7402 | ||
7403 | if (get_attr_cirrus (first) == CIRRUS_MOVE | |
7404 | && GET_CODE (XEXP (body, 1)) == REG | |
7405 | && arm_regno == REGNO (XEXP (body, 1))) | |
7406 | emit_insn_after (gen_nop (), first); | |
7407 | ||
7408 | return; | |
7409 | } | |
7410 | } | |
7411 | ||
e6d29d15 | 7412 | /* get_attr cannot accept USE or CLOBBER. */ |
9b6b54e2 NC |
7413 | if (!first |
7414 | || GET_CODE (first) != INSN | |
7415 | || GET_CODE (PATTERN (first)) == USE | |
7416 | || GET_CODE (PATTERN (first)) == CLOBBER) | |
7417 | return; | |
7418 | ||
7419 | attr = get_attr_cirrus (first); | |
7420 | ||
7421 | /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) | |
7422 | must be followed by a non-coprocessor instruction. */ | |
7423 | if (attr == CIRRUS_COMPARE) | |
7424 | { | |
7425 | nops = 0; | |
7426 | ||
7427 | t = next_nonnote_insn (first); | |
7428 | ||
f0375c66 | 7429 | if (arm_cirrus_insn_p (t)) |
9b6b54e2 NC |
7430 | ++ nops; |
7431 | ||
f0375c66 | 7432 | if (arm_cirrus_insn_p (next_nonnote_insn (t))) |
9b6b54e2 NC |
7433 | ++ nops; |
7434 | ||
7435 | while (nops --) | |
7436 | emit_insn_after (gen_nop (), first); | |
7437 | ||
7438 | return; | |
7439 | } | |
7440 | } | |
7441 | ||
2b835d68 RE |
7442 | /* Return TRUE if X references a SYMBOL_REF. */ |
7443 | int | |
e32bac5b | 7444 | symbol_mentioned_p (rtx x) |
2b835d68 | 7445 | { |
1d6e90ac NC |
7446 | const char * fmt; |
7447 | int i; | |
2b835d68 RE |
7448 | |
7449 | if (GET_CODE (x) == SYMBOL_REF) | |
7450 | return 1; | |
7451 | ||
d3585b76 DJ |
7452 | /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they |
7453 | are constant offsets, not symbols. */ | |
7454 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
7455 | return 0; | |
7456 | ||
2b835d68 | 7457 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
f676971a | 7458 | |
2b835d68 RE |
7459 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) |
7460 | { | |
7461 | if (fmt[i] == 'E') | |
7462 | { | |
1d6e90ac | 7463 | int j; |
2b835d68 RE |
7464 | |
7465 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7466 | if (symbol_mentioned_p (XVECEXP (x, i, j))) | |
7467 | return 1; | |
7468 | } | |
7469 | else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) | |
7470 | return 1; | |
7471 | } | |
7472 | ||
7473 | return 0; | |
7474 | } | |
7475 | ||
7476 | /* Return TRUE if X references a LABEL_REF. */ | |
7477 | int | |
e32bac5b | 7478 | label_mentioned_p (rtx x) |
2b835d68 | 7479 | { |
1d6e90ac NC |
7480 | const char * fmt; |
7481 | int i; | |
2b835d68 RE |
7482 | |
7483 | if (GET_CODE (x) == LABEL_REF) | |
7484 | return 1; | |
7485 | ||
d3585b76 DJ |
7486 | /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing |
7487 | instruction, but they are constant offsets, not symbols. */ | |
7488 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
7489 | return 0; | |
7490 | ||
2b835d68 RE |
7491 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
7492 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
7493 | { | |
7494 | if (fmt[i] == 'E') | |
7495 | { | |
1d6e90ac | 7496 | int j; |
2b835d68 RE |
7497 | |
7498 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7499 | if (label_mentioned_p (XVECEXP (x, i, j))) | |
7500 | return 1; | |
7501 | } | |
7502 | else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) | |
7503 | return 1; | |
7504 | } | |
7505 | ||
7506 | return 0; | |
7507 | } | |
7508 | ||
d3585b76 DJ |
7509 | int |
7510 | tls_mentioned_p (rtx x) | |
7511 | { | |
7512 | switch (GET_CODE (x)) | |
7513 | { | |
7514 | case CONST: | |
7515 | return tls_mentioned_p (XEXP (x, 0)); | |
7516 | ||
7517 | case UNSPEC: | |
7518 | if (XINT (x, 1) == UNSPEC_TLS) | |
7519 | return 1; | |
7520 | ||
7521 | default: | |
7522 | return 0; | |
7523 | } | |
7524 | } | |
7525 | ||
7526 | /* Must not copy a SET whose source operand is PC-relative. */ | |
7527 | ||
7528 | static bool | |
7529 | arm_cannot_copy_insn_p (rtx insn) | |
7530 | { | |
7531 | rtx pat = PATTERN (insn); | |
7532 | ||
10ae7c7b | 7533 | if (GET_CODE (pat) == SET) |
d3585b76 | 7534 | { |
10ae7c7b | 7535 | rtx rhs = SET_SRC (pat); |
d3585b76 DJ |
7536 | |
7537 | if (GET_CODE (rhs) == UNSPEC | |
7538 | && XINT (rhs, 1) == UNSPEC_PIC_BASE) | |
7539 | return TRUE; | |
7540 | ||
7541 | if (GET_CODE (rhs) == MEM | |
7542 | && GET_CODE (XEXP (rhs, 0)) == UNSPEC | |
7543 | && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) | |
7544 | return TRUE; | |
7545 | } | |
7546 | ||
7547 | return FALSE; | |
7548 | } | |
7549 | ||
ff9940b0 | 7550 | enum rtx_code |
e32bac5b | 7551 | minmax_code (rtx x) |
ff9940b0 RE |
7552 | { |
7553 | enum rtx_code code = GET_CODE (x); | |
7554 | ||
e6d29d15 NS |
7555 | switch (code) |
7556 | { | |
7557 | case SMAX: | |
7558 | return GE; | |
7559 | case SMIN: | |
7560 | return LE; | |
7561 | case UMIN: | |
7562 | return LEU; | |
7563 | case UMAX: | |
7564 | return GEU; | |
7565 | default: | |
7566 | gcc_unreachable (); | |
7567 | } | |
ff9940b0 RE |
7568 | } |
7569 | ||
6354dc9b | 7570 | /* Return 1 if memory locations are adjacent. */ |
f3bb6135 | 7571 | int |
e32bac5b | 7572 | adjacent_mem_locations (rtx a, rtx b) |
ff9940b0 | 7573 | { |
15b5c4c1 RE |
7574 | /* We don't guarantee to preserve the order of these memory refs. */ |
7575 | if (volatile_refs_p (a) || volatile_refs_p (b)) | |
7576 | return 0; | |
7577 | ||
ff9940b0 RE |
7578 | if ((GET_CODE (XEXP (a, 0)) == REG |
7579 | || (GET_CODE (XEXP (a, 0)) == PLUS | |
7580 | && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) | |
7581 | && (GET_CODE (XEXP (b, 0)) == REG | |
7582 | || (GET_CODE (XEXP (b, 0)) == PLUS | |
7583 | && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) | |
7584 | { | |
6555b6bd RE |
7585 | HOST_WIDE_INT val0 = 0, val1 = 0; |
7586 | rtx reg0, reg1; | |
7587 | int val_diff; | |
f676971a | 7588 | |
ff9940b0 RE |
7589 | if (GET_CODE (XEXP (a, 0)) == PLUS) |
7590 | { | |
6555b6bd | 7591 | reg0 = XEXP (XEXP (a, 0), 0); |
ff9940b0 RE |
7592 | val0 = INTVAL (XEXP (XEXP (a, 0), 1)); |
7593 | } | |
7594 | else | |
6555b6bd | 7595 | reg0 = XEXP (a, 0); |
1d6e90ac | 7596 | |
ff9940b0 RE |
7597 | if (GET_CODE (XEXP (b, 0)) == PLUS) |
7598 | { | |
6555b6bd | 7599 | reg1 = XEXP (XEXP (b, 0), 0); |
ff9940b0 RE |
7600 | val1 = INTVAL (XEXP (XEXP (b, 0), 1)); |
7601 | } | |
7602 | else | |
6555b6bd | 7603 | reg1 = XEXP (b, 0); |
1d6e90ac | 7604 | |
e32bac5b RE |
7605 | /* Don't accept any offset that will require multiple |
7606 | instructions to handle, since this would cause the | |
7607 | arith_adjacentmem pattern to output an overlong sequence. */ | |
bbbbb16a | 7608 | if (!const_ok_for_op (val0, PLUS) || !const_ok_for_op (val1, PLUS)) |
c75a3ddc | 7609 | return 0; |
f676971a | 7610 | |
6555b6bd RE |
7611 | /* Don't allow an eliminable register: register elimination can make |
7612 | the offset too large. */ | |
7613 | if (arm_eliminable_register (reg0)) | |
7614 | return 0; | |
7615 | ||
7616 | val_diff = val1 - val0; | |
15b5c4c1 RE |
7617 | |
7618 | if (arm_ld_sched) | |
7619 | { | |
7620 | /* If the target has load delay slots, then there's no benefit | |
7621 | to using an ldm instruction unless the offset is zero and | |
7622 | we are optimizing for size. */ | |
7623 | return (optimize_size && (REGNO (reg0) == REGNO (reg1)) | |
7624 | && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) | |
7625 | && (val_diff == 4 || val_diff == -4)); | |
7626 | } | |
7627 | ||
6555b6bd RE |
7628 | return ((REGNO (reg0) == REGNO (reg1)) |
7629 | && (val_diff == 4 || val_diff == -4)); | |
ff9940b0 | 7630 | } |
6555b6bd | 7631 | |
ff9940b0 RE |
7632 | return 0; |
7633 | } | |
7634 | ||
84ed5e79 | 7635 | int |
e32bac5b RE |
7636 | load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
7637 | HOST_WIDE_INT *load_offset) | |
84ed5e79 RE |
7638 | { |
7639 | int unsorted_regs[4]; | |
7640 | HOST_WIDE_INT unsorted_offsets[4]; | |
7641 | int order[4]; | |
ad076f4e | 7642 | int base_reg = -1; |
84ed5e79 RE |
7643 | int i; |
7644 | ||
1d6e90ac NC |
7645 | /* Can only handle 2, 3, or 4 insns at present, |
7646 | though could be easily extended if required. */ | |
e6d29d15 | 7647 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 | 7648 | |
f0b4bdd5 RE |
7649 | memset (order, 0, 4 * sizeof (int)); |
7650 | ||
84ed5e79 | 7651 | /* Loop over the operands and check that the memory references are |
112cdef5 | 7652 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
7653 | the same time, extract the target register, and the memory |
7654 | offsets. */ | |
7655 | for (i = 0; i < nops; i++) | |
7656 | { | |
7657 | rtx reg; | |
7658 | rtx offset; | |
7659 | ||
56636818 JL |
7660 | /* Convert a subreg of a mem into the mem itself. */ |
7661 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 7662 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 7663 | |
e6d29d15 | 7664 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
7665 | |
7666 | /* Don't reorder volatile memory references; it doesn't seem worth | |
7667 | looking for the case where the order is ok anyway. */ | |
7668 | if (MEM_VOLATILE_P (operands[nops + i])) | |
7669 | return 0; | |
7670 | ||
7671 | offset = const0_rtx; | |
7672 | ||
7673 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
7674 | || (GET_CODE (reg) == SUBREG | |
7675 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7676 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
7677 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
7678 | == REG) | |
7679 | || (GET_CODE (reg) == SUBREG | |
7680 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7681 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
7682 | == CONST_INT))) | |
7683 | { | |
7684 | if (i == 0) | |
7685 | { | |
d5b7b3ae | 7686 | base_reg = REGNO (reg); |
84ed5e79 RE |
7687 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
7688 | ? REGNO (operands[i]) | |
7689 | : REGNO (SUBREG_REG (operands[i]))); | |
7690 | order[0] = 0; | |
7691 | } | |
f676971a | 7692 | else |
84ed5e79 | 7693 | { |
6354dc9b | 7694 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
7695 | /* Not addressed from the same base register. */ |
7696 | return 0; | |
7697 | ||
7698 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
7699 | ? REGNO (operands[i]) | |
7700 | : REGNO (SUBREG_REG (operands[i]))); | |
7701 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
7702 | order[0] = i; | |
7703 | } | |
7704 | ||
7705 | /* If it isn't an integer register, or if it overwrites the | |
7706 | base register but isn't the last insn in the list, then | |
7707 | we can't do this. */ | |
7708 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 | |
7709 | || (i != nops - 1 && unsorted_regs[i] == base_reg)) | |
7710 | return 0; | |
7711 | ||
7712 | unsorted_offsets[i] = INTVAL (offset); | |
7713 | } | |
7714 | else | |
7715 | /* Not a suitable memory address. */ | |
7716 | return 0; | |
7717 | } | |
7718 | ||
7719 | /* All the useful information has now been extracted from the | |
7720 | operands into unsorted_regs and unsorted_offsets; additionally, | |
7721 | order[0] has been set to the lowest numbered register in the | |
7722 | list. Sort the registers into order, and check that the memory | |
7723 | offsets are ascending and adjacent. */ | |
7724 | ||
7725 | for (i = 1; i < nops; i++) | |
7726 | { | |
7727 | int j; | |
7728 | ||
7729 | order[i] = order[i - 1]; | |
7730 | for (j = 0; j < nops; j++) | |
7731 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
7732 | && (order[i] == order[i - 1] | |
7733 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
7734 | order[i] = j; | |
7735 | ||
7736 | /* Have we found a suitable register? if not, one must be used more | |
7737 | than once. */ | |
7738 | if (order[i] == order[i - 1]) | |
7739 | return 0; | |
7740 | ||
7741 | /* Is the memory address adjacent and ascending? */ | |
7742 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7743 | return 0; | |
7744 | } | |
7745 | ||
7746 | if (base) | |
7747 | { | |
7748 | *base = base_reg; | |
7749 | ||
7750 | for (i = 0; i < nops; i++) | |
7751 | regs[i] = unsorted_regs[order[i]]; | |
7752 | ||
7753 | *load_offset = unsorted_offsets[order[0]]; | |
7754 | } | |
7755 | ||
7756 | if (unsorted_offsets[order[0]] == 0) | |
7757 | return 1; /* ldmia */ | |
7758 | ||
5b3e6663 | 7759 | if (TARGET_ARM && unsorted_offsets[order[0]] == 4) |
84ed5e79 RE |
7760 | return 2; /* ldmib */ |
7761 | ||
5b3e6663 | 7762 | if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0) |
84ed5e79 RE |
7763 | return 3; /* ldmda */ |
7764 | ||
7765 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7766 | return 4; /* ldmdb */ | |
7767 | ||
949d79eb RE |
7768 | /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm |
7769 | if the offset isn't small enough. The reason 2 ldrs are faster | |
7770 | is because these ARMs are able to do more than one cache access | |
7771 | in a single cycle. The ARM9 and StrongARM have Harvard caches, | |
7772 | whilst the ARM8 has a double bandwidth cache. This means that | |
7773 | these cores can do both an instruction fetch and a data fetch in | |
7774 | a single cycle, so the trick of calculating the address into a | |
7775 | scratch register (one of the result regs) and then doing a load | |
7776 | multiple actually becomes slower (and no smaller in code size). | |
7777 | That is the transformation | |
f676971a | 7778 | |
6cc8c0b3 NC |
7779 | ldr rd1, [rbase + offset] |
7780 | ldr rd2, [rbase + offset + 4] | |
f676971a | 7781 | |
6cc8c0b3 | 7782 | to |
f676971a | 7783 | |
6cc8c0b3 NC |
7784 | add rd1, rbase, offset |
7785 | ldmia rd1, {rd1, rd2} | |
f676971a | 7786 | |
949d79eb RE |
7787 | produces worse code -- '3 cycles + any stalls on rd2' instead of |
7788 | '2 cycles + any stalls on rd2'. On ARMs with only one cache | |
7789 | access per cycle, the first sequence could never complete in less | |
7790 | than 6 cycles, whereas the ldm sequence would only take 5 and | |
7791 | would make better use of sequential accesses if not hitting the | |
7792 | cache. | |
7793 | ||
7794 | We cheat here and test 'arm_ld_sched' which we currently know to | |
7795 | only be true for the ARM8, ARM9 and StrongARM. If this ever | |
7796 | changes, then the test below needs to be reworked. */ | |
f5a1b0d2 | 7797 | if (nops == 2 && arm_ld_sched) |
b36ba79f RE |
7798 | return 0; |
7799 | ||
84ed5e79 RE |
7800 | /* Can't do it without setting up the offset, only do this if it takes |
7801 | no more than one insn. */ | |
f676971a | 7802 | return (const_ok_for_arm (unsorted_offsets[order[0]]) |
84ed5e79 RE |
7803 | || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; |
7804 | } | |
7805 | ||
cd2b33d0 | 7806 | const char * |
e32bac5b | 7807 | emit_ldm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7808 | { |
7809 | int regs[4]; | |
7810 | int base_reg; | |
7811 | HOST_WIDE_INT offset; | |
7812 | char buf[100]; | |
7813 | int i; | |
7814 | ||
7815 | switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
7816 | { | |
7817 | case 1: | |
5b3e6663 | 7818 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7819 | break; |
7820 | ||
7821 | case 2: | |
5b3e6663 | 7822 | strcpy (buf, "ldm%(ib%)\t"); |
84ed5e79 RE |
7823 | break; |
7824 | ||
7825 | case 3: | |
5b3e6663 | 7826 | strcpy (buf, "ldm%(da%)\t"); |
84ed5e79 RE |
7827 | break; |
7828 | ||
7829 | case 4: | |
5b3e6663 | 7830 | strcpy (buf, "ldm%(db%)\t"); |
84ed5e79 RE |
7831 | break; |
7832 | ||
7833 | case 5: | |
7834 | if (offset >= 0) | |
7835 | sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7836 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7837 | (long) offset); | |
7838 | else | |
7839 | sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, | |
7840 | reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], | |
7841 | (long) -offset); | |
7842 | output_asm_insn (buf, operands); | |
7843 | base_reg = regs[0]; | |
5b3e6663 | 7844 | strcpy (buf, "ldm%(ia%)\t"); |
84ed5e79 RE |
7845 | break; |
7846 | ||
7847 | default: | |
e6d29d15 | 7848 | gcc_unreachable (); |
84ed5e79 RE |
7849 | } |
7850 | ||
f676971a | 7851 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
7852 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
7853 | ||
7854 | for (i = 1; i < nops; i++) | |
7855 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
7856 | reg_names[regs[i]]); | |
7857 | ||
7858 | strcat (buf, "}\t%@ phole ldm"); | |
7859 | ||
7860 | output_asm_insn (buf, operands); | |
7861 | return ""; | |
7862 | } | |
7863 | ||
7864 | int | |
e32bac5b RE |
7865 | store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, |
7866 | HOST_WIDE_INT * load_offset) | |
84ed5e79 RE |
7867 | { |
7868 | int unsorted_regs[4]; | |
7869 | HOST_WIDE_INT unsorted_offsets[4]; | |
7870 | int order[4]; | |
ad076f4e | 7871 | int base_reg = -1; |
84ed5e79 RE |
7872 | int i; |
7873 | ||
7874 | /* Can only handle 2, 3, or 4 insns at present, though could be easily | |
7875 | extended if required. */ | |
e6d29d15 | 7876 | gcc_assert (nops >= 2 && nops <= 4); |
84ed5e79 | 7877 | |
f0b4bdd5 RE |
7878 | memset (order, 0, 4 * sizeof (int)); |
7879 | ||
84ed5e79 | 7880 | /* Loop over the operands and check that the memory references are |
112cdef5 | 7881 | suitable (i.e. immediate offsets from the same base register). At |
84ed5e79 RE |
7882 | the same time, extract the target register, and the memory |
7883 | offsets. */ | |
7884 | for (i = 0; i < nops; i++) | |
7885 | { | |
7886 | rtx reg; | |
7887 | rtx offset; | |
7888 | ||
56636818 JL |
7889 | /* Convert a subreg of a mem into the mem itself. */ |
7890 | if (GET_CODE (operands[nops + i]) == SUBREG) | |
4e26a7af | 7891 | operands[nops + i] = alter_subreg (operands + (nops + i)); |
56636818 | 7892 | |
e6d29d15 | 7893 | gcc_assert (GET_CODE (operands[nops + i]) == MEM); |
84ed5e79 RE |
7894 | |
7895 | /* Don't reorder volatile memory references; it doesn't seem worth | |
7896 | looking for the case where the order is ok anyway. */ | |
7897 | if (MEM_VOLATILE_P (operands[nops + i])) | |
7898 | return 0; | |
7899 | ||
7900 | offset = const0_rtx; | |
7901 | ||
7902 | if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG | |
7903 | || (GET_CODE (reg) == SUBREG | |
7904 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7905 | || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS | |
7906 | && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) | |
7907 | == REG) | |
7908 | || (GET_CODE (reg) == SUBREG | |
7909 | && GET_CODE (reg = SUBREG_REG (reg)) == REG)) | |
7910 | && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) | |
7911 | == CONST_INT))) | |
7912 | { | |
7913 | if (i == 0) | |
7914 | { | |
62b10bbc | 7915 | base_reg = REGNO (reg); |
84ed5e79 RE |
7916 | unsorted_regs[0] = (GET_CODE (operands[i]) == REG |
7917 | ? REGNO (operands[i]) | |
7918 | : REGNO (SUBREG_REG (operands[i]))); | |
7919 | order[0] = 0; | |
7920 | } | |
f676971a | 7921 | else |
84ed5e79 | 7922 | { |
6354dc9b | 7923 | if (base_reg != (int) REGNO (reg)) |
84ed5e79 RE |
7924 | /* Not addressed from the same base register. */ |
7925 | return 0; | |
7926 | ||
7927 | unsorted_regs[i] = (GET_CODE (operands[i]) == REG | |
7928 | ? REGNO (operands[i]) | |
7929 | : REGNO (SUBREG_REG (operands[i]))); | |
7930 | if (unsorted_regs[i] < unsorted_regs[order[0]]) | |
7931 | order[0] = i; | |
7932 | } | |
7933 | ||
7934 | /* If it isn't an integer register, then we can't do this. */ | |
7935 | if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) | |
7936 | return 0; | |
7937 | ||
7938 | unsorted_offsets[i] = INTVAL (offset); | |
7939 | } | |
7940 | else | |
7941 | /* Not a suitable memory address. */ | |
7942 | return 0; | |
7943 | } | |
7944 | ||
7945 | /* All the useful information has now been extracted from the | |
7946 | operands into unsorted_regs and unsorted_offsets; additionally, | |
7947 | order[0] has been set to the lowest numbered register in the | |
7948 | list. Sort the registers into order, and check that the memory | |
7949 | offsets are ascending and adjacent. */ | |
7950 | ||
7951 | for (i = 1; i < nops; i++) | |
7952 | { | |
7953 | int j; | |
7954 | ||
7955 | order[i] = order[i - 1]; | |
7956 | for (j = 0; j < nops; j++) | |
7957 | if (unsorted_regs[j] > unsorted_regs[order[i - 1]] | |
7958 | && (order[i] == order[i - 1] | |
7959 | || unsorted_regs[j] < unsorted_regs[order[i]])) | |
7960 | order[i] = j; | |
7961 | ||
7962 | /* Have we found a suitable register? if not, one must be used more | |
7963 | than once. */ | |
7964 | if (order[i] == order[i - 1]) | |
7965 | return 0; | |
7966 | ||
7967 | /* Is the memory address adjacent and ascending? */ | |
7968 | if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) | |
7969 | return 0; | |
7970 | } | |
7971 | ||
7972 | if (base) | |
7973 | { | |
7974 | *base = base_reg; | |
7975 | ||
7976 | for (i = 0; i < nops; i++) | |
7977 | regs[i] = unsorted_regs[order[i]]; | |
7978 | ||
7979 | *load_offset = unsorted_offsets[order[0]]; | |
7980 | } | |
7981 | ||
7982 | if (unsorted_offsets[order[0]] == 0) | |
7983 | return 1; /* stmia */ | |
7984 | ||
7985 | if (unsorted_offsets[order[0]] == 4) | |
7986 | return 2; /* stmib */ | |
7987 | ||
7988 | if (unsorted_offsets[order[nops - 1]] == 0) | |
7989 | return 3; /* stmda */ | |
7990 | ||
7991 | if (unsorted_offsets[order[nops - 1]] == -4) | |
7992 | return 4; /* stmdb */ | |
7993 | ||
7994 | return 0; | |
7995 | } | |
7996 | ||
cd2b33d0 | 7997 | const char * |
e32bac5b | 7998 | emit_stm_seq (rtx *operands, int nops) |
84ed5e79 RE |
7999 | { |
8000 | int regs[4]; | |
8001 | int base_reg; | |
8002 | HOST_WIDE_INT offset; | |
8003 | char buf[100]; | |
8004 | int i; | |
8005 | ||
8006 | switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) | |
8007 | { | |
8008 | case 1: | |
5b3e6663 | 8009 | strcpy (buf, "stm%(ia%)\t"); |
84ed5e79 RE |
8010 | break; |
8011 | ||
8012 | case 2: | |
5b3e6663 | 8013 | strcpy (buf, "stm%(ib%)\t"); |
84ed5e79 RE |
8014 | break; |
8015 | ||
8016 | case 3: | |
5b3e6663 | 8017 | strcpy (buf, "stm%(da%)\t"); |
84ed5e79 RE |
8018 | break; |
8019 | ||
8020 | case 4: | |
5b3e6663 | 8021 | strcpy (buf, "stm%(db%)\t"); |
84ed5e79 RE |
8022 | break; |
8023 | ||
8024 | default: | |
e6d29d15 | 8025 | gcc_unreachable (); |
84ed5e79 RE |
8026 | } |
8027 | ||
f676971a | 8028 | sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, |
84ed5e79 RE |
8029 | reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); |
8030 | ||
8031 | for (i = 1; i < nops; i++) | |
8032 | sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, | |
8033 | reg_names[regs[i]]); | |
8034 | ||
8035 | strcat (buf, "}\t%@ phole stm"); | |
8036 | ||
8037 | output_asm_insn (buf, operands); | |
8038 | return ""; | |
8039 | } | |
ff9940b0 | 8040 | \f |
6354dc9b | 8041 | /* Routines for use in generating RTL. */ |
1d6e90ac | 8042 | |
f3bb6135 | 8043 | rtx |
e32bac5b | 8044 | arm_gen_load_multiple (int base_regno, int count, rtx from, int up, |
50ed9cea | 8045 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 8046 | { |
50ed9cea | 8047 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
8048 | int i = 0, j; |
8049 | rtx result; | |
8050 | int sign = up ? 1 : -1; | |
50ed9cea | 8051 | rtx mem, addr; |
ff9940b0 | 8052 | |
d19fb8e3 | 8053 | /* XScale has load-store double instructions, but they have stricter |
1e5f1716 | 8054 | alignment requirements than load-store multiple, so we cannot |
d19fb8e3 NC |
8055 | use them. |
8056 | ||
8057 | For XScale ldm requires 2 + NREGS cycles to complete and blocks | |
8058 | the pipeline until completion. | |
8059 | ||
8060 | NREGS CYCLES | |
8061 | 1 3 | |
8062 | 2 4 | |
8063 | 3 5 | |
8064 | 4 6 | |
8065 | ||
8066 | An ldr instruction takes 1-3 cycles, but does not block the | |
8067 | pipeline. | |
8068 | ||
8069 | NREGS CYCLES | |
8070 | 1 1-3 | |
8071 | 2 2-6 | |
8072 | 3 3-9 | |
8073 | 4 4-12 | |
8074 | ||
8075 | Best case ldr will always win. However, the more ldr instructions | |
8076 | we issue, the less likely we are to be able to schedule them well. | |
8077 | Using ldr instructions also increases code size. | |
8078 | ||
8079 | As a compromise, we use ldr for counts of 1 or 2 regs, and ldm | |
8080 | for counts of 3 or 4 regs. */ | |
4b3c2e48 | 8081 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
8082 | { |
8083 | rtx seq; | |
f676971a | 8084 | |
d19fb8e3 | 8085 | start_sequence (); |
f676971a | 8086 | |
d19fb8e3 NC |
8087 | for (i = 0; i < count; i++) |
8088 | { | |
50ed9cea RH |
8089 | addr = plus_constant (from, i * 4 * sign); |
8090 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 8091 | emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); |
50ed9cea | 8092 | offset += 4 * sign; |
d19fb8e3 NC |
8093 | } |
8094 | ||
8095 | if (write_back) | |
50ed9cea RH |
8096 | { |
8097 | emit_move_insn (from, plus_constant (from, count * 4 * sign)); | |
8098 | *offsetp = offset; | |
8099 | } | |
d19fb8e3 | 8100 | |
2f937369 | 8101 | seq = get_insns (); |
d19fb8e3 | 8102 | end_sequence (); |
f676971a | 8103 | |
d19fb8e3 NC |
8104 | return seq; |
8105 | } | |
8106 | ||
43cffd11 | 8107 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 8108 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 8109 | if (write_back) |
f3bb6135 | 8110 | { |
ff9940b0 | 8111 | XVECEXP (result, 0, 0) |
d66437c5 | 8112 | = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); |
ff9940b0 RE |
8113 | i = 1; |
8114 | count++; | |
f3bb6135 RE |
8115 | } |
8116 | ||
ff9940b0 | 8117 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 8118 | { |
50ed9cea RH |
8119 | addr = plus_constant (from, j * 4 * sign); |
8120 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
8121 | XVECEXP (result, 0, i) |
8122 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); | |
50ed9cea | 8123 | offset += 4 * sign; |
f3bb6135 RE |
8124 | } |
8125 | ||
50ed9cea RH |
8126 | if (write_back) |
8127 | *offsetp = offset; | |
8128 | ||
ff9940b0 RE |
8129 | return result; |
8130 | } | |
8131 | ||
f3bb6135 | 8132 | rtx |
e32bac5b | 8133 | arm_gen_store_multiple (int base_regno, int count, rtx to, int up, |
50ed9cea | 8134 | int write_back, rtx basemem, HOST_WIDE_INT *offsetp) |
ff9940b0 | 8135 | { |
50ed9cea | 8136 | HOST_WIDE_INT offset = *offsetp; |
ff9940b0 RE |
8137 | int i = 0, j; |
8138 | rtx result; | |
8139 | int sign = up ? 1 : -1; | |
50ed9cea | 8140 | rtx mem, addr; |
ff9940b0 | 8141 | |
d19fb8e3 NC |
8142 | /* See arm_gen_load_multiple for discussion of |
8143 | the pros/cons of ldm/stm usage for XScale. */ | |
4b3c2e48 | 8144 | if (arm_tune_xscale && count <= 2 && ! optimize_size) |
d19fb8e3 NC |
8145 | { |
8146 | rtx seq; | |
f676971a | 8147 | |
d19fb8e3 | 8148 | start_sequence (); |
f676971a | 8149 | |
d19fb8e3 NC |
8150 | for (i = 0; i < count; i++) |
8151 | { | |
50ed9cea RH |
8152 | addr = plus_constant (to, i * 4 * sign); |
8153 | mem = adjust_automodify_address (basemem, SImode, addr, offset); | |
d19fb8e3 | 8154 | emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); |
50ed9cea | 8155 | offset += 4 * sign; |
d19fb8e3 NC |
8156 | } |
8157 | ||
8158 | if (write_back) | |
50ed9cea RH |
8159 | { |
8160 | emit_move_insn (to, plus_constant (to, count * 4 * sign)); | |
8161 | *offsetp = offset; | |
8162 | } | |
d19fb8e3 | 8163 | |
2f937369 | 8164 | seq = get_insns (); |
d19fb8e3 | 8165 | end_sequence (); |
f676971a | 8166 | |
d19fb8e3 NC |
8167 | return seq; |
8168 | } | |
8169 | ||
43cffd11 | 8170 | result = gen_rtx_PARALLEL (VOIDmode, |
41e3f998 | 8171 | rtvec_alloc (count + (write_back ? 1 : 0))); |
ff9940b0 | 8172 | if (write_back) |
f3bb6135 | 8173 | { |
ff9940b0 | 8174 | XVECEXP (result, 0, 0) |
d66437c5 | 8175 | = gen_rtx_SET (VOIDmode, to, |
43cffd11 | 8176 | plus_constant (to, count * 4 * sign)); |
ff9940b0 RE |
8177 | i = 1; |
8178 | count++; | |
f3bb6135 RE |
8179 | } |
8180 | ||
ff9940b0 | 8181 | for (j = 0; i < count; i++, j++) |
f3bb6135 | 8182 | { |
50ed9cea RH |
8183 | addr = plus_constant (to, j * 4 * sign); |
8184 | mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); | |
43cffd11 RE |
8185 | XVECEXP (result, 0, i) |
8186 | = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); | |
50ed9cea | 8187 | offset += 4 * sign; |
f3bb6135 RE |
8188 | } |
8189 | ||
50ed9cea RH |
8190 | if (write_back) |
8191 | *offsetp = offset; | |
8192 | ||
ff9940b0 RE |
8193 | return result; |
8194 | } | |
8195 | ||
880e2516 | 8196 | int |
70128ad9 | 8197 | arm_gen_movmemqi (rtx *operands) |
880e2516 RE |
8198 | { |
8199 | HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; | |
50ed9cea | 8200 | HOST_WIDE_INT srcoffset, dstoffset; |
ad076f4e | 8201 | int i; |
50ed9cea | 8202 | rtx src, dst, srcbase, dstbase; |
880e2516 | 8203 | rtx part_bytes_reg = NULL; |
56636818 | 8204 | rtx mem; |
880e2516 RE |
8205 | |
8206 | if (GET_CODE (operands[2]) != CONST_INT | |
8207 | || GET_CODE (operands[3]) != CONST_INT | |
8208 | || INTVAL (operands[2]) > 64 | |
8209 | || INTVAL (operands[3]) & 3) | |
8210 | return 0; | |
8211 | ||
50ed9cea RH |
8212 | dstbase = operands[0]; |
8213 | srcbase = operands[1]; | |
56636818 | 8214 | |
50ed9cea RH |
8215 | dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); |
8216 | src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); | |
880e2516 | 8217 | |
e9d7b180 | 8218 | in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); |
880e2516 RE |
8219 | out_words_to_go = INTVAL (operands[2]) / 4; |
8220 | last_bytes = INTVAL (operands[2]) & 3; | |
50ed9cea | 8221 | dstoffset = srcoffset = 0; |
880e2516 RE |
8222 | |
8223 | if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) | |
43cffd11 | 8224 | part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); |
880e2516 RE |
8225 | |
8226 | for (i = 0; in_words_to_go >= 2; i+=4) | |
8227 | { | |
bd9c7e23 | 8228 | if (in_words_to_go > 4) |
56636818 | 8229 | emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, |
50ed9cea | 8230 | srcbase, &srcoffset)); |
bd9c7e23 | 8231 | else |
f676971a | 8232 | emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, |
50ed9cea | 8233 | FALSE, srcbase, &srcoffset)); |
bd9c7e23 | 8234 | |
880e2516 RE |
8235 | if (out_words_to_go) |
8236 | { | |
bd9c7e23 | 8237 | if (out_words_to_go > 4) |
56636818 | 8238 | emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, |
50ed9cea | 8239 | dstbase, &dstoffset)); |
bd9c7e23 RE |
8240 | else if (out_words_to_go != 1) |
8241 | emit_insn (arm_gen_store_multiple (0, out_words_to_go, | |
f676971a | 8242 | dst, TRUE, |
bd9c7e23 | 8243 | (last_bytes == 0 |
56636818 | 8244 | ? FALSE : TRUE), |
50ed9cea | 8245 | dstbase, &dstoffset)); |
880e2516 RE |
8246 | else |
8247 | { | |
50ed9cea | 8248 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); |
43cffd11 | 8249 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
bd9c7e23 | 8250 | if (last_bytes != 0) |
50ed9cea RH |
8251 | { |
8252 | emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); | |
8253 | dstoffset += 4; | |
8254 | } | |
880e2516 RE |
8255 | } |
8256 | } | |
8257 | ||
8258 | in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; | |
8259 | out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; | |
8260 | } | |
8261 | ||
8262 | /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ | |
8263 | if (out_words_to_go) | |
62b10bbc NC |
8264 | { |
8265 | rtx sreg; | |
f676971a | 8266 | |
50ed9cea RH |
8267 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
8268 | sreg = copy_to_reg (mem); | |
8269 | ||
8270 | mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); | |
62b10bbc | 8271 | emit_move_insn (mem, sreg); |
62b10bbc | 8272 | in_words_to_go--; |
f676971a | 8273 | |
e6d29d15 | 8274 | gcc_assert (!in_words_to_go); /* Sanity check */ |
62b10bbc | 8275 | } |
880e2516 RE |
8276 | |
8277 | if (in_words_to_go) | |
8278 | { | |
e6d29d15 | 8279 | gcc_assert (in_words_to_go > 0); |
880e2516 | 8280 | |
50ed9cea | 8281 | mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); |
56636818 | 8282 | part_bytes_reg = copy_to_mode_reg (SImode, mem); |
880e2516 RE |
8283 | } |
8284 | ||
e6d29d15 | 8285 | gcc_assert (!last_bytes || part_bytes_reg); |
d5b7b3ae | 8286 | |
880e2516 RE |
8287 | if (BYTES_BIG_ENDIAN && last_bytes) |
8288 | { | |
8289 | rtx tmp = gen_reg_rtx (SImode); | |
8290 | ||
6354dc9b | 8291 | /* The bytes we want are in the top end of the word. */ |
bee06f3d RE |
8292 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, |
8293 | GEN_INT (8 * (4 - last_bytes)))); | |
880e2516 | 8294 | part_bytes_reg = tmp; |
f676971a | 8295 | |
880e2516 RE |
8296 | while (last_bytes) |
8297 | { | |
50ed9cea RH |
8298 | mem = adjust_automodify_address (dstbase, QImode, |
8299 | plus_constant (dst, last_bytes - 1), | |
8300 | dstoffset + last_bytes - 1); | |
5d5603e2 BS |
8301 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
8302 | ||
880e2516 RE |
8303 | if (--last_bytes) |
8304 | { | |
8305 | tmp = gen_reg_rtx (SImode); | |
8306 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); | |
8307 | part_bytes_reg = tmp; | |
8308 | } | |
8309 | } | |
f676971a | 8310 | |
880e2516 RE |
8311 | } |
8312 | else | |
8313 | { | |
d5b7b3ae | 8314 | if (last_bytes > 1) |
880e2516 | 8315 | { |
50ed9cea | 8316 | mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); |
5d5603e2 | 8317 | emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); |
d5b7b3ae RE |
8318 | last_bytes -= 2; |
8319 | if (last_bytes) | |
880e2516 RE |
8320 | { |
8321 | rtx tmp = gen_reg_rtx (SImode); | |
a556fd39 | 8322 | emit_insn (gen_addsi3 (dst, dst, const2_rtx)); |
d5b7b3ae | 8323 | emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); |
880e2516 | 8324 | part_bytes_reg = tmp; |
50ed9cea | 8325 | dstoffset += 2; |
880e2516 RE |
8326 | } |
8327 | } | |
f676971a | 8328 | |
d5b7b3ae RE |
8329 | if (last_bytes) |
8330 | { | |
50ed9cea | 8331 | mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); |
5d5603e2 | 8332 | emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); |
d5b7b3ae | 8333 | } |
880e2516 RE |
8334 | } |
8335 | ||
8336 | return 1; | |
8337 | } | |
8338 | ||
03f1640c RE |
8339 | /* Select a dominance comparison mode if possible for a test of the general |
8340 | form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. | |
f676971a | 8341 | COND_OR == DOM_CC_X_AND_Y => (X && Y) |
03f1640c | 8342 | COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) |
f676971a | 8343 | COND_OR == DOM_CC_X_OR_Y => (X || Y) |
03f1640c | 8344 | In all cases OP will be either EQ or NE, but we don't need to know which |
f676971a | 8345 | here. If we are unable to support a dominance comparison we return |
03f1640c RE |
8346 | CC mode. This will then fail to match for the RTL expressions that |
8347 | generate this call. */ | |
03f1640c | 8348 | enum machine_mode |
e32bac5b | 8349 | arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) |
84ed5e79 RE |
8350 | { |
8351 | enum rtx_code cond1, cond2; | |
8352 | int swapped = 0; | |
8353 | ||
8354 | /* Currently we will probably get the wrong result if the individual | |
8355 | comparisons are not simple. This also ensures that it is safe to | |
956d6950 | 8356 | reverse a comparison if necessary. */ |
84ed5e79 RE |
8357 | if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) |
8358 | != CCmode) | |
8359 | || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) | |
8360 | != CCmode)) | |
8361 | return CCmode; | |
8362 | ||
1646cf41 RE |
8363 | /* The if_then_else variant of this tests the second condition if the |
8364 | first passes, but is true if the first fails. Reverse the first | |
8365 | condition to get a true "inclusive-or" expression. */ | |
03f1640c | 8366 | if (cond_or == DOM_CC_NX_OR_Y) |
84ed5e79 RE |
8367 | cond1 = reverse_condition (cond1); |
8368 | ||
8369 | /* If the comparisons are not equal, and one doesn't dominate the other, | |
8370 | then we can't do this. */ | |
f676971a | 8371 | if (cond1 != cond2 |
5895f793 RE |
8372 | && !comparison_dominates_p (cond1, cond2) |
8373 | && (swapped = 1, !comparison_dominates_p (cond2, cond1))) | |
84ed5e79 RE |
8374 | return CCmode; |
8375 | ||
8376 | if (swapped) | |
8377 | { | |
8378 | enum rtx_code temp = cond1; | |
8379 | cond1 = cond2; | |
8380 | cond2 = temp; | |
8381 | } | |
8382 | ||
8383 | switch (cond1) | |
8384 | { | |
8385 | case EQ: | |
e6d29d15 | 8386 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 RE |
8387 | return CC_DEQmode; |
8388 | ||
8389 | switch (cond2) | |
8390 | { | |
e6d29d15 | 8391 | case EQ: return CC_DEQmode; |
84ed5e79 RE |
8392 | case LE: return CC_DLEmode; |
8393 | case LEU: return CC_DLEUmode; | |
8394 | case GE: return CC_DGEmode; | |
8395 | case GEU: return CC_DGEUmode; | |
e6d29d15 | 8396 | default: gcc_unreachable (); |
84ed5e79 RE |
8397 | } |
8398 | ||
84ed5e79 | 8399 | case LT: |
e6d29d15 | 8400 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8401 | return CC_DLTmode; |
e0b92319 | 8402 | |
e6d29d15 NS |
8403 | switch (cond2) |
8404 | { | |
8405 | case LT: | |
8406 | return CC_DLTmode; | |
8407 | case LE: | |
8408 | return CC_DLEmode; | |
8409 | case NE: | |
8410 | return CC_DNEmode; | |
8411 | default: | |
8412 | gcc_unreachable (); | |
8413 | } | |
84ed5e79 RE |
8414 | |
8415 | case GT: | |
e6d29d15 | 8416 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8417 | return CC_DGTmode; |
e6d29d15 NS |
8418 | |
8419 | switch (cond2) | |
8420 | { | |
8421 | case GT: | |
8422 | return CC_DGTmode; | |
8423 | case GE: | |
8424 | return CC_DGEmode; | |
8425 | case NE: | |
8426 | return CC_DNEmode; | |
8427 | default: | |
8428 | gcc_unreachable (); | |
8429 | } | |
f676971a | 8430 | |
84ed5e79 | 8431 | case LTU: |
e6d29d15 | 8432 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8433 | return CC_DLTUmode; |
e6d29d15 NS |
8434 | |
8435 | switch (cond2) | |
8436 | { | |
8437 | case LTU: | |
8438 | return CC_DLTUmode; | |
8439 | case LEU: | |
8440 | return CC_DLEUmode; | |
8441 | case NE: | |
8442 | return CC_DNEmode; | |
8443 | default: | |
8444 | gcc_unreachable (); | |
8445 | } | |
84ed5e79 RE |
8446 | |
8447 | case GTU: | |
e6d29d15 | 8448 | if (cond_or == DOM_CC_X_AND_Y) |
84ed5e79 | 8449 | return CC_DGTUmode; |
e0b92319 | 8450 | |
e6d29d15 NS |
8451 | switch (cond2) |
8452 | { | |
8453 | case GTU: | |
8454 | return CC_DGTUmode; | |
8455 | case GEU: | |
8456 | return CC_DGEUmode; | |
8457 | case NE: | |
8458 | return CC_DNEmode; | |
8459 | default: | |
8460 | gcc_unreachable (); | |
8461 | } | |
84ed5e79 RE |
8462 | |
8463 | /* The remaining cases only occur when both comparisons are the | |
8464 | same. */ | |
8465 | case NE: | |
e6d29d15 | 8466 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8467 | return CC_DNEmode; |
8468 | ||
8469 | case LE: | |
e6d29d15 | 8470 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8471 | return CC_DLEmode; |
8472 | ||
8473 | case GE: | |
e6d29d15 | 8474 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8475 | return CC_DGEmode; |
8476 | ||
8477 | case LEU: | |
e6d29d15 | 8478 | gcc_assert (cond1 == cond2); |
84ed5e79 RE |
8479 | return CC_DLEUmode; |
8480 | ||
8481 | case GEU: | |
e6d29d15 | 8482 | gcc_assert (cond1 == cond2); |
84ed5e79 | 8483 | return CC_DGEUmode; |
ad076f4e RE |
8484 | |
8485 | default: | |
e6d29d15 | 8486 | gcc_unreachable (); |
84ed5e79 | 8487 | } |
84ed5e79 RE |
8488 | } |
8489 | ||
8490 | enum machine_mode | |
e32bac5b | 8491 | arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) |
84ed5e79 RE |
8492 | { |
8493 | /* All floating point compares return CCFP if it is an equality | |
8494 | comparison, and CCFPE otherwise. */ | |
8495 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
e45b72c4 RE |
8496 | { |
8497 | switch (op) | |
8498 | { | |
8499 | case EQ: | |
8500 | case NE: | |
8501 | case UNORDERED: | |
8502 | case ORDERED: | |
8503 | case UNLT: | |
8504 | case UNLE: | |
8505 | case UNGT: | |
8506 | case UNGE: | |
8507 | case UNEQ: | |
8508 | case LTGT: | |
8509 | return CCFPmode; | |
8510 | ||
8511 | case LT: | |
8512 | case LE: | |
8513 | case GT: | |
8514 | case GE: | |
9b66ebb1 | 8515 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK) |
9b6b54e2 | 8516 | return CCFPmode; |
e45b72c4 RE |
8517 | return CCFPEmode; |
8518 | ||
8519 | default: | |
e6d29d15 | 8520 | gcc_unreachable (); |
e45b72c4 RE |
8521 | } |
8522 | } | |
f676971a | 8523 | |
84ed5e79 RE |
8524 | /* A compare with a shifted operand. Because of canonicalization, the |
8525 | comparison will have to be swapped when we emit the assembler. */ | |
8526 | if (GET_MODE (y) == SImode && GET_CODE (y) == REG | |
8527 | && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
8528 | || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE | |
8529 | || GET_CODE (x) == ROTATERT)) | |
8530 | return CC_SWPmode; | |
8531 | ||
04d8b819 RE |
8532 | /* This operation is performed swapped, but since we only rely on the Z |
8533 | flag we don't need an additional mode. */ | |
8534 | if (GET_MODE (y) == SImode && REG_P (y) | |
8535 | && GET_CODE (x) == NEG | |
8536 | && (op == EQ || op == NE)) | |
8537 | return CC_Zmode; | |
8538 | ||
f676971a | 8539 | /* This is a special case that is used by combine to allow a |
956d6950 | 8540 | comparison of a shifted byte load to be split into a zero-extend |
84ed5e79 | 8541 | followed by a comparison of the shifted integer (only valid for |
956d6950 | 8542 | equalities and unsigned inequalities). */ |
84ed5e79 RE |
8543 | if (GET_MODE (x) == SImode |
8544 | && GET_CODE (x) == ASHIFT | |
8545 | && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 | |
8546 | && GET_CODE (XEXP (x, 0)) == SUBREG | |
8547 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM | |
8548 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode | |
8549 | && (op == EQ || op == NE | |
8550 | || op == GEU || op == GTU || op == LTU || op == LEU) | |
8551 | && GET_CODE (y) == CONST_INT) | |
8552 | return CC_Zmode; | |
8553 | ||
1646cf41 RE |
8554 | /* A construct for a conditional compare, if the false arm contains |
8555 | 0, then both conditions must be true, otherwise either condition | |
8556 | must be true. Not all conditions are possible, so CCmode is | |
8557 | returned if it can't be done. */ | |
8558 | if (GET_CODE (x) == IF_THEN_ELSE | |
8559 | && (XEXP (x, 2) == const0_rtx | |
8560 | || XEXP (x, 2) == const1_rtx) | |
ec8e098d PB |
8561 | && COMPARISON_P (XEXP (x, 0)) |
8562 | && COMPARISON_P (XEXP (x, 1))) | |
f676971a | 8563 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
03f1640c | 8564 | INTVAL (XEXP (x, 2))); |
1646cf41 RE |
8565 | |
8566 | /* Alternate canonicalizations of the above. These are somewhat cleaner. */ | |
8567 | if (GET_CODE (x) == AND | |
ec8e098d PB |
8568 | && COMPARISON_P (XEXP (x, 0)) |
8569 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
8570 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
8571 | DOM_CC_X_AND_Y); | |
1646cf41 RE |
8572 | |
8573 | if (GET_CODE (x) == IOR | |
ec8e098d PB |
8574 | && COMPARISON_P (XEXP (x, 0)) |
8575 | && COMPARISON_P (XEXP (x, 1))) | |
03f1640c RE |
8576 | return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), |
8577 | DOM_CC_X_OR_Y); | |
1646cf41 | 8578 | |
defc0463 RE |
8579 | /* An operation (on Thumb) where we want to test for a single bit. |
8580 | This is done by shifting that bit up into the top bit of a | |
8581 | scratch register; we can then branch on the sign bit. */ | |
5b3e6663 | 8582 | if (TARGET_THUMB1 |
defc0463 RE |
8583 | && GET_MODE (x) == SImode |
8584 | && (op == EQ || op == NE) | |
f9fa4363 RE |
8585 | && GET_CODE (x) == ZERO_EXTRACT |
8586 | && XEXP (x, 1) == const1_rtx) | |
defc0463 RE |
8587 | return CC_Nmode; |
8588 | ||
84ed5e79 RE |
8589 | /* An operation that sets the condition codes as a side-effect, the |
8590 | V flag is not set correctly, so we can only use comparisons where | |
8591 | this doesn't matter. (For LT and GE we can use "mi" and "pl" | |
defc0463 | 8592 | instead.) */ |
5b3e6663 | 8593 | /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */ |
84ed5e79 RE |
8594 | if (GET_MODE (x) == SImode |
8595 | && y == const0_rtx | |
8596 | && (op == EQ || op == NE || op == LT || op == GE) | |
8597 | && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS | |
8598 | || GET_CODE (x) == AND || GET_CODE (x) == IOR | |
8599 | || GET_CODE (x) == XOR || GET_CODE (x) == MULT | |
8600 | || GET_CODE (x) == NOT || GET_CODE (x) == NEG | |
8601 | || GET_CODE (x) == LSHIFTRT | |
8602 | || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT | |
defc0463 | 8603 | || GET_CODE (x) == ROTATERT |
5b3e6663 | 8604 | || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) |
84ed5e79 RE |
8605 | return CC_NOOVmode; |
8606 | ||
84ed5e79 RE |
8607 | if (GET_MODE (x) == QImode && (op == EQ || op == NE)) |
8608 | return CC_Zmode; | |
8609 | ||
bd9c7e23 RE |
8610 | if (GET_MODE (x) == SImode && (op == LTU || op == GEU) |
8611 | && GET_CODE (x) == PLUS | |
8612 | && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) | |
8613 | return CC_Cmode; | |
8614 | ||
84ed5e79 RE |
8615 | return CCmode; |
8616 | } | |
8617 | ||
ff9940b0 RE |
8618 | /* X and Y are two things to compare using CODE. Emit the compare insn and |
8619 | return the rtx for register 0 in the proper mode. FP means this is a | |
8620 | floating point compare: I don't think that it is needed on the arm. */ | |
ff9940b0 | 8621 | rtx |
e32bac5b | 8622 | arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) |
ff9940b0 RE |
8623 | { |
8624 | enum machine_mode mode = SELECT_CC_MODE (code, x, y); | |
d5b7b3ae | 8625 | rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); |
ff9940b0 | 8626 | |
d66437c5 | 8627 | emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); |
ff9940b0 RE |
8628 | |
8629 | return cc_reg; | |
8630 | } | |
8631 | ||
fcd53748 JT |
8632 | /* Generate a sequence of insns that will generate the correct return |
8633 | address mask depending on the physical architecture that the program | |
8634 | is running on. */ | |
fcd53748 | 8635 | rtx |
e32bac5b | 8636 | arm_gen_return_addr_mask (void) |
fcd53748 JT |
8637 | { |
8638 | rtx reg = gen_reg_rtx (Pmode); | |
8639 | ||
8640 | emit_insn (gen_return_addr_mask (reg)); | |
8641 | return reg; | |
8642 | } | |
8643 | ||
0a81f500 | 8644 | void |
e32bac5b | 8645 | arm_reload_in_hi (rtx *operands) |
0a81f500 | 8646 | { |
f9cc092a RE |
8647 | rtx ref = operands[1]; |
8648 | rtx base, scratch; | |
8649 | HOST_WIDE_INT offset = 0; | |
8650 | ||
8651 | if (GET_CODE (ref) == SUBREG) | |
8652 | { | |
ddef6bc7 | 8653 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
8654 | ref = SUBREG_REG (ref); |
8655 | } | |
8656 | ||
8657 | if (GET_CODE (ref) == REG) | |
8658 | { | |
8659 | /* We have a pseudo which has been spilt onto the stack; there | |
8660 | are two cases here: the first where there is a simple | |
8661 | stack-slot replacement and a second where the stack-slot is | |
8662 | out of range, or is used as a subreg. */ | |
8663 | if (reg_equiv_mem[REGNO (ref)]) | |
8664 | { | |
8665 | ref = reg_equiv_mem[REGNO (ref)]; | |
8666 | base = find_replacement (&XEXP (ref, 0)); | |
8667 | } | |
8668 | else | |
6354dc9b | 8669 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
8670 | base = reg_equiv_address[REGNO (ref)]; |
8671 | } | |
8672 | else | |
8673 | base = find_replacement (&XEXP (ref, 0)); | |
0a81f500 | 8674 | |
e5e809f4 JL |
8675 | /* Handle the case where the address is too complex to be offset by 1. */ |
8676 | if (GET_CODE (base) == MINUS | |
8677 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
8678 | { | |
f9cc092a | 8679 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); |
e5e809f4 | 8680 | |
d66437c5 | 8681 | emit_set_insn (base_plus, base); |
e5e809f4 JL |
8682 | base = base_plus; |
8683 | } | |
f9cc092a RE |
8684 | else if (GET_CODE (base) == PLUS) |
8685 | { | |
6354dc9b | 8686 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
8687 | HOST_WIDE_INT hi, lo; |
8688 | ||
8689 | offset += INTVAL (XEXP (base, 1)); | |
8690 | base = XEXP (base, 0); | |
8691 | ||
6354dc9b | 8692 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
8693 | /* Valid range for lo is -4095 -> 4095 */ |
8694 | lo = (offset >= 0 | |
8695 | ? (offset & 0xfff) | |
8696 | : -((-offset) & 0xfff)); | |
8697 | ||
8698 | /* Corner case, if lo is the max offset then we would be out of range | |
8699 | once we have added the additional 1 below, so bump the msb into the | |
8700 | pre-loading insn(s). */ | |
8701 | if (lo == 4095) | |
8702 | lo &= 0x7ff; | |
8703 | ||
30cf4896 KG |
8704 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
8705 | ^ (HOST_WIDE_INT) 0x80000000) | |
8706 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 8707 | |
e6d29d15 | 8708 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
8709 | |
8710 | if (hi != 0) | |
8711 | { | |
8712 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8713 | ||
8714 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 8715 | that require more than one insn. */ |
f9cc092a RE |
8716 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
8717 | base = base_plus; | |
8718 | offset = lo; | |
8719 | } | |
8720 | } | |
e5e809f4 | 8721 | |
3a1944a6 RE |
8722 | /* Operands[2] may overlap operands[0] (though it won't overlap |
8723 | operands[1]), that's why we asked for a DImode reg -- so we can | |
8724 | use the bit that does not overlap. */ | |
8725 | if (REGNO (operands[2]) == REGNO (operands[0])) | |
8726 | scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8727 | else | |
8728 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
8729 | ||
f9cc092a RE |
8730 | emit_insn (gen_zero_extendqisi2 (scratch, |
8731 | gen_rtx_MEM (QImode, | |
8732 | plus_constant (base, | |
8733 | offset)))); | |
43cffd11 | 8734 | emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), |
f676971a | 8735 | gen_rtx_MEM (QImode, |
f9cc092a RE |
8736 | plus_constant (base, |
8737 | offset + 1)))); | |
5895f793 | 8738 | if (!BYTES_BIG_ENDIAN) |
d66437c5 RE |
8739 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8740 | gen_rtx_IOR (SImode, | |
8741 | gen_rtx_ASHIFT | |
8742 | (SImode, | |
8743 | gen_rtx_SUBREG (SImode, operands[0], 0), | |
8744 | GEN_INT (8)), | |
8745 | scratch)); | |
0a81f500 | 8746 | else |
d66437c5 RE |
8747 | emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), |
8748 | gen_rtx_IOR (SImode, | |
8749 | gen_rtx_ASHIFT (SImode, scratch, | |
8750 | GEN_INT (8)), | |
8751 | gen_rtx_SUBREG (SImode, operands[0], 0))); | |
0a81f500 RE |
8752 | } |
8753 | ||
72ac76be | 8754 | /* Handle storing a half-word to memory during reload by synthesizing as two |
f9cc092a RE |
8755 | byte stores. Take care not to clobber the input values until after we |
8756 | have moved them somewhere safe. This code assumes that if the DImode | |
8757 | scratch in operands[2] overlaps either the input value or output address | |
8758 | in some way, then that value must die in this insn (we absolutely need | |
8759 | two scratch registers for some corner cases). */ | |
f3bb6135 | 8760 | void |
e32bac5b | 8761 | arm_reload_out_hi (rtx *operands) |
af48348a | 8762 | { |
f9cc092a RE |
8763 | rtx ref = operands[0]; |
8764 | rtx outval = operands[1]; | |
8765 | rtx base, scratch; | |
8766 | HOST_WIDE_INT offset = 0; | |
8767 | ||
8768 | if (GET_CODE (ref) == SUBREG) | |
8769 | { | |
ddef6bc7 | 8770 | offset = SUBREG_BYTE (ref); |
f9cc092a RE |
8771 | ref = SUBREG_REG (ref); |
8772 | } | |
8773 | ||
f9cc092a RE |
8774 | if (GET_CODE (ref) == REG) |
8775 | { | |
8776 | /* We have a pseudo which has been spilt onto the stack; there | |
8777 | are two cases here: the first where there is a simple | |
8778 | stack-slot replacement and a second where the stack-slot is | |
8779 | out of range, or is used as a subreg. */ | |
8780 | if (reg_equiv_mem[REGNO (ref)]) | |
8781 | { | |
8782 | ref = reg_equiv_mem[REGNO (ref)]; | |
8783 | base = find_replacement (&XEXP (ref, 0)); | |
8784 | } | |
8785 | else | |
6354dc9b | 8786 | /* The slot is out of range, or was dressed up in a SUBREG. */ |
f9cc092a RE |
8787 | base = reg_equiv_address[REGNO (ref)]; |
8788 | } | |
8789 | else | |
8790 | base = find_replacement (&XEXP (ref, 0)); | |
8791 | ||
8792 | scratch = gen_rtx_REG (SImode, REGNO (operands[2])); | |
8793 | ||
8794 | /* Handle the case where the address is too complex to be offset by 1. */ | |
8795 | if (GET_CODE (base) == MINUS | |
8796 | || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) | |
8797 | { | |
8798 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8799 | ||
8800 | /* Be careful not to destroy OUTVAL. */ | |
8801 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8802 | { | |
8803 | /* Updating base_plus might destroy outval, see if we can | |
8804 | swap the scratch and base_plus. */ | |
5895f793 | 8805 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8806 | { |
8807 | rtx tmp = scratch; | |
8808 | scratch = base_plus; | |
8809 | base_plus = tmp; | |
8810 | } | |
8811 | else | |
8812 | { | |
8813 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8814 | ||
8815 | /* Be conservative and copy OUTVAL into the scratch now, | |
8816 | this should only be necessary if outval is a subreg | |
8817 | of something larger than a word. */ | |
8818 | /* XXX Might this clobber base? I can't see how it can, | |
8819 | since scratch is known to overlap with OUTVAL, and | |
8820 | must be wider than a word. */ | |
8821 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8822 | outval = scratch_hi; | |
8823 | } | |
8824 | } | |
8825 | ||
d66437c5 | 8826 | emit_set_insn (base_plus, base); |
f9cc092a RE |
8827 | base = base_plus; |
8828 | } | |
8829 | else if (GET_CODE (base) == PLUS) | |
8830 | { | |
6354dc9b | 8831 | /* The addend must be CONST_INT, or we would have dealt with it above. */ |
f9cc092a RE |
8832 | HOST_WIDE_INT hi, lo; |
8833 | ||
8834 | offset += INTVAL (XEXP (base, 1)); | |
8835 | base = XEXP (base, 0); | |
8836 | ||
6354dc9b | 8837 | /* Rework the address into a legal sequence of insns. */ |
f9cc092a RE |
8838 | /* Valid range for lo is -4095 -> 4095 */ |
8839 | lo = (offset >= 0 | |
8840 | ? (offset & 0xfff) | |
8841 | : -((-offset) & 0xfff)); | |
8842 | ||
8843 | /* Corner case, if lo is the max offset then we would be out of range | |
8844 | once we have added the additional 1 below, so bump the msb into the | |
8845 | pre-loading insn(s). */ | |
8846 | if (lo == 4095) | |
8847 | lo &= 0x7ff; | |
8848 | ||
30cf4896 KG |
8849 | hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) |
8850 | ^ (HOST_WIDE_INT) 0x80000000) | |
8851 | - (HOST_WIDE_INT) 0x80000000); | |
f9cc092a | 8852 | |
e6d29d15 | 8853 | gcc_assert (hi + lo == offset); |
f9cc092a RE |
8854 | |
8855 | if (hi != 0) | |
8856 | { | |
8857 | rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); | |
8858 | ||
8859 | /* Be careful not to destroy OUTVAL. */ | |
8860 | if (reg_overlap_mentioned_p (base_plus, outval)) | |
8861 | { | |
8862 | /* Updating base_plus might destroy outval, see if we | |
8863 | can swap the scratch and base_plus. */ | |
5895f793 | 8864 | if (!reg_overlap_mentioned_p (scratch, outval)) |
f9cc092a RE |
8865 | { |
8866 | rtx tmp = scratch; | |
8867 | scratch = base_plus; | |
8868 | base_plus = tmp; | |
8869 | } | |
8870 | else | |
8871 | { | |
8872 | rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); | |
8873 | ||
8874 | /* Be conservative and copy outval into scratch now, | |
8875 | this should only be necessary if outval is a | |
8876 | subreg of something larger than a word. */ | |
8877 | /* XXX Might this clobber base? I can't see how it | |
8878 | can, since scratch is known to overlap with | |
8879 | outval. */ | |
8880 | emit_insn (gen_movhi (scratch_hi, outval)); | |
8881 | outval = scratch_hi; | |
8882 | } | |
8883 | } | |
8884 | ||
8885 | /* Get the base address; addsi3 knows how to handle constants | |
6354dc9b | 8886 | that require more than one insn. */ |
f9cc092a RE |
8887 | emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); |
8888 | base = base_plus; | |
8889 | offset = lo; | |
8890 | } | |
8891 | } | |
af48348a | 8892 | |
b5cc037f RE |
8893 | if (BYTES_BIG_ENDIAN) |
8894 | { | |
f676971a | 8895 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
f9cc092a | 8896 | plus_constant (base, offset + 1)), |
5d5603e2 | 8897 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8898 | emit_insn (gen_lshrsi3 (scratch, |
8899 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8900 | GEN_INT (8))); |
f9cc092a | 8901 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8902 | gen_lowpart (QImode, scratch))); |
b5cc037f RE |
8903 | } |
8904 | else | |
8905 | { | |
f9cc092a | 8906 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), |
5d5603e2 | 8907 | gen_lowpart (QImode, outval))); |
f9cc092a RE |
8908 | emit_insn (gen_lshrsi3 (scratch, |
8909 | gen_rtx_SUBREG (SImode, outval, 0), | |
b5cc037f | 8910 | GEN_INT (8))); |
f9cc092a RE |
8911 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, |
8912 | plus_constant (base, offset + 1)), | |
5d5603e2 | 8913 | gen_lowpart (QImode, scratch))); |
b5cc037f | 8914 | } |
af48348a | 8915 | } |
866af8a9 JB |
8916 | |
8917 | /* Return true if a type must be passed in memory. For AAPCS, small aggregates | |
8918 | (padded to the size of a word) should be passed in a register. */ | |
8919 | ||
8920 | static bool | |
586de218 | 8921 | arm_must_pass_in_stack (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8922 | { |
8923 | if (TARGET_AAPCS_BASED) | |
8924 | return must_pass_in_stack_var_size (mode, type); | |
8925 | else | |
8926 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
8927 | } | |
8928 | ||
8929 | ||
8930 | /* For use by FUNCTION_ARG_PADDING (MODE, TYPE). | |
8931 | Return true if an argument passed on the stack should be padded upwards, | |
5a29b385 PB |
8932 | i.e. if the least-significant byte has useful data. |
8933 | For legacy APCS ABIs we use the default. For AAPCS based ABIs small | |
8934 | aggregate types are placed in the lowest memory address. */ | |
866af8a9 JB |
8935 | |
8936 | bool | |
586de218 | 8937 | arm_pad_arg_upward (enum machine_mode mode, const_tree type) |
866af8a9 JB |
8938 | { |
8939 | if (!TARGET_AAPCS_BASED) | |
5a29b385 | 8940 | return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; |
866af8a9 JB |
8941 | |
8942 | if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) | |
8943 | return false; | |
8944 | ||
8945 | return true; | |
8946 | } | |
8947 | ||
8948 | ||
8949 | /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). | |
8950 | For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant | |
8951 | byte of the register has useful data, and return the opposite if the | |
8952 | most significant byte does. | |
8953 | For AAPCS, small aggregates and small complex types are always padded | |
8954 | upwards. */ | |
8955 | ||
8956 | bool | |
8957 | arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, | |
8958 | tree type, int first ATTRIBUTE_UNUSED) | |
8959 | { | |
8960 | if (TARGET_AAPCS_BASED | |
8961 | && BYTES_BIG_ENDIAN | |
8962 | && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) | |
8963 | && int_size_in_bytes (type) <= 4) | |
8964 | return true; | |
8965 | ||
8966 | /* Otherwise, use default padding. */ | |
8967 | return !BYTES_BIG_ENDIAN; | |
8968 | } | |
8969 | ||
2b835d68 | 8970 | \f |
d5b7b3ae RE |
8971 | /* Print a symbolic form of X to the debug file, F. */ |
8972 | static void | |
e32bac5b | 8973 | arm_print_value (FILE *f, rtx x) |
d5b7b3ae RE |
8974 | { |
8975 | switch (GET_CODE (x)) | |
8976 | { | |
8977 | case CONST_INT: | |
8978 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); | |
8979 | return; | |
8980 | ||
8981 | case CONST_DOUBLE: | |
8982 | fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); | |
8983 | return; | |
8984 | ||
5a9335ef NC |
8985 | case CONST_VECTOR: |
8986 | { | |
8987 | int i; | |
8988 | ||
8989 | fprintf (f, "<"); | |
8990 | for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) | |
8991 | { | |
8992 | fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); | |
8993 | if (i < (CONST_VECTOR_NUNITS (x) - 1)) | |
8994 | fputc (',', f); | |
8995 | } | |
8996 | fprintf (f, ">"); | |
8997 | } | |
8998 | return; | |
8999 | ||
d5b7b3ae RE |
9000 | case CONST_STRING: |
9001 | fprintf (f, "\"%s\"", XSTR (x, 0)); | |
9002 | return; | |
9003 | ||
9004 | case SYMBOL_REF: | |
9005 | fprintf (f, "`%s'", XSTR (x, 0)); | |
9006 | return; | |
9007 | ||
9008 | case LABEL_REF: | |
9009 | fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); | |
9010 | return; | |
9011 | ||
9012 | case CONST: | |
9013 | arm_print_value (f, XEXP (x, 0)); | |
9014 | return; | |
9015 | ||
9016 | case PLUS: | |
9017 | arm_print_value (f, XEXP (x, 0)); | |
9018 | fprintf (f, "+"); | |
9019 | arm_print_value (f, XEXP (x, 1)); | |
9020 | return; | |
9021 | ||
9022 | case PC: | |
9023 | fprintf (f, "pc"); | |
9024 | return; | |
9025 | ||
9026 | default: | |
9027 | fprintf (f, "????"); | |
9028 | return; | |
9029 | } | |
9030 | } | |
9031 | \f | |
2b835d68 | 9032 | /* Routines for manipulation of the constant pool. */ |
2b835d68 | 9033 | |
949d79eb RE |
9034 | /* Arm instructions cannot load a large constant directly into a |
9035 | register; they have to come from a pc relative load. The constant | |
9036 | must therefore be placed in the addressable range of the pc | |
9037 | relative load. Depending on the precise pc relative load | |
9038 | instruction the range is somewhere between 256 bytes and 4k. This | |
9039 | means that we often have to dump a constant inside a function, and | |
2b835d68 RE |
9040 | generate code to branch around it. |
9041 | ||
949d79eb RE |
9042 | It is important to minimize this, since the branches will slow |
9043 | things down and make the code larger. | |
2b835d68 | 9044 | |
949d79eb RE |
9045 | Normally we can hide the table after an existing unconditional |
9046 | branch so that there is no interruption of the flow, but in the | |
9047 | worst case the code looks like this: | |
2b835d68 RE |
9048 | |
9049 | ldr rn, L1 | |
949d79eb | 9050 | ... |
2b835d68 RE |
9051 | b L2 |
9052 | align | |
9053 | L1: .long value | |
9054 | L2: | |
949d79eb | 9055 | ... |
2b835d68 | 9056 | |
2b835d68 | 9057 | ldr rn, L3 |
949d79eb | 9058 | ... |
2b835d68 RE |
9059 | b L4 |
9060 | align | |
2b835d68 RE |
9061 | L3: .long value |
9062 | L4: | |
949d79eb RE |
9063 | ... |
9064 | ||
9065 | We fix this by performing a scan after scheduling, which notices | |
9066 | which instructions need to have their operands fetched from the | |
9067 | constant table and builds the table. | |
9068 | ||
9069 | The algorithm starts by building a table of all the constants that | |
9070 | need fixing up and all the natural barriers in the function (places | |
9071 | where a constant table can be dropped without breaking the flow). | |
9072 | For each fixup we note how far the pc-relative replacement will be | |
9073 | able to reach and the offset of the instruction into the function. | |
9074 | ||
9075 | Having built the table we then group the fixes together to form | |
9076 | tables that are as large as possible (subject to addressing | |
9077 | constraints) and emit each table of constants after the last | |
9078 | barrier that is within range of all the instructions in the group. | |
9079 | If a group does not contain a barrier, then we forcibly create one | |
9080 | by inserting a jump instruction into the flow. Once the table has | |
9081 | been inserted, the insns are then modified to reference the | |
9082 | relevant entry in the pool. | |
9083 | ||
6354dc9b | 9084 | Possible enhancements to the algorithm (not implemented) are: |
949d79eb | 9085 | |
d5b7b3ae | 9086 | 1) For some processors and object formats, there may be benefit in |
949d79eb RE |
9087 | aligning the pools to the start of cache lines; this alignment |
9088 | would need to be taken into account when calculating addressability | |
6354dc9b | 9089 | of a pool. */ |
2b835d68 | 9090 | |
d5b7b3ae RE |
9091 | /* These typedefs are located at the start of this file, so that |
9092 | they can be used in the prototypes there. This comment is to | |
9093 | remind readers of that fact so that the following structures | |
9094 | can be understood more easily. | |
9095 | ||
9096 | typedef struct minipool_node Mnode; | |
9097 | typedef struct minipool_fixup Mfix; */ | |
9098 | ||
9099 | struct minipool_node | |
9100 | { | |
9101 | /* Doubly linked chain of entries. */ | |
9102 | Mnode * next; | |
9103 | Mnode * prev; | |
9104 | /* The maximum offset into the code that this entry can be placed. While | |
9105 | pushing fixes for forward references, all entries are sorted in order | |
9106 | of increasing max_address. */ | |
9107 | HOST_WIDE_INT max_address; | |
5519a4f9 | 9108 | /* Similarly for an entry inserted for a backwards ref. */ |
d5b7b3ae RE |
9109 | HOST_WIDE_INT min_address; |
9110 | /* The number of fixes referencing this entry. This can become zero | |
9111 | if we "unpush" an entry. In this case we ignore the entry when we | |
9112 | come to emit the code. */ | |
9113 | int refcount; | |
9114 | /* The offset from the start of the minipool. */ | |
9115 | HOST_WIDE_INT offset; | |
9116 | /* The value in table. */ | |
9117 | rtx value; | |
9118 | /* The mode of value. */ | |
9119 | enum machine_mode mode; | |
5a9335ef NC |
9120 | /* The size of the value. With iWMMXt enabled |
9121 | sizes > 4 also imply an alignment of 8-bytes. */ | |
d5b7b3ae RE |
9122 | int fix_size; |
9123 | }; | |
9124 | ||
9125 | struct minipool_fixup | |
2b835d68 | 9126 | { |
d5b7b3ae RE |
9127 | Mfix * next; |
9128 | rtx insn; | |
9129 | HOST_WIDE_INT address; | |
9130 | rtx * loc; | |
9131 | enum machine_mode mode; | |
9132 | int fix_size; | |
9133 | rtx value; | |
9134 | Mnode * minipool; | |
9135 | HOST_WIDE_INT forwards; | |
9136 | HOST_WIDE_INT backwards; | |
9137 | }; | |
2b835d68 | 9138 | |
d5b7b3ae RE |
9139 | /* Fixes less than a word need padding out to a word boundary. */ |
9140 | #define MINIPOOL_FIX_SIZE(mode) \ | |
9141 | (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) | |
2b835d68 | 9142 | |
d5b7b3ae RE |
9143 | static Mnode * minipool_vector_head; |
9144 | static Mnode * minipool_vector_tail; | |
9145 | static rtx minipool_vector_label; | |
34a9f549 | 9146 | static int minipool_pad; |
332072db | 9147 | |
d5b7b3ae RE |
9148 | /* The linked list of all minipool fixes required for this function. */ |
9149 | Mfix * minipool_fix_head; | |
9150 | Mfix * minipool_fix_tail; | |
9151 | /* The fix entry for the current minipool, once it has been placed. */ | |
9152 | Mfix * minipool_barrier; | |
9153 | ||
9154 | /* Determines if INSN is the start of a jump table. Returns the end | |
9155 | of the TABLE or NULL_RTX. */ | |
9156 | static rtx | |
e32bac5b | 9157 | is_jump_table (rtx insn) |
2b835d68 | 9158 | { |
d5b7b3ae | 9159 | rtx table; |
f676971a | 9160 | |
d5b7b3ae RE |
9161 | if (GET_CODE (insn) == JUMP_INSN |
9162 | && JUMP_LABEL (insn) != NULL | |
9163 | && ((table = next_real_insn (JUMP_LABEL (insn))) | |
9164 | == next_real_insn (insn)) | |
9165 | && table != NULL | |
9166 | && GET_CODE (table) == JUMP_INSN | |
9167 | && (GET_CODE (PATTERN (table)) == ADDR_VEC | |
9168 | || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) | |
9169 | return table; | |
9170 | ||
9171 | return NULL_RTX; | |
2b835d68 RE |
9172 | } |
9173 | ||
657d9449 RE |
9174 | #ifndef JUMP_TABLES_IN_TEXT_SECTION |
9175 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
9176 | #endif | |
9177 | ||
d5b7b3ae | 9178 | static HOST_WIDE_INT |
e32bac5b | 9179 | get_jump_table_size (rtx insn) |
2b835d68 | 9180 | { |
657d9449 RE |
9181 | /* ADDR_VECs only take room if read-only data does into the text |
9182 | section. */ | |
d6b5193b | 9183 | if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) |
657d9449 RE |
9184 | { |
9185 | rtx body = PATTERN (insn); | |
9186 | int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; | |
5b3e6663 PB |
9187 | HOST_WIDE_INT size; |
9188 | HOST_WIDE_INT modesize; | |
2b835d68 | 9189 | |
5b3e6663 PB |
9190 | modesize = GET_MODE_SIZE (GET_MODE (body)); |
9191 | size = modesize * XVECLEN (body, elt); | |
9192 | switch (modesize) | |
9193 | { | |
9194 | case 1: | |
88512ba0 | 9195 | /* Round up size of TBB table to a halfword boundary. */ |
5b3e6663 PB |
9196 | size = (size + 1) & ~(HOST_WIDE_INT)1; |
9197 | break; | |
9198 | case 2: | |
7a085dce | 9199 | /* No padding necessary for TBH. */ |
5b3e6663 PB |
9200 | break; |
9201 | case 4: | |
9202 | /* Add two bytes for alignment on Thumb. */ | |
9203 | if (TARGET_THUMB) | |
9204 | size += 2; | |
9205 | break; | |
9206 | default: | |
9207 | gcc_unreachable (); | |
9208 | } | |
9209 | return size; | |
657d9449 RE |
9210 | } |
9211 | ||
9212 | return 0; | |
d5b7b3ae | 9213 | } |
2b835d68 | 9214 | |
d5b7b3ae RE |
9215 | /* Move a minipool fix MP from its current location to before MAX_MP. |
9216 | If MAX_MP is NULL, then MP doesn't need moving, but the addressing | |
093354e0 | 9217 | constraints may need updating. */ |
d5b7b3ae | 9218 | static Mnode * |
e32bac5b RE |
9219 | move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, |
9220 | HOST_WIDE_INT max_address) | |
d5b7b3ae | 9221 | { |
e6d29d15 NS |
9222 | /* The code below assumes these are different. */ |
9223 | gcc_assert (mp != max_mp); | |
d5b7b3ae RE |
9224 | |
9225 | if (max_mp == NULL) | |
9226 | { | |
9227 | if (max_address < mp->max_address) | |
9228 | mp->max_address = max_address; | |
9229 | } | |
9230 | else | |
2b835d68 | 9231 | { |
d5b7b3ae RE |
9232 | if (max_address > max_mp->max_address - mp->fix_size) |
9233 | mp->max_address = max_mp->max_address - mp->fix_size; | |
9234 | else | |
9235 | mp->max_address = max_address; | |
2b835d68 | 9236 | |
d5b7b3ae RE |
9237 | /* Unlink MP from its current position. Since max_mp is non-null, |
9238 | mp->prev must be non-null. */ | |
9239 | mp->prev->next = mp->next; | |
9240 | if (mp->next != NULL) | |
9241 | mp->next->prev = mp->prev; | |
9242 | else | |
9243 | minipool_vector_tail = mp->prev; | |
2b835d68 | 9244 | |
d5b7b3ae RE |
9245 | /* Re-insert it before MAX_MP. */ |
9246 | mp->next = max_mp; | |
9247 | mp->prev = max_mp->prev; | |
9248 | max_mp->prev = mp; | |
f676971a | 9249 | |
d5b7b3ae RE |
9250 | if (mp->prev != NULL) |
9251 | mp->prev->next = mp; | |
9252 | else | |
9253 | minipool_vector_head = mp; | |
9254 | } | |
2b835d68 | 9255 | |
d5b7b3ae RE |
9256 | /* Save the new entry. */ |
9257 | max_mp = mp; | |
9258 | ||
d6a7951f | 9259 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
9260 | required. */ |
9261 | while (mp->prev != NULL | |
9262 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
9263 | { | |
9264 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
9265 | mp = mp->prev; | |
2b835d68 RE |
9266 | } |
9267 | ||
d5b7b3ae | 9268 | return max_mp; |
2b835d68 RE |
9269 | } |
9270 | ||
d5b7b3ae RE |
9271 | /* Add a constant to the minipool for a forward reference. Returns the |
9272 | node added or NULL if the constant will not fit in this pool. */ | |
9273 | static Mnode * | |
e32bac5b | 9274 | add_minipool_forward_ref (Mfix *fix) |
d5b7b3ae RE |
9275 | { |
9276 | /* If set, max_mp is the first pool_entry that has a lower | |
9277 | constraint than the one we are trying to add. */ | |
9278 | Mnode * max_mp = NULL; | |
34a9f549 | 9279 | HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; |
d5b7b3ae | 9280 | Mnode * mp; |
f676971a | 9281 | |
7a7017bc PB |
9282 | /* If the minipool starts before the end of FIX->INSN then this FIX |
9283 | can not be placed into the current pool. Furthermore, adding the | |
9284 | new constant pool entry may cause the pool to start FIX_SIZE bytes | |
9285 | earlier. */ | |
d5b7b3ae | 9286 | if (minipool_vector_head && |
7a7017bc PB |
9287 | (fix->address + get_attr_length (fix->insn) |
9288 | >= minipool_vector_head->max_address - fix->fix_size)) | |
d5b7b3ae | 9289 | return NULL; |
2b835d68 | 9290 | |
d5b7b3ae RE |
9291 | /* Scan the pool to see if a constant with the same value has |
9292 | already been added. While we are doing this, also note the | |
9293 | location where we must insert the constant if it doesn't already | |
9294 | exist. */ | |
9295 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9296 | { | |
9297 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
9298 | && fix->mode == mp->mode | |
9299 | && (GET_CODE (fix->value) != CODE_LABEL | |
9300 | || (CODE_LABEL_NUMBER (fix->value) | |
9301 | == CODE_LABEL_NUMBER (mp->value))) | |
9302 | && rtx_equal_p (fix->value, mp->value)) | |
9303 | { | |
9304 | /* More than one fix references this entry. */ | |
9305 | mp->refcount++; | |
9306 | return move_minipool_fix_forward_ref (mp, max_mp, max_address); | |
9307 | } | |
9308 | ||
9309 | /* Note the insertion point if necessary. */ | |
9310 | if (max_mp == NULL | |
9311 | && mp->max_address > max_address) | |
9312 | max_mp = mp; | |
5a9335ef NC |
9313 | |
9314 | /* If we are inserting an 8-bytes aligned quantity and | |
9315 | we have not already found an insertion point, then | |
9316 | make sure that all such 8-byte aligned quantities are | |
9317 | placed at the start of the pool. */ | |
5848830f | 9318 | if (ARM_DOUBLEWORD_ALIGN |
5a9335ef | 9319 | && max_mp == NULL |
88f77cba JB |
9320 | && fix->fix_size >= 8 |
9321 | && mp->fix_size < 8) | |
5a9335ef NC |
9322 | { |
9323 | max_mp = mp; | |
9324 | max_address = mp->max_address; | |
9325 | } | |
d5b7b3ae RE |
9326 | } |
9327 | ||
9328 | /* The value is not currently in the minipool, so we need to create | |
9329 | a new entry for it. If MAX_MP is NULL, the entry will be put on | |
9330 | the end of the list since the placement is less constrained than | |
9331 | any existing entry. Otherwise, we insert the new fix before | |
6bc82793 | 9332 | MAX_MP and, if necessary, adjust the constraints on the other |
d5b7b3ae | 9333 | entries. */ |
5ed6ace5 | 9334 | mp = XNEW (Mnode); |
d5b7b3ae RE |
9335 | mp->fix_size = fix->fix_size; |
9336 | mp->mode = fix->mode; | |
9337 | mp->value = fix->value; | |
9338 | mp->refcount = 1; | |
9339 | /* Not yet required for a backwards ref. */ | |
9340 | mp->min_address = -65536; | |
9341 | ||
9342 | if (max_mp == NULL) | |
9343 | { | |
9344 | mp->max_address = max_address; | |
9345 | mp->next = NULL; | |
9346 | mp->prev = minipool_vector_tail; | |
9347 | ||
9348 | if (mp->prev == NULL) | |
9349 | { | |
9350 | minipool_vector_head = mp; | |
9351 | minipool_vector_label = gen_label_rtx (); | |
7551cbc7 | 9352 | } |
2b835d68 | 9353 | else |
d5b7b3ae | 9354 | mp->prev->next = mp; |
2b835d68 | 9355 | |
d5b7b3ae RE |
9356 | minipool_vector_tail = mp; |
9357 | } | |
9358 | else | |
9359 | { | |
9360 | if (max_address > max_mp->max_address - mp->fix_size) | |
9361 | mp->max_address = max_mp->max_address - mp->fix_size; | |
9362 | else | |
9363 | mp->max_address = max_address; | |
9364 | ||
9365 | mp->next = max_mp; | |
9366 | mp->prev = max_mp->prev; | |
9367 | max_mp->prev = mp; | |
9368 | if (mp->prev != NULL) | |
9369 | mp->prev->next = mp; | |
9370 | else | |
9371 | minipool_vector_head = mp; | |
9372 | } | |
9373 | ||
9374 | /* Save the new entry. */ | |
9375 | max_mp = mp; | |
9376 | ||
d6a7951f | 9377 | /* Scan over the preceding entries and adjust their addresses as |
d5b7b3ae RE |
9378 | required. */ |
9379 | while (mp->prev != NULL | |
9380 | && mp->prev->max_address > mp->max_address - mp->prev->fix_size) | |
9381 | { | |
9382 | mp->prev->max_address = mp->max_address - mp->prev->fix_size; | |
9383 | mp = mp->prev; | |
2b835d68 RE |
9384 | } |
9385 | ||
d5b7b3ae RE |
9386 | return max_mp; |
9387 | } | |
9388 | ||
9389 | static Mnode * | |
e32bac5b RE |
9390 | move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, |
9391 | HOST_WIDE_INT min_address) | |
d5b7b3ae RE |
9392 | { |
9393 | HOST_WIDE_INT offset; | |
9394 | ||
e6d29d15 NS |
9395 | /* The code below assumes these are different. */ |
9396 | gcc_assert (mp != min_mp); | |
d5b7b3ae RE |
9397 | |
9398 | if (min_mp == NULL) | |
2b835d68 | 9399 | { |
d5b7b3ae RE |
9400 | if (min_address > mp->min_address) |
9401 | mp->min_address = min_address; | |
9402 | } | |
9403 | else | |
9404 | { | |
9405 | /* We will adjust this below if it is too loose. */ | |
9406 | mp->min_address = min_address; | |
9407 | ||
9408 | /* Unlink MP from its current position. Since min_mp is non-null, | |
9409 | mp->next must be non-null. */ | |
9410 | mp->next->prev = mp->prev; | |
9411 | if (mp->prev != NULL) | |
9412 | mp->prev->next = mp->next; | |
9413 | else | |
9414 | minipool_vector_head = mp->next; | |
9415 | ||
9416 | /* Reinsert it after MIN_MP. */ | |
9417 | mp->prev = min_mp; | |
9418 | mp->next = min_mp->next; | |
9419 | min_mp->next = mp; | |
9420 | if (mp->next != NULL) | |
9421 | mp->next->prev = mp; | |
2b835d68 | 9422 | else |
d5b7b3ae RE |
9423 | minipool_vector_tail = mp; |
9424 | } | |
9425 | ||
9426 | min_mp = mp; | |
9427 | ||
9428 | offset = 0; | |
9429 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9430 | { | |
9431 | mp->offset = offset; | |
9432 | if (mp->refcount > 0) | |
9433 | offset += mp->fix_size; | |
9434 | ||
9435 | if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) | |
9436 | mp->next->min_address = mp->min_address + mp->fix_size; | |
9437 | } | |
9438 | ||
9439 | return min_mp; | |
f676971a | 9440 | } |
d5b7b3ae RE |
9441 | |
9442 | /* Add a constant to the minipool for a backward reference. Returns the | |
f676971a | 9443 | node added or NULL if the constant will not fit in this pool. |
d5b7b3ae RE |
9444 | |
9445 | Note that the code for insertion for a backwards reference can be | |
9446 | somewhat confusing because the calculated offsets for each fix do | |
9447 | not take into account the size of the pool (which is still under | |
9448 | construction. */ | |
9449 | static Mnode * | |
e32bac5b | 9450 | add_minipool_backward_ref (Mfix *fix) |
d5b7b3ae RE |
9451 | { |
9452 | /* If set, min_mp is the last pool_entry that has a lower constraint | |
9453 | than the one we are trying to add. */ | |
e32bac5b | 9454 | Mnode *min_mp = NULL; |
d5b7b3ae RE |
9455 | /* This can be negative, since it is only a constraint. */ |
9456 | HOST_WIDE_INT min_address = fix->address - fix->backwards; | |
e32bac5b | 9457 | Mnode *mp; |
d5b7b3ae RE |
9458 | |
9459 | /* If we can't reach the current pool from this insn, or if we can't | |
9460 | insert this entry at the end of the pool without pushing other | |
9461 | fixes out of range, then we don't try. This ensures that we | |
9462 | can't fail later on. */ | |
9463 | if (min_address >= minipool_barrier->address | |
9464 | || (minipool_vector_tail->min_address + fix->fix_size | |
9465 | >= minipool_barrier->address)) | |
9466 | return NULL; | |
9467 | ||
9468 | /* Scan the pool to see if a constant with the same value has | |
9469 | already been added. While we are doing this, also note the | |
9470 | location where we must insert the constant if it doesn't already | |
9471 | exist. */ | |
9472 | for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) | |
9473 | { | |
9474 | if (GET_CODE (fix->value) == GET_CODE (mp->value) | |
9475 | && fix->mode == mp->mode | |
9476 | && (GET_CODE (fix->value) != CODE_LABEL | |
9477 | || (CODE_LABEL_NUMBER (fix->value) | |
9478 | == CODE_LABEL_NUMBER (mp->value))) | |
9479 | && rtx_equal_p (fix->value, mp->value) | |
9480 | /* Check that there is enough slack to move this entry to the | |
9481 | end of the table (this is conservative). */ | |
f676971a EC |
9482 | && (mp->max_address |
9483 | > (minipool_barrier->address | |
d5b7b3ae RE |
9484 | + minipool_vector_tail->offset |
9485 | + minipool_vector_tail->fix_size))) | |
9486 | { | |
9487 | mp->refcount++; | |
9488 | return move_minipool_fix_backward_ref (mp, min_mp, min_address); | |
9489 | } | |
9490 | ||
9491 | if (min_mp != NULL) | |
9492 | mp->min_address += fix->fix_size; | |
9493 | else | |
9494 | { | |
9495 | /* Note the insertion point if necessary. */ | |
9496 | if (mp->min_address < min_address) | |
5a9335ef NC |
9497 | { |
9498 | /* For now, we do not allow the insertion of 8-byte alignment | |
9499 | requiring nodes anywhere but at the start of the pool. */ | |
5848830f | 9500 | if (ARM_DOUBLEWORD_ALIGN |
88f77cba | 9501 | && fix->fix_size >= 8 && mp->fix_size < 8) |
5a9335ef NC |
9502 | return NULL; |
9503 | else | |
9504 | min_mp = mp; | |
9505 | } | |
d5b7b3ae RE |
9506 | else if (mp->max_address |
9507 | < minipool_barrier->address + mp->offset + fix->fix_size) | |
9508 | { | |
9509 | /* Inserting before this entry would push the fix beyond | |
9510 | its maximum address (which can happen if we have | |
9511 | re-located a forwards fix); force the new fix to come | |
9512 | after it. */ | |
853ff9e2 JM |
9513 | if (ARM_DOUBLEWORD_ALIGN |
9514 | && fix->fix_size >= 8 && mp->fix_size < 8) | |
9515 | return NULL; | |
9516 | else | |
9517 | { | |
9518 | min_mp = mp; | |
9519 | min_address = mp->min_address + fix->fix_size; | |
9520 | } | |
d5b7b3ae | 9521 | } |
853ff9e2 JM |
9522 | /* Do not insert a non-8-byte aligned quantity before 8-byte |
9523 | aligned quantities. */ | |
5848830f | 9524 | else if (ARM_DOUBLEWORD_ALIGN |
853ff9e2 JM |
9525 | && fix->fix_size < 8 |
9526 | && mp->fix_size >= 8) | |
5a9335ef NC |
9527 | { |
9528 | min_mp = mp; | |
9529 | min_address = mp->min_address + fix->fix_size; | |
9530 | } | |
d5b7b3ae RE |
9531 | } |
9532 | } | |
9533 | ||
9534 | /* We need to create a new entry. */ | |
5ed6ace5 | 9535 | mp = XNEW (Mnode); |
d5b7b3ae RE |
9536 | mp->fix_size = fix->fix_size; |
9537 | mp->mode = fix->mode; | |
9538 | mp->value = fix->value; | |
9539 | mp->refcount = 1; | |
9540 | mp->max_address = minipool_barrier->address + 65536; | |
9541 | ||
9542 | mp->min_address = min_address; | |
9543 | ||
9544 | if (min_mp == NULL) | |
9545 | { | |
9546 | mp->prev = NULL; | |
9547 | mp->next = minipool_vector_head; | |
9548 | ||
9549 | if (mp->next == NULL) | |
9550 | { | |
9551 | minipool_vector_tail = mp; | |
9552 | minipool_vector_label = gen_label_rtx (); | |
9553 | } | |
9554 | else | |
9555 | mp->next->prev = mp; | |
9556 | ||
9557 | minipool_vector_head = mp; | |
9558 | } | |
9559 | else | |
9560 | { | |
9561 | mp->next = min_mp->next; | |
9562 | mp->prev = min_mp; | |
9563 | min_mp->next = mp; | |
f676971a | 9564 | |
d5b7b3ae RE |
9565 | if (mp->next != NULL) |
9566 | mp->next->prev = mp; | |
9567 | else | |
9568 | minipool_vector_tail = mp; | |
9569 | } | |
9570 | ||
9571 | /* Save the new entry. */ | |
9572 | min_mp = mp; | |
9573 | ||
9574 | if (mp->prev) | |
9575 | mp = mp->prev; | |
9576 | else | |
9577 | mp->offset = 0; | |
9578 | ||
9579 | /* Scan over the following entries and adjust their offsets. */ | |
9580 | while (mp->next != NULL) | |
9581 | { | |
9582 | if (mp->next->min_address < mp->min_address + mp->fix_size) | |
9583 | mp->next->min_address = mp->min_address + mp->fix_size; | |
9584 | ||
9585 | if (mp->refcount) | |
9586 | mp->next->offset = mp->offset + mp->fix_size; | |
9587 | else | |
9588 | mp->next->offset = mp->offset; | |
9589 | ||
9590 | mp = mp->next; | |
9591 | } | |
9592 | ||
9593 | return min_mp; | |
9594 | } | |
9595 | ||
9596 | static void | |
e32bac5b | 9597 | assign_minipool_offsets (Mfix *barrier) |
d5b7b3ae RE |
9598 | { |
9599 | HOST_WIDE_INT offset = 0; | |
e32bac5b | 9600 | Mnode *mp; |
d5b7b3ae RE |
9601 | |
9602 | minipool_barrier = barrier; | |
9603 | ||
9604 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) | |
9605 | { | |
9606 | mp->offset = offset; | |
f676971a | 9607 | |
d5b7b3ae RE |
9608 | if (mp->refcount > 0) |
9609 | offset += mp->fix_size; | |
9610 | } | |
9611 | } | |
9612 | ||
9613 | /* Output the literal table */ | |
9614 | static void | |
e32bac5b | 9615 | dump_minipool (rtx scan) |
d5b7b3ae | 9616 | { |
5a9335ef NC |
9617 | Mnode * mp; |
9618 | Mnode * nmp; | |
9619 | int align64 = 0; | |
9620 | ||
5848830f | 9621 | if (ARM_DOUBLEWORD_ALIGN) |
5a9335ef | 9622 | for (mp = minipool_vector_head; mp != NULL; mp = mp->next) |
88f77cba | 9623 | if (mp->refcount > 0 && mp->fix_size >= 8) |
5a9335ef NC |
9624 | { |
9625 | align64 = 1; | |
9626 | break; | |
9627 | } | |
d5b7b3ae | 9628 | |
c263766c RH |
9629 | if (dump_file) |
9630 | fprintf (dump_file, | |
5a9335ef NC |
9631 | ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", |
9632 | INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); | |
d5b7b3ae RE |
9633 | |
9634 | scan = emit_label_after (gen_label_rtx (), scan); | |
5a9335ef | 9635 | scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); |
d5b7b3ae RE |
9636 | scan = emit_label_after (minipool_vector_label, scan); |
9637 | ||
9638 | for (mp = minipool_vector_head; mp != NULL; mp = nmp) | |
9639 | { | |
9640 | if (mp->refcount > 0) | |
9641 | { | |
c263766c | 9642 | if (dump_file) |
d5b7b3ae | 9643 | { |
f676971a | 9644 | fprintf (dump_file, |
d5b7b3ae RE |
9645 | ";; Offset %u, min %ld, max %ld ", |
9646 | (unsigned) mp->offset, (unsigned long) mp->min_address, | |
9647 | (unsigned long) mp->max_address); | |
c263766c RH |
9648 | arm_print_value (dump_file, mp->value); |
9649 | fputc ('\n', dump_file); | |
d5b7b3ae RE |
9650 | } |
9651 | ||
9652 | switch (mp->fix_size) | |
9653 | { | |
9654 | #ifdef HAVE_consttable_1 | |
9655 | case 1: | |
9656 | scan = emit_insn_after (gen_consttable_1 (mp->value), scan); | |
9657 | break; | |
9658 | ||
9659 | #endif | |
9660 | #ifdef HAVE_consttable_2 | |
9661 | case 2: | |
9662 | scan = emit_insn_after (gen_consttable_2 (mp->value), scan); | |
9663 | break; | |
9664 | ||
9665 | #endif | |
9666 | #ifdef HAVE_consttable_4 | |
9667 | case 4: | |
9668 | scan = emit_insn_after (gen_consttable_4 (mp->value), scan); | |
9669 | break; | |
9670 | ||
9671 | #endif | |
9672 | #ifdef HAVE_consttable_8 | |
9673 | case 8: | |
9674 | scan = emit_insn_after (gen_consttable_8 (mp->value), scan); | |
9675 | break; | |
9676 | ||
88f77cba JB |
9677 | #endif |
9678 | #ifdef HAVE_consttable_16 | |
9679 | case 16: | |
9680 | scan = emit_insn_after (gen_consttable_16 (mp->value), scan); | |
9681 | break; | |
9682 | ||
d5b7b3ae RE |
9683 | #endif |
9684 | default: | |
e6d29d15 | 9685 | gcc_unreachable (); |
d5b7b3ae RE |
9686 | } |
9687 | } | |
9688 | ||
9689 | nmp = mp->next; | |
9690 | free (mp); | |
2b835d68 RE |
9691 | } |
9692 | ||
d5b7b3ae RE |
9693 | minipool_vector_head = minipool_vector_tail = NULL; |
9694 | scan = emit_insn_after (gen_consttable_end (), scan); | |
9695 | scan = emit_barrier_after (scan); | |
2b835d68 RE |
9696 | } |
9697 | ||
d5b7b3ae RE |
9698 | /* Return the cost of forcibly inserting a barrier after INSN. */ |
9699 | static int | |
e32bac5b | 9700 | arm_barrier_cost (rtx insn) |
949d79eb | 9701 | { |
d5b7b3ae RE |
9702 | /* Basing the location of the pool on the loop depth is preferable, |
9703 | but at the moment, the basic block information seems to be | |
9704 | corrupt by this stage of the compilation. */ | |
9705 | int base_cost = 50; | |
9706 | rtx next = next_nonnote_insn (insn); | |
9707 | ||
9708 | if (next != NULL && GET_CODE (next) == CODE_LABEL) | |
9709 | base_cost -= 20; | |
9710 | ||
9711 | switch (GET_CODE (insn)) | |
9712 | { | |
9713 | case CODE_LABEL: | |
9714 | /* It will always be better to place the table before the label, rather | |
9715 | than after it. */ | |
f676971a | 9716 | return 50; |
949d79eb | 9717 | |
d5b7b3ae RE |
9718 | case INSN: |
9719 | case CALL_INSN: | |
9720 | return base_cost; | |
9721 | ||
9722 | case JUMP_INSN: | |
9723 | return base_cost - 10; | |
9724 | ||
9725 | default: | |
9726 | return base_cost + 10; | |
9727 | } | |
9728 | } | |
9729 | ||
9730 | /* Find the best place in the insn stream in the range | |
9731 | (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. | |
9732 | Create the barrier by inserting a jump and add a new fix entry for | |
9733 | it. */ | |
9734 | static Mfix * | |
e32bac5b | 9735 | create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) |
d5b7b3ae RE |
9736 | { |
9737 | HOST_WIDE_INT count = 0; | |
9738 | rtx barrier; | |
9739 | rtx from = fix->insn; | |
7a7017bc PB |
9740 | /* The instruction after which we will insert the jump. */ |
9741 | rtx selected = NULL; | |
d5b7b3ae | 9742 | int selected_cost; |
7a7017bc | 9743 | /* The address at which the jump instruction will be placed. */ |
d5b7b3ae RE |
9744 | HOST_WIDE_INT selected_address; |
9745 | Mfix * new_fix; | |
9746 | HOST_WIDE_INT max_count = max_address - fix->address; | |
9747 | rtx label = gen_label_rtx (); | |
9748 | ||
9749 | selected_cost = arm_barrier_cost (from); | |
9750 | selected_address = fix->address; | |
9751 | ||
9752 | while (from && count < max_count) | |
9753 | { | |
9754 | rtx tmp; | |
9755 | int new_cost; | |
9756 | ||
9757 | /* This code shouldn't have been called if there was a natural barrier | |
9758 | within range. */ | |
e6d29d15 | 9759 | gcc_assert (GET_CODE (from) != BARRIER); |
d5b7b3ae RE |
9760 | |
9761 | /* Count the length of this insn. */ | |
9762 | count += get_attr_length (from); | |
9763 | ||
9764 | /* If there is a jump table, add its length. */ | |
9765 | tmp = is_jump_table (from); | |
9766 | if (tmp != NULL) | |
9767 | { | |
9768 | count += get_jump_table_size (tmp); | |
9769 | ||
9770 | /* Jump tables aren't in a basic block, so base the cost on | |
9771 | the dispatch insn. If we select this location, we will | |
9772 | still put the pool after the table. */ | |
9773 | new_cost = arm_barrier_cost (from); | |
9774 | ||
7a7017bc PB |
9775 | if (count < max_count |
9776 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9777 | { |
9778 | selected = tmp; | |
9779 | selected_cost = new_cost; | |
9780 | selected_address = fix->address + count; | |
9781 | } | |
9782 | ||
9783 | /* Continue after the dispatch table. */ | |
9784 | from = NEXT_INSN (tmp); | |
9785 | continue; | |
9786 | } | |
9787 | ||
9788 | new_cost = arm_barrier_cost (from); | |
f676971a | 9789 | |
7a7017bc PB |
9790 | if (count < max_count |
9791 | && (!selected || new_cost <= selected_cost)) | |
d5b7b3ae RE |
9792 | { |
9793 | selected = from; | |
9794 | selected_cost = new_cost; | |
9795 | selected_address = fix->address + count; | |
9796 | } | |
9797 | ||
9798 | from = NEXT_INSN (from); | |
9799 | } | |
9800 | ||
7a7017bc PB |
9801 | /* Make sure that we found a place to insert the jump. */ |
9802 | gcc_assert (selected); | |
9803 | ||
d5b7b3ae RE |
9804 | /* Create a new JUMP_INSN that branches around a barrier. */ |
9805 | from = emit_jump_insn_after (gen_jump (label), selected); | |
9806 | JUMP_LABEL (from) = label; | |
9807 | barrier = emit_barrier_after (from); | |
9808 | emit_label_after (label, barrier); | |
9809 | ||
9810 | /* Create a minipool barrier entry for the new barrier. */ | |
c7319d87 | 9811 | new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); |
d5b7b3ae RE |
9812 | new_fix->insn = barrier; |
9813 | new_fix->address = selected_address; | |
9814 | new_fix->next = fix->next; | |
9815 | fix->next = new_fix; | |
9816 | ||
9817 | return new_fix; | |
9818 | } | |
9819 | ||
9820 | /* Record that there is a natural barrier in the insn stream at | |
9821 | ADDRESS. */ | |
949d79eb | 9822 | static void |
e32bac5b | 9823 | push_minipool_barrier (rtx insn, HOST_WIDE_INT address) |
2b835d68 | 9824 | { |
c7319d87 | 9825 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
ad076f4e | 9826 | |
949d79eb RE |
9827 | fix->insn = insn; |
9828 | fix->address = address; | |
2b835d68 | 9829 | |
949d79eb RE |
9830 | fix->next = NULL; |
9831 | if (minipool_fix_head != NULL) | |
9832 | minipool_fix_tail->next = fix; | |
9833 | else | |
9834 | minipool_fix_head = fix; | |
9835 | ||
9836 | minipool_fix_tail = fix; | |
9837 | } | |
2b835d68 | 9838 | |
d5b7b3ae RE |
9839 | /* Record INSN, which will need fixing up to load a value from the |
9840 | minipool. ADDRESS is the offset of the insn since the start of the | |
9841 | function; LOC is a pointer to the part of the insn which requires | |
9842 | fixing; VALUE is the constant that must be loaded, which is of type | |
9843 | MODE. */ | |
949d79eb | 9844 | static void |
e32bac5b RE |
9845 | push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, |
9846 | enum machine_mode mode, rtx value) | |
949d79eb | 9847 | { |
c7319d87 | 9848 | Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); |
949d79eb | 9849 | |
949d79eb RE |
9850 | fix->insn = insn; |
9851 | fix->address = address; | |
9852 | fix->loc = loc; | |
9853 | fix->mode = mode; | |
d5b7b3ae | 9854 | fix->fix_size = MINIPOOL_FIX_SIZE (mode); |
949d79eb | 9855 | fix->value = value; |
d5b7b3ae RE |
9856 | fix->forwards = get_attr_pool_range (insn); |
9857 | fix->backwards = get_attr_neg_pool_range (insn); | |
9858 | fix->minipool = NULL; | |
949d79eb RE |
9859 | |
9860 | /* If an insn doesn't have a range defined for it, then it isn't | |
e6d29d15 | 9861 | expecting to be reworked by this code. Better to stop now than |
949d79eb | 9862 | to generate duff assembly code. */ |
e6d29d15 | 9863 | gcc_assert (fix->forwards || fix->backwards); |
949d79eb | 9864 | |
34a9f549 PB |
9865 | /* If an entry requires 8-byte alignment then assume all constant pools |
9866 | require 4 bytes of padding. Trying to do this later on a per-pool | |
917f1b7e | 9867 | basis is awkward because existing pool entries have to be modified. */ |
88f77cba | 9868 | if (ARM_DOUBLEWORD_ALIGN && fix->fix_size >= 8) |
34a9f549 | 9869 | minipool_pad = 4; |
5a9335ef | 9870 | |
c263766c | 9871 | if (dump_file) |
d5b7b3ae | 9872 | { |
c263766c | 9873 | fprintf (dump_file, |
d5b7b3ae RE |
9874 | ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", |
9875 | GET_MODE_NAME (mode), | |
f676971a | 9876 | INSN_UID (insn), (unsigned long) address, |
d5b7b3ae | 9877 | -1 * (long)fix->backwards, (long)fix->forwards); |
c263766c RH |
9878 | arm_print_value (dump_file, fix->value); |
9879 | fprintf (dump_file, "\n"); | |
d5b7b3ae RE |
9880 | } |
9881 | ||
6354dc9b | 9882 | /* Add it to the chain of fixes. */ |
949d79eb | 9883 | fix->next = NULL; |
f676971a | 9884 | |
949d79eb RE |
9885 | if (minipool_fix_head != NULL) |
9886 | minipool_fix_tail->next = fix; | |
9887 | else | |
9888 | minipool_fix_head = fix; | |
9889 | ||
9890 | minipool_fix_tail = fix; | |
9891 | } | |
9892 | ||
9b901d50 | 9893 | /* Return the cost of synthesizing a 64-bit constant VAL inline. |
2075b05d RE |
9894 | Returns the number of insns needed, or 99 if we don't know how to |
9895 | do it. */ | |
9896 | int | |
9897 | arm_const_double_inline_cost (rtx val) | |
b9e8bfda | 9898 | { |
9b901d50 RE |
9899 | rtx lowpart, highpart; |
9900 | enum machine_mode mode; | |
e0b92319 | 9901 | |
9b901d50 | 9902 | mode = GET_MODE (val); |
b9e8bfda | 9903 | |
9b901d50 RE |
9904 | if (mode == VOIDmode) |
9905 | mode = DImode; | |
9906 | ||
9907 | gcc_assert (GET_MODE_SIZE (mode) == 8); | |
e0b92319 | 9908 | |
9b901d50 RE |
9909 | lowpart = gen_lowpart (SImode, val); |
9910 | highpart = gen_highpart_mode (SImode, mode, val); | |
e0b92319 | 9911 | |
9b901d50 RE |
9912 | gcc_assert (GET_CODE (lowpart) == CONST_INT); |
9913 | gcc_assert (GET_CODE (highpart) == CONST_INT); | |
9914 | ||
9915 | return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), | |
2075b05d | 9916 | NULL_RTX, NULL_RTX, 0, 0) |
9b901d50 | 9917 | + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), |
2075b05d RE |
9918 | NULL_RTX, NULL_RTX, 0, 0)); |
9919 | } | |
9920 | ||
f3b569ca | 9921 | /* Return true if it is worthwhile to split a 64-bit constant into two |
b4a58f80 RE |
9922 | 32-bit operations. This is the case if optimizing for size, or |
9923 | if we have load delay slots, or if one 32-bit part can be done with | |
9924 | a single data operation. */ | |
9925 | bool | |
9926 | arm_const_double_by_parts (rtx val) | |
9927 | { | |
9928 | enum machine_mode mode = GET_MODE (val); | |
9929 | rtx part; | |
9930 | ||
9931 | if (optimize_size || arm_ld_sched) | |
9932 | return true; | |
9933 | ||
9934 | if (mode == VOIDmode) | |
9935 | mode = DImode; | |
e0b92319 | 9936 | |
b4a58f80 | 9937 | part = gen_highpart_mode (SImode, mode, val); |
e0b92319 | 9938 | |
b4a58f80 | 9939 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9940 | |
b4a58f80 RE |
9941 | if (const_ok_for_arm (INTVAL (part)) |
9942 | || const_ok_for_arm (~INTVAL (part))) | |
9943 | return true; | |
e0b92319 | 9944 | |
b4a58f80 | 9945 | part = gen_lowpart (SImode, val); |
e0b92319 | 9946 | |
b4a58f80 | 9947 | gcc_assert (GET_CODE (part) == CONST_INT); |
e0b92319 | 9948 | |
b4a58f80 RE |
9949 | if (const_ok_for_arm (INTVAL (part)) |
9950 | || const_ok_for_arm (~INTVAL (part))) | |
9951 | return true; | |
e0b92319 | 9952 | |
b4a58f80 RE |
9953 | return false; |
9954 | } | |
9955 | ||
f0375c66 NC |
9956 | /* Scan INSN and note any of its operands that need fixing. |
9957 | If DO_PUSHES is false we do not actually push any of the fixups | |
9b901d50 | 9958 | needed. The function returns TRUE if any fixups were needed/pushed. |
f0375c66 NC |
9959 | This is used by arm_memory_load_p() which needs to know about loads |
9960 | of constants that will be converted into minipool loads. */ | |
f0375c66 | 9961 | static bool |
e32bac5b | 9962 | note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) |
949d79eb | 9963 | { |
f0375c66 | 9964 | bool result = false; |
949d79eb RE |
9965 | int opno; |
9966 | ||
d5b7b3ae | 9967 | extract_insn (insn); |
949d79eb | 9968 | |
5895f793 | 9969 | if (!constrain_operands (1)) |
949d79eb RE |
9970 | fatal_insn_not_found (insn); |
9971 | ||
8c2a5582 RE |
9972 | if (recog_data.n_alternatives == 0) |
9973 | return false; | |
9974 | ||
9b901d50 RE |
9975 | /* Fill in recog_op_alt with information about the constraints of |
9976 | this insn. */ | |
949d79eb RE |
9977 | preprocess_constraints (); |
9978 | ||
1ccbefce | 9979 | for (opno = 0; opno < recog_data.n_operands; opno++) |
949d79eb | 9980 | { |
6354dc9b | 9981 | /* Things we need to fix can only occur in inputs. */ |
36ab44c7 | 9982 | if (recog_data.operand_type[opno] != OP_IN) |
949d79eb RE |
9983 | continue; |
9984 | ||
9985 | /* If this alternative is a memory reference, then any mention | |
9986 | of constants in this alternative is really to fool reload | |
9987 | into allowing us to accept one there. We need to fix them up | |
9988 | now so that we output the right code. */ | |
9989 | if (recog_op_alt[opno][which_alternative].memory_ok) | |
9990 | { | |
1ccbefce | 9991 | rtx op = recog_data.operand[opno]; |
949d79eb | 9992 | |
9b901d50 | 9993 | if (CONSTANT_P (op)) |
f0375c66 NC |
9994 | { |
9995 | if (do_pushes) | |
9996 | push_minipool_fix (insn, address, recog_data.operand_loc[opno], | |
9997 | recog_data.operand_mode[opno], op); | |
9998 | result = true; | |
9999 | } | |
d5b7b3ae | 10000 | else if (GET_CODE (op) == MEM |
949d79eb RE |
10001 | && GET_CODE (XEXP (op, 0)) == SYMBOL_REF |
10002 | && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) | |
f0375c66 NC |
10003 | { |
10004 | if (do_pushes) | |
244b1afb RE |
10005 | { |
10006 | rtx cop = avoid_constant_pool_reference (op); | |
10007 | ||
10008 | /* Casting the address of something to a mode narrower | |
10009 | than a word can cause avoid_constant_pool_reference() | |
10010 | to return the pool reference itself. That's no good to | |
f676971a | 10011 | us here. Lets just hope that we can use the |
244b1afb RE |
10012 | constant pool value directly. */ |
10013 | if (op == cop) | |
c769a35d | 10014 | cop = get_pool_constant (XEXP (op, 0)); |
244b1afb RE |
10015 | |
10016 | push_minipool_fix (insn, address, | |
10017 | recog_data.operand_loc[opno], | |
c769a35d | 10018 | recog_data.operand_mode[opno], cop); |
244b1afb | 10019 | } |
f0375c66 NC |
10020 | |
10021 | result = true; | |
10022 | } | |
949d79eb | 10023 | } |
2b835d68 | 10024 | } |
f0375c66 NC |
10025 | |
10026 | return result; | |
2b835d68 RE |
10027 | } |
10028 | ||
18dbd950 RS |
10029 | /* Gcc puts the pool in the wrong place for ARM, since we can only |
10030 | load addresses a limited distance around the pc. We do some | |
10031 | special munging to move the constant pool values to the correct | |
10032 | point in the code. */ | |
18dbd950 | 10033 | static void |
e32bac5b | 10034 | arm_reorg (void) |
2b835d68 RE |
10035 | { |
10036 | rtx insn; | |
d5b7b3ae RE |
10037 | HOST_WIDE_INT address = 0; |
10038 | Mfix * fix; | |
ad076f4e | 10039 | |
949d79eb | 10040 | minipool_fix_head = minipool_fix_tail = NULL; |
2b835d68 | 10041 | |
949d79eb RE |
10042 | /* The first insn must always be a note, or the code below won't |
10043 | scan it properly. */ | |
18dbd950 | 10044 | insn = get_insns (); |
e6d29d15 | 10045 | gcc_assert (GET_CODE (insn) == NOTE); |
34a9f549 | 10046 | minipool_pad = 0; |
949d79eb RE |
10047 | |
10048 | /* Scan all the insns and record the operands that will need fixing. */ | |
18dbd950 | 10049 | for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) |
2b835d68 | 10050 | { |
9b6b54e2 | 10051 | if (TARGET_CIRRUS_FIX_INVALID_INSNS |
f0375c66 | 10052 | && (arm_cirrus_insn_p (insn) |
9b6b54e2 | 10053 | || GET_CODE (insn) == JUMP_INSN |
f0375c66 | 10054 | || arm_memory_load_p (insn))) |
9b6b54e2 NC |
10055 | cirrus_reorg (insn); |
10056 | ||
949d79eb | 10057 | if (GET_CODE (insn) == BARRIER) |
d5b7b3ae | 10058 | push_minipool_barrier (insn, address); |
f0375c66 | 10059 | else if (INSN_P (insn)) |
949d79eb RE |
10060 | { |
10061 | rtx table; | |
10062 | ||
f0375c66 | 10063 | note_invalid_constants (insn, address, true); |
949d79eb | 10064 | address += get_attr_length (insn); |
d5b7b3ae | 10065 | |
949d79eb RE |
10066 | /* If the insn is a vector jump, add the size of the table |
10067 | and skip the table. */ | |
d5b7b3ae | 10068 | if ((table = is_jump_table (insn)) != NULL) |
2b835d68 | 10069 | { |
d5b7b3ae | 10070 | address += get_jump_table_size (table); |
949d79eb RE |
10071 | insn = table; |
10072 | } | |
10073 | } | |
10074 | } | |
332072db | 10075 | |
d5b7b3ae | 10076 | fix = minipool_fix_head; |
f676971a | 10077 | |
949d79eb | 10078 | /* Now scan the fixups and perform the required changes. */ |
d5b7b3ae | 10079 | while (fix) |
949d79eb | 10080 | { |
d5b7b3ae RE |
10081 | Mfix * ftmp; |
10082 | Mfix * fdel; | |
10083 | Mfix * last_added_fix; | |
10084 | Mfix * last_barrier = NULL; | |
10085 | Mfix * this_fix; | |
949d79eb RE |
10086 | |
10087 | /* Skip any further barriers before the next fix. */ | |
10088 | while (fix && GET_CODE (fix->insn) == BARRIER) | |
10089 | fix = fix->next; | |
10090 | ||
d5b7b3ae | 10091 | /* No more fixes. */ |
949d79eb RE |
10092 | if (fix == NULL) |
10093 | break; | |
332072db | 10094 | |
d5b7b3ae | 10095 | last_added_fix = NULL; |
2b835d68 | 10096 | |
d5b7b3ae | 10097 | for (ftmp = fix; ftmp; ftmp = ftmp->next) |
949d79eb | 10098 | { |
949d79eb | 10099 | if (GET_CODE (ftmp->insn) == BARRIER) |
949d79eb | 10100 | { |
d5b7b3ae RE |
10101 | if (ftmp->address >= minipool_vector_head->max_address) |
10102 | break; | |
2b835d68 | 10103 | |
d5b7b3ae | 10104 | last_barrier = ftmp; |
2b835d68 | 10105 | } |
d5b7b3ae RE |
10106 | else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) |
10107 | break; | |
10108 | ||
10109 | last_added_fix = ftmp; /* Keep track of the last fix added. */ | |
2b835d68 | 10110 | } |
949d79eb | 10111 | |
d5b7b3ae RE |
10112 | /* If we found a barrier, drop back to that; any fixes that we |
10113 | could have reached but come after the barrier will now go in | |
10114 | the next mini-pool. */ | |
949d79eb RE |
10115 | if (last_barrier != NULL) |
10116 | { | |
f676971a | 10117 | /* Reduce the refcount for those fixes that won't go into this |
d5b7b3ae RE |
10118 | pool after all. */ |
10119 | for (fdel = last_barrier->next; | |
10120 | fdel && fdel != ftmp; | |
10121 | fdel = fdel->next) | |
10122 | { | |
10123 | fdel->minipool->refcount--; | |
10124 | fdel->minipool = NULL; | |
10125 | } | |
10126 | ||
949d79eb RE |
10127 | ftmp = last_barrier; |
10128 | } | |
10129 | else | |
2bfa88dc | 10130 | { |
d5b7b3ae RE |
10131 | /* ftmp is first fix that we can't fit into this pool and |
10132 | there no natural barriers that we could use. Insert a | |
10133 | new barrier in the code somewhere between the previous | |
10134 | fix and this one, and arrange to jump around it. */ | |
10135 | HOST_WIDE_INT max_address; | |
10136 | ||
10137 | /* The last item on the list of fixes must be a barrier, so | |
10138 | we can never run off the end of the list of fixes without | |
10139 | last_barrier being set. */ | |
e6d29d15 | 10140 | gcc_assert (ftmp); |
d5b7b3ae RE |
10141 | |
10142 | max_address = minipool_vector_head->max_address; | |
2bfa88dc RE |
10143 | /* Check that there isn't another fix that is in range that |
10144 | we couldn't fit into this pool because the pool was | |
10145 | already too large: we need to put the pool before such an | |
7a7017bc PB |
10146 | instruction. The pool itself may come just after the |
10147 | fix because create_fix_barrier also allows space for a | |
10148 | jump instruction. */ | |
d5b7b3ae | 10149 | if (ftmp->address < max_address) |
7a7017bc | 10150 | max_address = ftmp->address + 1; |
d5b7b3ae RE |
10151 | |
10152 | last_barrier = create_fix_barrier (last_added_fix, max_address); | |
10153 | } | |
10154 | ||
10155 | assign_minipool_offsets (last_barrier); | |
10156 | ||
10157 | while (ftmp) | |
10158 | { | |
10159 | if (GET_CODE (ftmp->insn) != BARRIER | |
10160 | && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) | |
10161 | == NULL)) | |
10162 | break; | |
2bfa88dc | 10163 | |
d5b7b3ae | 10164 | ftmp = ftmp->next; |
2bfa88dc | 10165 | } |
949d79eb RE |
10166 | |
10167 | /* Scan over the fixes we have identified for this pool, fixing them | |
10168 | up and adding the constants to the pool itself. */ | |
d5b7b3ae | 10169 | for (this_fix = fix; this_fix && ftmp != this_fix; |
949d79eb RE |
10170 | this_fix = this_fix->next) |
10171 | if (GET_CODE (this_fix->insn) != BARRIER) | |
10172 | { | |
949d79eb | 10173 | rtx addr |
f676971a | 10174 | = plus_constant (gen_rtx_LABEL_REF (VOIDmode, |
949d79eb | 10175 | minipool_vector_label), |
d5b7b3ae | 10176 | this_fix->minipool->offset); |
949d79eb RE |
10177 | *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); |
10178 | } | |
10179 | ||
d5b7b3ae | 10180 | dump_minipool (last_barrier->insn); |
949d79eb | 10181 | fix = ftmp; |
2b835d68 | 10182 | } |
4b632bf1 | 10183 | |
949d79eb RE |
10184 | /* From now on we must synthesize any constants that we can't handle |
10185 | directly. This can happen if the RTL gets split during final | |
10186 | instruction generation. */ | |
4b632bf1 | 10187 | after_arm_reorg = 1; |
c7319d87 RE |
10188 | |
10189 | /* Free the minipool memory. */ | |
10190 | obstack_free (&minipool_obstack, minipool_startobj); | |
2b835d68 | 10191 | } |
cce8749e CH |
10192 | \f |
10193 | /* Routines to output assembly language. */ | |
10194 | ||
f3bb6135 | 10195 | /* If the rtx is the correct value then return the string of the number. |
ff9940b0 | 10196 | In this way we can ensure that valid double constants are generated even |
6354dc9b | 10197 | when cross compiling. */ |
cd2b33d0 | 10198 | const char * |
e32bac5b | 10199 | fp_immediate_constant (rtx x) |
ff9940b0 RE |
10200 | { |
10201 | REAL_VALUE_TYPE r; | |
10202 | int i; | |
f676971a | 10203 | |
9b66ebb1 PB |
10204 | if (!fp_consts_inited) |
10205 | init_fp_table (); | |
f676971a | 10206 | |
ff9940b0 RE |
10207 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); |
10208 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
10209 | if (REAL_VALUES_EQUAL (r, values_fp[i])) |
10210 | return strings_fp[i]; | |
f3bb6135 | 10211 | |
e6d29d15 | 10212 | gcc_unreachable (); |
ff9940b0 RE |
10213 | } |
10214 | ||
9997d19d | 10215 | /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ |
cd2b33d0 | 10216 | static const char * |
e32bac5b | 10217 | fp_const_from_val (REAL_VALUE_TYPE *r) |
9997d19d RE |
10218 | { |
10219 | int i; | |
10220 | ||
9b66ebb1 PB |
10221 | if (!fp_consts_inited) |
10222 | init_fp_table (); | |
9997d19d RE |
10223 | |
10224 | for (i = 0; i < 8; i++) | |
9b66ebb1 PB |
10225 | if (REAL_VALUES_EQUAL (*r, values_fp[i])) |
10226 | return strings_fp[i]; | |
9997d19d | 10227 | |
e6d29d15 | 10228 | gcc_unreachable (); |
9997d19d | 10229 | } |
ff9940b0 | 10230 | |
cce8749e CH |
10231 | /* Output the operands of a LDM/STM instruction to STREAM. |
10232 | MASK is the ARM register set mask of which only bits 0-15 are important. | |
6d3d9133 | 10233 | REG is the base register, either the frame pointer or the stack pointer, |
a15908a4 PB |
10234 | INSTR is the possibly suffixed load or store instruction. |
10235 | RFE is nonzero if the instruction should also copy spsr to cpsr. */ | |
b279b20a | 10236 | |
d5b7b3ae | 10237 | static void |
b279b20a | 10238 | print_multi_reg (FILE *stream, const char *instr, unsigned reg, |
a15908a4 | 10239 | unsigned long mask, int rfe) |
cce8749e | 10240 | { |
b279b20a NC |
10241 | unsigned i; |
10242 | bool not_first = FALSE; | |
cce8749e | 10243 | |
a15908a4 | 10244 | gcc_assert (!rfe || (mask & (1 << PC_REGNUM))); |
1d5473cb | 10245 | fputc ('\t', stream); |
dd18ae56 | 10246 | asm_fprintf (stream, instr, reg); |
5b3e6663 | 10247 | fputc ('{', stream); |
f676971a | 10248 | |
d5b7b3ae | 10249 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
cce8749e CH |
10250 | if (mask & (1 << i)) |
10251 | { | |
10252 | if (not_first) | |
10253 | fprintf (stream, ", "); | |
f676971a | 10254 | |
dd18ae56 | 10255 | asm_fprintf (stream, "%r", i); |
cce8749e CH |
10256 | not_first = TRUE; |
10257 | } | |
f3bb6135 | 10258 | |
a15908a4 PB |
10259 | if (rfe) |
10260 | fprintf (stream, "}^\n"); | |
10261 | else | |
10262 | fprintf (stream, "}\n"); | |
f3bb6135 | 10263 | } |
cce8749e | 10264 | |
9b66ebb1 | 10265 | |
8edfc4cc | 10266 | /* Output a FLDMD instruction to STREAM. |
9728c9d1 PB |
10267 | BASE if the register containing the address. |
10268 | REG and COUNT specify the register range. | |
8edfc4cc MS |
10269 | Extra registers may be added to avoid hardware bugs. |
10270 | ||
10271 | We output FLDMD even for ARMv5 VFP implementations. Although | |
10272 | FLDMD is technically not supported until ARMv6, it is believed | |
10273 | that all VFP implementations support its use in this context. */ | |
9b66ebb1 PB |
10274 | |
10275 | static void | |
8edfc4cc | 10276 | vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count) |
9b66ebb1 PB |
10277 | { |
10278 | int i; | |
10279 | ||
9728c9d1 PB |
10280 | /* Workaround ARM10 VFPr1 bug. */ |
10281 | if (count == 2 && !arm_arch6) | |
10282 | { | |
10283 | if (reg == 15) | |
10284 | reg--; | |
10285 | count++; | |
10286 | } | |
10287 | ||
f1adb0a9 JB |
10288 | /* FLDMD may not load more than 16 doubleword registers at a time. Split the |
10289 | load into multiple parts if we have to handle more than 16 registers. */ | |
10290 | if (count > 16) | |
10291 | { | |
10292 | vfp_output_fldmd (stream, base, reg, 16); | |
10293 | vfp_output_fldmd (stream, base, reg + 16, count - 16); | |
10294 | return; | |
10295 | } | |
10296 | ||
9b66ebb1 | 10297 | fputc ('\t', stream); |
8edfc4cc | 10298 | asm_fprintf (stream, "fldmfdd\t%r!, {", base); |
9b66ebb1 | 10299 | |
9728c9d1 | 10300 | for (i = reg; i < reg + count; i++) |
9b66ebb1 | 10301 | { |
9728c9d1 | 10302 | if (i > reg) |
9b66ebb1 | 10303 | fputs (", ", stream); |
9728c9d1 | 10304 | asm_fprintf (stream, "d%d", i); |
9b66ebb1 PB |
10305 | } |
10306 | fputs ("}\n", stream); | |
9728c9d1 | 10307 | |
9b66ebb1 PB |
10308 | } |
10309 | ||
10310 | ||
10311 | /* Output the assembly for a store multiple. */ | |
10312 | ||
10313 | const char * | |
8edfc4cc | 10314 | vfp_output_fstmd (rtx * operands) |
9b66ebb1 PB |
10315 | { |
10316 | char pattern[100]; | |
10317 | int p; | |
10318 | int base; | |
10319 | int i; | |
10320 | ||
8edfc4cc | 10321 | strcpy (pattern, "fstmfdd\t%m0!, {%P1"); |
9b66ebb1 PB |
10322 | p = strlen (pattern); |
10323 | ||
e6d29d15 | 10324 | gcc_assert (GET_CODE (operands[1]) == REG); |
9b66ebb1 PB |
10325 | |
10326 | base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; | |
10327 | for (i = 1; i < XVECLEN (operands[2], 0); i++) | |
10328 | { | |
10329 | p += sprintf (&pattern[p], ", d%d", base + i); | |
10330 | } | |
10331 | strcpy (&pattern[p], "}"); | |
10332 | ||
10333 | output_asm_insn (pattern, operands); | |
10334 | return ""; | |
10335 | } | |
10336 | ||
10337 | ||
9728c9d1 PB |
10338 | /* Emit RTL to save block of VFP register pairs to the stack. Returns the |
10339 | number of bytes pushed. */ | |
9b66ebb1 | 10340 | |
9728c9d1 | 10341 | static int |
8edfc4cc | 10342 | vfp_emit_fstmd (int base_reg, int count) |
9b66ebb1 PB |
10343 | { |
10344 | rtx par; | |
10345 | rtx dwarf; | |
10346 | rtx tmp, reg; | |
10347 | int i; | |
10348 | ||
9728c9d1 PB |
10349 | /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two |
10350 | register pairs are stored by a store multiple insn. We avoid this | |
10351 | by pushing an extra pair. */ | |
10352 | if (count == 2 && !arm_arch6) | |
10353 | { | |
10354 | if (base_reg == LAST_VFP_REGNUM - 3) | |
10355 | base_reg -= 2; | |
10356 | count++; | |
10357 | } | |
10358 | ||
f1adb0a9 JB |
10359 | /* FSTMD may not store more than 16 doubleword registers at once. Split |
10360 | larger stores into multiple parts (up to a maximum of two, in | |
10361 | practice). */ | |
10362 | if (count > 16) | |
10363 | { | |
10364 | int saved; | |
10365 | /* NOTE: base_reg is an internal register number, so each D register | |
10366 | counts as 2. */ | |
10367 | saved = vfp_emit_fstmd (base_reg + 32, count - 16); | |
10368 | saved += vfp_emit_fstmd (base_reg, 16); | |
10369 | return saved; | |
10370 | } | |
10371 | ||
9b66ebb1 PB |
10372 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
10373 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); | |
10374 | ||
10375 | reg = gen_rtx_REG (DFmode, base_reg); | |
10376 | base_reg += 2; | |
10377 | ||
10378 | XVECEXP (par, 0, 0) | |
10379 | = gen_rtx_SET (VOIDmode, | |
31fa16b6 RE |
10380 | gen_frame_mem (BLKmode, |
10381 | gen_rtx_PRE_DEC (BLKmode, | |
10382 | stack_pointer_rtx)), | |
9b66ebb1 PB |
10383 | gen_rtx_UNSPEC (BLKmode, |
10384 | gen_rtvec (1, reg), | |
10385 | UNSPEC_PUSH_MULT)); | |
10386 | ||
10387 | tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8edfc4cc | 10388 | plus_constant (stack_pointer_rtx, -(count * 8))); |
9b66ebb1 PB |
10389 | RTX_FRAME_RELATED_P (tmp) = 1; |
10390 | XVECEXP (dwarf, 0, 0) = tmp; | |
10391 | ||
10392 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 10393 | gen_frame_mem (DFmode, stack_pointer_rtx), |
9b66ebb1 PB |
10394 | reg); |
10395 | RTX_FRAME_RELATED_P (tmp) = 1; | |
10396 | XVECEXP (dwarf, 0, 1) = tmp; | |
10397 | ||
10398 | for (i = 1; i < count; i++) | |
10399 | { | |
10400 | reg = gen_rtx_REG (DFmode, base_reg); | |
10401 | base_reg += 2; | |
10402 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
10403 | ||
10404 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 10405 | gen_frame_mem (DFmode, |
d66437c5 RE |
10406 | plus_constant (stack_pointer_rtx, |
10407 | i * 8)), | |
9b66ebb1 PB |
10408 | reg); |
10409 | RTX_FRAME_RELATED_P (tmp) = 1; | |
10410 | XVECEXP (dwarf, 0, i + 1) = tmp; | |
10411 | } | |
10412 | ||
10413 | par = emit_insn (par); | |
bbbbb16a | 10414 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
9728c9d1 PB |
10415 | RTX_FRAME_RELATED_P (par) = 1; |
10416 | ||
8edfc4cc | 10417 | return count * 8; |
9b66ebb1 PB |
10418 | } |
10419 | ||
9403b7f7 RS |
10420 | /* Emit a call instruction with pattern PAT. ADDR is the address of |
10421 | the call target. */ | |
10422 | ||
10423 | void | |
10424 | arm_emit_call_insn (rtx pat, rtx addr) | |
10425 | { | |
10426 | rtx insn; | |
10427 | ||
10428 | insn = emit_call_insn (pat); | |
10429 | ||
10430 | /* The PIC register is live on entry to VxWorks PIC PLT entries. | |
10431 | If the call might use such an entry, add a use of the PIC register | |
10432 | to the instruction's CALL_INSN_FUNCTION_USAGE. */ | |
10433 | if (TARGET_VXWORKS_RTP | |
10434 | && flag_pic | |
10435 | && GET_CODE (addr) == SYMBOL_REF | |
10436 | && (SYMBOL_REF_DECL (addr) | |
10437 | ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) | |
10438 | : !SYMBOL_REF_LOCAL_P (addr))) | |
10439 | { | |
10440 | require_pic_register (); | |
10441 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg); | |
10442 | } | |
10443 | } | |
9b66ebb1 | 10444 | |
6354dc9b | 10445 | /* Output a 'call' insn. */ |
cd2b33d0 | 10446 | const char * |
e32bac5b | 10447 | output_call (rtx *operands) |
cce8749e | 10448 | { |
e6d29d15 | 10449 | gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ |
cce8749e | 10450 | |
68d560d4 | 10451 | /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ |
62b10bbc | 10452 | if (REGNO (operands[0]) == LR_REGNUM) |
cce8749e | 10453 | { |
62b10bbc | 10454 | operands[0] = gen_rtx_REG (SImode, IP_REGNUM); |
1d5473cb | 10455 | output_asm_insn ("mov%?\t%0, %|lr", operands); |
cce8749e | 10456 | } |
f676971a | 10457 | |
1d5473cb | 10458 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); |
f676971a | 10459 | |
68d560d4 | 10460 | if (TARGET_INTERWORK || arm_arch4t) |
da6558fd NC |
10461 | output_asm_insn ("bx%?\t%0", operands); |
10462 | else | |
10463 | output_asm_insn ("mov%?\t%|pc, %0", operands); | |
f676971a | 10464 | |
f3bb6135 RE |
10465 | return ""; |
10466 | } | |
cce8749e | 10467 | |
6354dc9b | 10468 | /* Output a 'call' insn that is a reference in memory. */ |
cd2b33d0 | 10469 | const char * |
e32bac5b | 10470 | output_call_mem (rtx *operands) |
ff9940b0 | 10471 | { |
68d560d4 | 10472 | if (TARGET_INTERWORK && !arm_arch5) |
da6558fd NC |
10473 | { |
10474 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
10475 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10476 | output_asm_insn ("bx%?\t%|ip", operands); | |
10477 | } | |
6ab5da80 RE |
10478 | else if (regno_use_in (LR_REGNUM, operands[0])) |
10479 | { | |
10480 | /* LR is used in the memory address. We load the address in the | |
10481 | first instruction. It's safe to use IP as the target of the | |
10482 | load since the call will kill it anyway. */ | |
10483 | output_asm_insn ("ldr%?\t%|ip, %0", operands); | |
68d560d4 | 10484 | if (arm_arch5) |
07ec3810 | 10485 | output_asm_insn ("blx%?\t%|ip", operands); |
68d560d4 RE |
10486 | else |
10487 | { | |
10488 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10489 | if (arm_arch4t) | |
10490 | output_asm_insn ("bx%?\t%|ip", operands); | |
10491 | else | |
10492 | output_asm_insn ("mov%?\t%|pc, %|ip", operands); | |
10493 | } | |
6ab5da80 | 10494 | } |
da6558fd NC |
10495 | else |
10496 | { | |
10497 | output_asm_insn ("mov%?\t%|lr, %|pc", operands); | |
10498 | output_asm_insn ("ldr%?\t%|pc, %0", operands); | |
10499 | } | |
10500 | ||
f3bb6135 RE |
10501 | return ""; |
10502 | } | |
ff9940b0 RE |
10503 | |
10504 | ||
3b684012 RE |
10505 | /* Output a move from arm registers to an fpa registers. |
10506 | OPERANDS[0] is an fpa register. | |
ff9940b0 | 10507 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 10508 | const char * |
e32bac5b | 10509 | output_mov_long_double_fpa_from_arm (rtx *operands) |
ff9940b0 RE |
10510 | { |
10511 | int arm_reg0 = REGNO (operands[1]); | |
10512 | rtx ops[3]; | |
10513 | ||
e6d29d15 | 10514 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10515 | |
43cffd11 RE |
10516 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10517 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
10518 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
f676971a | 10519 | |
5b3e6663 | 10520 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
1d5473cb | 10521 | output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); |
f676971a | 10522 | |
f3bb6135 RE |
10523 | return ""; |
10524 | } | |
ff9940b0 | 10525 | |
3b684012 | 10526 | /* Output a move from an fpa register to arm registers. |
ff9940b0 | 10527 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 10528 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 10529 | const char * |
e32bac5b | 10530 | output_mov_long_double_arm_from_fpa (rtx *operands) |
ff9940b0 RE |
10531 | { |
10532 | int arm_reg0 = REGNO (operands[0]); | |
10533 | rtx ops[3]; | |
10534 | ||
e6d29d15 | 10535 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10536 | |
43cffd11 RE |
10537 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10538 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
10539 | ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); | |
ff9940b0 | 10540 | |
1d5473cb | 10541 | output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); |
5b3e6663 | 10542 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops); |
f3bb6135 RE |
10543 | return ""; |
10544 | } | |
ff9940b0 RE |
10545 | |
10546 | /* Output a move from arm registers to arm registers of a long double | |
10547 | OPERANDS[0] is the destination. | |
10548 | OPERANDS[1] is the source. */ | |
cd2b33d0 | 10549 | const char * |
e32bac5b | 10550 | output_mov_long_double_arm_from_arm (rtx *operands) |
ff9940b0 | 10551 | { |
6354dc9b | 10552 | /* We have to be careful here because the two might overlap. */ |
ff9940b0 RE |
10553 | int dest_start = REGNO (operands[0]); |
10554 | int src_start = REGNO (operands[1]); | |
10555 | rtx ops[2]; | |
10556 | int i; | |
10557 | ||
10558 | if (dest_start < src_start) | |
10559 | { | |
10560 | for (i = 0; i < 3; i++) | |
10561 | { | |
43cffd11 RE |
10562 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
10563 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 10564 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
10565 | } |
10566 | } | |
10567 | else | |
10568 | { | |
10569 | for (i = 2; i >= 0; i--) | |
10570 | { | |
43cffd11 RE |
10571 | ops[0] = gen_rtx_REG (SImode, dest_start + i); |
10572 | ops[1] = gen_rtx_REG (SImode, src_start + i); | |
9997d19d | 10573 | output_asm_insn ("mov%?\t%0, %1", ops); |
ff9940b0 RE |
10574 | } |
10575 | } | |
f3bb6135 | 10576 | |
ff9940b0 RE |
10577 | return ""; |
10578 | } | |
10579 | ||
10580 | ||
571191af PB |
10581 | /* Emit a MOVW/MOVT pair. */ |
10582 | void arm_emit_movpair (rtx dest, rtx src) | |
10583 | { | |
10584 | emit_set_insn (dest, gen_rtx_HIGH (SImode, src)); | |
10585 | emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src)); | |
10586 | } | |
10587 | ||
10588 | ||
3b684012 RE |
10589 | /* Output a move from arm registers to an fpa registers. |
10590 | OPERANDS[0] is an fpa register. | |
cce8749e | 10591 | OPERANDS[1] is the first registers of an arm register pair. */ |
cd2b33d0 | 10592 | const char * |
e32bac5b | 10593 | output_mov_double_fpa_from_arm (rtx *operands) |
cce8749e CH |
10594 | { |
10595 | int arm_reg0 = REGNO (operands[1]); | |
10596 | rtx ops[2]; | |
10597 | ||
e6d29d15 | 10598 | gcc_assert (arm_reg0 != IP_REGNUM); |
f676971a | 10599 | |
43cffd11 RE |
10600 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10601 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
5b3e6663 | 10602 | output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops); |
1d5473cb | 10603 | output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); |
f3bb6135 RE |
10604 | return ""; |
10605 | } | |
cce8749e | 10606 | |
3b684012 | 10607 | /* Output a move from an fpa register to arm registers. |
cce8749e | 10608 | OPERANDS[0] is the first registers of an arm register pair. |
3b684012 | 10609 | OPERANDS[1] is an fpa register. */ |
cd2b33d0 | 10610 | const char * |
e32bac5b | 10611 | output_mov_double_arm_from_fpa (rtx *operands) |
cce8749e CH |
10612 | { |
10613 | int arm_reg0 = REGNO (operands[0]); | |
10614 | rtx ops[2]; | |
10615 | ||
e6d29d15 | 10616 | gcc_assert (arm_reg0 != IP_REGNUM); |
f3bb6135 | 10617 | |
43cffd11 RE |
10618 | ops[0] = gen_rtx_REG (SImode, arm_reg0); |
10619 | ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); | |
1d5473cb | 10620 | output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); |
5b3e6663 | 10621 | output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops); |
f3bb6135 RE |
10622 | return ""; |
10623 | } | |
cce8749e CH |
10624 | |
10625 | /* Output a move between double words. | |
10626 | It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM | |
10627 | or MEM<-REG and all MEMs must be offsettable addresses. */ | |
cd2b33d0 | 10628 | const char * |
e32bac5b | 10629 | output_move_double (rtx *operands) |
cce8749e CH |
10630 | { |
10631 | enum rtx_code code0 = GET_CODE (operands[0]); | |
10632 | enum rtx_code code1 = GET_CODE (operands[1]); | |
56636818 | 10633 | rtx otherops[3]; |
cce8749e CH |
10634 | |
10635 | if (code0 == REG) | |
10636 | { | |
f0b4bdd5 | 10637 | unsigned int reg0 = REGNO (operands[0]); |
cce8749e | 10638 | |
43cffd11 | 10639 | otherops[0] = gen_rtx_REG (SImode, 1 + reg0); |
f676971a | 10640 | |
e6d29d15 NS |
10641 | gcc_assert (code1 == MEM); /* Constraints should ensure this. */ |
10642 | ||
10643 | switch (GET_CODE (XEXP (operands[1], 0))) | |
cce8749e | 10644 | { |
e6d29d15 | 10645 | case REG: |
5fd42423 PB |
10646 | if (TARGET_LDRD |
10647 | && !(fix_cm3_ldrd && reg0 == REGNO(XEXP (operands[1], 0)))) | |
5dea0c19 PB |
10648 | output_asm_insn ("ldr%(d%)\t%0, [%m1]", operands); |
10649 | else | |
10650 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
e6d29d15 | 10651 | break; |
e0b92319 | 10652 | |
e6d29d15 NS |
10653 | case PRE_INC: |
10654 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 10655 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands); |
e6d29d15 | 10656 | break; |
e0b92319 | 10657 | |
e6d29d15 | 10658 | case PRE_DEC: |
5b3e6663 PB |
10659 | if (TARGET_LDRD) |
10660 | output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands); | |
10661 | else | |
10662 | output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands); | |
e6d29d15 | 10663 | break; |
e0b92319 | 10664 | |
e6d29d15 | 10665 | case POST_INC: |
5dea0c19 PB |
10666 | if (TARGET_LDRD) |
10667 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #8", operands); | |
10668 | else | |
10669 | output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands); | |
e6d29d15 | 10670 | break; |
e0b92319 | 10671 | |
e6d29d15 NS |
10672 | case POST_DEC: |
10673 | gcc_assert (TARGET_LDRD); | |
5b3e6663 | 10674 | output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands); |
e6d29d15 | 10675 | break; |
e0b92319 | 10676 | |
e6d29d15 NS |
10677 | case PRE_MODIFY: |
10678 | case POST_MODIFY: | |
5fd42423 PB |
10679 | /* Autoicrement addressing modes should never have overlapping |
10680 | base and destination registers, and overlapping index registers | |
10681 | are already prohibited, so this doesn't need to worry about | |
10682 | fix_cm3_ldrd. */ | |
e6d29d15 NS |
10683 | otherops[0] = operands[0]; |
10684 | otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); | |
10685 | otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); | |
e0b92319 | 10686 | |
e6d29d15 | 10687 | if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) |
cce8749e | 10688 | { |
e6d29d15 | 10689 | if (reg_overlap_mentioned_p (otherops[0], otherops[2])) |
fdd695fd | 10690 | { |
e6d29d15 NS |
10691 | /* Registers overlap so split out the increment. */ |
10692 | output_asm_insn ("add%?\t%1, %1, %2", otherops); | |
5b3e6663 | 10693 | output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops); |
fdd695fd PB |
10694 | } |
10695 | else | |
fe2d934b | 10696 | { |
ff128632 RE |
10697 | /* Use a single insn if we can. |
10698 | FIXME: IWMMXT allows offsets larger than ldrd can | |
10699 | handle, fix these up with a pair of ldr. */ | |
10700 | if (TARGET_THUMB2 | |
10701 | || GET_CODE (otherops[2]) != CONST_INT | |
10702 | || (INTVAL (otherops[2]) > -256 | |
10703 | && INTVAL (otherops[2]) < 256)) | |
10704 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops); | |
10705 | else | |
fe2d934b PB |
10706 | { |
10707 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 10708 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b | 10709 | } |
fe2d934b | 10710 | } |
e6d29d15 NS |
10711 | } |
10712 | else | |
10713 | { | |
ff128632 RE |
10714 | /* Use a single insn if we can. |
10715 | FIXME: IWMMXT allows offsets larger than ldrd can handle, | |
fe2d934b | 10716 | fix these up with a pair of ldr. */ |
ff128632 RE |
10717 | if (TARGET_THUMB2 |
10718 | || GET_CODE (otherops[2]) != CONST_INT | |
10719 | || (INTVAL (otherops[2]) > -256 | |
10720 | && INTVAL (otherops[2]) < 256)) | |
10721 | output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops); | |
10722 | else | |
fe2d934b | 10723 | { |
ff128632 | 10724 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10725 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
10726 | } | |
e6d29d15 NS |
10727 | } |
10728 | break; | |
e0b92319 | 10729 | |
e6d29d15 NS |
10730 | case LABEL_REF: |
10731 | case CONST: | |
5dea0c19 PB |
10732 | /* We might be able to use ldrd %0, %1 here. However the range is |
10733 | different to ldr/adr, and it is broken on some ARMv7-M | |
10734 | implementations. */ | |
5fd42423 PB |
10735 | /* Use the second register of the pair to avoid problematic |
10736 | overlap. */ | |
10737 | otherops[1] = operands[1]; | |
10738 | output_asm_insn ("adr%?\t%0, %1", otherops); | |
10739 | operands[1] = otherops[0]; | |
5dea0c19 | 10740 | if (TARGET_LDRD) |
5fd42423 | 10741 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); |
5dea0c19 | 10742 | else |
5fd42423 | 10743 | output_asm_insn ("ldm%(ia%)\t%1, %M0", operands); |
e6d29d15 | 10744 | break; |
e0b92319 | 10745 | |
5b3e6663 | 10746 | /* ??? This needs checking for thumb2. */ |
e6d29d15 NS |
10747 | default: |
10748 | if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), | |
10749 | GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) | |
10750 | { | |
10751 | otherops[0] = operands[0]; | |
10752 | otherops[1] = XEXP (XEXP (operands[1], 0), 0); | |
10753 | otherops[2] = XEXP (XEXP (operands[1], 0), 1); | |
e0b92319 | 10754 | |
e6d29d15 | 10755 | if (GET_CODE (XEXP (operands[1], 0)) == PLUS) |
fdd695fd | 10756 | { |
5dea0c19 | 10757 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10758 | { |
e6d29d15 | 10759 | switch ((int) INTVAL (otherops[2])) |
2b835d68 | 10760 | { |
e6d29d15 | 10761 | case -8: |
5b3e6663 | 10762 | output_asm_insn ("ldm%(db%)\t%1, %M0", otherops); |
e6d29d15 NS |
10763 | return ""; |
10764 | case -4: | |
5b3e6663 PB |
10765 | if (TARGET_THUMB2) |
10766 | break; | |
10767 | output_asm_insn ("ldm%(da%)\t%1, %M0", otherops); | |
e6d29d15 NS |
10768 | return ""; |
10769 | case 4: | |
5b3e6663 PB |
10770 | if (TARGET_THUMB2) |
10771 | break; | |
10772 | output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops); | |
e6d29d15 | 10773 | return ""; |
fdd695fd | 10774 | } |
e6d29d15 | 10775 | } |
5fd42423 PB |
10776 | otherops[0] = gen_rtx_REG(SImode, REGNO(operands[0]) + 1); |
10777 | operands[1] = otherops[0]; | |
e6d29d15 NS |
10778 | if (TARGET_LDRD |
10779 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 10780 | || TARGET_THUMB2 |
e6d29d15 NS |
10781 | || (GET_CODE (otherops[2]) == CONST_INT |
10782 | && INTVAL (otherops[2]) > -256 | |
10783 | && INTVAL (otherops[2]) < 256))) | |
10784 | { | |
5fd42423 | 10785 | if (reg_overlap_mentioned_p (operands[0], |
e6d29d15 | 10786 | otherops[2])) |
fdd695fd | 10787 | { |
5fd42423 | 10788 | rtx tmp; |
e6d29d15 NS |
10789 | /* Swap base and index registers over to |
10790 | avoid a conflict. */ | |
5fd42423 PB |
10791 | tmp = otherops[1]; |
10792 | otherops[1] = otherops[2]; | |
10793 | otherops[2] = tmp; | |
fdd695fd | 10794 | } |
e6d29d15 NS |
10795 | /* If both registers conflict, it will usually |
10796 | have been fixed by a splitter. */ | |
5fd42423 PB |
10797 | if (reg_overlap_mentioned_p (operands[0], otherops[2]) |
10798 | || (fix_cm3_ldrd && reg0 == REGNO (otherops[1]))) | |
fdd695fd | 10799 | { |
5fd42423 PB |
10800 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
10801 | output_asm_insn ("ldr%(d%)\t%0, [%1]", operands); | |
2b835d68 RE |
10802 | } |
10803 | else | |
5fd42423 PB |
10804 | { |
10805 | otherops[0] = operands[0]; | |
10806 | output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops); | |
10807 | } | |
e6d29d15 | 10808 | return ""; |
2b835d68 | 10809 | } |
e0b92319 | 10810 | |
e6d29d15 | 10811 | if (GET_CODE (otherops[2]) == CONST_INT) |
2b835d68 | 10812 | { |
e6d29d15 NS |
10813 | if (!(const_ok_for_arm (INTVAL (otherops[2])))) |
10814 | output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); | |
10815 | else | |
10816 | output_asm_insn ("add%?\t%0, %1, %2", otherops); | |
2b835d68 RE |
10817 | } |
10818 | else | |
e6d29d15 NS |
10819 | output_asm_insn ("add%?\t%0, %1, %2", otherops); |
10820 | } | |
10821 | else | |
10822 | output_asm_insn ("sub%?\t%0, %1, %2", otherops); | |
10823 | ||
5dea0c19 | 10824 | if (TARGET_LDRD) |
5fd42423 | 10825 | return "ldr%(d%)\t%0, [%1]"; |
5dea0c19 | 10826 | |
5fd42423 | 10827 | return "ldm%(ia%)\t%1, %M0"; |
e6d29d15 NS |
10828 | } |
10829 | else | |
10830 | { | |
10831 | otherops[1] = adjust_address (operands[1], SImode, 4); | |
10832 | /* Take care of overlapping base/data reg. */ | |
10833 | if (reg_mentioned_p (operands[0], operands[1])) | |
10834 | { | |
10835 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
10836 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10837 | } | |
10838 | else | |
10839 | { | |
10840 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
10841 | output_asm_insn ("ldr%?\t%0, %1", otherops); | |
cce8749e CH |
10842 | } |
10843 | } | |
10844 | } | |
cce8749e | 10845 | } |
e6d29d15 | 10846 | else |
cce8749e | 10847 | { |
e6d29d15 NS |
10848 | /* Constraints should ensure this. */ |
10849 | gcc_assert (code0 == MEM && code1 == REG); | |
10850 | gcc_assert (REGNO (operands[1]) != IP_REGNUM); | |
2b835d68 | 10851 | |
ff9940b0 RE |
10852 | switch (GET_CODE (XEXP (operands[0], 0))) |
10853 | { | |
10854 | case REG: | |
5dea0c19 PB |
10855 | if (TARGET_LDRD) |
10856 | output_asm_insn ("str%(d%)\t%1, [%m0]", operands); | |
10857 | else | |
10858 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
ff9940b0 | 10859 | break; |
2b835d68 | 10860 | |
ff9940b0 | 10861 | case PRE_INC: |
e6d29d15 | 10862 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10863 | output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands); |
ff9940b0 | 10864 | break; |
2b835d68 | 10865 | |
ff9940b0 | 10866 | case PRE_DEC: |
5b3e6663 PB |
10867 | if (TARGET_LDRD) |
10868 | output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands); | |
10869 | else | |
10870 | output_asm_insn ("stm%(db%)\t%m0!, %M1", operands); | |
ff9940b0 | 10871 | break; |
2b835d68 | 10872 | |
ff9940b0 | 10873 | case POST_INC: |
5dea0c19 PB |
10874 | if (TARGET_LDRD) |
10875 | output_asm_insn ("str%(d%)\t%1, [%m0], #8", operands); | |
10876 | else | |
10877 | output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands); | |
ff9940b0 | 10878 | break; |
2b835d68 | 10879 | |
ff9940b0 | 10880 | case POST_DEC: |
e6d29d15 | 10881 | gcc_assert (TARGET_LDRD); |
5b3e6663 | 10882 | output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands); |
fdd695fd PB |
10883 | break; |
10884 | ||
10885 | case PRE_MODIFY: | |
10886 | case POST_MODIFY: | |
10887 | otherops[0] = operands[1]; | |
10888 | otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); | |
10889 | otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); | |
10890 | ||
fe2d934b PB |
10891 | /* IWMMXT allows offsets larger than ldrd can handle, |
10892 | fix these up with a pair of ldr. */ | |
ff128632 RE |
10893 | if (!TARGET_THUMB2 |
10894 | && GET_CODE (otherops[2]) == CONST_INT | |
fe2d934b PB |
10895 | && (INTVAL(otherops[2]) <= -256 |
10896 | || INTVAL(otherops[2]) >= 256)) | |
10897 | { | |
fe2d934b PB |
10898 | if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) |
10899 | { | |
10900 | output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); | |
ff128632 | 10901 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10902 | } |
10903 | else | |
10904 | { | |
ff128632 | 10905 | output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops); |
fe2d934b PB |
10906 | output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); |
10907 | } | |
10908 | } | |
10909 | else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) | |
5b3e6663 | 10910 | output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops); |
fdd695fd | 10911 | else |
5b3e6663 | 10912 | output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops); |
ff9940b0 | 10913 | break; |
2b835d68 RE |
10914 | |
10915 | case PLUS: | |
fdd695fd | 10916 | otherops[2] = XEXP (XEXP (operands[0], 0), 1); |
5dea0c19 | 10917 | if (GET_CODE (otherops[2]) == CONST_INT && !TARGET_LDRD) |
2b835d68 | 10918 | { |
06bea5aa | 10919 | switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) |
2b835d68 RE |
10920 | { |
10921 | case -8: | |
5b3e6663 | 10922 | output_asm_insn ("stm%(db%)\t%m0, %M1", operands); |
2b835d68 RE |
10923 | return ""; |
10924 | ||
10925 | case -4: | |
5b3e6663 PB |
10926 | if (TARGET_THUMB2) |
10927 | break; | |
10928 | output_asm_insn ("stm%(da%)\t%m0, %M1", operands); | |
2b835d68 RE |
10929 | return ""; |
10930 | ||
10931 | case 4: | |
5b3e6663 PB |
10932 | if (TARGET_THUMB2) |
10933 | break; | |
10934 | output_asm_insn ("stm%(ib%)\t%m0, %M1", operands); | |
2b835d68 RE |
10935 | return ""; |
10936 | } | |
10937 | } | |
fdd695fd PB |
10938 | if (TARGET_LDRD |
10939 | && (GET_CODE (otherops[2]) == REG | |
ff128632 | 10940 | || TARGET_THUMB2 |
fdd695fd PB |
10941 | || (GET_CODE (otherops[2]) == CONST_INT |
10942 | && INTVAL (otherops[2]) > -256 | |
10943 | && INTVAL (otherops[2]) < 256))) | |
10944 | { | |
10945 | otherops[0] = operands[1]; | |
10946 | otherops[1] = XEXP (XEXP (operands[0], 0), 0); | |
5b3e6663 | 10947 | output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops); |
fdd695fd PB |
10948 | return ""; |
10949 | } | |
2b835d68 RE |
10950 | /* Fall through */ |
10951 | ||
ff9940b0 | 10952 | default: |
a4a37b30 | 10953 | otherops[0] = adjust_address (operands[0], SImode, 4); |
ff128632 | 10954 | otherops[1] = operands[1]; |
9997d19d | 10955 | output_asm_insn ("str%?\t%1, %0", operands); |
ff128632 | 10956 | output_asm_insn ("str%?\t%H1, %0", otherops); |
cce8749e CH |
10957 | } |
10958 | } | |
cce8749e | 10959 | |
9997d19d RE |
10960 | return ""; |
10961 | } | |
cce8749e | 10962 | |
88f77cba | 10963 | /* Output a move, load or store for quad-word vectors in ARM registers. Only |
dc34db56 | 10964 | handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */ |
5b3e6663 PB |
10965 | |
10966 | const char * | |
88f77cba | 10967 | output_move_quad (rtx *operands) |
5b3e6663 | 10968 | { |
88f77cba JB |
10969 | if (REG_P (operands[0])) |
10970 | { | |
10971 | /* Load, or reg->reg move. */ | |
5b3e6663 | 10972 | |
88f77cba JB |
10973 | if (MEM_P (operands[1])) |
10974 | { | |
10975 | switch (GET_CODE (XEXP (operands[1], 0))) | |
10976 | { | |
10977 | case REG: | |
10978 | output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands); | |
10979 | break; | |
10980 | ||
10981 | case LABEL_REF: | |
10982 | case CONST: | |
10983 | output_asm_insn ("adr%?\t%0, %1", operands); | |
10984 | output_asm_insn ("ldm%(ia%)\t%0, %M0", operands); | |
10985 | break; | |
10986 | ||
10987 | default: | |
10988 | gcc_unreachable (); | |
10989 | } | |
10990 | } | |
10991 | else | |
10992 | { | |
10993 | rtx ops[2]; | |
10994 | int dest, src, i; | |
5b3e6663 | 10995 | |
88f77cba | 10996 | gcc_assert (REG_P (operands[1])); |
5b3e6663 | 10997 | |
88f77cba JB |
10998 | dest = REGNO (operands[0]); |
10999 | src = REGNO (operands[1]); | |
5b3e6663 | 11000 | |
88f77cba JB |
11001 | /* This seems pretty dumb, but hopefully GCC won't try to do it |
11002 | very often. */ | |
11003 | if (dest < src) | |
11004 | for (i = 0; i < 4; i++) | |
11005 | { | |
11006 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
11007 | ops[1] = gen_rtx_REG (SImode, src + i); | |
11008 | output_asm_insn ("mov%?\t%0, %1", ops); | |
11009 | } | |
11010 | else | |
11011 | for (i = 3; i >= 0; i--) | |
11012 | { | |
11013 | ops[0] = gen_rtx_REG (SImode, dest + i); | |
11014 | ops[1] = gen_rtx_REG (SImode, src + i); | |
11015 | output_asm_insn ("mov%?\t%0, %1", ops); | |
11016 | } | |
11017 | } | |
11018 | } | |
11019 | else | |
11020 | { | |
11021 | gcc_assert (MEM_P (operands[0])); | |
11022 | gcc_assert (REG_P (operands[1])); | |
11023 | gcc_assert (!reg_overlap_mentioned_p (operands[1], operands[0])); | |
11024 | ||
11025 | switch (GET_CODE (XEXP (operands[0], 0))) | |
11026 | { | |
11027 | case REG: | |
11028 | output_asm_insn ("stm%(ia%)\t%m0, %M1", operands); | |
11029 | break; | |
11030 | ||
11031 | default: | |
11032 | gcc_unreachable (); | |
11033 | } | |
11034 | } | |
11035 | ||
11036 | return ""; | |
11037 | } | |
11038 | ||
11039 | /* Output a VFP load or store instruction. */ | |
11040 | ||
11041 | const char * | |
11042 | output_move_vfp (rtx *operands) | |
11043 | { | |
11044 | rtx reg, mem, addr, ops[2]; | |
11045 | int load = REG_P (operands[0]); | |
11046 | int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8; | |
11047 | int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT; | |
0a2aaacc | 11048 | const char *templ; |
88f77cba JB |
11049 | char buff[50]; |
11050 | enum machine_mode mode; | |
11051 | ||
11052 | reg = operands[!load]; | |
11053 | mem = operands[load]; | |
11054 | ||
11055 | mode = GET_MODE (reg); | |
11056 | ||
11057 | gcc_assert (REG_P (reg)); | |
11058 | gcc_assert (IS_VFP_REGNUM (REGNO (reg))); | |
11059 | gcc_assert (mode == SFmode | |
11060 | || mode == DFmode | |
11061 | || mode == SImode | |
11062 | || mode == DImode | |
11063 | || (TARGET_NEON && VALID_NEON_DREG_MODE (mode))); | |
11064 | gcc_assert (MEM_P (mem)); | |
11065 | ||
11066 | addr = XEXP (mem, 0); | |
11067 | ||
11068 | switch (GET_CODE (addr)) | |
11069 | { | |
11070 | case PRE_DEC: | |
0a2aaacc | 11071 | templ = "f%smdb%c%%?\t%%0!, {%%%s1}%s"; |
88f77cba JB |
11072 | ops[0] = XEXP (addr, 0); |
11073 | ops[1] = reg; | |
5b3e6663 PB |
11074 | break; |
11075 | ||
11076 | case POST_INC: | |
0a2aaacc | 11077 | templ = "f%smia%c%%?\t%%0!, {%%%s1}%s"; |
5b3e6663 PB |
11078 | ops[0] = XEXP (addr, 0); |
11079 | ops[1] = reg; | |
11080 | break; | |
11081 | ||
11082 | default: | |
0a2aaacc | 11083 | templ = "f%s%c%%?\t%%%s0, %%1%s"; |
5b3e6663 PB |
11084 | ops[0] = reg; |
11085 | ops[1] = mem; | |
11086 | break; | |
11087 | } | |
11088 | ||
0a2aaacc | 11089 | sprintf (buff, templ, |
5b3e6663 PB |
11090 | load ? "ld" : "st", |
11091 | dp ? 'd' : 's', | |
11092 | dp ? "P" : "", | |
11093 | integer_p ? "\t%@ int" : ""); | |
11094 | output_asm_insn (buff, ops); | |
11095 | ||
11096 | return ""; | |
11097 | } | |
11098 | ||
88f77cba | 11099 | /* Output a Neon quad-word load or store, or a load or store for |
874d42b9 | 11100 | larger structure modes. |
88f77cba | 11101 | |
874d42b9 JM |
11102 | WARNING: The ordering of elements is weird in big-endian mode, |
11103 | because we use VSTM, as required by the EABI. GCC RTL defines | |
11104 | element ordering based on in-memory order. This can be differ | |
11105 | from the architectural ordering of elements within a NEON register. | |
11106 | The intrinsics defined in arm_neon.h use the NEON register element | |
11107 | ordering, not the GCC RTL element ordering. | |
88f77cba | 11108 | |
874d42b9 JM |
11109 | For example, the in-memory ordering of a big-endian a quadword |
11110 | vector with 16-bit elements when stored from register pair {d0,d1} | |
11111 | will be (lowest address first, d0[N] is NEON register element N): | |
88f77cba | 11112 | |
874d42b9 | 11113 | [d0[3], d0[2], d0[1], d0[0], d1[7], d1[6], d1[5], d1[4]] |
88f77cba | 11114 | |
874d42b9 JM |
11115 | When necessary, quadword registers (dN, dN+1) are moved to ARM |
11116 | registers from rN in the order: | |
88f77cba JB |
11117 | |
11118 | dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2) | |
11119 | ||
874d42b9 JM |
11120 | So that STM/LDM can be used on vectors in ARM registers, and the |
11121 | same memory layout will result as if VSTM/VLDM were used. */ | |
88f77cba JB |
11122 | |
11123 | const char * | |
11124 | output_move_neon (rtx *operands) | |
11125 | { | |
11126 | rtx reg, mem, addr, ops[2]; | |
11127 | int regno, load = REG_P (operands[0]); | |
0a2aaacc | 11128 | const char *templ; |
88f77cba JB |
11129 | char buff[50]; |
11130 | enum machine_mode mode; | |
11131 | ||
11132 | reg = operands[!load]; | |
11133 | mem = operands[load]; | |
11134 | ||
11135 | mode = GET_MODE (reg); | |
11136 | ||
11137 | gcc_assert (REG_P (reg)); | |
11138 | regno = REGNO (reg); | |
11139 | gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno) | |
11140 | || NEON_REGNO_OK_FOR_QUAD (regno)); | |
11141 | gcc_assert (VALID_NEON_DREG_MODE (mode) | |
11142 | || VALID_NEON_QREG_MODE (mode) | |
11143 | || VALID_NEON_STRUCT_MODE (mode)); | |
11144 | gcc_assert (MEM_P (mem)); | |
11145 | ||
11146 | addr = XEXP (mem, 0); | |
11147 | ||
11148 | /* Strip off const from addresses like (const (plus (...))). */ | |
11149 | if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS) | |
11150 | addr = XEXP (addr, 0); | |
11151 | ||
11152 | switch (GET_CODE (addr)) | |
11153 | { | |
11154 | case POST_INC: | |
0a2aaacc | 11155 | templ = "v%smia%%?\t%%0!, %%h1"; |
88f77cba JB |
11156 | ops[0] = XEXP (addr, 0); |
11157 | ops[1] = reg; | |
11158 | break; | |
11159 | ||
dc34db56 PB |
11160 | case PRE_DEC: |
11161 | /* FIXME: We should be using vld1/vst1 here in BE mode? */ | |
11162 | templ = "v%smdb%%?\t%%0!, %%h1"; | |
11163 | ops[0] = XEXP (addr, 0); | |
11164 | ops[1] = reg; | |
11165 | break; | |
11166 | ||
88f77cba JB |
11167 | case POST_MODIFY: |
11168 | /* FIXME: Not currently enabled in neon_vector_mem_operand. */ | |
11169 | gcc_unreachable (); | |
11170 | ||
11171 | case LABEL_REF: | |
11172 | case PLUS: | |
11173 | { | |
11174 | int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2; | |
11175 | int i; | |
11176 | int overlap = -1; | |
11177 | for (i = 0; i < nregs; i++) | |
11178 | { | |
11179 | /* We're only using DImode here because it's a convenient size. */ | |
11180 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i); | |
11181 | ops[1] = adjust_address (mem, SImode, 8 * i); | |
11182 | if (reg_overlap_mentioned_p (ops[0], mem)) | |
11183 | { | |
11184 | gcc_assert (overlap == -1); | |
11185 | overlap = i; | |
11186 | } | |
11187 | else | |
11188 | { | |
11189 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
11190 | output_asm_insn (buff, ops); | |
11191 | } | |
11192 | } | |
11193 | if (overlap != -1) | |
11194 | { | |
11195 | ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap); | |
11196 | ops[1] = adjust_address (mem, SImode, 8 * overlap); | |
11197 | sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st"); | |
11198 | output_asm_insn (buff, ops); | |
11199 | } | |
11200 | ||
11201 | return ""; | |
11202 | } | |
11203 | ||
11204 | default: | |
0a2aaacc | 11205 | templ = "v%smia%%?\t%%m0, %%h1"; |
88f77cba JB |
11206 | ops[0] = mem; |
11207 | ops[1] = reg; | |
11208 | } | |
11209 | ||
0a2aaacc | 11210 | sprintf (buff, templ, load ? "ld" : "st"); |
88f77cba JB |
11211 | output_asm_insn (buff, ops); |
11212 | ||
11213 | return ""; | |
11214 | } | |
11215 | ||
1d6e90ac NC |
11216 | /* Output an ADD r, s, #n where n may be too big for one instruction. |
11217 | If adding zero to one register, output nothing. */ | |
cd2b33d0 | 11218 | const char * |
e32bac5b | 11219 | output_add_immediate (rtx *operands) |
cce8749e | 11220 | { |
f3bb6135 | 11221 | HOST_WIDE_INT n = INTVAL (operands[2]); |
cce8749e CH |
11222 | |
11223 | if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) | |
11224 | { | |
11225 | if (n < 0) | |
11226 | output_multi_immediate (operands, | |
9997d19d RE |
11227 | "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, |
11228 | -n); | |
cce8749e CH |
11229 | else |
11230 | output_multi_immediate (operands, | |
9997d19d RE |
11231 | "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, |
11232 | n); | |
cce8749e | 11233 | } |
f3bb6135 RE |
11234 | |
11235 | return ""; | |
11236 | } | |
cce8749e | 11237 | |
cce8749e CH |
11238 | /* Output a multiple immediate operation. |
11239 | OPERANDS is the vector of operands referred to in the output patterns. | |
11240 | INSTR1 is the output pattern to use for the first constant. | |
11241 | INSTR2 is the output pattern to use for subsequent constants. | |
11242 | IMMED_OP is the index of the constant slot in OPERANDS. | |
11243 | N is the constant value. */ | |
cd2b33d0 | 11244 | static const char * |
e32bac5b RE |
11245 | output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, |
11246 | int immed_op, HOST_WIDE_INT n) | |
cce8749e | 11247 | { |
f3bb6135 | 11248 | #if HOST_BITS_PER_WIDE_INT > 32 |
30cf4896 | 11249 | n &= 0xffffffff; |
f3bb6135 RE |
11250 | #endif |
11251 | ||
cce8749e CH |
11252 | if (n == 0) |
11253 | { | |
1d6e90ac | 11254 | /* Quick and easy output. */ |
cce8749e | 11255 | operands[immed_op] = const0_rtx; |
1d6e90ac | 11256 | output_asm_insn (instr1, operands); |
cce8749e CH |
11257 | } |
11258 | else | |
11259 | { | |
11260 | int i; | |
cd2b33d0 | 11261 | const char * instr = instr1; |
cce8749e | 11262 | |
6354dc9b | 11263 | /* Note that n is never zero here (which would give no output). */ |
cce8749e CH |
11264 | for (i = 0; i < 32; i += 2) |
11265 | { | |
11266 | if (n & (3 << i)) | |
11267 | { | |
f3bb6135 RE |
11268 | operands[immed_op] = GEN_INT (n & (255 << i)); |
11269 | output_asm_insn (instr, operands); | |
cce8749e CH |
11270 | instr = instr2; |
11271 | i += 6; | |
11272 | } | |
11273 | } | |
11274 | } | |
f676971a | 11275 | |
f3bb6135 | 11276 | return ""; |
9997d19d | 11277 | } |
cce8749e | 11278 | |
5b3e6663 PB |
11279 | /* Return the name of a shifter operation. */ |
11280 | static const char * | |
11281 | arm_shift_nmem(enum rtx_code code) | |
11282 | { | |
11283 | switch (code) | |
11284 | { | |
11285 | case ASHIFT: | |
11286 | return ARM_LSL_NAME; | |
11287 | ||
11288 | case ASHIFTRT: | |
11289 | return "asr"; | |
11290 | ||
11291 | case LSHIFTRT: | |
11292 | return "lsr"; | |
11293 | ||
11294 | case ROTATERT: | |
11295 | return "ror"; | |
11296 | ||
11297 | default: | |
11298 | abort(); | |
11299 | } | |
11300 | } | |
11301 | ||
cce8749e CH |
11302 | /* Return the appropriate ARM instruction for the operation code. |
11303 | The returned result should not be overwritten. OP is the rtx of the | |
11304 | operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator | |
11305 | was shifted. */ | |
cd2b33d0 | 11306 | const char * |
e32bac5b | 11307 | arithmetic_instr (rtx op, int shift_first_arg) |
cce8749e | 11308 | { |
9997d19d | 11309 | switch (GET_CODE (op)) |
cce8749e CH |
11310 | { |
11311 | case PLUS: | |
f3bb6135 RE |
11312 | return "add"; |
11313 | ||
cce8749e | 11314 | case MINUS: |
f3bb6135 RE |
11315 | return shift_first_arg ? "rsb" : "sub"; |
11316 | ||
cce8749e | 11317 | case IOR: |
f3bb6135 RE |
11318 | return "orr"; |
11319 | ||
cce8749e | 11320 | case XOR: |
f3bb6135 RE |
11321 | return "eor"; |
11322 | ||
cce8749e | 11323 | case AND: |
f3bb6135 RE |
11324 | return "and"; |
11325 | ||
5b3e6663 PB |
11326 | case ASHIFT: |
11327 | case ASHIFTRT: | |
11328 | case LSHIFTRT: | |
11329 | case ROTATERT: | |
11330 | return arm_shift_nmem(GET_CODE(op)); | |
11331 | ||
cce8749e | 11332 | default: |
e6d29d15 | 11333 | gcc_unreachable (); |
cce8749e | 11334 | } |
f3bb6135 | 11335 | } |
cce8749e | 11336 | |
cce8749e CH |
11337 | /* Ensure valid constant shifts and return the appropriate shift mnemonic |
11338 | for the operation code. The returned result should not be overwritten. | |
11339 | OP is the rtx code of the shift. | |
9997d19d | 11340 | On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant |
6354dc9b | 11341 | shift. */ |
cd2b33d0 | 11342 | static const char * |
e32bac5b | 11343 | shift_op (rtx op, HOST_WIDE_INT *amountp) |
cce8749e | 11344 | { |
cd2b33d0 | 11345 | const char * mnem; |
e2c671ba | 11346 | enum rtx_code code = GET_CODE (op); |
cce8749e | 11347 | |
e6d29d15 NS |
11348 | switch (GET_CODE (XEXP (op, 1))) |
11349 | { | |
11350 | case REG: | |
11351 | case SUBREG: | |
11352 | *amountp = -1; | |
11353 | break; | |
11354 | ||
11355 | case CONST_INT: | |
11356 | *amountp = INTVAL (XEXP (op, 1)); | |
11357 | break; | |
11358 | ||
11359 | default: | |
11360 | gcc_unreachable (); | |
11361 | } | |
9997d19d | 11362 | |
e2c671ba | 11363 | switch (code) |
cce8749e | 11364 | { |
a657c98a | 11365 | case ROTATE: |
e6d29d15 | 11366 | gcc_assert (*amountp != -1); |
a657c98a | 11367 | *amountp = 32 - *amountp; |
5b3e6663 | 11368 | code = ROTATERT; |
a657c98a RE |
11369 | |
11370 | /* Fall through. */ | |
11371 | ||
5b3e6663 PB |
11372 | case ASHIFT: |
11373 | case ASHIFTRT: | |
11374 | case LSHIFTRT: | |
9997d19d | 11375 | case ROTATERT: |
5b3e6663 | 11376 | mnem = arm_shift_nmem(code); |
9997d19d RE |
11377 | break; |
11378 | ||
ff9940b0 | 11379 | case MULT: |
e2c671ba RE |
11380 | /* We never have to worry about the amount being other than a |
11381 | power of 2, since this case can never be reloaded from a reg. */ | |
e6d29d15 NS |
11382 | gcc_assert (*amountp != -1); |
11383 | *amountp = int_log2 (*amountp); | |
5b3e6663 | 11384 | return ARM_LSL_NAME; |
f3bb6135 | 11385 | |
cce8749e | 11386 | default: |
e6d29d15 | 11387 | gcc_unreachable (); |
cce8749e CH |
11388 | } |
11389 | ||
e2c671ba RE |
11390 | if (*amountp != -1) |
11391 | { | |
11392 | /* This is not 100% correct, but follows from the desire to merge | |
11393 | multiplication by a power of 2 with the recognizer for a | |
5b3e6663 | 11394 | shift. >=32 is not a valid shift for "lsl", so we must try and |
e2c671ba | 11395 | output a shift that produces the correct arithmetical result. |
ddd5a7c1 | 11396 | Using lsr #32 is identical except for the fact that the carry bit |
f676971a | 11397 | is not set correctly if we set the flags; but we never use the |
e2c671ba RE |
11398 | carry bit from such an operation, so we can ignore that. */ |
11399 | if (code == ROTATERT) | |
1d6e90ac NC |
11400 | /* Rotate is just modulo 32. */ |
11401 | *amountp &= 31; | |
e2c671ba RE |
11402 | else if (*amountp != (*amountp & 31)) |
11403 | { | |
11404 | if (code == ASHIFT) | |
11405 | mnem = "lsr"; | |
11406 | *amountp = 32; | |
11407 | } | |
11408 | ||
11409 | /* Shifts of 0 are no-ops. */ | |
11410 | if (*amountp == 0) | |
11411 | return NULL; | |
f676971a | 11412 | } |
e2c671ba | 11413 | |
9997d19d RE |
11414 | return mnem; |
11415 | } | |
cce8749e | 11416 | |
6354dc9b | 11417 | /* Obtain the shift from the POWER of two. */ |
1d6e90ac | 11418 | |
18af7313 | 11419 | static HOST_WIDE_INT |
e32bac5b | 11420 | int_log2 (HOST_WIDE_INT power) |
cce8749e | 11421 | { |
f3bb6135 | 11422 | HOST_WIDE_INT shift = 0; |
cce8749e | 11423 | |
30cf4896 | 11424 | while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) |
cce8749e | 11425 | { |
e6d29d15 | 11426 | gcc_assert (shift <= 31); |
e32bac5b | 11427 | shift++; |
cce8749e | 11428 | } |
f3bb6135 RE |
11429 | |
11430 | return shift; | |
11431 | } | |
cce8749e | 11432 | |
c5ff069d ZW |
11433 | /* Output a .ascii pseudo-op, keeping track of lengths. This is |
11434 | because /bin/as is horribly restrictive. The judgement about | |
11435 | whether or not each character is 'printable' (and can be output as | |
11436 | is) or not (and must be printed with an octal escape) must be made | |
11437 | with reference to the *host* character set -- the situation is | |
11438 | similar to that discussed in the comments above pp_c_char in | |
11439 | c-pretty-print.c. */ | |
11440 | ||
6cfc7210 | 11441 | #define MAX_ASCII_LEN 51 |
cce8749e CH |
11442 | |
11443 | void | |
e32bac5b | 11444 | output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) |
cce8749e CH |
11445 | { |
11446 | int i; | |
6cfc7210 | 11447 | int len_so_far = 0; |
cce8749e | 11448 | |
6cfc7210 | 11449 | fputs ("\t.ascii\t\"", stream); |
f676971a | 11450 | |
cce8749e CH |
11451 | for (i = 0; i < len; i++) |
11452 | { | |
1d6e90ac | 11453 | int c = p[i]; |
cce8749e | 11454 | |
6cfc7210 | 11455 | if (len_so_far >= MAX_ASCII_LEN) |
cce8749e | 11456 | { |
6cfc7210 | 11457 | fputs ("\"\n\t.ascii\t\"", stream); |
cce8749e | 11458 | len_so_far = 0; |
cce8749e CH |
11459 | } |
11460 | ||
c5ff069d | 11461 | if (ISPRINT (c)) |
cce8749e | 11462 | { |
c5ff069d | 11463 | if (c == '\\' || c == '\"') |
6cfc7210 | 11464 | { |
c5ff069d | 11465 | putc ('\\', stream); |
5895f793 | 11466 | len_so_far++; |
6cfc7210 | 11467 | } |
c5ff069d ZW |
11468 | putc (c, stream); |
11469 | len_so_far++; | |
11470 | } | |
11471 | else | |
11472 | { | |
11473 | fprintf (stream, "\\%03o", c); | |
11474 | len_so_far += 4; | |
cce8749e | 11475 | } |
cce8749e | 11476 | } |
f3bb6135 | 11477 | |
cce8749e | 11478 | fputs ("\"\n", stream); |
f3bb6135 | 11479 | } |
cce8749e | 11480 | \f |
c9ca9b88 | 11481 | /* Compute the register save mask for registers 0 through 12 |
5848830f | 11482 | inclusive. This code is used by arm_compute_save_reg_mask. */ |
b279b20a | 11483 | |
6d3d9133 | 11484 | static unsigned long |
e32bac5b | 11485 | arm_compute_save_reg0_reg12_mask (void) |
6d3d9133 | 11486 | { |
121308d4 | 11487 | unsigned long func_type = arm_current_func_type (); |
b279b20a | 11488 | unsigned long save_reg_mask = 0; |
6d3d9133 | 11489 | unsigned int reg; |
6d3d9133 | 11490 | |
7b8b8ade | 11491 | if (IS_INTERRUPT (func_type)) |
6d3d9133 | 11492 | { |
7b8b8ade | 11493 | unsigned int max_reg; |
7b8b8ade NC |
11494 | /* Interrupt functions must not corrupt any registers, |
11495 | even call clobbered ones. If this is a leaf function | |
11496 | we can just examine the registers used by the RTL, but | |
11497 | otherwise we have to assume that whatever function is | |
11498 | called might clobber anything, and so we have to save | |
11499 | all the call-clobbered registers as well. */ | |
11500 | if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) | |
11501 | /* FIQ handlers have registers r8 - r12 banked, so | |
11502 | we only need to check r0 - r7, Normal ISRs only | |
121308d4 | 11503 | bank r14 and r15, so we must check up to r12. |
7b8b8ade NC |
11504 | r13 is the stack pointer which is always preserved, |
11505 | so we do not need to consider it here. */ | |
11506 | max_reg = 7; | |
11507 | else | |
11508 | max_reg = 12; | |
f676971a | 11509 | |
7b8b8ade | 11510 | for (reg = 0; reg <= max_reg; reg++) |
6fb5fa3c DB |
11511 | if (df_regs_ever_live_p (reg) |
11512 | || (! current_function_is_leaf && call_used_regs[reg])) | |
6d3d9133 | 11513 | save_reg_mask |= (1 << reg); |
cfa01aab | 11514 | |
286d28c3 | 11515 | /* Also save the pic base register if necessary. */ |
cfa01aab PB |
11516 | if (flag_pic |
11517 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 11518 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 11519 | && crtl->uses_pic_offset_table) |
cfa01aab | 11520 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
6d3d9133 NC |
11521 | } |
11522 | else | |
11523 | { | |
11524 | /* In the normal case we only need to save those registers | |
11525 | which are call saved and which are used by this function. */ | |
ec6237e4 | 11526 | for (reg = 0; reg <= 11; reg++) |
6fb5fa3c | 11527 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
6d3d9133 NC |
11528 | save_reg_mask |= (1 << reg); |
11529 | ||
11530 | /* Handle the frame pointer as a special case. */ | |
ec6237e4 | 11531 | if (frame_pointer_needed) |
6d3d9133 NC |
11532 | save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; |
11533 | ||
11534 | /* If we aren't loading the PIC register, | |
11535 | don't stack it even though it may be live. */ | |
11536 | if (flag_pic | |
e0b92319 | 11537 | && !TARGET_SINGLE_PIC_BASE |
020a4035 | 11538 | && arm_pic_register != INVALID_REGNUM |
6fb5fa3c | 11539 | && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM) |
e3b5732b | 11540 | || crtl->uses_pic_offset_table)) |
6d3d9133 | 11541 | save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
5b3e6663 PB |
11542 | |
11543 | /* The prologue will copy SP into R0, so save it. */ | |
11544 | if (IS_STACKALIGN (func_type)) | |
11545 | save_reg_mask |= 1; | |
6d3d9133 NC |
11546 | } |
11547 | ||
c9ca9b88 | 11548 | /* Save registers so the exception handler can modify them. */ |
e3b5732b | 11549 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
11550 | { |
11551 | unsigned int i; | |
f676971a | 11552 | |
c9ca9b88 PB |
11553 | for (i = 0; ; i++) |
11554 | { | |
11555 | reg = EH_RETURN_DATA_REGNO (i); | |
11556 | if (reg == INVALID_REGNUM) | |
11557 | break; | |
11558 | save_reg_mask |= 1 << reg; | |
11559 | } | |
11560 | } | |
11561 | ||
121308d4 NC |
11562 | return save_reg_mask; |
11563 | } | |
11564 | ||
5b3e6663 | 11565 | |
35596784 AJ |
11566 | /* Compute the number of bytes used to store the static chain register on the |
11567 | stack, above the stack frame. We need to know this accurately to get the | |
11568 | alignment of the rest of the stack frame correct. */ | |
11569 | ||
11570 | static int arm_compute_static_chain_stack_bytes (void) | |
11571 | { | |
11572 | unsigned long func_type = arm_current_func_type (); | |
11573 | int static_chain_stack_bytes = 0; | |
11574 | ||
11575 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM && | |
11576 | IS_NESTED (func_type) && | |
11577 | df_regs_ever_live_p (3) && crtl->args.pretend_args_size == 0) | |
11578 | static_chain_stack_bytes = 4; | |
11579 | ||
11580 | return static_chain_stack_bytes; | |
11581 | } | |
11582 | ||
11583 | ||
121308d4 | 11584 | /* Compute a bit mask of which registers need to be |
954954d1 PB |
11585 | saved on the stack for the current function. |
11586 | This is used by arm_get_frame_offsets, which may add extra registers. */ | |
121308d4 NC |
11587 | |
11588 | static unsigned long | |
e32bac5b | 11589 | arm_compute_save_reg_mask (void) |
121308d4 NC |
11590 | { |
11591 | unsigned int save_reg_mask = 0; | |
11592 | unsigned long func_type = arm_current_func_type (); | |
5b3e6663 | 11593 | unsigned int reg; |
121308d4 NC |
11594 | |
11595 | if (IS_NAKED (func_type)) | |
11596 | /* This should never really happen. */ | |
11597 | return 0; | |
11598 | ||
11599 | /* If we are creating a stack frame, then we must save the frame pointer, | |
11600 | IP (which will hold the old stack pointer), LR and the PC. */ | |
ec6237e4 | 11601 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
121308d4 NC |
11602 | save_reg_mask |= |
11603 | (1 << ARM_HARD_FRAME_POINTER_REGNUM) | |
11604 | | (1 << IP_REGNUM) | |
11605 | | (1 << LR_REGNUM) | |
11606 | | (1 << PC_REGNUM); | |
11607 | ||
11608 | /* Volatile functions do not return, so there | |
11609 | is no need to save any other registers. */ | |
11610 | if (IS_VOLATILE (func_type)) | |
11611 | return save_reg_mask; | |
11612 | ||
11613 | save_reg_mask |= arm_compute_save_reg0_reg12_mask (); | |
11614 | ||
6d3d9133 NC |
11615 | /* Decide if we need to save the link register. |
11616 | Interrupt routines have their own banked link register, | |
11617 | so they never need to save it. | |
1768c26f | 11618 | Otherwise if we do not use the link register we do not need to save |
6d3d9133 NC |
11619 | it. If we are pushing other registers onto the stack however, we |
11620 | can save an instruction in the epilogue by pushing the link register | |
11621 | now and then popping it back into the PC. This incurs extra memory | |
72ac76be | 11622 | accesses though, so we only do it when optimizing for size, and only |
6d3d9133 | 11623 | if we know that we will not need a fancy return sequence. */ |
6fb5fa3c DB |
11624 | if (df_regs_ever_live_p (LR_REGNUM) |
11625 | || (save_reg_mask | |
11626 | && optimize_size | |
11627 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 11628 | && !crtl->calls_eh_return)) |
6d3d9133 NC |
11629 | save_reg_mask |= 1 << LR_REGNUM; |
11630 | ||
6f7ebcbb NC |
11631 | if (cfun->machine->lr_save_eliminated) |
11632 | save_reg_mask &= ~ (1 << LR_REGNUM); | |
11633 | ||
5a9335ef NC |
11634 | if (TARGET_REALLY_IWMMXT |
11635 | && ((bit_count (save_reg_mask) | |
35596784 AJ |
11636 | + ARM_NUM_INTS (crtl->args.pretend_args_size + |
11637 | arm_compute_static_chain_stack_bytes()) | |
11638 | ) % 2) != 0) | |
5a9335ef | 11639 | { |
5a9335ef NC |
11640 | /* The total number of registers that are going to be pushed |
11641 | onto the stack is odd. We need to ensure that the stack | |
11642 | is 64-bit aligned before we start to save iWMMXt registers, | |
11643 | and also before we start to create locals. (A local variable | |
11644 | might be a double or long long which we will load/store using | |
11645 | an iWMMXt instruction). Therefore we need to push another | |
11646 | ARM register, so that the stack will be 64-bit aligned. We | |
11647 | try to avoid using the arg registers (r0 -r3) as they might be | |
11648 | used to pass values in a tail call. */ | |
11649 | for (reg = 4; reg <= 12; reg++) | |
11650 | if ((save_reg_mask & (1 << reg)) == 0) | |
11651 | break; | |
11652 | ||
11653 | if (reg <= 12) | |
11654 | save_reg_mask |= (1 << reg); | |
11655 | else | |
11656 | { | |
11657 | cfun->machine->sibcall_blocked = 1; | |
11658 | save_reg_mask |= (1 << 3); | |
11659 | } | |
11660 | } | |
11661 | ||
5b3e6663 PB |
11662 | /* We may need to push an additional register for use initializing the |
11663 | PIC base register. */ | |
11664 | if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic | |
11665 | && (save_reg_mask & THUMB2_WORK_REGS) == 0) | |
11666 | { | |
11667 | reg = thumb_find_work_register (1 << 4); | |
11668 | if (!call_used_regs[reg]) | |
11669 | save_reg_mask |= (1 << reg); | |
11670 | } | |
11671 | ||
6d3d9133 NC |
11672 | return save_reg_mask; |
11673 | } | |
11674 | ||
9728c9d1 | 11675 | |
57934c39 PB |
11676 | /* Compute a bit mask of which registers need to be |
11677 | saved on the stack for the current function. */ | |
11678 | static unsigned long | |
5b3e6663 | 11679 | thumb1_compute_save_reg_mask (void) |
57934c39 PB |
11680 | { |
11681 | unsigned long mask; | |
b279b20a | 11682 | unsigned reg; |
57934c39 PB |
11683 | |
11684 | mask = 0; | |
11685 | for (reg = 0; reg < 12; reg ++) | |
6fb5fa3c | 11686 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b279b20a | 11687 | mask |= 1 << reg; |
57934c39 | 11688 | |
39c39be0 RE |
11689 | if (flag_pic |
11690 | && !TARGET_SINGLE_PIC_BASE | |
020a4035 | 11691 | && arm_pic_register != INVALID_REGNUM |
e3b5732b | 11692 | && crtl->uses_pic_offset_table) |
39c39be0 | 11693 | mask |= 1 << PIC_OFFSET_TABLE_REGNUM; |
b279b20a | 11694 | |
a2503645 RS |
11695 | /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ |
11696 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) | |
11697 | mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; | |
57934c39 | 11698 | |
b279b20a | 11699 | /* LR will also be pushed if any lo regs are pushed. */ |
57934c39 PB |
11700 | if (mask & 0xff || thumb_force_lr_save ()) |
11701 | mask |= (1 << LR_REGNUM); | |
11702 | ||
b279b20a NC |
11703 | /* Make sure we have a low work register if we need one. |
11704 | We will need one if we are going to push a high register, | |
11705 | but we are not currently intending to push a low register. */ | |
11706 | if ((mask & 0xff) == 0 | |
57934c39 | 11707 | && ((mask & 0x0f00) || TARGET_BACKTRACE)) |
b279b20a NC |
11708 | { |
11709 | /* Use thumb_find_work_register to choose which register | |
11710 | we will use. If the register is live then we will | |
11711 | have to push it. Use LAST_LO_REGNUM as our fallback | |
11712 | choice for the register to select. */ | |
11713 | reg = thumb_find_work_register (1 << LAST_LO_REGNUM); | |
19e723f4 PB |
11714 | /* Make sure the register returned by thumb_find_work_register is |
11715 | not part of the return value. */ | |
954954d1 | 11716 | if (reg * UNITS_PER_WORD <= (unsigned) arm_size_return_regs ()) |
19e723f4 | 11717 | reg = LAST_LO_REGNUM; |
b279b20a NC |
11718 | |
11719 | if (! call_used_regs[reg]) | |
11720 | mask |= 1 << reg; | |
11721 | } | |
57934c39 | 11722 | |
35596784 AJ |
11723 | /* The 504 below is 8 bytes less than 512 because there are two possible |
11724 | alignment words. We can't tell here if they will be present or not so we | |
11725 | have to play it safe and assume that they are. */ | |
11726 | if ((CALLER_INTERWORKING_SLOT_SIZE + | |
11727 | ROUND_UP_WORD (get_frame_size ()) + | |
11728 | crtl->outgoing_args_size) >= 504) | |
11729 | { | |
11730 | /* This is the same as the code in thumb1_expand_prologue() which | |
11731 | determines which register to use for stack decrement. */ | |
11732 | for (reg = LAST_ARG_REGNUM + 1; reg <= LAST_LO_REGNUM; reg++) | |
11733 | if (mask & (1 << reg)) | |
11734 | break; | |
11735 | ||
11736 | if (reg > LAST_LO_REGNUM) | |
11737 | { | |
11738 | /* Make sure we have a register available for stack decrement. */ | |
11739 | mask |= 1 << LAST_LO_REGNUM; | |
11740 | } | |
11741 | } | |
11742 | ||
57934c39 PB |
11743 | return mask; |
11744 | } | |
11745 | ||
11746 | ||
9728c9d1 PB |
11747 | /* Return the number of bytes required to save VFP registers. */ |
11748 | static int | |
11749 | arm_get_vfp_saved_size (void) | |
11750 | { | |
11751 | unsigned int regno; | |
11752 | int count; | |
11753 | int saved; | |
11754 | ||
11755 | saved = 0; | |
11756 | /* Space for saved VFP registers. */ | |
11757 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
11758 | { | |
11759 | count = 0; | |
11760 | for (regno = FIRST_VFP_REGNUM; | |
11761 | regno < LAST_VFP_REGNUM; | |
11762 | regno += 2) | |
11763 | { | |
6fb5fa3c DB |
11764 | if ((!df_regs_ever_live_p (regno) || call_used_regs[regno]) |
11765 | && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1])) | |
9728c9d1 PB |
11766 | { |
11767 | if (count > 0) | |
11768 | { | |
11769 | /* Workaround ARM10 VFPr1 bug. */ | |
11770 | if (count == 2 && !arm_arch6) | |
11771 | count++; | |
8edfc4cc | 11772 | saved += count * 8; |
9728c9d1 PB |
11773 | } |
11774 | count = 0; | |
11775 | } | |
11776 | else | |
11777 | count++; | |
11778 | } | |
11779 | if (count > 0) | |
11780 | { | |
11781 | if (count == 2 && !arm_arch6) | |
11782 | count++; | |
8edfc4cc | 11783 | saved += count * 8; |
9728c9d1 PB |
11784 | } |
11785 | } | |
11786 | return saved; | |
11787 | } | |
11788 | ||
11789 | ||
699a4925 | 11790 | /* Generate a function exit sequence. If REALLY_RETURN is false, then do |
6d3d9133 | 11791 | everything bar the final return instruction. */ |
cd2b33d0 | 11792 | const char * |
e32bac5b | 11793 | output_return_instruction (rtx operand, int really_return, int reverse) |
ff9940b0 | 11794 | { |
6d3d9133 | 11795 | char conditional[10]; |
ff9940b0 | 11796 | char instr[100]; |
b279b20a | 11797 | unsigned reg; |
6d3d9133 NC |
11798 | unsigned long live_regs_mask; |
11799 | unsigned long func_type; | |
5848830f | 11800 | arm_stack_offsets *offsets; |
e26053d1 | 11801 | |
6d3d9133 | 11802 | func_type = arm_current_func_type (); |
e2c671ba | 11803 | |
6d3d9133 | 11804 | if (IS_NAKED (func_type)) |
d5b7b3ae | 11805 | return ""; |
6d3d9133 NC |
11806 | |
11807 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) | |
e2c671ba | 11808 | { |
699a4925 RE |
11809 | /* If this function was declared non-returning, and we have |
11810 | found a tail call, then we have to trust that the called | |
11811 | function won't return. */ | |
3a5a4282 PB |
11812 | if (really_return) |
11813 | { | |
11814 | rtx ops[2]; | |
f676971a | 11815 | |
3a5a4282 PB |
11816 | /* Otherwise, trap an attempted return by aborting. */ |
11817 | ops[0] = operand; | |
f676971a | 11818 | ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" |
3a5a4282 PB |
11819 | : "abort"); |
11820 | assemble_external_libcall (ops[1]); | |
11821 | output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); | |
11822 | } | |
f676971a | 11823 | |
e2c671ba RE |
11824 | return ""; |
11825 | } | |
6d3d9133 | 11826 | |
e3b5732b | 11827 | gcc_assert (!cfun->calls_alloca || really_return); |
ff9940b0 | 11828 | |
c414f8a9 | 11829 | sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); |
d5b7b3ae | 11830 | |
934c2060 | 11831 | cfun->machine->return_used_this_function = 1; |
ff9940b0 | 11832 | |
954954d1 PB |
11833 | offsets = arm_get_frame_offsets (); |
11834 | live_regs_mask = offsets->saved_regs_mask; | |
ff9940b0 | 11835 | |
1768c26f | 11836 | if (live_regs_mask) |
6d3d9133 | 11837 | { |
1768c26f PB |
11838 | const char * return_reg; |
11839 | ||
f676971a | 11840 | /* If we do not have any special requirements for function exit |
a15908a4 | 11841 | (e.g. interworking) then we can load the return address |
1768c26f PB |
11842 | directly into the PC. Otherwise we must load it into LR. */ |
11843 | if (really_return | |
a15908a4 | 11844 | && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK)) |
1768c26f | 11845 | return_reg = reg_names[PC_REGNUM]; |
6d3d9133 | 11846 | else |
1768c26f PB |
11847 | return_reg = reg_names[LR_REGNUM]; |
11848 | ||
6d3d9133 | 11849 | if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) |
b034930f ILT |
11850 | { |
11851 | /* There are three possible reasons for the IP register | |
11852 | being saved. 1) a stack frame was created, in which case | |
11853 | IP contains the old stack pointer, or 2) an ISR routine | |
11854 | corrupted it, or 3) it was saved to align the stack on | |
11855 | iWMMXt. In case 1, restore IP into SP, otherwise just | |
11856 | restore IP. */ | |
11857 | if (frame_pointer_needed) | |
11858 | { | |
11859 | live_regs_mask &= ~ (1 << IP_REGNUM); | |
11860 | live_regs_mask |= (1 << SP_REGNUM); | |
11861 | } | |
11862 | else | |
e6d29d15 | 11863 | gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); |
b034930f | 11864 | } |
f3bb6135 | 11865 | |
3a7731fd PB |
11866 | /* On some ARM architectures it is faster to use LDR rather than |
11867 | LDM to load a single register. On other architectures, the | |
11868 | cost is the same. In 26 bit mode, or for exception handlers, | |
11869 | we have to use LDM to load the PC so that the CPSR is also | |
11870 | restored. */ | |
11871 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) | |
b279b20a NC |
11872 | if (live_regs_mask == (1U << reg)) |
11873 | break; | |
11874 | ||
3a7731fd PB |
11875 | if (reg <= LAST_ARM_REGNUM |
11876 | && (reg != LR_REGNUM | |
f676971a | 11877 | || ! really_return |
61f0ccff | 11878 | || ! IS_INTERRUPT (func_type))) |
3a7731fd | 11879 | { |
f676971a | 11880 | sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, |
3a7731fd | 11881 | (reg == LR_REGNUM) ? return_reg : reg_names[reg]); |
6d3d9133 | 11882 | } |
ff9940b0 | 11883 | else |
1d5473cb | 11884 | { |
1768c26f PB |
11885 | char *p; |
11886 | int first = 1; | |
6d3d9133 | 11887 | |
699a4925 RE |
11888 | /* Generate the load multiple instruction to restore the |
11889 | registers. Note we can get here, even if | |
11890 | frame_pointer_needed is true, but only if sp already | |
11891 | points to the base of the saved core registers. */ | |
11892 | if (live_regs_mask & (1 << SP_REGNUM)) | |
a72d4945 | 11893 | { |
5848830f PB |
11894 | unsigned HOST_WIDE_INT stack_adjust; |
11895 | ||
5848830f | 11896 | stack_adjust = offsets->outgoing_args - offsets->saved_regs; |
e6d29d15 | 11897 | gcc_assert (stack_adjust == 0 || stack_adjust == 4); |
a72d4945 | 11898 | |
5b3e6663 | 11899 | if (stack_adjust && arm_arch5 && TARGET_ARM) |
a72d4945 RE |
11900 | sprintf (instr, "ldm%sib\t%%|sp, {", conditional); |
11901 | else | |
11902 | { | |
b279b20a NC |
11903 | /* If we can't use ldmib (SA110 bug), |
11904 | then try to pop r3 instead. */ | |
a72d4945 RE |
11905 | if (stack_adjust) |
11906 | live_regs_mask |= 1 << 3; | |
11907 | sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); | |
11908 | } | |
11909 | } | |
da6558fd | 11910 | else |
1768c26f PB |
11911 | sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); |
11912 | ||
11913 | p = instr + strlen (instr); | |
6d3d9133 | 11914 | |
1768c26f PB |
11915 | for (reg = 0; reg <= SP_REGNUM; reg++) |
11916 | if (live_regs_mask & (1 << reg)) | |
11917 | { | |
11918 | int l = strlen (reg_names[reg]); | |
11919 | ||
11920 | if (first) | |
11921 | first = 0; | |
11922 | else | |
11923 | { | |
11924 | memcpy (p, ", ", 2); | |
11925 | p += 2; | |
11926 | } | |
11927 | ||
11928 | memcpy (p, "%|", 2); | |
11929 | memcpy (p + 2, reg_names[reg], l); | |
11930 | p += l + 2; | |
11931 | } | |
f676971a | 11932 | |
1768c26f PB |
11933 | if (live_regs_mask & (1 << LR_REGNUM)) |
11934 | { | |
b17fe233 | 11935 | sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); |
61f0ccff RE |
11936 | /* If returning from an interrupt, restore the CPSR. */ |
11937 | if (IS_INTERRUPT (func_type)) | |
b17fe233 | 11938 | strcat (p, "^"); |
1768c26f PB |
11939 | } |
11940 | else | |
11941 | strcpy (p, "}"); | |
1d5473cb | 11942 | } |
da6558fd | 11943 | |
1768c26f PB |
11944 | output_asm_insn (instr, & operand); |
11945 | ||
3a7731fd PB |
11946 | /* See if we need to generate an extra instruction to |
11947 | perform the actual function return. */ | |
11948 | if (really_return | |
11949 | && func_type != ARM_FT_INTERWORKED | |
11950 | && (live_regs_mask & (1 << LR_REGNUM)) != 0) | |
da6558fd | 11951 | { |
3a7731fd PB |
11952 | /* The return has already been handled |
11953 | by loading the LR into the PC. */ | |
11954 | really_return = 0; | |
da6558fd | 11955 | } |
ff9940b0 | 11956 | } |
e26053d1 | 11957 | |
1768c26f | 11958 | if (really_return) |
ff9940b0 | 11959 | { |
6d3d9133 NC |
11960 | switch ((int) ARM_FUNC_TYPE (func_type)) |
11961 | { | |
11962 | case ARM_FT_ISR: | |
11963 | case ARM_FT_FIQ: | |
5b3e6663 | 11964 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11965 | sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); |
11966 | break; | |
11967 | ||
11968 | case ARM_FT_INTERWORKED: | |
11969 | sprintf (instr, "bx%s\t%%|lr", conditional); | |
11970 | break; | |
11971 | ||
11972 | case ARM_FT_EXCEPTION: | |
5b3e6663 | 11973 | /* ??? This is wrong for unified assembly syntax. */ |
6d3d9133 NC |
11974 | sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); |
11975 | break; | |
11976 | ||
11977 | default: | |
68d560d4 RE |
11978 | /* Use bx if it's available. */ |
11979 | if (arm_arch5 || arm_arch4t) | |
f676971a | 11980 | sprintf (instr, "bx%s\t%%|lr", conditional); |
1768c26f | 11981 | else |
61f0ccff | 11982 | sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); |
6d3d9133 NC |
11983 | break; |
11984 | } | |
1768c26f PB |
11985 | |
11986 | output_asm_insn (instr, & operand); | |
ff9940b0 | 11987 | } |
f3bb6135 | 11988 | |
ff9940b0 RE |
11989 | return ""; |
11990 | } | |
11991 | ||
ef179a26 NC |
11992 | /* Write the function name into the code section, directly preceding |
11993 | the function prologue. | |
11994 | ||
11995 | Code will be output similar to this: | |
11996 | t0 | |
11997 | .ascii "arm_poke_function_name", 0 | |
11998 | .align | |
11999 | t1 | |
12000 | .word 0xff000000 + (t1 - t0) | |
12001 | arm_poke_function_name | |
12002 | mov ip, sp | |
12003 | stmfd sp!, {fp, ip, lr, pc} | |
12004 | sub fp, ip, #4 | |
12005 | ||
12006 | When performing a stack backtrace, code can inspect the value | |
12007 | of 'pc' stored at 'fp' + 0. If the trace function then looks | |
12008 | at location pc - 12 and the top 8 bits are set, then we know | |
12009 | that there is a function name embedded immediately preceding this | |
12010 | location and has length ((pc[-3]) & 0xff000000). | |
12011 | ||
12012 | We assume that pc is declared as a pointer to an unsigned long. | |
12013 | ||
12014 | It is of no benefit to output the function name if we are assembling | |
12015 | a leaf function. These function types will not contain a stack | |
12016 | backtrace structure, therefore it is not possible to determine the | |
12017 | function name. */ | |
ef179a26 | 12018 | void |
e32bac5b | 12019 | arm_poke_function_name (FILE *stream, const char *name) |
ef179a26 NC |
12020 | { |
12021 | unsigned long alignlength; | |
12022 | unsigned long length; | |
12023 | rtx x; | |
12024 | ||
d5b7b3ae | 12025 | length = strlen (name) + 1; |
0c2ca901 | 12026 | alignlength = ROUND_UP_WORD (length); |
f676971a | 12027 | |
949d79eb | 12028 | ASM_OUTPUT_ASCII (stream, name, length); |
ef179a26 | 12029 | ASM_OUTPUT_ALIGN (stream, 2); |
30cf4896 | 12030 | x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); |
301d03af | 12031 | assemble_aligned_integer (UNITS_PER_WORD, x); |
ef179a26 NC |
12032 | } |
12033 | ||
6d3d9133 NC |
12034 | /* Place some comments into the assembler stream |
12035 | describing the current function. */ | |
08c148a8 | 12036 | static void |
e32bac5b | 12037 | arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) |
cce8749e | 12038 | { |
6d3d9133 | 12039 | unsigned long func_type; |
08c148a8 | 12040 | |
5b3e6663 | 12041 | if (TARGET_THUMB1) |
08c148a8 | 12042 | { |
5b3e6663 | 12043 | thumb1_output_function_prologue (f, frame_size); |
08c148a8 NB |
12044 | return; |
12045 | } | |
f676971a | 12046 | |
6d3d9133 | 12047 | /* Sanity check. */ |
e6d29d15 | 12048 | gcc_assert (!arm_ccfsm_state && !arm_target_insn); |
31fdb4d5 | 12049 | |
6d3d9133 | 12050 | func_type = arm_current_func_type (); |
f676971a | 12051 | |
6d3d9133 NC |
12052 | switch ((int) ARM_FUNC_TYPE (func_type)) |
12053 | { | |
12054 | default: | |
12055 | case ARM_FT_NORMAL: | |
12056 | break; | |
12057 | case ARM_FT_INTERWORKED: | |
12058 | asm_fprintf (f, "\t%@ Function supports interworking.\n"); | |
12059 | break; | |
6d3d9133 NC |
12060 | case ARM_FT_ISR: |
12061 | asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); | |
12062 | break; | |
12063 | case ARM_FT_FIQ: | |
12064 | asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); | |
12065 | break; | |
12066 | case ARM_FT_EXCEPTION: | |
12067 | asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); | |
12068 | break; | |
12069 | } | |
f676971a | 12070 | |
6d3d9133 NC |
12071 | if (IS_NAKED (func_type)) |
12072 | asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); | |
12073 | ||
12074 | if (IS_VOLATILE (func_type)) | |
12075 | asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); | |
12076 | ||
12077 | if (IS_NESTED (func_type)) | |
12078 | asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); | |
5b3e6663 PB |
12079 | if (IS_STACKALIGN (func_type)) |
12080 | asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n"); | |
f676971a | 12081 | |
c53dddc2 | 12082 | asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", |
38173d38 JH |
12083 | crtl->args.size, |
12084 | crtl->args.pretend_args_size, frame_size); | |
6d3d9133 | 12085 | |
3cb66fd7 | 12086 | asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", |
dd18ae56 | 12087 | frame_pointer_needed, |
3cb66fd7 | 12088 | cfun->machine->uses_anonymous_args); |
cce8749e | 12089 | |
6f7ebcbb NC |
12090 | if (cfun->machine->lr_save_eliminated) |
12091 | asm_fprintf (f, "\t%@ link register save eliminated.\n"); | |
12092 | ||
e3b5732b | 12093 | if (crtl->calls_eh_return) |
c9ca9b88 PB |
12094 | asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); |
12095 | ||
f3bb6135 | 12096 | } |
cce8749e | 12097 | |
cd2b33d0 | 12098 | const char * |
a72d4945 | 12099 | arm_output_epilogue (rtx sibling) |
cce8749e | 12100 | { |
949d79eb | 12101 | int reg; |
6f7ebcbb | 12102 | unsigned long saved_regs_mask; |
6d3d9133 | 12103 | unsigned long func_type; |
f676971a | 12104 | /* Floats_offset is the offset from the "virtual" frame. In an APCS |
c882c7ac RE |
12105 | frame that is $fp + 4 for a non-variadic function. */ |
12106 | int floats_offset = 0; | |
cce8749e | 12107 | rtx operands[3]; |
d5b7b3ae | 12108 | FILE * f = asm_out_file; |
5a9335ef | 12109 | unsigned int lrm_count = 0; |
a72d4945 | 12110 | int really_return = (sibling == NULL); |
9b66ebb1 | 12111 | int start_reg; |
5848830f | 12112 | arm_stack_offsets *offsets; |
cce8749e | 12113 | |
6d3d9133 NC |
12114 | /* If we have already generated the return instruction |
12115 | then it is futile to generate anything else. */ | |
934c2060 RR |
12116 | if (use_return_insn (FALSE, sibling) && |
12117 | (cfun->machine->return_used_this_function != 0)) | |
949d79eb | 12118 | return ""; |
cce8749e | 12119 | |
6d3d9133 | 12120 | func_type = arm_current_func_type (); |
d5b7b3ae | 12121 | |
6d3d9133 NC |
12122 | if (IS_NAKED (func_type)) |
12123 | /* Naked functions don't have epilogues. */ | |
12124 | return ""; | |
0616531f | 12125 | |
6d3d9133 | 12126 | if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) |
e2c671ba | 12127 | { |
86efdc8e | 12128 | rtx op; |
f676971a | 12129 | |
6d3d9133 | 12130 | /* A volatile function should never return. Call abort. */ |
ed0e6530 | 12131 | op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); |
2b835d68 | 12132 | assemble_external_libcall (op); |
e2c671ba | 12133 | output_asm_insn ("bl\t%a0", &op); |
f676971a | 12134 | |
949d79eb | 12135 | return ""; |
e2c671ba RE |
12136 | } |
12137 | ||
e6d29d15 NS |
12138 | /* If we are throwing an exception, then we really must be doing a |
12139 | return, so we can't tail-call. */ | |
e3b5732b | 12140 | gcc_assert (!crtl->calls_eh_return || really_return); |
f676971a | 12141 | |
5848830f | 12142 | offsets = arm_get_frame_offsets (); |
954954d1 | 12143 | saved_regs_mask = offsets->saved_regs_mask; |
5a9335ef NC |
12144 | |
12145 | if (TARGET_IWMMXT) | |
12146 | lrm_count = bit_count (saved_regs_mask); | |
12147 | ||
5848830f | 12148 | floats_offset = offsets->saved_args; |
6d3d9133 | 12149 | /* Compute how far away the floats will be. */ |
5a9335ef | 12150 | for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) |
6f7ebcbb | 12151 | if (saved_regs_mask & (1 << reg)) |
6ed30148 | 12152 | floats_offset += 4; |
f676971a | 12153 | |
ec6237e4 | 12154 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) |
cce8749e | 12155 | { |
9b66ebb1 | 12156 | /* This variable is for the Virtual Frame Pointer, not VFP regs. */ |
5848830f | 12157 | int vfp_offset = offsets->frame; |
c882c7ac | 12158 | |
29ad9694 | 12159 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 12160 | { |
9b66ebb1 | 12161 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
6fb5fa3c | 12162 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
12163 | { |
12164 | floats_offset += 12; | |
f676971a | 12165 | asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", |
c882c7ac | 12166 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
12167 | } |
12168 | } | |
12169 | else | |
12170 | { | |
9b66ebb1 | 12171 | start_reg = LAST_FPA_REGNUM; |
b111229a | 12172 | |
9b66ebb1 | 12173 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) |
b111229a | 12174 | { |
6fb5fa3c | 12175 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
12176 | { |
12177 | floats_offset += 12; | |
f676971a | 12178 | |
6354dc9b | 12179 | /* We can't unstack more than four registers at once. */ |
b111229a RE |
12180 | if (start_reg - reg == 3) |
12181 | { | |
dd18ae56 | 12182 | asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", |
c882c7ac | 12183 | reg, FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
12184 | start_reg = reg - 1; |
12185 | } | |
12186 | } | |
12187 | else | |
12188 | { | |
12189 | if (reg != start_reg) | |
dd18ae56 NC |
12190 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
12191 | reg + 1, start_reg - reg, | |
c882c7ac | 12192 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a RE |
12193 | start_reg = reg - 1; |
12194 | } | |
12195 | } | |
12196 | ||
12197 | /* Just in case the last register checked also needs unstacking. */ | |
12198 | if (reg != start_reg) | |
dd18ae56 NC |
12199 | asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", |
12200 | reg + 1, start_reg - reg, | |
c882c7ac | 12201 | FP_REGNUM, floats_offset - vfp_offset); |
b111229a | 12202 | } |
6d3d9133 | 12203 | |
9b66ebb1 PB |
12204 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
12205 | { | |
9728c9d1 | 12206 | int saved_size; |
9b66ebb1 | 12207 | |
8edfc4cc MS |
12208 | /* The fldmd insns do not have base+offset addressing |
12209 | modes, so we use IP to hold the address. */ | |
9728c9d1 | 12210 | saved_size = arm_get_vfp_saved_size (); |
9b66ebb1 | 12211 | |
9728c9d1 | 12212 | if (saved_size > 0) |
9b66ebb1 | 12213 | { |
9728c9d1 | 12214 | floats_offset += saved_size; |
9b66ebb1 PB |
12215 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, |
12216 | FP_REGNUM, floats_offset - vfp_offset); | |
12217 | } | |
12218 | start_reg = FIRST_VFP_REGNUM; | |
12219 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12220 | { | |
6fb5fa3c DB |
12221 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12222 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
12223 | { |
12224 | if (start_reg != reg) | |
8edfc4cc | 12225 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
12226 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12227 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12228 | start_reg = reg + 2; |
12229 | } | |
12230 | } | |
12231 | if (start_reg != reg) | |
8edfc4cc | 12232 | vfp_output_fldmd (f, IP_REGNUM, |
9728c9d1 PB |
12233 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12234 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12235 | } |
12236 | ||
5a9335ef NC |
12237 | if (TARGET_IWMMXT) |
12238 | { | |
12239 | /* The frame pointer is guaranteed to be non-double-word aligned. | |
12240 | This is because it is set to (old_stack_pointer - 4) and the | |
12241 | old_stack_pointer was double word aligned. Thus the offset to | |
12242 | the iWMMXt registers to be loaded must also be non-double-word | |
12243 | sized, so that the resultant address *is* double-word aligned. | |
12244 | We can ignore floats_offset since that was already included in | |
12245 | the live_regs_mask. */ | |
12246 | lrm_count += (lrm_count % 2 ? 2 : 1); | |
f676971a | 12247 | |
01d4c813 | 12248 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) |
6fb5fa3c | 12249 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5a9335ef | 12250 | { |
f676971a | 12251 | asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", |
5a9335ef | 12252 | reg, FP_REGNUM, lrm_count * 4); |
f676971a | 12253 | lrm_count += 2; |
5a9335ef NC |
12254 | } |
12255 | } | |
12256 | ||
6f7ebcbb | 12257 | /* saved_regs_mask should contain the IP, which at the time of stack |
6d3d9133 NC |
12258 | frame generation actually contains the old stack pointer. So a |
12259 | quick way to unwind the stack is just pop the IP register directly | |
12260 | into the stack pointer. */ | |
e6d29d15 | 12261 | gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); |
6f7ebcbb NC |
12262 | saved_regs_mask &= ~ (1 << IP_REGNUM); |
12263 | saved_regs_mask |= (1 << SP_REGNUM); | |
6d3d9133 | 12264 | |
6f7ebcbb | 12265 | /* There are two registers left in saved_regs_mask - LR and PC. We |
6d3d9133 NC |
12266 | only need to restore the LR register (the return address), but to |
12267 | save time we can load it directly into the PC, unless we need a | |
12268 | special function exit sequence, or we are not really returning. */ | |
c9ca9b88 PB |
12269 | if (really_return |
12270 | && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL | |
e3b5732b | 12271 | && !crtl->calls_eh_return) |
6d3d9133 NC |
12272 | /* Delete the LR from the register mask, so that the LR on |
12273 | the stack is loaded into the PC in the register mask. */ | |
6f7ebcbb | 12274 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
b111229a | 12275 | else |
6f7ebcbb | 12276 | saved_regs_mask &= ~ (1 << PC_REGNUM); |
efc2515b RE |
12277 | |
12278 | /* We must use SP as the base register, because SP is one of the | |
12279 | registers being restored. If an interrupt or page fault | |
12280 | happens in the ldm instruction, the SP might or might not | |
12281 | have been restored. That would be bad, as then SP will no | |
12282 | longer indicate the safe area of stack, and we can get stack | |
12283 | corruption. Using SP as the base register means that it will | |
12284 | be reset correctly to the original value, should an interrupt | |
699a4925 RE |
12285 | occur. If the stack pointer already points at the right |
12286 | place, then omit the subtraction. */ | |
5848830f | 12287 | if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) |
e3b5732b | 12288 | || cfun->calls_alloca) |
699a4925 RE |
12289 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, |
12290 | 4 * bit_count (saved_regs_mask)); | |
a15908a4 | 12291 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0); |
7b8b8ade NC |
12292 | |
12293 | if (IS_INTERRUPT (func_type)) | |
12294 | /* Interrupt handlers will have pushed the | |
12295 | IP onto the stack, so restore it now. */ | |
a15908a4 | 12296 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0); |
cce8749e CH |
12297 | } |
12298 | else | |
12299 | { | |
ec6237e4 PB |
12300 | /* This branch is executed for ARM mode (non-apcs frames) and |
12301 | Thumb-2 mode. Frame layout is essentially the same for those | |
12302 | cases, except that in ARM mode frame pointer points to the | |
12303 | first saved register, while in Thumb-2 mode the frame pointer points | |
12304 | to the last saved register. | |
12305 | ||
12306 | It is possible to make frame pointer point to last saved | |
12307 | register in both cases, and remove some conditionals below. | |
12308 | That means that fp setup in prologue would be just "mov fp, sp" | |
12309 | and sp restore in epilogue would be just "mov sp, fp", whereas | |
12310 | now we have to use add/sub in those cases. However, the value | |
12311 | of that would be marginal, as both mov and add/sub are 32-bit | |
12312 | in ARM mode, and it would require extra conditionals | |
12313 | in arm_expand_prologue to distingish ARM-apcs-frame case | |
12314 | (where frame pointer is required to point at first register) | |
12315 | and ARM-non-apcs-frame. Therefore, such change is postponed | |
12316 | until real need arise. */ | |
f0b4bdd5 | 12317 | unsigned HOST_WIDE_INT amount; |
a15908a4 | 12318 | int rfe; |
d2288d8d | 12319 | /* Restore stack pointer if necessary. */ |
ec6237e4 | 12320 | if (TARGET_ARM && frame_pointer_needed) |
5b3e6663 PB |
12321 | { |
12322 | operands[0] = stack_pointer_rtx; | |
ec6237e4 PB |
12323 | operands[1] = hard_frame_pointer_rtx; |
12324 | ||
12325 | operands[2] = GEN_INT (offsets->frame - offsets->saved_regs); | |
12326 | output_add_immediate (operands); | |
5b3e6663 | 12327 | } |
ec6237e4 | 12328 | else |
5b3e6663 | 12329 | { |
ec6237e4 PB |
12330 | if (frame_pointer_needed) |
12331 | { | |
12332 | /* For Thumb-2 restore sp from the frame pointer. | |
12333 | Operand restrictions mean we have to incrememnt FP, then copy | |
12334 | to SP. */ | |
12335 | amount = offsets->locals_base - offsets->saved_regs; | |
12336 | operands[0] = hard_frame_pointer_rtx; | |
12337 | } | |
12338 | else | |
12339 | { | |
954954d1 | 12340 | unsigned long count; |
ec6237e4 PB |
12341 | operands[0] = stack_pointer_rtx; |
12342 | amount = offsets->outgoing_args - offsets->saved_regs; | |
954954d1 PB |
12343 | /* pop call clobbered registers if it avoids a |
12344 | separate stack adjustment. */ | |
12345 | count = offsets->saved_regs - offsets->saved_args; | |
12346 | if (optimize_size | |
12347 | && count != 0 | |
e3b5732b | 12348 | && !crtl->calls_eh_return |
954954d1 PB |
12349 | && bit_count(saved_regs_mask) * 4 == count |
12350 | && !IS_INTERRUPT (func_type) | |
e3b5732b | 12351 | && !crtl->tail_call_emit) |
954954d1 PB |
12352 | { |
12353 | unsigned long mask; | |
12354 | mask = (1 << (arm_size_return_regs() / 4)) - 1; | |
12355 | mask ^= 0xf; | |
12356 | mask &= ~saved_regs_mask; | |
12357 | reg = 0; | |
12358 | while (bit_count (mask) * 4 > amount) | |
12359 | { | |
12360 | while ((mask & (1 << reg)) == 0) | |
12361 | reg++; | |
12362 | mask &= ~(1 << reg); | |
12363 | } | |
12364 | if (bit_count (mask) * 4 == amount) { | |
12365 | amount = 0; | |
12366 | saved_regs_mask |= mask; | |
12367 | } | |
12368 | } | |
ec6237e4 PB |
12369 | } |
12370 | ||
12371 | if (amount) | |
12372 | { | |
12373 | operands[1] = operands[0]; | |
12374 | operands[2] = GEN_INT (amount); | |
12375 | output_add_immediate (operands); | |
12376 | } | |
12377 | if (frame_pointer_needed) | |
12378 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
12379 | SP_REGNUM, HARD_FRAME_POINTER_REGNUM); | |
d2288d8d TG |
12380 | } |
12381 | ||
29ad9694 | 12382 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) |
b111229a | 12383 | { |
9b66ebb1 | 12384 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
6fb5fa3c | 12385 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
dd18ae56 NC |
12386 | asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", |
12387 | reg, SP_REGNUM); | |
b111229a RE |
12388 | } |
12389 | else | |
12390 | { | |
9b66ebb1 | 12391 | start_reg = FIRST_FPA_REGNUM; |
b111229a | 12392 | |
9b66ebb1 | 12393 | for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) |
b111229a | 12394 | { |
6fb5fa3c | 12395 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
b111229a RE |
12396 | { |
12397 | if (reg - start_reg == 3) | |
12398 | { | |
dd18ae56 NC |
12399 | asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", |
12400 | start_reg, SP_REGNUM); | |
b111229a RE |
12401 | start_reg = reg + 1; |
12402 | } | |
12403 | } | |
12404 | else | |
12405 | { | |
12406 | if (reg != start_reg) | |
dd18ae56 NC |
12407 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
12408 | start_reg, reg - start_reg, | |
12409 | SP_REGNUM); | |
f676971a | 12410 | |
b111229a RE |
12411 | start_reg = reg + 1; |
12412 | } | |
12413 | } | |
12414 | ||
12415 | /* Just in case the last register checked also needs unstacking. */ | |
12416 | if (reg != start_reg) | |
dd18ae56 NC |
12417 | asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", |
12418 | start_reg, reg - start_reg, SP_REGNUM); | |
b111229a RE |
12419 | } |
12420 | ||
9b66ebb1 PB |
12421 | if (TARGET_HARD_FLOAT && TARGET_VFP) |
12422 | { | |
12423 | start_reg = FIRST_VFP_REGNUM; | |
12424 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
12425 | { | |
6fb5fa3c DB |
12426 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
12427 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
9b66ebb1 PB |
12428 | { |
12429 | if (start_reg != reg) | |
8edfc4cc | 12430 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
12431 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12432 | (reg - start_reg) / 2); | |
9b66ebb1 PB |
12433 | start_reg = reg + 2; |
12434 | } | |
12435 | } | |
12436 | if (start_reg != reg) | |
8edfc4cc | 12437 | vfp_output_fldmd (f, SP_REGNUM, |
9728c9d1 PB |
12438 | (start_reg - FIRST_VFP_REGNUM) / 2, |
12439 | (reg - start_reg) / 2); | |
9b66ebb1 | 12440 | } |
5a9335ef NC |
12441 | if (TARGET_IWMMXT) |
12442 | for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) | |
6fb5fa3c | 12443 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
01d4c813 | 12444 | asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); |
5a9335ef | 12445 | |
6d3d9133 | 12446 | /* If we can, restore the LR into the PC. */ |
a15908a4 PB |
12447 | if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED |
12448 | && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) | |
5b3e6663 | 12449 | && !IS_STACKALIGN (func_type) |
6d3d9133 | 12450 | && really_return |
38173d38 | 12451 | && crtl->args.pretend_args_size == 0 |
c9ca9b88 | 12452 | && saved_regs_mask & (1 << LR_REGNUM) |
e3b5732b | 12453 | && !crtl->calls_eh_return) |
cce8749e | 12454 | { |
6f7ebcbb NC |
12455 | saved_regs_mask &= ~ (1 << LR_REGNUM); |
12456 | saved_regs_mask |= (1 << PC_REGNUM); | |
a15908a4 | 12457 | rfe = IS_INTERRUPT (func_type); |
6d3d9133 | 12458 | } |
a15908a4 PB |
12459 | else |
12460 | rfe = 0; | |
d5b7b3ae | 12461 | |
6d3d9133 | 12462 | /* Load the registers off the stack. If we only have one register |
5b3e6663 PB |
12463 | to load use the LDR instruction - it is faster. For Thumb-2 |
12464 | always use pop and the assembler will pick the best instruction.*/ | |
a15908a4 PB |
12465 | if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM) |
12466 | && !IS_INTERRUPT(func_type)) | |
6d3d9133 | 12467 | { |
c9ca9b88 | 12468 | asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); |
cce8749e | 12469 | } |
6f7ebcbb | 12470 | else if (saved_regs_mask) |
f1acdf8b NC |
12471 | { |
12472 | if (saved_regs_mask & (1 << SP_REGNUM)) | |
12473 | /* Note - write back to the stack register is not enabled | |
112cdef5 | 12474 | (i.e. "ldmfd sp!..."). We know that the stack pointer is |
f1acdf8b NC |
12475 | in the list of registers and if we add writeback the |
12476 | instruction becomes UNPREDICTABLE. */ | |
a15908a4 PB |
12477 | print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, |
12478 | rfe); | |
5b3e6663 | 12479 | else if (TARGET_ARM) |
a15908a4 PB |
12480 | print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask, |
12481 | rfe); | |
f1acdf8b | 12482 | else |
a15908a4 | 12483 | print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0); |
f1acdf8b | 12484 | } |
6d3d9133 | 12485 | |
38173d38 | 12486 | if (crtl->args.pretend_args_size) |
cce8749e | 12487 | { |
6d3d9133 NC |
12488 | /* Unwind the pre-pushed regs. */ |
12489 | operands[0] = operands[1] = stack_pointer_rtx; | |
38173d38 | 12490 | operands[2] = GEN_INT (crtl->args.pretend_args_size); |
6d3d9133 NC |
12491 | output_add_immediate (operands); |
12492 | } | |
12493 | } | |
32de079a | 12494 | |
2966b00e | 12495 | /* We may have already restored PC directly from the stack. */ |
0cc3dda8 | 12496 | if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) |
6d3d9133 | 12497 | return ""; |
d5b7b3ae | 12498 | |
c9ca9b88 | 12499 | /* Stack adjustment for exception handler. */ |
e3b5732b | 12500 | if (crtl->calls_eh_return) |
f676971a | 12501 | asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, |
c9ca9b88 PB |
12502 | ARM_EH_STACKADJ_REGNUM); |
12503 | ||
6d3d9133 NC |
12504 | /* Generate the return instruction. */ |
12505 | switch ((int) ARM_FUNC_TYPE (func_type)) | |
12506 | { | |
6d3d9133 NC |
12507 | case ARM_FT_ISR: |
12508 | case ARM_FT_FIQ: | |
12509 | asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); | |
12510 | break; | |
12511 | ||
12512 | case ARM_FT_EXCEPTION: | |
12513 | asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
12514 | break; | |
12515 | ||
12516 | case ARM_FT_INTERWORKED: | |
12517 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
12518 | break; | |
12519 | ||
12520 | default: | |
5b3e6663 PB |
12521 | if (IS_STACKALIGN (func_type)) |
12522 | { | |
12523 | /* See comment in arm_expand_prologue. */ | |
12524 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0); | |
12525 | } | |
68d560d4 RE |
12526 | if (arm_arch5 || arm_arch4t) |
12527 | asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); | |
12528 | else | |
12529 | asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); | |
6d3d9133 | 12530 | break; |
cce8749e | 12531 | } |
f3bb6135 | 12532 | |
949d79eb RE |
12533 | return ""; |
12534 | } | |
12535 | ||
08c148a8 | 12536 | static void |
e32bac5b | 12537 | arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
5848830f | 12538 | HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) |
949d79eb | 12539 | { |
5848830f PB |
12540 | arm_stack_offsets *offsets; |
12541 | ||
5b3e6663 | 12542 | if (TARGET_THUMB1) |
d5b7b3ae | 12543 | { |
b12a00f1 RE |
12544 | int regno; |
12545 | ||
12546 | /* Emit any call-via-reg trampolines that are needed for v4t support | |
12547 | of call_reg and call_value_reg type insns. */ | |
57ecec57 | 12548 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
12549 | { |
12550 | rtx label = cfun->machine->call_via[regno]; | |
12551 | ||
12552 | if (label != NULL) | |
12553 | { | |
d6b5193b | 12554 | switch_to_section (function_section (current_function_decl)); |
b12a00f1 RE |
12555 | targetm.asm_out.internal_label (asm_out_file, "L", |
12556 | CODE_LABEL_NUMBER (label)); | |
12557 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
12558 | } | |
12559 | } | |
12560 | ||
d5b7b3ae RE |
12561 | /* ??? Probably not safe to set this here, since it assumes that a |
12562 | function will be emitted as assembly immediately after we generate | |
12563 | RTL for it. This does not happen for inline functions. */ | |
934c2060 | 12564 | cfun->machine->return_used_this_function = 0; |
d5b7b3ae | 12565 | } |
5b3e6663 | 12566 | else /* TARGET_32BIT */ |
d5b7b3ae | 12567 | { |
0977774b | 12568 | /* We need to take into account any stack-frame rounding. */ |
5848830f | 12569 | offsets = arm_get_frame_offsets (); |
0977774b | 12570 | |
e6d29d15 | 12571 | gcc_assert (!use_return_insn (FALSE, NULL) |
934c2060 | 12572 | || (cfun->machine->return_used_this_function != 0) |
e6d29d15 NS |
12573 | || offsets->saved_regs == offsets->outgoing_args |
12574 | || frame_pointer_needed); | |
f3bb6135 | 12575 | |
d5b7b3ae | 12576 | /* Reset the ARM-specific per-function variables. */ |
d5b7b3ae RE |
12577 | after_arm_reorg = 0; |
12578 | } | |
f3bb6135 | 12579 | } |
e2c671ba | 12580 | |
2c849145 JM |
12581 | /* Generate and emit an insn that we will recognize as a push_multi. |
12582 | Unfortunately, since this insn does not reflect very well the actual | |
12583 | semantics of the operation, we need to annotate the insn for the benefit | |
12584 | of DWARF2 frame unwind information. */ | |
2c849145 | 12585 | static rtx |
b279b20a | 12586 | emit_multi_reg_push (unsigned long mask) |
e2c671ba RE |
12587 | { |
12588 | int num_regs = 0; | |
9b598fa0 | 12589 | int num_dwarf_regs; |
e2c671ba RE |
12590 | int i, j; |
12591 | rtx par; | |
2c849145 | 12592 | rtx dwarf; |
87e27392 | 12593 | int dwarf_par_index; |
2c849145 | 12594 | rtx tmp, reg; |
e2c671ba | 12595 | |
d5b7b3ae | 12596 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba | 12597 | if (mask & (1 << i)) |
5895f793 | 12598 | num_regs++; |
e2c671ba | 12599 | |
e6d29d15 | 12600 | gcc_assert (num_regs && num_regs <= 16); |
e2c671ba | 12601 | |
9b598fa0 RE |
12602 | /* We don't record the PC in the dwarf frame information. */ |
12603 | num_dwarf_regs = num_regs; | |
12604 | if (mask & (1 << PC_REGNUM)) | |
12605 | num_dwarf_regs--; | |
12606 | ||
87e27392 | 12607 | /* For the body of the insn we are going to generate an UNSPEC in |
05713b80 | 12608 | parallel with several USEs. This allows the insn to be recognized |
87e27392 NC |
12609 | by the push_multi pattern in the arm.md file. The insn looks |
12610 | something like this: | |
12611 | ||
f676971a | 12612 | (parallel [ |
b15bca31 RE |
12613 | (set (mem:BLK (pre_dec:BLK (reg:SI sp))) |
12614 | (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) | |
87e27392 NC |
12615 | (use (reg:SI 11 fp)) |
12616 | (use (reg:SI 12 ip)) | |
12617 | (use (reg:SI 14 lr)) | |
12618 | (use (reg:SI 15 pc)) | |
12619 | ]) | |
12620 | ||
12621 | For the frame note however, we try to be more explicit and actually | |
12622 | show each register being stored into the stack frame, plus a (single) | |
12623 | decrement of the stack pointer. We do it this way in order to be | |
12624 | friendly to the stack unwinding code, which only wants to see a single | |
12625 | stack decrement per instruction. The RTL we generate for the note looks | |
12626 | something like this: | |
12627 | ||
f676971a | 12628 | (sequence [ |
87e27392 NC |
12629 | (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) |
12630 | (set (mem:SI (reg:SI sp)) (reg:SI r4)) | |
12631 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) | |
12632 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) | |
12633 | (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) | |
87e27392 NC |
12634 | ]) |
12635 | ||
12636 | This sequence is used both by the code to support stack unwinding for | |
12637 | exceptions handlers and the code to generate dwarf2 frame debugging. */ | |
f676971a | 12638 | |
43cffd11 | 12639 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); |
9b598fa0 | 12640 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); |
87e27392 | 12641 | dwarf_par_index = 1; |
e2c671ba | 12642 | |
d5b7b3ae | 12643 | for (i = 0; i <= LAST_ARM_REGNUM; i++) |
e2c671ba RE |
12644 | { |
12645 | if (mask & (1 << i)) | |
12646 | { | |
2c849145 JM |
12647 | reg = gen_rtx_REG (SImode, i); |
12648 | ||
e2c671ba | 12649 | XVECEXP (par, 0, 0) |
43cffd11 | 12650 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12651 | gen_frame_mem (BLKmode, |
12652 | gen_rtx_PRE_DEC (BLKmode, | |
12653 | stack_pointer_rtx)), | |
43cffd11 | 12654 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 12655 | gen_rtvec (1, reg), |
9b598fa0 | 12656 | UNSPEC_PUSH_MULT)); |
2c849145 | 12657 | |
9b598fa0 RE |
12658 | if (i != PC_REGNUM) |
12659 | { | |
12660 | tmp = gen_rtx_SET (VOIDmode, | |
31fa16b6 | 12661 | gen_frame_mem (SImode, stack_pointer_rtx), |
9b598fa0 RE |
12662 | reg); |
12663 | RTX_FRAME_RELATED_P (tmp) = 1; | |
12664 | XVECEXP (dwarf, 0, dwarf_par_index) = tmp; | |
12665 | dwarf_par_index++; | |
12666 | } | |
2c849145 | 12667 | |
e2c671ba RE |
12668 | break; |
12669 | } | |
12670 | } | |
12671 | ||
12672 | for (j = 1, i++; j < num_regs; i++) | |
12673 | { | |
12674 | if (mask & (1 << i)) | |
12675 | { | |
2c849145 JM |
12676 | reg = gen_rtx_REG (SImode, i); |
12677 | ||
12678 | XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); | |
12679 | ||
9b598fa0 RE |
12680 | if (i != PC_REGNUM) |
12681 | { | |
31fa16b6 RE |
12682 | tmp |
12683 | = gen_rtx_SET (VOIDmode, | |
12684 | gen_frame_mem (SImode, | |
9b598fa0 RE |
12685 | plus_constant (stack_pointer_rtx, |
12686 | 4 * j)), | |
31fa16b6 | 12687 | reg); |
9b598fa0 RE |
12688 | RTX_FRAME_RELATED_P (tmp) = 1; |
12689 | XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; | |
12690 | } | |
12691 | ||
e2c671ba RE |
12692 | j++; |
12693 | } | |
12694 | } | |
b111229a | 12695 | |
2c849145 | 12696 | par = emit_insn (par); |
f676971a | 12697 | |
d66437c5 | 12698 | tmp = gen_rtx_SET (VOIDmode, |
87e27392 | 12699 | stack_pointer_rtx, |
d66437c5 | 12700 | plus_constant (stack_pointer_rtx, -4 * num_regs)); |
87e27392 NC |
12701 | RTX_FRAME_RELATED_P (tmp) = 1; |
12702 | XVECEXP (dwarf, 0, 0) = tmp; | |
f676971a | 12703 | |
bbbbb16a ILT |
12704 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
12705 | ||
2c849145 | 12706 | return par; |
b111229a RE |
12707 | } |
12708 | ||
4f5dfed0 | 12709 | /* Calculate the size of the return value that is passed in registers. */ |
466e4b7a | 12710 | static unsigned |
4f5dfed0 JC |
12711 | arm_size_return_regs (void) |
12712 | { | |
12713 | enum machine_mode mode; | |
12714 | ||
38173d38 JH |
12715 | if (crtl->return_rtx != 0) |
12716 | mode = GET_MODE (crtl->return_rtx); | |
4f5dfed0 JC |
12717 | else |
12718 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); | |
12719 | ||
12720 | return GET_MODE_SIZE (mode); | |
12721 | } | |
12722 | ||
2c849145 | 12723 | static rtx |
e32bac5b | 12724 | emit_sfm (int base_reg, int count) |
b111229a RE |
12725 | { |
12726 | rtx par; | |
2c849145 JM |
12727 | rtx dwarf; |
12728 | rtx tmp, reg; | |
b111229a RE |
12729 | int i; |
12730 | ||
43cffd11 | 12731 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
8ee6eb4e | 12732 | dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); |
2c849145 JM |
12733 | |
12734 | reg = gen_rtx_REG (XFmode, base_reg++); | |
43cffd11 RE |
12735 | |
12736 | XVECEXP (par, 0, 0) | |
f676971a | 12737 | = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12738 | gen_frame_mem (BLKmode, |
12739 | gen_rtx_PRE_DEC (BLKmode, | |
12740 | stack_pointer_rtx)), | |
43cffd11 | 12741 | gen_rtx_UNSPEC (BLKmode, |
2c849145 | 12742 | gen_rtvec (1, reg), |
b15bca31 | 12743 | UNSPEC_PUSH_MULT)); |
f676971a | 12744 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 | 12745 | gen_frame_mem (XFmode, stack_pointer_rtx), reg); |
2c849145 | 12746 | RTX_FRAME_RELATED_P (tmp) = 1; |
f676971a EC |
12747 | XVECEXP (dwarf, 0, 1) = tmp; |
12748 | ||
b111229a | 12749 | for (i = 1; i < count; i++) |
2c849145 JM |
12750 | { |
12751 | reg = gen_rtx_REG (XFmode, base_reg++); | |
12752 | XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); | |
12753 | ||
f676971a | 12754 | tmp = gen_rtx_SET (VOIDmode, |
31fa16b6 RE |
12755 | gen_frame_mem (XFmode, |
12756 | plus_constant (stack_pointer_rtx, | |
12757 | i * 12)), | |
2c849145 JM |
12758 | reg); |
12759 | RTX_FRAME_RELATED_P (tmp) = 1; | |
f676971a | 12760 | XVECEXP (dwarf, 0, i + 1) = tmp; |
2c849145 | 12761 | } |
b111229a | 12762 | |
8ee6eb4e PB |
12763 | tmp = gen_rtx_SET (VOIDmode, |
12764 | stack_pointer_rtx, | |
d66437c5 RE |
12765 | plus_constant (stack_pointer_rtx, -12 * count)); |
12766 | ||
8ee6eb4e PB |
12767 | RTX_FRAME_RELATED_P (tmp) = 1; |
12768 | XVECEXP (dwarf, 0, 0) = tmp; | |
12769 | ||
2c849145 | 12770 | par = emit_insn (par); |
bbbbb16a ILT |
12771 | add_reg_note (par, REG_FRAME_RELATED_EXPR, dwarf); |
12772 | ||
2c849145 | 12773 | return par; |
e2c671ba RE |
12774 | } |
12775 | ||
9b66ebb1 | 12776 | |
3c7ad43e PB |
12777 | /* Return true if the current function needs to save/restore LR. */ |
12778 | ||
12779 | static bool | |
12780 | thumb_force_lr_save (void) | |
12781 | { | |
12782 | return !cfun->machine->lr_save_eliminated | |
12783 | && (!leaf_function_p () | |
12784 | || thumb_far_jump_used_p () | |
6fb5fa3c | 12785 | || df_regs_ever_live_p (LR_REGNUM)); |
3c7ad43e PB |
12786 | } |
12787 | ||
12788 | ||
095bb276 NC |
12789 | /* Compute the distance from register FROM to register TO. |
12790 | These can be the arg pointer (26), the soft frame pointer (25), | |
12791 | the stack pointer (13) or the hard frame pointer (11). | |
c9ca9b88 | 12792 | In thumb mode r7 is used as the soft frame pointer, if needed. |
095bb276 NC |
12793 | Typical stack layout looks like this: |
12794 | ||
12795 | old stack pointer -> | | | |
12796 | ---- | |
12797 | | | \ | |
12798 | | | saved arguments for | |
12799 | | | vararg functions | |
12800 | | | / | |
12801 | -- | |
12802 | hard FP & arg pointer -> | | \ | |
12803 | | | stack | |
12804 | | | frame | |
12805 | | | / | |
12806 | -- | |
12807 | | | \ | |
12808 | | | call saved | |
12809 | | | registers | |
12810 | soft frame pointer -> | | / | |
12811 | -- | |
12812 | | | \ | |
12813 | | | local | |
12814 | | | variables | |
2591db65 | 12815 | locals base pointer -> | | / |
095bb276 NC |
12816 | -- |
12817 | | | \ | |
12818 | | | outgoing | |
12819 | | | arguments | |
12820 | current stack pointer -> | | / | |
12821 | -- | |
12822 | ||
43aa4e05 | 12823 | For a given function some or all of these stack components |
095bb276 NC |
12824 | may not be needed, giving rise to the possibility of |
12825 | eliminating some of the registers. | |
12826 | ||
825dda42 | 12827 | The values returned by this function must reflect the behavior |
095bb276 NC |
12828 | of arm_expand_prologue() and arm_compute_save_reg_mask(). |
12829 | ||
12830 | The sign of the number returned reflects the direction of stack | |
12831 | growth, so the values are positive for all eliminations except | |
5848830f PB |
12832 | from the soft frame pointer to the hard frame pointer. |
12833 | ||
12834 | SFP may point just inside the local variables block to ensure correct | |
12835 | alignment. */ | |
12836 | ||
12837 | ||
12838 | /* Calculate stack offsets. These are used to calculate register elimination | |
954954d1 PB |
12839 | offsets and in prologue/epilogue code. Also calculates which registers |
12840 | should be saved. */ | |
5848830f PB |
12841 | |
12842 | static arm_stack_offsets * | |
12843 | arm_get_frame_offsets (void) | |
095bb276 | 12844 | { |
5848830f | 12845 | struct arm_stack_offsets *offsets; |
095bb276 | 12846 | unsigned long func_type; |
5848830f | 12847 | int leaf; |
5848830f | 12848 | int saved; |
954954d1 | 12849 | int core_saved; |
5848830f | 12850 | HOST_WIDE_INT frame_size; |
954954d1 | 12851 | int i; |
5848830f PB |
12852 | |
12853 | offsets = &cfun->machine->stack_offsets; | |
f676971a | 12854 | |
5848830f PB |
12855 | /* We need to know if we are a leaf function. Unfortunately, it |
12856 | is possible to be called after start_sequence has been called, | |
12857 | which causes get_insns to return the insns for the sequence, | |
12858 | not the function, which will cause leaf_function_p to return | |
12859 | the incorrect result. | |
095bb276 | 12860 | |
5848830f PB |
12861 | to know about leaf functions once reload has completed, and the |
12862 | frame size cannot be changed after that time, so we can safely | |
12863 | use the cached value. */ | |
12864 | ||
12865 | if (reload_completed) | |
12866 | return offsets; | |
12867 | ||
666c27b9 KH |
12868 | /* Initially this is the size of the local variables. It will translated |
12869 | into an offset once we have determined the size of preceding data. */ | |
5848830f PB |
12870 | frame_size = ROUND_UP_WORD (get_frame_size ()); |
12871 | ||
12872 | leaf = leaf_function_p (); | |
12873 | ||
12874 | /* Space for variadic functions. */ | |
38173d38 | 12875 | offsets->saved_args = crtl->args.pretend_args_size; |
5848830f | 12876 | |
5b3e6663 | 12877 | /* In Thumb mode this is incorrect, but never used. */ |
35596784 AJ |
12878 | offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0) + |
12879 | arm_compute_static_chain_stack_bytes(); | |
5848830f | 12880 | |
5b3e6663 | 12881 | if (TARGET_32BIT) |
095bb276 | 12882 | { |
5848830f | 12883 | unsigned int regno; |
ef7112de | 12884 | |
954954d1 PB |
12885 | offsets->saved_regs_mask = arm_compute_save_reg_mask (); |
12886 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12887 | saved = core_saved; | |
5a9335ef | 12888 | |
5848830f PB |
12889 | /* We know that SP will be doubleword aligned on entry, and we must |
12890 | preserve that condition at any subroutine call. We also require the | |
12891 | soft frame pointer to be doubleword aligned. */ | |
12892 | ||
12893 | if (TARGET_REALLY_IWMMXT) | |
9b66ebb1 | 12894 | { |
5848830f PB |
12895 | /* Check for the call-saved iWMMXt registers. */ |
12896 | for (regno = FIRST_IWMMXT_REGNUM; | |
12897 | regno <= LAST_IWMMXT_REGNUM; | |
12898 | regno++) | |
6fb5fa3c | 12899 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12900 | saved += 8; |
12901 | } | |
12902 | ||
12903 | func_type = arm_current_func_type (); | |
12904 | if (! IS_VOLATILE (func_type)) | |
12905 | { | |
12906 | /* Space for saved FPA registers. */ | |
12907 | for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) | |
6fb5fa3c | 12908 | if (df_regs_ever_live_p (regno) && ! call_used_regs[regno]) |
5848830f PB |
12909 | saved += 12; |
12910 | ||
12911 | /* Space for saved VFP registers. */ | |
12912 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
9728c9d1 | 12913 | saved += arm_get_vfp_saved_size (); |
9b66ebb1 | 12914 | } |
5848830f | 12915 | } |
5b3e6663 | 12916 | else /* TARGET_THUMB1 */ |
5848830f | 12917 | { |
954954d1 PB |
12918 | offsets->saved_regs_mask = thumb1_compute_save_reg_mask (); |
12919 | core_saved = bit_count (offsets->saved_regs_mask) * 4; | |
12920 | saved = core_saved; | |
5848830f | 12921 | if (TARGET_BACKTRACE) |
57934c39 | 12922 | saved += 16; |
5848830f | 12923 | } |
9b66ebb1 | 12924 | |
5848830f | 12925 | /* Saved registers include the stack frame. */ |
35596784 AJ |
12926 | offsets->saved_regs = offsets->saved_args + saved + |
12927 | arm_compute_static_chain_stack_bytes(); | |
a2503645 | 12928 | offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; |
5848830f PB |
12929 | /* A leaf function does not need any stack alignment if it has nothing |
12930 | on the stack. */ | |
12931 | if (leaf && frame_size == 0) | |
12932 | { | |
12933 | offsets->outgoing_args = offsets->soft_frame; | |
a3a531ec | 12934 | offsets->locals_base = offsets->soft_frame; |
5848830f PB |
12935 | return offsets; |
12936 | } | |
12937 | ||
12938 | /* Ensure SFP has the correct alignment. */ | |
12939 | if (ARM_DOUBLEWORD_ALIGN | |
12940 | && (offsets->soft_frame & 7)) | |
954954d1 PB |
12941 | { |
12942 | offsets->soft_frame += 4; | |
12943 | /* Try to align stack by pushing an extra reg. Don't bother doing this | |
12944 | when there is a stack frame as the alignment will be rolled into | |
12945 | the normal stack adjustment. */ | |
38173d38 | 12946 | if (frame_size + crtl->outgoing_args_size == 0) |
954954d1 PB |
12947 | { |
12948 | int reg = -1; | |
12949 | ||
55b2829b RE |
12950 | /* If it is safe to use r3, then do so. This sometimes |
12951 | generates better code on Thumb-2 by avoiding the need to | |
12952 | use 32-bit push/pop instructions. */ | |
12953 | if (!crtl->tail_call_emit | |
12954 | && arm_size_return_regs () <= 12) | |
954954d1 | 12955 | { |
954954d1 PB |
12956 | reg = 3; |
12957 | } | |
55b2829b RE |
12958 | else |
12959 | for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) | |
12960 | { | |
12961 | if ((offsets->saved_regs_mask & (1 << i)) == 0) | |
12962 | { | |
12963 | reg = i; | |
12964 | break; | |
12965 | } | |
12966 | } | |
954954d1 PB |
12967 | |
12968 | if (reg != -1) | |
12969 | { | |
12970 | offsets->saved_regs += 4; | |
12971 | offsets->saved_regs_mask |= (1 << reg); | |
12972 | } | |
12973 | } | |
12974 | } | |
5848830f | 12975 | |
2591db65 RE |
12976 | offsets->locals_base = offsets->soft_frame + frame_size; |
12977 | offsets->outgoing_args = (offsets->locals_base | |
38173d38 | 12978 | + crtl->outgoing_args_size); |
5848830f PB |
12979 | |
12980 | if (ARM_DOUBLEWORD_ALIGN) | |
12981 | { | |
12982 | /* Ensure SP remains doubleword aligned. */ | |
12983 | if (offsets->outgoing_args & 7) | |
12984 | offsets->outgoing_args += 4; | |
e6d29d15 | 12985 | gcc_assert (!(offsets->outgoing_args & 7)); |
095bb276 NC |
12986 | } |
12987 | ||
5848830f PB |
12988 | return offsets; |
12989 | } | |
12990 | ||
12991 | ||
666c27b9 | 12992 | /* Calculate the relative offsets for the different stack pointers. Positive |
5848830f PB |
12993 | offsets are in the direction of stack growth. */ |
12994 | ||
b3f8d95d | 12995 | HOST_WIDE_INT |
5848830f PB |
12996 | arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) |
12997 | { | |
12998 | arm_stack_offsets *offsets; | |
12999 | ||
13000 | offsets = arm_get_frame_offsets (); | |
095bb276 | 13001 | |
095bb276 NC |
13002 | /* OK, now we have enough information to compute the distances. |
13003 | There must be an entry in these switch tables for each pair | |
13004 | of registers in ELIMINABLE_REGS, even if some of the entries | |
13005 | seem to be redundant or useless. */ | |
13006 | switch (from) | |
13007 | { | |
13008 | case ARG_POINTER_REGNUM: | |
13009 | switch (to) | |
13010 | { | |
13011 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
13012 | return 0; | |
13013 | ||
13014 | case FRAME_POINTER_REGNUM: | |
13015 | /* This is the reverse of the soft frame pointer | |
13016 | to hard frame pointer elimination below. */ | |
5848830f | 13017 | return offsets->soft_frame - offsets->saved_args; |
095bb276 NC |
13018 | |
13019 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
35596784 AJ |
13020 | /* This is only non-zero in the case where the static chain register |
13021 | is stored above the frame. */ | |
13022 | return offsets->frame - offsets->saved_args - 4; | |
095bb276 NC |
13023 | |
13024 | case STACK_POINTER_REGNUM: | |
13025 | /* If nothing has been pushed on the stack at all | |
13026 | then this will return -4. This *is* correct! */ | |
5848830f | 13027 | return offsets->outgoing_args - (offsets->saved_args + 4); |
095bb276 NC |
13028 | |
13029 | default: | |
e6d29d15 | 13030 | gcc_unreachable (); |
095bb276 | 13031 | } |
e6d29d15 | 13032 | gcc_unreachable (); |
095bb276 NC |
13033 | |
13034 | case FRAME_POINTER_REGNUM: | |
13035 | switch (to) | |
13036 | { | |
13037 | case THUMB_HARD_FRAME_POINTER_REGNUM: | |
13038 | return 0; | |
13039 | ||
13040 | case ARM_HARD_FRAME_POINTER_REGNUM: | |
13041 | /* The hard frame pointer points to the top entry in the | |
13042 | stack frame. The soft frame pointer to the bottom entry | |
13043 | in the stack frame. If there is no stack frame at all, | |
13044 | then they are identical. */ | |
5848830f PB |
13045 | |
13046 | return offsets->frame - offsets->soft_frame; | |
095bb276 NC |
13047 | |
13048 | case STACK_POINTER_REGNUM: | |
5848830f | 13049 | return offsets->outgoing_args - offsets->soft_frame; |
095bb276 NC |
13050 | |
13051 | default: | |
e6d29d15 | 13052 | gcc_unreachable (); |
095bb276 | 13053 | } |
e6d29d15 | 13054 | gcc_unreachable (); |
095bb276 NC |
13055 | |
13056 | default: | |
13057 | /* You cannot eliminate from the stack pointer. | |
13058 | In theory you could eliminate from the hard frame | |
13059 | pointer to the stack pointer, but this will never | |
13060 | happen, since if a stack frame is not needed the | |
13061 | hard frame pointer will never be used. */ | |
e6d29d15 | 13062 | gcc_unreachable (); |
095bb276 NC |
13063 | } |
13064 | } | |
13065 | ||
0977774b | 13066 | |
7a085dce | 13067 | /* Emit RTL to save coprocessor registers on function entry. Returns the |
5b3e6663 PB |
13068 | number of bytes pushed. */ |
13069 | ||
13070 | static int | |
13071 | arm_save_coproc_regs(void) | |
13072 | { | |
13073 | int saved_size = 0; | |
13074 | unsigned reg; | |
13075 | unsigned start_reg; | |
13076 | rtx insn; | |
13077 | ||
13078 | for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) | |
6fb5fa3c | 13079 | if (df_regs_ever_live_p (reg) && ! call_used_regs[reg]) |
5b3e6663 PB |
13080 | { |
13081 | insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); | |
13082 | insn = gen_rtx_MEM (V2SImode, insn); | |
13083 | insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); | |
13084 | RTX_FRAME_RELATED_P (insn) = 1; | |
13085 | saved_size += 8; | |
13086 | } | |
13087 | ||
13088 | /* Save any floating point call-saved registers used by this | |
13089 | function. */ | |
13090 | if (arm_fpu_arch == FPUTYPE_FPA_EMU2) | |
13091 | { | |
13092 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
6fb5fa3c | 13093 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
13094 | { |
13095 | insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); | |
13096 | insn = gen_rtx_MEM (XFmode, insn); | |
13097 | insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); | |
13098 | RTX_FRAME_RELATED_P (insn) = 1; | |
13099 | saved_size += 12; | |
13100 | } | |
13101 | } | |
13102 | else | |
13103 | { | |
13104 | start_reg = LAST_FPA_REGNUM; | |
13105 | ||
13106 | for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) | |
13107 | { | |
6fb5fa3c | 13108 | if (df_regs_ever_live_p (reg) && !call_used_regs[reg]) |
5b3e6663 PB |
13109 | { |
13110 | if (start_reg - reg == 3) | |
13111 | { | |
13112 | insn = emit_sfm (reg, 4); | |
13113 | RTX_FRAME_RELATED_P (insn) = 1; | |
13114 | saved_size += 48; | |
13115 | start_reg = reg - 1; | |
13116 | } | |
13117 | } | |
13118 | else | |
13119 | { | |
13120 | if (start_reg != reg) | |
13121 | { | |
13122 | insn = emit_sfm (reg + 1, start_reg - reg); | |
13123 | RTX_FRAME_RELATED_P (insn) = 1; | |
13124 | saved_size += (start_reg - reg) * 12; | |
13125 | } | |
13126 | start_reg = reg - 1; | |
13127 | } | |
13128 | } | |
13129 | ||
13130 | if (start_reg != reg) | |
13131 | { | |
13132 | insn = emit_sfm (reg + 1, start_reg - reg); | |
13133 | saved_size += (start_reg - reg) * 12; | |
13134 | RTX_FRAME_RELATED_P (insn) = 1; | |
13135 | } | |
13136 | } | |
13137 | if (TARGET_HARD_FLOAT && TARGET_VFP) | |
13138 | { | |
13139 | start_reg = FIRST_VFP_REGNUM; | |
13140 | ||
13141 | for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) | |
13142 | { | |
6fb5fa3c DB |
13143 | if ((!df_regs_ever_live_p (reg) || call_used_regs[reg]) |
13144 | && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1])) | |
5b3e6663 PB |
13145 | { |
13146 | if (start_reg != reg) | |
13147 | saved_size += vfp_emit_fstmd (start_reg, | |
13148 | (reg - start_reg) / 2); | |
13149 | start_reg = reg + 2; | |
13150 | } | |
13151 | } | |
13152 | if (start_reg != reg) | |
13153 | saved_size += vfp_emit_fstmd (start_reg, | |
13154 | (reg - start_reg) / 2); | |
13155 | } | |
13156 | return saved_size; | |
13157 | } | |
13158 | ||
13159 | ||
13160 | /* Set the Thumb frame pointer from the stack pointer. */ | |
13161 | ||
13162 | static void | |
13163 | thumb_set_frame_pointer (arm_stack_offsets *offsets) | |
13164 | { | |
13165 | HOST_WIDE_INT amount; | |
13166 | rtx insn, dwarf; | |
13167 | ||
13168 | amount = offsets->outgoing_args - offsets->locals_base; | |
13169 | if (amount < 1024) | |
13170 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13171 | stack_pointer_rtx, GEN_INT (amount))); | |
13172 | else | |
13173 | { | |
13174 | emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); | |
f5c630c3 PB |
13175 | /* Thumb-2 RTL patterns expect sp as the first input. Thumb-1 |
13176 | expects the first two operands to be the same. */ | |
13177 | if (TARGET_THUMB2) | |
13178 | { | |
13179 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13180 | stack_pointer_rtx, | |
13181 | hard_frame_pointer_rtx)); | |
13182 | } | |
13183 | else | |
13184 | { | |
13185 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13186 | hard_frame_pointer_rtx, | |
13187 | stack_pointer_rtx)); | |
13188 | } | |
5b3e6663 PB |
13189 | dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, |
13190 | plus_constant (stack_pointer_rtx, amount)); | |
13191 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 13192 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
13193 | } |
13194 | ||
13195 | RTX_FRAME_RELATED_P (insn) = 1; | |
13196 | } | |
13197 | ||
13198 | /* Generate the prologue instructions for entry into an ARM or Thumb-2 | |
13199 | function. */ | |
e2c671ba | 13200 | void |
e32bac5b | 13201 | arm_expand_prologue (void) |
e2c671ba | 13202 | { |
6d3d9133 | 13203 | rtx amount; |
2c849145 | 13204 | rtx insn; |
68dfd979 | 13205 | rtx ip_rtx; |
6d3d9133 NC |
13206 | unsigned long live_regs_mask; |
13207 | unsigned long func_type; | |
68dfd979 | 13208 | int fp_offset = 0; |
095bb276 | 13209 | int saved_pretend_args = 0; |
5848830f | 13210 | int saved_regs = 0; |
b9705a21 | 13211 | unsigned HOST_WIDE_INT args_to_push; |
5848830f | 13212 | arm_stack_offsets *offsets; |
d3236b4d | 13213 | |
6d3d9133 | 13214 | func_type = arm_current_func_type (); |
e2c671ba | 13215 | |
31fdb4d5 | 13216 | /* Naked functions don't have prologues. */ |
6d3d9133 | 13217 | if (IS_NAKED (func_type)) |
31fdb4d5 DE |
13218 | return; |
13219 | ||
095bb276 | 13220 | /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ |
38173d38 | 13221 | args_to_push = crtl->args.pretend_args_size; |
f676971a | 13222 | |
6d3d9133 | 13223 | /* Compute which register we will have to save onto the stack. */ |
954954d1 PB |
13224 | offsets = arm_get_frame_offsets (); |
13225 | live_regs_mask = offsets->saved_regs_mask; | |
e2c671ba | 13226 | |
68dfd979 | 13227 | ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); |
d3236b4d | 13228 | |
5b3e6663 PB |
13229 | if (IS_STACKALIGN (func_type)) |
13230 | { | |
13231 | rtx dwarf; | |
13232 | rtx r0; | |
13233 | rtx r1; | |
13234 | /* Handle a word-aligned stack pointer. We generate the following: | |
13235 | ||
13236 | mov r0, sp | |
13237 | bic r1, r0, #7 | |
13238 | mov sp, r1 | |
13239 | <save and restore r0 in normal prologue/epilogue> | |
13240 | mov sp, r0 | |
13241 | bx lr | |
13242 | ||
13243 | The unwinder doesn't need to know about the stack realignment. | |
13244 | Just tell it we saved SP in r0. */ | |
13245 | gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0); | |
13246 | ||
13247 | r0 = gen_rtx_REG (SImode, 0); | |
13248 | r1 = gen_rtx_REG (SImode, 1); | |
44bfa35b NF |
13249 | /* Use a real rtvec rather than NULL_RTVEC so the rest of the |
13250 | compiler won't choke. */ | |
13251 | dwarf = gen_rtx_UNSPEC (SImode, rtvec_alloc (0), UNSPEC_STACK_ALIGN); | |
5b3e6663 PB |
13252 | dwarf = gen_rtx_SET (VOIDmode, r0, dwarf); |
13253 | insn = gen_movsi (r0, stack_pointer_rtx); | |
13254 | RTX_FRAME_RELATED_P (insn) = 1; | |
bbbbb16a | 13255 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
5b3e6663 PB |
13256 | emit_insn (insn); |
13257 | emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7))); | |
13258 | emit_insn (gen_movsi (stack_pointer_rtx, r1)); | |
13259 | } | |
13260 | ||
ec6237e4 PB |
13261 | /* For APCS frames, if IP register is clobbered |
13262 | when creating frame, save that register in a special | |
13263 | way. */ | |
13264 | if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) | |
e2c671ba | 13265 | { |
7b8b8ade NC |
13266 | if (IS_INTERRUPT (func_type)) |
13267 | { | |
13268 | /* Interrupt functions must not corrupt any registers. | |
13269 | Creating a frame pointer however, corrupts the IP | |
13270 | register, so we must push it first. */ | |
13271 | insn = emit_multi_reg_push (1 << IP_REGNUM); | |
121308d4 NC |
13272 | |
13273 | /* Do not set RTX_FRAME_RELATED_P on this insn. | |
13274 | The dwarf stack unwinding code only wants to see one | |
13275 | stack decrement per function, and this is not it. If | |
13276 | this instruction is labeled as being part of the frame | |
13277 | creation sequence then dwarf2out_frame_debug_expr will | |
e6d29d15 | 13278 | die when it encounters the assignment of IP to FP |
121308d4 NC |
13279 | later on, since the use of SP here establishes SP as |
13280 | the CFA register and not IP. | |
13281 | ||
13282 | Anyway this instruction is not really part of the stack | |
13283 | frame creation although it is part of the prologue. */ | |
7b8b8ade NC |
13284 | } |
13285 | else if (IS_NESTED (func_type)) | |
68dfd979 NC |
13286 | { |
13287 | /* The Static chain register is the same as the IP register | |
13288 | used as a scratch register during stack frame creation. | |
13289 | To get around this need to find somewhere to store IP | |
13290 | whilst the frame is being created. We try the following | |
13291 | places in order: | |
f676971a | 13292 | |
6d3d9133 | 13293 | 1. The last argument register. |
68dfd979 NC |
13294 | 2. A slot on the stack above the frame. (This only |
13295 | works if the function is not a varargs function). | |
095bb276 NC |
13296 | 3. Register r3, after pushing the argument registers |
13297 | onto the stack. | |
6d3d9133 | 13298 | |
34ce3d7b JM |
13299 | Note - we only need to tell the dwarf2 backend about the SP |
13300 | adjustment in the second variant; the static chain register | |
13301 | doesn't need to be unwound, as it doesn't contain a value | |
13302 | inherited from the caller. */ | |
d3236b4d | 13303 | |
6fb5fa3c | 13304 | if (df_regs_ever_live_p (3) == false) |
d66437c5 | 13305 | insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 13306 | else if (args_to_push == 0) |
68dfd979 | 13307 | { |
f0b4bdd5 RE |
13308 | rtx dwarf; |
13309 | ||
35596784 AJ |
13310 | gcc_assert(arm_compute_static_chain_stack_bytes() == 4); |
13311 | saved_regs += 4; | |
13312 | ||
d66437c5 RE |
13313 | insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); |
13314 | insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); | |
68dfd979 | 13315 | fp_offset = 4; |
34ce3d7b JM |
13316 | |
13317 | /* Just tell the dwarf backend that we adjusted SP. */ | |
13318 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
d66437c5 RE |
13319 | plus_constant (stack_pointer_rtx, |
13320 | -fp_offset)); | |
34ce3d7b | 13321 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 13322 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
68dfd979 NC |
13323 | } |
13324 | else | |
095bb276 NC |
13325 | { |
13326 | /* Store the args on the stack. */ | |
3cb66fd7 | 13327 | if (cfun->machine->uses_anonymous_args) |
095bb276 NC |
13328 | insn = emit_multi_reg_push |
13329 | ((0xf0 >> (args_to_push / 4)) & 0xf); | |
13330 | else | |
13331 | insn = emit_insn | |
f676971a | 13332 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 NC |
13333 | GEN_INT (- args_to_push))); |
13334 | ||
13335 | RTX_FRAME_RELATED_P (insn) = 1; | |
13336 | ||
13337 | saved_pretend_args = 1; | |
13338 | fp_offset = args_to_push; | |
13339 | args_to_push = 0; | |
13340 | ||
13341 | /* Now reuse r3 to preserve IP. */ | |
d66437c5 | 13342 | emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); |
095bb276 | 13343 | } |
68dfd979 NC |
13344 | } |
13345 | ||
d66437c5 RE |
13346 | insn = emit_set_insn (ip_rtx, |
13347 | plus_constant (stack_pointer_rtx, fp_offset)); | |
8e56560e | 13348 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
13349 | } |
13350 | ||
095bb276 | 13351 | if (args_to_push) |
e2c671ba | 13352 | { |
6d3d9133 | 13353 | /* Push the argument registers, or reserve space for them. */ |
3cb66fd7 | 13354 | if (cfun->machine->uses_anonymous_args) |
2c849145 | 13355 | insn = emit_multi_reg_push |
095bb276 | 13356 | ((0xf0 >> (args_to_push / 4)) & 0xf); |
e2c671ba | 13357 | else |
2c849145 | 13358 | insn = emit_insn |
f676971a | 13359 | (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
095bb276 | 13360 | GEN_INT (- args_to_push))); |
2c849145 | 13361 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba RE |
13362 | } |
13363 | ||
06bea5aa | 13364 | /* If this is an interrupt service routine, and the link register |
ec6237e4 PB |
13365 | is going to be pushed, and we're not generating extra |
13366 | push of IP (needed when frame is needed and frame layout if apcs), | |
06bea5aa NC |
13367 | subtracting four from LR now will mean that the function return |
13368 | can be done with a single instruction. */ | |
3a7731fd | 13369 | if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) |
06bea5aa | 13370 | && (live_regs_mask & (1 << LR_REGNUM)) != 0 |
ec6237e4 | 13371 | && !(frame_pointer_needed && TARGET_APCS_FRAME) |
a15908a4 | 13372 | && TARGET_ARM) |
d66437c5 RE |
13373 | { |
13374 | rtx lr = gen_rtx_REG (SImode, LR_REGNUM); | |
13375 | ||
13376 | emit_set_insn (lr, plus_constant (lr, -4)); | |
13377 | } | |
3a7731fd | 13378 | |
e2c671ba RE |
13379 | if (live_regs_mask) |
13380 | { | |
5848830f | 13381 | saved_regs += bit_count (live_regs_mask) * 4; |
954954d1 PB |
13382 | if (optimize_size && !frame_pointer_needed |
13383 | && saved_regs == offsets->saved_regs - offsets->saved_args) | |
13384 | { | |
13385 | /* If no coprocessor registers are being pushed and we don't have | |
13386 | to worry about a frame pointer then push extra registers to | |
13387 | create the stack frame. This is done is a way that does not | |
13388 | alter the frame layout, so is independent of the epilogue. */ | |
13389 | int n; | |
13390 | int frame; | |
13391 | n = 0; | |
13392 | while (n < 8 && (live_regs_mask & (1 << n)) == 0) | |
13393 | n++; | |
13394 | frame = offsets->outgoing_args - (offsets->saved_args + saved_regs); | |
13395 | if (frame && n * 4 >= frame) | |
13396 | { | |
13397 | n = frame / 4; | |
13398 | live_regs_mask |= (1 << n) - 1; | |
13399 | saved_regs += frame; | |
13400 | } | |
13401 | } | |
13402 | insn = emit_multi_reg_push (live_regs_mask); | |
2c849145 | 13403 | RTX_FRAME_RELATED_P (insn) = 1; |
e2c671ba | 13404 | } |
d5b7b3ae | 13405 | |
6d3d9133 | 13406 | if (! IS_VOLATILE (func_type)) |
5b3e6663 | 13407 | saved_regs += arm_save_coproc_regs (); |
b111229a | 13408 | |
5b3e6663 PB |
13409 | if (frame_pointer_needed && TARGET_ARM) |
13410 | { | |
13411 | /* Create the new frame pointer. */ | |
ec6237e4 | 13412 | if (TARGET_APCS_FRAME) |
9b66ebb1 | 13413 | { |
5b3e6663 PB |
13414 | insn = GEN_INT (-(4 + args_to_push + fp_offset)); |
13415 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); | |
13416 | RTX_FRAME_RELATED_P (insn) = 1; | |
9b66ebb1 | 13417 | |
5b3e6663 | 13418 | if (IS_NESTED (func_type)) |
9b66ebb1 | 13419 | { |
5b3e6663 | 13420 | /* Recover the static chain register. */ |
6fb5fa3c | 13421 | if (!df_regs_ever_live_p (3) |
5b3e6663 PB |
13422 | || saved_pretend_args) |
13423 | insn = gen_rtx_REG (SImode, 3); | |
38173d38 | 13424 | else /* if (crtl->args.pretend_args_size == 0) */ |
9b66ebb1 | 13425 | { |
5b3e6663 PB |
13426 | insn = plus_constant (hard_frame_pointer_rtx, 4); |
13427 | insn = gen_frame_mem (SImode, insn); | |
9b66ebb1 | 13428 | } |
5b3e6663 PB |
13429 | emit_set_insn (ip_rtx, insn); |
13430 | /* Add a USE to stop propagate_one_insn() from barfing. */ | |
13431 | emit_insn (gen_prologue_use (ip_rtx)); | |
9b66ebb1 | 13432 | } |
68dfd979 | 13433 | } |
ec6237e4 PB |
13434 | else |
13435 | { | |
13436 | insn = GEN_INT (saved_regs - 4); | |
13437 | insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, | |
13438 | stack_pointer_rtx, insn)); | |
13439 | RTX_FRAME_RELATED_P (insn) = 1; | |
13440 | } | |
2c849145 | 13441 | } |
e2c671ba | 13442 | |
5848830f | 13443 | if (offsets->outgoing_args != offsets->saved_args + saved_regs) |
e2c671ba | 13444 | { |
745b9093 JM |
13445 | /* This add can produce multiple insns for a large constant, so we |
13446 | need to get tricky. */ | |
13447 | rtx last = get_last_insn (); | |
5848830f PB |
13448 | |
13449 | amount = GEN_INT (offsets->saved_args + saved_regs | |
13450 | - offsets->outgoing_args); | |
13451 | ||
2c849145 JM |
13452 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, |
13453 | amount)); | |
745b9093 JM |
13454 | do |
13455 | { | |
13456 | last = last ? NEXT_INSN (last) : get_insns (); | |
13457 | RTX_FRAME_RELATED_P (last) = 1; | |
13458 | } | |
13459 | while (last != insn); | |
e04c2d6c RE |
13460 | |
13461 | /* If the frame pointer is needed, emit a special barrier that | |
13462 | will prevent the scheduler from moving stores to the frame | |
13463 | before the stack adjustment. */ | |
13464 | if (frame_pointer_needed) | |
3894f59e RE |
13465 | insn = emit_insn (gen_stack_tie (stack_pointer_rtx, |
13466 | hard_frame_pointer_rtx)); | |
e2c671ba RE |
13467 | } |
13468 | ||
876f13b0 | 13469 | |
5b3e6663 PB |
13470 | if (frame_pointer_needed && TARGET_THUMB2) |
13471 | thumb_set_frame_pointer (offsets); | |
13472 | ||
020a4035 | 13473 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
5b3e6663 PB |
13474 | { |
13475 | unsigned long mask; | |
13476 | ||
13477 | mask = live_regs_mask; | |
13478 | mask &= THUMB2_WORK_REGS; | |
13479 | if (!IS_NESTED (func_type)) | |
13480 | mask |= (1 << IP_REGNUM); | |
13481 | arm_load_pic_register (mask); | |
13482 | } | |
876f13b0 | 13483 | |
e2c671ba | 13484 | /* If we are profiling, make sure no instructions are scheduled before |
f5a1b0d2 | 13485 | the call to mcount. Similarly if the user has requested no |
74d9c39f DJ |
13486 | scheduling in the prolog. Similarly if we want non-call exceptions |
13487 | using the EABI unwinder, to prevent faulting instructions from being | |
13488 | swapped with a stack adjustment. */ | |
e3b5732b | 13489 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 13490 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
e2c671ba | 13491 | emit_insn (gen_blockage ()); |
6f7ebcbb NC |
13492 | |
13493 | /* If the link register is being kept alive, with the return address in it, | |
13494 | then make sure that it does not get reused by the ce2 pass. */ | |
13495 | if ((live_regs_mask & (1 << LR_REGNUM)) == 0) | |
6fb5fa3c | 13496 | cfun->machine->lr_save_eliminated = 1; |
e2c671ba | 13497 | } |
cce8749e | 13498 | \f |
5b3e6663 PB |
13499 | /* Print condition code to STREAM. Helper function for arm_print_operand. */ |
13500 | static void | |
13501 | arm_print_condition (FILE *stream) | |
13502 | { | |
13503 | if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) | |
13504 | { | |
13505 | /* Branch conversion is not implemented for Thumb-2. */ | |
13506 | if (TARGET_THUMB) | |
13507 | { | |
13508 | output_operand_lossage ("predicated Thumb instruction"); | |
13509 | return; | |
13510 | } | |
13511 | if (current_insn_predicate != NULL) | |
13512 | { | |
13513 | output_operand_lossage | |
13514 | ("predicated instruction in conditional sequence"); | |
13515 | return; | |
13516 | } | |
13517 | ||
13518 | fputs (arm_condition_codes[arm_current_cc], stream); | |
13519 | } | |
13520 | else if (current_insn_predicate) | |
13521 | { | |
13522 | enum arm_cond_code code; | |
13523 | ||
13524 | if (TARGET_THUMB1) | |
13525 | { | |
13526 | output_operand_lossage ("predicated Thumb instruction"); | |
13527 | return; | |
13528 | } | |
13529 | ||
13530 | code = get_arm_condition_code (current_insn_predicate); | |
13531 | fputs (arm_condition_codes[code], stream); | |
13532 | } | |
13533 | } | |
13534 | ||
13535 | ||
9997d19d RE |
13536 | /* If CODE is 'd', then the X is a condition operand and the instruction |
13537 | should only be executed if the condition is true. | |
ddd5a7c1 | 13538 | if CODE is 'D', then the X is a condition operand and the instruction |
9997d19d RE |
13539 | should only be executed if the condition is false: however, if the mode |
13540 | of the comparison is CCFPEmode, then always execute the instruction -- we | |
13541 | do this because in these circumstances !GE does not necessarily imply LT; | |
13542 | in these cases the instruction pattern will take care to make sure that | |
13543 | an instruction containing %d will follow, thereby undoing the effects of | |
ddd5a7c1 | 13544 | doing this instruction unconditionally. |
9997d19d RE |
13545 | If CODE is 'N' then X is a floating point operand that must be negated |
13546 | before output. | |
13547 | If CODE is 'B' then output a bitwise inverted value of X (a const int). | |
13548 | If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ | |
9997d19d | 13549 | void |
e32bac5b | 13550 | arm_print_operand (FILE *stream, rtx x, int code) |
9997d19d RE |
13551 | { |
13552 | switch (code) | |
13553 | { | |
13554 | case '@': | |
f3139301 | 13555 | fputs (ASM_COMMENT_START, stream); |
9997d19d RE |
13556 | return; |
13557 | ||
d5b7b3ae RE |
13558 | case '_': |
13559 | fputs (user_label_prefix, stream); | |
13560 | return; | |
f676971a | 13561 | |
9997d19d | 13562 | case '|': |
f3139301 | 13563 | fputs (REGISTER_PREFIX, stream); |
9997d19d RE |
13564 | return; |
13565 | ||
13566 | case '?': | |
5b3e6663 PB |
13567 | arm_print_condition (stream); |
13568 | return; | |
cca0a211 | 13569 | |
5b3e6663 PB |
13570 | case '(': |
13571 | /* Nothing in unified syntax, otherwise the current condition code. */ | |
13572 | if (!TARGET_UNIFIED_ASM) | |
13573 | arm_print_condition (stream); | |
13574 | break; | |
13575 | ||
13576 | case ')': | |
13577 | /* The current condition code in unified syntax, otherwise nothing. */ | |
13578 | if (TARGET_UNIFIED_ASM) | |
13579 | arm_print_condition (stream); | |
13580 | break; | |
13581 | ||
13582 | case '.': | |
13583 | /* The current condition code for a condition code setting instruction. | |
7a085dce | 13584 | Preceded by 's' in unified syntax, otherwise followed by 's'. */ |
5b3e6663 PB |
13585 | if (TARGET_UNIFIED_ASM) |
13586 | { | |
13587 | fputc('s', stream); | |
13588 | arm_print_condition (stream); | |
cca0a211 | 13589 | } |
5b3e6663 | 13590 | else |
cca0a211 | 13591 | { |
5b3e6663 PB |
13592 | arm_print_condition (stream); |
13593 | fputc('s', stream); | |
cca0a211 | 13594 | } |
9997d19d RE |
13595 | return; |
13596 | ||
5b3e6663 PB |
13597 | case '!': |
13598 | /* If the instruction is conditionally executed then print | |
13599 | the current condition code, otherwise print 's'. */ | |
13600 | gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM); | |
13601 | if (current_insn_predicate) | |
13602 | arm_print_condition (stream); | |
13603 | else | |
13604 | fputc('s', stream); | |
13605 | break; | |
13606 | ||
88f77cba | 13607 | /* %# is a "break" sequence. It doesn't output anything, but is used to |
cea618ac | 13608 | separate e.g. operand numbers from following text, if that text consists |
88f77cba JB |
13609 | of further digits which we don't want to be part of the operand |
13610 | number. */ | |
13611 | case '#': | |
13612 | return; | |
13613 | ||
9997d19d RE |
13614 | case 'N': |
13615 | { | |
13616 | REAL_VALUE_TYPE r; | |
13617 | REAL_VALUE_FROM_CONST_DOUBLE (r, x); | |
13618 | r = REAL_VALUE_NEGATE (r); | |
13619 | fprintf (stream, "%s", fp_const_from_val (&r)); | |
13620 | } | |
13621 | return; | |
13622 | ||
571191af | 13623 | /* An integer or symbol address without a preceding # sign. */ |
88f77cba | 13624 | case 'c': |
571191af PB |
13625 | switch (GET_CODE (x)) |
13626 | { | |
13627 | case CONST_INT: | |
13628 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
13629 | break; | |
13630 | ||
13631 | case SYMBOL_REF: | |
13632 | output_addr_const (stream, x); | |
13633 | break; | |
13634 | ||
13635 | default: | |
13636 | gcc_unreachable (); | |
13637 | } | |
88f77cba JB |
13638 | return; |
13639 | ||
9997d19d RE |
13640 | case 'B': |
13641 | if (GET_CODE (x) == CONST_INT) | |
4bc74ece NC |
13642 | { |
13643 | HOST_WIDE_INT val; | |
5895f793 | 13644 | val = ARM_SIGN_EXTEND (~INTVAL (x)); |
36ba9cb8 | 13645 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); |
4bc74ece | 13646 | } |
9997d19d RE |
13647 | else |
13648 | { | |
13649 | putc ('~', stream); | |
13650 | output_addr_const (stream, x); | |
13651 | } | |
13652 | return; | |
13653 | ||
5b3e6663 PB |
13654 | case 'L': |
13655 | /* The low 16 bits of an immediate constant. */ | |
13656 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff); | |
13657 | return; | |
13658 | ||
9997d19d RE |
13659 | case 'i': |
13660 | fprintf (stream, "%s", arithmetic_instr (x, 1)); | |
13661 | return; | |
13662 | ||
9b6b54e2 NC |
13663 | /* Truncate Cirrus shift counts. */ |
13664 | case 's': | |
13665 | if (GET_CODE (x) == CONST_INT) | |
13666 | { | |
13667 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); | |
13668 | return; | |
13669 | } | |
13670 | arm_print_operand (stream, x, 0); | |
13671 | return; | |
13672 | ||
9997d19d RE |
13673 | case 'I': |
13674 | fprintf (stream, "%s", arithmetic_instr (x, 0)); | |
13675 | return; | |
13676 | ||
13677 | case 'S': | |
13678 | { | |
13679 | HOST_WIDE_INT val; | |
beed32b8 RE |
13680 | const char *shift; |
13681 | ||
13682 | if (!shift_operator (x, SImode)) | |
13683 | { | |
13684 | output_operand_lossage ("invalid shift operand"); | |
13685 | break; | |
13686 | } | |
13687 | ||
13688 | shift = shift_op (x, &val); | |
9997d19d | 13689 | |
e2c671ba RE |
13690 | if (shift) |
13691 | { | |
beed32b8 | 13692 | fprintf (stream, ", %s ", shift); |
e2c671ba RE |
13693 | if (val == -1) |
13694 | arm_print_operand (stream, XEXP (x, 1), 0); | |
13695 | else | |
4a0a75dd | 13696 | fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); |
e2c671ba | 13697 | } |
9997d19d RE |
13698 | } |
13699 | return; | |
13700 | ||
d5b7b3ae | 13701 | /* An explanation of the 'Q', 'R' and 'H' register operands: |
f676971a | 13702 | |
d5b7b3ae RE |
13703 | In a pair of registers containing a DI or DF value the 'Q' |
13704 | operand returns the register number of the register containing | |
093354e0 | 13705 | the least significant part of the value. The 'R' operand returns |
d5b7b3ae RE |
13706 | the register number of the register containing the most |
13707 | significant part of the value. | |
f676971a | 13708 | |
d5b7b3ae RE |
13709 | The 'H' operand returns the higher of the two register numbers. |
13710 | On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the | |
093354e0 | 13711 | same as the 'Q' operand, since the most significant part of the |
d5b7b3ae RE |
13712 | value is held in the lower number register. The reverse is true |
13713 | on systems where WORDS_BIG_ENDIAN is false. | |
f676971a | 13714 | |
d5b7b3ae RE |
13715 | The purpose of these operands is to distinguish between cases |
13716 | where the endian-ness of the values is important (for example | |
13717 | when they are added together), and cases where the endian-ness | |
13718 | is irrelevant, but the order of register operations is important. | |
13719 | For example when loading a value from memory into a register | |
13720 | pair, the endian-ness does not matter. Provided that the value | |
13721 | from the lower memory address is put into the lower numbered | |
13722 | register, and the value from the higher address is put into the | |
13723 | higher numbered register, the load will work regardless of whether | |
13724 | the value being loaded is big-wordian or little-wordian. The | |
13725 | order of the two register loads can matter however, if the address | |
13726 | of the memory location is actually held in one of the registers | |
13727 | being overwritten by the load. */ | |
c1c2bc04 | 13728 | case 'Q': |
22de4c3d RE |
13729 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13730 | { | |
13731 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13732 | return; | |
13733 | } | |
13734 | ||
d5b7b3ae | 13735 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); |
c1c2bc04 RE |
13736 | return; |
13737 | ||
9997d19d | 13738 | case 'R': |
22de4c3d RE |
13739 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13740 | { | |
13741 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13742 | return; | |
13743 | } | |
13744 | ||
d5b7b3ae RE |
13745 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); |
13746 | return; | |
13747 | ||
13748 | case 'H': | |
22de4c3d RE |
13749 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) |
13750 | { | |
13751 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13752 | return; | |
13753 | } | |
13754 | ||
d5b7b3ae | 13755 | asm_fprintf (stream, "%r", REGNO (x) + 1); |
9997d19d RE |
13756 | return; |
13757 | ||
88f77cba JB |
13758 | case 'J': |
13759 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
13760 | { | |
13761 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13762 | return; | |
13763 | } | |
13764 | ||
13765 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 3 : 2)); | |
13766 | return; | |
13767 | ||
13768 | case 'K': | |
13769 | if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) | |
13770 | { | |
13771 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13772 | return; | |
13773 | } | |
13774 | ||
13775 | asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 2 : 3)); | |
13776 | return; | |
13777 | ||
9997d19d | 13778 | case 'm': |
f676971a | 13779 | asm_fprintf (stream, "%r", |
d5b7b3ae RE |
13780 | GET_CODE (XEXP (x, 0)) == REG |
13781 | ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); | |
9997d19d RE |
13782 | return; |
13783 | ||
13784 | case 'M': | |
dd18ae56 | 13785 | asm_fprintf (stream, "{%r-%r}", |
d5b7b3ae | 13786 | REGNO (x), |
e9d7b180 | 13787 | REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); |
9997d19d RE |
13788 | return; |
13789 | ||
88f77cba JB |
13790 | /* Like 'M', but writing doubleword vector registers, for use by Neon |
13791 | insns. */ | |
13792 | case 'h': | |
13793 | { | |
13794 | int regno = (REGNO (x) - FIRST_VFP_REGNUM) / 2; | |
13795 | int numregs = ARM_NUM_REGS (GET_MODE (x)) / 2; | |
13796 | if (numregs == 1) | |
13797 | asm_fprintf (stream, "{d%d}", regno); | |
13798 | else | |
13799 | asm_fprintf (stream, "{d%d-d%d}", regno, regno + numregs - 1); | |
13800 | } | |
13801 | return; | |
13802 | ||
9997d19d | 13803 | case 'd': |
64e92a26 RE |
13804 | /* CONST_TRUE_RTX means always -- that's the default. */ |
13805 | if (x == const_true_rtx) | |
d5b7b3ae | 13806 | return; |
f676971a | 13807 | |
22de4c3d RE |
13808 | if (!COMPARISON_P (x)) |
13809 | { | |
13810 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13811 | return; | |
13812 | } | |
13813 | ||
defc0463 RE |
13814 | fputs (arm_condition_codes[get_arm_condition_code (x)], |
13815 | stream); | |
9997d19d RE |
13816 | return; |
13817 | ||
13818 | case 'D': | |
112cdef5 | 13819 | /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever |
64e92a26 RE |
13820 | want to do that. */ |
13821 | if (x == const_true_rtx) | |
22de4c3d | 13822 | { |
4dad0aca | 13823 | output_operand_lossage ("instruction never executed"); |
22de4c3d RE |
13824 | return; |
13825 | } | |
13826 | if (!COMPARISON_P (x)) | |
13827 | { | |
13828 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13829 | return; | |
13830 | } | |
d5b7b3ae | 13831 | |
defc0463 RE |
13832 | fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE |
13833 | (get_arm_condition_code (x))], | |
13834 | stream); | |
9997d19d RE |
13835 | return; |
13836 | ||
9b6b54e2 NC |
13837 | /* Cirrus registers can be accessed in a variety of ways: |
13838 | single floating point (f) | |
13839 | double floating point (d) | |
13840 | 32bit integer (fx) | |
13841 | 64bit integer (dx). */ | |
13842 | case 'W': /* Cirrus register in F mode. */ | |
13843 | case 'X': /* Cirrus register in D mode. */ | |
13844 | case 'Y': /* Cirrus register in FX mode. */ | |
13845 | case 'Z': /* Cirrus register in DX mode. */ | |
e6d29d15 NS |
13846 | gcc_assert (GET_CODE (x) == REG |
13847 | && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); | |
9b6b54e2 NC |
13848 | |
13849 | fprintf (stream, "mv%s%s", | |
13850 | code == 'W' ? "f" | |
13851 | : code == 'X' ? "d" | |
13852 | : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); | |
13853 | ||
13854 | return; | |
13855 | ||
13856 | /* Print cirrus register in the mode specified by the register's mode. */ | |
13857 | case 'V': | |
13858 | { | |
13859 | int mode = GET_MODE (x); | |
13860 | ||
13861 | if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) | |
22de4c3d RE |
13862 | { |
13863 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13864 | return; | |
13865 | } | |
9b6b54e2 NC |
13866 | |
13867 | fprintf (stream, "mv%s%s", | |
13868 | mode == DFmode ? "d" | |
13869 | : mode == SImode ? "fx" | |
13870 | : mode == DImode ? "dx" | |
13871 | : "f", reg_names[REGNO (x)] + 2); | |
13872 | ||
13873 | return; | |
13874 | } | |
13875 | ||
5a9335ef NC |
13876 | case 'U': |
13877 | if (GET_CODE (x) != REG | |
13878 | || REGNO (x) < FIRST_IWMMXT_GR_REGNUM | |
13879 | || REGNO (x) > LAST_IWMMXT_GR_REGNUM) | |
13880 | /* Bad value for wCG register number. */ | |
22de4c3d RE |
13881 | { |
13882 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13883 | return; | |
13884 | } | |
13885 | ||
5a9335ef NC |
13886 | else |
13887 | fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); | |
13888 | return; | |
13889 | ||
13890 | /* Print an iWMMXt control register name. */ | |
13891 | case 'w': | |
13892 | if (GET_CODE (x) != CONST_INT | |
13893 | || INTVAL (x) < 0 | |
13894 | || INTVAL (x) >= 16) | |
13895 | /* Bad value for wC register number. */ | |
22de4c3d RE |
13896 | { |
13897 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13898 | return; | |
13899 | } | |
13900 | ||
5a9335ef NC |
13901 | else |
13902 | { | |
13903 | static const char * wc_reg_names [16] = | |
13904 | { | |
13905 | "wCID", "wCon", "wCSSF", "wCASF", | |
13906 | "wC4", "wC5", "wC6", "wC7", | |
13907 | "wCGR0", "wCGR1", "wCGR2", "wCGR3", | |
13908 | "wC12", "wC13", "wC14", "wC15" | |
13909 | }; | |
f676971a | 13910 | |
5a9335ef NC |
13911 | fprintf (stream, wc_reg_names [INTVAL (x)]); |
13912 | } | |
13913 | return; | |
13914 | ||
88f77cba | 13915 | /* Print a VFP/Neon double precision or quad precision register name. */ |
9b66ebb1 | 13916 | case 'P': |
88f77cba | 13917 | case 'q': |
9b66ebb1 PB |
13918 | { |
13919 | int mode = GET_MODE (x); | |
88f77cba JB |
13920 | int is_quad = (code == 'q'); |
13921 | int regno; | |
9b66ebb1 | 13922 | |
88f77cba | 13923 | if (GET_MODE_SIZE (mode) != (is_quad ? 16 : 8)) |
22de4c3d RE |
13924 | { |
13925 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13926 | return; | |
13927 | } | |
9b66ebb1 PB |
13928 | |
13929 | if (GET_CODE (x) != REG | |
13930 | || !IS_VFP_REGNUM (REGNO (x))) | |
22de4c3d RE |
13931 | { |
13932 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13933 | return; | |
13934 | } | |
9b66ebb1 | 13935 | |
88f77cba JB |
13936 | regno = REGNO (x); |
13937 | if ((is_quad && !NEON_REGNO_OK_FOR_QUAD (regno)) | |
13938 | || (!is_quad && !VFP_REGNO_OK_FOR_DOUBLE (regno))) | |
22de4c3d RE |
13939 | { |
13940 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13941 | return; | |
13942 | } | |
9b66ebb1 | 13943 | |
88f77cba JB |
13944 | fprintf (stream, "%c%d", is_quad ? 'q' : 'd', |
13945 | (regno - FIRST_VFP_REGNUM) >> (is_quad ? 2 : 1)); | |
13946 | } | |
13947 | return; | |
13948 | ||
13949 | /* These two codes print the low/high doubleword register of a Neon quad | |
13950 | register, respectively. For pair-structure types, can also print | |
13951 | low/high quadword registers. */ | |
13952 | case 'e': | |
13953 | case 'f': | |
13954 | { | |
13955 | int mode = GET_MODE (x); | |
13956 | int regno; | |
13957 | ||
13958 | if ((GET_MODE_SIZE (mode) != 16 | |
13959 | && GET_MODE_SIZE (mode) != 32) || GET_CODE (x) != REG) | |
13960 | { | |
13961 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13962 | return; | |
13963 | } | |
13964 | ||
13965 | regno = REGNO (x); | |
13966 | if (!NEON_REGNO_OK_FOR_QUAD (regno)) | |
13967 | { | |
13968 | output_operand_lossage ("invalid operand for code '%c'", code); | |
13969 | return; | |
13970 | } | |
13971 | ||
13972 | if (GET_MODE_SIZE (mode) == 16) | |
13973 | fprintf (stream, "d%d", ((regno - FIRST_VFP_REGNUM) >> 1) | |
13974 | + (code == 'f' ? 1 : 0)); | |
13975 | else | |
13976 | fprintf (stream, "q%d", ((regno - FIRST_VFP_REGNUM) >> 2) | |
13977 | + (code == 'f' ? 1 : 0)); | |
9b66ebb1 PB |
13978 | } |
13979 | return; | |
13980 | ||
f1adb0a9 JB |
13981 | /* Print a VFPv3 floating-point constant, represented as an integer |
13982 | index. */ | |
13983 | case 'G': | |
13984 | { | |
13985 | int index = vfp3_const_double_index (x); | |
13986 | gcc_assert (index != -1); | |
13987 | fprintf (stream, "%d", index); | |
13988 | } | |
13989 | return; | |
13990 | ||
88f77cba JB |
13991 | /* Print bits representing opcode features for Neon. |
13992 | ||
13993 | Bit 0 is 1 for signed, 0 for unsigned. Floats count as signed | |
13994 | and polynomials as unsigned. | |
13995 | ||
13996 | Bit 1 is 1 for floats and polynomials, 0 for ordinary integers. | |
13997 | ||
13998 | Bit 2 is 1 for rounding functions, 0 otherwise. */ | |
13999 | ||
14000 | /* Identify the type as 's', 'u', 'p' or 'f'. */ | |
14001 | case 'T': | |
14002 | { | |
14003 | HOST_WIDE_INT bits = INTVAL (x); | |
14004 | fputc ("uspf"[bits & 3], stream); | |
14005 | } | |
14006 | return; | |
14007 | ||
14008 | /* Likewise, but signed and unsigned integers are both 'i'. */ | |
14009 | case 'F': | |
14010 | { | |
14011 | HOST_WIDE_INT bits = INTVAL (x); | |
14012 | fputc ("iipf"[bits & 3], stream); | |
14013 | } | |
14014 | return; | |
14015 | ||
14016 | /* As for 'T', but emit 'u' instead of 'p'. */ | |
14017 | case 't': | |
14018 | { | |
14019 | HOST_WIDE_INT bits = INTVAL (x); | |
14020 | fputc ("usuf"[bits & 3], stream); | |
14021 | } | |
14022 | return; | |
14023 | ||
14024 | /* Bit 2: rounding (vs none). */ | |
14025 | case 'O': | |
14026 | { | |
14027 | HOST_WIDE_INT bits = INTVAL (x); | |
14028 | fputs ((bits & 4) != 0 ? "r" : "", stream); | |
14029 | } | |
14030 | return; | |
14031 | ||
dc34db56 PB |
14032 | /* Memory operand for vld1/vst1 instruction. */ |
14033 | case 'A': | |
14034 | { | |
14035 | rtx addr; | |
14036 | bool postinc = FALSE; | |
14037 | gcc_assert (GET_CODE (x) == MEM); | |
14038 | addr = XEXP (x, 0); | |
14039 | if (GET_CODE (addr) == POST_INC) | |
14040 | { | |
14041 | postinc = 1; | |
14042 | addr = XEXP (addr, 0); | |
14043 | } | |
14044 | asm_fprintf (stream, "[%r]", REGNO (addr)); | |
14045 | if (postinc) | |
14046 | fputs("!", stream); | |
14047 | } | |
14048 | return; | |
14049 | ||
0fd8c3ad SL |
14050 | /* Register specifier for vld1.16/vst1.16. Translate the S register |
14051 | number into a D register number and element index. */ | |
14052 | case 'z': | |
14053 | { | |
14054 | int mode = GET_MODE (x); | |
14055 | int regno; | |
14056 | ||
14057 | if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG) | |
14058 | { | |
14059 | output_operand_lossage ("invalid operand for code '%c'", code); | |
14060 | return; | |
14061 | } | |
14062 | ||
14063 | regno = REGNO (x); | |
14064 | if (!VFP_REGNO_OK_FOR_SINGLE (regno)) | |
14065 | { | |
14066 | output_operand_lossage ("invalid operand for code '%c'", code); | |
14067 | return; | |
14068 | } | |
14069 | ||
14070 | regno = regno - FIRST_VFP_REGNUM; | |
14071 | fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0)); | |
14072 | } | |
14073 | return; | |
14074 | ||
9997d19d RE |
14075 | default: |
14076 | if (x == 0) | |
22de4c3d RE |
14077 | { |
14078 | output_operand_lossage ("missing operand"); | |
14079 | return; | |
14080 | } | |
9997d19d | 14081 | |
e6d29d15 | 14082 | switch (GET_CODE (x)) |
9997d19d | 14083 | { |
e6d29d15 NS |
14084 | case REG: |
14085 | asm_fprintf (stream, "%r", REGNO (x)); | |
14086 | break; | |
14087 | ||
14088 | case MEM: | |
9997d19d RE |
14089 | output_memory_reference_mode = GET_MODE (x); |
14090 | output_address (XEXP (x, 0)); | |
e6d29d15 NS |
14091 | break; |
14092 | ||
14093 | case CONST_DOUBLE: | |
88f77cba JB |
14094 | if (TARGET_NEON) |
14095 | { | |
14096 | char fpstr[20]; | |
14097 | real_to_decimal (fpstr, CONST_DOUBLE_REAL_VALUE (x), | |
14098 | sizeof (fpstr), 0, 1); | |
14099 | fprintf (stream, "#%s", fpstr); | |
14100 | } | |
14101 | else | |
14102 | fprintf (stream, "#%s", fp_immediate_constant (x)); | |
e6d29d15 NS |
14103 | break; |
14104 | ||
14105 | default: | |
14106 | gcc_assert (GET_CODE (x) != NEG); | |
9997d19d | 14107 | fputc ('#', stream); |
d58bc084 NS |
14108 | if (GET_CODE (x) == HIGH) |
14109 | { | |
14110 | fputs (":lower16:", stream); | |
14111 | x = XEXP (x, 0); | |
14112 | } | |
14113 | ||
9997d19d | 14114 | output_addr_const (stream, x); |
e6d29d15 | 14115 | break; |
9997d19d RE |
14116 | } |
14117 | } | |
14118 | } | |
cce8749e | 14119 | \f |
301d03af RS |
14120 | /* Target hook for assembling integer objects. The ARM version needs to |
14121 | handle word-sized values specially. */ | |
301d03af | 14122 | static bool |
e32bac5b | 14123 | arm_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 14124 | { |
88f77cba JB |
14125 | enum machine_mode mode; |
14126 | ||
301d03af RS |
14127 | if (size == UNITS_PER_WORD && aligned_p) |
14128 | { | |
14129 | fputs ("\t.word\t", asm_out_file); | |
14130 | output_addr_const (asm_out_file, x); | |
14131 | ||
14132 | /* Mark symbols as position independent. We only do this in the | |
d6b4baa4 | 14133 | .text segment, not in the .data segment. */ |
301d03af RS |
14134 | if (NEED_GOT_RELOC && flag_pic && making_const_table && |
14135 | (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) | |
14136 | { | |
9403b7f7 RS |
14137 | /* See legitimize_pic_address for an explanation of the |
14138 | TARGET_VXWORKS_RTP check. */ | |
14139 | if (TARGET_VXWORKS_RTP | |
14140 | || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) | |
301d03af | 14141 | fputs ("(GOT)", asm_out_file); |
9403b7f7 RS |
14142 | else |
14143 | fputs ("(GOTOFF)", asm_out_file); | |
301d03af RS |
14144 | } |
14145 | fputc ('\n', asm_out_file); | |
14146 | return true; | |
14147 | } | |
1d6e90ac | 14148 | |
88f77cba JB |
14149 | mode = GET_MODE (x); |
14150 | ||
14151 | if (arm_vector_mode_supported_p (mode)) | |
5a9335ef NC |
14152 | { |
14153 | int i, units; | |
14154 | ||
e6d29d15 | 14155 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
14156 | |
14157 | units = CONST_VECTOR_NUNITS (x); | |
88f77cba | 14158 | size = GET_MODE_SIZE (GET_MODE_INNER (mode)); |
5a9335ef | 14159 | |
88f77cba JB |
14160 | if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) |
14161 | for (i = 0; i < units; i++) | |
14162 | { | |
874d42b9 | 14163 | rtx elt = CONST_VECTOR_ELT (x, i); |
88f77cba JB |
14164 | assemble_integer |
14165 | (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); | |
14166 | } | |
14167 | else | |
14168 | for (i = 0; i < units; i++) | |
14169 | { | |
14170 | rtx elt = CONST_VECTOR_ELT (x, i); | |
14171 | REAL_VALUE_TYPE rval; | |
5a9335ef | 14172 | |
88f77cba JB |
14173 | REAL_VALUE_FROM_CONST_DOUBLE (rval, elt); |
14174 | ||
14175 | assemble_real | |
14176 | (rval, GET_MODE_INNER (mode), | |
14177 | i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT); | |
14178 | } | |
5a9335ef NC |
14179 | |
14180 | return true; | |
14181 | } | |
14182 | ||
301d03af RS |
14183 | return default_assemble_integer (x, size, aligned_p); |
14184 | } | |
7abc66b1 | 14185 | |
7abc66b1 | 14186 | static void |
9f296620 | 14187 | arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) |
7abc66b1 | 14188 | { |
50603eed PB |
14189 | section *s; |
14190 | ||
7abc66b1 JB |
14191 | if (!TARGET_AAPCS_BASED) |
14192 | { | |
9f296620 MM |
14193 | (is_ctor ? |
14194 | default_named_section_asm_out_constructor | |
14195 | : default_named_section_asm_out_destructor) (symbol, priority); | |
7abc66b1 JB |
14196 | return; |
14197 | } | |
14198 | ||
14199 | /* Put these in the .init_array section, using a special relocation. */ | |
50603eed PB |
14200 | if (priority != DEFAULT_INIT_PRIORITY) |
14201 | { | |
14202 | char buf[18]; | |
9f296620 MM |
14203 | sprintf (buf, "%s.%.5u", |
14204 | is_ctor ? ".init_array" : ".fini_array", | |
14205 | priority); | |
50603eed PB |
14206 | s = get_section (buf, SECTION_WRITE, NULL_TREE); |
14207 | } | |
9f296620 | 14208 | else if (is_ctor) |
50603eed | 14209 | s = ctors_section; |
9f296620 MM |
14210 | else |
14211 | s = dtors_section; | |
50603eed PB |
14212 | |
14213 | switch_to_section (s); | |
7abc66b1 JB |
14214 | assemble_align (POINTER_SIZE); |
14215 | fputs ("\t.word\t", asm_out_file); | |
14216 | output_addr_const (asm_out_file, symbol); | |
14217 | fputs ("(target1)\n", asm_out_file); | |
14218 | } | |
9f296620 MM |
14219 | |
14220 | /* Add a function to the list of static constructors. */ | |
14221 | ||
14222 | static void | |
14223 | arm_elf_asm_constructor (rtx symbol, int priority) | |
14224 | { | |
14225 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true); | |
14226 | } | |
14227 | ||
14228 | /* Add a function to the list of static destructors. */ | |
14229 | ||
14230 | static void | |
14231 | arm_elf_asm_destructor (rtx symbol, int priority) | |
14232 | { | |
14233 | arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false); | |
14234 | } | |
301d03af | 14235 | \f |
cce8749e CH |
14236 | /* A finite state machine takes care of noticing whether or not instructions |
14237 | can be conditionally executed, and thus decrease execution time and code | |
14238 | size by deleting branch instructions. The fsm is controlled by | |
14239 | final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ | |
14240 | ||
14241 | /* The state of the fsm controlling condition codes are: | |
14242 | 0: normal, do nothing special | |
14243 | 1: make ASM_OUTPUT_OPCODE not output this instruction | |
14244 | 2: make ASM_OUTPUT_OPCODE not output this instruction | |
14245 | 3: make instructions conditional | |
14246 | 4: make instructions conditional | |
14247 | ||
14248 | State transitions (state->state by whom under condition): | |
14249 | 0 -> 1 final_prescan_insn if the `target' is a label | |
14250 | 0 -> 2 final_prescan_insn if the `target' is an unconditional branch | |
14251 | 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
14252 | 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch | |
4977bab6 | 14253 | 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached |
cce8749e CH |
14254 | (the target label has CODE_LABEL_NUMBER equal to arm_target_label). |
14255 | 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached | |
14256 | (the target insn is arm_target_insn). | |
14257 | ||
ff9940b0 RE |
14258 | If the jump clobbers the conditions then we use states 2 and 4. |
14259 | ||
14260 | A similar thing can be done with conditional return insns. | |
14261 | ||
cce8749e CH |
14262 | XXX In case the `target' is an unconditional branch, this conditionalising |
14263 | of the instructions always reduces code size, but not always execution | |
14264 | time. But then, I want to reduce the code size to somewhere near what | |
14265 | /bin/cc produces. */ | |
14266 | ||
5b3e6663 PB |
14267 | /* In addition to this, state is maintained for Thumb-2 COND_EXEC |
14268 | instructions. When a COND_EXEC instruction is seen the subsequent | |
14269 | instructions are scanned so that multiple conditional instructions can be | |
14270 | combined into a single IT block. arm_condexec_count and arm_condexec_mask | |
14271 | specify the length and true/false mask for the IT block. These will be | |
14272 | decremented/zeroed by arm_asm_output_opcode as the insns are output. */ | |
14273 | ||
cce8749e CH |
14274 | /* Returns the index of the ARM condition code string in |
14275 | `arm_condition_codes'. COMPARISON should be an rtx like | |
14276 | `(eq (...) (...))'. */ | |
84ed5e79 | 14277 | static enum arm_cond_code |
e32bac5b | 14278 | get_arm_condition_code (rtx comparison) |
cce8749e | 14279 | { |
5165176d | 14280 | enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); |
81f40b79 | 14281 | enum arm_cond_code code; |
1d6e90ac | 14282 | enum rtx_code comp_code = GET_CODE (comparison); |
5165176d RE |
14283 | |
14284 | if (GET_MODE_CLASS (mode) != MODE_CC) | |
84ed5e79 | 14285 | mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), |
5165176d RE |
14286 | XEXP (comparison, 1)); |
14287 | ||
14288 | switch (mode) | |
cce8749e | 14289 | { |
84ed5e79 RE |
14290 | case CC_DNEmode: code = ARM_NE; goto dominance; |
14291 | case CC_DEQmode: code = ARM_EQ; goto dominance; | |
14292 | case CC_DGEmode: code = ARM_GE; goto dominance; | |
14293 | case CC_DGTmode: code = ARM_GT; goto dominance; | |
14294 | case CC_DLEmode: code = ARM_LE; goto dominance; | |
14295 | case CC_DLTmode: code = ARM_LT; goto dominance; | |
14296 | case CC_DGEUmode: code = ARM_CS; goto dominance; | |
14297 | case CC_DGTUmode: code = ARM_HI; goto dominance; | |
14298 | case CC_DLEUmode: code = ARM_LS; goto dominance; | |
14299 | case CC_DLTUmode: code = ARM_CC; | |
14300 | ||
14301 | dominance: | |
e6d29d15 | 14302 | gcc_assert (comp_code == EQ || comp_code == NE); |
84ed5e79 RE |
14303 | |
14304 | if (comp_code == EQ) | |
14305 | return ARM_INVERSE_CONDITION_CODE (code); | |
14306 | return code; | |
14307 | ||
5165176d | 14308 | case CC_NOOVmode: |
84ed5e79 | 14309 | switch (comp_code) |
5165176d | 14310 | { |
84ed5e79 RE |
14311 | case NE: return ARM_NE; |
14312 | case EQ: return ARM_EQ; | |
14313 | case GE: return ARM_PL; | |
14314 | case LT: return ARM_MI; | |
e6d29d15 | 14315 | default: gcc_unreachable (); |
5165176d RE |
14316 | } |
14317 | ||
14318 | case CC_Zmode: | |
84ed5e79 | 14319 | switch (comp_code) |
5165176d | 14320 | { |
84ed5e79 RE |
14321 | case NE: return ARM_NE; |
14322 | case EQ: return ARM_EQ; | |
e6d29d15 | 14323 | default: gcc_unreachable (); |
5165176d RE |
14324 | } |
14325 | ||
defc0463 RE |
14326 | case CC_Nmode: |
14327 | switch (comp_code) | |
14328 | { | |
14329 | case NE: return ARM_MI; | |
14330 | case EQ: return ARM_PL; | |
e6d29d15 | 14331 | default: gcc_unreachable (); |
defc0463 RE |
14332 | } |
14333 | ||
5165176d | 14334 | case CCFPEmode: |
e45b72c4 RE |
14335 | case CCFPmode: |
14336 | /* These encodings assume that AC=1 in the FPA system control | |
14337 | byte. This allows us to handle all cases except UNEQ and | |
14338 | LTGT. */ | |
84ed5e79 RE |
14339 | switch (comp_code) |
14340 | { | |
14341 | case GE: return ARM_GE; | |
14342 | case GT: return ARM_GT; | |
14343 | case LE: return ARM_LS; | |
14344 | case LT: return ARM_MI; | |
e45b72c4 RE |
14345 | case NE: return ARM_NE; |
14346 | case EQ: return ARM_EQ; | |
14347 | case ORDERED: return ARM_VC; | |
14348 | case UNORDERED: return ARM_VS; | |
14349 | case UNLT: return ARM_LT; | |
14350 | case UNLE: return ARM_LE; | |
14351 | case UNGT: return ARM_HI; | |
14352 | case UNGE: return ARM_PL; | |
14353 | /* UNEQ and LTGT do not have a representation. */ | |
14354 | case UNEQ: /* Fall through. */ | |
14355 | case LTGT: /* Fall through. */ | |
e6d29d15 | 14356 | default: gcc_unreachable (); |
84ed5e79 RE |
14357 | } |
14358 | ||
14359 | case CC_SWPmode: | |
14360 | switch (comp_code) | |
14361 | { | |
14362 | case NE: return ARM_NE; | |
14363 | case EQ: return ARM_EQ; | |
14364 | case GE: return ARM_LE; | |
14365 | case GT: return ARM_LT; | |
14366 | case LE: return ARM_GE; | |
14367 | case LT: return ARM_GT; | |
14368 | case GEU: return ARM_LS; | |
14369 | case GTU: return ARM_CC; | |
14370 | case LEU: return ARM_CS; | |
14371 | case LTU: return ARM_HI; | |
e6d29d15 | 14372 | default: gcc_unreachable (); |
84ed5e79 RE |
14373 | } |
14374 | ||
bd9c7e23 RE |
14375 | case CC_Cmode: |
14376 | switch (comp_code) | |
14377 | { | |
14378 | case LTU: return ARM_CS; | |
14379 | case GEU: return ARM_CC; | |
e6d29d15 | 14380 | default: gcc_unreachable (); |
bd9c7e23 | 14381 | } |
f676971a | 14382 | |
5165176d | 14383 | case CCmode: |
84ed5e79 | 14384 | switch (comp_code) |
5165176d | 14385 | { |
84ed5e79 RE |
14386 | case NE: return ARM_NE; |
14387 | case EQ: return ARM_EQ; | |
14388 | case GE: return ARM_GE; | |
14389 | case GT: return ARM_GT; | |
14390 | case LE: return ARM_LE; | |
14391 | case LT: return ARM_LT; | |
14392 | case GEU: return ARM_CS; | |
14393 | case GTU: return ARM_HI; | |
14394 | case LEU: return ARM_LS; | |
14395 | case LTU: return ARM_CC; | |
e6d29d15 | 14396 | default: gcc_unreachable (); |
5165176d RE |
14397 | } |
14398 | ||
e6d29d15 | 14399 | default: gcc_unreachable (); |
cce8749e | 14400 | } |
f3bb6135 | 14401 | } |
cce8749e | 14402 | |
44c7bd63 | 14403 | /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed |
5b3e6663 PB |
14404 | instructions. */ |
14405 | void | |
14406 | thumb2_final_prescan_insn (rtx insn) | |
14407 | { | |
14408 | rtx first_insn = insn; | |
14409 | rtx body = PATTERN (insn); | |
14410 | rtx predicate; | |
14411 | enum arm_cond_code code; | |
14412 | int n; | |
14413 | int mask; | |
14414 | ||
14415 | /* Remove the previous insn from the count of insns to be output. */ | |
14416 | if (arm_condexec_count) | |
14417 | arm_condexec_count--; | |
14418 | ||
14419 | /* Nothing to do if we are already inside a conditional block. */ | |
14420 | if (arm_condexec_count) | |
14421 | return; | |
14422 | ||
14423 | if (GET_CODE (body) != COND_EXEC) | |
14424 | return; | |
14425 | ||
14426 | /* Conditional jumps are implemented directly. */ | |
14427 | if (GET_CODE (insn) == JUMP_INSN) | |
14428 | return; | |
14429 | ||
14430 | predicate = COND_EXEC_TEST (body); | |
14431 | arm_current_cc = get_arm_condition_code (predicate); | |
14432 | ||
14433 | n = get_attr_ce_count (insn); | |
14434 | arm_condexec_count = 1; | |
14435 | arm_condexec_mask = (1 << n) - 1; | |
14436 | arm_condexec_masklen = n; | |
14437 | /* See if subsequent instructions can be combined into the same block. */ | |
14438 | for (;;) | |
14439 | { | |
14440 | insn = next_nonnote_insn (insn); | |
14441 | ||
14442 | /* Jumping into the middle of an IT block is illegal, so a label or | |
14443 | barrier terminates the block. */ | |
14444 | if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN) | |
14445 | break; | |
14446 | ||
14447 | body = PATTERN (insn); | |
14448 | /* USE and CLOBBER aren't really insns, so just skip them. */ | |
14449 | if (GET_CODE (body) == USE | |
14450 | || GET_CODE (body) == CLOBBER) | |
5b0202af | 14451 | continue; |
5b3e6663 | 14452 | |
7a085dce | 14453 | /* ??? Recognize conditional jumps, and combine them with IT blocks. */ |
5b3e6663 PB |
14454 | if (GET_CODE (body) != COND_EXEC) |
14455 | break; | |
14456 | /* Allow up to 4 conditionally executed instructions in a block. */ | |
14457 | n = get_attr_ce_count (insn); | |
14458 | if (arm_condexec_masklen + n > 4) | |
14459 | break; | |
14460 | ||
14461 | predicate = COND_EXEC_TEST (body); | |
14462 | code = get_arm_condition_code (predicate); | |
14463 | mask = (1 << n) - 1; | |
14464 | if (arm_current_cc == code) | |
14465 | arm_condexec_mask |= (mask << arm_condexec_masklen); | |
14466 | else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code)) | |
14467 | break; | |
14468 | ||
14469 | arm_condexec_count++; | |
14470 | arm_condexec_masklen += n; | |
14471 | ||
14472 | /* A jump must be the last instruction in a conditional block. */ | |
14473 | if (GET_CODE(insn) == JUMP_INSN) | |
14474 | break; | |
14475 | } | |
14476 | /* Restore recog_data (getting the attributes of other insns can | |
14477 | destroy this array, but final.c assumes that it remains intact | |
14478 | across this call). */ | |
14479 | extract_constrain_insn_cached (first_insn); | |
14480 | } | |
14481 | ||
cce8749e | 14482 | void |
e32bac5b | 14483 | arm_final_prescan_insn (rtx insn) |
cce8749e CH |
14484 | { |
14485 | /* BODY will hold the body of INSN. */ | |
1d6e90ac | 14486 | rtx body = PATTERN (insn); |
cce8749e CH |
14487 | |
14488 | /* This will be 1 if trying to repeat the trick, and things need to be | |
14489 | reversed if it appears to fail. */ | |
14490 | int reverse = 0; | |
14491 | ||
ff9940b0 RE |
14492 | /* JUMP_CLOBBERS will be one implies that the conditions if a branch is |
14493 | taken are clobbered, even if the rtl suggests otherwise. It also | |
14494 | means that we have to grub around within the jump expression to find | |
14495 | out what the conditions are when the jump isn't taken. */ | |
14496 | int jump_clobbers = 0; | |
f676971a | 14497 | |
6354dc9b | 14498 | /* If we start with a return insn, we only succeed if we find another one. */ |
ff9940b0 | 14499 | int seeking_return = 0; |
f676971a | 14500 | |
cce8749e CH |
14501 | /* START_INSN will hold the insn from where we start looking. This is the |
14502 | first insn after the following code_label if REVERSE is true. */ | |
14503 | rtx start_insn = insn; | |
14504 | ||
14505 | /* If in state 4, check if the target branch is reached, in order to | |
14506 | change back to state 0. */ | |
14507 | if (arm_ccfsm_state == 4) | |
14508 | { | |
14509 | if (insn == arm_target_insn) | |
f5a1b0d2 NC |
14510 | { |
14511 | arm_target_insn = NULL; | |
14512 | arm_ccfsm_state = 0; | |
14513 | } | |
cce8749e CH |
14514 | return; |
14515 | } | |
14516 | ||
14517 | /* If in state 3, it is possible to repeat the trick, if this insn is an | |
14518 | unconditional branch to a label, and immediately following this branch | |
14519 | is the previous target label which is only used once, and the label this | |
14520 | branch jumps to is not too far off. */ | |
14521 | if (arm_ccfsm_state == 3) | |
14522 | { | |
14523 | if (simplejump_p (insn)) | |
14524 | { | |
14525 | start_insn = next_nonnote_insn (start_insn); | |
14526 | if (GET_CODE (start_insn) == BARRIER) | |
14527 | { | |
14528 | /* XXX Isn't this always a barrier? */ | |
14529 | start_insn = next_nonnote_insn (start_insn); | |
14530 | } | |
14531 | if (GET_CODE (start_insn) == CODE_LABEL | |
14532 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
14533 | && LABEL_NUSES (start_insn) == 1) | |
14534 | reverse = TRUE; | |
14535 | else | |
14536 | return; | |
14537 | } | |
ff9940b0 RE |
14538 | else if (GET_CODE (body) == RETURN) |
14539 | { | |
14540 | start_insn = next_nonnote_insn (start_insn); | |
14541 | if (GET_CODE (start_insn) == BARRIER) | |
14542 | start_insn = next_nonnote_insn (start_insn); | |
14543 | if (GET_CODE (start_insn) == CODE_LABEL | |
14544 | && CODE_LABEL_NUMBER (start_insn) == arm_target_label | |
14545 | && LABEL_NUSES (start_insn) == 1) | |
14546 | { | |
14547 | reverse = TRUE; | |
14548 | seeking_return = 1; | |
14549 | } | |
14550 | else | |
14551 | return; | |
14552 | } | |
cce8749e CH |
14553 | else |
14554 | return; | |
14555 | } | |
14556 | ||
e6d29d15 | 14557 | gcc_assert (!arm_ccfsm_state || reverse); |
cce8749e CH |
14558 | if (GET_CODE (insn) != JUMP_INSN) |
14559 | return; | |
14560 | ||
f676971a | 14561 | /* This jump might be paralleled with a clobber of the condition codes |
ff9940b0 RE |
14562 | the jump should always come first */ |
14563 | if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) | |
14564 | body = XVECEXP (body, 0, 0); | |
14565 | ||
cce8749e CH |
14566 | if (reverse |
14567 | || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC | |
14568 | && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) | |
14569 | { | |
bd9c7e23 RE |
14570 | int insns_skipped; |
14571 | int fail = FALSE, succeed = FALSE; | |
cce8749e CH |
14572 | /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ |
14573 | int then_not_else = TRUE; | |
ff9940b0 | 14574 | rtx this_insn = start_insn, label = 0; |
cce8749e | 14575 | |
f676971a | 14576 | /* If the jump cannot be done with one instruction, we cannot |
e45b72c4 | 14577 | conditionally execute the instruction in the inverse case. */ |
ff9940b0 | 14578 | if (get_attr_conds (insn) == CONDS_JUMP_CLOB) |
5bbe2d40 | 14579 | { |
5bbe2d40 RE |
14580 | jump_clobbers = 1; |
14581 | return; | |
14582 | } | |
f676971a | 14583 | |
cce8749e CH |
14584 | /* Register the insn jumped to. */ |
14585 | if (reverse) | |
ff9940b0 RE |
14586 | { |
14587 | if (!seeking_return) | |
14588 | label = XEXP (SET_SRC (body), 0); | |
14589 | } | |
cce8749e CH |
14590 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) |
14591 | label = XEXP (XEXP (SET_SRC (body), 1), 0); | |
14592 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) | |
14593 | { | |
14594 | label = XEXP (XEXP (SET_SRC (body), 2), 0); | |
14595 | then_not_else = FALSE; | |
14596 | } | |
ff9940b0 RE |
14597 | else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) |
14598 | seeking_return = 1; | |
14599 | else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) | |
14600 | { | |
14601 | seeking_return = 1; | |
14602 | then_not_else = FALSE; | |
14603 | } | |
cce8749e | 14604 | else |
e6d29d15 | 14605 | gcc_unreachable (); |
cce8749e CH |
14606 | |
14607 | /* See how many insns this branch skips, and what kind of insns. If all | |
14608 | insns are okay, and the label or unconditional branch to the same | |
14609 | label is not too far away, succeed. */ | |
14610 | for (insns_skipped = 0; | |
b36ba79f | 14611 | !fail && !succeed && insns_skipped++ < max_insns_skipped;) |
cce8749e CH |
14612 | { |
14613 | rtx scanbody; | |
14614 | ||
14615 | this_insn = next_nonnote_insn (this_insn); | |
14616 | if (!this_insn) | |
14617 | break; | |
14618 | ||
cce8749e CH |
14619 | switch (GET_CODE (this_insn)) |
14620 | { | |
14621 | case CODE_LABEL: | |
14622 | /* Succeed if it is the target label, otherwise fail since | |
14623 | control falls in from somewhere else. */ | |
14624 | if (this_insn == label) | |
14625 | { | |
ff9940b0 RE |
14626 | if (jump_clobbers) |
14627 | { | |
14628 | arm_ccfsm_state = 2; | |
14629 | this_insn = next_nonnote_insn (this_insn); | |
14630 | } | |
14631 | else | |
14632 | arm_ccfsm_state = 1; | |
cce8749e CH |
14633 | succeed = TRUE; |
14634 | } | |
14635 | else | |
14636 | fail = TRUE; | |
14637 | break; | |
14638 | ||
ff9940b0 | 14639 | case BARRIER: |
cce8749e | 14640 | /* Succeed if the following insn is the target label. |
f676971a EC |
14641 | Otherwise fail. |
14642 | If return insns are used then the last insn in a function | |
6354dc9b | 14643 | will be a barrier. */ |
cce8749e | 14644 | this_insn = next_nonnote_insn (this_insn); |
ff9940b0 | 14645 | if (this_insn && this_insn == label) |
cce8749e | 14646 | { |
ff9940b0 RE |
14647 | if (jump_clobbers) |
14648 | { | |
14649 | arm_ccfsm_state = 2; | |
14650 | this_insn = next_nonnote_insn (this_insn); | |
14651 | } | |
14652 | else | |
14653 | arm_ccfsm_state = 1; | |
cce8749e CH |
14654 | succeed = TRUE; |
14655 | } | |
14656 | else | |
14657 | fail = TRUE; | |
14658 | break; | |
14659 | ||
ff9940b0 | 14660 | case CALL_INSN: |
68d560d4 RE |
14661 | /* The AAPCS says that conditional calls should not be |
14662 | used since they make interworking inefficient (the | |
14663 | linker can't transform BL<cond> into BLX). That's | |
14664 | only a problem if the machine has BLX. */ | |
14665 | if (arm_arch5) | |
14666 | { | |
14667 | fail = TRUE; | |
14668 | break; | |
14669 | } | |
14670 | ||
61f0ccff RE |
14671 | /* Succeed if the following insn is the target label, or |
14672 | if the following two insns are a barrier and the | |
14673 | target label. */ | |
14674 | this_insn = next_nonnote_insn (this_insn); | |
14675 | if (this_insn && GET_CODE (this_insn) == BARRIER) | |
14676 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 | 14677 | |
61f0ccff RE |
14678 | if (this_insn && this_insn == label |
14679 | && insns_skipped < max_insns_skipped) | |
14680 | { | |
14681 | if (jump_clobbers) | |
bd9c7e23 | 14682 | { |
61f0ccff RE |
14683 | arm_ccfsm_state = 2; |
14684 | this_insn = next_nonnote_insn (this_insn); | |
bd9c7e23 RE |
14685 | } |
14686 | else | |
61f0ccff RE |
14687 | arm_ccfsm_state = 1; |
14688 | succeed = TRUE; | |
bd9c7e23 | 14689 | } |
61f0ccff RE |
14690 | else |
14691 | fail = TRUE; | |
ff9940b0 | 14692 | break; |
2b835d68 | 14693 | |
cce8749e CH |
14694 | case JUMP_INSN: |
14695 | /* If this is an unconditional branch to the same label, succeed. | |
14696 | If it is to another label, do nothing. If it is conditional, | |
14697 | fail. */ | |
e32bac5b RE |
14698 | /* XXX Probably, the tests for SET and the PC are |
14699 | unnecessary. */ | |
cce8749e | 14700 | |
ed4c4348 | 14701 | scanbody = PATTERN (this_insn); |
ff9940b0 RE |
14702 | if (GET_CODE (scanbody) == SET |
14703 | && GET_CODE (SET_DEST (scanbody)) == PC) | |
cce8749e CH |
14704 | { |
14705 | if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF | |
14706 | && XEXP (SET_SRC (scanbody), 0) == label && !reverse) | |
14707 | { | |
14708 | arm_ccfsm_state = 2; | |
14709 | succeed = TRUE; | |
14710 | } | |
14711 | else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) | |
14712 | fail = TRUE; | |
14713 | } | |
112cdef5 | 14714 | /* Fail if a conditional return is undesirable (e.g. on a |
b36ba79f RE |
14715 | StrongARM), but still allow this if optimizing for size. */ |
14716 | else if (GET_CODE (scanbody) == RETURN | |
a72d4945 | 14717 | && !use_return_insn (TRUE, NULL) |
5895f793 | 14718 | && !optimize_size) |
b36ba79f | 14719 | fail = TRUE; |
ff9940b0 RE |
14720 | else if (GET_CODE (scanbody) == RETURN |
14721 | && seeking_return) | |
14722 | { | |
14723 | arm_ccfsm_state = 2; | |
14724 | succeed = TRUE; | |
14725 | } | |
14726 | else if (GET_CODE (scanbody) == PARALLEL) | |
14727 | { | |
14728 | switch (get_attr_conds (this_insn)) | |
14729 | { | |
14730 | case CONDS_NOCOND: | |
14731 | break; | |
14732 | default: | |
14733 | fail = TRUE; | |
14734 | break; | |
14735 | } | |
14736 | } | |
4e67550b | 14737 | else |
112cdef5 | 14738 | fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ |
4e67550b | 14739 | |
cce8749e CH |
14740 | break; |
14741 | ||
14742 | case INSN: | |
ff9940b0 RE |
14743 | /* Instructions using or affecting the condition codes make it |
14744 | fail. */ | |
ed4c4348 | 14745 | scanbody = PATTERN (this_insn); |
5895f793 RE |
14746 | if (!(GET_CODE (scanbody) == SET |
14747 | || GET_CODE (scanbody) == PARALLEL) | |
74641843 | 14748 | || get_attr_conds (this_insn) != CONDS_NOCOND) |
cce8749e | 14749 | fail = TRUE; |
9b6b54e2 NC |
14750 | |
14751 | /* A conditional cirrus instruction must be followed by | |
14752 | a non Cirrus instruction. However, since we | |
14753 | conditionalize instructions in this function and by | |
14754 | the time we get here we can't add instructions | |
14755 | (nops), because shorten_branches() has already been | |
14756 | called, we will disable conditionalizing Cirrus | |
14757 | instructions to be safe. */ | |
14758 | if (GET_CODE (scanbody) != USE | |
14759 | && GET_CODE (scanbody) != CLOBBER | |
f0375c66 | 14760 | && get_attr_cirrus (this_insn) != CIRRUS_NOT) |
9b6b54e2 | 14761 | fail = TRUE; |
cce8749e CH |
14762 | break; |
14763 | ||
14764 | default: | |
14765 | break; | |
14766 | } | |
14767 | } | |
14768 | if (succeed) | |
14769 | { | |
ff9940b0 | 14770 | if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) |
cce8749e | 14771 | arm_target_label = CODE_LABEL_NUMBER (label); |
e6d29d15 | 14772 | else |
ff9940b0 | 14773 | { |
e6d29d15 | 14774 | gcc_assert (seeking_return || arm_ccfsm_state == 2); |
e0b92319 | 14775 | |
ff9940b0 RE |
14776 | while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) |
14777 | { | |
14778 | this_insn = next_nonnote_insn (this_insn); | |
e6d29d15 NS |
14779 | gcc_assert (!this_insn |
14780 | || (GET_CODE (this_insn) != BARRIER | |
14781 | && GET_CODE (this_insn) != CODE_LABEL)); | |
ff9940b0 RE |
14782 | } |
14783 | if (!this_insn) | |
14784 | { | |
d6b4baa4 | 14785 | /* Oh, dear! we ran off the end.. give up. */ |
5b3e6663 | 14786 | extract_constrain_insn_cached (insn); |
ff9940b0 | 14787 | arm_ccfsm_state = 0; |
abaa26e5 | 14788 | arm_target_insn = NULL; |
ff9940b0 RE |
14789 | return; |
14790 | } | |
14791 | arm_target_insn = this_insn; | |
14792 | } | |
ff9940b0 RE |
14793 | if (jump_clobbers) |
14794 | { | |
e6d29d15 | 14795 | gcc_assert (!reverse); |
f676971a | 14796 | arm_current_cc = |
ff9940b0 RE |
14797 | get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), |
14798 | 0), 0), 1)); | |
14799 | if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) | |
14800 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14801 | if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) | |
14802 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14803 | } | |
14804 | else | |
14805 | { | |
14806 | /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from | |
14807 | what it was. */ | |
14808 | if (!reverse) | |
14809 | arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), | |
14810 | 0)); | |
14811 | } | |
cce8749e | 14812 | |
cce8749e CH |
14813 | if (reverse || then_not_else) |
14814 | arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); | |
14815 | } | |
f676971a | 14816 | |
1ccbefce | 14817 | /* Restore recog_data (getting the attributes of other insns can |
ff9940b0 | 14818 | destroy this array, but final.c assumes that it remains intact |
5b3e6663 PB |
14819 | across this call. */ |
14820 | extract_constrain_insn_cached (insn); | |
14821 | } | |
14822 | } | |
14823 | ||
14824 | /* Output IT instructions. */ | |
14825 | void | |
14826 | thumb2_asm_output_opcode (FILE * stream) | |
14827 | { | |
14828 | char buff[5]; | |
14829 | int n; | |
14830 | ||
14831 | if (arm_condexec_mask) | |
14832 | { | |
14833 | for (n = 0; n < arm_condexec_masklen; n++) | |
14834 | buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e'; | |
14835 | buff[n] = 0; | |
14836 | asm_fprintf(stream, "i%s\t%s\n\t", buff, | |
14837 | arm_condition_codes[arm_current_cc]); | |
14838 | arm_condexec_mask = 0; | |
cce8749e | 14839 | } |
f3bb6135 | 14840 | } |
cce8749e | 14841 | |
4b02997f | 14842 | /* Returns true if REGNO is a valid register |
21b5653c | 14843 | for holding a quantity of type MODE. */ |
4b02997f | 14844 | int |
e32bac5b | 14845 | arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) |
4b02997f NC |
14846 | { |
14847 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
a6a5de04 RE |
14848 | return (regno == CC_REGNUM |
14849 | || (TARGET_HARD_FLOAT && TARGET_VFP | |
14850 | && regno == VFPCC_REGNUM)); | |
f676971a | 14851 | |
5b3e6663 | 14852 | if (TARGET_THUMB1) |
4b02997f NC |
14853 | /* For the Thumb we only allow values bigger than SImode in |
14854 | registers 0 - 6, so that there is always a second low | |
14855 | register available to hold the upper part of the value. | |
14856 | We probably we ought to ensure that the register is the | |
14857 | start of an even numbered register pair. */ | |
e9d7b180 | 14858 | return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); |
4b02997f | 14859 | |
a6a5de04 RE |
14860 | if (TARGET_HARD_FLOAT && TARGET_MAVERICK |
14861 | && IS_CIRRUS_REGNUM (regno)) | |
9b6b54e2 NC |
14862 | /* We have outlawed SI values in Cirrus registers because they |
14863 | reside in the lower 32 bits, but SF values reside in the | |
14864 | upper 32 bits. This causes gcc all sorts of grief. We can't | |
14865 | even split the registers into pairs because Cirrus SI values | |
14866 | get sign extended to 64bits-- aldyh. */ | |
14867 | return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); | |
14868 | ||
a6a5de04 RE |
14869 | if (TARGET_HARD_FLOAT && TARGET_VFP |
14870 | && IS_VFP_REGNUM (regno)) | |
9b66ebb1 PB |
14871 | { |
14872 | if (mode == SFmode || mode == SImode) | |
f1adb0a9 | 14873 | return VFP_REGNO_OK_FOR_SINGLE (regno); |
9b66ebb1 | 14874 | |
9b66ebb1 | 14875 | if (mode == DFmode) |
f1adb0a9 | 14876 | return VFP_REGNO_OK_FOR_DOUBLE (regno); |
88f77cba | 14877 | |
0fd8c3ad SL |
14878 | /* VFP registers can hold HFmode values, but there is no point in |
14879 | putting them there unless we have the NEON extensions for | |
14880 | loading/storing them, too. */ | |
14881 | if (mode == HFmode) | |
14882 | return TARGET_NEON_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno); | |
14883 | ||
88f77cba JB |
14884 | if (TARGET_NEON) |
14885 | return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno)) | |
14886 | || (VALID_NEON_QREG_MODE (mode) | |
14887 | && NEON_REGNO_OK_FOR_QUAD (regno)) | |
14888 | || (mode == TImode && NEON_REGNO_OK_FOR_NREGS (regno, 2)) | |
14889 | || (mode == EImode && NEON_REGNO_OK_FOR_NREGS (regno, 3)) | |
14890 | || (mode == OImode && NEON_REGNO_OK_FOR_NREGS (regno, 4)) | |
14891 | || (mode == CImode && NEON_REGNO_OK_FOR_NREGS (regno, 6)) | |
14892 | || (mode == XImode && NEON_REGNO_OK_FOR_NREGS (regno, 8)); | |
14893 | ||
9b66ebb1 PB |
14894 | return FALSE; |
14895 | } | |
14896 | ||
a6a5de04 RE |
14897 | if (TARGET_REALLY_IWMMXT) |
14898 | { | |
14899 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
14900 | return mode == SImode; | |
5a9335ef | 14901 | |
a6a5de04 RE |
14902 | if (IS_IWMMXT_REGNUM (regno)) |
14903 | return VALID_IWMMXT_REG_MODE (mode); | |
14904 | } | |
14905 | ||
2e94c12d | 14906 | /* We allow almost any value to be stored in the general registers. |
fdd695fd | 14907 | Restrict doubleword quantities to even register pairs so that we can |
2e94c12d JB |
14908 | use ldrd. Do not allow very large Neon structure opaque modes in |
14909 | general registers; they would use too many. */ | |
4b02997f | 14910 | if (regno <= LAST_ARM_REGNUM) |
88f77cba | 14911 | return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) |
2e94c12d | 14912 | && ARM_NUM_REGS (mode) <= 4; |
4b02997f | 14913 | |
a6a5de04 | 14914 | if (regno == FRAME_POINTER_REGNUM |
4b02997f NC |
14915 | || regno == ARG_POINTER_REGNUM) |
14916 | /* We only allow integers in the fake hard registers. */ | |
14917 | return GET_MODE_CLASS (mode) == MODE_INT; | |
14918 | ||
3b684012 | 14919 | /* The only registers left are the FPA registers |
4b02997f | 14920 | which we only allow to hold FP values. */ |
a6a5de04 RE |
14921 | return (TARGET_HARD_FLOAT && TARGET_FPA |
14922 | && GET_MODE_CLASS (mode) == MODE_FLOAT | |
14923 | && regno >= FIRST_FPA_REGNUM | |
14924 | && regno <= LAST_FPA_REGNUM); | |
4b02997f NC |
14925 | } |
14926 | ||
5b3e6663 PB |
14927 | /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are |
14928 | not used in arm mode. */ | |
bbbbb16a ILT |
14929 | |
14930 | enum reg_class | |
e32bac5b | 14931 | arm_regno_class (int regno) |
d5b7b3ae | 14932 | { |
5b3e6663 | 14933 | if (TARGET_THUMB1) |
d5b7b3ae RE |
14934 | { |
14935 | if (regno == STACK_POINTER_REGNUM) | |
14936 | return STACK_REG; | |
14937 | if (regno == CC_REGNUM) | |
14938 | return CC_REG; | |
14939 | if (regno < 8) | |
14940 | return LO_REGS; | |
14941 | return HI_REGS; | |
14942 | } | |
14943 | ||
5b3e6663 PB |
14944 | if (TARGET_THUMB2 && regno < 8) |
14945 | return LO_REGS; | |
14946 | ||
d5b7b3ae RE |
14947 | if ( regno <= LAST_ARM_REGNUM |
14948 | || regno == FRAME_POINTER_REGNUM | |
14949 | || regno == ARG_POINTER_REGNUM) | |
5b3e6663 | 14950 | return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS; |
f676971a | 14951 | |
9b66ebb1 | 14952 | if (regno == CC_REGNUM || regno == VFPCC_REGNUM) |
5b3e6663 | 14953 | return TARGET_THUMB2 ? CC_REG : NO_REGS; |
d5b7b3ae | 14954 | |
9b6b54e2 NC |
14955 | if (IS_CIRRUS_REGNUM (regno)) |
14956 | return CIRRUS_REGS; | |
14957 | ||
9b66ebb1 | 14958 | if (IS_VFP_REGNUM (regno)) |
f1adb0a9 JB |
14959 | { |
14960 | if (regno <= D7_VFP_REGNUM) | |
14961 | return VFP_D0_D7_REGS; | |
14962 | else if (regno <= LAST_LO_VFP_REGNUM) | |
14963 | return VFP_LO_REGS; | |
14964 | else | |
14965 | return VFP_HI_REGS; | |
14966 | } | |
9b66ebb1 | 14967 | |
5a9335ef NC |
14968 | if (IS_IWMMXT_REGNUM (regno)) |
14969 | return IWMMXT_REGS; | |
14970 | ||
e99faaaa ILT |
14971 | if (IS_IWMMXT_GR_REGNUM (regno)) |
14972 | return IWMMXT_GR_REGS; | |
14973 | ||
3b684012 | 14974 | return FPA_REGS; |
d5b7b3ae RE |
14975 | } |
14976 | ||
14977 | /* Handle a special case when computing the offset | |
14978 | of an argument from the frame pointer. */ | |
14979 | int | |
e32bac5b | 14980 | arm_debugger_arg_offset (int value, rtx addr) |
d5b7b3ae RE |
14981 | { |
14982 | rtx insn; | |
14983 | ||
14984 | /* We are only interested if dbxout_parms() failed to compute the offset. */ | |
14985 | if (value != 0) | |
14986 | return 0; | |
14987 | ||
14988 | /* We can only cope with the case where the address is held in a register. */ | |
14989 | if (GET_CODE (addr) != REG) | |
14990 | return 0; | |
14991 | ||
14992 | /* If we are using the frame pointer to point at the argument, then | |
14993 | an offset of 0 is correct. */ | |
cd2b33d0 | 14994 | if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) |
d5b7b3ae | 14995 | return 0; |
f676971a | 14996 | |
d5b7b3ae RE |
14997 | /* If we are using the stack pointer to point at the |
14998 | argument, then an offset of 0 is correct. */ | |
5b3e6663 | 14999 | /* ??? Check this is consistent with thumb2 frame layout. */ |
5895f793 | 15000 | if ((TARGET_THUMB || !frame_pointer_needed) |
d5b7b3ae RE |
15001 | && REGNO (addr) == SP_REGNUM) |
15002 | return 0; | |
f676971a | 15003 | |
d5b7b3ae RE |
15004 | /* Oh dear. The argument is pointed to by a register rather |
15005 | than being held in a register, or being stored at a known | |
15006 | offset from the frame pointer. Since GDB only understands | |
15007 | those two kinds of argument we must translate the address | |
15008 | held in the register into an offset from the frame pointer. | |
15009 | We do this by searching through the insns for the function | |
15010 | looking to see where this register gets its value. If the | |
4912a07c | 15011 | register is initialized from the frame pointer plus an offset |
d5b7b3ae | 15012 | then we are in luck and we can continue, otherwise we give up. |
f676971a | 15013 | |
d5b7b3ae RE |
15014 | This code is exercised by producing debugging information |
15015 | for a function with arguments like this: | |
f676971a | 15016 | |
d5b7b3ae | 15017 | double func (double a, double b, int c, double d) {return d;} |
f676971a | 15018 | |
d5b7b3ae RE |
15019 | Without this code the stab for parameter 'd' will be set to |
15020 | an offset of 0 from the frame pointer, rather than 8. */ | |
15021 | ||
15022 | /* The if() statement says: | |
15023 | ||
15024 | If the insn is a normal instruction | |
15025 | and if the insn is setting the value in a register | |
15026 | and if the register being set is the register holding the address of the argument | |
15027 | and if the address is computing by an addition | |
15028 | that involves adding to a register | |
15029 | which is the frame pointer | |
15030 | a constant integer | |
15031 | ||
d6b4baa4 | 15032 | then... */ |
f676971a | 15033 | |
d5b7b3ae RE |
15034 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
15035 | { | |
f676971a | 15036 | if ( GET_CODE (insn) == INSN |
d5b7b3ae RE |
15037 | && GET_CODE (PATTERN (insn)) == SET |
15038 | && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) | |
15039 | && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS | |
15040 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG | |
cd2b33d0 | 15041 | && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM |
d5b7b3ae RE |
15042 | && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT |
15043 | ) | |
15044 | { | |
15045 | value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); | |
f676971a | 15046 | |
d5b7b3ae RE |
15047 | break; |
15048 | } | |
15049 | } | |
f676971a | 15050 | |
d5b7b3ae RE |
15051 | if (value == 0) |
15052 | { | |
15053 | debug_rtx (addr); | |
d4ee4d25 | 15054 | warning (0, "unable to compute real location of stacked parameter"); |
d5b7b3ae RE |
15055 | value = 8; /* XXX magic hack */ |
15056 | } | |
15057 | ||
15058 | return value; | |
15059 | } | |
d5b7b3ae | 15060 | \f |
5a9335ef NC |
15061 | #define def_mbuiltin(MASK, NAME, TYPE, CODE) \ |
15062 | do \ | |
15063 | { \ | |
15064 | if ((MASK) & insn_flags) \ | |
c79efc4d RÁE |
15065 | add_builtin_function ((NAME), (TYPE), (CODE), \ |
15066 | BUILT_IN_MD, NULL, NULL_TREE); \ | |
5a9335ef NC |
15067 | } \ |
15068 | while (0) | |
15069 | ||
15070 | struct builtin_description | |
15071 | { | |
15072 | const unsigned int mask; | |
15073 | const enum insn_code icode; | |
15074 | const char * const name; | |
15075 | const enum arm_builtins code; | |
15076 | const enum rtx_code comparison; | |
15077 | const unsigned int flag; | |
15078 | }; | |
15079 | ||
15080 | static const struct builtin_description bdesc_2arg[] = | |
15081 | { | |
15082 | #define IWMMXT_BUILTIN(code, string, builtin) \ | |
15083 | { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ | |
81f40b79 | 15084 | ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
5a9335ef NC |
15085 | |
15086 | IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) | |
15087 | IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) | |
15088 | IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) | |
15089 | IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) | |
15090 | IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) | |
15091 | IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) | |
15092 | IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) | |
15093 | IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) | |
15094 | IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) | |
15095 | IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) | |
15096 | IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) | |
15097 | IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) | |
15098 | IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) | |
15099 | IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) | |
15100 | IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) | |
15101 | IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) | |
15102 | IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) | |
15103 | IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) | |
15104 | IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) | |
f07a6b21 BE |
15105 | IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) |
15106 | IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) | |
5a9335ef NC |
15107 | IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) |
15108 | IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) | |
15109 | IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) | |
15110 | IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) | |
15111 | IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) | |
15112 | IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) | |
15113 | IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) | |
15114 | IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) | |
15115 | IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) | |
15116 | IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) | |
15117 | IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) | |
15118 | IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) | |
15119 | IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) | |
15120 | IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) | |
15121 | IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) | |
15122 | IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) | |
15123 | IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) | |
15124 | IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) | |
15125 | IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) | |
15126 | IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) | |
15127 | IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) | |
15128 | IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) | |
15129 | IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) | |
15130 | IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) | |
15131 | IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) | |
15132 | IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) | |
15133 | IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) | |
15134 | IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) | |
15135 | IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) | |
15136 | IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) | |
15137 | IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) | |
15138 | IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) | |
15139 | IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) | |
15140 | IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) | |
15141 | IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) | |
15142 | IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) | |
15143 | IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) | |
15144 | ||
15145 | #define IWMMXT_BUILTIN2(code, builtin) \ | |
81f40b79 | 15146 | { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, UNKNOWN, 0 }, |
f676971a | 15147 | |
5a9335ef NC |
15148 | IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) |
15149 | IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) | |
15150 | IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) | |
15151 | IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) | |
15152 | IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) | |
15153 | IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) | |
15154 | IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) | |
88f77cba | 15155 | IWMMXT_BUILTIN2 (ashlv4hi3_iwmmxt, WSLLHI) |
5a9335ef | 15156 | IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) |
88f77cba | 15157 | IWMMXT_BUILTIN2 (ashlv2si3_iwmmxt, WSLLWI) |
5a9335ef NC |
15158 | IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) |
15159 | IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) | |
15160 | IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) | |
88f77cba | 15161 | IWMMXT_BUILTIN2 (lshrv4hi3_iwmmxt, WSRLHI) |
5a9335ef | 15162 | IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) |
88f77cba | 15163 | IWMMXT_BUILTIN2 (lshrv2si3_iwmmxt, WSRLWI) |
5a9335ef | 15164 | IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) |
9b66ebb1 | 15165 | IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) |
5a9335ef | 15166 | IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) |
88f77cba | 15167 | IWMMXT_BUILTIN2 (ashrv4hi3_iwmmxt, WSRAHI) |
5a9335ef | 15168 | IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) |
88f77cba | 15169 | IWMMXT_BUILTIN2 (ashrv2si3_iwmmxt, WSRAWI) |
5a9335ef | 15170 | IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) |
9b66ebb1 | 15171 | IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) |
5a9335ef NC |
15172 | IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) |
15173 | IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) | |
15174 | IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) | |
15175 | IWMMXT_BUILTIN2 (rorv2si3, WRORWI) | |
15176 | IWMMXT_BUILTIN2 (rordi3_di, WRORD) | |
15177 | IWMMXT_BUILTIN2 (rordi3, WRORDI) | |
15178 | IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) | |
15179 | IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) | |
15180 | }; | |
15181 | ||
15182 | static const struct builtin_description bdesc_1arg[] = | |
15183 | { | |
15184 | IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) | |
15185 | IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) | |
15186 | IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) | |
15187 | IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) | |
15188 | IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) | |
15189 | IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) | |
15190 | IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) | |
15191 | IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) | |
15192 | IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) | |
15193 | IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) | |
15194 | IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) | |
15195 | IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) | |
15196 | IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) | |
15197 | IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) | |
15198 | IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) | |
15199 | IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) | |
15200 | IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) | |
15201 | IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) | |
15202 | }; | |
15203 | ||
15204 | /* Set up all the iWMMXt builtins. This is | |
15205 | not called if TARGET_IWMMXT is zero. */ | |
15206 | ||
15207 | static void | |
15208 | arm_init_iwmmxt_builtins (void) | |
15209 | { | |
15210 | const struct builtin_description * d; | |
15211 | size_t i; | |
15212 | tree endlink = void_list_node; | |
15213 | ||
4a5eab38 PB |
15214 | tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); |
15215 | tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); | |
15216 | tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); | |
15217 | ||
5a9335ef NC |
15218 | tree int_ftype_int |
15219 | = build_function_type (integer_type_node, | |
15220 | tree_cons (NULL_TREE, integer_type_node, endlink)); | |
15221 | tree v8qi_ftype_v8qi_v8qi_int | |
15222 | = build_function_type (V8QI_type_node, | |
15223 | tree_cons (NULL_TREE, V8QI_type_node, | |
15224 | tree_cons (NULL_TREE, V8QI_type_node, | |
15225 | tree_cons (NULL_TREE, | |
15226 | integer_type_node, | |
15227 | endlink)))); | |
15228 | tree v4hi_ftype_v4hi_int | |
15229 | = build_function_type (V4HI_type_node, | |
15230 | tree_cons (NULL_TREE, V4HI_type_node, | |
15231 | tree_cons (NULL_TREE, integer_type_node, | |
15232 | endlink))); | |
15233 | tree v2si_ftype_v2si_int | |
15234 | = build_function_type (V2SI_type_node, | |
15235 | tree_cons (NULL_TREE, V2SI_type_node, | |
15236 | tree_cons (NULL_TREE, integer_type_node, | |
15237 | endlink))); | |
15238 | tree v2si_ftype_di_di | |
15239 | = build_function_type (V2SI_type_node, | |
15240 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
15241 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
15242 | endlink))); | |
15243 | tree di_ftype_di_int | |
15244 | = build_function_type (long_long_integer_type_node, | |
15245 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
15246 | tree_cons (NULL_TREE, integer_type_node, | |
15247 | endlink))); | |
15248 | tree di_ftype_di_int_int | |
15249 | = build_function_type (long_long_integer_type_node, | |
15250 | tree_cons (NULL_TREE, long_long_integer_type_node, | |
15251 | tree_cons (NULL_TREE, integer_type_node, | |
15252 | tree_cons (NULL_TREE, | |
15253 | integer_type_node, | |
15254 | endlink)))); | |
15255 | tree int_ftype_v8qi | |
15256 | = build_function_type (integer_type_node, | |
15257 | tree_cons (NULL_TREE, V8QI_type_node, | |
15258 | endlink)); | |
15259 | tree int_ftype_v4hi | |
15260 | = build_function_type (integer_type_node, | |
15261 | tree_cons (NULL_TREE, V4HI_type_node, | |
15262 | endlink)); | |
15263 | tree int_ftype_v2si | |
15264 | = build_function_type (integer_type_node, | |
15265 | tree_cons (NULL_TREE, V2SI_type_node, | |
15266 | endlink)); | |
15267 | tree int_ftype_v8qi_int | |
15268 | = build_function_type (integer_type_node, | |
15269 | tree_cons (NULL_TREE, V8QI_type_node, | |
15270 | tree_cons (NULL_TREE, integer_type_node, | |
15271 | endlink))); | |
15272 | tree int_ftype_v4hi_int | |
15273 | = build_function_type (integer_type_node, | |
15274 | tree_cons (NULL_TREE, V4HI_type_node, | |
15275 | tree_cons (NULL_TREE, integer_type_node, | |
15276 | endlink))); | |
15277 | tree int_ftype_v2si_int | |
15278 | = build_function_type (integer_type_node, | |
15279 | tree_cons (NULL_TREE, V2SI_type_node, | |
15280 | tree_cons (NULL_TREE, integer_type_node, | |
15281 | endlink))); | |
15282 | tree v8qi_ftype_v8qi_int_int | |
15283 | = build_function_type (V8QI_type_node, | |
15284 | tree_cons (NULL_TREE, V8QI_type_node, | |
15285 | tree_cons (NULL_TREE, integer_type_node, | |
15286 | tree_cons (NULL_TREE, | |
15287 | integer_type_node, | |
15288 | endlink)))); | |
15289 | tree v4hi_ftype_v4hi_int_int | |
15290 | = build_function_type (V4HI_type_node, | |
15291 | tree_cons (NULL_TREE, V4HI_type_node, | |
15292 | tree_cons (NULL_TREE, integer_type_node, | |
15293 | tree_cons (NULL_TREE, | |
15294 | integer_type_node, | |
15295 | endlink)))); | |
15296 | tree v2si_ftype_v2si_int_int | |
15297 | = build_function_type (V2SI_type_node, | |
15298 | tree_cons (NULL_TREE, V2SI_type_node, | |
15299 | tree_cons (NULL_TREE, integer_type_node, | |
15300 | tree_cons (NULL_TREE, | |
15301 | integer_type_node, | |
15302 | endlink)))); | |
15303 | /* Miscellaneous. */ | |
15304 | tree v8qi_ftype_v4hi_v4hi | |
15305 | = build_function_type (V8QI_type_node, | |
15306 | tree_cons (NULL_TREE, V4HI_type_node, | |
15307 | tree_cons (NULL_TREE, V4HI_type_node, | |
15308 | endlink))); | |
15309 | tree v4hi_ftype_v2si_v2si | |
15310 | = build_function_type (V4HI_type_node, | |
15311 | tree_cons (NULL_TREE, V2SI_type_node, | |
15312 | tree_cons (NULL_TREE, V2SI_type_node, | |
15313 | endlink))); | |
15314 | tree v2si_ftype_v4hi_v4hi | |
15315 | = build_function_type (V2SI_type_node, | |
15316 | tree_cons (NULL_TREE, V4HI_type_node, | |
15317 | tree_cons (NULL_TREE, V4HI_type_node, | |
15318 | endlink))); | |
15319 | tree v2si_ftype_v8qi_v8qi | |
15320 | = build_function_type (V2SI_type_node, | |
15321 | tree_cons (NULL_TREE, V8QI_type_node, | |
15322 | tree_cons (NULL_TREE, V8QI_type_node, | |
15323 | endlink))); | |
15324 | tree v4hi_ftype_v4hi_di | |
15325 | = build_function_type (V4HI_type_node, | |
15326 | tree_cons (NULL_TREE, V4HI_type_node, | |
15327 | tree_cons (NULL_TREE, | |
15328 | long_long_integer_type_node, | |
15329 | endlink))); | |
15330 | tree v2si_ftype_v2si_di | |
15331 | = build_function_type (V2SI_type_node, | |
15332 | tree_cons (NULL_TREE, V2SI_type_node, | |
15333 | tree_cons (NULL_TREE, | |
15334 | long_long_integer_type_node, | |
15335 | endlink))); | |
15336 | tree void_ftype_int_int | |
15337 | = build_function_type (void_type_node, | |
15338 | tree_cons (NULL_TREE, integer_type_node, | |
15339 | tree_cons (NULL_TREE, integer_type_node, | |
15340 | endlink))); | |
15341 | tree di_ftype_void | |
15342 | = build_function_type (long_long_unsigned_type_node, endlink); | |
15343 | tree di_ftype_v8qi | |
15344 | = build_function_type (long_long_integer_type_node, | |
15345 | tree_cons (NULL_TREE, V8QI_type_node, | |
15346 | endlink)); | |
15347 | tree di_ftype_v4hi | |
15348 | = build_function_type (long_long_integer_type_node, | |
15349 | tree_cons (NULL_TREE, V4HI_type_node, | |
15350 | endlink)); | |
15351 | tree di_ftype_v2si | |
15352 | = build_function_type (long_long_integer_type_node, | |
15353 | tree_cons (NULL_TREE, V2SI_type_node, | |
15354 | endlink)); | |
15355 | tree v2si_ftype_v4hi | |
15356 | = build_function_type (V2SI_type_node, | |
15357 | tree_cons (NULL_TREE, V4HI_type_node, | |
15358 | endlink)); | |
15359 | tree v4hi_ftype_v8qi | |
15360 | = build_function_type (V4HI_type_node, | |
15361 | tree_cons (NULL_TREE, V8QI_type_node, | |
15362 | endlink)); | |
15363 | ||
15364 | tree di_ftype_di_v4hi_v4hi | |
15365 | = build_function_type (long_long_unsigned_type_node, | |
15366 | tree_cons (NULL_TREE, | |
15367 | long_long_unsigned_type_node, | |
15368 | tree_cons (NULL_TREE, V4HI_type_node, | |
15369 | tree_cons (NULL_TREE, | |
15370 | V4HI_type_node, | |
15371 | endlink)))); | |
15372 | ||
15373 | tree di_ftype_v4hi_v4hi | |
15374 | = build_function_type (long_long_unsigned_type_node, | |
15375 | tree_cons (NULL_TREE, V4HI_type_node, | |
15376 | tree_cons (NULL_TREE, V4HI_type_node, | |
15377 | endlink))); | |
15378 | ||
15379 | /* Normal vector binops. */ | |
15380 | tree v8qi_ftype_v8qi_v8qi | |
15381 | = build_function_type (V8QI_type_node, | |
15382 | tree_cons (NULL_TREE, V8QI_type_node, | |
15383 | tree_cons (NULL_TREE, V8QI_type_node, | |
15384 | endlink))); | |
15385 | tree v4hi_ftype_v4hi_v4hi | |
15386 | = build_function_type (V4HI_type_node, | |
15387 | tree_cons (NULL_TREE, V4HI_type_node, | |
15388 | tree_cons (NULL_TREE, V4HI_type_node, | |
15389 | endlink))); | |
15390 | tree v2si_ftype_v2si_v2si | |
15391 | = build_function_type (V2SI_type_node, | |
15392 | tree_cons (NULL_TREE, V2SI_type_node, | |
15393 | tree_cons (NULL_TREE, V2SI_type_node, | |
15394 | endlink))); | |
15395 | tree di_ftype_di_di | |
15396 | = build_function_type (long_long_unsigned_type_node, | |
15397 | tree_cons (NULL_TREE, long_long_unsigned_type_node, | |
15398 | tree_cons (NULL_TREE, | |
15399 | long_long_unsigned_type_node, | |
15400 | endlink))); | |
15401 | ||
15402 | /* Add all builtins that are more or less simple operations on two | |
15403 | operands. */ | |
e97a46ce | 15404 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef NC |
15405 | { |
15406 | /* Use one of the operands; the target can have a different mode for | |
15407 | mask-generating compares. */ | |
15408 | enum machine_mode mode; | |
15409 | tree type; | |
15410 | ||
15411 | if (d->name == 0) | |
15412 | continue; | |
15413 | ||
15414 | mode = insn_data[d->icode].operand[1].mode; | |
15415 | ||
15416 | switch (mode) | |
15417 | { | |
15418 | case V8QImode: | |
15419 | type = v8qi_ftype_v8qi_v8qi; | |
15420 | break; | |
15421 | case V4HImode: | |
15422 | type = v4hi_ftype_v4hi_v4hi; | |
15423 | break; | |
15424 | case V2SImode: | |
15425 | type = v2si_ftype_v2si_v2si; | |
15426 | break; | |
15427 | case DImode: | |
15428 | type = di_ftype_di_di; | |
15429 | break; | |
15430 | ||
15431 | default: | |
e6d29d15 | 15432 | gcc_unreachable (); |
5a9335ef NC |
15433 | } |
15434 | ||
15435 | def_mbuiltin (d->mask, d->name, type, d->code); | |
15436 | } | |
15437 | ||
15438 | /* Add the remaining MMX insns with somewhat more complicated types. */ | |
15439 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); | |
15440 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); | |
15441 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); | |
15442 | ||
15443 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); | |
15444 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); | |
15445 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); | |
15446 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); | |
15447 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); | |
15448 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); | |
15449 | ||
15450 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); | |
15451 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); | |
15452 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); | |
15453 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); | |
15454 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); | |
15455 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); | |
15456 | ||
15457 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); | |
15458 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); | |
15459 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); | |
15460 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); | |
15461 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); | |
15462 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); | |
15463 | ||
15464 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); | |
15465 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); | |
15466 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); | |
15467 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); | |
15468 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); | |
15469 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); | |
15470 | ||
15471 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); | |
15472 | ||
15473 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); | |
15474 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); | |
15475 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); | |
15476 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); | |
15477 | ||
15478 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); | |
15479 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); | |
15480 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); | |
15481 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); | |
15482 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); | |
15483 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); | |
15484 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); | |
15485 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); | |
15486 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); | |
15487 | ||
15488 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); | |
15489 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); | |
15490 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); | |
15491 | ||
15492 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); | |
15493 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); | |
15494 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); | |
15495 | ||
15496 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); | |
15497 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); | |
15498 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); | |
15499 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); | |
15500 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); | |
15501 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); | |
15502 | ||
15503 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); | |
15504 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); | |
15505 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); | |
15506 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); | |
15507 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); | |
15508 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); | |
15509 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); | |
15510 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); | |
15511 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); | |
15512 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); | |
15513 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); | |
15514 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); | |
15515 | ||
15516 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); | |
15517 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); | |
15518 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); | |
15519 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); | |
15520 | ||
15521 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); | |
15522 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); | |
15523 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); | |
15524 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); | |
15525 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); | |
15526 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); | |
15527 | def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); | |
15528 | } | |
15529 | ||
d3585b76 DJ |
15530 | static void |
15531 | arm_init_tls_builtins (void) | |
15532 | { | |
ebfe65a3 | 15533 | tree ftype, decl; |
d3585b76 DJ |
15534 | |
15535 | ftype = build_function_type (ptr_type_node, void_list_node); | |
ebfe65a3 JJ |
15536 | decl = add_builtin_function ("__builtin_thread_pointer", ftype, |
15537 | ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
15538 | NULL, NULL_TREE); | |
15539 | TREE_NOTHROW (decl) = 1; | |
15540 | TREE_READONLY (decl) = 1; | |
d3585b76 DJ |
15541 | } |
15542 | ||
81f40b79 | 15543 | enum neon_builtin_type_bits { |
88f77cba JB |
15544 | T_V8QI = 0x0001, |
15545 | T_V4HI = 0x0002, | |
15546 | T_V2SI = 0x0004, | |
15547 | T_V2SF = 0x0008, | |
15548 | T_DI = 0x0010, | |
15549 | T_V16QI = 0x0020, | |
15550 | T_V8HI = 0x0040, | |
15551 | T_V4SI = 0x0080, | |
15552 | T_V4SF = 0x0100, | |
15553 | T_V2DI = 0x0200, | |
15554 | T_TI = 0x0400, | |
15555 | T_EI = 0x0800, | |
15556 | T_OI = 0x1000 | |
81f40b79 | 15557 | }; |
88f77cba JB |
15558 | |
15559 | #define v8qi_UP T_V8QI | |
15560 | #define v4hi_UP T_V4HI | |
15561 | #define v2si_UP T_V2SI | |
15562 | #define v2sf_UP T_V2SF | |
15563 | #define di_UP T_DI | |
15564 | #define v16qi_UP T_V16QI | |
15565 | #define v8hi_UP T_V8HI | |
15566 | #define v4si_UP T_V4SI | |
15567 | #define v4sf_UP T_V4SF | |
15568 | #define v2di_UP T_V2DI | |
15569 | #define ti_UP T_TI | |
15570 | #define ei_UP T_EI | |
15571 | #define oi_UP T_OI | |
15572 | ||
15573 | #define UP(X) X##_UP | |
15574 | ||
15575 | #define T_MAX 13 | |
15576 | ||
15577 | typedef enum { | |
15578 | NEON_BINOP, | |
15579 | NEON_TERNOP, | |
15580 | NEON_UNOP, | |
15581 | NEON_GETLANE, | |
15582 | NEON_SETLANE, | |
15583 | NEON_CREATE, | |
15584 | NEON_DUP, | |
15585 | NEON_DUPLANE, | |
15586 | NEON_COMBINE, | |
15587 | NEON_SPLIT, | |
15588 | NEON_LANEMUL, | |
15589 | NEON_LANEMULL, | |
15590 | NEON_LANEMULH, | |
15591 | NEON_LANEMAC, | |
15592 | NEON_SCALARMUL, | |
15593 | NEON_SCALARMULL, | |
15594 | NEON_SCALARMULH, | |
15595 | NEON_SCALARMAC, | |
15596 | NEON_CONVERT, | |
15597 | NEON_FIXCONV, | |
15598 | NEON_SELECT, | |
15599 | NEON_RESULTPAIR, | |
15600 | NEON_REINTERP, | |
15601 | NEON_VTBL, | |
15602 | NEON_VTBX, | |
15603 | NEON_LOAD1, | |
15604 | NEON_LOAD1LANE, | |
15605 | NEON_STORE1, | |
15606 | NEON_STORE1LANE, | |
15607 | NEON_LOADSTRUCT, | |
15608 | NEON_LOADSTRUCTLANE, | |
15609 | NEON_STORESTRUCT, | |
15610 | NEON_STORESTRUCTLANE, | |
15611 | NEON_LOGICBINOP, | |
15612 | NEON_SHIFTINSERT, | |
15613 | NEON_SHIFTIMM, | |
15614 | NEON_SHIFTACC | |
15615 | } neon_itype; | |
15616 | ||
15617 | typedef struct { | |
15618 | const char *name; | |
15619 | const neon_itype itype; | |
81f40b79 | 15620 | const int bits; |
88f77cba JB |
15621 | const enum insn_code codes[T_MAX]; |
15622 | const unsigned int num_vars; | |
15623 | unsigned int base_fcode; | |
15624 | } neon_builtin_datum; | |
15625 | ||
15626 | #define CF(N,X) CODE_FOR_neon_##N##X | |
15627 | ||
15628 | #define VAR1(T, N, A) \ | |
15629 | #N, NEON_##T, UP (A), { CF (N, A) }, 1, 0 | |
15630 | #define VAR2(T, N, A, B) \ | |
15631 | #N, NEON_##T, UP (A) | UP (B), { CF (N, A), CF (N, B) }, 2, 0 | |
15632 | #define VAR3(T, N, A, B, C) \ | |
15633 | #N, NEON_##T, UP (A) | UP (B) | UP (C), \ | |
15634 | { CF (N, A), CF (N, B), CF (N, C) }, 3, 0 | |
15635 | #define VAR4(T, N, A, B, C, D) \ | |
15636 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D), \ | |
15637 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D) }, 4, 0 | |
15638 | #define VAR5(T, N, A, B, C, D, E) \ | |
15639 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E), \ | |
15640 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E) }, 5, 0 | |
15641 | #define VAR6(T, N, A, B, C, D, E, F) \ | |
15642 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F), \ | |
15643 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F) }, 6, 0 | |
15644 | #define VAR7(T, N, A, B, C, D, E, F, G) \ | |
15645 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G), \ | |
15646 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15647 | CF (N, G) }, 7, 0 | |
15648 | #define VAR8(T, N, A, B, C, D, E, F, G, H) \ | |
15649 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15650 | | UP (H), \ | |
15651 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15652 | CF (N, G), CF (N, H) }, 8, 0 | |
15653 | #define VAR9(T, N, A, B, C, D, E, F, G, H, I) \ | |
15654 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15655 | | UP (H) | UP (I), \ | |
15656 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15657 | CF (N, G), CF (N, H), CF (N, I) }, 9, 0 | |
15658 | #define VAR10(T, N, A, B, C, D, E, F, G, H, I, J) \ | |
15659 | #N, NEON_##T, UP (A) | UP (B) | UP (C) | UP (D) | UP (E) | UP (F) | UP (G) \ | |
15660 | | UP (H) | UP (I) | UP (J), \ | |
15661 | { CF (N, A), CF (N, B), CF (N, C), CF (N, D), CF (N, E), CF (N, F), \ | |
15662 | CF (N, G), CF (N, H), CF (N, I), CF (N, J) }, 10, 0 | |
15663 | ||
15664 | /* The mode entries in the following table correspond to the "key" type of the | |
15665 | instruction variant, i.e. equivalent to that which would be specified after | |
15666 | the assembler mnemonic, which usually refers to the last vector operand. | |
15667 | (Signed/unsigned/polynomial types are not differentiated between though, and | |
15668 | are all mapped onto the same mode for a given element size.) The modes | |
15669 | listed per instruction should be the same as those defined for that | |
15670 | instruction's pattern in neon.md. | |
15671 | WARNING: Variants should be listed in the same increasing order as | |
15672 | neon_builtin_type_bits. */ | |
15673 | ||
15674 | static neon_builtin_datum neon_builtin_data[] = | |
15675 | { | |
15676 | { VAR10 (BINOP, vadd, | |
15677 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15678 | { VAR3 (BINOP, vaddl, v8qi, v4hi, v2si) }, | |
15679 | { VAR3 (BINOP, vaddw, v8qi, v4hi, v2si) }, | |
15680 | { VAR6 (BINOP, vhadd, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15681 | { VAR8 (BINOP, vqadd, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15682 | { VAR3 (BINOP, vaddhn, v8hi, v4si, v2di) }, | |
15683 | { VAR8 (BINOP, vmul, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15684 | { VAR8 (TERNOP, vmla, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15685 | { VAR3 (TERNOP, vmlal, v8qi, v4hi, v2si) }, | |
15686 | { VAR8 (TERNOP, vmls, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15687 | { VAR3 (TERNOP, vmlsl, v8qi, v4hi, v2si) }, | |
15688 | { VAR4 (BINOP, vqdmulh, v4hi, v2si, v8hi, v4si) }, | |
15689 | { VAR2 (TERNOP, vqdmlal, v4hi, v2si) }, | |
15690 | { VAR2 (TERNOP, vqdmlsl, v4hi, v2si) }, | |
15691 | { VAR3 (BINOP, vmull, v8qi, v4hi, v2si) }, | |
15692 | { VAR2 (SCALARMULL, vmull_n, v4hi, v2si) }, | |
15693 | { VAR2 (LANEMULL, vmull_lane, v4hi, v2si) }, | |
15694 | { VAR2 (SCALARMULL, vqdmull_n, v4hi, v2si) }, | |
15695 | { VAR2 (LANEMULL, vqdmull_lane, v4hi, v2si) }, | |
15696 | { VAR4 (SCALARMULH, vqdmulh_n, v4hi, v2si, v8hi, v4si) }, | |
15697 | { VAR4 (LANEMULH, vqdmulh_lane, v4hi, v2si, v8hi, v4si) }, | |
15698 | { VAR2 (BINOP, vqdmull, v4hi, v2si) }, | |
15699 | { VAR8 (BINOP, vshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15700 | { VAR8 (BINOP, vqshl, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15701 | { VAR8 (SHIFTIMM, vshr_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15702 | { VAR3 (SHIFTIMM, vshrn_n, v8hi, v4si, v2di) }, | |
15703 | { VAR3 (SHIFTIMM, vqshrn_n, v8hi, v4si, v2di) }, | |
15704 | { VAR3 (SHIFTIMM, vqshrun_n, v8hi, v4si, v2di) }, | |
15705 | { VAR8 (SHIFTIMM, vshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15706 | { VAR8 (SHIFTIMM, vqshl_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15707 | { VAR8 (SHIFTIMM, vqshlu_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15708 | { VAR3 (SHIFTIMM, vshll_n, v8qi, v4hi, v2si) }, | |
15709 | { VAR8 (SHIFTACC, vsra_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15710 | { VAR10 (BINOP, vsub, | |
15711 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15712 | { VAR3 (BINOP, vsubl, v8qi, v4hi, v2si) }, | |
15713 | { VAR3 (BINOP, vsubw, v8qi, v4hi, v2si) }, | |
15714 | { VAR8 (BINOP, vqsub, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15715 | { VAR6 (BINOP, vhsub, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15716 | { VAR3 (BINOP, vsubhn, v8hi, v4si, v2di) }, | |
15717 | { VAR8 (BINOP, vceq, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15718 | { VAR8 (BINOP, vcge, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15719 | { VAR8 (BINOP, vcgt, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15720 | { VAR2 (BINOP, vcage, v2sf, v4sf) }, | |
15721 | { VAR2 (BINOP, vcagt, v2sf, v4sf) }, | |
15722 | { VAR6 (BINOP, vtst, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15723 | { VAR8 (BINOP, vabd, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15724 | { VAR3 (BINOP, vabdl, v8qi, v4hi, v2si) }, | |
15725 | { VAR6 (TERNOP, vaba, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15726 | { VAR3 (TERNOP, vabal, v8qi, v4hi, v2si) }, | |
15727 | { VAR8 (BINOP, vmax, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15728 | { VAR8 (BINOP, vmin, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15729 | { VAR4 (BINOP, vpadd, v8qi, v4hi, v2si, v2sf) }, | |
15730 | { VAR6 (UNOP, vpaddl, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15731 | { VAR6 (BINOP, vpadal, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15732 | { VAR4 (BINOP, vpmax, v8qi, v4hi, v2si, v2sf) }, | |
15733 | { VAR4 (BINOP, vpmin, v8qi, v4hi, v2si, v2sf) }, | |
15734 | { VAR2 (BINOP, vrecps, v2sf, v4sf) }, | |
15735 | { VAR2 (BINOP, vrsqrts, v2sf, v4sf) }, | |
15736 | { VAR8 (SHIFTINSERT, vsri_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15737 | { VAR8 (SHIFTINSERT, vsli_n, v8qi, v4hi, v2si, di, v16qi, v8hi, v4si, v2di) }, | |
15738 | { VAR8 (UNOP, vabs, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15739 | { VAR6 (UNOP, vqabs, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15740 | { VAR8 (UNOP, vneg, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15741 | { VAR6 (UNOP, vqneg, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15742 | { VAR6 (UNOP, vcls, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15743 | { VAR6 (UNOP, vclz, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15744 | { VAR2 (UNOP, vcnt, v8qi, v16qi) }, | |
15745 | { VAR4 (UNOP, vrecpe, v2si, v2sf, v4si, v4sf) }, | |
15746 | { VAR4 (UNOP, vrsqrte, v2si, v2sf, v4si, v4sf) }, | |
15747 | { VAR6 (UNOP, vmvn, v8qi, v4hi, v2si, v16qi, v8hi, v4si) }, | |
15748 | /* FIXME: vget_lane supports more variants than this! */ | |
15749 | { VAR10 (GETLANE, vget_lane, | |
15750 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15751 | { VAR10 (SETLANE, vset_lane, | |
15752 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15753 | { VAR5 (CREATE, vcreate, v8qi, v4hi, v2si, v2sf, di) }, | |
15754 | { VAR10 (DUP, vdup_n, | |
15755 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15756 | { VAR10 (DUPLANE, vdup_lane, | |
15757 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15758 | { VAR5 (COMBINE, vcombine, v8qi, v4hi, v2si, v2sf, di) }, | |
15759 | { VAR5 (SPLIT, vget_high, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15760 | { VAR5 (SPLIT, vget_low, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15761 | { VAR3 (UNOP, vmovn, v8hi, v4si, v2di) }, | |
15762 | { VAR3 (UNOP, vqmovn, v8hi, v4si, v2di) }, | |
15763 | { VAR3 (UNOP, vqmovun, v8hi, v4si, v2di) }, | |
15764 | { VAR3 (UNOP, vmovl, v8qi, v4hi, v2si) }, | |
15765 | { VAR6 (LANEMUL, vmul_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15766 | { VAR6 (LANEMAC, vmla_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15767 | { VAR2 (LANEMAC, vmlal_lane, v4hi, v2si) }, | |
15768 | { VAR2 (LANEMAC, vqdmlal_lane, v4hi, v2si) }, | |
15769 | { VAR6 (LANEMAC, vmls_lane, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15770 | { VAR2 (LANEMAC, vmlsl_lane, v4hi, v2si) }, | |
15771 | { VAR2 (LANEMAC, vqdmlsl_lane, v4hi, v2si) }, | |
15772 | { VAR6 (SCALARMUL, vmul_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15773 | { VAR6 (SCALARMAC, vmla_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15774 | { VAR2 (SCALARMAC, vmlal_n, v4hi, v2si) }, | |
15775 | { VAR2 (SCALARMAC, vqdmlal_n, v4hi, v2si) }, | |
15776 | { VAR6 (SCALARMAC, vmls_n, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15777 | { VAR2 (SCALARMAC, vmlsl_n, v4hi, v2si) }, | |
15778 | { VAR2 (SCALARMAC, vqdmlsl_n, v4hi, v2si) }, | |
15779 | { VAR10 (BINOP, vext, | |
15780 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15781 | { VAR8 (UNOP, vrev64, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15782 | { VAR4 (UNOP, vrev32, v8qi, v4hi, v16qi, v8hi) }, | |
15783 | { VAR2 (UNOP, vrev16, v8qi, v16qi) }, | |
15784 | { VAR4 (CONVERT, vcvt, v2si, v2sf, v4si, v4sf) }, | |
15785 | { VAR4 (FIXCONV, vcvt_n, v2si, v2sf, v4si, v4sf) }, | |
15786 | { VAR10 (SELECT, vbsl, | |
15787 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15788 | { VAR1 (VTBL, vtbl1, v8qi) }, | |
15789 | { VAR1 (VTBL, vtbl2, v8qi) }, | |
15790 | { VAR1 (VTBL, vtbl3, v8qi) }, | |
15791 | { VAR1 (VTBL, vtbl4, v8qi) }, | |
15792 | { VAR1 (VTBX, vtbx1, v8qi) }, | |
15793 | { VAR1 (VTBX, vtbx2, v8qi) }, | |
15794 | { VAR1 (VTBX, vtbx3, v8qi) }, | |
15795 | { VAR1 (VTBX, vtbx4, v8qi) }, | |
15796 | { VAR8 (RESULTPAIR, vtrn, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15797 | { VAR8 (RESULTPAIR, vzip, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15798 | { VAR8 (RESULTPAIR, vuzp, v8qi, v4hi, v2si, v2sf, v16qi, v8hi, v4si, v4sf) }, | |
15799 | { VAR5 (REINTERP, vreinterpretv8qi, v8qi, v4hi, v2si, v2sf, di) }, | |
15800 | { VAR5 (REINTERP, vreinterpretv4hi, v8qi, v4hi, v2si, v2sf, di) }, | |
15801 | { VAR5 (REINTERP, vreinterpretv2si, v8qi, v4hi, v2si, v2sf, di) }, | |
15802 | { VAR5 (REINTERP, vreinterpretv2sf, v8qi, v4hi, v2si, v2sf, di) }, | |
15803 | { VAR5 (REINTERP, vreinterpretdi, v8qi, v4hi, v2si, v2sf, di) }, | |
15804 | { VAR5 (REINTERP, vreinterpretv16qi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15805 | { VAR5 (REINTERP, vreinterpretv8hi, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15806 | { VAR5 (REINTERP, vreinterpretv4si, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15807 | { VAR5 (REINTERP, vreinterpretv4sf, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15808 | { VAR5 (REINTERP, vreinterpretv2di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15809 | { VAR10 (LOAD1, vld1, | |
15810 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15811 | { VAR10 (LOAD1LANE, vld1_lane, | |
15812 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15813 | { VAR10 (LOAD1, vld1_dup, | |
15814 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15815 | { VAR10 (STORE1, vst1, | |
15816 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15817 | { VAR10 (STORE1LANE, vst1_lane, | |
15818 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15819 | { VAR9 (LOADSTRUCT, | |
15820 | vld2, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15821 | { VAR7 (LOADSTRUCTLANE, vld2_lane, | |
15822 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15823 | { VAR5 (LOADSTRUCT, vld2_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15824 | { VAR9 (STORESTRUCT, vst2, | |
15825 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15826 | { VAR7 (STORESTRUCTLANE, vst2_lane, | |
15827 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15828 | { VAR9 (LOADSTRUCT, | |
15829 | vld3, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15830 | { VAR7 (LOADSTRUCTLANE, vld3_lane, | |
15831 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15832 | { VAR5 (LOADSTRUCT, vld3_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15833 | { VAR9 (STORESTRUCT, vst3, | |
15834 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15835 | { VAR7 (STORESTRUCTLANE, vst3_lane, | |
15836 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15837 | { VAR9 (LOADSTRUCT, vld4, | |
15838 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15839 | { VAR7 (LOADSTRUCTLANE, vld4_lane, | |
15840 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15841 | { VAR5 (LOADSTRUCT, vld4_dup, v8qi, v4hi, v2si, v2sf, di) }, | |
15842 | { VAR9 (STORESTRUCT, vst4, | |
15843 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf) }, | |
15844 | { VAR7 (STORESTRUCTLANE, vst4_lane, | |
15845 | v8qi, v4hi, v2si, v2sf, v8hi, v4si, v4sf) }, | |
15846 | { VAR10 (LOGICBINOP, vand, | |
15847 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15848 | { VAR10 (LOGICBINOP, vorr, | |
15849 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15850 | { VAR10 (BINOP, veor, | |
15851 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15852 | { VAR10 (LOGICBINOP, vbic, | |
15853 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) }, | |
15854 | { VAR10 (LOGICBINOP, vorn, | |
15855 | v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) } | |
15856 | }; | |
15857 | ||
15858 | #undef CF | |
15859 | #undef VAR1 | |
15860 | #undef VAR2 | |
15861 | #undef VAR3 | |
15862 | #undef VAR4 | |
15863 | #undef VAR5 | |
15864 | #undef VAR6 | |
15865 | #undef VAR7 | |
15866 | #undef VAR8 | |
15867 | #undef VAR9 | |
15868 | #undef VAR10 | |
15869 | ||
15870 | static void | |
15871 | arm_init_neon_builtins (void) | |
15872 | { | |
15873 | unsigned int i, fcode = ARM_BUILTIN_NEON_BASE; | |
15874 | ||
af06585a JM |
15875 | tree neon_intQI_type_node; |
15876 | tree neon_intHI_type_node; | |
15877 | tree neon_polyQI_type_node; | |
15878 | tree neon_polyHI_type_node; | |
15879 | tree neon_intSI_type_node; | |
15880 | tree neon_intDI_type_node; | |
15881 | tree neon_float_type_node; | |
15882 | ||
15883 | tree intQI_pointer_node; | |
15884 | tree intHI_pointer_node; | |
15885 | tree intSI_pointer_node; | |
15886 | tree intDI_pointer_node; | |
15887 | tree float_pointer_node; | |
15888 | ||
15889 | tree const_intQI_node; | |
15890 | tree const_intHI_node; | |
15891 | tree const_intSI_node; | |
15892 | tree const_intDI_node; | |
15893 | tree const_float_node; | |
15894 | ||
15895 | tree const_intQI_pointer_node; | |
15896 | tree const_intHI_pointer_node; | |
15897 | tree const_intSI_pointer_node; | |
15898 | tree const_intDI_pointer_node; | |
15899 | tree const_float_pointer_node; | |
15900 | ||
15901 | tree V8QI_type_node; | |
15902 | tree V4HI_type_node; | |
15903 | tree V2SI_type_node; | |
15904 | tree V2SF_type_node; | |
15905 | tree V16QI_type_node; | |
15906 | tree V8HI_type_node; | |
15907 | tree V4SI_type_node; | |
15908 | tree V4SF_type_node; | |
15909 | tree V2DI_type_node; | |
15910 | ||
15911 | tree intUQI_type_node; | |
15912 | tree intUHI_type_node; | |
15913 | tree intUSI_type_node; | |
15914 | tree intUDI_type_node; | |
15915 | ||
15916 | tree intEI_type_node; | |
15917 | tree intOI_type_node; | |
15918 | tree intCI_type_node; | |
15919 | tree intXI_type_node; | |
15920 | ||
15921 | tree V8QI_pointer_node; | |
15922 | tree V4HI_pointer_node; | |
15923 | tree V2SI_pointer_node; | |
15924 | tree V2SF_pointer_node; | |
15925 | tree V16QI_pointer_node; | |
15926 | tree V8HI_pointer_node; | |
15927 | tree V4SI_pointer_node; | |
15928 | tree V4SF_pointer_node; | |
15929 | tree V2DI_pointer_node; | |
15930 | ||
15931 | tree void_ftype_pv8qi_v8qi_v8qi; | |
15932 | tree void_ftype_pv4hi_v4hi_v4hi; | |
15933 | tree void_ftype_pv2si_v2si_v2si; | |
15934 | tree void_ftype_pv2sf_v2sf_v2sf; | |
15935 | tree void_ftype_pdi_di_di; | |
15936 | tree void_ftype_pv16qi_v16qi_v16qi; | |
15937 | tree void_ftype_pv8hi_v8hi_v8hi; | |
15938 | tree void_ftype_pv4si_v4si_v4si; | |
15939 | tree void_ftype_pv4sf_v4sf_v4sf; | |
15940 | tree void_ftype_pv2di_v2di_v2di; | |
15941 | ||
15942 | tree reinterp_ftype_dreg[5][5]; | |
15943 | tree reinterp_ftype_qreg[5][5]; | |
15944 | tree dreg_types[5], qreg_types[5]; | |
15945 | ||
88f77cba JB |
15946 | /* Create distinguished type nodes for NEON vector element types, |
15947 | and pointers to values of such types, so we can detect them later. */ | |
af06585a JM |
15948 | neon_intQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); |
15949 | neon_intHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15950 | neon_polyQI_type_node = make_signed_type (GET_MODE_PRECISION (QImode)); | |
15951 | neon_polyHI_type_node = make_signed_type (GET_MODE_PRECISION (HImode)); | |
15952 | neon_intSI_type_node = make_signed_type (GET_MODE_PRECISION (SImode)); | |
15953 | neon_intDI_type_node = make_signed_type (GET_MODE_PRECISION (DImode)); | |
15954 | neon_float_type_node = make_node (REAL_TYPE); | |
15955 | TYPE_PRECISION (neon_float_type_node) = FLOAT_TYPE_SIZE; | |
15956 | layout_type (neon_float_type_node); | |
15957 | ||
bcbdbbb0 JM |
15958 | /* Define typedefs which exactly correspond to the modes we are basing vector |
15959 | types on. If you change these names you'll need to change | |
15960 | the table used by arm_mangle_type too. */ | |
15961 | (*lang_hooks.types.register_builtin_type) (neon_intQI_type_node, | |
15962 | "__builtin_neon_qi"); | |
15963 | (*lang_hooks.types.register_builtin_type) (neon_intHI_type_node, | |
15964 | "__builtin_neon_hi"); | |
15965 | (*lang_hooks.types.register_builtin_type) (neon_intSI_type_node, | |
15966 | "__builtin_neon_si"); | |
15967 | (*lang_hooks.types.register_builtin_type) (neon_float_type_node, | |
15968 | "__builtin_neon_sf"); | |
15969 | (*lang_hooks.types.register_builtin_type) (neon_intDI_type_node, | |
15970 | "__builtin_neon_di"); | |
15971 | (*lang_hooks.types.register_builtin_type) (neon_polyQI_type_node, | |
15972 | "__builtin_neon_poly8"); | |
15973 | (*lang_hooks.types.register_builtin_type) (neon_polyHI_type_node, | |
15974 | "__builtin_neon_poly16"); | |
15975 | ||
af06585a JM |
15976 | intQI_pointer_node = build_pointer_type (neon_intQI_type_node); |
15977 | intHI_pointer_node = build_pointer_type (neon_intHI_type_node); | |
15978 | intSI_pointer_node = build_pointer_type (neon_intSI_type_node); | |
15979 | intDI_pointer_node = build_pointer_type (neon_intDI_type_node); | |
15980 | float_pointer_node = build_pointer_type (neon_float_type_node); | |
88f77cba JB |
15981 | |
15982 | /* Next create constant-qualified versions of the above types. */ | |
af06585a JM |
15983 | const_intQI_node = build_qualified_type (neon_intQI_type_node, |
15984 | TYPE_QUAL_CONST); | |
15985 | const_intHI_node = build_qualified_type (neon_intHI_type_node, | |
15986 | TYPE_QUAL_CONST); | |
15987 | const_intSI_node = build_qualified_type (neon_intSI_type_node, | |
15988 | TYPE_QUAL_CONST); | |
15989 | const_intDI_node = build_qualified_type (neon_intDI_type_node, | |
15990 | TYPE_QUAL_CONST); | |
15991 | const_float_node = build_qualified_type (neon_float_type_node, | |
15992 | TYPE_QUAL_CONST); | |
15993 | ||
15994 | const_intQI_pointer_node = build_pointer_type (const_intQI_node); | |
15995 | const_intHI_pointer_node = build_pointer_type (const_intHI_node); | |
15996 | const_intSI_pointer_node = build_pointer_type (const_intSI_node); | |
15997 | const_intDI_pointer_node = build_pointer_type (const_intDI_node); | |
15998 | const_float_pointer_node = build_pointer_type (const_float_node); | |
88f77cba JB |
15999 | |
16000 | /* Now create vector types based on our NEON element types. */ | |
16001 | /* 64-bit vectors. */ | |
af06585a | 16002 | V8QI_type_node = |
88f77cba | 16003 | build_vector_type_for_mode (neon_intQI_type_node, V8QImode); |
af06585a | 16004 | V4HI_type_node = |
88f77cba | 16005 | build_vector_type_for_mode (neon_intHI_type_node, V4HImode); |
af06585a | 16006 | V2SI_type_node = |
88f77cba | 16007 | build_vector_type_for_mode (neon_intSI_type_node, V2SImode); |
af06585a | 16008 | V2SF_type_node = |
88f77cba JB |
16009 | build_vector_type_for_mode (neon_float_type_node, V2SFmode); |
16010 | /* 128-bit vectors. */ | |
af06585a | 16011 | V16QI_type_node = |
88f77cba | 16012 | build_vector_type_for_mode (neon_intQI_type_node, V16QImode); |
af06585a | 16013 | V8HI_type_node = |
88f77cba | 16014 | build_vector_type_for_mode (neon_intHI_type_node, V8HImode); |
af06585a | 16015 | V4SI_type_node = |
88f77cba | 16016 | build_vector_type_for_mode (neon_intSI_type_node, V4SImode); |
af06585a | 16017 | V4SF_type_node = |
88f77cba | 16018 | build_vector_type_for_mode (neon_float_type_node, V4SFmode); |
af06585a | 16019 | V2DI_type_node = |
88f77cba JB |
16020 | build_vector_type_for_mode (neon_intDI_type_node, V2DImode); |
16021 | ||
16022 | /* Unsigned integer types for various mode sizes. */ | |
af06585a JM |
16023 | intUQI_type_node = make_unsigned_type (GET_MODE_PRECISION (QImode)); |
16024 | intUHI_type_node = make_unsigned_type (GET_MODE_PRECISION (HImode)); | |
16025 | intUSI_type_node = make_unsigned_type (GET_MODE_PRECISION (SImode)); | |
16026 | intUDI_type_node = make_unsigned_type (GET_MODE_PRECISION (DImode)); | |
88f77cba | 16027 | |
bcbdbbb0 JM |
16028 | (*lang_hooks.types.register_builtin_type) (intUQI_type_node, |
16029 | "__builtin_neon_uqi"); | |
16030 | (*lang_hooks.types.register_builtin_type) (intUHI_type_node, | |
16031 | "__builtin_neon_uhi"); | |
16032 | (*lang_hooks.types.register_builtin_type) (intUSI_type_node, | |
16033 | "__builtin_neon_usi"); | |
16034 | (*lang_hooks.types.register_builtin_type) (intUDI_type_node, | |
16035 | "__builtin_neon_udi"); | |
16036 | ||
88f77cba | 16037 | /* Opaque integer types for structures of vectors. */ |
af06585a JM |
16038 | intEI_type_node = make_signed_type (GET_MODE_PRECISION (EImode)); |
16039 | intOI_type_node = make_signed_type (GET_MODE_PRECISION (OImode)); | |
16040 | intCI_type_node = make_signed_type (GET_MODE_PRECISION (CImode)); | |
16041 | intXI_type_node = make_signed_type (GET_MODE_PRECISION (XImode)); | |
88f77cba | 16042 | |
bcbdbbb0 JM |
16043 | (*lang_hooks.types.register_builtin_type) (intTI_type_node, |
16044 | "__builtin_neon_ti"); | |
16045 | (*lang_hooks.types.register_builtin_type) (intEI_type_node, | |
16046 | "__builtin_neon_ei"); | |
16047 | (*lang_hooks.types.register_builtin_type) (intOI_type_node, | |
16048 | "__builtin_neon_oi"); | |
16049 | (*lang_hooks.types.register_builtin_type) (intCI_type_node, | |
16050 | "__builtin_neon_ci"); | |
16051 | (*lang_hooks.types.register_builtin_type) (intXI_type_node, | |
16052 | "__builtin_neon_xi"); | |
16053 | ||
88f77cba | 16054 | /* Pointers to vector types. */ |
af06585a JM |
16055 | V8QI_pointer_node = build_pointer_type (V8QI_type_node); |
16056 | V4HI_pointer_node = build_pointer_type (V4HI_type_node); | |
16057 | V2SI_pointer_node = build_pointer_type (V2SI_type_node); | |
16058 | V2SF_pointer_node = build_pointer_type (V2SF_type_node); | |
16059 | V16QI_pointer_node = build_pointer_type (V16QI_type_node); | |
16060 | V8HI_pointer_node = build_pointer_type (V8HI_type_node); | |
16061 | V4SI_pointer_node = build_pointer_type (V4SI_type_node); | |
16062 | V4SF_pointer_node = build_pointer_type (V4SF_type_node); | |
16063 | V2DI_pointer_node = build_pointer_type (V2DI_type_node); | |
88f77cba JB |
16064 | |
16065 | /* Operations which return results as pairs. */ | |
af06585a | 16066 | void_ftype_pv8qi_v8qi_v8qi = |
88f77cba JB |
16067 | build_function_type_list (void_type_node, V8QI_pointer_node, V8QI_type_node, |
16068 | V8QI_type_node, NULL); | |
af06585a | 16069 | void_ftype_pv4hi_v4hi_v4hi = |
88f77cba JB |
16070 | build_function_type_list (void_type_node, V4HI_pointer_node, V4HI_type_node, |
16071 | V4HI_type_node, NULL); | |
af06585a | 16072 | void_ftype_pv2si_v2si_v2si = |
88f77cba JB |
16073 | build_function_type_list (void_type_node, V2SI_pointer_node, V2SI_type_node, |
16074 | V2SI_type_node, NULL); | |
af06585a | 16075 | void_ftype_pv2sf_v2sf_v2sf = |
88f77cba JB |
16076 | build_function_type_list (void_type_node, V2SF_pointer_node, V2SF_type_node, |
16077 | V2SF_type_node, NULL); | |
af06585a | 16078 | void_ftype_pdi_di_di = |
88f77cba JB |
16079 | build_function_type_list (void_type_node, intDI_pointer_node, |
16080 | neon_intDI_type_node, neon_intDI_type_node, NULL); | |
af06585a | 16081 | void_ftype_pv16qi_v16qi_v16qi = |
88f77cba JB |
16082 | build_function_type_list (void_type_node, V16QI_pointer_node, |
16083 | V16QI_type_node, V16QI_type_node, NULL); | |
af06585a | 16084 | void_ftype_pv8hi_v8hi_v8hi = |
88f77cba JB |
16085 | build_function_type_list (void_type_node, V8HI_pointer_node, V8HI_type_node, |
16086 | V8HI_type_node, NULL); | |
af06585a | 16087 | void_ftype_pv4si_v4si_v4si = |
88f77cba JB |
16088 | build_function_type_list (void_type_node, V4SI_pointer_node, V4SI_type_node, |
16089 | V4SI_type_node, NULL); | |
af06585a | 16090 | void_ftype_pv4sf_v4sf_v4sf = |
88f77cba JB |
16091 | build_function_type_list (void_type_node, V4SF_pointer_node, V4SF_type_node, |
16092 | V4SF_type_node, NULL); | |
af06585a | 16093 | void_ftype_pv2di_v2di_v2di = |
88f77cba JB |
16094 | build_function_type_list (void_type_node, V2DI_pointer_node, V2DI_type_node, |
16095 | V2DI_type_node, NULL); | |
16096 | ||
88f77cba JB |
16097 | dreg_types[0] = V8QI_type_node; |
16098 | dreg_types[1] = V4HI_type_node; | |
16099 | dreg_types[2] = V2SI_type_node; | |
16100 | dreg_types[3] = V2SF_type_node; | |
16101 | dreg_types[4] = neon_intDI_type_node; | |
16102 | ||
16103 | qreg_types[0] = V16QI_type_node; | |
16104 | qreg_types[1] = V8HI_type_node; | |
16105 | qreg_types[2] = V4SI_type_node; | |
16106 | qreg_types[3] = V4SF_type_node; | |
16107 | qreg_types[4] = V2DI_type_node; | |
16108 | ||
16109 | for (i = 0; i < 5; i++) | |
16110 | { | |
16111 | int j; | |
16112 | for (j = 0; j < 5; j++) | |
16113 | { | |
16114 | reinterp_ftype_dreg[i][j] | |
16115 | = build_function_type_list (dreg_types[i], dreg_types[j], NULL); | |
16116 | reinterp_ftype_qreg[i][j] | |
16117 | = build_function_type_list (qreg_types[i], qreg_types[j], NULL); | |
16118 | } | |
16119 | } | |
16120 | ||
16121 | for (i = 0; i < ARRAY_SIZE (neon_builtin_data); i++) | |
16122 | { | |
16123 | neon_builtin_datum *d = &neon_builtin_data[i]; | |
16124 | unsigned int j, codeidx = 0; | |
16125 | ||
16126 | d->base_fcode = fcode; | |
16127 | ||
16128 | for (j = 0; j < T_MAX; j++) | |
16129 | { | |
16130 | const char* const modenames[] = { | |
16131 | "v8qi", "v4hi", "v2si", "v2sf", "di", | |
16132 | "v16qi", "v8hi", "v4si", "v4sf", "v2di" | |
16133 | }; | |
16134 | char namebuf[60]; | |
16135 | tree ftype = NULL; | |
16136 | enum insn_code icode; | |
16137 | int is_load = 0, is_store = 0; | |
16138 | ||
16139 | if ((d->bits & (1 << j)) == 0) | |
16140 | continue; | |
16141 | ||
16142 | icode = d->codes[codeidx++]; | |
16143 | ||
16144 | switch (d->itype) | |
16145 | { | |
16146 | case NEON_LOAD1: | |
16147 | case NEON_LOAD1LANE: | |
16148 | case NEON_LOADSTRUCT: | |
16149 | case NEON_LOADSTRUCTLANE: | |
16150 | is_load = 1; | |
16151 | /* Fall through. */ | |
16152 | case NEON_STORE1: | |
16153 | case NEON_STORE1LANE: | |
16154 | case NEON_STORESTRUCT: | |
16155 | case NEON_STORESTRUCTLANE: | |
16156 | if (!is_load) | |
16157 | is_store = 1; | |
16158 | /* Fall through. */ | |
16159 | case NEON_UNOP: | |
16160 | case NEON_BINOP: | |
16161 | case NEON_LOGICBINOP: | |
16162 | case NEON_SHIFTINSERT: | |
16163 | case NEON_TERNOP: | |
16164 | case NEON_GETLANE: | |
16165 | case NEON_SETLANE: | |
16166 | case NEON_CREATE: | |
16167 | case NEON_DUP: | |
16168 | case NEON_DUPLANE: | |
16169 | case NEON_SHIFTIMM: | |
16170 | case NEON_SHIFTACC: | |
16171 | case NEON_COMBINE: | |
16172 | case NEON_SPLIT: | |
16173 | case NEON_CONVERT: | |
16174 | case NEON_FIXCONV: | |
16175 | case NEON_LANEMUL: | |
16176 | case NEON_LANEMULL: | |
16177 | case NEON_LANEMULH: | |
16178 | case NEON_LANEMAC: | |
16179 | case NEON_SCALARMUL: | |
16180 | case NEON_SCALARMULL: | |
16181 | case NEON_SCALARMULH: | |
16182 | case NEON_SCALARMAC: | |
16183 | case NEON_SELECT: | |
16184 | case NEON_VTBL: | |
16185 | case NEON_VTBX: | |
16186 | { | |
16187 | int k; | |
16188 | tree return_type = void_type_node, args = void_list_node; | |
16189 | ||
16190 | /* Build a function type directly from the insn_data for this | |
16191 | builtin. The build_function_type() function takes care of | |
16192 | removing duplicates for us. */ | |
16193 | for (k = insn_data[icode].n_operands - 1; k >= 0; k--) | |
16194 | { | |
16195 | tree eltype; | |
16196 | ||
16197 | if (is_load && k == 1) | |
16198 | { | |
16199 | /* Neon load patterns always have the memory operand | |
16200 | (a SImode pointer) in the operand 1 position. We | |
16201 | want a const pointer to the element type in that | |
16202 | position. */ | |
16203 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
16204 | ||
16205 | switch (1 << j) | |
16206 | { | |
16207 | case T_V8QI: | |
16208 | case T_V16QI: | |
16209 | eltype = const_intQI_pointer_node; | |
16210 | break; | |
16211 | ||
16212 | case T_V4HI: | |
16213 | case T_V8HI: | |
16214 | eltype = const_intHI_pointer_node; | |
16215 | break; | |
16216 | ||
16217 | case T_V2SI: | |
16218 | case T_V4SI: | |
16219 | eltype = const_intSI_pointer_node; | |
16220 | break; | |
16221 | ||
16222 | case T_V2SF: | |
16223 | case T_V4SF: | |
16224 | eltype = const_float_pointer_node; | |
16225 | break; | |
16226 | ||
16227 | case T_DI: | |
16228 | case T_V2DI: | |
16229 | eltype = const_intDI_pointer_node; | |
16230 | break; | |
16231 | ||
16232 | default: gcc_unreachable (); | |
16233 | } | |
16234 | } | |
16235 | else if (is_store && k == 0) | |
16236 | { | |
16237 | /* Similarly, Neon store patterns use operand 0 as | |
16238 | the memory location to store to (a SImode pointer). | |
16239 | Use a pointer to the element type of the store in | |
16240 | that position. */ | |
16241 | gcc_assert (insn_data[icode].operand[k].mode == SImode); | |
16242 | ||
16243 | switch (1 << j) | |
16244 | { | |
16245 | case T_V8QI: | |
16246 | case T_V16QI: | |
16247 | eltype = intQI_pointer_node; | |
16248 | break; | |
16249 | ||
16250 | case T_V4HI: | |
16251 | case T_V8HI: | |
16252 | eltype = intHI_pointer_node; | |
16253 | break; | |
16254 | ||
16255 | case T_V2SI: | |
16256 | case T_V4SI: | |
16257 | eltype = intSI_pointer_node; | |
16258 | break; | |
16259 | ||
16260 | case T_V2SF: | |
16261 | case T_V4SF: | |
16262 | eltype = float_pointer_node; | |
16263 | break; | |
16264 | ||
16265 | case T_DI: | |
16266 | case T_V2DI: | |
16267 | eltype = intDI_pointer_node; | |
16268 | break; | |
16269 | ||
16270 | default: gcc_unreachable (); | |
16271 | } | |
16272 | } | |
16273 | else | |
16274 | { | |
16275 | switch (insn_data[icode].operand[k].mode) | |
16276 | { | |
16277 | case VOIDmode: eltype = void_type_node; break; | |
16278 | /* Scalars. */ | |
16279 | case QImode: eltype = neon_intQI_type_node; break; | |
16280 | case HImode: eltype = neon_intHI_type_node; break; | |
16281 | case SImode: eltype = neon_intSI_type_node; break; | |
16282 | case SFmode: eltype = neon_float_type_node; break; | |
16283 | case DImode: eltype = neon_intDI_type_node; break; | |
16284 | case TImode: eltype = intTI_type_node; break; | |
16285 | case EImode: eltype = intEI_type_node; break; | |
16286 | case OImode: eltype = intOI_type_node; break; | |
16287 | case CImode: eltype = intCI_type_node; break; | |
16288 | case XImode: eltype = intXI_type_node; break; | |
16289 | /* 64-bit vectors. */ | |
16290 | case V8QImode: eltype = V8QI_type_node; break; | |
16291 | case V4HImode: eltype = V4HI_type_node; break; | |
16292 | case V2SImode: eltype = V2SI_type_node; break; | |
16293 | case V2SFmode: eltype = V2SF_type_node; break; | |
16294 | /* 128-bit vectors. */ | |
16295 | case V16QImode: eltype = V16QI_type_node; break; | |
16296 | case V8HImode: eltype = V8HI_type_node; break; | |
16297 | case V4SImode: eltype = V4SI_type_node; break; | |
16298 | case V4SFmode: eltype = V4SF_type_node; break; | |
16299 | case V2DImode: eltype = V2DI_type_node; break; | |
16300 | default: gcc_unreachable (); | |
16301 | } | |
16302 | } | |
16303 | ||
16304 | if (k == 0 && !is_store) | |
16305 | return_type = eltype; | |
16306 | else | |
16307 | args = tree_cons (NULL_TREE, eltype, args); | |
16308 | } | |
16309 | ||
16310 | ftype = build_function_type (return_type, args); | |
16311 | } | |
16312 | break; | |
16313 | ||
16314 | case NEON_RESULTPAIR: | |
16315 | { | |
16316 | switch (insn_data[icode].operand[1].mode) | |
16317 | { | |
16318 | case V8QImode: ftype = void_ftype_pv8qi_v8qi_v8qi; break; | |
16319 | case V4HImode: ftype = void_ftype_pv4hi_v4hi_v4hi; break; | |
16320 | case V2SImode: ftype = void_ftype_pv2si_v2si_v2si; break; | |
16321 | case V2SFmode: ftype = void_ftype_pv2sf_v2sf_v2sf; break; | |
16322 | case DImode: ftype = void_ftype_pdi_di_di; break; | |
16323 | case V16QImode: ftype = void_ftype_pv16qi_v16qi_v16qi; break; | |
16324 | case V8HImode: ftype = void_ftype_pv8hi_v8hi_v8hi; break; | |
16325 | case V4SImode: ftype = void_ftype_pv4si_v4si_v4si; break; | |
16326 | case V4SFmode: ftype = void_ftype_pv4sf_v4sf_v4sf; break; | |
16327 | case V2DImode: ftype = void_ftype_pv2di_v2di_v2di; break; | |
16328 | default: gcc_unreachable (); | |
16329 | } | |
16330 | } | |
16331 | break; | |
16332 | ||
16333 | case NEON_REINTERP: | |
16334 | { | |
16335 | /* We iterate over 5 doubleword types, then 5 quadword | |
16336 | types. */ | |
16337 | int rhs = j % 5; | |
16338 | switch (insn_data[icode].operand[0].mode) | |
16339 | { | |
16340 | case V8QImode: ftype = reinterp_ftype_dreg[0][rhs]; break; | |
16341 | case V4HImode: ftype = reinterp_ftype_dreg[1][rhs]; break; | |
16342 | case V2SImode: ftype = reinterp_ftype_dreg[2][rhs]; break; | |
16343 | case V2SFmode: ftype = reinterp_ftype_dreg[3][rhs]; break; | |
16344 | case DImode: ftype = reinterp_ftype_dreg[4][rhs]; break; | |
16345 | case V16QImode: ftype = reinterp_ftype_qreg[0][rhs]; break; | |
16346 | case V8HImode: ftype = reinterp_ftype_qreg[1][rhs]; break; | |
16347 | case V4SImode: ftype = reinterp_ftype_qreg[2][rhs]; break; | |
16348 | case V4SFmode: ftype = reinterp_ftype_qreg[3][rhs]; break; | |
16349 | case V2DImode: ftype = reinterp_ftype_qreg[4][rhs]; break; | |
16350 | default: gcc_unreachable (); | |
16351 | } | |
16352 | } | |
16353 | break; | |
16354 | ||
16355 | default: | |
16356 | gcc_unreachable (); | |
16357 | } | |
16358 | ||
16359 | gcc_assert (ftype != NULL); | |
16360 | ||
16361 | sprintf (namebuf, "__builtin_neon_%s%s", d->name, modenames[j]); | |
16362 | ||
16363 | add_builtin_function (namebuf, ftype, fcode++, BUILT_IN_MD, NULL, | |
16364 | NULL_TREE); | |
16365 | } | |
16366 | } | |
16367 | } | |
16368 | ||
0fd8c3ad SL |
16369 | static void |
16370 | arm_init_fp16_builtins (void) | |
16371 | { | |
16372 | tree fp16_type = make_node (REAL_TYPE); | |
16373 | TYPE_PRECISION (fp16_type) = 16; | |
16374 | layout_type (fp16_type); | |
16375 | (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16"); | |
16376 | } | |
16377 | ||
5a9335ef NC |
16378 | static void |
16379 | arm_init_builtins (void) | |
16380 | { | |
d3585b76 DJ |
16381 | arm_init_tls_builtins (); |
16382 | ||
5a9335ef NC |
16383 | if (TARGET_REALLY_IWMMXT) |
16384 | arm_init_iwmmxt_builtins (); | |
88f77cba JB |
16385 | |
16386 | if (TARGET_NEON) | |
16387 | arm_init_neon_builtins (); | |
0fd8c3ad SL |
16388 | |
16389 | if (arm_fp16_format) | |
16390 | arm_init_fp16_builtins (); | |
16391 | } | |
16392 | ||
16393 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
16394 | ||
16395 | static const char * | |
16396 | arm_invalid_parameter_type (const_tree t) | |
16397 | { | |
16398 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
16399 | return N_("function parameters cannot have __fp16 type"); | |
16400 | return NULL; | |
16401 | } | |
16402 | ||
16403 | /* Implement TARGET_INVALID_PARAMETER_TYPE. */ | |
16404 | ||
16405 | static const char * | |
16406 | arm_invalid_return_type (const_tree t) | |
16407 | { | |
16408 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
16409 | return N_("functions cannot return __fp16 type"); | |
16410 | return NULL; | |
16411 | } | |
16412 | ||
16413 | /* Implement TARGET_PROMOTED_TYPE. */ | |
16414 | ||
16415 | static tree | |
16416 | arm_promoted_type (const_tree t) | |
16417 | { | |
16418 | if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16) | |
16419 | return float_type_node; | |
16420 | return NULL_TREE; | |
16421 | } | |
16422 | ||
16423 | /* Implement TARGET_CONVERT_TO_TYPE. | |
16424 | Specifically, this hook implements the peculiarity of the ARM | |
16425 | half-precision floating-point C semantics that requires conversions between | |
16426 | __fp16 to or from double to do an intermediate conversion to float. */ | |
16427 | ||
16428 | static tree | |
16429 | arm_convert_to_type (tree type, tree expr) | |
16430 | { | |
16431 | tree fromtype = TREE_TYPE (expr); | |
16432 | if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type)) | |
16433 | return NULL_TREE; | |
16434 | if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32) | |
16435 | || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32)) | |
16436 | return convert (type, convert (float_type_node, expr)); | |
16437 | return NULL_TREE; | |
5a9335ef NC |
16438 | } |
16439 | ||
bdc4827b SL |
16440 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. |
16441 | This simply adds HFmode as a supported mode; even though we don't | |
16442 | implement arithmetic on this type directly, it's supported by | |
16443 | optabs conversions, much the way the double-word arithmetic is | |
16444 | special-cased in the default hook. */ | |
16445 | ||
16446 | static bool | |
16447 | arm_scalar_mode_supported_p (enum machine_mode mode) | |
16448 | { | |
16449 | if (mode == HFmode) | |
16450 | return (arm_fp16_format != ARM_FP16_FORMAT_NONE); | |
16451 | else | |
16452 | return default_scalar_mode_supported_p (mode); | |
16453 | } | |
16454 | ||
5a9335ef NC |
16455 | /* Errors in the source file can cause expand_expr to return const0_rtx |
16456 | where we expect a vector. To avoid crashing, use one of the vector | |
16457 | clear instructions. */ | |
16458 | ||
16459 | static rtx | |
16460 | safe_vector_operand (rtx x, enum machine_mode mode) | |
16461 | { | |
16462 | if (x != const0_rtx) | |
16463 | return x; | |
16464 | x = gen_reg_rtx (mode); | |
16465 | ||
16466 | emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x | |
16467 | : gen_rtx_SUBREG (DImode, x, 0))); | |
16468 | return x; | |
16469 | } | |
16470 | ||
16471 | /* Subroutine of arm_expand_builtin to take care of binop insns. */ | |
16472 | ||
16473 | static rtx | |
16474 | arm_expand_binop_builtin (enum insn_code icode, | |
5039610b | 16475 | tree exp, rtx target) |
5a9335ef NC |
16476 | { |
16477 | rtx pat; | |
5039610b SL |
16478 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
16479 | tree arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16480 | rtx op0 = expand_normal (arg0); |
16481 | rtx op1 = expand_normal (arg1); | |
5a9335ef NC |
16482 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
16483 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
16484 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
16485 | ||
16486 | if (VECTOR_MODE_P (mode0)) | |
16487 | op0 = safe_vector_operand (op0, mode0); | |
16488 | if (VECTOR_MODE_P (mode1)) | |
16489 | op1 = safe_vector_operand (op1, mode1); | |
16490 | ||
16491 | if (! target | |
16492 | || GET_MODE (target) != tmode | |
16493 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16494 | target = gen_reg_rtx (tmode); | |
16495 | ||
e6d29d15 | 16496 | gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); |
5a9335ef NC |
16497 | |
16498 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16499 | op0 = copy_to_mode_reg (mode0, op0); | |
16500 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16501 | op1 = copy_to_mode_reg (mode1, op1); | |
16502 | ||
16503 | pat = GEN_FCN (icode) (target, op0, op1); | |
16504 | if (! pat) | |
16505 | return 0; | |
16506 | emit_insn (pat); | |
16507 | return target; | |
16508 | } | |
16509 | ||
16510 | /* Subroutine of arm_expand_builtin to take care of unop insns. */ | |
16511 | ||
16512 | static rtx | |
16513 | arm_expand_unop_builtin (enum insn_code icode, | |
5039610b | 16514 | tree exp, rtx target, int do_load) |
5a9335ef NC |
16515 | { |
16516 | rtx pat; | |
5039610b | 16517 | tree arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 16518 | rtx op0 = expand_normal (arg0); |
5a9335ef NC |
16519 | enum machine_mode tmode = insn_data[icode].operand[0].mode; |
16520 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; | |
16521 | ||
16522 | if (! target | |
16523 | || GET_MODE (target) != tmode | |
16524 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16525 | target = gen_reg_rtx (tmode); | |
16526 | if (do_load) | |
16527 | op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); | |
16528 | else | |
16529 | { | |
16530 | if (VECTOR_MODE_P (mode0)) | |
16531 | op0 = safe_vector_operand (op0, mode0); | |
16532 | ||
16533 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16534 | op0 = copy_to_mode_reg (mode0, op0); | |
16535 | } | |
16536 | ||
16537 | pat = GEN_FCN (icode) (target, op0); | |
16538 | if (! pat) | |
16539 | return 0; | |
16540 | emit_insn (pat); | |
16541 | return target; | |
16542 | } | |
16543 | ||
88f77cba JB |
16544 | static int |
16545 | neon_builtin_compare (const void *a, const void *b) | |
16546 | { | |
5ead67f6 KG |
16547 | const neon_builtin_datum *const key = (const neon_builtin_datum *) a; |
16548 | const neon_builtin_datum *const memb = (const neon_builtin_datum *) b; | |
88f77cba JB |
16549 | unsigned int soughtcode = key->base_fcode; |
16550 | ||
16551 | if (soughtcode >= memb->base_fcode | |
16552 | && soughtcode < memb->base_fcode + memb->num_vars) | |
16553 | return 0; | |
16554 | else if (soughtcode < memb->base_fcode) | |
16555 | return -1; | |
16556 | else | |
16557 | return 1; | |
16558 | } | |
16559 | ||
16560 | static enum insn_code | |
16561 | locate_neon_builtin_icode (int fcode, neon_itype *itype) | |
16562 | { | |
16563 | neon_builtin_datum key, *found; | |
16564 | int idx; | |
16565 | ||
16566 | key.base_fcode = fcode; | |
5ead67f6 KG |
16567 | found = (neon_builtin_datum *) |
16568 | bsearch (&key, &neon_builtin_data[0], ARRAY_SIZE (neon_builtin_data), | |
88f77cba JB |
16569 | sizeof (neon_builtin_data[0]), neon_builtin_compare); |
16570 | gcc_assert (found); | |
16571 | idx = fcode - (int) found->base_fcode; | |
16572 | gcc_assert (idx >= 0 && idx < T_MAX && idx < (int)found->num_vars); | |
16573 | ||
16574 | if (itype) | |
16575 | *itype = found->itype; | |
16576 | ||
16577 | return found->codes[idx]; | |
16578 | } | |
16579 | ||
16580 | typedef enum { | |
16581 | NEON_ARG_COPY_TO_REG, | |
16582 | NEON_ARG_CONSTANT, | |
16583 | NEON_ARG_STOP | |
16584 | } builtin_arg; | |
16585 | ||
16586 | #define NEON_MAX_BUILTIN_ARGS 5 | |
16587 | ||
16588 | /* Expand a Neon builtin. */ | |
16589 | static rtx | |
16590 | arm_expand_neon_args (rtx target, int icode, int have_retval, | |
16591 | tree exp, ...) | |
16592 | { | |
16593 | va_list ap; | |
16594 | rtx pat; | |
16595 | tree arg[NEON_MAX_BUILTIN_ARGS]; | |
16596 | rtx op[NEON_MAX_BUILTIN_ARGS]; | |
16597 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
16598 | enum machine_mode mode[NEON_MAX_BUILTIN_ARGS]; | |
16599 | int argc = 0; | |
16600 | ||
16601 | if (have_retval | |
16602 | && (!target | |
16603 | || GET_MODE (target) != tmode | |
16604 | || !(*insn_data[icode].operand[0].predicate) (target, tmode))) | |
16605 | target = gen_reg_rtx (tmode); | |
16606 | ||
16607 | va_start (ap, exp); | |
16608 | ||
16609 | for (;;) | |
16610 | { | |
81f40b79 | 16611 | builtin_arg thisarg = (builtin_arg) va_arg (ap, int); |
88f77cba JB |
16612 | |
16613 | if (thisarg == NEON_ARG_STOP) | |
16614 | break; | |
16615 | else | |
16616 | { | |
16617 | arg[argc] = CALL_EXPR_ARG (exp, argc); | |
16618 | op[argc] = expand_normal (arg[argc]); | |
16619 | mode[argc] = insn_data[icode].operand[argc + have_retval].mode; | |
16620 | ||
16621 | switch (thisarg) | |
16622 | { | |
16623 | case NEON_ARG_COPY_TO_REG: | |
16624 | /*gcc_assert (GET_MODE (op[argc]) == mode[argc]);*/ | |
16625 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
16626 | (op[argc], mode[argc])) | |
16627 | op[argc] = copy_to_mode_reg (mode[argc], op[argc]); | |
16628 | break; | |
16629 | ||
16630 | case NEON_ARG_CONSTANT: | |
16631 | /* FIXME: This error message is somewhat unhelpful. */ | |
16632 | if (!(*insn_data[icode].operand[argc + have_retval].predicate) | |
16633 | (op[argc], mode[argc])) | |
16634 | error ("argument must be a constant"); | |
16635 | break; | |
16636 | ||
16637 | case NEON_ARG_STOP: | |
16638 | gcc_unreachable (); | |
16639 | } | |
16640 | ||
16641 | argc++; | |
16642 | } | |
16643 | } | |
16644 | ||
16645 | va_end (ap); | |
16646 | ||
16647 | if (have_retval) | |
16648 | switch (argc) | |
16649 | { | |
16650 | case 1: | |
16651 | pat = GEN_FCN (icode) (target, op[0]); | |
16652 | break; | |
16653 | ||
16654 | case 2: | |
16655 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
16656 | break; | |
16657 | ||
16658 | case 3: | |
16659 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
16660 | break; | |
16661 | ||
16662 | case 4: | |
16663 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
16664 | break; | |
16665 | ||
16666 | case 5: | |
16667 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
16668 | break; | |
16669 | ||
16670 | default: | |
16671 | gcc_unreachable (); | |
16672 | } | |
16673 | else | |
16674 | switch (argc) | |
16675 | { | |
16676 | case 1: | |
16677 | pat = GEN_FCN (icode) (op[0]); | |
16678 | break; | |
16679 | ||
16680 | case 2: | |
16681 | pat = GEN_FCN (icode) (op[0], op[1]); | |
16682 | break; | |
16683 | ||
16684 | case 3: | |
16685 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
16686 | break; | |
16687 | ||
16688 | case 4: | |
16689 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
16690 | break; | |
16691 | ||
16692 | case 5: | |
16693 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
16694 | break; | |
16695 | ||
16696 | default: | |
16697 | gcc_unreachable (); | |
16698 | } | |
16699 | ||
16700 | if (!pat) | |
16701 | return 0; | |
16702 | ||
16703 | emit_insn (pat); | |
16704 | ||
16705 | return target; | |
16706 | } | |
16707 | ||
16708 | /* Expand a Neon builtin. These are "special" because they don't have symbolic | |
16709 | constants defined per-instruction or per instruction-variant. Instead, the | |
16710 | required info is looked up in the table neon_builtin_data. */ | |
16711 | static rtx | |
16712 | arm_expand_neon_builtin (int fcode, tree exp, rtx target) | |
16713 | { | |
16714 | neon_itype itype; | |
16715 | enum insn_code icode = locate_neon_builtin_icode (fcode, &itype); | |
16716 | ||
16717 | switch (itype) | |
16718 | { | |
16719 | case NEON_UNOP: | |
16720 | case NEON_CONVERT: | |
16721 | case NEON_DUPLANE: | |
16722 | return arm_expand_neon_args (target, icode, 1, exp, | |
16723 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16724 | ||
16725 | case NEON_BINOP: | |
16726 | case NEON_SETLANE: | |
16727 | case NEON_SCALARMUL: | |
16728 | case NEON_SCALARMULL: | |
16729 | case NEON_SCALARMULH: | |
16730 | case NEON_SHIFTINSERT: | |
16731 | case NEON_LOGICBINOP: | |
16732 | return arm_expand_neon_args (target, icode, 1, exp, | |
16733 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16734 | NEON_ARG_STOP); | |
16735 | ||
16736 | case NEON_TERNOP: | |
16737 | return arm_expand_neon_args (target, icode, 1, exp, | |
16738 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16739 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16740 | ||
16741 | case NEON_GETLANE: | |
16742 | case NEON_FIXCONV: | |
16743 | case NEON_SHIFTIMM: | |
16744 | return arm_expand_neon_args (target, icode, 1, exp, | |
16745 | NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, | |
16746 | NEON_ARG_STOP); | |
16747 | ||
16748 | case NEON_CREATE: | |
16749 | return arm_expand_neon_args (target, icode, 1, exp, | |
16750 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16751 | ||
16752 | case NEON_DUP: | |
16753 | case NEON_SPLIT: | |
16754 | case NEON_REINTERP: | |
16755 | return arm_expand_neon_args (target, icode, 1, exp, | |
16756 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16757 | ||
16758 | case NEON_COMBINE: | |
16759 | case NEON_VTBL: | |
16760 | return arm_expand_neon_args (target, icode, 1, exp, | |
16761 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16762 | ||
16763 | case NEON_RESULTPAIR: | |
16764 | return arm_expand_neon_args (target, icode, 0, exp, | |
16765 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16766 | NEON_ARG_STOP); | |
16767 | ||
16768 | case NEON_LANEMUL: | |
16769 | case NEON_LANEMULL: | |
16770 | case NEON_LANEMULH: | |
16771 | return arm_expand_neon_args (target, icode, 1, exp, | |
16772 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16773 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16774 | ||
16775 | case NEON_LANEMAC: | |
16776 | return arm_expand_neon_args (target, icode, 1, exp, | |
16777 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16778 | NEON_ARG_CONSTANT, NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16779 | ||
16780 | case NEON_SHIFTACC: | |
16781 | return arm_expand_neon_args (target, icode, 1, exp, | |
16782 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16783 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16784 | ||
16785 | case NEON_SCALARMAC: | |
16786 | return arm_expand_neon_args (target, icode, 1, exp, | |
16787 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16788 | NEON_ARG_CONSTANT, NEON_ARG_STOP); | |
16789 | ||
16790 | case NEON_SELECT: | |
16791 | case NEON_VTBX: | |
16792 | return arm_expand_neon_args (target, icode, 1, exp, | |
16793 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, | |
16794 | NEON_ARG_STOP); | |
16795 | ||
16796 | case NEON_LOAD1: | |
16797 | case NEON_LOADSTRUCT: | |
16798 | return arm_expand_neon_args (target, icode, 1, exp, | |
16799 | NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16800 | ||
16801 | case NEON_LOAD1LANE: | |
16802 | case NEON_LOADSTRUCTLANE: | |
16803 | return arm_expand_neon_args (target, icode, 1, exp, | |
16804 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16805 | NEON_ARG_STOP); | |
16806 | ||
16807 | case NEON_STORE1: | |
16808 | case NEON_STORESTRUCT: | |
16809 | return arm_expand_neon_args (target, icode, 0, exp, | |
16810 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_STOP); | |
16811 | ||
16812 | case NEON_STORE1LANE: | |
16813 | case NEON_STORESTRUCTLANE: | |
16814 | return arm_expand_neon_args (target, icode, 0, exp, | |
16815 | NEON_ARG_COPY_TO_REG, NEON_ARG_COPY_TO_REG, NEON_ARG_CONSTANT, | |
16816 | NEON_ARG_STOP); | |
16817 | } | |
16818 | ||
16819 | gcc_unreachable (); | |
16820 | } | |
16821 | ||
16822 | /* Emit code to reinterpret one Neon type as another, without altering bits. */ | |
16823 | void | |
16824 | neon_reinterpret (rtx dest, rtx src) | |
16825 | { | |
16826 | emit_move_insn (dest, gen_lowpart (GET_MODE (dest), src)); | |
16827 | } | |
16828 | ||
16829 | /* Emit code to place a Neon pair result in memory locations (with equal | |
16830 | registers). */ | |
16831 | void | |
16832 | neon_emit_pair_result_insn (enum machine_mode mode, | |
16833 | rtx (*intfn) (rtx, rtx, rtx, rtx), rtx destaddr, | |
16834 | rtx op1, rtx op2) | |
16835 | { | |
16836 | rtx mem = gen_rtx_MEM (mode, destaddr); | |
16837 | rtx tmp1 = gen_reg_rtx (mode); | |
16838 | rtx tmp2 = gen_reg_rtx (mode); | |
16839 | ||
16840 | emit_insn (intfn (tmp1, op1, tmp2, op2)); | |
16841 | ||
16842 | emit_move_insn (mem, tmp1); | |
16843 | mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); | |
16844 | emit_move_insn (mem, tmp2); | |
16845 | } | |
16846 | ||
16847 | /* Set up operands for a register copy from src to dest, taking care not to | |
16848 | clobber registers in the process. | |
16849 | FIXME: This has rather high polynomial complexity (O(n^3)?) but shouldn't | |
16850 | be called with a large N, so that should be OK. */ | |
16851 | ||
16852 | void | |
16853 | neon_disambiguate_copy (rtx *operands, rtx *dest, rtx *src, unsigned int count) | |
16854 | { | |
16855 | unsigned int copied = 0, opctr = 0; | |
16856 | unsigned int done = (1 << count) - 1; | |
16857 | unsigned int i, j; | |
16858 | ||
16859 | while (copied != done) | |
16860 | { | |
16861 | for (i = 0; i < count; i++) | |
16862 | { | |
16863 | int good = 1; | |
16864 | ||
16865 | for (j = 0; good && j < count; j++) | |
16866 | if (i != j && (copied & (1 << j)) == 0 | |
16867 | && reg_overlap_mentioned_p (src[j], dest[i])) | |
16868 | good = 0; | |
16869 | ||
16870 | if (good) | |
16871 | { | |
16872 | operands[opctr++] = dest[i]; | |
16873 | operands[opctr++] = src[i]; | |
16874 | copied |= 1 << i; | |
16875 | } | |
16876 | } | |
16877 | } | |
16878 | ||
16879 | gcc_assert (opctr == count * 2); | |
16880 | } | |
16881 | ||
5a9335ef NC |
16882 | /* Expand an expression EXP that calls a built-in function, |
16883 | with result going to TARGET if that's convenient | |
16884 | (and in mode MODE if that's convenient). | |
16885 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
16886 | IGNORE is nonzero if the value is to be ignored. */ | |
16887 | ||
16888 | static rtx | |
16889 | arm_expand_builtin (tree exp, | |
16890 | rtx target, | |
16891 | rtx subtarget ATTRIBUTE_UNUSED, | |
16892 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
16893 | int ignore ATTRIBUTE_UNUSED) | |
16894 | { | |
16895 | const struct builtin_description * d; | |
16896 | enum insn_code icode; | |
5039610b | 16897 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
5a9335ef NC |
16898 | tree arg0; |
16899 | tree arg1; | |
16900 | tree arg2; | |
16901 | rtx op0; | |
16902 | rtx op1; | |
16903 | rtx op2; | |
16904 | rtx pat; | |
16905 | int fcode = DECL_FUNCTION_CODE (fndecl); | |
16906 | size_t i; | |
16907 | enum machine_mode tmode; | |
16908 | enum machine_mode mode0; | |
16909 | enum machine_mode mode1; | |
16910 | enum machine_mode mode2; | |
16911 | ||
88f77cba JB |
16912 | if (fcode >= ARM_BUILTIN_NEON_BASE) |
16913 | return arm_expand_neon_builtin (fcode, exp, target); | |
16914 | ||
5a9335ef NC |
16915 | switch (fcode) |
16916 | { | |
16917 | case ARM_BUILTIN_TEXTRMSB: | |
16918 | case ARM_BUILTIN_TEXTRMUB: | |
16919 | case ARM_BUILTIN_TEXTRMSH: | |
16920 | case ARM_BUILTIN_TEXTRMUH: | |
16921 | case ARM_BUILTIN_TEXTRMSW: | |
16922 | case ARM_BUILTIN_TEXTRMUW: | |
16923 | icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb | |
16924 | : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub | |
16925 | : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh | |
16926 | : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh | |
16927 | : CODE_FOR_iwmmxt_textrmw); | |
16928 | ||
5039610b SL |
16929 | arg0 = CALL_EXPR_ARG (exp, 0); |
16930 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16931 | op0 = expand_normal (arg0); |
16932 | op1 = expand_normal (arg1); | |
5a9335ef NC |
16933 | tmode = insn_data[icode].operand[0].mode; |
16934 | mode0 = insn_data[icode].operand[1].mode; | |
16935 | mode1 = insn_data[icode].operand[2].mode; | |
16936 | ||
16937 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16938 | op0 = copy_to_mode_reg (mode0, op0); | |
16939 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16940 | { | |
16941 | /* @@@ better error message */ | |
16942 | error ("selector must be an immediate"); | |
16943 | return gen_reg_rtx (tmode); | |
16944 | } | |
16945 | if (target == 0 | |
16946 | || GET_MODE (target) != tmode | |
16947 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16948 | target = gen_reg_rtx (tmode); | |
16949 | pat = GEN_FCN (icode) (target, op0, op1); | |
16950 | if (! pat) | |
16951 | return 0; | |
16952 | emit_insn (pat); | |
16953 | return target; | |
16954 | ||
16955 | case ARM_BUILTIN_TINSRB: | |
16956 | case ARM_BUILTIN_TINSRH: | |
16957 | case ARM_BUILTIN_TINSRW: | |
16958 | icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb | |
16959 | : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh | |
16960 | : CODE_FOR_iwmmxt_tinsrw); | |
5039610b SL |
16961 | arg0 = CALL_EXPR_ARG (exp, 0); |
16962 | arg1 = CALL_EXPR_ARG (exp, 1); | |
16963 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
16964 | op0 = expand_normal (arg0); |
16965 | op1 = expand_normal (arg1); | |
16966 | op2 = expand_normal (arg2); | |
5a9335ef NC |
16967 | tmode = insn_data[icode].operand[0].mode; |
16968 | mode0 = insn_data[icode].operand[1].mode; | |
16969 | mode1 = insn_data[icode].operand[2].mode; | |
16970 | mode2 = insn_data[icode].operand[3].mode; | |
16971 | ||
16972 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
16973 | op0 = copy_to_mode_reg (mode0, op0); | |
16974 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
16975 | op1 = copy_to_mode_reg (mode1, op1); | |
16976 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
16977 | { | |
16978 | /* @@@ better error message */ | |
16979 | error ("selector must be an immediate"); | |
16980 | return const0_rtx; | |
16981 | } | |
16982 | if (target == 0 | |
16983 | || GET_MODE (target) != tmode | |
16984 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
16985 | target = gen_reg_rtx (tmode); | |
16986 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
16987 | if (! pat) | |
16988 | return 0; | |
16989 | emit_insn (pat); | |
16990 | return target; | |
16991 | ||
16992 | case ARM_BUILTIN_SETWCX: | |
5039610b SL |
16993 | arg0 = CALL_EXPR_ARG (exp, 0); |
16994 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
16995 | op0 = force_reg (SImode, expand_normal (arg0)); |
16996 | op1 = expand_normal (arg1); | |
f07a6b21 | 16997 | emit_insn (gen_iwmmxt_tmcr (op1, op0)); |
5a9335ef NC |
16998 | return 0; |
16999 | ||
17000 | case ARM_BUILTIN_GETWCX: | |
5039610b | 17001 | arg0 = CALL_EXPR_ARG (exp, 0); |
84217346 | 17002 | op0 = expand_normal (arg0); |
5a9335ef NC |
17003 | target = gen_reg_rtx (SImode); |
17004 | emit_insn (gen_iwmmxt_tmrc (target, op0)); | |
17005 | return target; | |
17006 | ||
17007 | case ARM_BUILTIN_WSHUFH: | |
17008 | icode = CODE_FOR_iwmmxt_wshufh; | |
5039610b SL |
17009 | arg0 = CALL_EXPR_ARG (exp, 0); |
17010 | arg1 = CALL_EXPR_ARG (exp, 1); | |
84217346 MD |
17011 | op0 = expand_normal (arg0); |
17012 | op1 = expand_normal (arg1); | |
5a9335ef NC |
17013 | tmode = insn_data[icode].operand[0].mode; |
17014 | mode1 = insn_data[icode].operand[1].mode; | |
17015 | mode2 = insn_data[icode].operand[2].mode; | |
17016 | ||
17017 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) | |
17018 | op0 = copy_to_mode_reg (mode1, op0); | |
17019 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) | |
17020 | { | |
17021 | /* @@@ better error message */ | |
17022 | error ("mask must be an immediate"); | |
17023 | return const0_rtx; | |
17024 | } | |
17025 | if (target == 0 | |
17026 | || GET_MODE (target) != tmode | |
17027 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
17028 | target = gen_reg_rtx (tmode); | |
17029 | pat = GEN_FCN (icode) (target, op0, op1); | |
17030 | if (! pat) | |
17031 | return 0; | |
17032 | emit_insn (pat); | |
17033 | return target; | |
17034 | ||
17035 | case ARM_BUILTIN_WSADB: | |
5039610b | 17036 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target); |
5a9335ef | 17037 | case ARM_BUILTIN_WSADH: |
5039610b | 17038 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target); |
5a9335ef | 17039 | case ARM_BUILTIN_WSADBZ: |
5039610b | 17040 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target); |
5a9335ef | 17041 | case ARM_BUILTIN_WSADHZ: |
5039610b | 17042 | return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target); |
5a9335ef NC |
17043 | |
17044 | /* Several three-argument builtins. */ | |
17045 | case ARM_BUILTIN_WMACS: | |
17046 | case ARM_BUILTIN_WMACU: | |
17047 | case ARM_BUILTIN_WALIGN: | |
17048 | case ARM_BUILTIN_TMIA: | |
17049 | case ARM_BUILTIN_TMIAPH: | |
17050 | case ARM_BUILTIN_TMIATT: | |
17051 | case ARM_BUILTIN_TMIATB: | |
17052 | case ARM_BUILTIN_TMIABT: | |
17053 | case ARM_BUILTIN_TMIABB: | |
17054 | icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs | |
17055 | : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu | |
17056 | : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia | |
17057 | : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph | |
17058 | : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb | |
17059 | : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt | |
17060 | : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb | |
17061 | : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt | |
17062 | : CODE_FOR_iwmmxt_walign); | |
5039610b SL |
17063 | arg0 = CALL_EXPR_ARG (exp, 0); |
17064 | arg1 = CALL_EXPR_ARG (exp, 1); | |
17065 | arg2 = CALL_EXPR_ARG (exp, 2); | |
84217346 MD |
17066 | op0 = expand_normal (arg0); |
17067 | op1 = expand_normal (arg1); | |
17068 | op2 = expand_normal (arg2); | |
5a9335ef NC |
17069 | tmode = insn_data[icode].operand[0].mode; |
17070 | mode0 = insn_data[icode].operand[1].mode; | |
17071 | mode1 = insn_data[icode].operand[2].mode; | |
17072 | mode2 = insn_data[icode].operand[3].mode; | |
17073 | ||
17074 | if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) | |
17075 | op0 = copy_to_mode_reg (mode0, op0); | |
17076 | if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) | |
17077 | op1 = copy_to_mode_reg (mode1, op1); | |
17078 | if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) | |
17079 | op2 = copy_to_mode_reg (mode2, op2); | |
17080 | if (target == 0 | |
17081 | || GET_MODE (target) != tmode | |
17082 | || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) | |
17083 | target = gen_reg_rtx (tmode); | |
17084 | pat = GEN_FCN (icode) (target, op0, op1, op2); | |
17085 | if (! pat) | |
17086 | return 0; | |
17087 | emit_insn (pat); | |
17088 | return target; | |
f676971a | 17089 | |
5a9335ef NC |
17090 | case ARM_BUILTIN_WZERO: |
17091 | target = gen_reg_rtx (DImode); | |
17092 | emit_insn (gen_iwmmxt_clrdi (target)); | |
17093 | return target; | |
17094 | ||
d3585b76 DJ |
17095 | case ARM_BUILTIN_THREAD_POINTER: |
17096 | return arm_load_tp (target); | |
17097 | ||
5a9335ef NC |
17098 | default: |
17099 | break; | |
17100 | } | |
17101 | ||
e97a46ce | 17102 | for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) |
5a9335ef | 17103 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 17104 | return arm_expand_binop_builtin (d->icode, exp, target); |
5a9335ef | 17105 | |
e97a46ce | 17106 | for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) |
5a9335ef | 17107 | if (d->code == (const enum arm_builtins) fcode) |
5039610b | 17108 | return arm_expand_unop_builtin (d->icode, exp, target, 0); |
5a9335ef NC |
17109 | |
17110 | /* @@@ Should really do something sensible here. */ | |
17111 | return NULL_RTX; | |
17112 | } | |
17113 | \f | |
1d6e90ac NC |
17114 | /* Return the number (counting from 0) of |
17115 | the least significant set bit in MASK. */ | |
17116 | ||
e32bac5b | 17117 | inline static int |
b279b20a | 17118 | number_of_first_bit_set (unsigned mask) |
d5b7b3ae RE |
17119 | { |
17120 | int bit; | |
17121 | ||
17122 | for (bit = 0; | |
17123 | (mask & (1 << bit)) == 0; | |
5895f793 | 17124 | ++bit) |
d5b7b3ae RE |
17125 | continue; |
17126 | ||
17127 | return bit; | |
17128 | } | |
17129 | ||
b279b20a NC |
17130 | /* Emit code to push or pop registers to or from the stack. F is the |
17131 | assembly file. MASK is the registers to push or pop. PUSH is | |
17132 | nonzero if we should push, and zero if we should pop. For debugging | |
17133 | output, if pushing, adjust CFA_OFFSET by the amount of space added | |
17134 | to the stack. REAL_REGS should have the same number of bits set as | |
17135 | MASK, and will be used instead (in the same order) to describe which | |
17136 | registers were saved - this is used to mark the save slots when we | |
17137 | push high registers after moving them to low registers. */ | |
17138 | static void | |
17139 | thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, | |
17140 | unsigned long real_regs) | |
17141 | { | |
17142 | int regno; | |
17143 | int lo_mask = mask & 0xFF; | |
17144 | int pushed_words = 0; | |
17145 | ||
e6d29d15 | 17146 | gcc_assert (mask); |
b279b20a NC |
17147 | |
17148 | if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) | |
17149 | { | |
17150 | /* Special case. Do not generate a POP PC statement here, do it in | |
17151 | thumb_exit() */ | |
17152 | thumb_exit (f, -1); | |
17153 | return; | |
17154 | } | |
17155 | ||
617a1b71 PB |
17156 | if (ARM_EABI_UNWIND_TABLES && push) |
17157 | { | |
17158 | fprintf (f, "\t.save\t{"); | |
17159 | for (regno = 0; regno < 15; regno++) | |
17160 | { | |
17161 | if (real_regs & (1 << regno)) | |
17162 | { | |
17163 | if (real_regs & ((1 << regno) -1)) | |
17164 | fprintf (f, ", "); | |
17165 | asm_fprintf (f, "%r", regno); | |
17166 | } | |
17167 | } | |
17168 | fprintf (f, "}\n"); | |
17169 | } | |
17170 | ||
b279b20a NC |
17171 | fprintf (f, "\t%s\t{", push ? "push" : "pop"); |
17172 | ||
17173 | /* Look at the low registers first. */ | |
17174 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) | |
17175 | { | |
17176 | if (lo_mask & 1) | |
17177 | { | |
17178 | asm_fprintf (f, "%r", regno); | |
17179 | ||
17180 | if ((lo_mask & ~1) != 0) | |
17181 | fprintf (f, ", "); | |
17182 | ||
17183 | pushed_words++; | |
17184 | } | |
17185 | } | |
17186 | ||
17187 | if (push && (mask & (1 << LR_REGNUM))) | |
17188 | { | |
17189 | /* Catch pushing the LR. */ | |
17190 | if (mask & 0xFF) | |
17191 | fprintf (f, ", "); | |
17192 | ||
17193 | asm_fprintf (f, "%r", LR_REGNUM); | |
17194 | ||
17195 | pushed_words++; | |
17196 | } | |
17197 | else if (!push && (mask & (1 << PC_REGNUM))) | |
17198 | { | |
17199 | /* Catch popping the PC. */ | |
17200 | if (TARGET_INTERWORK || TARGET_BACKTRACE | |
e3b5732b | 17201 | || crtl->calls_eh_return) |
b279b20a NC |
17202 | { |
17203 | /* The PC is never poped directly, instead | |
17204 | it is popped into r3 and then BX is used. */ | |
17205 | fprintf (f, "}\n"); | |
17206 | ||
17207 | thumb_exit (f, -1); | |
17208 | ||
17209 | return; | |
17210 | } | |
17211 | else | |
17212 | { | |
17213 | if (mask & 0xFF) | |
17214 | fprintf (f, ", "); | |
17215 | ||
17216 | asm_fprintf (f, "%r", PC_REGNUM); | |
17217 | } | |
17218 | } | |
17219 | ||
17220 | fprintf (f, "}\n"); | |
17221 | ||
17222 | if (push && pushed_words && dwarf2out_do_frame ()) | |
17223 | { | |
d342c045 | 17224 | char *l = dwarf2out_cfi_label (false); |
b279b20a NC |
17225 | int pushed_mask = real_regs; |
17226 | ||
17227 | *cfa_offset += pushed_words * 4; | |
17228 | dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); | |
17229 | ||
17230 | pushed_words = 0; | |
17231 | pushed_mask = real_regs; | |
17232 | for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) | |
17233 | { | |
17234 | if (pushed_mask & 1) | |
17235 | dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); | |
17236 | } | |
17237 | } | |
17238 | } | |
17239 | ||
d5b7b3ae RE |
17240 | /* Generate code to return from a thumb function. |
17241 | If 'reg_containing_return_addr' is -1, then the return address is | |
17242 | actually on the stack, at the stack pointer. */ | |
17243 | static void | |
c9ca9b88 | 17244 | thumb_exit (FILE *f, int reg_containing_return_addr) |
d5b7b3ae RE |
17245 | { |
17246 | unsigned regs_available_for_popping; | |
17247 | unsigned regs_to_pop; | |
17248 | int pops_needed; | |
17249 | unsigned available; | |
17250 | unsigned required; | |
17251 | int mode; | |
17252 | int size; | |
17253 | int restore_a4 = FALSE; | |
17254 | ||
17255 | /* Compute the registers we need to pop. */ | |
17256 | regs_to_pop = 0; | |
17257 | pops_needed = 0; | |
17258 | ||
c9ca9b88 | 17259 | if (reg_containing_return_addr == -1) |
d5b7b3ae | 17260 | { |
d5b7b3ae | 17261 | regs_to_pop |= 1 << LR_REGNUM; |
5895f793 | 17262 | ++pops_needed; |
d5b7b3ae RE |
17263 | } |
17264 | ||
17265 | if (TARGET_BACKTRACE) | |
17266 | { | |
17267 | /* Restore the (ARM) frame pointer and stack pointer. */ | |
17268 | regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); | |
17269 | pops_needed += 2; | |
17270 | } | |
17271 | ||
17272 | /* If there is nothing to pop then just emit the BX instruction and | |
17273 | return. */ | |
17274 | if (pops_needed == 0) | |
17275 | { | |
e3b5732b | 17276 | if (crtl->calls_eh_return) |
c9ca9b88 | 17277 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
17278 | |
17279 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
17280 | return; | |
17281 | } | |
17282 | /* Otherwise if we are not supporting interworking and we have not created | |
17283 | a backtrace structure and the function was not entered in ARM mode then | |
17284 | just pop the return address straight into the PC. */ | |
5895f793 RE |
17285 | else if (!TARGET_INTERWORK |
17286 | && !TARGET_BACKTRACE | |
c9ca9b88 | 17287 | && !is_called_in_ARM_mode (current_function_decl) |
e3b5732b | 17288 | && !crtl->calls_eh_return) |
d5b7b3ae | 17289 | { |
c9ca9b88 | 17290 | asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); |
d5b7b3ae RE |
17291 | return; |
17292 | } | |
17293 | ||
17294 | /* Find out how many of the (return) argument registers we can corrupt. */ | |
17295 | regs_available_for_popping = 0; | |
17296 | ||
17297 | /* If returning via __builtin_eh_return, the bottom three registers | |
17298 | all contain information needed for the return. */ | |
e3b5732b | 17299 | if (crtl->calls_eh_return) |
d5b7b3ae RE |
17300 | size = 12; |
17301 | else | |
17302 | { | |
d5b7b3ae RE |
17303 | /* If we can deduce the registers used from the function's |
17304 | return value. This is more reliable that examining | |
6fb5fa3c | 17305 | df_regs_ever_live_p () because that will be set if the register is |
d5b7b3ae RE |
17306 | ever used in the function, not just if the register is used |
17307 | to hold a return value. */ | |
17308 | ||
38173d38 JH |
17309 | if (crtl->return_rtx != 0) |
17310 | mode = GET_MODE (crtl->return_rtx); | |
d5b7b3ae | 17311 | else |
d5b7b3ae RE |
17312 | mode = DECL_MODE (DECL_RESULT (current_function_decl)); |
17313 | ||
17314 | size = GET_MODE_SIZE (mode); | |
17315 | ||
17316 | if (size == 0) | |
17317 | { | |
17318 | /* In a void function we can use any argument register. | |
17319 | In a function that returns a structure on the stack | |
17320 | we can use the second and third argument registers. */ | |
17321 | if (mode == VOIDmode) | |
17322 | regs_available_for_popping = | |
17323 | (1 << ARG_REGISTER (1)) | |
17324 | | (1 << ARG_REGISTER (2)) | |
17325 | | (1 << ARG_REGISTER (3)); | |
17326 | else | |
17327 | regs_available_for_popping = | |
17328 | (1 << ARG_REGISTER (2)) | |
17329 | | (1 << ARG_REGISTER (3)); | |
17330 | } | |
17331 | else if (size <= 4) | |
17332 | regs_available_for_popping = | |
17333 | (1 << ARG_REGISTER (2)) | |
17334 | | (1 << ARG_REGISTER (3)); | |
17335 | else if (size <= 8) | |
17336 | regs_available_for_popping = | |
17337 | (1 << ARG_REGISTER (3)); | |
17338 | } | |
17339 | ||
17340 | /* Match registers to be popped with registers into which we pop them. */ | |
17341 | for (available = regs_available_for_popping, | |
17342 | required = regs_to_pop; | |
17343 | required != 0 && available != 0; | |
17344 | available &= ~(available & - available), | |
17345 | required &= ~(required & - required)) | |
17346 | -- pops_needed; | |
17347 | ||
17348 | /* If we have any popping registers left over, remove them. */ | |
17349 | if (available > 0) | |
5895f793 | 17350 | regs_available_for_popping &= ~available; |
f676971a | 17351 | |
d5b7b3ae RE |
17352 | /* Otherwise if we need another popping register we can use |
17353 | the fourth argument register. */ | |
17354 | else if (pops_needed) | |
17355 | { | |
17356 | /* If we have not found any free argument registers and | |
17357 | reg a4 contains the return address, we must move it. */ | |
17358 | if (regs_available_for_popping == 0 | |
17359 | && reg_containing_return_addr == LAST_ARG_REGNUM) | |
17360 | { | |
17361 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
17362 | reg_containing_return_addr = LR_REGNUM; | |
17363 | } | |
17364 | else if (size > 12) | |
17365 | { | |
17366 | /* Register a4 is being used to hold part of the return value, | |
17367 | but we have dire need of a free, low register. */ | |
17368 | restore_a4 = TRUE; | |
f676971a | 17369 | |
d5b7b3ae RE |
17370 | asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); |
17371 | } | |
f676971a | 17372 | |
d5b7b3ae RE |
17373 | if (reg_containing_return_addr != LAST_ARG_REGNUM) |
17374 | { | |
17375 | /* The fourth argument register is available. */ | |
17376 | regs_available_for_popping |= 1 << LAST_ARG_REGNUM; | |
f676971a | 17377 | |
5895f793 | 17378 | --pops_needed; |
d5b7b3ae RE |
17379 | } |
17380 | } | |
17381 | ||
17382 | /* Pop as many registers as we can. */ | |
980e61bb DJ |
17383 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17384 | regs_available_for_popping); | |
d5b7b3ae RE |
17385 | |
17386 | /* Process the registers we popped. */ | |
17387 | if (reg_containing_return_addr == -1) | |
17388 | { | |
17389 | /* The return address was popped into the lowest numbered register. */ | |
5895f793 | 17390 | regs_to_pop &= ~(1 << LR_REGNUM); |
f676971a | 17391 | |
d5b7b3ae RE |
17392 | reg_containing_return_addr = |
17393 | number_of_first_bit_set (regs_available_for_popping); | |
17394 | ||
17395 | /* Remove this register for the mask of available registers, so that | |
6bc82793 | 17396 | the return address will not be corrupted by further pops. */ |
5895f793 | 17397 | regs_available_for_popping &= ~(1 << reg_containing_return_addr); |
d5b7b3ae RE |
17398 | } |
17399 | ||
17400 | /* If we popped other registers then handle them here. */ | |
17401 | if (regs_available_for_popping) | |
17402 | { | |
17403 | int frame_pointer; | |
f676971a | 17404 | |
d5b7b3ae RE |
17405 | /* Work out which register currently contains the frame pointer. */ |
17406 | frame_pointer = number_of_first_bit_set (regs_available_for_popping); | |
17407 | ||
17408 | /* Move it into the correct place. */ | |
17409 | asm_fprintf (f, "\tmov\t%r, %r\n", | |
17410 | ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); | |
17411 | ||
17412 | /* (Temporarily) remove it from the mask of popped registers. */ | |
5895f793 RE |
17413 | regs_available_for_popping &= ~(1 << frame_pointer); |
17414 | regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); | |
f676971a | 17415 | |
d5b7b3ae RE |
17416 | if (regs_available_for_popping) |
17417 | { | |
17418 | int stack_pointer; | |
f676971a | 17419 | |
d5b7b3ae RE |
17420 | /* We popped the stack pointer as well, |
17421 | find the register that contains it. */ | |
17422 | stack_pointer = number_of_first_bit_set (regs_available_for_popping); | |
17423 | ||
17424 | /* Move it into the stack register. */ | |
17425 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); | |
f676971a | 17426 | |
d5b7b3ae RE |
17427 | /* At this point we have popped all necessary registers, so |
17428 | do not worry about restoring regs_available_for_popping | |
17429 | to its correct value: | |
17430 | ||
17431 | assert (pops_needed == 0) | |
17432 | assert (regs_available_for_popping == (1 << frame_pointer)) | |
17433 | assert (regs_to_pop == (1 << STACK_POINTER)) */ | |
17434 | } | |
17435 | else | |
17436 | { | |
17437 | /* Since we have just move the popped value into the frame | |
17438 | pointer, the popping register is available for reuse, and | |
17439 | we know that we still have the stack pointer left to pop. */ | |
17440 | regs_available_for_popping |= (1 << frame_pointer); | |
17441 | } | |
17442 | } | |
f676971a | 17443 | |
d5b7b3ae RE |
17444 | /* If we still have registers left on the stack, but we no longer have |
17445 | any registers into which we can pop them, then we must move the return | |
17446 | address into the link register and make available the register that | |
17447 | contained it. */ | |
17448 | if (regs_available_for_popping == 0 && pops_needed > 0) | |
17449 | { | |
17450 | regs_available_for_popping |= 1 << reg_containing_return_addr; | |
f676971a | 17451 | |
d5b7b3ae RE |
17452 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, |
17453 | reg_containing_return_addr); | |
f676971a | 17454 | |
d5b7b3ae RE |
17455 | reg_containing_return_addr = LR_REGNUM; |
17456 | } | |
17457 | ||
17458 | /* If we have registers left on the stack then pop some more. | |
17459 | We know that at most we will want to pop FP and SP. */ | |
17460 | if (pops_needed > 0) | |
17461 | { | |
17462 | int popped_into; | |
17463 | int move_to; | |
f676971a | 17464 | |
980e61bb DJ |
17465 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17466 | regs_available_for_popping); | |
d5b7b3ae RE |
17467 | |
17468 | /* We have popped either FP or SP. | |
17469 | Move whichever one it is into the correct register. */ | |
17470 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
17471 | move_to = number_of_first_bit_set (regs_to_pop); | |
17472 | ||
17473 | asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); | |
17474 | ||
5895f793 | 17475 | regs_to_pop &= ~(1 << move_to); |
d5b7b3ae | 17476 | |
5895f793 | 17477 | --pops_needed; |
d5b7b3ae | 17478 | } |
f676971a | 17479 | |
d5b7b3ae RE |
17480 | /* If we still have not popped everything then we must have only |
17481 | had one register available to us and we are now popping the SP. */ | |
17482 | if (pops_needed > 0) | |
17483 | { | |
17484 | int popped_into; | |
f676971a | 17485 | |
980e61bb DJ |
17486 | thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, |
17487 | regs_available_for_popping); | |
d5b7b3ae RE |
17488 | |
17489 | popped_into = number_of_first_bit_set (regs_available_for_popping); | |
17490 | ||
17491 | asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); | |
17492 | /* | |
17493 | assert (regs_to_pop == (1 << STACK_POINTER)) | |
17494 | assert (pops_needed == 1) | |
17495 | */ | |
17496 | } | |
17497 | ||
17498 | /* If necessary restore the a4 register. */ | |
17499 | if (restore_a4) | |
17500 | { | |
17501 | if (reg_containing_return_addr != LR_REGNUM) | |
17502 | { | |
17503 | asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); | |
17504 | reg_containing_return_addr = LR_REGNUM; | |
17505 | } | |
f676971a | 17506 | |
d5b7b3ae RE |
17507 | asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); |
17508 | } | |
17509 | ||
e3b5732b | 17510 | if (crtl->calls_eh_return) |
c9ca9b88 | 17511 | asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); |
d5b7b3ae RE |
17512 | |
17513 | /* Return to caller. */ | |
17514 | asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); | |
17515 | } | |
17516 | ||
d5b7b3ae RE |
17517 | \f |
17518 | void | |
5b3e6663 | 17519 | thumb1_final_prescan_insn (rtx insn) |
d5b7b3ae | 17520 | { |
d5b7b3ae | 17521 | if (flag_print_asm_name) |
9d98a694 AO |
17522 | asm_fprintf (asm_out_file, "%@ 0x%04x\n", |
17523 | INSN_ADDRESSES (INSN_UID (insn))); | |
d5b7b3ae RE |
17524 | } |
17525 | ||
17526 | int | |
e32bac5b | 17527 | thumb_shiftable_const (unsigned HOST_WIDE_INT val) |
d5b7b3ae RE |
17528 | { |
17529 | unsigned HOST_WIDE_INT mask = 0xff; | |
17530 | int i; | |
17531 | ||
ce41c38b | 17532 | val = val & (unsigned HOST_WIDE_INT)0xffffffffu; |
d5b7b3ae RE |
17533 | if (val == 0) /* XXX */ |
17534 | return 0; | |
f676971a | 17535 | |
d5b7b3ae RE |
17536 | for (i = 0; i < 25; i++) |
17537 | if ((val & (mask << i)) == val) | |
17538 | return 1; | |
17539 | ||
17540 | return 0; | |
17541 | } | |
17542 | ||
825dda42 | 17543 | /* Returns nonzero if the current function contains, |
d5b7b3ae | 17544 | or might contain a far jump. */ |
5848830f PB |
17545 | static int |
17546 | thumb_far_jump_used_p (void) | |
d5b7b3ae RE |
17547 | { |
17548 | rtx insn; | |
17549 | ||
17550 | /* This test is only important for leaf functions. */ | |
5895f793 | 17551 | /* assert (!leaf_function_p ()); */ |
f676971a | 17552 | |
d5b7b3ae RE |
17553 | /* If we have already decided that far jumps may be used, |
17554 | do not bother checking again, and always return true even if | |
17555 | it turns out that they are not being used. Once we have made | |
17556 | the decision that far jumps are present (and that hence the link | |
17557 | register will be pushed onto the stack) we cannot go back on it. */ | |
17558 | if (cfun->machine->far_jump_used) | |
17559 | return 1; | |
17560 | ||
17561 | /* If this function is not being called from the prologue/epilogue | |
17562 | generation code then it must be being called from the | |
17563 | INITIAL_ELIMINATION_OFFSET macro. */ | |
5848830f | 17564 | if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) |
d5b7b3ae RE |
17565 | { |
17566 | /* In this case we know that we are being asked about the elimination | |
17567 | of the arg pointer register. If that register is not being used, | |
17568 | then there are no arguments on the stack, and we do not have to | |
17569 | worry that a far jump might force the prologue to push the link | |
17570 | register, changing the stack offsets. In this case we can just | |
17571 | return false, since the presence of far jumps in the function will | |
17572 | not affect stack offsets. | |
17573 | ||
17574 | If the arg pointer is live (or if it was live, but has now been | |
17575 | eliminated and so set to dead) then we do have to test to see if | |
17576 | the function might contain a far jump. This test can lead to some | |
17577 | false negatives, since before reload is completed, then length of | |
17578 | branch instructions is not known, so gcc defaults to returning their | |
17579 | longest length, which in turn sets the far jump attribute to true. | |
17580 | ||
17581 | A false negative will not result in bad code being generated, but it | |
17582 | will result in a needless push and pop of the link register. We | |
5848830f PB |
17583 | hope that this does not occur too often. |
17584 | ||
17585 | If we need doubleword stack alignment this could affect the other | |
17586 | elimination offsets so we can't risk getting it wrong. */ | |
6fb5fa3c | 17587 | if (df_regs_ever_live_p (ARG_POINTER_REGNUM)) |
d5b7b3ae | 17588 | cfun->machine->arg_pointer_live = 1; |
5895f793 | 17589 | else if (!cfun->machine->arg_pointer_live) |
d5b7b3ae RE |
17590 | return 0; |
17591 | } | |
17592 | ||
17593 | /* Check to see if the function contains a branch | |
17594 | insn with the far jump attribute set. */ | |
17595 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
17596 | { | |
17597 | if (GET_CODE (insn) == JUMP_INSN | |
17598 | /* Ignore tablejump patterns. */ | |
17599 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
17600 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC | |
17601 | && get_attr_far_jump (insn) == FAR_JUMP_YES | |
17602 | ) | |
17603 | { | |
9a9f7594 | 17604 | /* Record the fact that we have decided that |
d5b7b3ae RE |
17605 | the function does use far jumps. */ |
17606 | cfun->machine->far_jump_used = 1; | |
17607 | return 1; | |
17608 | } | |
17609 | } | |
f676971a | 17610 | |
d5b7b3ae RE |
17611 | return 0; |
17612 | } | |
17613 | ||
825dda42 | 17614 | /* Return nonzero if FUNC must be entered in ARM mode. */ |
d5b7b3ae | 17615 | int |
e32bac5b | 17616 | is_called_in_ARM_mode (tree func) |
d5b7b3ae | 17617 | { |
e6d29d15 | 17618 | gcc_assert (TREE_CODE (func) == FUNCTION_DECL); |
d5b7b3ae | 17619 | |
696e78bf | 17620 | /* Ignore the problem about functions whose address is taken. */ |
d5b7b3ae RE |
17621 | if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) |
17622 | return TRUE; | |
17623 | ||
f676971a | 17624 | #ifdef ARM_PE |
91d231cb | 17625 | return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; |
d5b7b3ae RE |
17626 | #else |
17627 | return FALSE; | |
17628 | #endif | |
17629 | } | |
17630 | ||
d6b4baa4 | 17631 | /* The bits which aren't usefully expanded as rtl. */ |
cd2b33d0 | 17632 | const char * |
e32bac5b | 17633 | thumb_unexpanded_epilogue (void) |
d5b7b3ae | 17634 | { |
954954d1 | 17635 | arm_stack_offsets *offsets; |
d5b7b3ae | 17636 | int regno; |
b279b20a | 17637 | unsigned long live_regs_mask = 0; |
d5b7b3ae | 17638 | int high_regs_pushed = 0; |
d5b7b3ae | 17639 | int had_to_push_lr; |
57934c39 | 17640 | int size; |
d5b7b3ae | 17641 | |
934c2060 | 17642 | if (cfun->machine->return_used_this_function != 0) |
d5b7b3ae RE |
17643 | return ""; |
17644 | ||
58e60158 AN |
17645 | if (IS_NAKED (arm_current_func_type ())) |
17646 | return ""; | |
17647 | ||
954954d1 PB |
17648 | offsets = arm_get_frame_offsets (); |
17649 | live_regs_mask = offsets->saved_regs_mask; | |
57934c39 PB |
17650 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); |
17651 | ||
17652 | /* If we can deduce the registers used from the function's return value. | |
6fb5fa3c | 17653 | This is more reliable that examining df_regs_ever_live_p () because that |
57934c39 PB |
17654 | will be set if the register is ever used in the function, not just if |
17655 | the register is used to hold a return value. */ | |
4f5dfed0 | 17656 | size = arm_size_return_regs (); |
d5b7b3ae RE |
17657 | |
17658 | /* The prolog may have pushed some high registers to use as | |
112cdef5 | 17659 | work registers. e.g. the testsuite file: |
d5b7b3ae RE |
17660 | gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c |
17661 | compiles to produce: | |
17662 | push {r4, r5, r6, r7, lr} | |
17663 | mov r7, r9 | |
17664 | mov r6, r8 | |
17665 | push {r6, r7} | |
17666 | as part of the prolog. We have to undo that pushing here. */ | |
f676971a | 17667 | |
d5b7b3ae RE |
17668 | if (high_regs_pushed) |
17669 | { | |
b279b20a | 17670 | unsigned long mask = live_regs_mask & 0xff; |
d5b7b3ae | 17671 | int next_hi_reg; |
d5b7b3ae | 17672 | |
57934c39 PB |
17673 | /* The available low registers depend on the size of the value we are |
17674 | returning. */ | |
17675 | if (size <= 12) | |
d5b7b3ae | 17676 | mask |= 1 << 3; |
57934c39 PB |
17677 | if (size <= 8) |
17678 | mask |= 1 << 2; | |
d5b7b3ae RE |
17679 | |
17680 | if (mask == 0) | |
17681 | /* Oh dear! We have no low registers into which we can pop | |
17682 | high registers! */ | |
400500c4 RK |
17683 | internal_error |
17684 | ("no low registers available for popping high registers"); | |
f676971a | 17685 | |
d5b7b3ae | 17686 | for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 17687 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
17688 | break; |
17689 | ||
17690 | while (high_regs_pushed) | |
17691 | { | |
17692 | /* Find lo register(s) into which the high register(s) can | |
17693 | be popped. */ | |
17694 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
17695 | { | |
17696 | if (mask & (1 << regno)) | |
17697 | high_regs_pushed--; | |
17698 | if (high_regs_pushed == 0) | |
17699 | break; | |
17700 | } | |
17701 | ||
17702 | mask &= (2 << regno) - 1; /* A noop if regno == 8 */ | |
17703 | ||
d6b4baa4 | 17704 | /* Pop the values into the low register(s). */ |
980e61bb | 17705 | thumb_pushpop (asm_out_file, mask, 0, NULL, mask); |
d5b7b3ae RE |
17706 | |
17707 | /* Move the value(s) into the high registers. */ | |
17708 | for (regno = 0; regno <= LAST_LO_REGNUM; regno++) | |
17709 | { | |
17710 | if (mask & (1 << regno)) | |
17711 | { | |
17712 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, | |
17713 | regno); | |
f676971a | 17714 | |
d5b7b3ae | 17715 | for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) |
57934c39 | 17716 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae RE |
17717 | break; |
17718 | } | |
17719 | } | |
17720 | } | |
57934c39 | 17721 | live_regs_mask &= ~0x0f00; |
d5b7b3ae RE |
17722 | } |
17723 | ||
57934c39 PB |
17724 | had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; |
17725 | live_regs_mask &= 0xff; | |
17726 | ||
38173d38 | 17727 | if (crtl->args.pretend_args_size == 0 || TARGET_BACKTRACE) |
d5b7b3ae | 17728 | { |
f676971a | 17729 | /* Pop the return address into the PC. */ |
57934c39 | 17730 | if (had_to_push_lr) |
d5b7b3ae RE |
17731 | live_regs_mask |= 1 << PC_REGNUM; |
17732 | ||
17733 | /* Either no argument registers were pushed or a backtrace | |
17734 | structure was created which includes an adjusted stack | |
17735 | pointer, so just pop everything. */ | |
17736 | if (live_regs_mask) | |
980e61bb DJ |
17737 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
17738 | live_regs_mask); | |
57934c39 | 17739 | |
d5b7b3ae | 17740 | /* We have either just popped the return address into the |
57934c39 PB |
17741 | PC or it is was kept in LR for the entire function. */ |
17742 | if (!had_to_push_lr) | |
17743 | thumb_exit (asm_out_file, LR_REGNUM); | |
d5b7b3ae RE |
17744 | } |
17745 | else | |
17746 | { | |
17747 | /* Pop everything but the return address. */ | |
d5b7b3ae | 17748 | if (live_regs_mask) |
980e61bb DJ |
17749 | thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, |
17750 | live_regs_mask); | |
d5b7b3ae RE |
17751 | |
17752 | if (had_to_push_lr) | |
57934c39 PB |
17753 | { |
17754 | if (size > 12) | |
17755 | { | |
17756 | /* We have no free low regs, so save one. */ | |
17757 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, | |
17758 | LAST_ARG_REGNUM); | |
17759 | } | |
17760 | ||
17761 | /* Get the return address into a temporary register. */ | |
17762 | thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, | |
17763 | 1 << LAST_ARG_REGNUM); | |
17764 | ||
17765 | if (size > 12) | |
17766 | { | |
17767 | /* Move the return address to lr. */ | |
17768 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, | |
17769 | LAST_ARG_REGNUM); | |
17770 | /* Restore the low register. */ | |
17771 | asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, | |
17772 | IP_REGNUM); | |
17773 | regno = LR_REGNUM; | |
17774 | } | |
17775 | else | |
17776 | regno = LAST_ARG_REGNUM; | |
17777 | } | |
17778 | else | |
17779 | regno = LR_REGNUM; | |
f676971a | 17780 | |
d5b7b3ae RE |
17781 | /* Remove the argument registers that were pushed onto the stack. */ |
17782 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", | |
17783 | SP_REGNUM, SP_REGNUM, | |
38173d38 | 17784 | crtl->args.pretend_args_size); |
f676971a | 17785 | |
57934c39 | 17786 | thumb_exit (asm_out_file, regno); |
d5b7b3ae RE |
17787 | } |
17788 | ||
17789 | return ""; | |
17790 | } | |
17791 | ||
17792 | /* Functions to save and restore machine-specific function data. */ | |
e2500fed | 17793 | static struct machine_function * |
e32bac5b | 17794 | arm_init_machine_status (void) |
d5b7b3ae | 17795 | { |
e2500fed GK |
17796 | struct machine_function *machine; |
17797 | machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); | |
6d3d9133 | 17798 | |
f676971a | 17799 | #if ARM_FT_UNKNOWN != 0 |
e2500fed | 17800 | machine->func_type = ARM_FT_UNKNOWN; |
6d3d9133 | 17801 | #endif |
e2500fed | 17802 | return machine; |
f7a80099 NC |
17803 | } |
17804 | ||
d5b7b3ae RE |
17805 | /* Return an RTX indicating where the return address to the |
17806 | calling function can be found. */ | |
17807 | rtx | |
e32bac5b | 17808 | arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) |
d5b7b3ae | 17809 | { |
d5b7b3ae RE |
17810 | if (count != 0) |
17811 | return NULL_RTX; | |
17812 | ||
61f0ccff | 17813 | return get_hard_reg_initial_val (Pmode, LR_REGNUM); |
d5b7b3ae RE |
17814 | } |
17815 | ||
17816 | /* Do anything needed before RTL is emitted for each function. */ | |
17817 | void | |
e32bac5b | 17818 | arm_init_expanders (void) |
d5b7b3ae RE |
17819 | { |
17820 | /* Arrange to initialize and mark the machine per-function status. */ | |
17821 | init_machine_status = arm_init_machine_status; | |
3ac5ea7c RH |
17822 | |
17823 | /* This is to stop the combine pass optimizing away the alignment | |
17824 | adjustment of va_arg. */ | |
17825 | /* ??? It is claimed that this should not be necessary. */ | |
17826 | if (cfun) | |
17827 | mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); | |
d5b7b3ae RE |
17828 | } |
17829 | ||
0977774b | 17830 | |
2591db65 RE |
17831 | /* Like arm_compute_initial_elimination offset. Simpler because there |
17832 | isn't an ABI specified frame pointer for Thumb. Instead, we set it | |
17833 | to point at the base of the local variables after static stack | |
17834 | space for a function has been allocated. */ | |
0977774b | 17835 | |
5848830f PB |
17836 | HOST_WIDE_INT |
17837 | thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) | |
17838 | { | |
17839 | arm_stack_offsets *offsets; | |
0977774b | 17840 | |
5848830f | 17841 | offsets = arm_get_frame_offsets (); |
0977774b | 17842 | |
5848830f | 17843 | switch (from) |
0977774b | 17844 | { |
5848830f PB |
17845 | case ARG_POINTER_REGNUM: |
17846 | switch (to) | |
17847 | { | |
17848 | case STACK_POINTER_REGNUM: | |
17849 | return offsets->outgoing_args - offsets->saved_args; | |
0977774b | 17850 | |
5848830f PB |
17851 | case FRAME_POINTER_REGNUM: |
17852 | return offsets->soft_frame - offsets->saved_args; | |
0977774b | 17853 | |
5848830f PB |
17854 | case ARM_HARD_FRAME_POINTER_REGNUM: |
17855 | return offsets->saved_regs - offsets->saved_args; | |
0977774b | 17856 | |
2591db65 RE |
17857 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
17858 | return offsets->locals_base - offsets->saved_args; | |
17859 | ||
5848830f | 17860 | default: |
e6d29d15 | 17861 | gcc_unreachable (); |
5848830f PB |
17862 | } |
17863 | break; | |
0977774b | 17864 | |
5848830f PB |
17865 | case FRAME_POINTER_REGNUM: |
17866 | switch (to) | |
17867 | { | |
17868 | case STACK_POINTER_REGNUM: | |
17869 | return offsets->outgoing_args - offsets->soft_frame; | |
0977774b | 17870 | |
5848830f PB |
17871 | case ARM_HARD_FRAME_POINTER_REGNUM: |
17872 | return offsets->saved_regs - offsets->soft_frame; | |
0977774b | 17873 | |
2591db65 RE |
17874 | case THUMB_HARD_FRAME_POINTER_REGNUM: |
17875 | return offsets->locals_base - offsets->soft_frame; | |
17876 | ||
5848830f | 17877 | default: |
e6d29d15 | 17878 | gcc_unreachable (); |
5848830f PB |
17879 | } |
17880 | break; | |
0977774b | 17881 | |
5848830f | 17882 | default: |
e6d29d15 | 17883 | gcc_unreachable (); |
5848830f | 17884 | } |
0977774b JT |
17885 | } |
17886 | ||
d5b7b3ae RE |
17887 | /* Generate the rest of a function's prologue. */ |
17888 | void | |
5b3e6663 | 17889 | thumb1_expand_prologue (void) |
d5b7b3ae | 17890 | { |
980e61bb DJ |
17891 | rtx insn, dwarf; |
17892 | ||
5848830f PB |
17893 | HOST_WIDE_INT amount; |
17894 | arm_stack_offsets *offsets; | |
6d3d9133 | 17895 | unsigned long func_type; |
3c7ad43e | 17896 | int regno; |
57934c39 | 17897 | unsigned long live_regs_mask; |
6d3d9133 NC |
17898 | |
17899 | func_type = arm_current_func_type (); | |
f676971a | 17900 | |
d5b7b3ae | 17901 | /* Naked functions don't have prologues. */ |
6d3d9133 | 17902 | if (IS_NAKED (func_type)) |
d5b7b3ae RE |
17903 | return; |
17904 | ||
6d3d9133 NC |
17905 | if (IS_INTERRUPT (func_type)) |
17906 | { | |
c725bd79 | 17907 | error ("interrupt Service Routines cannot be coded in Thumb mode"); |
6d3d9133 NC |
17908 | return; |
17909 | } | |
17910 | ||
954954d1 PB |
17911 | offsets = arm_get_frame_offsets (); |
17912 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a NC |
17913 | /* Load the pic register before setting the frame pointer, |
17914 | so we can use r7 as a temporary work register. */ | |
020a4035 | 17915 | if (flag_pic && arm_pic_register != INVALID_REGNUM) |
e55ef7f4 | 17916 | arm_load_pic_register (live_regs_mask); |
876f13b0 | 17917 | |
2591db65 | 17918 | if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) |
a2503645 RS |
17919 | emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), |
17920 | stack_pointer_rtx); | |
d5b7b3ae | 17921 | |
5848830f | 17922 | amount = offsets->outgoing_args - offsets->saved_regs; |
d5b7b3ae RE |
17923 | if (amount) |
17924 | { | |
d5b7b3ae | 17925 | if (amount < 512) |
980e61bb DJ |
17926 | { |
17927 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
17928 | GEN_INT (- amount))); | |
17929 | RTX_FRAME_RELATED_P (insn) = 1; | |
17930 | } | |
d5b7b3ae RE |
17931 | else |
17932 | { | |
d5b7b3ae RE |
17933 | rtx reg; |
17934 | ||
17935 | /* The stack decrement is too big for an immediate value in a single | |
17936 | insn. In theory we could issue multiple subtracts, but after | |
17937 | three of them it becomes more space efficient to place the full | |
17938 | value in the constant pool and load into a register. (Also the | |
17939 | ARM debugger really likes to see only one stack decrement per | |
17940 | function). So instead we look for a scratch register into which | |
17941 | we can load the decrement, and then we subtract this from the | |
17942 | stack pointer. Unfortunately on the thumb the only available | |
17943 | scratch registers are the argument registers, and we cannot use | |
17944 | these as they may hold arguments to the function. Instead we | |
17945 | attempt to locate a call preserved register which is used by this | |
17946 | function. If we can find one, then we know that it will have | |
17947 | been pushed at the start of the prologue and so we can corrupt | |
17948 | it now. */ | |
17949 | for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) | |
35596784 | 17950 | if (live_regs_mask & (1 << regno)) |
d5b7b3ae RE |
17951 | break; |
17952 | ||
35596784 | 17953 | gcc_assert(regno <= LAST_LO_REGNUM); |
d5b7b3ae | 17954 | |
35596784 | 17955 | reg = gen_rtx_REG (SImode, regno); |
d5b7b3ae | 17956 | |
35596784 | 17957 | emit_insn (gen_movsi (reg, GEN_INT (- amount))); |
980e61bb | 17958 | |
35596784 AJ |
17959 | insn = emit_insn (gen_addsi3 (stack_pointer_rtx, |
17960 | stack_pointer_rtx, reg)); | |
17961 | RTX_FRAME_RELATED_P (insn) = 1; | |
17962 | dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
17963 | plus_constant (stack_pointer_rtx, | |
17964 | -amount)); | |
17965 | RTX_FRAME_RELATED_P (dwarf) = 1; | |
bbbbb16a | 17966 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf); |
d5b7b3ae | 17967 | } |
2591db65 RE |
17968 | } |
17969 | ||
17970 | if (frame_pointer_needed) | |
5b3e6663 | 17971 | thumb_set_frame_pointer (offsets); |
f676971a | 17972 | |
74d9c39f DJ |
17973 | /* If we are profiling, make sure no instructions are scheduled before |
17974 | the call to mcount. Similarly if the user has requested no | |
17975 | scheduling in the prolog. Similarly if we want non-call exceptions | |
17976 | using the EABI unwinder, to prevent faulting instructions from being | |
17977 | swapped with a stack adjustment. */ | |
e3b5732b | 17978 | if (crtl->profile || !TARGET_SCHED_PROLOG |
74d9c39f | 17979 | || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) |
d5b7b3ae | 17980 | emit_insn (gen_blockage ()); |
3c7ad43e PB |
17981 | |
17982 | cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); | |
57934c39 PB |
17983 | if (live_regs_mask & 0xff) |
17984 | cfun->machine->lr_save_eliminated = 0; | |
d5b7b3ae RE |
17985 | } |
17986 | ||
57934c39 | 17987 | |
d5b7b3ae | 17988 | void |
5b3e6663 | 17989 | thumb1_expand_epilogue (void) |
d5b7b3ae | 17990 | { |
5848830f PB |
17991 | HOST_WIDE_INT amount; |
17992 | arm_stack_offsets *offsets; | |
defc0463 RE |
17993 | int regno; |
17994 | ||
6d3d9133 NC |
17995 | /* Naked functions don't have prologues. */ |
17996 | if (IS_NAKED (arm_current_func_type ())) | |
d5b7b3ae RE |
17997 | return; |
17998 | ||
5848830f PB |
17999 | offsets = arm_get_frame_offsets (); |
18000 | amount = offsets->outgoing_args - offsets->saved_regs; | |
18001 | ||
d5b7b3ae | 18002 | if (frame_pointer_needed) |
2591db65 RE |
18003 | { |
18004 | emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); | |
18005 | amount = offsets->locals_base - offsets->saved_regs; | |
18006 | } | |
e0b92319 | 18007 | |
a3a531ec | 18008 | gcc_assert (amount >= 0); |
2591db65 | 18009 | if (amount) |
d5b7b3ae | 18010 | { |
d5b7b3ae RE |
18011 | if (amount < 512) |
18012 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, | |
18013 | GEN_INT (amount))); | |
18014 | else | |
18015 | { | |
18016 | /* r3 is always free in the epilogue. */ | |
f1c25d3b | 18017 | rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); |
d5b7b3ae RE |
18018 | |
18019 | emit_insn (gen_movsi (reg, GEN_INT (amount))); | |
18020 | emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); | |
18021 | } | |
18022 | } | |
f676971a | 18023 | |
d5b7b3ae RE |
18024 | /* Emit a USE (stack_pointer_rtx), so that |
18025 | the stack adjustment will not be deleted. */ | |
6bacc7b0 | 18026 | emit_insn (gen_prologue_use (stack_pointer_rtx)); |
d5b7b3ae | 18027 | |
e3b5732b | 18028 | if (crtl->profile || !TARGET_SCHED_PROLOG) |
d5b7b3ae | 18029 | emit_insn (gen_blockage ()); |
defc0463 RE |
18030 | |
18031 | /* Emit a clobber for each insn that will be restored in the epilogue, | |
18032 | so that flow2 will get register lifetimes correct. */ | |
18033 | for (regno = 0; regno < 13; regno++) | |
6fb5fa3c | 18034 | if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) |
c41c1387 | 18035 | emit_clobber (gen_rtx_REG (SImode, regno)); |
defc0463 | 18036 | |
6fb5fa3c | 18037 | if (! df_regs_ever_live_p (LR_REGNUM)) |
c41c1387 | 18038 | emit_use (gen_rtx_REG (SImode, LR_REGNUM)); |
d5b7b3ae RE |
18039 | } |
18040 | ||
08c148a8 | 18041 | static void |
5b3e6663 | 18042 | thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
d5b7b3ae | 18043 | { |
954954d1 | 18044 | arm_stack_offsets *offsets; |
b279b20a NC |
18045 | unsigned long live_regs_mask = 0; |
18046 | unsigned long l_mask; | |
18047 | unsigned high_regs_pushed = 0; | |
980e61bb | 18048 | int cfa_offset = 0; |
d5b7b3ae RE |
18049 | int regno; |
18050 | ||
6d3d9133 | 18051 | if (IS_NAKED (arm_current_func_type ())) |
d5b7b3ae RE |
18052 | return; |
18053 | ||
18054 | if (is_called_in_ARM_mode (current_function_decl)) | |
18055 | { | |
18056 | const char * name; | |
18057 | ||
e6d29d15 NS |
18058 | gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); |
18059 | gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) | |
18060 | == SYMBOL_REF); | |
d5b7b3ae | 18061 | name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); |
f676971a | 18062 | |
d5b7b3ae RE |
18063 | /* Generate code sequence to switch us into Thumb mode. */ |
18064 | /* The .code 32 directive has already been emitted by | |
6d77b53e | 18065 | ASM_DECLARE_FUNCTION_NAME. */ |
d5b7b3ae RE |
18066 | asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); |
18067 | asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); | |
18068 | ||
18069 | /* Generate a label, so that the debugger will notice the | |
18070 | change in instruction sets. This label is also used by | |
18071 | the assembler to bypass the ARM code when this function | |
18072 | is called from a Thumb encoded function elsewhere in the | |
18073 | same file. Hence the definition of STUB_NAME here must | |
d6b4baa4 | 18074 | agree with the definition in gas/config/tc-arm.c. */ |
f676971a | 18075 | |
d5b7b3ae | 18076 | #define STUB_NAME ".real_start_of" |
f676971a | 18077 | |
761c70aa | 18078 | fprintf (f, "\t.code\t16\n"); |
d5b7b3ae RE |
18079 | #ifdef ARM_PE |
18080 | if (arm_dllexport_name_p (name)) | |
e5951263 | 18081 | name = arm_strip_name_encoding (name); |
f676971a | 18082 | #endif |
d5b7b3ae | 18083 | asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); |
761c70aa | 18084 | fprintf (f, "\t.thumb_func\n"); |
d5b7b3ae RE |
18085 | asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); |
18086 | } | |
f676971a | 18087 | |
38173d38 | 18088 | if (crtl->args.pretend_args_size) |
d5b7b3ae | 18089 | { |
617a1b71 PB |
18090 | /* Output unwind directive for the stack adjustment. */ |
18091 | if (ARM_EABI_UNWIND_TABLES) | |
18092 | fprintf (f, "\t.pad #%d\n", | |
38173d38 | 18093 | crtl->args.pretend_args_size); |
617a1b71 | 18094 | |
3cb66fd7 | 18095 | if (cfun->machine->uses_anonymous_args) |
d5b7b3ae RE |
18096 | { |
18097 | int num_pushes; | |
f676971a | 18098 | |
761c70aa | 18099 | fprintf (f, "\tpush\t{"); |
d5b7b3ae | 18100 | |
38173d38 | 18101 | num_pushes = ARM_NUM_INTS (crtl->args.pretend_args_size); |
f676971a | 18102 | |
d5b7b3ae RE |
18103 | for (regno = LAST_ARG_REGNUM + 1 - num_pushes; |
18104 | regno <= LAST_ARG_REGNUM; | |
5895f793 | 18105 | regno++) |
d5b7b3ae RE |
18106 | asm_fprintf (f, "%r%s", regno, |
18107 | regno == LAST_ARG_REGNUM ? "" : ", "); | |
18108 | ||
761c70aa | 18109 | fprintf (f, "}\n"); |
d5b7b3ae RE |
18110 | } |
18111 | else | |
f676971a | 18112 | asm_fprintf (f, "\tsub\t%r, %r, #%d\n", |
d5b7b3ae | 18113 | SP_REGNUM, SP_REGNUM, |
38173d38 | 18114 | crtl->args.pretend_args_size); |
980e61bb DJ |
18115 | |
18116 | /* We don't need to record the stores for unwinding (would it | |
18117 | help the debugger any if we did?), but record the change in | |
18118 | the stack pointer. */ | |
18119 | if (dwarf2out_do_frame ()) | |
18120 | { | |
d342c045 | 18121 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 18122 | |
38173d38 | 18123 | cfa_offset = cfa_offset + crtl->args.pretend_args_size; |
980e61bb DJ |
18124 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); |
18125 | } | |
d5b7b3ae RE |
18126 | } |
18127 | ||
b279b20a | 18128 | /* Get the registers we are going to push. */ |
954954d1 PB |
18129 | offsets = arm_get_frame_offsets (); |
18130 | live_regs_mask = offsets->saved_regs_mask; | |
b279b20a | 18131 | /* Extract a mask of the ones we can give to the Thumb's push instruction. */ |
57934c39 | 18132 | l_mask = live_regs_mask & 0x40ff; |
b279b20a NC |
18133 | /* Then count how many other high registers will need to be pushed. */ |
18134 | high_regs_pushed = bit_count (live_regs_mask & 0x0f00); | |
d5b7b3ae RE |
18135 | |
18136 | if (TARGET_BACKTRACE) | |
18137 | { | |
b279b20a NC |
18138 | unsigned offset; |
18139 | unsigned work_register; | |
f676971a | 18140 | |
d5b7b3ae RE |
18141 | /* We have been asked to create a stack backtrace structure. |
18142 | The code looks like this: | |
f676971a | 18143 | |
d5b7b3ae RE |
18144 | 0 .align 2 |
18145 | 0 func: | |
18146 | 0 sub SP, #16 Reserve space for 4 registers. | |
57934c39 | 18147 | 2 push {R7} Push low registers. |
d5b7b3ae RE |
18148 | 4 add R7, SP, #20 Get the stack pointer before the push. |
18149 | 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). | |
18150 | 8 mov R7, PC Get hold of the start of this code plus 12. | |
18151 | 10 str R7, [SP, #16] Store it. | |
18152 | 12 mov R7, FP Get hold of the current frame pointer. | |
18153 | 14 str R7, [SP, #4] Store it. | |
18154 | 16 mov R7, LR Get hold of the current return address. | |
18155 | 18 str R7, [SP, #12] Store it. | |
18156 | 20 add R7, SP, #16 Point at the start of the backtrace structure. | |
18157 | 22 mov FP, R7 Put this value into the frame pointer. */ | |
18158 | ||
57934c39 | 18159 | work_register = thumb_find_work_register (live_regs_mask); |
f676971a | 18160 | |
617a1b71 PB |
18161 | if (ARM_EABI_UNWIND_TABLES) |
18162 | asm_fprintf (f, "\t.pad #16\n"); | |
18163 | ||
d5b7b3ae RE |
18164 | asm_fprintf |
18165 | (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", | |
18166 | SP_REGNUM, SP_REGNUM); | |
980e61bb DJ |
18167 | |
18168 | if (dwarf2out_do_frame ()) | |
18169 | { | |
d342c045 | 18170 | char *l = dwarf2out_cfi_label (false); |
b279b20a | 18171 | |
980e61bb DJ |
18172 | cfa_offset = cfa_offset + 16; |
18173 | dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); | |
18174 | } | |
18175 | ||
57934c39 PB |
18176 | if (l_mask) |
18177 | { | |
18178 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); | |
1a59548b | 18179 | offset = bit_count (l_mask) * UNITS_PER_WORD; |
57934c39 PB |
18180 | } |
18181 | else | |
18182 | offset = 0; | |
f676971a | 18183 | |
d5b7b3ae | 18184 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, |
38173d38 | 18185 | offset + 16 + crtl->args.pretend_args_size); |
f676971a | 18186 | |
d5b7b3ae RE |
18187 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, |
18188 | offset + 4); | |
18189 | ||
18190 | /* Make sure that the instruction fetching the PC is in the right place | |
18191 | to calculate "start of backtrace creation code + 12". */ | |
57934c39 | 18192 | if (l_mask) |
d5b7b3ae RE |
18193 | { |
18194 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
18195 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
18196 | offset + 12); | |
18197 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
18198 | ARM_HARD_FRAME_POINTER_REGNUM); | |
18199 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
18200 | offset); | |
18201 | } | |
18202 | else | |
18203 | { | |
18204 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, | |
18205 | ARM_HARD_FRAME_POINTER_REGNUM); | |
18206 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
18207 | offset); | |
18208 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); | |
18209 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
18210 | offset + 12); | |
18211 | } | |
f676971a | 18212 | |
d5b7b3ae RE |
18213 | asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); |
18214 | asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, | |
18215 | offset + 8); | |
18216 | asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, | |
18217 | offset + 12); | |
18218 | asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", | |
18219 | ARM_HARD_FRAME_POINTER_REGNUM, work_register); | |
18220 | } | |
0fa2e4df | 18221 | /* Optimization: If we are not pushing any low registers but we are going |
b279b20a NC |
18222 | to push some high registers then delay our first push. This will just |
18223 | be a push of LR and we can combine it with the push of the first high | |
18224 | register. */ | |
18225 | else if ((l_mask & 0xff) != 0 | |
18226 | || (high_regs_pushed == 0 && l_mask)) | |
57934c39 | 18227 | thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); |
d5b7b3ae | 18228 | |
d5b7b3ae RE |
18229 | if (high_regs_pushed) |
18230 | { | |
b279b20a NC |
18231 | unsigned pushable_regs; |
18232 | unsigned next_hi_reg; | |
d5b7b3ae RE |
18233 | |
18234 | for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) | |
57934c39 | 18235 | if (live_regs_mask & (1 << next_hi_reg)) |
e26053d1 | 18236 | break; |
d5b7b3ae | 18237 | |
57934c39 | 18238 | pushable_regs = l_mask & 0xff; |
d5b7b3ae RE |
18239 | |
18240 | if (pushable_regs == 0) | |
57934c39 | 18241 | pushable_regs = 1 << thumb_find_work_register (live_regs_mask); |
d5b7b3ae RE |
18242 | |
18243 | while (high_regs_pushed > 0) | |
18244 | { | |
b279b20a | 18245 | unsigned long real_regs_mask = 0; |
980e61bb | 18246 | |
b279b20a | 18247 | for (regno = LAST_LO_REGNUM; regno >= 0; regno --) |
d5b7b3ae | 18248 | { |
57934c39 | 18249 | if (pushable_regs & (1 << regno)) |
d5b7b3ae RE |
18250 | { |
18251 | asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); | |
f676971a | 18252 | |
b279b20a | 18253 | high_regs_pushed --; |
980e61bb | 18254 | real_regs_mask |= (1 << next_hi_reg); |
f676971a | 18255 | |
d5b7b3ae | 18256 | if (high_regs_pushed) |
aeaf4d25 | 18257 | { |
b279b20a NC |
18258 | for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; |
18259 | next_hi_reg --) | |
57934c39 | 18260 | if (live_regs_mask & (1 << next_hi_reg)) |
d5b7b3ae | 18261 | break; |
aeaf4d25 | 18262 | } |
d5b7b3ae RE |
18263 | else |
18264 | { | |
57934c39 | 18265 | pushable_regs &= ~((1 << regno) - 1); |
d5b7b3ae RE |
18266 | break; |
18267 | } | |
18268 | } | |
18269 | } | |
980e61bb | 18270 | |
b279b20a NC |
18271 | /* If we had to find a work register and we have not yet |
18272 | saved the LR then add it to the list of regs to push. */ | |
18273 | if (l_mask == (1 << LR_REGNUM)) | |
18274 | { | |
18275 | thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), | |
18276 | 1, &cfa_offset, | |
18277 | real_regs_mask | (1 << LR_REGNUM)); | |
18278 | l_mask = 0; | |
18279 | } | |
18280 | else | |
18281 | thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); | |
d5b7b3ae | 18282 | } |
d5b7b3ae RE |
18283 | } |
18284 | } | |
18285 | ||
18286 | /* Handle the case of a double word load into a low register from | |
18287 | a computed memory address. The computed address may involve a | |
18288 | register which is overwritten by the load. */ | |
cd2b33d0 | 18289 | const char * |
e32bac5b | 18290 | thumb_load_double_from_address (rtx *operands) |
d5b7b3ae RE |
18291 | { |
18292 | rtx addr; | |
18293 | rtx base; | |
18294 | rtx offset; | |
18295 | rtx arg1; | |
18296 | rtx arg2; | |
f676971a | 18297 | |
e6d29d15 NS |
18298 | gcc_assert (GET_CODE (operands[0]) == REG); |
18299 | gcc_assert (GET_CODE (operands[1]) == MEM); | |
d5b7b3ae RE |
18300 | |
18301 | /* Get the memory address. */ | |
18302 | addr = XEXP (operands[1], 0); | |
f676971a | 18303 | |
d5b7b3ae RE |
18304 | /* Work out how the memory address is computed. */ |
18305 | switch (GET_CODE (addr)) | |
18306 | { | |
18307 | case REG: | |
31fa16b6 | 18308 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 18309 | |
d5b7b3ae RE |
18310 | if (REGNO (operands[0]) == REGNO (addr)) |
18311 | { | |
18312 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18313 | output_asm_insn ("ldr\t%0, %1", operands); | |
18314 | } | |
18315 | else | |
18316 | { | |
18317 | output_asm_insn ("ldr\t%0, %1", operands); | |
18318 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18319 | } | |
18320 | break; | |
f676971a | 18321 | |
d5b7b3ae RE |
18322 | case CONST: |
18323 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 18324 | operands[2] = adjust_address (operands[1], SImode, 4); |
e0b92319 | 18325 | |
d5b7b3ae RE |
18326 | output_asm_insn ("ldr\t%0, %1", operands); |
18327 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18328 | break; | |
f676971a | 18329 | |
d5b7b3ae RE |
18330 | case PLUS: |
18331 | arg1 = XEXP (addr, 0); | |
18332 | arg2 = XEXP (addr, 1); | |
f676971a | 18333 | |
d5b7b3ae RE |
18334 | if (CONSTANT_P (arg1)) |
18335 | base = arg2, offset = arg1; | |
18336 | else | |
18337 | base = arg1, offset = arg2; | |
f676971a | 18338 | |
e6d29d15 | 18339 | gcc_assert (GET_CODE (base) == REG); |
d5b7b3ae RE |
18340 | |
18341 | /* Catch the case of <address> = <reg> + <reg> */ | |
18342 | if (GET_CODE (offset) == REG) | |
18343 | { | |
18344 | int reg_offset = REGNO (offset); | |
18345 | int reg_base = REGNO (base); | |
18346 | int reg_dest = REGNO (operands[0]); | |
f676971a | 18347 | |
d5b7b3ae RE |
18348 | /* Add the base and offset registers together into the |
18349 | higher destination register. */ | |
18350 | asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", | |
18351 | reg_dest + 1, reg_base, reg_offset); | |
f676971a | 18352 | |
d5b7b3ae RE |
18353 | /* Load the lower destination register from the address in |
18354 | the higher destination register. */ | |
18355 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", | |
18356 | reg_dest, reg_dest + 1); | |
f676971a | 18357 | |
d5b7b3ae RE |
18358 | /* Load the higher destination register from its own address |
18359 | plus 4. */ | |
18360 | asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", | |
18361 | reg_dest + 1, reg_dest + 1); | |
18362 | } | |
18363 | else | |
18364 | { | |
18365 | /* Compute <address> + 4 for the high order load. */ | |
31fa16b6 | 18366 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 18367 | |
d5b7b3ae RE |
18368 | /* If the computed address is held in the low order register |
18369 | then load the high order register first, otherwise always | |
18370 | load the low order register first. */ | |
18371 | if (REGNO (operands[0]) == REGNO (base)) | |
18372 | { | |
18373 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18374 | output_asm_insn ("ldr\t%0, %1", operands); | |
18375 | } | |
18376 | else | |
18377 | { | |
18378 | output_asm_insn ("ldr\t%0, %1", operands); | |
18379 | output_asm_insn ("ldr\t%H0, %2", operands); | |
18380 | } | |
18381 | } | |
18382 | break; | |
18383 | ||
18384 | case LABEL_REF: | |
18385 | /* With no registers to worry about we can just load the value | |
18386 | directly. */ | |
31fa16b6 | 18387 | operands[2] = adjust_address (operands[1], SImode, 4); |
f676971a | 18388 | |
d5b7b3ae RE |
18389 | output_asm_insn ("ldr\t%H0, %2", operands); |
18390 | output_asm_insn ("ldr\t%0, %1", operands); | |
18391 | break; | |
f676971a | 18392 | |
d5b7b3ae | 18393 | default: |
e6d29d15 | 18394 | gcc_unreachable (); |
d5b7b3ae | 18395 | } |
f676971a | 18396 | |
d5b7b3ae RE |
18397 | return ""; |
18398 | } | |
18399 | ||
cd2b33d0 | 18400 | const char * |
e32bac5b | 18401 | thumb_output_move_mem_multiple (int n, rtx *operands) |
d5b7b3ae RE |
18402 | { |
18403 | rtx tmp; | |
18404 | ||
18405 | switch (n) | |
18406 | { | |
18407 | case 2: | |
ca356f3a | 18408 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18409 | { |
ca356f3a RE |
18410 | tmp = operands[4]; |
18411 | operands[4] = operands[5]; | |
18412 | operands[5] = tmp; | |
d5b7b3ae | 18413 | } |
ca356f3a RE |
18414 | output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); |
18415 | output_asm_insn ("stmia\t%0!, {%4, %5}", operands); | |
d5b7b3ae RE |
18416 | break; |
18417 | ||
18418 | case 3: | |
ca356f3a | 18419 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18420 | { |
ca356f3a RE |
18421 | tmp = operands[4]; |
18422 | operands[4] = operands[5]; | |
18423 | operands[5] = tmp; | |
d5b7b3ae | 18424 | } |
ca356f3a | 18425 | if (REGNO (operands[5]) > REGNO (operands[6])) |
d5b7b3ae | 18426 | { |
ca356f3a RE |
18427 | tmp = operands[5]; |
18428 | operands[5] = operands[6]; | |
18429 | operands[6] = tmp; | |
d5b7b3ae | 18430 | } |
ca356f3a | 18431 | if (REGNO (operands[4]) > REGNO (operands[5])) |
d5b7b3ae | 18432 | { |
ca356f3a RE |
18433 | tmp = operands[4]; |
18434 | operands[4] = operands[5]; | |
18435 | operands[5] = tmp; | |
d5b7b3ae | 18436 | } |
f676971a | 18437 | |
ca356f3a RE |
18438 | output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); |
18439 | output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); | |
d5b7b3ae RE |
18440 | break; |
18441 | ||
18442 | default: | |
e6d29d15 | 18443 | gcc_unreachable (); |
d5b7b3ae RE |
18444 | } |
18445 | ||
18446 | return ""; | |
18447 | } | |
18448 | ||
b12a00f1 RE |
18449 | /* Output a call-via instruction for thumb state. */ |
18450 | const char * | |
18451 | thumb_call_via_reg (rtx reg) | |
18452 | { | |
18453 | int regno = REGNO (reg); | |
18454 | rtx *labelp; | |
18455 | ||
57ecec57 | 18456 | gcc_assert (regno < LR_REGNUM); |
b12a00f1 RE |
18457 | |
18458 | /* If we are in the normal text section we can use a single instance | |
18459 | per compilation unit. If we are doing function sections, then we need | |
18460 | an entry per section, since we can't rely on reachability. */ | |
d6b5193b | 18461 | if (in_section == text_section) |
b12a00f1 RE |
18462 | { |
18463 | thumb_call_reg_needed = 1; | |
18464 | ||
18465 | if (thumb_call_via_label[regno] == NULL) | |
18466 | thumb_call_via_label[regno] = gen_label_rtx (); | |
18467 | labelp = thumb_call_via_label + regno; | |
18468 | } | |
18469 | else | |
18470 | { | |
18471 | if (cfun->machine->call_via[regno] == NULL) | |
18472 | cfun->machine->call_via[regno] = gen_label_rtx (); | |
18473 | labelp = cfun->machine->call_via + regno; | |
18474 | } | |
18475 | ||
18476 | output_asm_insn ("bl\t%a0", labelp); | |
18477 | return ""; | |
18478 | } | |
18479 | ||
1d6e90ac | 18480 | /* Routines for generating rtl. */ |
d5b7b3ae | 18481 | void |
70128ad9 | 18482 | thumb_expand_movmemqi (rtx *operands) |
d5b7b3ae RE |
18483 | { |
18484 | rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); | |
18485 | rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); | |
18486 | HOST_WIDE_INT len = INTVAL (operands[2]); | |
18487 | HOST_WIDE_INT offset = 0; | |
18488 | ||
18489 | while (len >= 12) | |
18490 | { | |
ca356f3a | 18491 | emit_insn (gen_movmem12b (out, in, out, in)); |
d5b7b3ae RE |
18492 | len -= 12; |
18493 | } | |
f676971a | 18494 | |
d5b7b3ae RE |
18495 | if (len >= 8) |
18496 | { | |
ca356f3a | 18497 | emit_insn (gen_movmem8b (out, in, out, in)); |
d5b7b3ae RE |
18498 | len -= 8; |
18499 | } | |
f676971a | 18500 | |
d5b7b3ae RE |
18501 | if (len >= 4) |
18502 | { | |
18503 | rtx reg = gen_reg_rtx (SImode); | |
f1c25d3b KH |
18504 | emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); |
18505 | emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); | |
d5b7b3ae RE |
18506 | len -= 4; |
18507 | offset += 4; | |
18508 | } | |
f676971a | 18509 | |
d5b7b3ae RE |
18510 | if (len >= 2) |
18511 | { | |
18512 | rtx reg = gen_reg_rtx (HImode); | |
f676971a | 18513 | emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, |
f1c25d3b KH |
18514 | plus_constant (in, offset)))); |
18515 | emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
18516 | reg)); |
18517 | len -= 2; | |
18518 | offset += 2; | |
18519 | } | |
f676971a | 18520 | |
d5b7b3ae RE |
18521 | if (len) |
18522 | { | |
18523 | rtx reg = gen_reg_rtx (QImode); | |
f1c25d3b KH |
18524 | emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, |
18525 | plus_constant (in, offset)))); | |
18526 | emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), | |
d5b7b3ae RE |
18527 | reg)); |
18528 | } | |
18529 | } | |
18530 | ||
d5b7b3ae | 18531 | void |
e32bac5b | 18532 | thumb_reload_out_hi (rtx *operands) |
d5b7b3ae RE |
18533 | { |
18534 | emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); | |
18535 | } | |
18536 | ||
f676971a | 18537 | /* Handle reading a half-word from memory during reload. */ |
d5b7b3ae | 18538 | void |
e32bac5b | 18539 | thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) |
d5b7b3ae | 18540 | { |
e6d29d15 | 18541 | gcc_unreachable (); |
d5b7b3ae RE |
18542 | } |
18543 | ||
c27ba912 DM |
18544 | /* Return the length of a function name prefix |
18545 | that starts with the character 'c'. */ | |
18546 | static int | |
e32bac5b | 18547 | arm_get_strip_length (int c) |
c27ba912 DM |
18548 | { |
18549 | switch (c) | |
18550 | { | |
18551 | ARM_NAME_ENCODING_LENGTHS | |
f676971a | 18552 | default: return 0; |
c27ba912 DM |
18553 | } |
18554 | } | |
18555 | ||
18556 | /* Return a pointer to a function's name with any | |
18557 | and all prefix encodings stripped from it. */ | |
18558 | const char * | |
e32bac5b | 18559 | arm_strip_name_encoding (const char *name) |
c27ba912 DM |
18560 | { |
18561 | int skip; | |
f676971a | 18562 | |
c27ba912 DM |
18563 | while ((skip = arm_get_strip_length (* name))) |
18564 | name += skip; | |
18565 | ||
18566 | return name; | |
18567 | } | |
18568 | ||
e1944073 KW |
18569 | /* If there is a '*' anywhere in the name's prefix, then |
18570 | emit the stripped name verbatim, otherwise prepend an | |
18571 | underscore if leading underscores are being used. */ | |
e1944073 | 18572 | void |
e32bac5b | 18573 | arm_asm_output_labelref (FILE *stream, const char *name) |
e1944073 KW |
18574 | { |
18575 | int skip; | |
18576 | int verbatim = 0; | |
18577 | ||
18578 | while ((skip = arm_get_strip_length (* name))) | |
18579 | { | |
18580 | verbatim |= (*name == '*'); | |
18581 | name += skip; | |
18582 | } | |
18583 | ||
18584 | if (verbatim) | |
18585 | fputs (name, stream); | |
18586 | else | |
18587 | asm_fprintf (stream, "%U%s", name); | |
18588 | } | |
18589 | ||
6c6aa1af PB |
18590 | static void |
18591 | arm_file_start (void) | |
18592 | { | |
18593 | int val; | |
18594 | ||
5b3e6663 PB |
18595 | if (TARGET_UNIFIED_ASM) |
18596 | asm_fprintf (asm_out_file, "\t.syntax unified\n"); | |
18597 | ||
6c6aa1af PB |
18598 | if (TARGET_BPABI) |
18599 | { | |
18600 | const char *fpu_name; | |
18601 | if (arm_select[0].string) | |
18602 | asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string); | |
18603 | else if (arm_select[1].string) | |
18604 | asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string); | |
18605 | else | |
18606 | asm_fprintf (asm_out_file, "\t.cpu %s\n", | |
18607 | all_cores[arm_default_cpu].name); | |
18608 | ||
18609 | if (TARGET_SOFT_FLOAT) | |
18610 | { | |
18611 | if (TARGET_VFP) | |
18612 | fpu_name = "softvfp"; | |
18613 | else | |
18614 | fpu_name = "softfpa"; | |
18615 | } | |
18616 | else | |
18617 | { | |
f1adb0a9 | 18618 | int set_float_abi_attributes = 0; |
6c6aa1af PB |
18619 | switch (arm_fpu_arch) |
18620 | { | |
18621 | case FPUTYPE_FPA: | |
18622 | fpu_name = "fpa"; | |
18623 | break; | |
18624 | case FPUTYPE_FPA_EMU2: | |
18625 | fpu_name = "fpe2"; | |
18626 | break; | |
18627 | case FPUTYPE_FPA_EMU3: | |
18628 | fpu_name = "fpe3"; | |
18629 | break; | |
18630 | case FPUTYPE_MAVERICK: | |
18631 | fpu_name = "maverick"; | |
18632 | break; | |
18633 | case FPUTYPE_VFP: | |
6c6aa1af | 18634 | fpu_name = "vfp"; |
f1adb0a9 JB |
18635 | set_float_abi_attributes = 1; |
18636 | break; | |
302c3d8e PB |
18637 | case FPUTYPE_VFP3D16: |
18638 | fpu_name = "vfpv3-d16"; | |
18639 | set_float_abi_attributes = 1; | |
18640 | break; | |
f1adb0a9 | 18641 | case FPUTYPE_VFP3: |
302c3d8e | 18642 | fpu_name = "vfpv3"; |
f1adb0a9 | 18643 | set_float_abi_attributes = 1; |
6c6aa1af | 18644 | break; |
88f77cba JB |
18645 | case FPUTYPE_NEON: |
18646 | fpu_name = "neon"; | |
18647 | set_float_abi_attributes = 1; | |
18648 | break; | |
0fd8c3ad SL |
18649 | case FPUTYPE_NEON_FP16: |
18650 | fpu_name = "neon-fp16"; | |
18651 | set_float_abi_attributes = 1; | |
18652 | break; | |
6c6aa1af PB |
18653 | default: |
18654 | abort(); | |
18655 | } | |
f1adb0a9 JB |
18656 | if (set_float_abi_attributes) |
18657 | { | |
18658 | if (TARGET_HARD_FLOAT) | |
18659 | asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n"); | |
18660 | if (TARGET_HARD_FLOAT_ABI) | |
18661 | asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n"); | |
18662 | } | |
6c6aa1af PB |
18663 | } |
18664 | asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name); | |
18665 | ||
18666 | /* Some of these attributes only apply when the corresponding features | |
18667 | are used. However we don't have any easy way of figuring this out. | |
18668 | Conservatively record the setting that would have been used. */ | |
18669 | ||
6c6aa1af PB |
18670 | /* Tag_ABI_FP_rounding. */ |
18671 | if (flag_rounding_math) | |
18672 | asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n"); | |
18673 | if (!flag_unsafe_math_optimizations) | |
18674 | { | |
18675 | /* Tag_ABI_FP_denomal. */ | |
18676 | asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n"); | |
18677 | /* Tag_ABI_FP_exceptions. */ | |
18678 | asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n"); | |
18679 | } | |
18680 | /* Tag_ABI_FP_user_exceptions. */ | |
18681 | if (flag_signaling_nans) | |
18682 | asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n"); | |
18683 | /* Tag_ABI_FP_number_model. */ | |
18684 | asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n", | |
18685 | flag_finite_math_only ? 1 : 3); | |
18686 | ||
18687 | /* Tag_ABI_align8_needed. */ | |
18688 | asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n"); | |
18689 | /* Tag_ABI_align8_preserved. */ | |
18690 | asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n"); | |
18691 | /* Tag_ABI_enum_size. */ | |
18692 | asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n", | |
18693 | flag_short_enums ? 1 : 2); | |
18694 | ||
18695 | /* Tag_ABI_optimization_goals. */ | |
18696 | if (optimize_size) | |
18697 | val = 4; | |
18698 | else if (optimize >= 2) | |
18699 | val = 2; | |
18700 | else if (optimize) | |
18701 | val = 1; | |
18702 | else | |
18703 | val = 6; | |
18704 | asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val); | |
b76c3c4b | 18705 | |
0fd8c3ad SL |
18706 | /* Tag_ABI_FP_16bit_format. */ |
18707 | if (arm_fp16_format) | |
18708 | asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n", | |
18709 | (int)arm_fp16_format); | |
18710 | ||
b76c3c4b PB |
18711 | if (arm_lang_output_object_attributes_hook) |
18712 | arm_lang_output_object_attributes_hook(); | |
6c6aa1af PB |
18713 | } |
18714 | default_file_start(); | |
18715 | } | |
18716 | ||
b12a00f1 RE |
18717 | static void |
18718 | arm_file_end (void) | |
18719 | { | |
18720 | int regno; | |
18721 | ||
978e411f CD |
18722 | if (NEED_INDICATE_EXEC_STACK) |
18723 | /* Add .note.GNU-stack. */ | |
18724 | file_end_indicate_exec_stack (); | |
18725 | ||
b12a00f1 RE |
18726 | if (! thumb_call_reg_needed) |
18727 | return; | |
18728 | ||
d6b5193b | 18729 | switch_to_section (text_section); |
b12a00f1 RE |
18730 | asm_fprintf (asm_out_file, "\t.code 16\n"); |
18731 | ASM_OUTPUT_ALIGN (asm_out_file, 1); | |
18732 | ||
57ecec57 | 18733 | for (regno = 0; regno < LR_REGNUM; regno++) |
b12a00f1 RE |
18734 | { |
18735 | rtx label = thumb_call_via_label[regno]; | |
18736 | ||
18737 | if (label != 0) | |
18738 | { | |
18739 | targetm.asm_out.internal_label (asm_out_file, "L", | |
18740 | CODE_LABEL_NUMBER (label)); | |
18741 | asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); | |
18742 | } | |
18743 | } | |
18744 | } | |
18745 | ||
fb49053f RH |
18746 | #ifndef ARM_PE |
18747 | /* Symbols in the text segment can be accessed without indirecting via the | |
18748 | constant pool; it may take an extra binary operation, but this is still | |
18749 | faster than indirecting via memory. Don't do this when not optimizing, | |
18750 | since we won't be calculating al of the offsets necessary to do this | |
18751 | simplification. */ | |
18752 | ||
18753 | static void | |
e32bac5b | 18754 | arm_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 18755 | { |
3521b33c | 18756 | if (optimize > 0 && TREE_CONSTANT (decl)) |
c6a2438a | 18757 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
fb49053f | 18758 | |
d3585b76 | 18759 | default_encode_section_info (decl, rtl, first); |
fb49053f RH |
18760 | } |
18761 | #endif /* !ARM_PE */ | |
483ab821 | 18762 | |
4977bab6 | 18763 | static void |
e32bac5b | 18764 | arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) |
4977bab6 ZW |
18765 | { |
18766 | if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno | |
18767 | && !strcmp (prefix, "L")) | |
18768 | { | |
18769 | arm_ccfsm_state = 0; | |
18770 | arm_target_insn = NULL; | |
18771 | } | |
18772 | default_internal_label (stream, prefix, labelno); | |
18773 | } | |
18774 | ||
c590b625 RH |
18775 | /* Output code to add DELTA to the first argument, and then jump |
18776 | to FUNCTION. Used for C++ multiple inheritance. */ | |
c590b625 | 18777 | static void |
e32bac5b RE |
18778 | arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, |
18779 | HOST_WIDE_INT delta, | |
18780 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
18781 | tree function) | |
483ab821 | 18782 | { |
9b66ebb1 PB |
18783 | static int thunk_label = 0; |
18784 | char label[256]; | |
54b9e939 | 18785 | char labelpc[256]; |
483ab821 MM |
18786 | int mi_delta = delta; |
18787 | const char *const mi_op = mi_delta < 0 ? "sub" : "add"; | |
18788 | int shift = 0; | |
61f71b34 | 18789 | int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) |
483ab821 MM |
18790 | ? 1 : 0); |
18791 | if (mi_delta < 0) | |
18792 | mi_delta = - mi_delta; | |
bf98ec6c | 18793 | |
5b3e6663 | 18794 | if (TARGET_THUMB1) |
9b66ebb1 PB |
18795 | { |
18796 | int labelno = thunk_label++; | |
18797 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); | |
bf98ec6c PB |
18798 | /* Thunks are entered in arm mode when avaiable. */ |
18799 | if (TARGET_THUMB1_ONLY) | |
18800 | { | |
18801 | /* push r3 so we can use it as a temporary. */ | |
18802 | /* TODO: Omit this save if r3 is not used. */ | |
18803 | fputs ("\tpush {r3}\n", file); | |
18804 | fputs ("\tldr\tr3, ", file); | |
18805 | } | |
18806 | else | |
18807 | { | |
18808 | fputs ("\tldr\tr12, ", file); | |
18809 | } | |
9b66ebb1 PB |
18810 | assemble_name (file, label); |
18811 | fputc ('\n', file); | |
54b9e939 KH |
18812 | if (flag_pic) |
18813 | { | |
18814 | /* If we are generating PIC, the ldr instruction below loads | |
18815 | "(target - 7) - .LTHUNKPCn" into r12. The pc reads as | |
18816 | the address of the add + 8, so we have: | |
18817 | ||
18818 | r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) | |
18819 | = target + 1. | |
18820 | ||
18821 | Note that we have "+ 1" because some versions of GNU ld | |
18822 | don't set the low bit of the result for R_ARM_REL32 | |
bf98ec6c PB |
18823 | relocations against thumb function symbols. |
18824 | On ARMv6M this is +4, not +8. */ | |
54b9e939 KH |
18825 | ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); |
18826 | assemble_name (file, labelpc); | |
18827 | fputs (":\n", file); | |
bf98ec6c PB |
18828 | if (TARGET_THUMB1_ONLY) |
18829 | { | |
18830 | /* This is 2 insns after the start of the thunk, so we know it | |
18831 | is 4-byte aligned. */ | |
18832 | fputs ("\tadd\tr3, pc, r3\n", file); | |
18833 | fputs ("\tmov r12, r3\n", file); | |
18834 | } | |
18835 | else | |
18836 | fputs ("\tadd\tr12, pc, r12\n", file); | |
54b9e939 | 18837 | } |
bf98ec6c PB |
18838 | else if (TARGET_THUMB1_ONLY) |
18839 | fputs ("\tmov r12, r3\n", file); | |
9b66ebb1 | 18840 | } |
bf98ec6c | 18841 | if (TARGET_THUMB1_ONLY) |
483ab821 | 18842 | { |
bf98ec6c PB |
18843 | if (mi_delta > 255) |
18844 | { | |
18845 | fputs ("\tldr\tr3, ", file); | |
18846 | assemble_name (file, label); | |
18847 | fputs ("+4\n", file); | |
18848 | asm_fprintf (file, "\t%s\t%r, %r, r3\n", | |
18849 | mi_op, this_regno, this_regno); | |
18850 | } | |
18851 | else if (mi_delta != 0) | |
18852 | { | |
18853 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
18854 | mi_op, this_regno, this_regno, | |
18855 | mi_delta); | |
18856 | } | |
18857 | } | |
18858 | else | |
18859 | { | |
18860 | /* TODO: Use movw/movt for large constants when available. */ | |
18861 | while (mi_delta != 0) | |
18862 | { | |
18863 | if ((mi_delta & (3 << shift)) == 0) | |
18864 | shift += 2; | |
18865 | else | |
18866 | { | |
18867 | asm_fprintf (file, "\t%s\t%r, %r, #%d\n", | |
18868 | mi_op, this_regno, this_regno, | |
18869 | mi_delta & (0xff << shift)); | |
18870 | mi_delta &= ~(0xff << shift); | |
18871 | shift += 8; | |
18872 | } | |
18873 | } | |
483ab821 | 18874 | } |
5b3e6663 | 18875 | if (TARGET_THUMB1) |
9b66ebb1 | 18876 | { |
bf98ec6c PB |
18877 | if (TARGET_THUMB1_ONLY) |
18878 | fputs ("\tpop\t{r3}\n", file); | |
18879 | ||
9b66ebb1 PB |
18880 | fprintf (file, "\tbx\tr12\n"); |
18881 | ASM_OUTPUT_ALIGN (file, 2); | |
18882 | assemble_name (file, label); | |
18883 | fputs (":\n", file); | |
54b9e939 KH |
18884 | if (flag_pic) |
18885 | { | |
18886 | /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ | |
18887 | rtx tem = XEXP (DECL_RTL (function), 0); | |
18888 | tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); | |
18889 | tem = gen_rtx_MINUS (GET_MODE (tem), | |
18890 | tem, | |
18891 | gen_rtx_SYMBOL_REF (Pmode, | |
18892 | ggc_strdup (labelpc))); | |
18893 | assemble_integer (tem, 4, BITS_PER_WORD, 1); | |
18894 | } | |
18895 | else | |
18896 | /* Output ".word .LTHUNKn". */ | |
18897 | assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); | |
bf98ec6c PB |
18898 | |
18899 | if (TARGET_THUMB1_ONLY && mi_delta > 255) | |
18900 | assemble_integer (GEN_INT(mi_delta), 4, BITS_PER_WORD, 1); | |
9b66ebb1 PB |
18901 | } |
18902 | else | |
18903 | { | |
18904 | fputs ("\tb\t", file); | |
18905 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
18906 | if (NEED_PLT_RELOC) | |
18907 | fputs ("(PLT)", file); | |
18908 | fputc ('\n', file); | |
18909 | } | |
483ab821 | 18910 | } |
5a9335ef NC |
18911 | |
18912 | int | |
6f5f2481 | 18913 | arm_emit_vector_const (FILE *file, rtx x) |
5a9335ef NC |
18914 | { |
18915 | int i; | |
18916 | const char * pattern; | |
18917 | ||
e6d29d15 | 18918 | gcc_assert (GET_CODE (x) == CONST_VECTOR); |
5a9335ef NC |
18919 | |
18920 | switch (GET_MODE (x)) | |
18921 | { | |
18922 | case V2SImode: pattern = "%08x"; break; | |
18923 | case V4HImode: pattern = "%04x"; break; | |
18924 | case V8QImode: pattern = "%02x"; break; | |
e6d29d15 | 18925 | default: gcc_unreachable (); |
5a9335ef NC |
18926 | } |
18927 | ||
18928 | fprintf (file, "0x"); | |
18929 | for (i = CONST_VECTOR_NUNITS (x); i--;) | |
18930 | { | |
18931 | rtx element; | |
18932 | ||
18933 | element = CONST_VECTOR_ELT (x, i); | |
18934 | fprintf (file, pattern, INTVAL (element)); | |
18935 | } | |
18936 | ||
18937 | return 1; | |
18938 | } | |
18939 | ||
0fd8c3ad SL |
18940 | /* Emit a fp16 constant appropriately padded to occupy a 4-byte word. |
18941 | HFmode constant pool entries are actually loaded with ldr. */ | |
18942 | void | |
18943 | arm_emit_fp16_const (rtx c) | |
18944 | { | |
18945 | REAL_VALUE_TYPE r; | |
18946 | long bits; | |
18947 | ||
18948 | REAL_VALUE_FROM_CONST_DOUBLE (r, c); | |
18949 | bits = real_to_target (NULL, &r, HFmode); | |
18950 | if (WORDS_BIG_ENDIAN) | |
18951 | assemble_zeros (2); | |
18952 | assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1); | |
18953 | if (!WORDS_BIG_ENDIAN) | |
18954 | assemble_zeros (2); | |
18955 | } | |
18956 | ||
5a9335ef | 18957 | const char * |
6f5f2481 | 18958 | arm_output_load_gr (rtx *operands) |
5a9335ef NC |
18959 | { |
18960 | rtx reg; | |
18961 | rtx offset; | |
18962 | rtx wcgr; | |
18963 | rtx sum; | |
f676971a | 18964 | |
5a9335ef NC |
18965 | if (GET_CODE (operands [1]) != MEM |
18966 | || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS | |
18967 | || GET_CODE (reg = XEXP (sum, 0)) != REG | |
18968 | || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT | |
18969 | || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) | |
18970 | return "wldrw%?\t%0, %1"; | |
f676971a EC |
18971 | |
18972 | /* Fix up an out-of-range load of a GR register. */ | |
5a9335ef NC |
18973 | output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); |
18974 | wcgr = operands[0]; | |
18975 | operands[0] = reg; | |
18976 | output_asm_insn ("ldr%?\t%0, %1", operands); | |
18977 | ||
18978 | operands[0] = wcgr; | |
18979 | operands[1] = reg; | |
18980 | output_asm_insn ("tmcr%?\t%0, %1", operands); | |
18981 | output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); | |
18982 | ||
18983 | return ""; | |
18984 | } | |
f9ba5949 | 18985 | |
1cc9f5f5 KH |
18986 | /* Worker function for TARGET_SETUP_INCOMING_VARARGS. |
18987 | ||
18988 | On the ARM, PRETEND_SIZE is set in order to have the prologue push the last | |
18989 | named arg and all anonymous args onto the stack. | |
18990 | XXX I know the prologue shouldn't be pushing registers, but it is faster | |
18991 | that way. */ | |
18992 | ||
18993 | static void | |
18994 | arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, | |
22ccaaee JJ |
18995 | enum machine_mode mode, |
18996 | tree type, | |
1cc9f5f5 KH |
18997 | int *pretend_size, |
18998 | int second_time ATTRIBUTE_UNUSED) | |
18999 | { | |
22ccaaee JJ |
19000 | int nregs = cum->nregs; |
19001 | if (nregs & 1 | |
19002 | && ARM_DOUBLEWORD_ALIGN | |
19003 | && arm_needs_doubleword_align (mode, type)) | |
19004 | nregs++; | |
19005 | ||
1cc9f5f5 | 19006 | cfun->machine->uses_anonymous_args = 1; |
22ccaaee JJ |
19007 | if (nregs < NUM_ARG_REGS) |
19008 | *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; | |
1cc9f5f5 | 19009 | } |
9b66ebb1 | 19010 | |
59b9a953 | 19011 | /* Return nonzero if the CONSUMER instruction (a store) does not need |
9b66ebb1 PB |
19012 | PRODUCER's value to calculate the address. */ |
19013 | ||
19014 | int | |
19015 | arm_no_early_store_addr_dep (rtx producer, rtx consumer) | |
19016 | { | |
19017 | rtx value = PATTERN (producer); | |
19018 | rtx addr = PATTERN (consumer); | |
19019 | ||
19020 | if (GET_CODE (value) == COND_EXEC) | |
19021 | value = COND_EXEC_CODE (value); | |
19022 | if (GET_CODE (value) == PARALLEL) | |
19023 | value = XVECEXP (value, 0, 0); | |
19024 | value = XEXP (value, 0); | |
19025 | if (GET_CODE (addr) == COND_EXEC) | |
19026 | addr = COND_EXEC_CODE (addr); | |
19027 | if (GET_CODE (addr) == PARALLEL) | |
19028 | addr = XVECEXP (addr, 0, 0); | |
19029 | addr = XEXP (addr, 0); | |
f676971a | 19030 | |
9b66ebb1 PB |
19031 | return !reg_overlap_mentioned_p (value, addr); |
19032 | } | |
19033 | ||
59b9a953 | 19034 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
19035 | have an early register shift value or amount dependency on the |
19036 | result of PRODUCER. */ | |
19037 | ||
19038 | int | |
19039 | arm_no_early_alu_shift_dep (rtx producer, rtx consumer) | |
19040 | { | |
19041 | rtx value = PATTERN (producer); | |
19042 | rtx op = PATTERN (consumer); | |
19043 | rtx early_op; | |
19044 | ||
19045 | if (GET_CODE (value) == COND_EXEC) | |
19046 | value = COND_EXEC_CODE (value); | |
19047 | if (GET_CODE (value) == PARALLEL) | |
19048 | value = XVECEXP (value, 0, 0); | |
19049 | value = XEXP (value, 0); | |
19050 | if (GET_CODE (op) == COND_EXEC) | |
19051 | op = COND_EXEC_CODE (op); | |
19052 | if (GET_CODE (op) == PARALLEL) | |
19053 | op = XVECEXP (op, 0, 0); | |
19054 | op = XEXP (op, 1); | |
f676971a | 19055 | |
9b66ebb1 PB |
19056 | early_op = XEXP (op, 0); |
19057 | /* This is either an actual independent shift, or a shift applied to | |
19058 | the first operand of another operation. We want the whole shift | |
19059 | operation. */ | |
19060 | if (GET_CODE (early_op) == REG) | |
19061 | early_op = op; | |
19062 | ||
19063 | return !reg_overlap_mentioned_p (value, early_op); | |
19064 | } | |
19065 | ||
59b9a953 | 19066 | /* Return nonzero if the CONSUMER instruction (an ALU op) does not |
9b66ebb1 PB |
19067 | have an early register shift value dependency on the result of |
19068 | PRODUCER. */ | |
19069 | ||
19070 | int | |
19071 | arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) | |
19072 | { | |
19073 | rtx value = PATTERN (producer); | |
19074 | rtx op = PATTERN (consumer); | |
19075 | rtx early_op; | |
19076 | ||
19077 | if (GET_CODE (value) == COND_EXEC) | |
19078 | value = COND_EXEC_CODE (value); | |
19079 | if (GET_CODE (value) == PARALLEL) | |
19080 | value = XVECEXP (value, 0, 0); | |
19081 | value = XEXP (value, 0); | |
19082 | if (GET_CODE (op) == COND_EXEC) | |
19083 | op = COND_EXEC_CODE (op); | |
19084 | if (GET_CODE (op) == PARALLEL) | |
19085 | op = XVECEXP (op, 0, 0); | |
19086 | op = XEXP (op, 1); | |
f676971a | 19087 | |
9b66ebb1 PB |
19088 | early_op = XEXP (op, 0); |
19089 | ||
19090 | /* This is either an actual independent shift, or a shift applied to | |
19091 | the first operand of another operation. We want the value being | |
19092 | shifted, in either case. */ | |
19093 | if (GET_CODE (early_op) != REG) | |
19094 | early_op = XEXP (early_op, 0); | |
f676971a | 19095 | |
9b66ebb1 PB |
19096 | return !reg_overlap_mentioned_p (value, early_op); |
19097 | } | |
19098 | ||
59b9a953 | 19099 | /* Return nonzero if the CONSUMER (a mul or mac op) does not |
9b66ebb1 PB |
19100 | have an early register mult dependency on the result of |
19101 | PRODUCER. */ | |
19102 | ||
19103 | int | |
19104 | arm_no_early_mul_dep (rtx producer, rtx consumer) | |
19105 | { | |
19106 | rtx value = PATTERN (producer); | |
19107 | rtx op = PATTERN (consumer); | |
19108 | ||
19109 | if (GET_CODE (value) == COND_EXEC) | |
19110 | value = COND_EXEC_CODE (value); | |
19111 | if (GET_CODE (value) == PARALLEL) | |
19112 | value = XVECEXP (value, 0, 0); | |
19113 | value = XEXP (value, 0); | |
19114 | if (GET_CODE (op) == COND_EXEC) | |
19115 | op = COND_EXEC_CODE (op); | |
19116 | if (GET_CODE (op) == PARALLEL) | |
19117 | op = XVECEXP (op, 0, 0); | |
19118 | op = XEXP (op, 1); | |
f676971a | 19119 | |
756f763b PB |
19120 | if (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) |
19121 | { | |
19122 | if (GET_CODE (XEXP (op, 0)) == MULT) | |
19123 | return !reg_overlap_mentioned_p (value, XEXP (op, 0)); | |
19124 | else | |
19125 | return !reg_overlap_mentioned_p (value, XEXP (op, 1)); | |
19126 | } | |
19127 | ||
19128 | return 0; | |
9b66ebb1 PB |
19129 | } |
19130 | ||
70301b45 PB |
19131 | /* We can't rely on the caller doing the proper promotion when |
19132 | using APCS or ATPCS. */ | |
19133 | ||
19134 | static bool | |
586de218 | 19135 | arm_promote_prototypes (const_tree t ATTRIBUTE_UNUSED) |
70301b45 | 19136 | { |
b6685939 | 19137 | return !TARGET_AAPCS_BASED; |
70301b45 PB |
19138 | } |
19139 | ||
6b045785 PB |
19140 | |
19141 | /* AAPCS based ABIs use short enums by default. */ | |
19142 | ||
19143 | static bool | |
19144 | arm_default_short_enums (void) | |
19145 | { | |
077fc835 | 19146 | return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; |
6b045785 | 19147 | } |
13c1cd82 PB |
19148 | |
19149 | ||
19150 | /* AAPCS requires that anonymous bitfields affect structure alignment. */ | |
19151 | ||
19152 | static bool | |
19153 | arm_align_anon_bitfield (void) | |
19154 | { | |
19155 | return TARGET_AAPCS_BASED; | |
19156 | } | |
4185ae53 PB |
19157 | |
19158 | ||
19159 | /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ | |
19160 | ||
19161 | static tree | |
19162 | arm_cxx_guard_type (void) | |
19163 | { | |
19164 | return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; | |
19165 | } | |
19166 | ||
c956e102 MS |
19167 | /* Return non-zero if the consumer (a multiply-accumulate instruction) |
19168 | has an accumulator dependency on the result of the producer (a | |
19169 | multiplication instruction) and no other dependency on that result. */ | |
19170 | int | |
19171 | arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) | |
19172 | { | |
19173 | rtx mul = PATTERN (producer); | |
19174 | rtx mac = PATTERN (consumer); | |
19175 | rtx mul_result; | |
19176 | rtx mac_op0, mac_op1, mac_acc; | |
19177 | ||
19178 | if (GET_CODE (mul) == COND_EXEC) | |
19179 | mul = COND_EXEC_CODE (mul); | |
19180 | if (GET_CODE (mac) == COND_EXEC) | |
19181 | mac = COND_EXEC_CODE (mac); | |
19182 | ||
19183 | /* Check that mul is of the form (set (...) (mult ...)) | |
19184 | and mla is of the form (set (...) (plus (mult ...) (...))). */ | |
19185 | if ((GET_CODE (mul) != SET || GET_CODE (XEXP (mul, 1)) != MULT) | |
19186 | || (GET_CODE (mac) != SET || GET_CODE (XEXP (mac, 1)) != PLUS | |
19187 | || GET_CODE (XEXP (XEXP (mac, 1), 0)) != MULT)) | |
19188 | return 0; | |
19189 | ||
19190 | mul_result = XEXP (mul, 0); | |
19191 | mac_op0 = XEXP (XEXP (XEXP (mac, 1), 0), 0); | |
19192 | mac_op1 = XEXP (XEXP (XEXP (mac, 1), 0), 1); | |
19193 | mac_acc = XEXP (XEXP (mac, 1), 1); | |
19194 | ||
19195 | return (reg_overlap_mentioned_p (mul_result, mac_acc) | |
19196 | && !reg_overlap_mentioned_p (mul_result, mac_op0) | |
19197 | && !reg_overlap_mentioned_p (mul_result, mac_op1)); | |
19198 | } | |
19199 | ||
4185ae53 | 19200 | |
0fa2e4df | 19201 | /* The EABI says test the least significant bit of a guard variable. */ |
4185ae53 PB |
19202 | |
19203 | static bool | |
19204 | arm_cxx_guard_mask_bit (void) | |
19205 | { | |
19206 | return TARGET_AAPCS_BASED; | |
19207 | } | |
46e995e0 PB |
19208 | |
19209 | ||
19210 | /* The EABI specifies that all array cookies are 8 bytes long. */ | |
19211 | ||
19212 | static tree | |
19213 | arm_get_cookie_size (tree type) | |
19214 | { | |
19215 | tree size; | |
19216 | ||
19217 | if (!TARGET_AAPCS_BASED) | |
19218 | return default_cxx_get_cookie_size (type); | |
19219 | ||
7d60be94 | 19220 | size = build_int_cst (sizetype, 8); |
46e995e0 PB |
19221 | return size; |
19222 | } | |
19223 | ||
19224 | ||
19225 | /* The EABI says that array cookies should also contain the element size. */ | |
19226 | ||
19227 | static bool | |
19228 | arm_cookie_has_size (void) | |
19229 | { | |
19230 | return TARGET_AAPCS_BASED; | |
19231 | } | |
44d10c10 PB |
19232 | |
19233 | ||
19234 | /* The EABI says constructors and destructors should return a pointer to | |
19235 | the object constructed/destroyed. */ | |
19236 | ||
19237 | static bool | |
19238 | arm_cxx_cdtor_returns_this (void) | |
19239 | { | |
19240 | return TARGET_AAPCS_BASED; | |
19241 | } | |
c9ca9b88 | 19242 | |
505970fc MM |
19243 | /* The EABI says that an inline function may never be the key |
19244 | method. */ | |
19245 | ||
19246 | static bool | |
19247 | arm_cxx_key_method_may_be_inline (void) | |
19248 | { | |
19249 | return !TARGET_AAPCS_BASED; | |
19250 | } | |
19251 | ||
1e731102 MM |
19252 | static void |
19253 | arm_cxx_determine_class_data_visibility (tree decl) | |
19254 | { | |
711b2998 JB |
19255 | if (!TARGET_AAPCS_BASED |
19256 | || !TARGET_DLLIMPORT_DECL_ATTRIBUTES) | |
1e731102 | 19257 | return; |
505970fc | 19258 | |
1e731102 MM |
19259 | /* In general, \S 3.2.5.5 of the ARM EABI requires that class data |
19260 | is exported. However, on systems without dynamic vague linkage, | |
19261 | \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ | |
19262 | if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) | |
19263 | DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; | |
19264 | else | |
19265 | DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; | |
19266 | DECL_VISIBILITY_SPECIFIED (decl) = 1; | |
19267 | } | |
e0b92319 | 19268 | |
505970fc | 19269 | static bool |
1e731102 | 19270 | arm_cxx_class_data_always_comdat (void) |
505970fc | 19271 | { |
1e731102 MM |
19272 | /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have |
19273 | vague linkage if the class has no key function. */ | |
19274 | return !TARGET_AAPCS_BASED; | |
505970fc | 19275 | } |
c9ca9b88 | 19276 | |
9f62c3e3 PB |
19277 | |
19278 | /* The EABI says __aeabi_atexit should be used to register static | |
19279 | destructors. */ | |
19280 | ||
19281 | static bool | |
19282 | arm_cxx_use_aeabi_atexit (void) | |
19283 | { | |
19284 | return TARGET_AAPCS_BASED; | |
19285 | } | |
19286 | ||
19287 | ||
c9ca9b88 PB |
19288 | void |
19289 | arm_set_return_address (rtx source, rtx scratch) | |
19290 | { | |
19291 | arm_stack_offsets *offsets; | |
19292 | HOST_WIDE_INT delta; | |
19293 | rtx addr; | |
19294 | unsigned long saved_regs; | |
19295 | ||
954954d1 PB |
19296 | offsets = arm_get_frame_offsets (); |
19297 | saved_regs = offsets->saved_regs_mask; | |
c9ca9b88 PB |
19298 | |
19299 | if ((saved_regs & (1 << LR_REGNUM)) == 0) | |
19300 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
19301 | else | |
19302 | { | |
19303 | if (frame_pointer_needed) | |
19304 | addr = plus_constant(hard_frame_pointer_rtx, -4); | |
19305 | else | |
19306 | { | |
19307 | /* LR will be the first saved register. */ | |
c9ca9b88 PB |
19308 | delta = offsets->outgoing_args - (offsets->frame + 4); |
19309 | ||
f676971a | 19310 | |
c9ca9b88 PB |
19311 | if (delta >= 4096) |
19312 | { | |
19313 | emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, | |
19314 | GEN_INT (delta & ~4095))); | |
19315 | addr = scratch; | |
19316 | delta &= 4095; | |
19317 | } | |
19318 | else | |
19319 | addr = stack_pointer_rtx; | |
19320 | ||
19321 | addr = plus_constant (addr, delta); | |
19322 | } | |
31fa16b6 | 19323 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
19324 | } |
19325 | } | |
19326 | ||
19327 | ||
19328 | void | |
19329 | thumb_set_return_address (rtx source, rtx scratch) | |
19330 | { | |
19331 | arm_stack_offsets *offsets; | |
c9ca9b88 | 19332 | HOST_WIDE_INT delta; |
5b3e6663 | 19333 | HOST_WIDE_INT limit; |
c9ca9b88 PB |
19334 | int reg; |
19335 | rtx addr; | |
57934c39 | 19336 | unsigned long mask; |
c9ca9b88 | 19337 | |
c41c1387 | 19338 | emit_use (source); |
c9ca9b88 | 19339 | |
954954d1 PB |
19340 | offsets = arm_get_frame_offsets (); |
19341 | mask = offsets->saved_regs_mask; | |
57934c39 | 19342 | if (mask & (1 << LR_REGNUM)) |
c9ca9b88 | 19343 | { |
5b3e6663 | 19344 | limit = 1024; |
c9ca9b88 PB |
19345 | /* Find the saved regs. */ |
19346 | if (frame_pointer_needed) | |
19347 | { | |
19348 | delta = offsets->soft_frame - offsets->saved_args; | |
19349 | reg = THUMB_HARD_FRAME_POINTER_REGNUM; | |
5b3e6663 PB |
19350 | if (TARGET_THUMB1) |
19351 | limit = 128; | |
c9ca9b88 PB |
19352 | } |
19353 | else | |
19354 | { | |
19355 | delta = offsets->outgoing_args - offsets->saved_args; | |
19356 | reg = SP_REGNUM; | |
19357 | } | |
19358 | /* Allow for the stack frame. */ | |
5b3e6663 | 19359 | if (TARGET_THUMB1 && TARGET_BACKTRACE) |
c9ca9b88 PB |
19360 | delta -= 16; |
19361 | /* The link register is always the first saved register. */ | |
19362 | delta -= 4; | |
f676971a | 19363 | |
c9ca9b88 PB |
19364 | /* Construct the address. */ |
19365 | addr = gen_rtx_REG (SImode, reg); | |
5b3e6663 | 19366 | if (delta > limit) |
c9ca9b88 PB |
19367 | { |
19368 | emit_insn (gen_movsi (scratch, GEN_INT (delta))); | |
19369 | emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); | |
19370 | addr = scratch; | |
19371 | } | |
19372 | else | |
19373 | addr = plus_constant (addr, delta); | |
19374 | ||
31fa16b6 | 19375 | emit_move_insn (gen_frame_mem (Pmode, addr), source); |
c9ca9b88 PB |
19376 | } |
19377 | else | |
19378 | emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); | |
19379 | } | |
19380 | ||
f676971a EC |
19381 | /* Implements target hook vector_mode_supported_p. */ |
19382 | bool | |
19383 | arm_vector_mode_supported_p (enum machine_mode mode) | |
19384 | { | |
88f77cba JB |
19385 | /* Neon also supports V2SImode, etc. listed in the clause below. */ |
19386 | if (TARGET_NEON && (mode == V2SFmode || mode == V4SImode || mode == V8HImode | |
19387 | || mode == V16QImode || mode == V4SFmode || mode == V2DImode)) | |
19388 | return true; | |
19389 | ||
f676971a EC |
19390 | if ((mode == V2SImode) |
19391 | || (mode == V4HImode) | |
19392 | || (mode == V8QImode)) | |
19393 | return true; | |
19394 | ||
19395 | return false; | |
19396 | } | |
273a2526 RS |
19397 | |
19398 | /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal | |
19399 | ARM insns and therefore guarantee that the shift count is modulo 256. | |
19400 | DImode shifts (those implemented by lib1funcs.asm or by optabs.c) | |
19401 | guarantee no particular behavior for out-of-range counts. */ | |
19402 | ||
19403 | static unsigned HOST_WIDE_INT | |
19404 | arm_shift_truncation_mask (enum machine_mode mode) | |
19405 | { | |
19406 | return mode == SImode ? 255 : 0; | |
19407 | } | |
2fa330b2 PB |
19408 | |
19409 | ||
19410 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
19411 | ||
19412 | unsigned int | |
19413 | arm_dbx_register_number (unsigned int regno) | |
19414 | { | |
19415 | if (regno < 16) | |
19416 | return regno; | |
19417 | ||
19418 | /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards | |
19419 | compatibility. The EABI defines them as registers 96-103. */ | |
19420 | if (IS_FPA_REGNUM (regno)) | |
19421 | return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; | |
19422 | ||
f1adb0a9 | 19423 | /* FIXME: VFPv3 register numbering. */ |
2fa330b2 PB |
19424 | if (IS_VFP_REGNUM (regno)) |
19425 | return 64 + regno - FIRST_VFP_REGNUM; | |
19426 | ||
19427 | if (IS_IWMMXT_GR_REGNUM (regno)) | |
19428 | return 104 + regno - FIRST_IWMMXT_GR_REGNUM; | |
19429 | ||
19430 | if (IS_IWMMXT_REGNUM (regno)) | |
19431 | return 112 + regno - FIRST_IWMMXT_REGNUM; | |
19432 | ||
e6d29d15 | 19433 | gcc_unreachable (); |
2fa330b2 PB |
19434 | } |
19435 | ||
617a1b71 PB |
19436 | |
19437 | #ifdef TARGET_UNWIND_INFO | |
5b3e6663 PB |
19438 | /* Emit unwind directives for a store-multiple instruction or stack pointer |
19439 | push during alignment. | |
19440 | These should only ever be generated by the function prologue code, so | |
19441 | expect them to have a particular form. */ | |
617a1b71 PB |
19442 | |
19443 | static void | |
5b3e6663 | 19444 | arm_unwind_emit_sequence (FILE * asm_out_file, rtx p) |
617a1b71 PB |
19445 | { |
19446 | int i; | |
19447 | HOST_WIDE_INT offset; | |
19448 | HOST_WIDE_INT nregs; | |
19449 | int reg_size; | |
19450 | unsigned reg; | |
19451 | unsigned lastreg; | |
19452 | rtx e; | |
19453 | ||
617a1b71 | 19454 | e = XVECEXP (p, 0, 0); |
5b3e6663 PB |
19455 | if (GET_CODE (e) != SET) |
19456 | abort (); | |
19457 | ||
19458 | /* First insn will adjust the stack pointer. */ | |
617a1b71 PB |
19459 | if (GET_CODE (e) != SET |
19460 | || GET_CODE (XEXP (e, 0)) != REG | |
19461 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
19462 | || GET_CODE (XEXP (e, 1)) != PLUS) | |
19463 | abort (); | |
19464 | ||
19465 | offset = -INTVAL (XEXP (XEXP (e, 1), 1)); | |
19466 | nregs = XVECLEN (p, 0) - 1; | |
19467 | ||
19468 | reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); | |
19469 | if (reg < 16) | |
19470 | { | |
19471 | /* The function prologue may also push pc, but not annotate it as it is | |
569b7f6a | 19472 | never restored. We turn this into a stack pointer adjustment. */ |
617a1b71 PB |
19473 | if (nregs * 4 == offset - 4) |
19474 | { | |
19475 | fprintf (asm_out_file, "\t.pad #4\n"); | |
19476 | offset -= 4; | |
19477 | } | |
19478 | reg_size = 4; | |
8edfc4cc | 19479 | fprintf (asm_out_file, "\t.save {"); |
617a1b71 PB |
19480 | } |
19481 | else if (IS_VFP_REGNUM (reg)) | |
19482 | { | |
617a1b71 | 19483 | reg_size = 8; |
8edfc4cc | 19484 | fprintf (asm_out_file, "\t.vsave {"); |
617a1b71 PB |
19485 | } |
19486 | else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) | |
19487 | { | |
19488 | /* FPA registers are done differently. */ | |
ea40ba9c | 19489 | asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); |
617a1b71 PB |
19490 | return; |
19491 | } | |
19492 | else | |
19493 | /* Unknown register type. */ | |
19494 | abort (); | |
19495 | ||
19496 | /* If the stack increment doesn't match the size of the saved registers, | |
19497 | something has gone horribly wrong. */ | |
19498 | if (offset != nregs * reg_size) | |
19499 | abort (); | |
19500 | ||
617a1b71 PB |
19501 | offset = 0; |
19502 | lastreg = 0; | |
19503 | /* The remaining insns will describe the stores. */ | |
19504 | for (i = 1; i <= nregs; i++) | |
19505 | { | |
19506 | /* Expect (set (mem <addr>) (reg)). | |
19507 | Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ | |
19508 | e = XVECEXP (p, 0, i); | |
19509 | if (GET_CODE (e) != SET | |
19510 | || GET_CODE (XEXP (e, 0)) != MEM | |
19511 | || GET_CODE (XEXP (e, 1)) != REG) | |
19512 | abort (); | |
e0b92319 | 19513 | |
617a1b71 PB |
19514 | reg = REGNO (XEXP (e, 1)); |
19515 | if (reg < lastreg) | |
19516 | abort (); | |
e0b92319 | 19517 | |
617a1b71 PB |
19518 | if (i != 1) |
19519 | fprintf (asm_out_file, ", "); | |
19520 | /* We can't use %r for vfp because we need to use the | |
19521 | double precision register names. */ | |
19522 | if (IS_VFP_REGNUM (reg)) | |
19523 | asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); | |
19524 | else | |
19525 | asm_fprintf (asm_out_file, "%r", reg); | |
19526 | ||
19527 | #ifdef ENABLE_CHECKING | |
19528 | /* Check that the addresses are consecutive. */ | |
19529 | e = XEXP (XEXP (e, 0), 0); | |
19530 | if (GET_CODE (e) == PLUS) | |
19531 | { | |
19532 | offset += reg_size; | |
19533 | if (GET_CODE (XEXP (e, 0)) != REG | |
19534 | || REGNO (XEXP (e, 0)) != SP_REGNUM | |
19535 | || GET_CODE (XEXP (e, 1)) != CONST_INT | |
19536 | || offset != INTVAL (XEXP (e, 1))) | |
19537 | abort (); | |
19538 | } | |
19539 | else if (i != 1 | |
19540 | || GET_CODE (e) != REG | |
19541 | || REGNO (e) != SP_REGNUM) | |
19542 | abort (); | |
19543 | #endif | |
19544 | } | |
19545 | fprintf (asm_out_file, "}\n"); | |
19546 | } | |
19547 | ||
19548 | /* Emit unwind directives for a SET. */ | |
19549 | ||
19550 | static void | |
19551 | arm_unwind_emit_set (FILE * asm_out_file, rtx p) | |
19552 | { | |
19553 | rtx e0; | |
19554 | rtx e1; | |
5b3e6663 | 19555 | unsigned reg; |
617a1b71 PB |
19556 | |
19557 | e0 = XEXP (p, 0); | |
19558 | e1 = XEXP (p, 1); | |
19559 | switch (GET_CODE (e0)) | |
19560 | { | |
19561 | case MEM: | |
19562 | /* Pushing a single register. */ | |
19563 | if (GET_CODE (XEXP (e0, 0)) != PRE_DEC | |
19564 | || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG | |
19565 | || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) | |
19566 | abort (); | |
19567 | ||
19568 | asm_fprintf (asm_out_file, "\t.save "); | |
19569 | if (IS_VFP_REGNUM (REGNO (e1))) | |
19570 | asm_fprintf(asm_out_file, "{d%d}\n", | |
19571 | (REGNO (e1) - FIRST_VFP_REGNUM) / 2); | |
19572 | else | |
19573 | asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); | |
19574 | break; | |
19575 | ||
19576 | case REG: | |
19577 | if (REGNO (e0) == SP_REGNUM) | |
19578 | { | |
19579 | /* A stack increment. */ | |
19580 | if (GET_CODE (e1) != PLUS | |
19581 | || GET_CODE (XEXP (e1, 0)) != REG | |
19582 | || REGNO (XEXP (e1, 0)) != SP_REGNUM | |
19583 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
19584 | abort (); | |
19585 | ||
ea40ba9c | 19586 | asm_fprintf (asm_out_file, "\t.pad #%wd\n", |
617a1b71 PB |
19587 | -INTVAL (XEXP (e1, 1))); |
19588 | } | |
19589 | else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) | |
19590 | { | |
19591 | HOST_WIDE_INT offset; | |
e0b92319 | 19592 | |
617a1b71 PB |
19593 | if (GET_CODE (e1) == PLUS) |
19594 | { | |
19595 | if (GET_CODE (XEXP (e1, 0)) != REG | |
19596 | || GET_CODE (XEXP (e1, 1)) != CONST_INT) | |
19597 | abort (); | |
19598 | reg = REGNO (XEXP (e1, 0)); | |
19599 | offset = INTVAL (XEXP (e1, 1)); | |
ea40ba9c | 19600 | asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", |
617a1b71 PB |
19601 | HARD_FRAME_POINTER_REGNUM, reg, |
19602 | INTVAL (XEXP (e1, 1))); | |
19603 | } | |
19604 | else if (GET_CODE (e1) == REG) | |
19605 | { | |
19606 | reg = REGNO (e1); | |
19607 | asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", | |
19608 | HARD_FRAME_POINTER_REGNUM, reg); | |
19609 | } | |
19610 | else | |
19611 | abort (); | |
19612 | } | |
19613 | else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) | |
19614 | { | |
19615 | /* Move from sp to reg. */ | |
19616 | asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); | |
19617 | } | |
758ed9b2 PB |
19618 | else if (GET_CODE (e1) == PLUS |
19619 | && GET_CODE (XEXP (e1, 0)) == REG | |
19620 | && REGNO (XEXP (e1, 0)) == SP_REGNUM | |
19621 | && GET_CODE (XEXP (e1, 1)) == CONST_INT) | |
19622 | { | |
19623 | /* Set reg to offset from sp. */ | |
19624 | asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", | |
19625 | REGNO (e0), (int)INTVAL(XEXP (e1, 1))); | |
19626 | } | |
5b3e6663 PB |
19627 | else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN) |
19628 | { | |
19629 | /* Stack pointer save before alignment. */ | |
19630 | reg = REGNO (e0); | |
19631 | asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n", | |
19632 | reg + 0x90, reg); | |
19633 | } | |
617a1b71 PB |
19634 | else |
19635 | abort (); | |
19636 | break; | |
19637 | ||
19638 | default: | |
19639 | abort (); | |
19640 | } | |
19641 | } | |
19642 | ||
19643 | ||
19644 | /* Emit unwind directives for the given insn. */ | |
19645 | ||
19646 | static void | |
19647 | arm_unwind_emit (FILE * asm_out_file, rtx insn) | |
19648 | { | |
19649 | rtx pat; | |
19650 | ||
19651 | if (!ARM_EABI_UNWIND_TABLES) | |
19652 | return; | |
19653 | ||
e3b5732b | 19654 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 19655 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 19656 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
19657 | return; |
19658 | ||
617a1b71 PB |
19659 | if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) |
19660 | return; | |
19661 | ||
19662 | pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); | |
19663 | if (pat) | |
19664 | pat = XEXP (pat, 0); | |
19665 | else | |
19666 | pat = PATTERN (insn); | |
19667 | ||
19668 | switch (GET_CODE (pat)) | |
19669 | { | |
19670 | case SET: | |
19671 | arm_unwind_emit_set (asm_out_file, pat); | |
19672 | break; | |
19673 | ||
19674 | case SEQUENCE: | |
19675 | /* Store multiple. */ | |
5b3e6663 | 19676 | arm_unwind_emit_sequence (asm_out_file, pat); |
617a1b71 PB |
19677 | break; |
19678 | ||
19679 | default: | |
19680 | abort(); | |
19681 | } | |
19682 | } | |
19683 | ||
19684 | ||
19685 | /* Output a reference from a function exception table to the type_info | |
19686 | object X. The EABI specifies that the symbol should be relocated by | |
19687 | an R_ARM_TARGET2 relocation. */ | |
19688 | ||
19689 | static bool | |
19690 | arm_output_ttype (rtx x) | |
19691 | { | |
19692 | fputs ("\t.word\t", asm_out_file); | |
19693 | output_addr_const (asm_out_file, x); | |
19694 | /* Use special relocations for symbol references. */ | |
19695 | if (GET_CODE (x) != CONST_INT) | |
19696 | fputs ("(TARGET2)", asm_out_file); | |
19697 | fputc ('\n', asm_out_file); | |
19698 | ||
19699 | return TRUE; | |
19700 | } | |
19701 | #endif /* TARGET_UNWIND_INFO */ | |
19702 | ||
19703 | ||
5b3e6663 PB |
19704 | /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic |
19705 | stack alignment. */ | |
19706 | ||
19707 | static void | |
19708 | arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) | |
19709 | { | |
19710 | rtx unspec = SET_SRC (pattern); | |
19711 | gcc_assert (GET_CODE (unspec) == UNSPEC); | |
19712 | ||
19713 | switch (index) | |
19714 | { | |
19715 | case UNSPEC_STACK_ALIGN: | |
19716 | /* ??? We should set the CFA = (SP & ~7). At this point we haven't | |
19717 | put anything on the stack, so hopefully it won't matter. | |
19718 | CFA = SP will be correct after alignment. */ | |
19719 | dwarf2out_reg_save_reg (label, stack_pointer_rtx, | |
19720 | SET_DEST (pattern)); | |
19721 | break; | |
19722 | default: | |
19723 | gcc_unreachable (); | |
19724 | } | |
19725 | } | |
19726 | ||
19727 | ||
617a1b71 PB |
19728 | /* Output unwind directives for the start/end of a function. */ |
19729 | ||
19730 | void | |
19731 | arm_output_fn_unwind (FILE * f, bool prologue) | |
19732 | { | |
19733 | if (!ARM_EABI_UNWIND_TABLES) | |
19734 | return; | |
19735 | ||
19736 | if (prologue) | |
19737 | fputs ("\t.fnstart\n", f); | |
19738 | else | |
80efdb6a PB |
19739 | { |
19740 | /* If this function will never be unwound, then mark it as such. | |
19741 | The came condition is used in arm_unwind_emit to suppress | |
19742 | the frame annotations. */ | |
e3b5732b | 19743 | if (!(flag_unwind_tables || crtl->uses_eh_lsda) |
80efdb6a | 19744 | && (TREE_NOTHROW (current_function_decl) |
ad516a74 | 19745 | || crtl->all_throwers_are_sibcalls)) |
80efdb6a PB |
19746 | fputs("\t.cantunwind\n", f); |
19747 | ||
19748 | fputs ("\t.fnend\n", f); | |
19749 | } | |
617a1b71 | 19750 | } |
d3585b76 DJ |
19751 | |
19752 | static bool | |
19753 | arm_emit_tls_decoration (FILE *fp, rtx x) | |
19754 | { | |
19755 | enum tls_reloc reloc; | |
19756 | rtx val; | |
19757 | ||
19758 | val = XVECEXP (x, 0, 0); | |
32e8bb8e | 19759 | reloc = (enum tls_reloc) INTVAL (XVECEXP (x, 0, 1)); |
d3585b76 DJ |
19760 | |
19761 | output_addr_const (fp, val); | |
19762 | ||
19763 | switch (reloc) | |
19764 | { | |
19765 | case TLS_GD32: | |
19766 | fputs ("(tlsgd)", fp); | |
19767 | break; | |
19768 | case TLS_LDM32: | |
19769 | fputs ("(tlsldm)", fp); | |
19770 | break; | |
19771 | case TLS_LDO32: | |
19772 | fputs ("(tlsldo)", fp); | |
19773 | break; | |
19774 | case TLS_IE32: | |
19775 | fputs ("(gottpoff)", fp); | |
19776 | break; | |
19777 | case TLS_LE32: | |
19778 | fputs ("(tpoff)", fp); | |
19779 | break; | |
19780 | default: | |
19781 | gcc_unreachable (); | |
19782 | } | |
19783 | ||
19784 | switch (reloc) | |
19785 | { | |
19786 | case TLS_GD32: | |
19787 | case TLS_LDM32: | |
19788 | case TLS_IE32: | |
19789 | fputs (" + (. - ", fp); | |
19790 | output_addr_const (fp, XVECEXP (x, 0, 2)); | |
19791 | fputs (" - ", fp); | |
19792 | output_addr_const (fp, XVECEXP (x, 0, 3)); | |
19793 | fputc (')', fp); | |
19794 | break; | |
19795 | default: | |
19796 | break; | |
19797 | } | |
19798 | ||
19799 | return TRUE; | |
19800 | } | |
19801 | ||
afcc986d JM |
19802 | /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
19803 | ||
19804 | static void | |
19805 | arm_output_dwarf_dtprel (FILE *file, int size, rtx x) | |
19806 | { | |
19807 | gcc_assert (size == 4); | |
19808 | fputs ("\t.word\t", file); | |
19809 | output_addr_const (file, x); | |
19810 | fputs ("(tlsldo)", file); | |
19811 | } | |
19812 | ||
d3585b76 DJ |
19813 | bool |
19814 | arm_output_addr_const_extra (FILE *fp, rtx x) | |
19815 | { | |
19816 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) | |
19817 | return arm_emit_tls_decoration (fp, x); | |
f16fe45f DJ |
19818 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) |
19819 | { | |
19820 | char label[256]; | |
19821 | int labelno = INTVAL (XVECEXP (x, 0, 0)); | |
19822 | ||
19823 | ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); | |
19824 | assemble_name_raw (fp, label); | |
19825 | ||
f9bd1a89 RS |
19826 | return TRUE; |
19827 | } | |
19828 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_GOTSYM_OFF) | |
19829 | { | |
19830 | assemble_name (fp, "_GLOBAL_OFFSET_TABLE_"); | |
19831 | if (GOT_PCREL) | |
19832 | fputs ("+.", fp); | |
19833 | fputs ("-(", fp); | |
19834 | output_addr_const (fp, XVECEXP (x, 0, 0)); | |
19835 | fputc (')', fp); | |
f16fe45f DJ |
19836 | return TRUE; |
19837 | } | |
d3585b76 DJ |
19838 | else if (GET_CODE (x) == CONST_VECTOR) |
19839 | return arm_emit_vector_const (fp, x); | |
19840 | ||
19841 | return FALSE; | |
19842 | } | |
19843 | ||
5b3e6663 PB |
19844 | /* Output assembly for a shift instruction. |
19845 | SET_FLAGS determines how the instruction modifies the condition codes. | |
7a085dce | 19846 | 0 - Do not set condition codes. |
5b3e6663 PB |
19847 | 1 - Set condition codes. |
19848 | 2 - Use smallest instruction. */ | |
19849 | const char * | |
19850 | arm_output_shift(rtx * operands, int set_flags) | |
19851 | { | |
19852 | char pattern[100]; | |
19853 | static const char flag_chars[3] = {'?', '.', '!'}; | |
19854 | const char *shift; | |
19855 | HOST_WIDE_INT val; | |
19856 | char c; | |
19857 | ||
19858 | c = flag_chars[set_flags]; | |
19859 | if (TARGET_UNIFIED_ASM) | |
19860 | { | |
19861 | shift = shift_op(operands[3], &val); | |
19862 | if (shift) | |
19863 | { | |
19864 | if (val != -1) | |
19865 | operands[2] = GEN_INT(val); | |
19866 | sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c); | |
19867 | } | |
19868 | else | |
19869 | sprintf (pattern, "mov%%%c\t%%0, %%1", c); | |
19870 | } | |
19871 | else | |
19872 | sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c); | |
19873 | output_asm_insn (pattern, operands); | |
19874 | return ""; | |
19875 | } | |
19876 | ||
907dd0c7 RE |
19877 | /* Output a Thumb-1 casesi dispatch sequence. */ |
19878 | const char * | |
19879 | thumb1_output_casesi (rtx *operands) | |
19880 | { | |
19881 | rtx diff_vec = PATTERN (next_real_insn (operands[0])); | |
19882 | addr_diff_vec_flags flags; | |
19883 | ||
19884 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
19885 | ||
19886 | flags = ADDR_DIFF_VEC_FLAGS (diff_vec); | |
19887 | ||
19888 | switch (GET_MODE(diff_vec)) | |
19889 | { | |
19890 | case QImode: | |
19891 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
19892 | "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi"); | |
19893 | case HImode: | |
19894 | return (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned ? | |
19895 | "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi"); | |
19896 | case SImode: | |
19897 | return "bl\t%___gnu_thumb1_case_si"; | |
19898 | default: | |
19899 | gcc_unreachable (); | |
19900 | } | |
19901 | } | |
19902 | ||
5b3e6663 PB |
19903 | /* Output a Thumb-2 casesi instruction. */ |
19904 | const char * | |
19905 | thumb2_output_casesi (rtx *operands) | |
19906 | { | |
19907 | rtx diff_vec = PATTERN (next_real_insn (operands[2])); | |
19908 | ||
19909 | gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); | |
19910 | ||
19911 | output_asm_insn ("cmp\t%0, %1", operands); | |
19912 | output_asm_insn ("bhi\t%l3", operands); | |
19913 | switch (GET_MODE(diff_vec)) | |
19914 | { | |
19915 | case QImode: | |
19916 | return "tbb\t[%|pc, %0]"; | |
19917 | case HImode: | |
19918 | return "tbh\t[%|pc, %0, lsl #1]"; | |
19919 | case SImode: | |
19920 | if (flag_pic) | |
19921 | { | |
19922 | output_asm_insn ("adr\t%4, %l2", operands); | |
19923 | output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands); | |
19924 | output_asm_insn ("add\t%4, %4, %5", operands); | |
19925 | return "bx\t%4"; | |
19926 | } | |
19927 | else | |
19928 | { | |
19929 | output_asm_insn ("adr\t%4, %l2", operands); | |
19930 | return "ldr\t%|pc, [%4, %0, lsl #2]"; | |
19931 | } | |
19932 | default: | |
19933 | gcc_unreachable (); | |
19934 | } | |
19935 | } | |
19936 | ||
bd4dc3cd PB |
19937 | /* Most ARM cores are single issue, but some newer ones can dual issue. |
19938 | The scheduler descriptions rely on this being correct. */ | |
19939 | static int | |
19940 | arm_issue_rate (void) | |
19941 | { | |
19942 | switch (arm_tune) | |
19943 | { | |
19944 | case cortexr4: | |
51c69ddb | 19945 | case cortexr4f: |
bd4dc3cd | 19946 | case cortexa8: |
7612f14d | 19947 | case cortexa9: |
bd4dc3cd PB |
19948 | return 2; |
19949 | ||
19950 | default: | |
19951 | return 1; | |
19952 | } | |
19953 | } | |
19954 | ||
608063c3 JB |
19955 | /* A table and a function to perform ARM-specific name mangling for |
19956 | NEON vector types in order to conform to the AAPCS (see "Procedure | |
19957 | Call Standard for the ARM Architecture", Appendix A). To qualify | |
19958 | for emission with the mangled names defined in that document, a | |
19959 | vector type must not only be of the correct mode but also be | |
19960 | composed of NEON vector element types (e.g. __builtin_neon_qi). */ | |
19961 | typedef struct | |
19962 | { | |
19963 | enum machine_mode mode; | |
19964 | const char *element_type_name; | |
19965 | const char *aapcs_name; | |
19966 | } arm_mangle_map_entry; | |
19967 | ||
19968 | static arm_mangle_map_entry arm_mangle_map[] = { | |
19969 | /* 64-bit containerized types. */ | |
19970 | { V8QImode, "__builtin_neon_qi", "15__simd64_int8_t" }, | |
19971 | { V8QImode, "__builtin_neon_uqi", "16__simd64_uint8_t" }, | |
19972 | { V4HImode, "__builtin_neon_hi", "16__simd64_int16_t" }, | |
19973 | { V4HImode, "__builtin_neon_uhi", "17__simd64_uint16_t" }, | |
19974 | { V2SImode, "__builtin_neon_si", "16__simd64_int32_t" }, | |
19975 | { V2SImode, "__builtin_neon_usi", "17__simd64_uint32_t" }, | |
19976 | { V2SFmode, "__builtin_neon_sf", "18__simd64_float32_t" }, | |
19977 | { V8QImode, "__builtin_neon_poly8", "16__simd64_poly8_t" }, | |
19978 | { V4HImode, "__builtin_neon_poly16", "17__simd64_poly16_t" }, | |
19979 | /* 128-bit containerized types. */ | |
19980 | { V16QImode, "__builtin_neon_qi", "16__simd128_int8_t" }, | |
19981 | { V16QImode, "__builtin_neon_uqi", "17__simd128_uint8_t" }, | |
19982 | { V8HImode, "__builtin_neon_hi", "17__simd128_int16_t" }, | |
19983 | { V8HImode, "__builtin_neon_uhi", "18__simd128_uint16_t" }, | |
19984 | { V4SImode, "__builtin_neon_si", "17__simd128_int32_t" }, | |
19985 | { V4SImode, "__builtin_neon_usi", "18__simd128_uint32_t" }, | |
19986 | { V4SFmode, "__builtin_neon_sf", "19__simd128_float32_t" }, | |
19987 | { V16QImode, "__builtin_neon_poly8", "17__simd128_poly8_t" }, | |
19988 | { V8HImode, "__builtin_neon_poly16", "18__simd128_poly16_t" }, | |
19989 | { VOIDmode, NULL, NULL } | |
19990 | }; | |
19991 | ||
19992 | const char * | |
3101faab | 19993 | arm_mangle_type (const_tree type) |
608063c3 JB |
19994 | { |
19995 | arm_mangle_map_entry *pos = arm_mangle_map; | |
19996 | ||
07d8efe3 MM |
19997 | /* The ARM ABI documents (10th October 2008) say that "__va_list" |
19998 | has to be managled as if it is in the "std" namespace. */ | |
19999 | if (TARGET_AAPCS_BASED | |
ae46a823 | 20000 | && lang_hooks.types_compatible_p (CONST_CAST_TREE (type), va_list_type)) |
07d8efe3 MM |
20001 | { |
20002 | static bool warned; | |
20003 | if (!warned && warn_psabi) | |
20004 | { | |
20005 | warned = true; | |
20006 | inform (input_location, | |
20007 | "the mangling of %<va_list%> has changed in GCC 4.4"); | |
20008 | } | |
20009 | return "St9__va_list"; | |
20010 | } | |
20011 | ||
0fd8c3ad SL |
20012 | /* Half-precision float. */ |
20013 | if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16) | |
20014 | return "Dh"; | |
20015 | ||
608063c3 JB |
20016 | if (TREE_CODE (type) != VECTOR_TYPE) |
20017 | return NULL; | |
20018 | ||
20019 | /* Check the mode of the vector type, and the name of the vector | |
20020 | element type, against the table. */ | |
20021 | while (pos->mode != VOIDmode) | |
20022 | { | |
20023 | tree elt_type = TREE_TYPE (type); | |
20024 | ||
20025 | if (pos->mode == TYPE_MODE (type) | |
20026 | && TREE_CODE (TYPE_NAME (elt_type)) == TYPE_DECL | |
20027 | && !strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (elt_type))), | |
20028 | pos->element_type_name)) | |
20029 | return pos->aapcs_name; | |
20030 | ||
20031 | pos++; | |
20032 | } | |
20033 | ||
20034 | /* Use the default mangling for unrecognized (possibly user-defined) | |
20035 | vector types. */ | |
20036 | return NULL; | |
20037 | } | |
20038 | ||
795dc4fc PB |
20039 | /* Order of allocation of core registers for Thumb: this allocation is |
20040 | written over the corresponding initial entries of the array | |
20041 | initialized with REG_ALLOC_ORDER. We allocate all low registers | |
20042 | first. Saving and restoring a low register is usually cheaper than | |
20043 | using a call-clobbered high register. */ | |
20044 | ||
20045 | static const int thumb_core_reg_alloc_order[] = | |
20046 | { | |
20047 | 3, 2, 1, 0, 4, 5, 6, 7, | |
20048 | 14, 12, 8, 9, 10, 11, 13, 15 | |
20049 | }; | |
20050 | ||
20051 | /* Adjust register allocation order when compiling for Thumb. */ | |
20052 | ||
20053 | void | |
20054 | arm_order_regs_for_local_alloc (void) | |
20055 | { | |
20056 | const int arm_reg_alloc_order[] = REG_ALLOC_ORDER; | |
20057 | memcpy(reg_alloc_order, arm_reg_alloc_order, sizeof (reg_alloc_order)); | |
20058 | if (TARGET_THUMB) | |
20059 | memcpy (reg_alloc_order, thumb_core_reg_alloc_order, | |
20060 | sizeof (thumb_core_reg_alloc_order)); | |
20061 | } | |
20062 | ||
f67358da PB |
20063 | /* Set default optimization options. */ |
20064 | void | |
20065 | arm_optimization_options (int level, int size ATTRIBUTE_UNUSED) | |
20066 | { | |
b1bdaf40 ST |
20067 | /* Enable section anchors by default at -O1 or higher. |
20068 | Use 2 to distinguish from an explicit -fsection-anchors | |
20069 | given on the command line. */ | |
20070 | if (level > 0) | |
20071 | flag_section_anchors = 2; | |
f67358da PB |
20072 | } |
20073 | ||
d3585b76 | 20074 | #include "gt-arm.h" |