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1a94ca49 | 1 | /* Definitions of target machine for GNU compiler, for DEC Alpha. |
9ba3994a | 2 | Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. |
1e6c6f11 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1a94ca49 RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
38ead7f3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
1a94ca49 RK |
21 | |
22 | ||
21798cd8 RK |
23 | /* Write out the correct language type definition for the header files. |
24 | Unless we have assembler language, write out the symbols for C. */ | |
1a94ca49 | 25 | #define CPP_SPEC "\ |
21798cd8 | 26 | %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \ |
1a94ca49 | 27 | %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ |
21798cd8 RK |
28 | %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ |
29 | %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ | |
30 | %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \ | |
2bf6230d RK |
31 | %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \ |
32 | %{mieee:-D_IEEE_FP} \ | |
33 | %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT}" | |
1a94ca49 RK |
34 | |
35 | /* Set the spec to use for signed char. The default tests the above macro | |
36 | but DEC's compiler can't handle the conditional in a "constant" | |
37 | operand. */ | |
38 | ||
39 | #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" | |
40 | ||
b890f297 JM |
41 | #define WORD_SWITCH_TAKES_ARG(STR) \ |
42 | (!strcmp (STR, "rpath") || !strcmp (STR, "include") \ | |
43 | || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \ | |
44 | || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \ | |
45 | || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \ | |
46 | || !strcmp (STR, "isystem")) | |
8877eb00 | 47 | |
1a94ca49 RK |
48 | /* Print subsidiary information on the compiler version in use. */ |
49 | #define TARGET_VERSION | |
50 | ||
1a94ca49 RK |
51 | /* Run-time compilation parameters selecting different hardware subsets. */ |
52 | ||
f6f6a13c RK |
53 | /* Which processor to schedule for. The cpu attribute defines a list that |
54 | mirrors this list, so changes to alpha.md must be made at the same time. */ | |
55 | ||
56 | enum processor_type | |
57 | {PROCESSOR_EV4, /* 2106[46]{a,} */ | |
e9a25f70 JL |
58 | PROCESSOR_EV5, /* 21164{a,pc,} */ |
59 | PROCESSOR_EV6}; /* 21264 */ | |
f6f6a13c RK |
60 | |
61 | extern enum processor_type alpha_cpu; | |
62 | ||
2bf6230d RK |
63 | enum alpha_trap_precision |
64 | { | |
65 | ALPHA_TP_PROG, /* No precision (default). */ | |
66 | ALPHA_TP_FUNC, /* Trap contained within originating function. */ | |
67 | ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ | |
68 | }; | |
69 | ||
70 | enum alpha_fp_rounding_mode | |
71 | { | |
72 | ALPHA_FPRM_NORM, /* Normal rounding mode. */ | |
73 | ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ | |
74 | ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ | |
75 | ALPHA_FPRM_DYN /* Dynamic rounding mode. */ | |
76 | }; | |
77 | ||
78 | enum alpha_fp_trap_mode | |
79 | { | |
80 | ALPHA_FPTM_N, /* Normal trap mode. */ | |
81 | ALPHA_FPTM_U, /* Underflow traps enabled. */ | |
82 | ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ | |
83 | ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ | |
84 | }; | |
85 | ||
1a94ca49 RK |
86 | extern int target_flags; |
87 | ||
2bf6230d RK |
88 | extern enum alpha_trap_precision alpha_tp; |
89 | extern enum alpha_fp_rounding_mode alpha_fprm; | |
90 | extern enum alpha_fp_trap_mode alpha_fptm; | |
91 | ||
1a94ca49 RK |
92 | /* This means that floating-point support exists in the target implementation |
93 | of the Alpha architecture. This is usually the default. */ | |
94 | ||
2bf6230d RK |
95 | #define MASK_FP 1 |
96 | #define TARGET_FP (target_flags & MASK_FP) | |
1a94ca49 RK |
97 | |
98 | /* This means that floating-point registers are allowed to be used. Note | |
99 | that Alpha implementations without FP operations are required to | |
100 | provide the FP registers. */ | |
101 | ||
2bf6230d RK |
102 | #define MASK_FPREGS 2 |
103 | #define TARGET_FPREGS (target_flags & MASK_FPREGS) | |
03f8c4cc RK |
104 | |
105 | /* This means that gas is used to process the assembler file. */ | |
106 | ||
107 | #define MASK_GAS 4 | |
108 | #define TARGET_GAS (target_flags & MASK_GAS) | |
1a94ca49 | 109 | |
2bf6230d RK |
110 | /* This means that we should mark procedures as IEEE conformant. */ |
111 | ||
112 | #define MASK_IEEE_CONFORMANT 8 | |
113 | #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) | |
114 | ||
115 | /* This means we should be IEEE-compliant except for inexact. */ | |
116 | ||
117 | #define MASK_IEEE 16 | |
118 | #define TARGET_IEEE (target_flags & MASK_IEEE) | |
119 | ||
120 | /* This means we should be fully IEEE-compliant. */ | |
121 | ||
122 | #define MASK_IEEE_WITH_INEXACT 32 | |
123 | #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) | |
124 | ||
803fee69 RK |
125 | /* This means we must construct all constants rather than emitting |
126 | them as literal data. */ | |
127 | ||
128 | #define MASK_BUILD_CONSTANTS 128 | |
129 | #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) | |
130 | ||
e5958492 RK |
131 | /* This means we handle floating points in VAX F- (float) |
132 | or G- (double) Format. */ | |
133 | ||
134 | #define MASK_FLOAT_VAX 512 | |
135 | #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) | |
136 | ||
e9a25f70 JL |
137 | /* This means that the processor has byte and half word loads and stores |
138 | (the BWX extension). */ | |
025f3281 | 139 | |
e9a25f70 JL |
140 | #define MASK_BWX 1024 |
141 | #define TARGET_BWX (target_flags & MASK_BWX) | |
025f3281 | 142 | |
e9a25f70 JL |
143 | /* This means that the processor has the CIX extension. */ |
144 | #define MASK_CIX 2048 | |
145 | #define TARGET_CIX (target_flags & MASK_CIX) | |
146 | ||
147 | /* This means that the processor has the MAX extension. */ | |
148 | #define MASK_MAX 4096 | |
149 | #define TARGET_MAX (target_flags & MASK_MAX) | |
150 | ||
151 | /* This means that the processor is an EV5, EV56, or PCA56. This is defined | |
152 | only in TARGET_CPU_DEFAULT. */ | |
153 | #define MASK_CPU_EV5 8192 | |
154 | ||
155 | /* Likewise for EV6. */ | |
156 | #define MASK_CPU_EV6 16384 | |
157 | ||
158 | /* This means we support the .arch directive in the assembler. Only | |
159 | defined in TARGET_CPU_DEFAULT. */ | |
160 | #define MASK_SUPPORT_ARCH 32768 | |
161 | #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) | |
8f87939b | 162 | |
9ba3994a RH |
163 | /* These are for target os support and cannot be changed at runtime. */ |
164 | #ifndef TARGET_WINDOWS_NT | |
165 | #define TARGET_WINDOWS_NT 0 | |
166 | #endif | |
167 | #ifndef TARGET_OPEN_VMS | |
168 | #define TARGET_OPEN_VMS 0 | |
169 | #endif | |
170 | ||
171 | #ifndef TARGET_AS_CAN_SUBTRACT_LABELS | |
172 | #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS | |
173 | #endif | |
174 | ||
175 | ||
1a94ca49 RK |
176 | /* Macro to define tables used to set the flags. |
177 | This is a list in braces of pairs in braces, | |
178 | each pair being { "NAME", VALUE } | |
179 | where VALUE is the bits to set or minus the bits to clear. | |
180 | An empty string NAME is used to identify the default VALUE. */ | |
181 | ||
2bf6230d RK |
182 | #define TARGET_SWITCHES \ |
183 | { {"no-soft-float", MASK_FP}, \ | |
184 | {"soft-float", - MASK_FP}, \ | |
185 | {"fp-regs", MASK_FPREGS}, \ | |
186 | {"no-fp-regs", - (MASK_FP|MASK_FPREGS)}, \ | |
187 | {"alpha-as", -MASK_GAS}, \ | |
188 | {"gas", MASK_GAS}, \ | |
189 | {"ieee-conformant", MASK_IEEE_CONFORMANT}, \ | |
c01b5470 RK |
190 | {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT}, \ |
191 | {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \ | |
803fee69 | 192 | {"build-constants", MASK_BUILD_CONSTANTS}, \ |
e5958492 RK |
193 | {"float-vax", MASK_FLOAT_VAX}, \ |
194 | {"float-ieee", -MASK_FLOAT_VAX}, \ | |
e9a25f70 JL |
195 | {"bwx", MASK_BWX}, \ |
196 | {"no-bwx", -MASK_BWX}, \ | |
197 | {"cix", MASK_CIX}, \ | |
198 | {"no-cix", -MASK_CIX}, \ | |
199 | {"max", MASK_MAX}, \ | |
200 | {"no-max", -MASK_MAX}, \ | |
88681624 | 201 | {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} } |
1a94ca49 | 202 | |
c01b5470 | 203 | #define TARGET_DEFAULT MASK_FP|MASK_FPREGS |
1a94ca49 | 204 | |
88681624 ILT |
205 | #ifndef TARGET_CPU_DEFAULT |
206 | #define TARGET_CPU_DEFAULT 0 | |
207 | #endif | |
208 | ||
2bf6230d RK |
209 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
210 | command options that have values. Its definition is an initializer | |
211 | with a subgrouping for each command option. | |
212 | ||
213 | Each subgrouping contains a string constant, that defines the fixed | |
214 | part of the option name, and the address of a variable. The | |
215 | variable, type `char *', is set to the variable part of the given | |
216 | option if the fixed part matches. The actual option name is made | |
217 | by appending `-m' to the specified name. | |
218 | ||
219 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
220 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
221 | will be set to the string `"512"'. | |
222 | ||
223 | extern char *m88k_short_data; | |
224 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
225 | ||
bcbbac26 | 226 | extern char *alpha_cpu_string; /* For -mcpu= */ |
2bf6230d RK |
227 | extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ |
228 | extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ | |
229 | extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ | |
bcbbac26 | 230 | extern char *alpha_mlat_string; /* For -mmemory-latency= */ |
2bf6230d RK |
231 | |
232 | #define TARGET_OPTIONS \ | |
233 | { \ | |
f6f6a13c | 234 | {"cpu=", &alpha_cpu_string}, \ |
2bf6230d RK |
235 | {"fp-rounding-mode=", &alpha_fprm_string}, \ |
236 | {"fp-trap-mode=", &alpha_fptm_string}, \ | |
237 | {"trap-precision=", &alpha_tp_string}, \ | |
bcbbac26 | 238 | {"memory-latency=", &alpha_mlat_string}, \ |
2bf6230d RK |
239 | } |
240 | ||
241 | /* Sometimes certain combinations of command options do not make sense | |
242 | on a particular target machine. You can define a macro | |
243 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
244 | defined, is executed once just after all the command options have | |
245 | been parsed. | |
246 | ||
247 | On the Alpha, it is used to translate target-option strings into | |
248 | numeric values. */ | |
249 | ||
250 | extern void override_options (); | |
251 | #define OVERRIDE_OPTIONS override_options () | |
252 | ||
253 | ||
1a94ca49 RK |
254 | /* Define this macro to change register usage conditional on target flags. |
255 | ||
256 | On the Alpha, we use this to disable the floating-point registers when | |
257 | they don't exist. */ | |
258 | ||
259 | #define CONDITIONAL_REGISTER_USAGE \ | |
260 | if (! TARGET_FPREGS) \ | |
52a69200 | 261 | for (i = 32; i < 63; i++) \ |
1a94ca49 RK |
262 | fixed_regs[i] = call_used_regs[i] = 1; |
263 | ||
4f074454 RK |
264 | /* Show we can debug even without a frame pointer. */ |
265 | #define CAN_DEBUG_WITHOUT_FP | |
1a94ca49 RK |
266 | \f |
267 | /* target machine storage layout */ | |
268 | ||
2700ac93 RS |
269 | /* Define to enable software floating point emulation. */ |
270 | #define REAL_ARITHMETIC | |
271 | ||
861bb6c1 JL |
272 | /* The following #defines are used when compiling the routines in |
273 | libgcc1.c. Since the Alpha calling conventions require single | |
274 | precision floats to be passed in the floating-point registers | |
275 | (rather than in the general registers) we have to build the | |
276 | libgcc1.c routines in such a way that they know the actual types | |
277 | of their formal arguments and the actual types of their return | |
278 | values. Otherwise, gcc will generate calls to the libgcc1.c | |
279 | routines, passing arguments in the floating-point registers, | |
280 | but the libgcc1.c routines will expect their arguments on the | |
281 | stack (where the Alpha calling conventions require structs & | |
282 | unions to be passed). */ | |
283 | ||
284 | #define FLOAT_VALUE_TYPE double | |
285 | #define INTIFY(FLOATVAL) (FLOATVAL) | |
286 | #define FLOATIFY(INTVAL) (INTVAL) | |
287 | #define FLOAT_ARG_TYPE double | |
288 | ||
1a94ca49 RK |
289 | /* Define the size of `int'. The default is the same as the word size. */ |
290 | #define INT_TYPE_SIZE 32 | |
291 | ||
292 | /* Define the size of `long long'. The default is the twice the word size. */ | |
293 | #define LONG_LONG_TYPE_SIZE 64 | |
294 | ||
295 | /* The two floating-point formats we support are S-floating, which is | |
296 | 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' | |
297 | and `long double' are T. */ | |
298 | ||
299 | #define FLOAT_TYPE_SIZE 32 | |
300 | #define DOUBLE_TYPE_SIZE 64 | |
301 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
302 | ||
5258d7ae RK |
303 | #define WCHAR_TYPE "unsigned int" |
304 | #define WCHAR_TYPE_SIZE 32 | |
1a94ca49 | 305 | |
13d39dbc | 306 | /* Define this macro if it is advisable to hold scalars in registers |
1a94ca49 RK |
307 | in a wider mode than that declared by the program. In such cases, |
308 | the value is constrained to be within the bounds of the declared | |
309 | type, but kept valid in the wider mode. The signedness of the | |
310 | extension may differ from that of the type. | |
311 | ||
312 | For Alpha, we always store objects in a full register. 32-bit objects | |
313 | are always sign-extended, but smaller objects retain their signedness. */ | |
314 | ||
315 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
316 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
317 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
318 | { \ | |
319 | if ((MODE) == SImode) \ | |
320 | (UNSIGNEDP) = 0; \ | |
321 | (MODE) = DImode; \ | |
322 | } | |
323 | ||
324 | /* Define this if function arguments should also be promoted using the above | |
325 | procedure. */ | |
326 | ||
327 | #define PROMOTE_FUNCTION_ARGS | |
328 | ||
329 | /* Likewise, if the function return value is promoted. */ | |
330 | ||
331 | #define PROMOTE_FUNCTION_RETURN | |
332 | ||
333 | /* Define this if most significant bit is lowest numbered | |
334 | in instructions that operate on numbered bit-fields. | |
335 | ||
336 | There are no such instructions on the Alpha, but the documentation | |
337 | is little endian. */ | |
338 | #define BITS_BIG_ENDIAN 0 | |
339 | ||
340 | /* Define this if most significant byte of a word is the lowest numbered. | |
341 | This is false on the Alpha. */ | |
342 | #define BYTES_BIG_ENDIAN 0 | |
343 | ||
344 | /* Define this if most significant word of a multiword number is lowest | |
345 | numbered. | |
346 | ||
347 | For Alpha we can decide arbitrarily since there are no machine instructions | |
348 | for them. Might as well be consistent with bytes. */ | |
349 | #define WORDS_BIG_ENDIAN 0 | |
350 | ||
351 | /* number of bits in an addressable storage unit */ | |
352 | #define BITS_PER_UNIT 8 | |
353 | ||
354 | /* Width in bits of a "word", which is the contents of a machine register. | |
355 | Note that this is not necessarily the width of data type `int'; | |
356 | if using 16-bit ints on a 68000, this would still be 32. | |
357 | But on a machine with 16-bit registers, this would be 16. */ | |
358 | #define BITS_PER_WORD 64 | |
359 | ||
360 | /* Width of a word, in units (bytes). */ | |
361 | #define UNITS_PER_WORD 8 | |
362 | ||
363 | /* Width in bits of a pointer. | |
364 | See also the macro `Pmode' defined below. */ | |
365 | #define POINTER_SIZE 64 | |
366 | ||
367 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
368 | #define PARM_BOUNDARY 64 | |
369 | ||
370 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
371 | #define STACK_BOUNDARY 64 | |
372 | ||
373 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
374 | #define FUNCTION_BOUNDARY 64 | |
375 | ||
376 | /* Alignment of field after `int : 0' in a structure. */ | |
377 | #define EMPTY_FIELD_BOUNDARY 64 | |
378 | ||
379 | /* Every structure's size must be a multiple of this. */ | |
380 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
381 | ||
382 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
383 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
384 | ||
65823178 RK |
385 | /* Align loop starts for optimal branching. |
386 | ||
387 | ??? Kludge this and the next macro for the moment by not doing anything if | |
388 | we don't optimize and also if we are writing ECOFF symbols to work around | |
389 | a bug in DEC's assembler. */ | |
6c174fc0 RH |
390 | /* Aligning past 2**3 wastes insn cache lines, and doesn't buy much |
391 | issue-wise on average anyway. */ | |
1a94ca49 | 392 | |
fc470718 R |
393 | #define LOOP_ALIGN(LABEL) \ |
394 | (optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0) | |
1a94ca49 RK |
395 | |
396 | /* This is how to align an instruction for optimal branching. | |
397 | On Alpha we'll get better performance by aligning on a quadword | |
398 | boundary. */ | |
6c174fc0 RH |
399 | /* Aligning past 2**3 wastes insn cache lines, and doesn't buy much |
400 | issue-wise on average anyway. */ | |
130d2d72 | 401 | |
fc470718 R |
402 | #define ALIGN_LABEL_AFTER_BARRIER(FILE) \ |
403 | (optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0) | |
1a94ca49 RK |
404 | |
405 | /* No data type wants to be aligned rounder than this. */ | |
406 | #define BIGGEST_ALIGNMENT 64 | |
407 | ||
d16fe557 RK |
408 | /* For atomic access to objects, must have at least 32-bit alignment |
409 | unless the machine has byte operations. */ | |
e9a25f70 | 410 | #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32) |
d16fe557 | 411 | |
442b1685 RK |
412 | /* Align all constants and variables to at least a word boundary so |
413 | we can pick up pieces of them faster. */ | |
6c174fc0 RH |
414 | /* ??? Only if block-move stuff knows about different source/destination |
415 | alignment. */ | |
416 | #if 0 | |
442b1685 RK |
417 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) |
418 | #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) | |
6c174fc0 | 419 | #endif |
1a94ca49 RK |
420 | |
421 | /* Set this non-zero if move instructions will actually fail to work | |
422 | when given unaligned data. | |
423 | ||
424 | Since we get an error message when we do one, call them invalid. */ | |
425 | ||
426 | #define STRICT_ALIGNMENT 1 | |
427 | ||
428 | /* Set this non-zero if unaligned move instructions are extremely slow. | |
429 | ||
430 | On the Alpha, they trap. */ | |
130d2d72 RK |
431 | |
432 | #define SLOW_UNALIGNED_ACCESS 1 | |
1a94ca49 RK |
433 | \f |
434 | /* Standard register usage. */ | |
435 | ||
436 | /* Number of actual hardware registers. | |
437 | The hardware registers are assigned numbers for the compiler | |
438 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
439 | All registers that the compiler knows about must be given numbers, | |
440 | even those that are not normally considered general registers. | |
441 | ||
442 | We define all 32 integer registers, even though $31 is always zero, | |
443 | and all 32 floating-point registers, even though $f31 is also | |
444 | always zero. We do not bother defining the FP status register and | |
130d2d72 RK |
445 | there are no other registers. |
446 | ||
447 | Since $31 is always zero, we will use register number 31 as the | |
448 | argument pointer. It will never appear in the generated code | |
449 | because we will always be eliminating it in favor of the stack | |
52a69200 RK |
450 | pointer or hardware frame pointer. |
451 | ||
452 | Likewise, we use $f31 for the frame pointer, which will always | |
453 | be eliminated in favor of the hardware frame pointer or the | |
454 | stack pointer. */ | |
1a94ca49 RK |
455 | |
456 | #define FIRST_PSEUDO_REGISTER 64 | |
457 | ||
458 | /* 1 for registers that have pervasive standard uses | |
459 | and are not available for the register allocator. */ | |
460 | ||
461 | #define FIXED_REGISTERS \ | |
462 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
463 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ | |
464 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
465 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
466 | ||
467 | /* 1 for registers not available across function calls. | |
468 | These must include the FIXED_REGISTERS and also any | |
469 | registers that can be used without being saved. | |
470 | The latter must include the registers where values are returned | |
471 | and the register where structure-value addresses are passed. | |
472 | Aside from that, you can include as many other registers as you like. */ | |
473 | #define CALL_USED_REGISTERS \ | |
474 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ | |
475 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ | |
476 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
477 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
478 | ||
479 | /* List the order in which to allocate registers. Each register must be | |
480 | listed once, even those in FIXED_REGISTERS. | |
481 | ||
482 | We allocate in the following order: | |
2c4be73e | 483 | $f10-$f15 (nonsaved floating-point register) |
1a94ca49 RK |
484 | $f22-$f30 (likewise) |
485 | $f21-$f16 (likewise, but input args) | |
486 | $f0 (nonsaved, but return value) | |
2c4be73e | 487 | $f1 (nonsaved, but immediate before saved) |
1a94ca49 RK |
488 | $f2-$f9 (saved floating-point registers) |
489 | $1-$8 (nonsaved integer registers) | |
490 | $22-$25 (likewise) | |
491 | $28 (likewise) | |
492 | $0 (likewise, but return value) | |
493 | $21-$16 (likewise, but input args) | |
0076aa6b | 494 | $27 (procedure value in OSF, nonsaved in NT) |
1a94ca49 RK |
495 | $9-$14 (saved integer registers) |
496 | $26 (return PC) | |
497 | $15 (frame pointer) | |
498 | $29 (global pointer) | |
52a69200 | 499 | $30, $31, $f31 (stack pointer and always zero/ap & fp) */ |
1a94ca49 RK |
500 | |
501 | #define REG_ALLOC_ORDER \ | |
2c4be73e | 502 | {42, 43, 44, 45, 46, 47, \ |
1a94ca49 RK |
503 | 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
504 | 53, 52, 51, 50, 49, 48, \ | |
2c4be73e | 505 | 32, 33, \ |
1a94ca49 RK |
506 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
507 | 1, 2, 3, 4, 5, 6, 7, 8, \ | |
508 | 22, 23, 24, 25, \ | |
509 | 28, \ | |
510 | 0, \ | |
511 | 21, 20, 19, 18, 17, 16, \ | |
512 | 27, \ | |
513 | 9, 10, 11, 12, 13, 14, \ | |
514 | 26, \ | |
515 | 15, \ | |
516 | 29, \ | |
517 | 30, 31, 63 } | |
518 | ||
519 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
520 | to hold something of mode MODE. | |
521 | This is ordinarily the length in words of a value of mode MODE | |
522 | but can be less for certain modes in special long registers. */ | |
523 | ||
524 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
525 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
526 | ||
527 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
528 | On Alpha, the integer registers can hold any mode. The floating-point | |
529 | registers can hold 32-bit and 64-bit integers as well, but not 16-bit | |
530 | or 8-bit values. If we only allowed the larger integers into FP registers, | |
531 | we'd have to say that QImode and SImode aren't tiable, which is a | |
532 | pain. So say all registers can hold everything and see how that works. */ | |
533 | ||
534 | #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 | |
535 | ||
536 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
537 | when one has mode MODE1 and one has mode MODE2. | |
538 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
539 | for any hard reg, then this must be 0 for correct output. */ | |
540 | ||
541 | #define MODES_TIEABLE_P(MODE1, MODE2) 1 | |
542 | ||
543 | /* Specify the registers used for certain standard purposes. | |
544 | The values of these macros are register numbers. */ | |
545 | ||
546 | /* Alpha pc isn't overloaded on a register that the compiler knows about. */ | |
547 | /* #define PC_REGNUM */ | |
548 | ||
549 | /* Register to use for pushing function arguments. */ | |
550 | #define STACK_POINTER_REGNUM 30 | |
551 | ||
552 | /* Base register for access to local variables of the function. */ | |
52a69200 | 553 | #define HARD_FRAME_POINTER_REGNUM 15 |
1a94ca49 RK |
554 | |
555 | /* Value should be nonzero if functions must have frame pointers. | |
556 | Zero means the frame pointer need not be set up (and parms | |
557 | may be accessed via the stack pointer) in functions that seem suitable. | |
558 | This is computed in `reload', in reload1.c. */ | |
559 | #define FRAME_POINTER_REQUIRED 0 | |
560 | ||
561 | /* Base register for access to arguments of the function. */ | |
130d2d72 | 562 | #define ARG_POINTER_REGNUM 31 |
1a94ca49 | 563 | |
52a69200 RK |
564 | /* Base register for access to local variables of function. */ |
565 | #define FRAME_POINTER_REGNUM 63 | |
566 | ||
1a94ca49 RK |
567 | /* Register in which static-chain is passed to a function. |
568 | ||
569 | For the Alpha, this is based on an example; the calling sequence | |
570 | doesn't seem to specify this. */ | |
571 | #define STATIC_CHAIN_REGNUM 1 | |
572 | ||
573 | /* Register in which address to store a structure value | |
574 | arrives in the function. On the Alpha, the address is passed | |
575 | as a hidden argument. */ | |
576 | #define STRUCT_VALUE 0 | |
577 | \f | |
578 | /* Define the classes of registers for register constraints in the | |
579 | machine description. Also define ranges of constants. | |
580 | ||
581 | One of the classes must always be named ALL_REGS and include all hard regs. | |
582 | If there is more than one class, another class must be named NO_REGS | |
583 | and contain no registers. | |
584 | ||
585 | The name GENERAL_REGS must be the name of a class (or an alias for | |
586 | another name such as ALL_REGS). This is the class of registers | |
587 | that is allowed by "g" or "r" in a register constraint. | |
588 | Also, registers outside this class are allocated only when | |
589 | instructions express preferences for them. | |
590 | ||
591 | The classes must be numbered in nondecreasing order; that is, | |
592 | a larger-numbered class must never be contained completely | |
593 | in a smaller-numbered class. | |
594 | ||
595 | For any two classes, it is very desirable that there be another | |
596 | class that represents their union. */ | |
597 | ||
598 | enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, | |
599 | LIM_REG_CLASSES }; | |
600 | ||
601 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
602 | ||
603 | /* Give names of register classes as strings for dump file. */ | |
604 | ||
605 | #define REG_CLASS_NAMES \ | |
606 | {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } | |
607 | ||
608 | /* Define which registers fit in which classes. | |
609 | This is an initializer for a vector of HARD_REG_SET | |
610 | of length N_REG_CLASSES. */ | |
611 | ||
612 | #define REG_CLASS_CONTENTS \ | |
52a69200 | 613 | { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} } |
1a94ca49 RK |
614 | |
615 | /* The same information, inverted: | |
616 | Return the class number of the smallest class containing | |
617 | reg number REGNO. This could be a conditional expression | |
618 | or could index an array. */ | |
619 | ||
52a69200 RK |
620 | #define REGNO_REG_CLASS(REGNO) \ |
621 | ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS) | |
1a94ca49 RK |
622 | |
623 | /* The class value for index registers, and the one for base regs. */ | |
624 | #define INDEX_REG_CLASS NO_REGS | |
625 | #define BASE_REG_CLASS GENERAL_REGS | |
626 | ||
627 | /* Get reg_class from a letter such as appears in the machine description. */ | |
628 | ||
629 | #define REG_CLASS_FROM_LETTER(C) \ | |
630 | ((C) == 'f' ? FLOAT_REGS : NO_REGS) | |
631 | ||
632 | /* Define this macro to change register usage conditional on target flags. */ | |
633 | /* #define CONDITIONAL_REGISTER_USAGE */ | |
634 | ||
635 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
636 | can be used to stand for particular ranges of immediate operands. | |
637 | This macro defines what the ranges are. | |
638 | C is the letter, and VALUE is a constant value. | |
639 | Return 1 if VALUE is in the range specified by C. | |
640 | ||
641 | For Alpha: | |
642 | `I' is used for the range of constants most insns can contain. | |
643 | `J' is the constant zero. | |
644 | `K' is used for the constant in an LDA insn. | |
645 | `L' is used for the constant in a LDAH insn. | |
646 | `M' is used for the constants that can be AND'ed with using a ZAP insn. | |
647 | `N' is used for complemented 8-bit constants. | |
648 | `O' is used for negated 8-bit constants. | |
649 | `P' is used for the constants 1, 2 and 3. */ | |
650 | ||
651 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
652 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \ | |
653 | : (C) == 'J' ? (VALUE) == 0 \ | |
654 | : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
655 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ | |
c905c108 | 656 | && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \ |
1a94ca49 RK |
657 | : (C) == 'M' ? zap_mask (VALUE) \ |
658 | : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \ | |
659 | : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \ | |
660 | : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \ | |
661 | : 0) | |
662 | ||
663 | /* Similar, but for floating or large integer constants, and defining letters | |
664 | G and H. Here VALUE is the CONST_DOUBLE rtx itself. | |
665 | ||
666 | For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE | |
667 | that is the operand of a ZAP insn. */ | |
668 | ||
669 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
670 | ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ | |
671 | && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ | |
672 | : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \ | |
673 | && zap_mask (CONST_DOUBLE_LOW (VALUE)) \ | |
674 | && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \ | |
675 | : 0) | |
676 | ||
e560f226 RK |
677 | /* Optional extra constraints for this machine. |
678 | ||
679 | For the Alpha, `Q' means that this is a memory operand but not a | |
ac030a7b RK |
680 | reference to an unaligned location. |
681 | `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current | |
682 | function. */ | |
e560f226 RK |
683 | |
684 | #define EXTRA_CONSTRAINT(OP, C) \ | |
685 | ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \ | |
ac030a7b | 686 | : (C) == 'R' ? current_file_function_operand (OP, Pmode) \ |
e560f226 RK |
687 | : 0) |
688 | ||
1a94ca49 RK |
689 | /* Given an rtx X being reloaded into a reg required to be |
690 | in class CLASS, return the class of reg to actually use. | |
691 | In general this is just CLASS; but on some machines | |
692 | in some cases it is preferable to use a more restrictive class. | |
693 | ||
694 | On the Alpha, all constants except zero go into a floating-point | |
695 | register via memory. */ | |
696 | ||
697 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
698 | (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \ | |
a6a503ed | 699 | ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\ |
1a94ca49 RK |
700 | : (CLASS)) |
701 | ||
702 | /* Loading and storing HImode or QImode values to and from memory | |
703 | usually requires a scratch register. The exceptions are loading | |
e008606e RK |
704 | QImode and HImode from an aligned address to a general register |
705 | unless byte instructions are permitted. | |
ddd5a7c1 | 706 | We also cannot load an unaligned address or a paradoxical SUBREG into an |
e868b518 | 707 | FP register. */ |
1a94ca49 RK |
708 | |
709 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ | |
710 | (((GET_CODE (IN) == MEM \ | |
711 | || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \ | |
712 | || (GET_CODE (IN) == SUBREG \ | |
713 | && (GET_CODE (SUBREG_REG (IN)) == MEM \ | |
714 | || (GET_CODE (SUBREG_REG (IN)) == REG \ | |
715 | && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \ | |
716 | && (((CLASS) == FLOAT_REGS \ | |
717 | && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \ | |
718 | || (((MODE) == QImode || (MODE) == HImode) \ | |
e9a25f70 | 719 | && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \ |
e560f226 RK |
720 | ? GENERAL_REGS \ |
721 | : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \ | |
722 | && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \ | |
e868b518 RK |
723 | : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \ |
724 | && (GET_MODE_SIZE (GET_MODE (IN)) \ | |
725 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \ | |
e560f226 | 726 | : NO_REGS) |
1a94ca49 RK |
727 | |
728 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ | |
729 | (((GET_CODE (OUT) == MEM \ | |
730 | || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \ | |
731 | || (GET_CODE (OUT) == SUBREG \ | |
732 | && (GET_CODE (SUBREG_REG (OUT)) == MEM \ | |
733 | || (GET_CODE (SUBREG_REG (OUT)) == REG \ | |
734 | && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \ | |
956d6950 JL |
735 | && ((((MODE) == HImode || (MODE) == QImode) \ |
736 | && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \ | |
737 | || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \ | |
e560f226 RK |
738 | ? GENERAL_REGS \ |
739 | : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \ | |
740 | && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \ | |
e868b518 RK |
741 | : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \ |
742 | && (GET_MODE_SIZE (GET_MODE (OUT)) \ | |
743 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \ | |
744 | : NO_REGS) | |
1a94ca49 RK |
745 | |
746 | /* If we are copying between general and FP registers, we need a memory | |
e9a25f70 | 747 | location unless the CIX extension is available. */ |
1a94ca49 | 748 | |
e9a25f70 JL |
749 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
750 | (! TARGET_CIX && (CLASS1) != (CLASS2)) | |
1a94ca49 | 751 | |
acd94aaf RK |
752 | /* Specify the mode to be used for memory when a secondary memory |
753 | location is needed. If MODE is floating-point, use it. Otherwise, | |
754 | widen to a word like the default. This is needed because we always | |
755 | store integers in FP registers in quadword format. This whole | |
756 | area is very tricky! */ | |
757 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
758 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ | |
e868b518 | 759 | : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ |
acd94aaf RK |
760 | : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) |
761 | ||
1a94ca49 RK |
762 | /* Return the maximum number of consecutive registers |
763 | needed to represent mode MODE in a register of class CLASS. */ | |
764 | ||
765 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
766 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
767 | ||
c31dfe4d RK |
768 | /* If defined, gives a class of registers that cannot be used as the |
769 | operand of a SUBREG that changes the size of the object. */ | |
770 | ||
771 | #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS | |
772 | ||
1a94ca49 RK |
773 | /* Define the cost of moving between registers of various classes. Moving |
774 | between FLOAT_REGS and anything else except float regs is expensive. | |
775 | In fact, we make it quite expensive because we really don't want to | |
776 | do these moves unless it is clearly worth it. Optimizations may | |
777 | reduce the impact of not being able to allocate a pseudo to a | |
778 | hard register. */ | |
779 | ||
71d9b493 RH |
780 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
781 | (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ | |
782 | ? 2 \ | |
783 | : TARGET_CIX ? 3 : 4+2*alpha_memory_latency) | |
1a94ca49 RK |
784 | |
785 | /* A C expressions returning the cost of moving data of MODE from a register to | |
786 | or from memory. | |
787 | ||
788 | On the Alpha, bump this up a bit. */ | |
789 | ||
bcbbac26 | 790 | extern int alpha_memory_latency; |
cbd5b9a2 | 791 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) |
1a94ca49 RK |
792 | |
793 | /* Provide the cost of a branch. Exact meaning under development. */ | |
794 | #define BRANCH_COST 5 | |
795 | ||
796 | /* Adjust the cost of dependencies. */ | |
797 | ||
798 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ | |
799 | (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST) | |
800 | \f | |
801 | /* Stack layout; function entry, exit and calling. */ | |
802 | ||
803 | /* Define this if pushing a word on the stack | |
804 | makes the stack pointer a smaller address. */ | |
805 | #define STACK_GROWS_DOWNWARD | |
806 | ||
807 | /* Define this if the nominal address of the stack frame | |
808 | is at the high-address end of the local variables; | |
809 | that is, each additional local variable allocated | |
810 | goes at a more negative offset in the frame. */ | |
130d2d72 | 811 | /* #define FRAME_GROWS_DOWNWARD */ |
1a94ca49 RK |
812 | |
813 | /* Offset within stack frame to start allocating local variables at. | |
814 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
815 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
816 | of the first local allocated. */ | |
817 | ||
52a69200 | 818 | #define STARTING_FRAME_OFFSET 0 |
1a94ca49 RK |
819 | |
820 | /* If we generate an insn to push BYTES bytes, | |
821 | this says how many the stack pointer really advances by. | |
822 | On Alpha, don't define this because there are no push insns. */ | |
823 | /* #define PUSH_ROUNDING(BYTES) */ | |
824 | ||
e008606e RK |
825 | /* Define this to be nonzero if stack checking is built into the ABI. */ |
826 | #define STACK_CHECK_BUILTIN 1 | |
827 | ||
1a94ca49 RK |
828 | /* Define this if the maximum size of all the outgoing args is to be |
829 | accumulated and pushed during the prologue. The amount can be | |
830 | found in the variable current_function_outgoing_args_size. */ | |
831 | #define ACCUMULATE_OUTGOING_ARGS | |
832 | ||
833 | /* Offset of first parameter from the argument pointer register value. */ | |
834 | ||
130d2d72 | 835 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
1a94ca49 RK |
836 | |
837 | /* Definitions for register eliminations. | |
838 | ||
978e8952 | 839 | We have two registers that can be eliminated on the Alpha. First, the |
1a94ca49 | 840 | frame pointer register can often be eliminated in favor of the stack |
130d2d72 RK |
841 | pointer register. Secondly, the argument pointer register can always be |
842 | eliminated; it is replaced with either the stack or frame pointer. */ | |
1a94ca49 RK |
843 | |
844 | /* This is an array of structures. Each structure initializes one pair | |
845 | of eliminable registers. The "from" register number is given first, | |
846 | followed by "to". Eliminations of the same "from" register are listed | |
847 | in order of preference. */ | |
848 | ||
52a69200 RK |
849 | #define ELIMINABLE_REGS \ |
850 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
851 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
852 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
853 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1a94ca49 RK |
854 | |
855 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
856 | Frame pointer elimination is automatically handled. | |
857 | ||
130d2d72 | 858 | All eliminations are valid since the cases where FP can't be |
1a94ca49 RK |
859 | eliminated are already handled. */ |
860 | ||
130d2d72 | 861 | #define CAN_ELIMINATE(FROM, TO) 1 |
1a94ca49 | 862 | |
52a69200 RK |
863 | /* Round up to a multiple of 16 bytes. */ |
864 | #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) | |
865 | ||
1a94ca49 RK |
866 | /* Define the offset between two registers, one to be eliminated, and the other |
867 | its replacement, at the start of a routine. */ | |
868 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
52a69200 RK |
869 | { if ((FROM) == FRAME_POINTER_REGNUM) \ |
870 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
871 | + alpha_sa_size ()); \ | |
872 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
873 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
874 | + alpha_sa_size () \ | |
d772039b RK |
875 | + (ALPHA_ROUND (get_frame_size () \ |
876 | + current_function_pretend_args_size) \ | |
877 | - current_function_pretend_args_size)); \ | |
1a94ca49 RK |
878 | } |
879 | ||
880 | /* Define this if stack space is still allocated for a parameter passed | |
881 | in a register. */ | |
882 | /* #define REG_PARM_STACK_SPACE */ | |
883 | ||
884 | /* Value is the number of bytes of arguments automatically | |
885 | popped when returning from a subroutine call. | |
8b109b37 | 886 | FUNDECL is the declaration node of the function (as a tree), |
1a94ca49 RK |
887 | FUNTYPE is the data type of the function (as a tree), |
888 | or for a library call it is an identifier node for the subroutine name. | |
889 | SIZE is the number of bytes of arguments passed on the stack. */ | |
890 | ||
8b109b37 | 891 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1a94ca49 RK |
892 | |
893 | /* Define how to find the value returned by a function. | |
894 | VALTYPE is the data type of the value (as a tree). | |
895 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
896 | otherwise, FUNC is 0. | |
897 | ||
898 | On Alpha the value is found in $0 for integer functions and | |
899 | $f0 for floating-point functions. */ | |
900 | ||
901 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
e5958492 | 902 | gen_rtx (REG, \ |
956d6950 JL |
903 | ((INTEGRAL_TYPE_P (VALTYPE) \ |
904 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
905 | || POINTER_TYPE_P (VALTYPE)) \ | |
e5958492 RK |
906 | ? word_mode : TYPE_MODE (VALTYPE), \ |
907 | ((TARGET_FPREGS \ | |
908 | && (TREE_CODE (VALTYPE) == REAL_TYPE \ | |
909 | || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ | |
910 | ? 32 : 0)) | |
1a94ca49 RK |
911 | |
912 | /* Define how to find the value returned by a library function | |
913 | assuming the value has mode MODE. */ | |
914 | ||
915 | #define LIBCALL_VALUE(MODE) \ | |
e5958492 RK |
916 | gen_rtx (REG, MODE, \ |
917 | (TARGET_FPREGS \ | |
918 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
919 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
920 | ? 32 : 0)) | |
1a94ca49 | 921 | |
130d2d72 RK |
922 | /* The definition of this macro implies that there are cases where |
923 | a scalar value cannot be returned in registers. | |
924 | ||
925 | For the Alpha, any structure or union type is returned in memory, as | |
926 | are integers whose size is larger than 64 bits. */ | |
927 | ||
928 | #define RETURN_IN_MEMORY(TYPE) \ | |
e14fa9c4 | 929 | (TYPE_MODE (TYPE) == BLKmode \ |
130d2d72 RK |
930 | || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) |
931 | ||
1a94ca49 RK |
932 | /* 1 if N is a possible register number for a function value |
933 | as seen by the caller. */ | |
934 | ||
e5958492 RK |
935 | #define FUNCTION_VALUE_REGNO_P(N) \ |
936 | ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) | |
1a94ca49 RK |
937 | |
938 | /* 1 if N is a possible register number for function argument passing. | |
939 | On Alpha, these are $16-$21 and $f16-$f21. */ | |
940 | ||
941 | #define FUNCTION_ARG_REGNO_P(N) \ | |
942 | (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) | |
943 | \f | |
944 | /* Define a data type for recording info about an argument list | |
945 | during the scan of that argument list. This data type should | |
946 | hold all necessary information about the function itself | |
947 | and about the args processed so far, enough to enable macros | |
948 | such as FUNCTION_ARG to determine where the next arg should go. | |
949 | ||
950 | On Alpha, this is a single integer, which is a number of words | |
951 | of arguments scanned so far. | |
952 | Thus 6 or more means all following args should go on the stack. */ | |
953 | ||
954 | #define CUMULATIVE_ARGS int | |
955 | ||
956 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
957 | for a call to a function whose data type is FNTYPE. | |
958 | For a library call, FNTYPE is 0. */ | |
959 | ||
2c7ee1a6 | 960 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0 |
1a94ca49 RK |
961 | |
962 | /* Define intermediate macro to compute the size (in registers) of an argument | |
963 | for the Alpha. */ | |
964 | ||
965 | #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ | |
966 | ((MODE) != BLKmode \ | |
967 | ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ | |
968 | : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
969 | ||
970 | /* Update the data in CUM to advance over an argument | |
971 | of mode MODE and data type TYPE. | |
972 | (TYPE is null for libcalls where that information may not be available.) */ | |
973 | ||
974 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
975 | if (MUST_PASS_IN_STACK (MODE, TYPE)) \ | |
976 | (CUM) = 6; \ | |
977 | else \ | |
978 | (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) | |
979 | ||
980 | /* Determine where to put an argument to a function. | |
981 | Value is zero to push the argument on the stack, | |
982 | or a hard register in which to store the argument. | |
983 | ||
984 | MODE is the argument's machine mode. | |
985 | TYPE is the data type of the argument (as a tree). | |
986 | This is null for libcalls where that information may | |
987 | not be available. | |
988 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
989 | the preceding args and about the function being called. | |
990 | NAMED is nonzero if this argument is a named parameter | |
991 | (otherwise it is an extra parameter matching an ellipsis). | |
992 | ||
993 | On Alpha the first 6 words of args are normally in registers | |
994 | and the rest are pushed. */ | |
995 | ||
996 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
997 | ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \ | |
998 | ? gen_rtx(REG, (MODE), \ | |
14d4a67a RK |
999 | (CUM) + 16 + ((TARGET_FPREGS \ |
1000 | && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ | |
1001 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ | |
1002 | * 32)) \ | |
1003 | : 0) | |
1a94ca49 | 1004 | |
1a94ca49 RK |
1005 | /* Specify the padding direction of arguments. |
1006 | ||
1007 | On the Alpha, we must pad upwards in order to be able to pass args in | |
1008 | registers. */ | |
1009 | ||
1010 | #define FUNCTION_ARG_PADDING(MODE, TYPE) upward | |
1011 | ||
1012 | /* For an arg passed partly in registers and partly in memory, | |
1013 | this is the number of registers used. | |
1014 | For args passed entirely in registers or entirely in memory, zero. */ | |
1015 | ||
1016 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1017 | ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ | |
1018 | ? 6 - (CUM) : 0) | |
1019 | ||
130d2d72 RK |
1020 | /* Perform any needed actions needed for a function that is receiving a |
1021 | variable number of arguments. | |
1022 | ||
1023 | CUM is as above. | |
1024 | ||
1025 | MODE and TYPE are the mode and type of the current parameter. | |
1026 | ||
1027 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1028 | that must be pushed by the prolog to pretend that our caller pushed | |
1029 | it. | |
1030 | ||
1031 | Normally, this macro will push all remaining incoming registers on the | |
1032 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1033 | ||
1034 | On the Alpha, we allocate space for all 12 arg registers, but only | |
1035 | push those that are remaining. | |
1036 | ||
1037 | However, if NO registers need to be saved, don't allocate any space. | |
1038 | This is not only because we won't need the space, but because AP includes | |
1039 | the current_pretend_args_size and we don't want to mess up any | |
7a92339b RK |
1040 | ap-relative addresses already made. |
1041 | ||
1042 | If we are not to use the floating-point registers, save the integer | |
1043 | registers where we would put the floating-point registers. This is | |
1044 | not the most efficient way to implement varargs with just one register | |
1045 | class, but it isn't worth doing anything more efficient in this rare | |
1046 | case. */ | |
1047 | ||
130d2d72 RK |
1048 | |
1049 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ | |
1050 | { if ((CUM) < 6) \ | |
1051 | { \ | |
1052 | if (! (NO_RTL)) \ | |
1053 | { \ | |
1054 | move_block_from_reg \ | |
1055 | (16 + CUM, \ | |
1056 | gen_rtx (MEM, BLKmode, \ | |
1057 | plus_constant (virtual_incoming_args_rtx, \ | |
7f5bd4ff | 1058 | ((CUM) + 6)* UNITS_PER_WORD)), \ |
02892e06 | 1059 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
130d2d72 | 1060 | move_block_from_reg \ |
7a92339b | 1061 | (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \ |
130d2d72 RK |
1062 | gen_rtx (MEM, BLKmode, \ |
1063 | plus_constant (virtual_incoming_args_rtx, \ | |
7f5bd4ff | 1064 | (CUM) * UNITS_PER_WORD)), \ |
02892e06 | 1065 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
7a14fdc5 | 1066 | emit_insn (gen_blockage ()); \ |
130d2d72 RK |
1067 | } \ |
1068 | PRETEND_SIZE = 12 * UNITS_PER_WORD; \ | |
1069 | } \ | |
1070 | } | |
1071 | ||
c8e9adec RK |
1072 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1073 | done in less than N insns. Do all computations in MODE. Returns the place | |
1074 | where the output has been placed if it can be done and the insns have been | |
1075 | emitted. If it would take more than N insns, zero is returned and no | |
1076 | insns and emitted. */ | |
1077 | extern struct rtx_def *alpha_emit_set_const (); | |
803fee69 | 1078 | extern struct rtx_def *alpha_emit_set_long_const (); |
92e40a7a RK |
1079 | extern struct rtx_def *alpha_emit_conditional_move (); |
1080 | ||
1a94ca49 RK |
1081 | /* Generate necessary RTL for __builtin_saveregs(). |
1082 | ARGLIST is the argument list; see expr.c. */ | |
1083 | extern struct rtx_def *alpha_builtin_saveregs (); | |
1084 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST) | |
1085 | ||
1086 | /* Define the information needed to generate branch and scc insns. This is | |
1087 | stored from the compare operation. Note that we can't use "rtx" here | |
1088 | since it hasn't been defined! */ | |
1089 | ||
1090 | extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1; | |
1091 | extern int alpha_compare_fp_p; | |
1092 | ||
e5958492 RK |
1093 | /* Make (or fake) .linkage entry for function call. |
1094 | ||
1095 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ | |
1096 | extern void alpha_need_linkage (); | |
1097 | ||
bcbbac26 RH |
1098 | /* This macro defines the start of an assembly comment. */ |
1099 | ||
1100 | #define ASM_COMMENT_START " #" | |
1101 | ||
1a94ca49 | 1102 | /* This macro produces the initial definition of a function name. On the |
03f8c4cc | 1103 | Alpha, we need to save the function name for the prologue and epilogue. */ |
1a94ca49 RK |
1104 | |
1105 | extern char *alpha_function_name; | |
1106 | ||
1107 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ | |
03f8c4cc | 1108 | { \ |
1a94ca49 RK |
1109 | alpha_function_name = NAME; \ |
1110 | } | |
1111 | ||
1112 | /* This macro generates the assembly code for function entry. | |
1113 | FILE is a stdio stream to output the code to. | |
1114 | SIZE is an int: how many units of temporary storage to allocate. | |
1115 | Refer to the array `regs_ever_live' to determine which registers | |
1116 | to save; `regs_ever_live[I]' is nonzero if register number I | |
1117 | is ever used in the function. This macro is responsible for | |
1118 | knowing which registers should not be saved even if used. */ | |
1119 | ||
1120 | #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE) | |
1121 | ||
1122 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
e0fb9029 | 1123 | for profiling a function entry. Under OSF/1, profiling is enabled |
ddd5a7c1 | 1124 | by simply passing -pg to the assembler and linker. */ |
85d159a3 | 1125 | |
e0fb9029 | 1126 | #define FUNCTION_PROFILER(FILE, LABELNO) |
85d159a3 RK |
1127 | |
1128 | /* Output assembler code to FILE to initialize this source file's | |
1129 | basic block profiling info, if that has not already been done. | |
1130 | This assumes that __bb_init_func doesn't garble a1-a5. */ | |
1131 | ||
1132 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
1133 | do { \ | |
1134 | ASM_OUTPUT_REG_PUSH (FILE, 16); \ | |
a62eb16f JW |
1135 | fputs ("\tlda $16,$PBX32\n", (FILE)); \ |
1136 | fputs ("\tldq $26,0($16)\n", (FILE)); \ | |
1137 | fputs ("\tbne $26,1f\n", (FILE)); \ | |
1138 | fputs ("\tlda $27,__bb_init_func\n", (FILE)); \ | |
1139 | fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \ | |
1140 | fputs ("\tldgp $29,0($26)\n", (FILE)); \ | |
1141 | fputs ("1:\n", (FILE)); \ | |
85d159a3 RK |
1142 | ASM_OUTPUT_REG_POP (FILE, 16); \ |
1143 | } while (0); | |
1144 | ||
1145 | /* Output assembler code to FILE to increment the entry-count for | |
1146 | the BLOCKNO'th basic block in this source file. */ | |
1147 | ||
1148 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1149 | do { \ | |
1150 | int blockn = (BLOCKNO); \ | |
a62eb16f | 1151 | fputs ("\tsubq $30,16,$30\n", (FILE)); \ |
70a76f06 RK |
1152 | fputs ("\tstq $26,0($30)\n", (FILE)); \ |
1153 | fputs ("\tstq $27,8($30)\n", (FILE)); \ | |
1154 | fputs ("\tlda $26,$PBX34\n", (FILE)); \ | |
1155 | fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \ | |
1156 | fputs ("\taddq $27,1,$27\n", (FILE)); \ | |
1157 | fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \ | |
1158 | fputs ("\tldq $26,0($30)\n", (FILE)); \ | |
1159 | fputs ("\tldq $27,8($30)\n", (FILE)); \ | |
a62eb16f | 1160 | fputs ("\taddq $30,16,$30\n", (FILE)); \ |
85d159a3 | 1161 | } while (0) |
1a94ca49 | 1162 | |
1a94ca49 RK |
1163 | |
1164 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1165 | the stack pointer does not matter. The value is tested only in | |
1166 | functions that have frame pointers. | |
1167 | No definition is equivalent to always zero. */ | |
1168 | ||
1169 | #define EXIT_IGNORE_STACK 1 | |
1170 | ||
1171 | /* This macro generates the assembly code for function exit, | |
1172 | on machines that need it. If FUNCTION_EPILOGUE is not defined | |
1173 | then individual return instructions are generated for each | |
1174 | return statement. Args are same as for FUNCTION_PROLOGUE. | |
1175 | ||
1176 | The function epilogue should not depend on the current stack pointer! | |
1177 | It should use the frame pointer only. This is mandatory because | |
1178 | of alloca; we also take advantage of it to omit stack adjustments | |
1179 | before returning. */ | |
1180 | ||
1181 | #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE) | |
1182 | ||
1183 | \f | |
1184 | /* Output assembler code for a block containing the constant parts | |
1185 | of a trampoline, leaving space for the variable parts. | |
1186 | ||
1187 | The trampoline should set the static chain pointer to value placed | |
7981384f RK |
1188 | into the trampoline and should branch to the specified routine. |
1189 | Note that $27 has been set to the address of the trampoline, so we can | |
1190 | use it for addressability of the two data items. Trampolines are always | |
1191 | aligned to FUNCTION_BOUNDARY, which is 64 bits. */ | |
1a94ca49 RK |
1192 | |
1193 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
1194 | { \ | |
7981384f | 1195 | fprintf (FILE, "\tldq $1,24($27)\n"); \ |
1a94ca49 | 1196 | fprintf (FILE, "\tldq $27,16($27)\n"); \ |
7981384f RK |
1197 | fprintf (FILE, "\tjmp $31,($27),0\n"); \ |
1198 | fprintf (FILE, "\tnop\n"); \ | |
1a94ca49 RK |
1199 | fprintf (FILE, "\t.quad 0,0\n"); \ |
1200 | } | |
1201 | ||
3a523eeb RS |
1202 | /* Section in which to place the trampoline. On Alpha, instructions |
1203 | may only be placed in a text segment. */ | |
1204 | ||
1205 | #define TRAMPOLINE_SECTION text_section | |
1206 | ||
1a94ca49 RK |
1207 | /* Length in units of the trampoline for entering a nested function. */ |
1208 | ||
7981384f | 1209 | #define TRAMPOLINE_SIZE 32 |
1a94ca49 RK |
1210 | |
1211 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1212 | FNADDR is an RTX for the address of the function's pure code. | |
1213 | CXT is an RTX for the static chain value for the function. We assume | |
1214 | here that a function will be called many more times than its address | |
1215 | is taken (e.g., it might be passed to qsort), so we take the trouble | |
7981384f RK |
1216 | to initialize the "hint" field in the JMP insn. Note that the hint |
1217 | field is PC (new) + 4 * bits 13:0. */ | |
1a94ca49 RK |
1218 | |
1219 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1220 | { \ | |
1221 | rtx _temp, _temp1, _addr; \ | |
1222 | \ | |
1223 | _addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \ | |
1224 | emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR)); \ | |
7981384f | 1225 | _addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \ |
1a94ca49 RK |
1226 | emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT)); \ |
1227 | \ | |
7981384f RK |
1228 | _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX); \ |
1229 | _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1, \ | |
1230 | OPTAB_WIDEN); \ | |
1231 | _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp, \ | |
1a94ca49 | 1232 | build_int_2 (2, 0), NULL_RTX, 1); \ |
7981384f RK |
1233 | _temp = expand_and (gen_lowpart (SImode, _temp), \ |
1234 | GEN_INT (0x3fff), 0); \ | |
1a94ca49 | 1235 | \ |
7981384f | 1236 | _addr = memory_address (SImode, plus_constant ((TRAMP), 8)); \ |
1a94ca49 | 1237 | _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr)); \ |
7981384f | 1238 | _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX); \ |
1a94ca49 RK |
1239 | _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1, \ |
1240 | OPTAB_WIDEN); \ | |
1241 | \ | |
1242 | emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1); \ | |
7981384f RK |
1243 | \ |
1244 | emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \ | |
1245 | "__enable_execute_stack"), \ | |
1246 | 0, VOIDmode, 1,_addr, Pmode); \ | |
1247 | \ | |
1248 | emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \ | |
1249 | gen_rtvec (1, const0_rtx), 0)); \ | |
1250 | } | |
1251 | ||
1252 | /* Attempt to turn on access permissions for the stack. */ | |
1253 | ||
1254 | #define TRANSFER_FROM_TRAMPOLINE \ | |
1255 | \ | |
1256 | void \ | |
1257 | __enable_execute_stack (addr) \ | |
1258 | void *addr; \ | |
1259 | { \ | |
1260 | long size = getpagesize (); \ | |
1261 | long mask = ~(size-1); \ | |
1262 | char *page = (char *) (((long) addr) & mask); \ | |
1263 | char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \ | |
1264 | \ | |
1265 | /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \ | |
1266 | if (mprotect (page, end - page, 7) < 0) \ | |
1267 | perror ("mprotect of trampoline code"); \ | |
1a94ca49 | 1268 | } |
675f0e7c RK |
1269 | |
1270 | /* A C expression whose value is RTL representing the value of the return | |
1271 | address for the frame COUNT steps up from the current frame. | |
1272 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of | |
9ecc37f0 | 1273 | the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME} is defined. */ |
675f0e7c | 1274 | |
9ecc37f0 RH |
1275 | #define RETURN_ADDR_RTX alpha_return_addr |
1276 | extern struct rtx_def *alpha_return_addr (); | |
1277 | ||
1278 | /* Initialize data used by insn expanders. This is called from insn_emit, | |
1279 | once for every function before code is generated. */ | |
1280 | ||
1281 | #define INIT_EXPANDERS alpha_init_expanders () | |
1282 | extern void alpha_init_expanders (); | |
675f0e7c | 1283 | |
675f0e7c | 1284 | \f |
1a94ca49 RK |
1285 | /* Addressing modes, and classification of registers for them. */ |
1286 | ||
1287 | /* #define HAVE_POST_INCREMENT */ | |
1288 | /* #define HAVE_POST_DECREMENT */ | |
1289 | ||
1290 | /* #define HAVE_PRE_DECREMENT */ | |
1291 | /* #define HAVE_PRE_INCREMENT */ | |
1292 | ||
1293 | /* Macros to check register numbers against specific register classes. */ | |
1294 | ||
1295 | /* These assume that REGNO is a hard or pseudo reg number. | |
1296 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1297 | or a pseudo reg currently allocated to a suitable hard reg. | |
1298 | Since they use reg_renumber, they are safe only once reg_renumber | |
1299 | has been allocated, which happens in local-alloc.c. */ | |
1300 | ||
1301 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
1302 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
52a69200 RK |
1303 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ |
1304 | || (REGNO) == 63 || reg_renumber[REGNO] == 63) | |
1a94ca49 RK |
1305 | \f |
1306 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1307 | #define MAX_REGS_PER_ADDRESS 1 | |
1308 | ||
1309 | /* Recognize any constant value that is a valid address. For the Alpha, | |
1310 | there are only constants none since we want to use LDA to load any | |
1311 | symbolic addresses into registers. */ | |
1312 | ||
1313 | #define CONSTANT_ADDRESS_P(X) \ | |
1314 | (GET_CODE (X) == CONST_INT \ | |
1315 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
1316 | ||
1317 | /* Include all constant integers and constant doubles, but not | |
1318 | floating-point, except for floating-point zero. */ | |
1319 | ||
1320 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1321 | (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ | |
1322 | || (X) == CONST0_RTX (GET_MODE (X))) | |
1323 | ||
1324 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1325 | and check its validity for a certain class. | |
1326 | We have two alternate definitions for each of them. | |
1327 | The usual definition accepts all pseudo regs; the other rejects | |
1328 | them unless they have been allocated suitable hard regs. | |
1329 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1330 | ||
1331 | Most source files want to accept pseudo regs in the hope that | |
1332 | they will get allocated to the class that the insn wants them to be in. | |
1333 | Source files for reload pass need to be strict. | |
1334 | After reload, it makes no difference, since pseudo regs have | |
1335 | been eliminated by then. */ | |
1336 | ||
1337 | #ifndef REG_OK_STRICT | |
1338 | ||
1339 | /* Nonzero if X is a hard reg that can be used as an index | |
1340 | or if it is a pseudo reg. */ | |
1341 | #define REG_OK_FOR_INDEX_P(X) 0 | |
1342 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1343 | or if it is a pseudo reg. */ | |
1344 | #define REG_OK_FOR_BASE_P(X) \ | |
52a69200 | 1345 | (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1a94ca49 RK |
1346 | |
1347 | #else | |
1348 | ||
1349 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1350 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1351 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
1352 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1353 | ||
1354 | #endif | |
1355 | \f | |
1356 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1357 | that is a valid memory address for an instruction. | |
1358 | The MODE argument is the machine mode for the MEM expression | |
1359 | that wants to use this address. | |
1360 | ||
1361 | For Alpha, we have either a constant address or the sum of a register | |
1362 | and a constant address, or just a register. For DImode, any of those | |
1363 | forms can be surrounded with an AND that clear the low-order three bits; | |
1364 | this is an "unaligned" access. | |
1365 | ||
1a94ca49 RK |
1366 | First define the basic valid address. */ |
1367 | ||
1368 | #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \ | |
1369 | { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \ | |
1370 | goto ADDR; \ | |
1371 | if (CONSTANT_ADDRESS_P (X)) \ | |
1372 | goto ADDR; \ | |
1373 | if (GET_CODE (X) == PLUS \ | |
1374 | && REG_P (XEXP (X, 0)) \ | |
1375 | && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ | |
1376 | && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1377 | goto ADDR; \ | |
1378 | } | |
1379 | ||
1380 | /* Now accept the simple address, or, for DImode only, an AND of a simple | |
1381 | address that turns off the low three bits. */ | |
1382 | ||
1a94ca49 RK |
1383 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
1384 | { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \ | |
1385 | if ((MODE) == DImode \ | |
1386 | && GET_CODE (X) == AND \ | |
1387 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1388 | && INTVAL (XEXP (X, 1)) == -8) \ | |
1389 | GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \ | |
1a94ca49 RK |
1390 | } |
1391 | ||
1392 | /* Try machine-dependent ways of modifying an illegitimate address | |
1393 | to be legitimate. If we find one, return the new, valid address. | |
1394 | This macro is used in only one place: `memory_address' in explow.c. | |
1395 | ||
1396 | OLDX is the address as it was before break_out_memory_refs was called. | |
1397 | In some cases it is useful to look at this to decide what needs to be done. | |
1398 | ||
1399 | MODE and WIN are passed so that this macro can use | |
1400 | GO_IF_LEGITIMATE_ADDRESS. | |
1401 | ||
1402 | It is always safe for this macro to do nothing. It exists to recognize | |
1403 | opportunities to optimize the output. | |
1404 | ||
1405 | For the Alpha, there are three cases we handle: | |
1406 | ||
1407 | (1) If the address is (plus reg const_int) and the CONST_INT is not a | |
1408 | valid offset, compute the high part of the constant and add it to the | |
1409 | register. Then our address is (plus temp low-part-const). | |
1410 | (2) If the address is (const (plus FOO const_int)), find the low-order | |
1411 | part of the CONST_INT. Then load FOO plus any high-order part of the | |
1412 | CONST_INT into a register. Our address is (plus reg low-part-const). | |
1413 | This is done to reduce the number of GOT entries. | |
1414 | (3) If we have a (plus reg const), emit the load as in (2), then add | |
1415 | the two registers, and finally generate (plus reg low-part-const) as | |
1416 | our address. */ | |
1417 | ||
1418 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1419 | { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1420 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1421 | && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1422 | { \ | |
1423 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1424 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1425 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1426 | rtx high = GEN_INT (highpart); \ | |
1427 | rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \ | |
80f251fe | 1428 | high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1429 | \ |
1430 | (X) = plus_constant (temp, lowpart); \ | |
1431 | goto WIN; \ | |
1432 | } \ | |
1433 | else if (GET_CODE (X) == CONST \ | |
1434 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1435 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
1436 | { \ | |
1437 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
1438 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1439 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1440 | rtx high = XEXP (XEXP (X, 0), 0); \ | |
1441 | \ | |
1442 | if (highpart) \ | |
1443 | high = plus_constant (high, highpart); \ | |
1444 | \ | |
1445 | (X) = plus_constant (force_reg (Pmode, high), lowpart); \ | |
1446 | goto WIN; \ | |
1447 | } \ | |
1448 | else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1449 | && GET_CODE (XEXP (X, 1)) == CONST \ | |
1450 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \ | |
1451 | && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \ | |
1452 | { \ | |
1453 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \ | |
1454 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1455 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1456 | rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \ | |
1457 | \ | |
1458 | if (highpart) \ | |
1459 | high = plus_constant (high, highpart); \ | |
1460 | \ | |
1461 | high = expand_binop (Pmode, add_optab, XEXP (X, 0), \ | |
1462 | force_reg (Pmode, high), \ | |
80f251fe | 1463 | high, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1464 | (X) = plus_constant (high, lowpart); \ |
1465 | goto WIN; \ | |
1466 | } \ | |
1467 | } | |
1468 | ||
a9a2595b JR |
1469 | /* Try a machine-dependent way of reloading an illegitimate address |
1470 | operand. If we find one, push the reload and jump to WIN. This | |
1471 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1472 | ||
1473 | For the Alpha, we wish to handle large displacements off a base | |
1474 | register by splitting the addend across an ldah and the mem insn. | |
1475 | This cuts number of extra insns needed from 3 to 1. */ | |
1476 | ||
1477 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1478 | do { \ | |
1479 | if (GET_CODE (X) == PLUS \ | |
1480 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1481 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1482 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1483 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1484 | { \ | |
1485 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1486 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \ | |
1487 | HOST_WIDE_INT high \ | |
1488 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \ | |
1489 | \ | |
1490 | /* Check for 32-bit overflow. */ \ | |
1491 | if (high + low != val) \ | |
1492 | break; \ | |
1493 | \ | |
1494 | /* Reload the high part into a base reg; leave the low part \ | |
1495 | in the mem directly. */ \ | |
1496 | \ | |
1497 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1498 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1499 | GEN_INT (high)), \ | |
1500 | GEN_INT (low)); \ | |
1501 | \ | |
1502 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1503 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1504 | OPNUM, TYPE); \ | |
1505 | goto WIN; \ | |
1506 | } \ | |
1507 | } while (0) | |
1508 | ||
1a94ca49 RK |
1509 | /* Go to LABEL if ADDR (a legitimate address expression) |
1510 | has an effect that depends on the machine mode it is used for. | |
1511 | On the Alpha this is true only for the unaligned modes. We can | |
1512 | simplify this test since we know that the address must be valid. */ | |
1513 | ||
1514 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1515 | { if (GET_CODE (ADDR) == AND) goto LABEL; } | |
1516 | ||
1517 | /* Compute the cost of an address. For the Alpha, all valid addresses are | |
1518 | the same cost. */ | |
1519 | ||
1520 | #define ADDRESS_COST(X) 0 | |
1521 | ||
2ea844d3 RH |
1522 | /* Machine-dependent reorg pass. */ |
1523 | #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X) | |
1a94ca49 RK |
1524 | \f |
1525 | /* Specify the machine mode that this machine uses | |
1526 | for the index in the tablejump instruction. */ | |
1527 | #define CASE_VECTOR_MODE SImode | |
1528 | ||
18543a22 ILT |
1529 | /* Define as C expression which evaluates to nonzero if the tablejump |
1530 | instruction expects the table to contain offsets from the address of the | |
3aa9d5b6 | 1531 | table. |
b0435cf4 | 1532 | |
3aa9d5b6 | 1533 | Do not define this if the table should contain absolute addresses. |
260ced47 RK |
1534 | On the Alpha, the table is really GP-relative, not relative to the PC |
1535 | of the table, but we pretend that it is PC-relative; this should be OK, | |
0076aa6b | 1536 | but we should try to find some better way sometime. */ |
18543a22 | 1537 | #define CASE_VECTOR_PC_RELATIVE 1 |
1a94ca49 RK |
1538 | |
1539 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1540 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1541 | ||
1542 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1543 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1544 | ||
1545 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1546 | #define DEFAULT_SIGNED_CHAR 1 | |
1547 | ||
1548 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1549 | also convert validly to an unsigned one. | |
1550 | ||
1551 | We actually lie a bit here as overflow conditions are different. But | |
1552 | they aren't being checked anyway. */ | |
1553 | ||
1554 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1555 | ||
1556 | /* Max number of bytes we can move to or from memory | |
1557 | in one reasonably fast instruction. */ | |
1558 | ||
1559 | #define MOVE_MAX 8 | |
1560 | ||
6c174fc0 RH |
1561 | /* Controls how many units are moved by expr.c before resorting to movstr. |
1562 | Without byte/word accesses, we want no more than one; with, several single | |
1563 | byte accesses are better. */ | |
1564 | ||
1565 | #define MOVE_RATIO (TARGET_BWX ? 7 : 2) | |
1566 | ||
1a94ca49 RK |
1567 | /* Largest number of bytes of an object that can be placed in a register. |
1568 | On the Alpha we have plenty of registers, so use TImode. */ | |
1569 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
1570 | ||
1571 | /* Nonzero if access to memory by bytes is no faster than for words. | |
1572 | Also non-zero if doing byte operations (specifically shifts) in registers | |
1573 | is undesirable. | |
1574 | ||
1575 | On the Alpha, we want to not use the byte operation and instead use | |
1576 | masking operations to access fields; these will save instructions. */ | |
1577 | ||
1578 | #define SLOW_BYTE_ACCESS 1 | |
1579 | ||
9a63901f RK |
1580 | /* Define if operations between registers always perform the operation |
1581 | on the full register even if a narrower mode is specified. */ | |
1582 | #define WORD_REGISTER_OPERATIONS | |
1583 | ||
1584 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1585 | will either zero-extend or sign-extend. The value of this macro should | |
1586 | be the code that says which one of the two operations is implicitly | |
1587 | done, NIL if none. */ | |
b7747781 | 1588 | #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) |
1a94ca49 | 1589 | |
225211e2 RK |
1590 | /* Define if loading short immediate values into registers sign extends. */ |
1591 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1592 | ||
1a94ca49 RK |
1593 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1594 | is done just by pretending it is already truncated. */ | |
1595 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1596 | ||
1597 | /* We assume that the store-condition-codes instructions store 0 for false | |
1598 | and some other value for true. This is the value stored for true. */ | |
1599 | ||
1600 | #define STORE_FLAG_VALUE 1 | |
1601 | ||
1602 | /* Define the value returned by a floating-point comparison instruction. */ | |
1603 | ||
e9a25f70 | 1604 | #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0) |
1a94ca49 | 1605 | |
35bb77fd RK |
1606 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
1607 | ||
1608 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1609 | do { \ | |
1610 | if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ | |
1611 | && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ | |
1612 | { \ | |
1613 | rtx tem = (OP0); \ | |
1614 | (OP0) = (OP1); \ | |
1615 | (OP1) = tem; \ | |
1616 | (CODE) = swap_condition (CODE); \ | |
1617 | } \ | |
1618 | if (((CODE) == LT || (CODE) == LTU) \ | |
1619 | && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ | |
1620 | { \ | |
1621 | (CODE) = (CODE) == LT ? LE : LEU; \ | |
1622 | (OP1) = GEN_INT (255); \ | |
1623 | } \ | |
1624 | } while (0) | |
1625 | ||
1a94ca49 RK |
1626 | /* Specify the machine mode that pointers have. |
1627 | After generation of rtl, the compiler makes no further distinction | |
1628 | between pointers and any other objects of this machine mode. */ | |
1629 | #define Pmode DImode | |
1630 | ||
1631 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
1632 | ||
1633 | #define FUNCTION_MODE Pmode | |
1634 | ||
1635 | /* Define this if addresses of constant functions | |
1636 | shouldn't be put through pseudo regs where they can be cse'd. | |
1637 | Desirable on machines where ordinary constants are expensive | |
1638 | but a CALL with constant address is cheap. | |
1639 | ||
1640 | We define this on the Alpha so that gen_call and gen_call_value | |
1641 | get to see the SYMBOL_REF (for the hint field of the jsr). It will | |
1642 | then copy it into a register, thus actually letting the address be | |
1643 | cse'ed. */ | |
1644 | ||
1645 | #define NO_FUNCTION_CSE | |
1646 | ||
d969caf8 | 1647 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
1a94ca49 | 1648 | few bits. */ |
d969caf8 | 1649 | #define SHIFT_COUNT_TRUNCATED 1 |
1a94ca49 | 1650 | |
d721b776 RK |
1651 | /* Use atexit for static constructors/destructors, instead of defining |
1652 | our own exit function. */ | |
1653 | #define HAVE_ATEXIT | |
1654 | ||
71d9b493 | 1655 | /* The EV4 is dual issue; EV5/EV6 are quad issue. */ |
74835ed8 RH |
1656 | #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4) |
1657 | ||
1a94ca49 RK |
1658 | /* Compute the cost of computing a constant rtl expression RTX |
1659 | whose rtx-code is CODE. The body of this macro is a portion | |
1660 | of a switch statement. If the code is computed here, | |
1661 | return it with a return statement. Otherwise, break from the switch. | |
1662 | ||
8b7b2e36 RK |
1663 | If this is an 8-bit constant, return zero since it can be used |
1664 | nearly anywhere with no cost. If it is a valid operand for an | |
1665 | ADD or AND, likewise return 0 if we know it will be used in that | |
1666 | context. Otherwise, return 2 since it might be used there later. | |
1667 | All other constants take at least two insns. */ | |
1a94ca49 RK |
1668 | |
1669 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ | |
1670 | case CONST_INT: \ | |
06eb8e92 | 1671 | if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \ |
8b7b2e36 | 1672 | return 0; \ |
1a94ca49 | 1673 | case CONST_DOUBLE: \ |
8b7b2e36 RK |
1674 | if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \ |
1675 | || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \ | |
1676 | return 0; \ | |
1677 | else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \ | |
1678 | return 2; \ | |
1679 | else \ | |
1680 | return COSTS_N_INSNS (2); \ | |
1a94ca49 RK |
1681 | case CONST: \ |
1682 | case SYMBOL_REF: \ | |
1683 | case LABEL_REF: \ | |
f6f6a13c RK |
1684 | switch (alpha_cpu) \ |
1685 | { \ | |
1686 | case PROCESSOR_EV4: \ | |
1687 | return COSTS_N_INSNS (3); \ | |
1688 | case PROCESSOR_EV5: \ | |
1689 | return COSTS_N_INSNS (2); \ | |
1690 | } | |
1a94ca49 RK |
1691 | |
1692 | /* Provide the costs of a rtl expression. This is in the body of a | |
1693 | switch on CODE. */ | |
1694 | ||
1695 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
3bda6d11 RK |
1696 | case PLUS: case MINUS: \ |
1697 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
f6f6a13c RK |
1698 | switch (alpha_cpu) \ |
1699 | { \ | |
1700 | case PROCESSOR_EV4: \ | |
1701 | return COSTS_N_INSNS (6); \ | |
1702 | case PROCESSOR_EV5: \ | |
1703 | return COSTS_N_INSNS (4); \ | |
1704 | } \ | |
b49e978e RK |
1705 | else if (GET_CODE (XEXP (X, 0)) == MULT \ |
1706 | && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ | |
a5da0afe RK |
1707 | return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ |
1708 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1a94ca49 RK |
1709 | break; \ |
1710 | case MULT: \ | |
f6f6a13c RK |
1711 | switch (alpha_cpu) \ |
1712 | { \ | |
1713 | case PROCESSOR_EV4: \ | |
1714 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1715 | return COSTS_N_INSNS (6); \ | |
1716 | return COSTS_N_INSNS (23); \ | |
1717 | case PROCESSOR_EV5: \ | |
1718 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1719 | return COSTS_N_INSNS (4); \ | |
1720 | else if (GET_MODE (X) == DImode) \ | |
1721 | return COSTS_N_INSNS (12); \ | |
1722 | else \ | |
1723 | return COSTS_N_INSNS (8); \ | |
1724 | } \ | |
b49e978e RK |
1725 | case ASHIFT: \ |
1726 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1727 | && INTVAL (XEXP (X, 1)) <= 3) \ | |
1728 | break; \ | |
1729 | /* ... fall through ... */ \ | |
1730 | case ASHIFTRT: case LSHIFTRT: case IF_THEN_ELSE: \ | |
f6f6a13c RK |
1731 | switch (alpha_cpu) \ |
1732 | { \ | |
1733 | case PROCESSOR_EV4: \ | |
1734 | return COSTS_N_INSNS (2); \ | |
1735 | case PROCESSOR_EV5: \ | |
1736 | return COSTS_N_INSNS (1); \ | |
1737 | } \ | |
3bda6d11 | 1738 | case DIV: case UDIV: case MOD: case UMOD: \ |
f6f6a13c RK |
1739 | switch (alpha_cpu) \ |
1740 | { \ | |
1741 | case PROCESSOR_EV4: \ | |
1742 | if (GET_MODE (X) == SFmode) \ | |
1743 | return COSTS_N_INSNS (34); \ | |
1744 | else if (GET_MODE (X) == DFmode) \ | |
1745 | return COSTS_N_INSNS (63); \ | |
1746 | else \ | |
1747 | return COSTS_N_INSNS (70); \ | |
1748 | case PROCESSOR_EV5: \ | |
1749 | if (GET_MODE (X) == SFmode) \ | |
1750 | return COSTS_N_INSNS (15); \ | |
1751 | else if (GET_MODE (X) == DFmode) \ | |
1752 | return COSTS_N_INSNS (22); \ | |
1753 | else \ | |
1754 | return COSTS_N_INSNS (70); /* EV5 ??? */ \ | |
1755 | } \ | |
1a94ca49 | 1756 | case MEM: \ |
f6f6a13c RK |
1757 | switch (alpha_cpu) \ |
1758 | { \ | |
1759 | case PROCESSOR_EV4: \ | |
1760 | return COSTS_N_INSNS (3); \ | |
1761 | case PROCESSOR_EV5: \ | |
1762 | return COSTS_N_INSNS (2); \ | |
1763 | } \ | |
1764 | case NEG: case ABS: \ | |
1765 | if (! FLOAT_MODE_P (GET_MODE (X))) \ | |
1766 | break; \ | |
1767 | /* ... fall through ... */ \ | |
3bda6d11 RK |
1768 | case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \ |
1769 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ | |
f6f6a13c RK |
1770 | switch (alpha_cpu) \ |
1771 | { \ | |
1772 | case PROCESSOR_EV4: \ | |
1773 | return COSTS_N_INSNS (6); \ | |
1774 | case PROCESSOR_EV5: \ | |
1775 | return COSTS_N_INSNS (4); \ | |
1776 | } | |
1a94ca49 RK |
1777 | \f |
1778 | /* Control the assembler format that we output. */ | |
1779 | ||
40ef2fc5 JL |
1780 | /* We don't emit these labels, so as to avoid getting linker errors about |
1781 | missing exception handling info. If we emit a gcc_compiled. label into | |
1782 | text, and the file has no code, then the DEC assembler gives us a zero | |
1783 | sized text section with no associated exception handling info. The | |
1784 | DEC linker sees this text section, and gives a warning saying saying that | |
1785 | the exception handling info is missing. */ | |
1786 | #define ASM_IDENTIFY_GCC | |
1787 | #define ASM_IDENTIFY_LANGUAGE | |
1788 | ||
1a94ca49 RK |
1789 | /* Output to assembler file text saying following lines |
1790 | may contain character constants, extra white space, comments, etc. */ | |
1791 | ||
1792 | #define ASM_APP_ON "" | |
1793 | ||
1794 | /* Output to assembler file text saying following lines | |
1795 | no longer contain unusual constructs. */ | |
1796 | ||
1797 | #define ASM_APP_OFF "" | |
1798 | ||
1799 | #define TEXT_SECTION_ASM_OP ".text" | |
1800 | ||
1801 | /* Output before read-only data. */ | |
1802 | ||
1803 | #define READONLY_DATA_SECTION_ASM_OP ".rdata" | |
1804 | ||
1805 | /* Output before writable data. */ | |
1806 | ||
1807 | #define DATA_SECTION_ASM_OP ".data" | |
1808 | ||
1809 | /* Define an extra section for read-only data, a routine to enter it, and | |
c0388f29 RK |
1810 | indicate that it is for read-only data. |
1811 | ||
abc95ed3 | 1812 | The first time we enter the readonly data section for a file, we write |
c0388f29 RK |
1813 | eight bytes of zero. This works around a bug in DEC's assembler in |
1814 | some versions of OSF/1 V3.x. */ | |
1a94ca49 RK |
1815 | |
1816 | #define EXTRA_SECTIONS readonly_data | |
1817 | ||
1818 | #define EXTRA_SECTION_FUNCTIONS \ | |
1819 | void \ | |
1820 | literal_section () \ | |
1821 | { \ | |
1822 | if (in_section != readonly_data) \ | |
1823 | { \ | |
c0388f29 RK |
1824 | static int firsttime = 1; \ |
1825 | \ | |
1a94ca49 | 1826 | fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ |
c0388f29 RK |
1827 | if (firsttime) \ |
1828 | { \ | |
1829 | firsttime = 0; \ | |
1830 | ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \ | |
1831 | } \ | |
1832 | \ | |
1a94ca49 RK |
1833 | in_section = readonly_data; \ |
1834 | } \ | |
1835 | } \ | |
1836 | ||
1837 | #define READONLY_DATA_SECTION literal_section | |
1838 | ||
ac030a7b RK |
1839 | /* If we are referencing a function that is static, make the SYMBOL_REF |
1840 | special. We use this to see indicate we can branch to this function | |
1841 | without setting PV or restoring GP. */ | |
130d2d72 RK |
1842 | |
1843 | #define ENCODE_SECTION_INFO(DECL) \ | |
ac030a7b | 1844 | if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \ |
130d2d72 RK |
1845 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; |
1846 | ||
1a94ca49 RK |
1847 | /* How to refer to registers in assembler output. |
1848 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1849 | ||
1850 | #define REGISTER_NAMES \ | |
1851 | {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ | |
1852 | "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
1853 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
130d2d72 | 1854 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ |
1a94ca49 RK |
1855 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ |
1856 | "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
1857 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ | |
52a69200 | 1858 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} |
1a94ca49 RK |
1859 | |
1860 | /* How to renumber registers for dbx and gdb. */ | |
1861 | ||
1862 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1863 | ||
1864 | /* This is how to output the definition of a user-level label named NAME, | |
1865 | such as the label on a static function or variable NAME. */ | |
1866 | ||
1867 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1868 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1869 | ||
1870 | /* This is how to output a command to make the user-level label named NAME | |
1871 | defined for reference from other files. */ | |
1872 | ||
1873 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1874 | do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
1875 | ||
4e0c8ad2 | 1876 | /* The prefix to add to user-visible assembler symbols. */ |
1a94ca49 | 1877 | |
4e0c8ad2 | 1878 | #define USER_LABEL_PREFIX "" |
1a94ca49 RK |
1879 | |
1880 | /* This is how to output an internal numbered label where | |
1881 | PREFIX is the class of label and NUM is the number within the class. */ | |
1882 | ||
1883 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
531ea24e | 1884 | fprintf (FILE, "$%s%d:\n", PREFIX, NUM) |
1a94ca49 RK |
1885 | |
1886 | /* This is how to output a label for a jump table. Arguments are the same as | |
1887 | for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is | |
1888 | passed. */ | |
1889 | ||
1890 | #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ | |
1891 | { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } | |
1892 | ||
1893 | /* This is how to store into the string LABEL | |
1894 | the symbol_ref name of an internal numbered label where | |
1895 | PREFIX is the class of label and NUM is the number within the class. | |
1896 | This is suitable for output with `assemble_name'. */ | |
1897 | ||
1898 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
531ea24e | 1899 | sprintf (LABEL, "*$%s%d", PREFIX, NUM) |
1a94ca49 | 1900 | |
e247ca2a RK |
1901 | /* Check a floating-point value for validity for a particular machine mode. */ |
1902 | ||
1903 | #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \ | |
1904 | ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW)) | |
1905 | ||
1a94ca49 RK |
1906 | /* This is how to output an assembler line defining a `double' constant. */ |
1907 | ||
e99300f1 RS |
1908 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
1909 | { \ | |
1910 | if (REAL_VALUE_ISINF (VALUE) \ | |
1911 | || REAL_VALUE_ISNAN (VALUE) \ | |
1912 | || REAL_VALUE_MINUS_ZERO (VALUE)) \ | |
1913 | { \ | |
1914 | long t[2]; \ | |
1915 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
1916 | fprintf (FILE, "\t.quad 0x%lx%08lx\n", \ | |
1917 | t[1] & 0xffffffff, t[0] & 0xffffffff); \ | |
1918 | } \ | |
1919 | else \ | |
1920 | { \ | |
1921 | char str[30]; \ | |
1922 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \ | |
e5958492 | 1923 | fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \ |
e99300f1 RS |
1924 | } \ |
1925 | } | |
1a94ca49 RK |
1926 | |
1927 | /* This is how to output an assembler line defining a `float' constant. */ | |
1928 | ||
e247ca2a RK |
1929 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
1930 | do { \ | |
1931 | long t; \ | |
1932 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
1933 | fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \ | |
1934 | } while (0) | |
2700ac93 | 1935 | |
1a94ca49 RK |
1936 | /* This is how to output an assembler line defining an `int' constant. */ |
1937 | ||
1938 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
0076aa6b RK |
1939 | ( fprintf (FILE, "\t.long "), \ |
1940 | output_addr_const (FILE, (VALUE)), \ | |
1941 | fprintf (FILE, "\n")) | |
1a94ca49 RK |
1942 | |
1943 | /* This is how to output an assembler line defining a `long' constant. */ | |
1944 | ||
1945 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
1946 | ( fprintf (FILE, "\t.quad "), \ | |
1947 | output_addr_const (FILE, (VALUE)), \ | |
1948 | fprintf (FILE, "\n")) | |
1949 | ||
1950 | /* Likewise for `char' and `short' constants. */ | |
1951 | ||
1952 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
690ef02f | 1953 | fprintf (FILE, "\t.word %d\n", \ |
45c45e79 RK |
1954 | (GET_CODE (VALUE) == CONST_INT \ |
1955 | ? INTVAL (VALUE) & 0xffff : (abort (), 0))) | |
1a94ca49 RK |
1956 | |
1957 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
45c45e79 RK |
1958 | fprintf (FILE, "\t.byte %d\n", \ |
1959 | (GET_CODE (VALUE) == CONST_INT \ | |
1960 | ? INTVAL (VALUE) & 0xff : (abort (), 0))) | |
1a94ca49 RK |
1961 | |
1962 | /* We use the default ASCII-output routine, except that we don't write more | |
1963 | than 50 characters since the assembler doesn't support very long lines. */ | |
1964 | ||
1965 | #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ | |
1966 | do { \ | |
1967 | FILE *_hide_asm_out_file = (MYFILE); \ | |
1968 | unsigned char *_hide_p = (unsigned char *) (MYSTRING); \ | |
1969 | int _hide_thissize = (MYLENGTH); \ | |
1970 | int _size_so_far = 0; \ | |
1971 | { \ | |
1972 | FILE *asm_out_file = _hide_asm_out_file; \ | |
1973 | unsigned char *p = _hide_p; \ | |
1974 | int thissize = _hide_thissize; \ | |
1975 | int i; \ | |
1976 | fprintf (asm_out_file, "\t.ascii \""); \ | |
1977 | \ | |
1978 | for (i = 0; i < thissize; i++) \ | |
1979 | { \ | |
1980 | register int c = p[i]; \ | |
1981 | \ | |
1982 | if (_size_so_far ++ > 50 && i < thissize - 4) \ | |
1983 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ | |
1984 | \ | |
1985 | if (c == '\"' || c == '\\') \ | |
1986 | putc ('\\', asm_out_file); \ | |
1987 | if (c >= ' ' && c < 0177) \ | |
1988 | putc (c, asm_out_file); \ | |
1989 | else \ | |
1990 | { \ | |
1991 | fprintf (asm_out_file, "\\%o", c); \ | |
1992 | /* After an octal-escape, if a digit follows, \ | |
1993 | terminate one string constant and start another. \ | |
1994 | The Vax assembler fails to stop reading the escape \ | |
1995 | after three digits, so this is the only way we \ | |
1996 | can get it to parse the data properly. */ \ | |
1997 | if (i < thissize - 1 \ | |
1998 | && p[i + 1] >= '0' && p[i + 1] <= '9') \ | |
b2d5e311 | 1999 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ |
1a94ca49 RK |
2000 | } \ |
2001 | } \ | |
2002 | fprintf (asm_out_file, "\"\n"); \ | |
2003 | } \ | |
2004 | } \ | |
2005 | while (0) | |
52a69200 | 2006 | |
1a94ca49 RK |
2007 | /* This is how to output an insn to push a register on the stack. |
2008 | It need not be very fast code. */ | |
2009 | ||
2010 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
2011 | fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \ | |
2012 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2013 | (REGNO) & 31); | |
2014 | ||
2015 | /* This is how to output an insn to pop a register from the stack. | |
2016 | It need not be very fast code. */ | |
2017 | ||
2018 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
2019 | fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \ | |
2020 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2021 | (REGNO) & 31); | |
2022 | ||
2023 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2024 | ||
2025 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
45c45e79 | 2026 | fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff) |
1a94ca49 | 2027 | |
260ced47 RK |
2028 | /* This is how to output an element of a case-vector that is absolute. |
2029 | (Alpha does not use such vectors, but we must define this macro anyway.) */ | |
1a94ca49 | 2030 | |
260ced47 | 2031 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort () |
1a94ca49 | 2032 | |
260ced47 | 2033 | /* This is how to output an element of a case-vector that is relative. */ |
1a94ca49 | 2034 | |
33f7f353 | 2035 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
8dfe3c62 RH |
2036 | fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \ |
2037 | (VALUE)) | |
1a94ca49 RK |
2038 | |
2039 | /* This is how to output an assembler line | |
2040 | that says to advance the location counter | |
2041 | to a multiple of 2**LOG bytes. */ | |
2042 | ||
2043 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2044 | if ((LOG) != 0) \ | |
2045 | fprintf (FILE, "\t.align %d\n", LOG); | |
2046 | ||
2047 | /* This is how to advance the location counter by SIZE bytes. */ | |
2048 | ||
2049 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2050 | fprintf (FILE, "\t.space %d\n", (SIZE)) | |
2051 | ||
2052 | /* This says how to output an assembler line | |
2053 | to define a global common symbol. */ | |
2054 | ||
2055 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
2056 | ( fputs ("\t.comm ", (FILE)), \ | |
2057 | assemble_name ((FILE), (NAME)), \ | |
2058 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2059 | ||
2060 | /* This says how to output an assembler line | |
2061 | to define a local common symbol. */ | |
2062 | ||
2063 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ | |
2064 | ( fputs ("\t.lcomm ", (FILE)), \ | |
2065 | assemble_name ((FILE), (NAME)), \ | |
2066 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2067 | ||
2068 | /* Store in OUTPUT a string (made with alloca) containing | |
2069 | an assembler-name for a local static variable named NAME. | |
2070 | LABELNO is an integer which is different for each call. */ | |
2071 | ||
2072 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2073 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2074 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2075 | ||
2076 | /* Define the parentheses used to group arithmetic operations | |
2077 | in assembler code. */ | |
2078 | ||
2079 | #define ASM_OPEN_PAREN "(" | |
2080 | #define ASM_CLOSE_PAREN ")" | |
2081 | ||
60593797 RH |
2082 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2083 | Used for C++ multiple inheritance. */ | |
2084 | ||
2085 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ | |
2086 | do { \ | |
2087 | char *fn_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION)); \ | |
2088 | \ | |
2089 | fprintf (FILE, "\t.ent "); \ | |
2090 | assemble_name (FILE, alpha_function_name); \ | |
2091 | fputc ('\n', FILE); \ | |
2092 | ASM_OUTPUT_LABEL (FILE, alpha_function_name); \ | |
2093 | fprintf (FILE, "\tldgp $29,0($27)\n"); \ | |
2094 | fputc ('$', FILE); \ | |
2095 | assemble_name (FILE, alpha_function_name); \ | |
2096 | fprintf (FILE, "..ng:\n"); \ | |
2097 | fprintf (FILE, "\t.frame $30,0,$26,0\n"); \ | |
2098 | fprintf (FILE, "\t.prologue 1\n"); \ | |
2099 | \ | |
2100 | /* Rely on the assembler to macro expand a large delta. */ \ | |
2101 | fprintf (FILE, "\tlda $16,%ld($16)\n", (long)(DELTA)); \ | |
2102 | \ | |
2103 | if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \ | |
2104 | { \ | |
2105 | fprintf (FILE, "\tbr $31,$"); \ | |
2106 | assemble_name (FILE, fn_name); \ | |
2107 | fprintf (FILE, "..ng\n"); \ | |
2108 | } \ | |
2109 | else \ | |
2110 | { \ | |
2111 | fprintf (FILE, "\tlda $27,"); \ | |
2112 | assemble_name (FILE, fn_name); \ | |
2113 | fprintf (FILE, "\n\tjmp $31,($27),"); \ | |
2114 | assemble_name (FILE, fn_name); \ | |
2115 | fputc ('\n', FILE); \ | |
2116 | } \ | |
2117 | \ | |
2118 | fprintf (FILE, "\t.end "); \ | |
2119 | assemble_name (FILE, alpha_function_name); \ | |
2120 | fputc ('\n', FILE); \ | |
2121 | } while (0) | |
2122 | ||
2123 | \f | |
1a94ca49 RK |
2124 | /* Define results of standard character escape sequences. */ |
2125 | #define TARGET_BELL 007 | |
2126 | #define TARGET_BS 010 | |
2127 | #define TARGET_TAB 011 | |
2128 | #define TARGET_NEWLINE 012 | |
2129 | #define TARGET_VT 013 | |
2130 | #define TARGET_FF 014 | |
2131 | #define TARGET_CR 015 | |
2132 | ||
2133 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2134 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2135 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2136 | ||
2137 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2138 | ||
2139 | /* Determine which codes are valid without a following integer. These must | |
2bf6230d RK |
2140 | not be alphabetic (the characters are chosen so that |
2141 | PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when | |
2142 | using ASCII). | |
2143 | ||
2144 | & Generates fp-rounding mode suffix: nothing for normal, 'c' for | |
2145 | chopped, 'm' for minus-infinity, and 'd' for dynamic rounding | |
2146 | mode. alpha_fprm controls which suffix is generated. | |
2147 | ||
2148 | ' Generates trap-mode suffix for instructions that accept the | |
2149 | su suffix only (cmpt et al). | |
2150 | ||
0022a940 DMT |
2151 | ( Generates trap-mode suffix for instructions that accept the |
2152 | v, sv, and svi suffix. The only instruction that needs this | |
2153 | is cvttq. | |
2154 | ||
2bf6230d RK |
2155 | ) Generates trap-mode suffix for instructions that accept the |
2156 | u, su, and sui suffix. This is the bulk of the IEEE floating | |
2157 | point instructions (addt et al). | |
2158 | ||
2159 | + Generates trap-mode suffix for instructions that accept the | |
2160 | sui suffix (cvtqt and cvtqs). | |
e5958492 RK |
2161 | |
2162 | , Generates single precision suffix for floating point | |
2163 | instructions (s for IEEE, f for VAX) | |
2164 | ||
2165 | - Generates double precision suffix for floating point | |
2166 | instructions (t for IEEE, g for VAX) | |
2bf6230d | 2167 | */ |
1a94ca49 | 2168 | |
2bf6230d | 2169 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
0022a940 DMT |
2170 | ((CODE) == '&' || (CODE) == '\'' || (CODE) == '(' || (CODE) == ')' \ |
2171 | || (CODE) == '+' || (CODE) == ',' || (CODE) == '-') | |
1a94ca49 RK |
2172 | \f |
2173 | /* Print a memory address as an operand to reference that memory location. */ | |
2174 | ||
2175 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2176 | { rtx addr = (ADDR); \ | |
2177 | int basereg = 31; \ | |
2178 | HOST_WIDE_INT offset = 0; \ | |
2179 | \ | |
2180 | if (GET_CODE (addr) == AND) \ | |
2181 | addr = XEXP (addr, 0); \ | |
2182 | \ | |
2183 | if (GET_CODE (addr) == REG) \ | |
2184 | basereg = REGNO (addr); \ | |
2185 | else if (GET_CODE (addr) == CONST_INT) \ | |
2186 | offset = INTVAL (addr); \ | |
2187 | else if (GET_CODE (addr) == PLUS \ | |
2188 | && GET_CODE (XEXP (addr, 0)) == REG \ | |
2189 | && GET_CODE (XEXP (addr, 1)) == CONST_INT) \ | |
2190 | basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \ | |
2191 | else \ | |
2192 | abort (); \ | |
2193 | \ | |
2194 | fprintf (FILE, "%d($%d)", offset, basereg); \ | |
2195 | } | |
2196 | /* Define the codes that are matched by predicates in alpha.c. */ | |
2197 | ||
2198 | #define PREDICATE_CODES \ | |
2199 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
4a1d2a46 | 2200 | {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ |
1a94ca49 | 2201 | {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ |
9e2befc2 | 2202 | {"cint8_operand", {CONST_INT}}, \ |
1a94ca49 RK |
2203 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ |
2204 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2205 | {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2206 | {"const48_operand", {CONST_INT}}, \ | |
2207 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ | |
8395de26 | 2208 | {"or_operand", {SUBREG, REG, CONST_INT}}, \ |
1a94ca49 RK |
2209 | {"mode_mask_operand", {CONST_INT}}, \ |
2210 | {"mul8_operand", {CONST_INT}}, \ | |
2211 | {"mode_width_operand", {CONST_INT}}, \ | |
2212 | {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2213 | {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ | |
d1e03f31 | 2214 | {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ |
1a94ca49 | 2215 | {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ |
f8634644 | 2216 | {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ |
1a94ca49 | 2217 | {"fp0_operand", {CONST_DOUBLE}}, \ |
f8634644 | 2218 | {"current_file_function_operand", {SYMBOL_REF}}, \ |
ac030a7b | 2219 | {"call_operand", {REG, SYMBOL_REF}}, \ |
1a94ca49 RK |
2220 | {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
2221 | SYMBOL_REF, CONST, LABEL_REF}}, \ | |
4e26af5f RK |
2222 | {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
2223 | SYMBOL_REF, CONST, LABEL_REF}}, \ | |
1a94ca49 RK |
2224 | {"aligned_memory_operand", {MEM}}, \ |
2225 | {"unaligned_memory_operand", {MEM}}, \ | |
442b1685 | 2226 | {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ |
4ed43ff8 RH |
2227 | {"any_memory_operand", {MEM}}, \ |
2228 | {"hard_fp_register_operand", {SUBREG, REG}}, | |
03f8c4cc | 2229 | \f |
34fa88ab RK |
2230 | /* Tell collect that the object format is ECOFF. */ |
2231 | #define OBJECT_FORMAT_COFF | |
2232 | #define EXTENDED_COFF | |
2233 | ||
2234 | /* If we use NM, pass -g to it so it only lists globals. */ | |
2235 | #define NM_FLAGS "-pg" | |
2236 | ||
03f8c4cc RK |
2237 | /* Definitions for debugging. */ |
2238 | ||
2239 | #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ | |
2240 | #define DBX_DEBUGGING_INFO /* generate embedded stabs */ | |
2241 | #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ | |
2242 | ||
2243 | #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ | |
fe0986b4 | 2244 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG |
03f8c4cc RK |
2245 | #endif |
2246 | ||
2247 | ||
2248 | /* Correct the offset of automatic variables and arguments. Note that | |
2249 | the Alpha debug format wants all automatic variables and arguments | |
2250 | to be in terms of two different offsets from the virtual frame pointer, | |
2251 | which is the stack pointer before any adjustment in the function. | |
2252 | The offset for the argument pointer is fixed for the native compiler, | |
2253 | it is either zero (for the no arguments case) or large enough to hold | |
2254 | all argument registers. | |
2255 | The offset for the auto pointer is the fourth argument to the .frame | |
2256 | directive (local_offset). | |
2257 | To stay compatible with the native tools we use the same offsets | |
2258 | from the virtual frame pointer and adjust the debugger arg/auto offsets | |
2259 | accordingly. These debugger offsets are set up in output_prolog. */ | |
2260 | ||
9a0b18f2 RK |
2261 | extern long alpha_arg_offset; |
2262 | extern long alpha_auto_offset; | |
03f8c4cc RK |
2263 | #define DEBUGGER_AUTO_OFFSET(X) \ |
2264 | ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) | |
2265 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) | |
2266 | ||
2267 | ||
2268 | #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ | |
2269 | alpha_output_lineno (STREAM, LINE) | |
2270 | extern void alpha_output_lineno (); | |
2271 | ||
2272 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ | |
2273 | alpha_output_filename (STREAM, NAME) | |
2274 | extern void alpha_output_filename (); | |
2275 | ||
ab8b8941 RK |
2276 | /* mips-tfile.c limits us to strings of one page. */ |
2277 | #define DBX_CONTIN_LENGTH 4000 | |
03f8c4cc RK |
2278 | |
2279 | /* By default, turn on GDB extensions. */ | |
2280 | #define DEFAULT_GDB_EXTENSIONS 1 | |
2281 | ||
7aadc7c2 RK |
2282 | /* Stabs-in-ECOFF can't handle dbxout_function_end(). */ |
2283 | #define NO_DBX_FUNCTION_END 1 | |
2284 | ||
03f8c4cc RK |
2285 | /* If we are smuggling stabs through the ALPHA ECOFF object |
2286 | format, put a comment in front of the .stab<x> operation so | |
2287 | that the ALPHA assembler does not choke. The mips-tfile program | |
2288 | will correctly put the stab into the object file. */ | |
2289 | ||
2290 | #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs") | |
2291 | #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn") | |
2292 | #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd") | |
2293 | ||
2294 | /* Forward references to tags are allowed. */ | |
2295 | #define SDB_ALLOW_FORWARD_REFERENCES | |
2296 | ||
2297 | /* Unknown tags are also allowed. */ | |
2298 | #define SDB_ALLOW_UNKNOWN_REFERENCES | |
2299 | ||
2300 | #define PUT_SDB_DEF(a) \ | |
2301 | do { \ | |
2302 | fprintf (asm_out_file, "\t%s.def\t", \ | |
2303 | (TARGET_GAS) ? "" : "#"); \ | |
2304 | ASM_OUTPUT_LABELREF (asm_out_file, a); \ | |
2305 | fputc (';', asm_out_file); \ | |
2306 | } while (0) | |
2307 | ||
2308 | #define PUT_SDB_PLAIN_DEF(a) \ | |
2309 | do { \ | |
2310 | fprintf (asm_out_file, "\t%s.def\t.%s;", \ | |
2311 | (TARGET_GAS) ? "" : "#", (a)); \ | |
2312 | } while (0) | |
2313 | ||
2314 | #define PUT_SDB_TYPE(a) \ | |
2315 | do { \ | |
2316 | fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ | |
2317 | } while (0) | |
2318 | ||
2319 | /* For block start and end, we create labels, so that | |
2320 | later we can figure out where the correct offset is. | |
2321 | The normal .ent/.end serve well enough for functions, | |
2322 | so those are just commented out. */ | |
2323 | ||
2324 | extern int sdb_label_count; /* block start/end next label # */ | |
2325 | ||
2326 | #define PUT_SDB_BLOCK_START(LINE) \ | |
2327 | do { \ | |
2328 | fprintf (asm_out_file, \ | |
2329 | "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ | |
2330 | sdb_label_count, \ | |
2331 | (TARGET_GAS) ? "" : "#", \ | |
2332 | sdb_label_count, \ | |
2333 | (LINE)); \ | |
2334 | sdb_label_count++; \ | |
2335 | } while (0) | |
2336 | ||
2337 | #define PUT_SDB_BLOCK_END(LINE) \ | |
2338 | do { \ | |
2339 | fprintf (asm_out_file, \ | |
2340 | "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ | |
2341 | sdb_label_count, \ | |
2342 | (TARGET_GAS) ? "" : "#", \ | |
2343 | sdb_label_count, \ | |
2344 | (LINE)); \ | |
2345 | sdb_label_count++; \ | |
2346 | } while (0) | |
2347 | ||
2348 | #define PUT_SDB_FUNCTION_START(LINE) | |
2349 | ||
2350 | #define PUT_SDB_FUNCTION_END(LINE) | |
2351 | ||
2352 | #define PUT_SDB_EPILOGUE_END(NAME) | |
2353 | ||
03f8c4cc RK |
2354 | /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for |
2355 | mips-tdump.c to print them out. | |
2356 | ||
2357 | These must match the corresponding definitions in gdb/mipsread.c. | |
2358 | Unfortunately, gcc and gdb do not currently share any directories. */ | |
2359 | ||
2360 | #define CODE_MASK 0x8F300 | |
2361 | #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) | |
2362 | #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) | |
2363 | #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) | |
2364 | ||
2365 | /* Override some mips-tfile definitions. */ | |
2366 | ||
2367 | #define SHASH_SIZE 511 | |
2368 | #define THASH_SIZE 55 | |
1e6c6f11 RK |
2369 | |
2370 | /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ | |
2371 | ||
2372 | #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) | |
2f55b70b | 2373 | |
54190234 JM |
2374 | /* The linker will stick __main into the .init section. */ |
2375 | #define HAS_INIT_SECTION | |
68d69835 JM |
2376 | #define LD_INIT_SWITCH "-init" |
2377 | #define LD_FINI_SWITCH "-fini" | |
b0435cf4 RH |
2378 | |
2379 | /* The system headers under Alpha systems are generally C++-aware. */ | |
2380 | #define NO_IMPLICIT_EXTERN_C |