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1a94ca49 | 1 | /* Definitions of target machine for GNU compiler, for DEC Alpha. |
ca7cdae3 | 2 | Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc. |
1e6c6f11 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1a94ca49 RK |
4 | |
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
38ead7f3 RK |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
1a94ca49 RK |
21 | |
22 | ||
21798cd8 RK |
23 | /* Write out the correct language type definition for the header files. |
24 | Unless we have assembler language, write out the symbols for C. */ | |
1a94ca49 | 25 | #define CPP_SPEC "\ |
952fc2ed RH |
26 | %{!undef:\ |
27 | %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\ | |
28 | %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\ | |
29 | %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\ | |
30 | %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\ | |
31 | %{mieee:-D_IEEE_FP }\ | |
32 | %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\ | |
33 | %(cpp_cpu) %(cpp_subtarget)" | |
34 | ||
35 | #ifndef CPP_SUBTARGET_SPEC | |
36 | #define CPP_SUBTARGET_SPEC "" | |
37 | #endif | |
1a94ca49 RK |
38 | |
39 | /* Set the spec to use for signed char. The default tests the above macro | |
40 | but DEC's compiler can't handle the conditional in a "constant" | |
41 | operand. */ | |
42 | ||
43 | #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" | |
44 | ||
b890f297 JM |
45 | #define WORD_SWITCH_TAKES_ARG(STR) \ |
46 | (!strcmp (STR, "rpath") || !strcmp (STR, "include") \ | |
47 | || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \ | |
48 | || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \ | |
49 | || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \ | |
50 | || !strcmp (STR, "isystem")) | |
8877eb00 | 51 | |
1a94ca49 RK |
52 | /* Print subsidiary information on the compiler version in use. */ |
53 | #define TARGET_VERSION | |
54 | ||
1a94ca49 RK |
55 | /* Run-time compilation parameters selecting different hardware subsets. */ |
56 | ||
f6f6a13c RK |
57 | /* Which processor to schedule for. The cpu attribute defines a list that |
58 | mirrors this list, so changes to alpha.md must be made at the same time. */ | |
59 | ||
60 | enum processor_type | |
61 | {PROCESSOR_EV4, /* 2106[46]{a,} */ | |
e9a25f70 JL |
62 | PROCESSOR_EV5, /* 21164{a,pc,} */ |
63 | PROCESSOR_EV6}; /* 21264 */ | |
f6f6a13c RK |
64 | |
65 | extern enum processor_type alpha_cpu; | |
66 | ||
2bf6230d RK |
67 | enum alpha_trap_precision |
68 | { | |
69 | ALPHA_TP_PROG, /* No precision (default). */ | |
70 | ALPHA_TP_FUNC, /* Trap contained within originating function. */ | |
71 | ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ | |
72 | }; | |
73 | ||
74 | enum alpha_fp_rounding_mode | |
75 | { | |
76 | ALPHA_FPRM_NORM, /* Normal rounding mode. */ | |
77 | ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ | |
78 | ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ | |
79 | ALPHA_FPRM_DYN /* Dynamic rounding mode. */ | |
80 | }; | |
81 | ||
82 | enum alpha_fp_trap_mode | |
83 | { | |
84 | ALPHA_FPTM_N, /* Normal trap mode. */ | |
85 | ALPHA_FPTM_U, /* Underflow traps enabled. */ | |
86 | ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ | |
87 | ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ | |
88 | }; | |
89 | ||
1a94ca49 RK |
90 | extern int target_flags; |
91 | ||
2bf6230d RK |
92 | extern enum alpha_trap_precision alpha_tp; |
93 | extern enum alpha_fp_rounding_mode alpha_fprm; | |
94 | extern enum alpha_fp_trap_mode alpha_fptm; | |
95 | ||
1a94ca49 RK |
96 | /* This means that floating-point support exists in the target implementation |
97 | of the Alpha architecture. This is usually the default. */ | |
98 | ||
2bf6230d RK |
99 | #define MASK_FP 1 |
100 | #define TARGET_FP (target_flags & MASK_FP) | |
1a94ca49 RK |
101 | |
102 | /* This means that floating-point registers are allowed to be used. Note | |
103 | that Alpha implementations without FP operations are required to | |
104 | provide the FP registers. */ | |
105 | ||
2bf6230d RK |
106 | #define MASK_FPREGS 2 |
107 | #define TARGET_FPREGS (target_flags & MASK_FPREGS) | |
03f8c4cc RK |
108 | |
109 | /* This means that gas is used to process the assembler file. */ | |
110 | ||
111 | #define MASK_GAS 4 | |
112 | #define TARGET_GAS (target_flags & MASK_GAS) | |
1a94ca49 | 113 | |
2bf6230d RK |
114 | /* This means that we should mark procedures as IEEE conformant. */ |
115 | ||
116 | #define MASK_IEEE_CONFORMANT 8 | |
117 | #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) | |
118 | ||
119 | /* This means we should be IEEE-compliant except for inexact. */ | |
120 | ||
121 | #define MASK_IEEE 16 | |
122 | #define TARGET_IEEE (target_flags & MASK_IEEE) | |
123 | ||
124 | /* This means we should be fully IEEE-compliant. */ | |
125 | ||
126 | #define MASK_IEEE_WITH_INEXACT 32 | |
127 | #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) | |
128 | ||
803fee69 RK |
129 | /* This means we must construct all constants rather than emitting |
130 | them as literal data. */ | |
131 | ||
132 | #define MASK_BUILD_CONSTANTS 128 | |
133 | #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) | |
134 | ||
e5958492 RK |
135 | /* This means we handle floating points in VAX F- (float) |
136 | or G- (double) Format. */ | |
137 | ||
138 | #define MASK_FLOAT_VAX 512 | |
139 | #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) | |
140 | ||
e9a25f70 JL |
141 | /* This means that the processor has byte and half word loads and stores |
142 | (the BWX extension). */ | |
025f3281 | 143 | |
e9a25f70 JL |
144 | #define MASK_BWX 1024 |
145 | #define TARGET_BWX (target_flags & MASK_BWX) | |
025f3281 | 146 | |
e9a25f70 JL |
147 | /* This means that the processor has the CIX extension. */ |
148 | #define MASK_CIX 2048 | |
149 | #define TARGET_CIX (target_flags & MASK_CIX) | |
150 | ||
151 | /* This means that the processor has the MAX extension. */ | |
152 | #define MASK_MAX 4096 | |
153 | #define TARGET_MAX (target_flags & MASK_MAX) | |
154 | ||
155 | /* This means that the processor is an EV5, EV56, or PCA56. This is defined | |
156 | only in TARGET_CPU_DEFAULT. */ | |
157 | #define MASK_CPU_EV5 8192 | |
158 | ||
159 | /* Likewise for EV6. */ | |
160 | #define MASK_CPU_EV6 16384 | |
161 | ||
162 | /* This means we support the .arch directive in the assembler. Only | |
163 | defined in TARGET_CPU_DEFAULT. */ | |
164 | #define MASK_SUPPORT_ARCH 32768 | |
165 | #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) | |
8f87939b | 166 | |
9ba3994a RH |
167 | /* These are for target os support and cannot be changed at runtime. */ |
168 | #ifndef TARGET_WINDOWS_NT | |
169 | #define TARGET_WINDOWS_NT 0 | |
170 | #endif | |
171 | #ifndef TARGET_OPEN_VMS | |
172 | #define TARGET_OPEN_VMS 0 | |
173 | #endif | |
174 | ||
175 | #ifndef TARGET_AS_CAN_SUBTRACT_LABELS | |
176 | #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS | |
177 | #endif | |
9c0e94a5 RH |
178 | #ifndef TARGET_CAN_FAULT_IN_PROLOGUE |
179 | #define TARGET_CAN_FAULT_IN_PROLOGUE 0 | |
180 | #endif | |
9ba3994a | 181 | |
1a94ca49 RK |
182 | /* Macro to define tables used to set the flags. |
183 | This is a list in braces of pairs in braces, | |
184 | each pair being { "NAME", VALUE } | |
185 | where VALUE is the bits to set or minus the bits to clear. | |
186 | An empty string NAME is used to identify the default VALUE. */ | |
187 | ||
f8e52397 RH |
188 | #define TARGET_SWITCHES \ |
189 | { {"no-soft-float", MASK_FP, "Use hardware fp"}, \ | |
190 | {"soft-float", - MASK_FP, "Do not use hardware fp"}, \ | |
191 | {"fp-regs", MASK_FPREGS, "Use fp registers"}, \ | |
192 | {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \ | |
193 | {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \ | |
194 | {"gas", MASK_GAS, "Assume GAS"}, \ | |
195 | {"ieee-conformant", MASK_IEEE_CONFORMANT, \ | |
196 | "Request IEEE-conformant math library routines (OSF/1)"}, \ | |
197 | {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \ | |
198 | "Emit IEEE-conformant code, without inexact exceptions"}, \ | |
199 | {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \ | |
200 | "Emit IEEE-conformant code, with inexact exceptions"}, \ | |
201 | {"build-constants", MASK_BUILD_CONSTANTS, \ | |
202 | "Do not emit complex integer constants to read-only memory"}, \ | |
203 | {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \ | |
204 | {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \ | |
205 | {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \ | |
206 | {"no-bwx", -MASK_BWX, ""}, \ | |
207 | {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \ | |
208 | {"no-cix", -MASK_CIX, ""}, \ | |
209 | {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \ | |
210 | {"no-max", -MASK_MAX, ""}, \ | |
211 | {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} } | |
1a94ca49 | 212 | |
c01b5470 | 213 | #define TARGET_DEFAULT MASK_FP|MASK_FPREGS |
1a94ca49 | 214 | |
88681624 ILT |
215 | #ifndef TARGET_CPU_DEFAULT |
216 | #define TARGET_CPU_DEFAULT 0 | |
217 | #endif | |
218 | ||
2bf6230d RK |
219 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
220 | command options that have values. Its definition is an initializer | |
221 | with a subgrouping for each command option. | |
222 | ||
223 | Each subgrouping contains a string constant, that defines the fixed | |
224 | part of the option name, and the address of a variable. The | |
225 | variable, type `char *', is set to the variable part of the given | |
226 | option if the fixed part matches. The actual option name is made | |
227 | by appending `-m' to the specified name. | |
228 | ||
229 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
230 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
231 | will be set to the string `"512"'. | |
232 | ||
233 | extern char *m88k_short_data; | |
234 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
235 | ||
df45c7ea KG |
236 | extern const char *alpha_cpu_string; /* For -mcpu= */ |
237 | extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ | |
238 | extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ | |
239 | extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ | |
240 | extern const char *alpha_mlat_string; /* For -mmemory-latency= */ | |
2bf6230d | 241 | |
f8e52397 RH |
242 | #define TARGET_OPTIONS \ |
243 | { \ | |
244 | {"cpu=", &alpha_cpu_string, \ | |
245 | "Generate code for a given CPU"}, \ | |
246 | {"fp-rounding-mode=", &alpha_fprm_string, \ | |
247 | "Control the generated fp rounding mode"}, \ | |
248 | {"fp-trap-mode=", &alpha_fptm_string, \ | |
249 | "Control the IEEE trap mode"}, \ | |
250 | {"trap-precision=", &alpha_tp_string, \ | |
251 | "Control the precision given to fp exceptions"}, \ | |
252 | {"memory-latency=", &alpha_mlat_string, \ | |
253 | "Tune expected memory latency"}, \ | |
2bf6230d RK |
254 | } |
255 | ||
952fc2ed RH |
256 | /* Attempt to describe CPU characteristics to the preprocessor. */ |
257 | ||
258 | /* Corresponding to amask... */ | |
259 | #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)" | |
260 | #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)" | |
261 | #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)" | |
262 | ||
263 | /* Corresponding to implver... */ | |
264 | #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)" | |
265 | #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)" | |
266 | #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)" | |
267 | ||
268 | /* Common combinations. */ | |
269 | #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)" | |
270 | #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)" | |
271 | #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)" | |
272 | #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)" | |
273 | #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)" | |
274 | ||
275 | #ifndef CPP_CPU_DEFAULT_SPEC | |
276 | # if TARGET_CPU_DEFAULT & MASK_CPU_EV6 | |
277 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC | |
278 | # else | |
279 | # if TARGET_CPU_DEFAULT & MASK_CPU_EV5 | |
280 | # if TARGET_CPU_DEFAULT & MASK_MAX | |
281 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC | |
282 | # else | |
283 | # if TARGET_CPU_DEFAULT & MASK_BWX | |
284 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC | |
285 | # else | |
286 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC | |
287 | # endif | |
288 | # endif | |
289 | # else | |
290 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC | |
291 | # endif | |
292 | # endif | |
293 | #endif /* CPP_CPU_DEFAULT_SPEC */ | |
294 | ||
295 | #ifndef CPP_CPU_SPEC | |
296 | #define CPP_CPU_SPEC "\ | |
297 | %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \ | |
298 | %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\ | |
299 | %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\ | |
300 | %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\ | |
301 | %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\ | |
302 | %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\ | |
303 | %{!mcpu*:%(cpp_cpu_default) }}" | |
304 | #endif | |
305 | ||
306 | /* This macro defines names of additional specifications to put in the | |
307 | specs that can be used in various specifications like CC1_SPEC. Its | |
308 | definition is an initializer with a subgrouping for each command option. | |
309 | ||
310 | Each subgrouping contains a string constant, that defines the | |
311 | specification name, and a string constant that used by the GNU CC driver | |
312 | program. | |
313 | ||
314 | Do not define this macro if it does not need to do anything. */ | |
315 | ||
316 | #ifndef SUBTARGET_EXTRA_SPECS | |
317 | #define SUBTARGET_EXTRA_SPECS | |
318 | #endif | |
319 | ||
829245be KG |
320 | #define EXTRA_SPECS \ |
321 | { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \ | |
322 | { "cpp_am_max", CPP_AM_MAX_SPEC }, \ | |
323 | { "cpp_am_cix", CPP_AM_CIX_SPEC }, \ | |
324 | { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \ | |
325 | { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \ | |
326 | { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \ | |
327 | { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \ | |
328 | { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \ | |
329 | { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \ | |
330 | { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \ | |
331 | { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \ | |
332 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
333 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
334 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ | |
952fc2ed RH |
335 | SUBTARGET_EXTRA_SPECS |
336 | ||
337 | ||
2bf6230d RK |
338 | /* Sometimes certain combinations of command options do not make sense |
339 | on a particular target machine. You can define a macro | |
340 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
341 | defined, is executed once just after all the command options have | |
342 | been parsed. | |
343 | ||
344 | On the Alpha, it is used to translate target-option strings into | |
345 | numeric values. */ | |
346 | ||
347 | extern void override_options (); | |
348 | #define OVERRIDE_OPTIONS override_options () | |
349 | ||
350 | ||
1a94ca49 RK |
351 | /* Define this macro to change register usage conditional on target flags. |
352 | ||
353 | On the Alpha, we use this to disable the floating-point registers when | |
354 | they don't exist. */ | |
355 | ||
356 | #define CONDITIONAL_REGISTER_USAGE \ | |
357 | if (! TARGET_FPREGS) \ | |
52a69200 | 358 | for (i = 32; i < 63; i++) \ |
1a94ca49 RK |
359 | fixed_regs[i] = call_used_regs[i] = 1; |
360 | ||
4f074454 RK |
361 | /* Show we can debug even without a frame pointer. */ |
362 | #define CAN_DEBUG_WITHOUT_FP | |
1a94ca49 RK |
363 | \f |
364 | /* target machine storage layout */ | |
365 | ||
2700ac93 RS |
366 | /* Define to enable software floating point emulation. */ |
367 | #define REAL_ARITHMETIC | |
368 | ||
861bb6c1 JL |
369 | /* The following #defines are used when compiling the routines in |
370 | libgcc1.c. Since the Alpha calling conventions require single | |
371 | precision floats to be passed in the floating-point registers | |
372 | (rather than in the general registers) we have to build the | |
373 | libgcc1.c routines in such a way that they know the actual types | |
374 | of their formal arguments and the actual types of their return | |
375 | values. Otherwise, gcc will generate calls to the libgcc1.c | |
376 | routines, passing arguments in the floating-point registers, | |
377 | but the libgcc1.c routines will expect their arguments on the | |
378 | stack (where the Alpha calling conventions require structs & | |
379 | unions to be passed). */ | |
380 | ||
381 | #define FLOAT_VALUE_TYPE double | |
382 | #define INTIFY(FLOATVAL) (FLOATVAL) | |
383 | #define FLOATIFY(INTVAL) (INTVAL) | |
384 | #define FLOAT_ARG_TYPE double | |
385 | ||
1a94ca49 RK |
386 | /* Define the size of `int'. The default is the same as the word size. */ |
387 | #define INT_TYPE_SIZE 32 | |
388 | ||
389 | /* Define the size of `long long'. The default is the twice the word size. */ | |
390 | #define LONG_LONG_TYPE_SIZE 64 | |
391 | ||
392 | /* The two floating-point formats we support are S-floating, which is | |
393 | 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' | |
394 | and `long double' are T. */ | |
395 | ||
396 | #define FLOAT_TYPE_SIZE 32 | |
397 | #define DOUBLE_TYPE_SIZE 64 | |
398 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
399 | ||
5258d7ae RK |
400 | #define WCHAR_TYPE "unsigned int" |
401 | #define WCHAR_TYPE_SIZE 32 | |
1a94ca49 | 402 | |
13d39dbc | 403 | /* Define this macro if it is advisable to hold scalars in registers |
1a94ca49 RK |
404 | in a wider mode than that declared by the program. In such cases, |
405 | the value is constrained to be within the bounds of the declared | |
406 | type, but kept valid in the wider mode. The signedness of the | |
407 | extension may differ from that of the type. | |
408 | ||
409 | For Alpha, we always store objects in a full register. 32-bit objects | |
410 | are always sign-extended, but smaller objects retain their signedness. */ | |
411 | ||
412 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
413 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
414 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
415 | { \ | |
416 | if ((MODE) == SImode) \ | |
417 | (UNSIGNEDP) = 0; \ | |
418 | (MODE) = DImode; \ | |
419 | } | |
420 | ||
421 | /* Define this if function arguments should also be promoted using the above | |
422 | procedure. */ | |
423 | ||
424 | #define PROMOTE_FUNCTION_ARGS | |
425 | ||
426 | /* Likewise, if the function return value is promoted. */ | |
427 | ||
428 | #define PROMOTE_FUNCTION_RETURN | |
429 | ||
430 | /* Define this if most significant bit is lowest numbered | |
431 | in instructions that operate on numbered bit-fields. | |
432 | ||
433 | There are no such instructions on the Alpha, but the documentation | |
434 | is little endian. */ | |
435 | #define BITS_BIG_ENDIAN 0 | |
436 | ||
437 | /* Define this if most significant byte of a word is the lowest numbered. | |
438 | This is false on the Alpha. */ | |
439 | #define BYTES_BIG_ENDIAN 0 | |
440 | ||
441 | /* Define this if most significant word of a multiword number is lowest | |
442 | numbered. | |
443 | ||
444 | For Alpha we can decide arbitrarily since there are no machine instructions | |
445 | for them. Might as well be consistent with bytes. */ | |
446 | #define WORDS_BIG_ENDIAN 0 | |
447 | ||
448 | /* number of bits in an addressable storage unit */ | |
449 | #define BITS_PER_UNIT 8 | |
450 | ||
451 | /* Width in bits of a "word", which is the contents of a machine register. | |
452 | Note that this is not necessarily the width of data type `int'; | |
453 | if using 16-bit ints on a 68000, this would still be 32. | |
454 | But on a machine with 16-bit registers, this would be 16. */ | |
455 | #define BITS_PER_WORD 64 | |
456 | ||
457 | /* Width of a word, in units (bytes). */ | |
458 | #define UNITS_PER_WORD 8 | |
459 | ||
460 | /* Width in bits of a pointer. | |
461 | See also the macro `Pmode' defined below. */ | |
462 | #define POINTER_SIZE 64 | |
463 | ||
464 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
465 | #define PARM_BOUNDARY 64 | |
466 | ||
467 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
468 | #define STACK_BOUNDARY 64 | |
469 | ||
470 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9c0e94a5 | 471 | #define FUNCTION_BOUNDARY 256 |
1a94ca49 RK |
472 | |
473 | /* Alignment of field after `int : 0' in a structure. */ | |
474 | #define EMPTY_FIELD_BOUNDARY 64 | |
475 | ||
476 | /* Every structure's size must be a multiple of this. */ | |
477 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
478 | ||
479 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
480 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
481 | ||
65823178 RK |
482 | /* Align loop starts for optimal branching. |
483 | ||
484 | ??? Kludge this and the next macro for the moment by not doing anything if | |
485 | we don't optimize and also if we are writing ECOFF symbols to work around | |
486 | a bug in DEC's assembler. */ | |
1a94ca49 | 487 | |
fc470718 | 488 | #define LOOP_ALIGN(LABEL) \ |
9c0e94a5 | 489 | (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0) |
1a94ca49 | 490 | |
9c0e94a5 RH |
491 | /* This is how to align an instruction for optimal branching. On |
492 | Alpha we'll get better performance by aligning on an octaword | |
1a94ca49 | 493 | boundary. */ |
130d2d72 | 494 | |
7d0bfbd0 | 495 | #define LABEL_ALIGN_AFTER_BARRIER(FILE) \ |
9c0e94a5 | 496 | (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0) |
1a94ca49 RK |
497 | |
498 | /* No data type wants to be aligned rounder than this. */ | |
499 | #define BIGGEST_ALIGNMENT 64 | |
500 | ||
d16fe557 RK |
501 | /* For atomic access to objects, must have at least 32-bit alignment |
502 | unless the machine has byte operations. */ | |
e9a25f70 | 503 | #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32) |
d16fe557 | 504 | |
442b1685 RK |
505 | /* Align all constants and variables to at least a word boundary so |
506 | we can pick up pieces of them faster. */ | |
6c174fc0 RH |
507 | /* ??? Only if block-move stuff knows about different source/destination |
508 | alignment. */ | |
509 | #if 0 | |
442b1685 RK |
510 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) |
511 | #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) | |
6c174fc0 | 512 | #endif |
1a94ca49 RK |
513 | |
514 | /* Set this non-zero if move instructions will actually fail to work | |
515 | when given unaligned data. | |
516 | ||
517 | Since we get an error message when we do one, call them invalid. */ | |
518 | ||
519 | #define STRICT_ALIGNMENT 1 | |
520 | ||
521 | /* Set this non-zero if unaligned move instructions are extremely slow. | |
522 | ||
523 | On the Alpha, they trap. */ | |
130d2d72 RK |
524 | |
525 | #define SLOW_UNALIGNED_ACCESS 1 | |
1a94ca49 RK |
526 | \f |
527 | /* Standard register usage. */ | |
528 | ||
529 | /* Number of actual hardware registers. | |
530 | The hardware registers are assigned numbers for the compiler | |
531 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
532 | All registers that the compiler knows about must be given numbers, | |
533 | even those that are not normally considered general registers. | |
534 | ||
535 | We define all 32 integer registers, even though $31 is always zero, | |
536 | and all 32 floating-point registers, even though $f31 is also | |
537 | always zero. We do not bother defining the FP status register and | |
130d2d72 RK |
538 | there are no other registers. |
539 | ||
540 | Since $31 is always zero, we will use register number 31 as the | |
541 | argument pointer. It will never appear in the generated code | |
542 | because we will always be eliminating it in favor of the stack | |
52a69200 RK |
543 | pointer or hardware frame pointer. |
544 | ||
545 | Likewise, we use $f31 for the frame pointer, which will always | |
546 | be eliminated in favor of the hardware frame pointer or the | |
547 | stack pointer. */ | |
1a94ca49 RK |
548 | |
549 | #define FIRST_PSEUDO_REGISTER 64 | |
550 | ||
551 | /* 1 for registers that have pervasive standard uses | |
552 | and are not available for the register allocator. */ | |
553 | ||
554 | #define FIXED_REGISTERS \ | |
555 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
556 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ | |
557 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
558 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
559 | ||
560 | /* 1 for registers not available across function calls. | |
561 | These must include the FIXED_REGISTERS and also any | |
562 | registers that can be used without being saved. | |
563 | The latter must include the registers where values are returned | |
564 | and the register where structure-value addresses are passed. | |
565 | Aside from that, you can include as many other registers as you like. */ | |
566 | #define CALL_USED_REGISTERS \ | |
567 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ | |
568 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ | |
569 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
570 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
571 | ||
572 | /* List the order in which to allocate registers. Each register must be | |
573 | listed once, even those in FIXED_REGISTERS. | |
574 | ||
575 | We allocate in the following order: | |
2c4be73e | 576 | $f10-$f15 (nonsaved floating-point register) |
1a94ca49 RK |
577 | $f22-$f30 (likewise) |
578 | $f21-$f16 (likewise, but input args) | |
579 | $f0 (nonsaved, but return value) | |
2c4be73e | 580 | $f1 (nonsaved, but immediate before saved) |
1a94ca49 RK |
581 | $f2-$f9 (saved floating-point registers) |
582 | $1-$8 (nonsaved integer registers) | |
583 | $22-$25 (likewise) | |
584 | $28 (likewise) | |
585 | $0 (likewise, but return value) | |
586 | $21-$16 (likewise, but input args) | |
0076aa6b | 587 | $27 (procedure value in OSF, nonsaved in NT) |
1a94ca49 RK |
588 | $9-$14 (saved integer registers) |
589 | $26 (return PC) | |
590 | $15 (frame pointer) | |
591 | $29 (global pointer) | |
52a69200 | 592 | $30, $31, $f31 (stack pointer and always zero/ap & fp) */ |
1a94ca49 RK |
593 | |
594 | #define REG_ALLOC_ORDER \ | |
2c4be73e | 595 | {42, 43, 44, 45, 46, 47, \ |
1a94ca49 RK |
596 | 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
597 | 53, 52, 51, 50, 49, 48, \ | |
2c4be73e | 598 | 32, 33, \ |
1a94ca49 RK |
599 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
600 | 1, 2, 3, 4, 5, 6, 7, 8, \ | |
601 | 22, 23, 24, 25, \ | |
602 | 28, \ | |
603 | 0, \ | |
604 | 21, 20, 19, 18, 17, 16, \ | |
605 | 27, \ | |
606 | 9, 10, 11, 12, 13, 14, \ | |
607 | 26, \ | |
608 | 15, \ | |
609 | 29, \ | |
610 | 30, 31, 63 } | |
611 | ||
612 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
613 | to hold something of mode MODE. | |
614 | This is ordinarily the length in words of a value of mode MODE | |
615 | but can be less for certain modes in special long registers. */ | |
616 | ||
617 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
618 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
619 | ||
620 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
621 | On Alpha, the integer registers can hold any mode. The floating-point | |
622 | registers can hold 32-bit and 64-bit integers as well, but not 16-bit | |
a7adf08e | 623 | or 8-bit values. */ |
1a94ca49 | 624 | |
e6a8ebb4 RH |
625 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
626 | ((REGNO) >= 32 && (REGNO) <= 62 \ | |
627 | ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \ | |
628 | : 1) | |
629 | ||
630 | /* A C expression that is nonzero if a value of mode | |
631 | MODE1 is accessible in mode MODE2 without copying. | |
1a94ca49 | 632 | |
e6a8ebb4 RH |
633 | This asymmetric test is true when MODE1 could be put |
634 | in an FP register but MODE2 could not. */ | |
1a94ca49 | 635 | |
a7adf08e | 636 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
e6a8ebb4 RH |
637 | (HARD_REGNO_MODE_OK (32, (MODE1)) \ |
638 | ? HARD_REGNO_MODE_OK (32, (MODE2)) \ | |
a7adf08e | 639 | : 1) |
1a94ca49 RK |
640 | |
641 | /* Specify the registers used for certain standard purposes. | |
642 | The values of these macros are register numbers. */ | |
643 | ||
644 | /* Alpha pc isn't overloaded on a register that the compiler knows about. */ | |
645 | /* #define PC_REGNUM */ | |
646 | ||
647 | /* Register to use for pushing function arguments. */ | |
648 | #define STACK_POINTER_REGNUM 30 | |
649 | ||
650 | /* Base register for access to local variables of the function. */ | |
52a69200 | 651 | #define HARD_FRAME_POINTER_REGNUM 15 |
1a94ca49 RK |
652 | |
653 | /* Value should be nonzero if functions must have frame pointers. | |
654 | Zero means the frame pointer need not be set up (and parms | |
655 | may be accessed via the stack pointer) in functions that seem suitable. | |
656 | This is computed in `reload', in reload1.c. */ | |
657 | #define FRAME_POINTER_REQUIRED 0 | |
658 | ||
659 | /* Base register for access to arguments of the function. */ | |
130d2d72 | 660 | #define ARG_POINTER_REGNUM 31 |
1a94ca49 | 661 | |
52a69200 RK |
662 | /* Base register for access to local variables of function. */ |
663 | #define FRAME_POINTER_REGNUM 63 | |
664 | ||
1a94ca49 RK |
665 | /* Register in which static-chain is passed to a function. |
666 | ||
667 | For the Alpha, this is based on an example; the calling sequence | |
668 | doesn't seem to specify this. */ | |
669 | #define STATIC_CHAIN_REGNUM 1 | |
670 | ||
671 | /* Register in which address to store a structure value | |
672 | arrives in the function. On the Alpha, the address is passed | |
673 | as a hidden argument. */ | |
674 | #define STRUCT_VALUE 0 | |
675 | \f | |
676 | /* Define the classes of registers for register constraints in the | |
677 | machine description. Also define ranges of constants. | |
678 | ||
679 | One of the classes must always be named ALL_REGS and include all hard regs. | |
680 | If there is more than one class, another class must be named NO_REGS | |
681 | and contain no registers. | |
682 | ||
683 | The name GENERAL_REGS must be the name of a class (or an alias for | |
684 | another name such as ALL_REGS). This is the class of registers | |
685 | that is allowed by "g" or "r" in a register constraint. | |
686 | Also, registers outside this class are allocated only when | |
687 | instructions express preferences for them. | |
688 | ||
689 | The classes must be numbered in nondecreasing order; that is, | |
690 | a larger-numbered class must never be contained completely | |
691 | in a smaller-numbered class. | |
692 | ||
693 | For any two classes, it is very desirable that there be another | |
694 | class that represents their union. */ | |
695 | ||
696 | enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS, | |
697 | LIM_REG_CLASSES }; | |
698 | ||
699 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
700 | ||
701 | /* Give names of register classes as strings for dump file. */ | |
702 | ||
703 | #define REG_CLASS_NAMES \ | |
704 | {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } | |
705 | ||
706 | /* Define which registers fit in which classes. | |
707 | This is an initializer for a vector of HARD_REG_SET | |
708 | of length N_REG_CLASSES. */ | |
709 | ||
710 | #define REG_CLASS_CONTENTS \ | |
52a69200 | 711 | { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} } |
1a94ca49 RK |
712 | |
713 | /* The same information, inverted: | |
714 | Return the class number of the smallest class containing | |
715 | reg number REGNO. This could be a conditional expression | |
716 | or could index an array. */ | |
717 | ||
52a69200 RK |
718 | #define REGNO_REG_CLASS(REGNO) \ |
719 | ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS) | |
1a94ca49 RK |
720 | |
721 | /* The class value for index registers, and the one for base regs. */ | |
722 | #define INDEX_REG_CLASS NO_REGS | |
723 | #define BASE_REG_CLASS GENERAL_REGS | |
724 | ||
725 | /* Get reg_class from a letter such as appears in the machine description. */ | |
726 | ||
727 | #define REG_CLASS_FROM_LETTER(C) \ | |
728 | ((C) == 'f' ? FLOAT_REGS : NO_REGS) | |
729 | ||
730 | /* Define this macro to change register usage conditional on target flags. */ | |
731 | /* #define CONDITIONAL_REGISTER_USAGE */ | |
732 | ||
733 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
734 | can be used to stand for particular ranges of immediate operands. | |
735 | This macro defines what the ranges are. | |
736 | C is the letter, and VALUE is a constant value. | |
737 | Return 1 if VALUE is in the range specified by C. | |
738 | ||
739 | For Alpha: | |
740 | `I' is used for the range of constants most insns can contain. | |
741 | `J' is the constant zero. | |
742 | `K' is used for the constant in an LDA insn. | |
743 | `L' is used for the constant in a LDAH insn. | |
744 | `M' is used for the constants that can be AND'ed with using a ZAP insn. | |
745 | `N' is used for complemented 8-bit constants. | |
746 | `O' is used for negated 8-bit constants. | |
747 | `P' is used for the constants 1, 2 and 3. */ | |
748 | ||
749 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
750 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \ | |
751 | : (C) == 'J' ? (VALUE) == 0 \ | |
752 | : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
753 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ | |
c905c108 | 754 | && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \ |
1a94ca49 RK |
755 | : (C) == 'M' ? zap_mask (VALUE) \ |
756 | : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \ | |
757 | : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \ | |
758 | : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \ | |
759 | : 0) | |
760 | ||
761 | /* Similar, but for floating or large integer constants, and defining letters | |
762 | G and H. Here VALUE is the CONST_DOUBLE rtx itself. | |
763 | ||
764 | For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE | |
765 | that is the operand of a ZAP insn. */ | |
766 | ||
767 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
768 | ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ | |
769 | && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ | |
770 | : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \ | |
771 | && zap_mask (CONST_DOUBLE_LOW (VALUE)) \ | |
772 | && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \ | |
773 | : 0) | |
774 | ||
e560f226 RK |
775 | /* Optional extra constraints for this machine. |
776 | ||
777 | For the Alpha, `Q' means that this is a memory operand but not a | |
ac030a7b | 778 | reference to an unaligned location. |
9ec36da5 | 779 | |
ac030a7b | 780 | `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current |
9ec36da5 JL |
781 | function. |
782 | ||
783 | 'S' is a 6-bit constant (valid for a shift insn). */ | |
e560f226 RK |
784 | |
785 | #define EXTRA_CONSTRAINT(OP, C) \ | |
ab87f8c8 | 786 | ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \ |
9ec36da5 JL |
787 | : (C) == 'R' ? current_file_function_operand (OP, Pmode) \ |
788 | : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ | |
789 | && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \ | |
e560f226 | 790 | : 0) |
df45c7ea | 791 | extern int normal_memory_operand (); |
e560f226 | 792 | |
1a94ca49 RK |
793 | /* Given an rtx X being reloaded into a reg required to be |
794 | in class CLASS, return the class of reg to actually use. | |
795 | In general this is just CLASS; but on some machines | |
796 | in some cases it is preferable to use a more restrictive class. | |
797 | ||
798 | On the Alpha, all constants except zero go into a floating-point | |
799 | register via memory. */ | |
800 | ||
801 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
802 | (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \ | |
a6a503ed | 803 | ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\ |
1a94ca49 RK |
804 | : (CLASS)) |
805 | ||
806 | /* Loading and storing HImode or QImode values to and from memory | |
807 | usually requires a scratch register. The exceptions are loading | |
e008606e RK |
808 | QImode and HImode from an aligned address to a general register |
809 | unless byte instructions are permitted. | |
ddd5a7c1 | 810 | We also cannot load an unaligned address or a paradoxical SUBREG into an |
e868b518 | 811 | FP register. */ |
1a94ca49 RK |
812 | |
813 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ | |
814 | (((GET_CODE (IN) == MEM \ | |
815 | || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \ | |
816 | || (GET_CODE (IN) == SUBREG \ | |
817 | && (GET_CODE (SUBREG_REG (IN)) == MEM \ | |
818 | || (GET_CODE (SUBREG_REG (IN)) == REG \ | |
819 | && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \ | |
820 | && (((CLASS) == FLOAT_REGS \ | |
821 | && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \ | |
822 | || (((MODE) == QImode || (MODE) == HImode) \ | |
4e46365b | 823 | && ! TARGET_BWX && ! aligned_memory_operand (IN, MODE)))) \ |
e560f226 RK |
824 | ? GENERAL_REGS \ |
825 | : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \ | |
826 | && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \ | |
e868b518 RK |
827 | : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \ |
828 | && (GET_MODE_SIZE (GET_MODE (IN)) \ | |
829 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \ | |
e560f226 | 830 | : NO_REGS) |
1a94ca49 RK |
831 | |
832 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ | |
833 | (((GET_CODE (OUT) == MEM \ | |
834 | || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \ | |
835 | || (GET_CODE (OUT) == SUBREG \ | |
836 | && (GET_CODE (SUBREG_REG (OUT)) == MEM \ | |
837 | || (GET_CODE (SUBREG_REG (OUT)) == REG \ | |
838 | && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \ | |
956d6950 JL |
839 | && ((((MODE) == HImode || (MODE) == QImode) \ |
840 | && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \ | |
841 | || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \ | |
e560f226 RK |
842 | ? GENERAL_REGS \ |
843 | : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \ | |
844 | && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \ | |
e868b518 RK |
845 | : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \ |
846 | && (GET_MODE_SIZE (GET_MODE (OUT)) \ | |
847 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \ | |
848 | : NO_REGS) | |
1a94ca49 RK |
849 | |
850 | /* If we are copying between general and FP registers, we need a memory | |
e9a25f70 | 851 | location unless the CIX extension is available. */ |
1a94ca49 | 852 | |
e9a25f70 JL |
853 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
854 | (! TARGET_CIX && (CLASS1) != (CLASS2)) | |
1a94ca49 | 855 | |
acd94aaf RK |
856 | /* Specify the mode to be used for memory when a secondary memory |
857 | location is needed. If MODE is floating-point, use it. Otherwise, | |
858 | widen to a word like the default. This is needed because we always | |
859 | store integers in FP registers in quadword format. This whole | |
860 | area is very tricky! */ | |
861 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
862 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ | |
e868b518 | 863 | : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ |
acd94aaf RK |
864 | : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) |
865 | ||
1a94ca49 RK |
866 | /* Return the maximum number of consecutive registers |
867 | needed to represent mode MODE in a register of class CLASS. */ | |
868 | ||
869 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
870 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
871 | ||
c31dfe4d RK |
872 | /* If defined, gives a class of registers that cannot be used as the |
873 | operand of a SUBREG that changes the size of the object. */ | |
874 | ||
875 | #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS | |
876 | ||
1a94ca49 RK |
877 | /* Define the cost of moving between registers of various classes. Moving |
878 | between FLOAT_REGS and anything else except float regs is expensive. | |
879 | In fact, we make it quite expensive because we really don't want to | |
880 | do these moves unless it is clearly worth it. Optimizations may | |
881 | reduce the impact of not being able to allocate a pseudo to a | |
882 | hard register. */ | |
883 | ||
71d9b493 RH |
884 | #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ |
885 | (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ | |
886 | ? 2 \ | |
887 | : TARGET_CIX ? 3 : 4+2*alpha_memory_latency) | |
1a94ca49 RK |
888 | |
889 | /* A C expressions returning the cost of moving data of MODE from a register to | |
890 | or from memory. | |
891 | ||
892 | On the Alpha, bump this up a bit. */ | |
893 | ||
bcbbac26 | 894 | extern int alpha_memory_latency; |
cbd5b9a2 | 895 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) |
1a94ca49 RK |
896 | |
897 | /* Provide the cost of a branch. Exact meaning under development. */ | |
898 | #define BRANCH_COST 5 | |
899 | ||
900 | /* Adjust the cost of dependencies. */ | |
901 | ||
902 | #define ADJUST_COST(INSN,LINK,DEP,COST) \ | |
903 | (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST) | |
904 | \f | |
905 | /* Stack layout; function entry, exit and calling. */ | |
906 | ||
907 | /* Define this if pushing a word on the stack | |
908 | makes the stack pointer a smaller address. */ | |
909 | #define STACK_GROWS_DOWNWARD | |
910 | ||
911 | /* Define this if the nominal address of the stack frame | |
912 | is at the high-address end of the local variables; | |
913 | that is, each additional local variable allocated | |
914 | goes at a more negative offset in the frame. */ | |
130d2d72 | 915 | /* #define FRAME_GROWS_DOWNWARD */ |
1a94ca49 RK |
916 | |
917 | /* Offset within stack frame to start allocating local variables at. | |
918 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
919 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
920 | of the first local allocated. */ | |
921 | ||
52a69200 | 922 | #define STARTING_FRAME_OFFSET 0 |
1a94ca49 RK |
923 | |
924 | /* If we generate an insn to push BYTES bytes, | |
925 | this says how many the stack pointer really advances by. | |
926 | On Alpha, don't define this because there are no push insns. */ | |
927 | /* #define PUSH_ROUNDING(BYTES) */ | |
928 | ||
e008606e RK |
929 | /* Define this to be nonzero if stack checking is built into the ABI. */ |
930 | #define STACK_CHECK_BUILTIN 1 | |
931 | ||
1a94ca49 RK |
932 | /* Define this if the maximum size of all the outgoing args is to be |
933 | accumulated and pushed during the prologue. The amount can be | |
934 | found in the variable current_function_outgoing_args_size. */ | |
935 | #define ACCUMULATE_OUTGOING_ARGS | |
936 | ||
937 | /* Offset of first parameter from the argument pointer register value. */ | |
938 | ||
130d2d72 | 939 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
1a94ca49 RK |
940 | |
941 | /* Definitions for register eliminations. | |
942 | ||
978e8952 | 943 | We have two registers that can be eliminated on the Alpha. First, the |
1a94ca49 | 944 | frame pointer register can often be eliminated in favor of the stack |
130d2d72 RK |
945 | pointer register. Secondly, the argument pointer register can always be |
946 | eliminated; it is replaced with either the stack or frame pointer. */ | |
1a94ca49 RK |
947 | |
948 | /* This is an array of structures. Each structure initializes one pair | |
949 | of eliminable registers. The "from" register number is given first, | |
950 | followed by "to". Eliminations of the same "from" register are listed | |
951 | in order of preference. */ | |
952 | ||
52a69200 RK |
953 | #define ELIMINABLE_REGS \ |
954 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
955 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
956 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
957 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1a94ca49 RK |
958 | |
959 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
960 | Frame pointer elimination is automatically handled. | |
961 | ||
130d2d72 | 962 | All eliminations are valid since the cases where FP can't be |
1a94ca49 RK |
963 | eliminated are already handled. */ |
964 | ||
130d2d72 | 965 | #define CAN_ELIMINATE(FROM, TO) 1 |
1a94ca49 | 966 | |
52a69200 RK |
967 | /* Round up to a multiple of 16 bytes. */ |
968 | #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) | |
969 | ||
1a94ca49 RK |
970 | /* Define the offset between two registers, one to be eliminated, and the other |
971 | its replacement, at the start of a routine. */ | |
972 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
52a69200 RK |
973 | { if ((FROM) == FRAME_POINTER_REGNUM) \ |
974 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
975 | + alpha_sa_size ()); \ | |
976 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
977 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
978 | + alpha_sa_size () \ | |
d772039b RK |
979 | + (ALPHA_ROUND (get_frame_size () \ |
980 | + current_function_pretend_args_size) \ | |
981 | - current_function_pretend_args_size)); \ | |
1a94ca49 RK |
982 | } |
983 | ||
984 | /* Define this if stack space is still allocated for a parameter passed | |
985 | in a register. */ | |
986 | /* #define REG_PARM_STACK_SPACE */ | |
987 | ||
988 | /* Value is the number of bytes of arguments automatically | |
989 | popped when returning from a subroutine call. | |
8b109b37 | 990 | FUNDECL is the declaration node of the function (as a tree), |
1a94ca49 RK |
991 | FUNTYPE is the data type of the function (as a tree), |
992 | or for a library call it is an identifier node for the subroutine name. | |
993 | SIZE is the number of bytes of arguments passed on the stack. */ | |
994 | ||
8b109b37 | 995 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1a94ca49 RK |
996 | |
997 | /* Define how to find the value returned by a function. | |
998 | VALTYPE is the data type of the value (as a tree). | |
999 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
1000 | otherwise, FUNC is 0. | |
1001 | ||
1002 | On Alpha the value is found in $0 for integer functions and | |
1003 | $f0 for floating-point functions. */ | |
1004 | ||
4c020733 RH |
1005 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
1006 | gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \ | |
1007 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
1008 | || POINTER_TYPE_P (VALTYPE)) \ | |
1009 | ? word_mode : TYPE_MODE (VALTYPE), \ | |
1010 | ((TARGET_FPREGS \ | |
1011 | && (TREE_CODE (VALTYPE) == REAL_TYPE \ | |
1012 | || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ | |
1013 | ? 32 : 0)) | |
1a94ca49 RK |
1014 | |
1015 | /* Define how to find the value returned by a library function | |
1016 | assuming the value has mode MODE. */ | |
1017 | ||
4c020733 RH |
1018 | #define LIBCALL_VALUE(MODE) \ |
1019 | gen_rtx_REG (MODE, \ | |
1020 | (TARGET_FPREGS \ | |
1021 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
1022 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ | |
1023 | ? 32 : 0)) | |
1a94ca49 | 1024 | |
130d2d72 RK |
1025 | /* The definition of this macro implies that there are cases where |
1026 | a scalar value cannot be returned in registers. | |
1027 | ||
1028 | For the Alpha, any structure or union type is returned in memory, as | |
1029 | are integers whose size is larger than 64 bits. */ | |
1030 | ||
1031 | #define RETURN_IN_MEMORY(TYPE) \ | |
e14fa9c4 | 1032 | (TYPE_MODE (TYPE) == BLKmode \ |
130d2d72 RK |
1033 | || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) |
1034 | ||
1a94ca49 RK |
1035 | /* 1 if N is a possible register number for a function value |
1036 | as seen by the caller. */ | |
1037 | ||
e5958492 RK |
1038 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1039 | ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) | |
1a94ca49 RK |
1040 | |
1041 | /* 1 if N is a possible register number for function argument passing. | |
1042 | On Alpha, these are $16-$21 and $f16-$f21. */ | |
1043 | ||
1044 | #define FUNCTION_ARG_REGNO_P(N) \ | |
1045 | (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) | |
1046 | \f | |
1047 | /* Define a data type for recording info about an argument list | |
1048 | during the scan of that argument list. This data type should | |
1049 | hold all necessary information about the function itself | |
1050 | and about the args processed so far, enough to enable macros | |
1051 | such as FUNCTION_ARG to determine where the next arg should go. | |
1052 | ||
1053 | On Alpha, this is a single integer, which is a number of words | |
1054 | of arguments scanned so far. | |
1055 | Thus 6 or more means all following args should go on the stack. */ | |
1056 | ||
1057 | #define CUMULATIVE_ARGS int | |
1058 | ||
1059 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1060 | for a call to a function whose data type is FNTYPE. | |
1061 | For a library call, FNTYPE is 0. */ | |
1062 | ||
2c7ee1a6 | 1063 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0 |
1a94ca49 RK |
1064 | |
1065 | /* Define intermediate macro to compute the size (in registers) of an argument | |
1066 | for the Alpha. */ | |
1067 | ||
1068 | #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ | |
1069 | ((MODE) != BLKmode \ | |
1070 | ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ | |
1071 | : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
1072 | ||
1073 | /* Update the data in CUM to advance over an argument | |
1074 | of mode MODE and data type TYPE. | |
1075 | (TYPE is null for libcalls where that information may not be available.) */ | |
1076 | ||
1077 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1078 | if (MUST_PASS_IN_STACK (MODE, TYPE)) \ | |
1079 | (CUM) = 6; \ | |
1080 | else \ | |
1081 | (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) | |
1082 | ||
1083 | /* Determine where to put an argument to a function. | |
1084 | Value is zero to push the argument on the stack, | |
1085 | or a hard register in which to store the argument. | |
1086 | ||
1087 | MODE is the argument's machine mode. | |
1088 | TYPE is the data type of the argument (as a tree). | |
1089 | This is null for libcalls where that information may | |
1090 | not be available. | |
1091 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1092 | the preceding args and about the function being called. | |
1093 | NAMED is nonzero if this argument is a named parameter | |
1094 | (otherwise it is an extra parameter matching an ellipsis). | |
1095 | ||
1096 | On Alpha the first 6 words of args are normally in registers | |
1097 | and the rest are pushed. */ | |
1098 | ||
1099 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1100 | ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \ | |
1101 | ? gen_rtx(REG, (MODE), \ | |
14d4a67a RK |
1102 | (CUM) + 16 + ((TARGET_FPREGS \ |
1103 | && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \ | |
1104 | || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ | |
1105 | * 32)) \ | |
1106 | : 0) | |
1a94ca49 | 1107 | |
1a94ca49 RK |
1108 | /* Specify the padding direction of arguments. |
1109 | ||
1110 | On the Alpha, we must pad upwards in order to be able to pass args in | |
1111 | registers. */ | |
1112 | ||
1113 | #define FUNCTION_ARG_PADDING(MODE, TYPE) upward | |
1114 | ||
1115 | /* For an arg passed partly in registers and partly in memory, | |
1116 | this is the number of registers used. | |
1117 | For args passed entirely in registers or entirely in memory, zero. */ | |
1118 | ||
1119 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1120 | ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ | |
1121 | ? 6 - (CUM) : 0) | |
1122 | ||
130d2d72 RK |
1123 | /* Perform any needed actions needed for a function that is receiving a |
1124 | variable number of arguments. | |
1125 | ||
1126 | CUM is as above. | |
1127 | ||
1128 | MODE and TYPE are the mode and type of the current parameter. | |
1129 | ||
1130 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1131 | that must be pushed by the prolog to pretend that our caller pushed | |
1132 | it. | |
1133 | ||
1134 | Normally, this macro will push all remaining incoming registers on the | |
1135 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1136 | ||
1137 | On the Alpha, we allocate space for all 12 arg registers, but only | |
1138 | push those that are remaining. | |
1139 | ||
1140 | However, if NO registers need to be saved, don't allocate any space. | |
1141 | This is not only because we won't need the space, but because AP includes | |
1142 | the current_pretend_args_size and we don't want to mess up any | |
7a92339b RK |
1143 | ap-relative addresses already made. |
1144 | ||
1145 | If we are not to use the floating-point registers, save the integer | |
1146 | registers where we would put the floating-point registers. This is | |
1147 | not the most efficient way to implement varargs with just one register | |
1148 | class, but it isn't worth doing anything more efficient in this rare | |
1149 | case. */ | |
1150 | ||
130d2d72 RK |
1151 | |
1152 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ | |
1153 | { if ((CUM) < 6) \ | |
1154 | { \ | |
1155 | if (! (NO_RTL)) \ | |
1156 | { \ | |
1157 | move_block_from_reg \ | |
1158 | (16 + CUM, \ | |
1159 | gen_rtx (MEM, BLKmode, \ | |
1160 | plus_constant (virtual_incoming_args_rtx, \ | |
7f5bd4ff | 1161 | ((CUM) + 6)* UNITS_PER_WORD)), \ |
02892e06 | 1162 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
130d2d72 | 1163 | move_block_from_reg \ |
7a92339b | 1164 | (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \ |
130d2d72 RK |
1165 | gen_rtx (MEM, BLKmode, \ |
1166 | plus_constant (virtual_incoming_args_rtx, \ | |
7f5bd4ff | 1167 | (CUM) * UNITS_PER_WORD)), \ |
02892e06 | 1168 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
7a14fdc5 | 1169 | emit_insn (gen_blockage ()); \ |
130d2d72 RK |
1170 | } \ |
1171 | PRETEND_SIZE = 12 * UNITS_PER_WORD; \ | |
1172 | } \ | |
1173 | } | |
1174 | ||
c8e9adec RK |
1175 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1176 | done in less than N insns. Do all computations in MODE. Returns the place | |
1177 | where the output has been placed if it can be done and the insns have been | |
1178 | emitted. If it would take more than N insns, zero is returned and no | |
1179 | insns and emitted. */ | |
1180 | extern struct rtx_def *alpha_emit_set_const (); | |
803fee69 | 1181 | extern struct rtx_def *alpha_emit_set_long_const (); |
e83015a9 | 1182 | extern struct rtx_def *alpha_emit_conditional_branch (); |
92e40a7a RK |
1183 | extern struct rtx_def *alpha_emit_conditional_move (); |
1184 | ||
1a94ca49 RK |
1185 | /* Generate necessary RTL for __builtin_saveregs(). |
1186 | ARGLIST is the argument list; see expr.c. */ | |
1187 | extern struct rtx_def *alpha_builtin_saveregs (); | |
1188 | #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST) | |
1189 | ||
1190 | /* Define the information needed to generate branch and scc insns. This is | |
1191 | stored from the compare operation. Note that we can't use "rtx" here | |
1192 | since it hasn't been defined! */ | |
1193 | ||
1194 | extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1; | |
1195 | extern int alpha_compare_fp_p; | |
1196 | ||
71038426 RH |
1197 | /* Define the information needed to modify the epilogue for EH. */ |
1198 | ||
1199 | extern struct rtx_def *alpha_eh_epilogue_sp_ofs; | |
1200 | ||
e5958492 | 1201 | /* Make (or fake) .linkage entry for function call. |
e5958492 RK |
1202 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ |
1203 | extern void alpha_need_linkage (); | |
1204 | ||
bcbbac26 RH |
1205 | /* This macro defines the start of an assembly comment. */ |
1206 | ||
1207 | #define ASM_COMMENT_START " #" | |
1208 | ||
acd92049 | 1209 | /* This macro produces the initial definition of a function. */ |
1a94ca49 | 1210 | |
acd92049 RH |
1211 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ |
1212 | alpha_start_function(FILE,NAME,DECL); | |
1213 | extern void alpha_start_function (); | |
1a94ca49 | 1214 | |
acd92049 | 1215 | /* This macro closes up a function definition for the assembler. */ |
9c0e94a5 | 1216 | |
acd92049 RH |
1217 | #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ |
1218 | alpha_end_function(FILE,NAME,DECL) | |
1219 | extern void alpha_end_function (); | |
1220 | ||
9c0e94a5 RH |
1221 | /* This macro notes the end of the prologue. */ |
1222 | ||
1223 | #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE) | |
3c303f52 | 1224 | extern void output_end_prologue (); |
1a94ca49 | 1225 | |
acd92049 RH |
1226 | /* Output any profiling code before the prologue. */ |
1227 | ||
1228 | #define PROFILE_BEFORE_PROLOGUE 1 | |
1229 | ||
1a94ca49 | 1230 | /* Output assembler code to FILE to increment profiler label # LABELNO |
e0fb9029 | 1231 | for profiling a function entry. Under OSF/1, profiling is enabled |
ddd5a7c1 | 1232 | by simply passing -pg to the assembler and linker. */ |
85d159a3 | 1233 | |
e0fb9029 | 1234 | #define FUNCTION_PROFILER(FILE, LABELNO) |
85d159a3 RK |
1235 | |
1236 | /* Output assembler code to FILE to initialize this source file's | |
1237 | basic block profiling info, if that has not already been done. | |
1238 | This assumes that __bb_init_func doesn't garble a1-a5. */ | |
1239 | ||
1240 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
1241 | do { \ | |
1242 | ASM_OUTPUT_REG_PUSH (FILE, 16); \ | |
a62eb16f JW |
1243 | fputs ("\tlda $16,$PBX32\n", (FILE)); \ |
1244 | fputs ("\tldq $26,0($16)\n", (FILE)); \ | |
1245 | fputs ("\tbne $26,1f\n", (FILE)); \ | |
1246 | fputs ("\tlda $27,__bb_init_func\n", (FILE)); \ | |
1247 | fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \ | |
1248 | fputs ("\tldgp $29,0($26)\n", (FILE)); \ | |
1249 | fputs ("1:\n", (FILE)); \ | |
85d159a3 RK |
1250 | ASM_OUTPUT_REG_POP (FILE, 16); \ |
1251 | } while (0); | |
1252 | ||
1253 | /* Output assembler code to FILE to increment the entry-count for | |
1254 | the BLOCKNO'th basic block in this source file. */ | |
1255 | ||
1256 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1257 | do { \ | |
1258 | int blockn = (BLOCKNO); \ | |
a62eb16f | 1259 | fputs ("\tsubq $30,16,$30\n", (FILE)); \ |
70a76f06 RK |
1260 | fputs ("\tstq $26,0($30)\n", (FILE)); \ |
1261 | fputs ("\tstq $27,8($30)\n", (FILE)); \ | |
1262 | fputs ("\tlda $26,$PBX34\n", (FILE)); \ | |
1263 | fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \ | |
1264 | fputs ("\taddq $27,1,$27\n", (FILE)); \ | |
1265 | fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \ | |
1266 | fputs ("\tldq $26,0($30)\n", (FILE)); \ | |
1267 | fputs ("\tldq $27,8($30)\n", (FILE)); \ | |
a62eb16f | 1268 | fputs ("\taddq $30,16,$30\n", (FILE)); \ |
85d159a3 | 1269 | } while (0) |
1a94ca49 | 1270 | |
1a94ca49 RK |
1271 | |
1272 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1273 | the stack pointer does not matter. The value is tested only in | |
1274 | functions that have frame pointers. | |
1275 | No definition is equivalent to always zero. */ | |
1276 | ||
1277 | #define EXIT_IGNORE_STACK 1 | |
1a94ca49 RK |
1278 | \f |
1279 | /* Output assembler code for a block containing the constant parts | |
1280 | of a trampoline, leaving space for the variable parts. | |
1281 | ||
1282 | The trampoline should set the static chain pointer to value placed | |
7981384f RK |
1283 | into the trampoline and should branch to the specified routine. |
1284 | Note that $27 has been set to the address of the trampoline, so we can | |
1285 | use it for addressability of the two data items. Trampolines are always | |
1286 | aligned to FUNCTION_BOUNDARY, which is 64 bits. */ | |
1a94ca49 RK |
1287 | |
1288 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
c714f03d | 1289 | do { \ |
7981384f | 1290 | fprintf (FILE, "\tldq $1,24($27)\n"); \ |
1a94ca49 | 1291 | fprintf (FILE, "\tldq $27,16($27)\n"); \ |
7981384f RK |
1292 | fprintf (FILE, "\tjmp $31,($27),0\n"); \ |
1293 | fprintf (FILE, "\tnop\n"); \ | |
1a94ca49 | 1294 | fprintf (FILE, "\t.quad 0,0\n"); \ |
c714f03d | 1295 | } while (0) |
1a94ca49 | 1296 | |
3a523eeb RS |
1297 | /* Section in which to place the trampoline. On Alpha, instructions |
1298 | may only be placed in a text segment. */ | |
1299 | ||
1300 | #define TRAMPOLINE_SECTION text_section | |
1301 | ||
1a94ca49 RK |
1302 | /* Length in units of the trampoline for entering a nested function. */ |
1303 | ||
7981384f | 1304 | #define TRAMPOLINE_SIZE 32 |
1a94ca49 RK |
1305 | |
1306 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1307 | FNADDR is an RTX for the address of the function's pure code. | |
c714f03d | 1308 | CXT is an RTX for the static chain value for the function. */ |
1a94ca49 | 1309 | |
9ec36da5 | 1310 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
c714f03d | 1311 | alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8) |
804a4e13 | 1312 | extern void alpha_initialize_trampoline (); |
675f0e7c RK |
1313 | |
1314 | /* A C expression whose value is RTL representing the value of the return | |
1315 | address for the frame COUNT steps up from the current frame. | |
1316 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of | |
952fc2ed | 1317 | the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ |
675f0e7c | 1318 | |
9ecc37f0 RH |
1319 | #define RETURN_ADDR_RTX alpha_return_addr |
1320 | extern struct rtx_def *alpha_return_addr (); | |
1321 | ||
6abc6f40 RH |
1322 | /* Before the prologue, RA lives in $26. */ |
1323 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) | |
1324 | ||
9ecc37f0 RH |
1325 | /* Initialize data used by insn expanders. This is called from insn_emit, |
1326 | once for every function before code is generated. */ | |
1327 | ||
1328 | #define INIT_EXPANDERS alpha_init_expanders () | |
1329 | extern void alpha_init_expanders (); | |
675f0e7c | 1330 | \f |
1a94ca49 RK |
1331 | /* Addressing modes, and classification of registers for them. */ |
1332 | ||
940da324 JL |
1333 | /* #define HAVE_POST_INCREMENT 0 */ |
1334 | /* #define HAVE_POST_DECREMENT 0 */ | |
1a94ca49 | 1335 | |
940da324 JL |
1336 | /* #define HAVE_PRE_DECREMENT 0 */ |
1337 | /* #define HAVE_PRE_INCREMENT 0 */ | |
1a94ca49 RK |
1338 | |
1339 | /* Macros to check register numbers against specific register classes. */ | |
1340 | ||
1341 | /* These assume that REGNO is a hard or pseudo reg number. | |
1342 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1343 | or a pseudo reg currently allocated to a suitable hard reg. | |
1344 | Since they use reg_renumber, they are safe only once reg_renumber | |
1345 | has been allocated, which happens in local-alloc.c. */ | |
1346 | ||
1347 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
1348 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
52a69200 RK |
1349 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ |
1350 | || (REGNO) == 63 || reg_renumber[REGNO] == 63) | |
1a94ca49 RK |
1351 | \f |
1352 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1353 | #define MAX_REGS_PER_ADDRESS 1 | |
1354 | ||
1355 | /* Recognize any constant value that is a valid address. For the Alpha, | |
1356 | there are only constants none since we want to use LDA to load any | |
1357 | symbolic addresses into registers. */ | |
1358 | ||
1359 | #define CONSTANT_ADDRESS_P(X) \ | |
1360 | (GET_CODE (X) == CONST_INT \ | |
1361 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
1362 | ||
1363 | /* Include all constant integers and constant doubles, but not | |
1364 | floating-point, except for floating-point zero. */ | |
1365 | ||
1366 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1367 | (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ | |
1368 | || (X) == CONST0_RTX (GET_MODE (X))) | |
1369 | ||
1370 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1371 | and check its validity for a certain class. | |
1372 | We have two alternate definitions for each of them. | |
1373 | The usual definition accepts all pseudo regs; the other rejects | |
1374 | them unless they have been allocated suitable hard regs. | |
1375 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1376 | ||
1377 | Most source files want to accept pseudo regs in the hope that | |
1378 | they will get allocated to the class that the insn wants them to be in. | |
1379 | Source files for reload pass need to be strict. | |
1380 | After reload, it makes no difference, since pseudo regs have | |
1381 | been eliminated by then. */ | |
1382 | ||
1383 | #ifndef REG_OK_STRICT | |
1384 | ||
1385 | /* Nonzero if X is a hard reg that can be used as an index | |
1386 | or if it is a pseudo reg. */ | |
1387 | #define REG_OK_FOR_INDEX_P(X) 0 | |
5d02b6c2 | 1388 | |
1a94ca49 RK |
1389 | /* Nonzero if X is a hard reg that can be used as a base reg |
1390 | or if it is a pseudo reg. */ | |
1391 | #define REG_OK_FOR_BASE_P(X) \ | |
52a69200 | 1392 | (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1a94ca49 | 1393 | |
5d02b6c2 RH |
1394 | /* ??? Nonzero if X is the frame pointer, or some virtual register |
1395 | that may eliminate to the frame pointer. These will be allowed to | |
1396 | have offsets greater than 32K. This is done because register | |
1397 | elimination offsets will change the hi/lo split, and if we split | |
1398 | before reload, we will require additional instructions. */ | |
1399 | #define REG_OK_FP_BASE_P(X) \ | |
1400 | (REGNO (X) == 31 || REGNO (X) == 63 \ | |
1401 | || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1402 | && REGNO (X) < LAST_VIRTUAL_REGISTER)) | |
1403 | ||
1a94ca49 RK |
1404 | #else |
1405 | ||
1406 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1407 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
5d02b6c2 | 1408 | |
1a94ca49 RK |
1409 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
1410 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1411 | ||
5d02b6c2 RH |
1412 | #define REG_OK_FP_BASE_P(X) 0 |
1413 | ||
1a94ca49 RK |
1414 | #endif |
1415 | \f | |
1416 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1417 | that is a valid memory address for an instruction. | |
1418 | The MODE argument is the machine mode for the MEM expression | |
1419 | that wants to use this address. | |
1420 | ||
1421 | For Alpha, we have either a constant address or the sum of a register | |
1422 | and a constant address, or just a register. For DImode, any of those | |
1423 | forms can be surrounded with an AND that clear the low-order three bits; | |
1424 | this is an "unaligned" access. | |
1425 | ||
1a94ca49 RK |
1426 | First define the basic valid address. */ |
1427 | ||
4c020733 RH |
1428 | #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \ |
1429 | { \ | |
1430 | rtx tmp = (X); \ | |
1431 | if (GET_CODE (tmp) == SUBREG \ | |
1432 | && (GET_MODE_SIZE (GET_MODE (tmp)) \ | |
1433 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \ | |
1434 | tmp = SUBREG_REG (tmp); \ | |
1435 | if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \ | |
1436 | goto ADDR; \ | |
1437 | if (CONSTANT_ADDRESS_P (X)) \ | |
1438 | goto ADDR; \ | |
1439 | if (GET_CODE (X) == PLUS) \ | |
1440 | { \ | |
1441 | tmp = XEXP (X, 0); \ | |
1442 | if (GET_CODE (tmp) == SUBREG \ | |
1443 | && (GET_MODE_SIZE (GET_MODE (tmp)) \ | |
1444 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \ | |
1445 | tmp = SUBREG_REG (tmp); \ | |
1446 | if (REG_P (tmp)) \ | |
1447 | { \ | |
1448 | if (REG_OK_FP_BASE_P (tmp) \ | |
1449 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1450 | goto ADDR; \ | |
1451 | if (REG_OK_FOR_BASE_P (tmp) \ | |
1452 | && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1453 | goto ADDR; \ | |
1454 | } \ | |
1455 | } \ | |
1a94ca49 RK |
1456 | } |
1457 | ||
1458 | /* Now accept the simple address, or, for DImode only, an AND of a simple | |
1459 | address that turns off the low three bits. */ | |
1460 | ||
1a94ca49 RK |
1461 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
1462 | { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \ | |
1463 | if ((MODE) == DImode \ | |
1464 | && GET_CODE (X) == AND \ | |
1465 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1466 | && INTVAL (XEXP (X, 1)) == -8) \ | |
1467 | GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \ | |
1a94ca49 RK |
1468 | } |
1469 | ||
1470 | /* Try machine-dependent ways of modifying an illegitimate address | |
1471 | to be legitimate. If we find one, return the new, valid address. | |
1472 | This macro is used in only one place: `memory_address' in explow.c. | |
1473 | ||
1474 | OLDX is the address as it was before break_out_memory_refs was called. | |
1475 | In some cases it is useful to look at this to decide what needs to be done. | |
1476 | ||
1477 | MODE and WIN are passed so that this macro can use | |
1478 | GO_IF_LEGITIMATE_ADDRESS. | |
1479 | ||
1480 | It is always safe for this macro to do nothing. It exists to recognize | |
1481 | opportunities to optimize the output. | |
1482 | ||
1483 | For the Alpha, there are three cases we handle: | |
1484 | ||
1485 | (1) If the address is (plus reg const_int) and the CONST_INT is not a | |
1486 | valid offset, compute the high part of the constant and add it to the | |
1487 | register. Then our address is (plus temp low-part-const). | |
1488 | (2) If the address is (const (plus FOO const_int)), find the low-order | |
1489 | part of the CONST_INT. Then load FOO plus any high-order part of the | |
1490 | CONST_INT into a register. Our address is (plus reg low-part-const). | |
1491 | This is done to reduce the number of GOT entries. | |
1492 | (3) If we have a (plus reg const), emit the load as in (2), then add | |
1493 | the two registers, and finally generate (plus reg low-part-const) as | |
1494 | our address. */ | |
1495 | ||
1496 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1497 | { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1498 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1499 | && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1500 | { \ | |
1501 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1502 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1503 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1504 | rtx high = GEN_INT (highpart); \ | |
1505 | rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \ | |
80f251fe | 1506 | high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1507 | \ |
1508 | (X) = plus_constant (temp, lowpart); \ | |
1509 | goto WIN; \ | |
1510 | } \ | |
1511 | else if (GET_CODE (X) == CONST \ | |
1512 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1513 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
1514 | { \ | |
1515 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
1516 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1517 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1518 | rtx high = XEXP (XEXP (X, 0), 0); \ | |
1519 | \ | |
1520 | if (highpart) \ | |
1521 | high = plus_constant (high, highpart); \ | |
1522 | \ | |
1523 | (X) = plus_constant (force_reg (Pmode, high), lowpart); \ | |
1524 | goto WIN; \ | |
1525 | } \ | |
1526 | else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1527 | && GET_CODE (XEXP (X, 1)) == CONST \ | |
1528 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \ | |
1529 | && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \ | |
1530 | { \ | |
1531 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \ | |
1532 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1533 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1534 | rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \ | |
1535 | \ | |
1536 | if (highpart) \ | |
1537 | high = plus_constant (high, highpart); \ | |
1538 | \ | |
1539 | high = expand_binop (Pmode, add_optab, XEXP (X, 0), \ | |
1540 | force_reg (Pmode, high), \ | |
80f251fe | 1541 | high, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1542 | (X) = plus_constant (high, lowpart); \ |
1543 | goto WIN; \ | |
1544 | } \ | |
1545 | } | |
1546 | ||
a9a2595b JR |
1547 | /* Try a machine-dependent way of reloading an illegitimate address |
1548 | operand. If we find one, push the reload and jump to WIN. This | |
1549 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1550 | ||
1551 | For the Alpha, we wish to handle large displacements off a base | |
1552 | register by splitting the addend across an ldah and the mem insn. | |
1553 | This cuts number of extra insns needed from 3 to 1. */ | |
1554 | ||
1555 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1556 | do { \ | |
c8ab9901 RH |
1557 | /* We must recognize output that we have already generated ourselves. */ \ |
1558 | if (GET_CODE (X) == PLUS \ | |
1559 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1560 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1561 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1562 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1563 | { \ | |
1564 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1565 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1566 | OPNUM, TYPE); \ | |
1567 | goto WIN; \ | |
1568 | } \ | |
a9a2595b JR |
1569 | if (GET_CODE (X) == PLUS \ |
1570 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1571 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1572 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1573 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1574 | { \ | |
1575 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1576 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \ | |
1577 | HOST_WIDE_INT high \ | |
1578 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \ | |
1579 | \ | |
1580 | /* Check for 32-bit overflow. */ \ | |
1581 | if (high + low != val) \ | |
1582 | break; \ | |
1583 | \ | |
1584 | /* Reload the high part into a base reg; leave the low part \ | |
1585 | in the mem directly. */ \ | |
1586 | \ | |
1587 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1588 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1589 | GEN_INT (high)), \ | |
1590 | GEN_INT (low)); \ | |
1591 | \ | |
1592 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \ | |
1593 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ | |
1594 | OPNUM, TYPE); \ | |
1595 | goto WIN; \ | |
1596 | } \ | |
1597 | } while (0) | |
1598 | ||
1a94ca49 RK |
1599 | /* Go to LABEL if ADDR (a legitimate address expression) |
1600 | has an effect that depends on the machine mode it is used for. | |
1601 | On the Alpha this is true only for the unaligned modes. We can | |
1602 | simplify this test since we know that the address must be valid. */ | |
1603 | ||
1604 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1605 | { if (GET_CODE (ADDR) == AND) goto LABEL; } | |
1606 | ||
1607 | /* Compute the cost of an address. For the Alpha, all valid addresses are | |
1608 | the same cost. */ | |
1609 | ||
1610 | #define ADDRESS_COST(X) 0 | |
1611 | ||
2ea844d3 RH |
1612 | /* Machine-dependent reorg pass. */ |
1613 | #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X) | |
1a94ca49 RK |
1614 | \f |
1615 | /* Specify the machine mode that this machine uses | |
1616 | for the index in the tablejump instruction. */ | |
1617 | #define CASE_VECTOR_MODE SImode | |
1618 | ||
18543a22 ILT |
1619 | /* Define as C expression which evaluates to nonzero if the tablejump |
1620 | instruction expects the table to contain offsets from the address of the | |
3aa9d5b6 | 1621 | table. |
b0435cf4 | 1622 | |
3aa9d5b6 | 1623 | Do not define this if the table should contain absolute addresses. |
260ced47 RK |
1624 | On the Alpha, the table is really GP-relative, not relative to the PC |
1625 | of the table, but we pretend that it is PC-relative; this should be OK, | |
0076aa6b | 1626 | but we should try to find some better way sometime. */ |
18543a22 | 1627 | #define CASE_VECTOR_PC_RELATIVE 1 |
1a94ca49 RK |
1628 | |
1629 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1630 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1631 | ||
1632 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1633 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1634 | ||
1635 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1636 | #define DEFAULT_SIGNED_CHAR 1 | |
1637 | ||
1638 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1639 | also convert validly to an unsigned one. | |
1640 | ||
1641 | We actually lie a bit here as overflow conditions are different. But | |
1642 | they aren't being checked anyway. */ | |
1643 | ||
1644 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1645 | ||
1646 | /* Max number of bytes we can move to or from memory | |
1647 | in one reasonably fast instruction. */ | |
1648 | ||
1649 | #define MOVE_MAX 8 | |
1650 | ||
7e24ffc9 HPN |
1651 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
1652 | move-instruction pairs, we will do a movstr or libcall instead. | |
1653 | ||
1654 | Without byte/word accesses, we want no more than four instructions; | |
1655 | with, several single byte accesses are better. */ | |
6c174fc0 RH |
1656 | |
1657 | #define MOVE_RATIO (TARGET_BWX ? 7 : 2) | |
1658 | ||
1a94ca49 RK |
1659 | /* Largest number of bytes of an object that can be placed in a register. |
1660 | On the Alpha we have plenty of registers, so use TImode. */ | |
1661 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
1662 | ||
1663 | /* Nonzero if access to memory by bytes is no faster than for words. | |
1664 | Also non-zero if doing byte operations (specifically shifts) in registers | |
1665 | is undesirable. | |
1666 | ||
1667 | On the Alpha, we want to not use the byte operation and instead use | |
1668 | masking operations to access fields; these will save instructions. */ | |
1669 | ||
1670 | #define SLOW_BYTE_ACCESS 1 | |
1671 | ||
9a63901f RK |
1672 | /* Define if operations between registers always perform the operation |
1673 | on the full register even if a narrower mode is specified. */ | |
1674 | #define WORD_REGISTER_OPERATIONS | |
1675 | ||
1676 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1677 | will either zero-extend or sign-extend. The value of this macro should | |
1678 | be the code that says which one of the two operations is implicitly | |
1679 | done, NIL if none. */ | |
b7747781 | 1680 | #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) |
1a94ca49 | 1681 | |
225211e2 RK |
1682 | /* Define if loading short immediate values into registers sign extends. */ |
1683 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1684 | ||
1a94ca49 RK |
1685 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1686 | is done just by pretending it is already truncated. */ | |
1687 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1688 | ||
1689 | /* We assume that the store-condition-codes instructions store 0 for false | |
1690 | and some other value for true. This is the value stored for true. */ | |
1691 | ||
1692 | #define STORE_FLAG_VALUE 1 | |
1693 | ||
1694 | /* Define the value returned by a floating-point comparison instruction. */ | |
1695 | ||
e9a25f70 | 1696 | #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0) |
1a94ca49 | 1697 | |
35bb77fd RK |
1698 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
1699 | ||
1700 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1701 | do { \ | |
1702 | if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ | |
1703 | && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ | |
1704 | { \ | |
1705 | rtx tem = (OP0); \ | |
1706 | (OP0) = (OP1); \ | |
1707 | (OP1) = tem; \ | |
1708 | (CODE) = swap_condition (CODE); \ | |
1709 | } \ | |
1710 | if (((CODE) == LT || (CODE) == LTU) \ | |
1711 | && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ | |
1712 | { \ | |
1713 | (CODE) = (CODE) == LT ? LE : LEU; \ | |
1714 | (OP1) = GEN_INT (255); \ | |
1715 | } \ | |
1716 | } while (0) | |
1717 | ||
1a94ca49 RK |
1718 | /* Specify the machine mode that pointers have. |
1719 | After generation of rtl, the compiler makes no further distinction | |
1720 | between pointers and any other objects of this machine mode. */ | |
1721 | #define Pmode DImode | |
1722 | ||
1723 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
1724 | ||
1725 | #define FUNCTION_MODE Pmode | |
1726 | ||
1727 | /* Define this if addresses of constant functions | |
1728 | shouldn't be put through pseudo regs where they can be cse'd. | |
1729 | Desirable on machines where ordinary constants are expensive | |
1730 | but a CALL with constant address is cheap. | |
1731 | ||
1732 | We define this on the Alpha so that gen_call and gen_call_value | |
1733 | get to see the SYMBOL_REF (for the hint field of the jsr). It will | |
1734 | then copy it into a register, thus actually letting the address be | |
1735 | cse'ed. */ | |
1736 | ||
1737 | #define NO_FUNCTION_CSE | |
1738 | ||
d969caf8 | 1739 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
1a94ca49 | 1740 | few bits. */ |
d969caf8 | 1741 | #define SHIFT_COUNT_TRUNCATED 1 |
1a94ca49 | 1742 | |
d721b776 RK |
1743 | /* Use atexit for static constructors/destructors, instead of defining |
1744 | our own exit function. */ | |
1745 | #define HAVE_ATEXIT | |
1746 | ||
71d9b493 | 1747 | /* The EV4 is dual issue; EV5/EV6 are quad issue. */ |
74835ed8 RH |
1748 | #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4) |
1749 | ||
7d0bfbd0 RH |
1750 | /* Describe the fact that MULTI instructions are multiple instructions |
1751 | and so to assume they don't pair with anything. */ | |
1752 | #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \ | |
1753 | if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \ | |
1754 | (CAN_ISSUE_MORE) = 0 | |
1755 | ||
1a94ca49 RK |
1756 | /* Compute the cost of computing a constant rtl expression RTX |
1757 | whose rtx-code is CODE. The body of this macro is a portion | |
1758 | of a switch statement. If the code is computed here, | |
1759 | return it with a return statement. Otherwise, break from the switch. | |
1760 | ||
8b7b2e36 RK |
1761 | If this is an 8-bit constant, return zero since it can be used |
1762 | nearly anywhere with no cost. If it is a valid operand for an | |
1763 | ADD or AND, likewise return 0 if we know it will be used in that | |
1764 | context. Otherwise, return 2 since it might be used there later. | |
1765 | All other constants take at least two insns. */ | |
1a94ca49 RK |
1766 | |
1767 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ | |
1768 | case CONST_INT: \ | |
06eb8e92 | 1769 | if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \ |
8b7b2e36 | 1770 | return 0; \ |
1a94ca49 | 1771 | case CONST_DOUBLE: \ |
5d02ee66 RH |
1772 | if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \ |
1773 | return 0; \ | |
1774 | else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \ | |
8b7b2e36 RK |
1775 | || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \ |
1776 | return 0; \ | |
1777 | else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \ | |
1778 | return 2; \ | |
1779 | else \ | |
1780 | return COSTS_N_INSNS (2); \ | |
1a94ca49 RK |
1781 | case CONST: \ |
1782 | case SYMBOL_REF: \ | |
1783 | case LABEL_REF: \ | |
f6f6a13c RK |
1784 | switch (alpha_cpu) \ |
1785 | { \ | |
1786 | case PROCESSOR_EV4: \ | |
1787 | return COSTS_N_INSNS (3); \ | |
1788 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1789 | case PROCESSOR_EV6: \ |
f6f6a13c | 1790 | return COSTS_N_INSNS (2); \ |
5d02ee66 | 1791 | default: abort(); \ |
f6f6a13c | 1792 | } |
1a94ca49 RK |
1793 | |
1794 | /* Provide the costs of a rtl expression. This is in the body of a | |
1795 | switch on CODE. */ | |
1796 | ||
1797 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
3bda6d11 RK |
1798 | case PLUS: case MINUS: \ |
1799 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
f6f6a13c RK |
1800 | switch (alpha_cpu) \ |
1801 | { \ | |
1802 | case PROCESSOR_EV4: \ | |
1803 | return COSTS_N_INSNS (6); \ | |
1804 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1805 | case PROCESSOR_EV6: \ |
f6f6a13c | 1806 | return COSTS_N_INSNS (4); \ |
5d02ee66 | 1807 | default: abort(); \ |
f6f6a13c | 1808 | } \ |
b49e978e RK |
1809 | else if (GET_CODE (XEXP (X, 0)) == MULT \ |
1810 | && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ | |
a5da0afe RK |
1811 | return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ |
1812 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1a94ca49 RK |
1813 | break; \ |
1814 | case MULT: \ | |
f6f6a13c RK |
1815 | switch (alpha_cpu) \ |
1816 | { \ | |
1817 | case PROCESSOR_EV4: \ | |
1818 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1819 | return COSTS_N_INSNS (6); \ | |
1820 | return COSTS_N_INSNS (23); \ | |
1821 | case PROCESSOR_EV5: \ | |
1822 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1823 | return COSTS_N_INSNS (4); \ | |
1824 | else if (GET_MODE (X) == DImode) \ | |
1825 | return COSTS_N_INSNS (12); \ | |
1826 | else \ | |
1827 | return COSTS_N_INSNS (8); \ | |
5d02ee66 RH |
1828 | case PROCESSOR_EV6: \ |
1829 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1830 | return COSTS_N_INSNS (4); \ | |
1831 | else \ | |
1832 | return COSTS_N_INSNS (7); \ | |
1833 | default: abort(); \ | |
f6f6a13c | 1834 | } \ |
b49e978e RK |
1835 | case ASHIFT: \ |
1836 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1837 | && INTVAL (XEXP (X, 1)) <= 3) \ | |
1838 | break; \ | |
1839 | /* ... fall through ... */ \ | |
5d02ee66 | 1840 | case ASHIFTRT: case LSHIFTRT: \ |
f6f6a13c RK |
1841 | switch (alpha_cpu) \ |
1842 | { \ | |
1843 | case PROCESSOR_EV4: \ | |
1844 | return COSTS_N_INSNS (2); \ | |
1845 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1846 | case PROCESSOR_EV6: \ |
f6f6a13c | 1847 | return COSTS_N_INSNS (1); \ |
5d02ee66 RH |
1848 | default: abort(); \ |
1849 | } \ | |
1850 | case IF_THEN_ELSE: \ | |
1851 | switch (alpha_cpu) \ | |
1852 | { \ | |
1853 | case PROCESSOR_EV4: \ | |
1854 | case PROCESSOR_EV6: \ | |
1855 | return COSTS_N_INSNS (2); \ | |
1856 | case PROCESSOR_EV5: \ | |
1857 | return COSTS_N_INSNS (1); \ | |
1858 | default: abort(); \ | |
f6f6a13c | 1859 | } \ |
3bda6d11 | 1860 | case DIV: case UDIV: case MOD: case UMOD: \ |
f6f6a13c RK |
1861 | switch (alpha_cpu) \ |
1862 | { \ | |
1863 | case PROCESSOR_EV4: \ | |
1864 | if (GET_MODE (X) == SFmode) \ | |
1865 | return COSTS_N_INSNS (34); \ | |
1866 | else if (GET_MODE (X) == DFmode) \ | |
1867 | return COSTS_N_INSNS (63); \ | |
1868 | else \ | |
1869 | return COSTS_N_INSNS (70); \ | |
1870 | case PROCESSOR_EV5: \ | |
1871 | if (GET_MODE (X) == SFmode) \ | |
1872 | return COSTS_N_INSNS (15); \ | |
1873 | else if (GET_MODE (X) == DFmode) \ | |
1874 | return COSTS_N_INSNS (22); \ | |
1875 | else \ | |
5d02ee66 RH |
1876 | return COSTS_N_INSNS (70); /* ??? */ \ |
1877 | case PROCESSOR_EV6: \ | |
1878 | if (GET_MODE (X) == SFmode) \ | |
1879 | return COSTS_N_INSNS (12); \ | |
1880 | else if (GET_MODE (X) == DFmode) \ | |
1881 | return COSTS_N_INSNS (15); \ | |
1882 | else \ | |
1883 | return COSTS_N_INSNS (70); /* ??? */ \ | |
1884 | default: abort(); \ | |
f6f6a13c | 1885 | } \ |
1a94ca49 | 1886 | case MEM: \ |
f6f6a13c RK |
1887 | switch (alpha_cpu) \ |
1888 | { \ | |
1889 | case PROCESSOR_EV4: \ | |
5d02ee66 | 1890 | case PROCESSOR_EV6: \ |
f6f6a13c RK |
1891 | return COSTS_N_INSNS (3); \ |
1892 | case PROCESSOR_EV5: \ | |
1893 | return COSTS_N_INSNS (2); \ | |
5d02ee66 | 1894 | default: abort(); \ |
f6f6a13c RK |
1895 | } \ |
1896 | case NEG: case ABS: \ | |
1897 | if (! FLOAT_MODE_P (GET_MODE (X))) \ | |
1898 | break; \ | |
1899 | /* ... fall through ... */ \ | |
3bda6d11 RK |
1900 | case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \ |
1901 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ | |
f6f6a13c RK |
1902 | switch (alpha_cpu) \ |
1903 | { \ | |
1904 | case PROCESSOR_EV4: \ | |
1905 | return COSTS_N_INSNS (6); \ | |
1906 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1907 | case PROCESSOR_EV6: \ |
f6f6a13c | 1908 | return COSTS_N_INSNS (4); \ |
5d02ee66 | 1909 | default: abort(); \ |
f6f6a13c | 1910 | } |
1a94ca49 RK |
1911 | \f |
1912 | /* Control the assembler format that we output. */ | |
1913 | ||
40ef2fc5 JL |
1914 | /* We don't emit these labels, so as to avoid getting linker errors about |
1915 | missing exception handling info. If we emit a gcc_compiled. label into | |
1916 | text, and the file has no code, then the DEC assembler gives us a zero | |
1917 | sized text section with no associated exception handling info. The | |
38e01259 | 1918 | DEC linker sees this text section, and gives a warning saying that |
40ef2fc5 | 1919 | the exception handling info is missing. */ |
3c303f52 KG |
1920 | #define ASM_IDENTIFY_GCC(x) |
1921 | #define ASM_IDENTIFY_LANGUAGE(x) | |
40ef2fc5 | 1922 | |
1a94ca49 RK |
1923 | /* Output to assembler file text saying following lines |
1924 | may contain character constants, extra white space, comments, etc. */ | |
1925 | ||
1926 | #define ASM_APP_ON "" | |
1927 | ||
1928 | /* Output to assembler file text saying following lines | |
1929 | no longer contain unusual constructs. */ | |
1930 | ||
1931 | #define ASM_APP_OFF "" | |
1932 | ||
1933 | #define TEXT_SECTION_ASM_OP ".text" | |
1934 | ||
1935 | /* Output before read-only data. */ | |
1936 | ||
1937 | #define READONLY_DATA_SECTION_ASM_OP ".rdata" | |
1938 | ||
1939 | /* Output before writable data. */ | |
1940 | ||
1941 | #define DATA_SECTION_ASM_OP ".data" | |
1942 | ||
1943 | /* Define an extra section for read-only data, a routine to enter it, and | |
c0388f29 RK |
1944 | indicate that it is for read-only data. |
1945 | ||
abc95ed3 | 1946 | The first time we enter the readonly data section for a file, we write |
c0388f29 RK |
1947 | eight bytes of zero. This works around a bug in DEC's assembler in |
1948 | some versions of OSF/1 V3.x. */ | |
1a94ca49 RK |
1949 | |
1950 | #define EXTRA_SECTIONS readonly_data | |
1951 | ||
1952 | #define EXTRA_SECTION_FUNCTIONS \ | |
1953 | void \ | |
1954 | literal_section () \ | |
1955 | { \ | |
1956 | if (in_section != readonly_data) \ | |
1957 | { \ | |
c0388f29 RK |
1958 | static int firsttime = 1; \ |
1959 | \ | |
1a94ca49 | 1960 | fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ |
c0388f29 RK |
1961 | if (firsttime) \ |
1962 | { \ | |
1963 | firsttime = 0; \ | |
1964 | ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \ | |
1965 | } \ | |
1966 | \ | |
1a94ca49 RK |
1967 | in_section = readonly_data; \ |
1968 | } \ | |
1969 | } \ | |
1970 | ||
1971 | #define READONLY_DATA_SECTION literal_section | |
1972 | ||
ac030a7b RK |
1973 | /* If we are referencing a function that is static, make the SYMBOL_REF |
1974 | special. We use this to see indicate we can branch to this function | |
1975 | without setting PV or restoring GP. */ | |
130d2d72 RK |
1976 | |
1977 | #define ENCODE_SECTION_INFO(DECL) \ | |
ac030a7b | 1978 | if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \ |
130d2d72 RK |
1979 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; |
1980 | ||
1a94ca49 RK |
1981 | /* How to refer to registers in assembler output. |
1982 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1983 | ||
1984 | #define REGISTER_NAMES \ | |
1985 | {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ | |
1986 | "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
1987 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
130d2d72 | 1988 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ |
1a94ca49 RK |
1989 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ |
1990 | "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
1991 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ | |
52a69200 | 1992 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} |
1a94ca49 RK |
1993 | |
1994 | /* How to renumber registers for dbx and gdb. */ | |
1995 | ||
1996 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1997 | ||
1998 | /* This is how to output the definition of a user-level label named NAME, | |
1999 | such as the label on a static function or variable NAME. */ | |
2000 | ||
2001 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
2002 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
2003 | ||
2004 | /* This is how to output a command to make the user-level label named NAME | |
2005 | defined for reference from other files. */ | |
2006 | ||
2007 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
2008 | do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
2009 | ||
4e0c8ad2 | 2010 | /* The prefix to add to user-visible assembler symbols. */ |
1a94ca49 | 2011 | |
4e0c8ad2 | 2012 | #define USER_LABEL_PREFIX "" |
1a94ca49 RK |
2013 | |
2014 | /* This is how to output an internal numbered label where | |
2015 | PREFIX is the class of label and NUM is the number within the class. */ | |
2016 | ||
2017 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
531ea24e | 2018 | fprintf (FILE, "$%s%d:\n", PREFIX, NUM) |
1a94ca49 RK |
2019 | |
2020 | /* This is how to output a label for a jump table. Arguments are the same as | |
2021 | for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is | |
2022 | passed. */ | |
2023 | ||
2024 | #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ | |
2025 | { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } | |
2026 | ||
2027 | /* This is how to store into the string LABEL | |
2028 | the symbol_ref name of an internal numbered label where | |
2029 | PREFIX is the class of label and NUM is the number within the class. | |
2030 | This is suitable for output with `assemble_name'. */ | |
2031 | ||
2032 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
d1e6b55b | 2033 | sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) |
1a94ca49 | 2034 | |
e247ca2a RK |
2035 | /* Check a floating-point value for validity for a particular machine mode. */ |
2036 | ||
2037 | #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \ | |
2038 | ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW)) | |
2039 | ||
1a94ca49 RK |
2040 | /* This is how to output an assembler line defining a `double' constant. */ |
2041 | ||
e99300f1 RS |
2042 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
2043 | { \ | |
2044 | if (REAL_VALUE_ISINF (VALUE) \ | |
2045 | || REAL_VALUE_ISNAN (VALUE) \ | |
2046 | || REAL_VALUE_MINUS_ZERO (VALUE)) \ | |
2047 | { \ | |
2048 | long t[2]; \ | |
2049 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2050 | fprintf (FILE, "\t.quad 0x%lx%08lx\n", \ | |
2051 | t[1] & 0xffffffff, t[0] & 0xffffffff); \ | |
2052 | } \ | |
2053 | else \ | |
2054 | { \ | |
2055 | char str[30]; \ | |
2056 | REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \ | |
e5958492 | 2057 | fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \ |
e99300f1 RS |
2058 | } \ |
2059 | } | |
1a94ca49 RK |
2060 | |
2061 | /* This is how to output an assembler line defining a `float' constant. */ | |
2062 | ||
e247ca2a RK |
2063 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
2064 | do { \ | |
2065 | long t; \ | |
2066 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
2067 | fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \ | |
2068 | } while (0) | |
2700ac93 | 2069 | |
1a94ca49 RK |
2070 | /* This is how to output an assembler line defining an `int' constant. */ |
2071 | ||
2072 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
0076aa6b RK |
2073 | ( fprintf (FILE, "\t.long "), \ |
2074 | output_addr_const (FILE, (VALUE)), \ | |
2075 | fprintf (FILE, "\n")) | |
1a94ca49 RK |
2076 | |
2077 | /* This is how to output an assembler line defining a `long' constant. */ | |
2078 | ||
2079 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
2080 | ( fprintf (FILE, "\t.quad "), \ | |
2081 | output_addr_const (FILE, (VALUE)), \ | |
2082 | fprintf (FILE, "\n")) | |
2083 | ||
2084 | /* Likewise for `char' and `short' constants. */ | |
2085 | ||
2086 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
690ef02f | 2087 | fprintf (FILE, "\t.word %d\n", \ |
3c303f52 | 2088 | (int)(GET_CODE (VALUE) == CONST_INT \ |
45c45e79 | 2089 | ? INTVAL (VALUE) & 0xffff : (abort (), 0))) |
1a94ca49 RK |
2090 | |
2091 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
45c45e79 | 2092 | fprintf (FILE, "\t.byte %d\n", \ |
3c303f52 | 2093 | (int)(GET_CODE (VALUE) == CONST_INT \ |
45c45e79 | 2094 | ? INTVAL (VALUE) & 0xff : (abort (), 0))) |
1a94ca49 RK |
2095 | |
2096 | /* We use the default ASCII-output routine, except that we don't write more | |
2097 | than 50 characters since the assembler doesn't support very long lines. */ | |
2098 | ||
2099 | #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ | |
2100 | do { \ | |
2101 | FILE *_hide_asm_out_file = (MYFILE); \ | |
2102 | unsigned char *_hide_p = (unsigned char *) (MYSTRING); \ | |
2103 | int _hide_thissize = (MYLENGTH); \ | |
2104 | int _size_so_far = 0; \ | |
2105 | { \ | |
2106 | FILE *asm_out_file = _hide_asm_out_file; \ | |
2107 | unsigned char *p = _hide_p; \ | |
2108 | int thissize = _hide_thissize; \ | |
2109 | int i; \ | |
2110 | fprintf (asm_out_file, "\t.ascii \""); \ | |
2111 | \ | |
2112 | for (i = 0; i < thissize; i++) \ | |
2113 | { \ | |
2114 | register int c = p[i]; \ | |
2115 | \ | |
2116 | if (_size_so_far ++ > 50 && i < thissize - 4) \ | |
2117 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ | |
2118 | \ | |
2119 | if (c == '\"' || c == '\\') \ | |
2120 | putc ('\\', asm_out_file); \ | |
2121 | if (c >= ' ' && c < 0177) \ | |
2122 | putc (c, asm_out_file); \ | |
2123 | else \ | |
2124 | { \ | |
2125 | fprintf (asm_out_file, "\\%o", c); \ | |
2126 | /* After an octal-escape, if a digit follows, \ | |
2127 | terminate one string constant and start another. \ | |
2128 | The Vax assembler fails to stop reading the escape \ | |
2129 | after three digits, so this is the only way we \ | |
2130 | can get it to parse the data properly. */ \ | |
2131 | if (i < thissize - 1 \ | |
2132 | && p[i + 1] >= '0' && p[i + 1] <= '9') \ | |
b2d5e311 | 2133 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ |
1a94ca49 RK |
2134 | } \ |
2135 | } \ | |
2136 | fprintf (asm_out_file, "\"\n"); \ | |
2137 | } \ | |
2138 | } \ | |
2139 | while (0) | |
52a69200 | 2140 | |
1a94ca49 RK |
2141 | /* This is how to output an insn to push a register on the stack. |
2142 | It need not be very fast code. */ | |
2143 | ||
2144 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
2145 | fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \ | |
2146 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2147 | (REGNO) & 31); | |
2148 | ||
2149 | /* This is how to output an insn to pop a register from the stack. | |
2150 | It need not be very fast code. */ | |
2151 | ||
2152 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
2153 | fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \ | |
2154 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2155 | (REGNO) & 31); | |
2156 | ||
2157 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2158 | ||
2159 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
3c303f52 | 2160 | fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff)) |
1a94ca49 | 2161 | |
260ced47 RK |
2162 | /* This is how to output an element of a case-vector that is absolute. |
2163 | (Alpha does not use such vectors, but we must define this macro anyway.) */ | |
1a94ca49 | 2164 | |
260ced47 | 2165 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort () |
1a94ca49 | 2166 | |
260ced47 | 2167 | /* This is how to output an element of a case-vector that is relative. */ |
1a94ca49 | 2168 | |
33f7f353 | 2169 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
8dfe3c62 RH |
2170 | fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \ |
2171 | (VALUE)) | |
1a94ca49 RK |
2172 | |
2173 | /* This is how to output an assembler line | |
2174 | that says to advance the location counter | |
2175 | to a multiple of 2**LOG bytes. */ | |
2176 | ||
2177 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2178 | if ((LOG) != 0) \ | |
2179 | fprintf (FILE, "\t.align %d\n", LOG); | |
2180 | ||
2181 | /* This is how to advance the location counter by SIZE bytes. */ | |
2182 | ||
2183 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2184 | fprintf (FILE, "\t.space %d\n", (SIZE)) | |
2185 | ||
2186 | /* This says how to output an assembler line | |
2187 | to define a global common symbol. */ | |
2188 | ||
2189 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
2190 | ( fputs ("\t.comm ", (FILE)), \ | |
2191 | assemble_name ((FILE), (NAME)), \ | |
2192 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2193 | ||
2194 | /* This says how to output an assembler line | |
2195 | to define a local common symbol. */ | |
2196 | ||
2197 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ | |
2198 | ( fputs ("\t.lcomm ", (FILE)), \ | |
2199 | assemble_name ((FILE), (NAME)), \ | |
2200 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2201 | ||
2202 | /* Store in OUTPUT a string (made with alloca) containing | |
2203 | an assembler-name for a local static variable named NAME. | |
2204 | LABELNO is an integer which is different for each call. */ | |
2205 | ||
2206 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2207 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2208 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2209 | ||
2210 | /* Define the parentheses used to group arithmetic operations | |
2211 | in assembler code. */ | |
2212 | ||
2213 | #define ASM_OPEN_PAREN "(" | |
2214 | #define ASM_CLOSE_PAREN ")" | |
2215 | ||
60593797 RH |
2216 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2217 | Used for C++ multiple inheritance. */ | |
2218 | ||
2219 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ | |
2220 | do { \ | |
92d4501f | 2221 | char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \ |
54473ca7 | 2222 | int reg; \ |
60593797 | 2223 | \ |
acd92049 RH |
2224 | /* Mark end of prologue. */ \ |
2225 | output_end_prologue (FILE); \ | |
60593797 RH |
2226 | \ |
2227 | /* Rely on the assembler to macro expand a large delta. */ \ | |
54473ca7 L |
2228 | reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \ |
2229 | fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \ | |
60593797 RH |
2230 | \ |
2231 | if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \ | |
2232 | { \ | |
2233 | fprintf (FILE, "\tbr $31,$"); \ | |
2234 | assemble_name (FILE, fn_name); \ | |
2235 | fprintf (FILE, "..ng\n"); \ | |
2236 | } \ | |
2237 | else \ | |
2238 | { \ | |
acd92049 | 2239 | fprintf (FILE, "\tjmp $31,"); \ |
60593797 RH |
2240 | assemble_name (FILE, fn_name); \ |
2241 | fputc ('\n', FILE); \ | |
2242 | } \ | |
60593797 | 2243 | } while (0) |
60593797 | 2244 | \f |
9ec36da5 | 2245 | |
1a94ca49 RK |
2246 | /* Define results of standard character escape sequences. */ |
2247 | #define TARGET_BELL 007 | |
2248 | #define TARGET_BS 010 | |
2249 | #define TARGET_TAB 011 | |
2250 | #define TARGET_NEWLINE 012 | |
2251 | #define TARGET_VT 013 | |
2252 | #define TARGET_FF 014 | |
2253 | #define TARGET_CR 015 | |
2254 | ||
2255 | /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2256 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2257 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2258 | ||
2259 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2260 | ||
2261 | /* Determine which codes are valid without a following integer. These must | |
2bf6230d RK |
2262 | not be alphabetic (the characters are chosen so that |
2263 | PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when | |
2264 | using ASCII). | |
2265 | ||
2266 | & Generates fp-rounding mode suffix: nothing for normal, 'c' for | |
2267 | chopped, 'm' for minus-infinity, and 'd' for dynamic rounding | |
2268 | mode. alpha_fprm controls which suffix is generated. | |
2269 | ||
2270 | ' Generates trap-mode suffix for instructions that accept the | |
2271 | su suffix only (cmpt et al). | |
2272 | ||
e83015a9 RH |
2273 | ` Generates trap-mode suffix for instructions that accept the |
2274 | v and sv suffix. The only instruction that needs this is cvtql. | |
2275 | ||
0022a940 DMT |
2276 | ( Generates trap-mode suffix for instructions that accept the |
2277 | v, sv, and svi suffix. The only instruction that needs this | |
2278 | is cvttq. | |
2279 | ||
2bf6230d RK |
2280 | ) Generates trap-mode suffix for instructions that accept the |
2281 | u, su, and sui suffix. This is the bulk of the IEEE floating | |
2282 | point instructions (addt et al). | |
2283 | ||
2284 | + Generates trap-mode suffix for instructions that accept the | |
2285 | sui suffix (cvtqt and cvtqs). | |
e5958492 RK |
2286 | |
2287 | , Generates single precision suffix for floating point | |
2288 | instructions (s for IEEE, f for VAX) | |
2289 | ||
2290 | - Generates double precision suffix for floating point | |
2291 | instructions (t for IEEE, g for VAX) | |
2bf6230d | 2292 | */ |
1a94ca49 | 2293 | |
2bf6230d | 2294 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
e83015a9 RH |
2295 | ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \ |
2296 | || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-') | |
1a94ca49 RK |
2297 | \f |
2298 | /* Print a memory address as an operand to reference that memory location. */ | |
2299 | ||
714b019c RH |
2300 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
2301 | print_operand_address((FILE), (ADDR)) | |
2302 | ||
1a94ca49 RK |
2303 | /* Define the codes that are matched by predicates in alpha.c. */ |
2304 | ||
e3208d53 RH |
2305 | #define PREDICATE_CODES \ |
2306 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
eb8da868 RH |
2307 | {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ |
2308 | {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ | |
2309 | {"cint8_operand", {CONST_INT}}, \ | |
2310 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2311 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2312 | {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 | 2313 | {"const48_operand", {CONST_INT}}, \ |
eb8da868 RH |
2314 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ |
2315 | {"or_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 RH |
2316 | {"mode_mask_operand", {CONST_INT}}, \ |
2317 | {"mul8_operand", {CONST_INT}}, \ | |
2318 | {"mode_width_operand", {CONST_INT}}, \ | |
2319 | {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2320 | {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ | |
2321 | {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ | |
2322 | {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ | |
2323 | {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ | |
2324 | {"fp0_operand", {CONST_DOUBLE}}, \ | |
2325 | {"current_file_function_operand", {SYMBOL_REF}}, \ | |
2326 | {"call_operand", {REG, SYMBOL_REF}}, \ | |
2327 | {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ | |
eb8da868 | 2328 | SYMBOL_REF, CONST, LABEL_REF}}, \ |
e3208d53 | 2329 | {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
eb8da868 | 2330 | SYMBOL_REF, CONST, LABEL_REF}}, \ |
e3208d53 RH |
2331 | {"aligned_memory_operand", {MEM}}, \ |
2332 | {"unaligned_memory_operand", {MEM}}, \ | |
2333 | {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ | |
2334 | {"any_memory_operand", {MEM}}, \ | |
40b80dad | 2335 | {"hard_fp_register_operand", {SUBREG, REG}}, \ |
67070f5c RH |
2336 | {"reg_not_elim_operand", {SUBREG, REG}}, \ |
2337 | {"reg_no_subreg_operand", {REG}}, | |
03f8c4cc | 2338 | \f |
34fa88ab RK |
2339 | /* Tell collect that the object format is ECOFF. */ |
2340 | #define OBJECT_FORMAT_COFF | |
2341 | #define EXTENDED_COFF | |
2342 | ||
2343 | /* If we use NM, pass -g to it so it only lists globals. */ | |
2344 | #define NM_FLAGS "-pg" | |
2345 | ||
03f8c4cc RK |
2346 | /* Definitions for debugging. */ |
2347 | ||
2348 | #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ | |
2349 | #define DBX_DEBUGGING_INFO /* generate embedded stabs */ | |
2350 | #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ | |
2351 | ||
2352 | #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ | |
fe0986b4 | 2353 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG |
03f8c4cc RK |
2354 | #endif |
2355 | ||
2356 | ||
2357 | /* Correct the offset of automatic variables and arguments. Note that | |
2358 | the Alpha debug format wants all automatic variables and arguments | |
2359 | to be in terms of two different offsets from the virtual frame pointer, | |
2360 | which is the stack pointer before any adjustment in the function. | |
2361 | The offset for the argument pointer is fixed for the native compiler, | |
2362 | it is either zero (for the no arguments case) or large enough to hold | |
2363 | all argument registers. | |
2364 | The offset for the auto pointer is the fourth argument to the .frame | |
2365 | directive (local_offset). | |
2366 | To stay compatible with the native tools we use the same offsets | |
2367 | from the virtual frame pointer and adjust the debugger arg/auto offsets | |
2368 | accordingly. These debugger offsets are set up in output_prolog. */ | |
2369 | ||
9a0b18f2 RK |
2370 | extern long alpha_arg_offset; |
2371 | extern long alpha_auto_offset; | |
03f8c4cc RK |
2372 | #define DEBUGGER_AUTO_OFFSET(X) \ |
2373 | ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) | |
2374 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) | |
2375 | ||
2376 | ||
2377 | #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ | |
2378 | alpha_output_lineno (STREAM, LINE) | |
2379 | extern void alpha_output_lineno (); | |
2380 | ||
2381 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ | |
2382 | alpha_output_filename (STREAM, NAME) | |
2383 | extern void alpha_output_filename (); | |
2384 | ||
4330b0e7 JW |
2385 | /* mips-tfile.c limits us to strings of one page. We must underestimate this |
2386 | number, because the real length runs past this up to the next | |
2387 | continuation point. This is really a dbxout.c bug. */ | |
2388 | #define DBX_CONTIN_LENGTH 3000 | |
03f8c4cc RK |
2389 | |
2390 | /* By default, turn on GDB extensions. */ | |
2391 | #define DEFAULT_GDB_EXTENSIONS 1 | |
2392 | ||
7aadc7c2 RK |
2393 | /* Stabs-in-ECOFF can't handle dbxout_function_end(). */ |
2394 | #define NO_DBX_FUNCTION_END 1 | |
2395 | ||
03f8c4cc RK |
2396 | /* If we are smuggling stabs through the ALPHA ECOFF object |
2397 | format, put a comment in front of the .stab<x> operation so | |
2398 | that the ALPHA assembler does not choke. The mips-tfile program | |
2399 | will correctly put the stab into the object file. */ | |
2400 | ||
2401 | #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs") | |
2402 | #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn") | |
2403 | #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd") | |
2404 | ||
2405 | /* Forward references to tags are allowed. */ | |
2406 | #define SDB_ALLOW_FORWARD_REFERENCES | |
2407 | ||
2408 | /* Unknown tags are also allowed. */ | |
2409 | #define SDB_ALLOW_UNKNOWN_REFERENCES | |
2410 | ||
2411 | #define PUT_SDB_DEF(a) \ | |
2412 | do { \ | |
2413 | fprintf (asm_out_file, "\t%s.def\t", \ | |
2414 | (TARGET_GAS) ? "" : "#"); \ | |
2415 | ASM_OUTPUT_LABELREF (asm_out_file, a); \ | |
2416 | fputc (';', asm_out_file); \ | |
2417 | } while (0) | |
2418 | ||
2419 | #define PUT_SDB_PLAIN_DEF(a) \ | |
2420 | do { \ | |
2421 | fprintf (asm_out_file, "\t%s.def\t.%s;", \ | |
2422 | (TARGET_GAS) ? "" : "#", (a)); \ | |
2423 | } while (0) | |
2424 | ||
2425 | #define PUT_SDB_TYPE(a) \ | |
2426 | do { \ | |
2427 | fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ | |
2428 | } while (0) | |
2429 | ||
2430 | /* For block start and end, we create labels, so that | |
2431 | later we can figure out where the correct offset is. | |
2432 | The normal .ent/.end serve well enough for functions, | |
2433 | so those are just commented out. */ | |
2434 | ||
2435 | extern int sdb_label_count; /* block start/end next label # */ | |
2436 | ||
2437 | #define PUT_SDB_BLOCK_START(LINE) \ | |
2438 | do { \ | |
2439 | fprintf (asm_out_file, \ | |
2440 | "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ | |
2441 | sdb_label_count, \ | |
2442 | (TARGET_GAS) ? "" : "#", \ | |
2443 | sdb_label_count, \ | |
2444 | (LINE)); \ | |
2445 | sdb_label_count++; \ | |
2446 | } while (0) | |
2447 | ||
2448 | #define PUT_SDB_BLOCK_END(LINE) \ | |
2449 | do { \ | |
2450 | fprintf (asm_out_file, \ | |
2451 | "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ | |
2452 | sdb_label_count, \ | |
2453 | (TARGET_GAS) ? "" : "#", \ | |
2454 | sdb_label_count, \ | |
2455 | (LINE)); \ | |
2456 | sdb_label_count++; \ | |
2457 | } while (0) | |
2458 | ||
2459 | #define PUT_SDB_FUNCTION_START(LINE) | |
2460 | ||
2461 | #define PUT_SDB_FUNCTION_END(LINE) | |
2462 | ||
3c303f52 | 2463 | #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME)) |
03f8c4cc | 2464 | |
03f8c4cc RK |
2465 | /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for |
2466 | mips-tdump.c to print them out. | |
2467 | ||
2468 | These must match the corresponding definitions in gdb/mipsread.c. | |
2469 | Unfortunately, gcc and gdb do not currently share any directories. */ | |
2470 | ||
2471 | #define CODE_MASK 0x8F300 | |
2472 | #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) | |
2473 | #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) | |
2474 | #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) | |
2475 | ||
2476 | /* Override some mips-tfile definitions. */ | |
2477 | ||
2478 | #define SHASH_SIZE 511 | |
2479 | #define THASH_SIZE 55 | |
1e6c6f11 RK |
2480 | |
2481 | /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ | |
2482 | ||
2483 | #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) | |
2f55b70b | 2484 | |
54190234 JM |
2485 | /* The linker will stick __main into the .init section. */ |
2486 | #define HAS_INIT_SECTION | |
68d69835 JM |
2487 | #define LD_INIT_SWITCH "-init" |
2488 | #define LD_FINI_SWITCH "-fini" | |
b0435cf4 RH |
2489 | |
2490 | /* The system headers under Alpha systems are generally C++-aware. */ | |
2491 | #define NO_IMPLICIT_EXTERN_C | |
47747e53 | 2492 | |
3c303f52 | 2493 | /* Prototypes for alpha.c functions used in the md file & elsewhere. */ |
47747e53 | 2494 | extern struct rtx_def *get_unaligned_address (); |
3c303f52 KG |
2495 | extern void alpha_write_verstamp (); |
2496 | extern void alpha_reorg (); | |
2497 | extern int check_float_value (); | |
2498 | extern int direct_return (); | |
2499 | extern int const48_operand (); | |
2500 | extern int add_operand (); | |
2501 | extern int and_operand (); | |
2502 | extern int unaligned_memory_operand (); | |
2503 | extern int zap_mask (); | |
2504 | extern int current_file_function_operand (); | |
2505 | extern int alpha_sa_size (); | |
2506 | extern int alpha_adjust_cost (); | |
2507 | extern void print_operand (); | |
714b019c | 2508 | extern void print_operand_address (); |
3c303f52 KG |
2509 | extern int reg_or_0_operand (); |
2510 | extern int reg_or_8bit_operand (); | |
2511 | extern int mul8_operand (); | |
2512 | extern int reg_or_6bit_operand (); | |
2513 | extern int alpha_comparison_operator (); | |
2514 | extern int alpha_swapped_comparison_operator (); | |
2515 | extern int sext_add_operand (); | |
2516 | extern int cint8_operand (); | |
2517 | extern int mode_mask_operand (); | |
2518 | extern int or_operand (); | |
2519 | extern int mode_width_operand (); | |
2520 | extern int reg_or_fp0_operand (); | |
2521 | extern int signed_comparison_operator (); | |
2522 | extern int fp0_operand (); | |
2523 | extern int some_operand (); | |
2524 | extern int input_operand (); | |
2525 | extern int divmod_operator (); | |
2526 | extern int call_operand (); | |
2527 | extern int reg_or_cint_operand (); | |
2528 | extern int hard_fp_register_operand (); | |
40b80dad | 2529 | extern int reg_not_elim_operand (); |
3c303f52 KG |
2530 | extern void alpha_set_memflags (); |
2531 | extern int aligned_memory_operand (); | |
2532 | extern void get_aligned_mem (); | |
2533 | extern void alpha_expand_unaligned_load (); | |
2534 | extern void alpha_expand_unaligned_store (); | |
2535 | extern int alpha_expand_block_move (); | |
2536 | extern int alpha_expand_block_clear (); | |
2537 | extern void alpha_expand_prologue (); | |
2538 | extern void alpha_expand_epilogue (); |