]>
Commit | Line | Data |
---|---|---|
1a94ca49 | 1 | /* Definitions of target machine for GNU compiler, for DEC Alpha. |
9ddd9abd | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
cf011243 | 3 | 2000, 2001 Free Software Foundation, Inc. |
1e6c6f11 | 4 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1a94ca49 RK |
5 | |
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
38ead7f3 RK |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
1a94ca49 RK |
22 | |
23 | ||
887af1f2 RO |
24 | /* For C++ we need to ensure that __LANGUAGE_C_PLUS_PLUS is defined independent |
25 | of the source file extension. */ | |
26 | #define CPLUSPLUS_CPP_SPEC "\ | |
27 | -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus \ | |
28 | %(cpp) \ | |
29 | " | |
30 | ||
21798cd8 RK |
31 | /* Write out the correct language type definition for the header files. |
32 | Unless we have assembler language, write out the symbols for C. */ | |
1a94ca49 | 33 | #define CPP_SPEC "\ |
952fc2ed RH |
34 | %{!undef:\ |
35 | %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\ | |
952fc2ed | 36 | %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\ |
887af1f2 | 37 | %{!.S:%{!.cc:%{!.cxx:%{!.cpp:%{!.cp:%{!.c++:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}}}}\ |
952fc2ed RH |
38 | %{mieee:-D_IEEE_FP }\ |
39 | %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\ | |
40 | %(cpp_cpu) %(cpp_subtarget)" | |
41 | ||
42 | #ifndef CPP_SUBTARGET_SPEC | |
43 | #define CPP_SUBTARGET_SPEC "" | |
44 | #endif | |
1a94ca49 RK |
45 | |
46 | /* Set the spec to use for signed char. The default tests the above macro | |
47 | but DEC's compiler can't handle the conditional in a "constant" | |
48 | operand. */ | |
49 | ||
50 | #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}" | |
51 | ||
b890f297 | 52 | #define WORD_SWITCH_TAKES_ARG(STR) \ |
2efe55c1 | 53 | (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR)) |
8877eb00 | 54 | |
1a94ca49 RK |
55 | /* Print subsidiary information on the compiler version in use. */ |
56 | #define TARGET_VERSION | |
57 | ||
1a94ca49 RK |
58 | /* Run-time compilation parameters selecting different hardware subsets. */ |
59 | ||
f6f6a13c RK |
60 | /* Which processor to schedule for. The cpu attribute defines a list that |
61 | mirrors this list, so changes to alpha.md must be made at the same time. */ | |
62 | ||
63 | enum processor_type | |
64 | {PROCESSOR_EV4, /* 2106[46]{a,} */ | |
e9a25f70 JL |
65 | PROCESSOR_EV5, /* 21164{a,pc,} */ |
66 | PROCESSOR_EV6}; /* 21264 */ | |
f6f6a13c RK |
67 | |
68 | extern enum processor_type alpha_cpu; | |
69 | ||
2bf6230d RK |
70 | enum alpha_trap_precision |
71 | { | |
72 | ALPHA_TP_PROG, /* No precision (default). */ | |
73 | ALPHA_TP_FUNC, /* Trap contained within originating function. */ | |
74 | ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */ | |
75 | }; | |
76 | ||
77 | enum alpha_fp_rounding_mode | |
78 | { | |
79 | ALPHA_FPRM_NORM, /* Normal rounding mode. */ | |
80 | ALPHA_FPRM_MINF, /* Round towards minus-infinity. */ | |
81 | ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */ | |
82 | ALPHA_FPRM_DYN /* Dynamic rounding mode. */ | |
83 | }; | |
84 | ||
85 | enum alpha_fp_trap_mode | |
86 | { | |
87 | ALPHA_FPTM_N, /* Normal trap mode. */ | |
88 | ALPHA_FPTM_U, /* Underflow traps enabled. */ | |
89 | ALPHA_FPTM_SU, /* Software completion, w/underflow traps */ | |
90 | ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */ | |
91 | }; | |
92 | ||
1a94ca49 RK |
93 | extern int target_flags; |
94 | ||
2bf6230d RK |
95 | extern enum alpha_trap_precision alpha_tp; |
96 | extern enum alpha_fp_rounding_mode alpha_fprm; | |
97 | extern enum alpha_fp_trap_mode alpha_fptm; | |
98 | ||
1a94ca49 RK |
99 | /* This means that floating-point support exists in the target implementation |
100 | of the Alpha architecture. This is usually the default. */ | |
de4abb91 | 101 | #define MASK_FP (1 << 0) |
2bf6230d | 102 | #define TARGET_FP (target_flags & MASK_FP) |
1a94ca49 RK |
103 | |
104 | /* This means that floating-point registers are allowed to be used. Note | |
105 | that Alpha implementations without FP operations are required to | |
106 | provide the FP registers. */ | |
107 | ||
de4abb91 | 108 | #define MASK_FPREGS (1 << 1) |
2bf6230d | 109 | #define TARGET_FPREGS (target_flags & MASK_FPREGS) |
03f8c4cc RK |
110 | |
111 | /* This means that gas is used to process the assembler file. */ | |
112 | ||
de4abb91 | 113 | #define MASK_GAS (1 << 2) |
03f8c4cc | 114 | #define TARGET_GAS (target_flags & MASK_GAS) |
1a94ca49 | 115 | |
2bf6230d RK |
116 | /* This means that we should mark procedures as IEEE conformant. */ |
117 | ||
de4abb91 | 118 | #define MASK_IEEE_CONFORMANT (1 << 3) |
2bf6230d RK |
119 | #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT) |
120 | ||
121 | /* This means we should be IEEE-compliant except for inexact. */ | |
122 | ||
de4abb91 | 123 | #define MASK_IEEE (1 << 4) |
2bf6230d RK |
124 | #define TARGET_IEEE (target_flags & MASK_IEEE) |
125 | ||
126 | /* This means we should be fully IEEE-compliant. */ | |
127 | ||
de4abb91 | 128 | #define MASK_IEEE_WITH_INEXACT (1 << 5) |
2bf6230d RK |
129 | #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT) |
130 | ||
803fee69 RK |
131 | /* This means we must construct all constants rather than emitting |
132 | them as literal data. */ | |
133 | ||
de4abb91 | 134 | #define MASK_BUILD_CONSTANTS (1 << 6) |
803fee69 RK |
135 | #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS) |
136 | ||
e5958492 RK |
137 | /* This means we handle floating points in VAX F- (float) |
138 | or G- (double) Format. */ | |
139 | ||
de4abb91 | 140 | #define MASK_FLOAT_VAX (1 << 7) |
e5958492 RK |
141 | #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX) |
142 | ||
e9a25f70 JL |
143 | /* This means that the processor has byte and half word loads and stores |
144 | (the BWX extension). */ | |
025f3281 | 145 | |
de4abb91 | 146 | #define MASK_BWX (1 << 8) |
e9a25f70 | 147 | #define TARGET_BWX (target_flags & MASK_BWX) |
025f3281 | 148 | |
e9a25f70 | 149 | /* This means that the processor has the MAX extension. */ |
de4abb91 | 150 | #define MASK_MAX (1 << 9) |
e9a25f70 JL |
151 | #define TARGET_MAX (target_flags & MASK_MAX) |
152 | ||
de4abb91 RH |
153 | /* This means that the processor has the FIX extension. */ |
154 | #define MASK_FIX (1 << 10) | |
155 | #define TARGET_FIX (target_flags & MASK_FIX) | |
156 | ||
157 | /* This means that the processor has the CIX extension. */ | |
158 | #define MASK_CIX (1 << 11) | |
159 | #define TARGET_CIX (target_flags & MASK_CIX) | |
160 | ||
a3b815cb JJ |
161 | /* This means that the processor is an EV5, EV56, or PCA56. |
162 | Unlike alpha_cpu this is not affected by -mtune= setting. */ | |
a76c0119 | 163 | #define MASK_CPU_EV5 (1 << 28) |
a3b815cb | 164 | #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5) |
e9a25f70 JL |
165 | |
166 | /* Likewise for EV6. */ | |
a76c0119 | 167 | #define MASK_CPU_EV6 (1 << 29) |
a3b815cb | 168 | #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6) |
e9a25f70 JL |
169 | |
170 | /* This means we support the .arch directive in the assembler. Only | |
171 | defined in TARGET_CPU_DEFAULT. */ | |
a76c0119 | 172 | #define MASK_SUPPORT_ARCH (1 << 30) |
e9a25f70 | 173 | #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH) |
8f87939b | 174 | |
9ba3994a | 175 | /* These are for target os support and cannot be changed at runtime. */ |
be7b80f4 RH |
176 | #define TARGET_ABI_WINDOWS_NT 0 |
177 | #define TARGET_ABI_OPEN_VMS 0 | |
178 | #define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT && !TARGET_ABI_OPEN_VMS) | |
9ba3994a RH |
179 | |
180 | #ifndef TARGET_AS_CAN_SUBTRACT_LABELS | |
181 | #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS | |
182 | #endif | |
9c0e94a5 RH |
183 | #ifndef TARGET_CAN_FAULT_IN_PROLOGUE |
184 | #define TARGET_CAN_FAULT_IN_PROLOGUE 0 | |
185 | #endif | |
5495cc55 RH |
186 | #ifndef TARGET_HAS_XFLOATING_LIBS |
187 | #define TARGET_HAS_XFLOATING_LIBS 0 | |
188 | #endif | |
4f1c5cce RH |
189 | #ifndef TARGET_PROFILING_NEEDS_GP |
190 | #define TARGET_PROFILING_NEEDS_GP 0 | |
191 | #endif | |
ccb83cbc RH |
192 | #ifndef TARGET_LD_BUGGY_LDGP |
193 | #define TARGET_LD_BUGGY_LDGP 0 | |
194 | #endif | |
9ba3994a | 195 | |
1a94ca49 RK |
196 | /* Macro to define tables used to set the flags. |
197 | This is a list in braces of pairs in braces, | |
198 | each pair being { "NAME", VALUE } | |
199 | where VALUE is the bits to set or minus the bits to clear. | |
200 | An empty string NAME is used to identify the default VALUE. */ | |
201 | ||
f8e52397 | 202 | #define TARGET_SWITCHES \ |
047142d3 PT |
203 | { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \ |
204 | {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \ | |
205 | {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \ | |
206 | {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \ | |
207 | N_("Do not use fp registers")}, \ | |
208 | {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \ | |
209 | {"gas", MASK_GAS, N_("Assume GAS")}, \ | |
f8e52397 | 210 | {"ieee-conformant", MASK_IEEE_CONFORMANT, \ |
047142d3 | 211 | N_("Request IEEE-conformant math library routines (OSF/1)")}, \ |
f8e52397 | 212 | {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \ |
047142d3 | 213 | N_("Emit IEEE-conformant code, without inexact exceptions")}, \ |
f8e52397 | 214 | {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \ |
047142d3 | 215 | N_("Emit IEEE-conformant code, with inexact exceptions")}, \ |
f8e52397 | 216 | {"build-constants", MASK_BUILD_CONSTANTS, \ |
047142d3 PT |
217 | N_("Do not emit complex integer constants to read-only memory")}, \ |
218 | {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \ | |
219 | {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \ | |
220 | {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \ | |
f8e52397 | 221 | {"no-bwx", -MASK_BWX, ""}, \ |
047142d3 PT |
222 | {"max", MASK_MAX, \ |
223 | N_("Emit code for the motion video ISA extension")}, \ | |
f8e52397 | 224 | {"no-max", -MASK_MAX, ""}, \ |
047142d3 PT |
225 | {"fix", MASK_FIX, \ |
226 | N_("Emit code for the fp move and sqrt ISA extension")}, \ | |
de4abb91 | 227 | {"no-fix", -MASK_FIX, ""}, \ |
047142d3 | 228 | {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \ |
de4abb91 | 229 | {"no-cix", -MASK_CIX, ""}, \ |
f8e52397 | 230 | {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} } |
1a94ca49 | 231 | |
c01b5470 | 232 | #define TARGET_DEFAULT MASK_FP|MASK_FPREGS |
1a94ca49 | 233 | |
88681624 ILT |
234 | #ifndef TARGET_CPU_DEFAULT |
235 | #define TARGET_CPU_DEFAULT 0 | |
236 | #endif | |
237 | ||
2bf6230d RK |
238 | /* This macro is similar to `TARGET_SWITCHES' but defines names of |
239 | command options that have values. Its definition is an initializer | |
240 | with a subgrouping for each command option. | |
241 | ||
242 | Each subgrouping contains a string constant, that defines the fixed | |
243 | part of the option name, and the address of a variable. The | |
244 | variable, type `char *', is set to the variable part of the given | |
245 | option if the fixed part matches. The actual option name is made | |
246 | by appending `-m' to the specified name. | |
247 | ||
248 | Here is an example which defines `-mshort-data-NUMBER'. If the | |
249 | given option is `-mshort-data-512', the variable `m88k_short_data' | |
250 | will be set to the string `"512"'. | |
251 | ||
252 | extern char *m88k_short_data; | |
253 | #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */ | |
254 | ||
df45c7ea | 255 | extern const char *alpha_cpu_string; /* For -mcpu= */ |
a3b815cb | 256 | extern const char *alpha_tune_string; /* For -mtune= */ |
df45c7ea KG |
257 | extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ |
258 | extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ | |
259 | extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ | |
260 | extern const char *alpha_mlat_string; /* For -mmemory-latency= */ | |
2bf6230d | 261 | |
f8e52397 RH |
262 | #define TARGET_OPTIONS \ |
263 | { \ | |
264 | {"cpu=", &alpha_cpu_string, \ | |
a3b815cb JJ |
265 | N_("Use features of and schedule given CPU")}, \ |
266 | {"tune=", &alpha_tune_string, \ | |
267 | N_("Schedule given CPU")}, \ | |
f8e52397 | 268 | {"fp-rounding-mode=", &alpha_fprm_string, \ |
047142d3 | 269 | N_("Control the generated fp rounding mode")}, \ |
f8e52397 | 270 | {"fp-trap-mode=", &alpha_fptm_string, \ |
047142d3 | 271 | N_("Control the IEEE trap mode")}, \ |
f8e52397 | 272 | {"trap-precision=", &alpha_tp_string, \ |
047142d3 | 273 | N_("Control the precision given to fp exceptions")}, \ |
f8e52397 | 274 | {"memory-latency=", &alpha_mlat_string, \ |
047142d3 | 275 | N_("Tune expected memory latency")}, \ |
2bf6230d RK |
276 | } |
277 | ||
952fc2ed RH |
278 | /* Attempt to describe CPU characteristics to the preprocessor. */ |
279 | ||
280 | /* Corresponding to amask... */ | |
2b57e919 NB |
281 | #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx" |
282 | #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max" | |
283 | #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix" | |
284 | #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix" | |
952fc2ed RH |
285 | |
286 | /* Corresponding to implver... */ | |
2b57e919 NB |
287 | #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4" |
288 | #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5" | |
289 | #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6" | |
952fc2ed RH |
290 | |
291 | /* Common combinations. */ | |
292 | #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)" | |
293 | #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)" | |
294 | #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)" | |
295 | #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)" | |
d8ee3e20 RH |
296 | #define CPP_CPU_EV6_SPEC \ |
297 | "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)" | |
298 | #define CPP_CPU_EV67_SPEC \ | |
299 | "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)" | |
952fc2ed RH |
300 | |
301 | #ifndef CPP_CPU_DEFAULT_SPEC | |
302 | # if TARGET_CPU_DEFAULT & MASK_CPU_EV6 | |
8f4773ea | 303 | # if TARGET_CPU_DEFAULT & MASK_CIX |
d8ee3e20 RH |
304 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC |
305 | # else | |
306 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC | |
307 | # endif | |
952fc2ed RH |
308 | # else |
309 | # if TARGET_CPU_DEFAULT & MASK_CPU_EV5 | |
310 | # if TARGET_CPU_DEFAULT & MASK_MAX | |
311 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC | |
312 | # else | |
313 | # if TARGET_CPU_DEFAULT & MASK_BWX | |
314 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC | |
315 | # else | |
316 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC | |
317 | # endif | |
318 | # endif | |
319 | # else | |
320 | # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC | |
321 | # endif | |
322 | # endif | |
323 | #endif /* CPP_CPU_DEFAULT_SPEC */ | |
324 | ||
325 | #ifndef CPP_CPU_SPEC | |
326 | #define CPP_CPU_SPEC "\ | |
2b57e919 | 327 | %{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \ |
952fc2ed RH |
328 | %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\ |
329 | %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\ | |
330 | %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\ | |
331 | %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\ | |
332 | %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\ | |
d8ee3e20 | 333 | %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\ |
952fc2ed RH |
334 | %{!mcpu*:%(cpp_cpu_default) }}" |
335 | #endif | |
336 | ||
337 | /* This macro defines names of additional specifications to put in the | |
338 | specs that can be used in various specifications like CC1_SPEC. Its | |
339 | definition is an initializer with a subgrouping for each command option. | |
340 | ||
341 | Each subgrouping contains a string constant, that defines the | |
342 | specification name, and a string constant that used by the GNU CC driver | |
343 | program. | |
344 | ||
345 | Do not define this macro if it does not need to do anything. */ | |
346 | ||
347 | #ifndef SUBTARGET_EXTRA_SPECS | |
348 | #define SUBTARGET_EXTRA_SPECS | |
349 | #endif | |
350 | ||
829245be KG |
351 | #define EXTRA_SPECS \ |
352 | { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \ | |
353 | { "cpp_am_max", CPP_AM_MAX_SPEC }, \ | |
de4abb91 | 354 | { "cpp_am_fix", CPP_AM_FIX_SPEC }, \ |
829245be KG |
355 | { "cpp_am_cix", CPP_AM_CIX_SPEC }, \ |
356 | { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \ | |
357 | { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \ | |
358 | { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \ | |
359 | { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \ | |
360 | { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \ | |
361 | { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \ | |
362 | { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \ | |
363 | { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \ | |
d8ee3e20 | 364 | { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \ |
829245be KG |
365 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ |
366 | { "cpp_cpu", CPP_CPU_SPEC }, \ | |
367 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ | |
952fc2ed RH |
368 | SUBTARGET_EXTRA_SPECS |
369 | ||
370 | ||
2bf6230d RK |
371 | /* Sometimes certain combinations of command options do not make sense |
372 | on a particular target machine. You can define a macro | |
373 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
374 | defined, is executed once just after all the command options have | |
375 | been parsed. | |
376 | ||
377 | On the Alpha, it is used to translate target-option strings into | |
378 | numeric values. */ | |
379 | ||
2bf6230d RK |
380 | #define OVERRIDE_OPTIONS override_options () |
381 | ||
382 | ||
1a94ca49 RK |
383 | /* Define this macro to change register usage conditional on target flags. |
384 | ||
385 | On the Alpha, we use this to disable the floating-point registers when | |
386 | they don't exist. */ | |
387 | ||
388 | #define CONDITIONAL_REGISTER_USAGE \ | |
389 | if (! TARGET_FPREGS) \ | |
52a69200 | 390 | for (i = 32; i < 63; i++) \ |
1a94ca49 RK |
391 | fixed_regs[i] = call_used_regs[i] = 1; |
392 | ||
4f074454 RK |
393 | /* Show we can debug even without a frame pointer. */ |
394 | #define CAN_DEBUG_WITHOUT_FP | |
1a94ca49 RK |
395 | \f |
396 | /* target machine storage layout */ | |
397 | ||
2700ac93 RS |
398 | /* Define to enable software floating point emulation. */ |
399 | #define REAL_ARITHMETIC | |
400 | ||
1a94ca49 RK |
401 | /* Define the size of `int'. The default is the same as the word size. */ |
402 | #define INT_TYPE_SIZE 32 | |
403 | ||
404 | /* Define the size of `long long'. The default is the twice the word size. */ | |
405 | #define LONG_LONG_TYPE_SIZE 64 | |
406 | ||
407 | /* The two floating-point formats we support are S-floating, which is | |
408 | 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' | |
409 | and `long double' are T. */ | |
410 | ||
411 | #define FLOAT_TYPE_SIZE 32 | |
412 | #define DOUBLE_TYPE_SIZE 64 | |
413 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
414 | ||
5258d7ae RK |
415 | #define WCHAR_TYPE "unsigned int" |
416 | #define WCHAR_TYPE_SIZE 32 | |
1a94ca49 | 417 | |
13d39dbc | 418 | /* Define this macro if it is advisable to hold scalars in registers |
1a94ca49 RK |
419 | in a wider mode than that declared by the program. In such cases, |
420 | the value is constrained to be within the bounds of the declared | |
421 | type, but kept valid in the wider mode. The signedness of the | |
422 | extension may differ from that of the type. | |
423 | ||
424 | For Alpha, we always store objects in a full register. 32-bit objects | |
425 | are always sign-extended, but smaller objects retain their signedness. */ | |
426 | ||
427 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
428 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
429 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
430 | { \ | |
431 | if ((MODE) == SImode) \ | |
432 | (UNSIGNEDP) = 0; \ | |
433 | (MODE) = DImode; \ | |
434 | } | |
435 | ||
436 | /* Define this if function arguments should also be promoted using the above | |
437 | procedure. */ | |
438 | ||
439 | #define PROMOTE_FUNCTION_ARGS | |
440 | ||
441 | /* Likewise, if the function return value is promoted. */ | |
442 | ||
443 | #define PROMOTE_FUNCTION_RETURN | |
444 | ||
445 | /* Define this if most significant bit is lowest numbered | |
446 | in instructions that operate on numbered bit-fields. | |
447 | ||
448 | There are no such instructions on the Alpha, but the documentation | |
449 | is little endian. */ | |
450 | #define BITS_BIG_ENDIAN 0 | |
451 | ||
452 | /* Define this if most significant byte of a word is the lowest numbered. | |
453 | This is false on the Alpha. */ | |
454 | #define BYTES_BIG_ENDIAN 0 | |
455 | ||
456 | /* Define this if most significant word of a multiword number is lowest | |
457 | numbered. | |
458 | ||
459 | For Alpha we can decide arbitrarily since there are no machine instructions | |
460 | for them. Might as well be consistent with bytes. */ | |
461 | #define WORDS_BIG_ENDIAN 0 | |
462 | ||
463 | /* number of bits in an addressable storage unit */ | |
464 | #define BITS_PER_UNIT 8 | |
465 | ||
466 | /* Width in bits of a "word", which is the contents of a machine register. | |
467 | Note that this is not necessarily the width of data type `int'; | |
468 | if using 16-bit ints on a 68000, this would still be 32. | |
469 | But on a machine with 16-bit registers, this would be 16. */ | |
470 | #define BITS_PER_WORD 64 | |
471 | ||
472 | /* Width of a word, in units (bytes). */ | |
473 | #define UNITS_PER_WORD 8 | |
474 | ||
475 | /* Width in bits of a pointer. | |
476 | See also the macro `Pmode' defined below. */ | |
477 | #define POINTER_SIZE 64 | |
478 | ||
479 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
480 | #define PARM_BOUNDARY 64 | |
481 | ||
482 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
483 | #define STACK_BOUNDARY 64 | |
484 | ||
485 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
c176c051 | 486 | #define FUNCTION_BOUNDARY 32 |
1a94ca49 RK |
487 | |
488 | /* Alignment of field after `int : 0' in a structure. */ | |
489 | #define EMPTY_FIELD_BOUNDARY 64 | |
490 | ||
491 | /* Every structure's size must be a multiple of this. */ | |
492 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
493 | ||
494 | /* A bitfield declared as `int' forces `int' alignment for the struct. */ | |
495 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
496 | ||
1a94ca49 | 497 | /* No data type wants to be aligned rounder than this. */ |
5495cc55 | 498 | #define BIGGEST_ALIGNMENT 128 |
1a94ca49 | 499 | |
d16fe557 RK |
500 | /* For atomic access to objects, must have at least 32-bit alignment |
501 | unless the machine has byte operations. */ | |
13eb1f7f | 502 | #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32)) |
d16fe557 | 503 | |
442b1685 RK |
504 | /* Align all constants and variables to at least a word boundary so |
505 | we can pick up pieces of them faster. */ | |
6c174fc0 RH |
506 | /* ??? Only if block-move stuff knows about different source/destination |
507 | alignment. */ | |
508 | #if 0 | |
442b1685 RK |
509 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) |
510 | #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) | |
6c174fc0 | 511 | #endif |
1a94ca49 RK |
512 | |
513 | /* Set this non-zero if move instructions will actually fail to work | |
514 | when given unaligned data. | |
515 | ||
516 | Since we get an error message when we do one, call them invalid. */ | |
517 | ||
518 | #define STRICT_ALIGNMENT 1 | |
519 | ||
520 | /* Set this non-zero if unaligned move instructions are extremely slow. | |
521 | ||
522 | On the Alpha, they trap. */ | |
130d2d72 | 523 | |
e1565e65 | 524 | #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 |
1a94ca49 RK |
525 | \f |
526 | /* Standard register usage. */ | |
527 | ||
528 | /* Number of actual hardware registers. | |
529 | The hardware registers are assigned numbers for the compiler | |
530 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
531 | All registers that the compiler knows about must be given numbers, | |
532 | even those that are not normally considered general registers. | |
533 | ||
534 | We define all 32 integer registers, even though $31 is always zero, | |
535 | and all 32 floating-point registers, even though $f31 is also | |
536 | always zero. We do not bother defining the FP status register and | |
130d2d72 RK |
537 | there are no other registers. |
538 | ||
539 | Since $31 is always zero, we will use register number 31 as the | |
540 | argument pointer. It will never appear in the generated code | |
541 | because we will always be eliminating it in favor of the stack | |
52a69200 RK |
542 | pointer or hardware frame pointer. |
543 | ||
544 | Likewise, we use $f31 for the frame pointer, which will always | |
545 | be eliminated in favor of the hardware frame pointer or the | |
546 | stack pointer. */ | |
1a94ca49 RK |
547 | |
548 | #define FIRST_PSEUDO_REGISTER 64 | |
549 | ||
550 | /* 1 for registers that have pervasive standard uses | |
551 | and are not available for the register allocator. */ | |
552 | ||
553 | #define FIXED_REGISTERS \ | |
554 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
555 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ | |
556 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
557 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 } | |
558 | ||
559 | /* 1 for registers not available across function calls. | |
560 | These must include the FIXED_REGISTERS and also any | |
561 | registers that can be used without being saved. | |
562 | The latter must include the registers where values are returned | |
563 | and the register where structure-value addresses are passed. | |
564 | Aside from that, you can include as many other registers as you like. */ | |
565 | #define CALL_USED_REGISTERS \ | |
566 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \ | |
567 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \ | |
568 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ | |
569 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } | |
570 | ||
571 | /* List the order in which to allocate registers. Each register must be | |
572 | listed once, even those in FIXED_REGISTERS. | |
573 | ||
574 | We allocate in the following order: | |
2c4be73e | 575 | $f10-$f15 (nonsaved floating-point register) |
1a94ca49 RK |
576 | $f22-$f30 (likewise) |
577 | $f21-$f16 (likewise, but input args) | |
578 | $f0 (nonsaved, but return value) | |
2c4be73e | 579 | $f1 (nonsaved, but immediate before saved) |
1a94ca49 RK |
580 | $f2-$f9 (saved floating-point registers) |
581 | $1-$8 (nonsaved integer registers) | |
582 | $22-$25 (likewise) | |
583 | $28 (likewise) | |
584 | $0 (likewise, but return value) | |
585 | $21-$16 (likewise, but input args) | |
0076aa6b | 586 | $27 (procedure value in OSF, nonsaved in NT) |
1a94ca49 RK |
587 | $9-$14 (saved integer registers) |
588 | $26 (return PC) | |
589 | $15 (frame pointer) | |
590 | $29 (global pointer) | |
52a69200 | 591 | $30, $31, $f31 (stack pointer and always zero/ap & fp) */ |
1a94ca49 RK |
592 | |
593 | #define REG_ALLOC_ORDER \ | |
2c4be73e | 594 | {42, 43, 44, 45, 46, 47, \ |
1a94ca49 RK |
595 | 54, 55, 56, 57, 58, 59, 60, 61, 62, \ |
596 | 53, 52, 51, 50, 49, 48, \ | |
2c4be73e | 597 | 32, 33, \ |
1a94ca49 RK |
598 | 34, 35, 36, 37, 38, 39, 40, 41, \ |
599 | 1, 2, 3, 4, 5, 6, 7, 8, \ | |
600 | 22, 23, 24, 25, \ | |
601 | 28, \ | |
602 | 0, \ | |
603 | 21, 20, 19, 18, 17, 16, \ | |
604 | 27, \ | |
605 | 9, 10, 11, 12, 13, 14, \ | |
606 | 26, \ | |
607 | 15, \ | |
608 | 29, \ | |
609 | 30, 31, 63 } | |
610 | ||
611 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
612 | to hold something of mode MODE. | |
613 | This is ordinarily the length in words of a value of mode MODE | |
614 | but can be less for certain modes in special long registers. */ | |
615 | ||
616 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
617 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
618 | ||
619 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
620 | On Alpha, the integer registers can hold any mode. The floating-point | |
621 | registers can hold 32-bit and 64-bit integers as well, but not 16-bit | |
a7adf08e | 622 | or 8-bit values. */ |
1a94ca49 | 623 | |
e6a8ebb4 RH |
624 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
625 | ((REGNO) >= 32 && (REGNO) <= 62 \ | |
626 | ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \ | |
627 | : 1) | |
628 | ||
629 | /* A C expression that is nonzero if a value of mode | |
630 | MODE1 is accessible in mode MODE2 without copying. | |
1a94ca49 | 631 | |
e6a8ebb4 RH |
632 | This asymmetric test is true when MODE1 could be put |
633 | in an FP register but MODE2 could not. */ | |
1a94ca49 | 634 | |
a7adf08e | 635 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
e6a8ebb4 RH |
636 | (HARD_REGNO_MODE_OK (32, (MODE1)) \ |
637 | ? HARD_REGNO_MODE_OK (32, (MODE2)) \ | |
a7adf08e | 638 | : 1) |
1a94ca49 RK |
639 | |
640 | /* Specify the registers used for certain standard purposes. | |
641 | The values of these macros are register numbers. */ | |
642 | ||
643 | /* Alpha pc isn't overloaded on a register that the compiler knows about. */ | |
644 | /* #define PC_REGNUM */ | |
645 | ||
646 | /* Register to use for pushing function arguments. */ | |
647 | #define STACK_POINTER_REGNUM 30 | |
648 | ||
649 | /* Base register for access to local variables of the function. */ | |
52a69200 | 650 | #define HARD_FRAME_POINTER_REGNUM 15 |
1a94ca49 RK |
651 | |
652 | /* Value should be nonzero if functions must have frame pointers. | |
653 | Zero means the frame pointer need not be set up (and parms | |
654 | may be accessed via the stack pointer) in functions that seem suitable. | |
655 | This is computed in `reload', in reload1.c. */ | |
656 | #define FRAME_POINTER_REQUIRED 0 | |
657 | ||
658 | /* Base register for access to arguments of the function. */ | |
130d2d72 | 659 | #define ARG_POINTER_REGNUM 31 |
1a94ca49 | 660 | |
52a69200 RK |
661 | /* Base register for access to local variables of function. */ |
662 | #define FRAME_POINTER_REGNUM 63 | |
663 | ||
1a94ca49 RK |
664 | /* Register in which static-chain is passed to a function. |
665 | ||
666 | For the Alpha, this is based on an example; the calling sequence | |
667 | doesn't seem to specify this. */ | |
668 | #define STATIC_CHAIN_REGNUM 1 | |
669 | ||
670 | /* Register in which address to store a structure value | |
671 | arrives in the function. On the Alpha, the address is passed | |
672 | as a hidden argument. */ | |
673 | #define STRUCT_VALUE 0 | |
674 | \f | |
675 | /* Define the classes of registers for register constraints in the | |
676 | machine description. Also define ranges of constants. | |
677 | ||
678 | One of the classes must always be named ALL_REGS and include all hard regs. | |
679 | If there is more than one class, another class must be named NO_REGS | |
680 | and contain no registers. | |
681 | ||
682 | The name GENERAL_REGS must be the name of a class (or an alias for | |
683 | another name such as ALL_REGS). This is the class of registers | |
684 | that is allowed by "g" or "r" in a register constraint. | |
685 | Also, registers outside this class are allocated only when | |
686 | instructions express preferences for them. | |
687 | ||
688 | The classes must be numbered in nondecreasing order; that is, | |
689 | a larger-numbered class must never be contained completely | |
690 | in a smaller-numbered class. | |
691 | ||
692 | For any two classes, it is very desirable that there be another | |
693 | class that represents their union. */ | |
694 | ||
93c89ab3 | 695 | enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS, |
1a94ca49 RK |
696 | LIM_REG_CLASSES }; |
697 | ||
698 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
699 | ||
700 | /* Give names of register classes as strings for dump file. */ | |
701 | ||
702 | #define REG_CLASS_NAMES \ | |
93c89ab3 | 703 | {"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } |
1a94ca49 RK |
704 | |
705 | /* Define which registers fit in which classes. | |
706 | This is an initializer for a vector of HARD_REG_SET | |
707 | of length N_REG_CLASSES. */ | |
708 | ||
709 | #define REG_CLASS_CONTENTS \ | |
93c89ab3 | 710 | { {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} } |
1a94ca49 RK |
711 | |
712 | /* The same information, inverted: | |
713 | Return the class number of the smallest class containing | |
714 | reg number REGNO. This could be a conditional expression | |
715 | or could index an array. */ | |
716 | ||
93c89ab3 RH |
717 | #define REGNO_REG_CLASS(REGNO) \ |
718 | ((REGNO) == 27 ? PV_REG \ | |
719 | : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \ | |
720 | : GENERAL_REGS) | |
1a94ca49 RK |
721 | |
722 | /* The class value for index registers, and the one for base regs. */ | |
723 | #define INDEX_REG_CLASS NO_REGS | |
724 | #define BASE_REG_CLASS GENERAL_REGS | |
725 | ||
726 | /* Get reg_class from a letter such as appears in the machine description. */ | |
727 | ||
728 | #define REG_CLASS_FROM_LETTER(C) \ | |
93c89ab3 | 729 | ((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS) |
1a94ca49 RK |
730 | |
731 | /* Define this macro to change register usage conditional on target flags. */ | |
732 | /* #define CONDITIONAL_REGISTER_USAGE */ | |
733 | ||
734 | /* The letters I, J, K, L, M, N, O, and P in a register constraint string | |
735 | can be used to stand for particular ranges of immediate operands. | |
736 | This macro defines what the ranges are. | |
737 | C is the letter, and VALUE is a constant value. | |
738 | Return 1 if VALUE is in the range specified by C. | |
739 | ||
740 | For Alpha: | |
741 | `I' is used for the range of constants most insns can contain. | |
742 | `J' is the constant zero. | |
743 | `K' is used for the constant in an LDA insn. | |
744 | `L' is used for the constant in a LDAH insn. | |
745 | `M' is used for the constants that can be AND'ed with using a ZAP insn. | |
746 | `N' is used for complemented 8-bit constants. | |
747 | `O' is used for negated 8-bit constants. | |
748 | `P' is used for the constants 1, 2 and 3. */ | |
749 | ||
750 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
751 | ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \ | |
752 | : (C) == 'J' ? (VALUE) == 0 \ | |
753 | : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ | |
754 | : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ | |
c905c108 | 755 | && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \ |
1a94ca49 RK |
756 | : (C) == 'M' ? zap_mask (VALUE) \ |
757 | : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \ | |
758 | : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \ | |
759 | : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \ | |
760 | : 0) | |
761 | ||
762 | /* Similar, but for floating or large integer constants, and defining letters | |
763 | G and H. Here VALUE is the CONST_DOUBLE rtx itself. | |
764 | ||
765 | For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE | |
766 | that is the operand of a ZAP insn. */ | |
767 | ||
768 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ | |
769 | ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \ | |
770 | && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \ | |
771 | : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \ | |
772 | && zap_mask (CONST_DOUBLE_LOW (VALUE)) \ | |
773 | && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \ | |
774 | : 0) | |
775 | ||
e560f226 RK |
776 | /* Optional extra constraints for this machine. |
777 | ||
778 | For the Alpha, `Q' means that this is a memory operand but not a | |
ac030a7b | 779 | reference to an unaligned location. |
9ec36da5 | 780 | |
ac030a7b | 781 | `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current |
9ec36da5 JL |
782 | function. |
783 | ||
784 | 'S' is a 6-bit constant (valid for a shift insn). */ | |
e560f226 RK |
785 | |
786 | #define EXTRA_CONSTRAINT(OP, C) \ | |
ab87f8c8 | 787 | ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \ |
9ec36da5 JL |
788 | : (C) == 'R' ? current_file_function_operand (OP, Pmode) \ |
789 | : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \ | |
790 | && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \ | |
e560f226 RK |
791 | : 0) |
792 | ||
1a94ca49 RK |
793 | /* Given an rtx X being reloaded into a reg required to be |
794 | in class CLASS, return the class of reg to actually use. | |
795 | In general this is just CLASS; but on some machines | |
796 | in some cases it is preferable to use a more restrictive class. | |
797 | ||
798 | On the Alpha, all constants except zero go into a floating-point | |
799 | register via memory. */ | |
800 | ||
801 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
802 | (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \ | |
a6a503ed | 803 | ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\ |
1a94ca49 RK |
804 | : (CLASS)) |
805 | ||
806 | /* Loading and storing HImode or QImode values to and from memory | |
807 | usually requires a scratch register. The exceptions are loading | |
e008606e RK |
808 | QImode and HImode from an aligned address to a general register |
809 | unless byte instructions are permitted. | |
ddd5a7c1 | 810 | We also cannot load an unaligned address or a paradoxical SUBREG into an |
e868b518 | 811 | FP register. */ |
1a94ca49 | 812 | |
3611aef0 RH |
813 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \ |
814 | secondary_reload_class((CLASS), (MODE), (IN), 1) | |
815 | ||
816 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \ | |
817 | secondary_reload_class((CLASS), (MODE), (OUT), 0) | |
1a94ca49 RK |
818 | |
819 | /* If we are copying between general and FP registers, we need a memory | |
de4abb91 | 820 | location unless the FIX extension is available. */ |
1a94ca49 | 821 | |
e9a25f70 | 822 | #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ |
de4abb91 | 823 | (! TARGET_FIX && (CLASS1) != (CLASS2)) |
1a94ca49 | 824 | |
acd94aaf RK |
825 | /* Specify the mode to be used for memory when a secondary memory |
826 | location is needed. If MODE is floating-point, use it. Otherwise, | |
827 | widen to a word like the default. This is needed because we always | |
828 | store integers in FP registers in quadword format. This whole | |
829 | area is very tricky! */ | |
830 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
831 | (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \ | |
e868b518 | 832 | : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \ |
acd94aaf RK |
833 | : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0)) |
834 | ||
1a94ca49 RK |
835 | /* Return the maximum number of consecutive registers |
836 | needed to represent mode MODE in a register of class CLASS. */ | |
837 | ||
838 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
839 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
840 | ||
c31dfe4d | 841 | /* If defined, gives a class of registers that cannot be used as the |
02188693 | 842 | operand of a SUBREG that changes the mode of the object illegally. */ |
c31dfe4d | 843 | |
02188693 RH |
844 | #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS |
845 | ||
846 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
847 | ||
848 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
849 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
c31dfe4d | 850 | |
1a94ca49 RK |
851 | /* Define the cost of moving between registers of various classes. Moving |
852 | between FLOAT_REGS and anything else except float regs is expensive. | |
853 | In fact, we make it quite expensive because we really don't want to | |
854 | do these moves unless it is clearly worth it. Optimizations may | |
855 | reduce the impact of not being able to allocate a pseudo to a | |
856 | hard register. */ | |
857 | ||
cf011243 | 858 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
71d9b493 RH |
859 | (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \ |
860 | ? 2 \ | |
de4abb91 | 861 | : TARGET_FIX ? 3 : 4+2*alpha_memory_latency) |
1a94ca49 RK |
862 | |
863 | /* A C expressions returning the cost of moving data of MODE from a register to | |
864 | or from memory. | |
865 | ||
866 | On the Alpha, bump this up a bit. */ | |
867 | ||
bcbbac26 | 868 | extern int alpha_memory_latency; |
cbd5b9a2 | 869 | #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency) |
1a94ca49 RK |
870 | |
871 | /* Provide the cost of a branch. Exact meaning under development. */ | |
872 | #define BRANCH_COST 5 | |
1a94ca49 RK |
873 | \f |
874 | /* Stack layout; function entry, exit and calling. */ | |
875 | ||
876 | /* Define this if pushing a word on the stack | |
877 | makes the stack pointer a smaller address. */ | |
878 | #define STACK_GROWS_DOWNWARD | |
879 | ||
880 | /* Define this if the nominal address of the stack frame | |
881 | is at the high-address end of the local variables; | |
882 | that is, each additional local variable allocated | |
883 | goes at a more negative offset in the frame. */ | |
130d2d72 | 884 | /* #define FRAME_GROWS_DOWNWARD */ |
1a94ca49 RK |
885 | |
886 | /* Offset within stack frame to start allocating local variables at. | |
887 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
888 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
889 | of the first local allocated. */ | |
890 | ||
52a69200 | 891 | #define STARTING_FRAME_OFFSET 0 |
1a94ca49 RK |
892 | |
893 | /* If we generate an insn to push BYTES bytes, | |
894 | this says how many the stack pointer really advances by. | |
895 | On Alpha, don't define this because there are no push insns. */ | |
896 | /* #define PUSH_ROUNDING(BYTES) */ | |
897 | ||
e008606e RK |
898 | /* Define this to be nonzero if stack checking is built into the ABI. */ |
899 | #define STACK_CHECK_BUILTIN 1 | |
900 | ||
1a94ca49 RK |
901 | /* Define this if the maximum size of all the outgoing args is to be |
902 | accumulated and pushed during the prologue. The amount can be | |
903 | found in the variable current_function_outgoing_args_size. */ | |
f73ad30e | 904 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1a94ca49 RK |
905 | |
906 | /* Offset of first parameter from the argument pointer register value. */ | |
907 | ||
130d2d72 | 908 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
1a94ca49 RK |
909 | |
910 | /* Definitions for register eliminations. | |
911 | ||
978e8952 | 912 | We have two registers that can be eliminated on the Alpha. First, the |
1a94ca49 | 913 | frame pointer register can often be eliminated in favor of the stack |
130d2d72 RK |
914 | pointer register. Secondly, the argument pointer register can always be |
915 | eliminated; it is replaced with either the stack or frame pointer. */ | |
1a94ca49 RK |
916 | |
917 | /* This is an array of structures. Each structure initializes one pair | |
918 | of eliminable registers. The "from" register number is given first, | |
919 | followed by "to". Eliminations of the same "from" register are listed | |
920 | in order of preference. */ | |
921 | ||
52a69200 RK |
922 | #define ELIMINABLE_REGS \ |
923 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
924 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
925 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
926 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
1a94ca49 RK |
927 | |
928 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
929 | Frame pointer elimination is automatically handled. | |
930 | ||
130d2d72 | 931 | All eliminations are valid since the cases where FP can't be |
1a94ca49 RK |
932 | eliminated are already handled. */ |
933 | ||
130d2d72 | 934 | #define CAN_ELIMINATE(FROM, TO) 1 |
1a94ca49 | 935 | |
52a69200 RK |
936 | /* Round up to a multiple of 16 bytes. */ |
937 | #define ALPHA_ROUND(X) (((X) + 15) & ~ 15) | |
938 | ||
1a94ca49 RK |
939 | /* Define the offset between two registers, one to be eliminated, and the other |
940 | its replacement, at the start of a routine. */ | |
941 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
52a69200 RK |
942 | { if ((FROM) == FRAME_POINTER_REGNUM) \ |
943 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
944 | + alpha_sa_size ()); \ | |
945 | else if ((FROM) == ARG_POINTER_REGNUM) \ | |
946 | (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \ | |
947 | + alpha_sa_size () \ | |
d772039b RK |
948 | + (ALPHA_ROUND (get_frame_size () \ |
949 | + current_function_pretend_args_size) \ | |
950 | - current_function_pretend_args_size)); \ | |
c8d8ed65 RK |
951 | else \ |
952 | abort (); \ | |
1a94ca49 RK |
953 | } |
954 | ||
955 | /* Define this if stack space is still allocated for a parameter passed | |
956 | in a register. */ | |
957 | /* #define REG_PARM_STACK_SPACE */ | |
958 | ||
959 | /* Value is the number of bytes of arguments automatically | |
960 | popped when returning from a subroutine call. | |
8b109b37 | 961 | FUNDECL is the declaration node of the function (as a tree), |
1a94ca49 RK |
962 | FUNTYPE is the data type of the function (as a tree), |
963 | or for a library call it is an identifier node for the subroutine name. | |
964 | SIZE is the number of bytes of arguments passed on the stack. */ | |
965 | ||
8b109b37 | 966 | #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 |
1a94ca49 RK |
967 | |
968 | /* Define how to find the value returned by a function. | |
969 | VALTYPE is the data type of the value (as a tree). | |
970 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
971 | otherwise, FUNC is 0. | |
972 | ||
973 | On Alpha the value is found in $0 for integer functions and | |
974 | $f0 for floating-point functions. */ | |
975 | ||
c5c76735 | 976 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
4c020733 | 977 | gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \ |
c5c76735 JL |
978 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ |
979 | || POINTER_TYPE_P (VALTYPE)) \ | |
4c020733 RH |
980 | ? word_mode : TYPE_MODE (VALTYPE), \ |
981 | ((TARGET_FPREGS \ | |
c5c76735 | 982 | && (TREE_CODE (VALTYPE) == REAL_TYPE \ |
4c020733 | 983 | || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \ |
c5c76735 | 984 | ? 32 : 0)) |
1a94ca49 RK |
985 | |
986 | /* Define how to find the value returned by a library function | |
987 | assuming the value has mode MODE. */ | |
988 | ||
c5c76735 | 989 | #define LIBCALL_VALUE(MODE) \ |
4c020733 | 990 | gen_rtx_REG (MODE, \ |
c5c76735 JL |
991 | (TARGET_FPREGS \ |
992 | && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ | |
4c020733 | 993 | || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ |
c5c76735 | 994 | ? 32 : 0)) |
1a94ca49 | 995 | |
130d2d72 RK |
996 | /* The definition of this macro implies that there are cases where |
997 | a scalar value cannot be returned in registers. | |
998 | ||
999 | For the Alpha, any structure or union type is returned in memory, as | |
1000 | are integers whose size is larger than 64 bits. */ | |
1001 | ||
1002 | #define RETURN_IN_MEMORY(TYPE) \ | |
e14fa9c4 | 1003 | (TYPE_MODE (TYPE) == BLKmode \ |
5495cc55 RH |
1004 | || TYPE_MODE (TYPE) == TFmode \ |
1005 | || TYPE_MODE (TYPE) == TCmode \ | |
130d2d72 RK |
1006 | || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64)) |
1007 | ||
1a94ca49 RK |
1008 | /* 1 if N is a possible register number for a function value |
1009 | as seen by the caller. */ | |
1010 | ||
e5958492 RK |
1011 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1012 | ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33) | |
1a94ca49 RK |
1013 | |
1014 | /* 1 if N is a possible register number for function argument passing. | |
1015 | On Alpha, these are $16-$21 and $f16-$f21. */ | |
1016 | ||
1017 | #define FUNCTION_ARG_REGNO_P(N) \ | |
1018 | (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32)) | |
1019 | \f | |
1020 | /* Define a data type for recording info about an argument list | |
1021 | during the scan of that argument list. This data type should | |
1022 | hold all necessary information about the function itself | |
1023 | and about the args processed so far, enough to enable macros | |
1024 | such as FUNCTION_ARG to determine where the next arg should go. | |
1025 | ||
1026 | On Alpha, this is a single integer, which is a number of words | |
1027 | of arguments scanned so far. | |
1028 | Thus 6 or more means all following args should go on the stack. */ | |
1029 | ||
1030 | #define CUMULATIVE_ARGS int | |
1031 | ||
1032 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1033 | for a call to a function whose data type is FNTYPE. | |
1034 | For a library call, FNTYPE is 0. */ | |
1035 | ||
2c7ee1a6 | 1036 | #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0 |
1a94ca49 RK |
1037 | |
1038 | /* Define intermediate macro to compute the size (in registers) of an argument | |
1039 | for the Alpha. */ | |
1040 | ||
1041 | #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \ | |
5495cc55 RH |
1042 | ((MODE) == TFmode || (MODE) == TCmode ? 1 \ |
1043 | : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ | |
1044 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
1a94ca49 RK |
1045 | |
1046 | /* Update the data in CUM to advance over an argument | |
1047 | of mode MODE and data type TYPE. | |
1048 | (TYPE is null for libcalls where that information may not be available.) */ | |
1049 | ||
1050 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1051 | if (MUST_PASS_IN_STACK (MODE, TYPE)) \ | |
1052 | (CUM) = 6; \ | |
1053 | else \ | |
1054 | (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED) | |
1055 | ||
1056 | /* Determine where to put an argument to a function. | |
1057 | Value is zero to push the argument on the stack, | |
1058 | or a hard register in which to store the argument. | |
1059 | ||
1060 | MODE is the argument's machine mode. | |
1061 | TYPE is the data type of the argument (as a tree). | |
1062 | This is null for libcalls where that information may | |
1063 | not be available. | |
1064 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1065 | the preceding args and about the function being called. | |
1066 | NAMED is nonzero if this argument is a named parameter | |
1067 | (otherwise it is an extra parameter matching an ellipsis). | |
1068 | ||
1069 | On Alpha the first 6 words of args are normally in registers | |
1070 | and the rest are pushed. */ | |
1071 | ||
1072 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
5495cc55 RH |
1073 | function_arg((CUM), (MODE), (TYPE), (NAMED)) |
1074 | ||
1075 | /* A C expression that indicates when an argument must be passed by | |
1076 | reference. If nonzero for an argument, a copy of that argument is | |
1077 | made in memory and a pointer to the argument is passed instead of | |
1078 | the argument itself. The pointer is passed in whatever way is | |
1079 | appropriate for passing a pointer to that type. */ | |
1080 | ||
1081 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
1082 | ((MODE) == TFmode || (MODE) == TCmode) | |
1a94ca49 | 1083 | |
1a94ca49 RK |
1084 | /* Specify the padding direction of arguments. |
1085 | ||
1086 | On the Alpha, we must pad upwards in order to be able to pass args in | |
1087 | registers. */ | |
1088 | ||
1089 | #define FUNCTION_ARG_PADDING(MODE, TYPE) upward | |
1090 | ||
1091 | /* For an arg passed partly in registers and partly in memory, | |
1092 | this is the number of registers used. | |
1093 | For args passed entirely in registers or entirely in memory, zero. */ | |
1094 | ||
1095 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ | |
1096 | ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \ | |
1097 | ? 6 - (CUM) : 0) | |
1098 | ||
130d2d72 RK |
1099 | /* Perform any needed actions needed for a function that is receiving a |
1100 | variable number of arguments. | |
1101 | ||
1102 | CUM is as above. | |
1103 | ||
1104 | MODE and TYPE are the mode and type of the current parameter. | |
1105 | ||
1106 | PRETEND_SIZE is a variable that should be set to the amount of stack | |
1107 | that must be pushed by the prolog to pretend that our caller pushed | |
1108 | it. | |
1109 | ||
1110 | Normally, this macro will push all remaining incoming registers on the | |
1111 | stack and set PRETEND_SIZE to the length of the registers pushed. | |
1112 | ||
1113 | On the Alpha, we allocate space for all 12 arg registers, but only | |
1114 | push those that are remaining. | |
1115 | ||
1116 | However, if NO registers need to be saved, don't allocate any space. | |
1117 | This is not only because we won't need the space, but because AP includes | |
1118 | the current_pretend_args_size and we don't want to mess up any | |
7a92339b RK |
1119 | ap-relative addresses already made. |
1120 | ||
1121 | If we are not to use the floating-point registers, save the integer | |
1122 | registers where we would put the floating-point registers. This is | |
1123 | not the most efficient way to implement varargs with just one register | |
1124 | class, but it isn't worth doing anything more efficient in this rare | |
1125 | case. */ | |
1126 | ||
130d2d72 RK |
1127 | #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ |
1128 | { if ((CUM) < 6) \ | |
1129 | { \ | |
1130 | if (! (NO_RTL)) \ | |
1131 | { \ | |
63966b3b RH |
1132 | rtx tmp; int set = get_varargs_alias_set (); \ |
1133 | tmp = gen_rtx_MEM (BLKmode, \ | |
1134 | plus_constant (virtual_incoming_args_rtx, \ | |
1135 | ((CUM) + 6)* UNITS_PER_WORD)); \ | |
1136 | MEM_ALIAS_SET (tmp) = set; \ | |
130d2d72 | 1137 | move_block_from_reg \ |
63966b3b | 1138 | (16 + CUM, tmp, \ |
02892e06 | 1139 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
63966b3b RH |
1140 | \ |
1141 | tmp = gen_rtx_MEM (BLKmode, \ | |
1142 | plus_constant (virtual_incoming_args_rtx, \ | |
1143 | (CUM) * UNITS_PER_WORD)); \ | |
1144 | MEM_ALIAS_SET (tmp) = set; \ | |
130d2d72 | 1145 | move_block_from_reg \ |
63966b3b | 1146 | (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \ |
02892e06 | 1147 | 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \ |
130d2d72 RK |
1148 | } \ |
1149 | PRETEND_SIZE = 12 * UNITS_PER_WORD; \ | |
1150 | } \ | |
1151 | } | |
1152 | ||
7d89dda5 RH |
1153 | /* We do not allow indirect calls to be optimized into sibling calls, nor |
1154 | can we allow a call to a function in a different compilation unit to | |
1155 | be optimized into a sibcall. Except if the function is known not to | |
1156 | return, in which case our caller doesn't care what the gp is. */ | |
1157 | #define FUNCTION_OK_FOR_SIBCALL(DECL) \ | |
1158 | (DECL \ | |
1159 | && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \ | |
9a1ba437 | 1160 | || ! TREE_PUBLIC (DECL))) |
7d89dda5 | 1161 | |
c8e9adec RK |
1162 | /* Try to output insns to set TARGET equal to the constant C if it can be |
1163 | done in less than N insns. Do all computations in MODE. Returns the place | |
1164 | where the output has been placed if it can be done and the insns have been | |
1165 | emitted. If it would take more than N insns, zero is returned and no | |
1166 | insns and emitted. */ | |
92e40a7a | 1167 | |
1a94ca49 RK |
1168 | /* Define the information needed to generate branch and scc insns. This is |
1169 | stored from the compare operation. Note that we can't use "rtx" here | |
1170 | since it hasn't been defined! */ | |
1171 | ||
6db21c7f RH |
1172 | struct alpha_compare |
1173 | { | |
1174 | struct rtx_def *op0, *op1; | |
1175 | int fp_p; | |
1176 | }; | |
1177 | ||
1178 | extern struct alpha_compare alpha_compare; | |
1a94ca49 | 1179 | |
e5958492 | 1180 | /* Make (or fake) .linkage entry for function call. |
e5958492 | 1181 | IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */ |
e5958492 | 1182 | |
bcbbac26 RH |
1183 | /* This macro defines the start of an assembly comment. */ |
1184 | ||
1185 | #define ASM_COMMENT_START " #" | |
1186 | ||
acd92049 | 1187 | /* This macro produces the initial definition of a function. */ |
1a94ca49 | 1188 | |
acd92049 RH |
1189 | #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ |
1190 | alpha_start_function(FILE,NAME,DECL); | |
1a94ca49 | 1191 | |
acd92049 | 1192 | /* This macro closes up a function definition for the assembler. */ |
9c0e94a5 | 1193 | |
acd92049 RH |
1194 | #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \ |
1195 | alpha_end_function(FILE,NAME,DECL) | |
acd92049 | 1196 | |
acd92049 RH |
1197 | /* Output any profiling code before the prologue. */ |
1198 | ||
1199 | #define PROFILE_BEFORE_PROLOGUE 1 | |
1200 | ||
1a94ca49 | 1201 | /* Output assembler code to FILE to increment profiler label # LABELNO |
e0fb9029 | 1202 | for profiling a function entry. Under OSF/1, profiling is enabled |
ddd5a7c1 | 1203 | by simply passing -pg to the assembler and linker. */ |
85d159a3 | 1204 | |
e0fb9029 | 1205 | #define FUNCTION_PROFILER(FILE, LABELNO) |
85d159a3 RK |
1206 | |
1207 | /* Output assembler code to FILE to initialize this source file's | |
1208 | basic block profiling info, if that has not already been done. | |
1209 | This assumes that __bb_init_func doesn't garble a1-a5. */ | |
1210 | ||
1211 | #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ | |
1212 | do { \ | |
1213 | ASM_OUTPUT_REG_PUSH (FILE, 16); \ | |
a62eb16f JW |
1214 | fputs ("\tlda $16,$PBX32\n", (FILE)); \ |
1215 | fputs ("\tldq $26,0($16)\n", (FILE)); \ | |
1216 | fputs ("\tbne $26,1f\n", (FILE)); \ | |
1217 | fputs ("\tlda $27,__bb_init_func\n", (FILE)); \ | |
1218 | fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \ | |
1219 | fputs ("\tldgp $29,0($26)\n", (FILE)); \ | |
1220 | fputs ("1:\n", (FILE)); \ | |
85d159a3 RK |
1221 | ASM_OUTPUT_REG_POP (FILE, 16); \ |
1222 | } while (0); | |
1223 | ||
1224 | /* Output assembler code to FILE to increment the entry-count for | |
1225 | the BLOCKNO'th basic block in this source file. */ | |
1226 | ||
1227 | #define BLOCK_PROFILER(FILE, BLOCKNO) \ | |
1228 | do { \ | |
1229 | int blockn = (BLOCKNO); \ | |
a62eb16f | 1230 | fputs ("\tsubq $30,16,$30\n", (FILE)); \ |
70a76f06 RK |
1231 | fputs ("\tstq $26,0($30)\n", (FILE)); \ |
1232 | fputs ("\tstq $27,8($30)\n", (FILE)); \ | |
1233 | fputs ("\tlda $26,$PBX34\n", (FILE)); \ | |
1234 | fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \ | |
1235 | fputs ("\taddq $27,1,$27\n", (FILE)); \ | |
1236 | fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \ | |
1237 | fputs ("\tldq $26,0($30)\n", (FILE)); \ | |
1238 | fputs ("\tldq $27,8($30)\n", (FILE)); \ | |
a62eb16f | 1239 | fputs ("\taddq $30,16,$30\n", (FILE)); \ |
85d159a3 | 1240 | } while (0) |
1a94ca49 | 1241 | |
1a94ca49 RK |
1242 | |
1243 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1244 | the stack pointer does not matter. The value is tested only in | |
1245 | functions that have frame pointers. | |
1246 | No definition is equivalent to always zero. */ | |
1247 | ||
1248 | #define EXIT_IGNORE_STACK 1 | |
c112e233 RH |
1249 | |
1250 | /* Define registers used by the epilogue and return instruction. */ | |
1251 | ||
1252 | #define EPILOGUE_USES(REGNO) ((REGNO) == 26) | |
1a94ca49 RK |
1253 | \f |
1254 | /* Output assembler code for a block containing the constant parts | |
1255 | of a trampoline, leaving space for the variable parts. | |
1256 | ||
1257 | The trampoline should set the static chain pointer to value placed | |
7981384f RK |
1258 | into the trampoline and should branch to the specified routine. |
1259 | Note that $27 has been set to the address of the trampoline, so we can | |
1260 | use it for addressability of the two data items. Trampolines are always | |
1261 | aligned to FUNCTION_BOUNDARY, which is 64 bits. */ | |
1a94ca49 RK |
1262 | |
1263 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
c714f03d | 1264 | do { \ |
7981384f | 1265 | fprintf (FILE, "\tldq $1,24($27)\n"); \ |
1a94ca49 | 1266 | fprintf (FILE, "\tldq $27,16($27)\n"); \ |
7981384f RK |
1267 | fprintf (FILE, "\tjmp $31,($27),0\n"); \ |
1268 | fprintf (FILE, "\tnop\n"); \ | |
1a94ca49 | 1269 | fprintf (FILE, "\t.quad 0,0\n"); \ |
c714f03d | 1270 | } while (0) |
1a94ca49 | 1271 | |
3a523eeb RS |
1272 | /* Section in which to place the trampoline. On Alpha, instructions |
1273 | may only be placed in a text segment. */ | |
1274 | ||
1275 | #define TRAMPOLINE_SECTION text_section | |
1276 | ||
1a94ca49 RK |
1277 | /* Length in units of the trampoline for entering a nested function. */ |
1278 | ||
7981384f | 1279 | #define TRAMPOLINE_SIZE 32 |
1a94ca49 RK |
1280 | |
1281 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1282 | FNADDR is an RTX for the address of the function's pure code. | |
c714f03d | 1283 | CXT is an RTX for the static chain value for the function. */ |
1a94ca49 | 1284 | |
9ec36da5 | 1285 | #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ |
c714f03d | 1286 | alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8) |
675f0e7c RK |
1287 | |
1288 | /* A C expression whose value is RTL representing the value of the return | |
1289 | address for the frame COUNT steps up from the current frame. | |
1290 | FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of | |
952fc2ed | 1291 | the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */ |
675f0e7c | 1292 | |
9ecc37f0 | 1293 | #define RETURN_ADDR_RTX alpha_return_addr |
9ecc37f0 | 1294 | |
6abc6f40 RH |
1295 | /* Before the prologue, RA lives in $26. */ |
1296 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26) | |
8034da37 | 1297 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26) |
4573b4de RH |
1298 | |
1299 | /* Describe how we implement __builtin_eh_return. */ | |
1300 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM) | |
1301 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28) | |
1302 | #define EH_RETURN_HANDLER_RTX \ | |
1303 | gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ | |
1304 | current_function_outgoing_args_size)) | |
675f0e7c | 1305 | \f |
1a94ca49 RK |
1306 | /* Addressing modes, and classification of registers for them. */ |
1307 | ||
940da324 JL |
1308 | /* #define HAVE_POST_INCREMENT 0 */ |
1309 | /* #define HAVE_POST_DECREMENT 0 */ | |
1a94ca49 | 1310 | |
940da324 JL |
1311 | /* #define HAVE_PRE_DECREMENT 0 */ |
1312 | /* #define HAVE_PRE_INCREMENT 0 */ | |
1a94ca49 RK |
1313 | |
1314 | /* Macros to check register numbers against specific register classes. */ | |
1315 | ||
1316 | /* These assume that REGNO is a hard or pseudo reg number. | |
1317 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1318 | or a pseudo reg currently allocated to a suitable hard reg. | |
1319 | Since they use reg_renumber, they are safe only once reg_renumber | |
1320 | has been allocated, which happens in local-alloc.c. */ | |
1321 | ||
1322 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
1323 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
52a69200 RK |
1324 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \ |
1325 | || (REGNO) == 63 || reg_renumber[REGNO] == 63) | |
1a94ca49 RK |
1326 | \f |
1327 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1328 | #define MAX_REGS_PER_ADDRESS 1 | |
1329 | ||
1330 | /* Recognize any constant value that is a valid address. For the Alpha, | |
1331 | there are only constants none since we want to use LDA to load any | |
1332 | symbolic addresses into registers. */ | |
1333 | ||
1334 | #define CONSTANT_ADDRESS_P(X) \ | |
1335 | (GET_CODE (X) == CONST_INT \ | |
1336 | && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) | |
1337 | ||
1338 | /* Include all constant integers and constant doubles, but not | |
1339 | floating-point, except for floating-point zero. */ | |
1340 | ||
1341 | #define LEGITIMATE_CONSTANT_P(X) \ | |
1342 | (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ | |
1343 | || (X) == CONST0_RTX (GET_MODE (X))) | |
1344 | ||
1345 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1346 | and check its validity for a certain class. | |
1347 | We have two alternate definitions for each of them. | |
1348 | The usual definition accepts all pseudo regs; the other rejects | |
1349 | them unless they have been allocated suitable hard regs. | |
1350 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
1351 | ||
1352 | Most source files want to accept pseudo regs in the hope that | |
1353 | they will get allocated to the class that the insn wants them to be in. | |
1354 | Source files for reload pass need to be strict. | |
1355 | After reload, it makes no difference, since pseudo regs have | |
1356 | been eliminated by then. */ | |
1357 | ||
1358 | #ifndef REG_OK_STRICT | |
1359 | ||
1360 | /* Nonzero if X is a hard reg that can be used as an index | |
1361 | or if it is a pseudo reg. */ | |
1362 | #define REG_OK_FOR_INDEX_P(X) 0 | |
5d02b6c2 | 1363 | |
1a94ca49 RK |
1364 | /* Nonzero if X is a hard reg that can be used as a base reg |
1365 | or if it is a pseudo reg. */ | |
1366 | #define REG_OK_FOR_BASE_P(X) \ | |
52a69200 | 1367 | (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER) |
1a94ca49 | 1368 | |
5d02b6c2 RH |
1369 | /* ??? Nonzero if X is the frame pointer, or some virtual register |
1370 | that may eliminate to the frame pointer. These will be allowed to | |
1371 | have offsets greater than 32K. This is done because register | |
1372 | elimination offsets will change the hi/lo split, and if we split | |
1373 | before reload, we will require additional instructions. */ | |
1374 | #define REG_OK_FP_BASE_P(X) \ | |
1375 | (REGNO (X) == 31 || REGNO (X) == 63 \ | |
1376 | || (REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
1377 | && REGNO (X) < LAST_VIRTUAL_REGISTER)) | |
1378 | ||
1a94ca49 RK |
1379 | #else |
1380 | ||
1381 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
1382 | #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
5d02b6c2 | 1383 | |
1a94ca49 RK |
1384 | /* Nonzero if X is a hard reg that can be used as a base reg. */ |
1385 | #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1386 | ||
5d02b6c2 RH |
1387 | #define REG_OK_FP_BASE_P(X) 0 |
1388 | ||
1a94ca49 RK |
1389 | #endif |
1390 | \f | |
1391 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1392 | that is a valid memory address for an instruction. | |
1393 | The MODE argument is the machine mode for the MEM expression | |
1394 | that wants to use this address. | |
1395 | ||
1396 | For Alpha, we have either a constant address or the sum of a register | |
1397 | and a constant address, or just a register. For DImode, any of those | |
1398 | forms can be surrounded with an AND that clear the low-order three bits; | |
1399 | this is an "unaligned" access. | |
1400 | ||
1a94ca49 RK |
1401 | First define the basic valid address. */ |
1402 | ||
4c020733 RH |
1403 | #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \ |
1404 | { \ | |
1405 | rtx tmp = (X); \ | |
1406 | if (GET_CODE (tmp) == SUBREG \ | |
1407 | && (GET_MODE_SIZE (GET_MODE (tmp)) \ | |
1408 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \ | |
1409 | tmp = SUBREG_REG (tmp); \ | |
1410 | if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \ | |
1411 | goto ADDR; \ | |
1412 | if (CONSTANT_ADDRESS_P (X)) \ | |
1413 | goto ADDR; \ | |
1414 | if (GET_CODE (X) == PLUS) \ | |
1415 | { \ | |
1416 | tmp = XEXP (X, 0); \ | |
1417 | if (GET_CODE (tmp) == SUBREG \ | |
1418 | && (GET_MODE_SIZE (GET_MODE (tmp)) \ | |
1419 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \ | |
1420 | tmp = SUBREG_REG (tmp); \ | |
1421 | if (REG_P (tmp)) \ | |
1422 | { \ | |
1423 | if (REG_OK_FP_BASE_P (tmp) \ | |
1424 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1425 | goto ADDR; \ | |
1426 | if (REG_OK_FOR_BASE_P (tmp) \ | |
1427 | && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1428 | goto ADDR; \ | |
1429 | } \ | |
0c5912f4 RH |
1430 | else if (GET_CODE (tmp) == ADDRESSOF \ |
1431 | && CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1432 | goto ADDR; \ | |
4c020733 | 1433 | } \ |
1a94ca49 RK |
1434 | } |
1435 | ||
1436 | /* Now accept the simple address, or, for DImode only, an AND of a simple | |
1437 | address that turns off the low three bits. */ | |
1438 | ||
1a94ca49 RK |
1439 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ |
1440 | { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \ | |
1441 | if ((MODE) == DImode \ | |
1442 | && GET_CODE (X) == AND \ | |
1443 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1444 | && INTVAL (XEXP (X, 1)) == -8) \ | |
1445 | GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \ | |
1a94ca49 RK |
1446 | } |
1447 | ||
1448 | /* Try machine-dependent ways of modifying an illegitimate address | |
1449 | to be legitimate. If we find one, return the new, valid address. | |
1450 | This macro is used in only one place: `memory_address' in explow.c. | |
1451 | ||
1452 | OLDX is the address as it was before break_out_memory_refs was called. | |
1453 | In some cases it is useful to look at this to decide what needs to be done. | |
1454 | ||
1455 | MODE and WIN are passed so that this macro can use | |
1456 | GO_IF_LEGITIMATE_ADDRESS. | |
1457 | ||
1458 | It is always safe for this macro to do nothing. It exists to recognize | |
1459 | opportunities to optimize the output. | |
1460 | ||
1461 | For the Alpha, there are three cases we handle: | |
1462 | ||
1463 | (1) If the address is (plus reg const_int) and the CONST_INT is not a | |
1464 | valid offset, compute the high part of the constant and add it to the | |
1465 | register. Then our address is (plus temp low-part-const). | |
1466 | (2) If the address is (const (plus FOO const_int)), find the low-order | |
1467 | part of the CONST_INT. Then load FOO plus any high-order part of the | |
1468 | CONST_INT into a register. Our address is (plus reg low-part-const). | |
1469 | This is done to reduce the number of GOT entries. | |
1470 | (3) If we have a (plus reg const), emit the load as in (2), then add | |
1471 | the two registers, and finally generate (plus reg low-part-const) as | |
1472 | our address. */ | |
1473 | ||
1474 | #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ | |
1475 | { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1476 | && GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1477 | && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \ | |
1478 | { \ | |
1479 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1480 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1481 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1482 | rtx high = GEN_INT (highpart); \ | |
1483 | rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \ | |
80f251fe | 1484 | high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1485 | \ |
1486 | (X) = plus_constant (temp, lowpart); \ | |
1487 | goto WIN; \ | |
1488 | } \ | |
1489 | else if (GET_CODE (X) == CONST \ | |
1490 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1491 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \ | |
1492 | { \ | |
1493 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \ | |
1494 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1495 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1496 | rtx high = XEXP (XEXP (X, 0), 0); \ | |
1497 | \ | |
1498 | if (highpart) \ | |
1499 | high = plus_constant (high, highpart); \ | |
1500 | \ | |
1501 | (X) = plus_constant (force_reg (Pmode, high), lowpart); \ | |
1502 | goto WIN; \ | |
1503 | } \ | |
1504 | else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ | |
1505 | && GET_CODE (XEXP (X, 1)) == CONST \ | |
1506 | && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \ | |
1507 | && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \ | |
1508 | { \ | |
1509 | HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \ | |
1510 | HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \ | |
1511 | HOST_WIDE_INT highpart = val - lowpart; \ | |
1512 | rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \ | |
1513 | \ | |
1514 | if (highpart) \ | |
1515 | high = plus_constant (high, highpart); \ | |
1516 | \ | |
1517 | high = expand_binop (Pmode, add_optab, XEXP (X, 0), \ | |
1518 | force_reg (Pmode, high), \ | |
80f251fe | 1519 | high, 1, OPTAB_LIB_WIDEN); \ |
1a94ca49 RK |
1520 | (X) = plus_constant (high, lowpart); \ |
1521 | goto WIN; \ | |
1522 | } \ | |
1523 | } | |
1524 | ||
a9a2595b JR |
1525 | /* Try a machine-dependent way of reloading an illegitimate address |
1526 | operand. If we find one, push the reload and jump to WIN. This | |
1527 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1528 | ||
1529 | For the Alpha, we wish to handle large displacements off a base | |
1530 | register by splitting the addend across an ldah and the mem insn. | |
1531 | This cuts number of extra insns needed from 3 to 1. */ | |
1532 | ||
1533 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1534 | do { \ | |
c8ab9901 RH |
1535 | /* We must recognize output that we have already generated ourselves. */ \ |
1536 | if (GET_CODE (X) == PLUS \ | |
1537 | && GET_CODE (XEXP (X, 0)) == PLUS \ | |
1538 | && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ | |
1539 | && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ | |
1540 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1541 | { \ | |
df4ae160 | 1542 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
c8ab9901 RH |
1543 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1544 | OPNUM, TYPE); \ | |
1545 | goto WIN; \ | |
1546 | } \ | |
a9a2595b JR |
1547 | if (GET_CODE (X) == PLUS \ |
1548 | && GET_CODE (XEXP (X, 0)) == REG \ | |
1549 | && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ | |
1550 | && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ | |
1551 | && GET_CODE (XEXP (X, 1)) == CONST_INT) \ | |
1552 | { \ | |
1553 | HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ | |
1554 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \ | |
1555 | HOST_WIDE_INT high \ | |
1556 | = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \ | |
1557 | \ | |
1558 | /* Check for 32-bit overflow. */ \ | |
1559 | if (high + low != val) \ | |
1560 | break; \ | |
1561 | \ | |
1562 | /* Reload the high part into a base reg; leave the low part \ | |
1563 | in the mem directly. */ \ | |
1564 | \ | |
1565 | X = gen_rtx_PLUS (GET_MODE (X), \ | |
1566 | gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ | |
1567 | GEN_INT (high)), \ | |
1568 | GEN_INT (low)); \ | |
1569 | \ | |
df4ae160 | 1570 | push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ |
a9a2595b JR |
1571 | BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ |
1572 | OPNUM, TYPE); \ | |
1573 | goto WIN; \ | |
1574 | } \ | |
1575 | } while (0) | |
1576 | ||
1a94ca49 RK |
1577 | /* Go to LABEL if ADDR (a legitimate address expression) |
1578 | has an effect that depends on the machine mode it is used for. | |
1579 | On the Alpha this is true only for the unaligned modes. We can | |
1580 | simplify this test since we know that the address must be valid. */ | |
1581 | ||
1582 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ | |
1583 | { if (GET_CODE (ADDR) == AND) goto LABEL; } | |
1584 | ||
1585 | /* Compute the cost of an address. For the Alpha, all valid addresses are | |
1586 | the same cost. */ | |
1587 | ||
1588 | #define ADDRESS_COST(X) 0 | |
1589 | ||
2ea844d3 RH |
1590 | /* Machine-dependent reorg pass. */ |
1591 | #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X) | |
1a94ca49 RK |
1592 | \f |
1593 | /* Specify the machine mode that this machine uses | |
1594 | for the index in the tablejump instruction. */ | |
1595 | #define CASE_VECTOR_MODE SImode | |
1596 | ||
18543a22 ILT |
1597 | /* Define as C expression which evaluates to nonzero if the tablejump |
1598 | instruction expects the table to contain offsets from the address of the | |
3aa9d5b6 | 1599 | table. |
b0435cf4 | 1600 | |
3aa9d5b6 | 1601 | Do not define this if the table should contain absolute addresses. |
260ced47 RK |
1602 | On the Alpha, the table is really GP-relative, not relative to the PC |
1603 | of the table, but we pretend that it is PC-relative; this should be OK, | |
0076aa6b | 1604 | but we should try to find some better way sometime. */ |
18543a22 | 1605 | #define CASE_VECTOR_PC_RELATIVE 1 |
1a94ca49 RK |
1606 | |
1607 | /* Specify the tree operation to be used to convert reals to integers. */ | |
1608 | #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR | |
1609 | ||
1610 | /* This is the kind of divide that is easiest to do in the general case. */ | |
1611 | #define EASY_DIV_EXPR TRUNC_DIV_EXPR | |
1612 | ||
1613 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1614 | #define DEFAULT_SIGNED_CHAR 1 | |
1615 | ||
1616 | /* This flag, if defined, says the same insns that convert to a signed fixnum | |
1617 | also convert validly to an unsigned one. | |
1618 | ||
1619 | We actually lie a bit here as overflow conditions are different. But | |
1620 | they aren't being checked anyway. */ | |
1621 | ||
1622 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
1623 | ||
1624 | /* Max number of bytes we can move to or from memory | |
1625 | in one reasonably fast instruction. */ | |
1626 | ||
1627 | #define MOVE_MAX 8 | |
1628 | ||
7e24ffc9 HPN |
1629 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
1630 | move-instruction pairs, we will do a movstr or libcall instead. | |
1631 | ||
1632 | Without byte/word accesses, we want no more than four instructions; | |
1633 | with, several single byte accesses are better. */ | |
6c174fc0 RH |
1634 | |
1635 | #define MOVE_RATIO (TARGET_BWX ? 7 : 2) | |
1636 | ||
1a94ca49 RK |
1637 | /* Largest number of bytes of an object that can be placed in a register. |
1638 | On the Alpha we have plenty of registers, so use TImode. */ | |
1639 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) | |
1640 | ||
1641 | /* Nonzero if access to memory by bytes is no faster than for words. | |
1642 | Also non-zero if doing byte operations (specifically shifts) in registers | |
1643 | is undesirable. | |
1644 | ||
1645 | On the Alpha, we want to not use the byte operation and instead use | |
1646 | masking operations to access fields; these will save instructions. */ | |
1647 | ||
1648 | #define SLOW_BYTE_ACCESS 1 | |
1649 | ||
9a63901f RK |
1650 | /* Define if operations between registers always perform the operation |
1651 | on the full register even if a narrower mode is specified. */ | |
1652 | #define WORD_REGISTER_OPERATIONS | |
1653 | ||
1654 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1655 | will either zero-extend or sign-extend. The value of this macro should | |
1656 | be the code that says which one of the two operations is implicitly | |
1657 | done, NIL if none. */ | |
b7747781 | 1658 | #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND) |
1a94ca49 | 1659 | |
225211e2 RK |
1660 | /* Define if loading short immediate values into registers sign extends. */ |
1661 | #define SHORT_IMMEDIATES_SIGN_EXTEND | |
1662 | ||
1a94ca49 RK |
1663 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1664 | is done just by pretending it is already truncated. */ | |
1665 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1666 | ||
1667 | /* We assume that the store-condition-codes instructions store 0 for false | |
1668 | and some other value for true. This is the value stored for true. */ | |
1669 | ||
1670 | #define STORE_FLAG_VALUE 1 | |
1671 | ||
1672 | /* Define the value returned by a floating-point comparison instruction. */ | |
1673 | ||
12530dbe RH |
1674 | #define FLOAT_STORE_FLAG_VALUE(MODE) \ |
1675 | REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE)) | |
1a94ca49 | 1676 | |
35bb77fd RK |
1677 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
1678 | ||
1679 | #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \ | |
1680 | do { \ | |
1681 | if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \ | |
1682 | && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \ | |
1683 | { \ | |
1684 | rtx tem = (OP0); \ | |
1685 | (OP0) = (OP1); \ | |
1686 | (OP1) = tem; \ | |
1687 | (CODE) = swap_condition (CODE); \ | |
1688 | } \ | |
1689 | if (((CODE) == LT || (CODE) == LTU) \ | |
1690 | && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \ | |
1691 | { \ | |
1692 | (CODE) = (CODE) == LT ? LE : LEU; \ | |
1693 | (OP1) = GEN_INT (255); \ | |
1694 | } \ | |
1695 | } while (0) | |
1696 | ||
1a94ca49 RK |
1697 | /* Specify the machine mode that pointers have. |
1698 | After generation of rtl, the compiler makes no further distinction | |
1699 | between pointers and any other objects of this machine mode. */ | |
1700 | #define Pmode DImode | |
1701 | ||
1702 | /* Mode of a function address in a call instruction (for indexing purposes). */ | |
1703 | ||
1704 | #define FUNCTION_MODE Pmode | |
1705 | ||
1706 | /* Define this if addresses of constant functions | |
1707 | shouldn't be put through pseudo regs where they can be cse'd. | |
1708 | Desirable on machines where ordinary constants are expensive | |
1709 | but a CALL with constant address is cheap. | |
1710 | ||
1711 | We define this on the Alpha so that gen_call and gen_call_value | |
1712 | get to see the SYMBOL_REF (for the hint field of the jsr). It will | |
1713 | then copy it into a register, thus actually letting the address be | |
1714 | cse'ed. */ | |
1715 | ||
1716 | #define NO_FUNCTION_CSE | |
1717 | ||
d969caf8 | 1718 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
1a94ca49 | 1719 | few bits. */ |
d969caf8 | 1720 | #define SHIFT_COUNT_TRUNCATED 1 |
1a94ca49 RK |
1721 | |
1722 | /* Compute the cost of computing a constant rtl expression RTX | |
1723 | whose rtx-code is CODE. The body of this macro is a portion | |
1724 | of a switch statement. If the code is computed here, | |
1725 | return it with a return statement. Otherwise, break from the switch. | |
1726 | ||
8b7b2e36 RK |
1727 | If this is an 8-bit constant, return zero since it can be used |
1728 | nearly anywhere with no cost. If it is a valid operand for an | |
1729 | ADD or AND, likewise return 0 if we know it will be used in that | |
1730 | context. Otherwise, return 2 since it might be used there later. | |
1731 | All other constants take at least two insns. */ | |
1a94ca49 RK |
1732 | |
1733 | #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ | |
1734 | case CONST_INT: \ | |
06eb8e92 | 1735 | if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \ |
8b7b2e36 | 1736 | return 0; \ |
1a94ca49 | 1737 | case CONST_DOUBLE: \ |
5d02ee66 RH |
1738 | if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \ |
1739 | return 0; \ | |
1740 | else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \ | |
8b7b2e36 RK |
1741 | || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \ |
1742 | return 0; \ | |
1743 | else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \ | |
1744 | return 2; \ | |
1745 | else \ | |
1746 | return COSTS_N_INSNS (2); \ | |
1a94ca49 RK |
1747 | case CONST: \ |
1748 | case SYMBOL_REF: \ | |
1749 | case LABEL_REF: \ | |
f6f6a13c RK |
1750 | switch (alpha_cpu) \ |
1751 | { \ | |
1752 | case PROCESSOR_EV4: \ | |
1753 | return COSTS_N_INSNS (3); \ | |
1754 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1755 | case PROCESSOR_EV6: \ |
f6f6a13c | 1756 | return COSTS_N_INSNS (2); \ |
5d02ee66 | 1757 | default: abort(); \ |
f6f6a13c | 1758 | } |
1a94ca49 RK |
1759 | |
1760 | /* Provide the costs of a rtl expression. This is in the body of a | |
1761 | switch on CODE. */ | |
1762 | ||
1763 | #define RTX_COSTS(X,CODE,OUTER_CODE) \ | |
3bda6d11 RK |
1764 | case PLUS: case MINUS: \ |
1765 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
f6f6a13c RK |
1766 | switch (alpha_cpu) \ |
1767 | { \ | |
1768 | case PROCESSOR_EV4: \ | |
1769 | return COSTS_N_INSNS (6); \ | |
1770 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1771 | case PROCESSOR_EV6: \ |
f6f6a13c | 1772 | return COSTS_N_INSNS (4); \ |
5d02ee66 | 1773 | default: abort(); \ |
f6f6a13c | 1774 | } \ |
b49e978e RK |
1775 | else if (GET_CODE (XEXP (X, 0)) == MULT \ |
1776 | && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ | |
a5da0afe RK |
1777 | return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ |
1778 | + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ | |
1a94ca49 RK |
1779 | break; \ |
1780 | case MULT: \ | |
f6f6a13c RK |
1781 | switch (alpha_cpu) \ |
1782 | { \ | |
1783 | case PROCESSOR_EV4: \ | |
1784 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1785 | return COSTS_N_INSNS (6); \ | |
1786 | return COSTS_N_INSNS (23); \ | |
1787 | case PROCESSOR_EV5: \ | |
1788 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1789 | return COSTS_N_INSNS (4); \ | |
1790 | else if (GET_MODE (X) == DImode) \ | |
1791 | return COSTS_N_INSNS (12); \ | |
1792 | else \ | |
1793 | return COSTS_N_INSNS (8); \ | |
5d02ee66 RH |
1794 | case PROCESSOR_EV6: \ |
1795 | if (FLOAT_MODE_P (GET_MODE (X))) \ | |
1796 | return COSTS_N_INSNS (4); \ | |
1797 | else \ | |
1798 | return COSTS_N_INSNS (7); \ | |
1799 | default: abort(); \ | |
f6f6a13c | 1800 | } \ |
b49e978e RK |
1801 | case ASHIFT: \ |
1802 | if (GET_CODE (XEXP (X, 1)) == CONST_INT \ | |
1803 | && INTVAL (XEXP (X, 1)) <= 3) \ | |
1804 | break; \ | |
1805 | /* ... fall through ... */ \ | |
5d02ee66 | 1806 | case ASHIFTRT: case LSHIFTRT: \ |
f6f6a13c RK |
1807 | switch (alpha_cpu) \ |
1808 | { \ | |
1809 | case PROCESSOR_EV4: \ | |
1810 | return COSTS_N_INSNS (2); \ | |
1811 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1812 | case PROCESSOR_EV6: \ |
f6f6a13c | 1813 | return COSTS_N_INSNS (1); \ |
5d02ee66 RH |
1814 | default: abort(); \ |
1815 | } \ | |
1816 | case IF_THEN_ELSE: \ | |
1817 | switch (alpha_cpu) \ | |
1818 | { \ | |
1819 | case PROCESSOR_EV4: \ | |
1820 | case PROCESSOR_EV6: \ | |
1821 | return COSTS_N_INSNS (2); \ | |
1822 | case PROCESSOR_EV5: \ | |
1823 | return COSTS_N_INSNS (1); \ | |
1824 | default: abort(); \ | |
f6f6a13c | 1825 | } \ |
3bda6d11 | 1826 | case DIV: case UDIV: case MOD: case UMOD: \ |
f6f6a13c RK |
1827 | switch (alpha_cpu) \ |
1828 | { \ | |
1829 | case PROCESSOR_EV4: \ | |
1830 | if (GET_MODE (X) == SFmode) \ | |
1831 | return COSTS_N_INSNS (34); \ | |
1832 | else if (GET_MODE (X) == DFmode) \ | |
1833 | return COSTS_N_INSNS (63); \ | |
1834 | else \ | |
1835 | return COSTS_N_INSNS (70); \ | |
1836 | case PROCESSOR_EV5: \ | |
1837 | if (GET_MODE (X) == SFmode) \ | |
1838 | return COSTS_N_INSNS (15); \ | |
1839 | else if (GET_MODE (X) == DFmode) \ | |
1840 | return COSTS_N_INSNS (22); \ | |
1841 | else \ | |
5d02ee66 RH |
1842 | return COSTS_N_INSNS (70); /* ??? */ \ |
1843 | case PROCESSOR_EV6: \ | |
1844 | if (GET_MODE (X) == SFmode) \ | |
1845 | return COSTS_N_INSNS (12); \ | |
1846 | else if (GET_MODE (X) == DFmode) \ | |
1847 | return COSTS_N_INSNS (15); \ | |
1848 | else \ | |
1849 | return COSTS_N_INSNS (70); /* ??? */ \ | |
1850 | default: abort(); \ | |
f6f6a13c | 1851 | } \ |
1a94ca49 | 1852 | case MEM: \ |
f6f6a13c RK |
1853 | switch (alpha_cpu) \ |
1854 | { \ | |
1855 | case PROCESSOR_EV4: \ | |
5d02ee66 | 1856 | case PROCESSOR_EV6: \ |
f6f6a13c RK |
1857 | return COSTS_N_INSNS (3); \ |
1858 | case PROCESSOR_EV5: \ | |
1859 | return COSTS_N_INSNS (2); \ | |
5d02ee66 | 1860 | default: abort(); \ |
f6f6a13c RK |
1861 | } \ |
1862 | case NEG: case ABS: \ | |
1863 | if (! FLOAT_MODE_P (GET_MODE (X))) \ | |
1864 | break; \ | |
1865 | /* ... fall through ... */ \ | |
3bda6d11 RK |
1866 | case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \ |
1867 | case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ | |
f6f6a13c RK |
1868 | switch (alpha_cpu) \ |
1869 | { \ | |
1870 | case PROCESSOR_EV4: \ | |
1871 | return COSTS_N_INSNS (6); \ | |
1872 | case PROCESSOR_EV5: \ | |
5d02ee66 | 1873 | case PROCESSOR_EV6: \ |
f6f6a13c | 1874 | return COSTS_N_INSNS (4); \ |
5d02ee66 | 1875 | default: abort(); \ |
f6f6a13c | 1876 | } |
1a94ca49 RK |
1877 | \f |
1878 | /* Control the assembler format that we output. */ | |
1879 | ||
1a94ca49 RK |
1880 | /* Output to assembler file text saying following lines |
1881 | may contain character constants, extra white space, comments, etc. */ | |
1882 | ||
1883 | #define ASM_APP_ON "" | |
1884 | ||
1885 | /* Output to assembler file text saying following lines | |
1886 | no longer contain unusual constructs. */ | |
1887 | ||
1888 | #define ASM_APP_OFF "" | |
1889 | ||
93de6f51 | 1890 | #define TEXT_SECTION_ASM_OP "\t.text" |
1a94ca49 RK |
1891 | |
1892 | /* Output before read-only data. */ | |
1893 | ||
93de6f51 | 1894 | #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" |
1a94ca49 RK |
1895 | |
1896 | /* Output before writable data. */ | |
1897 | ||
93de6f51 | 1898 | #define DATA_SECTION_ASM_OP "\t.data" |
1a94ca49 RK |
1899 | |
1900 | /* Define an extra section for read-only data, a routine to enter it, and | |
c0388f29 RK |
1901 | indicate that it is for read-only data. |
1902 | ||
abc95ed3 | 1903 | The first time we enter the readonly data section for a file, we write |
c0388f29 RK |
1904 | eight bytes of zero. This works around a bug in DEC's assembler in |
1905 | some versions of OSF/1 V3.x. */ | |
1a94ca49 RK |
1906 | |
1907 | #define EXTRA_SECTIONS readonly_data | |
1908 | ||
1909 | #define EXTRA_SECTION_FUNCTIONS \ | |
1910 | void \ | |
1911 | literal_section () \ | |
1912 | { \ | |
1913 | if (in_section != readonly_data) \ | |
1914 | { \ | |
c0388f29 RK |
1915 | static int firsttime = 1; \ |
1916 | \ | |
1a94ca49 | 1917 | fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ |
c0388f29 RK |
1918 | if (firsttime) \ |
1919 | { \ | |
1920 | firsttime = 0; \ | |
1921 | ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \ | |
1922 | } \ | |
1923 | \ | |
1a94ca49 RK |
1924 | in_section = readonly_data; \ |
1925 | } \ | |
1926 | } \ | |
1927 | ||
1928 | #define READONLY_DATA_SECTION literal_section | |
1929 | ||
ac030a7b RK |
1930 | /* If we are referencing a function that is static, make the SYMBOL_REF |
1931 | special. We use this to see indicate we can branch to this function | |
1932 | without setting PV or restoring GP. */ | |
130d2d72 RK |
1933 | |
1934 | #define ENCODE_SECTION_INFO(DECL) \ | |
ac030a7b | 1935 | if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \ |
130d2d72 RK |
1936 | SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; |
1937 | ||
1a94ca49 RK |
1938 | /* How to refer to registers in assembler output. |
1939 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1940 | ||
1941 | #define REGISTER_NAMES \ | |
1942 | {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \ | |
1943 | "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
1944 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
130d2d72 | 1945 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \ |
1a94ca49 RK |
1946 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \ |
1947 | "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
1948 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\ | |
52a69200 | 1949 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"} |
1a94ca49 RK |
1950 | |
1951 | /* How to renumber registers for dbx and gdb. */ | |
1952 | ||
1953 | #define DBX_REGISTER_NUMBER(REGNO) (REGNO) | |
1954 | ||
1955 | /* This is how to output the definition of a user-level label named NAME, | |
1956 | such as the label on a static function or variable NAME. */ | |
1957 | ||
1958 | #define ASM_OUTPUT_LABEL(FILE,NAME) \ | |
1959 | do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) | |
1960 | ||
1961 | /* This is how to output a command to make the user-level label named NAME | |
1962 | defined for reference from other files. */ | |
1963 | ||
1964 | #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ | |
1965 | do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) | |
1966 | ||
4e0c8ad2 | 1967 | /* The prefix to add to user-visible assembler symbols. */ |
1a94ca49 | 1968 | |
4e0c8ad2 | 1969 | #define USER_LABEL_PREFIX "" |
1a94ca49 RK |
1970 | |
1971 | /* This is how to output an internal numbered label where | |
1972 | PREFIX is the class of label and NUM is the number within the class. */ | |
1973 | ||
1974 | #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ | |
531ea24e | 1975 | fprintf (FILE, "$%s%d:\n", PREFIX, NUM) |
1a94ca49 RK |
1976 | |
1977 | /* This is how to output a label for a jump table. Arguments are the same as | |
1978 | for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is | |
1979 | passed. */ | |
1980 | ||
1981 | #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \ | |
1982 | { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); } | |
1983 | ||
1984 | /* This is how to store into the string LABEL | |
1985 | the symbol_ref name of an internal numbered label where | |
1986 | PREFIX is the class of label and NUM is the number within the class. | |
1987 | This is suitable for output with `assemble_name'. */ | |
1988 | ||
1989 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
d1e6b55b | 1990 | sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) |
1a94ca49 | 1991 | |
e247ca2a RK |
1992 | /* Check a floating-point value for validity for a particular machine mode. */ |
1993 | ||
1994 | #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \ | |
1995 | ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW)) | |
1996 | ||
5495cc55 RH |
1997 | /* This is how to output an assembler line defining a `long double' |
1998 | constant. */ | |
1999 | ||
2000 | #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ | |
2001 | do { \ | |
2002 | long t[4]; \ | |
2003 | REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \ | |
2004 | fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \ | |
2005 | t[1] & 0xffffffff, t[0] & 0xffffffff, \ | |
2006 | t[3] & 0xffffffff, t[2] & 0xffffffff); \ | |
2007 | } while (0) | |
2008 | ||
1a94ca49 RK |
2009 | /* This is how to output an assembler line defining a `double' constant. */ |
2010 | ||
e99300f1 | 2011 | #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ |
5495cc55 RH |
2012 | do { \ |
2013 | long t[2]; \ | |
2014 | REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \ | |
2015 | fprintf (FILE, "\t.quad 0x%lx%08lx\n", \ | |
2016 | t[1] & 0xffffffff, t[0] & 0xffffffff); \ | |
2017 | } while (0) | |
1a94ca49 RK |
2018 | |
2019 | /* This is how to output an assembler line defining a `float' constant. */ | |
2020 | ||
e247ca2a RK |
2021 | #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ |
2022 | do { \ | |
2023 | long t; \ | |
2024 | REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \ | |
2025 | fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \ | |
5495cc55 | 2026 | } while (0) |
2700ac93 | 2027 | |
1a94ca49 RK |
2028 | /* This is how to output an assembler line defining an `int' constant. */ |
2029 | ||
2030 | #define ASM_OUTPUT_INT(FILE,VALUE) \ | |
0076aa6b RK |
2031 | ( fprintf (FILE, "\t.long "), \ |
2032 | output_addr_const (FILE, (VALUE)), \ | |
2033 | fprintf (FILE, "\n")) | |
1a94ca49 RK |
2034 | |
2035 | /* This is how to output an assembler line defining a `long' constant. */ | |
2036 | ||
2037 | #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \ | |
2038 | ( fprintf (FILE, "\t.quad "), \ | |
2039 | output_addr_const (FILE, (VALUE)), \ | |
2040 | fprintf (FILE, "\n")) | |
2041 | ||
2042 | /* Likewise for `char' and `short' constants. */ | |
2043 | ||
2044 | #define ASM_OUTPUT_SHORT(FILE,VALUE) \ | |
690ef02f | 2045 | fprintf (FILE, "\t.word %d\n", \ |
3c303f52 | 2046 | (int)(GET_CODE (VALUE) == CONST_INT \ |
45c45e79 | 2047 | ? INTVAL (VALUE) & 0xffff : (abort (), 0))) |
1a94ca49 RK |
2048 | |
2049 | #define ASM_OUTPUT_CHAR(FILE,VALUE) \ | |
45c45e79 | 2050 | fprintf (FILE, "\t.byte %d\n", \ |
3c303f52 | 2051 | (int)(GET_CODE (VALUE) == CONST_INT \ |
45c45e79 | 2052 | ? INTVAL (VALUE) & 0xff : (abort (), 0))) |
1a94ca49 RK |
2053 | |
2054 | /* We use the default ASCII-output routine, except that we don't write more | |
2055 | than 50 characters since the assembler doesn't support very long lines. */ | |
2056 | ||
2057 | #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \ | |
2058 | do { \ | |
2059 | FILE *_hide_asm_out_file = (MYFILE); \ | |
e03c5670 | 2060 | const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \ |
1a94ca49 RK |
2061 | int _hide_thissize = (MYLENGTH); \ |
2062 | int _size_so_far = 0; \ | |
2063 | { \ | |
2064 | FILE *asm_out_file = _hide_asm_out_file; \ | |
e03c5670 | 2065 | const unsigned char *p = _hide_p; \ |
1a94ca49 RK |
2066 | int thissize = _hide_thissize; \ |
2067 | int i; \ | |
2068 | fprintf (asm_out_file, "\t.ascii \""); \ | |
2069 | \ | |
2070 | for (i = 0; i < thissize; i++) \ | |
2071 | { \ | |
2072 | register int c = p[i]; \ | |
2073 | \ | |
2074 | if (_size_so_far ++ > 50 && i < thissize - 4) \ | |
2075 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ | |
2076 | \ | |
2077 | if (c == '\"' || c == '\\') \ | |
2078 | putc ('\\', asm_out_file); \ | |
2079 | if (c >= ' ' && c < 0177) \ | |
2080 | putc (c, asm_out_file); \ | |
2081 | else \ | |
2082 | { \ | |
2083 | fprintf (asm_out_file, "\\%o", c); \ | |
2084 | /* After an octal-escape, if a digit follows, \ | |
2085 | terminate one string constant and start another. \ | |
8aeea6e6 | 2086 | The VAX assembler fails to stop reading the escape \ |
1a94ca49 RK |
2087 | after three digits, so this is the only way we \ |
2088 | can get it to parse the data properly. */ \ | |
2089 | if (i < thissize - 1 \ | |
2090 | && p[i + 1] >= '0' && p[i + 1] <= '9') \ | |
b2d5e311 | 2091 | _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \ |
1a94ca49 RK |
2092 | } \ |
2093 | } \ | |
2094 | fprintf (asm_out_file, "\"\n"); \ | |
2095 | } \ | |
2096 | } \ | |
2097 | while (0) | |
52a69200 | 2098 | |
6690d24c | 2099 | /* To get unaligned data, we have to turn off auto alignment. */ |
93de6f51 HPN |
2100 | #define UNALIGNED_SHORT_ASM_OP "\t.align 0\n\t.word\t" |
2101 | #define UNALIGNED_INT_ASM_OP "\t.align 0\n\t.long\t" | |
2102 | #define UNALIGNED_DOUBLE_INT_ASM_OP "\t.align 0\n\t.quad\t" | |
6690d24c | 2103 | |
1a94ca49 RK |
2104 | /* This is how to output an insn to push a register on the stack. |
2105 | It need not be very fast code. */ | |
2106 | ||
2107 | #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ | |
2108 | fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \ | |
2109 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2110 | (REGNO) & 31); | |
2111 | ||
2112 | /* This is how to output an insn to pop a register from the stack. | |
2113 | It need not be very fast code. */ | |
2114 | ||
2115 | #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ | |
2116 | fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \ | |
2117 | (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \ | |
2118 | (REGNO) & 31); | |
2119 | ||
2120 | /* This is how to output an assembler line for a numeric constant byte. */ | |
2121 | ||
2122 | #define ASM_OUTPUT_BYTE(FILE,VALUE) \ | |
3c303f52 | 2123 | fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff)) |
1a94ca49 | 2124 | |
260ced47 RK |
2125 | /* This is how to output an element of a case-vector that is absolute. |
2126 | (Alpha does not use such vectors, but we must define this macro anyway.) */ | |
1a94ca49 | 2127 | |
260ced47 | 2128 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort () |
1a94ca49 | 2129 | |
260ced47 | 2130 | /* This is how to output an element of a case-vector that is relative. */ |
1a94ca49 | 2131 | |
33f7f353 | 2132 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
be7b80f4 | 2133 | fprintf (FILE, "\t.%s $L%d\n", TARGET_ABI_WINDOWS_NT ? "long" : "gprel32", \ |
8dfe3c62 | 2134 | (VALUE)) |
1a94ca49 RK |
2135 | |
2136 | /* This is how to output an assembler line | |
2137 | that says to advance the location counter | |
2138 | to a multiple of 2**LOG bytes. */ | |
2139 | ||
2140 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2141 | if ((LOG) != 0) \ | |
2142 | fprintf (FILE, "\t.align %d\n", LOG); | |
2143 | ||
2144 | /* This is how to advance the location counter by SIZE bytes. */ | |
2145 | ||
2146 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
2147 | fprintf (FILE, "\t.space %d\n", (SIZE)) | |
2148 | ||
2149 | /* This says how to output an assembler line | |
2150 | to define a global common symbol. */ | |
2151 | ||
2152 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
2153 | ( fputs ("\t.comm ", (FILE)), \ | |
2154 | assemble_name ((FILE), (NAME)), \ | |
2155 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2156 | ||
2157 | /* This says how to output an assembler line | |
2158 | to define a local common symbol. */ | |
2159 | ||
2160 | #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \ | |
2161 | ( fputs ("\t.lcomm ", (FILE)), \ | |
2162 | assemble_name ((FILE), (NAME)), \ | |
2163 | fprintf ((FILE), ",%d\n", (SIZE))) | |
2164 | ||
2165 | /* Store in OUTPUT a string (made with alloca) containing | |
2166 | an assembler-name for a local static variable named NAME. | |
2167 | LABELNO is an integer which is different for each call. */ | |
2168 | ||
2169 | #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ | |
2170 | ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ | |
2171 | sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) | |
2172 | ||
60593797 RH |
2173 | /* Output code to add DELTA to the first argument, and then jump to FUNCTION. |
2174 | Used for C++ multiple inheritance. */ | |
f2720858 RH |
2175 | /* ??? This is only used with the v2 ABI, and alpha.c makes assumptions |
2176 | about current_function_is_thunk that are not valid with the v3 ABI. */ | |
2177 | #if 0 | |
60593797 RH |
2178 | #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ |
2179 | do { \ | |
e03c5670 | 2180 | const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \ |
54473ca7 | 2181 | int reg; \ |
60593797 | 2182 | \ |
be7b80f4 | 2183 | if (TARGET_ABI_OSF) \ |
4c646291 JJ |
2184 | fprintf (FILE, "\tldgp $29,0($27)\n"); \ |
2185 | \ | |
acd92049 RH |
2186 | /* Mark end of prologue. */ \ |
2187 | output_end_prologue (FILE); \ | |
60593797 RH |
2188 | \ |
2189 | /* Rely on the assembler to macro expand a large delta. */ \ | |
2eecbd3f | 2190 | fprintf (FILE, "\t.set at\n"); \ |
54473ca7 L |
2191 | reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \ |
2192 | fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \ | |
60593797 | 2193 | \ |
b1afd7f4 KG |
2194 | if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \ |
2195 | VOIDmode)) \ | |
60593797 RH |
2196 | { \ |
2197 | fprintf (FILE, "\tbr $31,$"); \ | |
2198 | assemble_name (FILE, fn_name); \ | |
2199 | fprintf (FILE, "..ng\n"); \ | |
2200 | } \ | |
2201 | else \ | |
2202 | { \ | |
acd92049 | 2203 | fprintf (FILE, "\tjmp $31,"); \ |
60593797 RH |
2204 | assemble_name (FILE, fn_name); \ |
2205 | fputc ('\n', FILE); \ | |
2206 | } \ | |
2eecbd3f | 2207 | fprintf (FILE, "\t.set noat\n"); \ |
60593797 | 2208 | } while (0) |
f2720858 | 2209 | #endif |
60593797 | 2210 | \f |
9ec36da5 | 2211 | |
1a94ca49 RK |
2212 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2213 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2214 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2215 | ||
2216 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2217 | ||
2218 | /* Determine which codes are valid without a following integer. These must | |
941cc05a RK |
2219 | not be alphabetic. |
2220 | ||
2221 | ~ Generates the name of the current function. | |
2bf6230d | 2222 | |
be7560ea RH |
2223 | / Generates the instruction suffix. The TRAP_SUFFIX and ROUND_SUFFIX |
2224 | attributes are examined to determine what is appropriate. | |
e5958492 RK |
2225 | |
2226 | , Generates single precision suffix for floating point | |
2227 | instructions (s for IEEE, f for VAX) | |
2228 | ||
2229 | - Generates double precision suffix for floating point | |
2230 | instructions (t for IEEE, g for VAX) | |
2bf6230d | 2231 | */ |
1a94ca49 | 2232 | |
be7560ea RH |
2233 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ |
2234 | ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~') | |
1a94ca49 RK |
2235 | \f |
2236 | /* Print a memory address as an operand to reference that memory location. */ | |
2237 | ||
714b019c RH |
2238 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
2239 | print_operand_address((FILE), (ADDR)) | |
2240 | ||
1a94ca49 RK |
2241 | /* Define the codes that are matched by predicates in alpha.c. */ |
2242 | ||
e3208d53 RH |
2243 | #define PREDICATE_CODES \ |
2244 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ | |
eb8da868 RH |
2245 | {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ |
2246 | {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ | |
2247 | {"cint8_operand", {CONST_INT}}, \ | |
2248 | {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ | |
2249 | {"add_operand", {SUBREG, REG, CONST_INT}}, \ | |
2250 | {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 | 2251 | {"const48_operand", {CONST_INT}}, \ |
eb8da868 RH |
2252 | {"and_operand", {SUBREG, REG, CONST_INT}}, \ |
2253 | {"or_operand", {SUBREG, REG, CONST_INT}}, \ | |
e3208d53 RH |
2254 | {"mode_mask_operand", {CONST_INT}}, \ |
2255 | {"mul8_operand", {CONST_INT}}, \ | |
2256 | {"mode_width_operand", {CONST_INT}}, \ | |
2257 | {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ | |
2258 | {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ | |
8f4773ea | 2259 | {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \ |
e3208d53 RH |
2260 | {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ |
2261 | {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ | |
1eb8759b | 2262 | {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \ |
e3208d53 RH |
2263 | {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ |
2264 | {"fp0_operand", {CONST_DOUBLE}}, \ | |
2265 | {"current_file_function_operand", {SYMBOL_REF}}, \ | |
2266 | {"call_operand", {REG, SYMBOL_REF}}, \ | |
2267 | {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ | |
eb8da868 | 2268 | SYMBOL_REF, CONST, LABEL_REF}}, \ |
e3208d53 | 2269 | {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ |
eb8da868 | 2270 | SYMBOL_REF, CONST, LABEL_REF}}, \ |
f711a22b | 2271 | {"some_ni_operand", {SUBREG, REG, MEM}}, \ |
e3208d53 RH |
2272 | {"aligned_memory_operand", {MEM}}, \ |
2273 | {"unaligned_memory_operand", {MEM}}, \ | |
2274 | {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \ | |
2275 | {"any_memory_operand", {MEM}}, \ | |
40b80dad | 2276 | {"hard_fp_register_operand", {SUBREG, REG}}, \ |
d2c6a1b6 | 2277 | {"hard_int_register_operand", {SUBREG, REG}}, \ |
67070f5c | 2278 | {"reg_not_elim_operand", {SUBREG, REG}}, \ |
3611aef0 RH |
2279 | {"reg_no_subreg_operand", {REG}}, \ |
2280 | {"addition_operation", {PLUS}}, | |
03f8c4cc | 2281 | \f |
63966b3b RH |
2282 | /* Define the `__builtin_va_list' type for the ABI. */ |
2283 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
2284 | (VALIST) = alpha_build_va_list () | |
2285 | ||
2286 | /* Implement `va_start' for varargs and stdarg. */ | |
2287 | #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ | |
2288 | alpha_va_start (stdarg, valist, nextarg) | |
2289 | ||
2290 | /* Implement `va_arg'. */ | |
2291 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
2292 | alpha_va_arg (valist, type) | |
2293 | \f | |
34fa88ab RK |
2294 | /* Tell collect that the object format is ECOFF. */ |
2295 | #define OBJECT_FORMAT_COFF | |
2296 | #define EXTENDED_COFF | |
2297 | ||
2298 | /* If we use NM, pass -g to it so it only lists globals. */ | |
2299 | #define NM_FLAGS "-pg" | |
2300 | ||
03f8c4cc RK |
2301 | /* Definitions for debugging. */ |
2302 | ||
2303 | #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ | |
2304 | #define DBX_DEBUGGING_INFO /* generate embedded stabs */ | |
2305 | #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ | |
2306 | ||
2307 | #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ | |
fe0986b4 | 2308 | #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG |
03f8c4cc RK |
2309 | #endif |
2310 | ||
2311 | ||
2312 | /* Correct the offset of automatic variables and arguments. Note that | |
2313 | the Alpha debug format wants all automatic variables and arguments | |
2314 | to be in terms of two different offsets from the virtual frame pointer, | |
2315 | which is the stack pointer before any adjustment in the function. | |
2316 | The offset for the argument pointer is fixed for the native compiler, | |
2317 | it is either zero (for the no arguments case) or large enough to hold | |
2318 | all argument registers. | |
2319 | The offset for the auto pointer is the fourth argument to the .frame | |
2320 | directive (local_offset). | |
2321 | To stay compatible with the native tools we use the same offsets | |
2322 | from the virtual frame pointer and adjust the debugger arg/auto offsets | |
2323 | accordingly. These debugger offsets are set up in output_prolog. */ | |
2324 | ||
9a0b18f2 RK |
2325 | extern long alpha_arg_offset; |
2326 | extern long alpha_auto_offset; | |
03f8c4cc RK |
2327 | #define DEBUGGER_AUTO_OFFSET(X) \ |
2328 | ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset) | |
2329 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset) | |
2330 | ||
2331 | ||
2332 | #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \ | |
2333 | alpha_output_lineno (STREAM, LINE) | |
03f8c4cc RK |
2334 | |
2335 | #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \ | |
2336 | alpha_output_filename (STREAM, NAME) | |
03f8c4cc | 2337 | |
4330b0e7 JW |
2338 | /* mips-tfile.c limits us to strings of one page. We must underestimate this |
2339 | number, because the real length runs past this up to the next | |
2340 | continuation point. This is really a dbxout.c bug. */ | |
2341 | #define DBX_CONTIN_LENGTH 3000 | |
03f8c4cc RK |
2342 | |
2343 | /* By default, turn on GDB extensions. */ | |
2344 | #define DEFAULT_GDB_EXTENSIONS 1 | |
2345 | ||
7aadc7c2 RK |
2346 | /* Stabs-in-ECOFF can't handle dbxout_function_end(). */ |
2347 | #define NO_DBX_FUNCTION_END 1 | |
2348 | ||
03f8c4cc RK |
2349 | /* If we are smuggling stabs through the ALPHA ECOFF object |
2350 | format, put a comment in front of the .stab<x> operation so | |
2351 | that the ALPHA assembler does not choke. The mips-tfile program | |
2352 | will correctly put the stab into the object file. */ | |
2353 | ||
93de6f51 HPN |
2354 | #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t") |
2355 | #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t") | |
2356 | #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t") | |
03f8c4cc RK |
2357 | |
2358 | /* Forward references to tags are allowed. */ | |
2359 | #define SDB_ALLOW_FORWARD_REFERENCES | |
2360 | ||
2361 | /* Unknown tags are also allowed. */ | |
2362 | #define SDB_ALLOW_UNKNOWN_REFERENCES | |
2363 | ||
2364 | #define PUT_SDB_DEF(a) \ | |
2365 | do { \ | |
2366 | fprintf (asm_out_file, "\t%s.def\t", \ | |
2367 | (TARGET_GAS) ? "" : "#"); \ | |
2368 | ASM_OUTPUT_LABELREF (asm_out_file, a); \ | |
2369 | fputc (';', asm_out_file); \ | |
2370 | } while (0) | |
2371 | ||
2372 | #define PUT_SDB_PLAIN_DEF(a) \ | |
2373 | do { \ | |
2374 | fprintf (asm_out_file, "\t%s.def\t.%s;", \ | |
2375 | (TARGET_GAS) ? "" : "#", (a)); \ | |
2376 | } while (0) | |
2377 | ||
2378 | #define PUT_SDB_TYPE(a) \ | |
2379 | do { \ | |
2380 | fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \ | |
2381 | } while (0) | |
2382 | ||
2383 | /* For block start and end, we create labels, so that | |
2384 | later we can figure out where the correct offset is. | |
2385 | The normal .ent/.end serve well enough for functions, | |
2386 | so those are just commented out. */ | |
2387 | ||
2388 | extern int sdb_label_count; /* block start/end next label # */ | |
2389 | ||
2390 | #define PUT_SDB_BLOCK_START(LINE) \ | |
2391 | do { \ | |
2392 | fprintf (asm_out_file, \ | |
2393 | "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \ | |
2394 | sdb_label_count, \ | |
2395 | (TARGET_GAS) ? "" : "#", \ | |
2396 | sdb_label_count, \ | |
2397 | (LINE)); \ | |
2398 | sdb_label_count++; \ | |
2399 | } while (0) | |
2400 | ||
2401 | #define PUT_SDB_BLOCK_END(LINE) \ | |
2402 | do { \ | |
2403 | fprintf (asm_out_file, \ | |
2404 | "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \ | |
2405 | sdb_label_count, \ | |
2406 | (TARGET_GAS) ? "" : "#", \ | |
2407 | sdb_label_count, \ | |
2408 | (LINE)); \ | |
2409 | sdb_label_count++; \ | |
2410 | } while (0) | |
2411 | ||
2412 | #define PUT_SDB_FUNCTION_START(LINE) | |
2413 | ||
2414 | #define PUT_SDB_FUNCTION_END(LINE) | |
2415 | ||
3c303f52 | 2416 | #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME)) |
03f8c4cc | 2417 | |
03f8c4cc RK |
2418 | /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for |
2419 | mips-tdump.c to print them out. | |
2420 | ||
2421 | These must match the corresponding definitions in gdb/mipsread.c. | |
2422 | Unfortunately, gcc and gdb do not currently share any directories. */ | |
2423 | ||
2424 | #define CODE_MASK 0x8F300 | |
2425 | #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK) | |
2426 | #define MIPS_MARK_STAB(code) ((code)+CODE_MASK) | |
2427 | #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK) | |
2428 | ||
2429 | /* Override some mips-tfile definitions. */ | |
2430 | ||
2431 | #define SHASH_SIZE 511 | |
2432 | #define THASH_SIZE 55 | |
1e6c6f11 RK |
2433 | |
2434 | /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */ | |
2435 | ||
2436 | #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7) | |
2f55b70b | 2437 | |
b0435cf4 RH |
2438 | /* The system headers under Alpha systems are generally C++-aware. */ |
2439 | #define NO_IMPLICIT_EXTERN_C | |
b517dcd2 RH |
2440 | |
2441 | /* Generate calls to memcpy, etc., not bcopy, etc. */ | |
2442 | #define TARGET_MEM_FUNCTIONS 1 |