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a6f12d7c 1/* Subroutines used for code generation on the DEC Alpha.
9ddd9abd 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
ae46c4e0 3 2000, 2001, 2002 Free Software Foundation, Inc.
d60a05a1 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
a6f12d7c
RK		 5
6This file is part of GNU CC.
7
8GNU CC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 2, or (at your option)
11any later version.
12
13GNU CC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GNU CC; see the file COPYING. If not, write to
38ead7f3
RK		 20the Free Software Foundation, 59 Temple Place - Suite 330,
21Boston, MA 02111-1307, USA. */
a6f12d7c
RK		 22
23
a6f12d7c 24#include "config.h"
3c303f52 25#include "system.h"
a6f12d7c 26#include "rtl.h"
e78d8e51 27#include "tree.h"
a6f12d7c
RK		 28#include "regs.h"
29#include "hard-reg-set.h"
30#include "real.h"
31#include "insn-config.h"
32#include "conditions.h"
a6f12d7c
RK		 33#include "output.h"
34#include "insn-attr.h"
35#include "flags.h"
36#include "recog.h"
a6f12d7c 37#include "expr.h"
e78d8e51
ZW		 38#include "optabs.h"
39#include "reload.h"
a6f12d7c 40#include "obstack.h"
9ecc37f0
RH		 41#include "except.h"
42#include "function.h"
3c303f52 43#include "toplev.h"
01439aee 44#include "ggc.h"
b91055dd 45#include "integrate.h"
aead1ca3 46#include "tm_p.h"
672a6f42
NB		 47#include "target.h"
48#include "target-def.h"
14691f8d 49#include "debug.h"
f1e639b1 50#include "langhooks.h"
9ecc37f0 51
285a5742 52/* Specify which cpu to schedule for. */
9ecc37f0 53
9b009d45 54enum processor_type alpha_cpu;
df45c7ea 55static const char * const alpha_cpu_name[] =
bcbbac26
RH		 56{
57 "ev4", "ev5", "ev6"
58};
da792a68 59
6245e3df
RK		 60/* Specify how accurate floating-point traps need to be. */
61
62enum alpha_trap_precision alpha_tp;
63
64/* Specify the floating-point rounding mode. */
65
66enum alpha_fp_rounding_mode alpha_fprm;
67
68/* Specify which things cause traps. */
69
70enum alpha_fp_trap_mode alpha_fptm;
71
6f9b006d
RH		 72/* Specify bit size of immediate TLS offsets. */
73
74int alpha_tls_size = 32;
75
6245e3df 76/* Strings decoded into the above options. */
9ecc37f0 77
df45c7ea 78const char *alpha_cpu_string; /* -mcpu= */
a3b815cb 79const char *alpha_tune_string; /* -mtune= */
df45c7ea
KG		 80const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
81const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
82const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
83const char *alpha_mlat_string; /* -mmemory-latency= */
6f9b006d 84const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
6245e3df 85
a6f12d7c
RK		 86/* Save information from a "cmpxx" operation until the branch or scc is
87 emitted. */
88
6db21c7f 89struct alpha_compare alpha_compare;
a6f12d7c 90
825dda42 91/* Nonzero if inside of a function, because the Alpha asm can't
48f6bfac
RK		 92 handle .files inside of functions. */
93
94static int inside_function = FALSE;
95
bcbbac26
RH		 96/* The number of cycles of latency we should assume on memory reads. */
97
98int alpha_memory_latency = 3;
99
9c0e94a5
RH		 100/* Whether the function needs the GP. */
101
102static int alpha_function_needs_gp;
103
3873d24b
RH		 104/* The alias set for prologue/epilogue register save/restore. */
105
106static int alpha_sr_alias_set;
107
941cc05a
RK		 108/* The assembler name of the current function. */
109
110static const char *alpha_fnname;
111
1eb356b9
RH		 112/* The next explicit relocation sequence number. */
113int alpha_next_sequence_number = 1;
114
115/* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117int alpha_this_literal_sequence_number;
118int alpha_this_gpdisp_sequence_number;
119
d60a05a1 120/* Declarations of static functions. */
6f9b006d
RH		 121static int tls_symbolic_operand_1
122 PARAMS ((rtx, enum machine_mode, int, int));
123static enum tls_model tls_symbolic_operand_type
124 PARAMS ((rtx));
62918bd3
RH		 125static bool decl_in_text_section
126 PARAMS ((tree));
ae46c4e0
RH		 127static bool alpha_in_small_data_p
128 PARAMS ((tree));
fb49053f
RH		 129static void alpha_encode_section_info
130 PARAMS ((tree, int));
772c5265
RH		 131static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
a615ca3e 133static int some_small_symbolic_operand_1
1e7e480e 134 PARAMS ((rtx *, void *));
a615ca3e 135static int split_small_symbolic_operand_1
1e7e480e 136 PARAMS ((rtx *, void *));
9c0e94a5 137static void alpha_set_memflags_1
f6da8bc3 138 PARAMS ((rtx, int, int, int));
9c0e94a5 139static rtx alpha_emit_set_const_1
f6da8bc3 140 PARAMS ((rtx, enum machine_mode, HOST_WIDE_INT, int));
9c0e94a5 141static void alpha_expand_unaligned_load_words
f6da8bc3 142 PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
9c0e94a5 143static void alpha_expand_unaligned_store_words
f6da8bc3 144 PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
6d8fd7bb
RH		 145static void alpha_init_builtins
146 PARAMS ((void));
147static rtx alpha_expand_builtin
148 PARAMS ((tree, rtx, rtx, enum machine_mode, int));
9c0e94a5 149static void alpha_sa_mask
f6da8bc3 150 PARAMS ((unsigned long *imaskP, unsigned long *fmaskP));
1eb356b9
RH		 151static int find_lo_sum
152 PARAMS ((rtx *, void *));
9c0e94a5 153static int alpha_does_function_need_gp
f6da8bc3 154 PARAMS ((void));
5495cc55
RH		 155static int alpha_ra_ever_killed
156 PARAMS ((void));
be7560ea
RH		 157static const char *get_trap_mode_suffix
158 PARAMS ((void));
159static const char *get_round_mode_suffix
160 PARAMS ((void));
6f9b006d
RH		 161static const char *get_some_local_dynamic_name
162 PARAMS ((void));
163static int get_some_local_dynamic_name_1
164 PARAMS ((rtx *, void *));
5495cc55
RH		 165static rtx set_frame_related_p
166 PARAMS ((void));
167static const char *alpha_lookup_xfloating_lib_func
168 PARAMS ((enum rtx_code));
169static int alpha_compute_xfloating_mode_arg
170 PARAMS ((enum rtx_code, enum alpha_fp_rounding_mode));
171static void alpha_emit_xfloating_libcall
172 PARAMS ((const char *, rtx, rtx[], int, rtx));
173static rtx alpha_emit_xfloating_compare
174 PARAMS ((enum rtx_code, rtx, rtx));
b4c25db2
NB		 175static void alpha_output_function_end_prologue
176 PARAMS ((FILE *));
c237e94a
ZW		 177static int alpha_adjust_cost
178 PARAMS ((rtx, rtx, rtx, int));
179static int alpha_issue_rate
180 PARAMS ((void));
98791e3a
RH		 181static int alpha_use_dfa_pipeline_interface
182 PARAMS ((void));
183static int alpha_multipass_dfa_lookahead
184 PARAMS ((void));
89cfc2c6 185
b64a1b53
RH		 186#ifdef OBJECT_FORMAT_ELF
187static void alpha_elf_select_rtx_section
188 PARAMS ((enum machine_mode, rtx, unsigned HOST_WIDE_INT));
189#endif
190
1330f7d5
DR		 191#if TARGET_ABI_OPEN_VMS
192static bool alpha_linkage_symbol_p
193 PARAMS ((const char *symname));
194static void alpha_write_linkage
195 PARAMS ((FILE *, const char *, tree));
196#endif
197
e2500fed
GK		 198static struct machine_function * alpha_init_machine_status
199 PARAMS ((void));
30102605
RH		 200
201static void unicosmk_output_deferred_case_vectors PARAMS ((FILE *));
202static void unicosmk_gen_dsib PARAMS ((unsigned long *imaskP));
203static void unicosmk_output_ssib PARAMS ((FILE *, const char *));
204static int unicosmk_need_dex PARAMS ((rtx));
205
e9a25f70 206/* Get the number of args of a function in one of two ways. */
30102605 207#if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
e9a25f70
JL		 208#define NUM_ARGS current_function_args_info.num_args
209#else
210#define NUM_ARGS current_function_args_info
211#endif
26250081 212
26250081
RH		 213#define REG_PV 27
214#define REG_RA 26
a6f12d7c 215\f
672a6f42 216/* Initialize the GCC target structure. */
be7b80f4 217#if TARGET_ABI_OPEN_VMS
91d231cb 218const struct attribute_spec vms_attribute_table[];
7c262518 219static unsigned int vms_section_type_flags PARAMS ((tree, const char *, int));
715bdd29 220static void vms_asm_named_section PARAMS ((const char *, unsigned int));
2cc07db4
RH		 221static void vms_asm_out_constructor PARAMS ((rtx, int));
222static void vms_asm_out_destructor PARAMS ((rtx, int));
91d231cb
JM		 223# undef TARGET_ATTRIBUTE_TABLE
224# define TARGET_ATTRIBUTE_TABLE vms_attribute_table
7c262518
RH		 225# undef TARGET_SECTION_TYPE_FLAGS
226# define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
8289c43b 227#endif
672a6f42 228
ae46c4e0
RH		 229#undef TARGET_IN_SMALL_DATA_P
230#define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
fb49053f
RH		 231#undef TARGET_ENCODE_SECTION_INFO
232#define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
772c5265
RH		 233#undef TARGET_STRIP_NAME_ENCODING
234#define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
ae46c4e0 235
30102605
RH		 236#if TARGET_ABI_UNICOSMK
237static void unicosmk_asm_named_section PARAMS ((const char *, unsigned int));
238static void unicosmk_insert_attributes PARAMS ((tree, tree *));
239static unsigned int unicosmk_section_type_flags PARAMS ((tree, const char *,
240 int));
ae46c4e0 241static void unicosmk_unique_section PARAMS ((tree, int));
30102605
RH		 242# undef TARGET_INSERT_ATTRIBUTES
243# define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
244# undef TARGET_SECTION_TYPE_FLAGS
245# define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
ae46c4e0
RH		 246# undef TARGET_ASM_UNIQUE_SECTION
247# define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
5eb99654
KG		 248# undef TARGET_ASM_GLOBALIZE_LABEL
249# define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
30102605
RH		 250#endif
251
301d03af
RS		 252#undef TARGET_ASM_ALIGNED_HI_OP
253#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
254#undef TARGET_ASM_ALIGNED_DI_OP
255#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
256
257/* Default unaligned ops are provided for ELF systems. To get unaligned
258 data for non-ELF systems, we have to turn off auto alignment. */
259#ifndef OBJECT_FORMAT_ELF
260#undef TARGET_ASM_UNALIGNED_HI_OP
261#define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
262#undef TARGET_ASM_UNALIGNED_SI_OP
263#define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
264#undef TARGET_ASM_UNALIGNED_DI_OP
265#define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
266#endif
267
b64a1b53
RH		 268#ifdef OBJECT_FORMAT_ELF
269#undef TARGET_ASM_SELECT_RTX_SECTION
270#define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
271#endif
272
b4c25db2
NB		 273#undef TARGET_ASM_FUNCTION_END_PROLOGUE
274#define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
275
c237e94a
ZW		 276#undef TARGET_SCHED_ADJUST_COST
277#define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
278#undef TARGET_SCHED_ISSUE_RATE
279#define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
98791e3a
RH		 280#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
281#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
282 alpha_use_dfa_pipeline_interface
283#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
284#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
285 alpha_multipass_dfa_lookahead
c237e94a 286
6f9b006d
RH		 287#undef TARGET_HAVE_TLS
288#define TARGET_HAVE_TLS HAVE_AS_TLS
289
6d8fd7bb
RH		 290#undef TARGET_INIT_BUILTINS
291#define TARGET_INIT_BUILTINS alpha_init_builtins
292#undef TARGET_EXPAND_BUILTIN
293#define TARGET_EXPAND_BUILTIN alpha_expand_builtin
294
f6897b10 295struct gcc_target targetm = TARGET_INITIALIZER;
672a6f42 296\f
285a5742 297/* Parse target option strings. */
6245e3df
RK		 298
299void
300override_options ()
301{
a3b815cb 302 int i;
8b60264b
KG		 303 static const struct cpu_table {
304 const char *const name;
305 const enum processor_type processor;
306 const int flags;
a3b815cb
JJ		 307 } cpu_table[] = {
308#define EV5_MASK (MASK_CPU_EV5)
309#define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
310 { "ev4", PROCESSOR_EV4, 0 },
311 { "ev45", PROCESSOR_EV4, 0 },
312 { "21064", PROCESSOR_EV4, 0 },
313 { "ev5", PROCESSOR_EV5, EV5_MASK },
314 { "21164", PROCESSOR_EV5, EV5_MASK },
315 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
316 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
317 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
318 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
319 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
320 { "ev6", PROCESSOR_EV6, EV6_MASK },
321 { "21264", PROCESSOR_EV6, EV6_MASK },
322 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
323 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
324 { 0, 0, 0 }
325 };
326
30102605
RH		 327 /* Unicos/Mk doesn't have shared libraries. */
328 if (TARGET_ABI_UNICOSMK && flag_pic)
329 {
330 warning ("-f%s ignored for Unicos/Mk (not supported)",
331 (flag_pic > 1) ? "PIC" : "pic");
332 flag_pic = 0;
333 }
334
335 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
336 floating-point instructions. Make that the default for this target. */
337 if (TARGET_ABI_UNICOSMK)
338 alpha_fprm = ALPHA_FPRM_DYN;
339 else
340 alpha_fprm = ALPHA_FPRM_NORM;
341
6245e3df 342 alpha_tp = ALPHA_TP_PROG;
6245e3df
RK		 343 alpha_fptm = ALPHA_FPTM_N;
344
30102605
RH		 345 /* We cannot use su and sui qualifiers for conversion instructions on
346 Unicos/Mk. I'm not sure if this is due to assembler or hardware
347 limitations. Right now, we issue a warning if -mieee is specified
348 and then ignore it; eventually, we should either get it right or
349 disable the option altogether. */
350
6245e3df
RK		 351 if (TARGET_IEEE)
352 {
30102605
RH		 353 if (TARGET_ABI_UNICOSMK)
354 warning ("-mieee not supported on Unicos/Mk");
355 else
356 {
357 alpha_tp = ALPHA_TP_INSN;
358 alpha_fptm = ALPHA_FPTM_SU;
359 }
6245e3df
RK		 360 }
361
362 if (TARGET_IEEE_WITH_INEXACT)
363 {
30102605
RH		 364 if (TARGET_ABI_UNICOSMK)
365 warning ("-mieee-with-inexact not supported on Unicos/Mk");
366 else
367 {
368 alpha_tp = ALPHA_TP_INSN;
369 alpha_fptm = ALPHA_FPTM_SUI;
370 }
6245e3df
RK		 371 }
372
373 if (alpha_tp_string)
10d5c73f
RK		 374 {
375 if (! strcmp (alpha_tp_string, "p"))
6245e3df 376 alpha_tp = ALPHA_TP_PROG;
10d5c73f 377 else if (! strcmp (alpha_tp_string, "f"))
6245e3df 378 alpha_tp = ALPHA_TP_FUNC;
10d5c73f 379 else if (! strcmp (alpha_tp_string, "i"))
6245e3df 380 alpha_tp = ALPHA_TP_INSN;
10d5c73f
RK		 381 else
382 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
383 }
6245e3df
RK		 384
385 if (alpha_fprm_string)
10d5c73f
RK		 386 {
387 if (! strcmp (alpha_fprm_string, "n"))
6245e3df 388 alpha_fprm = ALPHA_FPRM_NORM;
10d5c73f 389 else if (! strcmp (alpha_fprm_string, "m"))
6245e3df 390 alpha_fprm = ALPHA_FPRM_MINF;
10d5c73f 391 else if (! strcmp (alpha_fprm_string, "c"))
6245e3df 392 alpha_fprm = ALPHA_FPRM_CHOP;
10d5c73f 393 else if (! strcmp (alpha_fprm_string,"d"))
6245e3df 394 alpha_fprm = ALPHA_FPRM_DYN;
10d5c73f
RK		 395 else
396 error ("bad value `%s' for -mfp-rounding-mode switch",
6245e3df 397 alpha_fprm_string);
10d5c73f 398 }
6245e3df
RK		 399
400 if (alpha_fptm_string)
10d5c73f
RK		 401 {
402 if (strcmp (alpha_fptm_string, "n") == 0)
403 alpha_fptm = ALPHA_FPTM_N;
404 else if (strcmp (alpha_fptm_string, "u") == 0)
405 alpha_fptm = ALPHA_FPTM_U;
406 else if (strcmp (alpha_fptm_string, "su") == 0)
407 alpha_fptm = ALPHA_FPTM_SU;
408 else if (strcmp (alpha_fptm_string, "sui") == 0)
409 alpha_fptm = ALPHA_FPTM_SUI;
410 else
411 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
412 }
6245e3df 413
6f9b006d
RH		 414 if (alpha_tls_size_string)
415 {
416 if (strcmp (alpha_tls_size_string, "16") == 0)
417 alpha_tls_size = 16;
418 else if (strcmp (alpha_tls_size_string, "32") == 0)
419 alpha_tls_size = 32;
420 else if (strcmp (alpha_tls_size_string, "64") == 0)
421 alpha_tls_size = 64;
422 else
423 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
424 }
425
de4abb91
RH		 426 alpha_cpu
427 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
428 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
429
430 if (alpha_cpu_string)
431 {
a3b815cb
JJ		 432 for (i = 0; cpu_table [i].name; i++)
433 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
434 {
435 alpha_cpu = cpu_table [i].processor;
436 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
437 | MASK_CPU_EV5 | MASK_CPU_EV6);
438 target_flags |= cpu_table [i].flags;
439 break;
440 }
441 if (! cpu_table [i].name)
de4abb91
RH		 442 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
443 }
444
a3b815cb
JJ		 445 if (alpha_tune_string)
446 {
447 for (i = 0; cpu_table [i].name; i++)
448 if (! strcmp (alpha_tune_string, cpu_table [i].name))
449 {
450 alpha_cpu = cpu_table [i].processor;
451 break;
452 }
453 if (! cpu_table [i].name)
454 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
455 }
456
285a5742 457 /* Do some sanity checks on the above options. */
6245e3df 458
30102605
RH		 459 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
460 {
461 warning ("trap mode not supported on Unicos/Mk");
462 alpha_fptm = ALPHA_FPTM_N;
463 }
464
10d5c73f 465 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
a3b815cb 466 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
6245e3df 467 {
10d5c73f 468 warning ("fp software completion requires -mtrap-precision=i");
6245e3df
RK		 469 alpha_tp = ALPHA_TP_INSN;
470 }
89cfc2c6 471
a3b815cb 472 if (TARGET_CPU_EV6)
981a828e
RH		 473 {
474 /* Except for EV6 pass 1 (not released), we always have precise
475 arithmetic traps. Which means we can do software completion
476 without minding trap shadows. */
477 alpha_tp = ALPHA_TP_PROG;
478 }
479
89cfc2c6
RK		 480 if (TARGET_FLOAT_VAX)
481 {
482 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
483 {
484 warning ("rounding mode not supported for VAX floats");
485 alpha_fprm = ALPHA_FPRM_NORM;
486 }
487 if (alpha_fptm == ALPHA_FPTM_SUI)
488 {
489 warning ("trap mode not supported for VAX floats");
490 alpha_fptm = ALPHA_FPTM_SU;
491 }
492 }
bcbbac26
RH		 493
494 {
495 char *end;
496 int lat;
497
498 if (!alpha_mlat_string)
499 alpha_mlat_string = "L1";
500
d1e6b55b 501 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
bcbbac26
RH		 502 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
503 ;
504 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
d1e6b55b 505 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
bcbbac26
RH		 506 && alpha_mlat_string[2] == '\0')
507 {
508 static int const cache_latency[][4] =
509 {
510 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
511 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
285a5742 512 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
bcbbac26
RH		 513 };
514
515 lat = alpha_mlat_string[1] - '0';
54f5c4b0 516 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
bcbbac26
RH		 517 {
518 warning ("L%d cache latency unknown for %s",
519 lat, alpha_cpu_name[alpha_cpu]);
520 lat = 3;
521 }
522 else
523 lat = cache_latency[alpha_cpu][lat-1];
524 }
525 else if (! strcmp (alpha_mlat_string, "main"))
526 {
527 /* Most current memories have about 370ns latency. This is
528 a reasonable guess for a fast cpu. */
529 lat = 150;
530 }
531 else
532 {
533 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
534 lat = 3;
535 }
536
537 alpha_memory_latency = lat;
538 }
bb8ebb7f
RH		 539
540 /* Default the definition of "small data" to 8 bytes. */
541 if (!g_switch_set)
542 g_switch_value = 8;
3873d24b 543
133d3133
RH		 544 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
545 if (flag_pic == 1)
546 target_flags |= MASK_SMALL_DATA;
547 else if (flag_pic == 2)
548 target_flags &= ~MASK_SMALL_DATA;
549
c176c051
RH		 550 /* Align labels and loops for optimal branching. */
551 /* ??? Kludge these by not doing anything if we don't optimize and also if
285a5742 552 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
c176c051
RH		 553 if (optimize > 0 && write_symbols != SDB_DEBUG)
554 {
555 if (align_loops <= 0)
556 align_loops = 16;
557 if (align_jumps <= 0)
558 align_jumps = 16;
559 }
560 if (align_functions <= 0)
561 align_functions = 16;
562
3873d24b
RH		 563 /* Acquire a unique set number for our register saves and restores. */
564 alpha_sr_alias_set = new_alias_set ();
30102605
RH		 565
566 /* Register variables and functions with the garbage collector. */
567
30102605
RH		 568 /* Set up function hooks. */
569 init_machine_status = alpha_init_machine_status;
3dc85dfb
RH		 570
571 /* Tell the compiler when we're using VAX floating point. */
572 if (TARGET_FLOAT_VAX)
573 {
574 real_format_for_mode[SFmode - QFmode] = &vax_f_format;
575 real_format_for_mode[DFmode - QFmode] = &vax_g_format;
576 real_format_for_mode[TFmode - QFmode] = NULL;
577 }
6245e3df
RK		 578}
579\f
a6f12d7c
RK		 580/* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
581
582int
583zap_mask (value)
584 HOST_WIDE_INT value;
585{
586 int i;
587
588 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
589 i++, value >>= 8)
590 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
591 return 0;
592
593 return 1;
594}
595
596/* Returns 1 if OP is either the constant zero or a register. If a
597 register, it must be in the proper mode unless MODE is VOIDmode. */
598
599int
600reg_or_0_operand (op, mode)
601 register rtx op;
602 enum machine_mode mode;
603{
73db7137 604 return op == CONST0_RTX (mode) || register_operand (op, mode);
a6f12d7c
RK		 605}
606
f4014bfd
RK		 607/* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
608 any register. */
609
610int
611reg_or_6bit_operand (op, mode)
612 register rtx op;
613 enum machine_mode mode;
614{
615 return ((GET_CODE (op) == CONST_INT
616 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
617 || register_operand (op, mode));
618}
619
620
a6f12d7c
RK		 621/* Return 1 if OP is an 8-bit constant or any register. */
622
623int
624reg_or_8bit_operand (op, mode)
625 register rtx op;
626 enum machine_mode mode;
627{
628 return ((GET_CODE (op) == CONST_INT
629 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
630 || register_operand (op, mode));
631}
632
6d8fd7bb
RH		 633/* Return 1 if OP is a constant or any register. */
634
635int
636reg_or_const_int_operand (op, mode)
637 register rtx op;
638 enum machine_mode mode;
639{
640 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
641}
642
14edc0e4
TG		 643/* Return 1 if OP is an 8-bit constant. */
644
645int
646cint8_operand (op, mode)
647 register rtx op;
3c303f52 648 enum machine_mode mode ATTRIBUTE_UNUSED;
14edc0e4 649{
e3208d53 650 return ((GET_CODE (op) == CONST_INT
eb8da868 651 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
14edc0e4
TG		 652}
653
a6f12d7c
RK		 654/* Return 1 if the operand is a valid second operand to an add insn. */
655
656int
657add_operand (op, mode)
658 register rtx op;
659 enum machine_mode mode;
660{
661 if (GET_CODE (op) == CONST_INT)
80df65c9 662 /* Constraints I, J, O and P are covered by K. */
e6118f89 663 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
80df65c9 664 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
a6f12d7c
RK		 665
666 return register_operand (op, mode);
667}
668
669/* Return 1 if the operand is a valid second operand to a sign-extending
670 add insn. */
671
672int
673sext_add_operand (op, mode)
674 register rtx op;
675 enum machine_mode mode;
676{
677 if (GET_CODE (op) == CONST_INT)
80df65c9
RH		 678 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
679 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
a6f12d7c 680
c5c76735 681 return reg_not_elim_operand (op, mode);
a6f12d7c
RK		 682}
683
684/* Return 1 if OP is the constant 4 or 8. */
685
686int
687const48_operand (op, mode)
688 register rtx op;
3c303f52 689 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c
RK		 690{
691 return (GET_CODE (op) == CONST_INT
692 && (INTVAL (op) == 4 || INTVAL (op) == 8));
693}
694
695/* Return 1 if OP is a valid first operand to an AND insn. */
696
697int
698and_operand (op, mode)
699 register rtx op;
700 enum machine_mode mode;
701{
702 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
703 return (zap_mask (CONST_DOUBLE_LOW (op))
704 && zap_mask (CONST_DOUBLE_HIGH (op)));
705
706 if (GET_CODE (op) == CONST_INT)
707 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
708 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
709 || zap_mask (INTVAL (op)));
710
711 return register_operand (op, mode);
712}
713
c7def335 714/* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
8088469d
RK		 715
716int
c7def335 717or_operand (op, mode)
8088469d
RK		 718 register rtx op;
719 enum machine_mode mode;
720{
721 if (GET_CODE (op) == CONST_INT)
722 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
723 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
724
725 return register_operand (op, mode);
726}
727
a6f12d7c
RK		 728/* Return 1 if OP is a constant that is the width, in bits, of an integral
729 mode smaller than DImode. */
730
731int
732mode_width_operand (op, mode)
733 register rtx op;
3c303f52 734 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c
RK		 735{
736 return (GET_CODE (op) == CONST_INT
6c174fc0
RH		 737 && (INTVAL (op) == 8 || INTVAL (op) == 16
738 || INTVAL (op) == 32 || INTVAL (op) == 64));
a6f12d7c
RK		 739}
740
741/* Return 1 if OP is a constant that is the width of an integral machine mode
742 smaller than an integer. */
743
744int
745mode_mask_operand (op, mode)
746 register rtx op;
3c303f52 747 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c 748{
c4b50f1a
RH		 749 if (GET_CODE (op) == CONST_INT)
750 {
751 HOST_WIDE_INT value = INTVAL (op);
a6f12d7c 752
c4b50f1a
RH		 753 if (value == 0xff)
754 return 1;
755 if (value == 0xffff)
756 return 1;
757 if (value == 0xffffffff)
758 return 1;
759 if (value == -1)
760 return 1;
761 }
762 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
763 {
764 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
765 return 1;
766 }
767
768 return 0;
a6f12d7c
RK		 769}
770
771/* Return 1 if OP is a multiple of 8 less than 64. */
772
773int
774mul8_operand (op, mode)
775 register rtx op;
3c303f52 776 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c
RK		 777{
778 return (GET_CODE (op) == CONST_INT
779 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
780 && (INTVAL (op) & 7) == 0);
781}
782
73db7137 783/* Return 1 if OP is the zero constant for MODE. */
a6f12d7c
RK		 784
785int
73db7137 786const0_operand (op, mode)
a6f12d7c
RK		 787 register rtx op;
788 enum machine_mode mode;
789{
73db7137 790 return op == CONST0_RTX (mode);
a6f12d7c
RK		 791}
792
4ed43ff8
RH		 793/* Return 1 if OP is a hard floating-point register. */
794
795int
796hard_fp_register_operand (op, mode)
797 register rtx op;
798 enum machine_mode mode;
799{
d2c6a1b6
RH		 800 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
801 return 0;
802
803 if (GET_CODE (op) == SUBREG)
804 op = SUBREG_REG (op);
805 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
806}
807
808/* Return 1 if OP is a hard general register. */
809
810int
811hard_int_register_operand (op, mode)
812 register rtx op;
813 enum machine_mode mode;
814{
815 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
816 return 0;
817
818 if (GET_CODE (op) == SUBREG)
819 op = SUBREG_REG (op);
820 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
4ed43ff8
RH		 821}
822
a6f12d7c
RK		 823/* Return 1 if OP is a register or a constant integer. */
824
825
826int
827reg_or_cint_operand (op, mode)
828 register rtx op;
829 enum machine_mode mode;
830{
e3208d53 831 return (GET_CODE (op) == CONST_INT
e3208d53 832 || register_operand (op, mode));
a6f12d7c
RK		 833}
834
8d36d33b
RK		 835/* Return 1 if OP is something that can be reloaded into a register;
836 if it is a MEM, it need not be valid. */
837
838int
839some_operand (op, mode)
840 register rtx op;
841 enum machine_mode mode;
842{
843 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
844 return 0;
845
846 switch (GET_CODE (op))
847 {
6d8fd7bb
RH		 848 case REG:
849 case MEM:
850 case CONST_INT:
851 case CONST_DOUBLE:
852 case CONST_VECTOR:
853 case LABEL_REF:
854 case SYMBOL_REF:
855 case CONST:
856 case HIGH:
8d36d33b
RK		 857 return 1;
858
859 case SUBREG:
860 return some_operand (SUBREG_REG (op), VOIDmode);
1d300e19
KG		 861
862 default:
863 break;
8d36d33b
RK		 864 }
865
866 return 0;
867}
868
f711a22b
RH		 869/* Likewise, but don't accept constants. */
870
871int
872some_ni_operand (op, mode)
873 register rtx op;
874 enum machine_mode mode;
875{
876 if (GET_MODE (op) != mode && mode != VOIDmode)
877 return 0;
878
879 if (GET_CODE (op) == SUBREG)
880 op = SUBREG_REG (op);
881
882 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
883}
884
a6f12d7c
RK		 885/* Return 1 if OP is a valid operand for the source of a move insn. */
886
887int
888input_operand (op, mode)
889 register rtx op;
890 enum machine_mode mode;
891{
892 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
893 return 0;
894
895 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
896 return 0;
897
898 switch (GET_CODE (op))
899 {
900 case LABEL_REF:
901 case SYMBOL_REF:
902 case CONST:
e2c9fb9b 903 if (TARGET_EXPLICIT_RELOCS)
551cc6fd
RH		 904 {
905 /* We don't split symbolic operands into something unintelligable
906 until after reload, but we do not wish non-small, non-global
907 symbolic operands to be reconstructed from their high/lo_sum
908 form. */
909 return (small_symbolic_operand (op, mode)
6f9b006d
RH		 910 || global_symbolic_operand (op, mode)
911 || gotdtp_symbolic_operand (op, mode)
912 || gottp_symbolic_operand (op, mode));
551cc6fd 913 }
e2c9fb9b 914
e3208d53 915 /* This handles both the Windows/NT and OSF cases. */
7daa56f5 916 return mode == ptr_mode || mode == DImode;
a6f12d7c 917
551cc6fd
RH		 918 case HIGH:
919 return (TARGET_EXPLICIT_RELOCS
920 && local_symbolic_operand (XEXP (op, 0), mode));
921
a6f12d7c 922 case REG:
14a774a9 923 case ADDRESSOF:
a6f12d7c
RK		 924 return 1;
925
926 case SUBREG:
927 if (register_operand (op, mode))
928 return 1;
285a5742 929 /* ... fall through ... */
a6f12d7c 930 case MEM:
e9a25f70 931 return ((TARGET_BWX || (mode != HImode && mode != QImode))
a2574dbe 932 && general_operand (op, mode));
a6f12d7c
RK		 933
934 case CONST_DOUBLE:
6d8fd7bb
RH		 935 case CONST_VECTOR:
936 return op == CONST0_RTX (mode);
a6f12d7c
RK		 937
938 case CONST_INT:
939 return mode == QImode || mode == HImode || add_operand (op, mode);
1d300e19 940
ee5332b8
RH		 941 case CONSTANT_P_RTX:
942 return 1;
943
1d300e19
KG		 944 default:
945 break;
a6f12d7c
RK		 946 }
947
948 return 0;
949}
950
0f33506c 951/* Return 1 if OP is a SYMBOL_REF for a function known to be in this
62918bd3 952 file, and in the same section as the current function. */
a6f12d7c
RK		 953
954int
0f33506c 955current_file_function_operand (op, mode)
a6f12d7c 956 rtx op;
3c303f52 957 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c 958{
1afec8ad
RH		 959 if (GET_CODE (op) != SYMBOL_REF)
960 return 0;
961
62918bd3
RH		 962 /* Easy test for recursion. */
963 if (op == XEXP (DECL_RTL (current_function_decl), 0))
964 return 1;
1afec8ad 965
62918bd3
RH		 966 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
967 So SYMBOL_REF_FLAG has been declared to imply that the function is
968 in the default text section. So we must also check that the current
969 function is also in the text section. */
970 if (SYMBOL_REF_FLAG (op) && decl_in_text_section (current_function_decl))
971 return 1;
972
973 return 0;
1afec8ad
RH		 974}
975
976/* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
977
978int
979direct_call_operand (op, mode)
980 rtx op;
981 enum machine_mode mode;
982{
983 /* Must be defined in this file. */
984 if (! current_file_function_operand (op, mode))
985 return 0;
986
987 /* If profiling is implemented via linker tricks, we can't jump
988 to the nogp alternate entry point. */
989 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
990 but is approximately correct for the OSF ABIs. Don't know
991 what to do for VMS, NT, or UMK. */
992 if (! TARGET_PROFILING_NEEDS_GP
70f4f91c 993 && ! current_function_profile)
1afec8ad 994 return 0;
4d8f669f
RH		 995
996 return 1;
a6f12d7c
RK		 997}
998
e2c9fb9b 999/* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
e9f09586 1000 a (non-tls) variable known to be defined in this file. */
e2c9fb9b 1001
1eb356b9
RH		 1002int
1003local_symbolic_operand (op, mode)
1004 rtx op;
30102605 1005 enum machine_mode mode;
1eb356b9 1006{
6f9b006d
RH		 1007 const char *str;
1008
30102605
RH		 1009 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1010 return 0;
1011
1eb356b9
RH		 1012 if (GET_CODE (op) == LABEL_REF)
1013 return 1;
1014
1015 if (GET_CODE (op) == CONST
1016 && GET_CODE (XEXP (op, 0)) == PLUS
1017 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1018 op = XEXP (XEXP (op, 0), 0);
1019
1020 if (GET_CODE (op) != SYMBOL_REF)
1021 return 0;
1022
6f9b006d
RH		 1023 /* Easy pickings. */
1024 if (CONSTANT_POOL_ADDRESS_P (op) || STRING_POOL_ADDRESS_P (op))
1025 return 1;
1026
1027 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1028 run into problems with the rtl inliner in that the symbol was
1029 once external, but is local after inlining, which results in
1030 unrecognizable insns. */
1031
1032 str = XSTR (op, 0);
1033
e9f09586 1034 /* If @[LS], then alpha_encode_section_info sez it's local. */
6f9b006d
RH		 1035 if (str[0] == '@' && (str[1] == 'L' || str[1] == 'S'))
1036 return 1;
1037
1038 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1039 if (str[0] == '*' && str[1] == '$')
1040 return 1;
1041
1042 return 0;
1eb356b9
RH		 1043}
1044
133d3133
RH		 1045/* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1046 known to be defined in this file in the small data area. */
1047
1048int
1049small_symbolic_operand (op, mode)
1050 rtx op;
1051 enum machine_mode mode ATTRIBUTE_UNUSED;
1052{
1053 const char *str;
1054
1055 if (! TARGET_SMALL_DATA)
1056 return 0;
1057
e2c9fb9b
RH		 1058 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1059 return 0;
1060
133d3133
RH		 1061 if (GET_CODE (op) == CONST
1062 && GET_CODE (XEXP (op, 0)) == PLUS
1063 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1064 op = XEXP (XEXP (op, 0), 0);
1065
1066 if (GET_CODE (op) != SYMBOL_REF)
1067 return 0;
1068
1069 if (CONSTANT_POOL_ADDRESS_P (op))
e2c9fb9b 1070 return GET_MODE_SIZE (get_pool_mode (op)) <= (unsigned) g_switch_value;
133d3133
RH		 1071 else
1072 {
1073 str = XSTR (op, 0);
6f9b006d 1074 return str[0] == '@' && str[1] == 'S';
133d3133
RH		 1075 }
1076}
1077
e2c9fb9b
RH		 1078/* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1079 not known (or known not) to be defined in this file. */
1080
1081int
1082global_symbolic_operand (op, mode)
1083 rtx op;
1084 enum machine_mode mode;
1085{
6f9b006d
RH		 1086 const char *str;
1087
e2c9fb9b
RH		 1088 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1089 return 0;
1090
1091 if (GET_CODE (op) == CONST
1092 && GET_CODE (XEXP (op, 0)) == PLUS
1093 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1094 op = XEXP (XEXP (op, 0), 0);
1095
1096 if (GET_CODE (op) != SYMBOL_REF)
1097 return 0;
1098
6f9b006d
RH		 1099 if (local_symbolic_operand (op, mode))
1100 return 0;
1101
1102 /* Also verify that it's not a TLS symbol. */
1103 str = XSTR (op, 0);
1104 return str[0] != '%' && str[0] != '@';
e2c9fb9b
RH		 1105}
1106
6bcf5f0a
RK		 1107/* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1108
1109int
1110call_operand (op, mode)
1111 rtx op;
1112 enum machine_mode mode;
1113{
1114 if (mode != Pmode)
1115 return 0;
1116
be7b80f4
RH		 1117 if (GET_CODE (op) == REG)
1118 {
1119 if (TARGET_ABI_OSF)
99407cf2
RH		 1120 {
1121 /* Disallow virtual registers to cope with pathalogical test cases
1122 such as compile/930117-1.c in which the virtual reg decomposes
1123 to the frame pointer. Which is a hard reg that is not $27. */
1124 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
1125 }
be7b80f4
RH		 1126 else
1127 return 1;
1128 }
e2c9fb9b
RH		 1129 if (TARGET_ABI_UNICOSMK)
1130 return 0;
1131 if (GET_CODE (op) == SYMBOL_REF)
1132 return 1;
be7b80f4
RH		 1133
1134 return 0;
6bcf5f0a
RK		 1135}
1136
30102605
RH		 1137/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1138 possibly with an offset. */
1139
1140int
1141symbolic_operand (op, mode)
1142 register rtx op;
1143 enum machine_mode mode;
1144{
1145 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1146 return 0;
1147 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1148 return 1;
1149 if (GET_CODE (op) == CONST
1150 && GET_CODE (XEXP (op,0)) == PLUS
1151 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1152 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1153 return 1;
1154 return 0;
1155}
1156
6f9b006d
RH		 1157/* Return true if OP is valid for a particular TLS relocation. */
1158
1159static int
1160tls_symbolic_operand_1 (op, mode, size, unspec)
1161 rtx op;
1162 enum machine_mode mode;
1163 int size, unspec;
1164{
1165 const char *str;
1166 int letter;
1167
1168 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1169 return 0;
1170
1171 if (GET_CODE (op) != CONST)
1172 return 0;
1173 op = XEXP (op, 0);
1174
1175 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1176 return 0;
1177 op = XVECEXP (op, 0, 0);
1178
1179 if (GET_CODE (op) != SYMBOL_REF)
1180 return 0;
1181 str = XSTR (op, 0);
1182
1183 if (str[0] == '%')
1184 {
1185 if (size != 64)
1186 return 0;
1187 }
1188 else if (str[0] == '@')
1189 {
1190 if (alpha_tls_size > size)
1191 return 0;
1192 }
1193 else
1194 return 0;
1195
1196 letter = (unspec == UNSPEC_DTPREL ? 'D' : 'T');
1197
1198 return str[1] == letter;
1199}
1200
1201/* Return true if OP is valid for 16-bit DTP relative relocations. */
1202
1203int
1204dtp16_symbolic_operand (op, mode)
1205 rtx op;
1206 enum machine_mode mode;
1207{
1208 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1209}
1210
1211/* Return true if OP is valid for 32-bit DTP relative relocations. */
1212
1213int
1214dtp32_symbolic_operand (op, mode)
1215 rtx op;
1216 enum machine_mode mode;
1217{
1218 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1219}
1220
1221/* Return true if OP is valid for 64-bit DTP relative relocations. */
1222
1223int
1224gotdtp_symbolic_operand (op, mode)
1225 rtx op;
1226 enum machine_mode mode;
1227{
1228 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1229}
1230
1231/* Return true if OP is valid for 16-bit TP relative relocations. */
1232
1233int
1234tp16_symbolic_operand (op, mode)
1235 rtx op;
1236 enum machine_mode mode;
1237{
1238 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1239}
1240
1241/* Return true if OP is valid for 32-bit TP relative relocations. */
1242
1243int
1244tp32_symbolic_operand (op, mode)
1245 rtx op;
1246 enum machine_mode mode;
1247{
1248 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1249}
1250
1251/* Return true if OP is valid for 64-bit TP relative relocations. */
1252
1253int
1254gottp_symbolic_operand (op, mode)
1255 rtx op;
1256 enum machine_mode mode;
1257{
1258 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1259}
1260
a6f12d7c
RK		 1261/* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1262 comparisons are valid in which insn. */
1263
1264int
1265alpha_comparison_operator (op, mode)
1266 register rtx op;
1267 enum machine_mode mode;
1268{
1269 enum rtx_code code = GET_CODE (op);
1270
1eb8759b 1271 if (mode != GET_MODE (op) && mode != VOIDmode)
a6f12d7c
RK		 1272 return 0;
1273
1274 return (code == EQ || code == LE || code == LT
a0e5a544 1275 || code == LEU || code == LTU);
a6f12d7c
RK		 1276}
1277
8f4773ea
RH		 1278/* Return 1 if OP is a valid Alpha comparison operator against zero.
1279 Here we know which comparisons are valid in which insn. */
1280
1281int
1282alpha_zero_comparison_operator (op, mode)
1283 register rtx op;
1284 enum machine_mode mode;
1285{
1286 enum rtx_code code = GET_CODE (op);
1287
1288 if (mode != GET_MODE (op) && mode != VOIDmode)
1289 return 0;
1290
1291 return (code == EQ || code == NE || code == LE || code == LT
1292 || code == LEU || code == LTU);
1293}
1294
5bf6c48a
RK		 1295/* Return 1 if OP is a valid Alpha swapped comparison operator. */
1296
1297int
1298alpha_swapped_comparison_operator (op, mode)
1299 register rtx op;
1300 enum machine_mode mode;
1301{
1302 enum rtx_code code = GET_CODE (op);
1303
1eb8759b
RH		 1304 if ((mode != GET_MODE (op) && mode != VOIDmode)
1305 || GET_RTX_CLASS (code) != '<')
5bf6c48a
RK		 1306 return 0;
1307
1308 code = swap_condition (code);
1309 return (code == EQ || code == LE || code == LT
a0e5a544 1310 || code == LEU || code == LTU);
5bf6c48a
RK		 1311}
1312
a6f12d7c
RK		 1313/* Return 1 if OP is a signed comparison operation. */
1314
1315int
1316signed_comparison_operator (op, mode)
1317 register rtx op;
3c303f52 1318 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c 1319{
1eb8759b 1320 enum rtx_code code = GET_CODE (op);
1d300e19 1321
1eb8759b
RH		 1322 if (mode != GET_MODE (op) && mode != VOIDmode)
1323 return 0;
a6f12d7c 1324
1eb8759b
RH		 1325 return (code == EQ || code == NE
1326 || code == LE || code == LT
1327 || code == GE || code == GT);
1328}
1329
1330/* Return 1 if OP is a valid Alpha floating point comparison operator.
1331 Here we know which comparisons are valid in which insn. */
1332
1333int
1334alpha_fp_comparison_operator (op, mode)
1335 register rtx op;
1336 enum machine_mode mode;
1337{
1338 enum rtx_code code = GET_CODE (op);
1339
1340 if (mode != GET_MODE (op) && mode != VOIDmode)
1341 return 0;
1342
1343 return (code == EQ || code == LE || code == LT || code == UNORDERED);
a6f12d7c
RK		 1344}
1345
1346/* Return 1 if this is a divide or modulus operator. */
1347
1348int
1349divmod_operator (op, mode)
1350 register rtx op;
3c303f52 1351 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c
RK		 1352{
1353 switch (GET_CODE (op))
1354 {
1355 case DIV: case MOD: case UDIV: case UMOD:
1356 return 1;
1d300e19
KG		 1357
1358 default:
1359 break;
a6f12d7c
RK		 1360 }
1361
1362 return 0;
1363}
1364
1365/* Return 1 if this memory address is a known aligned register plus
1366 a constant. It must be a valid address. This means that we can do
1367 this as an aligned reference plus some offset.
1368
96043e7e 1369 Take into account what reload will do. */
a6f12d7c
RK		 1370
1371int
1372aligned_memory_operand (op, mode)
1373 register rtx op;
1374 enum machine_mode mode;
1375{
4e46365b 1376 rtx base;
a6f12d7c 1377
96043e7e
RH		 1378 if (reload_in_progress)
1379 {
4e46365b
RH		 1380 rtx tmp = op;
1381 if (GET_CODE (tmp) == SUBREG)
1382 tmp = SUBREG_REG (tmp);
1383 if (GET_CODE (tmp) == REG
1384 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1385 {
1386 op = reg_equiv_memory_loc[REGNO (tmp)];
1387 if (op == 0)
1388 return 0;
1389 }
96043e7e 1390 }
a6f12d7c 1391
96043e7e 1392 if (GET_CODE (op) != MEM
4e46365b 1393 || GET_MODE (op) != mode)
a6f12d7c 1394 return 0;
a6f12d7c
RK		 1395 op = XEXP (op, 0);
1396
4e46365b
RH		 1397 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1398 sorts of constructs. Dig for the real base register. */
1399 if (reload_in_progress
1400 && GET_CODE (op) == PLUS
1401 && GET_CODE (XEXP (op, 0)) == PLUS)
1402 base = XEXP (XEXP (op, 0), 0);
1403 else
1404 {
1405 if (! memory_address_p (mode, op))
1406 return 0;
1407 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1408 }
a6f12d7c 1409
bdb429a5 1410 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
a6f12d7c
RK		 1411}
1412
1413/* Similar, but return 1 if OP is a MEM which is not alignable. */
1414
1415int
1416unaligned_memory_operand (op, mode)
1417 register rtx op;
1418 enum machine_mode mode;
1419{
4e46365b
RH		 1420 rtx base;
1421
1422 if (reload_in_progress)
a6f12d7c 1423 {
4e46365b
RH		 1424 rtx tmp = op;
1425 if (GET_CODE (tmp) == SUBREG)
1426 tmp = SUBREG_REG (tmp);
1427 if (GET_CODE (tmp) == REG
1428 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1429 {
1430 op = reg_equiv_memory_loc[REGNO (tmp)];
1431 if (op == 0)
1432 return 0;
1433 }
a6f12d7c
RK		 1434 }
1435
4e46365b
RH		 1436 if (GET_CODE (op) != MEM
1437 || GET_MODE (op) != mode)
a6f12d7c 1438 return 0;
a6f12d7c
RK		 1439 op = XEXP (op, 0);
1440
4e46365b
RH		 1441 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1442 sorts of constructs. Dig for the real base register. */
1443 if (reload_in_progress
1444 && GET_CODE (op) == PLUS
1445 && GET_CODE (XEXP (op, 0)) == PLUS)
1446 base = XEXP (XEXP (op, 0), 0);
1447 else
1448 {
1449 if (! memory_address_p (mode, op))
1450 return 0;
1451 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1452 }
a6f12d7c 1453
bdb429a5 1454 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
adb18b68
RK		 1455}
1456
1457/* Return 1 if OP is either a register or an unaligned memory location. */
1458
1459int
1460reg_or_unaligned_mem_operand (op, mode)
1461 rtx op;
1462 enum machine_mode mode;
1463{
1464 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
a6f12d7c
RK		 1465}
1466
1467/* Return 1 if OP is any memory location. During reload a pseudo matches. */
1468
1469int
1470any_memory_operand (op, mode)
1471 register rtx op;
3c303f52 1472 enum machine_mode mode ATTRIBUTE_UNUSED;
a6f12d7c
RK		 1473{
1474 return (GET_CODE (op) == MEM
1475 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1476 || (reload_in_progress && GET_CODE (op) == REG
1477 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1478 || (reload_in_progress && GET_CODE (op) == SUBREG
1479 && GET_CODE (SUBREG_REG (op)) == REG
1480 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1481}
1482
40b80dad
RH		 1483/* Returns 1 if OP is not an eliminable register.
1484
1485 This exists to cure a pathological abort in the s8addq (et al) patterns,
1486
1487 long foo () { long t; bar(); return (long) &t * 26107; }
1488
1489 which run afoul of a hack in reload to cure a (presumably) similar
1490 problem with lea-type instructions on other targets. But there is
1491 one of us and many of them, so work around the problem by selectively
1492 preventing combine from making the optimization. */
1493
1494int
1495reg_not_elim_operand (op, mode)
1496 register rtx op;
1497 enum machine_mode mode;
1498{
1499 rtx inner = op;
1500 if (GET_CODE (op) == SUBREG)
1501 inner = SUBREG_REG (op);
1502 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1503 return 0;
1504
1505 return register_operand (op, mode);
1506}
9c0e94a5 1507
67070f5c 1508/* Return 1 is OP is a memory location that is not a reference (using
ab87f8c8
JL		 1509 an AND) to an unaligned location. Take into account what reload
1510 will do. */
1511
1512int
1513normal_memory_operand (op, mode)
1514 register rtx op;
df45c7ea 1515 enum machine_mode mode ATTRIBUTE_UNUSED;
ab87f8c8 1516{
4e46365b 1517 if (reload_in_progress)
ab87f8c8 1518 {
4e46365b
RH		 1519 rtx tmp = op;
1520 if (GET_CODE (tmp) == SUBREG)
1521 tmp = SUBREG_REG (tmp);
1522 if (GET_CODE (tmp) == REG
1523 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1524 {
1525 op = reg_equiv_memory_loc[REGNO (tmp)];
ab87f8c8 1526
4e46365b
RH		 1527 /* This may not have been assigned an equivalent address if it will
1528 be eliminated. In that case, it doesn't matter what we do. */
1529 if (op == 0)
1530 return 1;
1531 }
ab87f8c8
JL		 1532 }
1533
1534 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1535}
67070f5c
RH		 1536
1537/* Accept a register, but not a subreg of any kind. This allows us to
1538 avoid pathological cases in reload wrt data movement common in
1539 int->fp conversion. */
1540
1541int
1542reg_no_subreg_operand (op, mode)
1543 register rtx op;
1544 enum machine_mode mode;
1545{
f6598df3 1546 if (GET_CODE (op) != REG)
67070f5c
RH		 1547 return 0;
1548 return register_operand (op, mode);
1549}
3611aef0 1550
5519a4f9 1551/* Recognize an addition operation that includes a constant. Used to
3611aef0
RH		 1552 convince reload to canonize (plus (plus reg c1) c2) during register
1553 elimination. */
1554
1555int
1556addition_operation (op, mode)
1557 register rtx op;
1558 enum machine_mode mode;
1559{
1560 if (GET_MODE (op) != mode && mode != VOIDmode)
1561 return 0;
1562 if (GET_CODE (op) == PLUS
1563 && register_operand (XEXP (op, 0), mode)
1564 && GET_CODE (XEXP (op, 1)) == CONST_INT
1565 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1566 return 1;
1567 return 0;
1568}
1569
551cc6fd
RH		 1570/* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1571 the range defined for C in [I-P]. */
1572
1573bool
1574alpha_const_ok_for_letter_p (value, c)
1575 HOST_WIDE_INT value;
1576 int c;
1577{
1578 switch (c)
1579 {
1580 case 'I':
1581 /* An unsigned 8 bit constant. */
1582 return (unsigned HOST_WIDE_INT) value < 0x100;
1583 case 'J':
1584 /* The constant zero. */
1585 return value == 0;
1586 case 'K':
1587 /* A signed 16 bit constant. */
1588 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1589 case 'L':
1590 /* A shifted signed 16 bit constant appropriate for LDAH. */
1591 return ((value & 0xffff) == 0
1592 && ((value) >> 31 == -1 || value >> 31 == 0));
1593 case 'M':
1594 /* A constant that can be AND'ed with using a ZAP insn. */
1595 return zap_mask (value);
1596 case 'N':
1597 /* A complemented unsigned 8 bit constant. */
1598 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1599 case 'O':
1600 /* A negated unsigned 8 bit constant. */
1601 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1602 case 'P':
1603 /* The constant 1, 2 or 3. */
1604 return value == 1 || value == 2 || value == 3;
1605
1606 default:
1607 return false;
1608 }
1609}
1610
1611/* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1612 matches for C in [GH]. */
1613
1614bool
1615alpha_const_double_ok_for_letter_p (value, c)
1616 rtx value;
1617 int c;
1618{
1619 switch (c)
1620 {
1621 case 'G':
1622 /* The floating point zero constant. */
1623 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1624 && value == CONST0_RTX (GET_MODE (value)));
1625
1626 case 'H':
1627 /* A valid operand of a ZAP insn. */
1628 return (GET_MODE (value) == VOIDmode
1629 && zap_mask (CONST_DOUBLE_LOW (value))
1630 && zap_mask (CONST_DOUBLE_HIGH (value)));
1631
1632 default:
1633 return false;
1634 }
1635}
1636
1637/* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1638 matches for C. */
1639
1640bool
1641alpha_extra_constraint (value, c)
1642 rtx value;
1643 int c;
1644{
1645 switch (c)
1646 {
1647 case 'Q':
1648 return normal_memory_operand (value, VOIDmode);
1649 case 'R':
1650 return direct_call_operand (value, Pmode);
1651 case 'S':
1652 return (GET_CODE (value) == CONST_INT
1653 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1654 case 'T':
1655 return GET_CODE (value) == HIGH;
1656 case 'U':
1657 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
6d8fd7bb
RH		 1658 case 'W':
1659 return (GET_CODE (value) == CONST_VECTOR
1660 && value == CONST0_RTX (GET_MODE (value)));
551cc6fd
RH		 1661 default:
1662 return false;
1663 }
1664}
1665
39157bcc
RH		 1666/* Return 1 if this function can directly return via $26. */
1667
1668int
1669direct_return ()
1670{
30102605 1671 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
be7b80f4
RH		 1672 && reload_completed
1673 && alpha_sa_size () == 0
39157bcc
RH		 1674 && get_frame_size () == 0
1675 && current_function_outgoing_args_size == 0
1676 && current_function_pretend_args_size == 0);
1677}
25e21aed
RH		 1678
1679/* Return the ADDR_VEC associated with a tablejump insn. */
1680
1681rtx
1682alpha_tablejump_addr_vec (insn)
1683 rtx insn;
1684{
1685 rtx tmp;
1686
1687 tmp = JUMP_LABEL (insn);
1688 if (!tmp)
1689 return NULL_RTX;
1690 tmp = NEXT_INSN (tmp);
1691 if (!tmp)
1692 return NULL_RTX;
1693 if (GET_CODE (tmp) == JUMP_INSN
1694 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1695 return PATTERN (tmp);
1696 return NULL_RTX;
1697}
1698
1699/* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1700
1701rtx
1702alpha_tablejump_best_label (insn)
1703 rtx insn;
1704{
1705 rtx jump_table = alpha_tablejump_addr_vec (insn);
1706 rtx best_label = NULL_RTX;
1707
1708 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1709 there for edge frequency counts from profile data. */
1710
1711 if (jump_table)
1712 {
1713 int n_labels = XVECLEN (jump_table, 1);
1714 int best_count = -1;
1715 int i, j;
1716
1717 for (i = 0; i < n_labels; i++)
1718 {
1719 int count = 1;
1720
1721 for (j = i + 1; j < n_labels; j++)
1722 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1723 == XEXP (XVECEXP (jump_table, 1, j), 0))
1724 count++;
1725
1726 if (count > best_count)
1727 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1728 }
1729 }
1730
1731 return best_label ? best_label : const0_rtx;
1732}
6f9b006d
RH		 1733
1734/* Return the TLS model to use for SYMBOL. */
1735
1736static enum tls_model
1737tls_symbolic_operand_type (symbol)
1738 rtx symbol;
1739{
1740 const char *str;
1741
1742 if (GET_CODE (symbol) != SYMBOL_REF)
1743 return 0;
1744 str = XSTR (symbol, 0);
1745
1746 if (str[0] == '%')
1747 {
1748 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1749 have separately encoded local-ness. On well, maybe the user will use
1750 attribute visibility next time. At least we don't crash... */
1751 if (str[1] == 'G' || str[1] == 'D')
1752 return TLS_MODEL_GLOBAL_DYNAMIC;
1753 if (str[1] == 'T')
1754 return TLS_MODEL_INITIAL_EXEC;
1755 }
1756 else if (str[0] == '@')
1757 {
1758 if (str[1] == 'D')
1759 {
1760 /* Local dynamic is a waste if we're not going to combine
1761 the __tls_get_addr calls. So avoid it if not optimizing. */
1762 if (optimize)
1763 return TLS_MODEL_LOCAL_DYNAMIC;
1764 else
1765 return TLS_MODEL_GLOBAL_DYNAMIC;
1766 }
1767 if (str[1] == 'T')
1768 {
1769 /* 64-bit local exec is the same as initial exec except without
1770 the dynamic relocation. In either case we use a got entry. */
1771 if (alpha_tls_size == 64)
1772 return TLS_MODEL_INITIAL_EXEC;
1773 else
1774 return TLS_MODEL_LOCAL_EXEC;
1775 }
1776 }
1777
1778 return 0;
1779}
1780
3611aef0 1781\f
62918bd3
RH		 1782/* Return true if the function DECL will be placed in the default text
1783 section. */
1784/* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1785 decl, as that would allow us to determine if two functions are in the
1786 same section, which is what we really want to know. */
1787
1788static bool
1789decl_in_text_section (decl)
1790 tree decl;
1791{
1792 return (DECL_SECTION_NAME (decl) == NULL_TREE
1793 && ! (flag_function_sections
1794 || (targetm.have_named_sections
1795 && DECL_ONE_ONLY (decl))));
1796}
1797
ae46c4e0
RH		 1798/* Return true if EXP should be placed in the small data section. */
1799
1800static bool
1801alpha_in_small_data_p (exp)
1802 tree exp;
1803{
34a6c2ec
RH		 1804 /* We want to merge strings, so we never consider them small data. */
1805 if (TREE_CODE (exp) == STRING_CST)
1806 return false;
1807
ae46c4e0
RH		 1808 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1809 {
1810 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1811 if (strcmp (section, ".sdata") == 0
1812 || strcmp (section, ".sbss") == 0)
1813 return true;
1814 }
1815 else
1816 {
1817 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1818
1819 /* If this is an incomplete type with size 0, then we can't put it
1820 in sdata because it might be too big when completed. */
1821 if (size > 0 && size <= g_switch_value)
1822 return true;
1823 }
1824
1825 return false;
1826}
1827
1eb356b9
RH		 1828/* If we are referencing a function that is static, make the SYMBOL_REF
1829 special. We use this to see indicate we can branch to this function
1830 without setting PV or restoring GP.
1831
1832 If this is a variable that is known to be defined locally, add "@v"
1833 to the name. If in addition the variable is to go in .sdata/.sbss,
1834 then add "@s" instead. */
1835
fb49053f 1836static void
b2003250 1837alpha_encode_section_info (decl, first)
1eb356b9 1838 tree decl;
b2003250 1839 int first ATTRIBUTE_UNUSED;
1eb356b9
RH		 1840{
1841 const char *symbol_str;
6f9b006d
RH		 1842 bool is_local;
1843 char encoding = 0;
47754fd5 1844 rtx rtl, symbol;
1eb356b9 1845
47754fd5
RH		 1846 rtl = DECL_P (decl) ? DECL_RTL (decl) : TREE_CST_RTL (decl);
1847
1848 /* Careful not to prod global register variables. */
1849 if (GET_CODE (rtl) != MEM)
1850 return;
1851 symbol = XEXP (rtl, 0);
1852 if (GET_CODE (symbol) != SYMBOL_REF)
1853 return;
1854
1eb356b9
RH		 1855 if (TREE_CODE (decl) == FUNCTION_DECL)
1856 {
62918bd3
RH		 1857 /* We mark public functions once they are emitted; otherwise we
1858 don't know that they exist in this unit of translation. */
1859 if (TREE_PUBLIC (decl))
1860 return;
eadccfbb 1861
62918bd3
RH		 1862 /* Do not mark functions that are not in .text; otherwise we
1863 don't know that they are near enough for a direct branch. */
1864 if (! decl_in_text_section (decl))
1865 return;
1866
47754fd5 1867 SYMBOL_REF_FLAG (symbol) = 1;
1eb356b9
RH		 1868 return;
1869 }
1870
1871 /* Early out if we're not going to do anything with this data. */
1872 if (! TARGET_EXPLICIT_RELOCS)
1873 return;
1874
47754fd5 1875 symbol_str = XSTR (symbol, 0);
1eb356b9
RH		 1876
1877 /* A variable is considered "local" if it is defined in this module. */
47754fd5 1878 is_local = (*targetm.binds_local_p) (decl);
1eb356b9 1879
6f9b006d
RH		 1880 /* Care for TLS variables. */
1881 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL (decl))
1882 {
1883 enum tls_model kind;
1884 if (!flag_pic)
1885 {
1886 if (is_local)
1887 kind = TLS_MODEL_LOCAL_EXEC;
1888 else
1889 kind = TLS_MODEL_INITIAL_EXEC;
1890 }
1891 else if (is_local)
1892 kind = TLS_MODEL_LOCAL_DYNAMIC;
1893 else
1894 kind = TLS_MODEL_GLOBAL_DYNAMIC;
1895 if (kind < flag_tls_default)
1896 kind = flag_tls_default;
1897
1898 switch (kind)
1899 {
1900 case TLS_MODEL_GLOBAL_DYNAMIC:
1901 encoding = 'G';
1902 break;
1903 case TLS_MODEL_LOCAL_DYNAMIC:
1904 encoding = 'D';
1905 break;
1906 case TLS_MODEL_INITIAL_EXEC:
1907 case TLS_MODEL_LOCAL_EXEC:
1908 encoding = 'T';
1909 break;
1910 }
1911 }
1912 else if (is_local)
1913 {
1914 /* Determine if DECL will wind up in .sdata/.sbss. */
1915 if (alpha_in_small_data_p (decl))
1916 encoding = 'S';
1917 else
1918 encoding = 'L';
1919 }
1eb356b9
RH		 1920
1921 /* Finally, encode this into the symbol string. */
6f9b006d 1922 if (encoding)
1eb356b9 1923 {
1eb356b9
RH		 1924 char *newstr;
1925 size_t len;
1926
6f9b006d 1927 if (symbol_str[0] == (is_local ? '@' : '%'))
1eb356b9 1928 {
6f9b006d 1929 if (symbol_str[1] == encoding)
1eb356b9
RH		 1930 return;
1931 symbol_str += 2;
1932 }
1933
1934 len = strlen (symbol_str) + 1;
1935 newstr = alloca (len + 2);
1936
6f9b006d
RH		 1937 newstr[0] = (is_local ? '@' : '%');
1938 newstr[1] = encoding;
1eb356b9
RH		 1939 memcpy (newstr + 2, symbol_str, len);
1940
47754fd5 1941 XSTR (symbol, 0) = ggc_alloc_string (newstr, len + 2 - 1);
1eb356b9 1942 }
1eb356b9
RH		 1943}
1944
772c5265
RH		 1945/* Undo the effects of the above. */
1946
1947static const char *
1948alpha_strip_name_encoding (str)
1949 const char *str;
1950{
6f9b006d 1951 if (str[0] == '@' || str[0] == '%')
772c5265
RH		 1952 str += 2;
1953 if (str[0] == '*')
1954 str++;
1955 return str;
1956}
1957
1330f7d5
DR		 1958#if TARGET_ABI_OPEN_VMS
1959static bool
1960alpha_linkage_symbol_p (symname)
1961 const char *symname;
1962{
1963 int symlen = strlen (symname);
1964
1965 if (symlen > 4)
1966 return strcmp (&symname [symlen - 4], "..lk") == 0;
1967
1968 return false;
1969}
1970
1971#define LINKAGE_SYMBOL_REF_P(X) \
1972 ((GET_CODE (X) == SYMBOL_REF \
1973 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1974 || (GET_CODE (X) == CONST \
1975 && GET_CODE (XEXP (X, 0)) == PLUS \
1976 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1977 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1978#endif
1979
a39bdefc
RH		 1980/* legitimate_address_p recognizes an RTL expression that is a valid
1981 memory address for an instruction. The MODE argument is the
1982 machine mode for the MEM expression that wants to use this address.
1983
1984 For Alpha, we have either a constant address or the sum of a
1985 register and a constant address, or just a register. For DImode,
1986 any of those forms can be surrounded with an AND that clear the
1987 low-order three bits; this is an "unaligned" access. */
1988
1989bool
1990alpha_legitimate_address_p (mode, x, strict)
1991 enum machine_mode mode;
1992 rtx x;
1993 int strict;
1994{
1995 /* If this is an ldq_u type address, discard the outer AND. */
1996 if (mode == DImode
1997 && GET_CODE (x) == AND
1998 && GET_CODE (XEXP (x, 1)) == CONST_INT
1999 && INTVAL (XEXP (x, 1)) == -8)
2000 x = XEXP (x, 0);
2001
2002 /* Discard non-paradoxical subregs. */
2003 if (GET_CODE (x) == SUBREG
2004 && (GET_MODE_SIZE (GET_MODE (x))
2005 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2006 x = SUBREG_REG (x);
2007
2008 /* Unadorned general registers are valid. */
2009 if (REG_P (x)
2010 && (strict
2011 ? STRICT_REG_OK_FOR_BASE_P (x)
2012 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
2013 return true;
2014
2015 /* Constant addresses (i.e. +/- 32k) are valid. */
2016 if (CONSTANT_ADDRESS_P (x))
2017 return true;
2018
1330f7d5
DR		 2019#if TARGET_ABI_OPEN_VMS
2020 if (LINKAGE_SYMBOL_REF_P (x))
2021 return true;
2022#endif
2023
a39bdefc
RH		 2024 /* Register plus a small constant offset is valid. */
2025 if (GET_CODE (x) == PLUS)
2026 {
2027 rtx ofs = XEXP (x, 1);
2028 x = XEXP (x, 0);
2029
2030 /* Discard non-paradoxical subregs. */
2031 if (GET_CODE (x) == SUBREG
2032 && (GET_MODE_SIZE (GET_MODE (x))
2033 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2034 x = SUBREG_REG (x);
2035
2036 if (REG_P (x))
2037 {
2038 if (! strict
2039 && NONSTRICT_REG_OK_FP_BASE_P (x)
2040 && GET_CODE (ofs) == CONST_INT)
2041 return true;
2042 if ((strict
2043 ? STRICT_REG_OK_FOR_BASE_P (x)
2044 : NONSTRICT_REG_OK_FOR_BASE_P (x))
2045 && CONSTANT_ADDRESS_P (ofs))
2046 return true;
2047 }
2048 else if (GET_CODE (x) == ADDRESSOF
2049 && GET_CODE (ofs) == CONST_INT)
2050 return true;
2051 }
2052
551cc6fd
RH		 2053 /* If we're managing explicit relocations, LO_SUM is valid, as
2054 are small data symbols. */
2055 else if (TARGET_EXPLICIT_RELOCS)
1eb356b9 2056 {
551cc6fd 2057 if (small_symbolic_operand (x, Pmode))
1eb356b9 2058 return true;
551cc6fd
RH		 2059
2060 if (GET_CODE (x) == LO_SUM)
2061 {
2062 rtx ofs = XEXP (x, 1);
2063 x = XEXP (x, 0);
2064
2065 /* Discard non-paradoxical subregs. */
2066 if (GET_CODE (x) == SUBREG
2067 && (GET_MODE_SIZE (GET_MODE (x))
2068 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2069 x = SUBREG_REG (x);
2070
2071 /* Must have a valid base register. */
2072 if (! (REG_P (x)
2073 && (strict
2074 ? STRICT_REG_OK_FOR_BASE_P (x)
2075 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
2076 return false;
2077
2078 /* The symbol must be local. */
6f9b006d
RH		 2079 if (local_symbolic_operand (ofs, Pmode)
2080 || dtp32_symbolic_operand (ofs, Pmode)
2081 || tp32_symbolic_operand (ofs, Pmode))
551cc6fd
RH		 2082 return true;
2083 }
1eb356b9
RH		 2084 }
2085
a39bdefc
RH		 2086 return false;
2087}
2088
aead1ca3
RH		 2089/* Try machine-dependent ways of modifying an illegitimate address
2090 to be legitimate. If we find one, return the new, valid address. */
2091
2092rtx
551cc6fd 2093alpha_legitimize_address (x, scratch, mode)
aead1ca3 2094 rtx x;
551cc6fd 2095 rtx scratch;
aead1ca3
RH		 2096 enum machine_mode mode ATTRIBUTE_UNUSED;
2097{
2098 HOST_WIDE_INT addend;
2099
2100 /* If the address is (plus reg const_int) and the CONST_INT is not a
2101 valid offset, compute the high part of the constant and add it to
2102 the register. Then our address is (plus temp low-part-const). */
2103 if (GET_CODE (x) == PLUS
2104 && GET_CODE (XEXP (x, 0)) == REG
2105 && GET_CODE (XEXP (x, 1)) == CONST_INT
2106 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
2107 {
2108 addend = INTVAL (XEXP (x, 1));
2109 x = XEXP (x, 0);
2110 goto split_addend;
2111 }
2112
2113 /* If the address is (const (plus FOO const_int)), find the low-order
2114 part of the CONST_INT. Then load FOO plus any high-order part of the
2115 CONST_INT into a register. Our address is (plus reg low-part-const).
2116 This is done to reduce the number of GOT entries. */
551cc6fd
RH		 2117 if (!no_new_pseudos
2118 && GET_CODE (x) == CONST
aead1ca3
RH		 2119 && GET_CODE (XEXP (x, 0)) == PLUS
2120 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2121 {
2122 addend = INTVAL (XEXP (XEXP (x, 0), 1));
2123 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
2124 goto split_addend;
2125 }
2126
2127 /* If we have a (plus reg const), emit the load as in (2), then add
2128 the two registers, and finally generate (plus reg low-part-const) as
2129 our address. */
551cc6fd
RH		 2130 if (!no_new_pseudos
2131 && GET_CODE (x) == PLUS
aead1ca3
RH		 2132 && GET_CODE (XEXP (x, 0)) == REG
2133 && GET_CODE (XEXP (x, 1)) == CONST
2134 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
2135 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
2136 {
2137 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
2138 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
2139 XEXP (XEXP (XEXP (x, 1), 0), 0),
2140 NULL_RTX, 1, OPTAB_LIB_WIDEN);
2141 goto split_addend;
2142 }
2143
1eb356b9 2144 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
e2c9fb9b 2145 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1eb356b9 2146 {
6f9b006d
RH		 2147 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
2148
2149 switch (tls_symbolic_operand_type (x))
2150 {
2151 case TLS_MODEL_GLOBAL_DYNAMIC:
2152 start_sequence ();
2153
2154 r0 = gen_rtx_REG (Pmode, 0);
2155 r16 = gen_rtx_REG (Pmode, 16);
2156 tga = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
2157 dest = gen_reg_rtx (Pmode);
2158 seq = GEN_INT (alpha_next_sequence_number++);
2159
2160 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
2161 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
2162 insn = emit_call_insn (insn);
2163 CONST_OR_PURE_CALL_P (insn) = 1;
2164 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
2165
2166 insn = get_insns ();
2167 end_sequence ();
2168
2169 emit_libcall_block (insn, dest, r0, x);
2170 return dest;
2171
2172 case TLS_MODEL_LOCAL_DYNAMIC:
2173 start_sequence ();
2174
2175 r0 = gen_rtx_REG (Pmode, 0);
2176 r16 = gen_rtx_REG (Pmode, 16);
2177 tga = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
2178 scratch = gen_reg_rtx (Pmode);
2179 seq = GEN_INT (alpha_next_sequence_number++);
2180
2181 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
2182 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
2183 insn = emit_call_insn (insn);
2184 CONST_OR_PURE_CALL_P (insn) = 1;
2185 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
2186
2187 insn = get_insns ();
2188 end_sequence ();
2189
2190 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2191 UNSPEC_TLSLDM_CALL);
2192 emit_libcall_block (insn, scratch, r0, eqv);
2193
2194 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
2195 eqv = gen_rtx_CONST (Pmode, eqv);
2196
2197 if (alpha_tls_size == 64)
2198 {
2199 dest = gen_reg_rtx (Pmode);
2200 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
2201 emit_insn (gen_adddi3 (dest, dest, scratch));
2202 return dest;
2203 }
2204 if (alpha_tls_size == 32)
2205 {
2206 insn = gen_rtx_HIGH (Pmode, eqv);
2207 insn = gen_rtx_PLUS (Pmode, scratch, insn);
2208 scratch = gen_reg_rtx (Pmode);
2209 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
2210 }
2211 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
2212
2213 case TLS_MODEL_INITIAL_EXEC:
2214 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
2215 eqv = gen_rtx_CONST (Pmode, eqv);
2216 tp = gen_reg_rtx (Pmode);
2217 scratch = gen_reg_rtx (Pmode);
2218 dest = gen_reg_rtx (Pmode);
2219
2220 emit_insn (gen_load_tp (tp));
2221 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
2222 emit_insn (gen_adddi3 (dest, tp, scratch));
2223 return dest;
2224
2225 case TLS_MODEL_LOCAL_EXEC:
2226 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
2227 eqv = gen_rtx_CONST (Pmode, eqv);
2228 tp = gen_reg_rtx (Pmode);
2229
2230 emit_insn (gen_load_tp (tp));
2231 if (alpha_tls_size == 32)
2232 {
2233 insn = gen_rtx_HIGH (Pmode, eqv);
2234 insn = gen_rtx_PLUS (Pmode, tp, insn);
2235 tp = gen_reg_rtx (Pmode);
2236 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
2237 }
2238 return gen_rtx_LO_SUM (Pmode, tp, eqv);
2239 }
2240
e2c9fb9b
RH		 2241 if (local_symbolic_operand (x, Pmode))
2242 {
2243 if (small_symbolic_operand (x, Pmode))
551cc6fd 2244 return x;
e2c9fb9b
RH		 2245 else
2246 {
551cc6fd
RH		 2247 if (!no_new_pseudos)
2248 scratch = gen_reg_rtx (Pmode);
2249 emit_insn (gen_rtx_SET (VOIDmode, scratch,
2250 gen_rtx_HIGH (Pmode, x)));
2251 return gen_rtx_LO_SUM (Pmode, scratch, x);
e2c9fb9b 2252 }
133d3133 2253 }
1eb356b9
RH		 2254 }
2255
aead1ca3
RH		 2256 return NULL;
2257
2258 split_addend:
2259 {
551cc6fd
RH		 2260 HOST_WIDE_INT low, high;
2261
2262 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
2263 addend -= low;
2264 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
2265 addend -= high;
2266
2267 if (addend)
2268 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
2269 (no_new_pseudos ? scratch : NULL_RTX),
2270 1, OPTAB_LIB_WIDEN);
2271 if (high)
2272 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
2273 (no_new_pseudos ? scratch : NULL_RTX),
2274 1, OPTAB_LIB_WIDEN);
2275
2276 return plus_constant (x, low);
aead1ca3
RH		 2277 }
2278}
2279
551cc6fd
RH		 2280/* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2281 small symbolic operand until after reload. At which point we need
2282 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2283 so that sched2 has the proper dependency information. */
2284
2285int
a615ca3e 2286some_small_symbolic_operand (x, mode)
551cc6fd
RH		 2287 rtx x;
2288 enum machine_mode mode ATTRIBUTE_UNUSED;
2289{
a615ca3e 2290 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
1e7e480e
RH		 2291}
2292
2293static int
a615ca3e 2294some_small_symbolic_operand_1 (px, data)
1e7e480e
RH		 2295 rtx *px;
2296 void *data ATTRIBUTE_UNUSED;
2297{
2298 rtx x = *px;
551cc6fd 2299
a615ca3e
RH		 2300 /* Don't re-split. */
2301 if (GET_CODE (x) == LO_SUM)
2302 return -1;
1e7e480e 2303
a615ca3e 2304 return small_symbolic_operand (x, Pmode) != 0;
551cc6fd
RH		 2305}
2306
2307rtx
a615ca3e 2308split_small_symbolic_operand (x)
551cc6fd
RH		 2309 rtx x;
2310{
8b9b74a9 2311 x = copy_insn (x);
a615ca3e 2312 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
1e7e480e
RH		 2313 return x;
2314}
551cc6fd 2315
1e7e480e 2316static int
a615ca3e 2317split_small_symbolic_operand_1 (px, data)
1e7e480e
RH		 2318 rtx *px;
2319 void *data ATTRIBUTE_UNUSED;
2320{
2321 rtx x = *px;
51c561e3 2322
a615ca3e
RH		 2323 /* Don't re-split. */
2324 if (GET_CODE (x) == LO_SUM)
2325 return -1;
551cc6fd 2326
1e7e480e
RH		 2327 if (small_symbolic_operand (x, Pmode))
2328 {
2329 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2330 *px = x;
a615ca3e 2331 return -1;
1e7e480e
RH		 2332 }
2333
a615ca3e 2334 return 0;
551cc6fd
RH		 2335}
2336
aead1ca3
RH		 2337/* Try a machine-dependent way of reloading an illegitimate address
2338 operand. If we find one, push the reload and return the new rtx. */
2339
2340rtx
2341alpha_legitimize_reload_address (x, mode, opnum, type, ind_levels)
2342 rtx x;
2343 enum machine_mode mode ATTRIBUTE_UNUSED;
2344 int opnum;
2345 int type;
2346 int ind_levels ATTRIBUTE_UNUSED;
2347{
2348 /* We must recognize output that we have already generated ourselves. */
2349 if (GET_CODE (x) == PLUS
2350 && GET_CODE (XEXP (x, 0)) == PLUS
2351 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2352 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2353 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2354 {
2355 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2356 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2357 opnum, type);
2358 return x;
2359 }
2360
2361 /* We wish to handle large displacements off a base register by
2362 splitting the addend across an ldah and the mem insn. This
2363 cuts number of extra insns needed from 3 to 1. */
2364 if (GET_CODE (x) == PLUS
2365 && GET_CODE (XEXP (x, 0)) == REG
2366 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2367 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2368 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2369 {
2370 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2371 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2372 HOST_WIDE_INT high
2373 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2374
2375 /* Check for 32-bit overflow. */
2376 if (high + low != val)
2377 return NULL_RTX;
2378
2379 /* Reload the high part into a base reg; leave the low part
2380 in the mem directly. */
2381 x = gen_rtx_PLUS (GET_MODE (x),
2382 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2383 GEN_INT (high)),
2384 GEN_INT (low));
2385
2386 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2387 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2388 opnum, type);
2389 return x;
2390 }
2391
2392 return NULL_RTX;
2393}
2394\f
a6f12d7c
RK		 2395/* REF is an alignable memory location. Place an aligned SImode
2396 reference into *PALIGNED_MEM and the number of bits to shift into
96043e7e
RH		 2397 *PBITNUM. SCRATCH is a free register for use in reloading out
2398 of range stack slots. */
a6f12d7c
RK		 2399
2400void
4e46365b
RH		 2401get_aligned_mem (ref, paligned_mem, pbitnum)
2402 rtx ref;
a6f12d7c
RK		 2403 rtx *paligned_mem, *pbitnum;
2404{
2405 rtx base;
2406 HOST_WIDE_INT offset = 0;
2407
4e46365b
RH		 2408 if (GET_CODE (ref) != MEM)
2409 abort ();
a6f12d7c 2410
4e46365b
RH		 2411 if (reload_in_progress
2412 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
96043e7e 2413 {
4e46365b
RH		 2414 base = find_replacement (&XEXP (ref, 0));
2415
2416 if (! memory_address_p (GET_MODE (ref), base))
2417 abort ();
96043e7e 2418 }
a6f12d7c 2419 else
96043e7e 2420 {
96043e7e
RH		 2421 base = XEXP (ref, 0);
2422 }
a6f12d7c
RK		 2423
2424 if (GET_CODE (base) == PLUS)
2425 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2426
e7dfe4bb
RH		 2427 *paligned_mem
2428 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
a6f12d7c 2429
30102605
RH		 2430 if (WORDS_BIG_ENDIAN)
2431 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2432 + (offset & 3) * 8));
2433 else
2434 *pbitnum = GEN_INT ((offset & 3) * 8);
a6f12d7c
RK		 2435}
2436
adb18b68
RK		 2437/* Similar, but just get the address. Handle the two reload cases.
2438 Add EXTRA_OFFSET to the address we return. */
a6f12d7c
RK		 2439
2440rtx
adb18b68 2441get_unaligned_address (ref, extra_offset)
a6f12d7c 2442 rtx ref;
adb18b68 2443 int extra_offset;
a6f12d7c
RK		 2444{
2445 rtx base;
2446 HOST_WIDE_INT offset = 0;
2447
4e46365b
RH		 2448 if (GET_CODE (ref) != MEM)
2449 abort ();
a6f12d7c 2450
4e46365b
RH		 2451 if (reload_in_progress
2452 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
96043e7e 2453 {
96043e7e 2454 base = find_replacement (&XEXP (ref, 0));
4e46365b
RH		 2455
2456 if (! memory_address_p (GET_MODE (ref), base))
2457 abort ();
96043e7e 2458 }
a6f12d7c 2459 else
96043e7e 2460 {
96043e7e
RH		 2461 base = XEXP (ref, 0);
2462 }
a6f12d7c
RK		 2463
2464 if (GET_CODE (base) == PLUS)
2465 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2466
adb18b68 2467 return plus_constant (base, offset + extra_offset);
a6f12d7c 2468}
3611aef0 2469
551cc6fd
RH		 2470/* On the Alpha, all (non-symbolic) constants except zero go into
2471 a floating-point register via memory. Note that we cannot
2472 return anything that is not a subset of CLASS, and that some
2473 symbolic constants cannot be dropped to memory. */
2474
2475enum reg_class
2476alpha_preferred_reload_class(x, class)
2477 rtx x;
2478 enum reg_class class;
2479{
2480 /* Zero is present in any register class. */
2481 if (x == CONST0_RTX (GET_MODE (x)))
2482 return class;
2483
2484 /* These sorts of constants we can easily drop to memory. */
2485 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2486 {
2487 if (class == FLOAT_REGS)
2488 return NO_REGS;
2489 if (class == ALL_REGS)
2490 return GENERAL_REGS;
2491 return class;
2492 }
2493
2494 /* All other kinds of constants should not (and in the case of HIGH
2495 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2496 secondary reload. */
2497 if (CONSTANT_P (x))
2498 return (class == ALL_REGS ? GENERAL_REGS : class);
2499
2500 return class;
2501}
2502
3611aef0
RH		 2503/* Loading and storing HImode or QImode values to and from memory
2504 usually requires a scratch register. The exceptions are loading
2505 QImode and HImode from an aligned address to a general register
2506 unless byte instructions are permitted.
2507
2508 We also cannot load an unaligned address or a paradoxical SUBREG
2509 into an FP register.
2510
2511 We also cannot do integral arithmetic into FP regs, as might result
2512 from register elimination into a DImode fp register. */
2513
2514enum reg_class
2515secondary_reload_class (class, mode, x, in)
2516 enum reg_class class;
2517 enum machine_mode mode;
2518 rtx x;
2519 int in;
2520{
41bd3d41 2521 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
35a414df 2522 {
41bd3d41
RH		 2523 if (GET_CODE (x) == MEM
2524 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2525 || (GET_CODE (x) == SUBREG
2526 && (GET_CODE (SUBREG_REG (x)) == MEM
2527 || (GET_CODE (SUBREG_REG (x)) == REG
2528 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
35a414df
RH		 2529 {
2530 if (!in || !aligned_memory_operand(x, mode))
2531 return GENERAL_REGS;
2532 }
2533 }
3611aef0
RH		 2534
2535 if (class == FLOAT_REGS)
2536 {
2537 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2538 return GENERAL_REGS;
2539
2540 if (GET_CODE (x) == SUBREG
2541 && (GET_MODE_SIZE (GET_MODE (x))
2542 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2543 return GENERAL_REGS;
2544
1eb356b9
RH		 2545 if (in && INTEGRAL_MODE_P (mode)
2546 && ! (memory_operand (x, mode) || x == const0_rtx))
3611aef0
RH		 2547 return GENERAL_REGS;
2548 }
2549
2550 return NO_REGS;
2551}
a6f12d7c
RK		 2552\f
2553/* Subfunction of the following function. Update the flags of any MEM
2554 found in part of X. */
2555
2556static void
80db34d8 2557alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
a6f12d7c 2558 rtx x;
80db34d8 2559 int in_struct_p, volatile_p, unchanging_p;
a6f12d7c
RK		 2560{
2561 int i;
2562
2563 switch (GET_CODE (x))
2564 {
2565 case SEQUENCE:
2f937369
DM		 2566 abort ();
2567
a6f12d7c
RK		 2568 case PARALLEL:
2569 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2570 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
80db34d8 2571 unchanging_p);
a6f12d7c
RK		 2572 break;
2573
2574 case INSN:
2575 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
80db34d8 2576 unchanging_p);
a6f12d7c
RK		 2577 break;
2578
2579 case SET:
2580 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
80db34d8 2581 unchanging_p);
a6f12d7c 2582 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
80db34d8 2583 unchanging_p);
a6f12d7c
RK		 2584 break;
2585
2586 case MEM:
2587 MEM_IN_STRUCT_P (x) = in_struct_p;
2588 MEM_VOLATILE_P (x) = volatile_p;
2589 RTX_UNCHANGING_P (x) = unchanging_p;
80db34d8
RH		 2590 /* Sadly, we cannot use alias sets because the extra aliasing
2591 produced by the AND interferes. Given that two-byte quantities
2592 are the only thing we would be able to differentiate anyway,
2593 there does not seem to be any point in convoluting the early
2594 out of the alias check. */
a6f12d7c 2595 break;
1d300e19
KG		 2596
2597 default:
2598 break;
a6f12d7c
RK		 2599 }
2600}
2601
2f937369
DM		 2602/* Given INSN, which is an INSN list or the PATTERN of a single insn
2603 generated to perform a memory operation, look for any MEMs in either
2604 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2605 volatile flags from REF into each of the MEMs found. If REF is not
2606 a MEM, don't do anything. */
a6f12d7c
RK		 2607
2608void
2609alpha_set_memflags (insn, ref)
2610 rtx insn;
2611 rtx ref;
2612{
80db34d8 2613 int in_struct_p, volatile_p, unchanging_p;
3873d24b
RH		 2614
2615 if (GET_CODE (ref) != MEM)
a6f12d7c
RK		 2616 return;
2617
3873d24b
RH		 2618 in_struct_p = MEM_IN_STRUCT_P (ref);
2619 volatile_p = MEM_VOLATILE_P (ref);
2620 unchanging_p = RTX_UNCHANGING_P (ref);
3873d24b
RH		 2621
2622 /* This is only called from alpha.md, after having had something
2623 generated from one of the insn patterns. So if everything is
2624 zero, the pattern is already up-to-date. */
80db34d8 2625 if (! in_struct_p && ! volatile_p && ! unchanging_p)
3873d24b
RH		 2626 return;
2627
80db34d8 2628 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
a6f12d7c
RK		 2629}
2630\f
2631/* Try to output insns to set TARGET equal to the constant C if it can be
fd94addf
RK		 2632 done in less than N insns. Do all computations in MODE. Returns the place
2633 where the output has been placed if it can be done and the insns have been
2634 emitted. If it would take more than N insns, zero is returned and no
2635 insns and emitted. */
a6f12d7c 2636
fd94addf
RK		 2637rtx
2638alpha_emit_set_const (target, mode, c, n)
a6f12d7c 2639 rtx target;
fd94addf 2640 enum machine_mode mode;
a6f12d7c
RK		 2641 HOST_WIDE_INT c;
2642 int n;
9102cd1f 2643{
b76b08ef
RK		 2644 rtx result = 0;
2645 rtx orig_target = target;
9102cd1f
RK		 2646 int i;
2647
b76b08ef
RK		 2648 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2649 can't load this constant in one insn, do this in DImode. */
2650 if (no_new_pseudos && mode == SImode
2651 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2652 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2653 {
2654 target = gen_lowpart (DImode, target);
2655 mode = DImode;
2656 }
2657
285a5742 2658 /* Try 1 insn, then 2, then up to N. */
1ef9531b
RH		 2659 for (i = 1; i <= n; i++)
2660 {
2661 result = alpha_emit_set_const_1 (target, mode, c, i);
2662 if (result)
2663 {
2664 rtx insn = get_last_insn ();
2665 rtx set = single_set (insn);
2666 if (! CONSTANT_P (SET_SRC (set)))
2667 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2668 break;
2669 }
2670 }
9102cd1f 2671
b76b08ef
RK		 2672 /* Allow for the case where we changed the mode of TARGET. */
2673 if (result == target)
2674 result = orig_target;
2675
2676 return result;
9102cd1f
RK		 2677}
2678
2679/* Internal routine for the above to check for N or below insns. */
2680
2681static rtx
2682alpha_emit_set_const_1 (target, mode, c, n)
2683 rtx target;
2684 enum machine_mode mode;
2685 HOST_WIDE_INT c;
2686 int n;
a6f12d7c 2687{
20a4db98 2688 HOST_WIDE_INT new;
a6f12d7c 2689 int i, bits;
fd94addf
RK		 2690 /* Use a pseudo if highly optimizing and still generating RTL. */
2691 rtx subtarget
b76b08ef 2692 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
b83b7fa3 2693 rtx temp, insn;
a6f12d7c 2694
a6f12d7c
RK		 2695 /* If this is a sign-extended 32-bit constant, we can do this in at most
2696 three insns, so do it if we have enough insns left. We always have
285a5742 2697 a sign-extended 32-bit constant when compiling on a narrow machine. */
a6f12d7c 2698
858e4e8c
RH		 2699 if (HOST_BITS_PER_WIDE_INT != 64
2700 || c >> 31 == -1 || c >> 31 == 0)
a6f12d7c 2701 {
20a4db98 2702 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
a6f12d7c 2703 HOST_WIDE_INT tmp1 = c - low;
20a4db98 2704 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
a6f12d7c
RK		 2705 HOST_WIDE_INT extra = 0;
2706
ab034cfc
RK		 2707 /* If HIGH will be interpreted as negative but the constant is
2708 positive, we must adjust it to do two ldha insns. */
2709
2710 if ((high & 0x8000) != 0 && c >= 0)
a6f12d7c
RK		 2711 {
2712 extra = 0x4000;
2713 tmp1 -= 0x40000000;
2714 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2715 }
2716
2717 if (c == low || (low == 0 && extra == 0))
858e4e8c
RH		 2718 {
2719 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2720 but that meant that we can't handle INT_MIN on 32-bit machines
2721 (like NT/Alpha), because we recurse indefinitely through
2722 emit_move_insn to gen_movdi. So instead, since we know exactly
2723 what we want, create it explicitly. */
2724
2725 if (target == NULL)
2726 target = gen_reg_rtx (mode);
38a448ca 2727 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
858e4e8c
RH		 2728 return target;
2729 }
9102cd1f 2730 else if (n >= 2 + (extra != 0))
a6f12d7c 2731 {
20a4db98 2732 temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode);
fd94addf 2733
b83b7fa3
RH		 2734 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2735 This means that if we go through expand_binop, we'll try to
2736 generate extensions, etc, which will require new pseudos, which
2737 will fail during some split phases. The SImode add patterns
2738 still exist, but are not named. So build the insns by hand. */
2739
a6f12d7c 2740 if (extra != 0)
b83b7fa3
RH		 2741 {
2742 if (! subtarget)
2743 subtarget = gen_reg_rtx (mode);
2744 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2745 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2746 emit_insn (insn);
1ef9531b 2747 temp = subtarget;
b83b7fa3 2748 }
a6f12d7c 2749
b83b7fa3
RH		 2750 if (target == NULL)
2751 target = gen_reg_rtx (mode);
2752 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2753 insn = gen_rtx_SET (VOIDmode, target, insn);
2754 emit_insn (insn);
2755 return target;
a6f12d7c
RK		 2756 }
2757 }
2758
0af3ee30 2759 /* If we couldn't do it that way, try some other methods. But if we have
f444f304
RK		 2760 no instructions left, don't bother. Likewise, if this is SImode and
2761 we can't make pseudos, we can't do anything since the expand_binop
2762 and expand_unop calls will widen and try to make pseudos. */
a6f12d7c 2763
b76b08ef 2764 if (n == 1 || (mode == SImode && no_new_pseudos))
a6f12d7c
RK		 2765 return 0;
2766
0af3ee30 2767 /* Next, see if we can load a related constant and then shift and possibly
a6f12d7c
RK		 2768 negate it to get the constant we want. Try this once each increasing
2769 numbers of insns. */
2770
2771 for (i = 1; i < n; i++)
2772 {
20a4db98
RH		 2773 /* First, see if minus some low bits, we've an easy load of
2774 high bits. */
2775
2776 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2777 if (new != 0
2778 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2779 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2780 target, 0, OPTAB_WIDEN);
2781
2782 /* Next try complementing. */
fd94addf
RK		 2783 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2784 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
a6f12d7c 2785
fd94addf 2786 /* Next try to form a constant and do a left shift. We can do this
a6f12d7c
RK		 2787 if some low-order bits are zero; the exact_log2 call below tells
2788 us that information. The bits we are shifting out could be any
2789 value, but here we'll just try the 0- and sign-extended forms of
2790 the constant. To try to increase the chance of having the same
2791 constant in more than one insn, start at the highest number of
2792 bits to shift, but try all possibilities in case a ZAPNOT will
2793 be useful. */
2794
2795 if ((bits = exact_log2 (c & - c)) > 0)
2796 for (; bits > 0; bits--)
0af3ee30 2797 if ((temp = (alpha_emit_set_const
20a4db98 2798 (subtarget, mode, c >> bits, i))) != 0
fd94addf
RK		 2799 || ((temp = (alpha_emit_set_const
2800 (subtarget, mode,
2801 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2802 != 0))
2803 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2804 target, 0, OPTAB_WIDEN);
a6f12d7c
RK		 2805
2806 /* Now try high-order zero bits. Here we try the shifted-in bits as
57cfde96
RK		 2807 all zero and all ones. Be careful to avoid shifting outside the
2808 mode and to avoid shifting outside the host wide int size. */
858e4e8c
RH		 2809 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2810 confuse the recursive call and set all of the high 32 bits. */
a6f12d7c 2811
57cfde96 2812 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
858e4e8c 2813 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
a6f12d7c 2814 for (; bits > 0; bits--)
fd94addf
RK		 2815 if ((temp = alpha_emit_set_const (subtarget, mode,
2816 c << bits, i)) != 0
2817 || ((temp = (alpha_emit_set_const
2818 (subtarget, mode,
2819 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2820 i)))
2821 != 0))
2822 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
57cfde96 2823 target, 1, OPTAB_WIDEN);
a6f12d7c
RK		 2824
2825 /* Now try high-order 1 bits. We get that with a sign-extension.
57cfde96 2826 But one bit isn't enough here. Be careful to avoid shifting outside
285a5742 2827 the mode and to avoid shifting outside the host wide int size. */
30102605 2828
57cfde96
RK		 2829 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2830 - floor_log2 (~ c) - 2)) > 0)
a6f12d7c 2831 for (; bits > 0; bits--)
fd94addf
RK		 2832 if ((temp = alpha_emit_set_const (subtarget, mode,
2833 c << bits, i)) != 0
2834 || ((temp = (alpha_emit_set_const
2835 (subtarget, mode,
2836 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2837 i)))
2838 != 0))
2839 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2840 target, 0, OPTAB_WIDEN);
a6f12d7c
RK		 2841 }
2842
20a4db98
RH		 2843#if HOST_BITS_PER_WIDE_INT == 64
2844 /* Finally, see if can load a value into the target that is the same as the
2845 constant except that all bytes that are 0 are changed to be 0xff. If we
2846 can, then we can do a ZAPNOT to obtain the desired constant. */
2847
2848 new = c;
2849 for (i = 0; i < 64; i += 8)
2850 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2851 new |= (HOST_WIDE_INT) 0xff << i;
e68c380c 2852
20a4db98
RH		 2853 /* We are only called for SImode and DImode. If this is SImode, ensure that
2854 we are sign extended to a full word. */
2855
2856 if (mode == SImode)
2857 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2858
2859 if (new != c && new != -1
2860 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2861 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
e68c380c 2862 target, 0, OPTAB_WIDEN);
20a4db98 2863#endif
e68c380c 2864
a6f12d7c
RK		 2865 return 0;
2866}
758d2c0c 2867
97aea203
RK		 2868/* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2869 fall back to a straight forward decomposition. We do this to avoid
2870 exponential run times encountered when looking for longer sequences
2871 with alpha_emit_set_const. */
2872
2873rtx
3fe5612d 2874alpha_emit_set_long_const (target, c1, c2)
97aea203 2875 rtx target;
3fe5612d 2876 HOST_WIDE_INT c1, c2;
97aea203 2877{
97aea203 2878 HOST_WIDE_INT d1, d2, d3, d4;
97aea203
RK		 2879
2880 /* Decompose the entire word */
3fe5612d
RH		 2881#if HOST_BITS_PER_WIDE_INT >= 64
2882 if (c2 != -(c1 < 0))
2883 abort ();
2884 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2885 c1 -= d1;
2886 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2887 c1 = (c1 - d2) >> 32;
2888 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2889 c1 -= d3;
2890 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2891 if (c1 != d4)
2892 abort ();
2893#else
2894 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2895 c1 -= d1;
2896 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2897 if (c1 != d2)
2898 abort ();
2899 c2 += (d2 < 0);
2900 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2901 c2 -= d3;
2902 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2903 if (c2 != d4)
2904 abort ();
2905#endif
97aea203
RK		 2906
2907 /* Construct the high word */
3fe5612d
RH		 2908 if (d4)
2909 {
2910 emit_move_insn (target, GEN_INT (d4));
2911 if (d3)
2912 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2913 }
97aea203 2914 else
3fe5612d 2915 emit_move_insn (target, GEN_INT (d3));
97aea203
RK		 2916
2917 /* Shift it into place */
3fe5612d 2918 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
97aea203 2919
3fe5612d
RH		 2920 /* Add in the low bits. */
2921 if (d2)
2922 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2923 if (d1)
2924 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
97aea203 2925
3fe5612d 2926 return target;
97aea203 2927}
97aea203 2928
23296a36
RH		 2929/* Expand a move instruction; return true if all work is done.
2930 We don't handle non-bwx subword loads here. */
2931
2932bool
2933alpha_expand_mov (mode, operands)
2934 enum machine_mode mode;
2935 rtx *operands;
2936{
2937 /* If the output is not a register, the input must be. */
2938 if (GET_CODE (operands[0]) == MEM
2939 && ! reg_or_0_operand (operands[1], mode))
2940 operands[1] = force_reg (mode, operands[1]);
2941
551cc6fd 2942 /* Allow legitimize_address to perform some simplifications. */
d3e98208 2943 if (mode == Pmode && symbolic_operand (operands[1], mode))
1eb356b9 2944 {
bc8e8e97
RH		 2945 rtx tmp;
2946
2947 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2948 compiled at the end of compilation. In the meantime, someone can
2949 re-encode-section-info on some symbol changing it e.g. from global
2950 to local-not-small. If this happens, we'd have emitted a plain
2951 load rather than a high+losum load and not recognize the insn.
2952
2953 So if rtl inlining is in effect, we delay the global/not-global
2954 decision until rest_of_compilation by wrapping it in an
2955 UNSPEC_SYMBOL. */
2956 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2957 && rtx_equal_function_value_matters
2958 && global_symbolic_operand (operands[1], mode))
2959 {
2960 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2961 return true;
2962 }
2963
2964 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
551cc6fd 2965 if (tmp)
133d3133 2966 {
6f9b006d
RH		 2967 if (tmp == operands[0])
2968 return true;
551cc6fd 2969 operands[1] = tmp;
e2c9fb9b
RH		 2970 return false;
2971 }
1eb356b9
RH		 2972 }
2973
23296a36
RH		 2974 /* Early out for non-constants and valid constants. */
2975 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2976 return false;
2977
2978 /* Split large integers. */
2979 if (GET_CODE (operands[1]) == CONST_INT
2980 || GET_CODE (operands[1]) == CONST_DOUBLE)
2981 {
2982 HOST_WIDE_INT i0, i1;
666b0481 2983 rtx temp = NULL_RTX;
23296a36
RH		 2984
2985 if (GET_CODE (operands[1]) == CONST_INT)
2986 {
2987 i0 = INTVAL (operands[1]);
2988 i1 = -(i0 < 0);
2989 }
2990 else if (HOST_BITS_PER_WIDE_INT >= 64)
2991 {
2992 i0 = CONST_DOUBLE_LOW (operands[1]);
2993 i1 = -(i0 < 0);
2994 }
2995 else
2996 {
2997 i0 = CONST_DOUBLE_LOW (operands[1]);
2998 i1 = CONST_DOUBLE_HIGH (operands[1]);
2999 }
3000
3001 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
3002 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
3003
3004 if (!temp && TARGET_BUILD_CONSTANTS)
3005 temp = alpha_emit_set_long_const (operands[0], i0, i1);
3006
3007 if (temp)
3008 {
3009 if (rtx_equal_p (operands[0], temp))
3010 return true;
3011 operands[1] = temp;
3012 return false;
3013 }
3014 }
3015
3016 /* Otherwise we've nothing left but to drop the thing to memory. */
3017 operands[1] = force_const_mem (DImode, operands[1]);
3018 if (reload_in_progress)
3019 {
3020 emit_move_insn (operands[0], XEXP (operands[1], 0));
3021 operands[1] = copy_rtx (operands[1]);
3022 XEXP (operands[1], 0) = operands[0];
3023 }
3024 else
3025 operands[1] = validize_mem (operands[1]);
3026 return false;
3027}
3028
3029/* Expand a non-bwx QImode or HImode move instruction;
3030 return true if all work is done. */
3031
3032bool
3033alpha_expand_mov_nobwx (mode, operands)
3034 enum machine_mode mode;
3035 rtx *operands;
3036{
3037 /* If the output is not a register, the input must be. */
3038 if (GET_CODE (operands[0]) == MEM)
3039 operands[1] = force_reg (mode, operands[1]);
3040
3041 /* Handle four memory cases, unaligned and aligned for either the input
3042 or the output. The only case where we can be called during reload is
3043 for aligned loads; all other cases require temporaries. */
3044
3045 if (GET_CODE (operands[1]) == MEM
3046 || (GET_CODE (operands[1]) == SUBREG
3047 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3048 || (reload_in_progress && GET_CODE (operands[1]) == REG
3049 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3050 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3051 && GET_CODE (SUBREG_REG (operands[1])) == REG
3052 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3053 {
3054 if (aligned_memory_operand (operands[1], mode))
3055 {
3056 if (reload_in_progress)
3057 {
3058 emit_insn ((mode == QImode
3059 ? gen_reload_inqi_help
3060 : gen_reload_inhi_help)
3061 (operands[0], operands[1],
3062 gen_rtx_REG (SImode, REGNO (operands[0]))));
3063 }
3064 else
3065 {
3066 rtx aligned_mem, bitnum;
3067 rtx scratch = gen_reg_rtx (SImode);
3068
3069 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3070
3071 emit_insn ((mode == QImode
3072 ? gen_aligned_loadqi
3073 : gen_aligned_loadhi)
3074 (operands[0], aligned_mem, bitnum, scratch));
3075 }
3076 }
3077 else
3078 {
3079 /* Don't pass these as parameters since that makes the generated
3080 code depend on parameter evaluation order which will cause
3081 bootstrap failures. */
3082
3083 rtx temp1 = gen_reg_rtx (DImode);
3084 rtx temp2 = gen_reg_rtx (DImode);
3085 rtx seq = ((mode == QImode
3086 ? gen_unaligned_loadqi
3087 : gen_unaligned_loadhi)
3088 (operands[0], get_unaligned_address (operands[1], 0),
3089 temp1, temp2));
3090
3091 alpha_set_memflags (seq, operands[1]);
3092 emit_insn (seq);
3093 }
3094 return true;
3095 }
3096
3097 if (GET_CODE (operands[0]) == MEM
3098 || (GET_CODE (operands[0]) == SUBREG
3099 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3100 || (reload_in_progress && GET_CODE (operands[0]) == REG
3101 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3102 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3103 && GET_CODE (SUBREG_REG (operands[0])) == REG
3104 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3105 {
3106 if (aligned_memory_operand (operands[0], mode))
3107 {
3108 rtx aligned_mem, bitnum;
3109 rtx temp1 = gen_reg_rtx (SImode);
3110 rtx temp2 = gen_reg_rtx (SImode);
3111
3112 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3113
3114 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3115 temp1, temp2));
3116 }
3117 else
3118 {
3119 rtx temp1 = gen_reg_rtx (DImode);
3120 rtx temp2 = gen_reg_rtx (DImode);
3121 rtx temp3 = gen_reg_rtx (DImode);
3122 rtx seq = ((mode == QImode
3123 ? gen_unaligned_storeqi
3124 : gen_unaligned_storehi)
3125 (get_unaligned_address (operands[0], 0),
3126 operands[1], temp1, temp2, temp3));
3127
3128 alpha_set_memflags (seq, operands[0]);
3129 emit_insn (seq);
3130 }
3131 return true;
3132 }
3133
3134 return false;
3135}
3136
01b9e84e
RH		 3137/* Generate an unsigned DImode to FP conversion. This is the same code
3138 optabs would emit if we didn't have TFmode patterns.
3139
3140 For SFmode, this is the only construction I've found that can pass
3141 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3142 intermediates will work, because you'll get intermediate rounding
3143 that ruins the end result. Some of this could be fixed by turning
3144 on round-to-positive-infinity, but that requires diddling the fpsr,
3145 which kills performance. I tried turning this around and converting
3146 to a negative number, so that I could turn on /m, but either I did
3147 it wrong or there's something else cause I wound up with the exact
3148 same single-bit error. There is a branch-less form of this same code:
3149
3150 srl $16,1,$1
3151 and $16,1,$2
3152 cmplt $16,0,$3
3153 or $1,$2,$2
3154 cmovge $16,$16,$2
3155 itoft $3,$f10
3156 itoft $2,$f11
3157 cvtqs $f11,$f11
3158 adds $f11,$f11,$f0
3159 fcmoveq $f10,$f11,$f0
3160
3161 I'm not using it because it's the same number of instructions as
3162 this branch-full form, and it has more serialized long latency
3163 instructions on the critical path.
3164
3165 For DFmode, we can avoid rounding errors by breaking up the word
3166 into two pieces, converting them separately, and adding them back:
3167
3168 LC0: .long 0,0x5f800000
3169
3170 itoft $16,$f11
3171 lda $2,LC0
70994f30 3172 cmplt $16,0,$1
01b9e84e
RH		 3173 cpyse $f11,$f31,$f10
3174 cpyse $f31,$f11,$f11
3175 s4addq $1,$2,$1
3176 lds $f12,0($1)
3177 cvtqt $f10,$f10
3178 cvtqt $f11,$f11
3179 addt $f12,$f10,$f0
3180 addt $f0,$f11,$f0
3181
3182 This doesn't seem to be a clear-cut win over the optabs form.
3183 It probably all depends on the distribution of numbers being
3184 converted -- in the optabs form, all but high-bit-set has a
3185 much lower minimum execution time. */
3186
3187void
3188alpha_emit_floatuns (operands)
3189 rtx operands[2];
3190{
3191 rtx neglab, donelab, i0, i1, f0, in, out;
3192 enum machine_mode mode;
3193
3194 out = operands[0];
57014cb9 3195 in = force_reg (DImode, operands[1]);
01b9e84e
RH		 3196 mode = GET_MODE (out);
3197 neglab = gen_label_rtx ();
3198 donelab = gen_label_rtx ();
3199 i0 = gen_reg_rtx (DImode);
3200 i1 = gen_reg_rtx (DImode);
3201 f0 = gen_reg_rtx (mode);
3202
d43e0b7d 3203 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
01b9e84e
RH		 3204
3205 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3206 emit_jump_insn (gen_jump (donelab));
70994f30 3207 emit_barrier ();
01b9e84e
RH		 3208
3209 emit_label (neglab);
3210
3211 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3212 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3213 emit_insn (gen_iordi3 (i0, i0, i1));
3214 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3215 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3216
3217 emit_label (donelab);
3218}
3219
f283421d
RH		 3220/* Generate the comparison for a conditional branch. */
3221
3222rtx
3223alpha_emit_conditional_branch (code)
3224 enum rtx_code code;
3225{
3226 enum rtx_code cmp_code, branch_code;
3227 enum machine_mode cmp_mode, branch_mode = VOIDmode;
6db21c7f 3228 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
f283421d
RH		 3229 rtx tem;
3230
5495cc55
RH		 3231 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3232 {
3233 if (! TARGET_HAS_XFLOATING_LIBS)
3234 abort ();
3235
3236 /* X_floating library comparison functions return
3237 -1 unordered
3238 0 false
3239 1 true
3240 Convert the compare against the raw return value. */
3241
b8de5050
RH		 3242 switch (code)
3243 {
3244 case UNORDERED:
3245 cmp_code = EQ;
3246 code = LT;
3247 break;
3248 case ORDERED:
3249 cmp_code = EQ;
3250 code = GE;
3251 break;
3252 case NE:
3253 cmp_code = NE;
3254 code = NE;
3255 break;
3256 default:
3257 cmp_code = code;
6b7d1a34 3258 code = GT;
b8de5050
RH		 3259 break;
3260 }
9e495700
RH		 3261
3262 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
5495cc55
RH		 3263 op1 = const0_rtx;
3264 alpha_compare.fp_p = 0;
5495cc55
RH		 3265 }
3266
f283421d
RH		 3267 /* The general case: fold the comparison code to the types of compares
3268 that we have, choosing the branch as necessary. */
3269 switch (code)
3270 {
3271 case EQ: case LE: case LT: case LEU: case LTU:
1eb8759b 3272 case UNORDERED:
f283421d
RH		 3273 /* We have these compares: */
3274 cmp_code = code, branch_code = NE;
3275 break;
3276
3277 case NE:
1eb8759b 3278 case ORDERED:
285a5742 3279 /* These must be reversed. */
1eb8759b 3280 cmp_code = reverse_condition (code), branch_code = EQ;
f283421d
RH		 3281 break;
3282
3283 case GE: case GT: case GEU: case GTU:
3284 /* For FP, we swap them, for INT, we reverse them. */
6db21c7f 3285 if (alpha_compare.fp_p)
f283421d
RH		 3286 {
3287 cmp_code = swap_condition (code);
3288 branch_code = NE;
3289 tem = op0, op0 = op1, op1 = tem;
3290 }
3291 else
3292 {
3293 cmp_code = reverse_condition (code);
3294 branch_code = EQ;
3295 }
3296 break;
3297
3298 default:
3299 abort ();
3300 }
3301
6db21c7f 3302 if (alpha_compare.fp_p)
f283421d
RH		 3303 {
3304 cmp_mode = DFmode;
de6c5979 3305 if (flag_unsafe_math_optimizations)
f283421d
RH		 3306 {
3307 /* When we are not as concerned about non-finite values, and we
3308 are comparing against zero, we can branch directly. */
3309 if (op1 == CONST0_RTX (DFmode))
3310 cmp_code = NIL, branch_code = code;
3311 else if (op0 == CONST0_RTX (DFmode))
3312 {
3313 /* Undo the swap we probably did just above. */
3314 tem = op0, op0 = op1, op1 = tem;
b771b6b4
RH		 3315 branch_code = swap_condition (cmp_code);
3316 cmp_code = NIL;
f283421d
RH		 3317 }
3318 }
3319 else
3320 {
27d30956 3321 /* ??? We mark the branch mode to be CCmode to prevent the
f283421d
RH		 3322 compare and branch from being combined, since the compare
3323 insn follows IEEE rules that the branch does not. */
3324 branch_mode = CCmode;
3325 }
3326 }
3327 else
3328 {
3329 cmp_mode = DImode;
3330
3331 /* The following optimizations are only for signed compares. */
3332 if (code != LEU && code != LTU && code != GEU && code != GTU)
3333 {
3334 /* Whee. Compare and branch against 0 directly. */
3335 if (op1 == const0_rtx)
3336 cmp_code = NIL, branch_code = code;
3337
3338 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3339 bypass between logicals and br/cmov on EV5. But we don't want to
3340 force valid immediate constants into registers needlessly. */
3341 else if (GET_CODE (op1) == CONST_INT)
3342 {
3343 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3344
3345 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3346 && (CONST_OK_FOR_LETTER_P (n, 'K')
3347 || CONST_OK_FOR_LETTER_P (n, 'L')))
3348 {
3349 cmp_code = PLUS, branch_code = code;
3350 op1 = GEN_INT (n);
3351 }
3352 }
3353 }
f283421d 3354
9e495700
RH		 3355 if (!reg_or_0_operand (op0, DImode))
3356 op0 = force_reg (DImode, op0);
3357 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3358 op1 = force_reg (DImode, op1);
3359 }
f283421d
RH		 3360
3361 /* Emit an initial compare instruction, if necessary. */
3362 tem = op0;
3363 if (cmp_code != NIL)
3364 {
3365 tem = gen_reg_rtx (cmp_mode);
3366 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3367 }
3368
6db21c7f
RH		 3369 /* Zero the operands. */
3370 memset (&alpha_compare, 0, sizeof (alpha_compare));
3371
f283421d
RH		 3372 /* Return the branch comparison. */
3373 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3374}
3375
9e495700
RH		 3376/* Certain simplifications can be done to make invalid setcc operations
3377 valid. Return the final comparison, or NULL if we can't work. */
3378
3379rtx
3380alpha_emit_setcc (code)
3381 enum rtx_code code;
3382{
3383 enum rtx_code cmp_code;
3384 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3385 int fp_p = alpha_compare.fp_p;
3386 rtx tmp;
3387
3388 /* Zero the operands. */
3389 memset (&alpha_compare, 0, sizeof (alpha_compare));
3390
3391 if (fp_p && GET_MODE (op0) == TFmode)
3392 {
3393 if (! TARGET_HAS_XFLOATING_LIBS)
3394 abort ();
3395
3396 /* X_floating library comparison functions return
3397 -1 unordered
3398 0 false
3399 1 true
3400 Convert the compare against the raw return value. */
3401
3402 if (code == UNORDERED || code == ORDERED)
3403 cmp_code = EQ;
3404 else
3405 cmp_code = code;
3406
3407 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3408 op1 = const0_rtx;
3409 fp_p = 0;
3410
3411 if (code == UNORDERED)
3412 code = LT;
3413 else if (code == ORDERED)
3414 code = GE;
3415 else
3416 code = GT;
3417 }
3418
3419 if (fp_p && !TARGET_FIX)
3420 return NULL_RTX;
3421
3422 /* The general case: fold the comparison code to the types of compares
3423 that we have, choosing the branch as necessary. */
3424
3425 cmp_code = NIL;
3426 switch (code)
3427 {
3428 case EQ: case LE: case LT: case LEU: case LTU:
3429 case UNORDERED:
3430 /* We have these compares. */
3431 if (fp_p)
3432 cmp_code = code, code = NE;
3433 break;
3434
3435 case NE:
3436 if (!fp_p && op1 == const0_rtx)
3437 break;
3438 /* FALLTHRU */
3439
3440 case ORDERED:
3441 cmp_code = reverse_condition (code);
3442 code = EQ;
3443 break;
3444
3445 case GE: case GT: case GEU: case GTU:
56f19d92 3446 /* These normally need swapping, but for integer zero we have
c74fa144
RH		 3447 special patterns that recognize swapped operands. */
3448 if (!fp_p && op1 == const0_rtx)
3449 break;
9e495700
RH		 3450 code = swap_condition (code);
3451 if (fp_p)
3452 cmp_code = code, code = NE;
3453 tmp = op0, op0 = op1, op1 = tmp;
3454 break;
3455
3456 default:
3457 abort ();
3458 }
3459
3460 if (!fp_p)
3461 {
c74fa144 3462 if (!register_operand (op0, DImode))
9e495700
RH		 3463 op0 = force_reg (DImode, op0);
3464 if (!reg_or_8bit_operand (op1, DImode))
3465 op1 = force_reg (DImode, op1);
3466 }
3467
3468 /* Emit an initial compare instruction, if necessary. */
3469 if (cmp_code != NIL)
3470 {
3471 enum machine_mode mode = fp_p ? DFmode : DImode;
3472
3473 tmp = gen_reg_rtx (mode);
3474 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3475 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3476
3477 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3478 op1 = const0_rtx;
3479 }
3480
3481 /* Return the setcc comparison. */
3482 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3483}
3484
f283421d 3485
758d2c0c
RK		 3486/* Rewrite a comparison against zero CMP of the form
3487 (CODE (cc0) (const_int 0)) so it can be written validly in
3488 a conditional move (if_then_else CMP ...).
825dda42 3489 If both of the operands that set cc0 are nonzero we must emit
758d2c0c 3490 an insn to perform the compare (it can't be done within
285a5742 3491 the conditional move). */
758d2c0c
RK		 3492rtx
3493alpha_emit_conditional_move (cmp, mode)
3494 rtx cmp;
3495 enum machine_mode mode;
3496{
1ad2a62d 3497 enum rtx_code code = GET_CODE (cmp);
89b7c471 3498 enum rtx_code cmov_code = NE;
6db21c7f
RH		 3499 rtx op0 = alpha_compare.op0;
3500 rtx op1 = alpha_compare.op1;
3501 int fp_p = alpha_compare.fp_p;
1ad2a62d
RK		 3502 enum machine_mode cmp_mode
3503 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
6db21c7f 3504 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
f283421d 3505 enum machine_mode cmov_mode = VOIDmode;
de6c5979 3506 int local_fast_math = flag_unsafe_math_optimizations;
1ad2a62d 3507 rtx tem;
758d2c0c 3508
6db21c7f
RH		 3509 /* Zero the operands. */
3510 memset (&alpha_compare, 0, sizeof (alpha_compare));
3511
3512 if (fp_p != FLOAT_MODE_P (mode))
09fe1c49
RH		 3513 {
3514 enum rtx_code cmp_code;
3515
3516 if (! TARGET_FIX)
3517 return 0;
3518
3519 /* If we have fp<->int register move instructions, do a cmov by
3520 performing the comparison in fp registers, and move the
825dda42 3521 zero/nonzero value to integer registers, where we can then
09fe1c49
RH		 3522 use a normal cmov, or vice-versa. */
3523
3524 switch (code)
3525 {
3526 case EQ: case LE: case LT: case LEU: case LTU:
3527 /* We have these compares. */
3528 cmp_code = code, code = NE;
3529 break;
3530
3531 case NE:
3532 /* This must be reversed. */
3533 cmp_code = EQ, code = EQ;
3534 break;
3535
3536 case GE: case GT: case GEU: case GTU:
56f19d92
RH		 3537 /* These normally need swapping, but for integer zero we have
3538 special patterns that recognize swapped operands. */
3539 if (!fp_p && op1 == const0_rtx)
c53f9f5b
RH		 3540 cmp_code = code, code = NE;
3541 else
3542 {
3543 cmp_code = swap_condition (code);
3544 code = NE;
3545 tem = op0, op0 = op1, op1 = tem;
3546 }
09fe1c49
RH		 3547 break;
3548
3549 default:
3550 abort ();
3551 }
3552
3553 tem = gen_reg_rtx (cmp_op_mode);
3554 emit_insn (gen_rtx_SET (VOIDmode, tem,
3555 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3556 op0, op1)));
3557
3558 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3559 op0 = gen_lowpart (cmp_op_mode, tem);
3560 op1 = CONST0_RTX (cmp_op_mode);
3561 fp_p = !fp_p;
3562 local_fast_math = 1;
3563 }
758d2c0c
RK		 3564
3565 /* We may be able to use a conditional move directly.
285a5742 3566 This avoids emitting spurious compares. */
01b9e84e 3567 if (signed_comparison_operator (cmp, VOIDmode)
09fe1c49 3568 && (!fp_p || local_fast_math)
1ad2a62d 3569 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
38a448ca 3570 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
758d2c0c 3571
000ca373 3572 /* We can't put the comparison inside the conditional move;
758d2c0c 3573 emit a compare instruction and put that inside the
1ad2a62d
RK		 3574 conditional move. Make sure we emit only comparisons we have;
3575 swap or reverse as necessary. */
758d2c0c 3576
000ca373
RH		 3577 if (no_new_pseudos)
3578 return NULL_RTX;
3579
758d2c0c
RK		 3580 switch (code)
3581 {
1ad2a62d
RK		 3582 case EQ: case LE: case LT: case LEU: case LTU:
3583 /* We have these compares: */
758d2c0c 3584 break;
1ad2a62d 3585
758d2c0c 3586 case NE:
285a5742 3587 /* This must be reversed. */
1ad2a62d 3588 code = reverse_condition (code);
89b7c471 3589 cmov_code = EQ;
758d2c0c 3590 break;
1ad2a62d
RK		 3591
3592 case GE: case GT: case GEU: case GTU:
9e495700 3593 /* These must be swapped. */
c53f9f5b
RH		 3594 if (op1 != CONST0_RTX (cmp_mode))
3595 {
3596 code = swap_condition (code);
3597 tem = op0, op0 = op1, op1 = tem;
3598 }
758d2c0c 3599 break;
1ad2a62d 3600
758d2c0c 3601 default:
1ad2a62d 3602 abort ();
758d2c0c
RK		 3603 }
3604
9e495700
RH		 3605 if (!fp_p)
3606 {
3607 if (!reg_or_0_operand (op0, DImode))
3608 op0 = force_reg (DImode, op0);
3609 if (!reg_or_8bit_operand (op1, DImode))
3610 op1 = force_reg (DImode, op1);
3611 }
3612
68aed21b 3613 /* ??? We mark the branch mode to be CCmode to prevent the compare
f283421d
RH		 3614 and cmov from being combined, since the compare insn follows IEEE
3615 rules that the cmov does not. */
09fe1c49 3616 if (fp_p && !local_fast_math)
f283421d
RH		 3617 cmov_mode = CCmode;
3618
1ad2a62d 3619 tem = gen_reg_rtx (cmp_op_mode);
38a448ca 3620 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
f283421d 3621 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
758d2c0c 3622}
8f4773ea
RH		 3623
3624/* Simplify a conditional move of two constants into a setcc with
3625 arithmetic. This is done with a splitter since combine would
3626 just undo the work if done during code generation. It also catches
3627 cases we wouldn't have before cse. */
3628
3629int
3630alpha_split_conditional_move (code, dest, cond, t_rtx, f_rtx)
3631 enum rtx_code code;
3632 rtx dest, cond, t_rtx, f_rtx;
3633{
3634 HOST_WIDE_INT t, f, diff;
3635 enum machine_mode mode;
3636 rtx target, subtarget, tmp;
3637
3638 mode = GET_MODE (dest);
3639 t = INTVAL (t_rtx);
3640 f = INTVAL (f_rtx);
3641 diff = t - f;
3642
3643 if (((code == NE || code == EQ) && diff < 0)
3644 || (code == GE || code == GT))
3645 {
3646 code = reverse_condition (code);
3647 diff = t, t = f, f = diff;
3648 diff = t - f;
3649 }
3650
3651 subtarget = target = dest;
3652 if (mode != DImode)
3653 {
3654 target = gen_lowpart (DImode, dest);
3655 if (! no_new_pseudos)
3656 subtarget = gen_reg_rtx (DImode);
3657 else
3658 subtarget = target;
3659 }
a5376276
RH		 3660 /* Below, we must be careful to use copy_rtx on target and subtarget
3661 in intermediate insns, as they may be a subreg rtx, which may not
3662 be shared. */
8f4773ea
RH		 3663
3664 if (f == 0 && exact_log2 (diff) > 0
3665 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3666 viable over a longer latency cmove. On EV5, the E0 slot is a
285a5742 3667 scarce resource, and on EV4 shift has the same latency as a cmove. */
8f4773ea
RH		 3668 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3669 {
3670 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
a5376276 3671 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
8f4773ea 3672
a5376276
RH		 3673 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3674 GEN_INT (exact_log2 (t)));
8f4773ea
RH		 3675 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3676 }
3677 else if (f == 0 && t == -1)
3678 {
3679 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
a5376276 3680 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
8f4773ea 3681
a5376276 3682 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
8f4773ea
RH		 3683 }
3684 else if (diff == 1 || diff == 4 || diff == 8)
3685 {
3686 rtx add_op;
3687
3688 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
a5376276 3689 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
8f4773ea
RH		 3690
3691 if (diff == 1)
a5376276 3692 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
8f4773ea
RH		 3693 else
3694 {
3695 add_op = GEN_INT (f);
3696 if (sext_add_operand (add_op, mode))
3697 {
a5376276
RH		 3698 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3699 GEN_INT (diff));
8f4773ea
RH		 3700 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3701 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3702 }
3703 else
3704 return 0;
3705 }
3706 }
3707 else
3708 return 0;
3709
3710 return 1;
3711}
6c174fc0 3712\f
5495cc55
RH		 3713/* Look up the function X_floating library function name for the
3714 given operation. */
3715
3716static const char *
3717alpha_lookup_xfloating_lib_func (code)
3718 enum rtx_code code;
3719{
3720 struct xfloating_op
3721 {
8b60264b
KG		 3722 const enum rtx_code code;
3723 const char *const func;
5495cc55
RH		 3724 };
3725
3726 static const struct xfloating_op vms_xfloating_ops[] =
3727 {
3728 { PLUS, "OTS$ADD_X" },
3729 { MINUS, "OTS$SUB_X" },
3730 { MULT, "OTS$MUL_X" },
3731 { DIV, "OTS$DIV_X" },
3732 { EQ, "OTS$EQL_X" },
3733 { NE, "OTS$NEQ_X" },
3734 { LT, "OTS$LSS_X" },
3735 { LE, "OTS$LEQ_X" },
3736 { GT, "OTS$GTR_X" },
3737 { GE, "OTS$GEQ_X" },
3738 { FIX, "OTS$CVTXQ" },
3739 { FLOAT, "OTS$CVTQX" },
3740 { UNSIGNED_FLOAT, "OTS$CVTQUX" },
3741 { FLOAT_EXTEND, "OTS$CVT_FLOAT_T_X" },
3742 { FLOAT_TRUNCATE, "OTS$CVT_FLOAT_X_T" },
3743 };
3744
3745 static const struct xfloating_op osf_xfloating_ops[] =
3746 {
3747 { PLUS, "_OtsAddX" },
3748 { MINUS, "_OtsSubX" },
3749 { MULT, "_OtsMulX" },
3750 { DIV, "_OtsDivX" },
3751 { EQ, "_OtsEqlX" },
3752 { NE, "_OtsNeqX" },
3753 { LT, "_OtsLssX" },
3754 { LE, "_OtsLeqX" },
3755 { GT, "_OtsGtrX" },
3756 { GE, "_OtsGeqX" },
3757 { FIX, "_OtsCvtXQ" },
3758 { FLOAT, "_OtsCvtQX" },
3759 { UNSIGNED_FLOAT, "_OtsCvtQUX" },
3760 { FLOAT_EXTEND, "_OtsConvertFloatTX" },
3761 { FLOAT_TRUNCATE, "_OtsConvertFloatXT" },
3762 };
3763
3764 const struct xfloating_op *ops;
b6a1cbae 3765 const long n = ARRAY_SIZE (osf_xfloating_ops);
5495cc55
RH		 3766 long i;
3767
3768 /* How irritating. Nothing to key off for the table. Hardcode
3769 knowledge of the G_floating routines. */
3770 if (TARGET_FLOAT_VAX)
3771 {
be7b80f4 3772 if (TARGET_ABI_OPEN_VMS)
5495cc55
RH		 3773 {
3774 if (code == FLOAT_EXTEND)
3775 return "OTS$CVT_FLOAT_G_X";
3776 if (code == FLOAT_TRUNCATE)
3777 return "OTS$CVT_FLOAT_X_G";
3778 }
3779 else
3780 {
3781 if (code == FLOAT_EXTEND)
3782 return "_OtsConvertFloatGX";
3783 if (code == FLOAT_TRUNCATE)
3784 return "_OtsConvertFloatXG";
3785 }
3786 }
3787
be7b80f4 3788 if (TARGET_ABI_OPEN_VMS)
5495cc55
RH		 3789 ops = vms_xfloating_ops;
3790 else
3791 ops = osf_xfloating_ops;
3792
3793 for (i = 0; i < n; ++i)
3794 if (ops[i].code == code)
3795 return ops[i].func;
3796
3797 abort();
3798}
3799
3800/* Most X_floating operations take the rounding mode as an argument.
3801 Compute that here. */
3802
3803static int
3804alpha_compute_xfloating_mode_arg (code, round)
3805 enum rtx_code code;
3806 enum alpha_fp_rounding_mode round;
3807{
3808 int mode;
3809
3810 switch (round)
3811 {
3812 case ALPHA_FPRM_NORM:
3813 mode = 2;
3814 break;
3815 case ALPHA_FPRM_MINF:
3816 mode = 1;
3817 break;
3818 case ALPHA_FPRM_CHOP:
3819 mode = 0;
3820 break;
3821 case ALPHA_FPRM_DYN:
3822 mode = 4;
3823 break;
3824 default:
3825 abort ();
3826
3827 /* XXX For reference, round to +inf is mode = 3. */
3828 }
3829
3830 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3831 mode |= 0x10000;
3832
3833 return mode;
3834}
3835
3836/* Emit an X_floating library function call.
3837
3838 Note that these functions do not follow normal calling conventions:
3839 TFmode arguments are passed in two integer registers (as opposed to
3840 indirect); TFmode return values appear in R16+R17.
3841
3842 FUNC is the function name to call.
3843 TARGET is where the output belongs.
3844 OPERANDS are the inputs.
3845 NOPERANDS is the count of inputs.
3846 EQUIV is the expression equivalent for the function.
3847*/
3848
3849static void
3850alpha_emit_xfloating_libcall (func, target, operands, noperands, equiv)
3851 const char *func;
3852 rtx target;
3853 rtx operands[];
3854 int noperands;
3855 rtx equiv;
3856{
3857 rtx usage = NULL_RTX, tmp, reg;
3858 int regno = 16, i;
3859
3860 start_sequence ();
3861
3862 for (i = 0; i < noperands; ++i)
3863 {
3864 switch (GET_MODE (operands[i]))
3865 {
3866 case TFmode:
3867 reg = gen_rtx_REG (TFmode, regno);
3868 regno += 2;
3869 break;
3870
3871 case DFmode:
3872 reg = gen_rtx_REG (DFmode, regno + 32);
3873 regno += 1;
3874 break;
3875
3876 case VOIDmode:
3877 if (GET_CODE (operands[i]) != CONST_INT)
3878 abort ();
3879 /* FALLTHRU */
3880 case DImode:
3881 reg = gen_rtx_REG (DImode, regno);
3882 regno += 1;
3883 break;
3884
3885 default:
3886 abort ();
3887 }
3888
3889 emit_move_insn (reg, operands[i]);
3890 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3891 }
3892
3893 switch (GET_MODE (target))
3894 {
3895 case TFmode:
3896 reg = gen_rtx_REG (TFmode, 16);
3897 break;
3898 case DFmode:
3899 reg = gen_rtx_REG (DFmode, 32);
3900 break;
3901 case DImode:
3902 reg = gen_rtx_REG (DImode, 0);
3903 break;
3904 default:
3905 abort ();
3906 }
3907
c8d8ed65 3908 tmp = gen_rtx_MEM (QImode, gen_rtx_SYMBOL_REF (Pmode, (char *) func));
0499c2e4 3909 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
5495cc55
RH		 3910 const0_rtx, const0_rtx));
3911 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3912
3913 tmp = get_insns ();
3914 end_sequence ();
3915
3916 emit_libcall_block (tmp, target, reg, equiv);
3917}
3918
3919/* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3920
3921void
3922alpha_emit_xfloating_arith (code, operands)
3923 enum rtx_code code;
3924 rtx operands[];
3925{
3926 const char *func;
3927 int mode;
c77f46c6 3928 rtx out_operands[3];
5495cc55
RH		 3929
3930 func = alpha_lookup_xfloating_lib_func (code);
3931 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3932
c77f46c6
AO		 3933 out_operands[0] = operands[1];
3934 out_operands[1] = operands[2];
3935 out_operands[2] = GEN_INT (mode);
3936 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
5495cc55
RH		 3937 gen_rtx_fmt_ee (code, TFmode, operands[1],
3938 operands[2]));
3939}
3940
3941/* Emit an X_floating library function call for a comparison. */
3942
3943static rtx
3944alpha_emit_xfloating_compare (code, op0, op1)
3945 enum rtx_code code;
3946 rtx op0, op1;
3947{
3948 const char *func;
3949 rtx out, operands[2];
3950
3951 func = alpha_lookup_xfloating_lib_func (code);
3952
3953 operands[0] = op0;
3954 operands[1] = op1;
3955 out = gen_reg_rtx (DImode);
3956
b762a0ef
RH		 3957 /* ??? Strange mode for equiv because what's actually returned
3958 is -1,0,1, not a proper boolean value. */
3959 alpha_emit_xfloating_libcall (func, out, operands, 2,
3960 gen_rtx_fmt_ee (code, CCmode, op0, op1));
5495cc55
RH		 3961
3962 return out;
3963}
3964
3965/* Emit an X_floating library function call for a conversion. */
3966
3967void
3968alpha_emit_xfloating_cvt (code, operands)
3969 enum rtx_code code;
3970 rtx operands[];
3971{
3972 int noperands = 1, mode;
c77f46c6 3973 rtx out_operands[2];
5495cc55
RH		 3974 const char *func;
3975
3976 func = alpha_lookup_xfloating_lib_func (code);
3977
c77f46c6
AO		 3978 out_operands[0] = operands[1];
3979
5495cc55
RH		 3980 switch (code)
3981 {
3982 case FIX:
3983 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
c77f46c6 3984 out_operands[1] = GEN_INT (mode);
d6cde845 3985 noperands = 2;
5495cc55
RH		 3986 break;
3987 case FLOAT_TRUNCATE:
3988 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
c77f46c6 3989 out_operands[1] = GEN_INT (mode);
d6cde845 3990 noperands = 2;
5495cc55
RH		 3991 break;
3992 default:
3993 break;
3994 }
3995
c77f46c6 3996 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
5495cc55
RH		 3997 gen_rtx_fmt_e (code, GET_MODE (operands[0]),
3998 operands[1]));
3999}
628d74de 4000
f940c352
RH		 4001/* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
4002 OP[0] into OP[0,1]. Naturally, output operand ordering is
4003 little-endian. */
4004
628d74de
RH		 4005void
4006alpha_split_tfmode_pair (operands)
4007 rtx operands[4];
4008{
4009 if (GET_CODE (operands[1]) == REG)
4010 {
4011 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
4012 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
4013 }
4014 else if (GET_CODE (operands[1]) == MEM)
4015 {
f4ef873c
RK		 4016 operands[3] = adjust_address (operands[1], DImode, 8);
4017 operands[2] = adjust_address (operands[1], DImode, 0);
628d74de
RH		 4018 }
4019 else if (operands[1] == CONST0_RTX (TFmode))
4020 operands[2] = operands[3] = const0_rtx;
4021 else
4022 abort ();
4023
4024 if (GET_CODE (operands[0]) == REG)
4025 {
4026 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
4027 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
4028 }
4029 else if (GET_CODE (operands[0]) == MEM)
4030 {
f4ef873c
RK		 4031 operands[1] = adjust_address (operands[0], DImode, 8);
4032 operands[0] = adjust_address (operands[0], DImode, 0);
628d74de
RH		 4033 }
4034 else
4035 abort ();
4036}
f940c352
RH		 4037
4038/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4039 op2 is a register containing the sign bit, operation is the
4040 logical operation to be performed. */
4041
4042void
4043alpha_split_tfmode_frobsign (operands, operation)
4044 rtx operands[3];
4045 rtx (*operation) PARAMS ((rtx, rtx, rtx));
4046{
4047 rtx high_bit = operands[2];
4048 rtx scratch;
4049 int move;
4050
4051 alpha_split_tfmode_pair (operands);
4052
825dda42 4053 /* Detect three flavors of operand overlap. */
f940c352
RH		 4054 move = 1;
4055 if (rtx_equal_p (operands[0], operands[2]))
4056 move = 0;
4057 else if (rtx_equal_p (operands[1], operands[2]))
4058 {
4059 if (rtx_equal_p (operands[0], high_bit))
4060 move = 2;
4061 else
4062 move = -1;
4063 }
4064
4065 if (move < 0)
4066 emit_move_insn (operands[0], operands[2]);
4067
4068 /* ??? If the destination overlaps both source tf and high_bit, then
4069 assume source tf is dead in its entirety and use the other half
4070 for a scratch register. Otherwise "scratch" is just the proper
4071 destination register. */
4072 scratch = operands[move < 2 ? 1 : 3];
4073
4074 emit_insn ((*operation) (scratch, high_bit, operands[3]));
4075
4076 if (move > 0)
4077 {
4078 emit_move_insn (operands[0], operands[2]);
4079 if (move > 1)
4080 emit_move_insn (operands[1], scratch);
4081 }
4082}
5495cc55 4083\f
6c174fc0
RH		 4084/* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4085 unaligned data:
4086
4087 unsigned: signed:
4088 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4089 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4090 lda r3,X(r11) lda r3,X+2(r11)
4091 extwl r1,r3,r1 extql r1,r3,r1
4092 extwh r2,r3,r2 extqh r2,r3,r2
4093 or r1.r2.r1 or r1,r2,r1
4094 sra r1,48,r1
4095
4096 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4097 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4098 lda r3,X(r11) lda r3,X(r11)
4099 extll r1,r3,r1 extll r1,r3,r1
4100 extlh r2,r3,r2 extlh r2,r3,r2
4101 or r1.r2.r1 addl r1,r2,r1
4102
4103 quad: ldq_u r1,X(r11)
4104 ldq_u r2,X+7(r11)
4105 lda r3,X(r11)
4106 extql r1,r3,r1
4107 extqh r2,r3,r2
4108 or r1.r2.r1
4109*/
4110
4111void
4112alpha_expand_unaligned_load (tgt, mem, size, ofs, sign)
4113 rtx tgt, mem;
4114 HOST_WIDE_INT size, ofs;
4115 int sign;
4116{
1eb356b9 4117 rtx meml, memh, addr, extl, exth, tmp, mema;
4208b40f 4118 enum machine_mode mode;
6c174fc0
RH		 4119
4120 meml = gen_reg_rtx (DImode);
4121 memh = gen_reg_rtx (DImode);
4122 addr = gen_reg_rtx (DImode);
4123 extl = gen_reg_rtx (DImode);
4124 exth = gen_reg_rtx (DImode);
4125
1eb356b9
RH		 4126 mema = XEXP (mem, 0);
4127 if (GET_CODE (mema) == LO_SUM)
4128 mema = force_reg (Pmode, mema);
4129
e01acbb1
RH		 4130 /* AND addresses cannot be in any alias set, since they may implicitly
4131 alias surrounding code. Ideally we'd have some alias set that
4132 covered all types except those with alignment 8 or higher. */
4133
4134 tmp = change_address (mem, DImode,
4135 gen_rtx_AND (DImode,
1eb356b9 4136 plus_constant (mema, ofs),
e01acbb1 4137 GEN_INT (-8)));
ba4828e0 4138 set_mem_alias_set (tmp, 0);
e01acbb1
RH		 4139 emit_move_insn (meml, tmp);
4140
4141 tmp = change_address (mem, DImode,
4142 gen_rtx_AND (DImode,
1eb356b9 4143 plus_constant (mema, ofs + size - 1),
e01acbb1 4144 GEN_INT (-8)));
ba4828e0 4145 set_mem_alias_set (tmp, 0);
e01acbb1 4146 emit_move_insn (memh, tmp);
6c174fc0 4147
30102605
RH		 4148 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
4149 {
4150 emit_move_insn (addr, plus_constant (mema, -1));
4151
4152 emit_insn (gen_extqh_be (extl, meml, addr));
4153 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
4154
4155 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4156 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
4157 addr, 1, OPTAB_WIDEN);
4158 }
4159 else if (sign && size == 2)
6c174fc0 4160 {
1eb356b9 4161 emit_move_insn (addr, plus_constant (mema, ofs+2));
6c174fc0 4162
30102605
RH		 4163 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
4164 emit_insn (gen_extqh_le (exth, memh, addr));
6c174fc0 4165
1a7cb241
JW		 4166 /* We must use tgt here for the target. Alpha-vms port fails if we use
4167 addr for the target, because addr is marked as a pointer and combine
4168 knows that pointers are always sign-extended 32 bit values. */
4169 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4208b40f
RH		 4170 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
4171 addr, 1, OPTAB_WIDEN);
6c174fc0 4172 }
4208b40f 4173 else
6c174fc0 4174 {
30102605 4175 if (WORDS_BIG_ENDIAN)
4208b40f 4176 {
30102605
RH		 4177 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
4178 switch ((int) size)
4179 {
4180 case 2:
4181 emit_insn (gen_extwh_be (extl, meml, addr));
4182 mode = HImode;
4183 break;
6c174fc0 4184
30102605
RH		 4185 case 4:
4186 emit_insn (gen_extlh_be (extl, meml, addr));
4187 mode = SImode;
4188 break;
6c174fc0 4189
30102605
RH		 4190 case 8:
4191 emit_insn (gen_extqh_be (extl, meml, addr));
4192 mode = DImode;
4193 break;
5495cc55 4194
30102605
RH		 4195 default:
4196 abort ();
4197 }
4198 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4199 }
4200 else
4201 {
4202 emit_move_insn (addr, plus_constant (mema, ofs));
4203 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4204 switch ((int) size)
4205 {
4206 case 2:
4207 emit_insn (gen_extwh_le (exth, memh, addr));
4208 mode = HImode;
4209 break;
4210
4211 case 4:
4212 emit_insn (gen_extlh_le (exth, memh, addr));
4213 mode = SImode;
4214 break;
4215
4216 case 8:
4217 emit_insn (gen_extqh_le (exth, memh, addr));
4218 mode = DImode;
4219 break;
4220
4221 default:
4222 abort();
4223 }
4208b40f
RH		 4224 }
4225
4226 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4227 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4228 sign, OPTAB_WIDEN);
6c174fc0
RH		 4229 }
4230
4208b40f
RH		 4231 if (addr != tgt)
4232 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
6c174fc0
RH		 4233}
4234
4235/* Similarly, use ins and msk instructions to perform unaligned stores. */
4236
4237void
4238alpha_expand_unaligned_store (dst, src, size, ofs)
4239 rtx dst, src;
4240 HOST_WIDE_INT size, ofs;
4241{
1eb356b9 4242 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
6c174fc0
RH		 4243
4244 dstl = gen_reg_rtx (DImode);
4245 dsth = gen_reg_rtx (DImode);
4246 insl = gen_reg_rtx (DImode);
4247 insh = gen_reg_rtx (DImode);
4248
1eb356b9
RH		 4249 dsta = XEXP (dst, 0);
4250 if (GET_CODE (dsta) == LO_SUM)
4251 dsta = force_reg (Pmode, dsta);
4252
e01acbb1
RH		 4253 /* AND addresses cannot be in any alias set, since they may implicitly
4254 alias surrounding code. Ideally we'd have some alias set that
4255 covered all types except those with alignment 8 or higher. */
4256
6c174fc0 4257 meml = change_address (dst, DImode,
38a448ca 4258 gen_rtx_AND (DImode,
1eb356b9 4259 plus_constant (dsta, ofs),
38a448ca 4260 GEN_INT (-8)));
ba4828e0 4261 set_mem_alias_set (meml, 0);
e01acbb1 4262
6c174fc0 4263 memh = change_address (dst, DImode,
38a448ca 4264 gen_rtx_AND (DImode,
1eb356b9 4265 plus_constant (dsta, ofs + size - 1),
38a448ca 4266 GEN_INT (-8)));
ba4828e0 4267 set_mem_alias_set (memh, 0);
6c174fc0
RH		 4268
4269 emit_move_insn (dsth, memh);
4270 emit_move_insn (dstl, meml);
30102605 4271 if (WORDS_BIG_ENDIAN)
6c174fc0 4272 {
30102605
RH		 4273 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4274
4275 if (src != const0_rtx)
4276 {
4277 switch ((int) size)
4278 {
4279 case 2:
4280 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4281 break;
4282 case 4:
4283 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4284 break;
4285 case 8:
4286 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4287 break;
4288 }
4289 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4290 GEN_INT (size*8), addr));
4291 }
6c174fc0 4292
c8d8ed65 4293 switch ((int) size)
6c174fc0
RH		 4294 {
4295 case 2:
30102605 4296 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
6c174fc0
RH		 4297 break;
4298 case 4:
30102605 4299 {
c4b50f1a 4300 rtx msk = immed_double_const (0xffffffff, 0, DImode);
30102605 4301 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
c4b50f1a 4302 break;
30102605 4303 }
c4b50f1a
RH		 4304 case 8:
4305 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
6c174fc0
RH		 4306 break;
4307 }
30102605
RH		 4308
4309 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
6c174fc0 4310 }
30102605
RH		 4311 else
4312 {
4313 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
6c174fc0 4314
30102605
RH		 4315 if (src != const0_rtx)
4316 {
4317 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4318 GEN_INT (size*8), addr));
6c174fc0 4319
30102605
RH		 4320 switch ((int) size)
4321 {
4322 case 2:
4323 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4324 break;
4325 case 4:
4326 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4327 break;
4328 case 8:
4329 emit_insn (gen_insql_le (insl, src, addr));
4330 break;
4331 }
4332 }
4333
4334 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4335
4336 switch ((int) size)
4337 {
4338 case 2:
4339 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4340 break;
4341 case 4:
30102605 4342 {
c4b50f1a 4343 rtx msk = immed_double_const (0xffffffff, 0, DImode);
30102605 4344 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
c4b50f1a 4345 break;
30102605 4346 }
c4b50f1a
RH		 4347 case 8:
4348 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
30102605
RH		 4349 break;
4350 }
6c174fc0
RH		 4351 }
4352
4353 if (src != const0_rtx)
4354 {
4208b40f
RH		 4355 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4356 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
6c174fc0 4357 }
30102605
RH		 4358
4359 if (WORDS_BIG_ENDIAN)
4360 {
4361 emit_move_insn (meml, dstl);
4362 emit_move_insn (memh, dsth);
4363 }
4364 else
4365 {
4366 /* Must store high before low for degenerate case of aligned. */
4367 emit_move_insn (memh, dsth);
4368 emit_move_insn (meml, dstl);
4369 }
6c174fc0
RH		 4370}
4371
4208b40f
RH		 4372/* The block move code tries to maximize speed by separating loads and
4373 stores at the expense of register pressure: we load all of the data
4374 before we store it back out. There are two secondary effects worth
4375 mentioning, that this speeds copying to/from aligned and unaligned
4376 buffers, and that it makes the code significantly easier to write. */
6c174fc0 4377
4208b40f
RH		 4378#define MAX_MOVE_WORDS 8
4379
4380/* Load an integral number of consecutive unaligned quadwords. */
6c174fc0
RH		 4381
4382static void
4208b40f
RH		 4383alpha_expand_unaligned_load_words (out_regs, smem, words, ofs)
4384 rtx *out_regs;
4385 rtx smem;
4386 HOST_WIDE_INT words, ofs;
6c174fc0
RH		 4387{
4388 rtx const im8 = GEN_INT (-8);
4389 rtx const i64 = GEN_INT (64);
4208b40f 4390 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
1eb356b9 4391 rtx sreg, areg, tmp, smema;
6c174fc0
RH		 4392 HOST_WIDE_INT i;
4393
1eb356b9
RH		 4394 smema = XEXP (smem, 0);
4395 if (GET_CODE (smema) == LO_SUM)
4396 smema = force_reg (Pmode, smema);
4397
6c174fc0
RH		 4398 /* Generate all the tmp registers we need. */
4399 for (i = 0; i < words; ++i)
4208b40f
RH		 4400 {
4401 data_regs[i] = out_regs[i];
4402 ext_tmps[i] = gen_reg_rtx (DImode);
4403 }
4404 data_regs[words] = gen_reg_rtx (DImode);
4405
4406 if (ofs != 0)
f4ef873c 4407 smem = adjust_address (smem, GET_MODE (smem), ofs);
6c174fc0
RH		 4408
4409 /* Load up all of the source data. */
4410 for (i = 0; i < words; ++i)
4411 {
e01acbb1
RH		 4412 tmp = change_address (smem, DImode,
4413 gen_rtx_AND (DImode,
1eb356b9 4414 plus_constant (smema, 8*i),
e01acbb1 4415 im8));
ba4828e0 4416 set_mem_alias_set (tmp, 0);
e01acbb1 4417 emit_move_insn (data_regs[i], tmp);
6c174fc0 4418 }
e01acbb1
RH		 4419
4420 tmp = change_address (smem, DImode,
4421 gen_rtx_AND (DImode,
1eb356b9 4422 plus_constant (smema, 8*words - 1),
e01acbb1 4423 im8));
ba4828e0 4424 set_mem_alias_set (tmp, 0);
e01acbb1 4425 emit_move_insn (data_regs[words], tmp);
6c174fc0
RH		 4426
4427 /* Extract the half-word fragments. Unfortunately DEC decided to make
4428 extxh with offset zero a noop instead of zeroing the register, so
4429 we must take care of that edge condition ourselves with cmov. */
4430
1eb356b9 4431 sreg = copy_addr_to_reg (smema);
4208b40f
RH		 4432 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4433 1, OPTAB_WIDEN);
30102605
RH		 4434 if (WORDS_BIG_ENDIAN)
4435 emit_move_insn (sreg, plus_constant (sreg, 7));
6c174fc0
RH		 4436 for (i = 0; i < words; ++i)
4437 {
30102605
RH		 4438 if (WORDS_BIG_ENDIAN)
4439 {
4440 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4441 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4442 }
4443 else
4444 {
4445 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4446 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4447 }
38a448ca
RH		 4448 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4449 gen_rtx_IF_THEN_ELSE (DImode,
4208b40f
RH		 4450 gen_rtx_EQ (DImode, areg,
4451 const0_rtx),
38a448ca 4452 const0_rtx, ext_tmps[i])));
6c174fc0
RH		 4453 }
4454
4455 /* Merge the half-words into whole words. */
4456 for (i = 0; i < words; ++i)
4457 {
4208b40f
RH		 4458 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4459 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
6c174fc0
RH		 4460 }
4461}
4462
4463/* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4464 may be NULL to store zeros. */
4465
4466static void
4208b40f 4467alpha_expand_unaligned_store_words (data_regs, dmem, words, ofs)
6c174fc0 4468 rtx *data_regs;
4208b40f
RH		 4469 rtx dmem;
4470 HOST_WIDE_INT words, ofs;
6c174fc0
RH		 4471{
4472 rtx const im8 = GEN_INT (-8);
4473 rtx const i64 = GEN_INT (64);
6c174fc0 4474 rtx ins_tmps[MAX_MOVE_WORDS];
4208b40f 4475 rtx st_tmp_1, st_tmp_2, dreg;
1eb356b9 4476 rtx st_addr_1, st_addr_2, dmema;
6c174fc0
RH		 4477 HOST_WIDE_INT i;
4478
1eb356b9
RH		 4479 dmema = XEXP (dmem, 0);
4480 if (GET_CODE (dmema) == LO_SUM)
4481 dmema = force_reg (Pmode, dmema);
4482
6c174fc0
RH		 4483 /* Generate all the tmp registers we need. */
4484 if (data_regs != NULL)
4485 for (i = 0; i < words; ++i)
4486 ins_tmps[i] = gen_reg_rtx(DImode);
4487 st_tmp_1 = gen_reg_rtx(DImode);
4488 st_tmp_2 = gen_reg_rtx(DImode);
4489
4208b40f 4490 if (ofs != 0)
f4ef873c 4491 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4208b40f
RH		 4492
4493 st_addr_2 = change_address (dmem, DImode,
38a448ca 4494 gen_rtx_AND (DImode,
1eb356b9 4495 plus_constant (dmema, words*8 - 1),
6c174fc0 4496 im8));
ba4828e0 4497 set_mem_alias_set (st_addr_2, 0);
e01acbb1 4498
4208b40f 4499 st_addr_1 = change_address (dmem, DImode,
1eb356b9 4500 gen_rtx_AND (DImode, dmema, im8));
ba4828e0 4501 set_mem_alias_set (st_addr_1, 0);
6c174fc0
RH		 4502
4503 /* Load up the destination end bits. */
4504 emit_move_insn (st_tmp_2, st_addr_2);
4505 emit_move_insn (st_tmp_1, st_addr_1);
4506
4507 /* Shift the input data into place. */
1eb356b9 4508 dreg = copy_addr_to_reg (dmema);
30102605
RH		 4509 if (WORDS_BIG_ENDIAN)
4510 emit_move_insn (dreg, plus_constant (dreg, 7));
6c174fc0
RH		 4511 if (data_regs != NULL)
4512 {
4513 for (i = words-1; i >= 0; --i)
4514 {
30102605
RH		 4515 if (WORDS_BIG_ENDIAN)
4516 {
4517 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4518 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4519 }
4520 else
4521 {
4522 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4523 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4524 }
6c174fc0 4525 }
6c174fc0
RH		 4526 for (i = words-1; i > 0; --i)
4527 {
4208b40f
RH		 4528 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4529 ins_tmps[i-1], ins_tmps[i-1], 1,
4530 OPTAB_WIDEN);
6c174fc0
RH		 4531 }
4532 }
4533
4534 /* Split and merge the ends with the destination data. */
30102605
RH		 4535 if (WORDS_BIG_ENDIAN)
4536 {
c4b50f1a 4537 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
30102605
RH		 4538 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4539 }
4540 else
4541 {
4542 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
c4b50f1a 4543 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
30102605 4544 }
6c174fc0
RH		 4545
4546 if (data_regs != NULL)
4547 {
4208b40f
RH		 4548 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4549 st_tmp_2, 1, OPTAB_WIDEN);
4550 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4551 st_tmp_1, 1, OPTAB_WIDEN);
6c174fc0
RH		 4552 }
4553
4554 /* Store it all. */
30102605
RH		 4555 if (WORDS_BIG_ENDIAN)
4556 emit_move_insn (st_addr_1, st_tmp_1);
4557 else
4558 emit_move_insn (st_addr_2, st_tmp_2);
6c174fc0
RH		 4559 for (i = words-1; i > 0; --i)
4560 {
e01acbb1
RH		 4561 rtx tmp = change_address (dmem, DImode,
4562 gen_rtx_AND (DImode,
30102605
RH		 4563 plus_constant(dmema,
4564 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
e01acbb1 4565 im8));
ba4828e0 4566 set_mem_alias_set (tmp, 0);
e01acbb1 4567 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
6c174fc0 4568 }
30102605
RH		 4569 if (WORDS_BIG_ENDIAN)
4570 emit_move_insn (st_addr_2, st_tmp_2);
4571 else
4572 emit_move_insn (st_addr_1, st_tmp_1);
6c174fc0
RH		 4573}
4574
4575
4576/* Expand string/block move operations.
4577
4578 operands[0] is the pointer to the destination.
4579 operands[1] is the pointer to the source.
4580 operands[2] is the number of bytes to move.
4581 operands[3] is the alignment. */
4582
4583int
4584alpha_expand_block_move (operands)
4585 rtx operands[];
4586{
4587 rtx bytes_rtx = operands[2];
4588 rtx align_rtx = operands[3];
f35cba21 4589 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
c17f08e1
RH		 4590 HOST_WIDE_INT bytes = orig_bytes;
4591 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4592 HOST_WIDE_INT dst_align = src_align;
bdb429a5
RK		 4593 rtx orig_src = operands[1];
4594 rtx orig_dst = operands[0];
4595 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4208b40f 4596 rtx tmp;
1eb356b9 4597 unsigned int i, words, ofs, nregs = 0;
6c174fc0 4598
bdb429a5 4599 if (orig_bytes <= 0)
6c174fc0 4600 return 1;
c17f08e1 4601 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
6c174fc0
RH		 4602 return 0;
4603
4208b40f
RH		 4604 /* Look for additional alignment information from recorded register info. */
4605
4606 tmp = XEXP (orig_src, 0);
4607 if (GET_CODE (tmp) == REG)
bdb429a5 4608 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4208b40f
RH		 4609 else if (GET_CODE (tmp) == PLUS
4610 && GET_CODE (XEXP (tmp, 0)) == REG
4611 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4612 {
bdb429a5
RK		 4613 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4614 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4208b40f
RH		 4615
4616 if (a > src_align)
4617 {
bdb429a5
RK		 4618 if (a >= 64 && c % 8 == 0)
4619 src_align = 64;
4620 else if (a >= 32 && c % 4 == 0)
4621 src_align = 32;
4622 else if (a >= 16 && c % 2 == 0)
4623 src_align = 16;
4208b40f
RH		 4624 }
4625 }
4626
4627 tmp = XEXP (orig_dst, 0);
4628 if (GET_CODE (tmp) == REG)
bdb429a5 4629 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4208b40f
RH		 4630 else if (GET_CODE (tmp) == PLUS
4631 && GET_CODE (XEXP (tmp, 0)) == REG
4632 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4633 {
bdb429a5
RK		 4634 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4635 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4208b40f
RH		 4636
4637 if (a > dst_align)
4638 {
bdb429a5
RK		 4639 if (a >= 64 && c % 8 == 0)
4640 dst_align = 64;
4641 else if (a >= 32 && c % 4 == 0)
4642 dst_align = 32;
4643 else if (a >= 16 && c % 2 == 0)
4644 dst_align = 16;
4208b40f
RH		 4645 }
4646 }
4647
bdb429a5 4648 /* Load the entire block into registers. */
15389075 4649 if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
4208b40f
RH		 4650 {
4651 enum machine_mode mode;
bdb429a5 4652
4208b40f 4653 tmp = XEXP (XEXP (orig_src, 0), 0);
15389075 4654
c576fce7
RH		 4655 /* Don't use the existing register if we're reading more than
4656 is held in the register. Nor if there is not a mode that
4657 handles the exact size. */
f35cba21 4658 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4208b40f 4659 if (mode != BLKmode
c576fce7 4660 && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
4208b40f 4661 {
c576fce7
RH		 4662 if (mode == TImode)
4663 {
4664 data_regs[nregs] = gen_lowpart (DImode, tmp);
5197bd50 4665 data_regs[nregs + 1] = gen_highpart (DImode, tmp);
c576fce7
RH		 4666 nregs += 2;
4667 }
4668 else
4669 data_regs[nregs++] = gen_lowpart (mode, tmp);
bdb429a5 4670
4208b40f
RH		 4671 goto src_done;
4672 }
6c174fc0 4673
4208b40f 4674 /* No appropriate mode; fall back on memory. */
792760b9
RK		 4675 orig_src = replace_equiv_address (orig_src,
4676 copy_addr_to_reg (XEXP (orig_src, 0)));
d0285326 4677 src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4208b40f
RH		 4678 }
4679
4680 ofs = 0;
bdb429a5 4681 if (src_align >= 64 && bytes >= 8)
6c174fc0
RH		 4682 {
4683 words = bytes / 8;
4684
6c174fc0 4685 for (i = 0; i < words; ++i)
5197bd50 4686 data_regs[nregs + i] = gen_reg_rtx (DImode);
6c174fc0 4687
6c174fc0 4688 for (i = 0; i < words; ++i)
bdb429a5 4689 emit_move_insn (data_regs[nregs + i],
f4ef873c 4690 adjust_address (orig_src, DImode, ofs + i * 8));
6c174fc0 4691
4208b40f 4692 nregs += words;
6c174fc0 4693 bytes -= words * 8;
cd36edbd 4694 ofs += words * 8;
6c174fc0 4695 }
bdb429a5
RK		 4696
4697 if (src_align >= 32 && bytes >= 4)
6c174fc0
RH		 4698 {
4699 words = bytes / 4;
4700
6c174fc0 4701 for (i = 0; i < words; ++i)
5197bd50 4702 data_regs[nregs + i] = gen_reg_rtx (SImode);
6c174fc0 4703
6c174fc0 4704 for (i = 0; i < words; ++i)
bdb429a5 4705 emit_move_insn (data_regs[nregs + i],
792760b9 4706 adjust_address (orig_src, SImode, ofs + i * 4));
6c174fc0 4707
4208b40f 4708 nregs += words;
6c174fc0 4709 bytes -= words * 4;
cd36edbd 4710 ofs += words * 4;
6c174fc0 4711 }
bdb429a5 4712
c17f08e1 4713 if (bytes >= 8)
6c174fc0
RH		 4714 {
4715 words = bytes / 8;
4716
6c174fc0 4717 for (i = 0; i < words+1; ++i)
5197bd50 4718 data_regs[nregs + i] = gen_reg_rtx (DImode);
6c174fc0 4719
c576fce7
RH		 4720 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4721 words, ofs);
6c174fc0 4722
4208b40f 4723 nregs += words;
6c174fc0 4724 bytes -= words * 8;
cd36edbd 4725 ofs += words * 8;
6c174fc0 4726 }
bdb429a5 4727
bdb429a5 4728 if (! TARGET_BWX && bytes >= 4)
6c174fc0 4729 {
4208b40f 4730 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
6c174fc0 4731 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
6c174fc0
RH		 4732 bytes -= 4;
4733 ofs += 4;
4734 }
bdb429a5 4735
6c174fc0
RH		 4736 if (bytes >= 2)
4737 {
bdb429a5 4738 if (src_align >= 16)
6c174fc0
RH		 4739 {
4740 do {
4208b40f 4741 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
f4ef873c 4742 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
6c174fc0
RH		 4743 bytes -= 2;
4744 ofs += 2;
4745 } while (bytes >= 2);
4746 }
bdb429a5 4747 else if (! TARGET_BWX)
6c174fc0 4748 {
4208b40f 4749 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
6c174fc0 4750 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
6c174fc0
RH		 4751 bytes -= 2;
4752 ofs += 2;
4753 }
4754 }
bdb429a5 4755
6c174fc0
RH		 4756 while (bytes > 0)
4757 {
4208b40f 4758 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
f4ef873c 4759 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
6c174fc0
RH		 4760 bytes -= 1;
4761 ofs += 1;
4762 }
bdb429a5 4763
4208b40f
RH		 4764 src_done:
4765
9a56f4f6 4766 if (nregs > ARRAY_SIZE (data_regs))
bdb429a5 4767 abort ();
4208b40f 4768
bdb429a5 4769 /* Now save it back out again. */
4208b40f
RH		 4770
4771 i = 0, ofs = 0;
4772
4773 if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
4774 {
4775 enum machine_mode mode;
4776 tmp = XEXP (XEXP (orig_dst, 0), 0);
4777
f35cba21 4778 mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
c576fce7 4779 if (GET_MODE (tmp) == mode)
4208b40f 4780 {
c576fce7
RH		 4781 if (nregs == 1)
4782 {
4783 emit_move_insn (tmp, data_regs[0]);
4784 i = 1;
4785 goto dst_done;
4786 }
bdb429a5 4787
c576fce7
RH		 4788 else if (nregs == 2 && mode == TImode)
4789 {
4790 /* Undo the subregging done above when copying between
4791 two TImode registers. */
4792 if (GET_CODE (data_regs[0]) == SUBREG
4793 && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
bdb429a5 4794 emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
c576fce7
RH		 4795 else
4796 {
4797 rtx seq;
4798
4799 start_sequence ();
4800 emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
4801 emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
34cea4e9 4802 seq = get_insns ();
c576fce7
RH		 4803 end_sequence ();
4804
4805 emit_no_conflict_block (seq, tmp, data_regs[0],
4806 data_regs[1], NULL_RTX);
4807 }
4808
4809 i = 2;
4810 goto dst_done;
4811 }
4208b40f
RH		 4812 }
4813
4814 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4815 /* ??? Optimize mode < dst_mode with strict_low_part. */
f35cba21
RH		 4816
4817 /* No appropriate mode; fall back on memory. We can speed things
4818 up by recognizing extra alignment information. */
792760b9
RK		 4819 orig_dst = replace_equiv_address (orig_dst,
4820 copy_addr_to_reg (XEXP (orig_dst, 0)));
d0285326 4821 dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4208b40f
RH		 4822 }
4823
4824 /* Write out the data in whatever chunks reading the source allowed. */
bdb429a5 4825 if (dst_align >= 64)
4208b40f
RH		 4826 {
4827 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4828 {
f4ef873c 4829 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4208b40f
RH		 4830 data_regs[i]);
4831 ofs += 8;
4832 i++;
4833 }
4834 }
bdb429a5
RK		 4835
4836 if (dst_align >= 32)
4208b40f
RH		 4837 {
4838 /* If the source has remaining DImode regs, write them out in
4839 two pieces. */
4840 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4841 {
4842 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4843 NULL_RTX, 1, OPTAB_WIDEN);
4844
f4ef873c 4845 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4208b40f 4846 gen_lowpart (SImode, data_regs[i]));
f4ef873c 4847 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4208b40f
RH		 4848 gen_lowpart (SImode, tmp));
4849 ofs += 8;
4850 i++;
4851 }
4852
4853 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4854 {
f4ef873c 4855 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4208b40f
RH		 4856 data_regs[i]);
4857 ofs += 4;
4858 i++;
4859 }
4860 }
bdb429a5 4861
4208b40f
RH		 4862 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4863 {
4864 /* Write out a remaining block of words using unaligned methods. */
4865
bdb429a5
RK		 4866 for (words = 1; i + words < nregs; words++)
4867 if (GET_MODE (data_regs[i + words]) != DImode)
4208b40f
RH		 4868 break;
4869
4870 if (words == 1)
4871 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4872 else
bdb429a5
RK		 4873 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4874 words, ofs);
4208b40f
RH		 4875
4876 i += words;
4877 ofs += words * 8;
4878 }
4879
4880 /* Due to the above, this won't be aligned. */
4881 /* ??? If we have more than one of these, consider constructing full
4882 words in registers and using alpha_expand_unaligned_store_words. */
4883 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4884 {
4885 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4886 ofs += 4;
4887 i++;
4888 }
4889
bdb429a5 4890 if (dst_align >= 16)
4208b40f
RH		 4891 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4892 {
f4ef873c 4893 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4208b40f
RH		 4894 i++;
4895 ofs += 2;
4896 }
4897 else
4898 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4899 {
4900 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4901 i++;
4902 ofs += 2;
4903 }
bdb429a5 4904
4208b40f
RH		 4905 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4906 {
f4ef873c 4907 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4208b40f
RH		 4908 i++;
4909 ofs += 1;
4910 }
bdb429a5 4911
4208b40f
RH		 4912 dst_done:
4913
4914 if (i != nregs)
bdb429a5 4915 abort ();
6c174fc0
RH		 4916
4917 return 1;
4918}
4919
4920int
4921alpha_expand_block_clear (operands)
4922 rtx operands[];
4923{
4924 rtx bytes_rtx = operands[1];
4925 rtx align_rtx = operands[2];
bdb429a5 4926 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
c17f08e1
RH		 4927 HOST_WIDE_INT bytes = orig_bytes;
4928 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4929 HOST_WIDE_INT alignofs = 0;
bdb429a5 4930 rtx orig_dst = operands[0];
4208b40f 4931 rtx tmp;
c17f08e1 4932 int i, words, ofs = 0;
6c174fc0 4933
bdb429a5 4934 if (orig_bytes <= 0)
6c174fc0 4935 return 1;
c17f08e1 4936 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
6c174fc0
RH		 4937 return 0;
4938
4208b40f 4939 /* Look for stricter alignment. */
4208b40f
RH		 4940 tmp = XEXP (orig_dst, 0);
4941 if (GET_CODE (tmp) == REG)
bdb429a5 4942 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4208b40f
RH		 4943 else if (GET_CODE (tmp) == PLUS
4944 && GET_CODE (XEXP (tmp, 0)) == REG
4945 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4946 {
c17f08e1
RH		 4947 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4948 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4208b40f
RH		 4949
4950 if (a > align)
4951 {
c17f08e1
RH		 4952 if (a >= 64)
4953 align = a, alignofs = 8 - c % 8;
4954 else if (a >= 32)
4955 align = a, alignofs = 4 - c % 4;
4956 else if (a >= 16)
4957 align = a, alignofs = 2 - c % 2;
4208b40f
RH		 4958 }
4959 }
c576fce7
RH		 4960 else if (GET_CODE (tmp) == ADDRESSOF)
4961 {
4962 enum machine_mode mode;
4963
4964 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4965 if (GET_MODE (XEXP (tmp, 0)) == mode)
4966 {
4967 emit_move_insn (XEXP (tmp, 0), const0_rtx);
4968 return 1;
4969 }
4970
4971 /* No appropriate mode; fall back on memory. */
792760b9 4972 orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
c17f08e1 4973 align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
c576fce7 4974 }
4208b40f 4975
c17f08e1
RH		 4976 /* Handle an unaligned prefix first. */
4977
4978 if (alignofs > 0)
4979 {
4980#if HOST_BITS_PER_WIDE_INT >= 64
4981 /* Given that alignofs is bounded by align, the only time BWX could
4982 generate three stores is for a 7 byte fill. Prefer two individual
4983 stores over a load/mask/store sequence. */
4984 if ((!TARGET_BWX || alignofs == 7)
4985 && align >= 32
4986 && !(alignofs == 4 && bytes >= 4))
4987 {
4988 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4989 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4990 rtx mem, tmp;
4991 HOST_WIDE_INT mask;
4992
f4ef873c 4993 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
ba4828e0 4994 set_mem_alias_set (mem, 0);
c17f08e1
RH		 4995
4996 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4997 if (bytes < alignofs)
4998 {
4999 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
5000 ofs += bytes;
5001 bytes = 0;
5002 }
5003 else
5004 {
5005 bytes -= alignofs;
5006 ofs += alignofs;
5007 }
5008 alignofs = 0;
5009
5010 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
5011 NULL_RTX, 1, OPTAB_WIDEN);
5012
5013 emit_move_insn (mem, tmp);
5014 }
5015#endif
5016
5017 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
5018 {
f4ef873c 5019 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
c17f08e1
RH		 5020 bytes -= 1;
5021 ofs += 1;
5022 alignofs -= 1;
5023 }
5024 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
5025 {
f4ef873c 5026 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
c17f08e1
RH		 5027 bytes -= 2;
5028 ofs += 2;
5029 alignofs -= 2;
5030 }
5031 if (alignofs == 4 && bytes >= 4)
5032 {
f4ef873c 5033 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
c17f08e1
RH		 5034 bytes -= 4;
5035 ofs += 4;
5036 alignofs = 0;
5037 }
5038
5039 /* If we've not used the extra lead alignment information by now,
5040 we won't be able to. Downgrade align to match what's left over. */
5041 if (alignofs > 0)
5042 {
5043 alignofs = alignofs & -alignofs;
5044 align = MIN (align, alignofs * BITS_PER_UNIT);
5045 }
5046 }
5047
5048 /* Handle a block of contiguous long-words. */
6c174fc0 5049
bdb429a5 5050 if (align >= 64 && bytes >= 8)
6c174fc0
RH		 5051 {
5052 words = bytes / 8;
5053
5054 for (i = 0; i < words; ++i)
1eb356b9 5055 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
f4ef873c 5056 const0_rtx);
6c174fc0
RH		 5057
5058 bytes -= words * 8;
cd36edbd 5059 ofs += words * 8;
6c174fc0 5060 }
bdb429a5 5061
c17f08e1
RH		 5062 /* If the block is large and appropriately aligned, emit a single
5063 store followed by a sequence of stq_u insns. */
5064
5065 if (align >= 32 && bytes > 16)
5066 {
1eb356b9
RH		 5067 rtx orig_dsta;
5068
f4ef873c 5069 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
c17f08e1
RH		 5070 bytes -= 4;
5071 ofs += 4;
5072
1eb356b9
RH		 5073 orig_dsta = XEXP (orig_dst, 0);
5074 if (GET_CODE (orig_dsta) == LO_SUM)
5075 orig_dsta = force_reg (Pmode, orig_dsta);
5076
c17f08e1
RH		 5077 words = bytes / 8;
5078 for (i = 0; i < words; ++i)
5079 {
ba4828e0
RK		 5080 rtx mem
5081 = change_address (orig_dst, DImode,
5082 gen_rtx_AND (DImode,
1eb356b9 5083 plus_constant (orig_dsta, ofs + i*8),
ba4828e0
RK		 5084 GEN_INT (-8)));
5085 set_mem_alias_set (mem, 0);
c17f08e1
RH		 5086 emit_move_insn (mem, const0_rtx);
5087 }
5088
5089 /* Depending on the alignment, the first stq_u may have overlapped
5090 with the initial stl, which means that the last stq_u didn't
5091 write as much as it would appear. Leave those questionable bytes
5092 unaccounted for. */
5093 bytes -= words * 8 - 4;
5094 ofs += words * 8 - 4;
5095 }
5096
5097 /* Handle a smaller block of aligned words. */
5098
5099 if ((align >= 64 && bytes == 4)
5100 || (align == 32 && bytes >= 4))
6c174fc0
RH		 5101 {
5102 words = bytes / 4;
5103
5104 for (i = 0; i < words; ++i)
f4ef873c 5105 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
bdb429a5 5106 const0_rtx);
6c174fc0
RH		 5107
5108 bytes -= words * 4;
cd36edbd 5109 ofs += words * 4;
6c174fc0 5110 }
bdb429a5 5111
c17f08e1
RH		 5112 /* An unaligned block uses stq_u stores for as many as possible. */
5113
5114 if (bytes >= 8)
6c174fc0
RH		 5115 {
5116 words = bytes / 8;
5117
cd36edbd 5118 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
6c174fc0
RH		 5119
5120 bytes -= words * 8;
cd36edbd 5121 ofs += words * 8;
6c174fc0
RH		 5122 }
5123
c17f08e1 5124 /* Next clean up any trailing pieces. */
6c174fc0 5125
c17f08e1
RH		 5126#if HOST_BITS_PER_WIDE_INT >= 64
5127 /* Count the number of bits in BYTES for which aligned stores could
5128 be emitted. */
5129 words = 0;
5130 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
5131 if (bytes & i)
5132 words += 1;
5133
5134 /* If we have appropriate alignment (and it wouldn't take too many
5135 instructions otherwise), mask out the bytes we need. */
5136 if (TARGET_BWX ? words > 2 : bytes > 0)
5137 {
5138 if (align >= 64)
5139 {
5140 rtx mem, tmp;
5141 HOST_WIDE_INT mask;
5142
f4ef873c 5143 mem = adjust_address (orig_dst, DImode, ofs);
ba4828e0 5144 set_mem_alias_set (mem, 0);
c17f08e1
RH		 5145
5146 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
5147
5148 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
5149 NULL_RTX, 1, OPTAB_WIDEN);
5150
5151 emit_move_insn (mem, tmp);
5152 return 1;
5153 }
5154 else if (align >= 32 && bytes < 4)
5155 {
5156 rtx mem, tmp;
5157 HOST_WIDE_INT mask;
5158
f4ef873c 5159 mem = adjust_address (orig_dst, SImode, ofs);
ba4828e0 5160 set_mem_alias_set (mem, 0);
c17f08e1
RH		 5161
5162 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
5163
5164 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
5165 NULL_RTX, 1, OPTAB_WIDEN);
5166
5167 emit_move_insn (mem, tmp);
5168 return 1;
5169 }
6c174fc0 5170 }
c17f08e1 5171#endif
bdb429a5 5172
6c174fc0
RH		 5173 if (!TARGET_BWX && bytes >= 4)
5174 {
5175 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
5176 bytes -= 4;
5177 ofs += 4;
5178 }
bdb429a5 5179
6c174fc0
RH		 5180 if (bytes >= 2)
5181 {
bdb429a5 5182 if (align >= 16)
6c174fc0
RH		 5183 {
5184 do {
f4ef873c 5185 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
6c174fc0
RH		 5186 const0_rtx);
5187 bytes -= 2;
5188 ofs += 2;
5189 } while (bytes >= 2);
5190 }
bdb429a5 5191 else if (! TARGET_BWX)
6c174fc0
RH		 5192 {
5193 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
5194 bytes -= 2;
5195 ofs += 2;
5196 }
5197 }
bdb429a5 5198
6c174fc0
RH		 5199 while (bytes > 0)
5200 {
f4ef873c 5201 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
6c174fc0
RH		 5202 bytes -= 1;
5203 ofs += 1;
5204 }
5205
5206 return 1;
5207}
6d8fd7bb
RH		 5208
5209/* Returns a mask so that zap(x, value) == x & mask. */
5210
5211rtx
5212alpha_expand_zap_mask (value)
5213 HOST_WIDE_INT value;
5214{
5215 rtx result;
5216 int i;
5217
5218 if (HOST_BITS_PER_WIDE_INT >= 64)
5219 {
5220 HOST_WIDE_INT mask = 0;
5221
5222 for (i = 7; i >= 0; --i)
5223 {
5224 mask <<= 8;
5225 if (!((value >> i) & 1))
5226 mask |= 0xff;
5227 }
5228
5229 result = gen_int_mode (mask, DImode);
5230 }
5231 else if (HOST_BITS_PER_WIDE_INT == 32)
5232 {
5233 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
5234
5235 for (i = 7; i >= 4; --i)
5236 {
5237 mask_hi <<= 8;
5238 if (!((value >> i) & 1))
5239 mask_hi |= 0xff;
5240 }
5241
5242 for (i = 3; i >= 0; --i)
5243 {
5244 mask_lo <<= 8;
5245 if (!((value >> i) & 1))
5246 mask_lo |= 0xff;
5247 }
5248
5249 result = immed_double_const (mask_lo, mask_hi, DImode);
5250 }
5251 else
5252 abort ();
5253
5254 return result;
5255}
5256
5257void
5258alpha_expand_builtin_vector_binop (gen, mode, op0, op1, op2)
5259 rtx (*gen) PARAMS ((rtx, rtx, rtx));
5260 enum machine_mode mode;
5261 rtx op0, op1, op2;
5262{
5263 op0 = gen_lowpart (mode, op0);
5264
5265 if (op1 == const0_rtx)
5266 op1 = CONST0_RTX (mode);
5267 else
5268 op1 = gen_lowpart (mode, op1);
c4b50f1a
RH		 5269
5270 if (op2 == const0_rtx)
6d8fd7bb
RH		 5271 op2 = CONST0_RTX (mode);
5272 else
5273 op2 = gen_lowpart (mode, op2);
5274
5275 emit_insn ((*gen) (op0, op1, op2));
5276}
a6f12d7c
RK		 5277\f
5278/* Adjust the cost of a scheduling dependency. Return the new cost of
5279 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5280
c237e94a 5281static int
a6f12d7c
RK		 5282alpha_adjust_cost (insn, link, dep_insn, cost)
5283 rtx insn;
5284 rtx link;
5285 rtx dep_insn;
5286 int cost;
5287{
26250081 5288 enum attr_type insn_type, dep_insn_type;
a6f12d7c
RK		 5289
5290 /* If the dependence is an anti-dependence, there is no cost. For an
5291 output dependence, there is sometimes a cost, but it doesn't seem
5292 worth handling those few cases. */
a6f12d7c 5293 if (REG_NOTE_KIND (link) != 0)
98791e3a 5294 return cost;
a6f12d7c 5295
26250081
RH		 5296 /* If we can't recognize the insns, we can't really do anything. */
5297 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5298 return cost;
5299
5300 insn_type = get_attr_type (insn);
5301 dep_insn_type = get_attr_type (dep_insn);
5302
bcbbac26 5303 /* Bring in the user-defined memory latency. */
71d9b493
RH		 5304 if (dep_insn_type == TYPE_ILD
5305 || dep_insn_type == TYPE_FLD
5306 || dep_insn_type == TYPE_LDSYM)
bcbbac26
RH		 5307 cost += alpha_memory_latency-1;
5308
98791e3a 5309 /* Everything else handled in DFA bypasses now. */
74835ed8 5310
a6f12d7c
RK		 5311 return cost;
5312}
c237e94a 5313
98791e3a
RH		 5314/* The number of instructions that can be issued per cycle. */
5315
c237e94a
ZW		 5316static int
5317alpha_issue_rate ()
5318{
5319 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5320}
5321
5322static int
98791e3a 5323alpha_use_dfa_pipeline_interface ()
c237e94a 5324{
98791e3a 5325 return true;
c237e94a
ZW		 5326}
5327
98791e3a
RH		 5328/* How many alternative schedules to try. This should be as wide as the
5329 scheduling freedom in the DFA, but no wider. Making this value too
5330 large results extra work for the scheduler.
5331
5332 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5333 alternative schedules. For EV5, we can choose between E0/E1 and
5334 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5335
5336static int
5337alpha_multipass_dfa_lookahead ()
5338{
5339 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5340}
9ecc37f0 5341\f
6f9b006d
RH		 5342/* Machine-specific function data. */
5343
e2500fed 5344struct machine_function GTY(())
6f9b006d 5345{
e2500fed 5346 /* For unicosmk. */
6f9b006d
RH		 5347 /* List of call information words for calls from this function. */
5348 struct rtx_def *first_ciw;
5349 struct rtx_def *last_ciw;
5350 int ciw_count;
5351
5352 /* List of deferred case vectors. */
5353 struct rtx_def *addr_list;
e2500fed
GK		 5354
5355 /* For OSF. */
6f9b006d 5356 const char *some_ld_name;
6f9b006d
RH		 5357};
5358
e2500fed 5359/* How to allocate a 'struct machine_function'. */
30102605 5360
e2500fed
GK		 5361static struct machine_function *
5362alpha_init_machine_status ()
30102605 5363{
e2500fed
GK		 5364 return ((struct machine_function *)
5365 ggc_alloc_cleared (sizeof (struct machine_function)));
30102605 5366}
30102605 5367
9ecc37f0
RH		 5368/* Functions to save and restore alpha_return_addr_rtx. */
5369
9ecc37f0
RH		 5370/* Start the ball rolling with RETURN_ADDR_RTX. */
5371
5372rtx
5373alpha_return_addr (count, frame)
5374 int count;
3c303f52 5375 rtx frame ATTRIBUTE_UNUSED;
9ecc37f0 5376{
9ecc37f0
RH		 5377 if (count != 0)
5378 return const0_rtx;
5379
b91055dd 5380 return get_hard_reg_initial_val (Pmode, REG_RA);
9ecc37f0
RH		 5381}
5382
ccb83cbc
RH		 5383/* Return or create a pseudo containing the gp value for the current
5384 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5385
5386rtx
5387alpha_gp_save_rtx ()
5388{
1eefb6c1
RH		 5389 rtx r = get_hard_reg_initial_val (DImode, 29);
5390 if (GET_CODE (r) != MEM)
5391 r = gen_mem_addressof (r, NULL_TREE);
5392 return r;
ccb83cbc
RH		 5393}
5394
9ecc37f0
RH		 5395static int
5396alpha_ra_ever_killed ()
5397{
6abc6f40
RH		 5398 rtx top;
5399
b91055dd 5400 if (!has_hard_reg_initial_val (Pmode, REG_RA))
9ecc37f0
RH		 5401 return regs_ever_live[REG_RA];
5402
6abc6f40
RH		 5403 push_topmost_sequence ();
5404 top = get_insns ();
5405 pop_topmost_sequence ();
5406
5407 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
9ecc37f0
RH		 5408}
5409
a6f12d7c 5410\f
be7560ea 5411/* Return the trap mode suffix applicable to the current
285a5742 5412 instruction, or NULL. */
a6f12d7c 5413
be7560ea
RH		 5414static const char *
5415get_trap_mode_suffix ()
a6f12d7c 5416{
be7560ea 5417 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
a6f12d7c 5418
be7560ea 5419 switch (s)
a6f12d7c 5420 {
be7560ea
RH		 5421 case TRAP_SUFFIX_NONE:
5422 return NULL;
6245e3df 5423
be7560ea 5424 case TRAP_SUFFIX_SU:
981a828e 5425 if (alpha_fptm >= ALPHA_FPTM_SU)
be7560ea
RH		 5426 return "su";
5427 return NULL;
6245e3df 5428
be7560ea
RH		 5429 case TRAP_SUFFIX_SUI:
5430 if (alpha_fptm >= ALPHA_FPTM_SUI)
5431 return "sui";
5432 return NULL;
5433
5434 case TRAP_SUFFIX_V_SV:
e83015a9
RH		 5435 switch (alpha_fptm)
5436 {
5437 case ALPHA_FPTM_N:
be7560ea 5438 return NULL;
e83015a9 5439 case ALPHA_FPTM_U:
be7560ea 5440 return "v";
e83015a9
RH		 5441 case ALPHA_FPTM_SU:
5442 case ALPHA_FPTM_SUI:
be7560ea 5443 return "sv";
e83015a9
RH		 5444 }
5445 break;
5446
be7560ea 5447 case TRAP_SUFFIX_V_SV_SVI:
0022a940
DMT		 5448 switch (alpha_fptm)
5449 {
5450 case ALPHA_FPTM_N:
be7560ea 5451 return NULL;
0022a940 5452 case ALPHA_FPTM_U:
be7560ea 5453 return "v";
0022a940 5454 case ALPHA_FPTM_SU:
be7560ea 5455 return "sv";
0022a940 5456 case ALPHA_FPTM_SUI:
be7560ea 5457 return "svi";
0022a940
DMT		 5458 }
5459 break;
5460
be7560ea 5461 case TRAP_SUFFIX_U_SU_SUI:
6245e3df
RK		 5462 switch (alpha_fptm)
5463 {
5464 case ALPHA_FPTM_N:
be7560ea 5465 return NULL;
6245e3df 5466 case ALPHA_FPTM_U:
be7560ea 5467 return "u";
6245e3df 5468 case ALPHA_FPTM_SU:
be7560ea 5469 return "su";
6245e3df 5470 case ALPHA_FPTM_SUI:
be7560ea 5471 return "sui";
6245e3df
RK		 5472 }
5473 break;
be7560ea
RH		 5474 }
5475 abort ();
5476}
6245e3df 5477
be7560ea 5478/* Return the rounding mode suffix applicable to the current
285a5742 5479 instruction, or NULL. */
be7560ea
RH		 5480
5481static const char *
5482get_round_mode_suffix ()
5483{
5484 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5485
5486 switch (s)
5487 {
5488 case ROUND_SUFFIX_NONE:
5489 return NULL;
5490 case ROUND_SUFFIX_NORMAL:
5491 switch (alpha_fprm)
6245e3df 5492 {
be7560ea
RH		 5493 case ALPHA_FPRM_NORM:
5494 return NULL;
5495 case ALPHA_FPRM_MINF:
5496 return "m";
5497 case ALPHA_FPRM_CHOP:
5498 return "c";
5499 case ALPHA_FPRM_DYN:
5500 return "d";
6245e3df
RK		 5501 }
5502 break;
5503
be7560ea
RH		 5504 case ROUND_SUFFIX_C:
5505 return "c";
5506 }
5507 abort ();
5508}
5509
6f9b006d
RH		 5510/* Locate some local-dynamic symbol still in use by this function
5511 so that we can print its name in some movdi_er_tlsldm pattern. */
5512
5513static const char *
5514get_some_local_dynamic_name ()
5515{
5516 rtx insn;
5517
5518 if (cfun->machine->some_ld_name)
5519 return cfun->machine->some_ld_name;
5520
5521 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5522 if (INSN_P (insn)
5523 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5524 return cfun->machine->some_ld_name;
5525
5526 abort ();
5527}
5528
5529static int
5530get_some_local_dynamic_name_1 (px, data)
5531 rtx *px;
5532 void *data ATTRIBUTE_UNUSED;
5533{
5534 rtx x = *px;
5535
5536 if (GET_CODE (x) == SYMBOL_REF)
5537 {
5538 const char *str = XSTR (x, 0);
5539 if (str[0] == '@' && str[1] == 'D')
5540 {
5541 cfun->machine->some_ld_name = str;
5542 return 1;
5543 }
5544 }
5545
5546 return 0;
5547}
5548
be7560ea
RH		 5549/* Print an operand. Recognize special options, documented below. */
5550
5551void
5552print_operand (file, x, code)
5553 FILE *file;
5554 rtx x;
5555 int code;
5556{
5557 int i;
5558
5559 switch (code)
5560 {
5561 case '~':
5562 /* Print the assembler name of the current function. */
5563 assemble_name (file, alpha_fnname);
5564 break;
5565
6f9b006d
RH		 5566 case '&':
5567 assemble_name (file, get_some_local_dynamic_name ());
5568 break;
5569
be7560ea
RH		 5570 case '/':
5571 {
5572 const char *trap = get_trap_mode_suffix ();
5573 const char *round = get_round_mode_suffix ();
5574
5575 if (trap || round)
30102605
RH		 5576 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5577 (trap ? trap : ""), (round ? round : ""));
be7560ea
RH		 5578 break;
5579 }
5580
89cfc2c6
RK		 5581 case ',':
5582 /* Generates single precision instruction suffix. */
be7560ea 5583 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
89cfc2c6
RK		 5584 break;
5585
5586 case '-':
5587 /* Generates double precision instruction suffix. */
be7560ea 5588 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
89cfc2c6
RK		 5589 break;
5590
1eb356b9
RH		 5591 case '#':
5592 if (alpha_this_literal_sequence_number == 0)
5593 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5594 fprintf (file, "%d", alpha_this_literal_sequence_number);
5595 break;
5596
5597 case '*':
5598 if (alpha_this_gpdisp_sequence_number == 0)
5599 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5600 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5601 break;
5602
5603 case 'H':
5604 if (GET_CODE (x) == HIGH)
133d3133 5605 output_addr_const (file, XEXP (x, 0));
1eb356b9
RH		 5606 else
5607 output_operand_lossage ("invalid %%H value");
5608 break;
5609
40571d67 5610 case 'J':
6f9b006d
RH		 5611 {
5612 const char *lituse;
5613
5614 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5615 {
5616 x = XVECEXP (x, 0, 0);
5617 lituse = "lituse_tlsgd";
5618 }
5619 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5620 {
5621 x = XVECEXP (x, 0, 0);
5622 lituse = "lituse_tlsldm";
5623 }
5624 else if (GET_CODE (x) == CONST_INT)
5625 lituse = "lituse_jsr";
5626 else
5627 {
5628 output_operand_lossage ("invalid %%J value");
5629 break;
5630 }
5631
5632 if (x != const0_rtx)
5633 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5634 }
40571d67
RH		 5635 break;
5636
a6f12d7c
RK		 5637 case 'r':
5638 /* If this operand is the constant zero, write it as "$31". */
5639 if (GET_CODE (x) == REG)
5640 fprintf (file, "%s", reg_names[REGNO (x)]);
5641 else if (x == CONST0_RTX (GET_MODE (x)))
5642 fprintf (file, "$31");
5643 else
5644 output_operand_lossage ("invalid %%r value");
a6f12d7c
RK		 5645 break;
5646
5647 case 'R':
5648 /* Similar, but for floating-point. */
5649 if (GET_CODE (x) == REG)
5650 fprintf (file, "%s", reg_names[REGNO (x)]);
5651 else if (x == CONST0_RTX (GET_MODE (x)))
5652 fprintf (file, "$f31");
5653 else
5654 output_operand_lossage ("invalid %%R value");
a6f12d7c
RK		 5655 break;
5656
5657 case 'N':
5658 /* Write the 1's complement of a constant. */
5659 if (GET_CODE (x) != CONST_INT)
5660 output_operand_lossage ("invalid %%N value");
5661
0bc8ae6e 5662 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
a6f12d7c
RK		 5663 break;
5664
5665 case 'P':
5666 /* Write 1 << C, for a constant C. */
5667 if (GET_CODE (x) != CONST_INT)
5668 output_operand_lossage ("invalid %%P value");
5669
0bc8ae6e 5670 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
a6f12d7c
RK		 5671 break;
5672
5673 case 'h':
5674 /* Write the high-order 16 bits of a constant, sign-extended. */
5675 if (GET_CODE (x) != CONST_INT)
5676 output_operand_lossage ("invalid %%h value");
5677
0bc8ae6e 5678 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
a6f12d7c
RK		 5679 break;
5680
5681 case 'L':
5682 /* Write the low-order 16 bits of a constant, sign-extended. */
5683 if (GET_CODE (x) != CONST_INT)
5684 output_operand_lossage ("invalid %%L value");
5685
0bc8ae6e
RK		 5686 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5687 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
a6f12d7c
RK		 5688 break;
5689
5690 case 'm':
5691 /* Write mask for ZAP insn. */
5692 if (GET_CODE (x) == CONST_DOUBLE)
5693 {
5694 HOST_WIDE_INT mask = 0;
5695 HOST_WIDE_INT value;
5696
5697 value = CONST_DOUBLE_LOW (x);
5698 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5699 i++, value >>= 8)
5700 if (value & 0xff)
5701 mask |= (1 << i);
5702
5703 value = CONST_DOUBLE_HIGH (x);
5704 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5705 i++, value >>= 8)
5706 if (value & 0xff)
5707 mask |= (1 << (i + sizeof (int)));
5708
0bc8ae6e 5709 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
a6f12d7c
RK		 5710 }
5711
5712 else if (GET_CODE (x) == CONST_INT)
5713 {
5714 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5715
5716 for (i = 0; i < 8; i++, value >>= 8)
5717 if (value & 0xff)
5718 mask |= (1 << i);
5719
0bc8ae6e 5720 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
a6f12d7c
RK		 5721 }
5722 else
5723 output_operand_lossage ("invalid %%m value");
5724 break;
5725
5726 case 'M':
6c174fc0 5727 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
a6f12d7c 5728 if (GET_CODE (x) != CONST_INT
6c174fc0
RH		 5729 || (INTVAL (x) != 8 && INTVAL (x) != 16
5730 && INTVAL (x) != 32 && INTVAL (x) != 64))
a6f12d7c
RK		 5731 output_operand_lossage ("invalid %%M value");
5732
5733 fprintf (file, "%s",
6c174fc0
RH		 5734 (INTVAL (x) == 8 ? "b"
5735 : INTVAL (x) == 16 ? "w"
5736 : INTVAL (x) == 32 ? "l"
5737 : "q"));
a6f12d7c
RK		 5738 break;
5739
5740 case 'U':
5741 /* Similar, except do it from the mask. */
c4b50f1a
RH		 5742 if (GET_CODE (x) == CONST_INT)
5743 {
5744 HOST_WIDE_INT value = INTVAL (x);
5745
5746 if (value == 0xff)
5747 {
5748 fputc ('b', file);
5749 break;
5750 }
5751 if (value == 0xffff)
5752 {
5753 fputc ('w', file);
5754 break;
5755 }
5756 if (value == 0xffffffff)
5757 {
5758 fputc ('l', file);
5759 break;
5760 }
5761 if (value == -1)
5762 {
5763 fputc ('q', file);
5764 break;
5765 }
5766 }
5767 else if (HOST_BITS_PER_WIDE_INT == 32
5768 && GET_CODE (x) == CONST_DOUBLE
5769 && CONST_DOUBLE_LOW (x) == 0xffffffff
5770 && CONST_DOUBLE_HIGH (x) == 0)
5771 {
5772 fputc ('l', file);
5773 break;
5774 }
5775 output_operand_lossage ("invalid %%U value");
a6f12d7c
RK		 5776 break;
5777
5778 case 's':
30102605
RH		 5779 /* Write the constant value divided by 8 for little-endian mode or
5780 (56 - value) / 8 for big-endian mode. */
5781
a6f12d7c 5782 if (GET_CODE (x) != CONST_INT
30102605
RH		 5783 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5784 ? 56
5785 : 64)
5786 || (INTVAL (x) & 7) != 0)
a6f12d7c
RK		 5787 output_operand_lossage ("invalid %%s value");
5788
30102605
RH		 5789 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5790 WORDS_BIG_ENDIAN
5791 ? (56 - INTVAL (x)) / 8
5792 : INTVAL (x) / 8);
a6f12d7c
RK		 5793 break;
5794
5795 case 'S':
5796 /* Same, except compute (64 - c) / 8 */
5797
5798 if (GET_CODE (x) != CONST_INT
5799 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5800 && (INTVAL (x) & 7) != 8)
5801 output_operand_lossage ("invalid %%s value");
5802
0bc8ae6e 5803 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
a6f12d7c
RK		 5804 break;
5805
30102605
RH		 5806 case 't':
5807 {
5808 /* On Unicos/Mk systems: use a DEX expression if the symbol
5809 clashes with a register name. */
5810 int dex = unicosmk_need_dex (x);
5811 if (dex)
5812 fprintf (file, "DEX(%d)", dex);
5813 else
5814 output_addr_const (file, x);
5815 }
5816 break;
5817
bdd4c95a 5818 case 'C': case 'D': case 'c': case 'd':
a6f12d7c 5819 /* Write out comparison name. */
bdd4c95a
RK		 5820 {
5821 enum rtx_code c = GET_CODE (x);
5822
5823 if (GET_RTX_CLASS (c) != '<')
5824 output_operand_lossage ("invalid %%C value");
5825
948068e2 5826 else if (code == 'D')
bdd4c95a
RK		 5827 c = reverse_condition (c);
5828 else if (code == 'c')
5829 c = swap_condition (c);
5830 else if (code == 'd')
5831 c = swap_condition (reverse_condition (c));
5832
5833 if (c == LEU)
5834 fprintf (file, "ule");
5835 else if (c == LTU)
5836 fprintf (file, "ult");
1eb8759b
RH		 5837 else if (c == UNORDERED)
5838 fprintf (file, "un");
bdd4c95a
RK		 5839 else
5840 fprintf (file, "%s", GET_RTX_NAME (c));
5841 }
ab561e66
RK		 5842 break;
5843
a6f12d7c
RK		 5844 case 'E':
5845 /* Write the divide or modulus operator. */
5846 switch (GET_CODE (x))
5847 {
5848 case DIV:
5849 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5850 break;
5851 case UDIV:
5852 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5853 break;
5854 case MOD:
5855 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5856 break;
5857 case UMOD:
5858 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5859 break;
5860 default:
5861 output_operand_lossage ("invalid %%E value");
5862 break;
5863 }
5864 break;
5865
a6f12d7c
RK		 5866 case 'A':
5867 /* Write "_u" for unaligned access. */
5868 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5869 fprintf (file, "_u");
5870 break;
5871
5872 case 0:
5873 if (GET_CODE (x) == REG)
5874 fprintf (file, "%s", reg_names[REGNO (x)]);
5875 else if (GET_CODE (x) == MEM)
5876 output_address (XEXP (x, 0));
6f9b006d
RH		 5877 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5878 {
5879 switch (XINT (XEXP (x, 0), 1))
5880 {
5881 case UNSPEC_DTPREL:
5882 case UNSPEC_TPREL:
5883 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5884 break;
5885 default:
5886 output_operand_lossage ("unknown relocation unspec");
5887 break;
5888 }
5889 }
a6f12d7c
RK		 5890 else
5891 output_addr_const (file, x);
5892 break;
5893
5894 default:
5895 output_operand_lossage ("invalid %%xn code");
5896 }
5897}
714b019c
RH		 5898
5899void
5900print_operand_address (file, addr)
5901 FILE *file;
5902 rtx addr;
5903{
e03ec28f 5904 int basereg = 31;
714b019c
RH		 5905 HOST_WIDE_INT offset = 0;
5906
5907 if (GET_CODE (addr) == AND)
5908 addr = XEXP (addr, 0);
714b019c 5909
e03ec28f
RH		 5910 if (GET_CODE (addr) == PLUS
5911 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
714b019c
RH		 5912 {
5913 offset = INTVAL (XEXP (addr, 1));
e03ec28f 5914 addr = XEXP (addr, 0);
714b019c 5915 }
1eb356b9
RH		 5916
5917 if (GET_CODE (addr) == LO_SUM)
5918 {
6f9b006d
RH		 5919 const char *reloc16, *reloclo;
5920 rtx op1 = XEXP (addr, 1);
5921
5922 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5923 {
5924 op1 = XEXP (op1, 0);
5925 switch (XINT (op1, 1))
5926 {
5927 case UNSPEC_DTPREL:
5928 reloc16 = NULL;
5929 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5930 break;
5931 case UNSPEC_TPREL:
5932 reloc16 = NULL;
5933 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5934 break;
5935 default:
5936 output_operand_lossage ("unknown relocation unspec");
5937 return;
5938 }
5939
5940 output_addr_const (file, XVECEXP (op1, 0, 0));
5941 }
5942 else
5943 {
5944 reloc16 = "gprel";
5945 reloclo = "gprellow";
5946 output_addr_const (file, op1);
5947 }
5948
1eb356b9
RH		 5949 if (offset)
5950 {
5951 fputc ('+', file);
5952 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
5953 }
5954
5955 addr = XEXP (addr, 0);
5956 if (GET_CODE (addr) == REG)
5957 basereg = REGNO (addr);
5958 else if (GET_CODE (addr) == SUBREG
5959 && GET_CODE (SUBREG_REG (addr)) == REG)
5960 basereg = subreg_regno (addr);
5961 else
5962 abort ();
133d3133
RH		 5963
5964 fprintf (file, "($%d)\t\t!%s", basereg,
6f9b006d 5965 (basereg == 29 ? reloc16 : reloclo));
1eb356b9
RH		 5966 return;
5967 }
5968
e03ec28f
RH		 5969 if (GET_CODE (addr) == REG)
5970 basereg = REGNO (addr);
5971 else if (GET_CODE (addr) == SUBREG
5972 && GET_CODE (SUBREG_REG (addr)) == REG)
1eb356b9 5973 basereg = subreg_regno (addr);
e03ec28f
RH		 5974 else if (GET_CODE (addr) == CONST_INT)
5975 offset = INTVAL (addr);
1330f7d5
DR		 5976
5977#if TARGET_ABI_OPEN_VMS
5978 else if (GET_CODE (addr) == SYMBOL_REF)
5979 {
5980 fprintf (file, "%s", XSTR (addr, 0));
5981 return;
5982 }
5983 else if (GET_CODE (addr) == CONST
5984 && GET_CODE (XEXP (addr, 0)) == PLUS
5985 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5986 {
5987 fprintf (file, "%s+%d",
5988 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5989 INTVAL (XEXP (XEXP (addr, 0), 1)));
5990 return;
5991 }
5992#endif
5993
714b019c
RH		 5994 else
5995 abort ();
5996
5997 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
e03ec28f 5998 fprintf (file, "($%d)", basereg);
714b019c 5999}
a6f12d7c 6000\f
9ec36da5
JL		 6001/* Emit RTL insns to initialize the variable parts of a trampoline at
6002 TRAMP. FNADDR is an RTX for the address of the function's pure
6003 code. CXT is an RTX for the static chain value for the function.
c714f03d
RH		 6004
6005 The three offset parameters are for the individual template's
6006 layout. A JMPOFS < 0 indicates that the trampoline does not
6007 contain instructions at all.
6008
9ec36da5
JL		 6009 We assume here that a function will be called many more times than
6010 its address is taken (e.g., it might be passed to qsort), so we
6011 take the trouble to initialize the "hint" field in the JMP insn.
6012 Note that the hint field is PC (new) + 4 * bits 13:0. */
6013
6014void
c714f03d
RH		 6015alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
6016 rtx tramp, fnaddr, cxt;
6017 int fnofs, cxtofs, jmpofs;
9ec36da5
JL		 6018{
6019 rtx temp, temp1, addr;
d2692ef8 6020 /* VMS really uses DImode pointers in memory at this point. */
be7b80f4 6021 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
9ec36da5 6022
d2692ef8
DT		 6023#ifdef POINTERS_EXTEND_UNSIGNED
6024 fnaddr = convert_memory_address (mode, fnaddr);
6025 cxt = convert_memory_address (mode, cxt);
6026#endif
6027
9ec36da5 6028 /* Store function address and CXT. */
d420e567 6029 addr = memory_address (mode, plus_constant (tramp, fnofs));
c5c76735 6030 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
d420e567 6031 addr = memory_address (mode, plus_constant (tramp, cxtofs));
c5c76735 6032 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
c714f03d
RH		 6033
6034 /* This has been disabled since the hint only has a 32k range, and in
285a5742 6035 no existing OS is the stack within 32k of the text segment. */
c714f03d
RH		 6036 if (0 && jmpofs >= 0)
6037 {
6038 /* Compute hint value. */
6039 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
6040 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
6041 OPTAB_WIDEN);
6042 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
6043 build_int_2 (2, 0), NULL_RTX, 1);
22273300
JJ		 6044 temp = expand_and (SImode, gen_lowpart (SImode, temp),
6045 GEN_INT (0x3fff), 0);
c714f03d
RH		 6046
6047 /* Merge in the hint. */
6048 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
c5c76735 6049 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
22273300 6050 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
c714f03d
RH		 6051 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
6052 OPTAB_WIDEN);
c5c76735 6053 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
c714f03d 6054 }
9ec36da5
JL		 6055
6056#ifdef TRANSFER_FROM_TRAMPOLINE
c5c76735 6057 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
9ec36da5
JL		 6058 0, VOIDmode, 1, addr, Pmode);
6059#endif
6060
c714f03d
RH		 6061 if (jmpofs >= 0)
6062 emit_insn (gen_imb ());
9ec36da5
JL		 6063}
6064\f
5495cc55
RH		 6065/* Determine where to put an argument to a function.
6066 Value is zero to push the argument on the stack,
6067 or a hard register in which to store the argument.
6068
6069 MODE is the argument's machine mode.
6070 TYPE is the data type of the argument (as a tree).
6071 This is null for libcalls where that information may
6072 not be available.
6073 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6074 the preceding args and about the function being called.
6075 NAMED is nonzero if this argument is a named parameter
6076 (otherwise it is an extra parameter matching an ellipsis).
6077
6078 On Alpha the first 6 words of args are normally in registers
6079 and the rest are pushed. */
6080
6081rtx
c5e1237f 6082function_arg (cum, mode, type, named)
5495cc55
RH		 6083 CUMULATIVE_ARGS cum;
6084 enum machine_mode mode;
6085 tree type;
6086 int named ATTRIBUTE_UNUSED;
6087{
6088 int basereg;
a82c7f05 6089 int num_args;
5495cc55 6090
30102605
RH		 6091 /* Set up defaults for FP operands passed in FP registers, and
6092 integral operands passed in integer registers. */
6093 if (TARGET_FPREGS
6094 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6095 || GET_MODE_CLASS (mode) == MODE_FLOAT))
6096 basereg = 32 + 16;
6097 else
6098 basereg = 16;
6099
6100 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6101 the three platforms, so we can't avoid conditional compilation. */
be7b80f4 6102#if TARGET_ABI_OPEN_VMS
30102605
RH		 6103 {
6104 if (mode == VOIDmode)
6105 return alpha_arg_info_reg_val (cum);
be7b80f4 6106
30102605
RH		 6107 num_args = cum.num_args;
6108 if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
6109 return NULL_RTX;
6110 }
be7b80f4 6111#else
30102605
RH		 6112#if TARGET_ABI_UNICOSMK
6113 {
6114 int size;
5495cc55 6115
30102605
RH		 6116 /* If this is the last argument, generate the call info word (CIW). */
6117 /* ??? We don't include the caller's line number in the CIW because
6118 I don't know how to determine it if debug infos are turned off. */
6119 if (mode == VOIDmode)
6120 {
6121 int i;
6122 HOST_WIDE_INT lo;
6123 HOST_WIDE_INT hi;
6124 rtx ciw;
6125
6126 lo = 0;
6127
6128 for (i = 0; i < cum.num_reg_words && i < 5; i++)
6129 if (cum.reg_args_type[i])
6130 lo |= (1 << (7 - i));
6131
6132 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
6133 lo |= 7;
6134 else
6135 lo |= cum.num_reg_words;
6136
6137#if HOST_BITS_PER_WIDE_INT == 32
6138 hi = (cum.num_args << 20) | cum.num_arg_words;
6139#else
999c746f
KG		 6140 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
6141 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
30102605
RH		 6142 hi = 0;
6143#endif
6144 ciw = immed_double_const (lo, hi, DImode);
6145
6146 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
6147 UNSPEC_UMK_LOAD_CIW);
6148 }
6149
6150 size = ALPHA_ARG_SIZE (mode, type, named);
6151 num_args = cum.num_reg_words;
6152 if (MUST_PASS_IN_STACK (mode, type)
6153 || cum.num_reg_words + size > 6 || cum.force_stack)
6154 return NULL_RTX;
6155 else if (type && TYPE_MODE (type) == BLKmode)
6156 {
6157 rtx reg1, reg2;
6158
6159 reg1 = gen_rtx_REG (DImode, num_args + 16);
6160 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
6161
6162 /* The argument fits in two registers. Note that we still need to
6163 reserve a register for empty structures. */
6164 if (size == 0)
6165 return NULL_RTX;
6166 else if (size == 1)
6167 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
6168 else
6169 {
6170 reg2 = gen_rtx_REG (DImode, num_args + 17);
6171 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
6172 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
6173 }
6174 }
6175 }
6176#else
6177 {
6178 if (cum >= 6)
6179 return NULL_RTX;
6180 num_args = cum;
6181
6182 /* VOID is passed as a special flag for "last argument". */
6183 if (type == void_type_node)
6184 basereg = 16;
6185 else if (MUST_PASS_IN_STACK (mode, type))
6186 return NULL_RTX;
6187 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
6188 basereg = 16;
6189 }
6190#endif /* TARGET_ABI_UNICOSMK */
be7b80f4 6191#endif /* TARGET_ABI_OPEN_VMS */
5495cc55 6192
a82c7f05 6193 return gen_rtx_REG (mode, num_args + basereg);
5495cc55
RH		 6194}
6195
63966b3b
RH		 6196tree
6197alpha_build_va_list ()
a6f12d7c 6198{
d4b15af9 6199 tree base, ofs, record, type_decl;
a6f12d7c 6200
30102605 6201 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
63966b3b
RH		 6202 return ptr_type_node;
6203
f1e639b1 6204 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
d4b15af9
RH		 6205 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6206 TREE_CHAIN (record) = type_decl;
6207 TYPE_NAME (record) = type_decl;
6208
63966b3b 6209 /* C++? SET_IS_AGGR_TYPE (record, 1); */
a6f12d7c 6210
63966b3b
RH		 6211 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6212 integer_type_node);
6213 DECL_FIELD_CONTEXT (ofs) = record;
29587b1c 6214
63966b3b
RH		 6215 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6216 ptr_type_node);
6217 DECL_FIELD_CONTEXT (base) = record;
6218 TREE_CHAIN (base) = ofs;
29587b1c 6219
63966b3b
RH		 6220 TYPE_FIELDS (record) = base;
6221 layout_type (record);
6222
6223 return record;
6224}
6225
6226void
e5faf155 6227alpha_va_start (valist, nextarg)
63966b3b
RH		 6228 tree valist;
6229 rtx nextarg ATTRIBUTE_UNUSED;
6230{
6231 HOST_WIDE_INT offset;
6232 tree t, offset_field, base_field;
29587b1c 6233
bdb429a5
RK		 6234 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6235 return;
6236
f7130778 6237 if (TARGET_ABI_UNICOSMK)
e5faf155 6238 std_expand_builtin_va_start (valist, nextarg);
63966b3b
RH		 6239
6240 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6241 up by 48, storing fp arg registers in the first 48 bytes, and the
6242 integer arg registers in the next 48 bytes. This is only done,
6243 however, if any integer registers need to be stored.
6244
6245 If no integer registers need be stored, then we must subtract 48
6246 in order to account for the integer arg registers which are counted
6247 in argsize above, but which are not actually stored on the stack. */
6248
6c535c69 6249 if (NUM_ARGS <= 6)
f7130778 6250 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
89cfc2c6 6251 else
63966b3b
RH		 6252 offset = -6 * UNITS_PER_WORD;
6253
f7130778
DR		 6254 if (TARGET_ABI_OPEN_VMS)
6255 {
6256 nextarg = plus_constant (nextarg, offset);
6257 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6258 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6259 make_tree (ptr_type_node, nextarg));
6260 TREE_SIDE_EFFECTS (t) = 1;
63966b3b 6261
f7130778
DR		 6262 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6263 }
6264 else
6265 {
6266 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6267 offset_field = TREE_CHAIN (base_field);
6268
6269 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6270 valist, base_field);
6271 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6272 valist, offset_field);
6273
6274 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6275 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6276 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6277 TREE_SIDE_EFFECTS (t) = 1;
6278 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6279
6280 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6281 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6282 TREE_SIDE_EFFECTS (t) = 1;
6283 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6284 }
63966b3b
RH		 6285}
6286
6287rtx
6288alpha_va_arg (valist, type)
6289 tree valist, type;
6290{
63966b3b 6291 rtx addr;
1fcd592b 6292 tree t, type_size, rounded_size;
63966b3b
RH		 6293 tree offset_field, base_field, addr_tree, addend;
6294 tree wide_type, wide_ofs;
09e98324 6295 int indirect = 0;
63966b3b 6296
30102605 6297 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
63966b3b 6298 return std_expand_builtin_va_arg (valist, type);
a6f12d7c 6299
1fcd592b
RH		 6300 if (type == error_mark_node
6301 || (type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type))) == NULL
6302 || TREE_OVERFLOW (type_size))
6303 rounded_size = size_zero_node;
6304 else
6305 rounded_size = fold (build (MULT_EXPR, sizetype,
6306 fold (build (TRUNC_DIV_EXPR, sizetype,
6307 fold (build (PLUS_EXPR, sizetype,
6308 type_size,
6309 size_int (7))),
6310 size_int (8))),
6311 size_int (8)));
1d783d31 6312
63966b3b
RH		 6313 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6314 offset_field = TREE_CHAIN (base_field);
1d783d31 6315
63966b3b
RH		 6316 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6317 valist, base_field);
6318 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6319 valist, offset_field);
6320
8e5fe23f
RH		 6321 /* If the type could not be passed in registers, skip the block
6322 reserved for the registers. */
6323 if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
6324 {
6325 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6326 build (MAX_EXPR, TREE_TYPE (offset_field),
6327 offset_field, build_int_2 (6*8, 0)));
6328 TREE_SIDE_EFFECTS (t) = 1;
6329 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6330 }
6331
63966b3b
RH		 6332 wide_type = make_signed_type (64);
6333 wide_ofs = save_expr (build1 (CONVERT_EXPR, wide_type, offset_field));
6334
6335 addend = wide_ofs;
09e98324
RO		 6336
6337 if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
6338 {
6339 indirect = 1;
1fcd592b 6340 rounded_size = size_int (UNITS_PER_WORD);
09e98324
RO		 6341 }
6342 else if (FLOAT_TYPE_P (type))
89cfc2c6 6343 {
63966b3b 6344 tree fpaddend, cond;
89cfc2c6 6345
63966b3b
RH		 6346 fpaddend = fold (build (PLUS_EXPR, TREE_TYPE (addend),
6347 addend, build_int_2 (-6*8, 0)));
89cfc2c6 6348
63966b3b
RH		 6349 cond = fold (build (LT_EXPR, integer_type_node,
6350 wide_ofs, build_int_2 (6*8, 0)));
89cfc2c6 6351
63966b3b
RH		 6352 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6353 fpaddend, addend));
89cfc2c6 6354 }
63966b3b
RH		 6355
6356 addr_tree = build (PLUS_EXPR, TREE_TYPE (base_field),
6357 base_field, addend);
6358
6359 addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
6360 addr = copy_to_reg (addr);
6361
6362 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6363 build (PLUS_EXPR, TREE_TYPE (offset_field),
1fcd592b 6364 offset_field, rounded_size));
63966b3b
RH		 6365 TREE_SIDE_EFFECTS (t) = 1;
6366 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6367
09e98324
RO		 6368 if (indirect)
6369 {
6370 addr = force_reg (Pmode, addr);
6371 addr = gen_rtx_MEM (Pmode, addr);
6372 }
6373
63966b3b 6374 return addr;
a6f12d7c
RK		 6375}
6376\f
6d8fd7bb
RH		 6377/* Builtins. */
6378
6379enum alpha_builtin
6380{
6381 ALPHA_BUILTIN_CMPBGE,
c4b50f1a
RH		 6382 ALPHA_BUILTIN_EXTBL,
6383 ALPHA_BUILTIN_EXTWL,
6384 ALPHA_BUILTIN_EXTLL,
6d8fd7bb 6385 ALPHA_BUILTIN_EXTQL,
c4b50f1a
RH		 6386 ALPHA_BUILTIN_EXTWH,
6387 ALPHA_BUILTIN_EXTLH,
6d8fd7bb 6388 ALPHA_BUILTIN_EXTQH,
c4b50f1a
RH		 6389 ALPHA_BUILTIN_INSBL,
6390 ALPHA_BUILTIN_INSWL,
6391 ALPHA_BUILTIN_INSLL,
6392 ALPHA_BUILTIN_INSQL,
6393 ALPHA_BUILTIN_INSWH,
6394 ALPHA_BUILTIN_INSLH,
6395 ALPHA_BUILTIN_INSQH,
6396 ALPHA_BUILTIN_MSKBL,
6397 ALPHA_BUILTIN_MSKWL,
6398 ALPHA_BUILTIN_MSKLL,
6399 ALPHA_BUILTIN_MSKQL,
6400 ALPHA_BUILTIN_MSKWH,
6401 ALPHA_BUILTIN_MSKLH,
6402 ALPHA_BUILTIN_MSKQH,
6403 ALPHA_BUILTIN_UMULH,
6d8fd7bb
RH		 6404 ALPHA_BUILTIN_ZAP,
6405 ALPHA_BUILTIN_ZAPNOT,
6406 ALPHA_BUILTIN_AMASK,
6407 ALPHA_BUILTIN_IMPLVER,
6408 ALPHA_BUILTIN_RPCC,
116b7a5e
RH		 6409 ALPHA_BUILTIN_THREAD_POINTER,
6410 ALPHA_BUILTIN_SET_THREAD_POINTER,
6d8fd7bb
RH		 6411
6412 /* TARGET_MAX */
6413 ALPHA_BUILTIN_MINUB8,
6414 ALPHA_BUILTIN_MINSB8,
6415 ALPHA_BUILTIN_MINUW4,
6416 ALPHA_BUILTIN_MINSW4,
6417 ALPHA_BUILTIN_MAXUB8,
6418 ALPHA_BUILTIN_MAXSB8,
6419 ALPHA_BUILTIN_MAXUW4,
6420 ALPHA_BUILTIN_MAXSW4,
6421 ALPHA_BUILTIN_PERR,
6422 ALPHA_BUILTIN_PKLB,
6423 ALPHA_BUILTIN_PKWB,
6424 ALPHA_BUILTIN_UNPKBL,
6425 ALPHA_BUILTIN_UNPKBW,
6426
c4b50f1a
RH		 6427 /* TARGET_CIX */
6428 ALPHA_BUILTIN_CTTZ,
6429 ALPHA_BUILTIN_CTLZ,
6430 ALPHA_BUILTIN_CTPOP,
6431
6d8fd7bb
RH		 6432 ALPHA_BUILTIN_max
6433};
6434
c4b50f1a
RH		 6435static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6436 CODE_FOR_builtin_cmpbge,
6437 CODE_FOR_builtin_extbl,
6438 CODE_FOR_builtin_extwl,
6439 CODE_FOR_builtin_extll,
6440 CODE_FOR_builtin_extql,
6441 CODE_FOR_builtin_extwh,
6442 CODE_FOR_builtin_extlh,
6443 CODE_FOR_builtin_extqh,
6444 CODE_FOR_builtin_insbl,
6445 CODE_FOR_builtin_inswl,
6446 CODE_FOR_builtin_insll,
6447 CODE_FOR_builtin_insql,
6448 CODE_FOR_builtin_inswh,
6449 CODE_FOR_builtin_inslh,
6450 CODE_FOR_builtin_insqh,
6451 CODE_FOR_builtin_mskbl,
6452 CODE_FOR_builtin_mskwl,
6453 CODE_FOR_builtin_mskll,
6454 CODE_FOR_builtin_mskql,
6455 CODE_FOR_builtin_mskwh,
6456 CODE_FOR_builtin_msklh,
6457 CODE_FOR_builtin_mskqh,
6458 CODE_FOR_umuldi3_highpart,
6459 CODE_FOR_builtin_zap,
6460 CODE_FOR_builtin_zapnot,
6461 CODE_FOR_builtin_amask,
6462 CODE_FOR_builtin_implver,
6463 CODE_FOR_builtin_rpcc,
116b7a5e
RH		 6464 CODE_FOR_load_tp,
6465 CODE_FOR_set_tp,
c4b50f1a
RH		 6466
6467 /* TARGET_MAX */
6468 CODE_FOR_builtin_minub8,
6469 CODE_FOR_builtin_minsb8,
6470 CODE_FOR_builtin_minuw4,
6471 CODE_FOR_builtin_minsw4,
6472 CODE_FOR_builtin_maxub8,
6473 CODE_FOR_builtin_maxsb8,
6474 CODE_FOR_builtin_maxuw4,
6475 CODE_FOR_builtin_maxsw4,
6476 CODE_FOR_builtin_perr,
6477 CODE_FOR_builtin_pklb,
6478 CODE_FOR_builtin_pkwb,
6479 CODE_FOR_builtin_unpkbl,
6480 CODE_FOR_builtin_unpkbw,
6481
6482 /* TARGET_CIX */
6483 CODE_FOR_builtin_cttz,
6484 CODE_FOR_builtin_ctlz,
6485 CODE_FOR_builtin_ctpop
6486};
6487
6d8fd7bb
RH		 6488struct alpha_builtin_def
6489{
6490 const char *name;
6491 enum alpha_builtin code;
6492 unsigned int target_mask;
6493};
6494
6495static struct alpha_builtin_def const zero_arg_builtins[] = {
6496 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6497 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6498};
6499
6500static struct alpha_builtin_def const one_arg_builtins[] = {
6501 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6502 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6503 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6504 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
c4b50f1a
RH		 6505 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6506 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6507 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6508 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6d8fd7bb
RH		 6509};
6510
6511static struct alpha_builtin_def const two_arg_builtins[] = {
6512 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
c4b50f1a
RH		 6513 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6514 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6515 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6d8fd7bb 6516 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
c4b50f1a
RH		 6517 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6518 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6d8fd7bb 6519 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
c4b50f1a
RH		 6520 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6521 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6522 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6523 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6524 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6525 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6526 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6527 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6528 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6529 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6530 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6531 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6532 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6533 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6534 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6d8fd7bb
RH		 6535 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6536 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6537 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6538 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6539 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6540 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6541 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6542 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6543 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6544 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6545 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6546};
6547
6548static void
6549alpha_init_builtins ()
6550{
6551 const struct alpha_builtin_def *p;
6552 tree ftype;
6553 size_t i;
6554
6555 ftype = build_function_type (long_integer_type_node, void_list_node);
6556
6557 p = zero_arg_builtins;
6558 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6559 if ((target_flags & p->target_mask) == p->target_mask)
6a2dd09a
RS		 6560 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6561 NULL, NULL_TREE);
6d8fd7bb 6562
b4de2f7d
AH		 6563 ftype = build_function_type_list (long_integer_type_node,
6564 long_integer_type_node, NULL_TREE);
6d8fd7bb
RH		 6565
6566 p = one_arg_builtins;
6567 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6568 if ((target_flags & p->target_mask) == p->target_mask)
6a2dd09a
RS		 6569 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6570 NULL, NULL_TREE);
6d8fd7bb 6571
b4de2f7d
AH		 6572 ftype = build_function_type_list (long_integer_type_node,
6573 long_integer_type_node,
6574 long_integer_type_node, NULL_TREE);
6d8fd7bb
RH		 6575
6576 p = two_arg_builtins;
6577 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6578 if ((target_flags & p->target_mask) == p->target_mask)
6a2dd09a
RS		 6579 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6580 NULL, NULL_TREE);
116b7a5e
RH		 6581
6582 ftype = build_function_type (ptr_type_node, void_list_node);
6583 builtin_function ("__builtin_thread_pointer", ftype,
6a2dd09a
RS		 6584 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6585 NULL, NULL_TREE);
116b7a5e 6586
b4de2f7d 6587 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
116b7a5e 6588 builtin_function ("__builtin_set_thread_pointer", ftype,
6a2dd09a
RS		 6589 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6590 NULL, NULL_TREE);
6d8fd7bb
RH		 6591}
6592
6593/* Expand an expression EXP that calls a built-in function,
6594 with result going to TARGET if that's convenient
6595 (and in mode MODE if that's convenient).
6596 SUBTARGET may be used as the target for computing one of EXP's operands.
6597 IGNORE is nonzero if the value is to be ignored. */
6598
6599static rtx
6600alpha_expand_builtin (exp, target, subtarget, mode, ignore)
6601 tree exp;
6602 rtx target;
6603 rtx subtarget ATTRIBUTE_UNUSED;
6604 enum machine_mode mode ATTRIBUTE_UNUSED;
6605 int ignore ATTRIBUTE_UNUSED;
6606{
6d8fd7bb
RH		 6607#define MAX_ARGS 2
6608
6609 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6610 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6611 tree arglist = TREE_OPERAND (exp, 1);
6612 enum insn_code icode;
6613 rtx op[MAX_ARGS], pat;
6614 int arity;
116b7a5e 6615 bool nonvoid;
6d8fd7bb
RH		 6616
6617 if (fcode >= ALPHA_BUILTIN_max)
6618 internal_error ("bad builtin fcode");
6619 icode = code_for_builtin[fcode];
6620 if (icode == 0)
6621 internal_error ("bad builtin fcode");
6622
116b7a5e
RH		 6623 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6624
6d8fd7bb
RH		 6625 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6626 arglist;
6627 arglist = TREE_CHAIN (arglist), arity++)
6628 {
6629 const struct insn_operand_data *insn_op;
6630
6631 tree arg = TREE_VALUE (arglist);
6632 if (arg == error_mark_node)
6633 return NULL_RTX;
6634 if (arity > MAX_ARGS)
6635 return NULL_RTX;
6636
116b7a5e
RH		 6637 insn_op = &insn_data[icode].operand[arity + nonvoid];
6638
6639 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6d8fd7bb 6640
6d8fd7bb
RH		 6641 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6642 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6643 }
6644
116b7a5e
RH		 6645 if (nonvoid)
6646 {
6647 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6648 if (!target
6649 || GET_MODE (target) != tmode
6650 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6651 target = gen_reg_rtx (tmode);
6652 }
6d8fd7bb
RH		 6653
6654 switch (arity)
6655 {
6656 case 0:
6657 pat = GEN_FCN (icode) (target);
6658 break;
6659 case 1:
116b7a5e
RH		 6660 if (nonvoid)
6661 pat = GEN_FCN (icode) (target, op[0]);
6662 else
6663 pat = GEN_FCN (icode) (op[0]);
6d8fd7bb
RH		 6664 break;
6665 case 2:
6666 pat = GEN_FCN (icode) (target, op[0], op[1]);
6667 break;
6668 default:
6669 abort ();
6670 }
6671 if (!pat)
6672 return NULL_RTX;
6673 emit_insn (pat);
6674
116b7a5e
RH		 6675 if (nonvoid)
6676 return target;
6677 else
6678 return const0_rtx;
6d8fd7bb
RH		 6679}
6680\f
a6f12d7c
RK		 6681/* This page contains routines that are used to determine what the function
6682 prologue and epilogue code will do and write them out. */
6683
6684/* Compute the size of the save area in the stack. */
6685
89cfc2c6
RK		 6686/* These variables are used for communication between the following functions.
6687 They indicate various things about the current function being compiled
6688 that are used to tell what kind of prologue, epilogue and procedure
285a5742 6689 descriptior to generate. */
89cfc2c6
RK		 6690
6691/* Nonzero if we need a stack procedure. */
c2ea1ac6
DR		 6692enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6693static enum alpha_procedure_types alpha_procedure_type;
89cfc2c6
RK		 6694
6695/* Register number (either FP or SP) that is used to unwind the frame. */
9c0e94a5 6696static int vms_unwind_regno;
89cfc2c6
RK		 6697
6698/* Register number used to save FP. We need not have one for RA since
6699 we don't modify it for register procedures. This is only defined
6700 for register frame procedures. */
9c0e94a5 6701static int vms_save_fp_regno;
89cfc2c6
RK		 6702
6703/* Register number used to reference objects off our PV. */
9c0e94a5 6704static int vms_base_regno;
89cfc2c6 6705
acd92049 6706/* Compute register masks for saved registers. */
89cfc2c6
RK		 6707
6708static void
6709alpha_sa_mask (imaskP, fmaskP)
6710 unsigned long *imaskP;
6711 unsigned long *fmaskP;
6712{
6713 unsigned long imask = 0;
6714 unsigned long fmask = 0;
1eb356b9 6715 unsigned int i;
89cfc2c6 6716
14691f8d
RH		 6717 /* Irritatingly, there are two kinds of thunks -- those created with
6718 ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go through
6719 the regular part of the compiler. In the ASM_OUTPUT_MI_THUNK case
6720 we don't have valid register life info, but assemble_start_function
6721 wants to output .frame and .mask directives. */
b76b08ef 6722 if (current_function_is_thunk && !no_new_pseudos)
acd92049 6723 {
14691f8d
RH		 6724 *imaskP = 0;
6725 *fmaskP = 0;
6726 return;
6727 }
89cfc2c6 6728
c2ea1ac6 6729 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
14691f8d 6730 imask |= (1L << HARD_FRAME_POINTER_REGNUM);
89cfc2c6 6731
14691f8d
RH		 6732 /* One for every register we have to save. */
6733 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6734 if (! fixed_regs[i] && ! call_used_regs[i]
6735 && regs_ever_live[i] && i != REG_RA
6736 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6737 {
6738 if (i < 32)
6739 imask |= (1L << i);
6740 else
6741 fmask |= (1L << (i - 32));
6742 }
6743
6744 /* We need to restore these for the handler. */
6745 if (current_function_calls_eh_return)
6746 for (i = 0; ; ++i)
6747 {
6748 unsigned regno = EH_RETURN_DATA_REGNO (i);
6749 if (regno == INVALID_REGNUM)
6750 break;
6751 imask |= 1L << regno;
6752 }
30102605 6753
14691f8d
RH		 6754 /* If any register spilled, then spill the return address also. */
6755 /* ??? This is required by the Digital stack unwind specification
6756 and isn't needed if we're doing Dwarf2 unwinding. */
6757 if (imask || fmask || alpha_ra_ever_killed ())
6758 imask |= (1L << REG_RA);
9c0e94a5 6759
89cfc2c6
RK		 6760 *imaskP = imask;
6761 *fmaskP = fmask;
89cfc2c6
RK		 6762}
6763
6764int
6765alpha_sa_size ()
6766{
61334ebe 6767 unsigned long mask[2];
89cfc2c6 6768 int sa_size = 0;
61334ebe 6769 int i, j;
89cfc2c6 6770
61334ebe
RH		 6771 alpha_sa_mask (&mask[0], &mask[1]);
6772
6773 if (TARGET_ABI_UNICOSMK)
6774 {
6775 if (mask[0] || mask[1])
6776 sa_size = 14;
6777 }
acd92049 6778 else
acd92049 6779 {
61334ebe
RH		 6780 for (j = 0; j < 2; ++j)
6781 for (i = 0; i < 32; ++i)
6782 if ((mask[j] >> i) & 1)
6783 sa_size++;
acd92049 6784 }
89cfc2c6 6785
30102605
RH		 6786 if (TARGET_ABI_UNICOSMK)
6787 {
6788 /* We might not need to generate a frame if we don't make any calls
6789 (including calls to __T3E_MISMATCH if this is a vararg function),
6790 don't have any local variables which require stack slots, don't
6791 use alloca and have not determined that we need a frame for other
6792 reasons. */
6793
c2ea1ac6
DR		 6794 alpha_procedure_type
6795 = (sa_size || get_frame_size() != 0
6c535c69 6796 || current_function_outgoing_args_size
c2ea1ac6
DR		 6797 || current_function_stdarg || current_function_calls_alloca
6798 || frame_pointer_needed)
6799 ? PT_STACK : PT_REGISTER;
30102605
RH		 6800
6801 /* Always reserve space for saving callee-saved registers if we
6802 need a frame as required by the calling convention. */
c2ea1ac6 6803 if (alpha_procedure_type == PT_STACK)
30102605
RH		 6804 sa_size = 14;
6805 }
6806 else if (TARGET_ABI_OPEN_VMS)
9c0e94a5
RH		 6807 {
6808 /* Start by assuming we can use a register procedure if we don't
6809 make any calls (REG_RA not used) or need to save any
6810 registers and a stack procedure if we do. */
c2ea1ac6
DR		 6811 if ((mask[0] >> REG_RA) & 1)
6812 alpha_procedure_type = PT_STACK;
6813 else if (get_frame_size() != 0)
6814 alpha_procedure_type = PT_REGISTER;
6815 else
6816 alpha_procedure_type = PT_NULL;
61334ebe 6817
cb9a8e97 6818 /* Don't reserve space for saving FP & RA yet. Do that later after we've
61334ebe 6819 made the final decision on stack procedure vs register procedure. */
c2ea1ac6 6820 if (alpha_procedure_type == PT_STACK)
cb9a8e97 6821 sa_size -= 2;
9c0e94a5
RH		 6822
6823 /* Decide whether to refer to objects off our PV via FP or PV.
6824 If we need FP for something else or if we receive a nonlocal
6825 goto (which expects PV to contain the value), we must use PV.
6826 Otherwise, start by assuming we can use FP. */
c2ea1ac6
DR		 6827
6828 vms_base_regno
6829 = (frame_pointer_needed
6830 || current_function_has_nonlocal_label
6831 || alpha_procedure_type == PT_STACK
6832 || current_function_outgoing_args_size)
6833 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
9c0e94a5
RH		 6834
6835 /* If we want to copy PV into FP, we need to find some register
6836 in which to save FP. */
6837
6838 vms_save_fp_regno = -1;
6839 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6840 for (i = 0; i < 32; i++)
6841 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6842 vms_save_fp_regno = i;
6843
c2ea1ac6
DR		 6844 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6845 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6846 else if (alpha_procedure_type == PT_NULL)
6847 vms_base_regno = REG_PV;
9c0e94a5
RH		 6848
6849 /* Stack unwinding should be done via FP unless we use it for PV. */
6850 vms_unwind_regno = (vms_base_regno == REG_PV
6851 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6852
6853 /* If this is a stack procedure, allow space for saving FP and RA. */
c2ea1ac6 6854 if (alpha_procedure_type == PT_STACK)
9c0e94a5
RH		 6855 sa_size += 2;
6856 }
6857 else
6858 {
9c0e94a5
RH		 6859 /* Our size must be even (multiple of 16 bytes). */
6860 if (sa_size & 1)
6861 sa_size++;
6862 }
89cfc2c6
RK		 6863
6864 return sa_size * 8;
6865}
6866
6867int
6868alpha_pv_save_size ()
6869{
6870 alpha_sa_size ();
c2ea1ac6 6871 return alpha_procedure_type == PT_STACK ? 8 : 0;
89cfc2c6
RK		 6872}
6873
6874int
6875alpha_using_fp ()
6876{
6877 alpha_sa_size ();
9c0e94a5 6878 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
89cfc2c6
RK		 6879}
6880
be7b80f4 6881#if TARGET_ABI_OPEN_VMS
8289c43b 6882
91d231cb 6883const struct attribute_spec vms_attribute_table[] =
a6f12d7c 6884{
91d231cb 6885 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
c1bd46a8
DR		 6886 { "overlaid", 0, 0, true, false, false, NULL },
6887 { "global", 0, 0, true, false, false, NULL },
6888 { "initialize", 0, 0, true, false, false, NULL },
6889 { NULL, 0, 0, false, false, false, NULL }
91d231cb 6890};
a6f12d7c 6891
8289c43b
NB		 6892#endif
6893
1eb356b9
RH		 6894static int
6895find_lo_sum (px, data)
6896 rtx *px;
6897 void *data ATTRIBUTE_UNUSED;
6898{
6899 return GET_CODE (*px) == LO_SUM;
6900}
6901
9c0e94a5
RH		 6902static int
6903alpha_does_function_need_gp ()
6904{
6905 rtx insn;
a6f12d7c 6906
30102605
RH		 6907 /* The GP being variable is an OSF abi thing. */
6908 if (! TARGET_ABI_OSF)
9c0e94a5 6909 return 0;
a6f12d7c 6910
70f4f91c 6911 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
9c0e94a5 6912 return 1;
d60a05a1 6913
acd92049
RH		 6914 if (current_function_is_thunk)
6915 return 1;
acd92049 6916
9c0e94a5
RH		 6917 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6918 Even if we are a static function, we still need to do this in case
6919 our address is taken and passed to something like qsort. */
a6f12d7c 6920
9c0e94a5
RH		 6921 push_topmost_sequence ();
6922 insn = get_insns ();
6923 pop_topmost_sequence ();
89cfc2c6 6924
9c0e94a5 6925 for (; insn; insn = NEXT_INSN (insn))
2c3c49de 6926 if (INSN_P (insn)
9c0e94a5
RH		 6927 && GET_CODE (PATTERN (insn)) != USE
6928 && GET_CODE (PATTERN (insn)) != CLOBBER)
6929 {
6930 enum attr_type type = get_attr_type (insn);
6931 if (type == TYPE_LDSYM || type == TYPE_JSR)
6932 return 1;
1eb356b9
RH		 6933 if (TARGET_EXPLICIT_RELOCS
6934 && for_each_rtx (&PATTERN (insn), find_lo_sum, NULL) > 0)
6935 return 1;
9c0e94a5 6936 }
a6f12d7c 6937
9c0e94a5 6938 return 0;
a6f12d7c
RK		 6939}
6940
0f33506c
RK		 6941/* Write a version stamp. Don't write anything if we are running as a
6942 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6943
9d654bba 6944#ifdef HAVE_STAMP_H
0f33506c
RK		 6945#include <stamp.h>
6946#endif
6947
6948void
6949alpha_write_verstamp (file)
4c020733 6950 FILE *file ATTRIBUTE_UNUSED;
0f33506c
RK		 6951{
6952#ifdef MS_STAMP
aec4ca5e 6953 fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
0f33506c
RK		 6954#endif
6955}
ec6840c1 6956\f
6abc6f40
RH		 6957/* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6958 sequences. */
6959
6960static rtx
6961set_frame_related_p ()
6962{
2f937369
DM		 6963 rtx seq = get_insns ();
6964 rtx insn;
6965
6abc6f40
RH		 6966 end_sequence ();
6967
2f937369
DM		 6968 if (!seq)
6969 return NULL_RTX;
6970
6971 if (INSN_P (seq))
6abc6f40 6972 {
2f937369
DM		 6973 insn = seq;
6974 while (insn != NULL_RTX)
6975 {
6976 RTX_FRAME_RELATED_P (insn) = 1;
6977 insn = NEXT_INSN (insn);
6978 }
6979 seq = emit_insn (seq);
6abc6f40
RH		 6980 }
6981 else
6982 {
6983 seq = emit_insn (seq);
6984 RTX_FRAME_RELATED_P (seq) = 1;
6abc6f40 6985 }
2f937369 6986 return seq;
6abc6f40
RH		 6987}
6988
6989#define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6990
a6f12d7c
RK		 6991/* Write function prologue. */
6992
89cfc2c6
RK		 6993/* On vms we have two kinds of functions:
6994
6995 - stack frame (PROC_STACK)
6996 these are 'normal' functions with local vars and which are
6997 calling other functions
6998 - register frame (PROC_REGISTER)
6999 keeps all data in registers, needs no stack
7000
7001 We must pass this to the assembler so it can generate the
7002 proper pdsc (procedure descriptor)
7003 This is done with the '.pdesc' command.
7004
9c0e94a5
RH		 7005 On not-vms, we don't really differentiate between the two, as we can
7006 simply allocate stack without saving registers. */
89cfc2c6
RK		 7007
7008void
9c0e94a5 7009alpha_expand_prologue ()
89cfc2c6 7010{
9c0e94a5 7011 /* Registers to save. */
89cfc2c6
RK		 7012 unsigned long imask = 0;
7013 unsigned long fmask = 0;
7014 /* Stack space needed for pushing registers clobbered by us. */
7015 HOST_WIDE_INT sa_size;
7016 /* Complete stack size needed. */
7017 HOST_WIDE_INT frame_size;
7018 /* Offset from base reg to register save area. */
9c0e94a5 7019 HOST_WIDE_INT reg_offset;
3873d24b 7020 rtx sa_reg, mem;
89cfc2c6
RK		 7021 int i;
7022
7023 sa_size = alpha_sa_size ();
89cfc2c6 7024
9c0e94a5 7025 frame_size = get_frame_size ();
be7b80f4 7026 if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7027 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7028 + (alpha_procedure_type == PT_STACK ? 8 : 0)
9c0e94a5
RH		 7029 + frame_size
7030 + current_function_pretend_args_size);
30102605
RH		 7031 else if (TARGET_ABI_UNICOSMK)
7032 /* We have to allocate space for the DSIB if we generate a frame. */
7033 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7034 + (alpha_procedure_type == PT_STACK ? 48 : 0))
30102605
RH		 7035 + ALPHA_ROUND (frame_size
7036 + current_function_outgoing_args_size);
9c0e94a5
RH		 7037 else
7038 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7039 + sa_size
7040 + ALPHA_ROUND (frame_size
7041 + current_function_pretend_args_size));
89cfc2c6 7042
be7b80f4 7043 if (TARGET_ABI_OPEN_VMS)
9c0e94a5
RH		 7044 reg_offset = 8;
7045 else
7046 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
89cfc2c6 7047
9c0e94a5 7048 alpha_sa_mask (&imask, &fmask);
89cfc2c6 7049
941cc05a 7050 /* Emit an insn to reload GP, if needed. */
be7b80f4 7051 if (TARGET_ABI_OSF)
941cc05a
RK		 7052 {
7053 alpha_function_needs_gp = alpha_does_function_need_gp ();
7054 if (alpha_function_needs_gp)
7055 emit_insn (gen_prologue_ldgp ());
7056 }
7057
4f1c5cce
RH		 7058 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7059 the call to mcount ourselves, rather than having the linker do it
7060 magically in response to -pg. Since _mcount has special linkage,
7061 don't represent the call as a call. */
70f4f91c 7062 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
4f1c5cce 7063 emit_insn (gen_prologue_mcount ());
30102605
RH		 7064
7065 if (TARGET_ABI_UNICOSMK)
7066 unicosmk_gen_dsib (&imask);
7067
89cfc2c6
RK		 7068 /* Adjust the stack by the frame size. If the frame size is > 4096
7069 bytes, we need to be sure we probe somewhere in the first and last
7070 4096 bytes (we can probably get away without the latter test) and
7071 every 8192 bytes in between. If the frame size is > 32768, we
7072 do this in a loop. Otherwise, we generate the explicit probe
7073 instructions.
7074
7075 Note that we are only allowed to adjust sp once in the prologue. */
7076
9c0e94a5 7077 if (frame_size <= 32768)
89cfc2c6
RK		 7078 {
7079 if (frame_size > 4096)
7080 {
7081 int probed = 4096;
7082
9c0e94a5 7083 do
30102605
RH		 7084 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7085 ? -probed + 64
7086 : -probed)));
9c0e94a5 7087 while ((probed += 8192) < frame_size);
89cfc2c6
RK		 7088
7089 /* We only have to do this probe if we aren't saving registers. */
7090 if (sa_size == 0 && probed + 4096 < frame_size)
9c0e94a5 7091 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
89cfc2c6
RK		 7092 }
7093
7094 if (frame_size != 0)
8207e7c6 7095 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
30102605
RH		 7096 GEN_INT (TARGET_ABI_UNICOSMK
7097 ? -frame_size + 64
7098 : -frame_size))));
89cfc2c6
RK		 7099 }
7100 else
7101 {
9c0e94a5 7102 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
89cfc2c6
RK		 7103 number of 8192 byte blocks to probe. We then probe each block
7104 in the loop and then set SP to the proper location. If the
7105 amount remaining is > 4096, we have to do one more probe if we
7106 are not saving any registers. */
7107
7108 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7109 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
9c0e94a5
RH		 7110 rtx ptr = gen_rtx_REG (DImode, 22);
7111 rtx count = gen_rtx_REG (DImode, 23);
37679e06 7112 rtx seq;
89cfc2c6 7113
9c0e94a5 7114 emit_move_insn (count, GEN_INT (blocks));
30102605
RH		 7115 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7116 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
89cfc2c6 7117
9c0e94a5
RH		 7118 /* Because of the difficulty in emitting a new basic block this
7119 late in the compilation, generate the loop as a single insn. */
7120 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
89cfc2c6
RK		 7121
7122 if (leftover > 4096 && sa_size == 0)
9c0e94a5
RH		 7123 {
7124 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7125 MEM_VOLATILE_P (last) = 1;
7126 emit_move_insn (last, const0_rtx);
7127 }
89cfc2c6 7128
be7b80f4 7129 if (TARGET_ABI_WINDOWS_NT)
f9d7e5cd
RH		 7130 {
7131 /* For NT stack unwind (done by 'reverse execution'), it's
7132 not OK to take the result of a loop, even though the value
7133 is already in ptr, so we reload it via a single operation
37679e06
RH		 7134 and subtract it to sp.
7135
7136 Yes, that's correct -- we have to reload the whole constant
7137 into a temporary via ldah+lda then subtract from sp. To
7138 ensure we get ldah+lda, we use a special pattern. */
f9d7e5cd
RH		 7139
7140 HOST_WIDE_INT lo, hi;
14eecd34
RH		 7141 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7142 hi = frame_size - lo;
6abc6f40 7143
37679e06
RH		 7144 emit_move_insn (ptr, GEN_INT (hi));
7145 emit_insn (gen_nt_lda (ptr, GEN_INT (lo)));
7146 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7147 ptr));
f9d7e5cd
RH		 7148 }
7149 else
7150 {
f9d7e5cd
RH		 7151 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7152 GEN_INT (-leftover)));
f9d7e5cd 7153 }
37679e06
RH		 7154
7155 /* This alternative is special, because the DWARF code cannot
7156 possibly intuit through the loop above. So we invent this
7157 note it looks at instead. */
7158 RTX_FRAME_RELATED_P (seq) = 1;
7159 REG_NOTES (seq)
7160 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7161 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7162 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
30102605
RH		 7163 GEN_INT (TARGET_ABI_UNICOSMK
7164 ? -frame_size + 64
7165 : -frame_size))),
37679e06 7166 REG_NOTES (seq));
89cfc2c6
RK		 7167 }
7168
30102605 7169 if (!TARGET_ABI_UNICOSMK)
89cfc2c6 7170 {
30102605
RH		 7171 /* Cope with very large offsets to the register save area. */
7172 sa_reg = stack_pointer_rtx;
7173 if (reg_offset + sa_size > 0x8000)
7174 {
7175 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7176 HOST_WIDE_INT bias;
89cfc2c6 7177
30102605
RH		 7178 if (low + sa_size <= 0x8000)
7179 bias = reg_offset - low, reg_offset = low;
7180 else
7181 bias = reg_offset, reg_offset = 0;
89cfc2c6 7182
30102605
RH		 7183 sa_reg = gen_rtx_REG (DImode, 24);
7184 FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
7185 GEN_INT (bias))));
7186 }
9c0e94a5 7187
30102605 7188 /* Save regs in stack order. Beginning with VMS PV. */
c2ea1ac6 7189 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
30102605
RH		 7190 {
7191 mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
7192 set_mem_alias_set (mem, alpha_sr_alias_set);
7193 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
7194 }
89cfc2c6 7195
30102605
RH		 7196 /* Save register RA next. */
7197 if (imask & (1L << REG_RA))
7198 {
7199 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7200 set_mem_alias_set (mem, alpha_sr_alias_set);
7201 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
7202 imask &= ~(1L << REG_RA);
7203 reg_offset += 8;
7204 }
89cfc2c6 7205
30102605
RH		 7206 /* Now save any other registers required to be saved. */
7207 for (i = 0; i < 32; i++)
7208 if (imask & (1L << i))
7209 {
7210 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7211 set_mem_alias_set (mem, alpha_sr_alias_set);
7212 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7213 reg_offset += 8;
7214 }
89cfc2c6 7215
30102605
RH		 7216 for (i = 0; i < 32; i++)
7217 if (fmask & (1L << i))
7218 {
7219 mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
7220 set_mem_alias_set (mem, alpha_sr_alias_set);
7221 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7222 reg_offset += 8;
7223 }
7224 }
c2ea1ac6 7225 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
30102605
RH		 7226 {
7227 /* The standard frame on the T3E includes space for saving registers.
7228 We just have to use it. We don't have to save the return address and
7229 the old frame pointer here - they are saved in the DSIB. */
7230
7231 reg_offset = -56;
7232 for (i = 9; i < 15; i++)
7233 if (imask & (1L << i))
7234 {
7235 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7236 reg_offset));
7237 set_mem_alias_set (mem, alpha_sr_alias_set);
7238 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7239 reg_offset -= 8;
7240 }
7241 for (i = 2; i < 10; i++)
7242 if (fmask & (1L << i))
7243 {
7244 mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
7245 reg_offset));
7246 set_mem_alias_set (mem, alpha_sr_alias_set);
7247 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7248 reg_offset -= 8;
7249 }
7250 }
89cfc2c6 7251
be7b80f4 7252 if (TARGET_ABI_OPEN_VMS)
89cfc2c6 7253 {
c2ea1ac6
DR		 7254 if (alpha_procedure_type == PT_REGISTER)
7255 /* Register frame procedures save the fp.
7256 ?? Ought to have a dwarf2 save for this. */
54aaa4ea
RH		 7257 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7258 hard_frame_pointer_rtx);
89cfc2c6 7259
c2ea1ac6 7260 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
54aaa4ea
RH		 7261 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7262 gen_rtx_REG (DImode, REG_PV)));
89cfc2c6 7263
c2ea1ac6
DR		 7264 if (alpha_procedure_type != PT_NULL
7265 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
8207e7c6 7266 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
89cfc2c6 7267
9c0e94a5
RH		 7268 /* If we have to allocate space for outgoing args, do it now. */
7269 if (current_function_outgoing_args_size != 0)
8207e7c6
RK		 7270 FRP (emit_move_insn
7271 (stack_pointer_rtx,
7272 plus_constant (hard_frame_pointer_rtx,
7273 - (ALPHA_ROUND
7274 (current_function_outgoing_args_size)))));
9c0e94a5 7275 }
30102605 7276 else if (!TARGET_ABI_UNICOSMK)
9c0e94a5
RH		 7277 {
7278 /* If we need a frame pointer, set it from the stack pointer. */
7279 if (frame_pointer_needed)
7280 {
7281 if (TARGET_CAN_FAULT_IN_PROLOGUE)
6abc6f40 7282 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
89cfc2c6 7283 else
8207e7c6
RK		 7284 /* This must always be the last instruction in the
7285 prologue, thus we emit a special move + clobber. */
6abc6f40
RH		 7286 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7287 stack_pointer_rtx, sa_reg)));
89cfc2c6 7288 }
89cfc2c6
RK		 7289 }
7290
9c0e94a5
RH		 7291 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7292 the prologue, for exception handling reasons, we cannot do this for
7293 any insn that might fault. We could prevent this for mems with a
7294 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7295 have to prevent all such scheduling with a blockage.
89cfc2c6 7296
9c0e94a5
RH		 7297 Linux, on the other hand, never bothered to implement OSF/1's
7298 exception handling, and so doesn't care about such things. Anyone
7299 planning to use dwarf2 frame-unwind info can also omit the blockage. */
89cfc2c6 7300
9c0e94a5
RH		 7301 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7302 emit_insn (gen_blockage ());
ef86d2ee
WL		 7303}
7304
acd92049 7305/* Output the textual info surrounding the prologue. */
89cfc2c6 7306
9c0e94a5 7307void
acd92049 7308alpha_start_function (file, fnname, decl)
9c0e94a5 7309 FILE *file;
e03c5670 7310 const char *fnname;
3c303f52 7311 tree decl ATTRIBUTE_UNUSED;
9ecc37f0 7312{
9c0e94a5
RH		 7313 unsigned long imask = 0;
7314 unsigned long fmask = 0;
7315 /* Stack space needed for pushing registers clobbered by us. */
7316 HOST_WIDE_INT sa_size;
7317 /* Complete stack size needed. */
7318 HOST_WIDE_INT frame_size;
7319 /* Offset from base reg to register save area. */
7320 HOST_WIDE_INT reg_offset;
acd92049 7321 char *entry_label = (char *) alloca (strlen (fnname) + 6);
9c0e94a5 7322 int i;
9ecc37f0 7323
30102605
RH		 7324 /* Don't emit an extern directive for functions defined in the same file. */
7325 if (TARGET_ABI_UNICOSMK)
7326 {
7327 tree name_tree;
7328 name_tree = get_identifier (fnname);
7329 TREE_ASM_WRITTEN (name_tree) = 1;
7330 }
7331
941cc05a 7332 alpha_fnname = fnname;
9c0e94a5 7333 sa_size = alpha_sa_size ();
9ecc37f0 7334
9c0e94a5 7335 frame_size = get_frame_size ();
be7b80f4 7336 if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7337 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7338 + (alpha_procedure_type == PT_STACK ? 8 : 0)
9c0e94a5
RH		 7339 + frame_size
7340 + current_function_pretend_args_size);
30102605
RH		 7341 else if (TARGET_ABI_UNICOSMK)
7342 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7343 + (alpha_procedure_type == PT_STACK ? 48 : 0))
30102605
RH		 7344 + ALPHA_ROUND (frame_size
7345 + current_function_outgoing_args_size);
9c0e94a5
RH		 7346 else
7347 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7348 + sa_size
7349 + ALPHA_ROUND (frame_size
7350 + current_function_pretend_args_size));
9ecc37f0 7351
be7b80f4 7352 if (TARGET_ABI_OPEN_VMS)
9c0e94a5
RH		 7353 reg_offset = 8;
7354 else
7355 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
9ecc37f0 7356
9c0e94a5 7357 alpha_sa_mask (&imask, &fmask);
a6f12d7c 7358
d60a05a1 7359 /* Ecoff can handle multiple .file directives, so put out file and lineno.
48f6bfac
RK		 7360 We have to do that before the .ent directive as we cannot switch
7361 files within procedures with native ecoff because line numbers are
7362 linked to procedure descriptors.
7363 Outputting the lineno helps debugging of one line functions as they
7364 would otherwise get no line number at all. Please note that we would
ddd5a7c1 7365 like to put out last_linenum from final.c, but it is not accessible. */
48f6bfac
RK		 7366
7367 if (write_symbols == SDB_DEBUG)
7368 {
30102605 7369#ifdef ASM_OUTPUT_SOURCE_FILENAME
48f6bfac
RK		 7370 ASM_OUTPUT_SOURCE_FILENAME (file,
7371 DECL_SOURCE_FILE (current_function_decl));
30102605
RH		 7372#endif
7373#ifdef ASM_OUTPUT_SOURCE_LINE
48f6bfac 7374 if (debug_info_level != DINFO_LEVEL_TERSE)
d60a05a1
RK		 7375 ASM_OUTPUT_SOURCE_LINE (file,
7376 DECL_SOURCE_LINE (current_function_decl));
30102605 7377#endif
48f6bfac
RK		 7378 }
7379
9c0e94a5 7380 /* Issue function start and label. */
30102605
RH		 7381 if (TARGET_ABI_OPEN_VMS
7382 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
33d01c33 7383 {
9c0e94a5 7384 fputs ("\t.ent ", file);
acd92049 7385 assemble_name (file, fnname);
9c0e94a5 7386 putc ('\n', file);
941cc05a
RK		 7387
7388 /* If the function needs GP, we'll write the "..ng" label there.
7389 Otherwise, do it here. */
14691f8d
RH		 7390 if (TARGET_ABI_OSF
7391 && ! alpha_function_needs_gp
7392 && ! current_function_is_thunk)
941cc05a
RK		 7393 {
7394 putc ('$', file);
7395 assemble_name (file, fnname);
7396 fputs ("..ng:\n", file);
7397 }
33d01c33 7398 }
48f6bfac 7399
acd92049 7400 strcpy (entry_label, fnname);
be7b80f4 7401 if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7402 strcat (entry_label, "..en");
30102605
RH		 7403
7404 /* For public functions, the label must be globalized by appending an
7405 additional colon. */
7406 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7407 strcat (entry_label, ":");
7408
9c0e94a5
RH		 7409 ASM_OUTPUT_LABEL (file, entry_label);
7410 inside_function = TRUE;
48f6bfac 7411
be7b80f4 7412 if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7413 fprintf (file, "\t.base $%d\n", vms_base_regno);
a6f12d7c 7414
30102605 7415 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
9c0e94a5 7416 && !flag_inhibit_size_directive)
9973f4a2 7417 {
9c0e94a5
RH		 7418 /* Set flags in procedure descriptor to request IEEE-conformant
7419 math-library routines. The value we set it to is PDSC_EXC_IEEE
285a5742 7420 (/usr/include/pdsc.h). */
9c0e94a5 7421 fputs ("\t.eflag 48\n", file);
9973f4a2 7422 }
a6f12d7c 7423
9c0e94a5
RH		 7424 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7425 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7426 alpha_arg_offset = -frame_size + 48;
c97e3db7 7427
9c0e94a5
RH		 7428 /* Describe our frame. If the frame size is larger than an integer,
7429 print it as zero to avoid an assembler error. We won't be
7430 properly describing such a frame, but that's the best we can do. */
30102605
RH		 7431 if (TARGET_ABI_UNICOSMK)
7432 ;
7433 else if (TARGET_ABI_OPEN_VMS)
a6f12d7c 7434 {
9c0e94a5
RH		 7435 fprintf (file, "\t.frame $%d,", vms_unwind_regno);
7436 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6f4fdd10 7437 frame_size >= ((HOST_WIDE_INT) 1 << 31) ? 0 : frame_size);
3c303f52
KG		 7438 fputs (",$26,", file);
7439 fprintf (file, HOST_WIDE_INT_PRINT_DEC, reg_offset);
7440 fputs ("\n", file);
a6f12d7c 7441 }
9c0e94a5 7442 else if (!flag_inhibit_size_directive)
33d01c33 7443 {
5665caa2 7444 fprintf (file, "\t.frame $%d,",
33d01c33 7445 (frame_pointer_needed
9c0e94a5 7446 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM));
5665caa2 7447 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9c0e94a5 7448 frame_size >= (1l << 31) ? 0 : frame_size);
5665caa2 7449 fprintf (file, ",$26,%d\n", current_function_pretend_args_size);
33d01c33 7450 }
0d24ff5d 7451
9c0e94a5 7452 /* Describe which registers were spilled. */
30102605
RH		 7453 if (TARGET_ABI_UNICOSMK)
7454 ;
7455 else if (TARGET_ABI_OPEN_VMS)
0d24ff5d 7456 {
9c0e94a5 7457 if (imask)
30102605 7458 /* ??? Does VMS care if mask contains ra? The old code didn't
9c0e94a5 7459 set it, so I don't here. */
3c303f52 7460 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1L << REG_RA));
9c0e94a5 7461 if (fmask)
3c303f52 7462 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
c2ea1ac6 7463 if (alpha_procedure_type == PT_REGISTER)
9c0e94a5
RH		 7464 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7465 }
7466 else if (!flag_inhibit_size_directive)
7467 {
7468 if (imask)
0d24ff5d 7469 {
3c303f52 7470 fprintf (file, "\t.mask 0x%lx,", imask);
9c0e94a5
RH		 7471 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7472 frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
7473 putc ('\n', file);
7474
7475 for (i = 0; i < 32; ++i)
7476 if (imask & (1L << i))
7477 reg_offset += 8;
0d24ff5d 7478 }
9c0e94a5
RH		 7479
7480 if (fmask)
0d24ff5d 7481 {
3c303f52 7482 fprintf (file, "\t.fmask 0x%lx,", fmask);
9c0e94a5
RH		 7483 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7484 frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
7485 putc ('\n', file);
0d24ff5d 7486 }
a6f12d7c
RK		 7487 }
7488
be7b80f4 7489#if TARGET_ABI_OPEN_VMS
d48bc59a
RH		 7490 /* Ifdef'ed cause link_section are only available then. */
7491 readonly_data_section ();
9c0e94a5 7492 fprintf (file, "\t.align 3\n");
acd92049 7493 assemble_name (file, fnname); fputs ("..na:\n", file);
9c0e94a5 7494 fputs ("\t.ascii \"", file);
acd92049 7495 assemble_name (file, fnname);
9c0e94a5 7496 fputs ("\\0\"\n", file);
acd92049 7497 alpha_need_linkage (fnname, 1);
9c0e94a5
RH		 7498 text_section ();
7499#endif
7500}
a6f12d7c 7501
9c0e94a5 7502/* Emit the .prologue note at the scheduled end of the prologue. */
0f33506c 7503
b4c25db2
NB		 7504static void
7505alpha_output_function_end_prologue (file)
9c0e94a5
RH		 7506 FILE *file;
7507{
30102605
RH		 7508 if (TARGET_ABI_UNICOSMK)
7509 ;
7510 else if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7511 fputs ("\t.prologue\n", file);
be7b80f4 7512 else if (TARGET_ABI_WINDOWS_NT)
9c0e94a5
RH		 7513 fputs ("\t.prologue 0\n", file);
7514 else if (!flag_inhibit_size_directive)
14691f8d
RH		 7515 fprintf (file, "\t.prologue %d\n",
7516 alpha_function_needs_gp || current_function_is_thunk);
a6f12d7c
RK		 7517}
7518
7519/* Write function epilogue. */
7520
6abc6f40
RH		 7521/* ??? At some point we will want to support full unwind, and so will
7522 need to mark the epilogue as well. At the moment, we just confuse
7523 dwarf2out. */
7524#undef FRP
7525#define FRP(exp) exp
7526
a6f12d7c 7527void
9c0e94a5 7528alpha_expand_epilogue ()
a6f12d7c 7529{
9c0e94a5
RH		 7530 /* Registers to save. */
7531 unsigned long imask = 0;
7532 unsigned long fmask = 0;
7533 /* Stack space needed for pushing registers clobbered by us. */
7534 HOST_WIDE_INT sa_size;
7535 /* Complete stack size needed. */
7536 HOST_WIDE_INT frame_size;
7537 /* Offset from base reg to register save area. */
7538 HOST_WIDE_INT reg_offset;
7539 int fp_is_frame_pointer, fp_offset;
7540 rtx sa_reg, sa_reg_exp = NULL;
3873d24b 7541 rtx sp_adj1, sp_adj2, mem;
01439aee 7542 rtx eh_ofs;
a6f12d7c
RK		 7543 int i;
7544
9c0e94a5 7545 sa_size = alpha_sa_size ();
a6f12d7c 7546
9c0e94a5 7547 frame_size = get_frame_size ();
be7b80f4 7548 if (TARGET_ABI_OPEN_VMS)
9c0e94a5 7549 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7550 + (alpha_procedure_type == PT_STACK ? 8 : 0)
9c0e94a5
RH		 7551 + frame_size
7552 + current_function_pretend_args_size);
30102605
RH		 7553 else if (TARGET_ABI_UNICOSMK)
7554 frame_size = ALPHA_ROUND (sa_size
c2ea1ac6 7555 + (alpha_procedure_type == PT_STACK ? 48 : 0))
30102605
RH		 7556 + ALPHA_ROUND (frame_size
7557 + current_function_outgoing_args_size);
9c0e94a5
RH		 7558 else
7559 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7560 + sa_size
7561 + ALPHA_ROUND (frame_size
7562 + current_function_pretend_args_size));
a6f12d7c 7563
be7b80f4 7564 if (TARGET_ABI_OPEN_VMS)
c2ea1ac6
DR		 7565 {
7566 if (alpha_procedure_type == PT_STACK)
7567 reg_offset = 8;
7568 else
7569 reg_offset = 0;
7570 }
9c0e94a5
RH		 7571 else
7572 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7573
7574 alpha_sa_mask (&imask, &fmask);
7575
c2ea1ac6
DR		 7576 fp_is_frame_pointer
7577 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7578 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
c8d8ed65
RK		 7579 fp_offset = 0;
7580 sa_reg = stack_pointer_rtx;
9c0e94a5 7581
4573b4de
RH		 7582 if (current_function_calls_eh_return)
7583 eh_ofs = EH_RETURN_STACKADJ_RTX;
7584 else
7585 eh_ofs = NULL_RTX;
7586
30102605 7587 if (!TARGET_ABI_UNICOSMK && sa_size)
9c0e94a5
RH		 7588 {
7589 /* If we have a frame pointer, restore SP from it. */
be7b80f4 7590 if ((TARGET_ABI_OPEN_VMS
9c0e94a5 7591 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
be7b80f4 7592 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
8207e7c6 7593 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
0d24ff5d 7594
9c0e94a5 7595 /* Cope with very large offsets to the register save area. */
9c0e94a5 7596 if (reg_offset + sa_size > 0x8000)
a6f12d7c 7597 {
9c0e94a5
RH		 7598 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7599 HOST_WIDE_INT bias;
7600
7601 if (low + sa_size <= 0x8000)
7602 bias = reg_offset - low, reg_offset = low;
7603 else
7604 bias = reg_offset, reg_offset = 0;
7605
7606 sa_reg = gen_rtx_REG (DImode, 22);
7607 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7608
6abc6f40 7609 FRP (emit_move_insn (sa_reg, sa_reg_exp));
a6f12d7c 7610 }
9c0e94a5 7611
285a5742 7612 /* Restore registers in order, excepting a true frame pointer. */
a6f12d7c 7613
4573b4de 7614 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
01439aee 7615 if (! eh_ofs)
ba4828e0 7616 set_mem_alias_set (mem, alpha_sr_alias_set);
4573b4de
RH		 7617 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7618
9c0e94a5
RH		 7619 reg_offset += 8;
7620 imask &= ~(1L << REG_RA);
0f33506c 7621
9c0e94a5
RH		 7622 for (i = 0; i < 32; ++i)
7623 if (imask & (1L << i))
a6f12d7c 7624 {
9c0e94a5 7625 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
0f33506c
RK		 7626 fp_offset = reg_offset;
7627 else
9c0e94a5 7628 {
3873d24b 7629 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
ba4828e0 7630 set_mem_alias_set (mem, alpha_sr_alias_set);
3873d24b 7631 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
9c0e94a5 7632 }
a6f12d7c
RK		 7633 reg_offset += 8;
7634 }
7635
9c0e94a5
RH		 7636 for (i = 0; i < 32; ++i)
7637 if (fmask & (1L << i))
a6f12d7c 7638 {
3873d24b 7639 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
ba4828e0 7640 set_mem_alias_set (mem, alpha_sr_alias_set);
3873d24b 7641 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
a6f12d7c
RK		 7642 reg_offset += 8;
7643 }
9c0e94a5 7644 }
c2ea1ac6 7645 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
30102605
RH		 7646 {
7647 /* Restore callee-saved general-purpose registers. */
7648
7649 reg_offset = -56;
7650
7651 for (i = 9; i < 15; i++)
7652 if (imask & (1L << i))
7653 {
7654 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7655 reg_offset));
7656 set_mem_alias_set (mem, alpha_sr_alias_set);
7657 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7658 reg_offset -= 8;
7659 }
7660
7661 for (i = 2; i < 10; i++)
7662 if (fmask & (1L << i))
7663 {
7664 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7665 reg_offset));
7666 set_mem_alias_set (mem, alpha_sr_alias_set);
7667 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7668 reg_offset -= 8;
7669 }
7670
7671 /* Restore the return address from the DSIB. */
7672
7673 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7674 set_mem_alias_set (mem, alpha_sr_alias_set);
7675 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7676 }
a6f12d7c 7677
01439aee 7678 if (frame_size || eh_ofs)
9c0e94a5 7679 {
71038426
RH		 7680 sp_adj1 = stack_pointer_rtx;
7681
01439aee 7682 if (eh_ofs)
71038426
RH		 7683 {
7684 sp_adj1 = gen_rtx_REG (DImode, 23);
7685 emit_move_insn (sp_adj1,
01439aee 7686 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
71038426
RH		 7687 }
7688
9c0e94a5
RH		 7689 /* If the stack size is large, begin computation into a temporary
7690 register so as not to interfere with a potential fp restore,
7691 which must be consecutive with an SP restore. */
30102605
RH		 7692 if (frame_size < 32768
7693 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
71038426 7694 sp_adj2 = GEN_INT (frame_size);
30102605
RH		 7695 else if (TARGET_ABI_UNICOSMK)
7696 {
7697 sp_adj1 = gen_rtx_REG (DImode, 23);
7698 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7699 sp_adj2 = const0_rtx;
7700 }
9c0e94a5
RH		 7701 else if (frame_size < 0x40007fffL)
7702 {
7703 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7704
71038426 7705 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
9c0e94a5
RH		 7706 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7707 sp_adj1 = sa_reg;
7708 else
7709 {
7710 sp_adj1 = gen_rtx_REG (DImode, 23);
6abc6f40 7711 FRP (emit_move_insn (sp_adj1, sp_adj2));
9c0e94a5
RH		 7712 }
7713 sp_adj2 = GEN_INT (low);
7714 }
d60a05a1 7715 else
9c0e94a5 7716 {
71038426
RH		 7717 rtx tmp = gen_rtx_REG (DImode, 23);
7718 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7719 if (!sp_adj2)
9c0e94a5
RH		 7720 {
7721 /* We can't drop new things to memory this late, afaik,
7722 so build it up by pieces. */
3fe5612d
RH		 7723 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7724 -(frame_size < 0)));
71038426 7725 if (!sp_adj2)
9c0e94a5 7726 abort ();
9c0e94a5 7727 }
9c0e94a5 7728 }
a6f12d7c 7729
9c0e94a5
RH		 7730 /* From now on, things must be in order. So emit blockages. */
7731
7732 /* Restore the frame pointer. */
30102605
RH		 7733 if (TARGET_ABI_UNICOSMK)
7734 {
7735 emit_insn (gen_blockage ());
7736 mem = gen_rtx_MEM (DImode,
7737 plus_constant (hard_frame_pointer_rtx, -16));
7738 set_mem_alias_set (mem, alpha_sr_alias_set);
7739 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7740 }
7741 else if (fp_is_frame_pointer)
9c0e94a5
RH		 7742 {
7743 emit_insn (gen_blockage ());
8207e7c6 7744 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
ba4828e0 7745 set_mem_alias_set (mem, alpha_sr_alias_set);
3873d24b 7746 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
9c0e94a5 7747 }
be7b80f4 7748 else if (TARGET_ABI_OPEN_VMS)
9c0e94a5
RH		 7749 {
7750 emit_insn (gen_blockage ());
6abc6f40
RH		 7751 FRP (emit_move_insn (hard_frame_pointer_rtx,
7752 gen_rtx_REG (DImode, vms_save_fp_regno)));
9c0e94a5
RH		 7753 }
7754
7755 /* Restore the stack pointer. */
7756 emit_insn (gen_blockage ());
30102605
RH		 7757 if (sp_adj2 == const0_rtx)
7758 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7759 else
7760 FRP (emit_move_insn (stack_pointer_rtx,
7761 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
9c0e94a5
RH		 7762 }
7763 else
7764 {
c2ea1ac6 7765 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
9c0e94a5
RH		 7766 {
7767 emit_insn (gen_blockage ());
6abc6f40
RH		 7768 FRP (emit_move_insn (hard_frame_pointer_rtx,
7769 gen_rtx_REG (DImode, vms_save_fp_regno)));
9c0e94a5 7770 }
c2ea1ac6 7771 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
30102605
RH		 7772 {
7773 /* Decrement the frame pointer if the function does not have a
7774 frame. */
7775
7776 emit_insn (gen_blockage ());
7777 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7778 hard_frame_pointer_rtx, GEN_INT (-1))));
7779 }
a6f12d7c 7780 }
9c0e94a5 7781}
1330f7d5
DR		 7782\f
7783#if TARGET_ABI_OPEN_VMS
7784#include <splay-tree.h>
7785
7786/* Structure to collect function names for final output
7787 in link section. */
7788
7789enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
7790enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
7791
7792struct alpha_funcs
7793{
7794 int num;
7795 splay_tree links;
7796};
7797
7798struct alpha_links
7799{
7800 int num;
7801 rtx linkage;
7802 enum links_kind lkind;
7803 enum reloc_kind rkind;
7804};
7805
7806static splay_tree alpha_funcs_tree;
7807static splay_tree alpha_links_tree;
7808
7809static int mark_alpha_links_node PARAMS ((splay_tree_node, void *));
7810static void mark_alpha_links PARAMS ((void *));
7811static int alpha_write_one_linkage PARAMS ((splay_tree_node, void *));
7812
7813static int alpha_funcs_num;
7814#endif
9c0e94a5
RH		 7815
7816/* Output the rest of the textual info surrounding the epilogue. */
7817
7818void
acd92049 7819alpha_end_function (file, fnname, decl)
9c0e94a5 7820 FILE *file;
e03c5670 7821 const char *fnname;
23626154 7822 tree decl;
9c0e94a5 7823{
a6f12d7c 7824 /* End the function. */
30102605 7825 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
33d01c33 7826 {
9c0e94a5 7827 fputs ("\t.end ", file);
acd92049 7828 assemble_name (file, fnname);
9c0e94a5 7829 putc ('\n', file);
33d01c33 7830 }
48f6bfac 7831 inside_function = FALSE;
9973f4a2 7832
1330f7d5
DR		 7833#if TARGET_ABI_OPEN_VMS
7834 alpha_write_linkage (file, fnname, decl);
7835#endif
7836
23626154 7837 /* Show that we know this function if it is called again.
60593797 7838
23626154 7839 Do this only for functions whose symbols bind locally.
62918bd3
RH		 7840
7841 Don't do this for functions not defined in the .text section, as
7842 otherwise it's not unlikely that the destination is out of range
7843 for a direct branch. */
60593797 7844
23626154
RH		 7845 if ((*targetm.binds_local_p) (decl) && decl_in_text_section (decl))
7846 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
30102605
RH		 7847
7848 /* Output jump tables and the static subroutine information block. */
7849 if (TARGET_ABI_UNICOSMK)
7850 {
7851 unicosmk_output_ssib (file, fnname);
7852 unicosmk_output_deferred_case_vectors (file);
7853 }
a6f12d7c 7854}
14691f8d
RH		 7855
7856/* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7857
7858 In order to avoid the hordes of differences between generated code
7859 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7860 lots of code loading up large constants, generate rtl and emit it
7861 instead of going straight to text.
7862
7863 Not sure why this idea hasn't been explored before... */
7864
7865void
7866alpha_output_mi_thunk_osf (file, thunk_fndecl, delta, function)
7867 FILE *file;
7868 tree thunk_fndecl ATTRIBUTE_UNUSED;
7869 HOST_WIDE_INT delta;
7870 tree function;
7871{
7872 HOST_WIDE_INT hi, lo;
7873 rtx this, insn, funexp;
7874
7875 /* We always require a valid GP. */
7876 emit_insn (gen_prologue_ldgp ());
7877 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
7878
7879 /* Find the "this" pointer. If the function returns a structure,
7880 the structure return pointer is in $16. */
7881 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
7882 this = gen_rtx_REG (Pmode, 17);
7883 else
7884 this = gen_rtx_REG (Pmode, 16);
7885
7886 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7887 entire constant for the add. */
7888 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7889 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7890 if (hi + lo == delta)
7891 {
7892 if (hi)
7893 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7894 if (lo)
7895 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7896 }
7897 else
7898 {
7899 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7900 delta, -(delta < 0));
7901 emit_insn (gen_adddi3 (this, this, tmp));
7902 }
7903
7904 /* Generate a tail call to the target function. */
7905 if (! TREE_USED (function))
7906 {
7907 assemble_external (function);
7908 TREE_USED (function) = 1;
7909 }
7910 funexp = XEXP (DECL_RTL (function), 0);
7911 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7912 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7913 SIBLING_CALL_P (insn) = 1;
7914
7915 /* Run just enough of rest_of_compilation to get the insns emitted.
7916 There's not really enough bulk here to make other passes such as
7917 instruction scheduling worth while. Note that use_thunk calls
7918 assemble_start_function and assemble_end_function. */
7919 insn = get_insns ();
7920 shorten_branches (insn);
7921 final_start_function (insn, file, 1);
7922 final (insn, file, 1, 0);
7923 final_end_function ();
7924}
48f6bfac
RK		 7925\f
7926/* Debugging support. */
7927
7928#include "gstab.h"
7929
7930/* Count the number of sdb related labels are generated (to find block
7931 start and end boundaries). */
7932
7933int sdb_label_count = 0;
7934
7935/* Next label # for each statement. */
7936
7937static int sym_lineno = 0;
7938
7939/* Count the number of .file directives, so that .loc is up to date. */
7940
7941static int num_source_filenames = 0;
7942
7943/* Name of the file containing the current function. */
7944
df45c7ea 7945static const char *current_function_file = "";
48f6bfac
RK		 7946
7947/* Offsets to alpha virtual arg/local debugging pointers. */
7948
7949long alpha_arg_offset;
7950long alpha_auto_offset;
7951\f
7952/* Emit a new filename to a stream. */
7953
7954void
7955alpha_output_filename (stream, name)
7956 FILE *stream;
aa388f29 7957 const char *name;
48f6bfac
RK		 7958{
7959 static int first_time = TRUE;
7960 char ltext_label_name[100];
7961
7962 if (first_time)
7963 {
7964 first_time = FALSE;
7965 ++num_source_filenames;
7966 current_function_file = name;
7967 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7968 output_quoted_string (stream, name);
7969 fprintf (stream, "\n");
7970 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
7971 fprintf (stream, "\t#@stabs\n");
7972 }
7973
6af601b3 7974 else if (write_symbols == DBX_DEBUG)
48f6bfac
RK		 7975 {
7976 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
8202cda0 7977 fprintf (stream, "%s", ASM_STABS_OP);
48f6bfac
RK		 7978 output_quoted_string (stream, name);
7979 fprintf (stream, ",%d,0,0,%s\n", N_SOL, &ltext_label_name[1]);
7980 }
7981
7982 else if (name != current_function_file
5665caa2 7983 && strcmp (name, current_function_file) != 0)
48f6bfac
RK		 7984 {
7985 if (inside_function && ! TARGET_GAS)
7986 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
7987 else
7988 {
7989 ++num_source_filenames;
7990 current_function_file = name;
7991 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7992 }
7993
7994 output_quoted_string (stream, name);
7995 fprintf (stream, "\n");
7996 }
7997}
7998\f
7999/* Emit a linenumber to a stream. */
8000
8001void
8002alpha_output_lineno (stream, line)
8003 FILE *stream;
8004 int line;
8005{
6af601b3 8006 if (write_symbols == DBX_DEBUG)
48f6bfac
RK		 8007 {
8008 /* mips-tfile doesn't understand .stabd directives. */
8009 ++sym_lineno;
8202cda0 8010 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
48f6bfac
RK		 8011 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8012 }
8013 else
40828e35 8014 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
48f6bfac 8015}
6245e3df
RK		 8016\f
8017/* Structure to show the current status of registers and memory. */
8018
8019struct shadow_summary
8020{
8021 struct {
1d11bf18
RH		 8022 unsigned int i : 31; /* Mask of int regs */
8023 unsigned int fp : 31; /* Mask of fp regs */
8024 unsigned int mem : 1; /* mem == imem | fpmem */
6245e3df
RK		 8025 } used, defd;
8026};
8027
f6da8bc3
KG		 8028static void summarize_insn PARAMS ((rtx, struct shadow_summary *, int));
8029static void alpha_handle_trap_shadows PARAMS ((rtx));
9c0e94a5 8030
6245e3df
RK		 8031/* Summary the effects of expression X on the machine. Update SUM, a pointer
8032 to the summary structure. SET is nonzero if the insn is setting the
8033 object, otherwise zero. */
8034
8035static void
8036summarize_insn (x, sum, set)
8037 rtx x;
8038 struct shadow_summary *sum;
8039 int set;
8040{
6f7d635c 8041 const char *format_ptr;
6245e3df
RK		 8042 int i, j;
8043
8044 if (x == 0)
8045 return;
8046
8047 switch (GET_CODE (x))
8048 {
8049 /* ??? Note that this case would be incorrect if the Alpha had a
8050 ZERO_EXTRACT in SET_DEST. */
8051 case SET:
8052 summarize_insn (SET_SRC (x), sum, 0);
8053 summarize_insn (SET_DEST (x), sum, 1);
8054 break;
8055
8056 case CLOBBER:
8057 summarize_insn (XEXP (x, 0), sum, 1);
8058 break;
8059
8060 case USE:
8061 summarize_insn (XEXP (x, 0), sum, 0);
8062 break;
8063
f4e31cf5
RH		 8064 case ASM_OPERANDS:
8065 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8066 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8067 break;
8068
6245e3df 8069 case PARALLEL:
8fed04e5 8070 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
6245e3df
RK		 8071 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8072 break;
8073
f4e31cf5 8074 case SUBREG:
9c0e94a5
RH		 8075 summarize_insn (SUBREG_REG (x), sum, 0);
8076 break;
f4e31cf5 8077
6245e3df
RK		 8078 case REG:
8079 {
8080 int regno = REGNO (x);
948068e2 8081 unsigned long mask = ((unsigned long) 1) << (regno % 32);
6245e3df
RK		 8082
8083 if (regno == 31 || regno == 63)
8084 break;
8085
8086 if (set)
8087 {
8088 if (regno < 32)
8089 sum->defd.i |= mask;
8090 else
8091 sum->defd.fp |= mask;
8092 }
8093 else
8094 {
8095 if (regno < 32)
8096 sum->used.i |= mask;
8097 else
8098 sum->used.fp |= mask;
8099 }
8100 }
8101 break;
8102
8103 case MEM:
8104 if (set)
8105 sum->defd.mem = 1;
8106 else
8107 sum->used.mem = 1;
8108
8109 /* Find the regs used in memory address computation: */
8110 summarize_insn (XEXP (x, 0), sum, 0);
8111 break;
8112
8ba46994
RK		 8113 case CONST_INT: case CONST_DOUBLE:
8114 case SYMBOL_REF: case LABEL_REF: case CONST:
368a1647 8115 case SCRATCH: case ASM_INPUT:
8ba46994
RK		 8116 break;
8117
6245e3df
RK		 8118 /* Handle common unary and binary ops for efficiency. */
8119 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8120 case MOD: case UDIV: case UMOD: case AND: case IOR:
8121 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8122 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8123 case NE: case EQ: case GE: case GT: case LE:
8124 case LT: case GEU: case GTU: case LEU: case LTU:
8125 summarize_insn (XEXP (x, 0), sum, 0);
8126 summarize_insn (XEXP (x, 1), sum, 0);
8127 break;
8128
8129 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8130 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8131 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8132 case SQRT: case FFS:
8133 summarize_insn (XEXP (x, 0), sum, 0);
8134 break;
8135
8136 default:
8137 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8fed04e5 8138 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
bed95fa1 8139 switch (format_ptr[i])
6245e3df
RK		 8140 {
8141 case 'e':
8142 summarize_insn (XEXP (x, i), sum, 0);
8143 break;
8144
8145 case 'E':
8fed04e5 8146 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6245e3df
RK		 8147 summarize_insn (XVECEXP (x, i, j), sum, 0);
8148 break;
8149
2b01d264
RH		 8150 case 'i':
8151 break;
8152
6245e3df
RK		 8153 default:
8154 abort ();
8155 }
8156 }
8157}
6245e3df 8158
9c0e94a5
RH		 8159/* Ensure a sufficient number of `trapb' insns are in the code when
8160 the user requests code with a trap precision of functions or
8161 instructions.
8162
8163 In naive mode, when the user requests a trap-precision of
8164 "instruction", a trapb is needed after every instruction that may
8165 generate a trap. This ensures that the code is resumption safe but
8166 it is also slow.
8167
8168 When optimizations are turned on, we delay issuing a trapb as long
8169 as possible. In this context, a trap shadow is the sequence of
8170 instructions that starts with a (potentially) trap generating
8171 instruction and extends to the next trapb or call_pal instruction
8172 (but GCC never generates call_pal by itself). We can delay (and
8173 therefore sometimes omit) a trapb subject to the following
8174 conditions:
8175
8176 (a) On entry to the trap shadow, if any Alpha register or memory
8177 location contains a value that is used as an operand value by some
8178 instruction in the trap shadow (live on entry), then no instruction
8179 in the trap shadow may modify the register or memory location.
8180
8181 (b) Within the trap shadow, the computation of the base register
8182 for a memory load or store instruction may not involve using the
8183 result of an instruction that might generate an UNPREDICTABLE
8184 result.
8185
8186 (c) Within the trap shadow, no register may be used more than once
8187 as a destination register. (This is to make life easier for the
8188 trap-handler.)
6245e3df 8189
2ea844d3 8190 (d) The trap shadow may not include any branch instructions. */
6245e3df 8191
2ea844d3
RH		 8192static void
8193alpha_handle_trap_shadows (insns)
8194 rtx insns;
6245e3df 8195{
2ea844d3
RH		 8196 struct shadow_summary shadow;
8197 int trap_pending, exception_nesting;
68aed21b 8198 rtx i, n;
6245e3df 8199
2ea844d3
RH		 8200 trap_pending = 0;
8201 exception_nesting = 0;
8202 shadow.used.i = 0;
8203 shadow.used.fp = 0;
8204 shadow.used.mem = 0;
8205 shadow.defd = shadow.used;
8206
8207 for (i = insns; i ; i = NEXT_INSN (i))
8208 {
8209 if (GET_CODE (i) == NOTE)
8210 {
8211 switch (NOTE_LINE_NUMBER (i))
8212 {
8213 case NOTE_INSN_EH_REGION_BEG:
8214 exception_nesting++;
8215 if (trap_pending)
8216 goto close_shadow;
8217 break;
8218
8219 case NOTE_INSN_EH_REGION_END:
8220 exception_nesting--;
8221 if (trap_pending)
8222 goto close_shadow;
8223 break;
8224
8225 case NOTE_INSN_EPILOGUE_BEG:
8226 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8227 goto close_shadow;
8228 break;
8229 }
8230 }
8231 else if (trap_pending)
8232 {
8233 if (alpha_tp == ALPHA_TP_FUNC)
8234 {
8235 if (GET_CODE (i) == JUMP_INSN
8236 && GET_CODE (PATTERN (i)) == RETURN)
8237 goto close_shadow;
8238 }
8239 else if (alpha_tp == ALPHA_TP_INSN)
8240 {
8241 if (optimize > 0)
8242 {
8243 struct shadow_summary sum;
8244
8245 sum.used.i = 0;
8246 sum.used.fp = 0;
8247 sum.used.mem = 0;
f4e31cf5 8248 sum.defd = sum.used;
2ea844d3
RH		 8249
8250 switch (GET_CODE (i))
8251 {
8252 case INSN:
bb02e7ea
RH		 8253 /* Annoyingly, get_attr_trap will abort on these. */
8254 if (GET_CODE (PATTERN (i)) == USE
8255 || GET_CODE (PATTERN (i)) == CLOBBER)
2ea844d3
RH		 8256 break;
8257
8258 summarize_insn (PATTERN (i), &sum, 0);
8259
8260 if ((sum.defd.i & shadow.defd.i)
8261 || (sum.defd.fp & shadow.defd.fp))
8262 {
8263 /* (c) would be violated */
8264 goto close_shadow;
8265 }
8266
8267 /* Combine shadow with summary of current insn: */
8268 shadow.used.i |= sum.used.i;
8269 shadow.used.fp |= sum.used.fp;
8270 shadow.used.mem |= sum.used.mem;
8271 shadow.defd.i |= sum.defd.i;
8272 shadow.defd.fp |= sum.defd.fp;
8273 shadow.defd.mem |= sum.defd.mem;
8274
8275 if ((sum.defd.i & shadow.used.i)
8276 || (sum.defd.fp & shadow.used.fp)
8277 || (sum.defd.mem & shadow.used.mem))
8278 {
8279 /* (a) would be violated (also takes care of (b)) */
8280 if (get_attr_trap (i) == TRAP_YES
8281 && ((sum.defd.i & sum.used.i)
8282 || (sum.defd.fp & sum.used.fp)))
8283 abort ();
8284
8285 goto close_shadow;
8286 }
8287 break;
8288
8289 case JUMP_INSN:
8290 case CALL_INSN:
8291 case CODE_LABEL:
8292 goto close_shadow;
8293
8294 default:
6245e3df 8295 abort ();
2ea844d3
RH		 8296 }
8297 }
8298 else
8299 {
8300 close_shadow:
68aed21b
RH		 8301 n = emit_insn_before (gen_trapb (), i);
8302 PUT_MODE (n, TImode);
8303 PUT_MODE (i, TImode);
2ea844d3
RH		 8304 trap_pending = 0;
8305 shadow.used.i = 0;
8306 shadow.used.fp = 0;
8307 shadow.used.mem = 0;
8308 shadow.defd = shadow.used;
8309 }
8310 }
8311 }
6245e3df 8312
4f3f5e9f
RH		 8313 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8314 && GET_CODE (i) == INSN
8315 && GET_CODE (PATTERN (i)) != USE
8316 && GET_CODE (PATTERN (i)) != CLOBBER
8317 && get_attr_trap (i) == TRAP_YES)
8318 {
8319 if (optimize && !trap_pending)
8320 summarize_insn (PATTERN (i), &shadow, 0);
8321 trap_pending = 1;
8322 }
6245e3df
RK		 8323 }
8324}
68aed21b 8325\f
68aed21b
RH		 8326/* Alpha can only issue instruction groups simultaneously if they are
8327 suitibly aligned. This is very processor-specific. */
8328
3873d24b
RH		 8329enum alphaev4_pipe {
8330 EV4_STOP = 0,
8331 EV4_IB0 = 1,
8332 EV4_IB1 = 2,
8333 EV4_IBX = 4
8334};
8335
68aed21b
RH		 8336enum alphaev5_pipe {
8337 EV5_STOP = 0,
8338 EV5_NONE = 1,
8339 EV5_E01 = 2,
8340 EV5_E0 = 4,
8341 EV5_E1 = 8,
8342 EV5_FAM = 16,
8343 EV5_FA = 32,
8344 EV5_FM = 64
8345};
8346
f6da8bc3
KG		 8347static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx));
8348static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx));
b81f53a1
RK		 8349static rtx alphaev4_next_group PARAMS ((rtx, int *, int *));
8350static rtx alphaev5_next_group PARAMS ((rtx, int *, int *));
8351static rtx alphaev4_next_nop PARAMS ((int *));
8352static rtx alphaev5_next_nop PARAMS ((int *));
3873d24b
RH		 8353
8354static void alpha_align_insns
b81f53a1 8355 PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *)));
3873d24b
RH		 8356
8357static enum alphaev4_pipe
8358alphaev4_insn_pipe (insn)
8359 rtx insn;
8360{
8361 if (recog_memoized (insn) < 0)
8362 return EV4_STOP;
8363 if (get_attr_length (insn) != 4)
8364 return EV4_STOP;
8365
8366 switch (get_attr_type (insn))
8367 {
8368 case TYPE_ILD:
8369 case TYPE_FLD:
8370 return EV4_IBX;
8371
8372 case TYPE_LDSYM:
8373 case TYPE_IADD:
8374 case TYPE_ILOG:
8375 case TYPE_ICMOV:
8376 case TYPE_ICMP:
8377 case TYPE_IST:
8378 case TYPE_FST:
8379 case TYPE_SHIFT:
8380 case TYPE_IMUL:
8381 case TYPE_FBR:
8382 return EV4_IB0;
8383
8384 case TYPE_MISC:
8385 case TYPE_IBR:
8386 case TYPE_JSR:
d5909a79 8387 case TYPE_CALLPAL:
3873d24b
RH		 8388 case TYPE_FCPYS:
8389 case TYPE_FCMOV:
8390 case TYPE_FADD:
8391 case TYPE_FDIV:
8392 case TYPE_FMUL:
8393 return EV4_IB1;
8394
8395 default:
b81f53a1 8396 abort ();
3873d24b
RH		 8397 }
8398}
8399
68aed21b
RH		 8400static enum alphaev5_pipe
8401alphaev5_insn_pipe (insn)
8402 rtx insn;
8403{
8404 if (recog_memoized (insn) < 0)
8405 return EV5_STOP;
8406 if (get_attr_length (insn) != 4)
8407 return EV5_STOP;
8408
8409 switch (get_attr_type (insn))
8410 {
8411 case TYPE_ILD:
8412 case TYPE_FLD:
8413 case TYPE_LDSYM:
8414 case TYPE_IADD:
8415 case TYPE_ILOG:
8416 case TYPE_ICMOV:
8417 case TYPE_ICMP:
8418 return EV5_E01;
8419
8420 case TYPE_IST:
8421 case TYPE_FST:
8422 case TYPE_SHIFT:
8423 case TYPE_IMUL:
8424 case TYPE_MISC:
8425 case TYPE_MVI:
8426 return EV5_E0;
8427
8428 case TYPE_IBR:
8429 case TYPE_JSR:
d5909a79 8430 case TYPE_CALLPAL:
68aed21b
RH		 8431 return EV5_E1;
8432
8433 case TYPE_FCPYS:
8434 return EV5_FAM;
8435
8436 case TYPE_FBR:
8437 case TYPE_FCMOV:
8438 case TYPE_FADD:
8439 case TYPE_FDIV:
8440 return EV5_FA;
8441
8442 case TYPE_FMUL:
8443 return EV5_FM;
2c01018f
RH		 8444
8445 default:
8446 abort();
68aed21b 8447 }
68aed21b
RH		 8448}
8449
3873d24b
RH		 8450/* IN_USE is a mask of the slots currently filled within the insn group.
8451 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8452 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8453
8454 LEN is, of course, the length of the group in bytes. */
8455
8456static rtx
8457alphaev4_next_group (insn, pin_use, plen)
8458 rtx insn;
8459 int *pin_use, *plen;
8460{
8461 int len, in_use;
8462
8463 len = in_use = 0;
8464
2c3c49de 8465 if (! INSN_P (insn)
3873d24b
RH		 8466 || GET_CODE (PATTERN (insn)) == CLOBBER
8467 || GET_CODE (PATTERN (insn)) == USE)
8468 goto next_and_done;
8469
8470 while (1)
8471 {
8472 enum alphaev4_pipe pipe;
8473
8474 pipe = alphaev4_insn_pipe (insn);
8475 switch (pipe)
8476 {
8477 case EV4_STOP:
8478 /* Force complex instructions to start new groups. */
8479 if (in_use)
8480 goto done;
8481
8482 /* If this is a completely unrecognized insn, its an asm.
8483 We don't know how long it is, so record length as -1 to
8484 signal a needed realignment. */
8485 if (recog_memoized (insn) < 0)
8486 len = -1;
8487 else
8488 len = get_attr_length (insn);
8489 goto next_and_done;
8490
8491 case EV4_IBX:
8492 if (in_use & EV4_IB0)
8493 {
8494 if (in_use & EV4_IB1)
8495 goto done;
8496 in_use |= EV4_IB1;
8497 }
8498 else
8499 in_use |= EV4_IB0 | EV4_IBX;
8500 break;
8501
8502 case EV4_IB0:
8503 if (in_use & EV4_IB0)
8504 {
8505 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8506 goto done;
8507 in_use |= EV4_IB1;
8508 }
8509 in_use |= EV4_IB0;
8510 break;
8511
8512 case EV4_IB1:
8513 if (in_use & EV4_IB1)
8514 goto done;
8515 in_use |= EV4_IB1;
8516 break;
8517
8518 default:
8519 abort();
8520 }
8521 len += 4;
8522
8523 /* Haifa doesn't do well scheduling branches. */
8524 if (GET_CODE (insn) == JUMP_INSN)
8525 goto next_and_done;
8526
8527 next:
8528 insn = next_nonnote_insn (insn);
8529
2c3c49de 8530 if (!insn || ! INSN_P (insn))
3873d24b
RH		 8531 goto done;
8532
8533 /* Let Haifa tell us where it thinks insn group boundaries are. */
8534 if (GET_MODE (insn) == TImode)
8535 goto done;
8536
8537 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8538 goto next;
8539 }
8540
8541 next_and_done:
8542 insn = next_nonnote_insn (insn);
8543
8544 done:
8545 *plen = len;
8546 *pin_use = in_use;
8547 return insn;
8548}
8549
8550/* IN_USE is a mask of the slots currently filled within the insn group.
8551 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8552 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
68aed21b
RH		 8553
8554 LEN is, of course, the length of the group in bytes. */
8555
8556static rtx
8557alphaev5_next_group (insn, pin_use, plen)
8558 rtx insn;
8559 int *pin_use, *plen;
8560{
8561 int len, in_use;
8562
8563 len = in_use = 0;
8564
2c3c49de 8565 if (! INSN_P (insn)
2c01018f
RH		 8566 || GET_CODE (PATTERN (insn)) == CLOBBER
8567 || GET_CODE (PATTERN (insn)) == USE)
8568 goto next_and_done;
68aed21b 8569
2c01018f 8570 while (1)
68aed21b
RH		 8571 {
8572 enum alphaev5_pipe pipe;
68aed21b
RH		 8573
8574 pipe = alphaev5_insn_pipe (insn);
8575 switch (pipe)
8576 {
8577 case EV5_STOP:
8578 /* Force complex instructions to start new groups. */
8579 if (in_use)
8580 goto done;
8581
8582 /* If this is a completely unrecognized insn, its an asm.
8583 We don't know how long it is, so record length as -1 to
8584 signal a needed realignment. */
8585 if (recog_memoized (insn) < 0)
8586 len = -1;
8587 else
8588 len = get_attr_length (insn);
2c01018f 8589 goto next_and_done;
68aed21b
RH		 8590
8591 /* ??? Most of the places below, we would like to abort, as
8592 it would indicate an error either in Haifa, or in the
8593 scheduling description. Unfortunately, Haifa never
8594 schedules the last instruction of the BB, so we don't
8595 have an accurate TI bit to go off. */
8596 case EV5_E01:
8597 if (in_use & EV5_E0)
8598 {
8599 if (in_use & EV5_E1)
8600 goto done;
8601 in_use |= EV5_E1;
8602 }
8603 else
8604 in_use |= EV5_E0 | EV5_E01;
8605 break;
8606
8607 case EV5_E0:
8608 if (in_use & EV5_E0)
8609 {
3873d24b 8610 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
68aed21b
RH		 8611 goto done;
8612 in_use |= EV5_E1;
8613 }
8614 in_use |= EV5_E0;
8615 break;
8616
8617 case EV5_E1:
8618 if (in_use & EV5_E1)
8619 goto done;
8620 in_use |= EV5_E1;
8621 break;
8622
8623 case EV5_FAM:
8624 if (in_use & EV5_FA)
8625 {
8626 if (in_use & EV5_FM)
8627 goto done;
8628 in_use |= EV5_FM;
8629 }
8630 else
8631 in_use |= EV5_FA | EV5_FAM;
8632 break;
8633
8634 case EV5_FA:
8635 if (in_use & EV5_FA)
8636 goto done;
8637 in_use |= EV5_FA;
8638 break;
8639
8640 case EV5_FM:
8641 if (in_use & EV5_FM)
8642 goto done;
8643 in_use |= EV5_FM;
8644 break;
8645
8646 case EV5_NONE:
8647 break;
8648
8649 default:
8650 abort();
8651 }
8652 len += 4;
8653
8654 /* Haifa doesn't do well scheduling branches. */
8655 /* ??? If this is predicted not-taken, slotting continues, except
8656 that no more IBR, FBR, or JSR insns may be slotted. */
8657 if (GET_CODE (insn) == JUMP_INSN)
2c01018f 8658 goto next_and_done;
68aed21b 8659
2c01018f 8660 next:
68aed21b
RH		 8661 insn = next_nonnote_insn (insn);
8662
2c3c49de 8663 if (!insn || ! INSN_P (insn))
68aed21b 8664 goto done;
a874dd18 8665
68aed21b
RH		 8666 /* Let Haifa tell us where it thinks insn group boundaries are. */
8667 if (GET_MODE (insn) == TImode)
8668 goto done;
8669
2c01018f
RH		 8670 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8671 goto next;
68aed21b 8672 }
2c01018f
RH		 8673
8674 next_and_done:
8675 insn = next_nonnote_insn (insn);
68aed21b
RH		 8676
8677 done:
8678 *plen = len;
8679 *pin_use = in_use;
8680 return insn;
68aed21b
RH		 8681}
8682
3873d24b
RH		 8683static rtx
8684alphaev4_next_nop (pin_use)
8685 int *pin_use;
8686{
8687 int in_use = *pin_use;
8688 rtx nop;
8689
8690 if (!(in_use & EV4_IB0))
8691 {
8692 in_use |= EV4_IB0;
8693 nop = gen_nop ();
8694 }
8695 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8696 {
8697 in_use |= EV4_IB1;
8698 nop = gen_nop ();
8699 }
8700 else if (TARGET_FP && !(in_use & EV4_IB1))
8701 {
8702 in_use |= EV4_IB1;
8703 nop = gen_fnop ();
8704 }
8705 else
8706 nop = gen_unop ();
8707
8708 *pin_use = in_use;
8709 return nop;
8710}
8711
8712static rtx
8713alphaev5_next_nop (pin_use)
8714 int *pin_use;
8715{
8716 int in_use = *pin_use;
8717 rtx nop;
8718
8719 if (!(in_use & EV5_E1))
8720 {
8721 in_use |= EV5_E1;
8722 nop = gen_nop ();
8723 }
8724 else if (TARGET_FP && !(in_use & EV5_FA))
8725 {
8726 in_use |= EV5_FA;
8727 nop = gen_fnop ();
8728 }
8729 else if (TARGET_FP && !(in_use & EV5_FM))
8730 {
8731 in_use |= EV5_FM;
8732 nop = gen_fnop ();
8733 }
8734 else
8735 nop = gen_unop ();
8736
8737 *pin_use = in_use;
8738 return nop;
8739}
8740
8741/* The instruction group alignment main loop. */
8742
68aed21b 8743static void
b81f53a1 8744alpha_align_insns (insns, max_align, next_group, next_nop)
68aed21b 8745 rtx insns;
b81f53a1
RK		 8746 unsigned int max_align;
8747 rtx (*next_group) PARAMS ((rtx, int *, int *));
8748 rtx (*next_nop) PARAMS ((int *));
68aed21b
RH		 8749{
8750 /* ALIGN is the known alignment for the insn group. */
b81f53a1 8751 unsigned int align;
68aed21b
RH		 8752 /* OFS is the offset of the current insn in the insn group. */
8753 int ofs;
8754 int prev_in_use, in_use, len;
8755 rtx i, next;
8756
8757 /* Let shorten branches care for assigning alignments to code labels. */
8758 shorten_branches (insns);
8759
30864e14
RH		 8760 if (align_functions < 4)
8761 align = 4;
21cb9e60 8762 else if ((unsigned int) align_functions < max_align)
30864e14
RH		 8763 align = align_functions;
8764 else
8765 align = max_align;
80db34d8 8766
68aed21b 8767 ofs = prev_in_use = 0;
68aed21b
RH		 8768 i = insns;
8769 if (GET_CODE (i) == NOTE)
8770 i = next_nonnote_insn (i);
8771
8772 while (i)
8773 {
b81f53a1 8774 next = (*next_group) (i, &in_use, &len);
68aed21b
RH		 8775
8776 /* When we see a label, resync alignment etc. */
8777 if (GET_CODE (i) == CODE_LABEL)
8778 {
b81f53a1
RK		 8779 unsigned int new_align = 1 << label_to_alignment (i);
8780
68aed21b
RH		 8781 if (new_align >= align)
8782 {
3873d24b 8783 align = new_align < max_align ? new_align : max_align;
68aed21b
RH		 8784 ofs = 0;
8785 }
b81f53a1 8786
68aed21b
RH		 8787 else if (ofs & (new_align-1))
8788 ofs = (ofs | (new_align-1)) + 1;
8789 if (len != 0)
8790 abort();
8791 }
8792
8793 /* Handle complex instructions special. */
8794 else if (in_use == 0)
8795 {
8796 /* Asms will have length < 0. This is a signal that we have
8797 lost alignment knowledge. Assume, however, that the asm
8798 will not mis-align instructions. */
8799 if (len < 0)
8800 {
8801 ofs = 0;
8802 align = 4;
8803 len = 0;
8804 }
8805 }
8806
8807 /* If the known alignment is smaller than the recognized insn group,
8808 realign the output. */
1eb356b9 8809 else if ((int) align < len)
68aed21b 8810 {
b81f53a1 8811 unsigned int new_log_align = len > 8 ? 4 : 3;
11cb1475 8812 rtx prev, where;
68aed21b 8813
11cb1475 8814 where = prev = prev_nonnote_insn (i);
68aed21b
RH		 8815 if (!where || GET_CODE (where) != CODE_LABEL)
8816 where = i;
8817
11cb1475
RH		 8818 /* Can't realign between a call and its gp reload. */
8819 if (! (TARGET_EXPLICIT_RELOCS
8820 && prev && GET_CODE (prev) == CALL_INSN))
8821 {
8822 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8823 align = 1 << new_log_align;
8824 ofs = 0;
8825 }
68aed21b
RH		 8826 }
8827
8828 /* If the group won't fit in the same INT16 as the previous,
8829 we need to add padding to keep the group together. Rather
8830 than simply leaving the insn filling to the assembler, we
8831 can make use of the knowledge of what sorts of instructions
8832 were issued in the previous group to make sure that all of
8833 the added nops are really free. */
1eb356b9 8834 else if (ofs + len > (int) align)
68aed21b
RH		 8835 {
8836 int nop_count = (align - ofs) / 4;
8837 rtx where;
8838
11cb1475
RH		 8839 /* Insert nops before labels, branches, and calls to truely merge
8840 the execution of the nops with the previous instruction group. */
68aed21b 8841 where = prev_nonnote_insn (i);
3873d24b 8842 if (where)
68aed21b 8843 {
3873d24b 8844 if (GET_CODE (where) == CODE_LABEL)
68aed21b 8845 {
3873d24b
RH		 8846 rtx where2 = prev_nonnote_insn (where);
8847 if (where2 && GET_CODE (where2) == JUMP_INSN)
8848 where = where2;
68aed21b 8849 }
11cb1475 8850 else if (GET_CODE (where) == INSN)
3873d24b 8851 where = i;
68aed21b 8852 }
3873d24b
RH		 8853 else
8854 where = i;
8855
8856 do
8857 emit_insn_before ((*next_nop)(&prev_in_use), where);
68aed21b
RH		 8858 while (--nop_count);
8859 ofs = 0;
8860 }
8861
8862 ofs = (ofs + len) & (align - 1);
8863 prev_in_use = in_use;
8864 i = next;
8865 }
8866}
68aed21b 8867\f
f5143c46 8868/* Machine dependent reorg pass. */
2ea844d3
RH		 8869
8870void
8871alpha_reorg (insns)
8872 rtx insns;
8873{
68aed21b
RH		 8874 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8875 alpha_handle_trap_shadows (insns);
8876
68aed21b
RH		 8877 /* Due to the number of extra trapb insns, don't bother fixing up
8878 alignment when trap precision is instruction. Moreover, we can
b81f53a1 8879 only do our job when sched2 is run. */
68aed21b
RH		 8880 if (optimize && !optimize_size
8881 && alpha_tp != ALPHA_TP_INSN
8882 && flag_schedule_insns_after_reload)
8883 {
3873d24b 8884 if (alpha_cpu == PROCESSOR_EV4)
b81f53a1 8885 alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop);
3873d24b 8886 else if (alpha_cpu == PROCESSOR_EV5)
b81f53a1 8887 alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop);
68aed21b 8888 }
2ea844d3 8889}
2ea844d3 8890\f
b64a1b53
RH		 8891#ifdef OBJECT_FORMAT_ELF
8892
8893/* Switch to the section to which we should output X. The only thing
8894 special we do here is to honor small data. */
8895
8896static void
8897alpha_elf_select_rtx_section (mode, x, align)
8898 enum machine_mode mode;
8899 rtx x;
8900 unsigned HOST_WIDE_INT align;
8901{
8902 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8903 /* ??? Consider using mergable sdata sections. */
8904 sdata_section ();
8905 else
8906 default_elf_select_rtx_section (mode, x, align);
8907}
8908
8909#endif /* OBJECT_FORMAT_ELF */
8910\f
be7b80f4 8911#if TARGET_ABI_OPEN_VMS
89cfc2c6 8912
e9a25f70 8913/* Return the VMS argument type corresponding to MODE. */
89cfc2c6 8914
e9a25f70
JL		 8915enum avms_arg_type
8916alpha_arg_type (mode)
8917 enum machine_mode mode;
8918{
8919 switch (mode)
89cfc2c6 8920 {
e9a25f70
JL		 8921 case SFmode:
8922 return TARGET_FLOAT_VAX ? FF : FS;
8923 case DFmode:
8924 return TARGET_FLOAT_VAX ? FD : FT;
8925 default:
8926 return I64;
89cfc2c6 8927 }
e9a25f70 8928}
89cfc2c6 8929
e9a25f70
JL		 8930/* Return an rtx for an integer representing the VMS Argument Information
8931 register value. */
89cfc2c6 8932
aa388f29 8933rtx
e9a25f70
JL		 8934alpha_arg_info_reg_val (cum)
8935 CUMULATIVE_ARGS cum;
8936{
8937 unsigned HOST_WIDE_INT regval = cum.num_args;
8938 int i;
89cfc2c6 8939
e9a25f70
JL		 8940 for (i = 0; i < 6; i++)
8941 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
89cfc2c6 8942
e9a25f70
JL		 8943 return GEN_INT (regval);
8944}
8945\f
a82c7f05
RH		 8946/* Protect alpha_links from garbage collection. */
8947
8948static int
8949mark_alpha_links_node (node, data)
8950 splay_tree_node node;
8951 void *data ATTRIBUTE_UNUSED;
8952{
8953 struct alpha_links *links = (struct alpha_links *) node->value;
8954 ggc_mark_rtx (links->linkage);
8955 return 0;
8956}
8957
8958static void
8959mark_alpha_links (ptr)
8960 void *ptr;
8961{
8962 splay_tree tree = *(splay_tree *) ptr;
8963 splay_tree_foreach (tree, mark_alpha_links_node, NULL);
8964}
89cfc2c6
RK		 8965
8966/* Make (or fake) .linkage entry for function call.
8967
a82c7f05 8968 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
89cfc2c6 8969
a82c7f05
RH		 8970 Return an SYMBOL_REF rtx for the linkage. */
8971
8972rtx
89cfc2c6 8973alpha_need_linkage (name, is_local)
e03c5670 8974 const char *name;
89cfc2c6
RK		 8975 int is_local;
8976{
a82c7f05
RH		 8977 splay_tree_node node;
8978 struct alpha_links *al;
1330f7d5 8979 struct alpha_funcs *cfaf;
89cfc2c6
RK		 8980
8981 if (name[0] == '*')
8982 name++;
8983
1330f7d5
DR		 8984 if (is_local)
8985 {
8986 alpha_funcs_tree = splay_tree_new
8987 ((splay_tree_compare_fn) splay_tree_compare_pointers,
8988 (splay_tree_delete_key_fn) free,
8989 (splay_tree_delete_key_fn) free);
8990
8991 cfaf = (struct alpha_funcs *) xmalloc (sizeof (struct alpha_funcs));
8992
8993 cfaf->links = 0;
8994 cfaf->num = ++alpha_funcs_num;
8995
8996 splay_tree_insert (alpha_funcs_tree,
8997 (splay_tree_key) current_function_decl,
8998 (splay_tree_value) cfaf);
8999
9000 }
9001
9002 if (alpha_links_tree)
a82c7f05
RH		 9003 {
9004 /* Is this name already defined? */
89cfc2c6 9005
1330f7d5 9006 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
a82c7f05
RH		 9007 if (node)
9008 {
9009 al = (struct alpha_links *) node->value;
9010 if (is_local)
9011 {
9012 /* Defined here but external assumed. */
1330f7d5
DR		 9013 if (al->lkind == KIND_EXTERN)
9014 al->lkind = KIND_LOCAL;
a82c7f05
RH		 9015 }
9016 else
9017 {
9018 /* Used here but unused assumed. */
1330f7d5
DR		 9019 if (al->lkind == KIND_UNUSED)
9020 al->lkind = KIND_LOCAL;
a82c7f05
RH		 9021 }
9022 return al->linkage;
9023 }
9024 }
9025 else
9026 {
1330f7d5
DR		 9027 alpha_links_tree = splay_tree_new
9028 ((splay_tree_compare_fn) strcmp,
9029 (splay_tree_delete_key_fn) free,
9030 (splay_tree_delete_key_fn) free);
9031
9032 ggc_add_root (&alpha_links_tree, 1, 1, mark_alpha_links);
a82c7f05 9033 }
89cfc2c6 9034
a82c7f05
RH		 9035 al = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
9036 name = xstrdup (name);
89cfc2c6
RK		 9037
9038 /* Assume external if no definition. */
1330f7d5 9039 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
89cfc2c6 9040
a82c7f05 9041 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9398dc27
RK		 9042 get_identifier (name);
9043
a82c7f05
RH		 9044 /* Construct a SYMBOL_REF for us to call. */
9045 {
9046 size_t name_len = strlen (name);
520a57c8 9047 char *linksym = alloca (name_len + 6);
a82c7f05
RH		 9048 linksym[0] = '$';
9049 memcpy (linksym + 1, name, name_len);
9050 memcpy (linksym + 1 + name_len, "..lk", 5);
520a57c8
ZW		 9051 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9052 ggc_alloc_string (linksym, name_len + 5));
a82c7f05
RH		 9053 }
9054
1330f7d5 9055 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
a82c7f05 9056 (splay_tree_value) al);
89cfc2c6 9057
a82c7f05 9058 return al->linkage;
89cfc2c6
RK		 9059}
9060
1330f7d5
DR		 9061rtx
9062alpha_use_linkage (linkage, cfundecl, lflag, rflag)
9063 rtx linkage;
9064 tree cfundecl;
9065 int lflag;
9066 int rflag;
9067{
9068 splay_tree_node cfunnode;
9069 struct alpha_funcs *cfaf;
9070 struct alpha_links *al;
9071 const char *name = XSTR (linkage, 0);
9072
9073 cfaf = (struct alpha_funcs *) 0;
9074 al = (struct alpha_links *) 0;
9075
9076 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9077 cfaf = (struct alpha_funcs *) cfunnode->value;
9078
9079 if (cfaf->links)
9080 {
9081 splay_tree_node lnode;
9082
9083 /* Is this name already defined? */
9084
9085 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9086 if (lnode)
9087 al = (struct alpha_links *) lnode->value;
9088 }
9089 else
9090 {
9091 cfaf->links = splay_tree_new
9092 ((splay_tree_compare_fn) strcmp,
9093 (splay_tree_delete_key_fn) free,
9094 (splay_tree_delete_key_fn) free);
9095 ggc_add_root (&cfaf->links, 1, 1, mark_alpha_links);
9096 }
9097
9098 if (!al)
9099 {
9100 size_t name_len;
9101 size_t buflen;
9102 char buf [512];
9103 char *linksym;
9104 splay_tree_node node = 0;
9105 struct alpha_links *anl;
9106
9107 if (name[0] == '*')
9108 name++;
9109
9110 name_len = strlen (name);
9111
9112 al = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
9113 al->num = cfaf->num;
9114
9115 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9116 if (node)
9117 {
9118 anl = (struct alpha_links *) node->value;
9119 al->lkind = anl->lkind;
9120 }
9121
9122 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9123 buflen = strlen (buf);
9124 linksym = alloca (buflen + 1);
9125 memcpy (linksym, buf, buflen + 1);
9126
9127 al->linkage = gen_rtx_SYMBOL_REF
9128 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9129
9130 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9131 (splay_tree_value) al);
9132 }
9133
9134 if (rflag)
9135 al->rkind = KIND_CODEADDR;
9136 else
9137 al->rkind = KIND_LINKAGE;
9138
9139 if (lflag)
9140 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9141 else
9142 return al->linkage;
9143}
9144
a82c7f05
RH		 9145static int
9146alpha_write_one_linkage (node, data)
9147 splay_tree_node node;
9148 void *data;
9149{
83182544 9150 const char *const name = (const char *) node->key;
1330f7d5 9151 struct alpha_links *link = (struct alpha_links *) node->value;
a82c7f05
RH		 9152 FILE *stream = (FILE *) data;
9153
1330f7d5
DR		 9154 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9155 if (link->rkind == KIND_CODEADDR)
a82c7f05 9156 {
1330f7d5
DR		 9157 if (link->lkind == KIND_LOCAL)
9158 {
9159 /* Local and used */
9160 fprintf (stream, "\t.quad %s..en\n", name);
9161 }
9162 else
9163 {
9164 /* External and used, request code address. */
9165 fprintf (stream, "\t.code_address %s\n", name);
9166 }
a82c7f05
RH		 9167 }
9168 else
9169 {
1330f7d5
DR		 9170 if (link->lkind == KIND_LOCAL)
9171 {
9172 /* Local and used, build linkage pair. */
9173 fprintf (stream, "\t.quad %s..en\n", name);
9174 fprintf (stream, "\t.quad %s\n", name);
9175 }
9176 else
9177 {
9178 /* External and used, request linkage pair. */
9179 fprintf (stream, "\t.linkage %s\n", name);
9180 }
a82c7f05
RH		 9181 }
9182
9183 return 0;
9184}
89cfc2c6 9185
1330f7d5
DR		 9186static void
9187alpha_write_linkage (stream, funname, fundecl)
9188 FILE *stream;
9189 const char *funname;
9190 tree fundecl;
89cfc2c6 9191{
1330f7d5
DR		 9192 splay_tree_node node;
9193 struct alpha_funcs *func;
9194
9195 link_section ();
9196 fprintf (stream, "\t.align 3\n");
9197 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9198 func = (struct alpha_funcs *) node->value;
9199
9200 fputs ("\t.name ", stream);
9201 assemble_name (stream, funname);
9202 fputs ("..na\n", stream);
9203 ASM_OUTPUT_LABEL (stream, funname);
9204 fprintf (stream, "\t.pdesc ");
9205 assemble_name (stream, funname);
9206 fprintf (stream, "..en,%s\n",
9207 alpha_procedure_type == PT_STACK ? "stack"
9208 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9209
9210 if (func->links)
c1bd46a8 9211 {
1330f7d5
DR		 9212 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9213 /* splay_tree_delete (func->links); */
c1bd46a8 9214 }
89cfc2c6
RK		 9215}
9216
7c262518
RH		 9217/* Given a decl, a section name, and whether the decl initializer
9218 has relocs, choose attributes for the section. */
9219
9220#define SECTION_VMS_OVERLAY SECTION_FORGET
c1bd46a8
DR		 9221#define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9222#define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
7c262518
RH		 9223
9224static unsigned int
9225vms_section_type_flags (decl, name, reloc)
9226 tree decl;
9227 const char *name;
9228 int reloc;
9229{
9230 unsigned int flags = default_section_type_flags (decl, name, reloc);
9231
91d231cb
JM		 9232 if (decl && DECL_ATTRIBUTES (decl)
9233 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
7c262518 9234 flags |= SECTION_VMS_OVERLAY;
c1bd46a8
DR		 9235 if (decl && DECL_ATTRIBUTES (decl)
9236 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9237 flags |= SECTION_VMS_GLOBAL;
9238 if (decl && DECL_ATTRIBUTES (decl)
9239 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9240 flags |= SECTION_VMS_INITIALIZE;
7c262518
RH		 9241
9242 return flags;
9243}
9244
9245/* Switch to an arbitrary section NAME with attributes as specified
9246 by FLAGS. ALIGN specifies any known alignment requirements for
9247 the section; 0 if the default should be used. */
9248
9249static void
715bdd29 9250vms_asm_named_section (name, flags)
7c262518
RH		 9251 const char *name;
9252 unsigned int flags;
7c262518 9253{
c1bd46a8
DR		 9254 fputc ('\n', asm_out_file);
9255 fprintf (asm_out_file, ".section\t%s", name);
7c262518
RH		 9256
9257 if (flags & SECTION_VMS_OVERLAY)
c1bd46a8
DR		 9258 fprintf (asm_out_file, ",OVR");
9259 if (flags & SECTION_VMS_GLOBAL)
9260 fprintf (asm_out_file, ",GBL");
9261 if (flags & SECTION_VMS_INITIALIZE)
9262 fprintf (asm_out_file, ",NOMOD");
9263 if (flags & SECTION_DEBUG)
9264 fprintf (asm_out_file, ",NOWRT");
9265
9266 fputc ('\n', asm_out_file);
7c262518
RH		 9267}
9268
2cc07db4
RH		 9269/* Record an element in the table of global constructors. SYMBOL is
9270 a SYMBOL_REF of the function to be called; PRIORITY is a number
9271 between 0 and MAX_INIT_PRIORITY.
9272
9273 Differs from default_ctors_section_asm_out_constructor in that the
9274 width of the .ctors entry is always 64 bits, rather than the 32 bits
9275 used by a normal pointer. */
9276
9277static void
9278vms_asm_out_constructor (symbol, priority)
9279 rtx symbol;
9280 int priority ATTRIBUTE_UNUSED;
9281{
9282 ctors_section ();
c8af3574
RH		 9283 assemble_align (BITS_PER_WORD);
9284 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
2cc07db4
RH		 9285}
9286
9287static void
9288vms_asm_out_destructor (symbol, priority)
9289 rtx symbol;
9290 int priority ATTRIBUTE_UNUSED;
9291{
9292 dtors_section ();
c8af3574
RH		 9293 assemble_align (BITS_PER_WORD);
9294 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
2cc07db4 9295}
89cfc2c6
RK		 9296#else
9297
a82c7f05 9298rtx
89cfc2c6 9299alpha_need_linkage (name, is_local)
e03c5670 9300 const char *name ATTRIBUTE_UNUSED;
3c303f52 9301 int is_local ATTRIBUTE_UNUSED;
89cfc2c6 9302{
a82c7f05 9303 return NULL_RTX;
89cfc2c6
RK		 9304}
9305
1330f7d5
DR		 9306rtx
9307alpha_use_linkage (linkage, cfundecl, lflag, rflag)
9308 rtx linkage ATTRIBUTE_UNUSED;
9309 tree cfundecl ATTRIBUTE_UNUSED;
9310 int lflag ATTRIBUTE_UNUSED;
9311 int rflag ATTRIBUTE_UNUSED;
9312{
9313 return NULL_RTX;
9314}
9315
be7b80f4 9316#endif /* TARGET_ABI_OPEN_VMS */
30102605
RH		 9317\f
9318#if TARGET_ABI_UNICOSMK
9319
9320static void unicosmk_output_module_name PARAMS ((FILE *));
9321static void unicosmk_output_default_externs PARAMS ((FILE *));
9322static void unicosmk_output_dex PARAMS ((FILE *));
9323static void unicosmk_output_externs PARAMS ((FILE *));
9324static void unicosmk_output_addr_vec PARAMS ((FILE *, rtx));
9325static const char *unicosmk_ssib_name PARAMS ((void));
950a3816 9326static int unicosmk_special_name PARAMS ((const char *));
30102605
RH		 9327
9328/* Define the offset between two registers, one to be eliminated, and the
9329 other its replacement, at the start of a routine. */
9330
9331int
9332unicosmk_initial_elimination_offset (from, to)
9333 int from;
9334 int to;
9335{
9336 int fixed_size;
9337
9338 fixed_size = alpha_sa_size();
9339 if (fixed_size != 0)
9340 fixed_size += 48;
9341
9342 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9343 return -fixed_size;
9344 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9345 return 0;
9346 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9347 return (ALPHA_ROUND (current_function_outgoing_args_size)
9348 + ALPHA_ROUND (get_frame_size()));
9349 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9350 return (ALPHA_ROUND (fixed_size)
9351 + ALPHA_ROUND (get_frame_size()
9352 + current_function_outgoing_args_size));
9353 else
9354 abort ();
9355}
9356
9357/* Output the module name for .ident and .end directives. We have to strip
9358 directories and add make sure that the module name starts with a letter
9359 or '$'. */
9360
9361static void
9362unicosmk_output_module_name (file)
9363 FILE *file;
9364{
9365 const char *name;
9366
9367 /* Strip directories. */
9368
9369 name = strrchr (main_input_filename, '/');
9370 if (name)
9371 ++name;
9372 else
9373 name = main_input_filename;
9374
9375 /* CAM only accepts module names that start with a letter or '$'. We
9376 prefix the module name with a '$' if necessary. */
9377
9378 if (!ISALPHA (*name))
211a0cbe
GDR		 9379 putc ('$', file);
9380 output_clean_symbol_name (file, name);
30102605
RH		 9381}
9382
9383/* Output text that to appear at the beginning of an assembler file. */
9384
9385void
9386unicosmk_asm_file_start (file)
9387 FILE *file;
9388{
9389 int i;
9390
9391 fputs ("\t.ident\t", file);
9392 unicosmk_output_module_name (file);
9393 fputs ("\n\n", file);
9394
9395 /* The Unicos/Mk assembler uses different register names. Instead of trying
9396 to support them, we simply use micro definitions. */
9397
9398 /* CAM has different register names: rN for the integer register N and fN
9399 for the floating-point register N. Instead of trying to use these in
9400 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9401 register. */
9402
9403 for (i = 0; i < 32; ++i)
9404 fprintf (file, "$%d <- r%d\n", i, i);
9405
9406 for (i = 0; i < 32; ++i)
9407 fprintf (file, "$f%d <- f%d\n", i, i);
9408
9409 putc ('\n', file);
9410
9411 /* The .align directive fill unused space with zeroes which does not work
9412 in code sections. We define the macro 'gcc@code@align' which uses nops
9413 instead. Note that it assumes that code sections always have the
9414 biggest possible alignment since . refers to the current offset from
9415 the beginning of the section. */
9416
9417 fputs ("\t.macro gcc@code@align n\n", file);
9418 fputs ("gcc@n@bytes = 1 << n\n", file);
9419 fputs ("gcc@here = . % gcc@n@bytes\n", file);
9420 fputs ("\t.if ne, gcc@here, 0\n", file);
9421 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file);
9422 fputs ("\tbis r31,r31,r31\n", file);
9423 fputs ("\t.endr\n", file);
9424 fputs ("\t.endif\n", file);
9425 fputs ("\t.endm gcc@code@align\n\n", file);
9426
9427 /* Output extern declarations which should always be visible. */
9428 unicosmk_output_default_externs (file);
9429
9430 /* Open a dummy section. We always need to be inside a section for the
9431 section-switching code to work correctly.
9432 ??? This should be a module id or something like that. I still have to
9433 figure out what the rules for those are. */
9434 fputs ("\n\t.psect\t$SG00000,data\n", file);
9435}
9436
9437/* Output text to appear at the end of an assembler file. This includes all
9438 pending extern declarations and DEX expressions. */
9439
9440void
9441unicosmk_asm_file_end (file)
9442 FILE *file;
9443{
9444 fputs ("\t.endp\n\n", file);
9445
9446 /* Output all pending externs. */
9447
9448 unicosmk_output_externs (file);
9449
9450 /* Output dex definitions used for functions whose names conflict with
9451 register names. */
9452
9453 unicosmk_output_dex (file);
9454
9455 fputs ("\t.end\t", file);
9456 unicosmk_output_module_name (file);
9457 putc ('\n', file);
9458}
9459
9460/* Output the definition of a common variable. */
9461
9462void
9463unicosmk_output_common (file, name, size, align)
9464 FILE *file;
9465 const char *name;
9466 int size;
9467 int align;
9468{
9469 tree name_tree;
9470 printf ("T3E__: common %s\n", name);
9471
9472 common_section ();
9473 fputs("\t.endp\n\n\t.psect ", file);
9474 assemble_name(file, name);
9475 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9476 fprintf(file, "\t.byte\t0:%d\n", size);
9477
9478 /* Mark the symbol as defined in this module. */
9479 name_tree = get_identifier (name);
9480 TREE_ASM_WRITTEN (name_tree) = 1;
9481}
9482
9483#define SECTION_PUBLIC SECTION_MACH_DEP
9484#define SECTION_MAIN (SECTION_PUBLIC << 1)
9485static int current_section_align;
9486
9487static unsigned int
9488unicosmk_section_type_flags (decl, name, reloc)
9489 tree decl;
9490 const char *name;
9491 int reloc ATTRIBUTE_UNUSED;
9492{
9493 unsigned int flags = default_section_type_flags (decl, name, reloc);
9494
9495 if (!decl)
9496 return flags;
9497
9498 if (TREE_CODE (decl) == FUNCTION_DECL)
9499 {
9500 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9501 if (align_functions_log > current_section_align)
9502 current_section_align = align_functions_log;
9503
9504 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9505 flags |= SECTION_MAIN;
9506 }
9507 else
9508 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9509
9510 if (TREE_PUBLIC (decl))
9511 flags |= SECTION_PUBLIC;
9512
9513 return flags;
9514}
9515
9516/* Generate a section name for decl and associate it with the
9517 declaration. */
9518
ae46c4e0 9519static void
30102605
RH		 9520unicosmk_unique_section (decl, reloc)
9521 tree decl;
9522 int reloc ATTRIBUTE_UNUSED;
9523{
9524 const char *name;
9525 int len;
9526
9527 if (!decl)
9528 abort ();
9529
9530 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
772c5265 9531 name = alpha_strip_name_encoding (name);
30102605
RH		 9532 len = strlen (name);
9533
9534 if (TREE_CODE (decl) == FUNCTION_DECL)
9535 {
9536 char *string;
9537
9538 /* It is essential that we prefix the section name here because
9539 otherwise the section names generated for constructors and
9540 destructors confuse collect2. */
9541
9542 string = alloca (len + 6);
9543 sprintf (string, "code@%s", name);
9544 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9545 }
9546 else if (TREE_PUBLIC (decl))
9547 DECL_SECTION_NAME (decl) = build_string (len, name);
9548 else
9549 {
9550 char *string;
9551
9552 string = alloca (len + 6);
9553 sprintf (string, "data@%s", name);
9554 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9555 }
9556}
9557
9558/* Switch to an arbitrary section NAME with attributes as specified
9559 by FLAGS. ALIGN specifies any known alignment requirements for
9560 the section; 0 if the default should be used. */
9561
9562static void
9563unicosmk_asm_named_section (name, flags)
9564 const char *name;
9565 unsigned int flags;
9566{
9567 const char *kind;
9568
9569 /* Close the previous section. */
9570
9571 fputs ("\t.endp\n\n", asm_out_file);
9572
9573 /* Find out what kind of section we are opening. */
9574
9575 if (flags & SECTION_MAIN)
9576 fputs ("\t.start\tmain\n", asm_out_file);
9577
9578 if (flags & SECTION_CODE)
9579 kind = "code";
9580 else if (flags & SECTION_PUBLIC)
9581 kind = "common";
9582 else
9583 kind = "data";
9584
9585 if (current_section_align != 0)
9586 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9587 current_section_align, kind);
9588 else
9589 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9590}
9591
9592static void
9593unicosmk_insert_attributes (decl, attr_ptr)
9594 tree decl;
9595 tree *attr_ptr ATTRIBUTE_UNUSED;
9596{
9597 if (DECL_P (decl)
9598 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
ae46c4e0 9599 unicosmk_unique_section (decl, 0);
30102605
RH		 9600}
9601
9602/* Output an alignment directive. We have to use the macro 'gcc@code@align'
9603 in code sections because .align fill unused space with zeroes. */
9604
9605void
9606unicosmk_output_align (file, align)
9607 FILE *file;
9608 int align;
9609{
9610 if (inside_function)
9611 fprintf (file, "\tgcc@code@align\t%d\n", align);
9612 else
9613 fprintf (file, "\t.align\t%d\n", align);
9614}
9615
9616/* Add a case vector to the current function's list of deferred case
9617 vectors. Case vectors have to be put into a separate section because CAM
9618 does not allow data definitions in code sections. */
9619
9620void
9621unicosmk_defer_case_vector (lab, vec)
9622 rtx lab;
9623 rtx vec;
9624{
9625 struct machine_function *machine = cfun->machine;
9626
9627 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9628 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9629 machine->addr_list);
9630}
9631
9632/* Output a case vector. */
9633
9634static void
9635unicosmk_output_addr_vec (file, vec)
9636 FILE *file;
9637 rtx vec;
9638{
9639 rtx lab = XEXP (vec, 0);
9640 rtx body = XEXP (vec, 1);
9641 int vlen = XVECLEN (body, 0);
9642 int idx;
9643
9644 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (lab));
9645
9646 for (idx = 0; idx < vlen; idx++)
9647 {
9648 ASM_OUTPUT_ADDR_VEC_ELT
9649 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9650 }
9651}
9652
9653/* Output current function's deferred case vectors. */
9654
9655static void
9656unicosmk_output_deferred_case_vectors (file)
9657 FILE *file;
9658{
9659 struct machine_function *machine = cfun->machine;
9660 rtx t;
9661
9662 if (machine->addr_list == NULL_RTX)
9663 return;
9664
9665 data_section ();
9666 for (t = machine->addr_list; t; t = XEXP (t, 1))
9667 unicosmk_output_addr_vec (file, XEXP (t, 0));
9668}
9669
9670/* Set up the dynamic subprogram information block (DSIB) and update the
9671 frame pointer register ($15) for subroutines which have a frame. If the
9672 subroutine doesn't have a frame, simply increment $15. */
9673
9674static void
9675unicosmk_gen_dsib (imaskP)
9676 unsigned long * imaskP;
9677{
c2ea1ac6 9678 if (alpha_procedure_type == PT_STACK)
30102605
RH		 9679 {
9680 const char *ssib_name;
9681 rtx mem;
9682
9683 /* Allocate 64 bytes for the DSIB. */
9684
9685 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9686 GEN_INT (-64))));
9687 emit_insn (gen_blockage ());
9688
9689 /* Save the return address. */
9690
9691 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9692 set_mem_alias_set (mem, alpha_sr_alias_set);
9693 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9694 (*imaskP) &= ~(1L << REG_RA);
9695
9696 /* Save the old frame pointer. */
9697
9698 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9699 set_mem_alias_set (mem, alpha_sr_alias_set);
9700 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9701 (*imaskP) &= ~(1L << HARD_FRAME_POINTER_REGNUM);
9702
9703 emit_insn (gen_blockage ());
9704
9705 /* Store the SSIB pointer. */
9706
9707 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9708 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9709 set_mem_alias_set (mem, alpha_sr_alias_set);
9710
9711 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9712 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9713 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9714
9715 /* Save the CIW index. */
9716
9717 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9718 set_mem_alias_set (mem, alpha_sr_alias_set);
9719 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9720
9721 emit_insn (gen_blockage ());
9722
9723 /* Set the new frame pointer. */
9724
9725 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9726 stack_pointer_rtx, GEN_INT (64))));
9727
9728 }
9729 else
9730 {
9731 /* Increment the frame pointer register to indicate that we do not
9732 have a frame. */
9733
9734 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9735 hard_frame_pointer_rtx, GEN_INT (1))));
9736 }
9737}
9738
9739#define SSIB_PREFIX "__SSIB_"
9740#define SSIB_PREFIX_LEN 7
9741
9742/* Generate the name of the SSIB section for the current function. */
9743
9744static const char *
9745unicosmk_ssib_name ()
9746{
9747 /* This is ok since CAM won't be able to deal with names longer than that
9748 anyway. */
9749
9750 static char name[256];
9751
9752 rtx x;
9753 const char *fnname;
30102605
RH		 9754 int len;
9755
9756 x = DECL_RTL (cfun->decl);
9757 if (GET_CODE (x) != MEM)
9758 abort ();
9759 x = XEXP (x, 0);
9760 if (GET_CODE (x) != SYMBOL_REF)
9761 abort ();
772c5265 9762 fnname = alpha_strip_name_encoding (XSTR (x, 0));
30102605
RH		 9763
9764 len = strlen (fnname);
9765 if (len + SSIB_PREFIX_LEN > 255)
9766 len = 255 - SSIB_PREFIX_LEN;
9767
9768 strcpy (name, SSIB_PREFIX);
9769 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9770 name[len + SSIB_PREFIX_LEN] = 0;
9771
9772 return name;
9773}
9774
9775/* Output the static subroutine information block for the current
9776 function. */
9777
9778static void
9779unicosmk_output_ssib (file, fnname)
9780 FILE *file;
9781 const char *fnname;
9782{
9783 int len;
9784 int i;
9785 rtx x;
9786 rtx ciw;
9787 struct machine_function *machine = cfun->machine;
9788
9789 ssib_section ();
9790 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9791 unicosmk_ssib_name ());
9792
9793 /* Some required stuff and the function name length. */
9794
9795 len = strlen (fnname);
9796 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9797
9798 /* Saved registers
9799 ??? We don't do that yet. */
9800
9801 fputs ("\t.quad\t0\n", file);
9802
9803 /* Function address. */
9804
9805 fputs ("\t.quad\t", file);
9806 assemble_name (file, fnname);
9807 putc ('\n', file);
9808
9809 fputs ("\t.quad\t0\n", file);
9810 fputs ("\t.quad\t0\n", file);
9811
9812 /* Function name.
9813 ??? We do it the same way Cray CC does it but this could be
9814 simplified. */
9815
9816 for( i = 0; i < len; i++ )
9817 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9818 if( (len % 8) == 0 )
9819 fputs ("\t.quad\t0\n", file);
9820 else
9821 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9822
9823 /* All call information words used in the function. */
9824
9825 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9826 {
9827 ciw = XEXP (x, 0);
9828 fprintf (file, "\t.quad\t");
9829#if HOST_BITS_PER_WIDE_INT == 32
9830 fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX,
9831 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9832#else
9833 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (ciw));
9834#endif
9835 fprintf (file, "\n");
9836 }
9837}
9838
9839/* Add a call information word (CIW) to the list of the current function's
9840 CIWs and return its index.
9841
9842 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9843
9844rtx
9845unicosmk_add_call_info_word (x)
9846 rtx x;
9847{
9848 rtx node;
9849 struct machine_function *machine = cfun->machine;
9850
9851 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9852 if (machine->first_ciw == NULL_RTX)
9853 machine->first_ciw = node;
9854 else
9855 XEXP (machine->last_ciw, 1) = node;
9856
9857 machine->last_ciw = node;
9858 ++machine->ciw_count;
9859
9860 return GEN_INT (machine->ciw_count
9861 + strlen (current_function_name)/8 + 5);
9862}
9863
9864static char unicosmk_section_buf[100];
9865
9866char *
9867unicosmk_text_section ()
9868{
9869 static int count = 0;
9870 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9871 count++);
9872 return unicosmk_section_buf;
9873}
9874
9875char *
9876unicosmk_data_section ()
9877{
9878 static int count = 1;
9879 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9880 count++);
9881 return unicosmk_section_buf;
9882}
9883
9884/* The Cray assembler doesn't accept extern declarations for symbols which
9885 are defined in the same file. We have to keep track of all global
9886 symbols which are referenced and/or defined in a source file and output
9887 extern declarations for those which are referenced but not defined at
9888 the end of file. */
9889
9890/* List of identifiers for which an extern declaration might have to be
9891 emitted. */
9892
9893struct unicosmk_extern_list
9894{
9895 struct unicosmk_extern_list *next;
9896 const char *name;
9897};
9898
9899static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9900
9901/* Output extern declarations which are required for every asm file. */
9902
9903static void
9904unicosmk_output_default_externs (file)
9905 FILE *file;
9906{
83182544 9907 static const char *const externs[] =
30102605
RH		 9908 { "__T3E_MISMATCH" };
9909
9910 int i;
9911 int n;
9912
9913 n = ARRAY_SIZE (externs);
9914
9915 for (i = 0; i < n; i++)
9916 fprintf (file, "\t.extern\t%s\n", externs[i]);
9917}
9918
9919/* Output extern declarations for global symbols which are have been
9920 referenced but not defined. */
9921
9922static void
9923unicosmk_output_externs (file)
9924 FILE *file;
9925{
9926 struct unicosmk_extern_list *p;
9927 const char *real_name;
9928 int len;
9929 tree name_tree;
9930
9931 len = strlen (user_label_prefix);
9932 for (p = unicosmk_extern_head; p != 0; p = p->next)
9933 {
9934 /* We have to strip the encoding and possibly remove user_label_prefix
9935 from the identifier in order to handle -fleading-underscore and
9936 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
772c5265 9937 real_name = alpha_strip_name_encoding (p->name);
30102605
RH		 9938 if (len && p->name[0] == '*'
9939 && !memcmp (real_name, user_label_prefix, len))
9940 real_name += len;
9941
9942 name_tree = get_identifier (real_name);
9943 if (! TREE_ASM_WRITTEN (name_tree))
9944 {
9945 TREE_ASM_WRITTEN (name_tree) = 1;
9946 fputs ("\t.extern\t", file);
9947 assemble_name (file, p->name);
9948 putc ('\n', file);
9949 }
9950 }
9951}
9952
9953/* Record an extern. */
9954
9955void
9956unicosmk_add_extern (name)
9957 const char *name;
9958{
9959 struct unicosmk_extern_list *p;
9960
9961 p = (struct unicosmk_extern_list *)
6d9f628e 9962 xmalloc (sizeof (struct unicosmk_extern_list));
30102605
RH		 9963 p->next = unicosmk_extern_head;
9964 p->name = name;
9965 unicosmk_extern_head = p;
9966}
9967
9968/* The Cray assembler generates incorrect code if identifiers which
9969 conflict with register names are used as instruction operands. We have
9970 to replace such identifiers with DEX expressions. */
9971
9972/* Structure to collect identifiers which have been replaced by DEX
9973 expressions. */
9974
9975struct unicosmk_dex {
9976 struct unicosmk_dex *next;
9977 const char *name;
9978};
9979
9980/* List of identifiers which have been replaced by DEX expressions. The DEX
9981 number is determined by the position in the list. */
9982
9983static struct unicosmk_dex *unicosmk_dex_list = NULL;
9984
9985/* The number of elements in the DEX list. */
9986
9987static int unicosmk_dex_count = 0;
9988
9989/* Check if NAME must be replaced by a DEX expression. */
9990
9991static int
9992unicosmk_special_name (name)
9993 const char *name;
9994{
9995 if (name[0] == '*')
9996 ++name;
9997
9998 if (name[0] == '$')
9999 ++name;
10000
10001 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
10002 return 0;
10003
10004 switch (name[1])
10005 {
10006 case '1': case '2':
10007 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
10008
10009 case '3':
10010 return (name[2] == '\0'
10011 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
10012
10013 default:
10014 return (ISDIGIT (name[1]) && name[2] == '\0');
10015 }
10016}
10017
10018/* Return the DEX number if X must be replaced by a DEX expression and 0
10019 otherwise. */
10020
10021static int
10022unicosmk_need_dex (x)
10023 rtx x;
10024{
10025 struct unicosmk_dex *dex;
10026 const char *name;
10027 int i;
10028
10029 if (GET_CODE (x) != SYMBOL_REF)
10030 return 0;
10031
10032 name = XSTR (x,0);
10033 if (! unicosmk_special_name (name))
10034 return 0;
10035
10036 i = unicosmk_dex_count;
10037 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10038 {
10039 if (! strcmp (name, dex->name))
10040 return i;
10041 --i;
10042 }
10043
6d9f628e 10044 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
30102605
RH		 10045 dex->name = name;
10046 dex->next = unicosmk_dex_list;
10047 unicosmk_dex_list = dex;
10048
10049 ++unicosmk_dex_count;
10050 return unicosmk_dex_count;
10051}
10052
10053/* Output the DEX definitions for this file. */
10054
10055static void
10056unicosmk_output_dex (file)
10057 FILE *file;
10058{
10059 struct unicosmk_dex *dex;
10060 int i;
10061
10062 if (unicosmk_dex_list == NULL)
10063 return;
10064
10065 fprintf (file, "\t.dexstart\n");
10066
10067 i = unicosmk_dex_count;
10068 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10069 {
10070 fprintf (file, "\tDEX (%d) = ", i);
10071 assemble_name (file, dex->name);
10072 putc ('\n', file);
10073 --i;
10074 }
10075
10076 fprintf (file, "\t.dexend\n");
10077}
10078
10079#else
10080
10081static void
10082unicosmk_output_deferred_case_vectors (file)
10083 FILE *file ATTRIBUTE_UNUSED;
10084{}
10085
10086static void
10087unicosmk_gen_dsib (imaskP)
10088 unsigned long * imaskP ATTRIBUTE_UNUSED;
10089{}
10090
10091static void
10092unicosmk_output_ssib (file, fnname)
10093 FILE * file ATTRIBUTE_UNUSED;
10094 const char * fnname ATTRIBUTE_UNUSED;
10095{}
10096
10097rtx
10098unicosmk_add_call_info_word (x)
10099 rtx x ATTRIBUTE_UNUSED;
10100{
10101 return NULL_RTX;
10102}
10103
10104static int
10105unicosmk_need_dex (x)
10106 rtx x ATTRIBUTE_UNUSED;
10107{
10108 return 0;
10109}
10110
10111#endif /* TARGET_ABI_UNICOSMK */
e2500fed
GK		 10112
10113#include "gt-alpha.h"
10114
GNU Compiler Collection
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