git://gcc.gnu.org / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 18c63565 | 1 | /* Machine description for AArch64 architecture. |
| 23a5b65a | 2 | Copyright (C) 2012-2014 Free Software Foundation, Inc. |
| 18c63565 JG |
3 | Contributed by ARM Ltd. |
| 4 | ||
| 5 | This file is part of GCC. | |
| 6 | ||
| 7 | GCC is free software; you can redistribute it and/or modify it | |
| 8 | under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | GCC is distributed in the hope that it will be useful, but | |
| 13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GCC; see the file COPYING3. If not see | |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| 342be7f7 | 20 | |
| 0ddec79f JG |
21 | /* In the list below, the BUILTIN_<ITERATOR> macros expand to create |
| 22 | builtins for each of the modes described by <ITERATOR>. When adding | |
| 23 | new builtins to this list, a helpful idiom to follow is to add | |
| 24 | a line for each pattern in the md file. Thus, ADDP, which has one | |
| 25 | pattern defined for the VD_BHSI iterator, and one for DImode, has two | |
| 26 | entries below. | |
| 342be7f7 | 27 | |
| 0ddec79f JG |
28 | Parameter 1 is the 'type' of the intrinsic. This is used to |
| 29 | describe the type modifiers (for example; unsigned) applied to | |
| 30 | each of the parameters to the intrinsic function. | |
| 342be7f7 | 31 | |
| 0ddec79f JG |
32 | Parameter 2 is the name of the intrinsic. This is appended |
| 33 | to `__builtin_aarch64_<name><mode>` to give the intrinsic name | |
| 34 | as exported to the front-ends. | |
| 342be7f7 | 35 | |
| 0ddec79f JG |
36 | Parameter 3 describes how to map from the name to the CODE_FOR_ |
| 37 | macro holding the RTL pattern for the intrinsic. This mapping is: | |
| 38 | 0 - CODE_FOR_aarch64_<name><mode> | |
| 39 | 1-9 - CODE_FOR_<name><mode><1-9> | |
| 40 | 10 - CODE_FOR_<name><mode>. */ | |
| 41 | ||
| 0ddec79f JG |
42 | BUILTIN_VDC (COMBINE, combine, 0) |
| 43 | BUILTIN_VB (BINOP, pmul, 0) | |
| 44 | BUILTIN_VDQF (UNOP, sqrt, 2) | |
| 45 | BUILTIN_VD_BHSI (BINOP, addp, 0) | |
| 46 | VAR1 (UNOP, addp, 0, di) | |
| 0fe04f5c | 47 | BUILTIN_VDQ_BHSI (UNOP, clz, 2) |
| 0ddec79f | 48 | |
| 2a49c16d AL |
49 | /* be_checked_get_lane does its own lane swapping, so not a lane index. */ |
| 50 | BUILTIN_VALL (GETREG, be_checked_get_lane, 0) | |
| 66adb8eb | 51 | |
| 342be7f7 | 52 | /* Implemented by aarch64_<sur>q<r>shl<mode>. */ |
| 0ddec79f | 53 | BUILTIN_VSDQ_I (BINOP, sqshl, 0) |
| de10bcce | 54 | BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0) |
| 0ddec79f | 55 | BUILTIN_VSDQ_I (BINOP, sqrshl, 0) |
| de10bcce | 56 | BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0) |
| 342be7f7 | 57 | /* Implemented by aarch64_<su_optab><optab><mode>. */ |
| 0ddec79f | 58 | BUILTIN_VSDQ_I (BINOP, sqadd, 0) |
| de10bcce | 59 | BUILTIN_VSDQ_I (BINOPU, uqadd, 0) |
| 0ddec79f | 60 | BUILTIN_VSDQ_I (BINOP, sqsub, 0) |
| de10bcce | 61 | BUILTIN_VSDQ_I (BINOPU, uqsub, 0) |
| 342be7f7 | 62 | /* Implemented by aarch64_<sur>qadd<mode>. */ |
| 918621d3 | 63 | BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0) |
| de10bcce | 64 | BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0) |
| 342be7f7 JG |
65 | |
| 66 | /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ | |
| 2a49c16d AL |
67 | BUILTIN_VDC (GETREG, get_dregoi, 0) |
| 68 | BUILTIN_VDC (GETREG, get_dregci, 0) | |
| 69 | BUILTIN_VDC (GETREG, get_dregxi, 0) | |
| 342be7f7 | 70 | /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 2a49c16d AL |
71 | BUILTIN_VQ (GETREG, get_qregoi, 0) |
| 72 | BUILTIN_VQ (GETREG, get_qregci, 0) | |
| 73 | BUILTIN_VQ (GETREG, get_qregxi, 0) | |
| 342be7f7 | 74 | /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 2a49c16d AL |
75 | BUILTIN_VQ (SETREG, set_qregoi, 0) |
| 76 | BUILTIN_VQ (SETREG, set_qregci, 0) | |
| 77 | BUILTIN_VQ (SETREG, set_qregxi, 0) | |
| 342be7f7 | 78 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
79 | BUILTIN_VDC (LOADSTRUCT, ld2, 0) |
| 80 | BUILTIN_VDC (LOADSTRUCT, ld3, 0) | |
| 81 | BUILTIN_VDC (LOADSTRUCT, ld4, 0) | |
| 342be7f7 | 82 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
83 | BUILTIN_VQ (LOADSTRUCT, ld2, 0) |
| 84 | BUILTIN_VQ (LOADSTRUCT, ld3, 0) | |
| 85 | BUILTIN_VQ (LOADSTRUCT, ld4, 0) | |
| 77efea31 FY |
86 | /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>. */ |
| 87 | BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0) | |
| 88 | BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0) | |
| 89 | BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0) | |
| 3ec1be97 CB |
90 | /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>. */ |
| 91 | BUILTIN_VQ (LOADSTRUCT_LANE, ld2_lane, 0) | |
| 92 | BUILTIN_VQ (LOADSTRUCT_LANE, ld3_lane, 0) | |
| 93 | BUILTIN_VQ (LOADSTRUCT_LANE, ld4_lane, 0) | |
| 342be7f7 | 94 | /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
95 | BUILTIN_VDC (STORESTRUCT, st2, 0) |
| 96 | BUILTIN_VDC (STORESTRUCT, st3, 0) | |
| 97 | BUILTIN_VDC (STORESTRUCT, st4, 0) | |
| 342be7f7 | 98 | /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
99 | BUILTIN_VQ (STORESTRUCT, st2, 0) |
| 100 | BUILTIN_VQ (STORESTRUCT, st3, 0) | |
| 101 | BUILTIN_VQ (STORESTRUCT, st4, 0) | |
| 342be7f7 | 102 | |
| ba081b77 JG |
103 | BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0) |
| 104 | BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0) | |
| 105 | BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0) | |
| 106 | ||
| 0ddec79f JG |
107 | BUILTIN_VQW (BINOP, saddl2, 0) |
| 108 | BUILTIN_VQW (BINOP, uaddl2, 0) | |
| 109 | BUILTIN_VQW (BINOP, ssubl2, 0) | |
| 110 | BUILTIN_VQW (BINOP, usubl2, 0) | |
| 111 | BUILTIN_VQW (BINOP, saddw2, 0) | |
| 112 | BUILTIN_VQW (BINOP, uaddw2, 0) | |
| 113 | BUILTIN_VQW (BINOP, ssubw2, 0) | |
| 114 | BUILTIN_VQW (BINOP, usubw2, 0) | |
| 342be7f7 | 115 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ |
| 0ddec79f JG |
116 | BUILTIN_VDW (BINOP, saddl, 0) |
| 117 | BUILTIN_VDW (BINOP, uaddl, 0) | |
| 118 | BUILTIN_VDW (BINOP, ssubl, 0) | |
| 119 | BUILTIN_VDW (BINOP, usubl, 0) | |
| 342be7f7 | 120 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ |
| 0ddec79f JG |
121 | BUILTIN_VDW (BINOP, saddw, 0) |
| 122 | BUILTIN_VDW (BINOP, uaddw, 0) | |
| 123 | BUILTIN_VDW (BINOP, ssubw, 0) | |
| 124 | BUILTIN_VDW (BINOP, usubw, 0) | |
| 342be7f7 | 125 | /* Implemented by aarch64_<sur>h<addsub><mode>. */ |
| 0ddec79f JG |
126 | BUILTIN_VQ_S (BINOP, shadd, 0) |
| 127 | BUILTIN_VQ_S (BINOP, uhadd, 0) | |
| 128 | BUILTIN_VQ_S (BINOP, srhadd, 0) | |
| 129 | BUILTIN_VQ_S (BINOP, urhadd, 0) | |
| 342be7f7 | 130 | /* Implemented by aarch64_<sur><addsub>hn<mode>. */ |
| 0ddec79f JG |
131 | BUILTIN_VQN (BINOP, addhn, 0) |
| 132 | BUILTIN_VQN (BINOP, raddhn, 0) | |
| 342be7f7 | 133 | /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ |
| 0ddec79f JG |
134 | BUILTIN_VQN (TERNOP, addhn2, 0) |
| 135 | BUILTIN_VQN (TERNOP, raddhn2, 0) | |
| 342be7f7 | 136 | |
| 0ddec79f | 137 | BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0) |
| 342be7f7 | 138 | /* Implemented by aarch64_<sur>qmovn<mode>. */ |
| 0ddec79f JG |
139 | BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0) |
| 140 | BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0) | |
| 342be7f7 | 141 | /* Implemented by aarch64_s<optab><mode>. */ |
| 9551c7ec AV |
142 | BUILTIN_VSDQ_I (UNOP, sqabs, 0) |
| 143 | BUILTIN_VSDQ_I (UNOP, sqneg, 0) | |
| 342be7f7 | 144 | |
| 342be7f7 | 145 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ |
| 0ddec79f JG |
146 | BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) |
| 147 | BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) | |
| 2a49c16d AL |
148 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>. */ |
| 149 | BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0) | |
| 150 | BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0) | |
| 151 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>. */ | |
| 152 | BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0) | |
| 153 | BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0) | |
| 342be7f7 | 154 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ |
| 0ddec79f JG |
155 | BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) |
| 156 | BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) | |
| 342be7f7 | 157 | |
| 2a49c16d AL |
158 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) |
| 159 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) | |
| 160 | BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0) | |
| 161 | BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0) | |
| 162 | BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0) | |
| 163 | BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0) | |
| 164 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) | |
| 165 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) | |
| 166 | ||
| 0ddec79f | 167 | BUILTIN_VSD_HSI (BINOP, sqdmull, 0) |
| 2a49c16d AL |
168 | BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0) |
| 169 | BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0) | |
| 0ddec79f JG |
170 | BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) |
| 171 | BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) | |
| 2a49c16d AL |
172 | BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0) |
| 173 | BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0) | |
| 0ddec79f | 174 | BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) |
| 342be7f7 | 175 | /* Implemented by aarch64_sq<r>dmulh<mode>. */ |
| 0ddec79f JG |
176 | BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) |
| 177 | BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) | |
| b7d7d917 | 178 | /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ |
| 2a49c16d AL |
179 | BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0) |
| 180 | BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0) | |
| 181 | BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0) | |
| 182 | BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0) | |
| 342be7f7 | 183 | |
| 0ddec79f | 184 | BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) |
| 342be7f7 | 185 | /* Implemented by aarch64_<sur>shl<mode>. */ |
| 0ddec79f | 186 | BUILTIN_VSDQ_I_DI (BINOP, sshl, 0) |
| 918621d3 | 187 | BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0) |
| 0ddec79f | 188 | BUILTIN_VSDQ_I_DI (BINOP, srshl, 0) |
| 918621d3 | 189 | BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0) |
| 342be7f7 | 190 | |
| f9a4c9a6 AV |
191 | BUILTIN_VDQ_I (SHIFTIMM, ashr, 3) |
| 192 | VAR1 (SHIFTIMM, ashr_simd, 0, di) | |
| 252c7556 AV |
193 | BUILTIN_VDQ_I (SHIFTIMM, lshr, 3) |
| 194 | VAR1 (USHIFTIMM, lshr_simd, 0, di) | |
| 342be7f7 | 195 | /* Implemented by aarch64_<sur>shr_n<mode>. */ |
| 0ddec79f | 196 | BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0) |
| 918621d3 | 197 | BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0) |
| 342be7f7 | 198 | /* Implemented by aarch64_<sur>sra_n<mode>. */ |
| 0ddec79f | 199 | BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0) |
| de10bcce | 200 | BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0) |
| 0ddec79f | 201 | BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) |
| de10bcce | 202 | BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0) |
| 342be7f7 | 203 | /* Implemented by aarch64_<sur>shll_n<mode>. */ |
| 0ddec79f | 204 | BUILTIN_VDW (SHIFTIMM, sshll_n, 0) |
| 918621d3 | 205 | BUILTIN_VDW (USHIFTIMM, ushll_n, 0) |
| 342be7f7 | 206 | /* Implemented by aarch64_<sur>shll2_n<mode>. */ |
| 0ddec79f JG |
207 | BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) |
| 208 | BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) | |
| 342be7f7 | 209 | /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ |
| 0ddec79f JG |
210 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0) |
| 211 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0) | |
| 212 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0) | |
| de10bcce | 213 | BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0) |
| 0ddec79f | 214 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0) |
| de10bcce | 215 | BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0) |
| 342be7f7 | 216 | /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ |
| 0ddec79f | 217 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0) |
| de10bcce | 218 | BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0) |
| 0ddec79f | 219 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0) |
| de10bcce | 220 | BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0) |
| 342be7f7 | 221 | /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ |
| de10bcce | 222 | BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0) |
| 0ddec79f | 223 | BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0) |
| de10bcce | 224 | BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0) |
| 342be7f7 | 225 | |
| f5156c3e AL |
226 | /* Implemented by aarch64_reduc_plus_<mode>. */ |
| 227 | BUILTIN_VALL (UNOP, reduc_plus_scal_, 10) | |
| 0ac198d3 | 228 | |
| 64b0f928 AL |
229 | /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar). */ |
| 230 | BUILTIN_VDQIF (UNOP, reduc_smax_scal_, 10) | |
| 231 | BUILTIN_VDQIF (UNOP, reduc_smin_scal_, 10) | |
| 232 | BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10) | |
| 233 | BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10) | |
| 234 | BUILTIN_VDQF (UNOP, reduc_smax_nan_scal_, 10) | |
| 235 | BUILTIN_VDQF (UNOP, reduc_smin_nan_scal_, 10) | |
| 998eaf97 JG |
236 | |
| 237 | /* Implemented by <maxmin><mode>3. | |
| 238 | smax variants map to fmaxnm, | |
| 239 | smax_nan variants map to fmax. */ | |
| 240 | BUILTIN_VDQIF (BINOP, smax, 3) | |
| 241 | BUILTIN_VDQIF (BINOP, smin, 3) | |
| 0ddec79f JG |
242 | BUILTIN_VDQ_BHSI (BINOP, umax, 3) |
| 243 | BUILTIN_VDQ_BHSI (BINOP, umin, 3) | |
| 998eaf97 JG |
244 | BUILTIN_VDQF (BINOP, smax_nan, 3) |
| 245 | BUILTIN_VDQF (BINOP, smin_nan, 3) | |
| 42fc9a7f | 246 | |
| 0659ce6f JG |
247 | /* Implemented by <frint_pattern><mode>2. */ |
| 248 | BUILTIN_VDQF (UNOP, btrunc, 2) | |
| 249 | BUILTIN_VDQF (UNOP, ceil, 2) | |
| 250 | BUILTIN_VDQF (UNOP, floor, 2) | |
| 251 | BUILTIN_VDQF (UNOP, nearbyint, 2) | |
| 252 | BUILTIN_VDQF (UNOP, rint, 2) | |
| 253 | BUILTIN_VDQF (UNOP, round, 2) | |
| 74dc11ed | 254 | BUILTIN_VDQF_DF (UNOP, frintn, 2) |
| 42fc9a7f | 255 | |
| ce966824 JG |
256 | /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ |
| 257 | VAR1 (UNOP, lbtruncv2sf, 2, v2si) | |
| 258 | VAR1 (UNOP, lbtruncv4sf, 2, v4si) | |
| 259 | VAR1 (UNOP, lbtruncv2df, 2, v2di) | |
| 260 | ||
| 261 | VAR1 (UNOP, lbtruncuv2sf, 2, v2si) | |
| 262 | VAR1 (UNOP, lbtruncuv4sf, 2, v4si) | |
| 263 | VAR1 (UNOP, lbtruncuv2df, 2, v2di) | |
| 264 | ||
| 265 | VAR1 (UNOP, lroundv2sf, 2, v2si) | |
| 266 | VAR1 (UNOP, lroundv4sf, 2, v4si) | |
| 267 | VAR1 (UNOP, lroundv2df, 2, v2di) | |
| 268 | /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */ | |
| 269 | VAR1 (UNOP, lroundsf, 2, si) | |
| 270 | VAR1 (UNOP, lrounddf, 2, di) | |
| 271 | ||
| 272 | VAR1 (UNOP, lrounduv2sf, 2, v2si) | |
| 273 | VAR1 (UNOP, lrounduv4sf, 2, v4si) | |
| 274 | VAR1 (UNOP, lrounduv2df, 2, v2di) | |
| 275 | VAR1 (UNOP, lroundusf, 2, si) | |
| 276 | VAR1 (UNOP, lroundudf, 2, di) | |
| 277 | ||
| 278 | VAR1 (UNOP, lceilv2sf, 2, v2si) | |
| 279 | VAR1 (UNOP, lceilv4sf, 2, v4si) | |
| 280 | VAR1 (UNOP, lceilv2df, 2, v2di) | |
| 281 | ||
| 282 | VAR1 (UNOP, lceiluv2sf, 2, v2si) | |
| 283 | VAR1 (UNOP, lceiluv4sf, 2, v4si) | |
| 284 | VAR1 (UNOP, lceiluv2df, 2, v2di) | |
| 285 | VAR1 (UNOP, lceilusf, 2, si) | |
| 286 | VAR1 (UNOP, lceiludf, 2, di) | |
| 287 | ||
| 288 | VAR1 (UNOP, lfloorv2sf, 2, v2si) | |
| 289 | VAR1 (UNOP, lfloorv4sf, 2, v4si) | |
| 290 | VAR1 (UNOP, lfloorv2df, 2, v2di) | |
| 291 | ||
| 292 | VAR1 (UNOP, lflooruv2sf, 2, v2si) | |
| 293 | VAR1 (UNOP, lflooruv4sf, 2, v4si) | |
| 294 | VAR1 (UNOP, lflooruv2df, 2, v2di) | |
| 295 | VAR1 (UNOP, lfloorusf, 2, si) | |
| 296 | VAR1 (UNOP, lfloorudf, 2, di) | |
| 297 | ||
| 298 | VAR1 (UNOP, lfrintnv2sf, 2, v2si) | |
| 299 | VAR1 (UNOP, lfrintnv4sf, 2, v4si) | |
| 300 | VAR1 (UNOP, lfrintnv2df, 2, v2di) | |
| 301 | VAR1 (UNOP, lfrintnsf, 2, si) | |
| 302 | VAR1 (UNOP, lfrintndf, 2, di) | |
| 303 | ||
| 304 | VAR1 (UNOP, lfrintnuv2sf, 2, v2si) | |
| 305 | VAR1 (UNOP, lfrintnuv4sf, 2, v4si) | |
| 306 | VAR1 (UNOP, lfrintnuv2df, 2, v2di) | |
| 307 | VAR1 (UNOP, lfrintnusf, 2, si) | |
| 308 | VAR1 (UNOP, lfrintnudf, 2, di) | |
| cc4d934f | 309 | |
| 1709ff9b JG |
310 | /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ |
| 311 | VAR1 (UNOP, floatv2si, 2, v2sf) | |
| 312 | VAR1 (UNOP, floatv4si, 2, v4sf) | |
| 313 | VAR1 (UNOP, floatv2di, 2, v2df) | |
| 314 | ||
| 315 | VAR1 (UNOP, floatunsv2si, 2, v2sf) | |
| 316 | VAR1 (UNOP, floatunsv4si, 2, v4sf) | |
| 317 | VAR1 (UNOP, floatunsv2di, 2, v2df) | |
| 318 | ||
| c7f28cd5 KT |
319 | VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di) |
| 320 | ||
| cf465d71 AL |
321 | BUILTIN_VB (UNOP, rbit, 0) |
| 322 | ||
| cc4d934f JG |
323 | /* Implemented by |
| 324 | aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ | |
| 0ddec79f JG |
325 | BUILTIN_VALL (BINOP, zip1, 0) |
| 326 | BUILTIN_VALL (BINOP, zip2, 0) | |
| 327 | BUILTIN_VALL (BINOP, uzp1, 0) | |
| 328 | BUILTIN_VALL (BINOP, uzp2, 0) | |
| 329 | BUILTIN_VALL (BINOP, trn1, 0) | |
| 330 | BUILTIN_VALL (BINOP, trn2, 0) | |
| 0050faf8 JG |
331 | |
| 332 | /* Implemented by | |
| 333 | aarch64_frecp<FRECP:frecp_suffix><mode>. */ | |
| 0ddec79f JG |
334 | BUILTIN_GPF (UNOP, frecpe, 0) |
| 335 | BUILTIN_GPF (BINOP, frecps, 0) | |
| 336 | BUILTIN_GPF (UNOP, frecpx, 0) | |
| 0050faf8 | 337 | |
| 0ddec79f JG |
338 | BUILTIN_VDQF (UNOP, frecpe, 0) |
| 339 | BUILTIN_VDQF (BINOP, frecps, 0) | |
| 9697e620 | 340 | |
| 096c59be AL |
341 | /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is |
| 342 | only ever used for the int64x1_t intrinsic, there is no scalar version. */ | |
| d05d0709 | 343 | BUILTIN_VALLDI (UNOP, abs, 2) |
| 4c871069 JG |
344 | |
| 345 | VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) | |
| 346 | VAR1 (BINOP, float_truncate_hi_, 0, v4sf) | |
| 347 | ||
| 348 | VAR1 (UNOP, float_extend_lo_, 0, v2df) | |
| 349 | VAR1 (UNOP, float_truncate_lo_, 0, v2sf) | |
| dec11868 JG |
350 | |
| 351 | /* Implemented by aarch64_ld1<VALL:mode>. */ | |
| 352 | BUILTIN_VALL (LOAD1, ld1, 0) | |
| 353 | ||
| 354 | /* Implemented by aarch64_st1<VALL:mode>. */ | |
| 355 | BUILTIN_VALL (STORE1, st1, 0) | |
| 356 | ||
| 828e70c1 JG |
357 | /* Implemented by fma<mode>4. */ |
| 358 | BUILTIN_VDQF (TERNOP, fma, 4) | |
| 359 | ||
| 46e778c4 JG |
360 | /* Implemented by aarch64_simd_bsl<mode>. */ |
| 361 | BUILTIN_VDQQH (BSL_P, simd_bsl, 0) | |
| 362 | BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0) | |
| 363 | BUILTIN_VALLDIF (BSL_S, simd_bsl, 0) | |
| 364 | ||
| 5a7a4e80 TB |
365 | /* Implemented by aarch64_crypto_aes<op><mode>. */ |
| 366 | VAR1 (BINOPU, crypto_aese, 0, v16qi) | |
| 367 | VAR1 (BINOPU, crypto_aesd, 0, v16qi) | |
| 368 | VAR1 (UNOPU, crypto_aesmc, 0, v16qi) | |
| 369 | VAR1 (UNOPU, crypto_aesimc, 0, v16qi) | |
| 30442682 TB |
370 | |
| 371 | /* Implemented by aarch64_crypto_sha1<op><mode>. */ | |
| 372 | VAR1 (UNOPU, crypto_sha1h, 0, si) | |
| 373 | VAR1 (BINOPU, crypto_sha1su1, 0, v4si) | |
| 374 | VAR1 (TERNOPU, crypto_sha1c, 0, v4si) | |
| 375 | VAR1 (TERNOPU, crypto_sha1m, 0, v4si) | |
| 376 | VAR1 (TERNOPU, crypto_sha1p, 0, v4si) | |
| 377 | VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) | |
| b9cb0a44 TB |
378 | |
| 379 | /* Implemented by aarch64_crypto_sha256<op><mode>. */ | |
| 380 | VAR1 (TERNOPU, crypto_sha256h, 0, v4si) | |
| 381 | VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) | |
| 382 | VAR1 (BINOPU, crypto_sha256su0, 0, v4si) | |
| 383 | VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) | |
| 7baa225d TB |
384 | |
| 385 | /* Implemented by aarch64_crypto_pmull<mode>. */ | |
| 386 | VAR1 (BINOPP, crypto_pmull, 0, di) | |
| 387 | VAR1 (BINOPP, crypto_pmull, 0, v2di) | |
| ae0533da AL |
388 | |
| 389 | /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin. */ | |
| 390 | VAR1 (BINOPV, im_lane_bound, 0, si) |