git://gcc.gnu.org / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 18c63565 JG |
1 | /* Machine description for AArch64 architecture. |
| 2 | Copyright (C) 2012-2013 Free Software Foundation, Inc. | |
| 3 | Contributed by ARM Ltd. | |
| 4 | ||
| 5 | This file is part of GCC. | |
| 6 | ||
| 7 | GCC is free software; you can redistribute it and/or modify it | |
| 8 | under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | GCC is distributed in the hope that it will be useful, but | |
| 13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GCC; see the file COPYING3. If not see | |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| 342be7f7 | 20 | |
| 0ddec79f JG |
21 | /* In the list below, the BUILTIN_<ITERATOR> macros expand to create |
| 22 | builtins for each of the modes described by <ITERATOR>. When adding | |
| 23 | new builtins to this list, a helpful idiom to follow is to add | |
| 24 | a line for each pattern in the md file. Thus, ADDP, which has one | |
| 25 | pattern defined for the VD_BHSI iterator, and one for DImode, has two | |
| 26 | entries below. | |
| 342be7f7 | 27 | |
| 0ddec79f JG |
28 | Parameter 1 is the 'type' of the intrinsic. This is used to |
| 29 | describe the type modifiers (for example; unsigned) applied to | |
| 30 | each of the parameters to the intrinsic function. | |
| 342be7f7 | 31 | |
| 0ddec79f JG |
32 | Parameter 2 is the name of the intrinsic. This is appended |
| 33 | to `__builtin_aarch64_<name><mode>` to give the intrinsic name | |
| 34 | as exported to the front-ends. | |
| 342be7f7 | 35 | |
| 0ddec79f JG |
36 | Parameter 3 describes how to map from the name to the CODE_FOR_ |
| 37 | macro holding the RTL pattern for the intrinsic. This mapping is: | |
| 38 | 0 - CODE_FOR_aarch64_<name><mode> | |
| 39 | 1-9 - CODE_FOR_<name><mode><1-9> | |
| 40 | 10 - CODE_FOR_<name><mode>. */ | |
| 41 | ||
| 42 | BUILTIN_VD_RE (CREATE, create, 0) | |
| 43 | BUILTIN_VQ_S (GETLANE, get_lane_signed, 0) | |
| 44 | BUILTIN_VDQ (GETLANE, get_lane_unsigned, 0) | |
| 45 | BUILTIN_VDQF (GETLANE, get_lane, 0) | |
| 46 | VAR1 (GETLANE, get_lane, 0, di) | |
| 47 | BUILTIN_VDC (COMBINE, combine, 0) | |
| 48 | BUILTIN_VB (BINOP, pmul, 0) | |
| 49 | BUILTIN_VDQF (UNOP, sqrt, 2) | |
| 50 | BUILTIN_VD_BHSI (BINOP, addp, 0) | |
| 51 | VAR1 (UNOP, addp, 0, di) | |
| 52 | ||
| 53 | BUILTIN_VD_RE (REINTERP, reinterpretdi, 0) | |
| 54 | BUILTIN_VDC (REINTERP, reinterpretv8qi, 0) | |
| 55 | BUILTIN_VDC (REINTERP, reinterpretv4hi, 0) | |
| 56 | BUILTIN_VDC (REINTERP, reinterpretv2si, 0) | |
| 57 | BUILTIN_VDC (REINTERP, reinterpretv2sf, 0) | |
| 58 | BUILTIN_VQ (REINTERP, reinterpretv16qi, 0) | |
| 59 | BUILTIN_VQ (REINTERP, reinterpretv8hi, 0) | |
| 60 | BUILTIN_VQ (REINTERP, reinterpretv4si, 0) | |
| 61 | BUILTIN_VQ (REINTERP, reinterpretv4sf, 0) | |
| 62 | BUILTIN_VQ (REINTERP, reinterpretv2di, 0) | |
| 63 | BUILTIN_VQ (REINTERP, reinterpretv2df, 0) | |
| 64 | ||
| 65 | BUILTIN_VDQ_I (BINOP, dup_lane, 0) | |
| 66 | BUILTIN_SDQ_I (BINOP, dup_lane, 0) | |
| 342be7f7 | 67 | /* Implemented by aarch64_<sur>q<r>shl<mode>. */ |
| 0ddec79f JG |
68 | BUILTIN_VSDQ_I (BINOP, sqshl, 0) |
| 69 | BUILTIN_VSDQ_I (BINOP, uqshl, 0) | |
| 70 | BUILTIN_VSDQ_I (BINOP, sqrshl, 0) | |
| 71 | BUILTIN_VSDQ_I (BINOP, uqrshl, 0) | |
| 342be7f7 | 72 | /* Implemented by aarch64_<su_optab><optab><mode>. */ |
| 0ddec79f JG |
73 | BUILTIN_VSDQ_I (BINOP, sqadd, 0) |
| 74 | BUILTIN_VSDQ_I (BINOP, uqadd, 0) | |
| 75 | BUILTIN_VSDQ_I (BINOP, sqsub, 0) | |
| 76 | BUILTIN_VSDQ_I (BINOP, uqsub, 0) | |
| 342be7f7 | 77 | /* Implemented by aarch64_<sur>qadd<mode>. */ |
| 0ddec79f JG |
78 | BUILTIN_VSDQ_I (BINOP, suqadd, 0) |
| 79 | BUILTIN_VSDQ_I (BINOP, usqadd, 0) | |
| 342be7f7 JG |
80 | |
| 81 | /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ | |
| 0ddec79f JG |
82 | BUILTIN_VDC (GETLANE, get_dregoi, 0) |
| 83 | BUILTIN_VDC (GETLANE, get_dregci, 0) | |
| 84 | BUILTIN_VDC (GETLANE, get_dregxi, 0) | |
| 342be7f7 | 85 | /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 0ddec79f JG |
86 | BUILTIN_VQ (GETLANE, get_qregoi, 0) |
| 87 | BUILTIN_VQ (GETLANE, get_qregci, 0) | |
| 88 | BUILTIN_VQ (GETLANE, get_qregxi, 0) | |
| 342be7f7 | 89 | /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 0ddec79f JG |
90 | BUILTIN_VQ (SETLANE, set_qregoi, 0) |
| 91 | BUILTIN_VQ (SETLANE, set_qregci, 0) | |
| 92 | BUILTIN_VQ (SETLANE, set_qregxi, 0) | |
| 342be7f7 | 93 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
94 | BUILTIN_VDC (LOADSTRUCT, ld2, 0) |
| 95 | BUILTIN_VDC (LOADSTRUCT, ld3, 0) | |
| 96 | BUILTIN_VDC (LOADSTRUCT, ld4, 0) | |
| 342be7f7 | 97 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
98 | BUILTIN_VQ (LOADSTRUCT, ld2, 0) |
| 99 | BUILTIN_VQ (LOADSTRUCT, ld3, 0) | |
| 100 | BUILTIN_VQ (LOADSTRUCT, ld4, 0) | |
| 342be7f7 | 101 | /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
102 | BUILTIN_VDC (STORESTRUCT, st2, 0) |
| 103 | BUILTIN_VDC (STORESTRUCT, st3, 0) | |
| 104 | BUILTIN_VDC (STORESTRUCT, st4, 0) | |
| 342be7f7 | 105 | /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
106 | BUILTIN_VQ (STORESTRUCT, st2, 0) |
| 107 | BUILTIN_VQ (STORESTRUCT, st3, 0) | |
| 108 | BUILTIN_VQ (STORESTRUCT, st4, 0) | |
| 342be7f7 | 109 | |
| 0ddec79f JG |
110 | BUILTIN_VQW (BINOP, saddl2, 0) |
| 111 | BUILTIN_VQW (BINOP, uaddl2, 0) | |
| 112 | BUILTIN_VQW (BINOP, ssubl2, 0) | |
| 113 | BUILTIN_VQW (BINOP, usubl2, 0) | |
| 114 | BUILTIN_VQW (BINOP, saddw2, 0) | |
| 115 | BUILTIN_VQW (BINOP, uaddw2, 0) | |
| 116 | BUILTIN_VQW (BINOP, ssubw2, 0) | |
| 117 | BUILTIN_VQW (BINOP, usubw2, 0) | |
| 342be7f7 | 118 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ |
| 0ddec79f JG |
119 | BUILTIN_VDW (BINOP, saddl, 0) |
| 120 | BUILTIN_VDW (BINOP, uaddl, 0) | |
| 121 | BUILTIN_VDW (BINOP, ssubl, 0) | |
| 122 | BUILTIN_VDW (BINOP, usubl, 0) | |
| 342be7f7 | 123 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ |
| 0ddec79f JG |
124 | BUILTIN_VDW (BINOP, saddw, 0) |
| 125 | BUILTIN_VDW (BINOP, uaddw, 0) | |
| 126 | BUILTIN_VDW (BINOP, ssubw, 0) | |
| 127 | BUILTIN_VDW (BINOP, usubw, 0) | |
| 342be7f7 | 128 | /* Implemented by aarch64_<sur>h<addsub><mode>. */ |
| 0ddec79f JG |
129 | BUILTIN_VQ_S (BINOP, shadd, 0) |
| 130 | BUILTIN_VQ_S (BINOP, uhadd, 0) | |
| 131 | BUILTIN_VQ_S (BINOP, srhadd, 0) | |
| 132 | BUILTIN_VQ_S (BINOP, urhadd, 0) | |
| 342be7f7 | 133 | /* Implemented by aarch64_<sur><addsub>hn<mode>. */ |
| 0ddec79f JG |
134 | BUILTIN_VQN (BINOP, addhn, 0) |
| 135 | BUILTIN_VQN (BINOP, raddhn, 0) | |
| 342be7f7 | 136 | /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ |
| 0ddec79f JG |
137 | BUILTIN_VQN (TERNOP, addhn2, 0) |
| 138 | BUILTIN_VQN (TERNOP, raddhn2, 0) | |
| 342be7f7 | 139 | |
| 0ddec79f | 140 | BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0) |
| 342be7f7 | 141 | /* Implemented by aarch64_<sur>qmovn<mode>. */ |
| 0ddec79f JG |
142 | BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0) |
| 143 | BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0) | |
| 342be7f7 | 144 | /* Implemented by aarch64_s<optab><mode>. */ |
| 0ddec79f JG |
145 | BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0) |
| 146 | BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0) | |
| 342be7f7 | 147 | |
| 0ddec79f JG |
148 | BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0) |
| 149 | BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0) | |
| 150 | BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0) | |
| 151 | BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0) | |
| 152 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) | |
| 153 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) | |
| 154 | BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0) | |
| 155 | BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0) | |
| 156 | BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0) | |
| 157 | BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0) | |
| 158 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) | |
| 159 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) | |
| 342be7f7 | 160 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ |
| 0ddec79f JG |
161 | BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) |
| 162 | BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) | |
| 342be7f7 | 163 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ |
| 0ddec79f JG |
164 | BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) |
| 165 | BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) | |
| 342be7f7 | 166 | |
| 0ddec79f JG |
167 | BUILTIN_VSD_HSI (BINOP, sqdmull, 0) |
| 168 | BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0) | |
| 169 | BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0) | |
| 170 | BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) | |
| 171 | BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) | |
| 172 | BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0) | |
| 173 | BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0) | |
| 174 | BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) | |
| 342be7f7 | 175 | /* Implemented by aarch64_sq<r>dmulh<mode>. */ |
| 0ddec79f JG |
176 | BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) |
| 177 | BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) | |
| b7d7d917 | 178 | /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ |
| 0ddec79f JG |
179 | BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0) |
| 180 | BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0) | |
| 181 | BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0) | |
| 182 | BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0) | |
| 183 | BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0) | |
| 184 | BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0) | |
| 342be7f7 | 185 | |
| 0ddec79f | 186 | BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) |
| 342be7f7 | 187 | /* Implemented by aarch64_<sur>shl<mode>. */ |
| 0ddec79f JG |
188 | BUILTIN_VSDQ_I_DI (BINOP, sshl, 0) |
| 189 | BUILTIN_VSDQ_I_DI (BINOP, ushl, 0) | |
| 190 | BUILTIN_VSDQ_I_DI (BINOP, srshl, 0) | |
| 191 | BUILTIN_VSDQ_I_DI (BINOP, urshl, 0) | |
| 342be7f7 | 192 | |
| 0ddec79f JG |
193 | BUILTIN_VSDQ_I_DI (SHIFTIMM, ashr, 3) |
| 194 | BUILTIN_VSDQ_I_DI (SHIFTIMM, lshr, 3) | |
| 342be7f7 | 195 | /* Implemented by aarch64_<sur>shr_n<mode>. */ |
| 0ddec79f JG |
196 | BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0) |
| 197 | BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0) | |
| 342be7f7 | 198 | /* Implemented by aarch64_<sur>sra_n<mode>. */ |
| 0ddec79f JG |
199 | BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0) |
| 200 | BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0) | |
| 201 | BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) | |
| 202 | BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0) | |
| 342be7f7 | 203 | /* Implemented by aarch64_<sur>shll_n<mode>. */ |
| 0ddec79f JG |
204 | BUILTIN_VDW (SHIFTIMM, sshll_n, 0) |
| 205 | BUILTIN_VDW (SHIFTIMM, ushll_n, 0) | |
| 342be7f7 | 206 | /* Implemented by aarch64_<sur>shll2_n<mode>. */ |
| 0ddec79f JG |
207 | BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) |
| 208 | BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) | |
| 342be7f7 | 209 | /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ |
| 0ddec79f JG |
210 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0) |
| 211 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0) | |
| 212 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0) | |
| 213 | BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0) | |
| 214 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0) | |
| 215 | BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0) | |
| 342be7f7 | 216 | /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ |
| 0ddec79f JG |
217 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0) |
| 218 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0) | |
| 219 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0) | |
| 220 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0) | |
| 342be7f7 | 221 | /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ |
| 0ddec79f JG |
222 | BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0) |
| 223 | BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0) | |
| 224 | BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0) | |
| 342be7f7 JG |
225 | |
| 226 | /* Implemented by aarch64_cm<cmp><mode>. */ | |
| 0ddec79f JG |
227 | BUILTIN_VSDQ_I_DI (BINOP, cmeq, 0) |
| 228 | BUILTIN_VSDQ_I_DI (BINOP, cmge, 0) | |
| 229 | BUILTIN_VSDQ_I_DI (BINOP, cmgt, 0) | |
| 230 | BUILTIN_VSDQ_I_DI (BINOP, cmle, 0) | |
| 231 | BUILTIN_VSDQ_I_DI (BINOP, cmlt, 0) | |
| 342be7f7 | 232 | /* Implemented by aarch64_cm<cmp><mode>. */ |
| 0ddec79f JG |
233 | BUILTIN_VSDQ_I_DI (BINOP, cmhs, 0) |
| 234 | BUILTIN_VSDQ_I_DI (BINOP, cmhi, 0) | |
| 235 | BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0) | |
| 342be7f7 JG |
236 | |
| 237 | /* Implemented by aarch64_<fmaxmin><mode>. */ | |
| 0ddec79f JG |
238 | BUILTIN_VDQF (BINOP, fmax, 0) |
| 239 | BUILTIN_VDQF (BINOP, fmin, 0) | |
| 240 | ||
| 0ac198d3 JG |
241 | /* Implemented by aarch64_addv<mode>. */ |
| 242 | BUILTIN_VDQF (UNOP, addv, 0) | |
| 243 | ||
| 0ddec79f JG |
244 | /* Implemented by <maxmin><mode>3. */ |
| 245 | BUILTIN_VDQ_BHSI (BINOP, smax, 3) | |
| 246 | BUILTIN_VDQ_BHSI (BINOP, smin, 3) | |
| 247 | BUILTIN_VDQ_BHSI (BINOP, umax, 3) | |
| 248 | BUILTIN_VDQ_BHSI (BINOP, umin, 3) | |
| 42fc9a7f | 249 | |
| 0659ce6f JG |
250 | /* Implemented by <frint_pattern><mode>2. */ |
| 251 | BUILTIN_VDQF (UNOP, btrunc, 2) | |
| 252 | BUILTIN_VDQF (UNOP, ceil, 2) | |
| 253 | BUILTIN_VDQF (UNOP, floor, 2) | |
| 254 | BUILTIN_VDQF (UNOP, nearbyint, 2) | |
| 255 | BUILTIN_VDQF (UNOP, rint, 2) | |
| 256 | BUILTIN_VDQF (UNOP, round, 2) | |
| 257 | BUILTIN_VDQF (UNOP, frintn, 2) | |
| 42fc9a7f | 258 | |
| ce966824 JG |
259 | /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ |
| 260 | VAR1 (UNOP, lbtruncv2sf, 2, v2si) | |
| 261 | VAR1 (UNOP, lbtruncv4sf, 2, v4si) | |
| 262 | VAR1 (UNOP, lbtruncv2df, 2, v2di) | |
| 263 | ||
| 264 | VAR1 (UNOP, lbtruncuv2sf, 2, v2si) | |
| 265 | VAR1 (UNOP, lbtruncuv4sf, 2, v4si) | |
| 266 | VAR1 (UNOP, lbtruncuv2df, 2, v2di) | |
| 267 | ||
| 268 | VAR1 (UNOP, lroundv2sf, 2, v2si) | |
| 269 | VAR1 (UNOP, lroundv4sf, 2, v4si) | |
| 270 | VAR1 (UNOP, lroundv2df, 2, v2di) | |
| 271 | /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */ | |
| 272 | VAR1 (UNOP, lroundsf, 2, si) | |
| 273 | VAR1 (UNOP, lrounddf, 2, di) | |
| 274 | ||
| 275 | VAR1 (UNOP, lrounduv2sf, 2, v2si) | |
| 276 | VAR1 (UNOP, lrounduv4sf, 2, v4si) | |
| 277 | VAR1 (UNOP, lrounduv2df, 2, v2di) | |
| 278 | VAR1 (UNOP, lroundusf, 2, si) | |
| 279 | VAR1 (UNOP, lroundudf, 2, di) | |
| 280 | ||
| 281 | VAR1 (UNOP, lceilv2sf, 2, v2si) | |
| 282 | VAR1 (UNOP, lceilv4sf, 2, v4si) | |
| 283 | VAR1 (UNOP, lceilv2df, 2, v2di) | |
| 284 | ||
| 285 | VAR1 (UNOP, lceiluv2sf, 2, v2si) | |
| 286 | VAR1 (UNOP, lceiluv4sf, 2, v4si) | |
| 287 | VAR1 (UNOP, lceiluv2df, 2, v2di) | |
| 288 | VAR1 (UNOP, lceilusf, 2, si) | |
| 289 | VAR1 (UNOP, lceiludf, 2, di) | |
| 290 | ||
| 291 | VAR1 (UNOP, lfloorv2sf, 2, v2si) | |
| 292 | VAR1 (UNOP, lfloorv4sf, 2, v4si) | |
| 293 | VAR1 (UNOP, lfloorv2df, 2, v2di) | |
| 294 | ||
| 295 | VAR1 (UNOP, lflooruv2sf, 2, v2si) | |
| 296 | VAR1 (UNOP, lflooruv4sf, 2, v4si) | |
| 297 | VAR1 (UNOP, lflooruv2df, 2, v2di) | |
| 298 | VAR1 (UNOP, lfloorusf, 2, si) | |
| 299 | VAR1 (UNOP, lfloorudf, 2, di) | |
| 300 | ||
| 301 | VAR1 (UNOP, lfrintnv2sf, 2, v2si) | |
| 302 | VAR1 (UNOP, lfrintnv4sf, 2, v4si) | |
| 303 | VAR1 (UNOP, lfrintnv2df, 2, v2di) | |
| 304 | VAR1 (UNOP, lfrintnsf, 2, si) | |
| 305 | VAR1 (UNOP, lfrintndf, 2, di) | |
| 306 | ||
| 307 | VAR1 (UNOP, lfrintnuv2sf, 2, v2si) | |
| 308 | VAR1 (UNOP, lfrintnuv4sf, 2, v4si) | |
| 309 | VAR1 (UNOP, lfrintnuv2df, 2, v2di) | |
| 310 | VAR1 (UNOP, lfrintnusf, 2, si) | |
| 311 | VAR1 (UNOP, lfrintnudf, 2, di) | |
| cc4d934f | 312 | |
| 1709ff9b JG |
313 | /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ |
| 314 | VAR1 (UNOP, floatv2si, 2, v2sf) | |
| 315 | VAR1 (UNOP, floatv4si, 2, v4sf) | |
| 316 | VAR1 (UNOP, floatv2di, 2, v2df) | |
| 317 | ||
| 318 | VAR1 (UNOP, floatunsv2si, 2, v2sf) | |
| 319 | VAR1 (UNOP, floatunsv4si, 2, v4sf) | |
| 320 | VAR1 (UNOP, floatunsv2di, 2, v2df) | |
| 321 | ||
| cc4d934f JG |
322 | /* Implemented by |
| 323 | aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ | |
| 0ddec79f JG |
324 | BUILTIN_VALL (BINOP, zip1, 0) |
| 325 | BUILTIN_VALL (BINOP, zip2, 0) | |
| 326 | BUILTIN_VALL (BINOP, uzp1, 0) | |
| 327 | BUILTIN_VALL (BINOP, uzp2, 0) | |
| 328 | BUILTIN_VALL (BINOP, trn1, 0) | |
| 329 | BUILTIN_VALL (BINOP, trn2, 0) | |
| 0050faf8 JG |
330 | |
| 331 | /* Implemented by | |
| 332 | aarch64_frecp<FRECP:frecp_suffix><mode>. */ | |
| 0ddec79f JG |
333 | BUILTIN_GPF (UNOP, frecpe, 0) |
| 334 | BUILTIN_GPF (BINOP, frecps, 0) | |
| 335 | BUILTIN_GPF (UNOP, frecpx, 0) | |
| 0050faf8 | 336 | |
| 0ddec79f JG |
337 | BUILTIN_VDQF (UNOP, frecpe, 0) |
| 338 | BUILTIN_VDQF (BINOP, frecps, 0) | |
| 9697e620 JG |
339 | |
| 340 | BUILTIN_VDQF (UNOP, abs, 2) |