git://gcc.gnu.org / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 18c63565 | 1 | /* Machine description for AArch64 architecture. |
| 23a5b65a | 2 | Copyright (C) 2012-2014 Free Software Foundation, Inc. |
| 18c63565 JG |
3 | Contributed by ARM Ltd. |
| 4 | ||
| 5 | This file is part of GCC. | |
| 6 | ||
| 7 | GCC is free software; you can redistribute it and/or modify it | |
| 8 | under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | GCC is distributed in the hope that it will be useful, but | |
| 13 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GCC; see the file COPYING3. If not see | |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| 342be7f7 | 20 | |
| 0ddec79f JG |
21 | /* In the list below, the BUILTIN_<ITERATOR> macros expand to create |
| 22 | builtins for each of the modes described by <ITERATOR>. When adding | |
| 23 | new builtins to this list, a helpful idiom to follow is to add | |
| 24 | a line for each pattern in the md file. Thus, ADDP, which has one | |
| 25 | pattern defined for the VD_BHSI iterator, and one for DImode, has two | |
| 26 | entries below. | |
| 342be7f7 | 27 | |
| 0ddec79f JG |
28 | Parameter 1 is the 'type' of the intrinsic. This is used to |
| 29 | describe the type modifiers (for example; unsigned) applied to | |
| 30 | each of the parameters to the intrinsic function. | |
| 342be7f7 | 31 | |
| 0ddec79f JG |
32 | Parameter 2 is the name of the intrinsic. This is appended |
| 33 | to `__builtin_aarch64_<name><mode>` to give the intrinsic name | |
| 34 | as exported to the front-ends. | |
| 342be7f7 | 35 | |
| 0ddec79f JG |
36 | Parameter 3 describes how to map from the name to the CODE_FOR_ |
| 37 | macro holding the RTL pattern for the intrinsic. This mapping is: | |
| 38 | 0 - CODE_FOR_aarch64_<name><mode> | |
| 39 | 1-9 - CODE_FOR_<name><mode><1-9> | |
| 40 | 10 - CODE_FOR_<name><mode>. */ | |
| 41 | ||
| c6a29a09 | 42 | BUILTIN_VD1 (CREATE, create, 0) |
| 0ddec79f JG |
43 | BUILTIN_VDC (COMBINE, combine, 0) |
| 44 | BUILTIN_VB (BINOP, pmul, 0) | |
| 45 | BUILTIN_VDQF (UNOP, sqrt, 2) | |
| 46 | BUILTIN_VD_BHSI (BINOP, addp, 0) | |
| 47 | VAR1 (UNOP, addp, 0, di) | |
| 0fe04f5c | 48 | BUILTIN_VDQ_BHSI (UNOP, clz, 2) |
| 0ddec79f | 49 | |
| dafb9b64 | 50 | BUILTIN_VALL (GETLANE, be_checked_get_lane, 0) |
| 66adb8eb | 51 | |
| c6a29a09 AL |
52 | VAR1 (REINTERP_SS, reinterpretdi, 0, v1df) |
| 53 | VAR1 (REINTERP_SS, reinterpretv8qi, 0, v1df) | |
| 54 | VAR1 (REINTERP_SS, reinterpretv4hi, 0, v1df) | |
| 55 | VAR1 (REINTERP_SS, reinterpretv2si, 0, v1df) | |
| 56 | VAR1 (REINTERP_SS, reinterpretv2sf, 0, v1df) | |
| 57 | BUILTIN_VD (REINTERP_SS, reinterpretv1df, 0) | |
| bcd48995 | 58 | |
| c6a29a09 | 59 | BUILTIN_VD (REINTERP_SU, reinterpretv1df, 0) |
| bcd48995 | 60 | |
| c6a29a09 AL |
61 | VAR1 (REINTERP_US, reinterpretdi, 0, v1df) |
| 62 | VAR1 (REINTERP_US, reinterpretv8qi, 0, v1df) | |
| 63 | VAR1 (REINTERP_US, reinterpretv4hi, 0, v1df) | |
| 64 | VAR1 (REINTERP_US, reinterpretv2si, 0, v1df) | |
| 65 | VAR1 (REINTERP_US, reinterpretv2sf, 0, v1df) | |
| bcd48995 | 66 | |
| c6a29a09 | 67 | BUILTIN_VD (REINTERP_SP, reinterpretv1df, 0) |
| bcd48995 | 68 | |
| c6a29a09 AL |
69 | VAR1 (REINTERP_PS, reinterpretdi, 0, v1df) |
| 70 | VAR1 (REINTERP_PS, reinterpretv8qi, 0, v1df) | |
| 71 | VAR1 (REINTERP_PS, reinterpretv4hi, 0, v1df) | |
| 72 | VAR1 (REINTERP_PS, reinterpretv2si, 0, v1df) | |
| 73 | VAR1 (REINTERP_PS, reinterpretv2sf, 0, v1df) | |
| 0ddec79f | 74 | |
| 342be7f7 | 75 | /* Implemented by aarch64_<sur>q<r>shl<mode>. */ |
| 0ddec79f | 76 | BUILTIN_VSDQ_I (BINOP, sqshl, 0) |
| de10bcce | 77 | BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0) |
| 0ddec79f | 78 | BUILTIN_VSDQ_I (BINOP, sqrshl, 0) |
| de10bcce | 79 | BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0) |
| 342be7f7 | 80 | /* Implemented by aarch64_<su_optab><optab><mode>. */ |
| 0ddec79f | 81 | BUILTIN_VSDQ_I (BINOP, sqadd, 0) |
| de10bcce | 82 | BUILTIN_VSDQ_I (BINOPU, uqadd, 0) |
| 0ddec79f | 83 | BUILTIN_VSDQ_I (BINOP, sqsub, 0) |
| de10bcce | 84 | BUILTIN_VSDQ_I (BINOPU, uqsub, 0) |
| 342be7f7 | 85 | /* Implemented by aarch64_<sur>qadd<mode>. */ |
| 918621d3 | 86 | BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0) |
| de10bcce | 87 | BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0) |
| 342be7f7 JG |
88 | |
| 89 | /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>. */ | |
| 0ddec79f JG |
90 | BUILTIN_VDC (GETLANE, get_dregoi, 0) |
| 91 | BUILTIN_VDC (GETLANE, get_dregci, 0) | |
| 92 | BUILTIN_VDC (GETLANE, get_dregxi, 0) | |
| 342be7f7 | 93 | /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 0ddec79f JG |
94 | BUILTIN_VQ (GETLANE, get_qregoi, 0) |
| 95 | BUILTIN_VQ (GETLANE, get_qregci, 0) | |
| 96 | BUILTIN_VQ (GETLANE, get_qregxi, 0) | |
| 342be7f7 | 97 | /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>. */ |
| 0ddec79f JG |
98 | BUILTIN_VQ (SETLANE, set_qregoi, 0) |
| 99 | BUILTIN_VQ (SETLANE, set_qregci, 0) | |
| 100 | BUILTIN_VQ (SETLANE, set_qregxi, 0) | |
| 342be7f7 | 101 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
102 | BUILTIN_VDC (LOADSTRUCT, ld2, 0) |
| 103 | BUILTIN_VDC (LOADSTRUCT, ld3, 0) | |
| 104 | BUILTIN_VDC (LOADSTRUCT, ld4, 0) | |
| 342be7f7 | 105 | /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
106 | BUILTIN_VQ (LOADSTRUCT, ld2, 0) |
| 107 | BUILTIN_VQ (LOADSTRUCT, ld3, 0) | |
| 108 | BUILTIN_VQ (LOADSTRUCT, ld4, 0) | |
| 342be7f7 | 109 | /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>. */ |
| 0ddec79f JG |
110 | BUILTIN_VDC (STORESTRUCT, st2, 0) |
| 111 | BUILTIN_VDC (STORESTRUCT, st3, 0) | |
| 112 | BUILTIN_VDC (STORESTRUCT, st4, 0) | |
| 342be7f7 | 113 | /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>. */ |
| 0ddec79f JG |
114 | BUILTIN_VQ (STORESTRUCT, st2, 0) |
| 115 | BUILTIN_VQ (STORESTRUCT, st3, 0) | |
| 116 | BUILTIN_VQ (STORESTRUCT, st4, 0) | |
| 342be7f7 | 117 | |
| ba081b77 JG |
118 | BUILTIN_VQ (STORESTRUCT_LANE, st2_lane, 0) |
| 119 | BUILTIN_VQ (STORESTRUCT_LANE, st3_lane, 0) | |
| 120 | BUILTIN_VQ (STORESTRUCT_LANE, st4_lane, 0) | |
| 121 | ||
| 0ddec79f JG |
122 | BUILTIN_VQW (BINOP, saddl2, 0) |
| 123 | BUILTIN_VQW (BINOP, uaddl2, 0) | |
| 124 | BUILTIN_VQW (BINOP, ssubl2, 0) | |
| 125 | BUILTIN_VQW (BINOP, usubl2, 0) | |
| 126 | BUILTIN_VQW (BINOP, saddw2, 0) | |
| 127 | BUILTIN_VQW (BINOP, uaddw2, 0) | |
| 128 | BUILTIN_VQW (BINOP, ssubw2, 0) | |
| 129 | BUILTIN_VQW (BINOP, usubw2, 0) | |
| 342be7f7 | 130 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */ |
| 0ddec79f JG |
131 | BUILTIN_VDW (BINOP, saddl, 0) |
| 132 | BUILTIN_VDW (BINOP, uaddl, 0) | |
| 133 | BUILTIN_VDW (BINOP, ssubl, 0) | |
| 134 | BUILTIN_VDW (BINOP, usubl, 0) | |
| 342be7f7 | 135 | /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */ |
| 0ddec79f JG |
136 | BUILTIN_VDW (BINOP, saddw, 0) |
| 137 | BUILTIN_VDW (BINOP, uaddw, 0) | |
| 138 | BUILTIN_VDW (BINOP, ssubw, 0) | |
| 139 | BUILTIN_VDW (BINOP, usubw, 0) | |
| 342be7f7 | 140 | /* Implemented by aarch64_<sur>h<addsub><mode>. */ |
| 0ddec79f JG |
141 | BUILTIN_VQ_S (BINOP, shadd, 0) |
| 142 | BUILTIN_VQ_S (BINOP, uhadd, 0) | |
| 143 | BUILTIN_VQ_S (BINOP, srhadd, 0) | |
| 144 | BUILTIN_VQ_S (BINOP, urhadd, 0) | |
| 342be7f7 | 145 | /* Implemented by aarch64_<sur><addsub>hn<mode>. */ |
| 0ddec79f JG |
146 | BUILTIN_VQN (BINOP, addhn, 0) |
| 147 | BUILTIN_VQN (BINOP, raddhn, 0) | |
| 342be7f7 | 148 | /* Implemented by aarch64_<sur><addsub>hn2<mode>. */ |
| 0ddec79f JG |
149 | BUILTIN_VQN (TERNOP, addhn2, 0) |
| 150 | BUILTIN_VQN (TERNOP, raddhn2, 0) | |
| 342be7f7 | 151 | |
| 0ddec79f | 152 | BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0) |
| 342be7f7 | 153 | /* Implemented by aarch64_<sur>qmovn<mode>. */ |
| 0ddec79f JG |
154 | BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0) |
| 155 | BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0) | |
| 342be7f7 | 156 | /* Implemented by aarch64_s<optab><mode>. */ |
| 9551c7ec AV |
157 | BUILTIN_VSDQ_I (UNOP, sqabs, 0) |
| 158 | BUILTIN_VSDQ_I (UNOP, sqneg, 0) | |
| 342be7f7 | 159 | |
| 0ddec79f JG |
160 | BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0) |
| 161 | BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0) | |
| 162 | BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0) | |
| 163 | BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0) | |
| 164 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0) | |
| 165 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0) | |
| 166 | BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0) | |
| 167 | BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0) | |
| 168 | BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0) | |
| 169 | BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0) | |
| 170 | BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0) | |
| 171 | BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0) | |
| 342be7f7 | 172 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>. */ |
| 0ddec79f JG |
173 | BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0) |
| 174 | BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0) | |
| 342be7f7 | 175 | /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>. */ |
| 0ddec79f JG |
176 | BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0) |
| 177 | BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0) | |
| 342be7f7 | 178 | |
| 0ddec79f JG |
179 | BUILTIN_VSD_HSI (BINOP, sqdmull, 0) |
| 180 | BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0) | |
| 181 | BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0) | |
| 182 | BUILTIN_VD_HSI (BINOP, sqdmull_n, 0) | |
| 183 | BUILTIN_VQ_HSI (BINOP, sqdmull2, 0) | |
| 184 | BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0) | |
| 185 | BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0) | |
| 186 | BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0) | |
| 342be7f7 | 187 | /* Implemented by aarch64_sq<r>dmulh<mode>. */ |
| 0ddec79f JG |
188 | BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0) |
| 189 | BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0) | |
| b7d7d917 | 190 | /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>. */ |
| 0ddec79f | 191 | BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0) |
| d2937a2e | 192 | BUILTIN_VSDQ_HSI (TERNOP, sqdmulh_laneq, 0) |
| 0ddec79f | 193 | BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0) |
| d2937a2e | 194 | BUILTIN_VSDQ_HSI (TERNOP, sqrdmulh_laneq, 0) |
| 0ddec79f JG |
195 | BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0) |
| 196 | BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0) | |
| 342be7f7 | 197 | |
| 0ddec79f | 198 | BUILTIN_VSDQ_I_DI (BINOP, ashl, 3) |
| 342be7f7 | 199 | /* Implemented by aarch64_<sur>shl<mode>. */ |
| 0ddec79f | 200 | BUILTIN_VSDQ_I_DI (BINOP, sshl, 0) |
| 918621d3 | 201 | BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0) |
| 0ddec79f | 202 | BUILTIN_VSDQ_I_DI (BINOP, srshl, 0) |
| 918621d3 | 203 | BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0) |
| 342be7f7 | 204 | |
| f9a4c9a6 AV |
205 | BUILTIN_VDQ_I (SHIFTIMM, ashr, 3) |
| 206 | VAR1 (SHIFTIMM, ashr_simd, 0, di) | |
| 252c7556 AV |
207 | BUILTIN_VDQ_I (SHIFTIMM, lshr, 3) |
| 208 | VAR1 (USHIFTIMM, lshr_simd, 0, di) | |
| 342be7f7 | 209 | /* Implemented by aarch64_<sur>shr_n<mode>. */ |
| 0ddec79f | 210 | BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0) |
| 918621d3 | 211 | BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0) |
| 342be7f7 | 212 | /* Implemented by aarch64_<sur>sra_n<mode>. */ |
| 0ddec79f | 213 | BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0) |
| de10bcce | 214 | BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0) |
| 0ddec79f | 215 | BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0) |
| de10bcce | 216 | BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0) |
| 342be7f7 | 217 | /* Implemented by aarch64_<sur>shll_n<mode>. */ |
| 0ddec79f | 218 | BUILTIN_VDW (SHIFTIMM, sshll_n, 0) |
| 918621d3 | 219 | BUILTIN_VDW (USHIFTIMM, ushll_n, 0) |
| 342be7f7 | 220 | /* Implemented by aarch64_<sur>shll2_n<mode>. */ |
| 0ddec79f JG |
221 | BUILTIN_VQW (SHIFTIMM, sshll2_n, 0) |
| 222 | BUILTIN_VQW (SHIFTIMM, ushll2_n, 0) | |
| 342be7f7 | 223 | /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>. */ |
| 0ddec79f JG |
224 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0) |
| 225 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0) | |
| 226 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0) | |
| de10bcce | 227 | BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0) |
| 0ddec79f | 228 | BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0) |
| de10bcce | 229 | BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0) |
| 342be7f7 | 230 | /* Implemented by aarch64_<sur>s<lr>i_n<mode>. */ |
| 0ddec79f | 231 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0) |
| de10bcce | 232 | BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0) |
| 0ddec79f | 233 | BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0) |
| de10bcce | 234 | BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0) |
| 342be7f7 | 235 | /* Implemented by aarch64_<sur>qshl<u>_n<mode>. */ |
| de10bcce | 236 | BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0) |
| 0ddec79f | 237 | BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0) |
| de10bcce | 238 | BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0) |
| 342be7f7 JG |
239 | |
| 240 | /* Implemented by aarch64_cm<cmp><mode>. */ | |
| bb60efd9 JG |
241 | BUILTIN_VALLDI (BINOP, cmeq, 0) |
| 242 | BUILTIN_VALLDI (BINOP, cmge, 0) | |
| 243 | BUILTIN_VALLDI (BINOP, cmgt, 0) | |
| 244 | BUILTIN_VALLDI (BINOP, cmle, 0) | |
| 245 | BUILTIN_VALLDI (BINOP, cmlt, 0) | |
| 342be7f7 | 246 | /* Implemented by aarch64_cm<cmp><mode>. */ |
| 889b9412 JG |
247 | BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0) |
| 248 | BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0) | |
| 0ddec79f | 249 | BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0) |
| 342be7f7 | 250 | |
| 36054fab JG |
251 | /* Implemented by reduc_<sur>plus_<mode>. */ |
| 252 | BUILTIN_VALL (UNOP, reduc_splus_, 10) | |
| 253 | BUILTIN_VDQ (UNOP, reduc_uplus_, 10) | |
| 0ac198d3 | 254 | |
| 998eaf97 JG |
255 | /* Implemented by reduc_<maxmin_uns>_<mode>. */ |
| 256 | BUILTIN_VDQIF (UNOP, reduc_smax_, 10) | |
| 257 | BUILTIN_VDQIF (UNOP, reduc_smin_, 10) | |
| 258 | BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10) | |
| 259 | BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10) | |
| 260 | BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10) | |
| 261 | BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10) | |
| 262 | ||
| 263 | /* Implemented by <maxmin><mode>3. | |
| 264 | smax variants map to fmaxnm, | |
| 265 | smax_nan variants map to fmax. */ | |
| 266 | BUILTIN_VDQIF (BINOP, smax, 3) | |
| 267 | BUILTIN_VDQIF (BINOP, smin, 3) | |
| 0ddec79f JG |
268 | BUILTIN_VDQ_BHSI (BINOP, umax, 3) |
| 269 | BUILTIN_VDQ_BHSI (BINOP, umin, 3) | |
| 998eaf97 JG |
270 | BUILTIN_VDQF (BINOP, smax_nan, 3) |
| 271 | BUILTIN_VDQF (BINOP, smin_nan, 3) | |
| 42fc9a7f | 272 | |
| 0659ce6f JG |
273 | /* Implemented by <frint_pattern><mode>2. */ |
| 274 | BUILTIN_VDQF (UNOP, btrunc, 2) | |
| 275 | BUILTIN_VDQF (UNOP, ceil, 2) | |
| 276 | BUILTIN_VDQF (UNOP, floor, 2) | |
| 277 | BUILTIN_VDQF (UNOP, nearbyint, 2) | |
| 278 | BUILTIN_VDQF (UNOP, rint, 2) | |
| 279 | BUILTIN_VDQF (UNOP, round, 2) | |
| 74dc11ed | 280 | BUILTIN_VDQF_DF (UNOP, frintn, 2) |
| 42fc9a7f | 281 | |
| ce966824 JG |
282 | /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2. */ |
| 283 | VAR1 (UNOP, lbtruncv2sf, 2, v2si) | |
| 284 | VAR1 (UNOP, lbtruncv4sf, 2, v4si) | |
| 285 | VAR1 (UNOP, lbtruncv2df, 2, v2di) | |
| 286 | ||
| 287 | VAR1 (UNOP, lbtruncuv2sf, 2, v2si) | |
| 288 | VAR1 (UNOP, lbtruncuv4sf, 2, v4si) | |
| 289 | VAR1 (UNOP, lbtruncuv2df, 2, v2di) | |
| 290 | ||
| 291 | VAR1 (UNOP, lroundv2sf, 2, v2si) | |
| 292 | VAR1 (UNOP, lroundv4sf, 2, v4si) | |
| 293 | VAR1 (UNOP, lroundv2df, 2, v2di) | |
| 294 | /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2. */ | |
| 295 | VAR1 (UNOP, lroundsf, 2, si) | |
| 296 | VAR1 (UNOP, lrounddf, 2, di) | |
| 297 | ||
| 298 | VAR1 (UNOP, lrounduv2sf, 2, v2si) | |
| 299 | VAR1 (UNOP, lrounduv4sf, 2, v4si) | |
| 300 | VAR1 (UNOP, lrounduv2df, 2, v2di) | |
| 301 | VAR1 (UNOP, lroundusf, 2, si) | |
| 302 | VAR1 (UNOP, lroundudf, 2, di) | |
| 303 | ||
| 304 | VAR1 (UNOP, lceilv2sf, 2, v2si) | |
| 305 | VAR1 (UNOP, lceilv4sf, 2, v4si) | |
| 306 | VAR1 (UNOP, lceilv2df, 2, v2di) | |
| 307 | ||
| 308 | VAR1 (UNOP, lceiluv2sf, 2, v2si) | |
| 309 | VAR1 (UNOP, lceiluv4sf, 2, v4si) | |
| 310 | VAR1 (UNOP, lceiluv2df, 2, v2di) | |
| 311 | VAR1 (UNOP, lceilusf, 2, si) | |
| 312 | VAR1 (UNOP, lceiludf, 2, di) | |
| 313 | ||
| 314 | VAR1 (UNOP, lfloorv2sf, 2, v2si) | |
| 315 | VAR1 (UNOP, lfloorv4sf, 2, v4si) | |
| 316 | VAR1 (UNOP, lfloorv2df, 2, v2di) | |
| 317 | ||
| 318 | VAR1 (UNOP, lflooruv2sf, 2, v2si) | |
| 319 | VAR1 (UNOP, lflooruv4sf, 2, v4si) | |
| 320 | VAR1 (UNOP, lflooruv2df, 2, v2di) | |
| 321 | VAR1 (UNOP, lfloorusf, 2, si) | |
| 322 | VAR1 (UNOP, lfloorudf, 2, di) | |
| 323 | ||
| 324 | VAR1 (UNOP, lfrintnv2sf, 2, v2si) | |
| 325 | VAR1 (UNOP, lfrintnv4sf, 2, v4si) | |
| 326 | VAR1 (UNOP, lfrintnv2df, 2, v2di) | |
| 327 | VAR1 (UNOP, lfrintnsf, 2, si) | |
| 328 | VAR1 (UNOP, lfrintndf, 2, di) | |
| 329 | ||
| 330 | VAR1 (UNOP, lfrintnuv2sf, 2, v2si) | |
| 331 | VAR1 (UNOP, lfrintnuv4sf, 2, v4si) | |
| 332 | VAR1 (UNOP, lfrintnuv2df, 2, v2di) | |
| 333 | VAR1 (UNOP, lfrintnusf, 2, si) | |
| 334 | VAR1 (UNOP, lfrintnudf, 2, di) | |
| cc4d934f | 335 | |
| 1709ff9b JG |
336 | /* Implemented by <optab><fcvt_target><VDQF:mode>2. */ |
| 337 | VAR1 (UNOP, floatv2si, 2, v2sf) | |
| 338 | VAR1 (UNOP, floatv4si, 2, v4sf) | |
| 339 | VAR1 (UNOP, floatv2di, 2, v2df) | |
| 340 | ||
| 341 | VAR1 (UNOP, floatunsv2si, 2, v2sf) | |
| 342 | VAR1 (UNOP, floatunsv4si, 2, v4sf) | |
| 343 | VAR1 (UNOP, floatunsv2di, 2, v2df) | |
| 344 | ||
| c7f28cd5 KT |
345 | VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di) |
| 346 | ||
| cc4d934f JG |
347 | /* Implemented by |
| 348 | aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>. */ | |
| 0ddec79f JG |
349 | BUILTIN_VALL (BINOP, zip1, 0) |
| 350 | BUILTIN_VALL (BINOP, zip2, 0) | |
| 351 | BUILTIN_VALL (BINOP, uzp1, 0) | |
| 352 | BUILTIN_VALL (BINOP, uzp2, 0) | |
| 353 | BUILTIN_VALL (BINOP, trn1, 0) | |
| 354 | BUILTIN_VALL (BINOP, trn2, 0) | |
| 0050faf8 JG |
355 | |
| 356 | /* Implemented by | |
| 357 | aarch64_frecp<FRECP:frecp_suffix><mode>. */ | |
| 0ddec79f JG |
358 | BUILTIN_GPF (UNOP, frecpe, 0) |
| 359 | BUILTIN_GPF (BINOP, frecps, 0) | |
| 360 | BUILTIN_GPF (UNOP, frecpx, 0) | |
| 0050faf8 | 361 | |
| 0ddec79f JG |
362 | BUILTIN_VDQF (UNOP, frecpe, 0) |
| 363 | BUILTIN_VDQF (BINOP, frecps, 0) | |
| 9697e620 | 364 | |
| 096c59be AL |
365 | /* Implemented by a mixture of abs2 patterns. Note the DImode builtin is |
| 366 | only ever used for the int64x1_t intrinsic, there is no scalar version. */ | |
| d05d0709 | 367 | BUILTIN_VALLDI (UNOP, abs, 2) |
| 4c871069 JG |
368 | |
| 369 | VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) | |
| 370 | VAR1 (BINOP, float_truncate_hi_, 0, v4sf) | |
| 371 | ||
| 372 | VAR1 (UNOP, float_extend_lo_, 0, v2df) | |
| 373 | VAR1 (UNOP, float_truncate_lo_, 0, v2sf) | |
| dec11868 JG |
374 | |
| 375 | /* Implemented by aarch64_ld1<VALL:mode>. */ | |
| 376 | BUILTIN_VALL (LOAD1, ld1, 0) | |
| 377 | ||
| 378 | /* Implemented by aarch64_st1<VALL:mode>. */ | |
| 379 | BUILTIN_VALL (STORE1, st1, 0) | |
| 380 | ||
| 828e70c1 JG |
381 | /* Implemented by fma<mode>4. */ |
| 382 | BUILTIN_VDQF (TERNOP, fma, 4) | |
| 383 | ||
| 46e778c4 JG |
384 | /* Implemented by aarch64_simd_bsl<mode>. */ |
| 385 | BUILTIN_VDQQH (BSL_P, simd_bsl, 0) | |
| 386 | BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0) | |
| 387 | BUILTIN_VALLDIF (BSL_S, simd_bsl, 0) | |
| 388 | ||
| 5a7a4e80 TB |
389 | /* Implemented by aarch64_crypto_aes<op><mode>. */ |
| 390 | VAR1 (BINOPU, crypto_aese, 0, v16qi) | |
| 391 | VAR1 (BINOPU, crypto_aesd, 0, v16qi) | |
| 392 | VAR1 (UNOPU, crypto_aesmc, 0, v16qi) | |
| 393 | VAR1 (UNOPU, crypto_aesimc, 0, v16qi) | |
| 30442682 TB |
394 | |
| 395 | /* Implemented by aarch64_crypto_sha1<op><mode>. */ | |
| 396 | VAR1 (UNOPU, crypto_sha1h, 0, si) | |
| 397 | VAR1 (BINOPU, crypto_sha1su1, 0, v4si) | |
| 398 | VAR1 (TERNOPU, crypto_sha1c, 0, v4si) | |
| 399 | VAR1 (TERNOPU, crypto_sha1m, 0, v4si) | |
| 400 | VAR1 (TERNOPU, crypto_sha1p, 0, v4si) | |
| 401 | VAR1 (TERNOPU, crypto_sha1su0, 0, v4si) | |
| b9cb0a44 TB |
402 | |
| 403 | /* Implemented by aarch64_crypto_sha256<op><mode>. */ | |
| 404 | VAR1 (TERNOPU, crypto_sha256h, 0, v4si) | |
| 405 | VAR1 (TERNOPU, crypto_sha256h2, 0, v4si) | |
| 406 | VAR1 (BINOPU, crypto_sha256su0, 0, v4si) | |
| 407 | VAR1 (TERNOPU, crypto_sha256su1, 0, v4si) | |
| 7baa225d TB |
408 | |
| 409 | /* Implemented by aarch64_crypto_pmull<mode>. */ | |
| 410 | VAR1 (BINOPP, crypto_pmull, 0, di) | |
| 411 | VAR1 (BINOPP, crypto_pmull, 0, v2di) | |
| ae0533da AL |
412 | |
| 413 | /* Meta-op to check lane bounds of immediate in aarch64_expand_builtin. */ | |
| 414 | VAR1 (BINOPV, im_lane_bound, 0, si) |