]> gcc.gnu.org Git - gcc.git/blame - gcc/combine.c
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
c-aux-info.c (concat): Don't define.
[gcc.git] / gcc / combine.c
CommitLineData
230d793d 1/* Optimize by combining instructions for GNU compiler.
1bf27b5b 2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
230d793d
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
940d9d63
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
230d793d
RS		 20
21
22/* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
230d793d 77#include "config.h"
670ee920 78#include "system.h"
789f983a 79#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
230d793d
RS		 80#include "flags.h"
81#include "regs.h"
55310dad 82#include "hard-reg-set.h"
230d793d
RS		 83#include "basic-block.h"
84#include "insn-config.h"
49ad7cfa 85#include "function.h"
d6f4ec51
KG		 86/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87#include "expr.h"
230d793d
RS		 88#include "insn-flags.h"
89#include "insn-codes.h"
90#include "insn-attr.h"
91#include "recog.h"
92#include "real.h"
2e107e9e 93#include "toplev.h"
230d793d
RS		 94
95/* It is not safe to use ordinary gen_lowpart in combine.
96 Use gen_lowpart_for_combine instead. See comments there. */
97#define gen_lowpart dont_use_gen_lowpart_you_dummy
98
99/* Number of attempts to combine instructions in this function. */
100
101static int combine_attempts;
102
103/* Number of attempts that got as far as substitution in this function. */
104
105static int combine_merges;
106
107/* Number of instructions combined with added SETs in this function. */
108
109static int combine_extras;
110
111/* Number of instructions combined in this function. */
112
113static int combine_successes;
114
115/* Totals over entire compilation. */
116
117static int total_attempts, total_merges, total_extras, total_successes;
9210df58 118
ddd5a7c1 119/* Define a default value for REVERSIBLE_CC_MODE.
9210df58
RK		 120 We can never assume that a condition code mode is safe to reverse unless
121 the md tells us so. */
122#ifndef REVERSIBLE_CC_MODE
123#define REVERSIBLE_CC_MODE(MODE) 0
124#endif
230d793d
RS		 125\f
126/* Vector mapping INSN_UIDs to cuids.
5089e22e 127 The cuids are like uids but increase monotonically always.
230d793d
RS		 128 Combine always uses cuids so that it can compare them.
129 But actually renumbering the uids, which we used to do,
130 proves to be a bad idea because it makes it hard to compare
131 the dumps produced by earlier passes with those from later passes. */
132
133static int *uid_cuid;
4255220d 134static int max_uid_cuid;
230d793d
RS		 135
136/* Get the cuid of an insn. */
137
1427d6d2
RK		 138#define INSN_CUID(INSN) \
139(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
230d793d
RS		 140
141/* Maximum register number, which is the size of the tables below. */
142
143static int combine_max_regno;
144
145/* Record last point of death of (hard or pseudo) register n. */
146
147static rtx *reg_last_death;
148
149/* Record last point of modification of (hard or pseudo) register n. */
150
151static rtx *reg_last_set;
152
153/* Record the cuid of the last insn that invalidated memory
154 (anything that writes memory, and subroutine calls, but not pushes). */
155
156static int mem_last_set;
157
158/* Record the cuid of the last CALL_INSN
159 so we can tell whether a potential combination crosses any calls. */
160
161static int last_call_cuid;
162
163/* When `subst' is called, this is the insn that is being modified
164 (by combining in a previous insn). The PATTERN of this insn
165 is still the old pattern partially modified and it should not be
166 looked at, but this may be used to examine the successors of the insn
167 to judge whether a simplification is valid. */
168
169static rtx subst_insn;
170
0d9641d1
JW		 171/* This is an insn that belongs before subst_insn, but is not currently
172 on the insn chain. */
173
174static rtx subst_prev_insn;
175
230d793d
RS		 176/* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
182
183static int subst_low_cuid;
184
6e25d159
RK		 185/* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
187
188static HARD_REG_SET newpat_used_regs;
189
abe6e52f
RK		 190/* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
192 that location. */
193
194static rtx added_links_insn;
195
0d4d42c3
RK		 196/* Basic block number of the block in which we are performing combines. */
197static int this_basic_block;
230d793d
RS		 198\f
199/* The next group of arrays allows the recording of the last value assigned
200 to (hard or pseudo) register n. We use this information to see if a
5089e22e 201 operation being processed is redundant given a prior operation performed
230d793d
RS		 202 on the register. For example, an `and' with a constant is redundant if
203 all the zero bits are already known to be turned off.
204
205 We use an approach similar to that used by cse, but change it in the
206 following ways:
207
208 (1) We do not want to reinitialize at each label.
209 (2) It is useful, but not critical, to know the actual value assigned
210 to a register. Often just its form is helpful.
211
212 Therefore, we maintain the following arrays:
213
214 reg_last_set_value the last value assigned
215 reg_last_set_label records the value of label_tick when the
216 register was assigned
217 reg_last_set_table_tick records the value of label_tick when a
218 value using the register is assigned
219 reg_last_set_invalid set to non-zero when it is not valid
220 to use the value of this register in some
221 register's value
222
223 To understand the usage of these tables, it is important to understand
224 the distinction between the value in reg_last_set_value being valid
225 and the register being validly contained in some other expression in the
226 table.
227
228 Entry I in reg_last_set_value is valid if it is non-zero, and either
229 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
230
231 Register I may validly appear in any expression returned for the value
232 of another register if reg_n_sets[i] is 1. It may also appear in the
233 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
234 reg_last_set_invalid[j] is zero.
235
236 If an expression is found in the table containing a register which may
237 not validly appear in an expression, the register is replaced by
238 something that won't match, (clobber (const_int 0)).
239
240 reg_last_set_invalid[i] is set non-zero when register I is being assigned
241 to and reg_last_set_table_tick[i] == label_tick. */
242
0f41302f 243/* Record last value assigned to (hard or pseudo) register n. */
230d793d
RS		 244
245static rtx *reg_last_set_value;
246
247/* Record the value of label_tick when the value for register n is placed in
248 reg_last_set_value[n]. */
249
568356af 250static int *reg_last_set_label;
230d793d
RS		 251
252/* Record the value of label_tick when an expression involving register n
0f41302f 253 is placed in reg_last_set_value. */
230d793d 254
568356af 255static int *reg_last_set_table_tick;
230d793d
RS		 256
257/* Set non-zero if references to register n in expressions should not be
258 used. */
259
260static char *reg_last_set_invalid;
261
0f41302f 262/* Incremented for each label. */
230d793d 263
568356af 264static int label_tick;
230d793d
RS		 265
266/* Some registers that are set more than once and used in more than one
267 basic block are nevertheless always set in similar ways. For example,
268 a QImode register may be loaded from memory in two places on a machine
269 where byte loads zero extend.
270
951553af 271 We record in the following array what we know about the nonzero
230d793d
RS		 272 bits of a register, specifically which bits are known to be zero.
273
274 If an entry is zero, it means that we don't know anything special. */
275
55310dad 276static unsigned HOST_WIDE_INT *reg_nonzero_bits;
230d793d 277
951553af 278/* Mode used to compute significance in reg_nonzero_bits. It is the largest
5f4f0e22 279 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
230d793d 280
951553af 281static enum machine_mode nonzero_bits_mode;
230d793d 282
d0ab8cd3
RK		 283/* Nonzero if we know that a register has some leading bits that are always
284 equal to the sign bit. */
285
286static char *reg_sign_bit_copies;
287
951553af 288/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
1a26b032
RK		 289 It is zero while computing them and after combine has completed. This
290 former test prevents propagating values based on previously set values,
291 which can be incorrect if a variable is modified in a loop. */
230d793d 292
951553af 293static int nonzero_sign_valid;
55310dad
RK		 294
295/* These arrays are maintained in parallel with reg_last_set_value
296 and are used to store the mode in which the register was last set,
297 the bits that were known to be zero when it was last set, and the
298 number of sign bits copies it was known to have when it was last set. */
299
300static enum machine_mode *reg_last_set_mode;
301static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
302static char *reg_last_set_sign_bit_copies;
230d793d
RS		 303\f
304/* Record one modification to rtl structure
305 to be undone by storing old_contents into *where.
306 is_int is 1 if the contents are an int. */
307
308struct undo
309{
241cea85 310 struct undo *next;
230d793d 311 int is_int;
f5393ab9
RS		 312 union {rtx r; int i;} old_contents;
313 union {rtx *r; int *i;} where;
230d793d
RS		 314};
315
316/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
317 num_undo says how many are currently recorded.
318
319 storage is nonzero if we must undo the allocation of new storage.
320 The value of storage is what to pass to obfree.
321
322 other_insn is nonzero if we have modified some other insn in the process
241cea85 323 of working on subst_insn. It must be verified too.
230d793d 324
241cea85
RK		 325 previous_undos is the value of undobuf.undos when we started processing
326 this substitution. This will prevent gen_rtx_combine from re-used a piece
327 from the previous expression. Doing so can produce circular rtl
328 structures. */
230d793d
RS		 329
330struct undobuf
331{
230d793d 332 char *storage;
241cea85
RK		 333 struct undo *undos;
334 struct undo *frees;
335 struct undo *previous_undos;
230d793d
RS		 336 rtx other_insn;
337};
338
339static struct undobuf undobuf;
340
cc876596 341/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
230d793d 342 insn. The substitution can be undone by undo_all. If INTO is already
cc876596
RK		 343 set to NEWVAL, do not record this change. Because computing NEWVAL might
344 also call SUBST, we have to compute it before we put anything into
345 the undo table. */
230d793d
RS		 346
347#define SUBST(INTO, NEWVAL) \
241cea85
RK		 348 do { rtx _new = (NEWVAL); \
349 struct undo *_buf; \
350 \
351 if (undobuf.frees) \
352 _buf = undobuf.frees, undobuf.frees = _buf->next; \
353 else \
354 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
355 \
356 _buf->is_int = 0; \
357 _buf->where.r = &INTO; \
358 _buf->old_contents.r = INTO; \
359 INTO = _new; \
360 if (_buf->old_contents.r == INTO) \
361 _buf->next = undobuf.frees, undobuf.frees = _buf; \
362 else \
363 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 364 } while (0)
365
241cea85
RK		 366/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
367 for the value of a HOST_WIDE_INT value (including CONST_INT) is
368 not safe. */
230d793d
RS		 369
370#define SUBST_INT(INTO, NEWVAL) \
241cea85
RK		 371 do { struct undo *_buf; \
372 \
373 if (undobuf.frees) \
374 _buf = undobuf.frees, undobuf.frees = _buf->next; \
375 else \
376 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
377 \
378 _buf->is_int = 1; \
379 _buf->where.i = (int *) &INTO; \
380 _buf->old_contents.i = INTO; \
381 INTO = NEWVAL; \
382 if (_buf->old_contents.i == INTO) \
383 _buf->next = undobuf.frees, undobuf.frees = _buf; \
384 else \
385 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 386 } while (0)
387
388/* Number of times the pseudo being substituted for
389 was found and replaced. */
390
391static int n_occurrences;
392
c5ad722c
RK		 393static void init_reg_last_arrays PROTO((void));
394static void setup_incoming_promotions PROTO((void));
fe2db4fb
RK		 395static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
396static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
e009aaf3 397static int sets_function_arg_p PROTO((rtx));
fe2db4fb
RK		 398static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
399static rtx try_combine PROTO((rtx, rtx, rtx));
400static void undo_all PROTO((void));
401static rtx *find_split_point PROTO((rtx *, rtx));
402static rtx subst PROTO((rtx, rtx, rtx, int, int));
8079805d
RK		 403static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
404static rtx simplify_if_then_else PROTO((rtx));
405static rtx simplify_set PROTO((rtx));
406static rtx simplify_logical PROTO((rtx, int));
fe2db4fb
RK		 407static rtx expand_compound_operation PROTO((rtx));
408static rtx expand_field_assignment PROTO((rtx));
409static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
410 int, int, int));
71923da7 411static rtx extract_left_shift PROTO((rtx, int));
fe2db4fb
RK		 412static rtx make_compound_operation PROTO((rtx, enum rtx_code));
413static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
6139ff20 414static rtx force_to_mode PROTO((rtx, enum machine_mode,
e3d616e3 415 unsigned HOST_WIDE_INT, rtx, int));
abe6e52f 416static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
fe2db4fb 417static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
e11fa86f 418static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
fe2db4fb
RK		 419static rtx make_field_assignment PROTO((rtx));
420static rtx apply_distributive_law PROTO((rtx));
421static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
422 unsigned HOST_WIDE_INT));
423static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
424static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
425static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
426 enum rtx_code, HOST_WIDE_INT,
427 enum machine_mode, int *));
428static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
429 rtx, int));
8e2f6e35 430static int recog_for_combine PROTO((rtx *, rtx, rtx *));
fe2db4fb 431static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
d18225c4 432static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
4f90e4a0 433 ...));
fe2db4fb
RK		 434static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
435 rtx, rtx));
0c1c8ea6
RK		 436static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
437 enum machine_mode, rtx));
fe2db4fb
RK		 438static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
439static int reversible_comparison_p PROTO((rtx));
440static void update_table_tick PROTO((rtx));
441static void record_value_for_reg PROTO((rtx, rtx, rtx));
442static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
443static void record_dead_and_set_regs PROTO((rtx));
9a893315 444static int get_last_value_validate PROTO((rtx *, rtx, int, int));
fe2db4fb
RK		 445static rtx get_last_value PROTO((rtx));
446static int use_crosses_set_p PROTO((rtx, int));
447static void reg_dead_at_p_1 PROTO((rtx, rtx));
448static int reg_dead_at_p PROTO((rtx, rtx));
6eb12cef 449static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
fe2db4fb
RK		 450static int reg_bitfield_target_p PROTO((rtx, rtx));
451static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
452static void distribute_links PROTO((rtx));
6e25d159 453static void mark_used_regs_combine PROTO((rtx));
1427d6d2 454static int insn_cuid PROTO((rtx));
230d793d
RS		 455\f
456/* Main entry point for combiner. F is the first insn of the function.
457 NREGS is the first unused pseudo-reg number. */
458
459void
460combine_instructions (f, nregs)
461 rtx f;
462 int nregs;
463{
b729186a
JL		 464 register rtx insn, next;
465#ifdef HAVE_cc0
466 register rtx prev;
467#endif
230d793d
RS		 468 register int i;
469 register rtx links, nextlinks;
470
471 combine_attempts = 0;
472 combine_merges = 0;
473 combine_extras = 0;
474 combine_successes = 0;
241cea85 475 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 476
477 combine_max_regno = nregs;
478
ef026f91
RS		 479 reg_nonzero_bits
480 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
481 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
482
4c9a05bc 483 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 484 bzero (reg_sign_bit_copies, nregs * sizeof (char));
485
230d793d
RS		 486 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
487 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
568356af
RK		 489 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
490 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
5f4f0e22 491 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
55310dad
RK		 492 reg_last_set_mode
493 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
494 reg_last_set_nonzero_bits
495 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
496 reg_last_set_sign_bit_copies
497 = (char *) alloca (nregs * sizeof (char));
498
ef026f91 499 init_reg_last_arrays ();
230d793d
RS		 500
501 init_recog_no_volatile ();
502
503 /* Compute maximum uid value so uid_cuid can be allocated. */
504
505 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
506 if (INSN_UID (insn) > i)
507 i = INSN_UID (insn);
508
509 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
4255220d 510 max_uid_cuid = i;
230d793d 511
951553af 512 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
230d793d 513
951553af 514 /* Don't use reg_nonzero_bits when computing it. This can cause problems
230d793d
RS		 515 when, for example, we have j <<= 1 in a loop. */
516
951553af 517 nonzero_sign_valid = 0;
230d793d
RS		 518
519 /* Compute the mapping from uids to cuids.
520 Cuids are numbers assigned to insns, like uids,
521 except that cuids increase monotonically through the code.
522
523 Scan all SETs and see if we can deduce anything about what
951553af 524 bits are known to be zero for some registers and how many copies
d79f08e0
RK		 525 of the sign bit are known to exist for those registers.
526
527 Also set any known values so that we can use it while searching
528 for what bits are known to be set. */
529
530 label_tick = 1;
230d793d 531
bcd49eb7
JW		 532 /* We need to initialize it here, because record_dead_and_set_regs may call
533 get_last_value. */
534 subst_prev_insn = NULL_RTX;
535
7988fd36
RK		 536 setup_incoming_promotions ();
537
230d793d
RS		 538 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
539 {
4255220d 540 uid_cuid[INSN_UID (insn)] = ++i;
d79f08e0
RK		 541 subst_low_cuid = i;
542 subst_insn = insn;
543
230d793d 544 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
d79f08e0
RK		 545 {
546 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
547 record_dead_and_set_regs (insn);
2dab894a
RK		 548
549#ifdef AUTO_INC_DEC
550 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
551 if (REG_NOTE_KIND (links) == REG_INC)
552 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
553#endif
d79f08e0
RK		 554 }
555
556 if (GET_CODE (insn) == CODE_LABEL)
557 label_tick++;
230d793d
RS		 558 }
559
951553af 560 nonzero_sign_valid = 1;
230d793d
RS		 561
562 /* Now scan all the insns in forward order. */
563
0d4d42c3 564 this_basic_block = -1;
230d793d
RS		 565 label_tick = 1;
566 last_call_cuid = 0;
567 mem_last_set = 0;
ef026f91 568 init_reg_last_arrays ();
7988fd36
RK		 569 setup_incoming_promotions ();
570
230d793d
RS		 571 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
572 {
573 next = 0;
574
0d4d42c3 575 /* If INSN starts a new basic block, update our basic block number. */
f085c9cd 576 if (this_basic_block + 1 < n_basic_blocks
3b413743 577 && BLOCK_HEAD (this_basic_block + 1) == insn)
0d4d42c3
RK		 578 this_basic_block++;
579
230d793d
RS		 580 if (GET_CODE (insn) == CODE_LABEL)
581 label_tick++;
582
0d4d42c3 583 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
230d793d
RS		 584 {
585 /* Try this insn with each insn it links back to. */
586
587 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
5f4f0e22 588 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
230d793d
RS		 589 goto retry;
590
591 /* Try each sequence of three linked insns ending with this one. */
592
593 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
594 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
595 nextlinks = XEXP (nextlinks, 1))
596 if ((next = try_combine (insn, XEXP (links, 0),
597 XEXP (nextlinks, 0))) != 0)
598 goto retry;
599
600#ifdef HAVE_cc0
601 /* Try to combine a jump insn that uses CC0
602 with a preceding insn that sets CC0, and maybe with its
603 logical predecessor as well.
604 This is how we make decrement-and-branch insns.
605 We need this special code because data flow connections
606 via CC0 do not get entered in LOG_LINKS. */
607
608 if (GET_CODE (insn) == JUMP_INSN
609 && (prev = prev_nonnote_insn (insn)) != 0
610 && GET_CODE (prev) == INSN
611 && sets_cc0_p (PATTERN (prev)))
612 {
5f4f0e22 613 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 614 goto retry;
615
616 for (nextlinks = LOG_LINKS (prev); nextlinks;
617 nextlinks = XEXP (nextlinks, 1))
618 if ((next = try_combine (insn, prev,
619 XEXP (nextlinks, 0))) != 0)
620 goto retry;
621 }
622
623 /* Do the same for an insn that explicitly references CC0. */
624 if (GET_CODE (insn) == INSN
625 && (prev = prev_nonnote_insn (insn)) != 0
626 && GET_CODE (prev) == INSN
627 && sets_cc0_p (PATTERN (prev))
628 && GET_CODE (PATTERN (insn)) == SET
629 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
630 {
5f4f0e22 631 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 632 goto retry;
633
634 for (nextlinks = LOG_LINKS (prev); nextlinks;
635 nextlinks = XEXP (nextlinks, 1))
636 if ((next = try_combine (insn, prev,
637 XEXP (nextlinks, 0))) != 0)
638 goto retry;
639 }
640
641 /* Finally, see if any of the insns that this insn links to
642 explicitly references CC0. If so, try this insn, that insn,
5089e22e 643 and its predecessor if it sets CC0. */
230d793d
RS		 644 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
645 if (GET_CODE (XEXP (links, 0)) == INSN
646 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
647 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
648 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
649 && GET_CODE (prev) == INSN
650 && sets_cc0_p (PATTERN (prev))
651 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
652 goto retry;
653#endif
654
655 /* Try combining an insn with two different insns whose results it
656 uses. */
657 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
658 for (nextlinks = XEXP (links, 1); nextlinks;
659 nextlinks = XEXP (nextlinks, 1))
660 if ((next = try_combine (insn, XEXP (links, 0),
661 XEXP (nextlinks, 0))) != 0)
662 goto retry;
663
664 if (GET_CODE (insn) != NOTE)
665 record_dead_and_set_regs (insn);
666
667 retry:
668 ;
669 }
670 }
671
672 total_attempts += combine_attempts;
673 total_merges += combine_merges;
674 total_extras += combine_extras;
675 total_successes += combine_successes;
1a26b032 676
951553af 677 nonzero_sign_valid = 0;
972b320c
R		 678
679 /* Make recognizer allow volatile MEMs again. */
680 init_recog ();
230d793d 681}
ef026f91
RS		 682
683/* Wipe the reg_last_xxx arrays in preparation for another pass. */
684
685static void
686init_reg_last_arrays ()
687{
688 int nregs = combine_max_regno;
689
4c9a05bc
RK		 690 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
692 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
693 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
694 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
ef026f91 695 bzero (reg_last_set_invalid, nregs * sizeof (char));
4c9a05bc
RK		 696 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
697 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 698 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699}
230d793d 700\f
7988fd36
RK		 701/* Set up any promoted values for incoming argument registers. */
702
ee791cc3 703static void
7988fd36
RK		 704setup_incoming_promotions ()
705{
706#ifdef PROMOTE_FUNCTION_ARGS
707 int regno;
708 rtx reg;
709 enum machine_mode mode;
710 int unsignedp;
711 rtx first = get_insns ();
712
713 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
714 if (FUNCTION_ARG_REGNO_P (regno)
715 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
38a448ca
RH		 716 {
717 record_value_for_reg
718 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
719 : SIGN_EXTEND),
720 GET_MODE (reg),
721 gen_rtx_CLOBBER (mode, const0_rtx)));
722 }
7988fd36
RK		 723#endif
724}
725\f
91102d5a
RK		 726/* Called via note_stores. If X is a pseudo that is narrower than
727 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
230d793d
RS		 728
729 If we are setting only a portion of X and we can't figure out what
730 portion, assume all bits will be used since we don't know what will
d0ab8cd3
RK		 731 be happening.
732
733 Similarly, set how many bits of X are known to be copies of the sign bit
734 at all locations in the function. This is the smallest number implied
735 by any set of X. */
230d793d
RS		 736
737static void
951553af 738set_nonzero_bits_and_sign_copies (x, set)
230d793d
RS		 739 rtx x;
740 rtx set;
741{
d0ab8cd3
RK		 742 int num;
743
230d793d
RS		 744 if (GET_CODE (x) == REG
745 && REGNO (x) >= FIRST_PSEUDO_REGISTER
e8095e80
RK		 746 /* If this register is undefined at the start of the file, we can't
747 say what its contents were. */
e881bb1b 748 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
5f4f0e22 749 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
230d793d 750 {
2dab894a 751 if (set == 0 || GET_CODE (set) == CLOBBER)
e8095e80
RK		 752 {
753 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 754 reg_sign_bit_copies[REGNO (x)] = 1;
e8095e80
RK		 755 return;
756 }
230d793d
RS		 757
758 /* If this is a complex assignment, see if we can convert it into a
5089e22e 759 simple assignment. */
230d793d 760 set = expand_field_assignment (set);
d79f08e0
RK		 761
762 /* If this is a simple assignment, or we have a paradoxical SUBREG,
763 set what we know about X. */
764
765 if (SET_DEST (set) == x
766 || (GET_CODE (SET_DEST (set)) == SUBREG
705c7b3b
JW		 767 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
768 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
d79f08e0 769 && SUBREG_REG (SET_DEST (set)) == x))
d0ab8cd3 770 {
9afa3d54
RK		 771 rtx src = SET_SRC (set);
772
773#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
774 /* If X is narrower than a word and SRC is a non-negative
775 constant that would appear negative in the mode of X,
776 sign-extend it for use in reg_nonzero_bits because some
777 machines (maybe most) will actually do the sign-extension
778 and this is the conservative approach.
779
780 ??? For 2.5, try to tighten up the MD files in this regard
781 instead of this kludge. */
782
783 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
784 && GET_CODE (src) == CONST_INT
785 && INTVAL (src) > 0
786 && 0 != (INTVAL (src)
787 & ((HOST_WIDE_INT) 1
9e69be8c 788 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 789 src = GEN_INT (INTVAL (src)
790 | ((HOST_WIDE_INT) (-1)
791 << GET_MODE_BITSIZE (GET_MODE (x))));
792#endif
793
951553af 794 reg_nonzero_bits[REGNO (x)]
9afa3d54 795 |= nonzero_bits (src, nonzero_bits_mode);
d0ab8cd3
RK		 796 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
797 if (reg_sign_bit_copies[REGNO (x)] == 0
798 || reg_sign_bit_copies[REGNO (x)] > num)
799 reg_sign_bit_copies[REGNO (x)] = num;
800 }
230d793d 801 else
d0ab8cd3 802 {
951553af 803 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 804 reg_sign_bit_copies[REGNO (x)] = 1;
d0ab8cd3 805 }
230d793d
RS		 806 }
807}
808\f
809/* See if INSN can be combined into I3. PRED and SUCC are optionally
810 insns that were previously combined into I3 or that will be combined
811 into the merger of INSN and I3.
812
813 Return 0 if the combination is not allowed for any reason.
814
815 If the combination is allowed, *PDEST will be set to the single
816 destination of INSN and *PSRC to the single source, and this function
817 will return 1. */
818
819static int
820can_combine_p (insn, i3, pred, succ, pdest, psrc)
821 rtx insn;
822 rtx i3;
e51712db
KG		 823 rtx pred ATTRIBUTE_UNUSED;
824 rtx succ;
230d793d
RS		 825 rtx *pdest, *psrc;
826{
827 int i;
828 rtx set = 0, src, dest;
b729186a
JL		 829 rtx p;
830#ifdef AUTO_INC_DEC
76d31c63 831 rtx link;
b729186a 832#endif
230d793d
RS		 833 int all_adjacent = (succ ? (next_active_insn (insn) == succ
834 && next_active_insn (succ) == i3)
835 : next_active_insn (insn) == i3);
836
837 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
838 or a PARALLEL consisting of such a SET and CLOBBERs.
839
840 If INSN has CLOBBER parallel parts, ignore them for our processing.
841 By definition, these happen during the execution of the insn. When it
842 is merged with another insn, all bets are off. If they are, in fact,
843 needed and aren't also supplied in I3, they may be added by
844 recog_for_combine. Otherwise, it won't match.
845
846 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
847 note.
848
849 Get the source and destination of INSN. If more than one, can't
850 combine. */
851
852 if (GET_CODE (PATTERN (insn)) == SET)
853 set = PATTERN (insn);
854 else if (GET_CODE (PATTERN (insn)) == PARALLEL
855 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
856 {
857 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
858 {
859 rtx elt = XVECEXP (PATTERN (insn), 0, i);
860
861 switch (GET_CODE (elt))
862 {
e3258cef
R		 863 /* This is important to combine floating point insns
864 for the SH4 port. */
865 case USE:
866 /* Combining an isolated USE doesn't make sense.
867 We depend here on combinable_i3_pat to reject them. */
868 /* The code below this loop only verifies that the inputs of
869 the SET in INSN do not change. We call reg_set_between_p
870 to verify that the REG in the USE does not change betweeen
871 I3 and INSN.
872 If the USE in INSN was for a pseudo register, the matching
873 insn pattern will likely match any register; combining this
874 with any other USE would only be safe if we knew that the
875 used registers have identical values, or if there was
876 something to tell them apart, e.g. different modes. For
877 now, we forgo such compilcated tests and simply disallow
878 combining of USES of pseudo registers with any other USE. */
879 if (GET_CODE (XEXP (elt, 0)) == REG
880 && GET_CODE (PATTERN (i3)) == PARALLEL)
881 {
882 rtx i3pat = PATTERN (i3);
883 int i = XVECLEN (i3pat, 0) - 1;
884 int regno = REGNO (XEXP (elt, 0));
885 do
886 {
887 rtx i3elt = XVECEXP (i3pat, 0, i);
888 if (GET_CODE (i3elt) == USE
889 && GET_CODE (XEXP (i3elt, 0)) == REG
890 && (REGNO (XEXP (i3elt, 0)) == regno
891 ? reg_set_between_p (XEXP (elt, 0),
892 PREV_INSN (insn), i3)
893 : regno >= FIRST_PSEUDO_REGISTER))
894 return 0;
895 }
896 while (--i >= 0);
897 }
898 break;
899
230d793d
RS		 900 /* We can ignore CLOBBERs. */
901 case CLOBBER:
902 break;
903
904 case SET:
905 /* Ignore SETs whose result isn't used but not those that
906 have side-effects. */
907 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
908 && ! side_effects_p (elt))
909 break;
910
911 /* If we have already found a SET, this is a second one and
912 so we cannot combine with this insn. */
913 if (set)
914 return 0;
915
916 set = elt;
917 break;
918
919 default:
920 /* Anything else means we can't combine. */
921 return 0;
922 }
923 }
924
925 if (set == 0
926 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
927 so don't do anything with it. */
928 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
929 return 0;
930 }
931 else
932 return 0;
933
934 if (set == 0)
935 return 0;
936
937 set = expand_field_assignment (set);
938 src = SET_SRC (set), dest = SET_DEST (set);
939
940 /* Don't eliminate a store in the stack pointer. */
941 if (dest == stack_pointer_rtx
230d793d
RS		 942 /* If we couldn't eliminate a field assignment, we can't combine. */
943 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
944 /* Don't combine with an insn that sets a register to itself if it has
945 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
5f4f0e22 946 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
230d793d
RS		 947 /* Can't merge a function call. */
948 || GET_CODE (src) == CALL
cd5e8f1f 949 /* Don't eliminate a function call argument. */
4dca5ec5
RK		 950 || (GET_CODE (i3) == CALL_INSN
951 && (find_reg_fusage (i3, USE, dest)
952 || (GET_CODE (dest) == REG
953 && REGNO (dest) < FIRST_PSEUDO_REGISTER
954 && global_regs[REGNO (dest)])))
230d793d
RS		 955 /* Don't substitute into an incremented register. */
956 || FIND_REG_INC_NOTE (i3, dest)
957 || (succ && FIND_REG_INC_NOTE (succ, dest))
ec35104c 958#if 0
230d793d 959 /* Don't combine the end of a libcall into anything. */
ec35104c
JL		 960 /* ??? This gives worse code, and appears to be unnecessary, since no
961 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
962 use REG_RETVAL notes for noconflict blocks, but other code here
963 makes sure that those insns don't disappear. */
5f4f0e22 964 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
ec35104c 965#endif
230d793d
RS		 966 /* Make sure that DEST is not used after SUCC but before I3. */
967 || (succ && ! all_adjacent
968 && reg_used_between_p (dest, succ, i3))
969 /* Make sure that the value that is to be substituted for the register
970 does not use any registers whose values alter in between. However,
971 If the insns are adjacent, a use can't cross a set even though we
972 think it might (this can happen for a sequence of insns each setting
973 the same destination; reg_last_set of that register might point to
d81481d3
RK		 974 a NOTE). If INSN has a REG_EQUIV note, the register is always
975 equivalent to the memory so the substitution is valid even if there
976 are intervening stores. Also, don't move a volatile asm or
977 UNSPEC_VOLATILE across any other insns. */
230d793d 978 || (! all_adjacent
d81481d3
RK		 979 && (((GET_CODE (src) != MEM
980 || ! find_reg_note (insn, REG_EQUIV, src))
981 && use_crosses_set_p (src, INSN_CUID (insn)))
a66a10c7
RS		 982 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
983 || GET_CODE (src) == UNSPEC_VOLATILE))
230d793d
RS		 984 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
985 better register allocation by not doing the combine. */
986 || find_reg_note (i3, REG_NO_CONFLICT, dest)
987 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
988 /* Don't combine across a CALL_INSN, because that would possibly
989 change whether the life span of some REGs crosses calls or not,
990 and it is a pain to update that information.
991 Exception: if source is a constant, moving it later can't hurt.
992 Accept that special case, because it helps -fforce-addr a lot. */
993 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
994 return 0;
995
996 /* DEST must either be a REG or CC0. */
997 if (GET_CODE (dest) == REG)
998 {
999 /* If register alignment is being enforced for multi-word items in all
1000 cases except for parameters, it is possible to have a register copy
1001 insn referencing a hard register that is not allowed to contain the
1002 mode being copied and which would not be valid as an operand of most
1003 insns. Eliminate this problem by not combining with such an insn.
1004
1005 Also, on some machines we don't want to extend the life of a hard
4d2c432d
RK		 1006 register.
1007
1008 This is the same test done in can_combine except that we don't test
1009 if SRC is a CALL operation to permit a hard register with
1010 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1011 into account. */
230d793d
RS		 1012
1013 if (GET_CODE (src) == REG
1014 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1015 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
c448a43e
RK		 1016 /* Don't extend the life of a hard register unless it is
1017 user variable (if we have few registers) or it can't
1018 fit into the desired register (meaning something special
ecd40809
RK		 1019 is going on).
1020 Also avoid substituting a return register into I3, because
1021 reload can't handle a conflict with constraints of other
1022 inputs. */
230d793d 1023 || (REGNO (src) < FIRST_PSEUDO_REGISTER
c448a43e 1024 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
f95182a4
ILT		 1025 || (SMALL_REGISTER_CLASSES
1026 && ((! all_adjacent && ! REG_USERVAR_P (src))
1027 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
e9a25f70 1028 && ! REG_USERVAR_P (src))))))))
230d793d
RS		 1029 return 0;
1030 }
1031 else if (GET_CODE (dest) != CC0)
1032 return 0;
1033
5f96750d
RS		 1034 /* Don't substitute for a register intended as a clobberable operand.
1035 Similarly, don't substitute an expression containing a register that
1036 will be clobbered in I3. */
230d793d
RS		 1037 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1038 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1039 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
5f96750d
RS		 1040 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1041 src)
1042 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
230d793d
RS		 1043 return 0;
1044
1045 /* If INSN contains anything volatile, or is an `asm' (whether volatile
d276f2bb 1046 or not), reject, unless nothing volatile comes between it and I3 */
230d793d
RS		 1047
1048 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
d276f2bb
CM		 1049 {
1050 /* Make sure succ doesn't contain a volatile reference. */
1051 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1052 return 0;
1053
1054 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1055 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1056 && p != succ && volatile_refs_p (PATTERN (p)))
1057 return 0;
1058 }
230d793d 1059
b79ee7eb
RH		 1060 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1061 to be an explicit register variable, and was chosen for a reason. */
1062
1063 if (GET_CODE (src) == ASM_OPERANDS
1064 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1065 return 0;
1066
4b2cb4a2
RS		 1067 /* If there are any volatile insns between INSN and I3, reject, because
1068 they might affect machine state. */
1069
1070 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1071 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1072 && p != succ && volatile_insn_p (PATTERN (p)))
1073 return 0;
1074
230d793d
RS		 1075 /* If INSN or I2 contains an autoincrement or autodecrement,
1076 make sure that register is not used between there and I3,
1077 and not already used in I3 either.
1078 Also insist that I3 not be a jump; if it were one
1079 and the incremented register were spilled, we would lose. */
1080
1081#ifdef AUTO_INC_DEC
1082 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1083 if (REG_NOTE_KIND (link) == REG_INC
1084 && (GET_CODE (i3) == JUMP_INSN
1085 || reg_used_between_p (XEXP (link, 0), insn, i3)
1086 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1087 return 0;
1088#endif
1089
1090#ifdef HAVE_cc0
1091 /* Don't combine an insn that follows a CC0-setting insn.
1092 An insn that uses CC0 must not be separated from the one that sets it.
1093 We do, however, allow I2 to follow a CC0-setting insn if that insn
1094 is passed as I1; in that case it will be deleted also.
1095 We also allow combining in this case if all the insns are adjacent
1096 because that would leave the two CC0 insns adjacent as well.
1097 It would be more logical to test whether CC0 occurs inside I1 or I2,
1098 but that would be much slower, and this ought to be equivalent. */
1099
1100 p = prev_nonnote_insn (insn);
1101 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1102 && ! all_adjacent)
1103 return 0;
1104#endif
1105
1106 /* If we get here, we have passed all the tests and the combination is
1107 to be allowed. */
1108
1109 *pdest = dest;
1110 *psrc = src;
1111
1112 return 1;
1113}
1114\f
956d6950
JL		 1115/* Check if PAT is an insn - or a part of it - used to set up an
1116 argument for a function in a hard register. */
1117
1118static int
1119sets_function_arg_p (pat)
1120 rtx pat;
1121{
1122 int i;
1123 rtx inner_dest;
1124
1125 switch (GET_CODE (pat))
1126 {
1127 case INSN:
1128 return sets_function_arg_p (PATTERN (pat));
1129
1130 case PARALLEL:
1131 for (i = XVECLEN (pat, 0); --i >= 0;)
1132 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1133 return 1;
1134
1135 break;
1136
1137 case SET:
1138 inner_dest = SET_DEST (pat);
1139 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1140 || GET_CODE (inner_dest) == SUBREG
1141 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1142 inner_dest = XEXP (inner_dest, 0);
1143
1144 return (GET_CODE (inner_dest) == REG
1145 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1146 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1d300e19
KG		 1147
1148 default:
1149 break;
956d6950
JL		 1150 }
1151
1152 return 0;
1153}
1154
230d793d
RS		 1155/* LOC is the location within I3 that contains its pattern or the component
1156 of a PARALLEL of the pattern. We validate that it is valid for combining.
1157
1158 One problem is if I3 modifies its output, as opposed to replacing it
1159 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1160 so would produce an insn that is not equivalent to the original insns.
1161
1162 Consider:
1163
1164 (set (reg:DI 101) (reg:DI 100))
1165 (set (subreg:SI (reg:DI 101) 0) <foo>)
1166
1167 This is NOT equivalent to:
1168
1169 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1170 (set (reg:DI 101) (reg:DI 100))])
1171
1172 Not only does this modify 100 (in which case it might still be valid
1173 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1174
1175 We can also run into a problem if I2 sets a register that I1
1176 uses and I1 gets directly substituted into I3 (not via I2). In that
1177 case, we would be getting the wrong value of I2DEST into I3, so we
1178 must reject the combination. This case occurs when I2 and I1 both
1179 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1180 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1181 of a SET must prevent combination from occurring.
1182
e9a25f70 1183 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
c448a43e
RK		 1184 if the destination of a SET is a hard register that isn't a user
1185 variable.
230d793d
RS		 1186
1187 Before doing the above check, we first try to expand a field assignment
1188 into a set of logical operations.
1189
1190 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1191 we place a register that is both set and used within I3. If more than one
1192 such register is detected, we fail.
1193
1194 Return 1 if the combination is valid, zero otherwise. */
1195
1196static int
1197combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1198 rtx i3;
1199 rtx *loc;
1200 rtx i2dest;
1201 rtx i1dest;
1202 int i1_not_in_src;
1203 rtx *pi3dest_killed;
1204{
1205 rtx x = *loc;
1206
1207 if (GET_CODE (x) == SET)
1208 {
1209 rtx set = expand_field_assignment (x);
1210 rtx dest = SET_DEST (set);
1211 rtx src = SET_SRC (set);
29a82058
JL		 1212 rtx inner_dest = dest;
1213
1214#if 0
1215 rtx inner_src = src;
1216#endif
230d793d
RS		 1217
1218 SUBST (*loc, set);
1219
1220 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1221 || GET_CODE (inner_dest) == SUBREG
1222 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1223 inner_dest = XEXP (inner_dest, 0);
1224
1225 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1226 was added. */
1227#if 0
1228 while (GET_CODE (inner_src) == STRICT_LOW_PART
1229 || GET_CODE (inner_src) == SUBREG
1230 || GET_CODE (inner_src) == ZERO_EXTRACT)
1231 inner_src = XEXP (inner_src, 0);
1232
1233 /* If it is better that two different modes keep two different pseudos,
1234 avoid combining them. This avoids producing the following pattern
1235 on a 386:
1236 (set (subreg:SI (reg/v:QI 21) 0)
1237 (lshiftrt:SI (reg/v:SI 20)
1238 (const_int 24)))
1239 If that were made, reload could not handle the pair of
1240 reg 20/21, since it would try to get any GENERAL_REGS
1241 but some of them don't handle QImode. */
1242
1243 if (rtx_equal_p (inner_src, i2dest)
1244 && GET_CODE (inner_dest) == REG
1245 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1246 return 0;
1247#endif
1248
1249 /* Check for the case where I3 modifies its output, as
1250 discussed above. */
1251 if ((inner_dest != dest
1252 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1253 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
956d6950 1254
3f508eca
RK		 1255 /* This is the same test done in can_combine_p except that we
1256 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
956d6950
JL		 1257 CALL operation. Moreover, we can't test all_adjacent; we don't
1258 have to, since this instruction will stay in place, thus we are
1259 not considering increasing the lifetime of INNER_DEST.
1260
1261 Also, if this insn sets a function argument, combining it with
1262 something that might need a spill could clobber a previous
1263 function argument; the all_adjacent test in can_combine_p also
1264 checks this; here, we do a more specific test for this case. */
1265
230d793d 1266 || (GET_CODE (inner_dest) == REG
dfbe1b2f 1267 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
c448a43e
RK		 1268 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1269 GET_MODE (inner_dest))
e9a25f70
JL		 1270 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1271 && ! REG_USERVAR_P (inner_dest)
956d6950
JL		 1272 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1273 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1274 && i3 != 0
1275 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
230d793d
RS		 1276 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1277 return 0;
1278
1279 /* If DEST is used in I3, it is being killed in this insn,
36a9c2e9
JL		 1280 so record that for later.
1281 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1282 STACK_POINTER_REGNUM, since these are always considered to be
1283 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
230d793d 1284 if (pi3dest_killed && GET_CODE (dest) == REG
36a9c2e9
JL		 1285 && reg_referenced_p (dest, PATTERN (i3))
1286 && REGNO (dest) != FRAME_POINTER_REGNUM
6d7096b0
DE		 1287#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1288 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1289#endif
36a9c2e9
JL		 1290#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1291 && (REGNO (dest) != ARG_POINTER_REGNUM
1292 || ! fixed_regs [REGNO (dest)])
1293#endif
1294 && REGNO (dest) != STACK_POINTER_REGNUM)
230d793d
RS		 1295 {
1296 if (*pi3dest_killed)
1297 return 0;
1298
1299 *pi3dest_killed = dest;
1300 }
1301 }
1302
1303 else if (GET_CODE (x) == PARALLEL)
1304 {
1305 int i;
1306
1307 for (i = 0; i < XVECLEN (x, 0); i++)
1308 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1309 i1_not_in_src, pi3dest_killed))
1310 return 0;
1311 }
1312
1313 return 1;
1314}
1315\f
1316/* Try to combine the insns I1 and I2 into I3.
1317 Here I1 and I2 appear earlier than I3.
1318 I1 can be zero; then we combine just I2 into I3.
1319
1320 It we are combining three insns and the resulting insn is not recognized,
1321 try splitting it into two insns. If that happens, I2 and I3 are retained
1322 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1323 are pseudo-deleted.
1324
abe6e52f
RK		 1325 Return 0 if the combination does not work. Then nothing is changed.
1326 If we did the combination, return the insn at which combine should
1327 resume scanning. */
230d793d
RS		 1328
1329static rtx
1330try_combine (i3, i2, i1)
1331 register rtx i3, i2, i1;
1332{
1333 /* New patterns for I3 and I3, respectively. */
1334 rtx newpat, newi2pat = 0;
1335 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1336 int added_sets_1, added_sets_2;
1337 /* Total number of SETs to put into I3. */
1338 int total_sets;
1339 /* Nonzero is I2's body now appears in I3. */
1340 int i2_is_used;
1341 /* INSN_CODEs for new I3, new I2, and user of condition code. */
6a651371 1342 int insn_code_number, i2_code_number = 0, other_code_number = 0;
230d793d
RS		 1343 /* Contains I3 if the destination of I3 is used in its source, which means
1344 that the old life of I3 is being killed. If that usage is placed into
1345 I2 and not in I3, a REG_DEAD note must be made. */
1346 rtx i3dest_killed = 0;
1347 /* SET_DEST and SET_SRC of I2 and I1. */
1348 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1349 /* PATTERN (I2), or a copy of it in certain cases. */
1350 rtx i2pat;
1351 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
c4e861e8 1352 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
230d793d
RS		 1353 int i1_feeds_i3 = 0;
1354 /* Notes that must be added to REG_NOTES in I3 and I2. */
1355 rtx new_i3_notes, new_i2_notes;
176c9e6b
JW		 1356 /* Notes that we substituted I3 into I2 instead of the normal case. */
1357 int i3_subst_into_i2 = 0;
df7d75de
RK		 1358 /* Notes that I1, I2 or I3 is a MULT operation. */
1359 int have_mult = 0;
230d793d
RS		 1360
1361 int maxreg;
1362 rtx temp;
1363 register rtx link;
1364 int i;
1365
1366 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1367 This can occur when flow deletes an insn that it has merged into an
1368 auto-increment address. We also can't do anything if I3 has a
1369 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1370 libcall. */
1371
1372 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1373 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1374 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
ec35104c
JL		 1375#if 0
1376 /* ??? This gives worse code, and appears to be unnecessary, since no
1377 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1378 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1379#endif
1380)
230d793d
RS		 1381 return 0;
1382
1383 combine_attempts++;
1384
241cea85 1385 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 1386 undobuf.other_insn = 0;
1387
1388 /* Save the current high-water-mark so we can free storage if we didn't
1389 accept this combination. */
1390 undobuf.storage = (char *) oballoc (0);
1391
6e25d159
RK		 1392 /* Reset the hard register usage information. */
1393 CLEAR_HARD_REG_SET (newpat_used_regs);
1394
230d793d
RS		 1395 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1396 code below, set I1 to be the earlier of the two insns. */
1397 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1398 temp = i1, i1 = i2, i2 = temp;
1399
abe6e52f 1400 added_links_insn = 0;
137e889e 1401
230d793d
RS		 1402 /* First check for one important special-case that the code below will
1403 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1404 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1405 we may be able to replace that destination with the destination of I3.
1406 This occurs in the common code where we compute both a quotient and
1407 remainder into a structure, in which case we want to do the computation
1408 directly into the structure to avoid register-register copies.
1409
1410 We make very conservative checks below and only try to handle the
1411 most common cases of this. For example, we only handle the case
1412 where I2 and I3 are adjacent to avoid making difficult register
1413 usage tests. */
1414
1415 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1416 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1417 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
f95182a4 1418 && (! SMALL_REGISTER_CLASSES
e9a25f70
JL		 1419 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1420 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1421 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
230d793d
RS		 1422 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1423 && GET_CODE (PATTERN (i2)) == PARALLEL
1424 && ! side_effects_p (SET_DEST (PATTERN (i3)))
5089e22e
RS		 1425 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1426 below would need to check what is inside (and reg_overlap_mentioned_p
1427 doesn't support those codes anyway). Don't allow those destinations;
1428 the resulting insn isn't likely to be recognized anyway. */
1429 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1430 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
230d793d
RS		 1431 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1432 SET_DEST (PATTERN (i3)))
1433 && next_real_insn (i2) == i3)
5089e22e
RS		 1434 {
1435 rtx p2 = PATTERN (i2);
1436
1437 /* Make sure that the destination of I3,
1438 which we are going to substitute into one output of I2,
1439 is not used within another output of I2. We must avoid making this:
1440 (parallel [(set (mem (reg 69)) ...)
1441 (set (reg 69) ...)])
1442 which is not well-defined as to order of actions.
1443 (Besides, reload can't handle output reloads for this.)
1444
1445 The problem can also happen if the dest of I3 is a memory ref,
1446 if another dest in I2 is an indirect memory ref. */
1447 for (i = 0; i < XVECLEN (p2, 0); i++)
7ca919b7
RK		 1448 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1449 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
5089e22e
RS		 1450 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1451 SET_DEST (XVECEXP (p2, 0, i))))
1452 break;
230d793d 1453
5089e22e
RS		 1454 if (i == XVECLEN (p2, 0))
1455 for (i = 0; i < XVECLEN (p2, 0); i++)
1456 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1457 {
1458 combine_merges++;
230d793d 1459
5089e22e
RS		 1460 subst_insn = i3;
1461 subst_low_cuid = INSN_CUID (i2);
230d793d 1462
c4e861e8 1463 added_sets_2 = added_sets_1 = 0;
5089e22e 1464 i2dest = SET_SRC (PATTERN (i3));
230d793d 1465
5089e22e
RS		 1466 /* Replace the dest in I2 with our dest and make the resulting
1467 insn the new pattern for I3. Then skip to where we
1468 validate the pattern. Everything was set up above. */
1469 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1470 SET_DEST (PATTERN (i3)));
1471
1472 newpat = p2;
176c9e6b 1473 i3_subst_into_i2 = 1;
5089e22e
RS		 1474 goto validate_replacement;
1475 }
1476 }
230d793d
RS		 1477
1478#ifndef HAVE_cc0
1479 /* If we have no I1 and I2 looks like:
1480 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1481 (set Y OP)])
1482 make up a dummy I1 that is
1483 (set Y OP)
1484 and change I2 to be
1485 (set (reg:CC X) (compare:CC Y (const_int 0)))
1486
1487 (We can ignore any trailing CLOBBERs.)
1488
1489 This undoes a previous combination and allows us to match a branch-and-
1490 decrement insn. */
1491
1492 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1493 && XVECLEN (PATTERN (i2), 0) >= 2
1494 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1495 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1496 == MODE_CC)
1497 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1498 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1499 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1500 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1501 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1502 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1503 {
1504 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1505 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1506 break;
1507
1508 if (i == 1)
1509 {
1510 /* We make I1 with the same INSN_UID as I2. This gives it
1511 the same INSN_CUID for value tracking. Our fake I1 will
1512 never appear in the insn stream so giving it the same INSN_UID
1513 as I2 will not cause a problem. */
1514
0d9641d1 1515 subst_prev_insn = i1
38a448ca
RH		 1516 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1517 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1518 NULL_RTX);
230d793d
RS		 1519
1520 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1521 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1522 SET_DEST (PATTERN (i1)));
1523 }
1524 }
1525#endif
1526
1527 /* Verify that I2 and I1 are valid for combining. */
5f4f0e22
CH		 1528 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1529 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
230d793d
RS		 1530 {
1531 undo_all ();
1532 return 0;
1533 }
1534
1535 /* Record whether I2DEST is used in I2SRC and similarly for the other
1536 cases. Knowing this will help in register status updating below. */
1537 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1538 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1539 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1540
916f14f1 1541 /* See if I1 directly feeds into I3. It does if I1DEST is not used
230d793d
RS		 1542 in I2SRC. */
1543 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1544
1545 /* Ensure that I3's pattern can be the destination of combines. */
1546 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1547 i1 && i2dest_in_i1src && i1_feeds_i3,
1548 &i3dest_killed))
1549 {
1550 undo_all ();
1551 return 0;
1552 }
1553
df7d75de
RK		 1554 /* See if any of the insns is a MULT operation. Unless one is, we will
1555 reject a combination that is, since it must be slower. Be conservative
1556 here. */
1557 if (GET_CODE (i2src) == MULT
1558 || (i1 != 0 && GET_CODE (i1src) == MULT)
1559 || (GET_CODE (PATTERN (i3)) == SET
1560 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1561 have_mult = 1;
1562
230d793d
RS		 1563 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1564 We used to do this EXCEPT in one case: I3 has a post-inc in an
1565 output operand. However, that exception can give rise to insns like
1566 mov r3,(r3)+
1567 which is a famous insn on the PDP-11 where the value of r3 used as the
5089e22e 1568 source was model-dependent. Avoid this sort of thing. */
230d793d
RS		 1569
1570#if 0
1571 if (!(GET_CODE (PATTERN (i3)) == SET
1572 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1573 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1574 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1575 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1576 /* It's not the exception. */
1577#endif
1578#ifdef AUTO_INC_DEC
1579 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1580 if (REG_NOTE_KIND (link) == REG_INC
1581 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1582 || (i1 != 0
1583 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1584 {
1585 undo_all ();
1586 return 0;
1587 }
1588#endif
1589
1590 /* See if the SETs in I1 or I2 need to be kept around in the merged
1591 instruction: whenever the value set there is still needed past I3.
1592 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1593
1594 For the SET in I1, we have two cases: If I1 and I2 independently
1595 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1596 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1597 in I1 needs to be kept around unless I1DEST dies or is set in either
1598 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1599 I1DEST. If so, we know I1 feeds into I2. */
1600
1601 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1602
1603 added_sets_1
1604 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1605 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1606
1607 /* If the set in I2 needs to be kept around, we must make a copy of
1608 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
5089e22e 1609 PATTERN (I2), we are only substituting for the original I1DEST, not into
230d793d
RS		 1610 an already-substituted copy. This also prevents making self-referential
1611 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1612 I2DEST. */
1613
1614 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
38a448ca 1615 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
230d793d
RS		 1616 : PATTERN (i2));
1617
1618 if (added_sets_2)
1619 i2pat = copy_rtx (i2pat);
1620
1621 combine_merges++;
1622
1623 /* Substitute in the latest insn for the regs set by the earlier ones. */
1624
1625 maxreg = max_reg_num ();
1626
1627 subst_insn = i3;
230d793d
RS		 1628
1629 /* It is possible that the source of I2 or I1 may be performing an
1630 unneeded operation, such as a ZERO_EXTEND of something that is known
1631 to have the high part zero. Handle that case by letting subst look at
1632 the innermost one of them.
1633
1634 Another way to do this would be to have a function that tries to
1635 simplify a single insn instead of merging two or more insns. We don't
1636 do this because of the potential of infinite loops and because
1637 of the potential extra memory required. However, doing it the way
1638 we are is a bit of a kludge and doesn't catch all cases.
1639
1640 But only do this if -fexpensive-optimizations since it slows things down
1641 and doesn't usually win. */
1642
1643 if (flag_expensive_optimizations)
1644 {
1645 /* Pass pc_rtx so no substitutions are done, just simplifications.
1646 The cases that we are interested in here do not involve the few
1647 cases were is_replaced is checked. */
1648 if (i1)
d0ab8cd3
RK		 1649 {
1650 subst_low_cuid = INSN_CUID (i1);
1651 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1652 }
230d793d 1653 else
d0ab8cd3
RK		 1654 {
1655 subst_low_cuid = INSN_CUID (i2);
1656 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1657 }
230d793d 1658
241cea85 1659 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1660 }
1661
1662#ifndef HAVE_cc0
1663 /* Many machines that don't use CC0 have insns that can both perform an
1664 arithmetic operation and set the condition code. These operations will
1665 be represented as a PARALLEL with the first element of the vector
1666 being a COMPARE of an arithmetic operation with the constant zero.
1667 The second element of the vector will set some pseudo to the result
1668 of the same arithmetic operation. If we simplify the COMPARE, we won't
1669 match such a pattern and so will generate an extra insn. Here we test
1670 for this case, where both the comparison and the operation result are
1671 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1672 I2SRC. Later we will make the PARALLEL that contains I2. */
1673
1674 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1675 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1676 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1677 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1678 {
081f5e7e 1679#ifdef EXTRA_CC_MODES
230d793d
RS		 1680 rtx *cc_use;
1681 enum machine_mode compare_mode;
081f5e7e 1682#endif
230d793d
RS		 1683
1684 newpat = PATTERN (i3);
1685 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1686
1687 i2_is_used = 1;
1688
1689#ifdef EXTRA_CC_MODES
1690 /* See if a COMPARE with the operand we substituted in should be done
1691 with the mode that is currently being used. If not, do the same
1692 processing we do in `subst' for a SET; namely, if the destination
1693 is used only once, try to replace it with a register of the proper
1694 mode and also replace the COMPARE. */
1695 if (undobuf.other_insn == 0
1696 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1697 &undobuf.other_insn))
77fa0940
RK		 1698 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1699 i2src, const0_rtx))
230d793d
RS		 1700 != GET_MODE (SET_DEST (newpat))))
1701 {
1702 int regno = REGNO (SET_DEST (newpat));
38a448ca 1703 rtx new_dest = gen_rtx_REG (compare_mode, regno);
230d793d
RS		 1704
1705 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 1706 || (REG_N_SETS (regno) == 1 && ! added_sets_2
230d793d
RS		 1707 && ! REG_USERVAR_P (SET_DEST (newpat))))
1708 {
1709 if (regno >= FIRST_PSEUDO_REGISTER)
1710 SUBST (regno_reg_rtx[regno], new_dest);
1711
1712 SUBST (SET_DEST (newpat), new_dest);
1713 SUBST (XEXP (*cc_use, 0), new_dest);
1714 SUBST (SET_SRC (newpat),
1715 gen_rtx_combine (COMPARE, compare_mode,
1716 i2src, const0_rtx));
1717 }
1718 else
1719 undobuf.other_insn = 0;
1720 }
1721#endif
1722 }
1723 else
1724#endif
1725 {
1726 n_occurrences = 0; /* `subst' counts here */
1727
1728 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1729 need to make a unique copy of I2SRC each time we substitute it
1730 to avoid self-referential rtl. */
1731
d0ab8cd3 1732 subst_low_cuid = INSN_CUID (i2);
230d793d
RS		 1733 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1734 ! i1_feeds_i3 && i1dest_in_i1src);
241cea85 1735 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1736
1737 /* Record whether i2's body now appears within i3's body. */
1738 i2_is_used = n_occurrences;
1739 }
1740
1741 /* If we already got a failure, don't try to do more. Otherwise,
1742 try to substitute in I1 if we have it. */
1743
1744 if (i1 && GET_CODE (newpat) != CLOBBER)
1745 {
1746 /* Before we can do this substitution, we must redo the test done
1747 above (see detailed comments there) that ensures that I1DEST
0f41302f 1748 isn't mentioned in any SETs in NEWPAT that are field assignments. */
230d793d 1749
5f4f0e22
CH		 1750 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1751 0, NULL_PTR))
230d793d
RS		 1752 {
1753 undo_all ();
1754 return 0;
1755 }
1756
1757 n_occurrences = 0;
d0ab8cd3 1758 subst_low_cuid = INSN_CUID (i1);
230d793d 1759 newpat = subst (newpat, i1dest, i1src, 0, 0);
241cea85 1760 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1761 }
1762
916f14f1
RK		 1763 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1764 to count all the ways that I2SRC and I1SRC can be used. */
5f4f0e22 1765 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
916f14f1 1766 && i2_is_used + added_sets_2 > 1)
5f4f0e22 1767 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
916f14f1
RK		 1768 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1769 > 1))
230d793d
RS		 1770 /* Fail if we tried to make a new register (we used to abort, but there's
1771 really no reason to). */
1772 || max_reg_num () != maxreg
1773 /* Fail if we couldn't do something and have a CLOBBER. */
df7d75de
RK		 1774 || GET_CODE (newpat) == CLOBBER
1775 /* Fail if this new pattern is a MULT and we didn't have one before
1776 at the outer level. */
1777 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1778 && ! have_mult))
230d793d
RS		 1779 {
1780 undo_all ();
1781 return 0;
1782 }
1783
1784 /* If the actions of the earlier insns must be kept
1785 in addition to substituting them into the latest one,
1786 we must make a new PARALLEL for the latest insn
1787 to hold additional the SETs. */
1788
1789 if (added_sets_1 || added_sets_2)
1790 {
1791 combine_extras++;
1792
1793 if (GET_CODE (newpat) == PARALLEL)
1794 {
1795 rtvec old = XVEC (newpat, 0);
1796 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
38a448ca 1797 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
59888de2 1798 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
230d793d
RS		 1799 sizeof (old->elem[0]) * old->num_elem);
1800 }
1801 else
1802 {
1803 rtx old = newpat;
1804 total_sets = 1 + added_sets_1 + added_sets_2;
38a448ca 1805 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
230d793d
RS		 1806 XVECEXP (newpat, 0, 0) = old;
1807 }
1808
1809 if (added_sets_1)
1810 XVECEXP (newpat, 0, --total_sets)
1811 = (GET_CODE (PATTERN (i1)) == PARALLEL
38a448ca 1812 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
230d793d
RS		 1813
1814 if (added_sets_2)
1815 {
1816 /* If there is no I1, use I2's body as is. We used to also not do
1817 the subst call below if I2 was substituted into I3,
1818 but that could lose a simplification. */
1819 if (i1 == 0)
1820 XVECEXP (newpat, 0, --total_sets) = i2pat;
1821 else
1822 /* See comment where i2pat is assigned. */
1823 XVECEXP (newpat, 0, --total_sets)
1824 = subst (i2pat, i1dest, i1src, 0, 0);
1825 }
1826 }
1827
1828 /* We come here when we are replacing a destination in I2 with the
1829 destination of I3. */
1830 validate_replacement:
1831
6e25d159
RK		 1832 /* Note which hard regs this insn has as inputs. */
1833 mark_used_regs_combine (newpat);
1834
230d793d 1835 /* Is the result of combination a valid instruction? */
8e2f6e35 1836 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1837
1838 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1839 the second SET's destination is a register that is unused. In that case,
1840 we just need the first SET. This can occur when simplifying a divmod
1841 insn. We *must* test for this case here because the code below that
1842 splits two independent SETs doesn't handle this case correctly when it
1843 updates the register status. Also check the case where the first
1844 SET's destination is unused. That would not cause incorrect code, but
1845 does cause an unneeded insn to remain. */
1846
1847 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1848 && XVECLEN (newpat, 0) == 2
1849 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1850 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1851 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1852 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1853 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1854 && asm_noperands (newpat) < 0)
1855 {
1856 newpat = XVECEXP (newpat, 0, 0);
8e2f6e35 1857 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1858 }
1859
1860 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1861 && XVECLEN (newpat, 0) == 2
1862 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1863 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1864 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1865 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1866 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1867 && asm_noperands (newpat) < 0)
1868 {
1869 newpat = XVECEXP (newpat, 0, 1);
8e2f6e35 1870 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1871 }
1872
1873 /* If we were combining three insns and the result is a simple SET
1874 with no ASM_OPERANDS that wasn't recognized, try to split it into two
916f14f1
RK		 1875 insns. There are two ways to do this. It can be split using a
1876 machine-specific method (like when you have an addition of a large
1877 constant) or by combine in the function find_split_point. */
1878
230d793d
RS		 1879 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1880 && asm_noperands (newpat) < 0)
1881 {
916f14f1 1882 rtx m_split, *split;
42495ca0 1883 rtx ni2dest = i2dest;
916f14f1
RK		 1884
1885 /* See if the MD file can split NEWPAT. If it can't, see if letting it
42495ca0
RK		 1886 use I2DEST as a scratch register will help. In the latter case,
1887 convert I2DEST to the mode of the source of NEWPAT if we can. */
916f14f1
RK		 1888
1889 m_split = split_insns (newpat, i3);
a70c61d9
JW		 1890
1891 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1892 inputs of NEWPAT. */
1893
1894 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1895 possible to try that as a scratch reg. This would require adding
1896 more code to make it work though. */
1897
1898 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
42495ca0
RK		 1899 {
1900 /* If I2DEST is a hard register or the only use of a pseudo,
1901 we can change its mode. */
1902 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
02f4ada4 1903 && GET_MODE (SET_DEST (newpat)) != VOIDmode
60654f77 1904 && GET_CODE (i2dest) == REG
42495ca0 1905 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1906 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
42495ca0 1907 && ! REG_USERVAR_P (i2dest))))
38a448ca 1908 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
42495ca0
RK		 1909 REGNO (i2dest));
1910
38a448ca
RH		 1911 m_split = split_insns
1912 (gen_rtx_PARALLEL (VOIDmode,
1913 gen_rtvec (2, newpat,
1914 gen_rtx_CLOBBER (VOIDmode,
1915 ni2dest))),
1916 i3);
42495ca0 1917 }
916f14f1
RK		 1918
1919 if (m_split && GET_CODE (m_split) == SEQUENCE
3f508eca
RK		 1920 && XVECLEN (m_split, 0) == 2
1921 && (next_real_insn (i2) == i3
1922 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1923 INSN_CUID (i2))))
916f14f1 1924 {
1a26b032 1925 rtx i2set, i3set;
d0ab8cd3 1926 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
916f14f1 1927 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
916f14f1 1928
e4ba89be
RK		 1929 i3set = single_set (XVECEXP (m_split, 0, 1));
1930 i2set = single_set (XVECEXP (m_split, 0, 0));
1a26b032 1931
42495ca0
RK		 1932 /* In case we changed the mode of I2DEST, replace it in the
1933 pseudo-register table here. We can't do it above in case this
1934 code doesn't get executed and we do a split the other way. */
1935
1936 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1937 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1938
8e2f6e35 1939 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1a26b032
RK		 1940
1941 /* If I2 or I3 has multiple SETs, we won't know how to track
9cc96794
RK		 1942 register status, so don't use these insns. If I2's destination
1943 is used between I2 and I3, we also can't use these insns. */
1a26b032 1944
9cc96794
RK		 1945 if (i2_code_number >= 0 && i2set && i3set
1946 && (next_real_insn (i2) == i3
1947 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
8e2f6e35
BS		 1948 insn_code_number = recog_for_combine (&newi3pat, i3,
1949 &new_i3_notes);
d0ab8cd3
RK		 1950 if (insn_code_number >= 0)
1951 newpat = newi3pat;
1952
c767f54b 1953 /* It is possible that both insns now set the destination of I3.
22609cbf 1954 If so, we must show an extra use of it. */
c767f54b 1955
393de53f
RK		 1956 if (insn_code_number >= 0)
1957 {
1958 rtx new_i3_dest = SET_DEST (i3set);
1959 rtx new_i2_dest = SET_DEST (i2set);
1960
1961 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1962 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1963 || GET_CODE (new_i3_dest) == SUBREG)
1964 new_i3_dest = XEXP (new_i3_dest, 0);
1965
d4096689
RK		 1966 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1967 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1968 || GET_CODE (new_i2_dest) == SUBREG)
1969 new_i2_dest = XEXP (new_i2_dest, 0);
1970
393de53f
RK		 1971 if (GET_CODE (new_i3_dest) == REG
1972 && GET_CODE (new_i2_dest) == REG
1973 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
b1f21e0a 1974 REG_N_SETS (REGNO (new_i2_dest))++;
393de53f 1975 }
916f14f1 1976 }
230d793d
RS		 1977
1978 /* If we can split it and use I2DEST, go ahead and see if that
1979 helps things be recognized. Verify that none of the registers
1980 are set between I2 and I3. */
d0ab8cd3 1981 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
230d793d
RS		 1982#ifdef HAVE_cc0
1983 && GET_CODE (i2dest) == REG
1984#endif
1985 /* We need I2DEST in the proper mode. If it is a hard register
1986 or the only use of a pseudo, we can change its mode. */
1987 && (GET_MODE (*split) == GET_MODE (i2dest)
1988 || GET_MODE (*split) == VOIDmode
1989 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1990 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
230d793d
RS		 1991 && ! REG_USERVAR_P (i2dest)))
1992 && (next_real_insn (i2) == i3
1993 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1994 /* We can't overwrite I2DEST if its value is still used by
1995 NEWPAT. */
1996 && ! reg_referenced_p (i2dest, newpat))
1997 {
1998 rtx newdest = i2dest;
df7d75de
RK		 1999 enum rtx_code split_code = GET_CODE (*split);
2000 enum machine_mode split_mode = GET_MODE (*split);
230d793d
RS		 2001
2002 /* Get NEWDEST as a register in the proper mode. We have already
2003 validated that we can do this. */
df7d75de 2004 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
230d793d 2005 {
38a448ca 2006 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
230d793d
RS		 2007
2008 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2009 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2010 }
2011
2012 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2013 an ASHIFT. This can occur if it was inside a PLUS and hence
2014 appeared to be a memory address. This is a kludge. */
df7d75de 2015 if (split_code == MULT
230d793d
RS		 2016 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2017 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1dc8a823
JW		 2018 {
2019 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2020 XEXP (*split, 0), GEN_INT (i)));
2021 /* Update split_code because we may not have a multiply
2022 anymore. */
2023 split_code = GET_CODE (*split);
2024 }
230d793d
RS		 2025
2026#ifdef INSN_SCHEDULING
2027 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2028 be written as a ZERO_EXTEND. */
df7d75de
RK		 2029 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2030 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
230d793d
RS		 2031 XEXP (*split, 0)));
2032#endif
2033
2034 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2035 SUBST (*split, newdest);
8e2f6e35 2036 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
df7d75de
RK		 2037
2038 /* If the split point was a MULT and we didn't have one before,
2039 don't use one now. */
2040 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
8e2f6e35 2041 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 2042 }
2043 }
2044
2045 /* Check for a case where we loaded from memory in a narrow mode and
2046 then sign extended it, but we need both registers. In that case,
2047 we have a PARALLEL with both loads from the same memory location.
2048 We can split this into a load from memory followed by a register-register
2049 copy. This saves at least one insn, more if register allocation can
f0343c74
RK		 2050 eliminate the copy.
2051
2052 We cannot do this if the destination of the second assignment is
2053 a register that we have already assumed is zero-extended. Similarly
2054 for a SUBREG of such a register. */
230d793d
RS		 2055
2056 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2057 && GET_CODE (newpat) == PARALLEL
2058 && XVECLEN (newpat, 0) == 2
2059 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2060 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2061 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2062 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2063 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2064 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2065 INSN_CUID (i2))
2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2067 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
f0343c74
RK		 2068 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2069 (GET_CODE (temp) == REG
2070 && reg_nonzero_bits[REGNO (temp)] != 0
2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2072 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2073 && (reg_nonzero_bits[REGNO (temp)]
2074 != GET_MODE_MASK (word_mode))))
2075 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2076 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2077 (GET_CODE (temp) == REG
2078 && reg_nonzero_bits[REGNO (temp)] != 0
2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2080 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2081 && (reg_nonzero_bits[REGNO (temp)]
2082 != GET_MODE_MASK (word_mode)))))
230d793d
RS		 2083 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2084 SET_SRC (XVECEXP (newpat, 0, 1)))
2085 && ! find_reg_note (i3, REG_UNUSED,
2086 SET_DEST (XVECEXP (newpat, 0, 0))))
2087 {
472fbdd1
RK		 2088 rtx ni2dest;
2089
230d793d 2090 newi2pat = XVECEXP (newpat, 0, 0);
472fbdd1 2091 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
230d793d
RS		 2092 newpat = XVECEXP (newpat, 0, 1);
2093 SUBST (SET_SRC (newpat),
472fbdd1 2094 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
8e2f6e35 2095 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2096
230d793d 2097 if (i2_code_number >= 0)
8e2f6e35 2098 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
5089e22e
RS		 2099
2100 if (insn_code_number >= 0)
2101 {
2102 rtx insn;
2103 rtx link;
2104
2105 /* If we will be able to accept this, we have made a change to the
2106 destination of I3. This can invalidate a LOG_LINKS pointing
2107 to I3. No other part of combine.c makes such a transformation.
2108
2109 The new I3 will have a destination that was previously the
2110 destination of I1 or I2 and which was used in i2 or I3. Call
2111 distribute_links to make a LOG_LINK from the next use of
2112 that destination. */
2113
2114 PATTERN (i3) = newpat;
38a448ca 2115 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
5089e22e
RS		 2116
2117 /* I3 now uses what used to be its destination and which is
2118 now I2's destination. That means we need a LOG_LINK from
2119 I3 to I2. But we used to have one, so we still will.
2120
2121 However, some later insn might be using I2's dest and have
2122 a LOG_LINK pointing at I3. We must remove this link.
2123 The simplest way to remove the link is to point it at I1,
2124 which we know will be a NOTE. */
2125
2126 for (insn = NEXT_INSN (i3);
0d4d42c3 2127 insn && (this_basic_block == n_basic_blocks - 1
3b413743 2128 || insn != BLOCK_HEAD (this_basic_block + 1));
5089e22e
RS		 2129 insn = NEXT_INSN (insn))
2130 {
2131 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
472fbdd1 2132 && reg_referenced_p (ni2dest, PATTERN (insn)))
5089e22e
RS		 2133 {
2134 for (link = LOG_LINKS (insn); link;
2135 link = XEXP (link, 1))
2136 if (XEXP (link, 0) == i3)
2137 XEXP (link, 0) = i1;
2138
2139 break;
2140 }
2141 }
2142 }
230d793d
RS		 2143 }
2144
2145 /* Similarly, check for a case where we have a PARALLEL of two independent
2146 SETs but we started with three insns. In this case, we can do the sets
2147 as two separate insns. This case occurs when some SET allows two
2148 other insns to combine, but the destination of that SET is still live. */
2149
2150 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2151 && GET_CODE (newpat) == PARALLEL
2152 && XVECLEN (newpat, 0) == 2
2153 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2154 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2155 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2156 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2158 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2159 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2160 INSN_CUID (i2))
2161 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2162 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2163 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2164 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2165 XVECEXP (newpat, 0, 0))
2166 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2167 XVECEXP (newpat, 0, 1)))
2168 {
e9a25f70
JL		 2169 /* Normally, it doesn't matter which of the two is done first,
2170 but it does if one references cc0. In that case, it has to
2171 be first. */
2172#ifdef HAVE_cc0
2173 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2174 {
2175 newi2pat = XVECEXP (newpat, 0, 0);
2176 newpat = XVECEXP (newpat, 0, 1);
2177 }
2178 else
2179#endif
2180 {
2181 newi2pat = XVECEXP (newpat, 0, 1);
2182 newpat = XVECEXP (newpat, 0, 0);
2183 }
230d793d 2184
8e2f6e35 2185 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2186
230d793d 2187 if (i2_code_number >= 0)
8e2f6e35 2188 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 2189 }
2190
2191 /* If it still isn't recognized, fail and change things back the way they
2192 were. */
2193 if ((insn_code_number < 0
2194 /* Is the result a reasonable ASM_OPERANDS? */
2195 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2196 {
2197 undo_all ();
2198 return 0;
2199 }
2200
2201 /* If we had to change another insn, make sure it is valid also. */
2202 if (undobuf.other_insn)
2203 {
230d793d
RS		 2204 rtx other_pat = PATTERN (undobuf.other_insn);
2205 rtx new_other_notes;
2206 rtx note, next;
2207
6e25d159
RK		 2208 CLEAR_HARD_REG_SET (newpat_used_regs);
2209
8e2f6e35
BS		 2210 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2211 &new_other_notes);
230d793d
RS		 2212
2213 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2214 {
2215 undo_all ();
2216 return 0;
2217 }
2218
2219 PATTERN (undobuf.other_insn) = other_pat;
2220
2221 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2222 are still valid. Then add any non-duplicate notes added by
2223 recog_for_combine. */
2224 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2225 {
2226 next = XEXP (note, 1);
2227
2228 if (REG_NOTE_KIND (note) == REG_UNUSED
2229 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1a26b032
RK		 2230 {
2231 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2232 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
1a26b032
RK		 2233
2234 remove_note (undobuf.other_insn, note);
2235 }
230d793d
RS		 2236 }
2237
1a26b032
RK		 2238 for (note = new_other_notes; note; note = XEXP (note, 1))
2239 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2240 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 2241
230d793d 2242 distribute_notes (new_other_notes, undobuf.other_insn,
5f4f0e22 2243 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
230d793d
RS		 2244 }
2245
2246 /* We now know that we can do this combination. Merge the insns and
2247 update the status of registers and LOG_LINKS. */
2248
2249 {
2250 rtx i3notes, i2notes, i1notes = 0;
2251 rtx i3links, i2links, i1links = 0;
2252 rtx midnotes = 0;
230d793d 2253 register int regno;
ff3467a9
JW		 2254 /* Compute which registers we expect to eliminate. newi2pat may be setting
2255 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2256 same as i3dest, in which case newi2pat may be setting i1dest. */
2257 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2258 || i2dest_in_i2src || i2dest_in_i1src
230d793d 2259 ? 0 : i2dest);
ff3467a9
JW		 2260 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2261 || (newi2pat && reg_set_p (i1dest, newi2pat))
2262 ? 0 : i1dest);
230d793d
RS		 2263
2264 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2265 clear them. */
2266 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2267 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2268 if (i1)
2269 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2270
2271 /* Ensure that we do not have something that should not be shared but
2272 occurs multiple times in the new insns. Check this by first
5089e22e 2273 resetting all the `used' flags and then copying anything is shared. */
230d793d
RS		 2274
2275 reset_used_flags (i3notes);
2276 reset_used_flags (i2notes);
2277 reset_used_flags (i1notes);
2278 reset_used_flags (newpat);
2279 reset_used_flags (newi2pat);
2280 if (undobuf.other_insn)
2281 reset_used_flags (PATTERN (undobuf.other_insn));
2282
2283 i3notes = copy_rtx_if_shared (i3notes);
2284 i2notes = copy_rtx_if_shared (i2notes);
2285 i1notes = copy_rtx_if_shared (i1notes);
2286 newpat = copy_rtx_if_shared (newpat);
2287 newi2pat = copy_rtx_if_shared (newi2pat);
2288 if (undobuf.other_insn)
2289 reset_used_flags (PATTERN (undobuf.other_insn));
2290
2291 INSN_CODE (i3) = insn_code_number;
2292 PATTERN (i3) = newpat;
2293 if (undobuf.other_insn)
2294 INSN_CODE (undobuf.other_insn) = other_code_number;
2295
2296 /* We had one special case above where I2 had more than one set and
2297 we replaced a destination of one of those sets with the destination
2298 of I3. In that case, we have to update LOG_LINKS of insns later
176c9e6b
JW		 2299 in this basic block. Note that this (expensive) case is rare.
2300
2301 Also, in this case, we must pretend that all REG_NOTEs for I2
2302 actually came from I3, so that REG_UNUSED notes from I2 will be
2303 properly handled. */
2304
2305 if (i3_subst_into_i2)
2306 {
2307 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2308 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2309 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2310 && ! find_reg_note (i2, REG_UNUSED,
2311 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2312 for (temp = NEXT_INSN (i2);
2313 temp && (this_basic_block == n_basic_blocks - 1
3b413743 2314 || BLOCK_HEAD (this_basic_block) != temp);
176c9e6b
JW		 2315 temp = NEXT_INSN (temp))
2316 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2317 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2318 if (XEXP (link, 0) == i2)
2319 XEXP (link, 0) = i3;
2320
2321 if (i3notes)
2322 {
2323 rtx link = i3notes;
2324 while (XEXP (link, 1))
2325 link = XEXP (link, 1);
2326 XEXP (link, 1) = i2notes;
2327 }
2328 else
2329 i3notes = i2notes;
2330 i2notes = 0;
2331 }
230d793d
RS		 2332
2333 LOG_LINKS (i3) = 0;
2334 REG_NOTES (i3) = 0;
2335 LOG_LINKS (i2) = 0;
2336 REG_NOTES (i2) = 0;
2337
2338 if (newi2pat)
2339 {
2340 INSN_CODE (i2) = i2_code_number;
2341 PATTERN (i2) = newi2pat;
2342 }
2343 else
2344 {
2345 PUT_CODE (i2, NOTE);
2346 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2347 NOTE_SOURCE_FILE (i2) = 0;
2348 }
2349
2350 if (i1)
2351 {
2352 LOG_LINKS (i1) = 0;
2353 REG_NOTES (i1) = 0;
2354 PUT_CODE (i1, NOTE);
2355 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2356 NOTE_SOURCE_FILE (i1) = 0;
2357 }
2358
2359 /* Get death notes for everything that is now used in either I3 or
6eb12cef
RK		 2360 I2 and used to die in a previous insn. If we built two new
2361 patterns, move from I1 to I2 then I2 to I3 so that we get the
2362 proper movement on registers that I2 modifies. */
230d793d 2363
230d793d 2364 if (newi2pat)
6eb12cef
RK		 2365 {
2366 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2367 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2368 }
2369 else
2370 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2371 i3, &midnotes);
230d793d
RS		 2372
2373 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2374 if (i3notes)
5f4f0e22
CH		 2375 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2376 elim_i2, elim_i1);
230d793d 2377 if (i2notes)
5f4f0e22
CH		 2378 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2379 elim_i2, elim_i1);
230d793d 2380 if (i1notes)
5f4f0e22
CH		 2381 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2382 elim_i2, elim_i1);
230d793d 2383 if (midnotes)
5f4f0e22
CH		 2384 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2385 elim_i2, elim_i1);
230d793d
RS		 2386
2387 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2388 know these are REG_UNUSED and want them to go to the desired insn,
1a26b032
RK		 2389 so we always pass it as i3. We have not counted the notes in
2390 reg_n_deaths yet, so we need to do so now. */
2391
230d793d 2392 if (newi2pat && new_i2_notes)
1a26b032
RK		 2393 {
2394 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2395 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2396 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2397
2398 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2399 }
2400
230d793d 2401 if (new_i3_notes)
1a26b032
RK		 2402 {
2403 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2404 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2405 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2406
2407 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2408 }
230d793d
RS		 2409
2410 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
e9a25f70
JL		 2411 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2412 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2413 in that case, it might delete I2. Similarly for I2 and I1.
1a26b032
RK		 2414 Show an additional death due to the REG_DEAD note we make here. If
2415 we discard it in distribute_notes, we will decrement it again. */
d0ab8cd3 2416
230d793d 2417 if (i3dest_killed)
1a26b032
RK		 2418 {
2419 if (GET_CODE (i3dest_killed) == REG)
b1f21e0a 2420 REG_N_DEATHS (REGNO (i3dest_killed))++;
1a26b032 2421
e9a25f70 2422 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
38a448ca
RH		 2423 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2424 NULL_RTX),
ff3467a9 2425 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
e9a25f70 2426 else
38a448ca
RH		 2427 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2428 NULL_RTX),
e9a25f70 2429 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
ff3467a9 2430 elim_i2, elim_i1);
1a26b032 2431 }
58c8c593 2432
230d793d 2433 if (i2dest_in_i2src)
58c8c593 2434 {
1a26b032 2435 if (GET_CODE (i2dest) == REG)
b1f21e0a 2436 REG_N_DEATHS (REGNO (i2dest))++;
1a26b032 2437
58c8c593 2438 if (newi2pat && reg_set_p (i2dest, newi2pat))
38a448ca 2439 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2440 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2441 else
38a448ca 2442 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2443 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2444 NULL_RTX, NULL_RTX);
2445 }
2446
230d793d 2447 if (i1dest_in_i1src)
58c8c593 2448 {
1a26b032 2449 if (GET_CODE (i1dest) == REG)
b1f21e0a 2450 REG_N_DEATHS (REGNO (i1dest))++;
1a26b032 2451
58c8c593 2452 if (newi2pat && reg_set_p (i1dest, newi2pat))
38a448ca 2453 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2454 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2455 else
38a448ca 2456 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2457 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2458 NULL_RTX, NULL_RTX);
2459 }
230d793d
RS		 2460
2461 distribute_links (i3links);
2462 distribute_links (i2links);
2463 distribute_links (i1links);
2464
2465 if (GET_CODE (i2dest) == REG)
2466 {
d0ab8cd3
RK		 2467 rtx link;
2468 rtx i2_insn = 0, i2_val = 0, set;
2469
2470 /* The insn that used to set this register doesn't exist, and
2471 this life of the register may not exist either. See if one of
2472 I3's links points to an insn that sets I2DEST. If it does,
2473 that is now the last known value for I2DEST. If we don't update
2474 this and I2 set the register to a value that depended on its old
230d793d
RS		 2475 contents, we will get confused. If this insn is used, thing
2476 will be set correctly in combine_instructions. */
d0ab8cd3
RK		 2477
2478 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2479 if ((set = single_set (XEXP (link, 0))) != 0
2480 && rtx_equal_p (i2dest, SET_DEST (set)))
2481 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2482
2483 record_value_for_reg (i2dest, i2_insn, i2_val);
230d793d
RS		 2484
2485 /* If the reg formerly set in I2 died only once and that was in I3,
2486 zero its use count so it won't make `reload' do any work. */
538fe8cd
ILT		 2487 if (! added_sets_2
2488 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2489 && ! i2dest_in_i2src)
230d793d
RS		 2490 {
2491 regno = REGNO (i2dest);
b1f21e0a
MM		 2492 REG_N_SETS (regno)--;
2493 if (REG_N_SETS (regno) == 0
e881bb1b
RH		 2494 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2495 regno))
b1f21e0a 2496 REG_N_REFS (regno) = 0;
230d793d
RS		 2497 }
2498 }
2499
2500 if (i1 && GET_CODE (i1dest) == REG)
2501 {
d0ab8cd3
RK		 2502 rtx link;
2503 rtx i1_insn = 0, i1_val = 0, set;
2504
2505 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2506 if ((set = single_set (XEXP (link, 0))) != 0
2507 && rtx_equal_p (i1dest, SET_DEST (set)))
2508 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2509
2510 record_value_for_reg (i1dest, i1_insn, i1_val);
2511
230d793d 2512 regno = REGNO (i1dest);
5af91171 2513 if (! added_sets_1 && ! i1dest_in_i1src)
230d793d 2514 {
b1f21e0a
MM		 2515 REG_N_SETS (regno)--;
2516 if (REG_N_SETS (regno) == 0
e881bb1b
RH		 2517 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2518 regno))
b1f21e0a 2519 REG_N_REFS (regno) = 0;
230d793d
RS		 2520 }
2521 }
2522
951553af 2523 /* Update reg_nonzero_bits et al for any changes that may have been made
22609cbf
RK		 2524 to this insn. */
2525
951553af 2526 note_stores (newpat, set_nonzero_bits_and_sign_copies);
22609cbf 2527 if (newi2pat)
951553af 2528 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
22609cbf 2529
230d793d
RS		 2530 /* If I3 is now an unconditional jump, ensure that it has a
2531 BARRIER following it since it may have initially been a
381ee8af 2532 conditional jump. It may also be the last nonnote insn. */
230d793d
RS		 2533
2534 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
381ee8af
TW		 2535 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2536 || GET_CODE (temp) != BARRIER))
230d793d
RS		 2537 emit_barrier_after (i3);
2538 }
2539
2540 combine_successes++;
2541
bcd49eb7
JW		 2542 /* Clear this here, so that subsequent get_last_value calls are not
2543 affected. */
2544 subst_prev_insn = NULL_RTX;
2545
abe6e52f
RK		 2546 if (added_links_insn
2547 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2548 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2549 return added_links_insn;
2550 else
2551 return newi2pat ? i2 : i3;
230d793d
RS		 2552}
2553\f
2554/* Undo all the modifications recorded in undobuf. */
2555
2556static void
2557undo_all ()
2558{
241cea85
RK		 2559 struct undo *undo, *next;
2560
2561 for (undo = undobuf.undos; undo; undo = next)
7c046e4e 2562 {
241cea85
RK		 2563 next = undo->next;
2564 if (undo->is_int)
2565 *undo->where.i = undo->old_contents.i;
7c046e4e 2566 else
241cea85
RK		 2567 *undo->where.r = undo->old_contents.r;
2568
2569 undo->next = undobuf.frees;
2570 undobuf.frees = undo;
7c046e4e 2571 }
230d793d
RS		 2572
2573 obfree (undobuf.storage);
845fc875 2574 undobuf.undos = undobuf.previous_undos = 0;
bcd49eb7
JW		 2575
2576 /* Clear this here, so that subsequent get_last_value calls are not
2577 affected. */
2578 subst_prev_insn = NULL_RTX;
230d793d
RS		 2579}
2580\f
2581/* Find the innermost point within the rtx at LOC, possibly LOC itself,
d0ab8cd3
RK		 2582 where we have an arithmetic expression and return that point. LOC will
2583 be inside INSN.
230d793d
RS		 2584
2585 try_combine will call this function to see if an insn can be split into
2586 two insns. */
2587
2588static rtx *
d0ab8cd3 2589find_split_point (loc, insn)
230d793d 2590 rtx *loc;
d0ab8cd3 2591 rtx insn;
230d793d
RS		 2592{
2593 rtx x = *loc;
2594 enum rtx_code code = GET_CODE (x);
2595 rtx *split;
6a651371
KG		 2596 int len = 0, pos = 0, unsignedp = 0;
2597 rtx inner = NULL_RTX;
230d793d
RS		 2598
2599 /* First special-case some codes. */
2600 switch (code)
2601 {
2602 case SUBREG:
2603#ifdef INSN_SCHEDULING
2604 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2605 point. */
2606 if (GET_CODE (SUBREG_REG (x)) == MEM)
2607 return loc;
2608#endif
d0ab8cd3 2609 return find_split_point (&SUBREG_REG (x), insn);
230d793d 2610
230d793d 2611 case MEM:
916f14f1 2612#ifdef HAVE_lo_sum
230d793d
RS		 2613 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2614 using LO_SUM and HIGH. */
2615 if (GET_CODE (XEXP (x, 0)) == CONST
2616 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2617 {
2618 SUBST (XEXP (x, 0),
2619 gen_rtx_combine (LO_SUM, Pmode,
2620 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2621 XEXP (x, 0)));
2622 return &XEXP (XEXP (x, 0), 0);
2623 }
230d793d
RS		 2624#endif
2625
916f14f1
RK		 2626 /* If we have a PLUS whose second operand is a constant and the
2627 address is not valid, perhaps will can split it up using
2628 the machine-specific way to split large constants. We use
ddd5a7c1 2629 the first pseudo-reg (one of the virtual regs) as a placeholder;
916f14f1
RK		 2630 it will not remain in the result. */
2631 if (GET_CODE (XEXP (x, 0)) == PLUS
2632 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2633 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2634 {
2635 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
38a448ca 2636 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
916f14f1
RK		 2637 subst_insn);
2638
2639 /* This should have produced two insns, each of which sets our
2640 placeholder. If the source of the second is a valid address,
2641 we can make put both sources together and make a split point
2642 in the middle. */
2643
2644 if (seq && XVECLEN (seq, 0) == 2
2645 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2646 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2647 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2648 && ! reg_mentioned_p (reg,
2649 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2650 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2651 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2652 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2653 && memory_address_p (GET_MODE (x),
2654 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2655 {
2656 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2657 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2658
2659 /* Replace the placeholder in SRC2 with SRC1. If we can
2660 find where in SRC2 it was placed, that can become our
2661 split point and we can replace this address with SRC2.
2662 Just try two obvious places. */
2663
2664 src2 = replace_rtx (src2, reg, src1);
2665 split = 0;
2666 if (XEXP (src2, 0) == src1)
2667 split = &XEXP (src2, 0);
2668 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2669 && XEXP (XEXP (src2, 0), 0) == src1)
2670 split = &XEXP (XEXP (src2, 0), 0);
2671
2672 if (split)
2673 {
2674 SUBST (XEXP (x, 0), src2);
2675 return split;
2676 }
2677 }
1a26b032
RK		 2678
2679 /* If that didn't work, perhaps the first operand is complex and
2680 needs to be computed separately, so make a split point there.
2681 This will occur on machines that just support REG + CONST
2682 and have a constant moved through some previous computation. */
2683
2684 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2685 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2686 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2687 == 'o')))
2688 return &XEXP (XEXP (x, 0), 0);
916f14f1
RK		 2689 }
2690 break;
2691
230d793d
RS		 2692 case SET:
2693#ifdef HAVE_cc0
2694 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2695 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2696 we need to put the operand into a register. So split at that
2697 point. */
2698
2699 if (SET_DEST (x) == cc0_rtx
2700 && GET_CODE (SET_SRC (x)) != COMPARE
2701 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2702 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2703 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2704 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2705 return &SET_SRC (x);
2706#endif
2707
2708 /* See if we can split SET_SRC as it stands. */
d0ab8cd3 2709 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2710 if (split && split != &SET_SRC (x))
2711 return split;
2712
041d7180
JL		 2713 /* See if we can split SET_DEST as it stands. */
2714 split = find_split_point (&SET_DEST (x), insn);
2715 if (split && split != &SET_DEST (x))
2716 return split;
2717
230d793d
RS		 2718 /* See if this is a bitfield assignment with everything constant. If
2719 so, this is an IOR of an AND, so split it into that. */
2720 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2721 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
5f4f0e22 2722 <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 2723 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2724 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2725 && GET_CODE (SET_SRC (x)) == CONST_INT
2726 && ((INTVAL (XEXP (SET_DEST (x), 1))
2727 + INTVAL (XEXP (SET_DEST (x), 2)))
2728 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2729 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2730 {
2731 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2732 int len = INTVAL (XEXP (SET_DEST (x), 1));
2733 int src = INTVAL (SET_SRC (x));
2734 rtx dest = XEXP (SET_DEST (x), 0);
2735 enum machine_mode mode = GET_MODE (dest);
5f4f0e22 2736 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
230d793d 2737
f76b9db2
ILT		 2738 if (BITS_BIG_ENDIAN)
2739 pos = GET_MODE_BITSIZE (mode) - len - pos;
230d793d 2740
e51712db 2741 if ((unsigned HOST_WIDE_INT) src == mask)
230d793d 2742 SUBST (SET_SRC (x),
5f4f0e22 2743 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
230d793d
RS		 2744 else
2745 SUBST (SET_SRC (x),
2746 gen_binary (IOR, mode,
2747 gen_binary (AND, mode, dest,
5f4f0e22
CH		 2748 GEN_INT (~ (mask << pos)
2749 & GET_MODE_MASK (mode))),
2750 GEN_INT (src << pos)));
230d793d
RS		 2751
2752 SUBST (SET_DEST (x), dest);
2753
d0ab8cd3 2754 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2755 if (split && split != &SET_SRC (x))
2756 return split;
2757 }
2758
2759 /* Otherwise, see if this is an operation that we can split into two.
2760 If so, try to split that. */
2761 code = GET_CODE (SET_SRC (x));
2762
2763 switch (code)
2764 {
d0ab8cd3
RK		 2765 case AND:
2766 /* If we are AND'ing with a large constant that is only a single
2767 bit and the result is only being used in a context where we
2768 need to know if it is zero or non-zero, replace it with a bit
2769 extraction. This will avoid the large constant, which might
2770 have taken more than one insn to make. If the constant were
2771 not a valid argument to the AND but took only one insn to make,
2772 this is no worse, but if it took more than one insn, it will
2773 be better. */
2774
2775 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2776 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2777 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2778 && GET_CODE (SET_DEST (x)) == REG
2779 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2780 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2781 && XEXP (*split, 0) == SET_DEST (x)
2782 && XEXP (*split, 1) == const0_rtx)
2783 {
76184def
DE		 2784 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2785 XEXP (SET_SRC (x), 0),
2786 pos, NULL_RTX, 1, 1, 0, 0);
2787 if (extraction != 0)
2788 {
2789 SUBST (SET_SRC (x), extraction);
2790 return find_split_point (loc, insn);
2791 }
d0ab8cd3
RK		 2792 }
2793 break;
2794
1a6ec070
RK		 2795 case NE:
2796 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2797 is known to be on, this can be converted into a NEG of a shift. */
2798 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2799 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4eb2cb10 2800 && 1 <= (pos = exact_log2
1a6ec070
RK		 2801 (nonzero_bits (XEXP (SET_SRC (x), 0),
2802 GET_MODE (XEXP (SET_SRC (x), 0))))))
2803 {
2804 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2805
2806 SUBST (SET_SRC (x),
2807 gen_rtx_combine (NEG, mode,
2808 gen_rtx_combine (LSHIFTRT, mode,
2809 XEXP (SET_SRC (x), 0),
4eb2cb10 2810 GEN_INT (pos))));
1a6ec070
RK		 2811
2812 split = find_split_point (&SET_SRC (x), insn);
2813 if (split && split != &SET_SRC (x))
2814 return split;
2815 }
2816 break;
2817
230d793d
RS		 2818 case SIGN_EXTEND:
2819 inner = XEXP (SET_SRC (x), 0);
101c1a3d
JL		 2820
2821 /* We can't optimize if either mode is a partial integer
2822 mode as we don't know how many bits are significant
2823 in those modes. */
2824 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2825 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2826 break;
2827
230d793d
RS		 2828 pos = 0;
2829 len = GET_MODE_BITSIZE (GET_MODE (inner));
2830 unsignedp = 0;
2831 break;
2832
2833 case SIGN_EXTRACT:
2834 case ZERO_EXTRACT:
2835 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2836 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2837 {
2838 inner = XEXP (SET_SRC (x), 0);
2839 len = INTVAL (XEXP (SET_SRC (x), 1));
2840 pos = INTVAL (XEXP (SET_SRC (x), 2));
2841
f76b9db2
ILT		 2842 if (BITS_BIG_ENDIAN)
2843 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
230d793d
RS		 2844 unsignedp = (code == ZERO_EXTRACT);
2845 }
2846 break;
e9a25f70
JL		 2847
2848 default:
2849 break;
230d793d
RS		 2850 }
2851
2852 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2853 {
2854 enum machine_mode mode = GET_MODE (SET_SRC (x));
2855
d0ab8cd3
RK		 2856 /* For unsigned, we have a choice of a shift followed by an
2857 AND or two shifts. Use two shifts for field sizes where the
2858 constant might be too large. We assume here that we can
2859 always at least get 8-bit constants in an AND insn, which is
2860 true for every current RISC. */
2861
2862 if (unsignedp && len <= 8)
230d793d
RS		 2863 {
2864 SUBST (SET_SRC (x),
2865 gen_rtx_combine
2866 (AND, mode,
2867 gen_rtx_combine (LSHIFTRT, mode,
2868 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2869 GEN_INT (pos)),
2870 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
230d793d 2871
d0ab8cd3 2872 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2873 if (split && split != &SET_SRC (x))
2874 return split;
2875 }
2876 else
2877 {
2878 SUBST (SET_SRC (x),
2879 gen_rtx_combine
d0ab8cd3 2880 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
230d793d
RS		 2881 gen_rtx_combine (ASHIFT, mode,
2882 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2883 GEN_INT (GET_MODE_BITSIZE (mode)
2884 - len - pos)),
2885 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
230d793d 2886
d0ab8cd3 2887 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2888 if (split && split != &SET_SRC (x))
2889 return split;
2890 }
2891 }
2892
2893 /* See if this is a simple operation with a constant as the second
2894 operand. It might be that this constant is out of range and hence
2895 could be used as a split point. */
2896 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2897 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2898 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2899 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2900 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2901 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2902 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2903 == 'o'))))
2904 return &XEXP (SET_SRC (x), 1);
2905
2906 /* Finally, see if this is a simple operation with its first operand
2907 not in a register. The operation might require this operand in a
2908 register, so return it as a split point. We can always do this
2909 because if the first operand were another operation, we would have
2910 already found it as a split point. */
2911 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2912 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2913 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2914 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2915 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2916 return &XEXP (SET_SRC (x), 0);
2917
2918 return 0;
2919
2920 case AND:
2921 case IOR:
2922 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2923 it is better to write this as (not (ior A B)) so we can split it.
2924 Similarly for IOR. */
2925 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2926 {
2927 SUBST (*loc,
2928 gen_rtx_combine (NOT, GET_MODE (x),
2929 gen_rtx_combine (code == IOR ? AND : IOR,
2930 GET_MODE (x),
2931 XEXP (XEXP (x, 0), 0),
2932 XEXP (XEXP (x, 1), 0))));
d0ab8cd3 2933 return find_split_point (loc, insn);
230d793d
RS		 2934 }
2935
2936 /* Many RISC machines have a large set of logical insns. If the
2937 second operand is a NOT, put it first so we will try to split the
2938 other operand first. */
2939 if (GET_CODE (XEXP (x, 1)) == NOT)
2940 {
2941 rtx tem = XEXP (x, 0);
2942 SUBST (XEXP (x, 0), XEXP (x, 1));
2943 SUBST (XEXP (x, 1), tem);
2944 }
2945 break;
e9a25f70
JL		 2946
2947 default:
2948 break;
230d793d
RS		 2949 }
2950
2951 /* Otherwise, select our actions depending on our rtx class. */
2952 switch (GET_RTX_CLASS (code))
2953 {
2954 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2955 case '3':
d0ab8cd3 2956 split = find_split_point (&XEXP (x, 2), insn);
230d793d
RS		 2957 if (split)
2958 return split;
0f41302f 2959 /* ... fall through ... */
230d793d
RS		 2960 case '2':
2961 case 'c':
2962 case '<':
d0ab8cd3 2963 split = find_split_point (&XEXP (x, 1), insn);
230d793d
RS		 2964 if (split)
2965 return split;
0f41302f 2966 /* ... fall through ... */
230d793d
RS		 2967 case '1':
2968 /* Some machines have (and (shift ...) ...) insns. If X is not
2969 an AND, but XEXP (X, 0) is, use it as our split point. */
2970 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2971 return &XEXP (x, 0);
2972
d0ab8cd3 2973 split = find_split_point (&XEXP (x, 0), insn);
230d793d
RS		 2974 if (split)
2975 return split;
2976 return loc;
2977 }
2978
2979 /* Otherwise, we don't have a split point. */
2980 return 0;
2981}
2982\f
2983/* Throughout X, replace FROM with TO, and return the result.
2984 The result is TO if X is FROM;
2985 otherwise the result is X, but its contents may have been modified.
2986 If they were modified, a record was made in undobuf so that
2987 undo_all will (among other things) return X to its original state.
2988
2989 If the number of changes necessary is too much to record to undo,
2990 the excess changes are not made, so the result is invalid.
2991 The changes already made can still be undone.
2992 undobuf.num_undo is incremented for such changes, so by testing that
2993 the caller can tell whether the result is valid.
2994
2995 `n_occurrences' is incremented each time FROM is replaced.
2996
2997 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2998
5089e22e 2999 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
230d793d
RS		 3000 by copying if `n_occurrences' is non-zero. */
3001
3002static rtx
3003subst (x, from, to, in_dest, unique_copy)
3004 register rtx x, from, to;
3005 int in_dest;
3006 int unique_copy;
3007{
f24ad0e4 3008 register enum rtx_code code = GET_CODE (x);
230d793d 3009 enum machine_mode op0_mode = VOIDmode;
6f7d635c 3010 register const char *fmt;
8079805d
RK		 3011 register int len, i;
3012 rtx new;
230d793d
RS		 3013
3014/* Two expressions are equal if they are identical copies of a shared
3015 RTX or if they are both registers with the same register number
3016 and mode. */
3017
3018#define COMBINE_RTX_EQUAL_P(X,Y) \
3019 ((X) == (Y) \
3020 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3021 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3022
3023 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3024 {
3025 n_occurrences++;
3026 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3027 }
3028
3029 /* If X and FROM are the same register but different modes, they will
3030 not have been seen as equal above. However, flow.c will make a
3031 LOG_LINKS entry for that case. If we do nothing, we will try to
3032 rerecognize our original insn and, when it succeeds, we will
3033 delete the feeding insn, which is incorrect.
3034
3035 So force this insn not to match in this (rare) case. */
3036 if (! in_dest && code == REG && GET_CODE (from) == REG
3037 && REGNO (x) == REGNO (from))
38a448ca 3038 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 3039
3040 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3041 of which may contain things that can be combined. */
3042 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3043 return x;
3044
3045 /* It is possible to have a subexpression appear twice in the insn.
3046 Suppose that FROM is a register that appears within TO.
3047 Then, after that subexpression has been scanned once by `subst',
3048 the second time it is scanned, TO may be found. If we were
3049 to scan TO here, we would find FROM within it and create a
3050 self-referent rtl structure which is completely wrong. */
3051 if (COMBINE_RTX_EQUAL_P (x, to))
3052 return to;
3053
4f4b3679
RH		 3054 /* Parallel asm_operands need special attention because all of the
3055 inputs are shared across the arms. Furthermore, unsharing the
3056 rtl results in recognition failures. Failure to handle this case
3057 specially can result in circular rtl.
3058
3059 Solve this by doing a normal pass across the first entry of the
3060 parallel, and only processing the SET_DESTs of the subsequent
3061 entries. Ug. */
3062
3063 if (code == PARALLEL
3064 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3065 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
230d793d 3066 {
4f4b3679
RH		 3067 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3068
3069 /* If this substitution failed, this whole thing fails. */
3070 if (GET_CODE (new) == CLOBBER
3071 && XEXP (new, 0) == const0_rtx)
3072 return new;
3073
3074 SUBST (XVECEXP (x, 0, 0), new);
3075
3076 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
230d793d 3077 {
4f4b3679
RH		 3078 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3079
3080 if (GET_CODE (dest) != REG
3081 && GET_CODE (dest) != CC0
3082 && GET_CODE (dest) != PC)
230d793d 3083 {
4f4b3679 3084 new = subst (dest, from, to, 0, unique_copy);
230d793d 3085
4f4b3679
RH		 3086 /* If this substitution failed, this whole thing fails. */
3087 if (GET_CODE (new) == CLOBBER
3088 && XEXP (new, 0) == const0_rtx)
3089 return new;
230d793d 3090
4f4b3679 3091 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
230d793d
RS		 3092 }
3093 }
4f4b3679
RH		 3094 }
3095 else
3096 {
3097 len = GET_RTX_LENGTH (code);
3098 fmt = GET_RTX_FORMAT (code);
3099
3100 /* We don't need to process a SET_DEST that is a register, CC0,
3101 or PC, so set up to skip this common case. All other cases
3102 where we want to suppress replacing something inside a
3103 SET_SRC are handled via the IN_DEST operand. */
3104 if (code == SET
3105 && (GET_CODE (SET_DEST (x)) == REG
3106 || GET_CODE (SET_DEST (x)) == CC0
3107 || GET_CODE (SET_DEST (x)) == PC))
3108 fmt = "ie";
3109
3110 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3111 constant. */
3112 if (fmt[0] == 'e')
3113 op0_mode = GET_MODE (XEXP (x, 0));
3114
3115 for (i = 0; i < len; i++)
230d793d 3116 {
4f4b3679 3117 if (fmt[i] == 'E')
230d793d 3118 {
4f4b3679
RH		 3119 register int j;
3120 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3121 {
3122 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3123 {
3124 new = (unique_copy && n_occurrences
3125 ? copy_rtx (to) : to);
3126 n_occurrences++;
3127 }
3128 else
3129 {
3130 new = subst (XVECEXP (x, i, j), from, to, 0,
3131 unique_copy);
3132
3133 /* If this substitution failed, this whole thing
3134 fails. */
3135 if (GET_CODE (new) == CLOBBER
3136 && XEXP (new, 0) == const0_rtx)
3137 return new;
3138 }
3139
3140 SUBST (XVECEXP (x, i, j), new);
3141 }
3142 }
3143 else if (fmt[i] == 'e')
3144 {
3145 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3146 {
3147 /* In general, don't install a subreg involving two
3148 modes not tieable. It can worsen register
3149 allocation, and can even make invalid reload
3150 insns, since the reg inside may need to be copied
3151 from in the outside mode, and that may be invalid
3152 if it is an fp reg copied in integer mode.
3153
3154 We allow two exceptions to this: It is valid if
3155 it is inside another SUBREG and the mode of that
3156 SUBREG and the mode of the inside of TO is
3157 tieable and it is valid if X is a SET that copies
3158 FROM to CC0. */
3159
3160 if (GET_CODE (to) == SUBREG
3161 && ! MODES_TIEABLE_P (GET_MODE (to),
3162 GET_MODE (SUBREG_REG (to)))
3163 && ! (code == SUBREG
3164 && MODES_TIEABLE_P (GET_MODE (x),
3165 GET_MODE (SUBREG_REG (to))))
42301240 3166#ifdef HAVE_cc0
4f4b3679 3167 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
42301240 3168#endif
4f4b3679
RH		 3169 )
3170 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
42301240 3171
4f4b3679
RH		 3172 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3173 n_occurrences++;
3174 }
3175 else
3176 /* If we are in a SET_DEST, suppress most cases unless we
3177 have gone inside a MEM, in which case we want to
3178 simplify the address. We assume here that things that
3179 are actually part of the destination have their inner
3180 parts in the first expression. This is true for SUBREG,
3181 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3182 things aside from REG and MEM that should appear in a
3183 SET_DEST. */
3184 new = subst (XEXP (x, i), from, to,
3185 (((in_dest
3186 && (code == SUBREG || code == STRICT_LOW_PART
3187 || code == ZERO_EXTRACT))
3188 || code == SET)
3189 && i == 0), unique_copy);
3190
3191 /* If we found that we will have to reject this combination,
3192 indicate that by returning the CLOBBER ourselves, rather than
3193 an expression containing it. This will speed things up as
3194 well as prevent accidents where two CLOBBERs are considered
3195 to be equal, thus producing an incorrect simplification. */
3196
3197 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3198 return new;
3199
3200 SUBST (XEXP (x, i), new);
230d793d 3201 }
230d793d
RS		 3202 }
3203 }
3204
8079805d
RK		 3205 /* Try to simplify X. If the simplification changed the code, it is likely
3206 that further simplification will help, so loop, but limit the number
3207 of repetitions that will be performed. */
3208
3209 for (i = 0; i < 4; i++)
3210 {
3211 /* If X is sufficiently simple, don't bother trying to do anything
3212 with it. */
3213 if (code != CONST_INT && code != REG && code != CLOBBER)
3214 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
d0ab8cd3 3215
8079805d
RK		 3216 if (GET_CODE (x) == code)
3217 break;
d0ab8cd3 3218
8079805d 3219 code = GET_CODE (x);
eeb43d32 3220
8079805d
RK		 3221 /* We no longer know the original mode of operand 0 since we
3222 have changed the form of X) */
3223 op0_mode = VOIDmode;
3224 }
eeb43d32 3225
8079805d
RK		 3226 return x;
3227}
3228\f
3229/* Simplify X, a piece of RTL. We just operate on the expression at the
3230 outer level; call `subst' to simplify recursively. Return the new
3231 expression.
3232
3233 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3234 will be the iteration even if an expression with a code different from
3235 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
eeb43d32 3236
8079805d
RK		 3237static rtx
3238simplify_rtx (x, op0_mode, last, in_dest)
3239 rtx x;
3240 enum machine_mode op0_mode;
3241 int last;
3242 int in_dest;
3243{
3244 enum rtx_code code = GET_CODE (x);
3245 enum machine_mode mode = GET_MODE (x);
3246 rtx temp;
3247 int i;
d0ab8cd3 3248
230d793d
RS		 3249 /* If this is a commutative operation, put a constant last and a complex
3250 expression first. We don't need to do this for comparisons here. */
3251 if (GET_RTX_CLASS (code) == 'c'
3252 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3253 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3254 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3255 || (GET_CODE (XEXP (x, 0)) == SUBREG
3256 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3257 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3258 {
3259 temp = XEXP (x, 0);
3260 SUBST (XEXP (x, 0), XEXP (x, 1));
3261 SUBST (XEXP (x, 1), temp);
3262 }
3263
22609cbf
RK		 3264 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3265 sign extension of a PLUS with a constant, reverse the order of the sign
3266 extension and the addition. Note that this not the same as the original
3267 code, but overflow is undefined for signed values. Also note that the
3268 PLUS will have been partially moved "inside" the sign-extension, so that
3269 the first operand of X will really look like:
3270 (ashiftrt (plus (ashift A C4) C5) C4).
3271 We convert this to
3272 (plus (ashiftrt (ashift A C4) C2) C4)
3273 and replace the first operand of X with that expression. Later parts
3274 of this function may simplify the expression further.
3275
3276 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3277 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3278 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3279
3280 We do this to simplify address expressions. */
3281
3282 if ((code == PLUS || code == MINUS || code == MULT)
3283 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3284 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3285 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3286 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3287 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3288 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3289 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3290 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3291 XEXP (XEXP (XEXP (x, 0), 0), 1),
3292 XEXP (XEXP (x, 0), 1))) != 0)
3293 {
3294 rtx new
3295 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3296 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3297 INTVAL (XEXP (XEXP (x, 0), 1)));
3298
3299 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3300 INTVAL (XEXP (XEXP (x, 0), 1)));
3301
3302 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3303 }
3304
d0ab8cd3
RK		 3305 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3306 applying it to the arms of the IF_THEN_ELSE. This often simplifies
abe6e52f
RK		 3307 things. Check for cases where both arms are testing the same
3308 condition.
3309
3310 Don't do anything if all operands are very simple. */
3311
3312 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3313 || GET_RTX_CLASS (code) == '<')
3314 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3315 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3316 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3317 == 'o')))
3318 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3319 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3320 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3321 == 'o')))))
3322 || (GET_RTX_CLASS (code) == '1'
3323 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3324 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3325 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3326 == 'o'))))))
d0ab8cd3 3327 {
abe6e52f
RK		 3328 rtx cond, true, false;
3329
3330 cond = if_then_else_cond (x, &true, &false);
0802d516
RK		 3331 if (cond != 0
3332 /* If everything is a comparison, what we have is highly unlikely
3333 to be simpler, so don't use it. */
3334 && ! (GET_RTX_CLASS (code) == '<'
3335 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3336 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
abe6e52f
RK		 3337 {
3338 rtx cop1 = const0_rtx;
3339 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3340
15448afc
RK		 3341 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3342 return x;
3343
9210df58
RK		 3344 /* Simplify the alternative arms; this may collapse the true and
3345 false arms to store-flag values. */
3346 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3347 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3348
3349 /* Restarting if we generate a store-flag expression will cause
3350 us to loop. Just drop through in this case. */
3351
abe6e52f
RK		 3352 /* If the result values are STORE_FLAG_VALUE and zero, we can
3353 just make the comparison operation. */
3354 if (true == const_true_rtx && false == const0_rtx)
3355 x = gen_binary (cond_code, mode, cond, cop1);
3356 else if (true == const0_rtx && false == const_true_rtx)
3357 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3358
3359 /* Likewise, we can make the negate of a comparison operation
3360 if the result values are - STORE_FLAG_VALUE and zero. */
3361 else if (GET_CODE (true) == CONST_INT
3362 && INTVAL (true) == - STORE_FLAG_VALUE
3363 && false == const0_rtx)
0c1c8ea6 3364 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3365 gen_binary (cond_code, mode, cond, cop1));
3366 else if (GET_CODE (false) == CONST_INT
3367 && INTVAL (false) == - STORE_FLAG_VALUE
3368 && true == const0_rtx)
0c1c8ea6 3369 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3370 gen_binary (reverse_condition (cond_code),
3371 mode, cond, cop1));
3372 else
38a448ca
RH		 3373 return gen_rtx_IF_THEN_ELSE (mode,
3374 gen_binary (cond_code, VOIDmode,
3375 cond, cop1),
3376 true, false);
5109d49f 3377
9210df58
RK		 3378 code = GET_CODE (x);
3379 op0_mode = VOIDmode;
abe6e52f 3380 }
d0ab8cd3
RK		 3381 }
3382
230d793d
RS		 3383 /* Try to fold this expression in case we have constants that weren't
3384 present before. */
3385 temp = 0;
3386 switch (GET_RTX_CLASS (code))
3387 {
3388 case '1':
3389 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3390 break;
3391 case '<':
3392 temp = simplify_relational_operation (code, op0_mode,
3393 XEXP (x, 0), XEXP (x, 1));
77fa0940
RK		 3394#ifdef FLOAT_STORE_FLAG_VALUE
3395 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3396 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3397 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3398#endif
230d793d
RS		 3399 break;
3400 case 'c':
3401 case '2':
3402 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3403 break;
3404 case 'b':
3405 case '3':
3406 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3407 XEXP (x, 1), XEXP (x, 2));
3408 break;
3409 }
3410
3411 if (temp)
d0ab8cd3 3412 x = temp, code = GET_CODE (temp);
230d793d 3413
230d793d 3414 /* First see if we can apply the inverse distributive law. */
224eeff2
RK		 3415 if (code == PLUS || code == MINUS
3416 || code == AND || code == IOR || code == XOR)
230d793d
RS		 3417 {
3418 x = apply_distributive_law (x);
3419 code = GET_CODE (x);
3420 }
3421
3422 /* If CODE is an associative operation not otherwise handled, see if we
3423 can associate some operands. This can win if they are constants or
3424 if they are logically related (i.e. (a & b) & a. */
3425 if ((code == PLUS || code == MINUS
3426 || code == MULT || code == AND || code == IOR || code == XOR
3427 || code == DIV || code == UDIV
3428 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3ad2180a 3429 && INTEGRAL_MODE_P (mode))
230d793d
RS		 3430 {
3431 if (GET_CODE (XEXP (x, 0)) == code)
3432 {
3433 rtx other = XEXP (XEXP (x, 0), 0);
3434 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3435 rtx inner_op1 = XEXP (x, 1);
3436 rtx inner;
3437
3438 /* Make sure we pass the constant operand if any as the second
3439 one if this is a commutative operation. */
3440 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3441 {
3442 rtx tem = inner_op0;
3443 inner_op0 = inner_op1;
3444 inner_op1 = tem;
3445 }
3446 inner = simplify_binary_operation (code == MINUS ? PLUS
3447 : code == DIV ? MULT
3448 : code == UDIV ? MULT
3449 : code,
3450 mode, inner_op0, inner_op1);
3451
3452 /* For commutative operations, try the other pair if that one
3453 didn't simplify. */
3454 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3455 {
3456 other = XEXP (XEXP (x, 0), 1);
3457 inner = simplify_binary_operation (code, mode,
3458 XEXP (XEXP (x, 0), 0),
3459 XEXP (x, 1));
3460 }
3461
3462 if (inner)
8079805d 3463 return gen_binary (code, mode, other, inner);
230d793d
RS		 3464 }
3465 }
3466
3467 /* A little bit of algebraic simplification here. */
3468 switch (code)
3469 {
3470 case MEM:
3471 /* Ensure that our address has any ASHIFTs converted to MULT in case
3472 address-recognizing predicates are called later. */
3473 temp = make_compound_operation (XEXP (x, 0), MEM);
3474 SUBST (XEXP (x, 0), temp);
3475 break;
3476
3477 case SUBREG:
3478 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3479 is paradoxical. If we can't do that safely, then it becomes
3480 something nonsensical so that this combination won't take place. */
3481
3482 if (GET_CODE (SUBREG_REG (x)) == MEM
3483 && (GET_MODE_SIZE (mode)
3484 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3485 {
3486 rtx inner = SUBREG_REG (x);
3487 int endian_offset = 0;
3488 /* Don't change the mode of the MEM
3489 if that would change the meaning of the address. */
3490 if (MEM_VOLATILE_P (SUBREG_REG (x))
3491 || mode_dependent_address_p (XEXP (inner, 0)))
38a448ca 3492 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d 3493
f76b9db2
ILT		 3494 if (BYTES_BIG_ENDIAN)
3495 {
3496 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3497 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3498 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3499 endian_offset -= (UNITS_PER_WORD
3500 - GET_MODE_SIZE (GET_MODE (inner)));
3501 }
230d793d
RS		 3502 /* Note if the plus_constant doesn't make a valid address
3503 then this combination won't be accepted. */
38a448ca
RH		 3504 x = gen_rtx_MEM (mode,
3505 plus_constant (XEXP (inner, 0),
3506 (SUBREG_WORD (x) * UNITS_PER_WORD
3507 + endian_offset)));
230d793d 3508 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
c6df88cb 3509 MEM_COPY_ATTRIBUTES (x, inner);
230d793d
RS		 3510 return x;
3511 }
3512
3513 /* If we are in a SET_DEST, these other cases can't apply. */
3514 if (in_dest)
3515 return x;
3516
3517 /* Changing mode twice with SUBREG => just change it once,
3518 or not at all if changing back to starting mode. */
3519 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3520 {
3521 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3522 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3523 return SUBREG_REG (SUBREG_REG (x));
3524
3525 SUBST_INT (SUBREG_WORD (x),
3526 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3527 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3528 }
3529
3530 /* SUBREG of a hard register => just change the register number
3531 and/or mode. If the hard register is not valid in that mode,
26ecfc76
RK		 3532 suppress this combination. If the hard register is the stack,
3533 frame, or argument pointer, leave this as a SUBREG. */
230d793d
RS		 3534
3535 if (GET_CODE (SUBREG_REG (x)) == REG
26ecfc76
RK		 3536 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3537 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
6d7096b0
DE		 3538#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3539 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3540#endif
26ecfc76
RK		 3541#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3542 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3543#endif
3544 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
230d793d
RS		 3545 {
3546 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3547 mode))
38a448ca
RH		 3548 return gen_rtx_REG (mode,
3549 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
230d793d 3550 else
38a448ca 3551 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d
RS		 3552 }
3553
3554 /* For a constant, try to pick up the part we want. Handle a full
a4bde0b1
RK		 3555 word and low-order part. Only do this if we are narrowing
3556 the constant; if it is being widened, we have no idea what
3557 the extra bits will have been set to. */
230d793d
RS		 3558
3559 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3560 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3c99d5ff 3561 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
230d793d
RS		 3562 && GET_MODE_CLASS (mode) == MODE_INT)
3563 {
3564 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
5f4f0e22 3565 0, op0_mode);
230d793d
RS		 3566 if (temp)
3567 return temp;
3568 }
3569
19808e22
RS		 3570 /* If we want a subreg of a constant, at offset 0,
3571 take the low bits. On a little-endian machine, that's
3572 always valid. On a big-endian machine, it's valid
3c99d5ff 3573 only if the constant's mode fits in one word. Note that we
61b1bece 3574 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3c99d5ff
RK		 3575 if (CONSTANT_P (SUBREG_REG (x))
3576 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3577 || ! WORDS_BIG_ENDIAN)
3578 ? SUBREG_WORD (x) == 0
3579 : (SUBREG_WORD (x)
3580 == ((GET_MODE_SIZE (op0_mode)
3581 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3582 / UNITS_PER_WORD)))
f82da7d2 3583 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
f76b9db2
ILT		 3584 && (! WORDS_BIG_ENDIAN
3585 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
230d793d
RS		 3586 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3587
b65c1b5b
RK		 3588 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3589 since we are saying that the high bits don't matter. */
3590 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3591 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3592 return SUBREG_REG (x);
3593
87e3e0c1
RK		 3594 /* Note that we cannot do any narrowing for non-constants since
3595 we might have been counting on using the fact that some bits were
3596 zero. We now do this in the SET. */
3597
230d793d
RS		 3598 break;
3599
3600 case NOT:
3601 /* (not (plus X -1)) can become (neg X). */
3602 if (GET_CODE (XEXP (x, 0)) == PLUS
3603 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
8079805d 3604 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3605
3606 /* Similarly, (not (neg X)) is (plus X -1). */
3607 if (GET_CODE (XEXP (x, 0)) == NEG)
8079805d
RK		 3608 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3609 constm1_rtx);
230d793d 3610
d0ab8cd3
RK		 3611 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3612 if (GET_CODE (XEXP (x, 0)) == XOR
3613 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3614 && (temp = simplify_unary_operation (NOT, mode,
3615 XEXP (XEXP (x, 0), 1),
3616 mode)) != 0)
787745f5 3617 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
d0ab8cd3 3618
230d793d
RS		 3619 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3620 other than 1, but that is not valid. We could do a similar
3621 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3622 but this doesn't seem common enough to bother with. */
3623 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3624 && XEXP (XEXP (x, 0), 0) == const1_rtx)
38a448ca
RH		 3625 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3626 XEXP (XEXP (x, 0), 1));
230d793d
RS		 3627
3628 if (GET_CODE (XEXP (x, 0)) == SUBREG
3629 && subreg_lowpart_p (XEXP (x, 0))
3630 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3631 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3633 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3634 {
3635 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3636
38a448ca
RH		 3637 x = gen_rtx_ROTATE (inner_mode,
3638 gen_unary (NOT, inner_mode, inner_mode,
3639 const1_rtx),
3640 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
8079805d 3641 return gen_lowpart_for_combine (mode, x);
230d793d
RS		 3642 }
3643
0802d516
RK		 3644 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3645 reversing the comparison code if valid. */
3646 if (STORE_FLAG_VALUE == -1
3647 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
230d793d
RS		 3648 && reversible_comparison_p (XEXP (x, 0)))
3649 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3650 mode, XEXP (XEXP (x, 0), 0),
3651 XEXP (XEXP (x, 0), 1));
500c518b
RK		 3652
3653 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
0802d516
RK		 3654 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3655 perform the above simplification. */
500c518b 3656
0802d516
RK		 3657 if (STORE_FLAG_VALUE == -1
3658 && XEXP (x, 1) == const1_rtx
500c518b
RK		 3659 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3660 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3661 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3662 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
230d793d
RS		 3663
3664 /* Apply De Morgan's laws to reduce number of patterns for machines
3665 with negating logical insns (and-not, nand, etc.). If result has
3666 only one NOT, put it first, since that is how the patterns are
3667 coded. */
3668
3669 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3670 {
3671 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3672
3673 if (GET_CODE (in1) == NOT)
3674 in1 = XEXP (in1, 0);
3675 else
3676 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3677
3678 if (GET_CODE (in2) == NOT)
3679 in2 = XEXP (in2, 0);
3680 else if (GET_CODE (in2) == CONST_INT
5f4f0e22
CH		 3681 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3682 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
230d793d
RS		 3683 else
3684 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3685
3686 if (GET_CODE (in2) == NOT)
3687 {
3688 rtx tem = in2;
3689 in2 = in1; in1 = tem;
3690 }
3691
8079805d
RK		 3692 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3693 mode, in1, in2);
230d793d
RS		 3694 }
3695 break;
3696
3697 case NEG:
3698 /* (neg (plus X 1)) can become (not X). */
3699 if (GET_CODE (XEXP (x, 0)) == PLUS
3700 && XEXP (XEXP (x, 0), 1) == const1_rtx)
8079805d 3701 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3702
3703 /* Similarly, (neg (not X)) is (plus X 1). */
3704 if (GET_CODE (XEXP (x, 0)) == NOT)
8079805d 3705 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
230d793d 3706
230d793d
RS		 3707 /* (neg (minus X Y)) can become (minus Y X). */
3708 if (GET_CODE (XEXP (x, 0)) == MINUS
3ad2180a 3709 && (! FLOAT_MODE_P (mode)
0f41302f 3710 /* x-y != -(y-x) with IEEE floating point. */
7e2a0d8e
RK		 3711 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3712 || flag_fast_math))
8079805d
RK		 3713 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3714 XEXP (XEXP (x, 0), 0));
230d793d 3715
0f41302f 3716 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
d0ab8cd3 3717 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
951553af 3718 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
8079805d 3719 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
d0ab8cd3 3720
230d793d
RS		 3721 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3722 if we can then eliminate the NEG (e.g.,
3723 if the operand is a constant). */
3724
3725 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3726 {
3727 temp = simplify_unary_operation (NEG, mode,
3728 XEXP (XEXP (x, 0), 0), mode);
3729 if (temp)
3730 {
3731 SUBST (XEXP (XEXP (x, 0), 0), temp);
3732 return XEXP (x, 0);
3733 }
3734 }
3735
3736 temp = expand_compound_operation (XEXP (x, 0));
3737
3738 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3739 replaced by (lshiftrt X C). This will convert
3740 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3741
3742 if (GET_CODE (temp) == ASHIFTRT
3743 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3744 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
8079805d
RK		 3745 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3746 INTVAL (XEXP (temp, 1)));
230d793d 3747
951553af 3748 /* If X has only a single bit that might be nonzero, say, bit I, convert
230d793d
RS		 3749 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3750 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3751 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3752 or a SUBREG of one since we'd be making the expression more
3753 complex if it was just a register. */
3754
3755 if (GET_CODE (temp) != REG
3756 && ! (GET_CODE (temp) == SUBREG
3757 && GET_CODE (SUBREG_REG (temp)) == REG)
951553af 3758 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
230d793d
RS		 3759 {
3760 rtx temp1 = simplify_shift_const
5f4f0e22
CH		 3761 (NULL_RTX, ASHIFTRT, mode,
3762 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
230d793d
RS		 3763 GET_MODE_BITSIZE (mode) - 1 - i),
3764 GET_MODE_BITSIZE (mode) - 1 - i);
3765
3766 /* If all we did was surround TEMP with the two shifts, we
3767 haven't improved anything, so don't use it. Otherwise,
3768 we are better off with TEMP1. */
3769 if (GET_CODE (temp1) != ASHIFTRT
3770 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3771 || XEXP (XEXP (temp1, 0), 0) != temp)
8079805d 3772 return temp1;
230d793d
RS		 3773 }
3774 break;
3775
2ca9ae17 3776 case TRUNCATE:
e30fb98f
JL		 3777 /* We can't handle truncation to a partial integer mode here
3778 because we don't know the real bitsize of the partial
3779 integer mode. */
3780 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3781 break;
3782
80608e27
JL		 3783 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3784 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3785 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
2ca9ae17
JW		 3786 SUBST (XEXP (x, 0),
3787 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3788 GET_MODE_MASK (mode), NULL_RTX, 0));
0f13a422
ILT		 3789
3790 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3791 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3792 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3793 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3794 return XEXP (XEXP (x, 0), 0);
3795
3796 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3797 (OP:SI foo:SI) if OP is NEG or ABS. */
3798 if ((GET_CODE (XEXP (x, 0)) == ABS
3799 || GET_CODE (XEXP (x, 0)) == NEG)
3800 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3801 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3802 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3803 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3804 XEXP (XEXP (XEXP (x, 0), 0), 0));
3805
3806 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3807 (truncate:SI x). */
3808 if (GET_CODE (XEXP (x, 0)) == SUBREG
3809 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3810 && subreg_lowpart_p (XEXP (x, 0)))
3811 return SUBREG_REG (XEXP (x, 0));
3812
3813 /* If we know that the value is already truncated, we can
6a992214
JL		 3814 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3815 nonzero for the corresponding modes. */
3816 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3817 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3818 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3819 >= GET_MODE_BITSIZE (mode) + 1)
0f13a422
ILT		 3820 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3821
3822 /* A truncate of a comparison can be replaced with a subreg if
3823 STORE_FLAG_VALUE permits. This is like the previous test,
3824 but it works even if the comparison is done in a mode larger
3825 than HOST_BITS_PER_WIDE_INT. */
3826 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3827 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3828 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3829 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3830
3831 /* Similarly, a truncate of a register whose value is a
3832 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3833 permits. */
3834 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3835 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3836 && (temp = get_last_value (XEXP (x, 0)))
3837 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3838 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3839
2ca9ae17
JW		 3840 break;
3841
230d793d
RS		 3842 case FLOAT_TRUNCATE:
3843 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3844 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3845 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3846 return XEXP (XEXP (x, 0), 0);
4635f748
RK		 3847
3848 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3849 (OP:SF foo:SF) if OP is NEG or ABS. */
3850 if ((GET_CODE (XEXP (x, 0)) == ABS
3851 || GET_CODE (XEXP (x, 0)) == NEG)
3852 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3853 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
0c1c8ea6
RK		 3854 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3855 XEXP (XEXP (XEXP (x, 0), 0), 0));
1d12df72
RK		 3856
3857 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3858 is (float_truncate:SF x). */
3859 if (GET_CODE (XEXP (x, 0)) == SUBREG
3860 && subreg_lowpart_p (XEXP (x, 0))
3861 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3862 return SUBREG_REG (XEXP (x, 0));
230d793d
RS		 3863 break;
3864
3865#ifdef HAVE_cc0
3866 case COMPARE:
3867 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3868 using cc0, in which case we want to leave it as a COMPARE
3869 so we can distinguish it from a register-register-copy. */
3870 if (XEXP (x, 1) == const0_rtx)
3871 return XEXP (x, 0);
3872
3873 /* In IEEE floating point, x-0 is not the same as x. */
3874 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e
RK		 3875 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3876 || flag_fast_math)
230d793d
RS		 3877 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3878 return XEXP (x, 0);
3879 break;
3880#endif
3881
3882 case CONST:
3883 /* (const (const X)) can become (const X). Do it this way rather than
3884 returning the inner CONST since CONST can be shared with a
3885 REG_EQUAL note. */
3886 if (GET_CODE (XEXP (x, 0)) == CONST)
3887 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3888 break;
3889
3890#ifdef HAVE_lo_sum
3891 case LO_SUM:
3892 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3893 can add in an offset. find_split_point will split this address up
3894 again if it doesn't match. */
3895 if (GET_CODE (XEXP (x, 0)) == HIGH
3896 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3897 return XEXP (x, 1);
3898 break;
3899#endif
3900
3901 case PLUS:
3902 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3903 outermost. That's because that's the way indexed addresses are
3904 supposed to appear. This code used to check many more cases, but
3905 they are now checked elsewhere. */
3906 if (GET_CODE (XEXP (x, 0)) == PLUS
3907 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3908 return gen_binary (PLUS, mode,
3909 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3910 XEXP (x, 1)),
3911 XEXP (XEXP (x, 0), 1));
3912
3913 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3914 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3915 bit-field and can be replaced by either a sign_extend or a
e6380233
JL		 3916 sign_extract. The `and' may be a zero_extend and the two
3917 <c>, -<c> constants may be reversed. */
230d793d
RS		 3918 if (GET_CODE (XEXP (x, 0)) == XOR
3919 && GET_CODE (XEXP (x, 1)) == CONST_INT
3920 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3921 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
e6380233
JL		 3922 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3923 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5f4f0e22 3924 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 3925 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3926 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3927 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5f4f0e22 3928 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
230d793d
RS		 3929 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3930 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3931 == i + 1))))
8079805d
RK		 3932 return simplify_shift_const
3933 (NULL_RTX, ASHIFTRT, mode,
3934 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3935 XEXP (XEXP (XEXP (x, 0), 0), 0),
3936 GET_MODE_BITSIZE (mode) - (i + 1)),
3937 GET_MODE_BITSIZE (mode) - (i + 1));
230d793d 3938
bc0776c6
RK		 3939 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3940 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3941 is 1. This produces better code than the alternative immediately
3942 below. */
3943 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3944 && reversible_comparison_p (XEXP (x, 0))
3945 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3946 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
8079805d 3947 return
0c1c8ea6 3948 gen_unary (NEG, mode, mode,
8079805d
RK		 3949 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3950 mode, XEXP (XEXP (x, 0), 0),
3951 XEXP (XEXP (x, 0), 1)));
bc0776c6
RK		 3952
3953 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
230d793d
RS		 3954 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3955 the bitsize of the mode - 1. This allows simplification of
3956 "a = (b & 8) == 0;" */
3957 if (XEXP (x, 1) == constm1_rtx
3958 && GET_CODE (XEXP (x, 0)) != REG
3959 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3960 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
951553af 3961 && nonzero_bits (XEXP (x, 0), mode) == 1)
8079805d
RK		 3962 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3963 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3964 gen_rtx_combine (XOR, mode,
3965 XEXP (x, 0), const1_rtx),
3966 GET_MODE_BITSIZE (mode) - 1),
3967 GET_MODE_BITSIZE (mode) - 1);
02f4ada4
RK		 3968
3969 /* If we are adding two things that have no bits in common, convert
3970 the addition into an IOR. This will often be further simplified,
3971 for example in cases like ((a & 1) + (a & 2)), which can
3972 become a & 3. */
3973
ac49a949 3974 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
951553af
RK		 3975 && (nonzero_bits (XEXP (x, 0), mode)
3976 & nonzero_bits (XEXP (x, 1), mode)) == 0)
8079805d 3977 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
230d793d
RS		 3978 break;
3979
3980 case MINUS:
0802d516
RK		 3981 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3982 by reversing the comparison code if valid. */
3983 if (STORE_FLAG_VALUE == 1
3984 && XEXP (x, 0) == const1_rtx
5109d49f
RK		 3985 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3986 && reversible_comparison_p (XEXP (x, 1)))
3987 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3988 mode, XEXP (XEXP (x, 1), 0),
3989 XEXP (XEXP (x, 1), 1));
5109d49f 3990
230d793d
RS		 3991 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3992 (and <foo> (const_int pow2-1)) */
3993 if (GET_CODE (XEXP (x, 1)) == AND
3994 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3995 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3996 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8079805d
RK		 3997 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3998 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
7bef8680
RK		 3999
4000 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4001 integers. */
4002 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
8079805d
RK		 4003 return gen_binary (MINUS, mode,
4004 gen_binary (MINUS, mode, XEXP (x, 0),
4005 XEXP (XEXP (x, 1), 0)),
4006 XEXP (XEXP (x, 1), 1));
230d793d
RS		 4007 break;
4008
4009 case MULT:
4010 /* If we have (mult (plus A B) C), apply the distributive law and then
4011 the inverse distributive law to see if things simplify. This
4012 occurs mostly in addresses, often when unrolling loops. */
4013
4014 if (GET_CODE (XEXP (x, 0)) == PLUS)
4015 {
4016 x = apply_distributive_law
4017 (gen_binary (PLUS, mode,
4018 gen_binary (MULT, mode,
4019 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4020 gen_binary (MULT, mode,
4021 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4022
4023 if (GET_CODE (x) != MULT)
8079805d 4024 return x;
230d793d 4025 }
230d793d
RS		 4026 break;
4027
4028 case UDIV:
4029 /* If this is a divide by a power of two, treat it as a shift if
4030 its first operand is a shift. */
4031 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4032 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4033 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4034 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4035 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4036 || GET_CODE (XEXP (x, 0)) == ROTATE
4037 || GET_CODE (XEXP (x, 0)) == ROTATERT))
8079805d 4038 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
230d793d
RS		 4039 break;
4040
4041 case EQ: case NE:
4042 case GT: case GTU: case GE: case GEU:
4043 case LT: case LTU: case LE: case LEU:
4044 /* If the first operand is a condition code, we can't do anything
4045 with it. */
4046 if (GET_CODE (XEXP (x, 0)) == COMPARE
4047 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4048#ifdef HAVE_cc0
4049 && XEXP (x, 0) != cc0_rtx
4050#endif
4051 ))
4052 {
4053 rtx op0 = XEXP (x, 0);
4054 rtx op1 = XEXP (x, 1);
4055 enum rtx_code new_code;
4056
4057 if (GET_CODE (op0) == COMPARE)
4058 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4059
4060 /* Simplify our comparison, if possible. */
4061 new_code = simplify_comparison (code, &op0, &op1);
4062
230d793d 4063 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
951553af 4064 if only the low-order bit is possibly nonzero in X (such as when
5109d49f
RK		 4065 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4066 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4067 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4068 (plus X 1).
4069
4070 Remove any ZERO_EXTRACT we made when thinking this was a
4071 comparison. It may now be simpler to use, e.g., an AND. If a
4072 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4073 the call to make_compound_operation in the SET case. */
4074
0802d516
RK		 4075 if (STORE_FLAG_VALUE == 1
4076 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4077 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4078 return gen_lowpart_for_combine (mode,
4079 expand_compound_operation (op0));
5109d49f 4080
0802d516
RK		 4081 else if (STORE_FLAG_VALUE == 1
4082 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4083 && op1 == const0_rtx
4084 && (num_sign_bit_copies (op0, mode)
4085 == GET_MODE_BITSIZE (mode)))
4086 {
4087 op0 = expand_compound_operation (op0);
0c1c8ea6 4088 return gen_unary (NEG, mode, mode,
8079805d 4089 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4090 }
4091
0802d516
RK		 4092 else if (STORE_FLAG_VALUE == 1
4093 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4094 && op1 == const0_rtx
5109d49f 4095 && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4096 {
4097 op0 = expand_compound_operation (op0);
8079805d
RK		 4098 return gen_binary (XOR, mode,
4099 gen_lowpart_for_combine (mode, op0),
4100 const1_rtx);
5109d49f 4101 }
818b11b9 4102
0802d516
RK		 4103 else if (STORE_FLAG_VALUE == 1
4104 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4105 && op1 == const0_rtx
4106 && (num_sign_bit_copies (op0, mode)
4107 == GET_MODE_BITSIZE (mode)))
4108 {
4109 op0 = expand_compound_operation (op0);
8079805d 4110 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
818b11b9 4111 }
230d793d 4112
5109d49f
RK		 4113 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4114 those above. */
0802d516
RK		 4115 if (STORE_FLAG_VALUE == -1
4116 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4117 && op1 == const0_rtx
5109d49f
RK		 4118 && (num_sign_bit_copies (op0, mode)
4119 == GET_MODE_BITSIZE (mode)))
4120 return gen_lowpart_for_combine (mode,
4121 expand_compound_operation (op0));
4122
0802d516
RK		 4123 else if (STORE_FLAG_VALUE == -1
4124 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4125 && op1 == const0_rtx
4126 && nonzero_bits (op0, mode) == 1)
4127 {
4128 op0 = expand_compound_operation (op0);
0c1c8ea6 4129 return gen_unary (NEG, mode, mode,
8079805d 4130 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4131 }
4132
0802d516
RK		 4133 else if (STORE_FLAG_VALUE == -1
4134 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4135 && op1 == const0_rtx
4136 && (num_sign_bit_copies (op0, mode)
4137 == GET_MODE_BITSIZE (mode)))
230d793d 4138 {
818b11b9 4139 op0 = expand_compound_operation (op0);
0c1c8ea6 4140 return gen_unary (NOT, mode, mode,
8079805d 4141 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4142 }
4143
4144 /* If X is 0/1, (eq X 0) is X-1. */
0802d516
RK		 4145 else if (STORE_FLAG_VALUE == -1
4146 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4147 && op1 == const0_rtx
4148 && nonzero_bits (op0, mode) == 1)
4149 {
4150 op0 = expand_compound_operation (op0);
8079805d 4151 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
230d793d 4152 }
230d793d
RS		 4153
4154 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
951553af
RK		 4155 one bit that might be nonzero, we can convert (ne x 0) to
4156 (ashift x c) where C puts the bit in the sign bit. Remove any
4157 AND with STORE_FLAG_VALUE when we are done, since we are only
4158 going to test the sign bit. */
3f508eca 4159 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5f4f0e22 4160 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 4161 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 4162 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
230d793d
RS		 4163 && op1 == const0_rtx
4164 && mode == GET_MODE (op0)
5109d49f 4165 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
230d793d 4166 {
818b11b9
RK		 4167 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4168 expand_compound_operation (op0),
230d793d
RS		 4169 GET_MODE_BITSIZE (mode) - 1 - i);
4170 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4171 return XEXP (x, 0);
4172 else
4173 return x;
4174 }
4175
4176 /* If the code changed, return a whole new comparison. */
4177 if (new_code != code)
4178 return gen_rtx_combine (new_code, mode, op0, op1);
4179
4180 /* Otherwise, keep this operation, but maybe change its operands.
4181 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4182 SUBST (XEXP (x, 0), op0);
4183 SUBST (XEXP (x, 1), op1);
4184 }
4185 break;
4186
4187 case IF_THEN_ELSE:
8079805d 4188 return simplify_if_then_else (x);
9210df58 4189
8079805d
RK		 4190 case ZERO_EXTRACT:
4191 case SIGN_EXTRACT:
4192 case ZERO_EXTEND:
4193 case SIGN_EXTEND:
0f41302f 4194 /* If we are processing SET_DEST, we are done. */
8079805d
RK		 4195 if (in_dest)
4196 return x;
d0ab8cd3 4197
8079805d 4198 return expand_compound_operation (x);
d0ab8cd3 4199
8079805d
RK		 4200 case SET:
4201 return simplify_set (x);
1a26b032 4202
8079805d
RK		 4203 case AND:
4204 case IOR:
4205 case XOR:
4206 return simplify_logical (x, last);
d0ab8cd3 4207
b472527b 4208 case ABS:
8079805d
RK		 4209 /* (abs (neg <foo>)) -> (abs <foo>) */
4210 if (GET_CODE (XEXP (x, 0)) == NEG)
4211 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
1a26b032 4212
b472527b
JL		 4213 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4214 do nothing. */
4215 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4216 break;
f40421ce 4217
8079805d
RK		 4218 /* If operand is something known to be positive, ignore the ABS. */
4219 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4220 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4221 <= HOST_BITS_PER_WIDE_INT)
4222 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4223 & ((HOST_WIDE_INT) 1
4224 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4225 == 0)))
4226 return XEXP (x, 0);
1a26b032 4227
1a26b032 4228
8079805d
RK		 4229 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4230 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4231 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
1a26b032 4232
8079805d 4233 break;
1a26b032 4234
8079805d
RK		 4235 case FFS:
4236 /* (ffs (*_extend <X>)) = (ffs <X>) */
4237 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4238 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4239 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4240 break;
1a26b032 4241
8079805d
RK		 4242 case FLOAT:
4243 /* (float (sign_extend <X>)) = (float <X>). */
4244 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4245 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4246 break;
1a26b032 4247
8079805d
RK		 4248 case ASHIFT:
4249 case LSHIFTRT:
4250 case ASHIFTRT:
4251 case ROTATE:
4252 case ROTATERT:
4253 /* If this is a shift by a constant amount, simplify it. */
4254 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4255 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4256 INTVAL (XEXP (x, 1)));
4257
4258#ifdef SHIFT_COUNT_TRUNCATED
4259 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4260 SUBST (XEXP (x, 1),
4261 force_to_mode (XEXP (x, 1), GET_MODE (x),
4262 ((HOST_WIDE_INT) 1
4263 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4264 - 1,
4265 NULL_RTX, 0));
4266#endif
4267
4268 break;
e9a25f70
JL		 4269
4270 default:
4271 break;
8079805d
RK		 4272 }
4273
4274 return x;
4275}
4276\f
4277/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5109d49f 4278
8079805d
RK		 4279static rtx
4280simplify_if_then_else (x)
4281 rtx x;
4282{
4283 enum machine_mode mode = GET_MODE (x);
4284 rtx cond = XEXP (x, 0);
4285 rtx true = XEXP (x, 1);
4286 rtx false = XEXP (x, 2);
4287 enum rtx_code true_code = GET_CODE (cond);
4288 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4289 rtx temp;
4290 int i;
4291
0f41302f 4292 /* Simplify storing of the truth value. */
8079805d
RK		 4293 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4294 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4295
0f41302f 4296 /* Also when the truth value has to be reversed. */
8079805d
RK		 4297 if (comparison_p && reversible_comparison_p (cond)
4298 && true == const0_rtx && false == const_true_rtx)
4299 return gen_binary (reverse_condition (true_code),
4300 mode, XEXP (cond, 0), XEXP (cond, 1));
4301
4302 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4303 in it is being compared against certain values. Get the true and false
4304 comparisons and see if that says anything about the value of each arm. */
4305
4306 if (comparison_p && reversible_comparison_p (cond)
4307 && GET_CODE (XEXP (cond, 0)) == REG)
4308 {
4309 HOST_WIDE_INT nzb;
4310 rtx from = XEXP (cond, 0);
4311 enum rtx_code false_code = reverse_condition (true_code);
4312 rtx true_val = XEXP (cond, 1);
4313 rtx false_val = true_val;
4314 int swapped = 0;
9210df58 4315
8079805d 4316 /* If FALSE_CODE is EQ, swap the codes and arms. */
5109d49f 4317
8079805d 4318 if (false_code == EQ)
1a26b032 4319 {
8079805d
RK		 4320 swapped = 1, true_code = EQ, false_code = NE;
4321 temp = true, true = false, false = temp;
4322 }
5109d49f 4323
8079805d
RK		 4324 /* If we are comparing against zero and the expression being tested has
4325 only a single bit that might be nonzero, that is its value when it is
4326 not equal to zero. Similarly if it is known to be -1 or 0. */
4327
4328 if (true_code == EQ && true_val == const0_rtx
4329 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4330 false_code = EQ, false_val = GEN_INT (nzb);
4331 else if (true_code == EQ && true_val == const0_rtx
4332 && (num_sign_bit_copies (from, GET_MODE (from))
4333 == GET_MODE_BITSIZE (GET_MODE (from))))
4334 false_code = EQ, false_val = constm1_rtx;
4335
4336 /* Now simplify an arm if we know the value of the register in the
4337 branch and it is used in the arm. Be careful due to the potential
4338 of locally-shared RTL. */
4339
4340 if (reg_mentioned_p (from, true))
4341 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4342 pc_rtx, pc_rtx, 0, 0);
4343 if (reg_mentioned_p (from, false))
4344 false = subst (known_cond (copy_rtx (false), false_code,
4345 from, false_val),
4346 pc_rtx, pc_rtx, 0, 0);
4347
4348 SUBST (XEXP (x, 1), swapped ? false : true);
4349 SUBST (XEXP (x, 2), swapped ? true : false);
4350
4351 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4352 }
5109d49f 4353
8079805d
RK		 4354 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4355 reversed, do so to avoid needing two sets of patterns for
4356 subtract-and-branch insns. Similarly if we have a constant in the true
4357 arm, the false arm is the same as the first operand of the comparison, or
4358 the false arm is more complicated than the true arm. */
4359
4360 if (comparison_p && reversible_comparison_p (cond)
4361 && (true == pc_rtx
4362 || (CONSTANT_P (true)
4363 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4364 || true == const0_rtx
4365 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4366 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4367 || (GET_CODE (true) == SUBREG
4368 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4369 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4370 || reg_mentioned_p (true, false)
4371 || rtx_equal_p (false, XEXP (cond, 0))))
4372 {
4373 true_code = reverse_condition (true_code);
4374 SUBST (XEXP (x, 0),
4375 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4376 XEXP (cond, 1)));
5109d49f 4377
8079805d
RK		 4378 SUBST (XEXP (x, 1), false);
4379 SUBST (XEXP (x, 2), true);
1a26b032 4380
8079805d 4381 temp = true, true = false, false = temp, cond = XEXP (x, 0);
bb821298 4382
0f41302f 4383 /* It is possible that the conditional has been simplified out. */
bb821298
RK		 4384 true_code = GET_CODE (cond);
4385 comparison_p = GET_RTX_CLASS (true_code) == '<';
8079805d 4386 }
abe6e52f 4387
8079805d 4388 /* If the two arms are identical, we don't need the comparison. */
1a26b032 4389
8079805d
RK		 4390 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4391 return true;
1a26b032 4392
5be669c7
RK		 4393 /* Convert a == b ? b : a to "a". */
4394 if (true_code == EQ && ! side_effects_p (cond)
4395 && rtx_equal_p (XEXP (cond, 0), false)
4396 && rtx_equal_p (XEXP (cond, 1), true))
4397 return false;
4398 else if (true_code == NE && ! side_effects_p (cond)
4399 && rtx_equal_p (XEXP (cond, 0), true)
4400 && rtx_equal_p (XEXP (cond, 1), false))
4401 return true;
4402
8079805d
RK		 4403 /* Look for cases where we have (abs x) or (neg (abs X)). */
4404
4405 if (GET_MODE_CLASS (mode) == MODE_INT
4406 && GET_CODE (false) == NEG
4407 && rtx_equal_p (true, XEXP (false, 0))
4408 && comparison_p
4409 && rtx_equal_p (true, XEXP (cond, 0))
4410 && ! side_effects_p (true))
4411 switch (true_code)
4412 {
4413 case GT:
4414 case GE:
0c1c8ea6 4415 return gen_unary (ABS, mode, mode, true);
8079805d
RK		 4416 case LT:
4417 case LE:
0c1c8ea6 4418 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
e9a25f70
JL		 4419 default:
4420 break;
8079805d
RK		 4421 }
4422
4423 /* Look for MIN or MAX. */
4424
34c8be72 4425 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
8079805d
RK		 4426 && comparison_p
4427 && rtx_equal_p (XEXP (cond, 0), true)
4428 && rtx_equal_p (XEXP (cond, 1), false)
4429 && ! side_effects_p (cond))
4430 switch (true_code)
4431 {
4432 case GE:
4433 case GT:
4434 return gen_binary (SMAX, mode, true, false);
4435 case LE:
4436 case LT:
4437 return gen_binary (SMIN, mode, true, false);
4438 case GEU:
4439 case GTU:
4440 return gen_binary (UMAX, mode, true, false);
4441 case LEU:
4442 case LTU:
4443 return gen_binary (UMIN, mode, true, false);
e9a25f70
JL		 4444 default:
4445 break;
8079805d
RK		 4446 }
4447
8079805d
RK		 4448 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4449 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4450 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4451 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4452 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
0802d516 4453 neither 1 or -1, but it isn't worth checking for. */
8079805d 4454
0802d516
RK		 4455 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4456 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
8079805d
RK		 4457 {
4458 rtx t = make_compound_operation (true, SET);
4459 rtx f = make_compound_operation (false, SET);
4460 rtx cond_op0 = XEXP (cond, 0);
4461 rtx cond_op1 = XEXP (cond, 1);
6a651371 4462 enum rtx_code op = NIL, extend_op = NIL;
8079805d 4463 enum machine_mode m = mode;
6a651371 4464 rtx z = 0, c1 = NULL_RTX;
8079805d 4465
8079805d
RK		 4466 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4467 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4468 || GET_CODE (t) == ASHIFT
4469 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4470 && rtx_equal_p (XEXP (t, 0), f))
4471 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4472
4473 /* If an identity-zero op is commutative, check whether there
0f41302f 4474 would be a match if we swapped the operands. */
8079805d
RK		 4475 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4476 || GET_CODE (t) == XOR)
4477 && rtx_equal_p (XEXP (t, 1), f))
4478 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4479 else if (GET_CODE (t) == SIGN_EXTEND
4480 && (GET_CODE (XEXP (t, 0)) == PLUS
4481 || GET_CODE (XEXP (t, 0)) == MINUS
4482 || GET_CODE (XEXP (t, 0)) == IOR
4483 || GET_CODE (XEXP (t, 0)) == XOR
4484 || GET_CODE (XEXP (t, 0)) == ASHIFT
4485 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4486 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4487 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4488 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4489 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4490 && (num_sign_bit_copies (f, GET_MODE (f))
4491 > (GET_MODE_BITSIZE (mode)
4492 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4493 {
4494 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4495 extend_op = SIGN_EXTEND;
4496 m = GET_MODE (XEXP (t, 0));
1a26b032 4497 }
8079805d
RK		 4498 else if (GET_CODE (t) == SIGN_EXTEND
4499 && (GET_CODE (XEXP (t, 0)) == PLUS
4500 || GET_CODE (XEXP (t, 0)) == IOR
4501 || GET_CODE (XEXP (t, 0)) == XOR)
4502 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4503 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4504 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4505 && (num_sign_bit_copies (f, GET_MODE (f))
4506 > (GET_MODE_BITSIZE (mode)
4507 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4508 {
4509 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4510 extend_op = SIGN_EXTEND;
4511 m = GET_MODE (XEXP (t, 0));
4512 }
4513 else if (GET_CODE (t) == ZERO_EXTEND
4514 && (GET_CODE (XEXP (t, 0)) == PLUS
4515 || GET_CODE (XEXP (t, 0)) == MINUS
4516 || GET_CODE (XEXP (t, 0)) == IOR
4517 || GET_CODE (XEXP (t, 0)) == XOR
4518 || GET_CODE (XEXP (t, 0)) == ASHIFT
4519 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4520 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4521 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4522 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4523 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4524 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4525 && ((nonzero_bits (f, GET_MODE (f))
4526 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4527 == 0))
4528 {
4529 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4530 extend_op = ZERO_EXTEND;
4531 m = GET_MODE (XEXP (t, 0));
4532 }
4533 else if (GET_CODE (t) == ZERO_EXTEND
4534 && (GET_CODE (XEXP (t, 0)) == PLUS
4535 || GET_CODE (XEXP (t, 0)) == IOR
4536 || GET_CODE (XEXP (t, 0)) == XOR)
4537 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4538 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4539 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4540 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4541 && ((nonzero_bits (f, GET_MODE (f))
4542 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4543 == 0))
4544 {
4545 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4546 extend_op = ZERO_EXTEND;
4547 m = GET_MODE (XEXP (t, 0));
4548 }
4549
4550 if (z)
4551 {
4552 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4553 pc_rtx, pc_rtx, 0, 0);
4554 temp = gen_binary (MULT, m, temp,
4555 gen_binary (MULT, m, c1, const_true_rtx));
4556 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4557 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4558
4559 if (extend_op != NIL)
0c1c8ea6 4560 temp = gen_unary (extend_op, mode, m, temp);
8079805d
RK		 4561
4562 return temp;
4563 }
4564 }
224eeff2 4565
8079805d
RK		 4566 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4567 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4568 negation of a single bit, we can convert this operation to a shift. We
4569 can actually do this more generally, but it doesn't seem worth it. */
4570
4571 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4572 && false == const0_rtx && GET_CODE (true) == CONST_INT
4573 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4574 && (i = exact_log2 (INTVAL (true))) >= 0)
4575 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4576 == GET_MODE_BITSIZE (mode))
4577 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4578 return
4579 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4580 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
230d793d 4581
8079805d
RK		 4582 return x;
4583}
4584\f
4585/* Simplify X, a SET expression. Return the new expression. */
230d793d 4586
8079805d
RK		 4587static rtx
4588simplify_set (x)
4589 rtx x;
4590{
4591 rtx src = SET_SRC (x);
4592 rtx dest = SET_DEST (x);
4593 enum machine_mode mode
4594 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4595 rtx other_insn;
4596 rtx *cc_use;
4597
4598 /* (set (pc) (return)) gets written as (return). */
4599 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4600 return src;
230d793d 4601
87e3e0c1
RK		 4602 /* Now that we know for sure which bits of SRC we are using, see if we can
4603 simplify the expression for the object knowing that we only need the
4604 low-order bits. */
4605
4606 if (GET_MODE_CLASS (mode) == MODE_INT)
4607 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4608
8079805d
RK		 4609 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4610 the comparison result and try to simplify it unless we already have used
4611 undobuf.other_insn. */
4612 if ((GET_CODE (src) == COMPARE
230d793d 4613#ifdef HAVE_cc0
8079805d 4614 || dest == cc0_rtx
230d793d 4615#endif
8079805d
RK		 4616 )
4617 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4618 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4619 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
c0d3ac4d 4620 && rtx_equal_p (XEXP (*cc_use, 0), dest))
8079805d
RK		 4621 {
4622 enum rtx_code old_code = GET_CODE (*cc_use);
4623 enum rtx_code new_code;
4624 rtx op0, op1;
4625 int other_changed = 0;
4626 enum machine_mode compare_mode = GET_MODE (dest);
4627
4628 if (GET_CODE (src) == COMPARE)
4629 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4630 else
4631 op0 = src, op1 = const0_rtx;
230d793d 4632
8079805d
RK		 4633 /* Simplify our comparison, if possible. */
4634 new_code = simplify_comparison (old_code, &op0, &op1);
230d793d 4635
c141a106 4636#ifdef EXTRA_CC_MODES
8079805d
RK		 4637 /* If this machine has CC modes other than CCmode, check to see if we
4638 need to use a different CC mode here. */
4639 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
c141a106 4640#endif /* EXTRA_CC_MODES */
230d793d 4641
c141a106 4642#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
8079805d
RK		 4643 /* If the mode changed, we have to change SET_DEST, the mode in the
4644 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4645 a hard register, just build new versions with the proper mode. If it
4646 is a pseudo, we lose unless it is only time we set the pseudo, in
4647 which case we can safely change its mode. */
4648 if (compare_mode != GET_MODE (dest))
4649 {
4650 int regno = REGNO (dest);
38a448ca 4651 rtx new_dest = gen_rtx_REG (compare_mode, regno);
8079805d
RK		 4652
4653 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 4654 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
230d793d 4655 {
8079805d
RK		 4656 if (regno >= FIRST_PSEUDO_REGISTER)
4657 SUBST (regno_reg_rtx[regno], new_dest);
230d793d 4658
8079805d
RK		 4659 SUBST (SET_DEST (x), new_dest);
4660 SUBST (XEXP (*cc_use, 0), new_dest);
4661 other_changed = 1;
230d793d 4662
8079805d 4663 dest = new_dest;
230d793d 4664 }
8079805d 4665 }
230d793d
RS		 4666#endif
4667
8079805d
RK		 4668 /* If the code changed, we have to build a new comparison in
4669 undobuf.other_insn. */
4670 if (new_code != old_code)
4671 {
4672 unsigned HOST_WIDE_INT mask;
4673
4674 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4675 dest, const0_rtx));
4676
4677 /* If the only change we made was to change an EQ into an NE or
4678 vice versa, OP0 has only one bit that might be nonzero, and OP1
4679 is zero, check if changing the user of the condition code will
4680 produce a valid insn. If it won't, we can keep the original code
4681 in that insn by surrounding our operation with an XOR. */
4682
4683 if (((old_code == NE && new_code == EQ)
4684 || (old_code == EQ && new_code == NE))
4685 && ! other_changed && op1 == const0_rtx
4686 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4687 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
230d793d 4688 {
8079805d 4689 rtx pat = PATTERN (other_insn), note = 0;
230d793d 4690
8e2f6e35 4691 if ((recog_for_combine (&pat, other_insn, &note) < 0
8079805d
RK		 4692 && ! check_asm_operands (pat)))
4693 {
4694 PUT_CODE (*cc_use, old_code);
4695 other_insn = 0;
230d793d 4696
8079805d 4697 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
230d793d 4698 }
230d793d
RS		 4699 }
4700
8079805d
RK		 4701 other_changed = 1;
4702 }
4703
4704 if (other_changed)
4705 undobuf.other_insn = other_insn;
230d793d
RS		 4706
4707#ifdef HAVE_cc0
8079805d
RK		 4708 /* If we are now comparing against zero, change our source if
4709 needed. If we do not use cc0, we always have a COMPARE. */
4710 if (op1 == const0_rtx && dest == cc0_rtx)
4711 {
4712 SUBST (SET_SRC (x), op0);
4713 src = op0;
4714 }
4715 else
230d793d
RS		 4716#endif
4717
8079805d
RK		 4718 /* Otherwise, if we didn't previously have a COMPARE in the
4719 correct mode, we need one. */
4720 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4721 {
4722 SUBST (SET_SRC (x),
4723 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4724 src = SET_SRC (x);
230d793d
RS		 4725 }
4726 else
4727 {
8079805d
RK		 4728 /* Otherwise, update the COMPARE if needed. */
4729 SUBST (XEXP (src, 0), op0);
4730 SUBST (XEXP (src, 1), op1);
230d793d 4731 }
8079805d
RK		 4732 }
4733 else
4734 {
4735 /* Get SET_SRC in a form where we have placed back any
4736 compound expressions. Then do the checks below. */
4737 src = make_compound_operation (src, SET);
4738 SUBST (SET_SRC (x), src);
4739 }
230d793d 4740
8079805d
RK		 4741 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4742 and X being a REG or (subreg (reg)), we may be able to convert this to
4743 (set (subreg:m2 x) (op)).
df62f951 4744
8079805d
RK		 4745 We can always do this if M1 is narrower than M2 because that means that
4746 we only care about the low bits of the result.
df62f951 4747
8079805d 4748 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
9ec36da5 4749 perform a narrower operation than requested since the high-order bits will
8079805d
RK		 4750 be undefined. On machine where it is defined, this transformation is safe
4751 as long as M1 and M2 have the same number of words. */
df62f951 4752
8079805d
RK		 4753 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4754 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4755 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4756 / UNITS_PER_WORD)
4757 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4758 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
8baf60bb 4759#ifndef WORD_REGISTER_OPERATIONS
8079805d
RK		 4760 && (GET_MODE_SIZE (GET_MODE (src))
4761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
df62f951 4762#endif
f507a070
RK		 4763#ifdef CLASS_CANNOT_CHANGE_SIZE
4764 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4765 && (TEST_HARD_REG_BIT
4766 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4767 REGNO (dest)))
4768 && (GET_MODE_SIZE (GET_MODE (src))
4769 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4770#endif
8079805d
RK		 4771 && (GET_CODE (dest) == REG
4772 || (GET_CODE (dest) == SUBREG
4773 && GET_CODE (SUBREG_REG (dest)) == REG)))
4774 {
4775 SUBST (SET_DEST (x),
4776 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4777 dest));
4778 SUBST (SET_SRC (x), SUBREG_REG (src));
4779
4780 src = SET_SRC (x), dest = SET_DEST (x);
4781 }
df62f951 4782
8baf60bb 4783#ifdef LOAD_EXTEND_OP
8079805d
RK		 4784 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4785 would require a paradoxical subreg. Replace the subreg with a
0f41302f 4786 zero_extend to avoid the reload that would otherwise be required. */
8079805d
RK		 4787
4788 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4789 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4790 && SUBREG_WORD (src) == 0
4791 && (GET_MODE_SIZE (GET_MODE (src))
4792 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4793 && GET_CODE (SUBREG_REG (src)) == MEM)
4794 {
4795 SUBST (SET_SRC (x),
4796 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4797 GET_MODE (src), XEXP (src, 0)));
4798
4799 src = SET_SRC (x);
4800 }
230d793d
RS		 4801#endif
4802
8079805d
RK		 4803 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4804 are comparing an item known to be 0 or -1 against 0, use a logical
4805 operation instead. Check for one of the arms being an IOR of the other
4806 arm with some value. We compute three terms to be IOR'ed together. In
4807 practice, at most two will be nonzero. Then we do the IOR's. */
4808
4809 if (GET_CODE (dest) != PC
4810 && GET_CODE (src) == IF_THEN_ELSE
36b8d792 4811 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
8079805d
RK		 4812 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4813 && XEXP (XEXP (src, 0), 1) == const0_rtx
6dd49058 4814 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
ea414472
DE		 4815#ifdef HAVE_conditional_move
4816 && ! can_conditionally_move_p (GET_MODE (src))
4817#endif
8079805d
RK		 4818 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4819 GET_MODE (XEXP (XEXP (src, 0), 0)))
4820 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4821 && ! side_effects_p (src))
4822 {
4823 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4824 ? XEXP (src, 1) : XEXP (src, 2));
4825 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4826 ? XEXP (src, 2) : XEXP (src, 1));
4827 rtx term1 = const0_rtx, term2, term3;
4828
4829 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4830 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4831 else if (GET_CODE (true) == IOR
4832 && rtx_equal_p (XEXP (true, 1), false))
4833 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4834 else if (GET_CODE (false) == IOR
4835 && rtx_equal_p (XEXP (false, 0), true))
4836 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4837 else if (GET_CODE (false) == IOR
4838 && rtx_equal_p (XEXP (false, 1), true))
4839 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4840
4841 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4842 term3 = gen_binary (AND, GET_MODE (src),
0c1c8ea6 4843 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
8079805d
RK		 4844 XEXP (XEXP (src, 0), 0)),
4845 false);
4846
4847 SUBST (SET_SRC (x),
4848 gen_binary (IOR, GET_MODE (src),
4849 gen_binary (IOR, GET_MODE (src), term1, term2),
4850 term3));
4851
4852 src = SET_SRC (x);
4853 }
230d793d 4854
246e00f2
RK		 4855 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4856 whole thing fail. */
4857 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4858 return src;
4859 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4860 return dest;
4861 else
4862 /* Convert this into a field assignment operation, if possible. */
4863 return make_field_assignment (x);
8079805d
RK		 4864}
4865\f
4866/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4867 result. LAST is nonzero if this is the last retry. */
4868
4869static rtx
4870simplify_logical (x, last)
4871 rtx x;
4872 int last;
4873{
4874 enum machine_mode mode = GET_MODE (x);
4875 rtx op0 = XEXP (x, 0);
4876 rtx op1 = XEXP (x, 1);
4877
4878 switch (GET_CODE (x))
4879 {
230d793d 4880 case AND:
8079805d
RK		 4881 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4882 insn (and may simplify more). */
4883 if (GET_CODE (op0) == XOR
4884 && rtx_equal_p (XEXP (op0, 0), op1)
4885 && ! side_effects_p (op1))
0c1c8ea6
RK		 4886 x = gen_binary (AND, mode,
4887 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
8079805d
RK		 4888
4889 if (GET_CODE (op0) == XOR
4890 && rtx_equal_p (XEXP (op0, 1), op1)
4891 && ! side_effects_p (op1))
0c1c8ea6
RK		 4892 x = gen_binary (AND, mode,
4893 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
8079805d
RK		 4894
4895 /* Similarly for (~ (A ^ B)) & A. */
4896 if (GET_CODE (op0) == NOT
4897 && GET_CODE (XEXP (op0, 0)) == XOR
4898 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4899 && ! side_effects_p (op1))
4900 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4901
4902 if (GET_CODE (op0) == NOT
4903 && GET_CODE (XEXP (op0, 0)) == XOR
4904 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4905 && ! side_effects_p (op1))
4906 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4907
2e8f9abf
DM		 4908 /* We can call simplify_and_const_int only if we don't lose
4909 any (sign) bits when converting INTVAL (op1) to
4910 "unsigned HOST_WIDE_INT". */
4911 if (GET_CODE (op1) == CONST_INT
4912 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4913 || INTVAL (op1) > 0))
230d793d 4914 {
8079805d 4915 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
230d793d
RS		 4916
4917 /* If we have (ior (and (X C1) C2)) and the next restart would be
4918 the last, simplify this by making C1 as small as possible
0f41302f 4919 and then exit. */
8079805d
RK		 4920 if (last
4921 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4922 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4923 && GET_CODE (op1) == CONST_INT)
4924 return gen_binary (IOR, mode,
4925 gen_binary (AND, mode, XEXP (op0, 0),
4926 GEN_INT (INTVAL (XEXP (op0, 1))
4927 & ~ INTVAL (op1))), op1);
230d793d
RS		 4928
4929 if (GET_CODE (x) != AND)
8079805d 4930 return x;
0e32506c
RK		 4931
4932 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4933 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4934 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
230d793d
RS		 4935 }
4936
4937 /* Convert (A | B) & A to A. */
8079805d
RK		 4938 if (GET_CODE (op0) == IOR
4939 && (rtx_equal_p (XEXP (op0, 0), op1)
4940 || rtx_equal_p (XEXP (op0, 1), op1))
4941 && ! side_effects_p (XEXP (op0, 0))
4942 && ! side_effects_p (XEXP (op0, 1)))
4943 return op1;
230d793d 4944
d0ab8cd3 4945 /* In the following group of tests (and those in case IOR below),
230d793d
RS		 4946 we start with some combination of logical operations and apply
4947 the distributive law followed by the inverse distributive law.
4948 Most of the time, this results in no change. However, if some of
4949 the operands are the same or inverses of each other, simplifications
4950 will result.
4951
4952 For example, (and (ior A B) (not B)) can occur as the result of
4953 expanding a bit field assignment. When we apply the distributive
4954 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8079805d 4955 which then simplifies to (and (A (not B))).
230d793d 4956
8079805d 4957 If we have (and (ior A B) C), apply the distributive law and then
230d793d
RS		 4958 the inverse distributive law to see if things simplify. */
4959
8079805d 4960 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
230d793d
RS		 4961 {
4962 x = apply_distributive_law
8079805d
RK		 4963 (gen_binary (GET_CODE (op0), mode,
4964 gen_binary (AND, mode, XEXP (op0, 0), op1),
4965 gen_binary (AND, mode, XEXP (op0, 1), op1)));
230d793d 4966 if (GET_CODE (x) != AND)
8079805d 4967 return x;
230d793d
RS		 4968 }
4969
8079805d
RK		 4970 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4971 return apply_distributive_law
4972 (gen_binary (GET_CODE (op1), mode,
4973 gen_binary (AND, mode, XEXP (op1, 0), op0),
4974 gen_binary (AND, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4975
4976 /* Similarly, taking advantage of the fact that
4977 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4978
8079805d
RK		 4979 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4980 return apply_distributive_law
4981 (gen_binary (XOR, mode,
4982 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4983 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
230d793d 4984
8079805d
RK		 4985 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4986 return apply_distributive_law
4987 (gen_binary (XOR, mode,
4988 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4989 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
230d793d
RS		 4990 break;
4991
4992 case IOR:
951553af 4993 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
8079805d 4994 if (GET_CODE (op1) == CONST_INT
ac49a949 4995 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8079805d
RK		 4996 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4997 return op1;
d0ab8cd3 4998
230d793d 4999 /* Convert (A & B) | A to A. */
8079805d
RK		 5000 if (GET_CODE (op0) == AND
5001 && (rtx_equal_p (XEXP (op0, 0), op1)
5002 || rtx_equal_p (XEXP (op0, 1), op1))
5003 && ! side_effects_p (XEXP (op0, 0))
5004 && ! side_effects_p (XEXP (op0, 1)))
5005 return op1;
230d793d
RS		 5006
5007 /* If we have (ior (and A B) C), apply the distributive law and then
5008 the inverse distributive law to see if things simplify. */
5009
8079805d 5010 if (GET_CODE (op0) == AND)
230d793d
RS		 5011 {
5012 x = apply_distributive_law
5013 (gen_binary (AND, mode,
8079805d
RK		 5014 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5015 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
230d793d
RS		 5016
5017 if (GET_CODE (x) != IOR)
8079805d 5018 return x;
230d793d
RS		 5019 }
5020
8079805d 5021 if (GET_CODE (op1) == AND)
230d793d
RS		 5022 {
5023 x = apply_distributive_law
5024 (gen_binary (AND, mode,
8079805d
RK		 5025 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5026 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
230d793d
RS		 5027
5028 if (GET_CODE (x) != IOR)
8079805d 5029 return x;
230d793d
RS		 5030 }
5031
5032 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5033 mode size to (rotate A CX). */
5034
8079805d
RK		 5035 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5036 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5037 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5038 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5039 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5040 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
230d793d 5041 == GET_MODE_BITSIZE (mode)))
38a448ca
RH		 5042 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5043 (GET_CODE (op0) == ASHIFT
5044 ? XEXP (op0, 1) : XEXP (op1, 1)));
230d793d 5045
71923da7
RK		 5046 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5047 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5048 does not affect any of the bits in OP1, it can really be done
5049 as a PLUS and we can associate. We do this by seeing if OP1
5050 can be safely shifted left C bits. */
5051 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5052 && GET_CODE (XEXP (op0, 0)) == PLUS
5053 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5054 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5055 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5056 {
5057 int count = INTVAL (XEXP (op0, 1));
5058 HOST_WIDE_INT mask = INTVAL (op1) << count;
5059
5060 if (mask >> count == INTVAL (op1)
5061 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5062 {
5063 SUBST (XEXP (XEXP (op0, 0), 1),
5064 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5065 return op0;
5066 }
5067 }
230d793d
RS		 5068 break;
5069
5070 case XOR:
5071 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5072 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5073 (NOT y). */
5074 {
5075 int num_negated = 0;
230d793d 5076
8079805d
RK		 5077 if (GET_CODE (op0) == NOT)
5078 num_negated++, op0 = XEXP (op0, 0);
5079 if (GET_CODE (op1) == NOT)
5080 num_negated++, op1 = XEXP (op1, 0);
230d793d
RS		 5081
5082 if (num_negated == 2)
5083 {
8079805d
RK		 5084 SUBST (XEXP (x, 0), op0);
5085 SUBST (XEXP (x, 1), op1);
230d793d
RS		 5086 }
5087 else if (num_negated == 1)
0c1c8ea6 5088 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
230d793d
RS		 5089 }
5090
5091 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5092 correspond to a machine insn or result in further simplifications
5093 if B is a constant. */
5094
8079805d
RK		 5095 if (GET_CODE (op0) == AND
5096 && rtx_equal_p (XEXP (op0, 1), op1)
5097 && ! side_effects_p (op1))
0c1c8ea6
RK		 5098 return gen_binary (AND, mode,
5099 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
8079805d 5100 op1);
230d793d 5101
8079805d
RK		 5102 else if (GET_CODE (op0) == AND
5103 && rtx_equal_p (XEXP (op0, 0), op1)
5104 && ! side_effects_p (op1))
0c1c8ea6
RK		 5105 return gen_binary (AND, mode,
5106 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
8079805d 5107 op1);
230d793d 5108
230d793d 5109 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
0802d516
RK		 5110 comparison if STORE_FLAG_VALUE is 1. */
5111 if (STORE_FLAG_VALUE == 1
5112 && op1 == const1_rtx
8079805d
RK		 5113 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5114 && reversible_comparison_p (op0))
5115 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5116 mode, XEXP (op0, 0), XEXP (op0, 1));
500c518b
RK		 5117
5118 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5119 is (lt foo (const_int 0)), so we can perform the above
0802d516 5120 simplification if STORE_FLAG_VALUE is 1. */
500c518b 5121
0802d516
RK		 5122 if (STORE_FLAG_VALUE == 1
5123 && op1 == const1_rtx
8079805d
RK		 5124 && GET_CODE (op0) == LSHIFTRT
5125 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5126 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5127 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
230d793d
RS		 5128
5129 /* (xor (comparison foo bar) (const_int sign-bit))
5130 when STORE_FLAG_VALUE is the sign bit. */
5f4f0e22 5131 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 5132 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 5133 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
8079805d
RK		 5134 && op1 == const_true_rtx
5135 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5136 && reversible_comparison_p (op0))
5137 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5138 mode, XEXP (op0, 0), XEXP (op0, 1));
230d793d 5139 break;
e9a25f70
JL		 5140
5141 default:
5142 abort ();
230d793d
RS		 5143 }
5144
5145 return x;
5146}
5147\f
5148/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5149 operations" because they can be replaced with two more basic operations.
5150 ZERO_EXTEND is also considered "compound" because it can be replaced with
5151 an AND operation, which is simpler, though only one operation.
5152
5153 The function expand_compound_operation is called with an rtx expression
5154 and will convert it to the appropriate shifts and AND operations,
5155 simplifying at each stage.
5156
5157 The function make_compound_operation is called to convert an expression
5158 consisting of shifts and ANDs into the equivalent compound expression.
5159 It is the inverse of this function, loosely speaking. */
5160
5161static rtx
5162expand_compound_operation (x)
5163 rtx x;
5164{
5165 int pos = 0, len;
5166 int unsignedp = 0;
5167 int modewidth;
5168 rtx tem;
5169
5170 switch (GET_CODE (x))
5171 {
5172 case ZERO_EXTEND:
5173 unsignedp = 1;
5174 case SIGN_EXTEND:
75473182
RS		 5175 /* We can't necessarily use a const_int for a multiword mode;
5176 it depends on implicitly extending the value.
5177 Since we don't know the right way to extend it,
5178 we can't tell whether the implicit way is right.
5179
5180 Even for a mode that is no wider than a const_int,
5181 we can't win, because we need to sign extend one of its bits through
5182 the rest of it, and we don't know which bit. */
230d793d 5183 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
75473182 5184 return x;
230d793d 5185
8079805d
RK		 5186 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5187 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5188 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5189 reloaded. If not for that, MEM's would very rarely be safe.
5190
5191 Reject MODEs bigger than a word, because we might not be able
5192 to reference a two-register group starting with an arbitrary register
5193 (and currently gen_lowpart might crash for a SUBREG). */
5194
5195 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
230d793d
RS		 5196 return x;
5197
5198 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5199 /* If the inner object has VOIDmode (the only way this can happen
5200 is if it is a ASM_OPERANDS), we can't do anything since we don't
5201 know how much masking to do. */
5202 if (len == 0)
5203 return x;
5204
5205 break;
5206
5207 case ZERO_EXTRACT:
5208 unsignedp = 1;
5209 case SIGN_EXTRACT:
5210 /* If the operand is a CLOBBER, just return it. */
5211 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5212 return XEXP (x, 0);
5213
5214 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5215 || GET_CODE (XEXP (x, 2)) != CONST_INT
5216 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5217 return x;
5218
5219 len = INTVAL (XEXP (x, 1));
5220 pos = INTVAL (XEXP (x, 2));
5221
5222 /* If this goes outside the object being extracted, replace the object
5223 with a (use (mem ...)) construct that only combine understands
5224 and is used only for this purpose. */
5225 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
38a448ca 5226 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
230d793d 5227
f76b9db2
ILT		 5228 if (BITS_BIG_ENDIAN)
5229 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5230
230d793d
RS		 5231 break;
5232
5233 default:
5234 return x;
5235 }
5236
0f13a422
ILT		 5237 /* We can optimize some special cases of ZERO_EXTEND. */
5238 if (GET_CODE (x) == ZERO_EXTEND)
5239 {
5240 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5241 know that the last value didn't have any inappropriate bits
5242 set. */
5243 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5244 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5245 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5246 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5247 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5248 return XEXP (XEXP (x, 0), 0);
5249
5250 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5251 if (GET_CODE (XEXP (x, 0)) == SUBREG
5252 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5253 && subreg_lowpart_p (XEXP (x, 0))
5254 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5255 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
fcc60894 5256 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
0f13a422
ILT		 5257 return SUBREG_REG (XEXP (x, 0));
5258
5259 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5260 is a comparison and STORE_FLAG_VALUE permits. This is like
5261 the first case, but it works even when GET_MODE (x) is larger
5262 than HOST_WIDE_INT. */
5263 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5264 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5265 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5266 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5267 <= HOST_BITS_PER_WIDE_INT)
5268 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5269 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5270 return XEXP (XEXP (x, 0), 0);
5271
5272 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5273 if (GET_CODE (XEXP (x, 0)) == SUBREG
5274 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5275 && subreg_lowpart_p (XEXP (x, 0))
5276 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5277 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5278 <= HOST_BITS_PER_WIDE_INT)
5279 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5280 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5281 return SUBREG_REG (XEXP (x, 0));
5282
5283 /* If sign extension is cheaper than zero extension, then use it
5284 if we know that no extraneous bits are set, and that the high
5285 bit is not set. */
5286 if (flag_expensive_optimizations
5287 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5288 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5289 & ~ (((unsigned HOST_WIDE_INT)
5290 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5291 >> 1))
5292 == 0))
5293 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5294 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5295 <= HOST_BITS_PER_WIDE_INT)
5296 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5297 & ~ (((unsigned HOST_WIDE_INT)
5298 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5299 >> 1))
5300 == 0))))
5301 {
38a448ca 5302 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
0f13a422
ILT		 5303
5304 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5305 return expand_compound_operation (temp);
5306 }
5307 }
5308
230d793d
RS		 5309 /* If we reach here, we want to return a pair of shifts. The inner
5310 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5311 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5312 logical depending on the value of UNSIGNEDP.
5313
5314 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5315 converted into an AND of a shift.
5316
5317 We must check for the case where the left shift would have a negative
5318 count. This can happen in a case like (x >> 31) & 255 on machines
5319 that can't shift by a constant. On those machines, we would first
5320 combine the shift with the AND to produce a variable-position
5321 extraction. Then the constant of 31 would be substituted in to produce
5322 a such a position. */
5323
5324 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5325 if (modewidth >= pos - len)
5f4f0e22 5326 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
230d793d 5327 GET_MODE (x),
5f4f0e22
CH		 5328 simplify_shift_const (NULL_RTX, ASHIFT,
5329 GET_MODE (x),
230d793d
RS		 5330 XEXP (x, 0),
5331 modewidth - pos - len),
5332 modewidth - len);
5333
5f4f0e22
CH		 5334 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5335 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5336 simplify_shift_const (NULL_RTX, LSHIFTRT,
230d793d
RS		 5337 GET_MODE (x),
5338 XEXP (x, 0), pos),
5f4f0e22 5339 ((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5340 else
5341 /* Any other cases we can't handle. */
5342 return x;
5343
5344
5345 /* If we couldn't do this for some reason, return the original
5346 expression. */
5347 if (GET_CODE (tem) == CLOBBER)
5348 return x;
5349
5350 return tem;
5351}
5352\f
5353/* X is a SET which contains an assignment of one object into
5354 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5355 or certain SUBREGS). If possible, convert it into a series of
5356 logical operations.
5357
5358 We half-heartedly support variable positions, but do not at all
5359 support variable lengths. */
5360
5361static rtx
5362expand_field_assignment (x)
5363 rtx x;
5364{
5365 rtx inner;
0f41302f 5366 rtx pos; /* Always counts from low bit. */
230d793d
RS		 5367 int len;
5368 rtx mask;
5369 enum machine_mode compute_mode;
5370
5371 /* Loop until we find something we can't simplify. */
5372 while (1)
5373 {
5374 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5375 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5376 {
5377 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5378 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4d9cfc7b 5379 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
230d793d
RS		 5380 }
5381 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5382 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5383 {
5384 inner = XEXP (SET_DEST (x), 0);
5385 len = INTVAL (XEXP (SET_DEST (x), 1));
5386 pos = XEXP (SET_DEST (x), 2);
5387
5388 /* If the position is constant and spans the width of INNER,
5389 surround INNER with a USE to indicate this. */
5390 if (GET_CODE (pos) == CONST_INT
5391 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
38a448ca 5392 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
230d793d 5393
f76b9db2
ILT		 5394 if (BITS_BIG_ENDIAN)
5395 {
5396 if (GET_CODE (pos) == CONST_INT)
5397 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5398 - INTVAL (pos));
5399 else if (GET_CODE (pos) == MINUS
5400 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5401 && (INTVAL (XEXP (pos, 1))
5402 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5403 /* If position is ADJUST - X, new position is X. */
5404 pos = XEXP (pos, 0);
5405 else
5406 pos = gen_binary (MINUS, GET_MODE (pos),
5407 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5408 - len),
5409 pos);
5410 }
230d793d
RS		 5411 }
5412
5413 /* A SUBREG between two modes that occupy the same numbers of words
5414 can be done by moving the SUBREG to the source. */
5415 else if (GET_CODE (SET_DEST (x)) == SUBREG
5416 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5417 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5418 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5419 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5420 {
38a448ca
RH		 5421 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5422 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5423 SET_SRC (x)));
230d793d
RS		 5424 continue;
5425 }
5426 else
5427 break;
5428
5429 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5430 inner = SUBREG_REG (inner);
5431
5432 compute_mode = GET_MODE (inner);
5433
861556b4
RH		 5434 /* Don't attempt bitwise arithmetic on non-integral modes. */
5435 if (! INTEGRAL_MODE_P (compute_mode))
5436 {
5437 enum machine_mode imode;
5438
5439 /* Something is probably seriously wrong if this matches. */
5440 if (! FLOAT_MODE_P (compute_mode))
5441 break;
5442
5443 /* Try to find an integral mode to pun with. */
5444 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5445 if (imode == BLKmode)
5446 break;
5447
5448 compute_mode = imode;
5449 inner = gen_lowpart_for_combine (imode, inner);
5450 }
5451
230d793d 5452 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5f4f0e22
CH		 5453 if (len < HOST_BITS_PER_WIDE_INT)
5454 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5455 else
5456 break;
5457
5458 /* Now compute the equivalent expression. Make a copy of INNER
5459 for the SET_DEST in case it is a MEM into which we will substitute;
5460 we don't want shared RTL in that case. */
38a448ca
RH		 5461 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5462 gen_binary (IOR, compute_mode,
5463 gen_binary (AND, compute_mode,
5464 gen_unary (NOT, compute_mode,
5465 compute_mode,
5466 gen_binary (ASHIFT,
5467 compute_mode,
5468 mask, pos)),
5469 inner),
5470 gen_binary (ASHIFT, compute_mode,
5471 gen_binary (AND, compute_mode,
5472 gen_lowpart_for_combine
5473 (compute_mode,
5474 SET_SRC (x)),
5475 mask),
5476 pos)));
230d793d
RS		 5477 }
5478
5479 return x;
5480}
5481\f
8999a12e
RK		 5482/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5483 it is an RTX that represents a variable starting position; otherwise,
5484 POS is the (constant) starting bit position (counted from the LSB).
230d793d
RS		 5485
5486 INNER may be a USE. This will occur when we started with a bitfield
5487 that went outside the boundary of the object in memory, which is
5488 allowed on most machines. To isolate this case, we produce a USE
5489 whose mode is wide enough and surround the MEM with it. The only
5490 code that understands the USE is this routine. If it is not removed,
5491 it will cause the resulting insn not to match.
5492
5493 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5494 signed reference.
5495
5496 IN_DEST is non-zero if this is a reference in the destination of a
5497 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5498 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5499 be used.
5500
5501 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5502 ZERO_EXTRACT should be built even for bits starting at bit 0.
5503
76184def
DE		 5504 MODE is the desired mode of the result (if IN_DEST == 0).
5505
5506 The result is an RTX for the extraction or NULL_RTX if the target
5507 can't handle it. */
230d793d
RS		 5508
5509static rtx
5510make_extraction (mode, inner, pos, pos_rtx, len,
5511 unsignedp, in_dest, in_compare)
5512 enum machine_mode mode;
5513 rtx inner;
5514 int pos;
5515 rtx pos_rtx;
5516 int len;
5517 int unsignedp;
5518 int in_dest, in_compare;
5519{
94b4b17a
RS		 5520 /* This mode describes the size of the storage area
5521 to fetch the overall value from. Within that, we
5522 ignore the POS lowest bits, etc. */
230d793d
RS		 5523 enum machine_mode is_mode = GET_MODE (inner);
5524 enum machine_mode inner_mode;
d7cd794f
RK		 5525 enum machine_mode wanted_inner_mode = byte_mode;
5526 enum machine_mode wanted_inner_reg_mode = word_mode;
230d793d
RS		 5527 enum machine_mode pos_mode = word_mode;
5528 enum machine_mode extraction_mode = word_mode;
5529 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5530 int spans_byte = 0;
5531 rtx new = 0;
8999a12e 5532 rtx orig_pos_rtx = pos_rtx;
6139ff20 5533 int orig_pos;
230d793d
RS		 5534
5535 /* Get some information about INNER and get the innermost object. */
5536 if (GET_CODE (inner) == USE)
94b4b17a 5537 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
230d793d
RS		 5538 /* We don't need to adjust the position because we set up the USE
5539 to pretend that it was a full-word object. */
5540 spans_byte = 1, inner = XEXP (inner, 0);
5541 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
94b4b17a
RS		 5542 {
5543 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5544 consider just the QI as the memory to extract from.
5545 The subreg adds or removes high bits; its mode is
5546 irrelevant to the meaning of this extraction,
5547 since POS and LEN count from the lsb. */
5548 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5549 is_mode = GET_MODE (SUBREG_REG (inner));
5550 inner = SUBREG_REG (inner);
5551 }
230d793d
RS		 5552
5553 inner_mode = GET_MODE (inner);
5554
5555 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
8999a12e 5556 pos = INTVAL (pos_rtx), pos_rtx = 0;
230d793d
RS		 5557
5558 /* See if this can be done without an extraction. We never can if the
5559 width of the field is not the same as that of some integer mode. For
5560 registers, we can only avoid the extraction if the position is at the
5561 low-order bit and this is either not in the destination or we have the
5562 appropriate STRICT_LOW_PART operation available.
5563
5564 For MEM, we can avoid an extract if the field starts on an appropriate
5565 boundary and we can change the mode of the memory reference. However,
5566 we cannot directly access the MEM if we have a USE and the underlying
5567 MEM is not TMODE. This combination means that MEM was being used in a
5568 context where bits outside its mode were being referenced; that is only
5569 valid in bit-field insns. */
5570
5571 if (tmode != BLKmode
5572 && ! (spans_byte && inner_mode != tmode)
4d9cfc7b
RK		 5573 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5574 && GET_CODE (inner) != MEM
230d793d 5575 && (! in_dest
df62f951
RK		 5576 || (GET_CODE (inner) == REG
5577 && (movstrict_optab->handlers[(int) tmode].insn_code
5578 != CODE_FOR_nothing))))
8999a12e 5579 || (GET_CODE (inner) == MEM && pos_rtx == 0
dfbe1b2f
RK		 5580 && (pos
5581 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5582 : BITS_PER_UNIT)) == 0
230d793d
RS		 5583 /* We can't do this if we are widening INNER_MODE (it
5584 may not be aligned, for one thing). */
5585 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5586 && (inner_mode == tmode
5587 || (! mode_dependent_address_p (XEXP (inner, 0))
5588 && ! MEM_VOLATILE_P (inner))))))
5589 {
230d793d
RS		 5590 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5591 field. If the original and current mode are the same, we need not
5592 adjust the offset. Otherwise, we do if bytes big endian.
5593
4d9cfc7b
RK		 5594 If INNER is not a MEM, get a piece consisting of just the field
5595 of interest (in this case POS % BITS_PER_WORD must be 0). */
230d793d
RS		 5596
5597 if (GET_CODE (inner) == MEM)
5598 {
94b4b17a
RS		 5599 int offset;
5600 /* POS counts from lsb, but make OFFSET count in memory order. */
5601 if (BYTES_BIG_ENDIAN)
5602 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5603 else
5604 offset = pos / BITS_PER_UNIT;
230d793d 5605
38a448ca 5606 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
230d793d 5607 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
c6df88cb 5608 MEM_COPY_ATTRIBUTES (new, inner);
230d793d 5609 }
df62f951 5610 else if (GET_CODE (inner) == REG)
c0d3ac4d
RK		 5611 {
5612 /* We can't call gen_lowpart_for_combine here since we always want
5613 a SUBREG and it would sometimes return a new hard register. */
5614 if (tmode != inner_mode)
38a448ca
RH		 5615 new = gen_rtx_SUBREG (tmode, inner,
5616 (WORDS_BIG_ENDIAN
5617 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5618 ? (((GET_MODE_SIZE (inner_mode)
5619 - GET_MODE_SIZE (tmode))
5620 / UNITS_PER_WORD)
5621 - pos / BITS_PER_WORD)
5622 : pos / BITS_PER_WORD));
c0d3ac4d
RK		 5623 else
5624 new = inner;
5625 }
230d793d 5626 else
6139ff20
RK		 5627 new = force_to_mode (inner, tmode,
5628 len >= HOST_BITS_PER_WIDE_INT
5629 ? GET_MODE_MASK (tmode)
5630 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 5631 NULL_RTX, 0);
230d793d
RS		 5632
5633 /* If this extraction is going into the destination of a SET,
5634 make a STRICT_LOW_PART unless we made a MEM. */
5635
5636 if (in_dest)
5637 return (GET_CODE (new) == MEM ? new
77fa0940 5638 : (GET_CODE (new) != SUBREG
38a448ca 5639 ? gen_rtx_CLOBBER (tmode, const0_rtx)
77fa0940 5640 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
230d793d
RS		 5641
5642 /* Otherwise, sign- or zero-extend unless we already are in the
5643 proper mode. */
5644
5645 return (mode == tmode ? new
5646 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5647 mode, new));
5648 }
5649
cc471082
RS		 5650 /* Unless this is a COMPARE or we have a funny memory reference,
5651 don't do anything with zero-extending field extracts starting at
5652 the low-order bit since they are simple AND operations. */
8999a12e
RK		 5653 if (pos_rtx == 0 && pos == 0 && ! in_dest
5654 && ! in_compare && ! spans_byte && unsignedp)
230d793d
RS		 5655 return 0;
5656
e7373556
RK		 5657 /* Unless we are allowed to span bytes, reject this if we would be
5658 spanning bytes or if the position is not a constant and the length
5659 is not 1. In all other cases, we would only be going outside
5660 out object in cases when an original shift would have been
5661 undefined. */
5662 if (! spans_byte
5663 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5664 || (pos_rtx != 0 && len != 1)))
5665 return 0;
5666
d7cd794f 5667 /* Get the mode to use should INNER not be a MEM, the mode for the position,
230d793d
RS		 5668 and the mode for the result. */
5669#ifdef HAVE_insv
5670 if (in_dest)
5671 {
0d8e55d8
JL		 5672 wanted_inner_reg_mode
5673 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode
5674 ? word_mode
5675 : insn_operand_mode[(int) CODE_FOR_insv][0]);
5676 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode
5677 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]);
5678 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode
5679 ? word_mode
5680 : insn_operand_mode[(int) CODE_FOR_insv][3]);
230d793d
RS		 5681 }
5682#endif
5683
5684#ifdef HAVE_extzv
5685 if (! in_dest && unsignedp)
5686 {
0d8e55d8
JL		 5687 wanted_inner_reg_mode
5688 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode
5689 ? word_mode
5690 : insn_operand_mode[(int) CODE_FOR_extzv][1]);
5691 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode
5692 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]);
5693 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode
5694 ? word_mode
5695 : insn_operand_mode[(int) CODE_FOR_extzv][0]);
230d793d
RS		 5696 }
5697#endif
5698
5699#ifdef HAVE_extv
5700 if (! in_dest && ! unsignedp)
5701 {
0d8e55d8
JL		 5702 wanted_inner_reg_mode
5703 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode
5704 ? word_mode
5705 : insn_operand_mode[(int) CODE_FOR_extv][1]);
5706 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode
5707 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]);
5708 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode
5709 ? word_mode
5710 : insn_operand_mode[(int) CODE_FOR_extv][0]);
230d793d
RS		 5711 }
5712#endif
5713
5714 /* Never narrow an object, since that might not be safe. */
5715
5716 if (mode != VOIDmode
5717 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5718 extraction_mode = mode;
5719
5720 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5721 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5722 pos_mode = GET_MODE (pos_rtx);
5723
d7cd794f
RK		 5724 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5725 if we have to change the mode of memory and cannot, the desired mode is
5726 EXTRACTION_MODE. */
5727 if (GET_CODE (inner) != MEM)
5728 wanted_inner_mode = wanted_inner_reg_mode;
5729 else if (inner_mode != wanted_inner_mode
5730 && (mode_dependent_address_p (XEXP (inner, 0))
5731 || MEM_VOLATILE_P (inner)))
5732 wanted_inner_mode = extraction_mode;
230d793d 5733
6139ff20
RK		 5734 orig_pos = pos;
5735
f76b9db2
ILT		 5736 if (BITS_BIG_ENDIAN)
5737 {
cf54c2cd
DE		 5738 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5739 BITS_BIG_ENDIAN style. If position is constant, compute new
5740 position. Otherwise, build subtraction.
5741 Note that POS is relative to the mode of the original argument.
5742 If it's a MEM we need to recompute POS relative to that.
5743 However, if we're extracting from (or inserting into) a register,
5744 we want to recompute POS relative to wanted_inner_mode. */
5745 int width = (GET_CODE (inner) == MEM
5746 ? GET_MODE_BITSIZE (is_mode)
5747 : GET_MODE_BITSIZE (wanted_inner_mode));
5748
f76b9db2 5749 if (pos_rtx == 0)
cf54c2cd 5750 pos = width - len - pos;
f76b9db2
ILT		 5751 else
5752 pos_rtx
5753 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
cf54c2cd
DE		 5754 GEN_INT (width - len), pos_rtx);
5755 /* POS may be less than 0 now, but we check for that below.
5756 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
f76b9db2 5757 }
230d793d
RS		 5758
5759 /* If INNER has a wider mode, make it smaller. If this is a constant
5760 extract, try to adjust the byte to point to the byte containing
5761 the value. */
d7cd794f
RK		 5762 if (wanted_inner_mode != VOIDmode
5763 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
230d793d 5764 && ((GET_CODE (inner) == MEM
d7cd794f 5765 && (inner_mode == wanted_inner_mode
230d793d
RS		 5766 || (! mode_dependent_address_p (XEXP (inner, 0))
5767 && ! MEM_VOLATILE_P (inner))))))
5768 {
5769 int offset = 0;
5770
5771 /* The computations below will be correct if the machine is big
5772 endian in both bits and bytes or little endian in bits and bytes.
5773 If it is mixed, we must adjust. */
5774
230d793d 5775 /* If bytes are big endian and we had a paradoxical SUBREG, we must
0f41302f 5776 adjust OFFSET to compensate. */
f76b9db2
ILT		 5777 if (BYTES_BIG_ENDIAN
5778 && ! spans_byte
230d793d
RS		 5779 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5780 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
230d793d
RS		 5781
5782 /* If this is a constant position, we can move to the desired byte. */
8999a12e 5783 if (pos_rtx == 0)
230d793d
RS		 5784 {
5785 offset += pos / BITS_PER_UNIT;
d7cd794f 5786 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
230d793d
RS		 5787 }
5788
f76b9db2
ILT		 5789 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5790 && ! spans_byte
d7cd794f 5791 && is_mode != wanted_inner_mode)
c6b3f1f2 5792 offset = (GET_MODE_SIZE (is_mode)
d7cd794f 5793 - GET_MODE_SIZE (wanted_inner_mode) - offset);
c6b3f1f2 5794
d7cd794f 5795 if (offset != 0 || inner_mode != wanted_inner_mode)
230d793d 5796 {
38a448ca
RH		 5797 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5798 plus_constant (XEXP (inner, 0), offset));
230d793d 5799 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
c6df88cb 5800 MEM_COPY_ATTRIBUTES (newmem, inner);
230d793d
RS		 5801 inner = newmem;
5802 }
5803 }
5804
9e74dc41
RK		 5805 /* If INNER is not memory, we can always get it into the proper mode. If we
5806 are changing its mode, POS must be a constant and smaller than the size
5807 of the new mode. */
230d793d 5808 else if (GET_CODE (inner) != MEM)
9e74dc41
RK		 5809 {
5810 if (GET_MODE (inner) != wanted_inner_mode
5811 && (pos_rtx != 0
5812 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5813 return 0;
5814
5815 inner = force_to_mode (inner, wanted_inner_mode,
5816 pos_rtx
5817 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5818 ? GET_MODE_MASK (wanted_inner_mode)
5819 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5820 NULL_RTX, 0);
5821 }
230d793d
RS		 5822
5823 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5824 have to zero extend. Otherwise, we can just use a SUBREG. */
8999a12e 5825 if (pos_rtx != 0
230d793d
RS		 5826 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5827 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
8999a12e 5828 else if (pos_rtx != 0
230d793d
RS		 5829 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5830 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5831
8999a12e
RK		 5832 /* Make POS_RTX unless we already have it and it is correct. If we don't
5833 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
0f41302f 5834 be a CONST_INT. */
8999a12e
RK		 5835 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5836 pos_rtx = orig_pos_rtx;
5837
5838 else if (pos_rtx == 0)
5f4f0e22 5839 pos_rtx = GEN_INT (pos);
230d793d
RS		 5840
5841 /* Make the required operation. See if we can use existing rtx. */
5842 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5f4f0e22 5843 extraction_mode, inner, GEN_INT (len), pos_rtx);
230d793d
RS		 5844 if (! in_dest)
5845 new = gen_lowpart_for_combine (mode, new);
5846
5847 return new;
5848}
5849\f
71923da7
RK		 5850/* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5851 with any other operations in X. Return X without that shift if so. */
5852
5853static rtx
5854extract_left_shift (x, count)
5855 rtx x;
5856 int count;
5857{
5858 enum rtx_code code = GET_CODE (x);
5859 enum machine_mode mode = GET_MODE (x);
5860 rtx tem;
5861
5862 switch (code)
5863 {
5864 case ASHIFT:
5865 /* This is the shift itself. If it is wide enough, we will return
5866 either the value being shifted if the shift count is equal to
5867 COUNT or a shift for the difference. */
5868 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5869 && INTVAL (XEXP (x, 1)) >= count)
5870 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5871 INTVAL (XEXP (x, 1)) - count);
5872 break;
5873
5874 case NEG: case NOT:
5875 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
0c1c8ea6 5876 return gen_unary (code, mode, mode, tem);
71923da7
RK		 5877
5878 break;
5879
5880 case PLUS: case IOR: case XOR: case AND:
5881 /* If we can safely shift this constant and we find the inner shift,
5882 make a new operation. */
5883 if (GET_CODE (XEXP (x,1)) == CONST_INT
b729186a 5884 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
71923da7
RK		 5885 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5886 return gen_binary (code, mode, tem,
5887 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5888
5889 break;
e9a25f70
JL		 5890
5891 default:
5892 break;
71923da7
RK		 5893 }
5894
5895 return 0;
5896}
5897\f
230d793d
RS		 5898/* Look at the expression rooted at X. Look for expressions
5899 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5900 Form these expressions.
5901
5902 Return the new rtx, usually just X.
5903
5904 Also, for machines like the Vax that don't have logical shift insns,
5905 try to convert logical to arithmetic shift operations in cases where
5906 they are equivalent. This undoes the canonicalizations to logical
5907 shifts done elsewhere.
5908
5909 We try, as much as possible, to re-use rtl expressions to save memory.
5910
5911 IN_CODE says what kind of expression we are processing. Normally, it is
42495ca0
RK		 5912 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5913 being kludges), it is MEM. When processing the arguments of a comparison
230d793d
RS		 5914 or a COMPARE against zero, it is COMPARE. */
5915
5916static rtx
5917make_compound_operation (x, in_code)
5918 rtx x;
5919 enum rtx_code in_code;
5920{
5921 enum rtx_code code = GET_CODE (x);
5922 enum machine_mode mode = GET_MODE (x);
5923 int mode_width = GET_MODE_BITSIZE (mode);
71923da7 5924 rtx rhs, lhs;
230d793d 5925 enum rtx_code next_code;
f24ad0e4 5926 int i;
230d793d 5927 rtx new = 0;
280f58ba 5928 rtx tem;
6f7d635c 5929 const char *fmt;
230d793d
RS		 5930
5931 /* Select the code to be used in recursive calls. Once we are inside an
5932 address, we stay there. If we have a comparison, set to COMPARE,
5933 but once inside, go back to our default of SET. */
5934
42495ca0 5935 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
230d793d
RS		 5936 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5937 && XEXP (x, 1) == const0_rtx) ? COMPARE
5938 : in_code == COMPARE ? SET : in_code);
5939
5940 /* Process depending on the code of this operation. If NEW is set
5941 non-zero, it will be returned. */
5942
5943 switch (code)
5944 {
5945 case ASHIFT:
230d793d
RS		 5946 /* Convert shifts by constants into multiplications if inside
5947 an address. */
5948 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 5949 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
230d793d 5950 && INTVAL (XEXP (x, 1)) >= 0)
280f58ba
RK		 5951 {
5952 new = make_compound_operation (XEXP (x, 0), next_code);
5953 new = gen_rtx_combine (MULT, mode, new,
5954 GEN_INT ((HOST_WIDE_INT) 1
5955 << INTVAL (XEXP (x, 1))));
5956 }
230d793d
RS		 5957 break;
5958
5959 case AND:
5960 /* If the second operand is not a constant, we can't do anything
5961 with it. */
5962 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5963 break;
5964
5965 /* If the constant is a power of two minus one and the first operand
5966 is a logical right shift, make an extraction. */
5967 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5968 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5969 {
5970 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5971 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5972 0, in_code == COMPARE);
5973 }
dfbe1b2f 5974
230d793d
RS		 5975 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5976 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5977 && subreg_lowpart_p (XEXP (x, 0))
5978 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5979 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5980 {
5981 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5982 next_code);
2f99f437 5983 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
280f58ba
RK		 5984 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5985 0, in_code == COMPARE);
5986 }
45620ed4 5987 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
c2f9f64e
JW		 5988 else if ((GET_CODE (XEXP (x, 0)) == XOR
5989 || GET_CODE (XEXP (x, 0)) == IOR)
5990 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5991 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5992 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5993 {
5994 /* Apply the distributive law, and then try to make extractions. */
5995 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
38a448ca
RH		 5996 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5997 XEXP (x, 1)),
5998 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5999 XEXP (x, 1)));
c2f9f64e
JW		 6000 new = make_compound_operation (new, in_code);
6001 }
a7c99304
RK		 6002
6003 /* If we are have (and (rotate X C) M) and C is larger than the number
6004 of bits in M, this is an extraction. */
6005
6006 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6007 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6008 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6009 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
280f58ba
RK		 6010 {
6011 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6012 new = make_extraction (mode, new,
6013 (GET_MODE_BITSIZE (mode)
6014 - INTVAL (XEXP (XEXP (x, 0), 1))),
6015 NULL_RTX, i, 1, 0, in_code == COMPARE);
6016 }
a7c99304
RK		 6017
6018 /* On machines without logical shifts, if the operand of the AND is
230d793d
RS		 6019 a logical shift and our mask turns off all the propagated sign
6020 bits, we can replace the logical shift with an arithmetic shift. */
d0ab8cd3
RK		 6021 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6022 && (lshr_optab->handlers[(int) mode].insn_code
6023 == CODE_FOR_nothing)
230d793d
RS		 6024 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6025 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6026 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5f4f0e22
CH		 6027 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6028 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 6029 {
5f4f0e22 6030 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 6031
6032 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6033 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6034 SUBST (XEXP (x, 0),
280f58ba
RK		 6035 gen_rtx_combine (ASHIFTRT, mode,
6036 make_compound_operation (XEXP (XEXP (x, 0), 0),
6037 next_code),
230d793d
RS		 6038 XEXP (XEXP (x, 0), 1)));
6039 }
6040
6041 /* If the constant is one less than a power of two, this might be
6042 representable by an extraction even if no shift is present.
6043 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6044 we are in a COMPARE. */
6045 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 6046 new = make_extraction (mode,
6047 make_compound_operation (XEXP (x, 0),
6048 next_code),
6049 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
230d793d
RS		 6050
6051 /* If we are in a comparison and this is an AND with a power of two,
6052 convert this into the appropriate bit extract. */
6053 else if (in_code == COMPARE
6054 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
280f58ba
RK		 6055 new = make_extraction (mode,
6056 make_compound_operation (XEXP (x, 0),
6057 next_code),
6058 i, NULL_RTX, 1, 1, 0, 1);
230d793d
RS		 6059
6060 break;
6061
6062 case LSHIFTRT:
6063 /* If the sign bit is known to be zero, replace this with an
6064 arithmetic shift. */
d0ab8cd3
RK		 6065 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6066 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5f4f0e22 6067 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 6068 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
230d793d 6069 {
280f58ba
RK		 6070 new = gen_rtx_combine (ASHIFTRT, mode,
6071 make_compound_operation (XEXP (x, 0),
6072 next_code),
6073 XEXP (x, 1));
230d793d
RS		 6074 break;
6075 }
6076
0f41302f 6077 /* ... fall through ... */
230d793d
RS		 6078
6079 case ASHIFTRT:
71923da7
RK		 6080 lhs = XEXP (x, 0);
6081 rhs = XEXP (x, 1);
6082
230d793d
RS		 6083 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6084 this is a SIGN_EXTRACT. */
71923da7
RK		 6085 if (GET_CODE (rhs) == CONST_INT
6086 && GET_CODE (lhs) == ASHIFT
6087 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6088 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
280f58ba 6089 {
71923da7 6090 new = make_compound_operation (XEXP (lhs, 0), next_code);
280f58ba 6091 new = make_extraction (mode, new,
71923da7
RK		 6092 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6093 NULL_RTX, mode_width - INTVAL (rhs),
d0ab8cd3
RK		 6094 code == LSHIFTRT, 0, in_code == COMPARE);
6095 }
6096
71923da7
RK		 6097 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6098 If so, try to merge the shifts into a SIGN_EXTEND. We could
6099 also do this for some cases of SIGN_EXTRACT, but it doesn't
6100 seem worth the effort; the case checked for occurs on Alpha. */
6101
6102 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6103 && ! (GET_CODE (lhs) == SUBREG
6104 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6105 && GET_CODE (rhs) == CONST_INT
6106 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6107 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6108 new = make_extraction (mode, make_compound_operation (new, next_code),
6109 0, NULL_RTX, mode_width - INTVAL (rhs),
6110 code == LSHIFTRT, 0, in_code == COMPARE);
6111
230d793d 6112 break;
280f58ba
RK		 6113
6114 case SUBREG:
6115 /* Call ourselves recursively on the inner expression. If we are
6116 narrowing the object and it has a different RTL code from
6117 what it originally did, do this SUBREG as a force_to_mode. */
6118
0a5cbff6 6119 tem = make_compound_operation (SUBREG_REG (x), in_code);
280f58ba
RK		 6120 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6121 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6122 && subreg_lowpart_p (x))
0a5cbff6
RK		 6123 {
6124 rtx newer = force_to_mode (tem, mode,
e3d616e3 6125 GET_MODE_MASK (mode), NULL_RTX, 0);
0a5cbff6
RK		 6126
6127 /* If we have something other than a SUBREG, we might have
6128 done an expansion, so rerun outselves. */
6129 if (GET_CODE (newer) != SUBREG)
6130 newer = make_compound_operation (newer, in_code);
6131
6132 return newer;
6133 }
6f28d3e9
RH		 6134
6135 /* If this is a paradoxical subreg, and the new code is a sign or
6136 zero extension, omit the subreg and widen the extension. If it
6137 is a regular subreg, we can still get rid of the subreg by not
6138 widening so much, or in fact removing the extension entirely. */
6139 if ((GET_CODE (tem) == SIGN_EXTEND
6140 || GET_CODE (tem) == ZERO_EXTEND)
6141 && subreg_lowpart_p (x))
6142 {
6143 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6144 || (GET_MODE_SIZE (mode) >
6145 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6146 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6147 else
6148 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6149 return tem;
6150 }
e9a25f70
JL		 6151 break;
6152
6153 default:
6154 break;
230d793d
RS		 6155 }
6156
6157 if (new)
6158 {
df62f951 6159 x = gen_lowpart_for_combine (mode, new);
230d793d
RS		 6160 code = GET_CODE (x);
6161 }
6162
6163 /* Now recursively process each operand of this operation. */
6164 fmt = GET_RTX_FORMAT (code);
6165 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6166 if (fmt[i] == 'e')
6167 {
6168 new = make_compound_operation (XEXP (x, i), next_code);
6169 SUBST (XEXP (x, i), new);
6170 }
6171
6172 return x;
6173}
6174\f
6175/* Given M see if it is a value that would select a field of bits
6176 within an item, but not the entire word. Return -1 if not.
6177 Otherwise, return the starting position of the field, where 0 is the
6178 low-order bit.
6179
6180 *PLEN is set to the length of the field. */
6181
6182static int
6183get_pos_from_mask (m, plen)
5f4f0e22 6184 unsigned HOST_WIDE_INT m;
230d793d
RS		 6185 int *plen;
6186{
6187 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6188 int pos = exact_log2 (m & - m);
6189
6190 if (pos < 0)
6191 return -1;
6192
6193 /* Now shift off the low-order zero bits and see if we have a power of
6194 two minus 1. */
6195 *plen = exact_log2 ((m >> pos) + 1);
6196
6197 if (*plen <= 0)
6198 return -1;
6199
6200 return pos;
6201}
6202\f
6139ff20
RK		 6203/* See if X can be simplified knowing that we will only refer to it in
6204 MODE and will only refer to those bits that are nonzero in MASK.
6205 If other bits are being computed or if masking operations are done
6206 that select a superset of the bits in MASK, they can sometimes be
6207 ignored.
6208
6209 Return a possibly simplified expression, but always convert X to
6210 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
dfbe1b2f
RK		 6211
6212 Also, if REG is non-zero and X is a register equal in value to REG,
e3d616e3
RK		 6213 replace X with REG.
6214
6215 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6216 are all off in X. This is used when X will be complemented, by either
180b8e4b 6217 NOT, NEG, or XOR. */
dfbe1b2f
RK		 6218
6219static rtx
e3d616e3 6220force_to_mode (x, mode, mask, reg, just_select)
dfbe1b2f
RK		 6221 rtx x;
6222 enum machine_mode mode;
6139ff20 6223 unsigned HOST_WIDE_INT mask;
dfbe1b2f 6224 rtx reg;
e3d616e3 6225 int just_select;
dfbe1b2f
RK		 6226{
6227 enum rtx_code code = GET_CODE (x);
180b8e4b 6228 int next_select = just_select || code == XOR || code == NOT || code == NEG;
ef026f91
RS		 6229 enum machine_mode op_mode;
6230 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6139ff20
RK		 6231 rtx op0, op1, temp;
6232
132d2040
RK		 6233 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6234 code below will do the wrong thing since the mode of such an
be3d27d6
CI		 6235 expression is VOIDmode.
6236
6237 Also do nothing if X is a CLOBBER; this can happen if X was
6238 the return value from a call to gen_lowpart_for_combine. */
6239 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
246e00f2
RK		 6240 return x;
6241
6139ff20
RK		 6242 /* We want to perform the operation is its present mode unless we know
6243 that the operation is valid in MODE, in which case we do the operation
6244 in MODE. */
1c75dfa4
RK		 6245 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6246 && code_to_optab[(int) code] != 0
ef026f91
RS		 6247 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6248 != CODE_FOR_nothing))
6249 ? mode : GET_MODE (x));
e3d616e3 6250
aa988991
RS		 6251 /* It is not valid to do a right-shift in a narrower mode
6252 than the one it came in with. */
6253 if ((code == LSHIFTRT || code == ASHIFTRT)
6254 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6255 op_mode = GET_MODE (x);
ef026f91
RS		 6256
6257 /* Truncate MASK to fit OP_MODE. */
6258 if (op_mode)
6259 mask &= GET_MODE_MASK (op_mode);
6139ff20
RK		 6260
6261 /* When we have an arithmetic operation, or a shift whose count we
6262 do not know, we need to assume that all bit the up to the highest-order
6263 bit in MASK will be needed. This is how we form such a mask. */
ef026f91
RS		 6264 if (op_mode)
6265 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6266 ? GET_MODE_MASK (op_mode)
6267 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6268 else
6269 fuller_mask = ~ (HOST_WIDE_INT) 0;
6270
6271 /* Determine what bits of X are guaranteed to be (non)zero. */
6272 nonzero = nonzero_bits (x, mode);
6139ff20
RK		 6273
6274 /* If none of the bits in X are needed, return a zero. */
e3d616e3 6275 if (! just_select && (nonzero & mask) == 0)
6139ff20 6276 return const0_rtx;
dfbe1b2f 6277
6139ff20
RK		 6278 /* If X is a CONST_INT, return a new one. Do this here since the
6279 test below will fail. */
6280 if (GET_CODE (x) == CONST_INT)
ceb7983c
RK		 6281 {
6282 HOST_WIDE_INT cval = INTVAL (x) & mask;
6283 int width = GET_MODE_BITSIZE (mode);
6284
6285 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6286 number, sign extend it. */
6287 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6288 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6289 cval |= (HOST_WIDE_INT) -1 << width;
6290
6291 return GEN_INT (cval);
6292 }
dfbe1b2f 6293
180b8e4b
RK		 6294 /* If X is narrower than MODE and we want all the bits in X's mode, just
6295 get X in the proper mode. */
6296 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6297 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
dfbe1b2f
RK		 6298 return gen_lowpart_for_combine (mode, x);
6299
71923da7
RK		 6300 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6301 MASK are already known to be zero in X, we need not do anything. */
6302 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6139ff20
RK		 6303 return x;
6304
dfbe1b2f
RK		 6305 switch (code)
6306 {
6139ff20
RK		 6307 case CLOBBER:
6308 /* If X is a (clobber (const_int)), return it since we know we are
0f41302f 6309 generating something that won't match. */
6139ff20
RK		 6310 return x;
6311
6139ff20
RK		 6312 case USE:
6313 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6314 spanned the boundary of the MEM. If we are now masking so it is
6315 within that boundary, we don't need the USE any more. */
f76b9db2
ILT		 6316 if (! BITS_BIG_ENDIAN
6317 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
e3d616e3 6318 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
f76b9db2 6319 break;
6139ff20 6320
dfbe1b2f
RK		 6321 case SIGN_EXTEND:
6322 case ZERO_EXTEND:
6323 case ZERO_EXTRACT:
6324 case SIGN_EXTRACT:
6325 x = expand_compound_operation (x);
6326 if (GET_CODE (x) != code)
e3d616e3 6327 return force_to_mode (x, mode, mask, reg, next_select);
dfbe1b2f
RK		 6328 break;
6329
6330 case REG:
6331 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6332 || rtx_equal_p (reg, get_last_value (x))))
6333 x = reg;
6334 break;
6335
dfbe1b2f 6336 case SUBREG:
6139ff20 6337 if (subreg_lowpart_p (x)
180b8e4b
RK		 6338 /* We can ignore the effect of this SUBREG if it narrows the mode or
6339 if the constant masks to zero all the bits the mode doesn't
6340 have. */
6139ff20
RK		 6341 && ((GET_MODE_SIZE (GET_MODE (x))
6342 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6139ff20
RK		 6343 || (0 == (mask
6344 & GET_MODE_MASK (GET_MODE (x))
180b8e4b 6345 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
e3d616e3 6346 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
dfbe1b2f
RK		 6347 break;
6348
6349 case AND:
6139ff20
RK		 6350 /* If this is an AND with a constant, convert it into an AND
6351 whose constant is the AND of that constant with MASK. If it
6352 remains an AND of MASK, delete it since it is redundant. */
dfbe1b2f 6353
2ca9ae17 6354 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
dfbe1b2f 6355 {
6139ff20
RK		 6356 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6357 mask & INTVAL (XEXP (x, 1)));
dfbe1b2f
RK		 6358
6359 /* If X is still an AND, see if it is an AND with a mask that
71923da7
RK		 6360 is just some low-order bits. If so, and it is MASK, we don't
6361 need it. */
dfbe1b2f
RK		 6362
6363 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
e51712db 6364 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
dfbe1b2f 6365 x = XEXP (x, 0);
d0ab8cd3 6366
71923da7
RK		 6367 /* If it remains an AND, try making another AND with the bits
6368 in the mode mask that aren't in MASK turned on. If the
6369 constant in the AND is wide enough, this might make a
6370 cheaper constant. */
6371
6372 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
2ca9ae17
JW		 6373 && GET_MODE_MASK (GET_MODE (x)) != mask
6374 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
71923da7
RK		 6375 {
6376 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6377 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6378 int width = GET_MODE_BITSIZE (GET_MODE (x));
6379 rtx y;
6380
6381 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6382 number, sign extend it. */
6383 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6384 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6385 cval |= (HOST_WIDE_INT) -1 << width;
6386
6387 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6388 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6389 x = y;
6390 }
6391
d0ab8cd3 6392 break;
dfbe1b2f
RK		 6393 }
6394
6139ff20 6395 goto binop;
dfbe1b2f
RK		 6396
6397 case PLUS:
6139ff20
RK		 6398 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6399 low-order bits (as in an alignment operation) and FOO is already
6400 aligned to that boundary, mask C1 to that boundary as well.
6401 This may eliminate that PLUS and, later, the AND. */
9fa6d012
TG		 6402
6403 {
6404 int width = GET_MODE_BITSIZE (mode);
6405 unsigned HOST_WIDE_INT smask = mask;
6406
6407 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6408 number, sign extend it. */
6409
6410 if (width < HOST_BITS_PER_WIDE_INT
6411 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6412 smask |= (HOST_WIDE_INT) -1 << width;
6413
6414 if (GET_CODE (XEXP (x, 1)) == CONST_INT
0e9ff885
DM		 6415 && exact_log2 (- smask) >= 0)
6416 {
6417#ifdef STACK_BIAS
6418 if (STACK_BIAS
6419 && (XEXP (x, 0) == stack_pointer_rtx
6420 || XEXP (x, 0) == frame_pointer_rtx))
6421 {
6422 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6423 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6424
6425 sp_mask &= ~ (sp_alignment - 1);
835c8e04
DT		 6426 if ((sp_mask & ~ smask) == 0
6427 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
0e9ff885
DM		 6428 return force_to_mode (plus_constant (XEXP (x, 0),
6429 ((INTVAL (XEXP (x, 1)) -
835c8e04 6430 STACK_BIAS) & smask)
0e9ff885 6431 + STACK_BIAS),
835c8e04 6432 mode, smask, reg, next_select);
0e9ff885
DM		 6433 }
6434#endif
835c8e04
DT		 6435 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6436 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
0e9ff885 6437 return force_to_mode (plus_constant (XEXP (x, 0),
835c8e04
DT		 6438 (INTVAL (XEXP (x, 1))
6439 & smask)),
6440 mode, smask, reg, next_select);
0e9ff885 6441 }
9fa6d012 6442 }
6139ff20 6443
0f41302f 6444 /* ... fall through ... */
6139ff20 6445
dfbe1b2f
RK		 6446 case MINUS:
6447 case MULT:
6139ff20
RK		 6448 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6449 most significant bit in MASK since carries from those bits will
6450 affect the bits we are interested in. */
6451 mask = fuller_mask;
6452 goto binop;
6453
dfbe1b2f
RK		 6454 case IOR:
6455 case XOR:
6139ff20
RK		 6456 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6457 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6458 operation which may be a bitfield extraction. Ensure that the
6459 constant we form is not wider than the mode of X. */
6460
6461 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6462 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6463 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6464 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6465 && GET_CODE (XEXP (x, 1)) == CONST_INT
6466 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6467 + floor_log2 (INTVAL (XEXP (x, 1))))
6468 < GET_MODE_BITSIZE (GET_MODE (x)))
6469 && (INTVAL (XEXP (x, 1))
01c82bbb 6470 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6139ff20
RK		 6471 {
6472 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6473 << INTVAL (XEXP (XEXP (x, 0), 1)));
6474 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6475 XEXP (XEXP (x, 0), 0), temp);
d4d2b13f
RK		 6476 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6477 XEXP (XEXP (x, 0), 1));
e3d616e3 6478 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6479 }
6480
6481 binop:
dfbe1b2f 6482 /* For most binary operations, just propagate into the operation and
6139ff20
RK		 6483 change the mode if we have an operation of that mode. */
6484
e3d616e3
RK		 6485 op0 = gen_lowpart_for_combine (op_mode,
6486 force_to_mode (XEXP (x, 0), mode, mask,
6487 reg, next_select));
6488 op1 = gen_lowpart_for_combine (op_mode,
6489 force_to_mode (XEXP (x, 1), mode, mask,
6490 reg, next_select));
6139ff20 6491
2dd484ed
RK		 6492 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6493 MASK since OP1 might have been sign-extended but we never want
6494 to turn on extra bits, since combine might have previously relied
6495 on them being off. */
6496 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6497 && (INTVAL (op1) & mask) != 0)
6498 op1 = GEN_INT (INTVAL (op1) & mask);
6499
6139ff20
RK		 6500 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6501 x = gen_binary (code, op_mode, op0, op1);
d0ab8cd3 6502 break;
dfbe1b2f
RK		 6503
6504 case ASHIFT:
dfbe1b2f 6505 /* For left shifts, do the same, but just for the first operand.
f6785026
RK		 6506 However, we cannot do anything with shifts where we cannot
6507 guarantee that the counts are smaller than the size of the mode
6508 because such a count will have a different meaning in a
6139ff20 6509 wider mode. */
f6785026
RK		 6510
6511 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6512 && INTVAL (XEXP (x, 1)) >= 0
f6785026
RK		 6513 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6514 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6515 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
adb7a1cb 6516 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
f6785026
RK		 6517 break;
6518
6139ff20
RK		 6519 /* If the shift count is a constant and we can do arithmetic in
6520 the mode of the shift, refine which bits we need. Otherwise, use the
6521 conservative form of the mask. */
6522 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6523 && INTVAL (XEXP (x, 1)) >= 0
6524 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6525 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6526 mask >>= INTVAL (XEXP (x, 1));
6527 else
6528 mask = fuller_mask;
6529
6530 op0 = gen_lowpart_for_combine (op_mode,
6531 force_to_mode (XEXP (x, 0), op_mode,
e3d616e3 6532 mask, reg, next_select));
6139ff20
RK		 6533
6534 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6535 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
d0ab8cd3 6536 break;
dfbe1b2f
RK		 6537
6538 case LSHIFTRT:
1347292b
JW		 6539 /* Here we can only do something if the shift count is a constant,
6540 this shift constant is valid for the host, and we can do arithmetic
6541 in OP_MODE. */
dfbe1b2f
RK		 6542
6543 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1347292b 6544 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6139ff20 6545 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 6546 {
6139ff20
RK		 6547 rtx inner = XEXP (x, 0);
6548
6549 /* Select the mask of the bits we need for the shift operand. */
6550 mask <<= INTVAL (XEXP (x, 1));
d0ab8cd3 6551
6139ff20
RK		 6552 /* We can only change the mode of the shift if we can do arithmetic
6553 in the mode of the shift and MASK is no wider than the width of
6554 OP_MODE. */
6555 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6556 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
d0ab8cd3
RK		 6557 op_mode = GET_MODE (x);
6558
e3d616e3 6559 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6139ff20
RK		 6560
6561 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6562 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
d0ab8cd3 6563 }
6139ff20
RK		 6564
6565 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6566 shift and AND produces only copies of the sign bit (C2 is one less
6567 than a power of two), we can do this with just a shift. */
6568
6569 if (GET_CODE (x) == LSHIFTRT
6570 && GET_CODE (XEXP (x, 1)) == CONST_INT
6571 && ((INTVAL (XEXP (x, 1))
6572 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6573 >= GET_MODE_BITSIZE (GET_MODE (x)))
6574 && exact_log2 (mask + 1) >= 0
6575 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6576 >= exact_log2 (mask + 1)))
6577 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6578 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6579 - exact_log2 (mask + 1)));
fae2db47
JW		 6580
6581 goto shiftrt;
d0ab8cd3
RK		 6582
6583 case ASHIFTRT:
6139ff20
RK		 6584 /* If we are just looking for the sign bit, we don't need this shift at
6585 all, even if it has a variable count. */
9bf22b75 6586 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
e51712db 6587 && (mask == ((unsigned HOST_WIDE_INT) 1
9bf22b75 6588 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
e3d616e3 6589 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20
RK		 6590
6591 /* If this is a shift by a constant, get a mask that contains those bits
6592 that are not copies of the sign bit. We then have two cases: If
6593 MASK only includes those bits, this can be a logical shift, which may
6594 allow simplifications. If MASK is a single-bit field not within
6595 those bits, we are requesting a copy of the sign bit and hence can
6596 shift the sign bit to the appropriate location. */
6597
6598 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6599 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6600 {
6601 int i = -1;
6602
b69960ac
RK		 6603 /* If the considered data is wider then HOST_WIDE_INT, we can't
6604 represent a mask for all its bits in a single scalar.
6605 But we only care about the lower bits, so calculate these. */
6606
6a11342f 6607 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
b69960ac 6608 {
0f41302f 6609 nonzero = ~ (HOST_WIDE_INT) 0;
b69960ac
RK		 6610
6611 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6612 is the number of bits a full-width mask would have set.
6613 We need only shift if these are fewer than nonzero can
6614 hold. If not, we must keep all bits set in nonzero. */
6615
6616 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6617 < HOST_BITS_PER_WIDE_INT)
6618 nonzero >>= INTVAL (XEXP (x, 1))
6619 + HOST_BITS_PER_WIDE_INT
6620 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6621 }
6622 else
6623 {
6624 nonzero = GET_MODE_MASK (GET_MODE (x));
6625 nonzero >>= INTVAL (XEXP (x, 1));
6626 }
6139ff20
RK		 6627
6628 if ((mask & ~ nonzero) == 0
6629 || (i = exact_log2 (mask)) >= 0)
6630 {
6631 x = simplify_shift_const
6632 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6633 i < 0 ? INTVAL (XEXP (x, 1))
6634 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6635
6636 if (GET_CODE (x) != ASHIFTRT)
e3d616e3 6637 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6638 }
6639 }
6640
6641 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6642 even if the shift count isn't a constant. */
6643 if (mask == 1)
6644 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6645
fae2db47
JW		 6646 shiftrt:
6647
6648 /* If this is a zero- or sign-extension operation that just affects bits
4c002f29
RK		 6649 we don't care about, remove it. Be sure the call above returned
6650 something that is still a shift. */
d0ab8cd3 6651
4c002f29
RK		 6652 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6653 && GET_CODE (XEXP (x, 1)) == CONST_INT
d0ab8cd3 6654 && INTVAL (XEXP (x, 1)) >= 0
6139ff20
RK		 6655 && (INTVAL (XEXP (x, 1))
6656 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
d0ab8cd3
RK		 6657 && GET_CODE (XEXP (x, 0)) == ASHIFT
6658 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6659 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
e3d616e3
RK		 6660 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6661 reg, next_select);
6139ff20 6662
dfbe1b2f
RK		 6663 break;
6664
6139ff20
RK		 6665 case ROTATE:
6666 case ROTATERT:
6667 /* If the shift count is constant and we can do computations
6668 in the mode of X, compute where the bits we care about are.
6669 Otherwise, we can't do anything. Don't change the mode of
6670 the shift or propagate MODE into the shift, though. */
6671 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6672 && INTVAL (XEXP (x, 1)) >= 0)
6673 {
6674 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6675 GET_MODE (x), GEN_INT (mask),
6676 XEXP (x, 1));
7d171a1e 6677 if (temp && GET_CODE(temp) == CONST_INT)
6139ff20
RK		 6678 SUBST (XEXP (x, 0),
6679 force_to_mode (XEXP (x, 0), GET_MODE (x),
e3d616e3 6680 INTVAL (temp), reg, next_select));
6139ff20
RK		 6681 }
6682 break;
6683
dfbe1b2f 6684 case NEG:
180b8e4b
RK		 6685 /* If we just want the low-order bit, the NEG isn't needed since it
6686 won't change the low-order bit. */
6687 if (mask == 1)
6688 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6689
6139ff20
RK		 6690 /* We need any bits less significant than the most significant bit in
6691 MASK since carries from those bits will affect the bits we are
6692 interested in. */
6693 mask = fuller_mask;
6694 goto unop;
6695
dfbe1b2f 6696 case NOT:
6139ff20
RK		 6697 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6698 same as the XOR case above. Ensure that the constant we form is not
6699 wider than the mode of X. */
6700
6701 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6702 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6703 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6704 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6705 < GET_MODE_BITSIZE (GET_MODE (x)))
6706 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6707 {
6708 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6709 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6710 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6711
e3d616e3 6712 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6713 }
6714
f82da7d2
JW		 6715 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6716 use the full mask inside the NOT. */
6717 mask = fuller_mask;
6718
6139ff20 6719 unop:
e3d616e3
RK		 6720 op0 = gen_lowpart_for_combine (op_mode,
6721 force_to_mode (XEXP (x, 0), mode, mask,
6722 reg, next_select));
6139ff20 6723 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
0c1c8ea6 6724 x = gen_unary (code, op_mode, op_mode, op0);
6139ff20
RK		 6725 break;
6726
6727 case NE:
6728 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
3aceff0d 6729 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
1a6ec070 6730 which is equal to STORE_FLAG_VALUE. */
3aceff0d
RK		 6731 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6732 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
1a6ec070 6733 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
e3d616e3 6734 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20 6735
d0ab8cd3
RK		 6736 break;
6737
6738 case IF_THEN_ELSE:
6739 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6740 written in a narrower mode. We play it safe and do not do so. */
6741
6742 SUBST (XEXP (x, 1),
6743 gen_lowpart_for_combine (GET_MODE (x),
6744 force_to_mode (XEXP (x, 1), mode,
e3d616e3 6745 mask, reg, next_select)));
d0ab8cd3
RK		 6746 SUBST (XEXP (x, 2),
6747 gen_lowpart_for_combine (GET_MODE (x),
6748 force_to_mode (XEXP (x, 2), mode,
e3d616e3 6749 mask, reg,next_select)));
d0ab8cd3 6750 break;
e9a25f70
JL		 6751
6752 default:
6753 break;
dfbe1b2f
RK		 6754 }
6755
d0ab8cd3 6756 /* Ensure we return a value of the proper mode. */
dfbe1b2f
RK		 6757 return gen_lowpart_for_combine (mode, x);
6758}
6759\f
abe6e52f
RK		 6760/* Return nonzero if X is an expression that has one of two values depending on
6761 whether some other value is zero or nonzero. In that case, we return the
6762 value that is being tested, *PTRUE is set to the value if the rtx being
6763 returned has a nonzero value, and *PFALSE is set to the other alternative.
6764
6765 If we return zero, we set *PTRUE and *PFALSE to X. */
6766
6767static rtx
6768if_then_else_cond (x, ptrue, pfalse)
6769 rtx x;
6770 rtx *ptrue, *pfalse;
6771{
6772 enum machine_mode mode = GET_MODE (x);
6773 enum rtx_code code = GET_CODE (x);
6774 int size = GET_MODE_BITSIZE (mode);
6775 rtx cond0, cond1, true0, true1, false0, false1;
6776 unsigned HOST_WIDE_INT nz;
6777
6778 /* If this is a unary operation whose operand has one of two values, apply
6779 our opcode to compute those values. */
6780 if (GET_RTX_CLASS (code) == '1'
6781 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6782 {
0c1c8ea6
RK		 6783 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6784 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
abe6e52f
RK		 6785 return cond0;
6786 }
6787
3a19aabc 6788 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
ddd5a7c1 6789 make can't possibly match and would suppress other optimizations. */
3a19aabc
RK		 6790 else if (code == COMPARE)
6791 ;
6792
abe6e52f
RK		 6793 /* If this is a binary operation, see if either side has only one of two
6794 values. If either one does or if both do and they are conditional on
6795 the same value, compute the new true and false values. */
6796 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6797 || GET_RTX_CLASS (code) == '<')
6798 {
6799 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6800 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6801
6802 if ((cond0 != 0 || cond1 != 0)
6803 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6804 {
987e845a
JW		 6805 /* If if_then_else_cond returned zero, then true/false are the
6806 same rtl. We must copy one of them to prevent invalid rtl
6807 sharing. */
6808 if (cond0 == 0)
6809 true0 = copy_rtx (true0);
6810 else if (cond1 == 0)
6811 true1 = copy_rtx (true1);
6812
abe6e52f
RK		 6813 *ptrue = gen_binary (code, mode, true0, true1);
6814 *pfalse = gen_binary (code, mode, false0, false1);
6815 return cond0 ? cond0 : cond1;
6816 }
9210df58 6817
9210df58 6818 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
0802d516
RK		 6819 operands is zero when the other is non-zero, and vice-versa,
6820 and STORE_FLAG_VALUE is 1 or -1. */
9210df58 6821
0802d516
RK		 6822 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6823 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9210df58
RK		 6824 || code == UMAX)
6825 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6826 {
6827 rtx op0 = XEXP (XEXP (x, 0), 1);
6828 rtx op1 = XEXP (XEXP (x, 1), 1);
6829
6830 cond0 = XEXP (XEXP (x, 0), 0);
6831 cond1 = XEXP (XEXP (x, 1), 0);
6832
6833 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6834 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6835 && reversible_comparison_p (cond1)
6836 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6837 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6838 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6839 || ((swap_condition (GET_CODE (cond0))
6840 == reverse_condition (GET_CODE (cond1)))
6841 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6842 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6843 && ! side_effects_p (x))
6844 {
6845 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6846 *pfalse = gen_binary (MULT, mode,
6847 (code == MINUS
0c1c8ea6 6848 ? gen_unary (NEG, mode, mode, op1) : op1),
9210df58
RK		 6849 const_true_rtx);
6850 return cond0;
6851 }
6852 }
6853
6854 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6855 is always zero. */
0802d516
RK		 6856 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6857 && (code == MULT || code == AND || code == UMIN)
9210df58
RK		 6858 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6859 {
6860 cond0 = XEXP (XEXP (x, 0), 0);
6861 cond1 = XEXP (XEXP (x, 1), 0);
6862
6863 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6864 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6865 && reversible_comparison_p (cond1)
6866 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6867 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6868 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6869 || ((swap_condition (GET_CODE (cond0))
6870 == reverse_condition (GET_CODE (cond1)))
6871 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6872 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6873 && ! side_effects_p (x))
6874 {
6875 *ptrue = *pfalse = const0_rtx;
6876 return cond0;
6877 }
6878 }
abe6e52f
RK		 6879 }
6880
6881 else if (code == IF_THEN_ELSE)
6882 {
6883 /* If we have IF_THEN_ELSE already, extract the condition and
6884 canonicalize it if it is NE or EQ. */
6885 cond0 = XEXP (x, 0);
6886 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6887 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6888 return XEXP (cond0, 0);
6889 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6890 {
6891 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6892 return XEXP (cond0, 0);
6893 }
6894 else
6895 return cond0;
6896 }
6897
6898 /* If X is a normal SUBREG with both inner and outer modes integral,
6899 we can narrow both the true and false values of the inner expression,
6900 if there is a condition. */
6901 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6902 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6903 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6904 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6905 &true0, &false0)))
6906 {
00244e6b
RK		 6907 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6908 *pfalse
6909 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
abe6e52f 6910
abe6e52f
RK		 6911 return cond0;
6912 }
6913
6914 /* If X is a constant, this isn't special and will cause confusions
6915 if we treat it as such. Likewise if it is equivalent to a constant. */
6916 else if (CONSTANT_P (x)
6917 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6918 ;
6919
6920 /* If X is known to be either 0 or -1, those are the true and
6921 false values when testing X. */
6922 else if (num_sign_bit_copies (x, mode) == size)
6923 {
6924 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6925 return x;
6926 }
6927
6928 /* Likewise for 0 or a single bit. */
6929 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6930 {
6931 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6932 return x;
6933 }
6934
6935 /* Otherwise fail; show no condition with true and false values the same. */
6936 *ptrue = *pfalse = x;
6937 return 0;
6938}
6939\f
1a26b032
RK		 6940/* Return the value of expression X given the fact that condition COND
6941 is known to be true when applied to REG as its first operand and VAL
6942 as its second. X is known to not be shared and so can be modified in
6943 place.
6944
6945 We only handle the simplest cases, and specifically those cases that
6946 arise with IF_THEN_ELSE expressions. */
6947
6948static rtx
6949known_cond (x, cond, reg, val)
6950 rtx x;
6951 enum rtx_code cond;
6952 rtx reg, val;
6953{
6954 enum rtx_code code = GET_CODE (x);
f24ad0e4 6955 rtx temp;
6f7d635c 6956 const char *fmt;
1a26b032
RK		 6957 int i, j;
6958
6959 if (side_effects_p (x))
6960 return x;
6961
6962 if (cond == EQ && rtx_equal_p (x, reg))
6963 return val;
6964
6965 /* If X is (abs REG) and we know something about REG's relationship
6966 with zero, we may be able to simplify this. */
6967
6968 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6969 switch (cond)
6970 {
6971 case GE: case GT: case EQ:
6972 return XEXP (x, 0);
6973 case LT: case LE:
0c1c8ea6
RK		 6974 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6975 XEXP (x, 0));
e9a25f70
JL		 6976 default:
6977 break;
1a26b032
RK		 6978 }
6979
6980 /* The only other cases we handle are MIN, MAX, and comparisons if the
6981 operands are the same as REG and VAL. */
6982
6983 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6984 {
6985 if (rtx_equal_p (XEXP (x, 0), val))
6986 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6987
6988 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6989 {
6990 if (GET_RTX_CLASS (code) == '<')
6991 return (comparison_dominates_p (cond, code) ? const_true_rtx
6992 : (comparison_dominates_p (cond,
6993 reverse_condition (code))
6994 ? const0_rtx : x));
6995
6996 else if (code == SMAX || code == SMIN
6997 || code == UMIN || code == UMAX)
6998 {
6999 int unsignedp = (code == UMIN || code == UMAX);
7000
7001 if (code == SMAX || code == UMAX)
7002 cond = reverse_condition (cond);
7003
7004 switch (cond)
7005 {
7006 case GE: case GT:
7007 return unsignedp ? x : XEXP (x, 1);
7008 case LE: case LT:
7009 return unsignedp ? x : XEXP (x, 0);
7010 case GEU: case GTU:
7011 return unsignedp ? XEXP (x, 1) : x;
7012 case LEU: case LTU:
7013 return unsignedp ? XEXP (x, 0) : x;
e9a25f70
JL		 7014 default:
7015 break;
1a26b032
RK		 7016 }
7017 }
7018 }
7019 }
7020
7021 fmt = GET_RTX_FORMAT (code);
7022 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7023 {
7024 if (fmt[i] == 'e')
7025 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7026 else if (fmt[i] == 'E')
7027 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7028 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7029 cond, reg, val));
7030 }
7031
7032 return x;
7033}
7034\f
e11fa86f
RK		 7035/* See if X and Y are equal for the purposes of seeing if we can rewrite an
7036 assignment as a field assignment. */
7037
7038static int
7039rtx_equal_for_field_assignment_p (x, y)
7040 rtx x;
7041 rtx y;
7042{
e11fa86f
RK		 7043 if (x == y || rtx_equal_p (x, y))
7044 return 1;
7045
7046 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7047 return 0;
7048
7049 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7050 Note that all SUBREGs of MEM are paradoxical; otherwise they
7051 would have been rewritten. */
7052 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7053 && GET_CODE (SUBREG_REG (y)) == MEM
7054 && rtx_equal_p (SUBREG_REG (y),
7055 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7056 return 1;
7057
7058 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7059 && GET_CODE (SUBREG_REG (x)) == MEM
7060 && rtx_equal_p (SUBREG_REG (x),
7061 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7062 return 1;
7063
9ec36da5
JL		 7064 /* We used to see if get_last_value of X and Y were the same but that's
7065 not correct. In one direction, we'll cause the assignment to have
7066 the wrong destination and in the case, we'll import a register into this
7067 insn that might have already have been dead. So fail if none of the
7068 above cases are true. */
7069 return 0;
e11fa86f
RK		 7070}
7071\f
230d793d
RS		 7072/* See if X, a SET operation, can be rewritten as a bit-field assignment.
7073 Return that assignment if so.
7074
7075 We only handle the most common cases. */
7076
7077static rtx
7078make_field_assignment (x)
7079 rtx x;
7080{
7081 rtx dest = SET_DEST (x);
7082 rtx src = SET_SRC (x);
dfbe1b2f 7083 rtx assign;
e11fa86f 7084 rtx rhs, lhs;
5f4f0e22
CH		 7085 HOST_WIDE_INT c1;
7086 int pos, len;
dfbe1b2f
RK		 7087 rtx other;
7088 enum machine_mode mode;
230d793d
RS		 7089
7090 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7091 a clear of a one-bit field. We will have changed it to
7092 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7093 for a SUBREG. */
7094
7095 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7096 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7097 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
e11fa86f 7098 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7099 {
8999a12e 7100 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7101 1, 1, 1, 0);
76184def 7102 if (assign != 0)
38a448ca 7103 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7104 return x;
230d793d
RS		 7105 }
7106
7107 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7108 && subreg_lowpart_p (XEXP (src, 0))
7109 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7110 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7111 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7112 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
e11fa86f 7113 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7114 {
8999a12e 7115 assign = make_extraction (VOIDmode, dest, 0,
230d793d
RS		 7116 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7117 1, 1, 1, 0);
76184def 7118 if (assign != 0)
38a448ca 7119 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7120 return x;
230d793d
RS		 7121 }
7122
9dd11dcb 7123 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
230d793d
RS		 7124 one-bit field. */
7125 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7126 && XEXP (XEXP (src, 0), 0) == const1_rtx
e11fa86f 7127 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7128 {
8999a12e 7129 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7130 1, 1, 1, 0);
76184def 7131 if (assign != 0)
38a448ca 7132 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
76184def 7133 return x;
230d793d
RS		 7134 }
7135
dfbe1b2f 7136 /* The other case we handle is assignments into a constant-position
9dd11dcb 7137 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
dfbe1b2f
RK		 7138 a mask that has all one bits except for a group of zero bits and
7139 OTHER is known to have zeros where C1 has ones, this is such an
7140 assignment. Compute the position and length from C1. Shift OTHER
7141 to the appropriate position, force it to the required mode, and
7142 make the extraction. Check for the AND in both operands. */
7143
9dd11dcb 7144 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
e11fa86f
RK		 7145 return x;
7146
7147 rhs = expand_compound_operation (XEXP (src, 0));
7148 lhs = expand_compound_operation (XEXP (src, 1));
7149
7150 if (GET_CODE (rhs) == AND
7151 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7152 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7153 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7154 else if (GET_CODE (lhs) == AND
7155 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7156 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7157 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
dfbe1b2f
RK		 7158 else
7159 return x;
230d793d 7160
e11fa86f 7161 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
dfbe1b2f 7162 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
e5e809f4
JL		 7163 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7164 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
dfbe1b2f 7165 return x;
230d793d 7166
5f4f0e22 7167 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
76184def
DE		 7168 if (assign == 0)
7169 return x;
230d793d 7170
dfbe1b2f
RK		 7171 /* The mode to use for the source is the mode of the assignment, or of
7172 what is inside a possible STRICT_LOW_PART. */
7173 mode = (GET_CODE (assign) == STRICT_LOW_PART
7174 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
230d793d 7175
dfbe1b2f
RK		 7176 /* Shift OTHER right POS places and make it the source, restricting it
7177 to the proper length and mode. */
230d793d 7178
5f4f0e22
CH		 7179 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7180 GET_MODE (src), other, pos),
6139ff20
RK		 7181 mode,
7182 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7183 ? GET_MODE_MASK (mode)
7184 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 7185 dest, 0);
230d793d 7186
dfbe1b2f 7187 return gen_rtx_combine (SET, VOIDmode, assign, src);
230d793d
RS		 7188}
7189\f
7190/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7191 if so. */
7192
7193static rtx
7194apply_distributive_law (x)
7195 rtx x;
7196{
7197 enum rtx_code code = GET_CODE (x);
7198 rtx lhs, rhs, other;
7199 rtx tem;
7200 enum rtx_code inner_code;
7201
d8a8a4da
RS		 7202 /* Distributivity is not true for floating point.
7203 It can change the value. So don't do it.
7204 -- rms and moshier@world.std.com. */
3ad2180a 7205 if (FLOAT_MODE_P (GET_MODE (x)))
d8a8a4da
RS		 7206 return x;
7207
230d793d
RS		 7208 /* The outer operation can only be one of the following: */
7209 if (code != IOR && code != AND && code != XOR
7210 && code != PLUS && code != MINUS)
7211 return x;
7212
7213 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7214
0f41302f
MS		 7215 /* If either operand is a primitive we can't do anything, so get out
7216 fast. */
230d793d 7217 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
dfbe1b2f 7218 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
230d793d
RS		 7219 return x;
7220
7221 lhs = expand_compound_operation (lhs);
7222 rhs = expand_compound_operation (rhs);
7223 inner_code = GET_CODE (lhs);
7224 if (inner_code != GET_CODE (rhs))
7225 return x;
7226
7227 /* See if the inner and outer operations distribute. */
7228 switch (inner_code)
7229 {
7230 case LSHIFTRT:
7231 case ASHIFTRT:
7232 case AND:
7233 case IOR:
7234 /* These all distribute except over PLUS. */
7235 if (code == PLUS || code == MINUS)
7236 return x;
7237 break;
7238
7239 case MULT:
7240 if (code != PLUS && code != MINUS)
7241 return x;
7242 break;
7243
7244 case ASHIFT:
45620ed4 7245 /* This is also a multiply, so it distributes over everything. */
230d793d
RS		 7246 break;
7247
7248 case SUBREG:
dfbe1b2f
RK		 7249 /* Non-paradoxical SUBREGs distributes over all operations, provided
7250 the inner modes and word numbers are the same, this is an extraction
2b4bd1bc
JW		 7251 of a low-order part, we don't convert an fp operation to int or
7252 vice versa, and we would not be converting a single-word
dfbe1b2f 7253 operation into a multi-word operation. The latter test is not
2b4bd1bc 7254 required, but it prevents generating unneeded multi-word operations.
dfbe1b2f
RK		 7255 Some of the previous tests are redundant given the latter test, but
7256 are retained because they are required for correctness.
7257
7258 We produce the result slightly differently in this case. */
7259
7260 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7261 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7262 || ! subreg_lowpart_p (lhs)
2b4bd1bc
JW		 7263 || (GET_MODE_CLASS (GET_MODE (lhs))
7264 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7265 || (GET_MODE_SIZE (GET_MODE (lhs))
8af24e26 7266 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7267 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
230d793d
RS		 7268 return x;
7269
7270 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7271 SUBREG_REG (lhs), SUBREG_REG (rhs));
7272 return gen_lowpart_for_combine (GET_MODE (x), tem);
7273
7274 default:
7275 return x;
7276 }
7277
7278 /* Set LHS and RHS to the inner operands (A and B in the example
7279 above) and set OTHER to the common operand (C in the example).
7280 These is only one way to do this unless the inner operation is
7281 commutative. */
7282 if (GET_RTX_CLASS (inner_code) == 'c'
7283 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7284 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7285 else if (GET_RTX_CLASS (inner_code) == 'c'
7286 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7287 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7288 else if (GET_RTX_CLASS (inner_code) == 'c'
7289 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7290 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7291 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7292 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7293 else
7294 return x;
7295
7296 /* Form the new inner operation, seeing if it simplifies first. */
7297 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7298
7299 /* There is one exception to the general way of distributing:
7300 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7301 if (code == XOR && inner_code == IOR)
7302 {
7303 inner_code = AND;
0c1c8ea6 7304 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
230d793d
RS		 7305 }
7306
7307 /* We may be able to continuing distributing the result, so call
7308 ourselves recursively on the inner operation before forming the
7309 outer operation, which we return. */
7310 return gen_binary (inner_code, GET_MODE (x),
7311 apply_distributive_law (tem), other);
7312}
7313\f
7314/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7315 in MODE.
7316
7317 Return an equivalent form, if different from X. Otherwise, return X. If
7318 X is zero, we are to always construct the equivalent form. */
7319
7320static rtx
7321simplify_and_const_int (x, mode, varop, constop)
7322 rtx x;
7323 enum machine_mode mode;
7324 rtx varop;
5f4f0e22 7325 unsigned HOST_WIDE_INT constop;
230d793d 7326{
951553af 7327 unsigned HOST_WIDE_INT nonzero;
42301240 7328 int i;
230d793d 7329
6139ff20
RK		 7330 /* Simplify VAROP knowing that we will be only looking at some of the
7331 bits in it. */
e3d616e3 7332 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
230d793d 7333
6139ff20
RK		 7334 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7335 CONST_INT, we are done. */
7336 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7337 return varop;
230d793d 7338
fc06d7aa
RK		 7339 /* See what bits may be nonzero in VAROP. Unlike the general case of
7340 a call to nonzero_bits, here we don't care about bits outside
7341 MODE. */
7342
7343 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7e4ce834 7344 nonzero = trunc_int_for_mode (nonzero, mode);
9fa6d012 7345
230d793d 7346 /* Turn off all bits in the constant that are known to already be zero.
951553af 7347 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
230d793d
RS		 7348 which is tested below. */
7349
951553af 7350 constop &= nonzero;
230d793d
RS		 7351
7352 /* If we don't have any bits left, return zero. */
7353 if (constop == 0)
7354 return const0_rtx;
7355
42301240
RK		 7356 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7357 a power of two, we can replace this with a ASHIFT. */
7358 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7359 && (i = exact_log2 (constop)) >= 0)
7360 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7361
6139ff20
RK		 7362 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7363 or XOR, then try to apply the distributive law. This may eliminate
7364 operations if either branch can be simplified because of the AND.
7365 It may also make some cases more complex, but those cases probably
7366 won't match a pattern either with or without this. */
7367
7368 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7369 return
7370 gen_lowpart_for_combine
7371 (mode,
7372 apply_distributive_law
7373 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7374 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7375 XEXP (varop, 0), constop),
7376 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7377 XEXP (varop, 1), constop))));
7378
230d793d
RS		 7379 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7380 if we already had one (just check for the simplest cases). */
7381 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7382 && GET_MODE (XEXP (x, 0)) == mode
7383 && SUBREG_REG (XEXP (x, 0)) == varop)
7384 varop = XEXP (x, 0);
7385 else
7386 varop = gen_lowpart_for_combine (mode, varop);
7387
0f41302f 7388 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 7389 if (GET_CODE (varop) == CLOBBER)
7390 return x ? x : varop;
7391
7392 /* If we are only masking insignificant bits, return VAROP. */
951553af 7393 if (constop == nonzero)
230d793d
RS		 7394 x = varop;
7395
7396 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7397 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6139ff20 7398 x = gen_binary (AND, mode, varop, GEN_INT (constop));
230d793d
RS		 7399
7400 else
7401 {
7402 if (GET_CODE (XEXP (x, 1)) != CONST_INT
e51712db 7403 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
5f4f0e22 7404 SUBST (XEXP (x, 1), GEN_INT (constop));
230d793d
RS		 7405
7406 SUBST (XEXP (x, 0), varop);
7407 }
7408
7409 return x;
7410}
7411\f
b3728b0e
JW		 7412/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7413 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7414 is less useful. We can't allow both, because that results in exponential
956d6950 7415 run time recursion. There is a nullstone testcase that triggered
b3728b0e
JW		 7416 this. This macro avoids accidental uses of num_sign_bit_copies. */
7417#define num_sign_bit_copies()
7418
230d793d
RS		 7419/* Given an expression, X, compute which bits in X can be non-zero.
7420 We don't care about bits outside of those defined in MODE.
7421
7422 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7423 a shift, AND, or zero_extract, we can do better. */
7424
5f4f0e22 7425static unsigned HOST_WIDE_INT
951553af 7426nonzero_bits (x, mode)
230d793d
RS		 7427 rtx x;
7428 enum machine_mode mode;
7429{
951553af
RK		 7430 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7431 unsigned HOST_WIDE_INT inner_nz;
230d793d
RS		 7432 enum rtx_code code;
7433 int mode_width = GET_MODE_BITSIZE (mode);
7434 rtx tem;
7435
1c75dfa4
RK		 7436 /* For floating-point values, assume all bits are needed. */
7437 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7438 return nonzero;
7439
230d793d
RS		 7440 /* If X is wider than MODE, use its mode instead. */
7441 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7442 {
7443 mode = GET_MODE (x);
951553af 7444 nonzero = GET_MODE_MASK (mode);
230d793d
RS		 7445 mode_width = GET_MODE_BITSIZE (mode);
7446 }
7447
5f4f0e22 7448 if (mode_width > HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7449 /* Our only callers in this case look for single bit values. So
7450 just return the mode mask. Those tests will then be false. */
951553af 7451 return nonzero;
230d793d 7452
8baf60bb 7453#ifndef WORD_REGISTER_OPERATIONS
c6965c0f 7454 /* If MODE is wider than X, but both are a single word for both the host
0840fd91
RK		 7455 and target machines, we can compute this from which bits of the
7456 object might be nonzero in its own mode, taking into account the fact
7457 that on many CISC machines, accessing an object in a wider mode
7458 causes the high-order bits to become undefined. So they are
7459 not known to be zero. */
7460
7461 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7462 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7463 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
c6965c0f 7464 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
0840fd91
RK		 7465 {
7466 nonzero &= nonzero_bits (x, GET_MODE (x));
7467 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7468 return nonzero;
7469 }
7470#endif
7471
230d793d
RS		 7472 code = GET_CODE (x);
7473 switch (code)
7474 {
7475 case REG:
320dd7a7
RK		 7476#ifdef POINTERS_EXTEND_UNSIGNED
7477 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7478 all the bits above ptr_mode are known to be zero. */
7479 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7480 && REGNO_POINTER_FLAG (REGNO (x)))
7481 nonzero &= GET_MODE_MASK (ptr_mode);
7482#endif
7483
b0d71df9
RK		 7484#ifdef STACK_BOUNDARY
7485 /* If this is the stack pointer, we may know something about its
7486 alignment. If PUSH_ROUNDING is defined, it is possible for the
230d793d
RS		 7487 stack to be momentarily aligned only to that amount, so we pick
7488 the least alignment. */
7489
ee49a9c7
JW		 7490 /* We can't check for arg_pointer_rtx here, because it is not
7491 guaranteed to have as much alignment as the stack pointer.
7492 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7493 alignment but the argument pointer has only 64 bit alignment. */
7494
0e9ff885
DM		 7495 if ((x == frame_pointer_rtx
7496 || x == stack_pointer_rtx
7497 || x == hard_frame_pointer_rtx
7498 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7499 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7500#ifdef STACK_BIAS
7501 && !STACK_BIAS
7502#endif
7503 )
230d793d 7504 {
b0d71df9 7505 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
230d793d
RS		 7506
7507#ifdef PUSH_ROUNDING
91102d5a 7508 if (REGNO (x) == STACK_POINTER_REGNUM)
b0d71df9 7509 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
230d793d
RS		 7510#endif
7511
320dd7a7
RK		 7512 /* We must return here, otherwise we may get a worse result from
7513 one of the choices below. There is nothing useful below as
7514 far as the stack pointer is concerned. */
b0d71df9 7515 return nonzero &= ~ (sp_alignment - 1);
230d793d 7516 }
b0d71df9 7517#endif
230d793d 7518
55310dad
RK		 7519 /* If X is a register whose nonzero bits value is current, use it.
7520 Otherwise, if X is a register whose value we can find, use that
7521 value. Otherwise, use the previously-computed global nonzero bits
7522 for this register. */
7523
7524 if (reg_last_set_value[REGNO (x)] != 0
7525 && reg_last_set_mode[REGNO (x)] == mode
57cf50a4
GRK		 7526 && (reg_last_set_label[REGNO (x)] == label_tick
7527 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7528 && REG_N_SETS (REGNO (x)) == 1
7529 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7530 REGNO (x))))
55310dad
RK		 7531 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7532 return reg_last_set_nonzero_bits[REGNO (x)];
230d793d
RS		 7533
7534 tem = get_last_value (x);
9afa3d54 7535
230d793d 7536 if (tem)
9afa3d54
RK		 7537 {
7538#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7539 /* If X is narrower than MODE and TEM is a non-negative
7540 constant that would appear negative in the mode of X,
7541 sign-extend it for use in reg_nonzero_bits because some
7542 machines (maybe most) will actually do the sign-extension
7543 and this is the conservative approach.
7544
7545 ??? For 2.5, try to tighten up the MD files in this regard
7546 instead of this kludge. */
7547
7548 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7549 && GET_CODE (tem) == CONST_INT
7550 && INTVAL (tem) > 0
7551 && 0 != (INTVAL (tem)
7552 & ((HOST_WIDE_INT) 1
9e69be8c 7553 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 7554 tem = GEN_INT (INTVAL (tem)
7555 | ((HOST_WIDE_INT) (-1)
7556 << GET_MODE_BITSIZE (GET_MODE (x))));
7557#endif
7558 return nonzero_bits (tem, mode);
7559 }
951553af
RK		 7560 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7561 return reg_nonzero_bits[REGNO (x)] & nonzero;
230d793d 7562 else
951553af 7563 return nonzero;
230d793d
RS		 7564
7565 case CONST_INT:
9afa3d54
RK		 7566#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7567 /* If X is negative in MODE, sign-extend the value. */
9e69be8c
RK		 7568 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7569 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7570 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
9afa3d54
RK		 7571#endif
7572
230d793d
RS		 7573 return INTVAL (x);
7574
230d793d 7575 case MEM:
8baf60bb 7576#ifdef LOAD_EXTEND_OP
230d793d
RS		 7577 /* In many, if not most, RISC machines, reading a byte from memory
7578 zeros the rest of the register. Noticing that fact saves a lot
7579 of extra zero-extends. */
8baf60bb
RK		 7580 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7581 nonzero &= GET_MODE_MASK (GET_MODE (x));
230d793d 7582#endif
8baf60bb 7583 break;
230d793d 7584
230d793d
RS		 7585 case EQ: case NE:
7586 case GT: case GTU:
7587 case LT: case LTU:
7588 case GE: case GEU:
7589 case LE: case LEU:
3f508eca 7590
c6965c0f
RK		 7591 /* If this produces an integer result, we know which bits are set.
7592 Code here used to clear bits outside the mode of X, but that is
7593 now done above. */
230d793d 7594
c6965c0f
RK		 7595 if (GET_MODE_CLASS (mode) == MODE_INT
7596 && mode_width <= HOST_BITS_PER_WIDE_INT)
7597 nonzero = STORE_FLAG_VALUE;
230d793d 7598 break;
230d793d 7599
230d793d 7600 case NEG:
b3728b0e
JW		 7601#if 0
7602 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7603 and num_sign_bit_copies. */
d0ab8cd3
RK		 7604 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7605 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7606 nonzero = 1;
b3728b0e 7607#endif
230d793d
RS		 7608
7609 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
951553af 7610 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
230d793d 7611 break;
d0ab8cd3
RK		 7612
7613 case ABS:
b3728b0e
JW		 7614#if 0
7615 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7616 and num_sign_bit_copies. */
d0ab8cd3
RK		 7617 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7618 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7619 nonzero = 1;
b3728b0e 7620#endif
d0ab8cd3 7621 break;
230d793d
RS		 7622
7623 case TRUNCATE:
951553af 7624 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
230d793d
RS		 7625 break;
7626
7627 case ZERO_EXTEND:
951553af 7628 nonzero &= nonzero_bits (XEXP (x, 0), mode);
230d793d 7629 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
951553af 7630 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
230d793d
RS		 7631 break;
7632
7633 case SIGN_EXTEND:
7634 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7635 Otherwise, show all the bits in the outer mode but not the inner
7636 may be non-zero. */
951553af 7637 inner_nz = nonzero_bits (XEXP (x, 0), mode);
230d793d
RS		 7638 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7639 {
951553af 7640 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
e3da301d
MS		 7641 if (inner_nz
7642 & (((HOST_WIDE_INT) 1
7643 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
951553af 7644 inner_nz |= (GET_MODE_MASK (mode)
230d793d
RS		 7645 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7646 }
7647
951553af 7648 nonzero &= inner_nz;
230d793d
RS		 7649 break;
7650
7651 case AND:
951553af
RK		 7652 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7653 & nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7654 break;
7655
d0ab8cd3
RK		 7656 case XOR: case IOR:
7657 case UMIN: case UMAX: case SMIN: case SMAX:
951553af
RK		 7658 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7659 | nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7660 break;
7661
7662 case PLUS: case MINUS:
7663 case MULT:
7664 case DIV: case UDIV:
7665 case MOD: case UMOD:
7666 /* We can apply the rules of arithmetic to compute the number of
7667 high- and low-order zero bits of these operations. We start by
7668 computing the width (position of the highest-order non-zero bit)
7669 and the number of low-order zero bits for each value. */
7670 {
951553af
RK		 7671 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7672 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7673 int width0 = floor_log2 (nz0) + 1;
7674 int width1 = floor_log2 (nz1) + 1;
7675 int low0 = floor_log2 (nz0 & -nz0);
7676 int low1 = floor_log2 (nz1 & -nz1);
318b149c
RK		 7677 HOST_WIDE_INT op0_maybe_minusp
7678 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7679 HOST_WIDE_INT op1_maybe_minusp
7680 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
230d793d
RS		 7681 int result_width = mode_width;
7682 int result_low = 0;
7683
7684 switch (code)
7685 {
7686 case PLUS:
0e9ff885
DM		 7687#ifdef STACK_BIAS
7688 if (STACK_BIAS
7689 && (XEXP (x, 0) == stack_pointer_rtx
7690 || XEXP (x, 0) == frame_pointer_rtx)
7691 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7692 {
7693 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7694
7695 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7696 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7697 width0 = floor_log2 (nz0) + 1;
7698 width1 = floor_log2 (nz1) + 1;
7699 low0 = floor_log2 (nz0 & -nz0);
7700 low1 = floor_log2 (nz1 & -nz1);
7701 }
7702#endif
230d793d
RS		 7703 result_width = MAX (width0, width1) + 1;
7704 result_low = MIN (low0, low1);
7705 break;
7706 case MINUS:
7707 result_low = MIN (low0, low1);
7708 break;
7709 case MULT:
7710 result_width = width0 + width1;
7711 result_low = low0 + low1;
7712 break;
7713 case DIV:
7714 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7715 result_width = width0;
7716 break;
7717 case UDIV:
7718 result_width = width0;
7719 break;
7720 case MOD:
7721 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7722 result_width = MIN (width0, width1);
7723 result_low = MIN (low0, low1);
7724 break;
7725 case UMOD:
7726 result_width = MIN (width0, width1);
7727 result_low = MIN (low0, low1);
7728 break;
e9a25f70
JL		 7729 default:
7730 abort ();
230d793d
RS		 7731 }
7732
7733 if (result_width < mode_width)
951553af 7734 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
230d793d
RS		 7735
7736 if (result_low > 0)
951553af 7737 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
230d793d
RS		 7738 }
7739 break;
7740
7741 case ZERO_EXTRACT:
7742 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 7743 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
951553af 7744 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
230d793d
RS		 7745 break;
7746
7747 case SUBREG:
c3c2cb37
RK		 7748 /* If this is a SUBREG formed for a promoted variable that has
7749 been zero-extended, we know that at least the high-order bits
7750 are zero, though others might be too. */
7751
7752 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
951553af
RK		 7753 nonzero = (GET_MODE_MASK (GET_MODE (x))
7754 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
c3c2cb37 7755
230d793d
RS		 7756 /* If the inner mode is a single word for both the host and target
7757 machines, we can compute this from which bits of the inner
951553af 7758 object might be nonzero. */
230d793d 7759 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5f4f0e22
CH		 7760 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7761 <= HOST_BITS_PER_WIDE_INT))
230d793d 7762 {
951553af 7763 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8baf60bb 7764
b52ce03d
R		 7765#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7766 /* If this is a typical RISC machine, we only have to worry
7767 about the way loads are extended. */
7768 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7769 ? (nonzero
7770 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7771 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
230d793d 7772#endif
b52ce03d
R		 7773 {
7774 /* On many CISC machines, accessing an object in a wider mode
7775 causes the high-order bits to become undefined. So they are
7776 not known to be zero. */
7777 if (GET_MODE_SIZE (GET_MODE (x))
7778 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7779 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7780 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7781 }
230d793d
RS		 7782 }
7783 break;
7784
7785 case ASHIFTRT:
7786 case LSHIFTRT:
7787 case ASHIFT:
230d793d 7788 case ROTATE:
951553af 7789 /* The nonzero bits are in two classes: any bits within MODE
230d793d 7790 that aren't in GET_MODE (x) are always significant. The rest of the
951553af 7791 nonzero bits are those that are significant in the operand of
230d793d
RS		 7792 the shift when shifted the appropriate number of bits. This
7793 shows that high-order bits are cleared by the right shift and
7794 low-order bits by left shifts. */
7795 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7796 && INTVAL (XEXP (x, 1)) >= 0
5f4f0e22 7797 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7798 {
7799 enum machine_mode inner_mode = GET_MODE (x);
7800 int width = GET_MODE_BITSIZE (inner_mode);
7801 int count = INTVAL (XEXP (x, 1));
5f4f0e22 7802 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
951553af
RK		 7803 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7804 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5f4f0e22 7805 unsigned HOST_WIDE_INT outer = 0;
230d793d
RS		 7806
7807 if (mode_width > width)
951553af 7808 outer = (op_nonzero & nonzero & ~ mode_mask);
230d793d
RS		 7809
7810 if (code == LSHIFTRT)
7811 inner >>= count;
7812 else if (code == ASHIFTRT)
7813 {
7814 inner >>= count;
7815
951553af 7816 /* If the sign bit may have been nonzero before the shift, we
230d793d 7817 need to mark all the places it could have been copied to
951553af 7818 by the shift as possibly nonzero. */
5f4f0e22
CH		 7819 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7820 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
230d793d 7821 }
45620ed4 7822 else if (code == ASHIFT)
230d793d
RS		 7823 inner <<= count;
7824 else
7825 inner = ((inner << (count % width)
7826 | (inner >> (width - (count % width)))) & mode_mask);
7827
951553af 7828 nonzero &= (outer | inner);
230d793d
RS		 7829 }
7830 break;
7831
7832 case FFS:
7833 /* This is at most the number of bits in the mode. */
951553af 7834 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
230d793d 7835 break;
d0ab8cd3
RK		 7836
7837 case IF_THEN_ELSE:
951553af
RK		 7838 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7839 | nonzero_bits (XEXP (x, 2), mode));
d0ab8cd3 7840 break;
e9a25f70
JL		 7841
7842 default:
7843 break;
230d793d
RS		 7844 }
7845
951553af 7846 return nonzero;
230d793d 7847}
b3728b0e
JW		 7848
7849/* See the macro definition above. */
7850#undef num_sign_bit_copies
230d793d 7851\f
d0ab8cd3 7852/* Return the number of bits at the high-order end of X that are known to
5109d49f
RK		 7853 be equal to the sign bit. X will be used in mode MODE; if MODE is
7854 VOIDmode, X will be used in its own mode. The returned value will always
7855 be between 1 and the number of bits in MODE. */
d0ab8cd3
RK		 7856
7857static int
7858num_sign_bit_copies (x, mode)
7859 rtx x;
7860 enum machine_mode mode;
7861{
7862 enum rtx_code code = GET_CODE (x);
7863 int bitwidth;
7864 int num0, num1, result;
951553af 7865 unsigned HOST_WIDE_INT nonzero;
d0ab8cd3
RK		 7866 rtx tem;
7867
7868 /* If we weren't given a mode, use the mode of X. If the mode is still
1c75dfa4
RK		 7869 VOIDmode, we don't know anything. Likewise if one of the modes is
7870 floating-point. */
d0ab8cd3
RK		 7871
7872 if (mode == VOIDmode)
7873 mode = GET_MODE (x);
7874
1c75dfa4 7875 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
6752e8d2 7876 return 1;
d0ab8cd3
RK		 7877
7878 bitwidth = GET_MODE_BITSIZE (mode);
7879
0f41302f 7880 /* For a smaller object, just ignore the high bits. */
312def2e
RK		 7881 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7882 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7883 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7884
e9a25f70
JL		 7885 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7886 {
0c314d1a
RK		 7887#ifndef WORD_REGISTER_OPERATIONS
7888 /* If this machine does not do all register operations on the entire
7889 register and MODE is wider than the mode of X, we can say nothing
7890 at all about the high-order bits. */
e9a25f70
JL		 7891 return 1;
7892#else
7893 /* Likewise on machines that do, if the mode of the object is smaller
7894 than a word and loads of that size don't sign extend, we can say
7895 nothing about the high order bits. */
7896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7897#ifdef LOAD_EXTEND_OP
7898 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7899#endif
7900 )
7901 return 1;
0c314d1a 7902#endif
e9a25f70 7903 }
0c314d1a 7904
d0ab8cd3
RK		 7905 switch (code)
7906 {
7907 case REG:
55310dad 7908
ff0dbdd1
RK		 7909#ifdef POINTERS_EXTEND_UNSIGNED
7910 /* If pointers extend signed and this is a pointer in Pmode, say that
7911 all the bits above ptr_mode are known to be sign bit copies. */
7912 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7913 && REGNO_POINTER_FLAG (REGNO (x)))
7914 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7915#endif
7916
55310dad
RK		 7917 if (reg_last_set_value[REGNO (x)] != 0
7918 && reg_last_set_mode[REGNO (x)] == mode
57cf50a4
GRK		 7919 && (reg_last_set_label[REGNO (x)] == label_tick
7920 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7921 && REG_N_SETS (REGNO (x)) == 1
7922 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7923 REGNO (x))))
55310dad
RK		 7924 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7925 return reg_last_set_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7926
7927 tem = get_last_value (x);
7928 if (tem != 0)
7929 return num_sign_bit_copies (tem, mode);
55310dad
RK		 7930
7931 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7932 return reg_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7933 break;
7934
457816e2 7935 case MEM:
8baf60bb 7936#ifdef LOAD_EXTEND_OP
457816e2 7937 /* Some RISC machines sign-extend all loads of smaller than a word. */
8baf60bb
RK		 7938 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7939 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
457816e2 7940#endif
8baf60bb 7941 break;
457816e2 7942
d0ab8cd3
RK		 7943 case CONST_INT:
7944 /* If the constant is negative, take its 1's complement and remask.
7945 Then see how many zero bits we have. */
951553af 7946 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
ac49a949 7947 if (bitwidth <= HOST_BITS_PER_WIDE_INT
951553af
RK		 7948 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7949 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
d0ab8cd3 7950
951553af 7951 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7952
7953 case SUBREG:
c3c2cb37
RK		 7954 /* If this is a SUBREG for a promoted object that is sign-extended
7955 and we are looking at it in a wider mode, we know that at least the
7956 high-order bits are known to be sign bit copies. */
7957
7958 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
dc3e17ad
RK		 7959 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7960 num_sign_bit_copies (SUBREG_REG (x), mode));
c3c2cb37 7961
0f41302f 7962 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7963 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7964 {
7965 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7966 return MAX (1, (num0
7967 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7968 - bitwidth)));
7969 }
457816e2 7970
8baf60bb 7971#ifdef WORD_REGISTER_OPERATIONS
2aec5b7a 7972#ifdef LOAD_EXTEND_OP
8baf60bb
RK		 7973 /* For paradoxical SUBREGs on machines where all register operations
7974 affect the entire register, just look inside. Note that we are
7975 passing MODE to the recursive call, so the number of sign bit copies
7976 will remain relative to that mode, not the inner mode. */
457816e2 7977
2aec5b7a
JW		 7978 /* This works only if loads sign extend. Otherwise, if we get a
7979 reload for the inner part, it may be loaded from the stack, and
7980 then we lose all sign bit copies that existed before the store
7981 to the stack. */
7982
7983 if ((GET_MODE_SIZE (GET_MODE (x))
7984 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7985 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
457816e2 7986 return num_sign_bit_copies (SUBREG_REG (x), mode);
2aec5b7a 7987#endif
457816e2 7988#endif
d0ab8cd3
RK		 7989 break;
7990
7991 case SIGN_EXTRACT:
7992 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7993 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7994 break;
7995
7996 case SIGN_EXTEND:
7997 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7998 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7999
8000 case TRUNCATE:
0f41302f 8001 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 8002 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8003 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8004 - bitwidth)));
8005
8006 case NOT:
8007 return num_sign_bit_copies (XEXP (x, 0), mode);
8008
8009 case ROTATE: case ROTATERT:
8010 /* If we are rotating left by a number of bits less than the number
8011 of sign bit copies, we can just subtract that amount from the
8012 number. */
8013 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8014 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8015 {
8016 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8017 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8018 : bitwidth - INTVAL (XEXP (x, 1))));
8019 }
8020 break;
8021
8022 case NEG:
8023 /* In general, this subtracts one sign bit copy. But if the value
8024 is known to be positive, the number of sign bit copies is the
951553af
RK		 8025 same as that of the input. Finally, if the input has just one bit
8026 that might be nonzero, all the bits are copies of the sign bit. */
70186b34
BS		 8027 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8028 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8029 return num0 > 1 ? num0 - 1 : 1;
8030
951553af
RK		 8031 nonzero = nonzero_bits (XEXP (x, 0), mode);
8032 if (nonzero == 1)
d0ab8cd3
RK		 8033 return bitwidth;
8034
d0ab8cd3 8035 if (num0 > 1
951553af 8036 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
d0ab8cd3
RK		 8037 num0--;
8038
8039 return num0;
8040
8041 case IOR: case AND: case XOR:
8042 case SMIN: case SMAX: case UMIN: case UMAX:
8043 /* Logical operations will preserve the number of sign-bit copies.
8044 MIN and MAX operations always return one of the operands. */
8045 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8046 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8047 return MIN (num0, num1);
8048
8049 case PLUS: case MINUS:
8050 /* For addition and subtraction, we can have a 1-bit carry. However,
8051 if we are subtracting 1 from a positive number, there will not
8052 be such a carry. Furthermore, if the positive number is known to
8053 be 0 or 1, we know the result is either -1 or 0. */
8054
3e3ea975 8055 if (code == PLUS && XEXP (x, 1) == constm1_rtx
9295e6af 8056 && bitwidth <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 8057 {
951553af
RK		 8058 nonzero = nonzero_bits (XEXP (x, 0), mode);
8059 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8060 return (nonzero == 1 || nonzero == 0 ? bitwidth
8061 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8062 }
8063
8064 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8065 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8066 return MAX (1, MIN (num0, num1) - 1);
8067
8068 case MULT:
8069 /* The number of bits of the product is the sum of the number of
8070 bits of both terms. However, unless one of the terms if known
8071 to be positive, we must allow for an additional bit since negating
8072 a negative number can remove one sign bit copy. */
8073
8074 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8075 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8076
8077 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8078 if (result > 0
70186b34
BS		 8079 && (bitwidth > HOST_BITS_PER_WIDE_INT
8080 || (((nonzero_bits (XEXP (x, 0), mode)
8081 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8082 && ((nonzero_bits (XEXP (x, 1), mode)
8083 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
d0ab8cd3
RK		 8084 result--;
8085
8086 return MAX (1, result);
8087
8088 case UDIV:
70186b34
BS		 8089 /* The result must be <= the first operand. If the first operand
8090 has the high bit set, we know nothing about the number of sign
8091 bit copies. */
8092 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8093 return 1;
8094 else if ((nonzero_bits (XEXP (x, 0), mode)
8095 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8096 return 1;
8097 else
8098 return num_sign_bit_copies (XEXP (x, 0), mode);
8099
d0ab8cd3
RK		 8100 case UMOD:
8101 /* The result must be <= the scond operand. */
8102 return num_sign_bit_copies (XEXP (x, 1), mode);
8103
8104 case DIV:
8105 /* Similar to unsigned division, except that we have to worry about
8106 the case where the divisor is negative, in which case we have
8107 to add 1. */
8108 result = num_sign_bit_copies (XEXP (x, 0), mode);
8109 if (result > 1
70186b34
BS		 8110 && (bitwidth > HOST_BITS_PER_WIDE_INT
8111 || (nonzero_bits (XEXP (x, 1), mode)
8112 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8113 result--;
d0ab8cd3
RK		 8114
8115 return result;
8116
8117 case MOD:
8118 result = num_sign_bit_copies (XEXP (x, 1), mode);
8119 if (result > 1
70186b34
BS		 8120 && (bitwidth > HOST_BITS_PER_WIDE_INT
8121 || (nonzero_bits (XEXP (x, 1), mode)
8122 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8123 result--;
d0ab8cd3
RK		 8124
8125 return result;
8126
8127 case ASHIFTRT:
8128 /* Shifts by a constant add to the number of bits equal to the
8129 sign bit. */
8130 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8131 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8132 && INTVAL (XEXP (x, 1)) > 0)
8133 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8134
8135 return num0;
8136
8137 case ASHIFT:
d0ab8cd3
RK		 8138 /* Left shifts destroy copies. */
8139 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8140 || INTVAL (XEXP (x, 1)) < 0
8141 || INTVAL (XEXP (x, 1)) >= bitwidth)
8142 return 1;
8143
8144 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8145 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8146
8147 case IF_THEN_ELSE:
8148 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8149 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8150 return MIN (num0, num1);
8151
d0ab8cd3
RK		 8152 case EQ: case NE: case GE: case GT: case LE: case LT:
8153 case GEU: case GTU: case LEU: case LTU:
0802d516
RK		 8154 if (STORE_FLAG_VALUE == -1)
8155 return bitwidth;
e9a25f70
JL		 8156 break;
8157
8158 default:
8159 break;
d0ab8cd3
RK		 8160 }
8161
8162 /* If we haven't been able to figure it out by one of the above rules,
8163 see if some of the high-order bits are known to be zero. If so,
ac49a949
RS		 8164 count those bits and return one less than that amount. If we can't
8165 safely compute the mask for this mode, always return BITWIDTH. */
8166
8167 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6752e8d2 8168 return 1;
d0ab8cd3 8169
951553af 8170 nonzero = nonzero_bits (x, mode);
df6f4086 8171 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
951553af 8172 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8173}
8174\f
1a26b032
RK		 8175/* Return the number of "extended" bits there are in X, when interpreted
8176 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8177 unsigned quantities, this is the number of high-order zero bits.
8178 For signed quantities, this is the number of copies of the sign bit
8179 minus 1. In both case, this function returns the number of "spare"
8180 bits. For example, if two quantities for which this function returns
8181 at least 1 are added, the addition is known not to overflow.
8182
8183 This function will always return 0 unless called during combine, which
8184 implies that it must be called from a define_split. */
8185
8186int
8187extended_count (x, mode, unsignedp)
8188 rtx x;
8189 enum machine_mode mode;
8190 int unsignedp;
8191{
951553af 8192 if (nonzero_sign_valid == 0)
1a26b032
RK		 8193 return 0;
8194
8195 return (unsignedp
ac49a949
RS		 8196 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8197 && (GET_MODE_BITSIZE (mode) - 1
951553af 8198 - floor_log2 (nonzero_bits (x, mode))))
1a26b032
RK		 8199 : num_sign_bit_copies (x, mode) - 1);
8200}
8201\f
230d793d
RS		 8202/* This function is called from `simplify_shift_const' to merge two
8203 outer operations. Specifically, we have already found that we need
8204 to perform operation *POP0 with constant *PCONST0 at the outermost
8205 position. We would now like to also perform OP1 with constant CONST1
8206 (with *POP0 being done last).
8207
8208 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8209 the resulting operation. *PCOMP_P is set to 1 if we would need to
8210 complement the innermost operand, otherwise it is unchanged.
8211
8212 MODE is the mode in which the operation will be done. No bits outside
8213 the width of this mode matter. It is assumed that the width of this mode
5f4f0e22 8214 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
230d793d
RS		 8215
8216 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8217 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8218 result is simply *PCONST0.
8219
8220 If the resulting operation cannot be expressed as one operation, we
8221 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8222
8223static int
8224merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8225 enum rtx_code *pop0;
5f4f0e22 8226 HOST_WIDE_INT *pconst0;
230d793d 8227 enum rtx_code op1;
5f4f0e22 8228 HOST_WIDE_INT const1;
230d793d
RS		 8229 enum machine_mode mode;
8230 int *pcomp_p;
8231{
8232 enum rtx_code op0 = *pop0;
5f4f0e22 8233 HOST_WIDE_INT const0 = *pconst0;
230d793d
RS		 8234
8235 const0 &= GET_MODE_MASK (mode);
8236 const1 &= GET_MODE_MASK (mode);
8237
8238 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8239 if (op0 == AND)
8240 const1 &= const0;
8241
8242 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8243 if OP0 is SET. */
8244
8245 if (op1 == NIL || op0 == SET)
8246 return 1;
8247
8248 else if (op0 == NIL)
8249 op0 = op1, const0 = const1;
8250
8251 else if (op0 == op1)
8252 {
8253 switch (op0)
8254 {
8255 case AND:
8256 const0 &= const1;
8257 break;
8258 case IOR:
8259 const0 |= const1;
8260 break;
8261 case XOR:
8262 const0 ^= const1;
8263 break;
8264 case PLUS:
8265 const0 += const1;
8266 break;
8267 case NEG:
8268 op0 = NIL;
8269 break;
e9a25f70
JL		 8270 default:
8271 break;
230d793d
RS		 8272 }
8273 }
8274
8275 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8276 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8277 return 0;
8278
8279 /* If the two constants aren't the same, we can't do anything. The
8280 remaining six cases can all be done. */
8281 else if (const0 != const1)
8282 return 0;
8283
8284 else
8285 switch (op0)
8286 {
8287 case IOR:
8288 if (op1 == AND)
8289 /* (a & b) | b == b */
8290 op0 = SET;
8291 else /* op1 == XOR */
8292 /* (a ^ b) | b == a | b */
b729186a 8293 {;}
230d793d
RS		 8294 break;
8295
8296 case XOR:
8297 if (op1 == AND)
8298 /* (a & b) ^ b == (~a) & b */
8299 op0 = AND, *pcomp_p = 1;
8300 else /* op1 == IOR */
8301 /* (a | b) ^ b == a & ~b */
8302 op0 = AND, *pconst0 = ~ const0;
8303 break;
8304
8305 case AND:
8306 if (op1 == IOR)
8307 /* (a | b) & b == b */
8308 op0 = SET;
8309 else /* op1 == XOR */
8310 /* (a ^ b) & b) == (~a) & b */
8311 *pcomp_p = 1;
8312 break;
e9a25f70
JL		 8313 default:
8314 break;
230d793d
RS		 8315 }
8316
8317 /* Check for NO-OP cases. */
8318 const0 &= GET_MODE_MASK (mode);
8319 if (const0 == 0
8320 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8321 op0 = NIL;
8322 else if (const0 == 0 && op0 == AND)
8323 op0 = SET;
e51712db
KG		 8324 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8325 && op0 == AND)
230d793d
RS		 8326 op0 = NIL;
8327
7e4ce834
RH		 8328 /* ??? Slightly redundant with the above mask, but not entirely.
8329 Moving this above means we'd have to sign-extend the mode mask
8330 for the final test. */
8331 const0 = trunc_int_for_mode (const0, mode);
9fa6d012 8332
230d793d
RS		 8333 *pop0 = op0;
8334 *pconst0 = const0;
8335
8336 return 1;
8337}
8338\f
8339/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8340 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8341 that we started with.
8342
8343 The shift is normally computed in the widest mode we find in VAROP, as
8344 long as it isn't a different number of words than RESULT_MODE. Exceptions
8345 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8346
8347static rtx
8348simplify_shift_const (x, code, result_mode, varop, count)
8349 rtx x;
8350 enum rtx_code code;
8351 enum machine_mode result_mode;
8352 rtx varop;
8353 int count;
8354{
8355 enum rtx_code orig_code = code;
8356 int orig_count = count;
8357 enum machine_mode mode = result_mode;
8358 enum machine_mode shift_mode, tmode;
8359 int mode_words
8360 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8361 /* We form (outer_op (code varop count) (outer_const)). */
8362 enum rtx_code outer_op = NIL;
c4e861e8 8363 HOST_WIDE_INT outer_const = 0;
230d793d
RS		 8364 rtx const_rtx;
8365 int complement_p = 0;
8366 rtx new;
8367
8368 /* If we were given an invalid count, don't do anything except exactly
8369 what was requested. */
8370
8371 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8372 {
8373 if (x)
8374 return x;
8375
38a448ca 8376 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
230d793d
RS		 8377 }
8378
8379 /* Unless one of the branches of the `if' in this loop does a `continue',
8380 we will `break' the loop after the `if'. */
8381
8382 while (count != 0)
8383 {
8384 /* If we have an operand of (clobber (const_int 0)), just return that
8385 value. */
8386 if (GET_CODE (varop) == CLOBBER)
8387 return varop;
8388
8389 /* If we discovered we had to complement VAROP, leave. Making a NOT
8390 here would cause an infinite loop. */
8391 if (complement_p)
8392 break;
8393
abc95ed3 8394 /* Convert ROTATERT to ROTATE. */
230d793d
RS		 8395 if (code == ROTATERT)
8396 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8397
230d793d 8398 /* We need to determine what mode we will do the shift in. If the
f6789c77
RK		 8399 shift is a right shift or a ROTATE, we must always do it in the mode
8400 it was originally done in. Otherwise, we can do it in MODE, the
0f41302f 8401 widest mode encountered. */
f6789c77
RK		 8402 shift_mode
8403 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8404 ? result_mode : mode);
230d793d
RS		 8405
8406 /* Handle cases where the count is greater than the size of the mode
8407 minus 1. For ASHIFT, use the size minus one as the count (this can
8408 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8409 take the count modulo the size. For other shifts, the result is
8410 zero.
8411
8412 Since these shifts are being produced by the compiler by combining
8413 multiple operations, each of which are defined, we know what the
8414 result is supposed to be. */
8415
8416 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8417 {
8418 if (code == ASHIFTRT)
8419 count = GET_MODE_BITSIZE (shift_mode) - 1;
8420 else if (code == ROTATE || code == ROTATERT)
8421 count %= GET_MODE_BITSIZE (shift_mode);
8422 else
8423 {
8424 /* We can't simply return zero because there may be an
8425 outer op. */
8426 varop = const0_rtx;
8427 count = 0;
8428 break;
8429 }
8430 }
8431
8432 /* Negative counts are invalid and should not have been made (a
8433 programmer-specified negative count should have been handled
0f41302f 8434 above). */
230d793d
RS		 8435 else if (count < 0)
8436 abort ();
8437
312def2e
RK		 8438 /* An arithmetic right shift of a quantity known to be -1 or 0
8439 is a no-op. */
8440 if (code == ASHIFTRT
8441 && (num_sign_bit_copies (varop, shift_mode)
8442 == GET_MODE_BITSIZE (shift_mode)))
d0ab8cd3 8443 {
312def2e
RK		 8444 count = 0;
8445 break;
8446 }
d0ab8cd3 8447
312def2e
RK		 8448 /* If we are doing an arithmetic right shift and discarding all but
8449 the sign bit copies, this is equivalent to doing a shift by the
8450 bitsize minus one. Convert it into that shift because it will often
8451 allow other simplifications. */
500c518b 8452
312def2e
RK		 8453 if (code == ASHIFTRT
8454 && (count + num_sign_bit_copies (varop, shift_mode)
8455 >= GET_MODE_BITSIZE (shift_mode)))
8456 count = GET_MODE_BITSIZE (shift_mode) - 1;
500c518b 8457
230d793d
RS		 8458 /* We simplify the tests below and elsewhere by converting
8459 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8460 `make_compound_operation' will convert it to a ASHIFTRT for
8461 those machines (such as Vax) that don't have a LSHIFTRT. */
5f4f0e22 8462 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8463 && code == ASHIFTRT
951553af 8464 && ((nonzero_bits (varop, shift_mode)
5f4f0e22
CH		 8465 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8466 == 0))
230d793d
RS		 8467 code = LSHIFTRT;
8468
8469 switch (GET_CODE (varop))
8470 {
8471 case SIGN_EXTEND:
8472 case ZERO_EXTEND:
8473 case SIGN_EXTRACT:
8474 case ZERO_EXTRACT:
8475 new = expand_compound_operation (varop);
8476 if (new != varop)
8477 {
8478 varop = new;
8479 continue;
8480 }
8481 break;
8482
8483 case MEM:
8484 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8485 minus the width of a smaller mode, we can do this with a
8486 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8487 if ((code == ASHIFTRT || code == LSHIFTRT)
8488 && ! mode_dependent_address_p (XEXP (varop, 0))
8489 && ! MEM_VOLATILE_P (varop)
8490 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8491 MODE_INT, 1)) != BLKmode)
8492 {
f76b9db2 8493 if (BYTES_BIG_ENDIAN)
38a448ca 8494 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
f76b9db2 8495 else
38a448ca
RH		 8496 new = gen_rtx_MEM (tmode,
8497 plus_constant (XEXP (varop, 0),
8498 count / BITS_PER_UNIT));
e24b00c8 8499 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
c6df88cb 8500 MEM_COPY_ATTRIBUTES (new, varop);
230d793d
RS		 8501 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8502 : ZERO_EXTEND, mode, new);
8503 count = 0;
8504 continue;
8505 }
8506 break;
8507
8508 case USE:
8509 /* Similar to the case above, except that we can only do this if
8510 the resulting mode is the same as that of the underlying
8511 MEM and adjust the address depending on the *bits* endianness
8512 because of the way that bit-field extract insns are defined. */
8513 if ((code == ASHIFTRT || code == LSHIFTRT)
8514 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8515 MODE_INT, 1)) != BLKmode
8516 && tmode == GET_MODE (XEXP (varop, 0)))
8517 {
f76b9db2
ILT		 8518 if (BITS_BIG_ENDIAN)
8519 new = XEXP (varop, 0);
8520 else
8521 {
8522 new = copy_rtx (XEXP (varop, 0));
8523 SUBST (XEXP (new, 0),
8524 plus_constant (XEXP (new, 0),
8525 count / BITS_PER_UNIT));
8526 }
230d793d
RS		 8527
8528 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8529 : ZERO_EXTEND, mode, new);
8530 count = 0;
8531 continue;
8532 }
8533 break;
8534
8535 case SUBREG:
8536 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8537 the same number of words as what we've seen so far. Then store
8538 the widest mode in MODE. */
f9e67232
RS		 8539 if (subreg_lowpart_p (varop)
8540 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8541 > GET_MODE_SIZE (GET_MODE (varop)))
230d793d
RS		 8542 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8543 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8544 == mode_words))
8545 {
8546 varop = SUBREG_REG (varop);
8547 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8548 mode = GET_MODE (varop);
8549 continue;
8550 }
8551 break;
8552
8553 case MULT:
8554 /* Some machines use MULT instead of ASHIFT because MULT
8555 is cheaper. But it is still better on those machines to
8556 merge two shifts into one. */
8557 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8558 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8559 {
8560 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
6d649d26 8561 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS		 8562 continue;
8563 }
8564 break;
8565
8566 case UDIV:
8567 /* Similar, for when divides are cheaper. */
8568 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8569 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8570 {
8571 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8572 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS		 8573 continue;
8574 }
8575 break;
8576
8577 case ASHIFTRT:
8578 /* If we are extracting just the sign bit of an arithmetic right
8579 shift, that shift is not needed. */
8580 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8581 {
8582 varop = XEXP (varop, 0);
8583 continue;
8584 }
8585
0f41302f 8586 /* ... fall through ... */
230d793d
RS		 8587
8588 case LSHIFTRT:
8589 case ASHIFT:
230d793d
RS		 8590 case ROTATE:
8591 /* Here we have two nested shifts. The result is usually the
8592 AND of a new shift with a mask. We compute the result below. */
8593 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8594 && INTVAL (XEXP (varop, 1)) >= 0
8595 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5f4f0e22
CH		 8596 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8597 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 8598 {
8599 enum rtx_code first_code = GET_CODE (varop);
8600 int first_count = INTVAL (XEXP (varop, 1));
5f4f0e22 8601 unsigned HOST_WIDE_INT mask;
230d793d 8602 rtx mask_rtx;
230d793d 8603
230d793d
RS		 8604 /* We have one common special case. We can't do any merging if
8605 the inner code is an ASHIFTRT of a smaller mode. However, if
8606 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8607 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8608 we can convert it to
8609 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8610 This simplifies certain SIGN_EXTEND operations. */
8611 if (code == ASHIFT && first_code == ASHIFTRT
8612 && (GET_MODE_BITSIZE (result_mode)
8613 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8614 {
8615 /* C3 has the low-order C1 bits zero. */
8616
5f4f0e22
CH		 8617 mask = (GET_MODE_MASK (mode)
8618 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
230d793d 8619
5f4f0e22 8620 varop = simplify_and_const_int (NULL_RTX, result_mode,
230d793d 8621 XEXP (varop, 0), mask);
5f4f0e22 8622 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
230d793d
RS		 8623 varop, count);
8624 count = first_count;
8625 code = ASHIFTRT;
8626 continue;
8627 }
8628
d0ab8cd3
RK		 8629 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8630 than C1 high-order bits equal to the sign bit, we can convert
8631 this to either an ASHIFT or a ASHIFTRT depending on the
8632 two counts.
230d793d
RS		 8633
8634 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8635
8636 if (code == ASHIFTRT && first_code == ASHIFT
8637 && GET_MODE (varop) == shift_mode
d0ab8cd3
RK		 8638 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8639 > first_count))
230d793d 8640 {
d0ab8cd3
RK		 8641 count -= first_count;
8642 if (count < 0)
8643 count = - count, code = ASHIFT;
8644 varop = XEXP (varop, 0);
8645 continue;
230d793d
RS		 8646 }
8647
8648 /* There are some cases we can't do. If CODE is ASHIFTRT,
8649 we can only do this if FIRST_CODE is also ASHIFTRT.
8650
8651 We can't do the case when CODE is ROTATE and FIRST_CODE is
8652 ASHIFTRT.
8653
8654 If the mode of this shift is not the mode of the outer shift,
bdaae9a0 8655 we can't do this if either shift is a right shift or ROTATE.
230d793d
RS		 8656
8657 Finally, we can't do any of these if the mode is too wide
8658 unless the codes are the same.
8659
8660 Handle the case where the shift codes are the same
8661 first. */
8662
8663 if (code == first_code)
8664 {
8665 if (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8666 && (code == ASHIFTRT || code == LSHIFTRT
8667 || code == ROTATE))
230d793d
RS		 8668 break;
8669
8670 count += first_count;
8671 varop = XEXP (varop, 0);
8672 continue;
8673 }
8674
8675 if (code == ASHIFTRT
8676 || (code == ROTATE && first_code == ASHIFTRT)
5f4f0e22 8677 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
230d793d 8678 || (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8679 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8680 || first_code == ROTATE
230d793d
RS		 8681 || code == ROTATE)))
8682 break;
8683
8684 /* To compute the mask to apply after the shift, shift the
951553af 8685 nonzero bits of the inner shift the same way the
230d793d
RS		 8686 outer shift will. */
8687
951553af 8688 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
230d793d
RS		 8689
8690 mask_rtx
8691 = simplify_binary_operation (code, result_mode, mask_rtx,
5f4f0e22 8692 GEN_INT (count));
230d793d
RS		 8693
8694 /* Give up if we can't compute an outer operation to use. */
8695 if (mask_rtx == 0
8696 || GET_CODE (mask_rtx) != CONST_INT
8697 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8698 INTVAL (mask_rtx),
8699 result_mode, &complement_p))
8700 break;
8701
8702 /* If the shifts are in the same direction, we add the
8703 counts. Otherwise, we subtract them. */
8704 if ((code == ASHIFTRT || code == LSHIFTRT)
8705 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8706 count += first_count;
8707 else
8708 count -= first_count;
8709
8710 /* If COUNT is positive, the new shift is usually CODE,
8711 except for the two exceptions below, in which case it is
8712 FIRST_CODE. If the count is negative, FIRST_CODE should
8713 always be used */
8714 if (count > 0
8715 && ((first_code == ROTATE && code == ASHIFT)
8716 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8717 code = first_code;
8718 else if (count < 0)
8719 code = first_code, count = - count;
8720
8721 varop = XEXP (varop, 0);
8722 continue;
8723 }
8724
8725 /* If we have (A << B << C) for any shift, we can convert this to
8726 (A << C << B). This wins if A is a constant. Only try this if
8727 B is not a constant. */
8728
8729 else if (GET_CODE (varop) == code
8730 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8731 && 0 != (new
8732 = simplify_binary_operation (code, mode,
8733 XEXP (varop, 0),
5f4f0e22 8734 GEN_INT (count))))
230d793d
RS		 8735 {
8736 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8737 count = 0;
8738 continue;
8739 }
8740 break;
8741
8742 case NOT:
8743 /* Make this fit the case below. */
8744 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5f4f0e22 8745 GEN_INT (GET_MODE_MASK (mode)));
230d793d
RS		 8746 continue;
8747
8748 case IOR:
8749 case AND:
8750 case XOR:
8751 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8752 with C the size of VAROP - 1 and the shift is logical if
8753 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8754 we have an (le X 0) operation. If we have an arithmetic shift
8755 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8756 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8757
8758 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8759 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8760 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8761 && (code == LSHIFTRT || code == ASHIFTRT)
8762 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8763 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8764 {
8765 count = 0;
8766 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8767 const0_rtx);
8768
8769 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8770 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8771
8772 continue;
8773 }
8774
8775 /* If we have (shift (logical)), move the logical to the outside
8776 to allow it to possibly combine with another logical and the
8777 shift to combine with another shift. This also canonicalizes to
8778 what a ZERO_EXTRACT looks like. Also, some machines have
8779 (and (shift)) insns. */
8780
8781 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8782 && (new = simplify_binary_operation (code, result_mode,
8783 XEXP (varop, 1),
5f4f0e22 8784 GEN_INT (count))) != 0
7d171a1e 8785 && GET_CODE(new) == CONST_INT
230d793d
RS		 8786 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8787 INTVAL (new), result_mode, &complement_p))
8788 {
8789 varop = XEXP (varop, 0);
8790 continue;
8791 }
8792
8793 /* If we can't do that, try to simplify the shift in each arm of the
8794 logical expression, make a new logical expression, and apply
8795 the inverse distributive law. */
8796 {
00d4ca1c 8797 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d 8798 XEXP (varop, 0), count);
00d4ca1c 8799 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d
RS		 8800 XEXP (varop, 1), count);
8801
21a64bf1 8802 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
230d793d
RS		 8803 varop = apply_distributive_law (varop);
8804
8805 count = 0;
8806 }
8807 break;
8808
8809 case EQ:
45620ed4 8810 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
230d793d 8811 says that the sign bit can be tested, FOO has mode MODE, C is
45620ed4
RK		 8812 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8813 that may be nonzero. */
8814 if (code == LSHIFTRT
230d793d
RS		 8815 && XEXP (varop, 1) == const0_rtx
8816 && GET_MODE (XEXP (varop, 0)) == result_mode
8817 && count == GET_MODE_BITSIZE (result_mode) - 1
5f4f0e22 8818 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8819 && ((STORE_FLAG_VALUE
5f4f0e22 8820 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
951553af 8821 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8822 && merge_outer_ops (&outer_op, &outer_const, XOR,
8823 (HOST_WIDE_INT) 1, result_mode,
8824 &complement_p))
230d793d
RS		 8825 {
8826 varop = XEXP (varop, 0);
8827 count = 0;
8828 continue;
8829 }
8830 break;
8831
8832 case NEG:
d0ab8cd3
RK		 8833 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8834 than the number of bits in the mode is equivalent to A. */
8835 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
951553af 8836 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
230d793d 8837 {
d0ab8cd3 8838 varop = XEXP (varop, 0);
230d793d
RS		 8839 count = 0;
8840 continue;
8841 }
8842
8843 /* NEG commutes with ASHIFT since it is multiplication. Move the
8844 NEG outside to allow shifts to combine. */
8845 if (code == ASHIFT
5f4f0e22
CH		 8846 && merge_outer_ops (&outer_op, &outer_const, NEG,
8847 (HOST_WIDE_INT) 0, result_mode,
8848 &complement_p))
230d793d
RS		 8849 {
8850 varop = XEXP (varop, 0);
8851 continue;
8852 }
8853 break;
8854
8855 case PLUS:
d0ab8cd3
RK		 8856 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8857 is one less than the number of bits in the mode is
8858 equivalent to (xor A 1). */
230d793d
RS		 8859 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8860 && XEXP (varop, 1) == constm1_rtx
951553af 8861 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8862 && merge_outer_ops (&outer_op, &outer_const, XOR,
8863 (HOST_WIDE_INT) 1, result_mode,
8864 &complement_p))
230d793d
RS		 8865 {
8866 count = 0;
8867 varop = XEXP (varop, 0);
8868 continue;
8869 }
8870
3f508eca 8871 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
951553af 8872 that might be nonzero in BAR are those being shifted out and those
3f508eca
RK		 8873 bits are known zero in FOO, we can replace the PLUS with FOO.
8874 Similarly in the other operand order. This code occurs when
8875 we are computing the size of a variable-size array. */
8876
8877 if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8878 && count < HOST_BITS_PER_WIDE_INT
951553af
RK		 8879 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8880 && (nonzero_bits (XEXP (varop, 1), result_mode)
8881 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
3f508eca
RK		 8882 {
8883 varop = XEXP (varop, 0);
8884 continue;
8885 }
8886 else if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8887 && count < HOST_BITS_PER_WIDE_INT
ac49a949 8888 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
951553af 8889 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
3f508eca 8890 >> count)
951553af
RK		 8891 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8892 & nonzero_bits (XEXP (varop, 1),
3f508eca
RK		 8893 result_mode)))
8894 {
8895 varop = XEXP (varop, 1);
8896 continue;
8897 }
8898
230d793d
RS		 8899 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8900 if (code == ASHIFT
8901 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8902 && (new = simplify_binary_operation (ASHIFT, result_mode,
8903 XEXP (varop, 1),
5f4f0e22 8904 GEN_INT (count))) != 0
7d171a1e 8905 && GET_CODE(new) == CONST_INT
230d793d
RS		 8906 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8907 INTVAL (new), result_mode, &complement_p))
8908 {
8909 varop = XEXP (varop, 0);
8910 continue;
8911 }
8912 break;
8913
8914 case MINUS:
8915 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8916 with C the size of VAROP - 1 and the shift is logical if
8917 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8918 we have a (gt X 0) operation. If the shift is arithmetic with
8919 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8920 we have a (neg (gt X 0)) operation. */
8921
0802d516
RK		 8922 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8923 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
230d793d 8924 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
230d793d
RS		 8925 && (code == LSHIFTRT || code == ASHIFTRT)
8926 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8927 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8928 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8929 {
8930 count = 0;
8931 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8932 const0_rtx);
8933
8934 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8935 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8936
8937 continue;
8938 }
8939 break;
6e0ef100
JC		 8940
8941 case TRUNCATE:
8942 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8943 if the truncate does not affect the value. */
8944 if (code == LSHIFTRT
8945 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8946 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8947 && (INTVAL (XEXP (XEXP (varop, 0), 1))
b577a8ff
JL		 8948 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8949 - GET_MODE_BITSIZE (GET_MODE (varop)))))
6e0ef100
JC		 8950 {
8951 rtx varop_inner = XEXP (varop, 0);
8952
8953 varop_inner = gen_rtx_combine (LSHIFTRT,
8954 GET_MODE (varop_inner),
8955 XEXP (varop_inner, 0),
8956 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8957 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8958 varop_inner);
8959 count = 0;
8960 continue;
8961 }
8962 break;
e9a25f70
JL		 8963
8964 default:
8965 break;
230d793d
RS		 8966 }
8967
8968 break;
8969 }
8970
8971 /* We need to determine what mode to do the shift in. If the shift is
f6789c77
RK		 8972 a right shift or ROTATE, we must always do it in the mode it was
8973 originally done in. Otherwise, we can do it in MODE, the widest mode
8974 encountered. The code we care about is that of the shift that will
8975 actually be done, not the shift that was originally requested. */
8976 shift_mode
8977 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8978 ? result_mode : mode);
230d793d
RS		 8979
8980 /* We have now finished analyzing the shift. The result should be
8981 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8982 OUTER_OP is non-NIL, it is an operation that needs to be applied
8983 to the result of the shift. OUTER_CONST is the relevant constant,
8984 but we must turn off all bits turned off in the shift.
8985
8986 If we were passed a value for X, see if we can use any pieces of
8987 it. If not, make new rtx. */
8988
8989 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8990 && GET_CODE (XEXP (x, 1)) == CONST_INT
8991 && INTVAL (XEXP (x, 1)) == count)
8992 const_rtx = XEXP (x, 1);
8993 else
5f4f0e22 8994 const_rtx = GEN_INT (count);
230d793d
RS		 8995
8996 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8997 && GET_MODE (XEXP (x, 0)) == shift_mode
8998 && SUBREG_REG (XEXP (x, 0)) == varop)
8999 varop = XEXP (x, 0);
9000 else if (GET_MODE (varop) != shift_mode)
9001 varop = gen_lowpart_for_combine (shift_mode, varop);
9002
0f41302f 9003 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 9004 if (GET_CODE (varop) == CLOBBER)
9005 return x ? x : varop;
9006
9007 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9008 if (new != 0)
9009 x = new;
9010 else
9011 {
9012 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9013 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9014
9015 SUBST (XEXP (x, 0), varop);
9016 SUBST (XEXP (x, 1), const_rtx);
9017 }
9018
224eeff2
RK		 9019 /* If we have an outer operation and we just made a shift, it is
9020 possible that we could have simplified the shift were it not
9021 for the outer operation. So try to do the simplification
9022 recursively. */
9023
9024 if (outer_op != NIL && GET_CODE (x) == code
9025 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9026 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9027 INTVAL (XEXP (x, 1)));
9028
230d793d
RS		 9029 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9030 turn off all the bits that the shift would have turned off. */
9031 if (orig_code == LSHIFTRT && result_mode != shift_mode)
5f4f0e22 9032 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
230d793d
RS		 9033 GET_MODE_MASK (result_mode) >> orig_count);
9034
9035 /* Do the remainder of the processing in RESULT_MODE. */
9036 x = gen_lowpart_for_combine (result_mode, x);
9037
9038 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9039 operation. */
9040 if (complement_p)
0c1c8ea6 9041 x = gen_unary (NOT, result_mode, result_mode, x);
230d793d
RS		 9042
9043 if (outer_op != NIL)
9044 {
5f4f0e22 9045 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7e4ce834 9046 outer_const = trunc_int_for_mode (outer_const, result_mode);
230d793d
RS		 9047
9048 if (outer_op == AND)
5f4f0e22 9049 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
230d793d
RS		 9050 else if (outer_op == SET)
9051 /* This means that we have determined that the result is
9052 equivalent to a constant. This should be rare. */
5f4f0e22 9053 x = GEN_INT (outer_const);
230d793d 9054 else if (GET_RTX_CLASS (outer_op) == '1')
0c1c8ea6 9055 x = gen_unary (outer_op, result_mode, result_mode, x);
230d793d 9056 else
5f4f0e22 9057 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
230d793d
RS		 9058 }
9059
9060 return x;
9061}
9062\f
9063/* Like recog, but we receive the address of a pointer to a new pattern.
9064 We try to match the rtx that the pointer points to.
9065 If that fails, we may try to modify or replace the pattern,
9066 storing the replacement into the same pointer object.
9067
9068 Modifications include deletion or addition of CLOBBERs.
9069
9070 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9071 the CLOBBERs are placed.
9072
9073 The value is the final insn code from the pattern ultimately matched,
9074 or -1. */
9075
9076static int
8e2f6e35 9077recog_for_combine (pnewpat, insn, pnotes)
230d793d
RS		 9078 rtx *pnewpat;
9079 rtx insn;
9080 rtx *pnotes;
9081{
9082 register rtx pat = *pnewpat;
9083 int insn_code_number;
9084 int num_clobbers_to_add = 0;
9085 int i;
9086 rtx notes = 0;
9087
974f4146
RK		 9088 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9089 we use to indicate that something didn't match. If we find such a
9090 thing, force rejection. */
d96023cf 9091 if (GET_CODE (pat) == PARALLEL)
974f4146 9092 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
d96023cf
RK		 9093 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9094 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
974f4146
RK		 9095 return -1;
9096
230d793d
RS		 9097 /* Is the result of combination a valid instruction? */
9098 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9099
9100 /* If it isn't, there is the possibility that we previously had an insn
9101 that clobbered some register as a side effect, but the combined
9102 insn doesn't need to do that. So try once more without the clobbers
9103 unless this represents an ASM insn. */
9104
9105 if (insn_code_number < 0 && ! check_asm_operands (pat)
9106 && GET_CODE (pat) == PARALLEL)
9107 {
9108 int pos;
9109
9110 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9111 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9112 {
9113 if (i != pos)
9114 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9115 pos++;
9116 }
9117
9118 SUBST_INT (XVECLEN (pat, 0), pos);
9119
9120 if (pos == 1)
9121 pat = XVECEXP (pat, 0, 0);
9122
9123 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9124 }
9125
9126 /* If we had any clobbers to add, make a new pattern than contains
9127 them. Then check to make sure that all of them are dead. */
9128 if (num_clobbers_to_add)
9129 {
38a448ca
RH		 9130 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9131 gen_rtvec (GET_CODE (pat) == PARALLEL
9132 ? XVECLEN (pat, 0) + num_clobbers_to_add
9133 : num_clobbers_to_add + 1));
230d793d
RS		 9134
9135 if (GET_CODE (pat) == PARALLEL)
9136 for (i = 0; i < XVECLEN (pat, 0); i++)
9137 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9138 else
9139 XVECEXP (newpat, 0, 0) = pat;
9140
9141 add_clobbers (newpat, insn_code_number);
9142
9143 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9144 i < XVECLEN (newpat, 0); i++)
9145 {
9146 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9147 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9148 return -1;
38a448ca
RH		 9149 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9150 XEXP (XVECEXP (newpat, 0, i), 0), notes);
230d793d
RS		 9151 }
9152 pat = newpat;
9153 }
9154
9155 *pnewpat = pat;
9156 *pnotes = notes;
9157
9158 return insn_code_number;
9159}
9160\f
9161/* Like gen_lowpart but for use by combine. In combine it is not possible
9162 to create any new pseudoregs. However, it is safe to create
9163 invalid memory addresses, because combine will try to recognize
9164 them and all they will do is make the combine attempt fail.
9165
9166 If for some reason this cannot do its job, an rtx
9167 (clobber (const_int 0)) is returned.
9168 An insn containing that will not be recognized. */
9169
9170#undef gen_lowpart
9171
9172static rtx
9173gen_lowpart_for_combine (mode, x)
9174 enum machine_mode mode;
9175 register rtx x;
9176{
9177 rtx result;
9178
9179 if (GET_MODE (x) == mode)
9180 return x;
9181
eae957a8
RK		 9182 /* We can only support MODE being wider than a word if X is a
9183 constant integer or has a mode the same size. */
9184
9185 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9186 && ! ((GET_MODE (x) == VOIDmode
9187 && (GET_CODE (x) == CONST_INT
9188 || GET_CODE (x) == CONST_DOUBLE))
9189 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
38a448ca 9190 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9191
9192 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9193 won't know what to do. So we will strip off the SUBREG here and
9194 process normally. */
9195 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9196 {
9197 x = SUBREG_REG (x);
9198 if (GET_MODE (x) == mode)
9199 return x;
9200 }
9201
9202 result = gen_lowpart_common (mode, x);
64bf47a2
RK		 9203 if (result != 0
9204 && GET_CODE (result) == SUBREG
9205 && GET_CODE (SUBREG_REG (result)) == REG
9206 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9207 && (GET_MODE_SIZE (GET_MODE (result))
9208 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
b1f21e0a 9209 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
64bf47a2 9210
230d793d
RS		 9211 if (result)
9212 return result;
9213
9214 if (GET_CODE (x) == MEM)
9215 {
9216 register int offset = 0;
9217 rtx new;
9218
9219 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9220 address. */
9221 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
38a448ca 9222 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9223
9224 /* If we want to refer to something bigger than the original memref,
9225 generate a perverse subreg instead. That will force a reload
9226 of the original memref X. */
9227 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
38a448ca 9228 return gen_rtx_SUBREG (mode, x, 0);
230d793d 9229
f76b9db2
ILT		 9230 if (WORDS_BIG_ENDIAN)
9231 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9232 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9233 if (BYTES_BIG_ENDIAN)
9234 {
9235 /* Adjust the address so that the address-after-the-data is
9236 unchanged. */
9237 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9238 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9239 }
38a448ca 9240 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
230d793d 9241 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
c6df88cb 9242 MEM_COPY_ATTRIBUTES (new, x);
230d793d
RS		 9243 return new;
9244 }
9245
9246 /* If X is a comparison operator, rewrite it in a new mode. This
9247 probably won't match, but may allow further simplifications. */
9248 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9249 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9250
9251 /* If we couldn't simplify X any other way, just enclose it in a
9252 SUBREG. Normally, this SUBREG won't match, but some patterns may
a7c99304 9253 include an explicit SUBREG or we may simplify it further in combine. */
230d793d 9254 else
dfbe1b2f
RK		 9255 {
9256 int word = 0;
9257
9258 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9259 word = ((GET_MODE_SIZE (GET_MODE (x))
9260 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9261 / UNITS_PER_WORD);
38a448ca 9262 return gen_rtx_SUBREG (mode, x, word);
dfbe1b2f 9263 }
230d793d
RS		 9264}
9265\f
9266/* Make an rtx expression. This is a subset of gen_rtx and only supports
9267 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9268
9269 If the identical expression was previously in the insn (in the undobuf),
9270 it will be returned. Only if it is not found will a new expression
9271 be made. */
9272
9273/*VARARGS2*/
9274static rtx
4f90e4a0 9275gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
230d793d 9276{
5148a72b 9277#ifndef ANSI_PROTOTYPES
230d793d
RS		 9278 enum rtx_code code;
9279 enum machine_mode mode;
4f90e4a0
RK		 9280#endif
9281 va_list p;
230d793d
RS		 9282 int n_args;
9283 rtx args[3];
b729186a 9284 int j;
6f7d635c 9285 const char *fmt;
230d793d 9286 rtx rt;
241cea85 9287 struct undo *undo;
230d793d 9288
4f90e4a0
RK		 9289 VA_START (p, mode);
9290
5148a72b 9291#ifndef ANSI_PROTOTYPES
230d793d
RS		 9292 code = va_arg (p, enum rtx_code);
9293 mode = va_arg (p, enum machine_mode);
4f90e4a0
RK		 9294#endif
9295
230d793d
RS		 9296 n_args = GET_RTX_LENGTH (code);
9297 fmt = GET_RTX_FORMAT (code);
9298
9299 if (n_args == 0 || n_args > 3)
9300 abort ();
9301
9302 /* Get each arg and verify that it is supposed to be an expression. */
9303 for (j = 0; j < n_args; j++)
9304 {
9305 if (*fmt++ != 'e')
9306 abort ();
9307
9308 args[j] = va_arg (p, rtx);
9309 }
9310
9311 /* See if this is in undobuf. Be sure we don't use objects that came
9312 from another insn; this could produce circular rtl structures. */
9313
241cea85
RK		 9314 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9315 if (!undo->is_int
9316 && GET_CODE (undo->old_contents.r) == code
9317 && GET_MODE (undo->old_contents.r) == mode)
230d793d
RS		 9318 {
9319 for (j = 0; j < n_args; j++)
241cea85 9320 if (XEXP (undo->old_contents.r, j) != args[j])
230d793d
RS		 9321 break;
9322
9323 if (j == n_args)
241cea85 9324 return undo->old_contents.r;
230d793d
RS		 9325 }
9326
9327 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9328 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9329 rt = rtx_alloc (code);
9330 PUT_MODE (rt, mode);
9331 XEXP (rt, 0) = args[0];
9332 if (n_args > 1)
9333 {
9334 XEXP (rt, 1) = args[1];
9335 if (n_args > 2)
9336 XEXP (rt, 2) = args[2];
9337 }
9338 return rt;
9339}
9340
9341/* These routines make binary and unary operations by first seeing if they
9342 fold; if not, a new expression is allocated. */
9343
9344static rtx
9345gen_binary (code, mode, op0, op1)
9346 enum rtx_code code;
9347 enum machine_mode mode;
9348 rtx op0, op1;
9349{
9350 rtx result;
1a26b032
RK		 9351 rtx tem;
9352
9353 if (GET_RTX_CLASS (code) == 'c'
9354 && (GET_CODE (op0) == CONST_INT
9355 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9356 tem = op0, op0 = op1, op1 = tem;
230d793d
RS		 9357
9358 if (GET_RTX_CLASS (code) == '<')
9359 {
9360 enum machine_mode op_mode = GET_MODE (op0);
9210df58
RK		 9361
9362 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
0f41302f 9363 just (REL_OP X Y). */
9210df58
RK		 9364 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9365 {
9366 op1 = XEXP (op0, 1);
9367 op0 = XEXP (op0, 0);
9368 op_mode = GET_MODE (op0);
9369 }
9370
230d793d
RS		 9371 if (op_mode == VOIDmode)
9372 op_mode = GET_MODE (op1);
9373 result = simplify_relational_operation (code, op_mode, op0, op1);
9374 }
9375 else
9376 result = simplify_binary_operation (code, mode, op0, op1);
9377
9378 if (result)
9379 return result;
9380
9381 /* Put complex operands first and constants second. */
9382 if (GET_RTX_CLASS (code) == 'c'
9383 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9384 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9385 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9386 || (GET_CODE (op0) == SUBREG
9387 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9388 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9389 return gen_rtx_combine (code, mode, op1, op0);
9390
e5e809f4
JL		 9391 /* If we are turning off bits already known off in OP0, we need not do
9392 an AND. */
9393 else if (code == AND && GET_CODE (op1) == CONST_INT
9394 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9395 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9396 return op0;
9397
230d793d
RS		 9398 return gen_rtx_combine (code, mode, op0, op1);
9399}
9400
9401static rtx
0c1c8ea6 9402gen_unary (code, mode, op0_mode, op0)
230d793d 9403 enum rtx_code code;
0c1c8ea6 9404 enum machine_mode mode, op0_mode;
230d793d
RS		 9405 rtx op0;
9406{
0c1c8ea6 9407 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
230d793d
RS		 9408
9409 if (result)
9410 return result;
9411
9412 return gen_rtx_combine (code, mode, op0);
9413}
9414\f
9415/* Simplify a comparison between *POP0 and *POP1 where CODE is the
9416 comparison code that will be tested.
9417
9418 The result is a possibly different comparison code to use. *POP0 and
9419 *POP1 may be updated.
9420
9421 It is possible that we might detect that a comparison is either always
9422 true or always false. However, we do not perform general constant
5089e22e 9423 folding in combine, so this knowledge isn't useful. Such tautologies
230d793d
RS		 9424 should have been detected earlier. Hence we ignore all such cases. */
9425
9426static enum rtx_code
9427simplify_comparison (code, pop0, pop1)
9428 enum rtx_code code;
9429 rtx *pop0;
9430 rtx *pop1;
9431{
9432 rtx op0 = *pop0;
9433 rtx op1 = *pop1;
9434 rtx tem, tem1;
9435 int i;
9436 enum machine_mode mode, tmode;
9437
9438 /* Try a few ways of applying the same transformation to both operands. */
9439 while (1)
9440 {
3a19aabc
RK		 9441#ifndef WORD_REGISTER_OPERATIONS
9442 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9443 so check specially. */
9444 if (code != GTU && code != GEU && code != LTU && code != LEU
9445 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9446 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9447 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9448 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9449 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9450 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
ad25ba17 9451 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
3a19aabc
RK		 9452 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9453 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9454 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9455 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9456 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9457 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9458 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9459 && (INTVAL (XEXP (op0, 1))
9460 == (GET_MODE_BITSIZE (GET_MODE (op0))
9461 - (GET_MODE_BITSIZE
9462 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9463 {
9464 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9465 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9466 }
9467#endif
9468
230d793d
RS		 9469 /* If both operands are the same constant shift, see if we can ignore the
9470 shift. We can if the shift is a rotate or if the bits shifted out of
951553af 9471 this shift are known to be zero for both inputs and if the type of
230d793d 9472 comparison is compatible with the shift. */
67232b23
RK		 9473 if (GET_CODE (op0) == GET_CODE (op1)
9474 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9475 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
45620ed4 9476 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
67232b23
RK		 9477 && (code != GT && code != LT && code != GE && code != LE))
9478 || (GET_CODE (op0) == ASHIFTRT
9479 && (code != GTU && code != LTU
9480 && code != GEU && code != GEU)))
9481 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9482 && INTVAL (XEXP (op0, 1)) >= 0
9483 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9484 && XEXP (op0, 1) == XEXP (op1, 1))
230d793d
RS		 9485 {
9486 enum machine_mode mode = GET_MODE (op0);
5f4f0e22 9487 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9488 int shift_count = INTVAL (XEXP (op0, 1));
9489
9490 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9491 mask &= (mask >> shift_count) << shift_count;
45620ed4 9492 else if (GET_CODE (op0) == ASHIFT)
230d793d
RS		 9493 mask = (mask & (mask << shift_count)) >> shift_count;
9494
951553af
RK		 9495 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9496 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
230d793d
RS		 9497 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9498 else
9499 break;
9500 }
9501
9502 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9503 SUBREGs are of the same mode, and, in both cases, the AND would
9504 be redundant if the comparison was done in the narrower mode,
9505 do the comparison in the narrower mode (e.g., we are AND'ing with 1
951553af
RK		 9506 and the operand's possibly nonzero bits are 0xffffff01; in that case
9507 if we only care about QImode, we don't need the AND). This case
9508 occurs if the output mode of an scc insn is not SImode and
7e4dc511
RK		 9509 STORE_FLAG_VALUE == 1 (e.g., the 386).
9510
9511 Similarly, check for a case where the AND's are ZERO_EXTEND
9512 operations from some narrower mode even though a SUBREG is not
9513 present. */
230d793d
RS		 9514
9515 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9516 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7e4dc511 9517 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
230d793d 9518 {
7e4dc511
RK		 9519 rtx inner_op0 = XEXP (op0, 0);
9520 rtx inner_op1 = XEXP (op1, 0);
9521 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9522 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9523 int changed = 0;
9524
9525 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9526 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9527 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9528 && (GET_MODE (SUBREG_REG (inner_op0))
9529 == GET_MODE (SUBREG_REG (inner_op1)))
729a2bc6 9530 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
7e4dc511 9531 <= HOST_BITS_PER_WIDE_INT)
01c82bbb 9532 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
729a2bc6 9533 GET_MODE (SUBREG_REG (inner_op0)))))
01c82bbb
RK		 9534 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9535 GET_MODE (SUBREG_REG (inner_op1))))))
7e4dc511
RK		 9536 {
9537 op0 = SUBREG_REG (inner_op0);
9538 op1 = SUBREG_REG (inner_op1);
9539
9540 /* The resulting comparison is always unsigned since we masked
0f41302f 9541 off the original sign bit. */
7e4dc511
RK		 9542 code = unsigned_condition (code);
9543
9544 changed = 1;
9545 }
230d793d 9546
7e4dc511
RK		 9547 else if (c0 == c1)
9548 for (tmode = GET_CLASS_NARROWEST_MODE
9549 (GET_MODE_CLASS (GET_MODE (op0)));
9550 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
e51712db 9551 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
7e4dc511
RK		 9552 {
9553 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9554 op1 = gen_lowpart_for_combine (tmode, inner_op1);
66415c8b 9555 code = unsigned_condition (code);
7e4dc511
RK		 9556 changed = 1;
9557 break;
9558 }
9559
9560 if (! changed)
9561 break;
230d793d 9562 }
3a19aabc 9563
ad25ba17
RK		 9564 /* If both operands are NOT, we can strip off the outer operation
9565 and adjust the comparison code for swapped operands; similarly for
9566 NEG, except that this must be an equality comparison. */
9567 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9568 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9569 && (code == EQ || code == NE)))
9570 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
3a19aabc 9571
230d793d
RS		 9572 else
9573 break;
9574 }
9575
9576 /* If the first operand is a constant, swap the operands and adjust the
3aceff0d
RK		 9577 comparison code appropriately, but don't do this if the second operand
9578 is already a constant integer. */
9579 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
230d793d
RS		 9580 {
9581 tem = op0, op0 = op1, op1 = tem;
9582 code = swap_condition (code);
9583 }
9584
9585 /* We now enter a loop during which we will try to simplify the comparison.
9586 For the most part, we only are concerned with comparisons with zero,
9587 but some things may really be comparisons with zero but not start
9588 out looking that way. */
9589
9590 while (GET_CODE (op1) == CONST_INT)
9591 {
9592 enum machine_mode mode = GET_MODE (op0);
9593 int mode_width = GET_MODE_BITSIZE (mode);
5f4f0e22 9594 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9595 int equality_comparison_p;
9596 int sign_bit_comparison_p;
9597 int unsigned_comparison_p;
5f4f0e22 9598 HOST_WIDE_INT const_op;
230d793d
RS		 9599
9600 /* We only want to handle integral modes. This catches VOIDmode,
9601 CCmode, and the floating-point modes. An exception is that we
9602 can handle VOIDmode if OP0 is a COMPARE or a comparison
9603 operation. */
9604
9605 if (GET_MODE_CLASS (mode) != MODE_INT
9606 && ! (mode == VOIDmode
9607 && (GET_CODE (op0) == COMPARE
9608 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9609 break;
9610
9611 /* Get the constant we are comparing against and turn off all bits
9612 not on in our mode. */
9613 const_op = INTVAL (op1);
5f4f0e22 9614 if (mode_width <= HOST_BITS_PER_WIDE_INT)
4803a34a 9615 const_op &= mask;
230d793d
RS		 9616
9617 /* If we are comparing against a constant power of two and the value
951553af 9618 being compared can only have that single bit nonzero (e.g., it was
230d793d
RS		 9619 `and'ed with that bit), we can replace this with a comparison
9620 with zero. */
9621 if (const_op
9622 && (code == EQ || code == NE || code == GE || code == GEU
9623 || code == LT || code == LTU)
5f4f0e22 9624 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 9625 && exact_log2 (const_op) >= 0
e51712db 9626 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
230d793d
RS		 9627 {
9628 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9629 op1 = const0_rtx, const_op = 0;
9630 }
9631
d0ab8cd3
RK		 9632 /* Similarly, if we are comparing a value known to be either -1 or
9633 0 with -1, change it to the opposite comparison against zero. */
9634
9635 if (const_op == -1
9636 && (code == EQ || code == NE || code == GT || code == LE
9637 || code == GEU || code == LTU)
9638 && num_sign_bit_copies (op0, mode) == mode_width)
9639 {
9640 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9641 op1 = const0_rtx, const_op = 0;
9642 }
9643
230d793d 9644 /* Do some canonicalizations based on the comparison code. We prefer
4803a34a
RK		 9645 comparisons against zero and then prefer equality comparisons.
9646 If we can reduce the size of a constant, we will do that too. */
230d793d
RS		 9647
9648 switch (code)
9649 {
9650 case LT:
4803a34a
RK		 9651 /* < C is equivalent to <= (C - 1) */
9652 if (const_op > 0)
230d793d 9653 {
4803a34a 9654 const_op -= 1;
5f4f0e22 9655 op1 = GEN_INT (const_op);
230d793d
RS		 9656 code = LE;
9657 /* ... fall through to LE case below. */
9658 }
9659 else
9660 break;
9661
9662 case LE:
4803a34a
RK		 9663 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9664 if (const_op < 0)
9665 {
9666 const_op += 1;
5f4f0e22 9667 op1 = GEN_INT (const_op);
4803a34a
RK		 9668 code = LT;
9669 }
230d793d
RS		 9670
9671 /* If we are doing a <= 0 comparison on a value known to have
9672 a zero sign bit, we can replace this with == 0. */
9673 else if (const_op == 0
5f4f0e22 9674 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9675 && (nonzero_bits (op0, mode)
5f4f0e22 9676 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9677 code = EQ;
9678 break;
9679
9680 case GE:
0f41302f 9681 /* >= C is equivalent to > (C - 1). */
4803a34a 9682 if (const_op > 0)
230d793d 9683 {
4803a34a 9684 const_op -= 1;
5f4f0e22 9685 op1 = GEN_INT (const_op);
230d793d
RS		 9686 code = GT;
9687 /* ... fall through to GT below. */
9688 }
9689 else
9690 break;
9691
9692 case GT:
4803a34a
RK		 9693 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9694 if (const_op < 0)
9695 {
9696 const_op += 1;
5f4f0e22 9697 op1 = GEN_INT (const_op);
4803a34a
RK		 9698 code = GE;
9699 }
230d793d
RS		 9700
9701 /* If we are doing a > 0 comparison on a value known to have
9702 a zero sign bit, we can replace this with != 0. */
9703 else if (const_op == 0
5f4f0e22 9704 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9705 && (nonzero_bits (op0, mode)
5f4f0e22 9706 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9707 code = NE;
9708 break;
9709
230d793d 9710 case LTU:
4803a34a
RK		 9711 /* < C is equivalent to <= (C - 1). */
9712 if (const_op > 0)
9713 {
9714 const_op -= 1;
5f4f0e22 9715 op1 = GEN_INT (const_op);
4803a34a 9716 code = LEU;
0f41302f 9717 /* ... fall through ... */
4803a34a 9718 }
d0ab8cd3
RK		 9719
9720 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
f77aada2
JW		 9721 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9722 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9723 {
9724 const_op = 0, op1 = const0_rtx;
9725 code = GE;
9726 break;
9727 }
4803a34a
RK		 9728 else
9729 break;
230d793d
RS		 9730
9731 case LEU:
9732 /* unsigned <= 0 is equivalent to == 0 */
9733 if (const_op == 0)
9734 code = EQ;
d0ab8cd3 9735
0f41302f 9736 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
f77aada2
JW		 9737 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9738 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9739 {
9740 const_op = 0, op1 = const0_rtx;
9741 code = GE;
9742 }
230d793d
RS		 9743 break;
9744
4803a34a
RK		 9745 case GEU:
9746 /* >= C is equivalent to < (C - 1). */
9747 if (const_op > 1)
9748 {
9749 const_op -= 1;
5f4f0e22 9750 op1 = GEN_INT (const_op);
4803a34a 9751 code = GTU;
0f41302f 9752 /* ... fall through ... */
4803a34a 9753 }
d0ab8cd3
RK		 9754
9755 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
f77aada2
JW		 9756 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9757 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9758 {
9759 const_op = 0, op1 = const0_rtx;
9760 code = LT;
8b2e69e1 9761 break;
d0ab8cd3 9762 }
4803a34a
RK		 9763 else
9764 break;
9765
230d793d
RS		 9766 case GTU:
9767 /* unsigned > 0 is equivalent to != 0 */
9768 if (const_op == 0)
9769 code = NE;
d0ab8cd3
RK		 9770
9771 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
f77aada2
JW		 9772 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9773 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9774 {
9775 const_op = 0, op1 = const0_rtx;
9776 code = LT;
9777 }
230d793d 9778 break;
e9a25f70
JL		 9779
9780 default:
9781 break;
230d793d
RS		 9782 }
9783
9784 /* Compute some predicates to simplify code below. */
9785
9786 equality_comparison_p = (code == EQ || code == NE);
9787 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9788 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9789 || code == LEU);
9790
6139ff20
RK		 9791 /* If this is a sign bit comparison and we can do arithmetic in
9792 MODE, say that we will only be needing the sign bit of OP0. */
9793 if (sign_bit_comparison_p
9794 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9795 op0 = force_to_mode (op0, mode,
9796 ((HOST_WIDE_INT) 1
9797 << (GET_MODE_BITSIZE (mode) - 1)),
e3d616e3 9798 NULL_RTX, 0);
6139ff20 9799
230d793d
RS		 9800 /* Now try cases based on the opcode of OP0. If none of the cases
9801 does a "continue", we exit this loop immediately after the
9802 switch. */
9803
9804 switch (GET_CODE (op0))
9805 {
9806 case ZERO_EXTRACT:
9807 /* If we are extracting a single bit from a variable position in
9808 a constant that has only a single bit set and are comparing it
9809 with zero, we can convert this into an equality comparison
d7cd794f 9810 between the position and the location of the single bit. */
230d793d 9811
230d793d
RS		 9812 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9813 && XEXP (op0, 1) == const1_rtx
9814 && equality_comparison_p && const_op == 0
d7cd794f 9815 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
230d793d 9816 {
f76b9db2 9817 if (BITS_BIG_ENDIAN)
0d8e55d8 9818 {
d7cd794f 9819#ifdef HAVE_extzv
0d8e55d8
JL		 9820 mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
9821 if (mode == VOIDmode)
9822 mode = word_mode;
9823 i = (GET_MODE_BITSIZE (mode) - 1 - i);
d7cd794f 9824#else
0d8e55d8 9825 i = BITS_PER_WORD - 1 - i;
230d793d 9826#endif
0d8e55d8 9827 }
230d793d
RS		 9828
9829 op0 = XEXP (op0, 2);
5f4f0e22 9830 op1 = GEN_INT (i);
230d793d
RS		 9831 const_op = i;
9832
9833 /* Result is nonzero iff shift count is equal to I. */
9834 code = reverse_condition (code);
9835 continue;
9836 }
230d793d 9837
0f41302f 9838 /* ... fall through ... */
230d793d
RS		 9839
9840 case SIGN_EXTRACT:
9841 tem = expand_compound_operation (op0);
9842 if (tem != op0)
9843 {
9844 op0 = tem;
9845 continue;
9846 }
9847 break;
9848
9849 case NOT:
9850 /* If testing for equality, we can take the NOT of the constant. */
9851 if (equality_comparison_p
9852 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9853 {
9854 op0 = XEXP (op0, 0);
9855 op1 = tem;
9856 continue;
9857 }
9858
9859 /* If just looking at the sign bit, reverse the sense of the
9860 comparison. */
9861 if (sign_bit_comparison_p)
9862 {
9863 op0 = XEXP (op0, 0);
9864 code = (code == GE ? LT : GE);
9865 continue;
9866 }
9867 break;
9868
9869 case NEG:
9870 /* If testing for equality, we can take the NEG of the constant. */
9871 if (equality_comparison_p
9872 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9873 {
9874 op0 = XEXP (op0, 0);
9875 op1 = tem;
9876 continue;
9877 }
9878
9879 /* The remaining cases only apply to comparisons with zero. */
9880 if (const_op != 0)
9881 break;
9882
9883 /* When X is ABS or is known positive,
9884 (neg X) is < 0 if and only if X != 0. */
9885
9886 if (sign_bit_comparison_p
9887 && (GET_CODE (XEXP (op0, 0)) == ABS
5f4f0e22 9888 || (mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9889 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 9890 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
230d793d
RS		 9891 {
9892 op0 = XEXP (op0, 0);
9893 code = (code == LT ? NE : EQ);
9894 continue;
9895 }
9896
3bed8141 9897 /* If we have NEG of something whose two high-order bits are the
0f41302f 9898 same, we know that "(-a) < 0" is equivalent to "a > 0". */
3bed8141 9899 if (num_sign_bit_copies (op0, mode) >= 2)
230d793d
RS		 9900 {
9901 op0 = XEXP (op0, 0);
9902 code = swap_condition (code);
9903 continue;
9904 }
9905 break;
9906
9907 case ROTATE:
9908 /* If we are testing equality and our count is a constant, we
9909 can perform the inverse operation on our RHS. */
9910 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9911 && (tem = simplify_binary_operation (ROTATERT, mode,
9912 op1, XEXP (op0, 1))) != 0)
9913 {
9914 op0 = XEXP (op0, 0);
9915 op1 = tem;
9916 continue;
9917 }
9918
9919 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9920 a particular bit. Convert it to an AND of a constant of that
9921 bit. This will be converted into a ZERO_EXTRACT. */
9922 if (const_op == 0 && sign_bit_comparison_p
9923 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 9924 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 9925 {
5f4f0e22
CH		 9926 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9927 ((HOST_WIDE_INT) 1
9928 << (mode_width - 1
9929 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 9930 code = (code == LT ? NE : EQ);
9931 continue;
9932 }
9933
0f41302f 9934 /* ... fall through ... */
230d793d
RS		 9935
9936 case ABS:
9937 /* ABS is ignorable inside an equality comparison with zero. */
9938 if (const_op == 0 && equality_comparison_p)
9939 {
9940 op0 = XEXP (op0, 0);
9941 continue;
9942 }
9943 break;
9944
9945
9946 case SIGN_EXTEND:
9947 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9948 to (compare FOO CONST) if CONST fits in FOO's mode and we
9949 are either testing inequality or have an unsigned comparison
9950 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9951 if (! unsigned_comparison_p
9952 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9953 <= HOST_BITS_PER_WIDE_INT)
9954 && ((unsigned HOST_WIDE_INT) const_op
e51712db 9955 < (((unsigned HOST_WIDE_INT) 1
5f4f0e22 9956 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
230d793d
RS		 9957 {
9958 op0 = XEXP (op0, 0);
9959 continue;
9960 }
9961 break;
9962
9963 case SUBREG:
a687e897 9964 /* Check for the case where we are comparing A - C1 with C2,
abc95ed3 9965 both constants are smaller than 1/2 the maximum positive
a687e897
RK		 9966 value in MODE, and the comparison is equality or unsigned.
9967 In that case, if A is either zero-extended to MODE or has
9968 sufficient sign bits so that the high-order bit in MODE
9969 is a copy of the sign in the inner mode, we can prove that it is
9970 safe to do the operation in the wider mode. This simplifies
9971 many range checks. */
9972
9973 if (mode_width <= HOST_BITS_PER_WIDE_INT
9974 && subreg_lowpart_p (op0)
9975 && GET_CODE (SUBREG_REG (op0)) == PLUS
9976 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9977 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9978 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
e51712db 9979 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
adb7a1cb 9980 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
951553af
RK		 9981 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9982 GET_MODE (SUBREG_REG (op0)))
a687e897
RK		 9983 & ~ GET_MODE_MASK (mode))
9984 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9985 GET_MODE (SUBREG_REG (op0)))
9986 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9987 - GET_MODE_BITSIZE (mode)))))
9988 {
9989 op0 = SUBREG_REG (op0);
9990 continue;
9991 }
9992
fe0cf571
RK		 9993 /* If the inner mode is narrower and we are extracting the low part,
9994 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9995 if (subreg_lowpart_p (op0)
89f1c7f2
RS		 9996 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9997 /* Fall through */ ;
9998 else
230d793d
RS		 9999 break;
10000
0f41302f 10001 /* ... fall through ... */
230d793d
RS		 10002
10003 case ZERO_EXTEND:
10004 if ((unsigned_comparison_p || equality_comparison_p)
10005 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 10006 <= HOST_BITS_PER_WIDE_INT)
10007 && ((unsigned HOST_WIDE_INT) const_op
230d793d
RS		 10008 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10009 {
10010 op0 = XEXP (op0, 0);
10011 continue;
10012 }
10013 break;
10014
10015 case PLUS:
20fdd649 10016 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
5089e22e 10017 this for equality comparisons due to pathological cases involving
230d793d 10018 overflows. */
20fdd649
RK		 10019 if (equality_comparison_p
10020 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10021 op1, XEXP (op0, 1))))
230d793d
RS		 10022 {
10023 op0 = XEXP (op0, 0);
10024 op1 = tem;
10025 continue;
10026 }
10027
10028 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10029 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10030 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10031 {
10032 op0 = XEXP (XEXP (op0, 0), 0);
10033 code = (code == LT ? EQ : NE);
10034 continue;
10035 }
10036 break;
10037
10038 case MINUS:
20fdd649
RK		 10039 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10040 (eq B (minus A C)), whichever simplifies. We can only do
10041 this for equality comparisons due to pathological cases involving
10042 overflows. */
10043 if (equality_comparison_p
10044 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10045 XEXP (op0, 1), op1)))
10046 {
10047 op0 = XEXP (op0, 0);
10048 op1 = tem;
10049 continue;
10050 }
10051
10052 if (equality_comparison_p
10053 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10054 XEXP (op0, 0), op1)))
10055 {
10056 op0 = XEXP (op0, 1);
10057 op1 = tem;
10058 continue;
10059 }
10060
230d793d
RS		 10061 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10062 of bits in X minus 1, is one iff X > 0. */
10063 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10064 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10065 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10066 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10067 {
10068 op0 = XEXP (op0, 1);
10069 code = (code == GE ? LE : GT);
10070 continue;
10071 }
10072 break;
10073
10074 case XOR:
10075 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10076 if C is zero or B is a constant. */
10077 if (equality_comparison_p
10078 && 0 != (tem = simplify_binary_operation (XOR, mode,
10079 XEXP (op0, 1), op1)))
10080 {
10081 op0 = XEXP (op0, 0);
10082 op1 = tem;
10083 continue;
10084 }
10085 break;
10086
10087 case EQ: case NE:
10088 case LT: case LTU: case LE: case LEU:
10089 case GT: case GTU: case GE: case GEU:
10090 /* We can't do anything if OP0 is a condition code value, rather
10091 than an actual data value. */
10092 if (const_op != 0
10093#ifdef HAVE_cc0
10094 || XEXP (op0, 0) == cc0_rtx
10095#endif
10096 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10097 break;
10098
10099 /* Get the two operands being compared. */
10100 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10101 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10102 else
10103 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10104
10105 /* Check for the cases where we simply want the result of the
10106 earlier test or the opposite of that result. */
10107 if (code == NE
10108 || (code == EQ && reversible_comparison_p (op0))
5f4f0e22 10109 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
3f508eca 10110 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
230d793d 10111 && (STORE_FLAG_VALUE
5f4f0e22
CH		 10112 & (((HOST_WIDE_INT) 1
10113 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
230d793d
RS		 10114 && (code == LT
10115 || (code == GE && reversible_comparison_p (op0)))))
10116 {
10117 code = (code == LT || code == NE
10118 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10119 op0 = tem, op1 = tem1;
10120 continue;
10121 }
10122 break;
10123
10124 case IOR:
10125 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10126 iff X <= 0. */
10127 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10128 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10129 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10130 {
10131 op0 = XEXP (op0, 1);
10132 code = (code == GE ? GT : LE);
10133 continue;
10134 }
10135 break;
10136
10137 case AND:
10138 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10139 will be converted to a ZERO_EXTRACT later. */
10140 if (const_op == 0 && equality_comparison_p
45620ed4 10141 && GET_CODE (XEXP (op0, 0)) == ASHIFT
230d793d
RS		 10142 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10143 {
10144 op0 = simplify_and_const_int
10145 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10146 XEXP (op0, 1),
10147 XEXP (XEXP (op0, 0), 1)),
5f4f0e22 10148 (HOST_WIDE_INT) 1);
230d793d
RS		 10149 continue;
10150 }
10151
10152 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10153 zero and X is a comparison and C1 and C2 describe only bits set
10154 in STORE_FLAG_VALUE, we can compare with X. */
10155 if (const_op == 0 && equality_comparison_p
5f4f0e22 10156 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 10157 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10158 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10159 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10160 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
5f4f0e22 10161 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 10162 {
10163 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10164 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10165 if ((~ STORE_FLAG_VALUE & mask) == 0
10166 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10167 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10168 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10169 {
10170 op0 = XEXP (XEXP (op0, 0), 0);
10171 continue;
10172 }
10173 }
10174
10175 /* If we are doing an equality comparison of an AND of a bit equal
10176 to the sign bit, replace this with a LT or GE comparison of
10177 the underlying value. */
10178 if (equality_comparison_p
10179 && const_op == 0
10180 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10181 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 10182 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
e51712db 10183 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
230d793d
RS		 10184 {
10185 op0 = XEXP (op0, 0);
10186 code = (code == EQ ? GE : LT);
10187 continue;
10188 }
10189
10190 /* If this AND operation is really a ZERO_EXTEND from a narrower
10191 mode, the constant fits within that mode, and this is either an
10192 equality or unsigned comparison, try to do this comparison in
10193 the narrower mode. */
10194 if ((equality_comparison_p || unsigned_comparison_p)
10195 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10196 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10197 & GET_MODE_MASK (mode))
10198 + 1)) >= 0
10199 && const_op >> i == 0
10200 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10201 {
10202 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10203 continue;
10204 }
e5e809f4
JL		 10205
10206 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10207 in both M1 and M2 and the SUBREG is either paradoxical or
10208 represents the low part, permute the SUBREG and the AND and
10209 try again. */
10210 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10211 && ((mode_width
10212 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
9ec36da5
JL		 10213#ifdef WORD_REGISTER_OPERATIONS
10214 || subreg_lowpart_p (XEXP (op0, 0))
10215#endif
10216 )
adc05e6c
JL		 10217#ifndef WORD_REGISTER_OPERATIONS
10218 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10219 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10220 As originally written the upper bits have a defined value
10221 due to the AND operation. However, if we commute the AND
10222 inside the SUBREG then they no longer have defined values
10223 and the meaning of the code has been changed. */
10224 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10225 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10226#endif
e5e809f4
JL		 10227 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10228 && mode_width <= HOST_BITS_PER_WIDE_INT
10229 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10230 <= HOST_BITS_PER_WIDE_INT)
10231 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10232 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
9ec36da5 10233 & INTVAL (XEXP (op0, 1)))
e51712db
KG		 10234 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10235 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
9ec36da5 10236 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
e5e809f4
JL		 10237
10238 {
10239 op0
10240 = gen_lowpart_for_combine
10241 (mode,
10242 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10243 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10244 continue;
10245 }
10246
230d793d
RS		 10247 break;
10248
10249 case ASHIFT:
45620ed4 10250 /* If we have (compare (ashift FOO N) (const_int C)) and
230d793d 10251 the high order N bits of FOO (N+1 if an inequality comparison)
951553af 10252 are known to be zero, we can do this by comparing FOO with C
230d793d
RS		 10253 shifted right N bits so long as the low-order N bits of C are
10254 zero. */
10255 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10256 && INTVAL (XEXP (op0, 1)) >= 0
10257 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
5f4f0e22
CH		 10258 < HOST_BITS_PER_WIDE_INT)
10259 && ((const_op
34785d05 10260 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
5f4f0e22 10261 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10262 && (nonzero_bits (XEXP (op0, 0), mode)
230d793d
RS		 10263 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10264 + ! equality_comparison_p))) == 0)
10265 {
10266 const_op >>= INTVAL (XEXP (op0, 1));
5f4f0e22 10267 op1 = GEN_INT (const_op);
230d793d
RS		 10268 op0 = XEXP (op0, 0);
10269 continue;
10270 }
10271
dfbe1b2f 10272 /* If we are doing a sign bit comparison, it means we are testing
230d793d 10273 a particular bit. Convert it to the appropriate AND. */
dfbe1b2f 10274 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10275 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 10276 {
5f4f0e22
CH		 10277 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10278 ((HOST_WIDE_INT) 1
10279 << (mode_width - 1
10280 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 10281 code = (code == LT ? NE : EQ);
10282 continue;
10283 }
dfbe1b2f
RK		 10284
10285 /* If this an equality comparison with zero and we are shifting
10286 the low bit to the sign bit, we can convert this to an AND of the
10287 low-order bit. */
10288 if (const_op == 0 && equality_comparison_p
10289 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10290 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10291 {
5f4f0e22
CH		 10292 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10293 (HOST_WIDE_INT) 1);
dfbe1b2f
RK		 10294 continue;
10295 }
230d793d
RS		 10296 break;
10297
10298 case ASHIFTRT:
d0ab8cd3
RK		 10299 /* If this is an equality comparison with zero, we can do this
10300 as a logical shift, which might be much simpler. */
10301 if (equality_comparison_p && const_op == 0
10302 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10303 {
10304 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10305 XEXP (op0, 0),
10306 INTVAL (XEXP (op0, 1)));
10307 continue;
10308 }
10309
230d793d
RS		 10310 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10311 do the comparison in a narrower mode. */
10312 if (! unsigned_comparison_p
10313 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10314 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10315 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10316 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
22331794 10317 MODE_INT, 1)) != BLKmode
5f4f0e22
CH		 10318 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10319 || ((unsigned HOST_WIDE_INT) - const_op
10320 <= GET_MODE_MASK (tmode))))
230d793d
RS		 10321 {
10322 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10323 continue;
10324 }
10325
0f41302f 10326 /* ... fall through ... */
230d793d
RS		 10327 case LSHIFTRT:
10328 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
951553af 10329 the low order N bits of FOO are known to be zero, we can do this
230d793d
RS		 10330 by comparing FOO with C shifted left N bits so long as no
10331 overflow occurs. */
10332 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10333 && INTVAL (XEXP (op0, 1)) >= 0
5f4f0e22
CH		 10334 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10335 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10336 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 10337 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
230d793d
RS		 10338 && (const_op == 0
10339 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10340 < mode_width)))
10341 {
10342 const_op <<= INTVAL (XEXP (op0, 1));
5f4f0e22 10343 op1 = GEN_INT (const_op);
230d793d
RS		 10344 op0 = XEXP (op0, 0);
10345 continue;
10346 }
10347
10348 /* If we are using this shift to extract just the sign bit, we
10349 can replace this with an LT or GE comparison. */
10350 if (const_op == 0
10351 && (equality_comparison_p || sign_bit_comparison_p)
10352 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10353 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10354 {
10355 op0 = XEXP (op0, 0);
10356 code = (code == NE || code == GT ? LT : GE);
10357 continue;
10358 }
10359 break;
e9a25f70
JL		 10360
10361 default:
10362 break;
230d793d
RS		 10363 }
10364
10365 break;
10366 }
10367
10368 /* Now make any compound operations involved in this comparison. Then,
76d31c63 10369 check for an outmost SUBREG on OP0 that is not doing anything or is
230d793d
RS		 10370 paradoxical. The latter case can only occur when it is known that the
10371 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10372 We can never remove a SUBREG for a non-equality comparison because the
10373 sign bit is in a different place in the underlying object. */
10374
10375 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10376 op1 = make_compound_operation (op1, SET);
10377
10378 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10379 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10380 && (code == NE || code == EQ)
10381 && ((GET_MODE_SIZE (GET_MODE (op0))
10382 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10383 {
10384 op0 = SUBREG_REG (op0);
10385 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10386 }
10387
10388 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10389 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10390 && (code == NE || code == EQ)
ac49a949
RS		 10391 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10392 <= HOST_BITS_PER_WIDE_INT)
951553af 10393 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10394 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10395 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10396 op1),
951553af 10397 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10398 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10399 op0 = SUBREG_REG (op0), op1 = tem;
10400
10401 /* We now do the opposite procedure: Some machines don't have compare
10402 insns in all modes. If OP0's mode is an integer mode smaller than a
10403 word and we can't do a compare in that mode, see if there is a larger
a687e897
RK		 10404 mode for which we can do the compare. There are a number of cases in
10405 which we can use the wider mode. */
230d793d
RS		 10406
10407 mode = GET_MODE (op0);
10408 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10409 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10410 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10411 for (tmode = GET_MODE_WIDER_MODE (mode);
5f4f0e22
CH		 10412 (tmode != VOIDmode
10413 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
230d793d 10414 tmode = GET_MODE_WIDER_MODE (tmode))
a687e897 10415 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
230d793d 10416 {
951553af 10417 /* If the only nonzero bits in OP0 and OP1 are those in the
a687e897
RK		 10418 narrower mode and this is an equality or unsigned comparison,
10419 we can use the wider mode. Similarly for sign-extended
7e4dc511 10420 values, in which case it is true for all comparisons. */
a687e897
RK		 10421 if (((code == EQ || code == NE
10422 || code == GEU || code == GTU || code == LEU || code == LTU)
951553af
RK		 10423 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10424 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
7e4dc511
RK		 10425 || ((num_sign_bit_copies (op0, tmode)
10426 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
a687e897 10427 && (num_sign_bit_copies (op1, tmode)
58744483 10428 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
a687e897
RK		 10429 {
10430 op0 = gen_lowpart_for_combine (tmode, op0);
10431 op1 = gen_lowpart_for_combine (tmode, op1);
10432 break;
10433 }
230d793d 10434
a687e897
RK		 10435 /* If this is a test for negative, we can make an explicit
10436 test of the sign bit. */
10437
10438 if (op1 == const0_rtx && (code == LT || code == GE)
10439 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d 10440 {
a687e897
RK		 10441 op0 = gen_binary (AND, tmode,
10442 gen_lowpart_for_combine (tmode, op0),
5f4f0e22
CH		 10443 GEN_INT ((HOST_WIDE_INT) 1
10444 << (GET_MODE_BITSIZE (mode) - 1)));
230d793d 10445 code = (code == LT) ? NE : EQ;
a687e897 10446 break;
230d793d 10447 }
230d793d
RS		 10448 }
10449
b7a775b2
RK		 10450#ifdef CANONICALIZE_COMPARISON
10451 /* If this machine only supports a subset of valid comparisons, see if we
10452 can convert an unsupported one into a supported one. */
10453 CANONICALIZE_COMPARISON (code, op0, op1);
10454#endif
10455
230d793d
RS		 10456 *pop0 = op0;
10457 *pop1 = op1;
10458
10459 return code;
10460}
10461\f
10462/* Return 1 if we know that X, a comparison operation, is not operating
10463 on a floating-point value or is EQ or NE, meaning that we can safely
10464 reverse it. */
10465
10466static int
10467reversible_comparison_p (x)
10468 rtx x;
10469{
10470 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e 10471 || flag_fast_math
230d793d
RS		 10472 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10473 return 1;
10474
10475 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10476 {
10477 case MODE_INT:
3ad2180a
RK		 10478 case MODE_PARTIAL_INT:
10479 case MODE_COMPLEX_INT:
230d793d
RS		 10480 return 1;
10481
10482 case MODE_CC:
9210df58
RK		 10483 /* If the mode of the condition codes tells us that this is safe,
10484 we need look no further. */
10485 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10486 return 1;
10487
10488 /* Otherwise try and find where the condition codes were last set and
10489 use that. */
230d793d
RS		 10490 x = get_last_value (XEXP (x, 0));
10491 return (x && GET_CODE (x) == COMPARE
3ad2180a 10492 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
e9a25f70
JL		 10493
10494 default:
10495 return 0;
230d793d 10496 }
230d793d
RS		 10497}
10498\f
10499/* Utility function for following routine. Called when X is part of a value
10500 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10501 for each register mentioned. Similar to mention_regs in cse.c */
10502
10503static void
10504update_table_tick (x)
10505 rtx x;
10506{
10507 register enum rtx_code code = GET_CODE (x);
6f7d635c 10508 register const char *fmt = GET_RTX_FORMAT (code);
230d793d
RS		 10509 register int i;
10510
10511 if (code == REG)
10512 {
10513 int regno = REGNO (x);
10514 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10515 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10516
10517 for (i = regno; i < endregno; i++)
10518 reg_last_set_table_tick[i] = label_tick;
10519
10520 return;
10521 }
10522
10523 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10524 /* Note that we can't have an "E" in values stored; see
10525 get_last_value_validate. */
10526 if (fmt[i] == 'e')
10527 update_table_tick (XEXP (x, i));
10528}
10529
10530/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10531 are saying that the register is clobbered and we no longer know its
7988fd36
RK		 10532 value. If INSN is zero, don't update reg_last_set; this is only permitted
10533 with VALUE also zero and is used to invalidate the register. */
230d793d
RS		 10534
10535static void
10536record_value_for_reg (reg, insn, value)
10537 rtx reg;
10538 rtx insn;
10539 rtx value;
10540{
10541 int regno = REGNO (reg);
10542 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10543 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10544 int i;
10545
10546 /* If VALUE contains REG and we have a previous value for REG, substitute
10547 the previous value. */
10548 if (value && insn && reg_overlap_mentioned_p (reg, value))
10549 {
10550 rtx tem;
10551
10552 /* Set things up so get_last_value is allowed to see anything set up to
10553 our insn. */
10554 subst_low_cuid = INSN_CUID (insn);
10555 tem = get_last_value (reg);
10556
10557 if (tem)
10558 value = replace_rtx (copy_rtx (value), reg, tem);
10559 }
10560
10561 /* For each register modified, show we don't know its value, that
ef026f91
RS		 10562 we don't know about its bitwise content, that its value has been
10563 updated, and that we don't know the location of the death of the
10564 register. */
230d793d
RS		 10565 for (i = regno; i < endregno; i ++)
10566 {
10567 if (insn)
10568 reg_last_set[i] = insn;
10569 reg_last_set_value[i] = 0;
ef026f91
RS		 10570 reg_last_set_mode[i] = 0;
10571 reg_last_set_nonzero_bits[i] = 0;
10572 reg_last_set_sign_bit_copies[i] = 0;
230d793d
RS		 10573 reg_last_death[i] = 0;
10574 }
10575
10576 /* Mark registers that are being referenced in this value. */
10577 if (value)
10578 update_table_tick (value);
10579
10580 /* Now update the status of each register being set.
10581 If someone is using this register in this block, set this register
10582 to invalid since we will get confused between the two lives in this
10583 basic block. This makes using this register always invalid. In cse, we
10584 scan the table to invalidate all entries using this register, but this
10585 is too much work for us. */
10586
10587 for (i = regno; i < endregno; i++)
10588 {
10589 reg_last_set_label[i] = label_tick;
10590 if (value && reg_last_set_table_tick[i] == label_tick)
10591 reg_last_set_invalid[i] = 1;
10592 else
10593 reg_last_set_invalid[i] = 0;
10594 }
10595
10596 /* The value being assigned might refer to X (like in "x++;"). In that
10597 case, we must replace it with (clobber (const_int 0)) to prevent
10598 infinite loops. */
9a893315 10599 if (value && ! get_last_value_validate (&value, insn,
230d793d
RS		 10600 reg_last_set_label[regno], 0))
10601 {
10602 value = copy_rtx (value);
9a893315
JW		 10603 if (! get_last_value_validate (&value, insn,
10604 reg_last_set_label[regno], 1))
230d793d
RS		 10605 value = 0;
10606 }
10607
55310dad
RK		 10608 /* For the main register being modified, update the value, the mode, the
10609 nonzero bits, and the number of sign bit copies. */
10610
230d793d
RS		 10611 reg_last_set_value[regno] = value;
10612
55310dad
RK		 10613 if (value)
10614 {
2afabb48 10615 subst_low_cuid = INSN_CUID (insn);
55310dad
RK		 10616 reg_last_set_mode[regno] = GET_MODE (reg);
10617 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10618 reg_last_set_sign_bit_copies[regno]
10619 = num_sign_bit_copies (value, GET_MODE (reg));
10620 }
230d793d
RS		 10621}
10622
10623/* Used for communication between the following two routines. */
10624static rtx record_dead_insn;
10625
10626/* Called via note_stores from record_dead_and_set_regs to handle one
10627 SET or CLOBBER in an insn. */
10628
10629static void
10630record_dead_and_set_regs_1 (dest, setter)
10631 rtx dest, setter;
10632{
ca89d290
RK		 10633 if (GET_CODE (dest) == SUBREG)
10634 dest = SUBREG_REG (dest);
10635
230d793d
RS		 10636 if (GET_CODE (dest) == REG)
10637 {
10638 /* If we are setting the whole register, we know its value. Otherwise
10639 show that we don't know the value. We can handle SUBREG in
10640 some cases. */
10641 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10642 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10643 else if (GET_CODE (setter) == SET
10644 && GET_CODE (SET_DEST (setter)) == SUBREG
10645 && SUBREG_REG (SET_DEST (setter)) == dest
90bf8081 10646 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
230d793d 10647 && subreg_lowpart_p (SET_DEST (setter)))
d0ab8cd3
RK		 10648 record_value_for_reg (dest, record_dead_insn,
10649 gen_lowpart_for_combine (GET_MODE (dest),
10650 SET_SRC (setter)));
230d793d 10651 else
5f4f0e22 10652 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
230d793d
RS		 10653 }
10654 else if (GET_CODE (dest) == MEM
10655 /* Ignore pushes, they clobber nothing. */
10656 && ! push_operand (dest, GET_MODE (dest)))
10657 mem_last_set = INSN_CUID (record_dead_insn);
10658}
10659
10660/* Update the records of when each REG was most recently set or killed
10661 for the things done by INSN. This is the last thing done in processing
10662 INSN in the combiner loop.
10663
ef026f91
RS		 10664 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10665 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10666 and also the similar information mem_last_set (which insn most recently
10667 modified memory) and last_call_cuid (which insn was the most recent
10668 subroutine call). */
230d793d
RS		 10669
10670static void
10671record_dead_and_set_regs (insn)
10672 rtx insn;
10673{
10674 register rtx link;
55310dad
RK		 10675 int i;
10676
230d793d
RS		 10677 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10678 {
dbc131f3
RK		 10679 if (REG_NOTE_KIND (link) == REG_DEAD
10680 && GET_CODE (XEXP (link, 0)) == REG)
10681 {
10682 int regno = REGNO (XEXP (link, 0));
10683 int endregno
10684 = regno + (regno < FIRST_PSEUDO_REGISTER
10685 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10686 : 1);
dbc131f3
RK		 10687
10688 for (i = regno; i < endregno; i++)
10689 reg_last_death[i] = insn;
10690 }
230d793d 10691 else if (REG_NOTE_KIND (link) == REG_INC)
5f4f0e22 10692 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
230d793d
RS		 10693 }
10694
10695 if (GET_CODE (insn) == CALL_INSN)
55310dad
RK		 10696 {
10697 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10698 if (call_used_regs[i])
10699 {
10700 reg_last_set_value[i] = 0;
ef026f91
RS		 10701 reg_last_set_mode[i] = 0;
10702 reg_last_set_nonzero_bits[i] = 0;
10703 reg_last_set_sign_bit_copies[i] = 0;
55310dad
RK		 10704 reg_last_death[i] = 0;
10705 }
10706
10707 last_call_cuid = mem_last_set = INSN_CUID (insn);
10708 }
230d793d
RS		 10709
10710 record_dead_insn = insn;
10711 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10712}
10713\f
10714/* Utility routine for the following function. Verify that all the registers
10715 mentioned in *LOC are valid when *LOC was part of a value set when
10716 label_tick == TICK. Return 0 if some are not.
10717
10718 If REPLACE is non-zero, replace the invalid reference with
10719 (clobber (const_int 0)) and return 1. This replacement is useful because
10720 we often can get useful information about the form of a value (e.g., if
10721 it was produced by a shift that always produces -1 or 0) even though
10722 we don't know exactly what registers it was produced from. */
10723
10724static int
9a893315 10725get_last_value_validate (loc, insn, tick, replace)
230d793d 10726 rtx *loc;
9a893315 10727 rtx insn;
230d793d
RS		 10728 int tick;
10729 int replace;
10730{
10731 rtx x = *loc;
6f7d635c 10732 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
230d793d
RS		 10733 int len = GET_RTX_LENGTH (GET_CODE (x));
10734 int i;
10735
10736 if (GET_CODE (x) == REG)
10737 {
10738 int regno = REGNO (x);
10739 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10740 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10741 int j;
10742
10743 for (j = regno; j < endregno; j++)
10744 if (reg_last_set_invalid[j]
57cf50a4
GRK		 10745 /* If this is a pseudo-register that was only set once and not
10746 live at the beginning of the function, it is always valid. */
10747 || (! (regno >= FIRST_PSEUDO_REGISTER
10748 && REG_N_SETS (regno) == 1
10749 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
230d793d
RS		 10750 && reg_last_set_label[j] > tick))
10751 {
10752 if (replace)
38a448ca 10753 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 10754 return replace;
10755 }
10756
10757 return 1;
10758 }
9a893315
JW		 10759 /* If this is a memory reference, make sure that there were
10760 no stores after it that might have clobbered the value. We don't
10761 have alias info, so we assume any store invalidates it. */
10762 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10763 && INSN_CUID (insn) <= mem_last_set)
10764 {
10765 if (replace)
38a448ca 10766 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9a893315
JW		 10767 return replace;
10768 }
230d793d
RS		 10769
10770 for (i = 0; i < len; i++)
10771 if ((fmt[i] == 'e'
9a893315 10772 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
230d793d
RS		 10773 /* Don't bother with these. They shouldn't occur anyway. */
10774 || fmt[i] == 'E')
10775 return 0;
10776
10777 /* If we haven't found a reason for it to be invalid, it is valid. */
10778 return 1;
10779}
10780
10781/* Get the last value assigned to X, if known. Some registers
10782 in the value may be replaced with (clobber (const_int 0)) if their value
10783 is known longer known reliably. */
10784
10785static rtx
10786get_last_value (x)
10787 rtx x;
10788{
10789 int regno;
10790 rtx value;
10791
10792 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10793 then convert it to the desired mode. If this is a paradoxical SUBREG,
0f41302f 10794 we cannot predict what values the "extra" bits might have. */
230d793d
RS		 10795 if (GET_CODE (x) == SUBREG
10796 && subreg_lowpart_p (x)
10797 && (GET_MODE_SIZE (GET_MODE (x))
10798 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10799 && (value = get_last_value (SUBREG_REG (x))) != 0)
10800 return gen_lowpart_for_combine (GET_MODE (x), value);
10801
10802 if (GET_CODE (x) != REG)
10803 return 0;
10804
10805 regno = REGNO (x);
10806 value = reg_last_set_value[regno];
10807
57cf50a4
GRK		 10808 /* If we don't have a value, or if it isn't for this basic block and
10809 it's either a hard register, set more than once, or it's a live
10810 at the beginning of the function, return 0.
10811
10812 Because if it's not live at the beginnning of the function then the reg
10813 is always set before being used (is never used without being set).
10814 And, if it's set only once, and it's always set before use, then all
10815 uses must have the same last value, even if it's not from this basic
10816 block. */
230d793d
RS		 10817
10818 if (value == 0
57cf50a4
GRK		 10819 || (reg_last_set_label[regno] != label_tick
10820 && (regno < FIRST_PSEUDO_REGISTER
10821 || REG_N_SETS (regno) != 1
10822 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
230d793d
RS		 10823 return 0;
10824
4255220d 10825 /* If the value was set in a later insn than the ones we are processing,
4090a6b3
RK		 10826 we can't use it even if the register was only set once, but make a quick
10827 check to see if the previous insn set it to something. This is commonly
0d9641d1
JW		 10828 the case when the same pseudo is used by repeated insns.
10829
10830 This does not work if there exists an instruction which is temporarily
10831 not on the insn chain. */
d0ab8cd3 10832
bcd49eb7 10833 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
d0ab8cd3
RK		 10834 {
10835 rtx insn, set;
10836
6c1b3bf2
BS		 10837 /* We can't do anything if the value is set in between the insns we are
10838 processing. */
10839 if (INSN_CUID (reg_last_set[regno]) <= INSN_CUID (subst_insn))
10840 return 0;
10841
bcd49eb7
JW		 10842 /* We can not do anything useful in this case, because there is
10843 an instruction which is not on the insn chain. */
10844 if (subst_prev_insn)
10845 return 0;
10846
4255220d
JW		 10847 /* Skip over USE insns. They are not useful here, and they may have
10848 been made by combine, in which case they do not have a INSN_CUID
d6c80562 10849 value. We can't use prev_real_insn, because that would incorrectly
e340018d
JW		 10850 take us backwards across labels. Skip over BARRIERs also, since
10851 they could have been made by combine. If we see one, we must be
10852 optimizing dead code, so it doesn't matter what we do. */
d6c80562
JW		 10853 for (insn = prev_nonnote_insn (subst_insn);
10854 insn && ((GET_CODE (insn) == INSN
10855 && GET_CODE (PATTERN (insn)) == USE)
e340018d 10856 || GET_CODE (insn) == BARRIER
4255220d 10857 || INSN_CUID (insn) >= subst_low_cuid);
d6c80562 10858 insn = prev_nonnote_insn (insn))
3adde2a5 10859 ;
d0ab8cd3
RK		 10860
10861 if (insn
10862 && (set = single_set (insn)) != 0
10863 && rtx_equal_p (SET_DEST (set), x))
10864 {
10865 value = SET_SRC (set);
10866
10867 /* Make sure that VALUE doesn't reference X. Replace any
ddd5a7c1 10868 explicit references with a CLOBBER. If there are any remaining
d0ab8cd3
RK		 10869 references (rare), don't use the value. */
10870
10871 if (reg_mentioned_p (x, value))
10872 value = replace_rtx (copy_rtx (value), x,
38a448ca 10873 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
d0ab8cd3
RK		 10874
10875 if (reg_overlap_mentioned_p (x, value))
10876 return 0;
10877 }
10878 else
10879 return 0;
10880 }
10881
10882 /* If the value has all its registers valid, return it. */
9a893315
JW		 10883 if (get_last_value_validate (&value, reg_last_set[regno],
10884 reg_last_set_label[regno], 0))
230d793d
RS		 10885 return value;
10886
10887 /* Otherwise, make a copy and replace any invalid register with
10888 (clobber (const_int 0)). If that fails for some reason, return 0. */
10889
10890 value = copy_rtx (value);
9a893315
JW		 10891 if (get_last_value_validate (&value, reg_last_set[regno],
10892 reg_last_set_label[regno], 1))
230d793d
RS		 10893 return value;
10894
10895 return 0;
10896}
10897\f
10898/* Return nonzero if expression X refers to a REG or to memory
10899 that is set in an instruction more recent than FROM_CUID. */
10900
10901static int
10902use_crosses_set_p (x, from_cuid)
10903 register rtx x;
10904 int from_cuid;
10905{
6f7d635c 10906 register const char *fmt;
230d793d
RS		 10907 register int i;
10908 register enum rtx_code code = GET_CODE (x);
10909
10910 if (code == REG)
10911 {
10912 register int regno = REGNO (x);
e28f5732
RK		 10913 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10914 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10915
230d793d
RS		 10916#ifdef PUSH_ROUNDING
10917 /* Don't allow uses of the stack pointer to be moved,
10918 because we don't know whether the move crosses a push insn. */
10919 if (regno == STACK_POINTER_REGNUM)
10920 return 1;
10921#endif
e28f5732
RK		 10922 for (;regno < endreg; regno++)
10923 if (reg_last_set[regno]
10924 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10925 return 1;
10926 return 0;
230d793d
RS		 10927 }
10928
10929 if (code == MEM && mem_last_set > from_cuid)
10930 return 1;
10931
10932 fmt = GET_RTX_FORMAT (code);
10933
10934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10935 {
10936 if (fmt[i] == 'E')
10937 {
10938 register int j;
10939 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10940 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10941 return 1;
10942 }
10943 else if (fmt[i] == 'e'
10944 && use_crosses_set_p (XEXP (x, i), from_cuid))
10945 return 1;
10946 }
10947 return 0;
10948}
10949\f
10950/* Define three variables used for communication between the following
10951 routines. */
10952
10953static int reg_dead_regno, reg_dead_endregno;
10954static int reg_dead_flag;
10955
10956/* Function called via note_stores from reg_dead_at_p.
10957
ddd5a7c1 10958 If DEST is within [reg_dead_regno, reg_dead_endregno), set
230d793d
RS		 10959 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10960
10961static void
10962reg_dead_at_p_1 (dest, x)
10963 rtx dest;
10964 rtx x;
10965{
10966 int regno, endregno;
10967
10968 if (GET_CODE (dest) != REG)
10969 return;
10970
10971 regno = REGNO (dest);
10972 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10973 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10974
10975 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10976 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10977}
10978
10979/* Return non-zero if REG is known to be dead at INSN.
10980
10981 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10982 referencing REG, it is dead. If we hit a SET referencing REG, it is
10983 live. Otherwise, see if it is live or dead at the start of the basic
6e25d159
RK		 10984 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10985 must be assumed to be always live. */
230d793d
RS		 10986
10987static int
10988reg_dead_at_p (reg, insn)
10989 rtx reg;
10990 rtx insn;
10991{
10992 int block, i;
10993
10994 /* Set variables for reg_dead_at_p_1. */
10995 reg_dead_regno = REGNO (reg);
10996 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10997 ? HARD_REGNO_NREGS (reg_dead_regno,
10998 GET_MODE (reg))
10999 : 1);
11000
11001 reg_dead_flag = 0;
11002
6e25d159
RK		 11003 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11004 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11005 {
11006 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11007 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11008 return 0;
11009 }
11010
230d793d
RS		 11011 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11012 beginning of function. */
60715d0b 11013 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
230d793d
RS		 11014 insn = prev_nonnote_insn (insn))
11015 {
11016 note_stores (PATTERN (insn), reg_dead_at_p_1);
11017 if (reg_dead_flag)
11018 return reg_dead_flag == 1 ? 1 : 0;
11019
11020 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11021 return 1;
11022 }
11023
11024 /* Get the basic block number that we were in. */
11025 if (insn == 0)
11026 block = 0;
11027 else
11028 {
11029 for (block = 0; block < n_basic_blocks; block++)
3b413743 11030 if (insn == BLOCK_HEAD (block))
230d793d
RS		 11031 break;
11032
11033 if (block == n_basic_blocks)
11034 return 0;
11035 }
11036
11037 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
e881bb1b 11038 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
230d793d
RS		 11039 return 0;
11040
11041 return 1;
11042}
6e25d159
RK		 11043\f
11044/* Note hard registers in X that are used. This code is similar to
11045 that in flow.c, but much simpler since we don't care about pseudos. */
11046
11047static void
11048mark_used_regs_combine (x)
11049 rtx x;
11050{
11051 register RTX_CODE code = GET_CODE (x);
11052 register int regno;
11053 int i;
11054
11055 switch (code)
11056 {
11057 case LABEL_REF:
11058 case SYMBOL_REF:
11059 case CONST_INT:
11060 case CONST:
11061 case CONST_DOUBLE:
11062 case PC:
11063 case ADDR_VEC:
11064 case ADDR_DIFF_VEC:
11065 case ASM_INPUT:
11066#ifdef HAVE_cc0
11067 /* CC0 must die in the insn after it is set, so we don't need to take
11068 special note of it here. */
11069 case CC0:
11070#endif
11071 return;
11072
11073 case CLOBBER:
11074 /* If we are clobbering a MEM, mark any hard registers inside the
11075 address as used. */
11076 if (GET_CODE (XEXP (x, 0)) == MEM)
11077 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11078 return;
11079
11080 case REG:
11081 regno = REGNO (x);
11082 /* A hard reg in a wide mode may really be multiple registers.
11083 If so, mark all of them just like the first. */
11084 if (regno < FIRST_PSEUDO_REGISTER)
11085 {
11086 /* None of this applies to the stack, frame or arg pointers */
11087 if (regno == STACK_POINTER_REGNUM
11088#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11089 || regno == HARD_FRAME_POINTER_REGNUM
11090#endif
11091#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11092 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11093#endif
11094 || regno == FRAME_POINTER_REGNUM)
11095 return;
11096
11097 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11098 while (i-- > 0)
11099 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11100 }
11101 return;
11102
11103 case SET:
11104 {
11105 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11106 the address. */
11107 register rtx testreg = SET_DEST (x);
11108
e048778f
RK		 11109 while (GET_CODE (testreg) == SUBREG
11110 || GET_CODE (testreg) == ZERO_EXTRACT
11111 || GET_CODE (testreg) == SIGN_EXTRACT
11112 || GET_CODE (testreg) == STRICT_LOW_PART)
6e25d159
RK		 11113 testreg = XEXP (testreg, 0);
11114
11115 if (GET_CODE (testreg) == MEM)
11116 mark_used_regs_combine (XEXP (testreg, 0));
11117
11118 mark_used_regs_combine (SET_SRC (x));
6e25d159 11119 }
e9a25f70
JL		 11120 return;
11121
11122 default:
11123 break;
6e25d159
RK		 11124 }
11125
11126 /* Recursively scan the operands of this expression. */
11127
11128 {
6f7d635c 11129 register const char *fmt = GET_RTX_FORMAT (code);
6e25d159
RK		 11130
11131 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11132 {
11133 if (fmt[i] == 'e')
11134 mark_used_regs_combine (XEXP (x, i));
11135 else if (fmt[i] == 'E')
11136 {
11137 register int j;
11138
11139 for (j = 0; j < XVECLEN (x, i); j++)
11140 mark_used_regs_combine (XVECEXP (x, i, j));
11141 }
11142 }
11143 }
11144}
11145
230d793d
RS		 11146\f
11147/* Remove register number REGNO from the dead registers list of INSN.
11148
11149 Return the note used to record the death, if there was one. */
11150
11151rtx
11152remove_death (regno, insn)
11153 int regno;
11154 rtx insn;
11155{
11156 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11157
11158 if (note)
1a26b032 11159 {
b1f21e0a 11160 REG_N_DEATHS (regno)--;
1a26b032
RK		 11161 remove_note (insn, note);
11162 }
230d793d
RS		 11163
11164 return note;
11165}
11166
11167/* For each register (hardware or pseudo) used within expression X, if its
11168 death is in an instruction with cuid between FROM_CUID (inclusive) and
11169 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11170 list headed by PNOTES.
11171
6eb12cef
RK		 11172 That said, don't move registers killed by maybe_kill_insn.
11173
230d793d
RS		 11174 This is done when X is being merged by combination into TO_INSN. These
11175 notes will then be distributed as needed. */
11176
11177static void
6eb12cef 11178move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
230d793d 11179 rtx x;
6eb12cef 11180 rtx maybe_kill_insn;
230d793d
RS		 11181 int from_cuid;
11182 rtx to_insn;
11183 rtx *pnotes;
11184{
6f7d635c 11185 register const char *fmt;
230d793d
RS		 11186 register int len, i;
11187 register enum rtx_code code = GET_CODE (x);
11188
11189 if (code == REG)
11190 {
11191 register int regno = REGNO (x);
11192 register rtx where_dead = reg_last_death[regno];
e340018d
JW		 11193 register rtx before_dead, after_dead;
11194
6eb12cef
RK		 11195 /* Don't move the register if it gets killed in between from and to */
11196 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11197 && !reg_referenced_p (x, maybe_kill_insn))
11198 return;
11199
e340018d
JW		 11200 /* WHERE_DEAD could be a USE insn made by combine, so first we
11201 make sure that we have insns with valid INSN_CUID values. */
11202 before_dead = where_dead;
11203 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11204 before_dead = PREV_INSN (before_dead);
11205 after_dead = where_dead;
11206 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11207 after_dead = NEXT_INSN (after_dead);
11208
11209 if (before_dead && after_dead
11210 && INSN_CUID (before_dead) >= from_cuid
11211 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11212 || (where_dead != after_dead
11213 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
230d793d 11214 {
dbc131f3 11215 rtx note = remove_death (regno, where_dead);
230d793d
RS		 11216
11217 /* It is possible for the call above to return 0. This can occur
11218 when reg_last_death points to I2 or I1 that we combined with.
dbc131f3
RK		 11219 In that case make a new note.
11220
11221 We must also check for the case where X is a hard register
11222 and NOTE is a death note for a range of hard registers
11223 including X. In that case, we must put REG_DEAD notes for
11224 the remaining registers in place of NOTE. */
11225
11226 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11227 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
24e46fc4 11228 > GET_MODE_SIZE (GET_MODE (x))))
dbc131f3
RK		 11229 {
11230 int deadregno = REGNO (XEXP (note, 0));
11231 int deadend
11232 = (deadregno + HARD_REGNO_NREGS (deadregno,
11233 GET_MODE (XEXP (note, 0))));
11234 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11235 int i;
11236
11237 for (i = deadregno; i < deadend; i++)
11238 if (i < regno || i >= ourend)
11239 REG_NOTES (where_dead)
38a448ca
RH		 11240 = gen_rtx_EXPR_LIST (REG_DEAD,
11241 gen_rtx_REG (reg_raw_mode[i], i),
11242 REG_NOTES (where_dead));
dbc131f3 11243 }
24e46fc4
JW		 11244 /* If we didn't find any note, or if we found a REG_DEAD note that
11245 covers only part of the given reg, and we have a multi-reg hard
fabd69e8
RK		 11246 register, then to be safe we must check for REG_DEAD notes
11247 for each register other than the first. They could have
11248 their own REG_DEAD notes lying around. */
24e46fc4
JW		 11249 else if ((note == 0
11250 || (note != 0
11251 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11252 < GET_MODE_SIZE (GET_MODE (x)))))
11253 && regno < FIRST_PSEUDO_REGISTER
fabd69e8
RK		 11254 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11255 {
11256 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
24e46fc4 11257 int i, offset;
fabd69e8
RK		 11258 rtx oldnotes = 0;
11259
24e46fc4
JW		 11260 if (note)
11261 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11262 else
11263 offset = 1;
11264
11265 for (i = regno + offset; i < ourend; i++)
38a448ca 11266 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
6eb12cef 11267 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
fabd69e8 11268 }
230d793d 11269
dbc131f3 11270 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
230d793d
RS		 11271 {
11272 XEXP (note, 1) = *pnotes;
11273 *pnotes = note;
11274 }
11275 else
38a448ca 11276 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
1a26b032 11277
b1f21e0a 11278 REG_N_DEATHS (regno)++;
230d793d
RS		 11279 }
11280
11281 return;
11282 }
11283
11284 else if (GET_CODE (x) == SET)
11285 {
11286 rtx dest = SET_DEST (x);
11287
6eb12cef 11288 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d 11289
a7c99304
RK		 11290 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11291 that accesses one word of a multi-word item, some
11292 piece of everything register in the expression is used by
11293 this insn, so remove any old death. */
11294
11295 if (GET_CODE (dest) == ZERO_EXTRACT
11296 || GET_CODE (dest) == STRICT_LOW_PART
11297 || (GET_CODE (dest) == SUBREG
11298 && (((GET_MODE_SIZE (GET_MODE (dest))
11299 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11300 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11301 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
230d793d 11302 {
6eb12cef 11303 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
a7c99304 11304 return;
230d793d
RS		 11305 }
11306
a7c99304
RK		 11307 /* If this is some other SUBREG, we know it replaces the entire
11308 value, so use that as the destination. */
11309 if (GET_CODE (dest) == SUBREG)
11310 dest = SUBREG_REG (dest);
11311
11312 /* If this is a MEM, adjust deaths of anything used in the address.
11313 For a REG (the only other possibility), the entire value is
11314 being replaced so the old value is not used in this insn. */
230d793d
RS		 11315
11316 if (GET_CODE (dest) == MEM)
6eb12cef
RK		 11317 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11318 to_insn, pnotes);
230d793d
RS		 11319 return;
11320 }
11321
11322 else if (GET_CODE (x) == CLOBBER)
11323 return;
11324
11325 len = GET_RTX_LENGTH (code);
11326 fmt = GET_RTX_FORMAT (code);
11327
11328 for (i = 0; i < len; i++)
11329 {
11330 if (fmt[i] == 'E')
11331 {
11332 register int j;
11333 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6eb12cef
RK		 11334 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11335 to_insn, pnotes);
230d793d
RS		 11336 }
11337 else if (fmt[i] == 'e')
6eb12cef 11338 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d
RS		 11339 }
11340}
11341\f
a7c99304
RK		 11342/* Return 1 if X is the target of a bit-field assignment in BODY, the
11343 pattern of an insn. X must be a REG. */
230d793d
RS		 11344
11345static int
a7c99304
RK		 11346reg_bitfield_target_p (x, body)
11347 rtx x;
230d793d
RS		 11348 rtx body;
11349{
11350 int i;
11351
11352 if (GET_CODE (body) == SET)
a7c99304
RK		 11353 {
11354 rtx dest = SET_DEST (body);
11355 rtx target;
11356 int regno, tregno, endregno, endtregno;
11357
11358 if (GET_CODE (dest) == ZERO_EXTRACT)
11359 target = XEXP (dest, 0);
11360 else if (GET_CODE (dest) == STRICT_LOW_PART)
11361 target = SUBREG_REG (XEXP (dest, 0));
11362 else
11363 return 0;
11364
11365 if (GET_CODE (target) == SUBREG)
11366 target = SUBREG_REG (target);
11367
11368 if (GET_CODE (target) != REG)
11369 return 0;
11370
11371 tregno = REGNO (target), regno = REGNO (x);
11372 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11373 return target == x;
11374
11375 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11376 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11377
11378 return endregno > tregno && regno < endtregno;
11379 }
230d793d
RS		 11380
11381 else if (GET_CODE (body) == PARALLEL)
11382 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
a7c99304 11383 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
230d793d
RS		 11384 return 1;
11385
11386 return 0;
11387}
11388\f
11389/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11390 as appropriate. I3 and I2 are the insns resulting from the combination
11391 insns including FROM (I2 may be zero).
11392
11393 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11394 not need REG_DEAD notes because they are being substituted for. This
11395 saves searching in the most common cases.
11396
11397 Each note in the list is either ignored or placed on some insns, depending
11398 on the type of note. */
11399
11400static void
11401distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11402 rtx notes;
11403 rtx from_insn;
11404 rtx i3, i2;
11405 rtx elim_i2, elim_i1;
11406{
11407 rtx note, next_note;
11408 rtx tem;
11409
11410 for (note = notes; note; note = next_note)
11411 {
11412 rtx place = 0, place2 = 0;
11413
11414 /* If this NOTE references a pseudo register, ensure it references
11415 the latest copy of that register. */
11416 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11417 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11418 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11419
11420 next_note = XEXP (note, 1);
11421 switch (REG_NOTE_KIND (note))
11422 {
c9903b44
DE		 11423 case REG_BR_PROB:
11424 case REG_EXEC_COUNT:
11425 /* Doesn't matter much where we put this, as long as it's somewhere.
11426 It is preferable to keep these notes on branches, which is most
11427 likely to be i3. */
11428 place = i3;
11429 break;
11430
4b7c585f 11431 case REG_EH_REGION:
0e403ec3
AS		 11432 case REG_EH_RETHROW:
11433 /* These notes must remain with the call. It should not be
11434 possible for both I2 and I3 to be a call. */
4b7c585f
JL		 11435 if (GET_CODE (i3) == CALL_INSN)
11436 place = i3;
11437 else if (i2 && GET_CODE (i2) == CALL_INSN)
11438 place = i2;
11439 else
11440 abort ();
11441 break;
11442
230d793d 11443 case REG_UNUSED:
07d0cbdd 11444 /* Any clobbers for i3 may still exist, and so we must process
176c9e6b
JW		 11445 REG_UNUSED notes from that insn.
11446
11447 Any clobbers from i2 or i1 can only exist if they were added by
11448 recog_for_combine. In that case, recog_for_combine created the
11449 necessary REG_UNUSED notes. Trying to keep any original
11450 REG_UNUSED notes from these insns can cause incorrect output
11451 if it is for the same register as the original i3 dest.
11452 In that case, we will notice that the register is set in i3,
11453 and then add a REG_UNUSED note for the destination of i3, which
07d0cbdd
JW		 11454 is wrong. However, it is possible to have REG_UNUSED notes from
11455 i2 or i1 for register which were both used and clobbered, so
11456 we keep notes from i2 or i1 if they will turn into REG_DEAD
11457 notes. */
176c9e6b 11458
230d793d
RS		 11459 /* If this register is set or clobbered in I3, put the note there
11460 unless there is one already. */
07d0cbdd 11461 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
230d793d 11462 {
07d0cbdd
JW		 11463 if (from_insn != i3)
11464 break;
11465
230d793d
RS		 11466 if (! (GET_CODE (XEXP (note, 0)) == REG
11467 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11468 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11469 place = i3;
11470 }
11471 /* Otherwise, if this register is used by I3, then this register
11472 now dies here, so we must put a REG_DEAD note here unless there
11473 is one already. */
11474 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11475 && ! (GET_CODE (XEXP (note, 0)) == REG
11476 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11477 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11478 {
11479 PUT_REG_NOTE_KIND (note, REG_DEAD);
11480 place = i3;
11481 }
11482 break;
11483
11484 case REG_EQUAL:
11485 case REG_EQUIV:
11486 case REG_NONNEG:
9ae8ffe7 11487 case REG_NOALIAS:
230d793d
RS		 11488 /* These notes say something about results of an insn. We can
11489 only support them if they used to be on I3 in which case they
a687e897
RK		 11490 remain on I3. Otherwise they are ignored.
11491
11492 If the note refers to an expression that is not a constant, we
11493 must also ignore the note since we cannot tell whether the
11494 equivalence is still true. It might be possible to do
11495 slightly better than this (we only have a problem if I2DEST
11496 or I1DEST is present in the expression), but it doesn't
11497 seem worth the trouble. */
11498
11499 if (from_insn == i3
11500 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
230d793d
RS		 11501 place = i3;
11502 break;
11503
11504 case REG_INC:
11505 case REG_NO_CONFLICT:
230d793d
RS		 11506 /* These notes say something about how a register is used. They must
11507 be present on any use of the register in I2 or I3. */
11508 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11509 place = i3;
11510
11511 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11512 {
11513 if (place)
11514 place2 = i2;
11515 else
11516 place = i2;
11517 }
11518 break;
11519
e55b4486
RH		 11520 case REG_LABEL:
11521 /* This can show up in several ways -- either directly in the
11522 pattern, or hidden off in the constant pool with (or without?)
11523 a REG_EQUAL note. */
11524 /* ??? Ignore the without-reg_equal-note problem for now. */
11525 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11526 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11527 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11528 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11529 place = i3;
11530
11531 if (i2
11532 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11533 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11534 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11535 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11536 {
11537 if (place)
11538 place2 = i2;
11539 else
11540 place = i2;
11541 }
11542 break;
11543
230d793d
RS		 11544 case REG_WAS_0:
11545 /* It is too much trouble to try to see if this note is still
11546 correct in all situations. It is better to simply delete it. */
11547 break;
11548
11549 case REG_RETVAL:
11550 /* If the insn previously containing this note still exists,
11551 put it back where it was. Otherwise move it to the previous
11552 insn. Adjust the corresponding REG_LIBCALL note. */
11553 if (GET_CODE (from_insn) != NOTE)
11554 place = from_insn;
11555 else
11556 {
5f4f0e22 11557 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
230d793d
RS		 11558 place = prev_real_insn (from_insn);
11559 if (tem && place)
11560 XEXP (tem, 0) = place;
11561 }
11562 break;
11563
11564 case REG_LIBCALL:
11565 /* This is handled similarly to REG_RETVAL. */
11566 if (GET_CODE (from_insn) != NOTE)
11567 place = from_insn;
11568 else
11569 {
5f4f0e22 11570 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
230d793d
RS		 11571 place = next_real_insn (from_insn);
11572 if (tem && place)
11573 XEXP (tem, 0) = place;
11574 }
11575 break;
11576
11577 case REG_DEAD:
11578 /* If the register is used as an input in I3, it dies there.
11579 Similarly for I2, if it is non-zero and adjacent to I3.
11580
11581 If the register is not used as an input in either I3 or I2
11582 and it is not one of the registers we were supposed to eliminate,
11583 there are two possibilities. We might have a non-adjacent I2
11584 or we might have somehow eliminated an additional register
11585 from a computation. For example, we might have had A & B where
11586 we discover that B will always be zero. In this case we will
11587 eliminate the reference to A.
11588
11589 In both cases, we must search to see if we can find a previous
11590 use of A and put the death note there. */
11591
6e2d1486
RK		 11592 if (from_insn
11593 && GET_CODE (from_insn) == CALL_INSN
11594 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11595 place = from_insn;
11596 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
230d793d
RS		 11597 place = i3;
11598 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11599 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11600 place = i2;
11601
11602 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11603 break;
11604
510dd77e
RK		 11605 /* If the register is used in both I2 and I3 and it dies in I3,
11606 we might have added another reference to it. If reg_n_refs
11607 was 2, bump it to 3. This has to be correct since the
11608 register must have been set somewhere. The reason this is
11609 done is because local-alloc.c treats 2 references as a
11610 special case. */
11611
11612 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
b1f21e0a 11613 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
510dd77e 11614 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
b1f21e0a 11615 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
510dd77e 11616
230d793d 11617 if (place == 0)
38d8473f
RK		 11618 {
11619 for (tem = prev_nonnote_insn (i3);
11620 place == 0 && tem
11621 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11622 tem = prev_nonnote_insn (tem))
11623 {
11624 /* If the register is being set at TEM, see if that is all
11625 TEM is doing. If so, delete TEM. Otherwise, make this
11626 into a REG_UNUSED note instead. */
11627 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11628 {
11629 rtx set = single_set (tem);
e5e809f4 11630 rtx inner_dest = 0;
e51712db 11631#ifdef HAVE_cc0
f5c97640 11632 rtx cc0_setter = NULL_RTX;
e51712db 11633#endif
e5e809f4
JL		 11634
11635 if (set != 0)
11636 for (inner_dest = SET_DEST (set);
11637 GET_CODE (inner_dest) == STRICT_LOW_PART
11638 || GET_CODE (inner_dest) == SUBREG
11639 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11640 inner_dest = XEXP (inner_dest, 0))
11641 ;
38d8473f
RK		 11642
11643 /* Verify that it was the set, and not a clobber that
f5c97640
RH		 11644 modified the register.
11645
11646 CC0 targets must be careful to maintain setter/user
11647 pairs. If we cannot delete the setter due to side
11648 effects, mark the user with an UNUSED note instead
11649 of deleting it. */
38d8473f
RK		 11650
11651 if (set != 0 && ! side_effects_p (SET_SRC (set))
f5c97640
RH		 11652 && rtx_equal_p (XEXP (note, 0), inner_dest)
11653#ifdef HAVE_cc0
11654 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11655 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11656 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11657#endif
11658 )
38d8473f
RK		 11659 {
11660 /* Move the notes and links of TEM elsewhere.
11661 This might delete other dead insns recursively.
11662 First set the pattern to something that won't use
11663 any register. */
11664
11665 PATTERN (tem) = pc_rtx;
11666
11667 distribute_notes (REG_NOTES (tem), tem, tem,
11668 NULL_RTX, NULL_RTX, NULL_RTX);
11669 distribute_links (LOG_LINKS (tem));
11670
11671 PUT_CODE (tem, NOTE);
11672 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11673 NOTE_SOURCE_FILE (tem) = 0;
f5c97640
RH		 11674
11675#ifdef HAVE_cc0
11676 /* Delete the setter too. */
11677 if (cc0_setter)
11678 {
11679 PATTERN (cc0_setter) = pc_rtx;
11680
11681 distribute_notes (REG_NOTES (cc0_setter),
11682 cc0_setter, cc0_setter,
11683 NULL_RTX, NULL_RTX, NULL_RTX);
11684 distribute_links (LOG_LINKS (cc0_setter));
11685
11686 PUT_CODE (cc0_setter, NOTE);
11687 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED;
11688 NOTE_SOURCE_FILE (cc0_setter) = 0;
11689 }
11690#endif
38d8473f 11691 }
e5e809f4
JL		 11692 /* If the register is both set and used here, put the
11693 REG_DEAD note here, but place a REG_UNUSED note
11694 here too unless there already is one. */
11695 else if (reg_referenced_p (XEXP (note, 0),
11696 PATTERN (tem)))
11697 {
11698 place = tem;
11699
11700 if (! find_regno_note (tem, REG_UNUSED,
11701 REGNO (XEXP (note, 0))))
11702 REG_NOTES (tem)
9e6a5703
JC		 11703 = gen_rtx_EXPR_LIST (REG_UNUSED,
11704 XEXP (note, 0),
11705 REG_NOTES (tem));
e5e809f4 11706 }
38d8473f
RK		 11707 else
11708 {
11709 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11710
11711 /* If there isn't already a REG_UNUSED note, put one
11712 here. */
11713 if (! find_regno_note (tem, REG_UNUSED,
11714 REGNO (XEXP (note, 0))))
11715 place = tem;
11716 break;
230d793d
RS		 11717 }
11718 }
13018fad
RE		 11719 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11720 || (GET_CODE (tem) == CALL_INSN
11721 && find_reg_fusage (tem, USE, XEXP (note, 0))))
230d793d
RS		 11722 {
11723 place = tem;
932d1119
RK		 11724
11725 /* If we are doing a 3->2 combination, and we have a
11726 register which formerly died in i3 and was not used
11727 by i2, which now no longer dies in i3 and is used in
11728 i2 but does not die in i2, and place is between i2
11729 and i3, then we may need to move a link from place to
11730 i2. */
a8908849
RK		 11731 if (i2 && INSN_UID (place) <= max_uid_cuid
11732 && INSN_CUID (place) > INSN_CUID (i2)
932d1119
RK		 11733 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11734 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11735 {
11736 rtx links = LOG_LINKS (place);
11737 LOG_LINKS (place) = 0;
11738 distribute_links (links);
11739 }
230d793d
RS		 11740 break;
11741 }
38d8473f
RK		 11742 }
11743
11744 /* If we haven't found an insn for the death note and it
11745 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11746 insert a USE insn for the register at that label and
11747 put the death node there. This prevents problems with
11748 call-state tracking in caller-save.c. */
11749 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
e2cce0cf
RK		 11750 {
11751 place
38a448ca 11752 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
e2cce0cf
RK		 11753 tem);
11754
11755 /* If this insn was emitted between blocks, then update
3b413743
RH		 11756 BLOCK_HEAD of the current block to include it. */
11757 if (BLOCK_END (this_basic_block - 1) == tem)
11758 BLOCK_HEAD (this_basic_block) = place;
e2cce0cf 11759 }
38d8473f 11760 }
230d793d
RS		 11761
11762 /* If the register is set or already dead at PLACE, we needn't do
e5e809f4
JL		 11763 anything with this note if it is still a REG_DEAD note.
11764 We can here if it is set at all, not if is it totally replace,
11765 which is what `dead_or_set_p' checks, so also check for it being
11766 set partially. */
11767
230d793d 11768
230d793d
RS		 11769 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11770 {
11771 int regno = REGNO (XEXP (note, 0));
11772
11773 if (dead_or_set_p (place, XEXP (note, 0))
11774 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11775 {
11776 /* Unless the register previously died in PLACE, clear
11777 reg_last_death. [I no longer understand why this is
11778 being done.] */
11779 if (reg_last_death[regno] != place)
11780 reg_last_death[regno] = 0;
11781 place = 0;
11782 }
11783 else
11784 reg_last_death[regno] = place;
11785
11786 /* If this is a death note for a hard reg that is occupying
11787 multiple registers, ensure that we are still using all
11788 parts of the object. If we find a piece of the object
11789 that is unused, we must add a USE for that piece before
11790 PLACE and put the appropriate REG_DEAD note on it.
11791
11792 An alternative would be to put a REG_UNUSED for the pieces
11793 on the insn that set the register, but that can't be done if
11794 it is not in the same block. It is simpler, though less
11795 efficient, to add the USE insns. */
11796
11797 if (place && regno < FIRST_PSEUDO_REGISTER
11798 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11799 {
11800 int endregno
11801 = regno + HARD_REGNO_NREGS (regno,
11802 GET_MODE (XEXP (note, 0)));
11803 int all_used = 1;
11804 int i;
11805
11806 for (i = regno; i < endregno; i++)
9fd5bb62
JW		 11807 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11808 && ! find_regno_fusage (place, USE, i))
230d793d 11809 {
38a448ca 11810 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
28f6d3af
RK		 11811 rtx p;
11812
11813 /* See if we already placed a USE note for this
11814 register in front of PLACE. */
11815 for (p = place;
11816 GET_CODE (PREV_INSN (p)) == INSN
11817 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11818 p = PREV_INSN (p))
11819 if (rtx_equal_p (piece,
11820 XEXP (PATTERN (PREV_INSN (p)), 0)))
11821 {
11822 p = 0;
11823 break;
11824 }
11825
11826 if (p)
11827 {
11828 rtx use_insn
38a448ca
RH		 11829 = emit_insn_before (gen_rtx_USE (VOIDmode,
11830 piece),
28f6d3af
RK		 11831 p);
11832 REG_NOTES (use_insn)
38a448ca
RH		 11833 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11834 REG_NOTES (use_insn));
28f6d3af 11835 }
230d793d 11836
5089e22e 11837 all_used = 0;
230d793d
RS		 11838 }
11839
a394b17b
JW		 11840 /* Check for the case where the register dying partially
11841 overlaps the register set by this insn. */
11842 if (all_used)
11843 for (i = regno; i < endregno; i++)
11844 if (dead_or_set_regno_p (place, i))
11845 {
11846 all_used = 0;
11847 break;
11848 }
11849
230d793d
RS		 11850 if (! all_used)
11851 {
11852 /* Put only REG_DEAD notes for pieces that are
11853 still used and that are not already dead or set. */
11854
11855 for (i = regno; i < endregno; i++)
11856 {
38a448ca 11857 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
230d793d 11858
17cbf358
JW		 11859 if ((reg_referenced_p (piece, PATTERN (place))
11860 || (GET_CODE (place) == CALL_INSN
11861 && find_reg_fusage (place, USE, piece)))
230d793d
RS		 11862 && ! dead_or_set_p (place, piece)
11863 && ! reg_bitfield_target_p (piece,
11864 PATTERN (place)))
38a448ca
RH		 11865 REG_NOTES (place)
11866 = gen_rtx_EXPR_LIST (REG_DEAD,
11867 piece, REG_NOTES (place));
230d793d
RS		 11868 }
11869
11870 place = 0;
11871 }
11872 }
11873 }
11874 break;
11875
11876 default:
11877 /* Any other notes should not be present at this point in the
11878 compilation. */
11879 abort ();
11880 }
11881
11882 if (place)
11883 {
11884 XEXP (note, 1) = REG_NOTES (place);
11885 REG_NOTES (place) = note;
11886 }
1a26b032
RK		 11887 else if ((REG_NOTE_KIND (note) == REG_DEAD
11888 || REG_NOTE_KIND (note) == REG_UNUSED)
11889 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11890 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
230d793d
RS		 11891
11892 if (place2)
1a26b032
RK		 11893 {
11894 if ((REG_NOTE_KIND (note) == REG_DEAD
11895 || REG_NOTE_KIND (note) == REG_UNUSED)
11896 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11897 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 11898
38a448ca
RH		 11899 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11900 REG_NOTE_KIND (note),
11901 XEXP (note, 0),
11902 REG_NOTES (place2));
1a26b032 11903 }
230d793d
RS		 11904 }
11905}
11906\f
11907/* Similarly to above, distribute the LOG_LINKS that used to be present on
5089e22e
RS		 11908 I3, I2, and I1 to new locations. This is also called in one case to
11909 add a link pointing at I3 when I3's destination is changed. */
230d793d
RS		 11910
11911static void
11912distribute_links (links)
11913 rtx links;
11914{
11915 rtx link, next_link;
11916
11917 for (link = links; link; link = next_link)
11918 {
11919 rtx place = 0;
11920 rtx insn;
11921 rtx set, reg;
11922
11923 next_link = XEXP (link, 1);
11924
11925 /* If the insn that this link points to is a NOTE or isn't a single
11926 set, ignore it. In the latter case, it isn't clear what we
11927 can do other than ignore the link, since we can't tell which
11928 register it was for. Such links wouldn't be used by combine
11929 anyway.
11930
11931 It is not possible for the destination of the target of the link to
11932 have been changed by combine. The only potential of this is if we
11933 replace I3, I2, and I1 by I3 and I2. But in that case the
11934 destination of I2 also remains unchanged. */
11935
11936 if (GET_CODE (XEXP (link, 0)) == NOTE
11937 || (set = single_set (XEXP (link, 0))) == 0)
11938 continue;
11939
11940 reg = SET_DEST (set);
11941 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11942 || GET_CODE (reg) == SIGN_EXTRACT
11943 || GET_CODE (reg) == STRICT_LOW_PART)
11944 reg = XEXP (reg, 0);
11945
11946 /* A LOG_LINK is defined as being placed on the first insn that uses
11947 a register and points to the insn that sets the register. Start
11948 searching at the next insn after the target of the link and stop
11949 when we reach a set of the register or the end of the basic block.
11950
11951 Note that this correctly handles the link that used to point from
5089e22e 11952 I3 to I2. Also note that not much searching is typically done here
230d793d
RS		 11953 since most links don't point very far away. */
11954
11955 for (insn = NEXT_INSN (XEXP (link, 0));
0d4d42c3 11956 (insn && (this_basic_block == n_basic_blocks - 1
3b413743 11957 || BLOCK_HEAD (this_basic_block + 1) != insn));
230d793d
RS		 11958 insn = NEXT_INSN (insn))
11959 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11960 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11961 {
11962 if (reg_referenced_p (reg, PATTERN (insn)))
11963 place = insn;
11964 break;
11965 }
6e2d1486
RK		 11966 else if (GET_CODE (insn) == CALL_INSN
11967 && find_reg_fusage (insn, USE, reg))
11968 {
11969 place = insn;
11970 break;
11971 }
230d793d
RS		 11972
11973 /* If we found a place to put the link, place it there unless there
11974 is already a link to the same insn as LINK at that point. */
11975
11976 if (place)
11977 {
11978 rtx link2;
11979
11980 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11981 if (XEXP (link2, 0) == XEXP (link, 0))
11982 break;
11983
11984 if (link2 == 0)
11985 {
11986 XEXP (link, 1) = LOG_LINKS (place);
11987 LOG_LINKS (place) = link;
abe6e52f
RK		 11988
11989 /* Set added_links_insn to the earliest insn we added a
11990 link to. */
11991 if (added_links_insn == 0
11992 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11993 added_links_insn = place;
230d793d
RS		 11994 }
11995 }
11996 }
11997}
11998\f
1427d6d2
RK		 11999/* Compute INSN_CUID for INSN, which is an insn made by combine. */
12000
12001static int
12002insn_cuid (insn)
12003 rtx insn;
12004{
12005 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12006 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12007 insn = NEXT_INSN (insn);
12008
12009 if (INSN_UID (insn) > max_uid_cuid)
12010 abort ();
12011
12012 return INSN_CUID (insn);
12013}
12014\f
230d793d
RS		 12015void
12016dump_combine_stats (file)
12017 FILE *file;
12018{
ab87f8c8 12019 fnotice
230d793d
RS		 12020 (file,
12021 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12022 combine_attempts, combine_merges, combine_extras, combine_successes);
12023}
12024
12025void
12026dump_combine_total_stats (file)
12027 FILE *file;
12028{
ab87f8c8 12029 fnotice
230d793d
RS		 12030 (file,
12031 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12032 total_attempts, total_merges, total_extras, total_successes);
12033}
GNU Compiler Collection
This page took 2.425135 seconds and 5 git commands to generate.