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230d793d 1/* Optimize by combining instructions for GNU compiler.
c85f7c16 2 Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
230d793d
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
940d9d63
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
230d793d
RS		 20
21
22/* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
230d793d 77#include "config.h"
4f90e4a0 78#ifdef __STDC__
04fe4385 79#include <stdarg.h>
4f90e4a0 80#else
04fe4385 81#include <varargs.h>
4f90e4a0 82#endif
dfa3449b 83
670ee920
KG		 84/* stdio.h must precede rtl.h for FFS. */
85#include "system.h"
9c3b4c8b 86
230d793d
RS		 87#include "rtl.h"
88#include "flags.h"
89#include "regs.h"
55310dad 90#include "hard-reg-set.h"
230d793d
RS		 91#include "basic-block.h"
92#include "insn-config.h"
d6f4ec51
KG		 93/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
94#include "expr.h"
230d793d
RS		 95#include "insn-flags.h"
96#include "insn-codes.h"
97#include "insn-attr.h"
98#include "recog.h"
99#include "real.h"
2e107e9e 100#include "toplev.h"
230d793d
RS		 101
102/* It is not safe to use ordinary gen_lowpart in combine.
103 Use gen_lowpart_for_combine instead. See comments there. */
104#define gen_lowpart dont_use_gen_lowpart_you_dummy
105
106/* Number of attempts to combine instructions in this function. */
107
108static int combine_attempts;
109
110/* Number of attempts that got as far as substitution in this function. */
111
112static int combine_merges;
113
114/* Number of instructions combined with added SETs in this function. */
115
116static int combine_extras;
117
118/* Number of instructions combined in this function. */
119
120static int combine_successes;
121
122/* Totals over entire compilation. */
123
124static int total_attempts, total_merges, total_extras, total_successes;
9210df58 125
ddd5a7c1 126/* Define a default value for REVERSIBLE_CC_MODE.
9210df58
RK		 127 We can never assume that a condition code mode is safe to reverse unless
128 the md tells us so. */
129#ifndef REVERSIBLE_CC_MODE
130#define REVERSIBLE_CC_MODE(MODE) 0
131#endif
230d793d
RS		 132\f
133/* Vector mapping INSN_UIDs to cuids.
5089e22e 134 The cuids are like uids but increase monotonically always.
230d793d
RS		 135 Combine always uses cuids so that it can compare them.
136 But actually renumbering the uids, which we used to do,
137 proves to be a bad idea because it makes it hard to compare
138 the dumps produced by earlier passes with those from later passes. */
139
140static int *uid_cuid;
4255220d 141static int max_uid_cuid;
230d793d
RS		 142
143/* Get the cuid of an insn. */
144
1427d6d2
RK		 145#define INSN_CUID(INSN) \
146(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
230d793d
RS		 147
148/* Maximum register number, which is the size of the tables below. */
149
150static int combine_max_regno;
151
152/* Record last point of death of (hard or pseudo) register n. */
153
154static rtx *reg_last_death;
155
156/* Record last point of modification of (hard or pseudo) register n. */
157
158static rtx *reg_last_set;
159
160/* Record the cuid of the last insn that invalidated memory
161 (anything that writes memory, and subroutine calls, but not pushes). */
162
163static int mem_last_set;
164
165/* Record the cuid of the last CALL_INSN
166 so we can tell whether a potential combination crosses any calls. */
167
168static int last_call_cuid;
169
170/* When `subst' is called, this is the insn that is being modified
171 (by combining in a previous insn). The PATTERN of this insn
172 is still the old pattern partially modified and it should not be
173 looked at, but this may be used to examine the successors of the insn
174 to judge whether a simplification is valid. */
175
176static rtx subst_insn;
177
0d9641d1
JW		 178/* This is an insn that belongs before subst_insn, but is not currently
179 on the insn chain. */
180
181static rtx subst_prev_insn;
182
230d793d
RS		 183/* This is the lowest CUID that `subst' is currently dealing with.
184 get_last_value will not return a value if the register was set at or
185 after this CUID. If not for this mechanism, we could get confused if
186 I2 or I1 in try_combine were an insn that used the old value of a register
187 to obtain a new value. In that case, we might erroneously get the
188 new value of the register when we wanted the old one. */
189
190static int subst_low_cuid;
191
6e25d159
RK		 192/* This contains any hard registers that are used in newpat; reg_dead_at_p
193 must consider all these registers to be always live. */
194
195static HARD_REG_SET newpat_used_regs;
196
abe6e52f
RK		 197/* This is an insn to which a LOG_LINKS entry has been added. If this
198 insn is the earlier than I2 or I3, combine should rescan starting at
199 that location. */
200
201static rtx added_links_insn;
202
0d4d42c3
RK		 203/* Basic block number of the block in which we are performing combines. */
204static int this_basic_block;
230d793d
RS		 205\f
206/* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
5089e22e 208 operation being processed is redundant given a prior operation performed
230d793d
RS		 209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
211
212 We use an approach similar to that used by cse, but change it in the
213 following ways:
214
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
218
219 Therefore, we maintain the following arrays:
220
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
228 register's value
229
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
233 table.
234
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
237
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
242
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
246
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
249
0f41302f 250/* Record last value assigned to (hard or pseudo) register n. */
230d793d
RS		 251
252static rtx *reg_last_set_value;
253
254/* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
256
568356af 257static int *reg_last_set_label;
230d793d
RS		 258
259/* Record the value of label_tick when an expression involving register n
0f41302f 260 is placed in reg_last_set_value. */
230d793d 261
568356af 262static int *reg_last_set_table_tick;
230d793d
RS		 263
264/* Set non-zero if references to register n in expressions should not be
265 used. */
266
267static char *reg_last_set_invalid;
268
0f41302f 269/* Incremented for each label. */
230d793d 270
568356af 271static int label_tick;
230d793d
RS		 272
273/* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
277
951553af 278 We record in the following array what we know about the nonzero
230d793d
RS		 279 bits of a register, specifically which bits are known to be zero.
280
281 If an entry is zero, it means that we don't know anything special. */
282
55310dad 283static unsigned HOST_WIDE_INT *reg_nonzero_bits;
230d793d 284
951553af 285/* Mode used to compute significance in reg_nonzero_bits. It is the largest
5f4f0e22 286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
230d793d 287
951553af 288static enum machine_mode nonzero_bits_mode;
230d793d 289
d0ab8cd3
RK		 290/* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
292
293static char *reg_sign_bit_copies;
294
951553af 295/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
1a26b032
RK		 296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
230d793d 299
951553af 300static int nonzero_sign_valid;
55310dad
RK		 301
302/* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
306
307static enum machine_mode *reg_last_set_mode;
308static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309static char *reg_last_set_sign_bit_copies;
230d793d
RS		 310\f
311/* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
314
315struct undo
316{
241cea85 317 struct undo *next;
230d793d 318 int is_int;
f5393ab9
RS		 319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
230d793d
RS		 321};
322
323/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
325
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
328
329 other_insn is nonzero if we have modified some other insn in the process
241cea85 330 of working on subst_insn. It must be verified too.
230d793d 331
241cea85
RK		 332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
335 structures. */
230d793d
RS		 336
337struct undobuf
338{
230d793d 339 char *storage;
241cea85
RK		 340 struct undo *undos;
341 struct undo *frees;
342 struct undo *previous_undos;
230d793d
RS		 343 rtx other_insn;
344};
345
346static struct undobuf undobuf;
347
cc876596 348/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
230d793d 349 insn. The substitution can be undone by undo_all. If INTO is already
cc876596
RK		 350 set to NEWVAL, do not record this change. Because computing NEWVAL might
351 also call SUBST, we have to compute it before we put anything into
352 the undo table. */
230d793d
RS		 353
354#define SUBST(INTO, NEWVAL) \
241cea85
RK		 355 do { rtx _new = (NEWVAL); \
356 struct undo *_buf; \
357 \
358 if (undobuf.frees) \
359 _buf = undobuf.frees, undobuf.frees = _buf->next; \
360 else \
361 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 \
363 _buf->is_int = 0; \
364 _buf->where.r = &INTO; \
365 _buf->old_contents.r = INTO; \
366 INTO = _new; \
367 if (_buf->old_contents.r == INTO) \
368 _buf->next = undobuf.frees, undobuf.frees = _buf; \
369 else \
370 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 371 } while (0)
372
241cea85
RK		 373/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
374 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 not safe. */
230d793d
RS		 376
377#define SUBST_INT(INTO, NEWVAL) \
241cea85
RK		 378 do { struct undo *_buf; \
379 \
380 if (undobuf.frees) \
381 _buf = undobuf.frees, undobuf.frees = _buf->next; \
382 else \
383 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 \
385 _buf->is_int = 1; \
386 _buf->where.i = (int *) &INTO; \
387 _buf->old_contents.i = INTO; \
388 INTO = NEWVAL; \
389 if (_buf->old_contents.i == INTO) \
390 _buf->next = undobuf.frees, undobuf.frees = _buf; \
391 else \
392 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 393 } while (0)
394
395/* Number of times the pseudo being substituted for
396 was found and replaced. */
397
398static int n_occurrences;
399
c5ad722c
RK		 400static void init_reg_last_arrays PROTO((void));
401static void setup_incoming_promotions PROTO((void));
fe2db4fb
RK		 402static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
403static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
e009aaf3 404static int sets_function_arg_p PROTO((rtx));
fe2db4fb
RK		 405static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
406static rtx try_combine PROTO((rtx, rtx, rtx));
407static void undo_all PROTO((void));
408static rtx *find_split_point PROTO((rtx *, rtx));
409static rtx subst PROTO((rtx, rtx, rtx, int, int));
8079805d
RK		 410static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
411static rtx simplify_if_then_else PROTO((rtx));
412static rtx simplify_set PROTO((rtx));
413static rtx simplify_logical PROTO((rtx, int));
fe2db4fb
RK		 414static rtx expand_compound_operation PROTO((rtx));
415static rtx expand_field_assignment PROTO((rtx));
416static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
417 int, int, int));
71923da7 418static rtx extract_left_shift PROTO((rtx, int));
fe2db4fb
RK		 419static rtx make_compound_operation PROTO((rtx, enum rtx_code));
420static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
6139ff20 421static rtx force_to_mode PROTO((rtx, enum machine_mode,
e3d616e3 422 unsigned HOST_WIDE_INT, rtx, int));
abe6e52f 423static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
fe2db4fb 424static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
e11fa86f 425static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
fe2db4fb
RK		 426static rtx make_field_assignment PROTO((rtx));
427static rtx apply_distributive_law PROTO((rtx));
428static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
429 unsigned HOST_WIDE_INT));
430static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
431static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
432static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
433 enum rtx_code, HOST_WIDE_INT,
434 enum machine_mode, int *));
435static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
436 rtx, int));
a29ca9db 437static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
fe2db4fb 438static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
d18225c4 439static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
4f90e4a0 440 ...));
fe2db4fb
RK		 441static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
442 rtx, rtx));
0c1c8ea6
RK		 443static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
444 enum machine_mode, rtx));
fe2db4fb
RK		 445static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
446static int reversible_comparison_p PROTO((rtx));
447static void update_table_tick PROTO((rtx));
448static void record_value_for_reg PROTO((rtx, rtx, rtx));
449static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
450static void record_dead_and_set_regs PROTO((rtx));
9a893315 451static int get_last_value_validate PROTO((rtx *, rtx, int, int));
fe2db4fb
RK		 452static rtx get_last_value PROTO((rtx));
453static int use_crosses_set_p PROTO((rtx, int));
454static void reg_dead_at_p_1 PROTO((rtx, rtx));
455static int reg_dead_at_p PROTO((rtx, rtx));
6eb12cef 456static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
fe2db4fb
RK		 457static int reg_bitfield_target_p PROTO((rtx, rtx));
458static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
459static void distribute_links PROTO((rtx));
6e25d159 460static void mark_used_regs_combine PROTO((rtx));
1427d6d2 461static int insn_cuid PROTO((rtx));
230d793d
RS		 462\f
463/* Main entry point for combiner. F is the first insn of the function.
464 NREGS is the first unused pseudo-reg number. */
465
466void
467combine_instructions (f, nregs)
468 rtx f;
469 int nregs;
470{
b729186a
JL		 471 register rtx insn, next;
472#ifdef HAVE_cc0
473 register rtx prev;
474#endif
230d793d
RS		 475 register int i;
476 register rtx links, nextlinks;
477
478 combine_attempts = 0;
479 combine_merges = 0;
480 combine_extras = 0;
481 combine_successes = 0;
241cea85 482 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 483
484 combine_max_regno = nregs;
485
ef026f91
RS		 486 reg_nonzero_bits
487 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
488 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
489
4c9a05bc 490 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 491 bzero (reg_sign_bit_copies, nregs * sizeof (char));
492
230d793d
RS		 493 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
494 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
495 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
568356af
RK		 496 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
497 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
5f4f0e22 498 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
55310dad
RK		 499 reg_last_set_mode
500 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
501 reg_last_set_nonzero_bits
502 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
503 reg_last_set_sign_bit_copies
504 = (char *) alloca (nregs * sizeof (char));
505
ef026f91 506 init_reg_last_arrays ();
230d793d
RS		 507
508 init_recog_no_volatile ();
509
510 /* Compute maximum uid value so uid_cuid can be allocated. */
511
512 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
513 if (INSN_UID (insn) > i)
514 i = INSN_UID (insn);
515
516 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
4255220d 517 max_uid_cuid = i;
230d793d 518
951553af 519 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
230d793d 520
951553af 521 /* Don't use reg_nonzero_bits when computing it. This can cause problems
230d793d
RS		 522 when, for example, we have j <<= 1 in a loop. */
523
951553af 524 nonzero_sign_valid = 0;
230d793d
RS		 525
526 /* Compute the mapping from uids to cuids.
527 Cuids are numbers assigned to insns, like uids,
528 except that cuids increase monotonically through the code.
529
530 Scan all SETs and see if we can deduce anything about what
951553af 531 bits are known to be zero for some registers and how many copies
d79f08e0
RK		 532 of the sign bit are known to exist for those registers.
533
534 Also set any known values so that we can use it while searching
535 for what bits are known to be set. */
536
537 label_tick = 1;
230d793d 538
bcd49eb7
JW		 539 /* We need to initialize it here, because record_dead_and_set_regs may call
540 get_last_value. */
541 subst_prev_insn = NULL_RTX;
542
7988fd36
RK		 543 setup_incoming_promotions ();
544
230d793d
RS		 545 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
546 {
4255220d 547 uid_cuid[INSN_UID (insn)] = ++i;
d79f08e0
RK		 548 subst_low_cuid = i;
549 subst_insn = insn;
550
230d793d 551 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
d79f08e0
RK		 552 {
553 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
554 record_dead_and_set_regs (insn);
2dab894a
RK		 555
556#ifdef AUTO_INC_DEC
557 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
558 if (REG_NOTE_KIND (links) == REG_INC)
559 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
560#endif
d79f08e0
RK		 561 }
562
563 if (GET_CODE (insn) == CODE_LABEL)
564 label_tick++;
230d793d
RS		 565 }
566
951553af 567 nonzero_sign_valid = 1;
230d793d
RS		 568
569 /* Now scan all the insns in forward order. */
570
0d4d42c3 571 this_basic_block = -1;
230d793d
RS		 572 label_tick = 1;
573 last_call_cuid = 0;
574 mem_last_set = 0;
ef026f91 575 init_reg_last_arrays ();
7988fd36
RK		 576 setup_incoming_promotions ();
577
230d793d
RS		 578 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
579 {
580 next = 0;
581
0d4d42c3 582 /* If INSN starts a new basic block, update our basic block number. */
f085c9cd 583 if (this_basic_block + 1 < n_basic_blocks
0d4d42c3
RK		 584 && basic_block_head[this_basic_block + 1] == insn)
585 this_basic_block++;
586
230d793d
RS		 587 if (GET_CODE (insn) == CODE_LABEL)
588 label_tick++;
589
0d4d42c3 590 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
230d793d
RS		 591 {
592 /* Try this insn with each insn it links back to. */
593
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
5f4f0e22 595 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
230d793d
RS		 596 goto retry;
597
598 /* Try each sequence of three linked insns ending with this one. */
599
600 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
601 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
602 nextlinks = XEXP (nextlinks, 1))
603 if ((next = try_combine (insn, XEXP (links, 0),
604 XEXP (nextlinks, 0))) != 0)
605 goto retry;
606
607#ifdef HAVE_cc0
608 /* Try to combine a jump insn that uses CC0
609 with a preceding insn that sets CC0, and maybe with its
610 logical predecessor as well.
611 This is how we make decrement-and-branch insns.
612 We need this special code because data flow connections
613 via CC0 do not get entered in LOG_LINKS. */
614
615 if (GET_CODE (insn) == JUMP_INSN
616 && (prev = prev_nonnote_insn (insn)) != 0
617 && GET_CODE (prev) == INSN
618 && sets_cc0_p (PATTERN (prev)))
619 {
5f4f0e22 620 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 621 goto retry;
622
623 for (nextlinks = LOG_LINKS (prev); nextlinks;
624 nextlinks = XEXP (nextlinks, 1))
625 if ((next = try_combine (insn, prev,
626 XEXP (nextlinks, 0))) != 0)
627 goto retry;
628 }
629
630 /* Do the same for an insn that explicitly references CC0. */
631 if (GET_CODE (insn) == INSN
632 && (prev = prev_nonnote_insn (insn)) != 0
633 && GET_CODE (prev) == INSN
634 && sets_cc0_p (PATTERN (prev))
635 && GET_CODE (PATTERN (insn)) == SET
636 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
637 {
5f4f0e22 638 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 639 goto retry;
640
641 for (nextlinks = LOG_LINKS (prev); nextlinks;
642 nextlinks = XEXP (nextlinks, 1))
643 if ((next = try_combine (insn, prev,
644 XEXP (nextlinks, 0))) != 0)
645 goto retry;
646 }
647
648 /* Finally, see if any of the insns that this insn links to
649 explicitly references CC0. If so, try this insn, that insn,
5089e22e 650 and its predecessor if it sets CC0. */
230d793d
RS		 651 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
652 if (GET_CODE (XEXP (links, 0)) == INSN
653 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
654 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
655 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
656 && GET_CODE (prev) == INSN
657 && sets_cc0_p (PATTERN (prev))
658 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
659 goto retry;
660#endif
661
662 /* Try combining an insn with two different insns whose results it
663 uses. */
664 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
665 for (nextlinks = XEXP (links, 1); nextlinks;
666 nextlinks = XEXP (nextlinks, 1))
667 if ((next = try_combine (insn, XEXP (links, 0),
668 XEXP (nextlinks, 0))) != 0)
669 goto retry;
670
671 if (GET_CODE (insn) != NOTE)
672 record_dead_and_set_regs (insn);
673
674 retry:
675 ;
676 }
677 }
678
679 total_attempts += combine_attempts;
680 total_merges += combine_merges;
681 total_extras += combine_extras;
682 total_successes += combine_successes;
1a26b032 683
951553af 684 nonzero_sign_valid = 0;
230d793d 685}
ef026f91
RS		 686
687/* Wipe the reg_last_xxx arrays in preparation for another pass. */
688
689static void
690init_reg_last_arrays ()
691{
692 int nregs = combine_max_regno;
693
4c9a05bc
RK		 694 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
695 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
696 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
697 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
698 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
ef026f91 699 bzero (reg_last_set_invalid, nregs * sizeof (char));
4c9a05bc
RK		 700 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
701 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 702 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
703}
230d793d 704\f
7988fd36
RK		 705/* Set up any promoted values for incoming argument registers. */
706
ee791cc3 707static void
7988fd36
RK		 708setup_incoming_promotions ()
709{
710#ifdef PROMOTE_FUNCTION_ARGS
711 int regno;
712 rtx reg;
713 enum machine_mode mode;
714 int unsignedp;
715 rtx first = get_insns ();
716
717 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
718 if (FUNCTION_ARG_REGNO_P (regno)
719 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
38a448ca
RH		 720 {
721 record_value_for_reg
722 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
723 : SIGN_EXTEND),
724 GET_MODE (reg),
725 gen_rtx_CLOBBER (mode, const0_rtx)));
726 }
7988fd36
RK		 727#endif
728}
729\f
91102d5a
RK		 730/* Called via note_stores. If X is a pseudo that is narrower than
731 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
230d793d
RS		 732
733 If we are setting only a portion of X and we can't figure out what
734 portion, assume all bits will be used since we don't know what will
d0ab8cd3
RK		 735 be happening.
736
737 Similarly, set how many bits of X are known to be copies of the sign bit
738 at all locations in the function. This is the smallest number implied
739 by any set of X. */
230d793d
RS		 740
741static void
951553af 742set_nonzero_bits_and_sign_copies (x, set)
230d793d
RS		 743 rtx x;
744 rtx set;
745{
d0ab8cd3
RK		 746 int num;
747
230d793d
RS		 748 if (GET_CODE (x) == REG
749 && REGNO (x) >= FIRST_PSEUDO_REGISTER
e8095e80
RK		 750 /* If this register is undefined at the start of the file, we can't
751 say what its contents were. */
8e08106d 752 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
5f4f0e22 753 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
230d793d 754 {
2dab894a 755 if (set == 0 || GET_CODE (set) == CLOBBER)
e8095e80
RK		 756 {
757 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 758 reg_sign_bit_copies[REGNO (x)] = 1;
e8095e80
RK		 759 return;
760 }
230d793d
RS		 761
762 /* If this is a complex assignment, see if we can convert it into a
5089e22e 763 simple assignment. */
230d793d 764 set = expand_field_assignment (set);
d79f08e0
RK		 765
766 /* If this is a simple assignment, or we have a paradoxical SUBREG,
767 set what we know about X. */
768
769 if (SET_DEST (set) == x
770 || (GET_CODE (SET_DEST (set)) == SUBREG
705c7b3b
JW		 771 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
772 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
d79f08e0 773 && SUBREG_REG (SET_DEST (set)) == x))
d0ab8cd3 774 {
9afa3d54
RK		 775 rtx src = SET_SRC (set);
776
777#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
778 /* If X is narrower than a word and SRC is a non-negative
779 constant that would appear negative in the mode of X,
780 sign-extend it for use in reg_nonzero_bits because some
781 machines (maybe most) will actually do the sign-extension
782 and this is the conservative approach.
783
784 ??? For 2.5, try to tighten up the MD files in this regard
785 instead of this kludge. */
786
787 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
788 && GET_CODE (src) == CONST_INT
789 && INTVAL (src) > 0
790 && 0 != (INTVAL (src)
791 & ((HOST_WIDE_INT) 1
9e69be8c 792 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 793 src = GEN_INT (INTVAL (src)
794 | ((HOST_WIDE_INT) (-1)
795 << GET_MODE_BITSIZE (GET_MODE (x))));
796#endif
797
951553af 798 reg_nonzero_bits[REGNO (x)]
9afa3d54 799 |= nonzero_bits (src, nonzero_bits_mode);
d0ab8cd3
RK		 800 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
801 if (reg_sign_bit_copies[REGNO (x)] == 0
802 || reg_sign_bit_copies[REGNO (x)] > num)
803 reg_sign_bit_copies[REGNO (x)] = num;
804 }
230d793d 805 else
d0ab8cd3 806 {
951553af 807 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 808 reg_sign_bit_copies[REGNO (x)] = 1;
d0ab8cd3 809 }
230d793d
RS		 810 }
811}
812\f
813/* See if INSN can be combined into I3. PRED and SUCC are optionally
814 insns that were previously combined into I3 or that will be combined
815 into the merger of INSN and I3.
816
817 Return 0 if the combination is not allowed for any reason.
818
819 If the combination is allowed, *PDEST will be set to the single
820 destination of INSN and *PSRC to the single source, and this function
821 will return 1. */
822
823static int
824can_combine_p (insn, i3, pred, succ, pdest, psrc)
825 rtx insn;
826 rtx i3;
827 rtx pred, succ;
828 rtx *pdest, *psrc;
829{
830 int i;
831 rtx set = 0, src, dest;
b729186a
JL		 832 rtx p;
833#ifdef AUTO_INC_DEC
76d31c63 834 rtx link;
b729186a 835#endif
230d793d
RS		 836 int all_adjacent = (succ ? (next_active_insn (insn) == succ
837 && next_active_insn (succ) == i3)
838 : next_active_insn (insn) == i3);
839
840 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
841 or a PARALLEL consisting of such a SET and CLOBBERs.
842
843 If INSN has CLOBBER parallel parts, ignore them for our processing.
844 By definition, these happen during the execution of the insn. When it
845 is merged with another insn, all bets are off. If they are, in fact,
846 needed and aren't also supplied in I3, they may be added by
847 recog_for_combine. Otherwise, it won't match.
848
849 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
850 note.
851
852 Get the source and destination of INSN. If more than one, can't
853 combine. */
854
855 if (GET_CODE (PATTERN (insn)) == SET)
856 set = PATTERN (insn);
857 else if (GET_CODE (PATTERN (insn)) == PARALLEL
858 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
859 {
860 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
861 {
862 rtx elt = XVECEXP (PATTERN (insn), 0, i);
863
864 switch (GET_CODE (elt))
865 {
e3258cef
R		 866 /* This is important to combine floating point insns
867 for the SH4 port. */
868 case USE:
869 /* Combining an isolated USE doesn't make sense.
870 We depend here on combinable_i3_pat to reject them. */
871 /* The code below this loop only verifies that the inputs of
872 the SET in INSN do not change. We call reg_set_between_p
873 to verify that the REG in the USE does not change betweeen
874 I3 and INSN.
875 If the USE in INSN was for a pseudo register, the matching
876 insn pattern will likely match any register; combining this
877 with any other USE would only be safe if we knew that the
878 used registers have identical values, or if there was
879 something to tell them apart, e.g. different modes. For
880 now, we forgo such compilcated tests and simply disallow
881 combining of USES of pseudo registers with any other USE. */
882 if (GET_CODE (XEXP (elt, 0)) == REG
883 && GET_CODE (PATTERN (i3)) == PARALLEL)
884 {
885 rtx i3pat = PATTERN (i3);
886 int i = XVECLEN (i3pat, 0) - 1;
887 int regno = REGNO (XEXP (elt, 0));
888 do
889 {
890 rtx i3elt = XVECEXP (i3pat, 0, i);
891 if (GET_CODE (i3elt) == USE
892 && GET_CODE (XEXP (i3elt, 0)) == REG
893 && (REGNO (XEXP (i3elt, 0)) == regno
894 ? reg_set_between_p (XEXP (elt, 0),
895 PREV_INSN (insn), i3)
896 : regno >= FIRST_PSEUDO_REGISTER))
897 return 0;
898 }
899 while (--i >= 0);
900 }
901 break;
902
230d793d
RS		 903 /* We can ignore CLOBBERs. */
904 case CLOBBER:
905 break;
906
907 case SET:
908 /* Ignore SETs whose result isn't used but not those that
909 have side-effects. */
910 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
911 && ! side_effects_p (elt))
912 break;
913
914 /* If we have already found a SET, this is a second one and
915 so we cannot combine with this insn. */
916 if (set)
917 return 0;
918
919 set = elt;
920 break;
921
922 default:
923 /* Anything else means we can't combine. */
924 return 0;
925 }
926 }
927
928 if (set == 0
929 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
930 so don't do anything with it. */
931 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
932 return 0;
933 }
934 else
935 return 0;
936
937 if (set == 0)
938 return 0;
939
940 set = expand_field_assignment (set);
941 src = SET_SRC (set), dest = SET_DEST (set);
942
943 /* Don't eliminate a store in the stack pointer. */
944 if (dest == stack_pointer_rtx
230d793d
RS		 945 /* If we couldn't eliminate a field assignment, we can't combine. */
946 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
947 /* Don't combine with an insn that sets a register to itself if it has
948 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
5f4f0e22 949 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
230d793d
RS		 950 /* Can't merge a function call. */
951 || GET_CODE (src) == CALL
cd5e8f1f 952 /* Don't eliminate a function call argument. */
4dca5ec5
RK		 953 || (GET_CODE (i3) == CALL_INSN
954 && (find_reg_fusage (i3, USE, dest)
955 || (GET_CODE (dest) == REG
956 && REGNO (dest) < FIRST_PSEUDO_REGISTER
957 && global_regs[REGNO (dest)])))
230d793d
RS		 958 /* Don't substitute into an incremented register. */
959 || FIND_REG_INC_NOTE (i3, dest)
960 || (succ && FIND_REG_INC_NOTE (succ, dest))
961 /* Don't combine the end of a libcall into anything. */
5f4f0e22 962 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
230d793d
RS		 963 /* Make sure that DEST is not used after SUCC but before I3. */
964 || (succ && ! all_adjacent
965 && reg_used_between_p (dest, succ, i3))
966 /* Make sure that the value that is to be substituted for the register
967 does not use any registers whose values alter in between. However,
968 If the insns are adjacent, a use can't cross a set even though we
969 think it might (this can happen for a sequence of insns each setting
970 the same destination; reg_last_set of that register might point to
d81481d3
RK		 971 a NOTE). If INSN has a REG_EQUIV note, the register is always
972 equivalent to the memory so the substitution is valid even if there
973 are intervening stores. Also, don't move a volatile asm or
974 UNSPEC_VOLATILE across any other insns. */
230d793d 975 || (! all_adjacent
d81481d3
RK		 976 && (((GET_CODE (src) != MEM
977 || ! find_reg_note (insn, REG_EQUIV, src))
978 && use_crosses_set_p (src, INSN_CUID (insn)))
a66a10c7
RS		 979 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
980 || GET_CODE (src) == UNSPEC_VOLATILE))
230d793d
RS		 981 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
982 better register allocation by not doing the combine. */
983 || find_reg_note (i3, REG_NO_CONFLICT, dest)
984 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
985 /* Don't combine across a CALL_INSN, because that would possibly
986 change whether the life span of some REGs crosses calls or not,
987 and it is a pain to update that information.
988 Exception: if source is a constant, moving it later can't hurt.
989 Accept that special case, because it helps -fforce-addr a lot. */
990 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
991 return 0;
992
993 /* DEST must either be a REG or CC0. */
994 if (GET_CODE (dest) == REG)
995 {
996 /* If register alignment is being enforced for multi-word items in all
997 cases except for parameters, it is possible to have a register copy
998 insn referencing a hard register that is not allowed to contain the
999 mode being copied and which would not be valid as an operand of most
1000 insns. Eliminate this problem by not combining with such an insn.
1001
1002 Also, on some machines we don't want to extend the life of a hard
4d2c432d
RK		 1003 register.
1004
1005 This is the same test done in can_combine except that we don't test
1006 if SRC is a CALL operation to permit a hard register with
1007 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1008 into account. */
230d793d
RS		 1009
1010 if (GET_CODE (src) == REG
1011 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1012 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
c448a43e
RK		 1013 /* Don't extend the life of a hard register unless it is
1014 user variable (if we have few registers) or it can't
1015 fit into the desired register (meaning something special
ecd40809
RK		 1016 is going on).
1017 Also avoid substituting a return register into I3, because
1018 reload can't handle a conflict with constraints of other
1019 inputs. */
230d793d 1020 || (REGNO (src) < FIRST_PSEUDO_REGISTER
c448a43e 1021 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
f95182a4
ILT		 1022 || (SMALL_REGISTER_CLASSES
1023 && ((! all_adjacent && ! REG_USERVAR_P (src))
1024 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
e9a25f70 1025 && ! REG_USERVAR_P (src))))))))
230d793d
RS		 1026 return 0;
1027 }
1028 else if (GET_CODE (dest) != CC0)
1029 return 0;
1030
5f96750d
RS		 1031 /* Don't substitute for a register intended as a clobberable operand.
1032 Similarly, don't substitute an expression containing a register that
1033 will be clobbered in I3. */
230d793d
RS		 1034 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1035 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1036 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
5f96750d
RS		 1037 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1038 src)
1039 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
230d793d
RS		 1040 return 0;
1041
1042 /* If INSN contains anything volatile, or is an `asm' (whether volatile
d276f2bb 1043 or not), reject, unless nothing volatile comes between it and I3 */
230d793d
RS		 1044
1045 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
d276f2bb
CM		 1046 {
1047 /* Make sure succ doesn't contain a volatile reference. */
1048 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1049 return 0;
1050
1051 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1052 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1053 && p != succ && volatile_refs_p (PATTERN (p)))
1054 return 0;
1055 }
230d793d 1056
b79ee7eb
RH		 1057 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1058 to be an explicit register variable, and was chosen for a reason. */
1059
1060 if (GET_CODE (src) == ASM_OPERANDS
1061 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1062 return 0;
1063
4b2cb4a2
RS		 1064 /* If there are any volatile insns between INSN and I3, reject, because
1065 they might affect machine state. */
1066
1067 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1068 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1069 && p != succ && volatile_insn_p (PATTERN (p)))
1070 return 0;
1071
230d793d
RS		 1072 /* If INSN or I2 contains an autoincrement or autodecrement,
1073 make sure that register is not used between there and I3,
1074 and not already used in I3 either.
1075 Also insist that I3 not be a jump; if it were one
1076 and the incremented register were spilled, we would lose. */
1077
1078#ifdef AUTO_INC_DEC
1079 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1080 if (REG_NOTE_KIND (link) == REG_INC
1081 && (GET_CODE (i3) == JUMP_INSN
1082 || reg_used_between_p (XEXP (link, 0), insn, i3)
1083 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1084 return 0;
1085#endif
1086
1087#ifdef HAVE_cc0
1088 /* Don't combine an insn that follows a CC0-setting insn.
1089 An insn that uses CC0 must not be separated from the one that sets it.
1090 We do, however, allow I2 to follow a CC0-setting insn if that insn
1091 is passed as I1; in that case it will be deleted also.
1092 We also allow combining in this case if all the insns are adjacent
1093 because that would leave the two CC0 insns adjacent as well.
1094 It would be more logical to test whether CC0 occurs inside I1 or I2,
1095 but that would be much slower, and this ought to be equivalent. */
1096
1097 p = prev_nonnote_insn (insn);
1098 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1099 && ! all_adjacent)
1100 return 0;
1101#endif
1102
1103 /* If we get here, we have passed all the tests and the combination is
1104 to be allowed. */
1105
1106 *pdest = dest;
1107 *psrc = src;
1108
1109 return 1;
1110}
1111\f
956d6950
JL		 1112/* Check if PAT is an insn - or a part of it - used to set up an
1113 argument for a function in a hard register. */
1114
1115static int
1116sets_function_arg_p (pat)
1117 rtx pat;
1118{
1119 int i;
1120 rtx inner_dest;
1121
1122 switch (GET_CODE (pat))
1123 {
1124 case INSN:
1125 return sets_function_arg_p (PATTERN (pat));
1126
1127 case PARALLEL:
1128 for (i = XVECLEN (pat, 0); --i >= 0;)
1129 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1130 return 1;
1131
1132 break;
1133
1134 case SET:
1135 inner_dest = SET_DEST (pat);
1136 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1137 || GET_CODE (inner_dest) == SUBREG
1138 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1139 inner_dest = XEXP (inner_dest, 0);
1140
1141 return (GET_CODE (inner_dest) == REG
1142 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1143 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1d300e19
KG		 1144
1145 default:
1146 break;
956d6950
JL		 1147 }
1148
1149 return 0;
1150}
1151
230d793d
RS		 1152/* LOC is the location within I3 that contains its pattern or the component
1153 of a PARALLEL of the pattern. We validate that it is valid for combining.
1154
1155 One problem is if I3 modifies its output, as opposed to replacing it
1156 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1157 so would produce an insn that is not equivalent to the original insns.
1158
1159 Consider:
1160
1161 (set (reg:DI 101) (reg:DI 100))
1162 (set (subreg:SI (reg:DI 101) 0) <foo>)
1163
1164 This is NOT equivalent to:
1165
1166 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1167 (set (reg:DI 101) (reg:DI 100))])
1168
1169 Not only does this modify 100 (in which case it might still be valid
1170 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1171
1172 We can also run into a problem if I2 sets a register that I1
1173 uses and I1 gets directly substituted into I3 (not via I2). In that
1174 case, we would be getting the wrong value of I2DEST into I3, so we
1175 must reject the combination. This case occurs when I2 and I1 both
1176 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1177 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1178 of a SET must prevent combination from occurring.
1179
e9a25f70 1180 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
c448a43e
RK		 1181 if the destination of a SET is a hard register that isn't a user
1182 variable.
230d793d
RS		 1183
1184 Before doing the above check, we first try to expand a field assignment
1185 into a set of logical operations.
1186
1187 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1188 we place a register that is both set and used within I3. If more than one
1189 such register is detected, we fail.
1190
1191 Return 1 if the combination is valid, zero otherwise. */
1192
1193static int
1194combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1195 rtx i3;
1196 rtx *loc;
1197 rtx i2dest;
1198 rtx i1dest;
1199 int i1_not_in_src;
1200 rtx *pi3dest_killed;
1201{
1202 rtx x = *loc;
1203
1204 if (GET_CODE (x) == SET)
1205 {
1206 rtx set = expand_field_assignment (x);
1207 rtx dest = SET_DEST (set);
1208 rtx src = SET_SRC (set);
29a82058
JL		 1209 rtx inner_dest = dest;
1210
1211#if 0
1212 rtx inner_src = src;
1213#endif
230d793d
RS		 1214
1215 SUBST (*loc, set);
1216
1217 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1218 || GET_CODE (inner_dest) == SUBREG
1219 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1220 inner_dest = XEXP (inner_dest, 0);
1221
1222 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1223 was added. */
1224#if 0
1225 while (GET_CODE (inner_src) == STRICT_LOW_PART
1226 || GET_CODE (inner_src) == SUBREG
1227 || GET_CODE (inner_src) == ZERO_EXTRACT)
1228 inner_src = XEXP (inner_src, 0);
1229
1230 /* If it is better that two different modes keep two different pseudos,
1231 avoid combining them. This avoids producing the following pattern
1232 on a 386:
1233 (set (subreg:SI (reg/v:QI 21) 0)
1234 (lshiftrt:SI (reg/v:SI 20)
1235 (const_int 24)))
1236 If that were made, reload could not handle the pair of
1237 reg 20/21, since it would try to get any GENERAL_REGS
1238 but some of them don't handle QImode. */
1239
1240 if (rtx_equal_p (inner_src, i2dest)
1241 && GET_CODE (inner_dest) == REG
1242 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1243 return 0;
1244#endif
1245
1246 /* Check for the case where I3 modifies its output, as
1247 discussed above. */
1248 if ((inner_dest != dest
1249 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1250 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
956d6950 1251
3f508eca
RK		 1252 /* This is the same test done in can_combine_p except that we
1253 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
956d6950
JL		 1254 CALL operation. Moreover, we can't test all_adjacent; we don't
1255 have to, since this instruction will stay in place, thus we are
1256 not considering increasing the lifetime of INNER_DEST.
1257
1258 Also, if this insn sets a function argument, combining it with
1259 something that might need a spill could clobber a previous
1260 function argument; the all_adjacent test in can_combine_p also
1261 checks this; here, we do a more specific test for this case. */
1262
230d793d 1263 || (GET_CODE (inner_dest) == REG
dfbe1b2f 1264 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
c448a43e
RK		 1265 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1266 GET_MODE (inner_dest))
e9a25f70
JL		 1267 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1268 && ! REG_USERVAR_P (inner_dest)
956d6950
JL		 1269 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1270 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1271 && i3 != 0
1272 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
230d793d
RS		 1273 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1274 return 0;
1275
1276 /* If DEST is used in I3, it is being killed in this insn,
36a9c2e9
JL		 1277 so record that for later.
1278 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1279 STACK_POINTER_REGNUM, since these are always considered to be
1280 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
230d793d 1281 if (pi3dest_killed && GET_CODE (dest) == REG
36a9c2e9
JL		 1282 && reg_referenced_p (dest, PATTERN (i3))
1283 && REGNO (dest) != FRAME_POINTER_REGNUM
6d7096b0
DE		 1284#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1285 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1286#endif
36a9c2e9
JL		 1287#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1288 && (REGNO (dest) != ARG_POINTER_REGNUM
1289 || ! fixed_regs [REGNO (dest)])
1290#endif
1291 && REGNO (dest) != STACK_POINTER_REGNUM)
230d793d
RS		 1292 {
1293 if (*pi3dest_killed)
1294 return 0;
1295
1296 *pi3dest_killed = dest;
1297 }
1298 }
1299
1300 else if (GET_CODE (x) == PARALLEL)
1301 {
1302 int i;
1303
1304 for (i = 0; i < XVECLEN (x, 0); i++)
1305 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1306 i1_not_in_src, pi3dest_killed))
1307 return 0;
1308 }
1309
1310 return 1;
1311}
1312\f
1313/* Try to combine the insns I1 and I2 into I3.
1314 Here I1 and I2 appear earlier than I3.
1315 I1 can be zero; then we combine just I2 into I3.
1316
1317 It we are combining three insns and the resulting insn is not recognized,
1318 try splitting it into two insns. If that happens, I2 and I3 are retained
1319 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1320 are pseudo-deleted.
1321
abe6e52f
RK		 1322 Return 0 if the combination does not work. Then nothing is changed.
1323 If we did the combination, return the insn at which combine should
1324 resume scanning. */
230d793d
RS		 1325
1326static rtx
1327try_combine (i3, i2, i1)
1328 register rtx i3, i2, i1;
1329{
1330 /* New patterns for I3 and I3, respectively. */
1331 rtx newpat, newi2pat = 0;
1332 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1333 int added_sets_1, added_sets_2;
1334 /* Total number of SETs to put into I3. */
1335 int total_sets;
1336 /* Nonzero is I2's body now appears in I3. */
1337 int i2_is_used;
1338 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1339 int insn_code_number, i2_code_number, other_code_number;
1340 /* Contains I3 if the destination of I3 is used in its source, which means
1341 that the old life of I3 is being killed. If that usage is placed into
1342 I2 and not in I3, a REG_DEAD note must be made. */
1343 rtx i3dest_killed = 0;
1344 /* SET_DEST and SET_SRC of I2 and I1. */
1345 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1346 /* PATTERN (I2), or a copy of it in certain cases. */
1347 rtx i2pat;
1348 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
c4e861e8 1349 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
230d793d
RS		 1350 int i1_feeds_i3 = 0;
1351 /* Notes that must be added to REG_NOTES in I3 and I2. */
1352 rtx new_i3_notes, new_i2_notes;
176c9e6b
JW		 1353 /* Notes that we substituted I3 into I2 instead of the normal case. */
1354 int i3_subst_into_i2 = 0;
df7d75de
RK		 1355 /* Notes that I1, I2 or I3 is a MULT operation. */
1356 int have_mult = 0;
a29ca9db
RK		 1357 /* Number of clobbers of SCRATCH we had to add. */
1358 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
230d793d
RS		 1359
1360 int maxreg;
1361 rtx temp;
1362 register rtx link;
1363 int i;
1364
1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1366 This can occur when flow deletes an insn that it has merged into an
1367 auto-increment address. We also can't do anything if I3 has a
1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1369 libcall. */
1370
1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
5f4f0e22 1374 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
230d793d
RS		 1375 return 0;
1376
1377 combine_attempts++;
1378
241cea85 1379 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 1380 undobuf.other_insn = 0;
1381
1382 /* Save the current high-water-mark so we can free storage if we didn't
1383 accept this combination. */
1384 undobuf.storage = (char *) oballoc (0);
1385
6e25d159
RK		 1386 /* Reset the hard register usage information. */
1387 CLEAR_HARD_REG_SET (newpat_used_regs);
1388
230d793d
RS		 1389 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1390 code below, set I1 to be the earlier of the two insns. */
1391 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1392 temp = i1, i1 = i2, i2 = temp;
1393
abe6e52f 1394 added_links_insn = 0;
137e889e 1395
230d793d
RS		 1396 /* First check for one important special-case that the code below will
1397 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1398 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1399 we may be able to replace that destination with the destination of I3.
1400 This occurs in the common code where we compute both a quotient and
1401 remainder into a structure, in which case we want to do the computation
1402 directly into the structure to avoid register-register copies.
1403
1404 We make very conservative checks below and only try to handle the
1405 most common cases of this. For example, we only handle the case
1406 where I2 and I3 are adjacent to avoid making difficult register
1407 usage tests. */
1408
1409 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1410 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1411 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
f95182a4 1412 && (! SMALL_REGISTER_CLASSES
e9a25f70
JL		 1413 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1414 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1415 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
230d793d
RS		 1416 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1417 && GET_CODE (PATTERN (i2)) == PARALLEL
1418 && ! side_effects_p (SET_DEST (PATTERN (i3)))
5089e22e
RS		 1419 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1420 below would need to check what is inside (and reg_overlap_mentioned_p
1421 doesn't support those codes anyway). Don't allow those destinations;
1422 the resulting insn isn't likely to be recognized anyway. */
1423 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1424 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
230d793d
RS		 1425 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1426 SET_DEST (PATTERN (i3)))
1427 && next_real_insn (i2) == i3)
5089e22e
RS		 1428 {
1429 rtx p2 = PATTERN (i2);
1430
1431 /* Make sure that the destination of I3,
1432 which we are going to substitute into one output of I2,
1433 is not used within another output of I2. We must avoid making this:
1434 (parallel [(set (mem (reg 69)) ...)
1435 (set (reg 69) ...)])
1436 which is not well-defined as to order of actions.
1437 (Besides, reload can't handle output reloads for this.)
1438
1439 The problem can also happen if the dest of I3 is a memory ref,
1440 if another dest in I2 is an indirect memory ref. */
1441 for (i = 0; i < XVECLEN (p2, 0); i++)
7ca919b7
RK		 1442 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1443 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
5089e22e
RS		 1444 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1445 SET_DEST (XVECEXP (p2, 0, i))))
1446 break;
230d793d 1447
5089e22e
RS		 1448 if (i == XVECLEN (p2, 0))
1449 for (i = 0; i < XVECLEN (p2, 0); i++)
1450 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1451 {
1452 combine_merges++;
230d793d 1453
5089e22e
RS		 1454 subst_insn = i3;
1455 subst_low_cuid = INSN_CUID (i2);
230d793d 1456
c4e861e8 1457 added_sets_2 = added_sets_1 = 0;
5089e22e 1458 i2dest = SET_SRC (PATTERN (i3));
230d793d 1459
5089e22e
RS		 1460 /* Replace the dest in I2 with our dest and make the resulting
1461 insn the new pattern for I3. Then skip to where we
1462 validate the pattern. Everything was set up above. */
1463 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1464 SET_DEST (PATTERN (i3)));
1465
1466 newpat = p2;
176c9e6b 1467 i3_subst_into_i2 = 1;
5089e22e
RS		 1468 goto validate_replacement;
1469 }
1470 }
230d793d
RS		 1471
1472#ifndef HAVE_cc0
1473 /* If we have no I1 and I2 looks like:
1474 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1475 (set Y OP)])
1476 make up a dummy I1 that is
1477 (set Y OP)
1478 and change I2 to be
1479 (set (reg:CC X) (compare:CC Y (const_int 0)))
1480
1481 (We can ignore any trailing CLOBBERs.)
1482
1483 This undoes a previous combination and allows us to match a branch-and-
1484 decrement insn. */
1485
1486 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1487 && XVECLEN (PATTERN (i2), 0) >= 2
1488 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1489 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1490 == MODE_CC)
1491 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1492 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1494 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1495 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1496 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1497 {
1498 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1499 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1500 break;
1501
1502 if (i == 1)
1503 {
1504 /* We make I1 with the same INSN_UID as I2. This gives it
1505 the same INSN_CUID for value tracking. Our fake I1 will
1506 never appear in the insn stream so giving it the same INSN_UID
1507 as I2 will not cause a problem. */
1508
0d9641d1 1509 subst_prev_insn = i1
38a448ca
RH		 1510 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1511 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1512 NULL_RTX);
230d793d
RS		 1513
1514 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1515 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1516 SET_DEST (PATTERN (i1)));
1517 }
1518 }
1519#endif
1520
1521 /* Verify that I2 and I1 are valid for combining. */
5f4f0e22
CH		 1522 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1523 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
230d793d
RS		 1524 {
1525 undo_all ();
1526 return 0;
1527 }
1528
1529 /* Record whether I2DEST is used in I2SRC and similarly for the other
1530 cases. Knowing this will help in register status updating below. */
1531 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1532 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1533 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1534
916f14f1 1535 /* See if I1 directly feeds into I3. It does if I1DEST is not used
230d793d
RS		 1536 in I2SRC. */
1537 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1538
1539 /* Ensure that I3's pattern can be the destination of combines. */
1540 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1541 i1 && i2dest_in_i1src && i1_feeds_i3,
1542 &i3dest_killed))
1543 {
1544 undo_all ();
1545 return 0;
1546 }
1547
df7d75de
RK		 1548 /* See if any of the insns is a MULT operation. Unless one is, we will
1549 reject a combination that is, since it must be slower. Be conservative
1550 here. */
1551 if (GET_CODE (i2src) == MULT
1552 || (i1 != 0 && GET_CODE (i1src) == MULT)
1553 || (GET_CODE (PATTERN (i3)) == SET
1554 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1555 have_mult = 1;
1556
230d793d
RS		 1557 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1558 We used to do this EXCEPT in one case: I3 has a post-inc in an
1559 output operand. However, that exception can give rise to insns like
1560 mov r3,(r3)+
1561 which is a famous insn on the PDP-11 where the value of r3 used as the
5089e22e 1562 source was model-dependent. Avoid this sort of thing. */
230d793d
RS		 1563
1564#if 0
1565 if (!(GET_CODE (PATTERN (i3)) == SET
1566 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1567 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1568 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1569 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1570 /* It's not the exception. */
1571#endif
1572#ifdef AUTO_INC_DEC
1573 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1574 if (REG_NOTE_KIND (link) == REG_INC
1575 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1576 || (i1 != 0
1577 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1578 {
1579 undo_all ();
1580 return 0;
1581 }
1582#endif
1583
1584 /* See if the SETs in I1 or I2 need to be kept around in the merged
1585 instruction: whenever the value set there is still needed past I3.
1586 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1587
1588 For the SET in I1, we have two cases: If I1 and I2 independently
1589 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1590 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1591 in I1 needs to be kept around unless I1DEST dies or is set in either
1592 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1593 I1DEST. If so, we know I1 feeds into I2. */
1594
1595 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1596
1597 added_sets_1
1598 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1599 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1600
1601 /* If the set in I2 needs to be kept around, we must make a copy of
1602 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
5089e22e 1603 PATTERN (I2), we are only substituting for the original I1DEST, not into
230d793d
RS		 1604 an already-substituted copy. This also prevents making self-referential
1605 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1606 I2DEST. */
1607
1608 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
38a448ca 1609 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
230d793d
RS		 1610 : PATTERN (i2));
1611
1612 if (added_sets_2)
1613 i2pat = copy_rtx (i2pat);
1614
1615 combine_merges++;
1616
1617 /* Substitute in the latest insn for the regs set by the earlier ones. */
1618
1619 maxreg = max_reg_num ();
1620
1621 subst_insn = i3;
230d793d
RS		 1622
1623 /* It is possible that the source of I2 or I1 may be performing an
1624 unneeded operation, such as a ZERO_EXTEND of something that is known
1625 to have the high part zero. Handle that case by letting subst look at
1626 the innermost one of them.
1627
1628 Another way to do this would be to have a function that tries to
1629 simplify a single insn instead of merging two or more insns. We don't
1630 do this because of the potential of infinite loops and because
1631 of the potential extra memory required. However, doing it the way
1632 we are is a bit of a kludge and doesn't catch all cases.
1633
1634 But only do this if -fexpensive-optimizations since it slows things down
1635 and doesn't usually win. */
1636
1637 if (flag_expensive_optimizations)
1638 {
1639 /* Pass pc_rtx so no substitutions are done, just simplifications.
1640 The cases that we are interested in here do not involve the few
1641 cases were is_replaced is checked. */
1642 if (i1)
d0ab8cd3
RK		 1643 {
1644 subst_low_cuid = INSN_CUID (i1);
1645 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1646 }
230d793d 1647 else
d0ab8cd3
RK		 1648 {
1649 subst_low_cuid = INSN_CUID (i2);
1650 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1651 }
230d793d 1652
241cea85 1653 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1654 }
1655
1656#ifndef HAVE_cc0
1657 /* Many machines that don't use CC0 have insns that can both perform an
1658 arithmetic operation and set the condition code. These operations will
1659 be represented as a PARALLEL with the first element of the vector
1660 being a COMPARE of an arithmetic operation with the constant zero.
1661 The second element of the vector will set some pseudo to the result
1662 of the same arithmetic operation. If we simplify the COMPARE, we won't
1663 match such a pattern and so will generate an extra insn. Here we test
1664 for this case, where both the comparison and the operation result are
1665 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1666 I2SRC. Later we will make the PARALLEL that contains I2. */
1667
1668 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1669 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1670 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1671 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1672 {
081f5e7e 1673#ifdef EXTRA_CC_MODES
230d793d
RS		 1674 rtx *cc_use;
1675 enum machine_mode compare_mode;
081f5e7e 1676#endif
230d793d
RS		 1677
1678 newpat = PATTERN (i3);
1679 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1680
1681 i2_is_used = 1;
1682
1683#ifdef EXTRA_CC_MODES
1684 /* See if a COMPARE with the operand we substituted in should be done
1685 with the mode that is currently being used. If not, do the same
1686 processing we do in `subst' for a SET; namely, if the destination
1687 is used only once, try to replace it with a register of the proper
1688 mode and also replace the COMPARE. */
1689 if (undobuf.other_insn == 0
1690 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1691 &undobuf.other_insn))
77fa0940
RK		 1692 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1693 i2src, const0_rtx))
230d793d
RS		 1694 != GET_MODE (SET_DEST (newpat))))
1695 {
1696 int regno = REGNO (SET_DEST (newpat));
38a448ca 1697 rtx new_dest = gen_rtx_REG (compare_mode, regno);
230d793d
RS		 1698
1699 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 1700 || (REG_N_SETS (regno) == 1 && ! added_sets_2
230d793d
RS		 1701 && ! REG_USERVAR_P (SET_DEST (newpat))))
1702 {
1703 if (regno >= FIRST_PSEUDO_REGISTER)
1704 SUBST (regno_reg_rtx[regno], new_dest);
1705
1706 SUBST (SET_DEST (newpat), new_dest);
1707 SUBST (XEXP (*cc_use, 0), new_dest);
1708 SUBST (SET_SRC (newpat),
1709 gen_rtx_combine (COMPARE, compare_mode,
1710 i2src, const0_rtx));
1711 }
1712 else
1713 undobuf.other_insn = 0;
1714 }
1715#endif
1716 }
1717 else
1718#endif
1719 {
1720 n_occurrences = 0; /* `subst' counts here */
1721
1722 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1723 need to make a unique copy of I2SRC each time we substitute it
1724 to avoid self-referential rtl. */
1725
d0ab8cd3 1726 subst_low_cuid = INSN_CUID (i2);
230d793d
RS		 1727 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1728 ! i1_feeds_i3 && i1dest_in_i1src);
241cea85 1729 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1730
1731 /* Record whether i2's body now appears within i3's body. */
1732 i2_is_used = n_occurrences;
1733 }
1734
1735 /* If we already got a failure, don't try to do more. Otherwise,
1736 try to substitute in I1 if we have it. */
1737
1738 if (i1 && GET_CODE (newpat) != CLOBBER)
1739 {
1740 /* Before we can do this substitution, we must redo the test done
1741 above (see detailed comments there) that ensures that I1DEST
0f41302f 1742 isn't mentioned in any SETs in NEWPAT that are field assignments. */
230d793d 1743
5f4f0e22
CH		 1744 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1745 0, NULL_PTR))
230d793d
RS		 1746 {
1747 undo_all ();
1748 return 0;
1749 }
1750
1751 n_occurrences = 0;
d0ab8cd3 1752 subst_low_cuid = INSN_CUID (i1);
230d793d 1753 newpat = subst (newpat, i1dest, i1src, 0, 0);
241cea85 1754 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1755 }
1756
916f14f1
RK		 1757 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1758 to count all the ways that I2SRC and I1SRC can be used. */
5f4f0e22 1759 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
916f14f1 1760 && i2_is_used + added_sets_2 > 1)
5f4f0e22 1761 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
916f14f1
RK		 1762 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1763 > 1))
230d793d
RS		 1764 /* Fail if we tried to make a new register (we used to abort, but there's
1765 really no reason to). */
1766 || max_reg_num () != maxreg
1767 /* Fail if we couldn't do something and have a CLOBBER. */
df7d75de
RK		 1768 || GET_CODE (newpat) == CLOBBER
1769 /* Fail if this new pattern is a MULT and we didn't have one before
1770 at the outer level. */
1771 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1772 && ! have_mult))
230d793d
RS		 1773 {
1774 undo_all ();
1775 return 0;
1776 }
1777
1778 /* If the actions of the earlier insns must be kept
1779 in addition to substituting them into the latest one,
1780 we must make a new PARALLEL for the latest insn
1781 to hold additional the SETs. */
1782
1783 if (added_sets_1 || added_sets_2)
1784 {
1785 combine_extras++;
1786
1787 if (GET_CODE (newpat) == PARALLEL)
1788 {
1789 rtvec old = XVEC (newpat, 0);
1790 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
38a448ca 1791 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
59888de2 1792 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
230d793d
RS		 1793 sizeof (old->elem[0]) * old->num_elem);
1794 }
1795 else
1796 {
1797 rtx old = newpat;
1798 total_sets = 1 + added_sets_1 + added_sets_2;
38a448ca 1799 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
230d793d
RS		 1800 XVECEXP (newpat, 0, 0) = old;
1801 }
1802
1803 if (added_sets_1)
1804 XVECEXP (newpat, 0, --total_sets)
1805 = (GET_CODE (PATTERN (i1)) == PARALLEL
38a448ca 1806 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
230d793d
RS		 1807
1808 if (added_sets_2)
1809 {
1810 /* If there is no I1, use I2's body as is. We used to also not do
1811 the subst call below if I2 was substituted into I3,
1812 but that could lose a simplification. */
1813 if (i1 == 0)
1814 XVECEXP (newpat, 0, --total_sets) = i2pat;
1815 else
1816 /* See comment where i2pat is assigned. */
1817 XVECEXP (newpat, 0, --total_sets)
1818 = subst (i2pat, i1dest, i1src, 0, 0);
1819 }
1820 }
1821
1822 /* We come here when we are replacing a destination in I2 with the
1823 destination of I3. */
1824 validate_replacement:
1825
6e25d159
RK		 1826 /* Note which hard regs this insn has as inputs. */
1827 mark_used_regs_combine (newpat);
1828
230d793d 1829 /* Is the result of combination a valid instruction? */
a29ca9db
RK		 1830 insn_code_number
1831 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1832
1833 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1834 the second SET's destination is a register that is unused. In that case,
1835 we just need the first SET. This can occur when simplifying a divmod
1836 insn. We *must* test for this case here because the code below that
1837 splits two independent SETs doesn't handle this case correctly when it
1838 updates the register status. Also check the case where the first
1839 SET's destination is unused. That would not cause incorrect code, but
1840 does cause an unneeded insn to remain. */
1841
1842 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1843 && XVECLEN (newpat, 0) == 2
1844 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1845 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1846 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1847 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1848 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1849 && asm_noperands (newpat) < 0)
1850 {
1851 newpat = XVECEXP (newpat, 0, 0);
a29ca9db
RK		 1852 insn_code_number
1853 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1854 }
1855
1856 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1857 && XVECLEN (newpat, 0) == 2
1858 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1859 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1860 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1861 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1862 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1863 && asm_noperands (newpat) < 0)
1864 {
1865 newpat = XVECEXP (newpat, 0, 1);
a29ca9db
RK		 1866 insn_code_number
1867 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1868 }
1869
1870 /* If we were combining three insns and the result is a simple SET
1871 with no ASM_OPERANDS that wasn't recognized, try to split it into two
916f14f1
RK		 1872 insns. There are two ways to do this. It can be split using a
1873 machine-specific method (like when you have an addition of a large
1874 constant) or by combine in the function find_split_point. */
1875
230d793d
RS		 1876 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1877 && asm_noperands (newpat) < 0)
1878 {
916f14f1 1879 rtx m_split, *split;
42495ca0 1880 rtx ni2dest = i2dest;
916f14f1
RK		 1881
1882 /* See if the MD file can split NEWPAT. If it can't, see if letting it
42495ca0
RK		 1883 use I2DEST as a scratch register will help. In the latter case,
1884 convert I2DEST to the mode of the source of NEWPAT if we can. */
916f14f1
RK		 1885
1886 m_split = split_insns (newpat, i3);
a70c61d9
JW		 1887
1888 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1889 inputs of NEWPAT. */
1890
1891 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1892 possible to try that as a scratch reg. This would require adding
1893 more code to make it work though. */
1894
1895 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
42495ca0
RK		 1896 {
1897 /* If I2DEST is a hard register or the only use of a pseudo,
1898 we can change its mode. */
1899 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
02f4ada4 1900 && GET_MODE (SET_DEST (newpat)) != VOIDmode
60654f77 1901 && GET_CODE (i2dest) == REG
42495ca0 1902 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1903 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
42495ca0 1904 && ! REG_USERVAR_P (i2dest))))
38a448ca 1905 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
42495ca0
RK		 1906 REGNO (i2dest));
1907
38a448ca
RH		 1908 m_split = split_insns
1909 (gen_rtx_PARALLEL (VOIDmode,
1910 gen_rtvec (2, newpat,
1911 gen_rtx_CLOBBER (VOIDmode,
1912 ni2dest))),
1913 i3);
42495ca0 1914 }
916f14f1
RK		 1915
1916 if (m_split && GET_CODE (m_split) == SEQUENCE
3f508eca
RK		 1917 && XVECLEN (m_split, 0) == 2
1918 && (next_real_insn (i2) == i3
1919 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1920 INSN_CUID (i2))))
916f14f1 1921 {
1a26b032 1922 rtx i2set, i3set;
d0ab8cd3 1923 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
916f14f1 1924 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
916f14f1 1925
e4ba89be
RK		 1926 i3set = single_set (XVECEXP (m_split, 0, 1));
1927 i2set = single_set (XVECEXP (m_split, 0, 0));
1a26b032 1928
42495ca0
RK		 1929 /* In case we changed the mode of I2DEST, replace it in the
1930 pseudo-register table here. We can't do it above in case this
1931 code doesn't get executed and we do a split the other way. */
1932
1933 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1934 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1935
a29ca9db
RK		 1936 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1937 &i2_scratches);
1a26b032
RK		 1938
1939 /* If I2 or I3 has multiple SETs, we won't know how to track
9cc96794
RK		 1940 register status, so don't use these insns. If I2's destination
1941 is used between I2 and I3, we also can't use these insns. */
1a26b032 1942
9cc96794
RK		 1943 if (i2_code_number >= 0 && i2set && i3set
1944 && (next_real_insn (i2) == i3
1945 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
a29ca9db
RK		 1946 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1947 &i3_scratches);
d0ab8cd3
RK		 1948 if (insn_code_number >= 0)
1949 newpat = newi3pat;
1950
c767f54b 1951 /* It is possible that both insns now set the destination of I3.
22609cbf 1952 If so, we must show an extra use of it. */
c767f54b 1953
393de53f
RK		 1954 if (insn_code_number >= 0)
1955 {
1956 rtx new_i3_dest = SET_DEST (i3set);
1957 rtx new_i2_dest = SET_DEST (i2set);
1958
1959 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1960 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1961 || GET_CODE (new_i3_dest) == SUBREG)
1962 new_i3_dest = XEXP (new_i3_dest, 0);
1963
d4096689
RK		 1964 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1965 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1966 || GET_CODE (new_i2_dest) == SUBREG)
1967 new_i2_dest = XEXP (new_i2_dest, 0);
1968
393de53f
RK		 1969 if (GET_CODE (new_i3_dest) == REG
1970 && GET_CODE (new_i2_dest) == REG
1971 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
b1f21e0a 1972 REG_N_SETS (REGNO (new_i2_dest))++;
393de53f 1973 }
916f14f1 1974 }
230d793d
RS		 1975
1976 /* If we can split it and use I2DEST, go ahead and see if that
1977 helps things be recognized. Verify that none of the registers
1978 are set between I2 and I3. */
d0ab8cd3 1979 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
230d793d
RS		 1980#ifdef HAVE_cc0
1981 && GET_CODE (i2dest) == REG
1982#endif
1983 /* We need I2DEST in the proper mode. If it is a hard register
1984 or the only use of a pseudo, we can change its mode. */
1985 && (GET_MODE (*split) == GET_MODE (i2dest)
1986 || GET_MODE (*split) == VOIDmode
1987 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1988 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
230d793d
RS		 1989 && ! REG_USERVAR_P (i2dest)))
1990 && (next_real_insn (i2) == i3
1991 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1992 /* We can't overwrite I2DEST if its value is still used by
1993 NEWPAT. */
1994 && ! reg_referenced_p (i2dest, newpat))
1995 {
1996 rtx newdest = i2dest;
df7d75de
RK		 1997 enum rtx_code split_code = GET_CODE (*split);
1998 enum machine_mode split_mode = GET_MODE (*split);
230d793d
RS		 1999
2000 /* Get NEWDEST as a register in the proper mode. We have already
2001 validated that we can do this. */
df7d75de 2002 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
230d793d 2003 {
38a448ca 2004 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
230d793d
RS		 2005
2006 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2007 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2008 }
2009
2010 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2011 an ASHIFT. This can occur if it was inside a PLUS and hence
2012 appeared to be a memory address. This is a kludge. */
df7d75de 2013 if (split_code == MULT
230d793d
RS		 2014 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2015 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1dc8a823
JW		 2016 {
2017 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2018 XEXP (*split, 0), GEN_INT (i)));
2019 /* Update split_code because we may not have a multiply
2020 anymore. */
2021 split_code = GET_CODE (*split);
2022 }
230d793d
RS		 2023
2024#ifdef INSN_SCHEDULING
2025 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2026 be written as a ZERO_EXTEND. */
df7d75de
RK		 2027 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2028 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
230d793d
RS		 2029 XEXP (*split, 0)));
2030#endif
2031
2032 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2033 SUBST (*split, newdest);
a29ca9db
RK		 2034 i2_code_number
2035 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
df7d75de
RK		 2036
2037 /* If the split point was a MULT and we didn't have one before,
2038 don't use one now. */
2039 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
a29ca9db
RK		 2040 insn_code_number
2041 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 2042 }
2043 }
2044
2045 /* Check for a case where we loaded from memory in a narrow mode and
2046 then sign extended it, but we need both registers. In that case,
2047 we have a PARALLEL with both loads from the same memory location.
2048 We can split this into a load from memory followed by a register-register
2049 copy. This saves at least one insn, more if register allocation can
f0343c74
RK		 2050 eliminate the copy.
2051
2052 We cannot do this if the destination of the second assignment is
2053 a register that we have already assumed is zero-extended. Similarly
2054 for a SUBREG of such a register. */
230d793d
RS		 2055
2056 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2057 && GET_CODE (newpat) == PARALLEL
2058 && XVECLEN (newpat, 0) == 2
2059 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2060 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2061 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2062 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2063 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2064 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2065 INSN_CUID (i2))
2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2067 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
f0343c74
RK		 2068 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2069 (GET_CODE (temp) == REG
2070 && reg_nonzero_bits[REGNO (temp)] != 0
2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2072 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2073 && (reg_nonzero_bits[REGNO (temp)]
2074 != GET_MODE_MASK (word_mode))))
2075 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2076 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2077 (GET_CODE (temp) == REG
2078 && reg_nonzero_bits[REGNO (temp)] != 0
2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2080 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2081 && (reg_nonzero_bits[REGNO (temp)]
2082 != GET_MODE_MASK (word_mode)))))
230d793d
RS		 2083 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2084 SET_SRC (XVECEXP (newpat, 0, 1)))
2085 && ! find_reg_note (i3, REG_UNUSED,
2086 SET_DEST (XVECEXP (newpat, 0, 0))))
2087 {
472fbdd1
RK		 2088 rtx ni2dest;
2089
230d793d 2090 newi2pat = XVECEXP (newpat, 0, 0);
472fbdd1 2091 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
230d793d
RS		 2092 newpat = XVECEXP (newpat, 0, 1);
2093 SUBST (SET_SRC (newpat),
472fbdd1 2094 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
a29ca9db
RK		 2095 i2_code_number
2096 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2097
230d793d 2098 if (i2_code_number >= 0)
a29ca9db
RK		 2099 insn_code_number
2100 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
5089e22e
RS		 2101
2102 if (insn_code_number >= 0)
2103 {
2104 rtx insn;
2105 rtx link;
2106
2107 /* If we will be able to accept this, we have made a change to the
2108 destination of I3. This can invalidate a LOG_LINKS pointing
2109 to I3. No other part of combine.c makes such a transformation.
2110
2111 The new I3 will have a destination that was previously the
2112 destination of I1 or I2 and which was used in i2 or I3. Call
2113 distribute_links to make a LOG_LINK from the next use of
2114 that destination. */
2115
2116 PATTERN (i3) = newpat;
38a448ca 2117 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
5089e22e
RS		 2118
2119 /* I3 now uses what used to be its destination and which is
2120 now I2's destination. That means we need a LOG_LINK from
2121 I3 to I2. But we used to have one, so we still will.
2122
2123 However, some later insn might be using I2's dest and have
2124 a LOG_LINK pointing at I3. We must remove this link.
2125 The simplest way to remove the link is to point it at I1,
2126 which we know will be a NOTE. */
2127
2128 for (insn = NEXT_INSN (i3);
0d4d42c3
RK		 2129 insn && (this_basic_block == n_basic_blocks - 1
2130 || insn != basic_block_head[this_basic_block + 1]);
5089e22e
RS		 2131 insn = NEXT_INSN (insn))
2132 {
2133 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
472fbdd1 2134 && reg_referenced_p (ni2dest, PATTERN (insn)))
5089e22e
RS		 2135 {
2136 for (link = LOG_LINKS (insn); link;
2137 link = XEXP (link, 1))
2138 if (XEXP (link, 0) == i3)
2139 XEXP (link, 0) = i1;
2140
2141 break;
2142 }
2143 }
2144 }
230d793d
RS		 2145 }
2146
2147 /* Similarly, check for a case where we have a PARALLEL of two independent
2148 SETs but we started with three insns. In this case, we can do the sets
2149 as two separate insns. This case occurs when some SET allows two
2150 other insns to combine, but the destination of that SET is still live. */
2151
2152 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2153 && GET_CODE (newpat) == PARALLEL
2154 && XVECLEN (newpat, 0) == 2
2155 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2156 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2158 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2159 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2160 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2161 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2162 INSN_CUID (i2))
2163 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2164 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2165 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2166 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2167 XVECEXP (newpat, 0, 0))
2168 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2169 XVECEXP (newpat, 0, 1)))
2170 {
e9a25f70
JL		 2171 /* Normally, it doesn't matter which of the two is done first,
2172 but it does if one references cc0. In that case, it has to
2173 be first. */
2174#ifdef HAVE_cc0
2175 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2176 {
2177 newi2pat = XVECEXP (newpat, 0, 0);
2178 newpat = XVECEXP (newpat, 0, 1);
2179 }
2180 else
2181#endif
2182 {
2183 newi2pat = XVECEXP (newpat, 0, 1);
2184 newpat = XVECEXP (newpat, 0, 0);
2185 }
230d793d 2186
a29ca9db
RK		 2187 i2_code_number
2188 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2189
230d793d 2190 if (i2_code_number >= 0)
a29ca9db
RK		 2191 insn_code_number
2192 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 2193 }
2194
2195 /* If it still isn't recognized, fail and change things back the way they
2196 were. */
2197 if ((insn_code_number < 0
2198 /* Is the result a reasonable ASM_OPERANDS? */
2199 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2200 {
2201 undo_all ();
2202 return 0;
2203 }
2204
2205 /* If we had to change another insn, make sure it is valid also. */
2206 if (undobuf.other_insn)
2207 {
230d793d
RS		 2208 rtx other_pat = PATTERN (undobuf.other_insn);
2209 rtx new_other_notes;
2210 rtx note, next;
2211
6e25d159
RK		 2212 CLEAR_HARD_REG_SET (newpat_used_regs);
2213
a29ca9db
RK		 2214 other_code_number
2215 = recog_for_combine (&other_pat, undobuf.other_insn,
2216 &new_other_notes, &other_scratches);
230d793d
RS		 2217
2218 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2219 {
2220 undo_all ();
2221 return 0;
2222 }
2223
2224 PATTERN (undobuf.other_insn) = other_pat;
2225
2226 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2227 are still valid. Then add any non-duplicate notes added by
2228 recog_for_combine. */
2229 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2230 {
2231 next = XEXP (note, 1);
2232
2233 if (REG_NOTE_KIND (note) == REG_UNUSED
2234 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1a26b032
RK		 2235 {
2236 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2237 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
1a26b032
RK		 2238
2239 remove_note (undobuf.other_insn, note);
2240 }
230d793d
RS		 2241 }
2242
1a26b032
RK		 2243 for (note = new_other_notes; note; note = XEXP (note, 1))
2244 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2245 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 2246
230d793d 2247 distribute_notes (new_other_notes, undobuf.other_insn,
5f4f0e22 2248 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
230d793d
RS		 2249 }
2250
2251 /* We now know that we can do this combination. Merge the insns and
2252 update the status of registers and LOG_LINKS. */
2253
2254 {
2255 rtx i3notes, i2notes, i1notes = 0;
2256 rtx i3links, i2links, i1links = 0;
2257 rtx midnotes = 0;
230d793d 2258 register int regno;
ff3467a9
JW		 2259 /* Compute which registers we expect to eliminate. newi2pat may be setting
2260 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2261 same as i3dest, in which case newi2pat may be setting i1dest. */
2262 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2263 || i2dest_in_i2src || i2dest_in_i1src
230d793d 2264 ? 0 : i2dest);
ff3467a9
JW		 2265 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2266 || (newi2pat && reg_set_p (i1dest, newi2pat))
2267 ? 0 : i1dest);
230d793d
RS		 2268
2269 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2270 clear them. */
2271 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2272 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2273 if (i1)
2274 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2275
2276 /* Ensure that we do not have something that should not be shared but
2277 occurs multiple times in the new insns. Check this by first
5089e22e 2278 resetting all the `used' flags and then copying anything is shared. */
230d793d
RS		 2279
2280 reset_used_flags (i3notes);
2281 reset_used_flags (i2notes);
2282 reset_used_flags (i1notes);
2283 reset_used_flags (newpat);
2284 reset_used_flags (newi2pat);
2285 if (undobuf.other_insn)
2286 reset_used_flags (PATTERN (undobuf.other_insn));
2287
2288 i3notes = copy_rtx_if_shared (i3notes);
2289 i2notes = copy_rtx_if_shared (i2notes);
2290 i1notes = copy_rtx_if_shared (i1notes);
2291 newpat = copy_rtx_if_shared (newpat);
2292 newi2pat = copy_rtx_if_shared (newi2pat);
2293 if (undobuf.other_insn)
2294 reset_used_flags (PATTERN (undobuf.other_insn));
2295
2296 INSN_CODE (i3) = insn_code_number;
2297 PATTERN (i3) = newpat;
2298 if (undobuf.other_insn)
2299 INSN_CODE (undobuf.other_insn) = other_code_number;
2300
2301 /* We had one special case above where I2 had more than one set and
2302 we replaced a destination of one of those sets with the destination
2303 of I3. In that case, we have to update LOG_LINKS of insns later
176c9e6b
JW		 2304 in this basic block. Note that this (expensive) case is rare.
2305
2306 Also, in this case, we must pretend that all REG_NOTEs for I2
2307 actually came from I3, so that REG_UNUSED notes from I2 will be
2308 properly handled. */
2309
2310 if (i3_subst_into_i2)
2311 {
2312 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2313 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2314 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2315 && ! find_reg_note (i2, REG_UNUSED,
2316 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2317 for (temp = NEXT_INSN (i2);
2318 temp && (this_basic_block == n_basic_blocks - 1
2319 || basic_block_head[this_basic_block] != temp);
2320 temp = NEXT_INSN (temp))
2321 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2322 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2323 if (XEXP (link, 0) == i2)
2324 XEXP (link, 0) = i3;
2325
2326 if (i3notes)
2327 {
2328 rtx link = i3notes;
2329 while (XEXP (link, 1))
2330 link = XEXP (link, 1);
2331 XEXP (link, 1) = i2notes;
2332 }
2333 else
2334 i3notes = i2notes;
2335 i2notes = 0;
2336 }
230d793d
RS		 2337
2338 LOG_LINKS (i3) = 0;
2339 REG_NOTES (i3) = 0;
2340 LOG_LINKS (i2) = 0;
2341 REG_NOTES (i2) = 0;
2342
2343 if (newi2pat)
2344 {
2345 INSN_CODE (i2) = i2_code_number;
2346 PATTERN (i2) = newi2pat;
2347 }
2348 else
2349 {
2350 PUT_CODE (i2, NOTE);
2351 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2352 NOTE_SOURCE_FILE (i2) = 0;
2353 }
2354
2355 if (i1)
2356 {
2357 LOG_LINKS (i1) = 0;
2358 REG_NOTES (i1) = 0;
2359 PUT_CODE (i1, NOTE);
2360 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2361 NOTE_SOURCE_FILE (i1) = 0;
2362 }
2363
2364 /* Get death notes for everything that is now used in either I3 or
6eb12cef
RK		 2365 I2 and used to die in a previous insn. If we built two new
2366 patterns, move from I1 to I2 then I2 to I3 so that we get the
2367 proper movement on registers that I2 modifies. */
230d793d 2368
230d793d 2369 if (newi2pat)
6eb12cef
RK		 2370 {
2371 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2372 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2373 }
2374 else
2375 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2376 i3, &midnotes);
230d793d
RS		 2377
2378 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2379 if (i3notes)
5f4f0e22
CH		 2380 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2381 elim_i2, elim_i1);
230d793d 2382 if (i2notes)
5f4f0e22
CH		 2383 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2384 elim_i2, elim_i1);
230d793d 2385 if (i1notes)
5f4f0e22
CH		 2386 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2387 elim_i2, elim_i1);
230d793d 2388 if (midnotes)
5f4f0e22
CH		 2389 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2390 elim_i2, elim_i1);
230d793d
RS		 2391
2392 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2393 know these are REG_UNUSED and want them to go to the desired insn,
1a26b032
RK		 2394 so we always pass it as i3. We have not counted the notes in
2395 reg_n_deaths yet, so we need to do so now. */
2396
230d793d 2397 if (newi2pat && new_i2_notes)
1a26b032
RK		 2398 {
2399 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2400 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2401 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2402
2403 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2404 }
2405
230d793d 2406 if (new_i3_notes)
1a26b032
RK		 2407 {
2408 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2409 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2410 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2411
2412 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2413 }
230d793d
RS		 2414
2415 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
e9a25f70
JL		 2416 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2417 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2418 in that case, it might delete I2. Similarly for I2 and I1.
1a26b032
RK		 2419 Show an additional death due to the REG_DEAD note we make here. If
2420 we discard it in distribute_notes, we will decrement it again. */
d0ab8cd3 2421
230d793d 2422 if (i3dest_killed)
1a26b032
RK		 2423 {
2424 if (GET_CODE (i3dest_killed) == REG)
b1f21e0a 2425 REG_N_DEATHS (REGNO (i3dest_killed))++;
1a26b032 2426
e9a25f70 2427 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
38a448ca
RH		 2428 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2429 NULL_RTX),
ff3467a9 2430 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
e9a25f70 2431 else
38a448ca
RH		 2432 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2433 NULL_RTX),
e9a25f70 2434 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
ff3467a9 2435 elim_i2, elim_i1);
1a26b032 2436 }
58c8c593 2437
230d793d 2438 if (i2dest_in_i2src)
58c8c593 2439 {
1a26b032 2440 if (GET_CODE (i2dest) == REG)
b1f21e0a 2441 REG_N_DEATHS (REGNO (i2dest))++;
1a26b032 2442
58c8c593 2443 if (newi2pat && reg_set_p (i2dest, newi2pat))
38a448ca 2444 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2445 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2446 else
38a448ca 2447 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2448 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2449 NULL_RTX, NULL_RTX);
2450 }
2451
230d793d 2452 if (i1dest_in_i1src)
58c8c593 2453 {
1a26b032 2454 if (GET_CODE (i1dest) == REG)
b1f21e0a 2455 REG_N_DEATHS (REGNO (i1dest))++;
1a26b032 2456
58c8c593 2457 if (newi2pat && reg_set_p (i1dest, newi2pat))
38a448ca 2458 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2459 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2460 else
38a448ca 2461 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2462 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2463 NULL_RTX, NULL_RTX);
2464 }
230d793d
RS		 2465
2466 distribute_links (i3links);
2467 distribute_links (i2links);
2468 distribute_links (i1links);
2469
2470 if (GET_CODE (i2dest) == REG)
2471 {
d0ab8cd3
RK		 2472 rtx link;
2473 rtx i2_insn = 0, i2_val = 0, set;
2474
2475 /* The insn that used to set this register doesn't exist, and
2476 this life of the register may not exist either. See if one of
2477 I3's links points to an insn that sets I2DEST. If it does,
2478 that is now the last known value for I2DEST. If we don't update
2479 this and I2 set the register to a value that depended on its old
230d793d
RS		 2480 contents, we will get confused. If this insn is used, thing
2481 will be set correctly in combine_instructions. */
d0ab8cd3
RK		 2482
2483 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2484 if ((set = single_set (XEXP (link, 0))) != 0
2485 && rtx_equal_p (i2dest, SET_DEST (set)))
2486 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2487
2488 record_value_for_reg (i2dest, i2_insn, i2_val);
230d793d
RS		 2489
2490 /* If the reg formerly set in I2 died only once and that was in I3,
2491 zero its use count so it won't make `reload' do any work. */
538fe8cd
ILT		 2492 if (! added_sets_2
2493 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2494 && ! i2dest_in_i2src)
230d793d
RS		 2495 {
2496 regno = REGNO (i2dest);
b1f21e0a
MM		 2497 REG_N_SETS (regno)--;
2498 if (REG_N_SETS (regno) == 0
8e08106d 2499 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2500 REG_N_REFS (regno) = 0;
230d793d
RS		 2501 }
2502 }
2503
2504 if (i1 && GET_CODE (i1dest) == REG)
2505 {
d0ab8cd3
RK		 2506 rtx link;
2507 rtx i1_insn = 0, i1_val = 0, set;
2508
2509 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2510 if ((set = single_set (XEXP (link, 0))) != 0
2511 && rtx_equal_p (i1dest, SET_DEST (set)))
2512 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2513
2514 record_value_for_reg (i1dest, i1_insn, i1_val);
2515
230d793d 2516 regno = REGNO (i1dest);
5af91171 2517 if (! added_sets_1 && ! i1dest_in_i1src)
230d793d 2518 {
b1f21e0a
MM		 2519 REG_N_SETS (regno)--;
2520 if (REG_N_SETS (regno) == 0
8e08106d 2521 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2522 REG_N_REFS (regno) = 0;
230d793d
RS		 2523 }
2524 }
2525
951553af 2526 /* Update reg_nonzero_bits et al for any changes that may have been made
22609cbf
RK		 2527 to this insn. */
2528
951553af 2529 note_stores (newpat, set_nonzero_bits_and_sign_copies);
22609cbf 2530 if (newi2pat)
951553af 2531 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
22609cbf 2532
a29ca9db
RK		 2533 /* If we added any (clobber (scratch)), add them to the max for a
2534 block. This is a very pessimistic calculation, since we might
2535 have had them already and this might not be the worst block, but
2536 it's not worth doing any better. */
2537 max_scratch += i3_scratches + i2_scratches + other_scratches;
2538
230d793d
RS		 2539 /* If I3 is now an unconditional jump, ensure that it has a
2540 BARRIER following it since it may have initially been a
381ee8af 2541 conditional jump. It may also be the last nonnote insn. */
230d793d
RS		 2542
2543 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
381ee8af
TW		 2544 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2545 || GET_CODE (temp) != BARRIER))
230d793d
RS		 2546 emit_barrier_after (i3);
2547 }
2548
2549 combine_successes++;
2550
bcd49eb7
JW		 2551 /* Clear this here, so that subsequent get_last_value calls are not
2552 affected. */
2553 subst_prev_insn = NULL_RTX;
2554
abe6e52f
RK		 2555 if (added_links_insn
2556 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2557 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2558 return added_links_insn;
2559 else
2560 return newi2pat ? i2 : i3;
230d793d
RS		 2561}
2562\f
2563/* Undo all the modifications recorded in undobuf. */
2564
2565static void
2566undo_all ()
2567{
241cea85
RK		 2568 struct undo *undo, *next;
2569
2570 for (undo = undobuf.undos; undo; undo = next)
7c046e4e 2571 {
241cea85
RK		 2572 next = undo->next;
2573 if (undo->is_int)
2574 *undo->where.i = undo->old_contents.i;
7c046e4e 2575 else
241cea85
RK		 2576 *undo->where.r = undo->old_contents.r;
2577
2578 undo->next = undobuf.frees;
2579 undobuf.frees = undo;
7c046e4e 2580 }
230d793d
RS		 2581
2582 obfree (undobuf.storage);
845fc875 2583 undobuf.undos = undobuf.previous_undos = 0;
bcd49eb7
JW		 2584
2585 /* Clear this here, so that subsequent get_last_value calls are not
2586 affected. */
2587 subst_prev_insn = NULL_RTX;
230d793d
RS		 2588}
2589\f
2590/* Find the innermost point within the rtx at LOC, possibly LOC itself,
d0ab8cd3
RK		 2591 where we have an arithmetic expression and return that point. LOC will
2592 be inside INSN.
230d793d
RS		 2593
2594 try_combine will call this function to see if an insn can be split into
2595 two insns. */
2596
2597static rtx *
d0ab8cd3 2598find_split_point (loc, insn)
230d793d 2599 rtx *loc;
d0ab8cd3 2600 rtx insn;
230d793d
RS		 2601{
2602 rtx x = *loc;
2603 enum rtx_code code = GET_CODE (x);
2604 rtx *split;
2605 int len = 0, pos, unsignedp;
2606 rtx inner;
2607
2608 /* First special-case some codes. */
2609 switch (code)
2610 {
2611 case SUBREG:
2612#ifdef INSN_SCHEDULING
2613 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2614 point. */
2615 if (GET_CODE (SUBREG_REG (x)) == MEM)
2616 return loc;
2617#endif
d0ab8cd3 2618 return find_split_point (&SUBREG_REG (x), insn);
230d793d 2619
230d793d 2620 case MEM:
916f14f1 2621#ifdef HAVE_lo_sum
230d793d
RS		 2622 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2623 using LO_SUM and HIGH. */
2624 if (GET_CODE (XEXP (x, 0)) == CONST
2625 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2626 {
2627 SUBST (XEXP (x, 0),
2628 gen_rtx_combine (LO_SUM, Pmode,
2629 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2630 XEXP (x, 0)));
2631 return &XEXP (XEXP (x, 0), 0);
2632 }
230d793d
RS		 2633#endif
2634
916f14f1
RK		 2635 /* If we have a PLUS whose second operand is a constant and the
2636 address is not valid, perhaps will can split it up using
2637 the machine-specific way to split large constants. We use
ddd5a7c1 2638 the first pseudo-reg (one of the virtual regs) as a placeholder;
916f14f1
RK		 2639 it will not remain in the result. */
2640 if (GET_CODE (XEXP (x, 0)) == PLUS
2641 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2642 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2643 {
2644 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
38a448ca 2645 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
916f14f1
RK		 2646 subst_insn);
2647
2648 /* This should have produced two insns, each of which sets our
2649 placeholder. If the source of the second is a valid address,
2650 we can make put both sources together and make a split point
2651 in the middle. */
2652
2653 if (seq && XVECLEN (seq, 0) == 2
2654 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2655 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2656 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2657 && ! reg_mentioned_p (reg,
2658 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2659 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2660 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2661 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2662 && memory_address_p (GET_MODE (x),
2663 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2664 {
2665 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2666 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2667
2668 /* Replace the placeholder in SRC2 with SRC1. If we can
2669 find where in SRC2 it was placed, that can become our
2670 split point and we can replace this address with SRC2.
2671 Just try two obvious places. */
2672
2673 src2 = replace_rtx (src2, reg, src1);
2674 split = 0;
2675 if (XEXP (src2, 0) == src1)
2676 split = &XEXP (src2, 0);
2677 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2678 && XEXP (XEXP (src2, 0), 0) == src1)
2679 split = &XEXP (XEXP (src2, 0), 0);
2680
2681 if (split)
2682 {
2683 SUBST (XEXP (x, 0), src2);
2684 return split;
2685 }
2686 }
1a26b032
RK		 2687
2688 /* If that didn't work, perhaps the first operand is complex and
2689 needs to be computed separately, so make a split point there.
2690 This will occur on machines that just support REG + CONST
2691 and have a constant moved through some previous computation. */
2692
2693 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2694 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2695 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2696 == 'o')))
2697 return &XEXP (XEXP (x, 0), 0);
916f14f1
RK		 2698 }
2699 break;
2700
230d793d
RS		 2701 case SET:
2702#ifdef HAVE_cc0
2703 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2704 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2705 we need to put the operand into a register. So split at that
2706 point. */
2707
2708 if (SET_DEST (x) == cc0_rtx
2709 && GET_CODE (SET_SRC (x)) != COMPARE
2710 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2711 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2712 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2713 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2714 return &SET_SRC (x);
2715#endif
2716
2717 /* See if we can split SET_SRC as it stands. */
d0ab8cd3 2718 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2719 if (split && split != &SET_SRC (x))
2720 return split;
2721
041d7180
JL		 2722 /* See if we can split SET_DEST as it stands. */
2723 split = find_split_point (&SET_DEST (x), insn);
2724 if (split && split != &SET_DEST (x))
2725 return split;
2726
230d793d
RS		 2727 /* See if this is a bitfield assignment with everything constant. If
2728 so, this is an IOR of an AND, so split it into that. */
2729 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2730 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
5f4f0e22 2731 <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 2732 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2733 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2734 && GET_CODE (SET_SRC (x)) == CONST_INT
2735 && ((INTVAL (XEXP (SET_DEST (x), 1))
2736 + INTVAL (XEXP (SET_DEST (x), 2)))
2737 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2738 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2739 {
2740 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2741 int len = INTVAL (XEXP (SET_DEST (x), 1));
2742 int src = INTVAL (SET_SRC (x));
2743 rtx dest = XEXP (SET_DEST (x), 0);
2744 enum machine_mode mode = GET_MODE (dest);
5f4f0e22 2745 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
230d793d 2746
f76b9db2
ILT		 2747 if (BITS_BIG_ENDIAN)
2748 pos = GET_MODE_BITSIZE (mode) - len - pos;
230d793d
RS		 2749
2750 if (src == mask)
2751 SUBST (SET_SRC (x),
5f4f0e22 2752 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
230d793d
RS		 2753 else
2754 SUBST (SET_SRC (x),
2755 gen_binary (IOR, mode,
2756 gen_binary (AND, mode, dest,
5f4f0e22
CH		 2757 GEN_INT (~ (mask << pos)
2758 & GET_MODE_MASK (mode))),
2759 GEN_INT (src << pos)));
230d793d
RS		 2760
2761 SUBST (SET_DEST (x), dest);
2762
d0ab8cd3 2763 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2764 if (split && split != &SET_SRC (x))
2765 return split;
2766 }
2767
2768 /* Otherwise, see if this is an operation that we can split into two.
2769 If so, try to split that. */
2770 code = GET_CODE (SET_SRC (x));
2771
2772 switch (code)
2773 {
d0ab8cd3
RK		 2774 case AND:
2775 /* If we are AND'ing with a large constant that is only a single
2776 bit and the result is only being used in a context where we
2777 need to know if it is zero or non-zero, replace it with a bit
2778 extraction. This will avoid the large constant, which might
2779 have taken more than one insn to make. If the constant were
2780 not a valid argument to the AND but took only one insn to make,
2781 this is no worse, but if it took more than one insn, it will
2782 be better. */
2783
2784 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2785 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2786 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2787 && GET_CODE (SET_DEST (x)) == REG
2788 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2789 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2790 && XEXP (*split, 0) == SET_DEST (x)
2791 && XEXP (*split, 1) == const0_rtx)
2792 {
76184def
DE		 2793 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2794 XEXP (SET_SRC (x), 0),
2795 pos, NULL_RTX, 1, 1, 0, 0);
2796 if (extraction != 0)
2797 {
2798 SUBST (SET_SRC (x), extraction);
2799 return find_split_point (loc, insn);
2800 }
d0ab8cd3
RK		 2801 }
2802 break;
2803
1a6ec070
RK		 2804 case NE:
2805 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2806 is known to be on, this can be converted into a NEG of a shift. */
2807 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2808 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4eb2cb10 2809 && 1 <= (pos = exact_log2
1a6ec070
RK		 2810 (nonzero_bits (XEXP (SET_SRC (x), 0),
2811 GET_MODE (XEXP (SET_SRC (x), 0))))))
2812 {
2813 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2814
2815 SUBST (SET_SRC (x),
2816 gen_rtx_combine (NEG, mode,
2817 gen_rtx_combine (LSHIFTRT, mode,
2818 XEXP (SET_SRC (x), 0),
4eb2cb10 2819 GEN_INT (pos))));
1a6ec070
RK		 2820
2821 split = find_split_point (&SET_SRC (x), insn);
2822 if (split && split != &SET_SRC (x))
2823 return split;
2824 }
2825 break;
2826
230d793d
RS		 2827 case SIGN_EXTEND:
2828 inner = XEXP (SET_SRC (x), 0);
101c1a3d
JL		 2829
2830 /* We can't optimize if either mode is a partial integer
2831 mode as we don't know how many bits are significant
2832 in those modes. */
2833 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2834 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2835 break;
2836
230d793d
RS		 2837 pos = 0;
2838 len = GET_MODE_BITSIZE (GET_MODE (inner));
2839 unsignedp = 0;
2840 break;
2841
2842 case SIGN_EXTRACT:
2843 case ZERO_EXTRACT:
2844 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2845 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2846 {
2847 inner = XEXP (SET_SRC (x), 0);
2848 len = INTVAL (XEXP (SET_SRC (x), 1));
2849 pos = INTVAL (XEXP (SET_SRC (x), 2));
2850
f76b9db2
ILT		 2851 if (BITS_BIG_ENDIAN)
2852 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
230d793d
RS		 2853 unsignedp = (code == ZERO_EXTRACT);
2854 }
2855 break;
e9a25f70
JL		 2856
2857 default:
2858 break;
230d793d
RS		 2859 }
2860
2861 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2862 {
2863 enum machine_mode mode = GET_MODE (SET_SRC (x));
2864
d0ab8cd3
RK		 2865 /* For unsigned, we have a choice of a shift followed by an
2866 AND or two shifts. Use two shifts for field sizes where the
2867 constant might be too large. We assume here that we can
2868 always at least get 8-bit constants in an AND insn, which is
2869 true for every current RISC. */
2870
2871 if (unsignedp && len <= 8)
230d793d
RS		 2872 {
2873 SUBST (SET_SRC (x),
2874 gen_rtx_combine
2875 (AND, mode,
2876 gen_rtx_combine (LSHIFTRT, mode,
2877 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2878 GEN_INT (pos)),
2879 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
230d793d 2880
d0ab8cd3 2881 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2882 if (split && split != &SET_SRC (x))
2883 return split;
2884 }
2885 else
2886 {
2887 SUBST (SET_SRC (x),
2888 gen_rtx_combine
d0ab8cd3 2889 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
230d793d
RS		 2890 gen_rtx_combine (ASHIFT, mode,
2891 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2892 GEN_INT (GET_MODE_BITSIZE (mode)
2893 - len - pos)),
2894 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
230d793d 2895
d0ab8cd3 2896 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2897 if (split && split != &SET_SRC (x))
2898 return split;
2899 }
2900 }
2901
2902 /* See if this is a simple operation with a constant as the second
2903 operand. It might be that this constant is out of range and hence
2904 could be used as a split point. */
2905 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2906 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2907 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2908 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2909 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2910 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2911 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2912 == 'o'))))
2913 return &XEXP (SET_SRC (x), 1);
2914
2915 /* Finally, see if this is a simple operation with its first operand
2916 not in a register. The operation might require this operand in a
2917 register, so return it as a split point. We can always do this
2918 because if the first operand were another operation, we would have
2919 already found it as a split point. */
2920 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2921 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2922 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2923 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2924 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2925 return &XEXP (SET_SRC (x), 0);
2926
2927 return 0;
2928
2929 case AND:
2930 case IOR:
2931 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2932 it is better to write this as (not (ior A B)) so we can split it.
2933 Similarly for IOR. */
2934 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2935 {
2936 SUBST (*loc,
2937 gen_rtx_combine (NOT, GET_MODE (x),
2938 gen_rtx_combine (code == IOR ? AND : IOR,
2939 GET_MODE (x),
2940 XEXP (XEXP (x, 0), 0),
2941 XEXP (XEXP (x, 1), 0))));
d0ab8cd3 2942 return find_split_point (loc, insn);
230d793d
RS		 2943 }
2944
2945 /* Many RISC machines have a large set of logical insns. If the
2946 second operand is a NOT, put it first so we will try to split the
2947 other operand first. */
2948 if (GET_CODE (XEXP (x, 1)) == NOT)
2949 {
2950 rtx tem = XEXP (x, 0);
2951 SUBST (XEXP (x, 0), XEXP (x, 1));
2952 SUBST (XEXP (x, 1), tem);
2953 }
2954 break;
e9a25f70
JL		 2955
2956 default:
2957 break;
230d793d
RS		 2958 }
2959
2960 /* Otherwise, select our actions depending on our rtx class. */
2961 switch (GET_RTX_CLASS (code))
2962 {
2963 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2964 case '3':
d0ab8cd3 2965 split = find_split_point (&XEXP (x, 2), insn);
230d793d
RS		 2966 if (split)
2967 return split;
0f41302f 2968 /* ... fall through ... */
230d793d
RS		 2969 case '2':
2970 case 'c':
2971 case '<':
d0ab8cd3 2972 split = find_split_point (&XEXP (x, 1), insn);
230d793d
RS		 2973 if (split)
2974 return split;
0f41302f 2975 /* ... fall through ... */
230d793d
RS		 2976 case '1':
2977 /* Some machines have (and (shift ...) ...) insns. If X is not
2978 an AND, but XEXP (X, 0) is, use it as our split point. */
2979 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2980 return &XEXP (x, 0);
2981
d0ab8cd3 2982 split = find_split_point (&XEXP (x, 0), insn);
230d793d
RS		 2983 if (split)
2984 return split;
2985 return loc;
2986 }
2987
2988 /* Otherwise, we don't have a split point. */
2989 return 0;
2990}
2991\f
2992/* Throughout X, replace FROM with TO, and return the result.
2993 The result is TO if X is FROM;
2994 otherwise the result is X, but its contents may have been modified.
2995 If they were modified, a record was made in undobuf so that
2996 undo_all will (among other things) return X to its original state.
2997
2998 If the number of changes necessary is too much to record to undo,
2999 the excess changes are not made, so the result is invalid.
3000 The changes already made can still be undone.
3001 undobuf.num_undo is incremented for such changes, so by testing that
3002 the caller can tell whether the result is valid.
3003
3004 `n_occurrences' is incremented each time FROM is replaced.
3005
3006 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3007
5089e22e 3008 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
230d793d
RS		 3009 by copying if `n_occurrences' is non-zero. */
3010
3011static rtx
3012subst (x, from, to, in_dest, unique_copy)
3013 register rtx x, from, to;
3014 int in_dest;
3015 int unique_copy;
3016{
f24ad0e4 3017 register enum rtx_code code = GET_CODE (x);
230d793d 3018 enum machine_mode op0_mode = VOIDmode;
8079805d
RK		 3019 register char *fmt;
3020 register int len, i;
3021 rtx new;
230d793d
RS		 3022
3023/* Two expressions are equal if they are identical copies of a shared
3024 RTX or if they are both registers with the same register number
3025 and mode. */
3026
3027#define COMBINE_RTX_EQUAL_P(X,Y) \
3028 ((X) == (Y) \
3029 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3030 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3031
3032 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3033 {
3034 n_occurrences++;
3035 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3036 }
3037
3038 /* If X and FROM are the same register but different modes, they will
3039 not have been seen as equal above. However, flow.c will make a
3040 LOG_LINKS entry for that case. If we do nothing, we will try to
3041 rerecognize our original insn and, when it succeeds, we will
3042 delete the feeding insn, which is incorrect.
3043
3044 So force this insn not to match in this (rare) case. */
3045 if (! in_dest && code == REG && GET_CODE (from) == REG
3046 && REGNO (x) == REGNO (from))
38a448ca 3047 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 3048
3049 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3050 of which may contain things that can be combined. */
3051 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3052 return x;
3053
3054 /* It is possible to have a subexpression appear twice in the insn.
3055 Suppose that FROM is a register that appears within TO.
3056 Then, after that subexpression has been scanned once by `subst',
3057 the second time it is scanned, TO may be found. If we were
3058 to scan TO here, we would find FROM within it and create a
3059 self-referent rtl structure which is completely wrong. */
3060 if (COMBINE_RTX_EQUAL_P (x, to))
3061 return to;
3062
3063 len = GET_RTX_LENGTH (code);
3064 fmt = GET_RTX_FORMAT (code);
3065
3066 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
3067 set up to skip this common case. All other cases where we want to
3068 suppress replacing something inside a SET_SRC are handled via the
3069 IN_DEST operand. */
3070 if (code == SET
3071 && (GET_CODE (SET_DEST (x)) == REG
3072 || GET_CODE (SET_DEST (x)) == CC0
3073 || GET_CODE (SET_DEST (x)) == PC))
3074 fmt = "ie";
3075
0f41302f
MS		 3076 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3077 constant. */
230d793d
RS		 3078 if (fmt[0] == 'e')
3079 op0_mode = GET_MODE (XEXP (x, 0));
3080
3081 for (i = 0; i < len; i++)
3082 {
3083 if (fmt[i] == 'E')
3084 {
3085 register int j;
3086 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3087 {
230d793d
RS		 3088 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3089 {
3090 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3091 n_occurrences++;
3092 }
3093 else
3094 {
3095 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3096
3097 /* If this substitution failed, this whole thing fails. */
3098 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3099 return new;
3100 }
3101
3102 SUBST (XVECEXP (x, i, j), new);
3103 }
3104 }
3105 else if (fmt[i] == 'e')
3106 {
230d793d
RS		 3107 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3108 {
42301240
RK		 3109 /* In general, don't install a subreg involving two modes not
3110 tieable. It can worsen register allocation, and can even
3111 make invalid reload insns, since the reg inside may need to
3112 be copied from in the outside mode, and that may be invalid
3113 if it is an fp reg copied in integer mode.
3114
3115 We allow two exceptions to this: It is valid if it is inside
3116 another SUBREG and the mode of that SUBREG and the mode of
3117 the inside of TO is tieable and it is valid if X is a SET
3118 that copies FROM to CC0. */
3119 if (GET_CODE (to) == SUBREG
3120 && ! MODES_TIEABLE_P (GET_MODE (to),
3121 GET_MODE (SUBREG_REG (to)))
3122 && ! (code == SUBREG
8079805d
RK		 3123 && MODES_TIEABLE_P (GET_MODE (x),
3124 GET_MODE (SUBREG_REG (to))))
42301240
RK		 3125#ifdef HAVE_cc0
3126 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3127#endif
3128 )
38a448ca 3129 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
42301240 3130
230d793d
RS		 3131 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3132 n_occurrences++;
3133 }
3134 else
3135 /* If we are in a SET_DEST, suppress most cases unless we
3136 have gone inside a MEM, in which case we want to
3137 simplify the address. We assume here that things that
3138 are actually part of the destination have their inner
3139 parts in the first expression. This is true for SUBREG,
3140 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3141 things aside from REG and MEM that should appear in a
3142 SET_DEST. */
3143 new = subst (XEXP (x, i), from, to,
3144 (((in_dest
3145 && (code == SUBREG || code == STRICT_LOW_PART
3146 || code == ZERO_EXTRACT))
3147 || code == SET)
3148 && i == 0), unique_copy);
3149
3150 /* If we found that we will have to reject this combination,
3151 indicate that by returning the CLOBBER ourselves, rather than
3152 an expression containing it. This will speed things up as
3153 well as prevent accidents where two CLOBBERs are considered
3154 to be equal, thus producing an incorrect simplification. */
3155
3156 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3157 return new;
3158
3159 SUBST (XEXP (x, i), new);
3160 }
3161 }
3162
8079805d
RK		 3163 /* Try to simplify X. If the simplification changed the code, it is likely
3164 that further simplification will help, so loop, but limit the number
3165 of repetitions that will be performed. */
3166
3167 for (i = 0; i < 4; i++)
3168 {
3169 /* If X is sufficiently simple, don't bother trying to do anything
3170 with it. */
3171 if (code != CONST_INT && code != REG && code != CLOBBER)
3172 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
d0ab8cd3 3173
8079805d
RK		 3174 if (GET_CODE (x) == code)
3175 break;
d0ab8cd3 3176
8079805d 3177 code = GET_CODE (x);
eeb43d32 3178
8079805d
RK		 3179 /* We no longer know the original mode of operand 0 since we
3180 have changed the form of X) */
3181 op0_mode = VOIDmode;
3182 }
eeb43d32 3183
8079805d
RK		 3184 return x;
3185}
3186\f
3187/* Simplify X, a piece of RTL. We just operate on the expression at the
3188 outer level; call `subst' to simplify recursively. Return the new
3189 expression.
3190
3191 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3192 will be the iteration even if an expression with a code different from
3193 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
eeb43d32 3194
8079805d
RK		 3195static rtx
3196simplify_rtx (x, op0_mode, last, in_dest)
3197 rtx x;
3198 enum machine_mode op0_mode;
3199 int last;
3200 int in_dest;
3201{
3202 enum rtx_code code = GET_CODE (x);
3203 enum machine_mode mode = GET_MODE (x);
3204 rtx temp;
3205 int i;
d0ab8cd3 3206
230d793d
RS		 3207 /* If this is a commutative operation, put a constant last and a complex
3208 expression first. We don't need to do this for comparisons here. */
3209 if (GET_RTX_CLASS (code) == 'c'
3210 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3211 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3212 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3213 || (GET_CODE (XEXP (x, 0)) == SUBREG
3214 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3215 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3216 {
3217 temp = XEXP (x, 0);
3218 SUBST (XEXP (x, 0), XEXP (x, 1));
3219 SUBST (XEXP (x, 1), temp);
3220 }
3221
22609cbf
RK		 3222 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3223 sign extension of a PLUS with a constant, reverse the order of the sign
3224 extension and the addition. Note that this not the same as the original
3225 code, but overflow is undefined for signed values. Also note that the
3226 PLUS will have been partially moved "inside" the sign-extension, so that
3227 the first operand of X will really look like:
3228 (ashiftrt (plus (ashift A C4) C5) C4).
3229 We convert this to
3230 (plus (ashiftrt (ashift A C4) C2) C4)
3231 and replace the first operand of X with that expression. Later parts
3232 of this function may simplify the expression further.
3233
3234 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3235 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3236 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3237
3238 We do this to simplify address expressions. */
3239
3240 if ((code == PLUS || code == MINUS || code == MULT)
3241 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3242 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3243 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3244 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3245 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3246 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3247 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3248 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3249 XEXP (XEXP (XEXP (x, 0), 0), 1),
3250 XEXP (XEXP (x, 0), 1))) != 0)
3251 {
3252 rtx new
3253 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3254 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3255 INTVAL (XEXP (XEXP (x, 0), 1)));
3256
3257 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3258 INTVAL (XEXP (XEXP (x, 0), 1)));
3259
3260 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3261 }
3262
d0ab8cd3
RK		 3263 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3264 applying it to the arms of the IF_THEN_ELSE. This often simplifies
abe6e52f
RK		 3265 things. Check for cases where both arms are testing the same
3266 condition.
3267
3268 Don't do anything if all operands are very simple. */
3269
3270 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3271 || GET_RTX_CLASS (code) == '<')
3272 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3273 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3274 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3275 == 'o')))
3276 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3277 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3278 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3279 == 'o')))))
3280 || (GET_RTX_CLASS (code) == '1'
3281 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3282 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3283 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3284 == 'o'))))))
d0ab8cd3 3285 {
abe6e52f
RK		 3286 rtx cond, true, false;
3287
3288 cond = if_then_else_cond (x, &true, &false);
0802d516
RK		 3289 if (cond != 0
3290 /* If everything is a comparison, what we have is highly unlikely
3291 to be simpler, so don't use it. */
3292 && ! (GET_RTX_CLASS (code) == '<'
3293 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3294 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
abe6e52f
RK		 3295 {
3296 rtx cop1 = const0_rtx;
3297 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3298
15448afc
RK		 3299 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3300 return x;
3301
9210df58
RK		 3302 /* Simplify the alternative arms; this may collapse the true and
3303 false arms to store-flag values. */
3304 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3305 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3306
3307 /* Restarting if we generate a store-flag expression will cause
3308 us to loop. Just drop through in this case. */
3309
abe6e52f
RK		 3310 /* If the result values are STORE_FLAG_VALUE and zero, we can
3311 just make the comparison operation. */
3312 if (true == const_true_rtx && false == const0_rtx)
3313 x = gen_binary (cond_code, mode, cond, cop1);
3314 else if (true == const0_rtx && false == const_true_rtx)
3315 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3316
3317 /* Likewise, we can make the negate of a comparison operation
3318 if the result values are - STORE_FLAG_VALUE and zero. */
3319 else if (GET_CODE (true) == CONST_INT
3320 && INTVAL (true) == - STORE_FLAG_VALUE
3321 && false == const0_rtx)
0c1c8ea6 3322 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3323 gen_binary (cond_code, mode, cond, cop1));
3324 else if (GET_CODE (false) == CONST_INT
3325 && INTVAL (false) == - STORE_FLAG_VALUE
3326 && true == const0_rtx)
0c1c8ea6 3327 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3328 gen_binary (reverse_condition (cond_code),
3329 mode, cond, cop1));
3330 else
38a448ca
RH		 3331 return gen_rtx_IF_THEN_ELSE (mode,
3332 gen_binary (cond_code, VOIDmode,
3333 cond, cop1),
3334 true, false);
5109d49f 3335
9210df58
RK		 3336 code = GET_CODE (x);
3337 op0_mode = VOIDmode;
abe6e52f 3338 }
d0ab8cd3
RK		 3339 }
3340
230d793d
RS		 3341 /* Try to fold this expression in case we have constants that weren't
3342 present before. */
3343 temp = 0;
3344 switch (GET_RTX_CLASS (code))
3345 {
3346 case '1':
3347 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3348 break;
3349 case '<':
3350 temp = simplify_relational_operation (code, op0_mode,
3351 XEXP (x, 0), XEXP (x, 1));
77fa0940
RK		 3352#ifdef FLOAT_STORE_FLAG_VALUE
3353 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3354 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3355 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3356#endif
230d793d
RS		 3357 break;
3358 case 'c':
3359 case '2':
3360 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3361 break;
3362 case 'b':
3363 case '3':
3364 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3365 XEXP (x, 1), XEXP (x, 2));
3366 break;
3367 }
3368
3369 if (temp)
d0ab8cd3 3370 x = temp, code = GET_CODE (temp);
230d793d 3371
230d793d 3372 /* First see if we can apply the inverse distributive law. */
224eeff2
RK		 3373 if (code == PLUS || code == MINUS
3374 || code == AND || code == IOR || code == XOR)
230d793d
RS		 3375 {
3376 x = apply_distributive_law (x);
3377 code = GET_CODE (x);
3378 }
3379
3380 /* If CODE is an associative operation not otherwise handled, see if we
3381 can associate some operands. This can win if they are constants or
3382 if they are logically related (i.e. (a & b) & a. */
3383 if ((code == PLUS || code == MINUS
3384 || code == MULT || code == AND || code == IOR || code == XOR
3385 || code == DIV || code == UDIV
3386 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3ad2180a 3387 && INTEGRAL_MODE_P (mode))
230d793d
RS		 3388 {
3389 if (GET_CODE (XEXP (x, 0)) == code)
3390 {
3391 rtx other = XEXP (XEXP (x, 0), 0);
3392 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3393 rtx inner_op1 = XEXP (x, 1);
3394 rtx inner;
3395
3396 /* Make sure we pass the constant operand if any as the second
3397 one if this is a commutative operation. */
3398 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3399 {
3400 rtx tem = inner_op0;
3401 inner_op0 = inner_op1;
3402 inner_op1 = tem;
3403 }
3404 inner = simplify_binary_operation (code == MINUS ? PLUS
3405 : code == DIV ? MULT
3406 : code == UDIV ? MULT
3407 : code,
3408 mode, inner_op0, inner_op1);
3409
3410 /* For commutative operations, try the other pair if that one
3411 didn't simplify. */
3412 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3413 {
3414 other = XEXP (XEXP (x, 0), 1);
3415 inner = simplify_binary_operation (code, mode,
3416 XEXP (XEXP (x, 0), 0),
3417 XEXP (x, 1));
3418 }
3419
3420 if (inner)
8079805d 3421 return gen_binary (code, mode, other, inner);
230d793d
RS		 3422 }
3423 }
3424
3425 /* A little bit of algebraic simplification here. */
3426 switch (code)
3427 {
3428 case MEM:
3429 /* Ensure that our address has any ASHIFTs converted to MULT in case
3430 address-recognizing predicates are called later. */
3431 temp = make_compound_operation (XEXP (x, 0), MEM);
3432 SUBST (XEXP (x, 0), temp);
3433 break;
3434
3435 case SUBREG:
3436 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3437 is paradoxical. If we can't do that safely, then it becomes
3438 something nonsensical so that this combination won't take place. */
3439
3440 if (GET_CODE (SUBREG_REG (x)) == MEM
3441 && (GET_MODE_SIZE (mode)
3442 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3443 {
3444 rtx inner = SUBREG_REG (x);
3445 int endian_offset = 0;
3446 /* Don't change the mode of the MEM
3447 if that would change the meaning of the address. */
3448 if (MEM_VOLATILE_P (SUBREG_REG (x))
3449 || mode_dependent_address_p (XEXP (inner, 0)))
38a448ca 3450 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d 3451
f76b9db2
ILT		 3452 if (BYTES_BIG_ENDIAN)
3453 {
3454 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3455 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3456 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3457 endian_offset -= (UNITS_PER_WORD
3458 - GET_MODE_SIZE (GET_MODE (inner)));
3459 }
230d793d
RS		 3460 /* Note if the plus_constant doesn't make a valid address
3461 then this combination won't be accepted. */
38a448ca
RH		 3462 x = gen_rtx_MEM (mode,
3463 plus_constant (XEXP (inner, 0),
3464 (SUBREG_WORD (x) * UNITS_PER_WORD
3465 + endian_offset)));
230d793d
RS		 3466 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3467 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3468 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3469 return x;
3470 }
3471
3472 /* If we are in a SET_DEST, these other cases can't apply. */
3473 if (in_dest)
3474 return x;
3475
3476 /* Changing mode twice with SUBREG => just change it once,
3477 or not at all if changing back to starting mode. */
3478 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3479 {
3480 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3481 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3482 return SUBREG_REG (SUBREG_REG (x));
3483
3484 SUBST_INT (SUBREG_WORD (x),
3485 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3486 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3487 }
3488
3489 /* SUBREG of a hard register => just change the register number
3490 and/or mode. If the hard register is not valid in that mode,
26ecfc76
RK		 3491 suppress this combination. If the hard register is the stack,
3492 frame, or argument pointer, leave this as a SUBREG. */
230d793d
RS		 3493
3494 if (GET_CODE (SUBREG_REG (x)) == REG
26ecfc76
RK		 3495 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3496 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
6d7096b0
DE		 3497#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3498 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3499#endif
26ecfc76
RK		 3500#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3501 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3502#endif
3503 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
230d793d
RS		 3504 {
3505 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3506 mode))
38a448ca
RH		 3507 return gen_rtx_REG (mode,
3508 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
230d793d 3509 else
38a448ca 3510 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d
RS		 3511 }
3512
3513 /* For a constant, try to pick up the part we want. Handle a full
a4bde0b1
RK		 3514 word and low-order part. Only do this if we are narrowing
3515 the constant; if it is being widened, we have no idea what
3516 the extra bits will have been set to. */
230d793d
RS		 3517
3518 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3519 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3c99d5ff 3520 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
230d793d
RS		 3521 && GET_MODE_CLASS (mode) == MODE_INT)
3522 {
3523 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
5f4f0e22 3524 0, op0_mode);
230d793d
RS		 3525 if (temp)
3526 return temp;
3527 }
3528
19808e22
RS		 3529 /* If we want a subreg of a constant, at offset 0,
3530 take the low bits. On a little-endian machine, that's
3531 always valid. On a big-endian machine, it's valid
3c99d5ff 3532 only if the constant's mode fits in one word. Note that we
61b1bece 3533 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3c99d5ff
RK		 3534 if (CONSTANT_P (SUBREG_REG (x))
3535 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3536 || ! WORDS_BIG_ENDIAN)
3537 ? SUBREG_WORD (x) == 0
3538 : (SUBREG_WORD (x)
3539 == ((GET_MODE_SIZE (op0_mode)
3540 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3541 / UNITS_PER_WORD)))
f82da7d2 3542 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
f76b9db2
ILT		 3543 && (! WORDS_BIG_ENDIAN
3544 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
230d793d
RS		 3545 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3546
b65c1b5b
RK		 3547 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3548 since we are saying that the high bits don't matter. */
3549 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3550 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3551 return SUBREG_REG (x);
3552
87e3e0c1
RK		 3553 /* Note that we cannot do any narrowing for non-constants since
3554 we might have been counting on using the fact that some bits were
3555 zero. We now do this in the SET. */
3556
230d793d
RS		 3557 break;
3558
3559 case NOT:
3560 /* (not (plus X -1)) can become (neg X). */
3561 if (GET_CODE (XEXP (x, 0)) == PLUS
3562 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
8079805d 3563 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3564
3565 /* Similarly, (not (neg X)) is (plus X -1). */
3566 if (GET_CODE (XEXP (x, 0)) == NEG)
8079805d
RK		 3567 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3568 constm1_rtx);
230d793d 3569
d0ab8cd3
RK		 3570 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3571 if (GET_CODE (XEXP (x, 0)) == XOR
3572 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3573 && (temp = simplify_unary_operation (NOT, mode,
3574 XEXP (XEXP (x, 0), 1),
3575 mode)) != 0)
787745f5 3576 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
d0ab8cd3 3577
230d793d
RS		 3578 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3579 other than 1, but that is not valid. We could do a similar
3580 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3581 but this doesn't seem common enough to bother with. */
3582 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3583 && XEXP (XEXP (x, 0), 0) == const1_rtx)
38a448ca
RH		 3584 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3585 XEXP (XEXP (x, 0), 1));
230d793d
RS		 3586
3587 if (GET_CODE (XEXP (x, 0)) == SUBREG
3588 && subreg_lowpart_p (XEXP (x, 0))
3589 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3590 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3591 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3592 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3593 {
3594 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3595
38a448ca
RH		 3596 x = gen_rtx_ROTATE (inner_mode,
3597 gen_unary (NOT, inner_mode, inner_mode,
3598 const1_rtx),
3599 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
8079805d 3600 return gen_lowpart_for_combine (mode, x);
230d793d
RS		 3601 }
3602
0802d516
RK		 3603 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3604 reversing the comparison code if valid. */
3605 if (STORE_FLAG_VALUE == -1
3606 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
230d793d
RS		 3607 && reversible_comparison_p (XEXP (x, 0)))
3608 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3609 mode, XEXP (XEXP (x, 0), 0),
3610 XEXP (XEXP (x, 0), 1));
500c518b
RK		 3611
3612 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
0802d516
RK		 3613 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3614 perform the above simplification. */
500c518b 3615
0802d516
RK		 3616 if (STORE_FLAG_VALUE == -1
3617 && XEXP (x, 1) == const1_rtx
500c518b
RK		 3618 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3619 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3620 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3621 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
230d793d
RS		 3622
3623 /* Apply De Morgan's laws to reduce number of patterns for machines
3624 with negating logical insns (and-not, nand, etc.). If result has
3625 only one NOT, put it first, since that is how the patterns are
3626 coded. */
3627
3628 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3629 {
3630 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3631
3632 if (GET_CODE (in1) == NOT)
3633 in1 = XEXP (in1, 0);
3634 else
3635 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3636
3637 if (GET_CODE (in2) == NOT)
3638 in2 = XEXP (in2, 0);
3639 else if (GET_CODE (in2) == CONST_INT
5f4f0e22
CH		 3640 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3641 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
230d793d
RS		 3642 else
3643 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3644
3645 if (GET_CODE (in2) == NOT)
3646 {
3647 rtx tem = in2;
3648 in2 = in1; in1 = tem;
3649 }
3650
8079805d
RK		 3651 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3652 mode, in1, in2);
230d793d
RS		 3653 }
3654 break;
3655
3656 case NEG:
3657 /* (neg (plus X 1)) can become (not X). */
3658 if (GET_CODE (XEXP (x, 0)) == PLUS
3659 && XEXP (XEXP (x, 0), 1) == const1_rtx)
8079805d 3660 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3661
3662 /* Similarly, (neg (not X)) is (plus X 1). */
3663 if (GET_CODE (XEXP (x, 0)) == NOT)
8079805d 3664 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
230d793d 3665
230d793d
RS		 3666 /* (neg (minus X Y)) can become (minus Y X). */
3667 if (GET_CODE (XEXP (x, 0)) == MINUS
3ad2180a 3668 && (! FLOAT_MODE_P (mode)
0f41302f 3669 /* x-y != -(y-x) with IEEE floating point. */
7e2a0d8e
RK		 3670 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3671 || flag_fast_math))
8079805d
RK		 3672 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3673 XEXP (XEXP (x, 0), 0));
230d793d 3674
0f41302f 3675 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
d0ab8cd3 3676 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
951553af 3677 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
8079805d 3678 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
d0ab8cd3 3679
230d793d
RS		 3680 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3681 if we can then eliminate the NEG (e.g.,
3682 if the operand is a constant). */
3683
3684 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3685 {
3686 temp = simplify_unary_operation (NEG, mode,
3687 XEXP (XEXP (x, 0), 0), mode);
3688 if (temp)
3689 {
3690 SUBST (XEXP (XEXP (x, 0), 0), temp);
3691 return XEXP (x, 0);
3692 }
3693 }
3694
3695 temp = expand_compound_operation (XEXP (x, 0));
3696
3697 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3698 replaced by (lshiftrt X C). This will convert
3699 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3700
3701 if (GET_CODE (temp) == ASHIFTRT
3702 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3703 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
8079805d
RK		 3704 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3705 INTVAL (XEXP (temp, 1)));
230d793d 3706
951553af 3707 /* If X has only a single bit that might be nonzero, say, bit I, convert
230d793d
RS		 3708 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3709 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3710 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3711 or a SUBREG of one since we'd be making the expression more
3712 complex if it was just a register. */
3713
3714 if (GET_CODE (temp) != REG
3715 && ! (GET_CODE (temp) == SUBREG
3716 && GET_CODE (SUBREG_REG (temp)) == REG)
951553af 3717 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
230d793d
RS		 3718 {
3719 rtx temp1 = simplify_shift_const
5f4f0e22
CH		 3720 (NULL_RTX, ASHIFTRT, mode,
3721 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
230d793d
RS		 3722 GET_MODE_BITSIZE (mode) - 1 - i),
3723 GET_MODE_BITSIZE (mode) - 1 - i);
3724
3725 /* If all we did was surround TEMP with the two shifts, we
3726 haven't improved anything, so don't use it. Otherwise,
3727 we are better off with TEMP1. */
3728 if (GET_CODE (temp1) != ASHIFTRT
3729 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3730 || XEXP (XEXP (temp1, 0), 0) != temp)
8079805d 3731 return temp1;
230d793d
RS		 3732 }
3733 break;
3734
2ca9ae17 3735 case TRUNCATE:
e30fb98f
JL		 3736 /* We can't handle truncation to a partial integer mode here
3737 because we don't know the real bitsize of the partial
3738 integer mode. */
3739 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3740 break;
3741
80608e27
JL		 3742 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3743 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3744 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
2ca9ae17
JW		 3745 SUBST (XEXP (x, 0),
3746 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3747 GET_MODE_MASK (mode), NULL_RTX, 0));
0f13a422
ILT		 3748
3749 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3750 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3751 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3752 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3753 return XEXP (XEXP (x, 0), 0);
3754
3755 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3756 (OP:SI foo:SI) if OP is NEG or ABS. */
3757 if ((GET_CODE (XEXP (x, 0)) == ABS
3758 || GET_CODE (XEXP (x, 0)) == NEG)
3759 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3760 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3761 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3762 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3763 XEXP (XEXP (XEXP (x, 0), 0), 0));
3764
3765 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3766 (truncate:SI x). */
3767 if (GET_CODE (XEXP (x, 0)) == SUBREG
3768 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3769 && subreg_lowpart_p (XEXP (x, 0)))
3770 return SUBREG_REG (XEXP (x, 0));
3771
3772 /* If we know that the value is already truncated, we can
3773 replace the TRUNCATE with a SUBREG. */
9ec36da5
JL		 3774 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3775 >= GET_MODE_BITSIZE (mode) + 1)
0f13a422
ILT		 3776 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3777
3778 /* A truncate of a comparison can be replaced with a subreg if
3779 STORE_FLAG_VALUE permits. This is like the previous test,
3780 but it works even if the comparison is done in a mode larger
3781 than HOST_BITS_PER_WIDE_INT. */
3782 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3783 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3784 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3785 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3786
3787 /* Similarly, a truncate of a register whose value is a
3788 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3789 permits. */
3790 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3791 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3792 && (temp = get_last_value (XEXP (x, 0)))
3793 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3794 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3795
2ca9ae17
JW		 3796 break;
3797
230d793d
RS		 3798 case FLOAT_TRUNCATE:
3799 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3800 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3801 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3802 return XEXP (XEXP (x, 0), 0);
4635f748
RK		 3803
3804 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3805 (OP:SF foo:SF) if OP is NEG or ABS. */
3806 if ((GET_CODE (XEXP (x, 0)) == ABS
3807 || GET_CODE (XEXP (x, 0)) == NEG)
3808 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3809 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
0c1c8ea6
RK		 3810 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3811 XEXP (XEXP (XEXP (x, 0), 0), 0));
1d12df72
RK		 3812
3813 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3814 is (float_truncate:SF x). */
3815 if (GET_CODE (XEXP (x, 0)) == SUBREG
3816 && subreg_lowpart_p (XEXP (x, 0))
3817 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3818 return SUBREG_REG (XEXP (x, 0));
230d793d
RS		 3819 break;
3820
3821#ifdef HAVE_cc0
3822 case COMPARE:
3823 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3824 using cc0, in which case we want to leave it as a COMPARE
3825 so we can distinguish it from a register-register-copy. */
3826 if (XEXP (x, 1) == const0_rtx)
3827 return XEXP (x, 0);
3828
3829 /* In IEEE floating point, x-0 is not the same as x. */
3830 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e
RK		 3831 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3832 || flag_fast_math)
230d793d
RS		 3833 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3834 return XEXP (x, 0);
3835 break;
3836#endif
3837
3838 case CONST:
3839 /* (const (const X)) can become (const X). Do it this way rather than
3840 returning the inner CONST since CONST can be shared with a
3841 REG_EQUAL note. */
3842 if (GET_CODE (XEXP (x, 0)) == CONST)
3843 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3844 break;
3845
3846#ifdef HAVE_lo_sum
3847 case LO_SUM:
3848 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3849 can add in an offset. find_split_point will split this address up
3850 again if it doesn't match. */
3851 if (GET_CODE (XEXP (x, 0)) == HIGH
3852 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3853 return XEXP (x, 1);
3854 break;
3855#endif
3856
3857 case PLUS:
3858 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3859 outermost. That's because that's the way indexed addresses are
3860 supposed to appear. This code used to check many more cases, but
3861 they are now checked elsewhere. */
3862 if (GET_CODE (XEXP (x, 0)) == PLUS
3863 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3864 return gen_binary (PLUS, mode,
3865 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3866 XEXP (x, 1)),
3867 XEXP (XEXP (x, 0), 1));
3868
3869 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3870 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3871 bit-field and can be replaced by either a sign_extend or a
3872 sign_extract. The `and' may be a zero_extend. */
3873 if (GET_CODE (XEXP (x, 0)) == XOR
3874 && GET_CODE (XEXP (x, 1)) == CONST_INT
3875 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3876 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3877 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5f4f0e22 3878 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 3879 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3880 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3881 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5f4f0e22 3882 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
230d793d
RS		 3883 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3884 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3885 == i + 1))))
8079805d
RK		 3886 return simplify_shift_const
3887 (NULL_RTX, ASHIFTRT, mode,
3888 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3889 XEXP (XEXP (XEXP (x, 0), 0), 0),
3890 GET_MODE_BITSIZE (mode) - (i + 1)),
3891 GET_MODE_BITSIZE (mode) - (i + 1));
230d793d 3892
bc0776c6
RK		 3893 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3894 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3895 is 1. This produces better code than the alternative immediately
3896 below. */
3897 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3898 && reversible_comparison_p (XEXP (x, 0))
3899 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3900 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
8079805d 3901 return
0c1c8ea6 3902 gen_unary (NEG, mode, mode,
8079805d
RK		 3903 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3904 mode, XEXP (XEXP (x, 0), 0),
3905 XEXP (XEXP (x, 0), 1)));
bc0776c6
RK		 3906
3907 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
230d793d
RS		 3908 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3909 the bitsize of the mode - 1. This allows simplification of
3910 "a = (b & 8) == 0;" */
3911 if (XEXP (x, 1) == constm1_rtx
3912 && GET_CODE (XEXP (x, 0)) != REG
3913 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3914 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
951553af 3915 && nonzero_bits (XEXP (x, 0), mode) == 1)
8079805d
RK		 3916 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3917 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3918 gen_rtx_combine (XOR, mode,
3919 XEXP (x, 0), const1_rtx),
3920 GET_MODE_BITSIZE (mode) - 1),
3921 GET_MODE_BITSIZE (mode) - 1);
02f4ada4
RK		 3922
3923 /* If we are adding two things that have no bits in common, convert
3924 the addition into an IOR. This will often be further simplified,
3925 for example in cases like ((a & 1) + (a & 2)), which can
3926 become a & 3. */
3927
ac49a949 3928 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
951553af
RK		 3929 && (nonzero_bits (XEXP (x, 0), mode)
3930 & nonzero_bits (XEXP (x, 1), mode)) == 0)
8079805d 3931 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
230d793d
RS		 3932 break;
3933
3934 case MINUS:
0802d516
RK		 3935 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3936 by reversing the comparison code if valid. */
3937 if (STORE_FLAG_VALUE == 1
3938 && XEXP (x, 0) == const1_rtx
5109d49f
RK		 3939 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3940 && reversible_comparison_p (XEXP (x, 1)))
3941 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3942 mode, XEXP (XEXP (x, 1), 0),
3943 XEXP (XEXP (x, 1), 1));
5109d49f 3944
230d793d
RS		 3945 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3946 (and <foo> (const_int pow2-1)) */
3947 if (GET_CODE (XEXP (x, 1)) == AND
3948 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3949 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3950 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8079805d
RK		 3951 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3952 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
7bef8680
RK		 3953
3954 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3955 integers. */
3956 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
8079805d
RK		 3957 return gen_binary (MINUS, mode,
3958 gen_binary (MINUS, mode, XEXP (x, 0),
3959 XEXP (XEXP (x, 1), 0)),
3960 XEXP (XEXP (x, 1), 1));
230d793d
RS		 3961 break;
3962
3963 case MULT:
3964 /* If we have (mult (plus A B) C), apply the distributive law and then
3965 the inverse distributive law to see if things simplify. This
3966 occurs mostly in addresses, often when unrolling loops. */
3967
3968 if (GET_CODE (XEXP (x, 0)) == PLUS)
3969 {
3970 x = apply_distributive_law
3971 (gen_binary (PLUS, mode,
3972 gen_binary (MULT, mode,
3973 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3974 gen_binary (MULT, mode,
3975 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3976
3977 if (GET_CODE (x) != MULT)
8079805d 3978 return x;
230d793d 3979 }
230d793d
RS		 3980 break;
3981
3982 case UDIV:
3983 /* If this is a divide by a power of two, treat it as a shift if
3984 its first operand is a shift. */
3985 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3986 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3987 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3988 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3989 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3990 || GET_CODE (XEXP (x, 0)) == ROTATE
3991 || GET_CODE (XEXP (x, 0)) == ROTATERT))
8079805d 3992 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
230d793d
RS		 3993 break;
3994
3995 case EQ: case NE:
3996 case GT: case GTU: case GE: case GEU:
3997 case LT: case LTU: case LE: case LEU:
3998 /* If the first operand is a condition code, we can't do anything
3999 with it. */
4000 if (GET_CODE (XEXP (x, 0)) == COMPARE
4001 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4002#ifdef HAVE_cc0
4003 && XEXP (x, 0) != cc0_rtx
4004#endif
4005 ))
4006 {
4007 rtx op0 = XEXP (x, 0);
4008 rtx op1 = XEXP (x, 1);
4009 enum rtx_code new_code;
4010
4011 if (GET_CODE (op0) == COMPARE)
4012 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4013
4014 /* Simplify our comparison, if possible. */
4015 new_code = simplify_comparison (code, &op0, &op1);
4016
230d793d 4017 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
951553af 4018 if only the low-order bit is possibly nonzero in X (such as when
5109d49f
RK		 4019 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4020 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4021 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4022 (plus X 1).
4023
4024 Remove any ZERO_EXTRACT we made when thinking this was a
4025 comparison. It may now be simpler to use, e.g., an AND. If a
4026 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4027 the call to make_compound_operation in the SET case. */
4028
0802d516
RK		 4029 if (STORE_FLAG_VALUE == 1
4030 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4031 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4032 return gen_lowpart_for_combine (mode,
4033 expand_compound_operation (op0));
5109d49f 4034
0802d516
RK		 4035 else if (STORE_FLAG_VALUE == 1
4036 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4037 && op1 == const0_rtx
4038 && (num_sign_bit_copies (op0, mode)
4039 == GET_MODE_BITSIZE (mode)))
4040 {
4041 op0 = expand_compound_operation (op0);
0c1c8ea6 4042 return gen_unary (NEG, mode, mode,
8079805d 4043 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4044 }
4045
0802d516
RK		 4046 else if (STORE_FLAG_VALUE == 1
4047 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4048 && op1 == const0_rtx
5109d49f 4049 && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4050 {
4051 op0 = expand_compound_operation (op0);
8079805d
RK		 4052 return gen_binary (XOR, mode,
4053 gen_lowpart_for_combine (mode, op0),
4054 const1_rtx);
5109d49f 4055 }
818b11b9 4056
0802d516
RK		 4057 else if (STORE_FLAG_VALUE == 1
4058 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4059 && op1 == const0_rtx
4060 && (num_sign_bit_copies (op0, mode)
4061 == GET_MODE_BITSIZE (mode)))
4062 {
4063 op0 = expand_compound_operation (op0);
8079805d 4064 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
818b11b9 4065 }
230d793d 4066
5109d49f
RK		 4067 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4068 those above. */
0802d516
RK		 4069 if (STORE_FLAG_VALUE == -1
4070 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4071 && op1 == const0_rtx
5109d49f
RK		 4072 && (num_sign_bit_copies (op0, mode)
4073 == GET_MODE_BITSIZE (mode)))
4074 return gen_lowpart_for_combine (mode,
4075 expand_compound_operation (op0));
4076
0802d516
RK		 4077 else if (STORE_FLAG_VALUE == -1
4078 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4079 && op1 == const0_rtx
4080 && nonzero_bits (op0, mode) == 1)
4081 {
4082 op0 = expand_compound_operation (op0);
0c1c8ea6 4083 return gen_unary (NEG, mode, mode,
8079805d 4084 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4085 }
4086
0802d516
RK		 4087 else if (STORE_FLAG_VALUE == -1
4088 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4089 && op1 == const0_rtx
4090 && (num_sign_bit_copies (op0, mode)
4091 == GET_MODE_BITSIZE (mode)))
230d793d 4092 {
818b11b9 4093 op0 = expand_compound_operation (op0);
0c1c8ea6 4094 return gen_unary (NOT, mode, mode,
8079805d 4095 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4096 }
4097
4098 /* If X is 0/1, (eq X 0) is X-1. */
0802d516
RK		 4099 else if (STORE_FLAG_VALUE == -1
4100 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4101 && op1 == const0_rtx
4102 && nonzero_bits (op0, mode) == 1)
4103 {
4104 op0 = expand_compound_operation (op0);
8079805d 4105 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
230d793d 4106 }
230d793d
RS		 4107
4108 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
951553af
RK		 4109 one bit that might be nonzero, we can convert (ne x 0) to
4110 (ashift x c) where C puts the bit in the sign bit. Remove any
4111 AND with STORE_FLAG_VALUE when we are done, since we are only
4112 going to test the sign bit. */
3f508eca 4113 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5f4f0e22 4114 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 4115 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5f4f0e22 4116 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
230d793d
RS		 4117 && op1 == const0_rtx
4118 && mode == GET_MODE (op0)
5109d49f 4119 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
230d793d 4120 {
818b11b9
RK		 4121 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4122 expand_compound_operation (op0),
230d793d
RS		 4123 GET_MODE_BITSIZE (mode) - 1 - i);
4124 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4125 return XEXP (x, 0);
4126 else
4127 return x;
4128 }
4129
4130 /* If the code changed, return a whole new comparison. */
4131 if (new_code != code)
4132 return gen_rtx_combine (new_code, mode, op0, op1);
4133
4134 /* Otherwise, keep this operation, but maybe change its operands.
4135 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4136 SUBST (XEXP (x, 0), op0);
4137 SUBST (XEXP (x, 1), op1);
4138 }
4139 break;
4140
4141 case IF_THEN_ELSE:
8079805d 4142 return simplify_if_then_else (x);
9210df58 4143
8079805d
RK		 4144 case ZERO_EXTRACT:
4145 case SIGN_EXTRACT:
4146 case ZERO_EXTEND:
4147 case SIGN_EXTEND:
0f41302f 4148 /* If we are processing SET_DEST, we are done. */
8079805d
RK		 4149 if (in_dest)
4150 return x;
d0ab8cd3 4151
8079805d 4152 return expand_compound_operation (x);
d0ab8cd3 4153
8079805d
RK		 4154 case SET:
4155 return simplify_set (x);
1a26b032 4156
8079805d
RK		 4157 case AND:
4158 case IOR:
4159 case XOR:
4160 return simplify_logical (x, last);
d0ab8cd3 4161
b472527b 4162 case ABS:
8079805d
RK		 4163 /* (abs (neg <foo>)) -> (abs <foo>) */
4164 if (GET_CODE (XEXP (x, 0)) == NEG)
4165 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
1a26b032 4166
b472527b
JL		 4167 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4168 do nothing. */
4169 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4170 break;
f40421ce 4171
8079805d
RK		 4172 /* If operand is something known to be positive, ignore the ABS. */
4173 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4174 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4175 <= HOST_BITS_PER_WIDE_INT)
4176 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4177 & ((HOST_WIDE_INT) 1
4178 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4179 == 0)))
4180 return XEXP (x, 0);
1a26b032 4181
1a26b032 4182
8079805d
RK		 4183 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4184 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4185 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
1a26b032 4186
8079805d 4187 break;
1a26b032 4188
8079805d
RK		 4189 case FFS:
4190 /* (ffs (*_extend <X>)) = (ffs <X>) */
4191 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4192 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4193 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4194 break;
1a26b032 4195
8079805d
RK		 4196 case FLOAT:
4197 /* (float (sign_extend <X>)) = (float <X>). */
4198 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4199 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4200 break;
1a26b032 4201
8079805d
RK		 4202 case ASHIFT:
4203 case LSHIFTRT:
4204 case ASHIFTRT:
4205 case ROTATE:
4206 case ROTATERT:
4207 /* If this is a shift by a constant amount, simplify it. */
4208 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4209 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4210 INTVAL (XEXP (x, 1)));
4211
4212#ifdef SHIFT_COUNT_TRUNCATED
4213 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4214 SUBST (XEXP (x, 1),
4215 force_to_mode (XEXP (x, 1), GET_MODE (x),
4216 ((HOST_WIDE_INT) 1
4217 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4218 - 1,
4219 NULL_RTX, 0));
4220#endif
4221
4222 break;
e9a25f70
JL		 4223
4224 default:
4225 break;
8079805d
RK		 4226 }
4227
4228 return x;
4229}
4230\f
4231/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5109d49f 4232
8079805d
RK		 4233static rtx
4234simplify_if_then_else (x)
4235 rtx x;
4236{
4237 enum machine_mode mode = GET_MODE (x);
4238 rtx cond = XEXP (x, 0);
4239 rtx true = XEXP (x, 1);
4240 rtx false = XEXP (x, 2);
4241 enum rtx_code true_code = GET_CODE (cond);
4242 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4243 rtx temp;
4244 int i;
4245
0f41302f 4246 /* Simplify storing of the truth value. */
8079805d
RK		 4247 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4248 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4249
0f41302f 4250 /* Also when the truth value has to be reversed. */
8079805d
RK		 4251 if (comparison_p && reversible_comparison_p (cond)
4252 && true == const0_rtx && false == const_true_rtx)
4253 return gen_binary (reverse_condition (true_code),
4254 mode, XEXP (cond, 0), XEXP (cond, 1));
4255
4256 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4257 in it is being compared against certain values. Get the true and false
4258 comparisons and see if that says anything about the value of each arm. */
4259
4260 if (comparison_p && reversible_comparison_p (cond)
4261 && GET_CODE (XEXP (cond, 0)) == REG)
4262 {
4263 HOST_WIDE_INT nzb;
4264 rtx from = XEXP (cond, 0);
4265 enum rtx_code false_code = reverse_condition (true_code);
4266 rtx true_val = XEXP (cond, 1);
4267 rtx false_val = true_val;
4268 int swapped = 0;
9210df58 4269
8079805d 4270 /* If FALSE_CODE is EQ, swap the codes and arms. */
5109d49f 4271
8079805d 4272 if (false_code == EQ)
1a26b032 4273 {
8079805d
RK		 4274 swapped = 1, true_code = EQ, false_code = NE;
4275 temp = true, true = false, false = temp;
4276 }
5109d49f 4277
8079805d
RK		 4278 /* If we are comparing against zero and the expression being tested has
4279 only a single bit that might be nonzero, that is its value when it is
4280 not equal to zero. Similarly if it is known to be -1 or 0. */
4281
4282 if (true_code == EQ && true_val == const0_rtx
4283 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4284 false_code = EQ, false_val = GEN_INT (nzb);
4285 else if (true_code == EQ && true_val == const0_rtx
4286 && (num_sign_bit_copies (from, GET_MODE (from))
4287 == GET_MODE_BITSIZE (GET_MODE (from))))
4288 false_code = EQ, false_val = constm1_rtx;
4289
4290 /* Now simplify an arm if we know the value of the register in the
4291 branch and it is used in the arm. Be careful due to the potential
4292 of locally-shared RTL. */
4293
4294 if (reg_mentioned_p (from, true))
4295 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4296 pc_rtx, pc_rtx, 0, 0);
4297 if (reg_mentioned_p (from, false))
4298 false = subst (known_cond (copy_rtx (false), false_code,
4299 from, false_val),
4300 pc_rtx, pc_rtx, 0, 0);
4301
4302 SUBST (XEXP (x, 1), swapped ? false : true);
4303 SUBST (XEXP (x, 2), swapped ? true : false);
4304
4305 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4306 }
5109d49f 4307
8079805d
RK		 4308 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4309 reversed, do so to avoid needing two sets of patterns for
4310 subtract-and-branch insns. Similarly if we have a constant in the true
4311 arm, the false arm is the same as the first operand of the comparison, or
4312 the false arm is more complicated than the true arm. */
4313
4314 if (comparison_p && reversible_comparison_p (cond)
4315 && (true == pc_rtx
4316 || (CONSTANT_P (true)
4317 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4318 || true == const0_rtx
4319 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4320 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4321 || (GET_CODE (true) == SUBREG
4322 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4323 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4324 || reg_mentioned_p (true, false)
4325 || rtx_equal_p (false, XEXP (cond, 0))))
4326 {
4327 true_code = reverse_condition (true_code);
4328 SUBST (XEXP (x, 0),
4329 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4330 XEXP (cond, 1)));
5109d49f 4331
8079805d
RK		 4332 SUBST (XEXP (x, 1), false);
4333 SUBST (XEXP (x, 2), true);
1a26b032 4334
8079805d 4335 temp = true, true = false, false = temp, cond = XEXP (x, 0);
bb821298 4336
0f41302f 4337 /* It is possible that the conditional has been simplified out. */
bb821298
RK		 4338 true_code = GET_CODE (cond);
4339 comparison_p = GET_RTX_CLASS (true_code) == '<';
8079805d 4340 }
abe6e52f 4341
8079805d 4342 /* If the two arms are identical, we don't need the comparison. */
1a26b032 4343
8079805d
RK		 4344 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4345 return true;
1a26b032 4346
5be669c7
RK		 4347 /* Convert a == b ? b : a to "a". */
4348 if (true_code == EQ && ! side_effects_p (cond)
4349 && rtx_equal_p (XEXP (cond, 0), false)
4350 && rtx_equal_p (XEXP (cond, 1), true))
4351 return false;
4352 else if (true_code == NE && ! side_effects_p (cond)
4353 && rtx_equal_p (XEXP (cond, 0), true)
4354 && rtx_equal_p (XEXP (cond, 1), false))
4355 return true;
4356
8079805d
RK		 4357 /* Look for cases where we have (abs x) or (neg (abs X)). */
4358
4359 if (GET_MODE_CLASS (mode) == MODE_INT
4360 && GET_CODE (false) == NEG
4361 && rtx_equal_p (true, XEXP (false, 0))
4362 && comparison_p
4363 && rtx_equal_p (true, XEXP (cond, 0))
4364 && ! side_effects_p (true))
4365 switch (true_code)
4366 {
4367 case GT:
4368 case GE:
0c1c8ea6 4369 return gen_unary (ABS, mode, mode, true);
8079805d
RK		 4370 case LT:
4371 case LE:
0c1c8ea6 4372 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
e9a25f70
JL		 4373 default:
4374 break;
8079805d
RK		 4375 }
4376
4377 /* Look for MIN or MAX. */
4378
34c8be72 4379 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
8079805d
RK		 4380 && comparison_p
4381 && rtx_equal_p (XEXP (cond, 0), true)
4382 && rtx_equal_p (XEXP (cond, 1), false)
4383 && ! side_effects_p (cond))
4384 switch (true_code)
4385 {
4386 case GE:
4387 case GT:
4388 return gen_binary (SMAX, mode, true, false);
4389 case LE:
4390 case LT:
4391 return gen_binary (SMIN, mode, true, false);
4392 case GEU:
4393 case GTU:
4394 return gen_binary (UMAX, mode, true, false);
4395 case LEU:
4396 case LTU:
4397 return gen_binary (UMIN, mode, true, false);
e9a25f70
JL		 4398 default:
4399 break;
8079805d
RK		 4400 }
4401
8079805d
RK		 4402 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4403 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4404 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4405 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4406 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
0802d516 4407 neither 1 or -1, but it isn't worth checking for. */
8079805d 4408
0802d516
RK		 4409 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4410 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
8079805d
RK		 4411 {
4412 rtx t = make_compound_operation (true, SET);
4413 rtx f = make_compound_operation (false, SET);
4414 rtx cond_op0 = XEXP (cond, 0);
4415 rtx cond_op1 = XEXP (cond, 1);
4416 enum rtx_code op, extend_op = NIL;
4417 enum machine_mode m = mode;
f24ad0e4 4418 rtx z = 0, c1;
8079805d 4419
8079805d
RK		 4420 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4421 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4422 || GET_CODE (t) == ASHIFT
4423 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4424 && rtx_equal_p (XEXP (t, 0), f))
4425 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4426
4427 /* If an identity-zero op is commutative, check whether there
0f41302f 4428 would be a match if we swapped the operands. */
8079805d
RK		 4429 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4430 || GET_CODE (t) == XOR)
4431 && rtx_equal_p (XEXP (t, 1), f))
4432 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4433 else if (GET_CODE (t) == SIGN_EXTEND
4434 && (GET_CODE (XEXP (t, 0)) == PLUS
4435 || GET_CODE (XEXP (t, 0)) == MINUS
4436 || GET_CODE (XEXP (t, 0)) == IOR
4437 || GET_CODE (XEXP (t, 0)) == XOR
4438 || GET_CODE (XEXP (t, 0)) == ASHIFT
4439 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4440 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4441 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4442 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4443 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4444 && (num_sign_bit_copies (f, GET_MODE (f))
4445 > (GET_MODE_BITSIZE (mode)
4446 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4447 {
4448 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4449 extend_op = SIGN_EXTEND;
4450 m = GET_MODE (XEXP (t, 0));
1a26b032 4451 }
8079805d
RK		 4452 else if (GET_CODE (t) == SIGN_EXTEND
4453 && (GET_CODE (XEXP (t, 0)) == PLUS
4454 || GET_CODE (XEXP (t, 0)) == IOR
4455 || GET_CODE (XEXP (t, 0)) == XOR)
4456 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4457 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4458 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4459 && (num_sign_bit_copies (f, GET_MODE (f))
4460 > (GET_MODE_BITSIZE (mode)
4461 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4462 {
4463 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4464 extend_op = SIGN_EXTEND;
4465 m = GET_MODE (XEXP (t, 0));
4466 }
4467 else if (GET_CODE (t) == ZERO_EXTEND
4468 && (GET_CODE (XEXP (t, 0)) == PLUS
4469 || GET_CODE (XEXP (t, 0)) == MINUS
4470 || GET_CODE (XEXP (t, 0)) == IOR
4471 || GET_CODE (XEXP (t, 0)) == XOR
4472 || GET_CODE (XEXP (t, 0)) == ASHIFT
4473 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4474 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4475 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4476 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4477 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4478 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4479 && ((nonzero_bits (f, GET_MODE (f))
4480 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4481 == 0))
4482 {
4483 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4484 extend_op = ZERO_EXTEND;
4485 m = GET_MODE (XEXP (t, 0));
4486 }
4487 else if (GET_CODE (t) == ZERO_EXTEND
4488 && (GET_CODE (XEXP (t, 0)) == PLUS
4489 || GET_CODE (XEXP (t, 0)) == IOR
4490 || GET_CODE (XEXP (t, 0)) == XOR)
4491 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4492 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4493 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4494 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4495 && ((nonzero_bits (f, GET_MODE (f))
4496 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4497 == 0))
4498 {
4499 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4500 extend_op = ZERO_EXTEND;
4501 m = GET_MODE (XEXP (t, 0));
4502 }
4503
4504 if (z)
4505 {
4506 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4507 pc_rtx, pc_rtx, 0, 0);
4508 temp = gen_binary (MULT, m, temp,
4509 gen_binary (MULT, m, c1, const_true_rtx));
4510 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4511 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4512
4513 if (extend_op != NIL)
0c1c8ea6 4514 temp = gen_unary (extend_op, mode, m, temp);
8079805d
RK		 4515
4516 return temp;
4517 }
4518 }
224eeff2 4519
8079805d
RK		 4520 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4521 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4522 negation of a single bit, we can convert this operation to a shift. We
4523 can actually do this more generally, but it doesn't seem worth it. */
4524
4525 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4526 && false == const0_rtx && GET_CODE (true) == CONST_INT
4527 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4528 && (i = exact_log2 (INTVAL (true))) >= 0)
4529 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4530 == GET_MODE_BITSIZE (mode))
4531 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4532 return
4533 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4534 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
230d793d 4535
8079805d
RK		 4536 return x;
4537}
4538\f
4539/* Simplify X, a SET expression. Return the new expression. */
230d793d 4540
8079805d
RK		 4541static rtx
4542simplify_set (x)
4543 rtx x;
4544{
4545 rtx src = SET_SRC (x);
4546 rtx dest = SET_DEST (x);
4547 enum machine_mode mode
4548 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4549 rtx other_insn;
4550 rtx *cc_use;
4551
4552 /* (set (pc) (return)) gets written as (return). */
4553 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4554 return src;
230d793d 4555
87e3e0c1
RK		 4556 /* Now that we know for sure which bits of SRC we are using, see if we can
4557 simplify the expression for the object knowing that we only need the
4558 low-order bits. */
4559
4560 if (GET_MODE_CLASS (mode) == MODE_INT)
4561 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4562
8079805d
RK		 4563 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4564 the comparison result and try to simplify it unless we already have used
4565 undobuf.other_insn. */
4566 if ((GET_CODE (src) == COMPARE
230d793d 4567#ifdef HAVE_cc0
8079805d 4568 || dest == cc0_rtx
230d793d 4569#endif
8079805d
RK		 4570 )
4571 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4572 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4573 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
c0d3ac4d 4574 && rtx_equal_p (XEXP (*cc_use, 0), dest))
8079805d
RK		 4575 {
4576 enum rtx_code old_code = GET_CODE (*cc_use);
4577 enum rtx_code new_code;
4578 rtx op0, op1;
4579 int other_changed = 0;
4580 enum machine_mode compare_mode = GET_MODE (dest);
4581
4582 if (GET_CODE (src) == COMPARE)
4583 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4584 else
4585 op0 = src, op1 = const0_rtx;
230d793d 4586
8079805d
RK		 4587 /* Simplify our comparison, if possible. */
4588 new_code = simplify_comparison (old_code, &op0, &op1);
230d793d 4589
c141a106 4590#ifdef EXTRA_CC_MODES
8079805d
RK		 4591 /* If this machine has CC modes other than CCmode, check to see if we
4592 need to use a different CC mode here. */
4593 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
c141a106 4594#endif /* EXTRA_CC_MODES */
230d793d 4595
c141a106 4596#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
8079805d
RK		 4597 /* If the mode changed, we have to change SET_DEST, the mode in the
4598 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4599 a hard register, just build new versions with the proper mode. If it
4600 is a pseudo, we lose unless it is only time we set the pseudo, in
4601 which case we can safely change its mode. */
4602 if (compare_mode != GET_MODE (dest))
4603 {
4604 int regno = REGNO (dest);
38a448ca 4605 rtx new_dest = gen_rtx_REG (compare_mode, regno);
8079805d
RK		 4606
4607 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 4608 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
230d793d 4609 {
8079805d
RK		 4610 if (regno >= FIRST_PSEUDO_REGISTER)
4611 SUBST (regno_reg_rtx[regno], new_dest);
230d793d 4612
8079805d
RK		 4613 SUBST (SET_DEST (x), new_dest);
4614 SUBST (XEXP (*cc_use, 0), new_dest);
4615 other_changed = 1;
230d793d 4616
8079805d 4617 dest = new_dest;
230d793d 4618 }
8079805d 4619 }
230d793d
RS		 4620#endif
4621
8079805d
RK		 4622 /* If the code changed, we have to build a new comparison in
4623 undobuf.other_insn. */
4624 if (new_code != old_code)
4625 {
4626 unsigned HOST_WIDE_INT mask;
4627
4628 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4629 dest, const0_rtx));
4630
4631 /* If the only change we made was to change an EQ into an NE or
4632 vice versa, OP0 has only one bit that might be nonzero, and OP1
4633 is zero, check if changing the user of the condition code will
4634 produce a valid insn. If it won't, we can keep the original code
4635 in that insn by surrounding our operation with an XOR. */
4636
4637 if (((old_code == NE && new_code == EQ)
4638 || (old_code == EQ && new_code == NE))
4639 && ! other_changed && op1 == const0_rtx
4640 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4641 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
230d793d 4642 {
8079805d 4643 rtx pat = PATTERN (other_insn), note = 0;
a29ca9db 4644 int scratches;
230d793d 4645
a29ca9db 4646 if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
8079805d
RK		 4647 && ! check_asm_operands (pat)))
4648 {
4649 PUT_CODE (*cc_use, old_code);
4650 other_insn = 0;
230d793d 4651
8079805d 4652 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
230d793d 4653 }
230d793d
RS		 4654 }
4655
8079805d
RK		 4656 other_changed = 1;
4657 }
4658
4659 if (other_changed)
4660 undobuf.other_insn = other_insn;
230d793d
RS		 4661
4662#ifdef HAVE_cc0
8079805d
RK		 4663 /* If we are now comparing against zero, change our source if
4664 needed. If we do not use cc0, we always have a COMPARE. */
4665 if (op1 == const0_rtx && dest == cc0_rtx)
4666 {
4667 SUBST (SET_SRC (x), op0);
4668 src = op0;
4669 }
4670 else
230d793d
RS		 4671#endif
4672
8079805d
RK		 4673 /* Otherwise, if we didn't previously have a COMPARE in the
4674 correct mode, we need one. */
4675 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4676 {
4677 SUBST (SET_SRC (x),
4678 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4679 src = SET_SRC (x);
230d793d
RS		 4680 }
4681 else
4682 {
8079805d
RK		 4683 /* Otherwise, update the COMPARE if needed. */
4684 SUBST (XEXP (src, 0), op0);
4685 SUBST (XEXP (src, 1), op1);
230d793d 4686 }
8079805d
RK		 4687 }
4688 else
4689 {
4690 /* Get SET_SRC in a form where we have placed back any
4691 compound expressions. Then do the checks below. */
4692 src = make_compound_operation (src, SET);
4693 SUBST (SET_SRC (x), src);
4694 }
230d793d 4695
8079805d
RK		 4696 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4697 and X being a REG or (subreg (reg)), we may be able to convert this to
4698 (set (subreg:m2 x) (op)).
df62f951 4699
8079805d
RK		 4700 We can always do this if M1 is narrower than M2 because that means that
4701 we only care about the low bits of the result.
df62f951 4702
8079805d 4703 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
9ec36da5 4704 perform a narrower operation than requested since the high-order bits will
8079805d
RK		 4705 be undefined. On machine where it is defined, this transformation is safe
4706 as long as M1 and M2 have the same number of words. */
df62f951 4707
8079805d
RK		 4708 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4709 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4710 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4711 / UNITS_PER_WORD)
4712 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4713 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
8baf60bb 4714#ifndef WORD_REGISTER_OPERATIONS
8079805d
RK		 4715 && (GET_MODE_SIZE (GET_MODE (src))
4716 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
df62f951 4717#endif
f507a070
RK		 4718#ifdef CLASS_CANNOT_CHANGE_SIZE
4719 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4720 && (TEST_HARD_REG_BIT
4721 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4722 REGNO (dest)))
4723 && (GET_MODE_SIZE (GET_MODE (src))
4724 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4725#endif
8079805d
RK		 4726 && (GET_CODE (dest) == REG
4727 || (GET_CODE (dest) == SUBREG
4728 && GET_CODE (SUBREG_REG (dest)) == REG)))
4729 {
4730 SUBST (SET_DEST (x),
4731 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4732 dest));
4733 SUBST (SET_SRC (x), SUBREG_REG (src));
4734
4735 src = SET_SRC (x), dest = SET_DEST (x);
4736 }
df62f951 4737
8baf60bb 4738#ifdef LOAD_EXTEND_OP
8079805d
RK		 4739 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4740 would require a paradoxical subreg. Replace the subreg with a
0f41302f 4741 zero_extend to avoid the reload that would otherwise be required. */
8079805d
RK		 4742
4743 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4744 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4745 && SUBREG_WORD (src) == 0
4746 && (GET_MODE_SIZE (GET_MODE (src))
4747 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4748 && GET_CODE (SUBREG_REG (src)) == MEM)
4749 {
4750 SUBST (SET_SRC (x),
4751 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4752 GET_MODE (src), XEXP (src, 0)));
4753
4754 src = SET_SRC (x);
4755 }
230d793d
RS		 4756#endif
4757
8079805d
RK		 4758 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4759 are comparing an item known to be 0 or -1 against 0, use a logical
4760 operation instead. Check for one of the arms being an IOR of the other
4761 arm with some value. We compute three terms to be IOR'ed together. In
4762 practice, at most two will be nonzero. Then we do the IOR's. */
4763
4764 if (GET_CODE (dest) != PC
4765 && GET_CODE (src) == IF_THEN_ELSE
36b8d792 4766 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
8079805d
RK		 4767 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4768 && XEXP (XEXP (src, 0), 1) == const0_rtx
6dd49058 4769 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
ea414472
DE		 4770#ifdef HAVE_conditional_move
4771 && ! can_conditionally_move_p (GET_MODE (src))
4772#endif
8079805d
RK		 4773 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4774 GET_MODE (XEXP (XEXP (src, 0), 0)))
4775 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4776 && ! side_effects_p (src))
4777 {
4778 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4779 ? XEXP (src, 1) : XEXP (src, 2));
4780 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4781 ? XEXP (src, 2) : XEXP (src, 1));
4782 rtx term1 = const0_rtx, term2, term3;
4783
4784 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4785 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4786 else if (GET_CODE (true) == IOR
4787 && rtx_equal_p (XEXP (true, 1), false))
4788 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4789 else if (GET_CODE (false) == IOR
4790 && rtx_equal_p (XEXP (false, 0), true))
4791 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4792 else if (GET_CODE (false) == IOR
4793 && rtx_equal_p (XEXP (false, 1), true))
4794 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4795
4796 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4797 term3 = gen_binary (AND, GET_MODE (src),
0c1c8ea6 4798 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
8079805d
RK		 4799 XEXP (XEXP (src, 0), 0)),
4800 false);
4801
4802 SUBST (SET_SRC (x),
4803 gen_binary (IOR, GET_MODE (src),
4804 gen_binary (IOR, GET_MODE (src), term1, term2),
4805 term3));
4806
4807 src = SET_SRC (x);
4808 }
230d793d 4809
246e00f2
RK		 4810 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4811 whole thing fail. */
4812 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4813 return src;
4814 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4815 return dest;
4816 else
4817 /* Convert this into a field assignment operation, if possible. */
4818 return make_field_assignment (x);
8079805d
RK		 4819}
4820\f
4821/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4822 result. LAST is nonzero if this is the last retry. */
4823
4824static rtx
4825simplify_logical (x, last)
4826 rtx x;
4827 int last;
4828{
4829 enum machine_mode mode = GET_MODE (x);
4830 rtx op0 = XEXP (x, 0);
4831 rtx op1 = XEXP (x, 1);
4832
4833 switch (GET_CODE (x))
4834 {
230d793d 4835 case AND:
8079805d
RK		 4836 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4837 insn (and may simplify more). */
4838 if (GET_CODE (op0) == XOR
4839 && rtx_equal_p (XEXP (op0, 0), op1)
4840 && ! side_effects_p (op1))
0c1c8ea6
RK		 4841 x = gen_binary (AND, mode,
4842 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
8079805d
RK		 4843
4844 if (GET_CODE (op0) == XOR
4845 && rtx_equal_p (XEXP (op0, 1), op1)
4846 && ! side_effects_p (op1))
0c1c8ea6
RK		 4847 x = gen_binary (AND, mode,
4848 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
8079805d
RK		 4849
4850 /* Similarly for (~ (A ^ B)) & A. */
4851 if (GET_CODE (op0) == NOT
4852 && GET_CODE (XEXP (op0, 0)) == XOR
4853 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4854 && ! side_effects_p (op1))
4855 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4856
4857 if (GET_CODE (op0) == NOT
4858 && GET_CODE (XEXP (op0, 0)) == XOR
4859 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4860 && ! side_effects_p (op1))
4861 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4862
4863 if (GET_CODE (op1) == CONST_INT)
230d793d 4864 {
8079805d 4865 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
230d793d
RS		 4866
4867 /* If we have (ior (and (X C1) C2)) and the next restart would be
4868 the last, simplify this by making C1 as small as possible
0f41302f 4869 and then exit. */
8079805d
RK		 4870 if (last
4871 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4872 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4873 && GET_CODE (op1) == CONST_INT)
4874 return gen_binary (IOR, mode,
4875 gen_binary (AND, mode, XEXP (op0, 0),
4876 GEN_INT (INTVAL (XEXP (op0, 1))
4877 & ~ INTVAL (op1))), op1);
230d793d
RS		 4878
4879 if (GET_CODE (x) != AND)
8079805d 4880 return x;
0e32506c
RK		 4881
4882 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4883 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4884 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
230d793d
RS		 4885 }
4886
4887 /* Convert (A | B) & A to A. */
8079805d
RK		 4888 if (GET_CODE (op0) == IOR
4889 && (rtx_equal_p (XEXP (op0, 0), op1)
4890 || rtx_equal_p (XEXP (op0, 1), op1))
4891 && ! side_effects_p (XEXP (op0, 0))
4892 && ! side_effects_p (XEXP (op0, 1)))
4893 return op1;
230d793d 4894
d0ab8cd3 4895 /* In the following group of tests (and those in case IOR below),
230d793d
RS		 4896 we start with some combination of logical operations and apply
4897 the distributive law followed by the inverse distributive law.
4898 Most of the time, this results in no change. However, if some of
4899 the operands are the same or inverses of each other, simplifications
4900 will result.
4901
4902 For example, (and (ior A B) (not B)) can occur as the result of
4903 expanding a bit field assignment. When we apply the distributive
4904 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8079805d 4905 which then simplifies to (and (A (not B))).
230d793d 4906
8079805d 4907 If we have (and (ior A B) C), apply the distributive law and then
230d793d
RS		 4908 the inverse distributive law to see if things simplify. */
4909
8079805d 4910 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
230d793d
RS		 4911 {
4912 x = apply_distributive_law
8079805d
RK		 4913 (gen_binary (GET_CODE (op0), mode,
4914 gen_binary (AND, mode, XEXP (op0, 0), op1),
4915 gen_binary (AND, mode, XEXP (op0, 1), op1)));
230d793d 4916 if (GET_CODE (x) != AND)
8079805d 4917 return x;
230d793d
RS		 4918 }
4919
8079805d
RK		 4920 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4921 return apply_distributive_law
4922 (gen_binary (GET_CODE (op1), mode,
4923 gen_binary (AND, mode, XEXP (op1, 0), op0),
4924 gen_binary (AND, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4925
4926 /* Similarly, taking advantage of the fact that
4927 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4928
8079805d
RK		 4929 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4930 return apply_distributive_law
4931 (gen_binary (XOR, mode,
4932 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4933 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
230d793d 4934
8079805d
RK		 4935 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4936 return apply_distributive_law
4937 (gen_binary (XOR, mode,
4938 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4939 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
230d793d
RS		 4940 break;
4941
4942 case IOR:
951553af 4943 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
8079805d 4944 if (GET_CODE (op1) == CONST_INT
ac49a949 4945 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8079805d
RK		 4946 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4947 return op1;
d0ab8cd3 4948
230d793d 4949 /* Convert (A & B) | A to A. */
8079805d
RK		 4950 if (GET_CODE (op0) == AND
4951 && (rtx_equal_p (XEXP (op0, 0), op1)
4952 || rtx_equal_p (XEXP (op0, 1), op1))
4953 && ! side_effects_p (XEXP (op0, 0))
4954 && ! side_effects_p (XEXP (op0, 1)))
4955 return op1;
230d793d
RS		 4956
4957 /* If we have (ior (and A B) C), apply the distributive law and then
4958 the inverse distributive law to see if things simplify. */
4959
8079805d 4960 if (GET_CODE (op0) == AND)
230d793d
RS		 4961 {
4962 x = apply_distributive_law
4963 (gen_binary (AND, mode,
8079805d
RK		 4964 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4965 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
230d793d
RS		 4966
4967 if (GET_CODE (x) != IOR)
8079805d 4968 return x;
230d793d
RS		 4969 }
4970
8079805d 4971 if (GET_CODE (op1) == AND)
230d793d
RS		 4972 {
4973 x = apply_distributive_law
4974 (gen_binary (AND, mode,
8079805d
RK		 4975 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4976 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4977
4978 if (GET_CODE (x) != IOR)
8079805d 4979 return x;
230d793d
RS		 4980 }
4981
4982 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4983 mode size to (rotate A CX). */
4984
8079805d
RK		 4985 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4986 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4987 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4988 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4989 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4990 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
230d793d 4991 == GET_MODE_BITSIZE (mode)))
38a448ca
RH		 4992 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
4993 (GET_CODE (op0) == ASHIFT
4994 ? XEXP (op0, 1) : XEXP (op1, 1)));
230d793d 4995
71923da7
RK		 4996 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4997 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4998 does not affect any of the bits in OP1, it can really be done
4999 as a PLUS and we can associate. We do this by seeing if OP1
5000 can be safely shifted left C bits. */
5001 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5002 && GET_CODE (XEXP (op0, 0)) == PLUS
5003 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5004 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5005 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5006 {
5007 int count = INTVAL (XEXP (op0, 1));
5008 HOST_WIDE_INT mask = INTVAL (op1) << count;
5009
5010 if (mask >> count == INTVAL (op1)
5011 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5012 {
5013 SUBST (XEXP (XEXP (op0, 0), 1),
5014 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5015 return op0;
5016 }
5017 }
230d793d
RS		 5018 break;
5019
5020 case XOR:
5021 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5022 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5023 (NOT y). */
5024 {
5025 int num_negated = 0;
230d793d 5026
8079805d
RK		 5027 if (GET_CODE (op0) == NOT)
5028 num_negated++, op0 = XEXP (op0, 0);
5029 if (GET_CODE (op1) == NOT)
5030 num_negated++, op1 = XEXP (op1, 0);
230d793d
RS		 5031
5032 if (num_negated == 2)
5033 {
8079805d
RK		 5034 SUBST (XEXP (x, 0), op0);
5035 SUBST (XEXP (x, 1), op1);
230d793d
RS		 5036 }
5037 else if (num_negated == 1)
0c1c8ea6 5038 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
230d793d
RS		 5039 }
5040
5041 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5042 correspond to a machine insn or result in further simplifications
5043 if B is a constant. */
5044
8079805d
RK		 5045 if (GET_CODE (op0) == AND
5046 && rtx_equal_p (XEXP (op0, 1), op1)
5047 && ! side_effects_p (op1))
0c1c8ea6
RK		 5048 return gen_binary (AND, mode,
5049 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
8079805d 5050 op1);
230d793d 5051
8079805d
RK		 5052 else if (GET_CODE (op0) == AND
5053 && rtx_equal_p (XEXP (op0, 0), op1)
5054 && ! side_effects_p (op1))
0c1c8ea6
RK		 5055 return gen_binary (AND, mode,
5056 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
8079805d 5057 op1);
230d793d 5058
230d793d 5059 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
0802d516
RK		 5060 comparison if STORE_FLAG_VALUE is 1. */
5061 if (STORE_FLAG_VALUE == 1
5062 && op1 == const1_rtx
8079805d
RK		 5063 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5064 && reversible_comparison_p (op0))
5065 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5066 mode, XEXP (op0, 0), XEXP (op0, 1));
500c518b
RK		 5067
5068 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5069 is (lt foo (const_int 0)), so we can perform the above
0802d516 5070 simplification if STORE_FLAG_VALUE is 1. */
500c518b 5071
0802d516
RK		 5072 if (STORE_FLAG_VALUE == 1
5073 && op1 == const1_rtx
8079805d
RK		 5074 && GET_CODE (op0) == LSHIFTRT
5075 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5076 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5077 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
230d793d
RS		 5078
5079 /* (xor (comparison foo bar) (const_int sign-bit))
5080 when STORE_FLAG_VALUE is the sign bit. */
5f4f0e22 5081 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 5082 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5f4f0e22 5083 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
8079805d
RK		 5084 && op1 == const_true_rtx
5085 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5086 && reversible_comparison_p (op0))
5087 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5088 mode, XEXP (op0, 0), XEXP (op0, 1));
230d793d 5089 break;
e9a25f70
JL		 5090
5091 default:
5092 abort ();
230d793d
RS		 5093 }
5094
5095 return x;
5096}
5097\f
5098/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5099 operations" because they can be replaced with two more basic operations.
5100 ZERO_EXTEND is also considered "compound" because it can be replaced with
5101 an AND operation, which is simpler, though only one operation.
5102
5103 The function expand_compound_operation is called with an rtx expression
5104 and will convert it to the appropriate shifts and AND operations,
5105 simplifying at each stage.
5106
5107 The function make_compound_operation is called to convert an expression
5108 consisting of shifts and ANDs into the equivalent compound expression.
5109 It is the inverse of this function, loosely speaking. */
5110
5111static rtx
5112expand_compound_operation (x)
5113 rtx x;
5114{
5115 int pos = 0, len;
5116 int unsignedp = 0;
5117 int modewidth;
5118 rtx tem;
5119
5120 switch (GET_CODE (x))
5121 {
5122 case ZERO_EXTEND:
5123 unsignedp = 1;
5124 case SIGN_EXTEND:
75473182
RS		 5125 /* We can't necessarily use a const_int for a multiword mode;
5126 it depends on implicitly extending the value.
5127 Since we don't know the right way to extend it,
5128 we can't tell whether the implicit way is right.
5129
5130 Even for a mode that is no wider than a const_int,
5131 we can't win, because we need to sign extend one of its bits through
5132 the rest of it, and we don't know which bit. */
230d793d 5133 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
75473182 5134 return x;
230d793d 5135
8079805d
RK		 5136 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5137 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5138 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5139 reloaded. If not for that, MEM's would very rarely be safe.
5140
5141 Reject MODEs bigger than a word, because we might not be able
5142 to reference a two-register group starting with an arbitrary register
5143 (and currently gen_lowpart might crash for a SUBREG). */
5144
5145 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
230d793d
RS		 5146 return x;
5147
5148 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5149 /* If the inner object has VOIDmode (the only way this can happen
5150 is if it is a ASM_OPERANDS), we can't do anything since we don't
5151 know how much masking to do. */
5152 if (len == 0)
5153 return x;
5154
5155 break;
5156
5157 case ZERO_EXTRACT:
5158 unsignedp = 1;
5159 case SIGN_EXTRACT:
5160 /* If the operand is a CLOBBER, just return it. */
5161 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5162 return XEXP (x, 0);
5163
5164 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5165 || GET_CODE (XEXP (x, 2)) != CONST_INT
5166 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5167 return x;
5168
5169 len = INTVAL (XEXP (x, 1));
5170 pos = INTVAL (XEXP (x, 2));
5171
5172 /* If this goes outside the object being extracted, replace the object
5173 with a (use (mem ...)) construct that only combine understands
5174 and is used only for this purpose. */
5175 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
38a448ca 5176 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
230d793d 5177
f76b9db2
ILT		 5178 if (BITS_BIG_ENDIAN)
5179 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5180
230d793d
RS		 5181 break;
5182
5183 default:
5184 return x;
5185 }
5186
0f13a422
ILT		 5187 /* We can optimize some special cases of ZERO_EXTEND. */
5188 if (GET_CODE (x) == ZERO_EXTEND)
5189 {
5190 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5191 know that the last value didn't have any inappropriate bits
5192 set. */
5193 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5194 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5195 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5196 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5197 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5198 return XEXP (XEXP (x, 0), 0);
5199
5200 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5201 if (GET_CODE (XEXP (x, 0)) == SUBREG
5202 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5203 && subreg_lowpart_p (XEXP (x, 0))
5204 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5205 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5206 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5207 return SUBREG_REG (XEXP (x, 0));
5208
5209 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5210 is a comparison and STORE_FLAG_VALUE permits. This is like
5211 the first case, but it works even when GET_MODE (x) is larger
5212 than HOST_WIDE_INT. */
5213 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5214 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5215 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5216 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5217 <= HOST_BITS_PER_WIDE_INT)
5218 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5219 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5220 return XEXP (XEXP (x, 0), 0);
5221
5222 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5223 if (GET_CODE (XEXP (x, 0)) == SUBREG
5224 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5225 && subreg_lowpart_p (XEXP (x, 0))
5226 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5227 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5228 <= HOST_BITS_PER_WIDE_INT)
5229 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5230 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5231 return SUBREG_REG (XEXP (x, 0));
5232
5233 /* If sign extension is cheaper than zero extension, then use it
5234 if we know that no extraneous bits are set, and that the high
5235 bit is not set. */
5236 if (flag_expensive_optimizations
5237 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5238 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5239 & ~ (((unsigned HOST_WIDE_INT)
5240 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5241 >> 1))
5242 == 0))
5243 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5244 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5245 <= HOST_BITS_PER_WIDE_INT)
5246 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5247 & ~ (((unsigned HOST_WIDE_INT)
5248 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5249 >> 1))
5250 == 0))))
5251 {
38a448ca 5252 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
0f13a422
ILT		 5253
5254 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5255 return expand_compound_operation (temp);
5256 }
5257 }
5258
230d793d
RS		 5259 /* If we reach here, we want to return a pair of shifts. The inner
5260 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5261 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5262 logical depending on the value of UNSIGNEDP.
5263
5264 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5265 converted into an AND of a shift.
5266
5267 We must check for the case where the left shift would have a negative
5268 count. This can happen in a case like (x >> 31) & 255 on machines
5269 that can't shift by a constant. On those machines, we would first
5270 combine the shift with the AND to produce a variable-position
5271 extraction. Then the constant of 31 would be substituted in to produce
5272 a such a position. */
5273
5274 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5275 if (modewidth >= pos - len)
5f4f0e22 5276 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
230d793d 5277 GET_MODE (x),
5f4f0e22
CH		 5278 simplify_shift_const (NULL_RTX, ASHIFT,
5279 GET_MODE (x),
230d793d
RS		 5280 XEXP (x, 0),
5281 modewidth - pos - len),
5282 modewidth - len);
5283
5f4f0e22
CH		 5284 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5285 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5286 simplify_shift_const (NULL_RTX, LSHIFTRT,
230d793d
RS		 5287 GET_MODE (x),
5288 XEXP (x, 0), pos),
5f4f0e22 5289 ((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5290 else
5291 /* Any other cases we can't handle. */
5292 return x;
5293
5294
5295 /* If we couldn't do this for some reason, return the original
5296 expression. */
5297 if (GET_CODE (tem) == CLOBBER)
5298 return x;
5299
5300 return tem;
5301}
5302\f
5303/* X is a SET which contains an assignment of one object into
5304 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5305 or certain SUBREGS). If possible, convert it into a series of
5306 logical operations.
5307
5308 We half-heartedly support variable positions, but do not at all
5309 support variable lengths. */
5310
5311static rtx
5312expand_field_assignment (x)
5313 rtx x;
5314{
5315 rtx inner;
0f41302f 5316 rtx pos; /* Always counts from low bit. */
230d793d
RS		 5317 int len;
5318 rtx mask;
5319 enum machine_mode compute_mode;
5320
5321 /* Loop until we find something we can't simplify. */
5322 while (1)
5323 {
5324 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5325 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5326 {
5327 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5328 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4d9cfc7b 5329 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
230d793d
RS		 5330 }
5331 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5332 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5333 {
5334 inner = XEXP (SET_DEST (x), 0);
5335 len = INTVAL (XEXP (SET_DEST (x), 1));
5336 pos = XEXP (SET_DEST (x), 2);
5337
5338 /* If the position is constant and spans the width of INNER,
5339 surround INNER with a USE to indicate this. */
5340 if (GET_CODE (pos) == CONST_INT
5341 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
38a448ca 5342 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
230d793d 5343
f76b9db2
ILT		 5344 if (BITS_BIG_ENDIAN)
5345 {
5346 if (GET_CODE (pos) == CONST_INT)
5347 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5348 - INTVAL (pos));
5349 else if (GET_CODE (pos) == MINUS
5350 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5351 && (INTVAL (XEXP (pos, 1))
5352 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5353 /* If position is ADJUST - X, new position is X. */
5354 pos = XEXP (pos, 0);
5355 else
5356 pos = gen_binary (MINUS, GET_MODE (pos),
5357 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5358 - len),
5359 pos);
5360 }
230d793d
RS		 5361 }
5362
5363 /* A SUBREG between two modes that occupy the same numbers of words
5364 can be done by moving the SUBREG to the source. */
5365 else if (GET_CODE (SET_DEST (x)) == SUBREG
5366 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5367 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5368 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5369 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5370 {
38a448ca
RH		 5371 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5372 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5373 SET_SRC (x)));
230d793d
RS		 5374 continue;
5375 }
5376 else
5377 break;
5378
5379 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5380 inner = SUBREG_REG (inner);
5381
5382 compute_mode = GET_MODE (inner);
5383
5384 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5f4f0e22
CH		 5385 if (len < HOST_BITS_PER_WIDE_INT)
5386 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5387 else
5388 break;
5389
5390 /* Now compute the equivalent expression. Make a copy of INNER
5391 for the SET_DEST in case it is a MEM into which we will substitute;
5392 we don't want shared RTL in that case. */
38a448ca
RH		 5393 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5394 gen_binary (IOR, compute_mode,
5395 gen_binary (AND, compute_mode,
5396 gen_unary (NOT, compute_mode,
5397 compute_mode,
5398 gen_binary (ASHIFT,
5399 compute_mode,
5400 mask, pos)),
5401 inner),
5402 gen_binary (ASHIFT, compute_mode,
5403 gen_binary (AND, compute_mode,
5404 gen_lowpart_for_combine
5405 (compute_mode,
5406 SET_SRC (x)),
5407 mask),
5408 pos)));
230d793d
RS		 5409 }
5410
5411 return x;
5412}
5413\f
8999a12e
RK		 5414/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5415 it is an RTX that represents a variable starting position; otherwise,
5416 POS is the (constant) starting bit position (counted from the LSB).
230d793d
RS		 5417
5418 INNER may be a USE. This will occur when we started with a bitfield
5419 that went outside the boundary of the object in memory, which is
5420 allowed on most machines. To isolate this case, we produce a USE
5421 whose mode is wide enough and surround the MEM with it. The only
5422 code that understands the USE is this routine. If it is not removed,
5423 it will cause the resulting insn not to match.
5424
5425 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5426 signed reference.
5427
5428 IN_DEST is non-zero if this is a reference in the destination of a
5429 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5430 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5431 be used.
5432
5433 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5434 ZERO_EXTRACT should be built even for bits starting at bit 0.
5435
76184def
DE		 5436 MODE is the desired mode of the result (if IN_DEST == 0).
5437
5438 The result is an RTX for the extraction or NULL_RTX if the target
5439 can't handle it. */
230d793d
RS		 5440
5441static rtx
5442make_extraction (mode, inner, pos, pos_rtx, len,
5443 unsignedp, in_dest, in_compare)
5444 enum machine_mode mode;
5445 rtx inner;
5446 int pos;
5447 rtx pos_rtx;
5448 int len;
5449 int unsignedp;
5450 int in_dest, in_compare;
5451{
94b4b17a
RS		 5452 /* This mode describes the size of the storage area
5453 to fetch the overall value from. Within that, we
5454 ignore the POS lowest bits, etc. */
230d793d
RS		 5455 enum machine_mode is_mode = GET_MODE (inner);
5456 enum machine_mode inner_mode;
d7cd794f
RK		 5457 enum machine_mode wanted_inner_mode = byte_mode;
5458 enum machine_mode wanted_inner_reg_mode = word_mode;
230d793d
RS		 5459 enum machine_mode pos_mode = word_mode;
5460 enum machine_mode extraction_mode = word_mode;
5461 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5462 int spans_byte = 0;
5463 rtx new = 0;
8999a12e 5464 rtx orig_pos_rtx = pos_rtx;
6139ff20 5465 int orig_pos;
230d793d
RS		 5466
5467 /* Get some information about INNER and get the innermost object. */
5468 if (GET_CODE (inner) == USE)
94b4b17a 5469 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
230d793d
RS		 5470 /* We don't need to adjust the position because we set up the USE
5471 to pretend that it was a full-word object. */
5472 spans_byte = 1, inner = XEXP (inner, 0);
5473 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
94b4b17a
RS		 5474 {
5475 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5476 consider just the QI as the memory to extract from.
5477 The subreg adds or removes high bits; its mode is
5478 irrelevant to the meaning of this extraction,
5479 since POS and LEN count from the lsb. */
5480 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5481 is_mode = GET_MODE (SUBREG_REG (inner));
5482 inner = SUBREG_REG (inner);
5483 }
230d793d
RS		 5484
5485 inner_mode = GET_MODE (inner);
5486
5487 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
8999a12e 5488 pos = INTVAL (pos_rtx), pos_rtx = 0;
230d793d
RS		 5489
5490 /* See if this can be done without an extraction. We never can if the
5491 width of the field is not the same as that of some integer mode. For
5492 registers, we can only avoid the extraction if the position is at the
5493 low-order bit and this is either not in the destination or we have the
5494 appropriate STRICT_LOW_PART operation available.
5495
5496 For MEM, we can avoid an extract if the field starts on an appropriate
5497 boundary and we can change the mode of the memory reference. However,
5498 we cannot directly access the MEM if we have a USE and the underlying
5499 MEM is not TMODE. This combination means that MEM was being used in a
5500 context where bits outside its mode were being referenced; that is only
5501 valid in bit-field insns. */
5502
5503 if (tmode != BLKmode
5504 && ! (spans_byte && inner_mode != tmode)
4d9cfc7b
RK		 5505 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5506 && GET_CODE (inner) != MEM
230d793d 5507 && (! in_dest
df62f951
RK		 5508 || (GET_CODE (inner) == REG
5509 && (movstrict_optab->handlers[(int) tmode].insn_code
5510 != CODE_FOR_nothing))))
8999a12e 5511 || (GET_CODE (inner) == MEM && pos_rtx == 0
dfbe1b2f
RK		 5512 && (pos
5513 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5514 : BITS_PER_UNIT)) == 0
230d793d
RS		 5515 /* We can't do this if we are widening INNER_MODE (it
5516 may not be aligned, for one thing). */
5517 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5518 && (inner_mode == tmode
5519 || (! mode_dependent_address_p (XEXP (inner, 0))
5520 && ! MEM_VOLATILE_P (inner))))))
5521 {
230d793d
RS		 5522 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5523 field. If the original and current mode are the same, we need not
5524 adjust the offset. Otherwise, we do if bytes big endian.
5525
4d9cfc7b
RK		 5526 If INNER is not a MEM, get a piece consisting of just the field
5527 of interest (in this case POS % BITS_PER_WORD must be 0). */
230d793d
RS		 5528
5529 if (GET_CODE (inner) == MEM)
5530 {
94b4b17a
RS		 5531 int offset;
5532 /* POS counts from lsb, but make OFFSET count in memory order. */
5533 if (BYTES_BIG_ENDIAN)
5534 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5535 else
5536 offset = pos / BITS_PER_UNIT;
230d793d 5537
38a448ca 5538 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5539 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5540 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5541 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5542 }
df62f951 5543 else if (GET_CODE (inner) == REG)
c0d3ac4d
RK		 5544 {
5545 /* We can't call gen_lowpart_for_combine here since we always want
5546 a SUBREG and it would sometimes return a new hard register. */
5547 if (tmode != inner_mode)
38a448ca
RH		 5548 new = gen_rtx_SUBREG (tmode, inner,
5549 (WORDS_BIG_ENDIAN
5550 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5551 ? (((GET_MODE_SIZE (inner_mode)
5552 - GET_MODE_SIZE (tmode))
5553 / UNITS_PER_WORD)
5554 - pos / BITS_PER_WORD)
5555 : pos / BITS_PER_WORD));
c0d3ac4d
RK		 5556 else
5557 new = inner;
5558 }
230d793d 5559 else
6139ff20
RK		 5560 new = force_to_mode (inner, tmode,
5561 len >= HOST_BITS_PER_WIDE_INT
5562 ? GET_MODE_MASK (tmode)
5563 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 5564 NULL_RTX, 0);
230d793d
RS		 5565
5566 /* If this extraction is going into the destination of a SET,
5567 make a STRICT_LOW_PART unless we made a MEM. */
5568
5569 if (in_dest)
5570 return (GET_CODE (new) == MEM ? new
77fa0940 5571 : (GET_CODE (new) != SUBREG
38a448ca 5572 ? gen_rtx_CLOBBER (tmode, const0_rtx)
77fa0940 5573 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
230d793d
RS		 5574
5575 /* Otherwise, sign- or zero-extend unless we already are in the
5576 proper mode. */
5577
5578 return (mode == tmode ? new
5579 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5580 mode, new));
5581 }
5582
cc471082
RS		 5583 /* Unless this is a COMPARE or we have a funny memory reference,
5584 don't do anything with zero-extending field extracts starting at
5585 the low-order bit since they are simple AND operations. */
8999a12e
RK		 5586 if (pos_rtx == 0 && pos == 0 && ! in_dest
5587 && ! in_compare && ! spans_byte && unsignedp)
230d793d
RS		 5588 return 0;
5589
e7373556
RK		 5590 /* Unless we are allowed to span bytes, reject this if we would be
5591 spanning bytes or if the position is not a constant and the length
5592 is not 1. In all other cases, we would only be going outside
5593 out object in cases when an original shift would have been
5594 undefined. */
5595 if (! spans_byte
5596 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5597 || (pos_rtx != 0 && len != 1)))
5598 return 0;
5599
d7cd794f 5600 /* Get the mode to use should INNER not be a MEM, the mode for the position,
230d793d
RS		 5601 and the mode for the result. */
5602#ifdef HAVE_insv
5603 if (in_dest)
5604 {
d7cd794f 5605 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
230d793d
RS		 5606 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5607 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5608 }
5609#endif
5610
5611#ifdef HAVE_extzv
5612 if (! in_dest && unsignedp)
5613 {
d7cd794f 5614 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
230d793d
RS		 5615 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5616 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5617 }
5618#endif
5619
5620#ifdef HAVE_extv
5621 if (! in_dest && ! unsignedp)
5622 {
d7cd794f 5623 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
230d793d
RS		 5624 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5625 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5626 }
5627#endif
5628
5629 /* Never narrow an object, since that might not be safe. */
5630
5631 if (mode != VOIDmode
5632 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5633 extraction_mode = mode;
5634
5635 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5636 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5637 pos_mode = GET_MODE (pos_rtx);
5638
d7cd794f
RK		 5639 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5640 if we have to change the mode of memory and cannot, the desired mode is
5641 EXTRACTION_MODE. */
5642 if (GET_CODE (inner) != MEM)
5643 wanted_inner_mode = wanted_inner_reg_mode;
5644 else if (inner_mode != wanted_inner_mode
5645 && (mode_dependent_address_p (XEXP (inner, 0))
5646 || MEM_VOLATILE_P (inner)))
5647 wanted_inner_mode = extraction_mode;
230d793d 5648
6139ff20
RK		 5649 orig_pos = pos;
5650
f76b9db2
ILT		 5651 if (BITS_BIG_ENDIAN)
5652 {
cf54c2cd
DE		 5653 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5654 BITS_BIG_ENDIAN style. If position is constant, compute new
5655 position. Otherwise, build subtraction.
5656 Note that POS is relative to the mode of the original argument.
5657 If it's a MEM we need to recompute POS relative to that.
5658 However, if we're extracting from (or inserting into) a register,
5659 we want to recompute POS relative to wanted_inner_mode. */
5660 int width = (GET_CODE (inner) == MEM
5661 ? GET_MODE_BITSIZE (is_mode)
5662 : GET_MODE_BITSIZE (wanted_inner_mode));
5663
f76b9db2 5664 if (pos_rtx == 0)
cf54c2cd 5665 pos = width - len - pos;
f76b9db2
ILT		 5666 else
5667 pos_rtx
5668 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
cf54c2cd
DE		 5669 GEN_INT (width - len), pos_rtx);
5670 /* POS may be less than 0 now, but we check for that below.
5671 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
f76b9db2 5672 }
230d793d
RS		 5673
5674 /* If INNER has a wider mode, make it smaller. If this is a constant
5675 extract, try to adjust the byte to point to the byte containing
5676 the value. */
d7cd794f
RK		 5677 if (wanted_inner_mode != VOIDmode
5678 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
230d793d 5679 && ((GET_CODE (inner) == MEM
d7cd794f 5680 && (inner_mode == wanted_inner_mode
230d793d
RS		 5681 || (! mode_dependent_address_p (XEXP (inner, 0))
5682 && ! MEM_VOLATILE_P (inner))))))
5683 {
5684 int offset = 0;
5685
5686 /* The computations below will be correct if the machine is big
5687 endian in both bits and bytes or little endian in bits and bytes.
5688 If it is mixed, we must adjust. */
5689
230d793d 5690 /* If bytes are big endian and we had a paradoxical SUBREG, we must
0f41302f 5691 adjust OFFSET to compensate. */
f76b9db2
ILT		 5692 if (BYTES_BIG_ENDIAN
5693 && ! spans_byte
230d793d
RS		 5694 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5695 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
230d793d
RS		 5696
5697 /* If this is a constant position, we can move to the desired byte. */
8999a12e 5698 if (pos_rtx == 0)
230d793d
RS		 5699 {
5700 offset += pos / BITS_PER_UNIT;
d7cd794f 5701 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
230d793d
RS		 5702 }
5703
f76b9db2
ILT		 5704 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5705 && ! spans_byte
d7cd794f 5706 && is_mode != wanted_inner_mode)
c6b3f1f2 5707 offset = (GET_MODE_SIZE (is_mode)
d7cd794f 5708 - GET_MODE_SIZE (wanted_inner_mode) - offset);
c6b3f1f2 5709
d7cd794f 5710 if (offset != 0 || inner_mode != wanted_inner_mode)
230d793d 5711 {
38a448ca
RH		 5712 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5713 plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5714 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5715 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5716 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5717 inner = newmem;
5718 }
5719 }
5720
9e74dc41
RK		 5721 /* If INNER is not memory, we can always get it into the proper mode. If we
5722 are changing its mode, POS must be a constant and smaller than the size
5723 of the new mode. */
230d793d 5724 else if (GET_CODE (inner) != MEM)
9e74dc41
RK		 5725 {
5726 if (GET_MODE (inner) != wanted_inner_mode
5727 && (pos_rtx != 0
5728 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5729 return 0;
5730
5731 inner = force_to_mode (inner, wanted_inner_mode,
5732 pos_rtx
5733 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5734 ? GET_MODE_MASK (wanted_inner_mode)
5735 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5736 NULL_RTX, 0);
5737 }
230d793d
RS		 5738
5739 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5740 have to zero extend. Otherwise, we can just use a SUBREG. */
8999a12e 5741 if (pos_rtx != 0
230d793d
RS		 5742 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5743 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
8999a12e 5744 else if (pos_rtx != 0
230d793d
RS		 5745 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5746 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5747
8999a12e
RK		 5748 /* Make POS_RTX unless we already have it and it is correct. If we don't
5749 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
0f41302f 5750 be a CONST_INT. */
8999a12e
RK		 5751 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5752 pos_rtx = orig_pos_rtx;
5753
5754 else if (pos_rtx == 0)
5f4f0e22 5755 pos_rtx = GEN_INT (pos);
230d793d
RS		 5756
5757 /* Make the required operation. See if we can use existing rtx. */
5758 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5f4f0e22 5759 extraction_mode, inner, GEN_INT (len), pos_rtx);
230d793d
RS		 5760 if (! in_dest)
5761 new = gen_lowpart_for_combine (mode, new);
5762
5763 return new;
5764}
5765\f
71923da7
RK		 5766/* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5767 with any other operations in X. Return X without that shift if so. */
5768
5769static rtx
5770extract_left_shift (x, count)
5771 rtx x;
5772 int count;
5773{
5774 enum rtx_code code = GET_CODE (x);
5775 enum machine_mode mode = GET_MODE (x);
5776 rtx tem;
5777
5778 switch (code)
5779 {
5780 case ASHIFT:
5781 /* This is the shift itself. If it is wide enough, we will return
5782 either the value being shifted if the shift count is equal to
5783 COUNT or a shift for the difference. */
5784 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5785 && INTVAL (XEXP (x, 1)) >= count)
5786 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5787 INTVAL (XEXP (x, 1)) - count);
5788 break;
5789
5790 case NEG: case NOT:
5791 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
0c1c8ea6 5792 return gen_unary (code, mode, mode, tem);
71923da7
RK		 5793
5794 break;
5795
5796 case PLUS: case IOR: case XOR: case AND:
5797 /* If we can safely shift this constant and we find the inner shift,
5798 make a new operation. */
5799 if (GET_CODE (XEXP (x,1)) == CONST_INT
b729186a 5800 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
71923da7
RK		 5801 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5802 return gen_binary (code, mode, tem,
5803 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5804
5805 break;
e9a25f70
JL		 5806
5807 default:
5808 break;
71923da7
RK		 5809 }
5810
5811 return 0;
5812}
5813\f
230d793d
RS		 5814/* Look at the expression rooted at X. Look for expressions
5815 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5816 Form these expressions.
5817
5818 Return the new rtx, usually just X.
5819
5820 Also, for machines like the Vax that don't have logical shift insns,
5821 try to convert logical to arithmetic shift operations in cases where
5822 they are equivalent. This undoes the canonicalizations to logical
5823 shifts done elsewhere.
5824
5825 We try, as much as possible, to re-use rtl expressions to save memory.
5826
5827 IN_CODE says what kind of expression we are processing. Normally, it is
42495ca0
RK		 5828 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5829 being kludges), it is MEM. When processing the arguments of a comparison
230d793d
RS		 5830 or a COMPARE against zero, it is COMPARE. */
5831
5832static rtx
5833make_compound_operation (x, in_code)
5834 rtx x;
5835 enum rtx_code in_code;
5836{
5837 enum rtx_code code = GET_CODE (x);
5838 enum machine_mode mode = GET_MODE (x);
5839 int mode_width = GET_MODE_BITSIZE (mode);
71923da7 5840 rtx rhs, lhs;
230d793d 5841 enum rtx_code next_code;
f24ad0e4 5842 int i;
230d793d 5843 rtx new = 0;
280f58ba 5844 rtx tem;
230d793d
RS		 5845 char *fmt;
5846
5847 /* Select the code to be used in recursive calls. Once we are inside an
5848 address, we stay there. If we have a comparison, set to COMPARE,
5849 but once inside, go back to our default of SET. */
5850
42495ca0 5851 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
230d793d
RS		 5852 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5853 && XEXP (x, 1) == const0_rtx) ? COMPARE
5854 : in_code == COMPARE ? SET : in_code);
5855
5856 /* Process depending on the code of this operation. If NEW is set
5857 non-zero, it will be returned. */
5858
5859 switch (code)
5860 {
5861 case ASHIFT:
230d793d
RS		 5862 /* Convert shifts by constants into multiplications if inside
5863 an address. */
5864 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 5865 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
230d793d 5866 && INTVAL (XEXP (x, 1)) >= 0)
280f58ba
RK		 5867 {
5868 new = make_compound_operation (XEXP (x, 0), next_code);
5869 new = gen_rtx_combine (MULT, mode, new,
5870 GEN_INT ((HOST_WIDE_INT) 1
5871 << INTVAL (XEXP (x, 1))));
5872 }
230d793d
RS		 5873 break;
5874
5875 case AND:
5876 /* If the second operand is not a constant, we can't do anything
5877 with it. */
5878 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5879 break;
5880
5881 /* If the constant is a power of two minus one and the first operand
5882 is a logical right shift, make an extraction. */
5883 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5884 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5885 {
5886 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5887 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5888 0, in_code == COMPARE);
5889 }
dfbe1b2f 5890
230d793d
RS		 5891 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5892 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5893 && subreg_lowpart_p (XEXP (x, 0))
5894 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5895 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5896 {
5897 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5898 next_code);
2f99f437 5899 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
280f58ba
RK		 5900 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5901 0, in_code == COMPARE);
5902 }
45620ed4 5903 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
c2f9f64e
JW		 5904 else if ((GET_CODE (XEXP (x, 0)) == XOR
5905 || GET_CODE (XEXP (x, 0)) == IOR)
5906 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5907 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5908 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5909 {
5910 /* Apply the distributive law, and then try to make extractions. */
5911 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
38a448ca
RH		 5912 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5913 XEXP (x, 1)),
5914 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5915 XEXP (x, 1)));
c2f9f64e
JW		 5916 new = make_compound_operation (new, in_code);
5917 }
a7c99304
RK		 5918
5919 /* If we are have (and (rotate X C) M) and C is larger than the number
5920 of bits in M, this is an extraction. */
5921
5922 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5923 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5924 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5925 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
280f58ba
RK		 5926 {
5927 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5928 new = make_extraction (mode, new,
5929 (GET_MODE_BITSIZE (mode)
5930 - INTVAL (XEXP (XEXP (x, 0), 1))),
5931 NULL_RTX, i, 1, 0, in_code == COMPARE);
5932 }
a7c99304
RK		 5933
5934 /* On machines without logical shifts, if the operand of the AND is
230d793d
RS		 5935 a logical shift and our mask turns off all the propagated sign
5936 bits, we can replace the logical shift with an arithmetic shift. */
d0ab8cd3
RK		 5937 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5938 && (lshr_optab->handlers[(int) mode].insn_code
5939 == CODE_FOR_nothing)
230d793d
RS		 5940 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5941 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5942 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5f4f0e22
CH		 5943 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5944 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 5945 {
5f4f0e22 5946 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 5947
5948 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5949 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5950 SUBST (XEXP (x, 0),
280f58ba
RK		 5951 gen_rtx_combine (ASHIFTRT, mode,
5952 make_compound_operation (XEXP (XEXP (x, 0), 0),
5953 next_code),
230d793d
RS		 5954 XEXP (XEXP (x, 0), 1)));
5955 }
5956
5957 /* If the constant is one less than a power of two, this might be
5958 representable by an extraction even if no shift is present.
5959 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5960 we are in a COMPARE. */
5961 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5962 new = make_extraction (mode,
5963 make_compound_operation (XEXP (x, 0),
5964 next_code),
5965 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
230d793d
RS		 5966
5967 /* If we are in a comparison and this is an AND with a power of two,
5968 convert this into the appropriate bit extract. */
5969 else if (in_code == COMPARE
5970 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
280f58ba
RK		 5971 new = make_extraction (mode,
5972 make_compound_operation (XEXP (x, 0),
5973 next_code),
5974 i, NULL_RTX, 1, 1, 0, 1);
230d793d
RS		 5975
5976 break;
5977
5978 case LSHIFTRT:
5979 /* If the sign bit is known to be zero, replace this with an
5980 arithmetic shift. */
d0ab8cd3
RK		 5981 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5982 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5f4f0e22 5983 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 5984 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
230d793d 5985 {
280f58ba
RK		 5986 new = gen_rtx_combine (ASHIFTRT, mode,
5987 make_compound_operation (XEXP (x, 0),
5988 next_code),
5989 XEXP (x, 1));
230d793d
RS		 5990 break;
5991 }
5992
0f41302f 5993 /* ... fall through ... */
230d793d
RS		 5994
5995 case ASHIFTRT:
71923da7
RK		 5996 lhs = XEXP (x, 0);
5997 rhs = XEXP (x, 1);
5998
230d793d
RS		 5999 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6000 this is a SIGN_EXTRACT. */
71923da7
RK		 6001 if (GET_CODE (rhs) == CONST_INT
6002 && GET_CODE (lhs) == ASHIFT
6003 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6004 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
280f58ba 6005 {
71923da7 6006 new = make_compound_operation (XEXP (lhs, 0), next_code);
280f58ba 6007 new = make_extraction (mode, new,
71923da7
RK		 6008 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6009 NULL_RTX, mode_width - INTVAL (rhs),
d0ab8cd3
RK		 6010 code == LSHIFTRT, 0, in_code == COMPARE);
6011 }
6012
71923da7
RK		 6013 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6014 If so, try to merge the shifts into a SIGN_EXTEND. We could
6015 also do this for some cases of SIGN_EXTRACT, but it doesn't
6016 seem worth the effort; the case checked for occurs on Alpha. */
6017
6018 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6019 && ! (GET_CODE (lhs) == SUBREG
6020 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6021 && GET_CODE (rhs) == CONST_INT
6022 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6023 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6024 new = make_extraction (mode, make_compound_operation (new, next_code),
6025 0, NULL_RTX, mode_width - INTVAL (rhs),
6026 code == LSHIFTRT, 0, in_code == COMPARE);
6027
230d793d 6028 break;
280f58ba
RK		 6029
6030 case SUBREG:
6031 /* Call ourselves recursively on the inner expression. If we are
6032 narrowing the object and it has a different RTL code from
6033 what it originally did, do this SUBREG as a force_to_mode. */
6034
0a5cbff6 6035 tem = make_compound_operation (SUBREG_REG (x), in_code);
280f58ba
RK		 6036 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6037 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6038 && subreg_lowpart_p (x))
0a5cbff6
RK		 6039 {
6040 rtx newer = force_to_mode (tem, mode,
e3d616e3 6041 GET_MODE_MASK (mode), NULL_RTX, 0);
0a5cbff6
RK		 6042
6043 /* If we have something other than a SUBREG, we might have
6044 done an expansion, so rerun outselves. */
6045 if (GET_CODE (newer) != SUBREG)
6046 newer = make_compound_operation (newer, in_code);
6047
6048 return newer;
6049 }
6f28d3e9
RH		 6050
6051 /* If this is a paradoxical subreg, and the new code is a sign or
6052 zero extension, omit the subreg and widen the extension. If it
6053 is a regular subreg, we can still get rid of the subreg by not
6054 widening so much, or in fact removing the extension entirely. */
6055 if ((GET_CODE (tem) == SIGN_EXTEND
6056 || GET_CODE (tem) == ZERO_EXTEND)
6057 && subreg_lowpart_p (x))
6058 {
6059 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6060 || (GET_MODE_SIZE (mode) >
6061 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6062 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6063 else
6064 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6065 return tem;
6066 }
e9a25f70
JL		 6067 break;
6068
6069 default:
6070 break;
230d793d
RS		 6071 }
6072
6073 if (new)
6074 {
df62f951 6075 x = gen_lowpart_for_combine (mode, new);
230d793d
RS		 6076 code = GET_CODE (x);
6077 }
6078
6079 /* Now recursively process each operand of this operation. */
6080 fmt = GET_RTX_FORMAT (code);
6081 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6082 if (fmt[i] == 'e')
6083 {
6084 new = make_compound_operation (XEXP (x, i), next_code);
6085 SUBST (XEXP (x, i), new);
6086 }
6087
6088 return x;
6089}
6090\f
6091/* Given M see if it is a value that would select a field of bits
6092 within an item, but not the entire word. Return -1 if not.
6093 Otherwise, return the starting position of the field, where 0 is the
6094 low-order bit.
6095
6096 *PLEN is set to the length of the field. */
6097
6098static int
6099get_pos_from_mask (m, plen)
5f4f0e22 6100 unsigned HOST_WIDE_INT m;
230d793d
RS		 6101 int *plen;
6102{
6103 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6104 int pos = exact_log2 (m & - m);
6105
6106 if (pos < 0)
6107 return -1;
6108
6109 /* Now shift off the low-order zero bits and see if we have a power of
6110 two minus 1. */
6111 *plen = exact_log2 ((m >> pos) + 1);
6112
6113 if (*plen <= 0)
6114 return -1;
6115
6116 return pos;
6117}
6118\f
6139ff20
RK		 6119/* See if X can be simplified knowing that we will only refer to it in
6120 MODE and will only refer to those bits that are nonzero in MASK.
6121 If other bits are being computed or if masking operations are done
6122 that select a superset of the bits in MASK, they can sometimes be
6123 ignored.
6124
6125 Return a possibly simplified expression, but always convert X to
6126 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
dfbe1b2f
RK		 6127
6128 Also, if REG is non-zero and X is a register equal in value to REG,
e3d616e3
RK		 6129 replace X with REG.
6130
6131 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6132 are all off in X. This is used when X will be complemented, by either
180b8e4b 6133 NOT, NEG, or XOR. */
dfbe1b2f
RK		 6134
6135static rtx
e3d616e3 6136force_to_mode (x, mode, mask, reg, just_select)
dfbe1b2f
RK		 6137 rtx x;
6138 enum machine_mode mode;
6139ff20 6139 unsigned HOST_WIDE_INT mask;
dfbe1b2f 6140 rtx reg;
e3d616e3 6141 int just_select;
dfbe1b2f
RK		 6142{
6143 enum rtx_code code = GET_CODE (x);
180b8e4b 6144 int next_select = just_select || code == XOR || code == NOT || code == NEG;
ef026f91
RS		 6145 enum machine_mode op_mode;
6146 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6139ff20
RK		 6147 rtx op0, op1, temp;
6148
132d2040
RK		 6149 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6150 code below will do the wrong thing since the mode of such an
be3d27d6
CI		 6151 expression is VOIDmode.
6152
6153 Also do nothing if X is a CLOBBER; this can happen if X was
6154 the return value from a call to gen_lowpart_for_combine. */
6155 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
246e00f2
RK		 6156 return x;
6157
6139ff20
RK		 6158 /* We want to perform the operation is its present mode unless we know
6159 that the operation is valid in MODE, in which case we do the operation
6160 in MODE. */
1c75dfa4
RK		 6161 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6162 && code_to_optab[(int) code] != 0
ef026f91
RS		 6163 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6164 != CODE_FOR_nothing))
6165 ? mode : GET_MODE (x));
e3d616e3 6166
aa988991
RS		 6167 /* It is not valid to do a right-shift in a narrower mode
6168 than the one it came in with. */
6169 if ((code == LSHIFTRT || code == ASHIFTRT)
6170 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6171 op_mode = GET_MODE (x);
ef026f91
RS		 6172
6173 /* Truncate MASK to fit OP_MODE. */
6174 if (op_mode)
6175 mask &= GET_MODE_MASK (op_mode);
6139ff20
RK		 6176
6177 /* When we have an arithmetic operation, or a shift whose count we
6178 do not know, we need to assume that all bit the up to the highest-order
6179 bit in MASK will be needed. This is how we form such a mask. */
ef026f91
RS		 6180 if (op_mode)
6181 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6182 ? GET_MODE_MASK (op_mode)
6183 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6184 else
6185 fuller_mask = ~ (HOST_WIDE_INT) 0;
6186
6187 /* Determine what bits of X are guaranteed to be (non)zero. */
6188 nonzero = nonzero_bits (x, mode);
6139ff20
RK		 6189
6190 /* If none of the bits in X are needed, return a zero. */
e3d616e3 6191 if (! just_select && (nonzero & mask) == 0)
6139ff20 6192 return const0_rtx;
dfbe1b2f 6193
6139ff20
RK		 6194 /* If X is a CONST_INT, return a new one. Do this here since the
6195 test below will fail. */
6196 if (GET_CODE (x) == CONST_INT)
ceb7983c
RK		 6197 {
6198 HOST_WIDE_INT cval = INTVAL (x) & mask;
6199 int width = GET_MODE_BITSIZE (mode);
6200
6201 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6202 number, sign extend it. */
6203 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6204 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6205 cval |= (HOST_WIDE_INT) -1 << width;
6206
6207 return GEN_INT (cval);
6208 }
dfbe1b2f 6209
180b8e4b
RK		 6210 /* If X is narrower than MODE and we want all the bits in X's mode, just
6211 get X in the proper mode. */
6212 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6213 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
dfbe1b2f
RK		 6214 return gen_lowpart_for_combine (mode, x);
6215
71923da7
RK		 6216 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6217 MASK are already known to be zero in X, we need not do anything. */
6218 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6139ff20
RK		 6219 return x;
6220
dfbe1b2f
RK		 6221 switch (code)
6222 {
6139ff20
RK		 6223 case CLOBBER:
6224 /* If X is a (clobber (const_int)), return it since we know we are
0f41302f 6225 generating something that won't match. */
6139ff20
RK		 6226 return x;
6227
6139ff20
RK		 6228 case USE:
6229 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6230 spanned the boundary of the MEM. If we are now masking so it is
6231 within that boundary, we don't need the USE any more. */
f76b9db2
ILT		 6232 if (! BITS_BIG_ENDIAN
6233 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
e3d616e3 6234 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
f76b9db2 6235 break;
6139ff20 6236
dfbe1b2f
RK		 6237 case SIGN_EXTEND:
6238 case ZERO_EXTEND:
6239 case ZERO_EXTRACT:
6240 case SIGN_EXTRACT:
6241 x = expand_compound_operation (x);
6242 if (GET_CODE (x) != code)
e3d616e3 6243 return force_to_mode (x, mode, mask, reg, next_select);
dfbe1b2f
RK		 6244 break;
6245
6246 case REG:
6247 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6248 || rtx_equal_p (reg, get_last_value (x))))
6249 x = reg;
6250 break;
6251
dfbe1b2f 6252 case SUBREG:
6139ff20 6253 if (subreg_lowpart_p (x)
180b8e4b
RK		 6254 /* We can ignore the effect of this SUBREG if it narrows the mode or
6255 if the constant masks to zero all the bits the mode doesn't
6256 have. */
6139ff20
RK		 6257 && ((GET_MODE_SIZE (GET_MODE (x))
6258 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6139ff20
RK		 6259 || (0 == (mask
6260 & GET_MODE_MASK (GET_MODE (x))
180b8e4b 6261 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
e3d616e3 6262 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
dfbe1b2f
RK		 6263 break;
6264
6265 case AND:
6139ff20
RK		 6266 /* If this is an AND with a constant, convert it into an AND
6267 whose constant is the AND of that constant with MASK. If it
6268 remains an AND of MASK, delete it since it is redundant. */
dfbe1b2f 6269
2ca9ae17 6270 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
dfbe1b2f 6271 {
6139ff20
RK		 6272 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6273 mask & INTVAL (XEXP (x, 1)));
dfbe1b2f
RK		 6274
6275 /* If X is still an AND, see if it is an AND with a mask that
71923da7
RK		 6276 is just some low-order bits. If so, and it is MASK, we don't
6277 need it. */
dfbe1b2f
RK		 6278
6279 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6280 && INTVAL (XEXP (x, 1)) == mask)
dfbe1b2f 6281 x = XEXP (x, 0);
d0ab8cd3 6282
71923da7
RK		 6283 /* If it remains an AND, try making another AND with the bits
6284 in the mode mask that aren't in MASK turned on. If the
6285 constant in the AND is wide enough, this might make a
6286 cheaper constant. */
6287
6288 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
2ca9ae17
JW		 6289 && GET_MODE_MASK (GET_MODE (x)) != mask
6290 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
71923da7
RK		 6291 {
6292 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6293 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6294 int width = GET_MODE_BITSIZE (GET_MODE (x));
6295 rtx y;
6296
6297 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6298 number, sign extend it. */
6299 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6300 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6301 cval |= (HOST_WIDE_INT) -1 << width;
6302
6303 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6304 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6305 x = y;
6306 }
6307
d0ab8cd3 6308 break;
dfbe1b2f
RK		 6309 }
6310
6139ff20 6311 goto binop;
dfbe1b2f
RK		 6312
6313 case PLUS:
6139ff20
RK		 6314 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6315 low-order bits (as in an alignment operation) and FOO is already
6316 aligned to that boundary, mask C1 to that boundary as well.
6317 This may eliminate that PLUS and, later, the AND. */
9fa6d012
TG		 6318
6319 {
6320 int width = GET_MODE_BITSIZE (mode);
6321 unsigned HOST_WIDE_INT smask = mask;
6322
6323 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6324 number, sign extend it. */
6325
6326 if (width < HOST_BITS_PER_WIDE_INT
6327 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6328 smask |= (HOST_WIDE_INT) -1 << width;
6329
6330 if (GET_CODE (XEXP (x, 1)) == CONST_INT
0e9ff885
DM		 6331 && exact_log2 (- smask) >= 0)
6332 {
6333#ifdef STACK_BIAS
6334 if (STACK_BIAS
6335 && (XEXP (x, 0) == stack_pointer_rtx
6336 || XEXP (x, 0) == frame_pointer_rtx))
6337 {
6338 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6339 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6340
6341 sp_mask &= ~ (sp_alignment - 1);
6342 if ((sp_mask & ~ mask) == 0
6343 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6344 return force_to_mode (plus_constant (XEXP (x, 0),
6345 ((INTVAL (XEXP (x, 1)) -
6346 STACK_BIAS) & mask)
6347 + STACK_BIAS),
6348 mode, mask, reg, next_select);
6349 }
6350#endif
6351 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6352 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6353 return force_to_mode (plus_constant (XEXP (x, 0),
6354 INTVAL (XEXP (x, 1)) & mask),
6355 mode, mask, reg, next_select);
6356 }
9fa6d012 6357 }
6139ff20 6358
0f41302f 6359 /* ... fall through ... */
6139ff20 6360
dfbe1b2f
RK		 6361 case MINUS:
6362 case MULT:
6139ff20
RK		 6363 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6364 most significant bit in MASK since carries from those bits will
6365 affect the bits we are interested in. */
6366 mask = fuller_mask;
6367 goto binop;
6368
dfbe1b2f
RK		 6369 case IOR:
6370 case XOR:
6139ff20
RK		 6371 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6372 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6373 operation which may be a bitfield extraction. Ensure that the
6374 constant we form is not wider than the mode of X. */
6375
6376 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6377 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6378 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6379 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6380 && GET_CODE (XEXP (x, 1)) == CONST_INT
6381 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6382 + floor_log2 (INTVAL (XEXP (x, 1))))
6383 < GET_MODE_BITSIZE (GET_MODE (x)))
6384 && (INTVAL (XEXP (x, 1))
01c82bbb 6385 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6139ff20
RK		 6386 {
6387 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6388 << INTVAL (XEXP (XEXP (x, 0), 1)));
6389 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6390 XEXP (XEXP (x, 0), 0), temp);
d4d2b13f
RK		 6391 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6392 XEXP (XEXP (x, 0), 1));
e3d616e3 6393 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6394 }
6395
6396 binop:
dfbe1b2f 6397 /* For most binary operations, just propagate into the operation and
6139ff20
RK		 6398 change the mode if we have an operation of that mode. */
6399
e3d616e3
RK		 6400 op0 = gen_lowpart_for_combine (op_mode,
6401 force_to_mode (XEXP (x, 0), mode, mask,
6402 reg, next_select));
6403 op1 = gen_lowpart_for_combine (op_mode,
6404 force_to_mode (XEXP (x, 1), mode, mask,
6405 reg, next_select));
6139ff20 6406
2dd484ed
RK		 6407 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6408 MASK since OP1 might have been sign-extended but we never want
6409 to turn on extra bits, since combine might have previously relied
6410 on them being off. */
6411 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6412 && (INTVAL (op1) & mask) != 0)
6413 op1 = GEN_INT (INTVAL (op1) & mask);
6414
6139ff20
RK		 6415 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6416 x = gen_binary (code, op_mode, op0, op1);
d0ab8cd3 6417 break;
dfbe1b2f
RK		 6418
6419 case ASHIFT:
dfbe1b2f 6420 /* For left shifts, do the same, but just for the first operand.
f6785026
RK		 6421 However, we cannot do anything with shifts where we cannot
6422 guarantee that the counts are smaller than the size of the mode
6423 because such a count will have a different meaning in a
6139ff20 6424 wider mode. */
f6785026
RK		 6425
6426 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6427 && INTVAL (XEXP (x, 1)) >= 0
f6785026
RK		 6428 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6429 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6430 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
adb7a1cb 6431 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
f6785026
RK		 6432 break;
6433
6139ff20
RK		 6434 /* If the shift count is a constant and we can do arithmetic in
6435 the mode of the shift, refine which bits we need. Otherwise, use the
6436 conservative form of the mask. */
6437 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6438 && INTVAL (XEXP (x, 1)) >= 0
6439 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6440 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6441 mask >>= INTVAL (XEXP (x, 1));
6442 else
6443 mask = fuller_mask;
6444
6445 op0 = gen_lowpart_for_combine (op_mode,
6446 force_to_mode (XEXP (x, 0), op_mode,
e3d616e3 6447 mask, reg, next_select));
6139ff20
RK		 6448
6449 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6450 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
d0ab8cd3 6451 break;
dfbe1b2f
RK		 6452
6453 case LSHIFTRT:
1347292b
JW		 6454 /* Here we can only do something if the shift count is a constant,
6455 this shift constant is valid for the host, and we can do arithmetic
6456 in OP_MODE. */
dfbe1b2f
RK		 6457
6458 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1347292b 6459 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6139ff20 6460 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 6461 {
6139ff20
RK		 6462 rtx inner = XEXP (x, 0);
6463
6464 /* Select the mask of the bits we need for the shift operand. */
6465 mask <<= INTVAL (XEXP (x, 1));
d0ab8cd3 6466
6139ff20
RK		 6467 /* We can only change the mode of the shift if we can do arithmetic
6468 in the mode of the shift and MASK is no wider than the width of
6469 OP_MODE. */
6470 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6471 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
d0ab8cd3
RK		 6472 op_mode = GET_MODE (x);
6473
e3d616e3 6474 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6139ff20
RK		 6475
6476 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6477 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
d0ab8cd3 6478 }
6139ff20
RK		 6479
6480 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6481 shift and AND produces only copies of the sign bit (C2 is one less
6482 than a power of two), we can do this with just a shift. */
6483
6484 if (GET_CODE (x) == LSHIFTRT
6485 && GET_CODE (XEXP (x, 1)) == CONST_INT
6486 && ((INTVAL (XEXP (x, 1))
6487 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6488 >= GET_MODE_BITSIZE (GET_MODE (x)))
6489 && exact_log2 (mask + 1) >= 0
6490 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6491 >= exact_log2 (mask + 1)))
6492 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6493 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6494 - exact_log2 (mask + 1)));
d0ab8cd3
RK		 6495 break;
6496
6497 case ASHIFTRT:
6139ff20
RK		 6498 /* If we are just looking for the sign bit, we don't need this shift at
6499 all, even if it has a variable count. */
9bf22b75
RK		 6500 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6501 && (mask == ((HOST_WIDE_INT) 1
6502 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
e3d616e3 6503 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20
RK		 6504
6505 /* If this is a shift by a constant, get a mask that contains those bits
6506 that are not copies of the sign bit. We then have two cases: If
6507 MASK only includes those bits, this can be a logical shift, which may
6508 allow simplifications. If MASK is a single-bit field not within
6509 those bits, we are requesting a copy of the sign bit and hence can
6510 shift the sign bit to the appropriate location. */
6511
6512 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6513 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6514 {
6515 int i = -1;
6516
b69960ac
RK		 6517 /* If the considered data is wider then HOST_WIDE_INT, we can't
6518 represent a mask for all its bits in a single scalar.
6519 But we only care about the lower bits, so calculate these. */
6520
6a11342f 6521 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
b69960ac 6522 {
0f41302f 6523 nonzero = ~ (HOST_WIDE_INT) 0;
b69960ac
RK		 6524
6525 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6526 is the number of bits a full-width mask would have set.
6527 We need only shift if these are fewer than nonzero can
6528 hold. If not, we must keep all bits set in nonzero. */
6529
6530 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6531 < HOST_BITS_PER_WIDE_INT)
6532 nonzero >>= INTVAL (XEXP (x, 1))
6533 + HOST_BITS_PER_WIDE_INT
6534 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6535 }
6536 else
6537 {
6538 nonzero = GET_MODE_MASK (GET_MODE (x));
6539 nonzero >>= INTVAL (XEXP (x, 1));
6540 }
6139ff20
RK		 6541
6542 if ((mask & ~ nonzero) == 0
6543 || (i = exact_log2 (mask)) >= 0)
6544 {
6545 x = simplify_shift_const
6546 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6547 i < 0 ? INTVAL (XEXP (x, 1))
6548 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6549
6550 if (GET_CODE (x) != ASHIFTRT)
e3d616e3 6551 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6552 }
6553 }
6554
6555 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6556 even if the shift count isn't a constant. */
6557 if (mask == 1)
6558 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6559
d0ab8cd3 6560 /* If this is a sign-extension operation that just affects bits
4c002f29
RK		 6561 we don't care about, remove it. Be sure the call above returned
6562 something that is still a shift. */
d0ab8cd3 6563
4c002f29
RK		 6564 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6565 && GET_CODE (XEXP (x, 1)) == CONST_INT
d0ab8cd3 6566 && INTVAL (XEXP (x, 1)) >= 0
6139ff20
RK		 6567 && (INTVAL (XEXP (x, 1))
6568 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
d0ab8cd3
RK		 6569 && GET_CODE (XEXP (x, 0)) == ASHIFT
6570 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6571 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
e3d616e3
RK		 6572 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6573 reg, next_select);
6139ff20 6574
dfbe1b2f
RK		 6575 break;
6576
6139ff20
RK		 6577 case ROTATE:
6578 case ROTATERT:
6579 /* If the shift count is constant and we can do computations
6580 in the mode of X, compute where the bits we care about are.
6581 Otherwise, we can't do anything. Don't change the mode of
6582 the shift or propagate MODE into the shift, though. */
6583 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6584 && INTVAL (XEXP (x, 1)) >= 0)
6585 {
6586 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6587 GET_MODE (x), GEN_INT (mask),
6588 XEXP (x, 1));
7d171a1e 6589 if (temp && GET_CODE(temp) == CONST_INT)
6139ff20
RK		 6590 SUBST (XEXP (x, 0),
6591 force_to_mode (XEXP (x, 0), GET_MODE (x),
e3d616e3 6592 INTVAL (temp), reg, next_select));
6139ff20
RK		 6593 }
6594 break;
6595
dfbe1b2f 6596 case NEG:
180b8e4b
RK		 6597 /* If we just want the low-order bit, the NEG isn't needed since it
6598 won't change the low-order bit. */
6599 if (mask == 1)
6600 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6601
6139ff20
RK		 6602 /* We need any bits less significant than the most significant bit in
6603 MASK since carries from those bits will affect the bits we are
6604 interested in. */
6605 mask = fuller_mask;
6606 goto unop;
6607
dfbe1b2f 6608 case NOT:
6139ff20
RK		 6609 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6610 same as the XOR case above. Ensure that the constant we form is not
6611 wider than the mode of X. */
6612
6613 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6614 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6615 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6616 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6617 < GET_MODE_BITSIZE (GET_MODE (x)))
6618 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6619 {
6620 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6621 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6622 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6623
e3d616e3 6624 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6625 }
6626
f82da7d2
JW		 6627 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6628 use the full mask inside the NOT. */
6629 mask = fuller_mask;
6630
6139ff20 6631 unop:
e3d616e3
RK		 6632 op0 = gen_lowpart_for_combine (op_mode,
6633 force_to_mode (XEXP (x, 0), mode, mask,
6634 reg, next_select));
6139ff20 6635 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
0c1c8ea6 6636 x = gen_unary (code, op_mode, op_mode, op0);
6139ff20
RK		 6637 break;
6638
6639 case NE:
6640 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
3aceff0d 6641 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
1a6ec070 6642 which is equal to STORE_FLAG_VALUE. */
3aceff0d
RK		 6643 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6644 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
1a6ec070 6645 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
e3d616e3 6646 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20 6647
d0ab8cd3
RK		 6648 break;
6649
6650 case IF_THEN_ELSE:
6651 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6652 written in a narrower mode. We play it safe and do not do so. */
6653
6654 SUBST (XEXP (x, 1),
6655 gen_lowpart_for_combine (GET_MODE (x),
6656 force_to_mode (XEXP (x, 1), mode,
e3d616e3 6657 mask, reg, next_select)));
d0ab8cd3
RK		 6658 SUBST (XEXP (x, 2),
6659 gen_lowpart_for_combine (GET_MODE (x),
6660 force_to_mode (XEXP (x, 2), mode,
e3d616e3 6661 mask, reg,next_select)));
d0ab8cd3 6662 break;
e9a25f70
JL		 6663
6664 default:
6665 break;
dfbe1b2f
RK		 6666 }
6667
d0ab8cd3 6668 /* Ensure we return a value of the proper mode. */
dfbe1b2f
RK		 6669 return gen_lowpart_for_combine (mode, x);
6670}
6671\f
abe6e52f
RK		 6672/* Return nonzero if X is an expression that has one of two values depending on
6673 whether some other value is zero or nonzero. In that case, we return the
6674 value that is being tested, *PTRUE is set to the value if the rtx being
6675 returned has a nonzero value, and *PFALSE is set to the other alternative.
6676
6677 If we return zero, we set *PTRUE and *PFALSE to X. */
6678
6679static rtx
6680if_then_else_cond (x, ptrue, pfalse)
6681 rtx x;
6682 rtx *ptrue, *pfalse;
6683{
6684 enum machine_mode mode = GET_MODE (x);
6685 enum rtx_code code = GET_CODE (x);
6686 int size = GET_MODE_BITSIZE (mode);
6687 rtx cond0, cond1, true0, true1, false0, false1;
6688 unsigned HOST_WIDE_INT nz;
6689
6690 /* If this is a unary operation whose operand has one of two values, apply
6691 our opcode to compute those values. */
6692 if (GET_RTX_CLASS (code) == '1'
6693 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6694 {
0c1c8ea6
RK		 6695 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6696 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
abe6e52f
RK		 6697 return cond0;
6698 }
6699
3a19aabc 6700 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
ddd5a7c1 6701 make can't possibly match and would suppress other optimizations. */
3a19aabc
RK		 6702 else if (code == COMPARE)
6703 ;
6704
abe6e52f
RK		 6705 /* If this is a binary operation, see if either side has only one of two
6706 values. If either one does or if both do and they are conditional on
6707 the same value, compute the new true and false values. */
6708 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6709 || GET_RTX_CLASS (code) == '<')
6710 {
6711 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6712 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6713
6714 if ((cond0 != 0 || cond1 != 0)
6715 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6716 {
987e845a
JW		 6717 /* If if_then_else_cond returned zero, then true/false are the
6718 same rtl. We must copy one of them to prevent invalid rtl
6719 sharing. */
6720 if (cond0 == 0)
6721 true0 = copy_rtx (true0);
6722 else if (cond1 == 0)
6723 true1 = copy_rtx (true1);
6724
abe6e52f
RK		 6725 *ptrue = gen_binary (code, mode, true0, true1);
6726 *pfalse = gen_binary (code, mode, false0, false1);
6727 return cond0 ? cond0 : cond1;
6728 }
9210df58 6729
9210df58 6730 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
0802d516
RK		 6731 operands is zero when the other is non-zero, and vice-versa,
6732 and STORE_FLAG_VALUE is 1 or -1. */
9210df58 6733
0802d516
RK		 6734 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6735 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9210df58
RK		 6736 || code == UMAX)
6737 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6738 {
6739 rtx op0 = XEXP (XEXP (x, 0), 1);
6740 rtx op1 = XEXP (XEXP (x, 1), 1);
6741
6742 cond0 = XEXP (XEXP (x, 0), 0);
6743 cond1 = XEXP (XEXP (x, 1), 0);
6744
6745 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6746 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6747 && reversible_comparison_p (cond1)
6748 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6749 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6750 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6751 || ((swap_condition (GET_CODE (cond0))
6752 == reverse_condition (GET_CODE (cond1)))
6753 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6754 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6755 && ! side_effects_p (x))
6756 {
6757 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6758 *pfalse = gen_binary (MULT, mode,
6759 (code == MINUS
0c1c8ea6 6760 ? gen_unary (NEG, mode, mode, op1) : op1),
9210df58
RK		 6761 const_true_rtx);
6762 return cond0;
6763 }
6764 }
6765
6766 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6767 is always zero. */
0802d516
RK		 6768 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6769 && (code == MULT || code == AND || code == UMIN)
9210df58
RK		 6770 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6771 {
6772 cond0 = XEXP (XEXP (x, 0), 0);
6773 cond1 = XEXP (XEXP (x, 1), 0);
6774
6775 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6776 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6777 && reversible_comparison_p (cond1)
6778 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6779 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6780 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6781 || ((swap_condition (GET_CODE (cond0))
6782 == reverse_condition (GET_CODE (cond1)))
6783 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6784 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6785 && ! side_effects_p (x))
6786 {
6787 *ptrue = *pfalse = const0_rtx;
6788 return cond0;
6789 }
6790 }
abe6e52f
RK		 6791 }
6792
6793 else if (code == IF_THEN_ELSE)
6794 {
6795 /* If we have IF_THEN_ELSE already, extract the condition and
6796 canonicalize it if it is NE or EQ. */
6797 cond0 = XEXP (x, 0);
6798 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6799 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6800 return XEXP (cond0, 0);
6801 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6802 {
6803 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6804 return XEXP (cond0, 0);
6805 }
6806 else
6807 return cond0;
6808 }
6809
6810 /* If X is a normal SUBREG with both inner and outer modes integral,
6811 we can narrow both the true and false values of the inner expression,
6812 if there is a condition. */
6813 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6814 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6815 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6816 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6817 &true0, &false0)))
6818 {
00244e6b
RK		 6819 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6820 *pfalse
6821 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
abe6e52f 6822
abe6e52f
RK		 6823 return cond0;
6824 }
6825
6826 /* If X is a constant, this isn't special and will cause confusions
6827 if we treat it as such. Likewise if it is equivalent to a constant. */
6828 else if (CONSTANT_P (x)
6829 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6830 ;
6831
6832 /* If X is known to be either 0 or -1, those are the true and
6833 false values when testing X. */
6834 else if (num_sign_bit_copies (x, mode) == size)
6835 {
6836 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6837 return x;
6838 }
6839
6840 /* Likewise for 0 or a single bit. */
6841 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6842 {
6843 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6844 return x;
6845 }
6846
6847 /* Otherwise fail; show no condition with true and false values the same. */
6848 *ptrue = *pfalse = x;
6849 return 0;
6850}
6851\f
1a26b032
RK		 6852/* Return the value of expression X given the fact that condition COND
6853 is known to be true when applied to REG as its first operand and VAL
6854 as its second. X is known to not be shared and so can be modified in
6855 place.
6856
6857 We only handle the simplest cases, and specifically those cases that
6858 arise with IF_THEN_ELSE expressions. */
6859
6860static rtx
6861known_cond (x, cond, reg, val)
6862 rtx x;
6863 enum rtx_code cond;
6864 rtx reg, val;
6865{
6866 enum rtx_code code = GET_CODE (x);
f24ad0e4 6867 rtx temp;
1a26b032
RK		 6868 char *fmt;
6869 int i, j;
6870
6871 if (side_effects_p (x))
6872 return x;
6873
6874 if (cond == EQ && rtx_equal_p (x, reg))
6875 return val;
6876
6877 /* If X is (abs REG) and we know something about REG's relationship
6878 with zero, we may be able to simplify this. */
6879
6880 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6881 switch (cond)
6882 {
6883 case GE: case GT: case EQ:
6884 return XEXP (x, 0);
6885 case LT: case LE:
0c1c8ea6
RK		 6886 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6887 XEXP (x, 0));
e9a25f70
JL		 6888 default:
6889 break;
1a26b032
RK		 6890 }
6891
6892 /* The only other cases we handle are MIN, MAX, and comparisons if the
6893 operands are the same as REG and VAL. */
6894
6895 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6896 {
6897 if (rtx_equal_p (XEXP (x, 0), val))
6898 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6899
6900 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6901 {
6902 if (GET_RTX_CLASS (code) == '<')
6903 return (comparison_dominates_p (cond, code) ? const_true_rtx
6904 : (comparison_dominates_p (cond,
6905 reverse_condition (code))
6906 ? const0_rtx : x));
6907
6908 else if (code == SMAX || code == SMIN
6909 || code == UMIN || code == UMAX)
6910 {
6911 int unsignedp = (code == UMIN || code == UMAX);
6912
6913 if (code == SMAX || code == UMAX)
6914 cond = reverse_condition (cond);
6915
6916 switch (cond)
6917 {
6918 case GE: case GT:
6919 return unsignedp ? x : XEXP (x, 1);
6920 case LE: case LT:
6921 return unsignedp ? x : XEXP (x, 0);
6922 case GEU: case GTU:
6923 return unsignedp ? XEXP (x, 1) : x;
6924 case LEU: case LTU:
6925 return unsignedp ? XEXP (x, 0) : x;
e9a25f70
JL		 6926 default:
6927 break;
1a26b032
RK		 6928 }
6929 }
6930 }
6931 }
6932
6933 fmt = GET_RTX_FORMAT (code);
6934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6935 {
6936 if (fmt[i] == 'e')
6937 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6938 else if (fmt[i] == 'E')
6939 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6940 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6941 cond, reg, val));
6942 }
6943
6944 return x;
6945}
6946\f
e11fa86f
RK		 6947/* See if X and Y are equal for the purposes of seeing if we can rewrite an
6948 assignment as a field assignment. */
6949
6950static int
6951rtx_equal_for_field_assignment_p (x, y)
6952 rtx x;
6953 rtx y;
6954{
e11fa86f
RK		 6955 if (x == y || rtx_equal_p (x, y))
6956 return 1;
6957
6958 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6959 return 0;
6960
6961 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6962 Note that all SUBREGs of MEM are paradoxical; otherwise they
6963 would have been rewritten. */
6964 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6965 && GET_CODE (SUBREG_REG (y)) == MEM
6966 && rtx_equal_p (SUBREG_REG (y),
6967 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6968 return 1;
6969
6970 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6971 && GET_CODE (SUBREG_REG (x)) == MEM
6972 && rtx_equal_p (SUBREG_REG (x),
6973 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6974 return 1;
6975
9ec36da5
JL		 6976 /* We used to see if get_last_value of X and Y were the same but that's
6977 not correct. In one direction, we'll cause the assignment to have
6978 the wrong destination and in the case, we'll import a register into this
6979 insn that might have already have been dead. So fail if none of the
6980 above cases are true. */
6981 return 0;
e11fa86f
RK		 6982}
6983\f
230d793d
RS		 6984/* See if X, a SET operation, can be rewritten as a bit-field assignment.
6985 Return that assignment if so.
6986
6987 We only handle the most common cases. */
6988
6989static rtx
6990make_field_assignment (x)
6991 rtx x;
6992{
6993 rtx dest = SET_DEST (x);
6994 rtx src = SET_SRC (x);
dfbe1b2f 6995 rtx assign;
e11fa86f 6996 rtx rhs, lhs;
5f4f0e22
CH		 6997 HOST_WIDE_INT c1;
6998 int pos, len;
dfbe1b2f
RK		 6999 rtx other;
7000 enum machine_mode mode;
230d793d
RS		 7001
7002 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7003 a clear of a one-bit field. We will have changed it to
7004 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7005 for a SUBREG. */
7006
7007 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7008 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7009 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
e11fa86f 7010 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7011 {
8999a12e 7012 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7013 1, 1, 1, 0);
76184def 7014 if (assign != 0)
38a448ca 7015 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7016 return x;
230d793d
RS		 7017 }
7018
7019 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7020 && subreg_lowpart_p (XEXP (src, 0))
7021 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7022 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7023 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7024 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
e11fa86f 7025 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7026 {
8999a12e 7027 assign = make_extraction (VOIDmode, dest, 0,
230d793d
RS		 7028 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7029 1, 1, 1, 0);
76184def 7030 if (assign != 0)
38a448ca 7031 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7032 return x;
230d793d
RS		 7033 }
7034
9dd11dcb 7035 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
230d793d
RS		 7036 one-bit field. */
7037 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7038 && XEXP (XEXP (src, 0), 0) == const1_rtx
e11fa86f 7039 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7040 {
8999a12e 7041 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7042 1, 1, 1, 0);
76184def 7043 if (assign != 0)
38a448ca 7044 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
76184def 7045 return x;
230d793d
RS		 7046 }
7047
dfbe1b2f 7048 /* The other case we handle is assignments into a constant-position
9dd11dcb 7049 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
dfbe1b2f
RK		 7050 a mask that has all one bits except for a group of zero bits and
7051 OTHER is known to have zeros where C1 has ones, this is such an
7052 assignment. Compute the position and length from C1. Shift OTHER
7053 to the appropriate position, force it to the required mode, and
7054 make the extraction. Check for the AND in both operands. */
7055
9dd11dcb 7056 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
e11fa86f
RK		 7057 return x;
7058
7059 rhs = expand_compound_operation (XEXP (src, 0));
7060 lhs = expand_compound_operation (XEXP (src, 1));
7061
7062 if (GET_CODE (rhs) == AND
7063 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7064 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7065 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7066 else if (GET_CODE (lhs) == AND
7067 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7068 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7069 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
dfbe1b2f
RK		 7070 else
7071 return x;
230d793d 7072
e11fa86f 7073 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
dfbe1b2f 7074 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
e5e809f4
JL		 7075 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7076 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
dfbe1b2f 7077 return x;
230d793d 7078
5f4f0e22 7079 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
76184def
DE		 7080 if (assign == 0)
7081 return x;
230d793d 7082
dfbe1b2f
RK		 7083 /* The mode to use for the source is the mode of the assignment, or of
7084 what is inside a possible STRICT_LOW_PART. */
7085 mode = (GET_CODE (assign) == STRICT_LOW_PART
7086 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
230d793d 7087
dfbe1b2f
RK		 7088 /* Shift OTHER right POS places and make it the source, restricting it
7089 to the proper length and mode. */
230d793d 7090
5f4f0e22
CH		 7091 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7092 GET_MODE (src), other, pos),
6139ff20
RK		 7093 mode,
7094 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7095 ? GET_MODE_MASK (mode)
7096 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 7097 dest, 0);
230d793d 7098
dfbe1b2f 7099 return gen_rtx_combine (SET, VOIDmode, assign, src);
230d793d
RS		 7100}
7101\f
7102/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7103 if so. */
7104
7105static rtx
7106apply_distributive_law (x)
7107 rtx x;
7108{
7109 enum rtx_code code = GET_CODE (x);
7110 rtx lhs, rhs, other;
7111 rtx tem;
7112 enum rtx_code inner_code;
7113
d8a8a4da
RS		 7114 /* Distributivity is not true for floating point.
7115 It can change the value. So don't do it.
7116 -- rms and moshier@world.std.com. */
3ad2180a 7117 if (FLOAT_MODE_P (GET_MODE (x)))
d8a8a4da
RS		 7118 return x;
7119
230d793d
RS		 7120 /* The outer operation can only be one of the following: */
7121 if (code != IOR && code != AND && code != XOR
7122 && code != PLUS && code != MINUS)
7123 return x;
7124
7125 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7126
0f41302f
MS		 7127 /* If either operand is a primitive we can't do anything, so get out
7128 fast. */
230d793d 7129 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
dfbe1b2f 7130 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
230d793d
RS		 7131 return x;
7132
7133 lhs = expand_compound_operation (lhs);
7134 rhs = expand_compound_operation (rhs);
7135 inner_code = GET_CODE (lhs);
7136 if (inner_code != GET_CODE (rhs))
7137 return x;
7138
7139 /* See if the inner and outer operations distribute. */
7140 switch (inner_code)
7141 {
7142 case LSHIFTRT:
7143 case ASHIFTRT:
7144 case AND:
7145 case IOR:
7146 /* These all distribute except over PLUS. */
7147 if (code == PLUS || code == MINUS)
7148 return x;
7149 break;
7150
7151 case MULT:
7152 if (code != PLUS && code != MINUS)
7153 return x;
7154 break;
7155
7156 case ASHIFT:
45620ed4 7157 /* This is also a multiply, so it distributes over everything. */
230d793d
RS		 7158 break;
7159
7160 case SUBREG:
dfbe1b2f
RK		 7161 /* Non-paradoxical SUBREGs distributes over all operations, provided
7162 the inner modes and word numbers are the same, this is an extraction
2b4bd1bc
JW		 7163 of a low-order part, we don't convert an fp operation to int or
7164 vice versa, and we would not be converting a single-word
dfbe1b2f 7165 operation into a multi-word operation. The latter test is not
2b4bd1bc 7166 required, but it prevents generating unneeded multi-word operations.
dfbe1b2f
RK		 7167 Some of the previous tests are redundant given the latter test, but
7168 are retained because they are required for correctness.
7169
7170 We produce the result slightly differently in this case. */
7171
7172 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7173 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7174 || ! subreg_lowpart_p (lhs)
2b4bd1bc
JW		 7175 || (GET_MODE_CLASS (GET_MODE (lhs))
7176 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7177 || (GET_MODE_SIZE (GET_MODE (lhs))
8af24e26 7178 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7179 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
230d793d
RS		 7180 return x;
7181
7182 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7183 SUBREG_REG (lhs), SUBREG_REG (rhs));
7184 return gen_lowpart_for_combine (GET_MODE (x), tem);
7185
7186 default:
7187 return x;
7188 }
7189
7190 /* Set LHS and RHS to the inner operands (A and B in the example
7191 above) and set OTHER to the common operand (C in the example).
7192 These is only one way to do this unless the inner operation is
7193 commutative. */
7194 if (GET_RTX_CLASS (inner_code) == 'c'
7195 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7196 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7197 else if (GET_RTX_CLASS (inner_code) == 'c'
7198 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7199 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7200 else if (GET_RTX_CLASS (inner_code) == 'c'
7201 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7202 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7203 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7204 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7205 else
7206 return x;
7207
7208 /* Form the new inner operation, seeing if it simplifies first. */
7209 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7210
7211 /* There is one exception to the general way of distributing:
7212 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7213 if (code == XOR && inner_code == IOR)
7214 {
7215 inner_code = AND;
0c1c8ea6 7216 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
230d793d
RS		 7217 }
7218
7219 /* We may be able to continuing distributing the result, so call
7220 ourselves recursively on the inner operation before forming the
7221 outer operation, which we return. */
7222 return gen_binary (inner_code, GET_MODE (x),
7223 apply_distributive_law (tem), other);
7224}
7225\f
7226/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7227 in MODE.
7228
7229 Return an equivalent form, if different from X. Otherwise, return X. If
7230 X is zero, we are to always construct the equivalent form. */
7231
7232static rtx
7233simplify_and_const_int (x, mode, varop, constop)
7234 rtx x;
7235 enum machine_mode mode;
7236 rtx varop;
5f4f0e22 7237 unsigned HOST_WIDE_INT constop;
230d793d 7238{
951553af 7239 unsigned HOST_WIDE_INT nonzero;
9fa6d012 7240 int width = GET_MODE_BITSIZE (mode);
42301240 7241 int i;
230d793d 7242
6139ff20
RK		 7243 /* Simplify VAROP knowing that we will be only looking at some of the
7244 bits in it. */
e3d616e3 7245 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
230d793d 7246
6139ff20
RK		 7247 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7248 CONST_INT, we are done. */
7249 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7250 return varop;
230d793d 7251
fc06d7aa
RK		 7252 /* See what bits may be nonzero in VAROP. Unlike the general case of
7253 a call to nonzero_bits, here we don't care about bits outside
7254 MODE. */
7255
7256 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
230d793d 7257
9fa6d012
TG		 7258 /* If this would be an entire word for the target, but is not for
7259 the host, then sign-extend on the host so that the number will look
7260 the same way on the host that it would on the target.
7261
7262 For example, when building a 64 bit alpha hosted 32 bit sparc
7263 targeted compiler, then we want the 32 bit unsigned value -1 to be
7264 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7265 The later confuses the sparc backend. */
7266
7267 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7268 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7269 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7270
230d793d 7271 /* Turn off all bits in the constant that are known to already be zero.
951553af 7272 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
230d793d
RS		 7273 which is tested below. */
7274
951553af 7275 constop &= nonzero;
230d793d
RS		 7276
7277 /* If we don't have any bits left, return zero. */
7278 if (constop == 0)
7279 return const0_rtx;
7280
42301240
RK		 7281 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7282 a power of two, we can replace this with a ASHIFT. */
7283 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7284 && (i = exact_log2 (constop)) >= 0)
7285 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7286
6139ff20
RK		 7287 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7288 or XOR, then try to apply the distributive law. This may eliminate
7289 operations if either branch can be simplified because of the AND.
7290 It may also make some cases more complex, but those cases probably
7291 won't match a pattern either with or without this. */
7292
7293 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7294 return
7295 gen_lowpart_for_combine
7296 (mode,
7297 apply_distributive_law
7298 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7299 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7300 XEXP (varop, 0), constop),
7301 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7302 XEXP (varop, 1), constop))));
7303
230d793d
RS		 7304 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7305 if we already had one (just check for the simplest cases). */
7306 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7307 && GET_MODE (XEXP (x, 0)) == mode
7308 && SUBREG_REG (XEXP (x, 0)) == varop)
7309 varop = XEXP (x, 0);
7310 else
7311 varop = gen_lowpart_for_combine (mode, varop);
7312
0f41302f 7313 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 7314 if (GET_CODE (varop) == CLOBBER)
7315 return x ? x : varop;
7316
7317 /* If we are only masking insignificant bits, return VAROP. */
951553af 7318 if (constop == nonzero)
230d793d
RS		 7319 x = varop;
7320
7321 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7322 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6139ff20 7323 x = gen_binary (AND, mode, varop, GEN_INT (constop));
230d793d
RS		 7324
7325 else
7326 {
7327 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7328 || INTVAL (XEXP (x, 1)) != constop)
5f4f0e22 7329 SUBST (XEXP (x, 1), GEN_INT (constop));
230d793d
RS		 7330
7331 SUBST (XEXP (x, 0), varop);
7332 }
7333
7334 return x;
7335}
7336\f
b3728b0e
JW		 7337/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7338 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7339 is less useful. We can't allow both, because that results in exponential
956d6950 7340 run time recursion. There is a nullstone testcase that triggered
b3728b0e
JW		 7341 this. This macro avoids accidental uses of num_sign_bit_copies. */
7342#define num_sign_bit_copies()
7343
230d793d
RS		 7344/* Given an expression, X, compute which bits in X can be non-zero.
7345 We don't care about bits outside of those defined in MODE.
7346
7347 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7348 a shift, AND, or zero_extract, we can do better. */
7349
5f4f0e22 7350static unsigned HOST_WIDE_INT
951553af 7351nonzero_bits (x, mode)
230d793d
RS		 7352 rtx x;
7353 enum machine_mode mode;
7354{
951553af
RK		 7355 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7356 unsigned HOST_WIDE_INT inner_nz;
230d793d
RS		 7357 enum rtx_code code;
7358 int mode_width = GET_MODE_BITSIZE (mode);
7359 rtx tem;
7360
1c75dfa4
RK		 7361 /* For floating-point values, assume all bits are needed. */
7362 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7363 return nonzero;
7364
230d793d
RS		 7365 /* If X is wider than MODE, use its mode instead. */
7366 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7367 {
7368 mode = GET_MODE (x);
951553af 7369 nonzero = GET_MODE_MASK (mode);
230d793d
RS		 7370 mode_width = GET_MODE_BITSIZE (mode);
7371 }
7372
5f4f0e22 7373 if (mode_width > HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7374 /* Our only callers in this case look for single bit values. So
7375 just return the mode mask. Those tests will then be false. */
951553af 7376 return nonzero;
230d793d 7377
8baf60bb 7378#ifndef WORD_REGISTER_OPERATIONS
c6965c0f 7379 /* If MODE is wider than X, but both are a single word for both the host
0840fd91
RK		 7380 and target machines, we can compute this from which bits of the
7381 object might be nonzero in its own mode, taking into account the fact
7382 that on many CISC machines, accessing an object in a wider mode
7383 causes the high-order bits to become undefined. So they are
7384 not known to be zero. */
7385
7386 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7387 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7388 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
c6965c0f 7389 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
0840fd91
RK		 7390 {
7391 nonzero &= nonzero_bits (x, GET_MODE (x));
7392 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7393 return nonzero;
7394 }
7395#endif
7396
230d793d
RS		 7397 code = GET_CODE (x);
7398 switch (code)
7399 {
7400 case REG:
320dd7a7
RK		 7401#ifdef POINTERS_EXTEND_UNSIGNED
7402 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7403 all the bits above ptr_mode are known to be zero. */
7404 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7405 && REGNO_POINTER_FLAG (REGNO (x)))
7406 nonzero &= GET_MODE_MASK (ptr_mode);
7407#endif
7408
b0d71df9
RK		 7409#ifdef STACK_BOUNDARY
7410 /* If this is the stack pointer, we may know something about its
7411 alignment. If PUSH_ROUNDING is defined, it is possible for the
230d793d
RS		 7412 stack to be momentarily aligned only to that amount, so we pick
7413 the least alignment. */
7414
ee49a9c7
JW		 7415 /* We can't check for arg_pointer_rtx here, because it is not
7416 guaranteed to have as much alignment as the stack pointer.
7417 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7418 alignment but the argument pointer has only 64 bit alignment. */
7419
0e9ff885
DM		 7420 if ((x == frame_pointer_rtx
7421 || x == stack_pointer_rtx
7422 || x == hard_frame_pointer_rtx
7423 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7424 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7425#ifdef STACK_BIAS
7426 && !STACK_BIAS
7427#endif
7428 )
230d793d 7429 {
b0d71df9 7430 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
230d793d
RS		 7431
7432#ifdef PUSH_ROUNDING
91102d5a 7433 if (REGNO (x) == STACK_POINTER_REGNUM)
b0d71df9 7434 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
230d793d
RS		 7435#endif
7436
320dd7a7
RK		 7437 /* We must return here, otherwise we may get a worse result from
7438 one of the choices below. There is nothing useful below as
7439 far as the stack pointer is concerned. */
b0d71df9 7440 return nonzero &= ~ (sp_alignment - 1);
230d793d 7441 }
b0d71df9 7442#endif
230d793d 7443
55310dad
RK		 7444 /* If X is a register whose nonzero bits value is current, use it.
7445 Otherwise, if X is a register whose value we can find, use that
7446 value. Otherwise, use the previously-computed global nonzero bits
7447 for this register. */
7448
7449 if (reg_last_set_value[REGNO (x)] != 0
7450 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7451 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7452 || reg_last_set_label[REGNO (x)] == label_tick)
7453 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7454 return reg_last_set_nonzero_bits[REGNO (x)];
230d793d
RS		 7455
7456 tem = get_last_value (x);
9afa3d54 7457
230d793d 7458 if (tem)
9afa3d54
RK		 7459 {
7460#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7461 /* If X is narrower than MODE and TEM is a non-negative
7462 constant that would appear negative in the mode of X,
7463 sign-extend it for use in reg_nonzero_bits because some
7464 machines (maybe most) will actually do the sign-extension
7465 and this is the conservative approach.
7466
7467 ??? For 2.5, try to tighten up the MD files in this regard
7468 instead of this kludge. */
7469
7470 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7471 && GET_CODE (tem) == CONST_INT
7472 && INTVAL (tem) > 0
7473 && 0 != (INTVAL (tem)
7474 & ((HOST_WIDE_INT) 1
9e69be8c 7475 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 7476 tem = GEN_INT (INTVAL (tem)
7477 | ((HOST_WIDE_INT) (-1)
7478 << GET_MODE_BITSIZE (GET_MODE (x))));
7479#endif
7480 return nonzero_bits (tem, mode);
7481 }
951553af
RK		 7482 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7483 return reg_nonzero_bits[REGNO (x)] & nonzero;
230d793d 7484 else
951553af 7485 return nonzero;
230d793d
RS		 7486
7487 case CONST_INT:
9afa3d54
RK		 7488#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7489 /* If X is negative in MODE, sign-extend the value. */
9e69be8c
RK		 7490 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7491 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7492 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
9afa3d54
RK		 7493#endif
7494
230d793d
RS		 7495 return INTVAL (x);
7496
230d793d 7497 case MEM:
8baf60bb 7498#ifdef LOAD_EXTEND_OP
230d793d
RS		 7499 /* In many, if not most, RISC machines, reading a byte from memory
7500 zeros the rest of the register. Noticing that fact saves a lot
7501 of extra zero-extends. */
8baf60bb
RK		 7502 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7503 nonzero &= GET_MODE_MASK (GET_MODE (x));
230d793d 7504#endif
8baf60bb 7505 break;
230d793d 7506
230d793d
RS		 7507 case EQ: case NE:
7508 case GT: case GTU:
7509 case LT: case LTU:
7510 case GE: case GEU:
7511 case LE: case LEU:
3f508eca 7512
c6965c0f
RK		 7513 /* If this produces an integer result, we know which bits are set.
7514 Code here used to clear bits outside the mode of X, but that is
7515 now done above. */
230d793d 7516
c6965c0f
RK		 7517 if (GET_MODE_CLASS (mode) == MODE_INT
7518 && mode_width <= HOST_BITS_PER_WIDE_INT)
7519 nonzero = STORE_FLAG_VALUE;
230d793d 7520 break;
230d793d 7521
230d793d 7522 case NEG:
b3728b0e
JW		 7523#if 0
7524 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7525 and num_sign_bit_copies. */
d0ab8cd3
RK		 7526 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7527 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7528 nonzero = 1;
b3728b0e 7529#endif
230d793d
RS		 7530
7531 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
951553af 7532 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
230d793d 7533 break;
d0ab8cd3
RK		 7534
7535 case ABS:
b3728b0e
JW		 7536#if 0
7537 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7538 and num_sign_bit_copies. */
d0ab8cd3
RK		 7539 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7540 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7541 nonzero = 1;
b3728b0e 7542#endif
d0ab8cd3 7543 break;
230d793d
RS		 7544
7545 case TRUNCATE:
951553af 7546 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
230d793d
RS		 7547 break;
7548
7549 case ZERO_EXTEND:
951553af 7550 nonzero &= nonzero_bits (XEXP (x, 0), mode);
230d793d 7551 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
951553af 7552 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
230d793d
RS		 7553 break;
7554
7555 case SIGN_EXTEND:
7556 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7557 Otherwise, show all the bits in the outer mode but not the inner
7558 may be non-zero. */
951553af 7559 inner_nz = nonzero_bits (XEXP (x, 0), mode);
230d793d
RS		 7560 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7561 {
951553af 7562 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
e3da301d
MS		 7563 if (inner_nz
7564 & (((HOST_WIDE_INT) 1
7565 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
951553af 7566 inner_nz |= (GET_MODE_MASK (mode)
230d793d
RS		 7567 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7568 }
7569
951553af 7570 nonzero &= inner_nz;
230d793d
RS		 7571 break;
7572
7573 case AND:
951553af
RK		 7574 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7575 & nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7576 break;
7577
d0ab8cd3
RK		 7578 case XOR: case IOR:
7579 case UMIN: case UMAX: case SMIN: case SMAX:
951553af
RK		 7580 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7581 | nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7582 break;
7583
7584 case PLUS: case MINUS:
7585 case MULT:
7586 case DIV: case UDIV:
7587 case MOD: case UMOD:
7588 /* We can apply the rules of arithmetic to compute the number of
7589 high- and low-order zero bits of these operations. We start by
7590 computing the width (position of the highest-order non-zero bit)
7591 and the number of low-order zero bits for each value. */
7592 {
951553af
RK		 7593 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7594 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7595 int width0 = floor_log2 (nz0) + 1;
7596 int width1 = floor_log2 (nz1) + 1;
7597 int low0 = floor_log2 (nz0 & -nz0);
7598 int low1 = floor_log2 (nz1 & -nz1);
318b149c
RK		 7599 HOST_WIDE_INT op0_maybe_minusp
7600 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7601 HOST_WIDE_INT op1_maybe_minusp
7602 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
230d793d
RS		 7603 int result_width = mode_width;
7604 int result_low = 0;
7605
7606 switch (code)
7607 {
7608 case PLUS:
0e9ff885
DM		 7609#ifdef STACK_BIAS
7610 if (STACK_BIAS
7611 && (XEXP (x, 0) == stack_pointer_rtx
7612 || XEXP (x, 0) == frame_pointer_rtx)
7613 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7614 {
7615 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7616
7617 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7618 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7619 width0 = floor_log2 (nz0) + 1;
7620 width1 = floor_log2 (nz1) + 1;
7621 low0 = floor_log2 (nz0 & -nz0);
7622 low1 = floor_log2 (nz1 & -nz1);
7623 }
7624#endif
230d793d
RS		 7625 result_width = MAX (width0, width1) + 1;
7626 result_low = MIN (low0, low1);
7627 break;
7628 case MINUS:
7629 result_low = MIN (low0, low1);
7630 break;
7631 case MULT:
7632 result_width = width0 + width1;
7633 result_low = low0 + low1;
7634 break;
7635 case DIV:
7636 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7637 result_width = width0;
7638 break;
7639 case UDIV:
7640 result_width = width0;
7641 break;
7642 case MOD:
7643 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7644 result_width = MIN (width0, width1);
7645 result_low = MIN (low0, low1);
7646 break;
7647 case UMOD:
7648 result_width = MIN (width0, width1);
7649 result_low = MIN (low0, low1);
7650 break;
e9a25f70
JL		 7651 default:
7652 abort ();
230d793d
RS		 7653 }
7654
7655 if (result_width < mode_width)
951553af 7656 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
230d793d
RS		 7657
7658 if (result_low > 0)
951553af 7659 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
230d793d
RS		 7660 }
7661 break;
7662
7663 case ZERO_EXTRACT:
7664 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 7665 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
951553af 7666 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
230d793d
RS		 7667 break;
7668
7669 case SUBREG:
c3c2cb37
RK		 7670 /* If this is a SUBREG formed for a promoted variable that has
7671 been zero-extended, we know that at least the high-order bits
7672 are zero, though others might be too. */
7673
7674 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
951553af
RK		 7675 nonzero = (GET_MODE_MASK (GET_MODE (x))
7676 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
c3c2cb37 7677
230d793d
RS		 7678 /* If the inner mode is a single word for both the host and target
7679 machines, we can compute this from which bits of the inner
951553af 7680 object might be nonzero. */
230d793d 7681 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5f4f0e22
CH		 7682 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7683 <= HOST_BITS_PER_WIDE_INT))
230d793d 7684 {
951553af 7685 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8baf60bb 7686
b52ce03d
R		 7687#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7688 /* If this is a typical RISC machine, we only have to worry
7689 about the way loads are extended. */
7690 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7691 ? (nonzero
7692 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7693 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
230d793d 7694#endif
b52ce03d
R		 7695 {
7696 /* On many CISC machines, accessing an object in a wider mode
7697 causes the high-order bits to become undefined. So they are
7698 not known to be zero. */
7699 if (GET_MODE_SIZE (GET_MODE (x))
7700 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7701 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7702 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7703 }
230d793d
RS		 7704 }
7705 break;
7706
7707 case ASHIFTRT:
7708 case LSHIFTRT:
7709 case ASHIFT:
230d793d 7710 case ROTATE:
951553af 7711 /* The nonzero bits are in two classes: any bits within MODE
230d793d 7712 that aren't in GET_MODE (x) are always significant. The rest of the
951553af 7713 nonzero bits are those that are significant in the operand of
230d793d
RS		 7714 the shift when shifted the appropriate number of bits. This
7715 shows that high-order bits are cleared by the right shift and
7716 low-order bits by left shifts. */
7717 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7718 && INTVAL (XEXP (x, 1)) >= 0
5f4f0e22 7719 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7720 {
7721 enum machine_mode inner_mode = GET_MODE (x);
7722 int width = GET_MODE_BITSIZE (inner_mode);
7723 int count = INTVAL (XEXP (x, 1));
5f4f0e22 7724 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
951553af
RK		 7725 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7726 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5f4f0e22 7727 unsigned HOST_WIDE_INT outer = 0;
230d793d
RS		 7728
7729 if (mode_width > width)
951553af 7730 outer = (op_nonzero & nonzero & ~ mode_mask);
230d793d
RS		 7731
7732 if (code == LSHIFTRT)
7733 inner >>= count;
7734 else if (code == ASHIFTRT)
7735 {
7736 inner >>= count;
7737
951553af 7738 /* If the sign bit may have been nonzero before the shift, we
230d793d 7739 need to mark all the places it could have been copied to
951553af 7740 by the shift as possibly nonzero. */
5f4f0e22
CH		 7741 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7742 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
230d793d 7743 }
45620ed4 7744 else if (code == ASHIFT)
230d793d
RS		 7745 inner <<= count;
7746 else
7747 inner = ((inner << (count % width)
7748 | (inner >> (width - (count % width)))) & mode_mask);
7749
951553af 7750 nonzero &= (outer | inner);
230d793d
RS		 7751 }
7752 break;
7753
7754 case FFS:
7755 /* This is at most the number of bits in the mode. */
951553af 7756 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
230d793d 7757 break;
d0ab8cd3
RK		 7758
7759 case IF_THEN_ELSE:
951553af
RK		 7760 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7761 | nonzero_bits (XEXP (x, 2), mode));
d0ab8cd3 7762 break;
e9a25f70
JL		 7763
7764 default:
7765 break;
230d793d
RS		 7766 }
7767
951553af 7768 return nonzero;
230d793d 7769}
b3728b0e
JW		 7770
7771/* See the macro definition above. */
7772#undef num_sign_bit_copies
230d793d 7773\f
d0ab8cd3 7774/* Return the number of bits at the high-order end of X that are known to
5109d49f
RK		 7775 be equal to the sign bit. X will be used in mode MODE; if MODE is
7776 VOIDmode, X will be used in its own mode. The returned value will always
7777 be between 1 and the number of bits in MODE. */
d0ab8cd3
RK		 7778
7779static int
7780num_sign_bit_copies (x, mode)
7781 rtx x;
7782 enum machine_mode mode;
7783{
7784 enum rtx_code code = GET_CODE (x);
7785 int bitwidth;
7786 int num0, num1, result;
951553af 7787 unsigned HOST_WIDE_INT nonzero;
d0ab8cd3
RK		 7788 rtx tem;
7789
7790 /* If we weren't given a mode, use the mode of X. If the mode is still
1c75dfa4
RK		 7791 VOIDmode, we don't know anything. Likewise if one of the modes is
7792 floating-point. */
d0ab8cd3
RK		 7793
7794 if (mode == VOIDmode)
7795 mode = GET_MODE (x);
7796
1c75dfa4 7797 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
6752e8d2 7798 return 1;
d0ab8cd3
RK		 7799
7800 bitwidth = GET_MODE_BITSIZE (mode);
7801
0f41302f 7802 /* For a smaller object, just ignore the high bits. */
312def2e
RK		 7803 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7804 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7805 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7806
e9a25f70
JL		 7807 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7808 {
0c314d1a
RK		 7809#ifndef WORD_REGISTER_OPERATIONS
7810 /* If this machine does not do all register operations on the entire
7811 register and MODE is wider than the mode of X, we can say nothing
7812 at all about the high-order bits. */
e9a25f70
JL		 7813 return 1;
7814#else
7815 /* Likewise on machines that do, if the mode of the object is smaller
7816 than a word and loads of that size don't sign extend, we can say
7817 nothing about the high order bits. */
7818 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7819#ifdef LOAD_EXTEND_OP
7820 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7821#endif
7822 )
7823 return 1;
0c314d1a 7824#endif
e9a25f70 7825 }
0c314d1a 7826
d0ab8cd3
RK		 7827 switch (code)
7828 {
7829 case REG:
55310dad 7830
ff0dbdd1
RK		 7831#ifdef POINTERS_EXTEND_UNSIGNED
7832 /* If pointers extend signed and this is a pointer in Pmode, say that
7833 all the bits above ptr_mode are known to be sign bit copies. */
7834 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7835 && REGNO_POINTER_FLAG (REGNO (x)))
7836 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7837#endif
7838
55310dad
RK		 7839 if (reg_last_set_value[REGNO (x)] != 0
7840 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7841 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7842 || reg_last_set_label[REGNO (x)] == label_tick)
7843 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7844 return reg_last_set_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7845
7846 tem = get_last_value (x);
7847 if (tem != 0)
7848 return num_sign_bit_copies (tem, mode);
55310dad
RK		 7849
7850 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7851 return reg_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7852 break;
7853
457816e2 7854 case MEM:
8baf60bb 7855#ifdef LOAD_EXTEND_OP
457816e2 7856 /* Some RISC machines sign-extend all loads of smaller than a word. */
8baf60bb
RK		 7857 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7858 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
457816e2 7859#endif
8baf60bb 7860 break;
457816e2 7861
d0ab8cd3
RK		 7862 case CONST_INT:
7863 /* If the constant is negative, take its 1's complement and remask.
7864 Then see how many zero bits we have. */
951553af 7865 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
ac49a949 7866 if (bitwidth <= HOST_BITS_PER_WIDE_INT
951553af
RK		 7867 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7868 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
d0ab8cd3 7869
951553af 7870 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7871
7872 case SUBREG:
c3c2cb37
RK		 7873 /* If this is a SUBREG for a promoted object that is sign-extended
7874 and we are looking at it in a wider mode, we know that at least the
7875 high-order bits are known to be sign bit copies. */
7876
7877 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
dc3e17ad
RK		 7878 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7879 num_sign_bit_copies (SUBREG_REG (x), mode));
c3c2cb37 7880
0f41302f 7881 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7882 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7883 {
7884 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7885 return MAX (1, (num0
7886 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7887 - bitwidth)));
7888 }
457816e2 7889
8baf60bb 7890#ifdef WORD_REGISTER_OPERATIONS
2aec5b7a 7891#ifdef LOAD_EXTEND_OP
8baf60bb
RK		 7892 /* For paradoxical SUBREGs on machines where all register operations
7893 affect the entire register, just look inside. Note that we are
7894 passing MODE to the recursive call, so the number of sign bit copies
7895 will remain relative to that mode, not the inner mode. */
457816e2 7896
2aec5b7a
JW		 7897 /* This works only if loads sign extend. Otherwise, if we get a
7898 reload for the inner part, it may be loaded from the stack, and
7899 then we lose all sign bit copies that existed before the store
7900 to the stack. */
7901
7902 if ((GET_MODE_SIZE (GET_MODE (x))
7903 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7904 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
457816e2 7905 return num_sign_bit_copies (SUBREG_REG (x), mode);
2aec5b7a 7906#endif
457816e2 7907#endif
d0ab8cd3
RK		 7908 break;
7909
7910 case SIGN_EXTRACT:
7911 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7912 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7913 break;
7914
7915 case SIGN_EXTEND:
7916 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7917 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7918
7919 case TRUNCATE:
0f41302f 7920 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7921 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7922 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7923 - bitwidth)));
7924
7925 case NOT:
7926 return num_sign_bit_copies (XEXP (x, 0), mode);
7927
7928 case ROTATE: case ROTATERT:
7929 /* If we are rotating left by a number of bits less than the number
7930 of sign bit copies, we can just subtract that amount from the
7931 number. */
7932 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7933 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7934 {
7935 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7936 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7937 : bitwidth - INTVAL (XEXP (x, 1))));
7938 }
7939 break;
7940
7941 case NEG:
7942 /* In general, this subtracts one sign bit copy. But if the value
7943 is known to be positive, the number of sign bit copies is the
951553af
RK		 7944 same as that of the input. Finally, if the input has just one bit
7945 that might be nonzero, all the bits are copies of the sign bit. */
7946 nonzero = nonzero_bits (XEXP (x, 0), mode);
7947 if (nonzero == 1)
d0ab8cd3
RK		 7948 return bitwidth;
7949
7950 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7951 if (num0 > 1
ac49a949 7952 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7953 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
d0ab8cd3
RK		 7954 num0--;
7955
7956 return num0;
7957
7958 case IOR: case AND: case XOR:
7959 case SMIN: case SMAX: case UMIN: case UMAX:
7960 /* Logical operations will preserve the number of sign-bit copies.
7961 MIN and MAX operations always return one of the operands. */
7962 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7963 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7964 return MIN (num0, num1);
7965
7966 case PLUS: case MINUS:
7967 /* For addition and subtraction, we can have a 1-bit carry. However,
7968 if we are subtracting 1 from a positive number, there will not
7969 be such a carry. Furthermore, if the positive number is known to
7970 be 0 or 1, we know the result is either -1 or 0. */
7971
3e3ea975 7972 if (code == PLUS && XEXP (x, 1) == constm1_rtx
9295e6af 7973 && bitwidth <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 7974 {
951553af
RK		 7975 nonzero = nonzero_bits (XEXP (x, 0), mode);
7976 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7977 return (nonzero == 1 || nonzero == 0 ? bitwidth
7978 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7979 }
7980
7981 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7982 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7983 return MAX (1, MIN (num0, num1) - 1);
7984
7985 case MULT:
7986 /* The number of bits of the product is the sum of the number of
7987 bits of both terms. However, unless one of the terms if known
7988 to be positive, we must allow for an additional bit since negating
7989 a negative number can remove one sign bit copy. */
7990
7991 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7992 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7993
7994 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7995 if (result > 0
9295e6af 7996 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7997 && ((nonzero_bits (XEXP (x, 0), mode)
d0ab8cd3 7998 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
01c82bbb
RK		 7999 && ((nonzero_bits (XEXP (x, 1), mode)
8000 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
d0ab8cd3
RK		 8001 result--;
8002
8003 return MAX (1, result);
8004
8005 case UDIV:
8006 /* The result must be <= the first operand. */
8007 return num_sign_bit_copies (XEXP (x, 0), mode);
8008
8009 case UMOD:
8010 /* The result must be <= the scond operand. */
8011 return num_sign_bit_copies (XEXP (x, 1), mode);
8012
8013 case DIV:
8014 /* Similar to unsigned division, except that we have to worry about
8015 the case where the divisor is negative, in which case we have
8016 to add 1. */
8017 result = num_sign_bit_copies (XEXP (x, 0), mode);
8018 if (result > 1
ac49a949 8019 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8020 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 8021 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8022 result --;
8023
8024 return result;
8025
8026 case MOD:
8027 result = num_sign_bit_copies (XEXP (x, 1), mode);
8028 if (result > 1
ac49a949 8029 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8030 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 8031 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8032 result --;
8033
8034 return result;
8035
8036 case ASHIFTRT:
8037 /* Shifts by a constant add to the number of bits equal to the
8038 sign bit. */
8039 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8040 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8041 && INTVAL (XEXP (x, 1)) > 0)
8042 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8043
8044 return num0;
8045
8046 case ASHIFT:
d0ab8cd3
RK		 8047 /* Left shifts destroy copies. */
8048 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8049 || INTVAL (XEXP (x, 1)) < 0
8050 || INTVAL (XEXP (x, 1)) >= bitwidth)
8051 return 1;
8052
8053 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8054 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8055
8056 case IF_THEN_ELSE:
8057 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8058 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8059 return MIN (num0, num1);
8060
d0ab8cd3
RK		 8061 case EQ: case NE: case GE: case GT: case LE: case LT:
8062 case GEU: case GTU: case LEU: case LTU:
0802d516
RK		 8063 if (STORE_FLAG_VALUE == -1)
8064 return bitwidth;
e9a25f70
JL		 8065 break;
8066
8067 default:
8068 break;
d0ab8cd3
RK		 8069 }
8070
8071 /* If we haven't been able to figure it out by one of the above rules,
8072 see if some of the high-order bits are known to be zero. If so,
ac49a949
RS		 8073 count those bits and return one less than that amount. If we can't
8074 safely compute the mask for this mode, always return BITWIDTH. */
8075
8076 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6752e8d2 8077 return 1;
d0ab8cd3 8078
951553af 8079 nonzero = nonzero_bits (x, mode);
df6f4086 8080 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
951553af 8081 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8082}
8083\f
1a26b032
RK		 8084/* Return the number of "extended" bits there are in X, when interpreted
8085 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8086 unsigned quantities, this is the number of high-order zero bits.
8087 For signed quantities, this is the number of copies of the sign bit
8088 minus 1. In both case, this function returns the number of "spare"
8089 bits. For example, if two quantities for which this function returns
8090 at least 1 are added, the addition is known not to overflow.
8091
8092 This function will always return 0 unless called during combine, which
8093 implies that it must be called from a define_split. */
8094
8095int
8096extended_count (x, mode, unsignedp)
8097 rtx x;
8098 enum machine_mode mode;
8099 int unsignedp;
8100{
951553af 8101 if (nonzero_sign_valid == 0)
1a26b032
RK		 8102 return 0;
8103
8104 return (unsignedp
ac49a949
RS		 8105 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8106 && (GET_MODE_BITSIZE (mode) - 1
951553af 8107 - floor_log2 (nonzero_bits (x, mode))))
1a26b032
RK		 8108 : num_sign_bit_copies (x, mode) - 1);
8109}
8110\f
230d793d
RS		 8111/* This function is called from `simplify_shift_const' to merge two
8112 outer operations. Specifically, we have already found that we need
8113 to perform operation *POP0 with constant *PCONST0 at the outermost
8114 position. We would now like to also perform OP1 with constant CONST1
8115 (with *POP0 being done last).
8116
8117 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8118 the resulting operation. *PCOMP_P is set to 1 if we would need to
8119 complement the innermost operand, otherwise it is unchanged.
8120
8121 MODE is the mode in which the operation will be done. No bits outside
8122 the width of this mode matter. It is assumed that the width of this mode
5f4f0e22 8123 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
230d793d
RS		 8124
8125 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8126 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8127 result is simply *PCONST0.
8128
8129 If the resulting operation cannot be expressed as one operation, we
8130 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8131
8132static int
8133merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8134 enum rtx_code *pop0;
5f4f0e22 8135 HOST_WIDE_INT *pconst0;
230d793d 8136 enum rtx_code op1;
5f4f0e22 8137 HOST_WIDE_INT const1;
230d793d
RS		 8138 enum machine_mode mode;
8139 int *pcomp_p;
8140{
8141 enum rtx_code op0 = *pop0;
5f4f0e22 8142 HOST_WIDE_INT const0 = *pconst0;
9fa6d012 8143 int width = GET_MODE_BITSIZE (mode);
230d793d
RS		 8144
8145 const0 &= GET_MODE_MASK (mode);
8146 const1 &= GET_MODE_MASK (mode);
8147
8148 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8149 if (op0 == AND)
8150 const1 &= const0;
8151
8152 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8153 if OP0 is SET. */
8154
8155 if (op1 == NIL || op0 == SET)
8156 return 1;
8157
8158 else if (op0 == NIL)
8159 op0 = op1, const0 = const1;
8160
8161 else if (op0 == op1)
8162 {
8163 switch (op0)
8164 {
8165 case AND:
8166 const0 &= const1;
8167 break;
8168 case IOR:
8169 const0 |= const1;
8170 break;
8171 case XOR:
8172 const0 ^= const1;
8173 break;
8174 case PLUS:
8175 const0 += const1;
8176 break;
8177 case NEG:
8178 op0 = NIL;
8179 break;
e9a25f70
JL		 8180 default:
8181 break;
230d793d
RS		 8182 }
8183 }
8184
8185 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8186 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8187 return 0;
8188
8189 /* If the two constants aren't the same, we can't do anything. The
8190 remaining six cases can all be done. */
8191 else if (const0 != const1)
8192 return 0;
8193
8194 else
8195 switch (op0)
8196 {
8197 case IOR:
8198 if (op1 == AND)
8199 /* (a & b) | b == b */
8200 op0 = SET;
8201 else /* op1 == XOR */
8202 /* (a ^ b) | b == a | b */
b729186a 8203 {;}
230d793d
RS		 8204 break;
8205
8206 case XOR:
8207 if (op1 == AND)
8208 /* (a & b) ^ b == (~a) & b */
8209 op0 = AND, *pcomp_p = 1;
8210 else /* op1 == IOR */
8211 /* (a | b) ^ b == a & ~b */
8212 op0 = AND, *pconst0 = ~ const0;
8213 break;
8214
8215 case AND:
8216 if (op1 == IOR)
8217 /* (a | b) & b == b */
8218 op0 = SET;
8219 else /* op1 == XOR */
8220 /* (a ^ b) & b) == (~a) & b */
8221 *pcomp_p = 1;
8222 break;
e9a25f70
JL		 8223 default:
8224 break;
230d793d
RS		 8225 }
8226
8227 /* Check for NO-OP cases. */
8228 const0 &= GET_MODE_MASK (mode);
8229 if (const0 == 0
8230 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8231 op0 = NIL;
8232 else if (const0 == 0 && op0 == AND)
8233 op0 = SET;
8234 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8235 op0 = NIL;
8236
9fa6d012
TG		 8237 /* If this would be an entire word for the target, but is not for
8238 the host, then sign-extend on the host so that the number will look
8239 the same way on the host that it would on the target.
8240
8241 For example, when building a 64 bit alpha hosted 32 bit sparc
8242 targeted compiler, then we want the 32 bit unsigned value -1 to be
8243 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8244 The later confuses the sparc backend. */
8245
8246 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8247 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8248 const0 |= ((HOST_WIDE_INT) (-1) << width);
8249
230d793d
RS		 8250 *pop0 = op0;
8251 *pconst0 = const0;
8252
8253 return 1;
8254}
8255\f
8256/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8257 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8258 that we started with.
8259
8260 The shift is normally computed in the widest mode we find in VAROP, as
8261 long as it isn't a different number of words than RESULT_MODE. Exceptions
8262 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8263
8264static rtx
8265simplify_shift_const (x, code, result_mode, varop, count)
8266 rtx x;
8267 enum rtx_code code;
8268 enum machine_mode result_mode;
8269 rtx varop;
8270 int count;
8271{
8272 enum rtx_code orig_code = code;
8273 int orig_count = count;
8274 enum machine_mode mode = result_mode;
8275 enum machine_mode shift_mode, tmode;
8276 int mode_words
8277 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8278 /* We form (outer_op (code varop count) (outer_const)). */
8279 enum rtx_code outer_op = NIL;
c4e861e8 8280 HOST_WIDE_INT outer_const = 0;
230d793d
RS		 8281 rtx const_rtx;
8282 int complement_p = 0;
8283 rtx new;
8284
8285 /* If we were given an invalid count, don't do anything except exactly
8286 what was requested. */
8287
8288 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8289 {
8290 if (x)
8291 return x;
8292
38a448ca 8293 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
230d793d
RS		 8294 }
8295
8296 /* Unless one of the branches of the `if' in this loop does a `continue',
8297 we will `break' the loop after the `if'. */
8298
8299 while (count != 0)
8300 {
8301 /* If we have an operand of (clobber (const_int 0)), just return that
8302 value. */
8303 if (GET_CODE (varop) == CLOBBER)
8304 return varop;
8305
8306 /* If we discovered we had to complement VAROP, leave. Making a NOT
8307 here would cause an infinite loop. */
8308 if (complement_p)
8309 break;
8310
abc95ed3 8311 /* Convert ROTATERT to ROTATE. */
230d793d
RS		 8312 if (code == ROTATERT)
8313 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8314
230d793d 8315 /* We need to determine what mode we will do the shift in. If the
f6789c77
RK		 8316 shift is a right shift or a ROTATE, we must always do it in the mode
8317 it was originally done in. Otherwise, we can do it in MODE, the
0f41302f 8318 widest mode encountered. */
f6789c77
RK		 8319 shift_mode
8320 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8321 ? result_mode : mode);
230d793d
RS		 8322
8323 /* Handle cases where the count is greater than the size of the mode
8324 minus 1. For ASHIFT, use the size minus one as the count (this can
8325 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8326 take the count modulo the size. For other shifts, the result is
8327 zero.
8328
8329 Since these shifts are being produced by the compiler by combining
8330 multiple operations, each of which are defined, we know what the
8331 result is supposed to be. */
8332
8333 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8334 {
8335 if (code == ASHIFTRT)
8336 count = GET_MODE_BITSIZE (shift_mode) - 1;
8337 else if (code == ROTATE || code == ROTATERT)
8338 count %= GET_MODE_BITSIZE (shift_mode);
8339 else
8340 {
8341 /* We can't simply return zero because there may be an
8342 outer op. */
8343 varop = const0_rtx;
8344 count = 0;
8345 break;
8346 }
8347 }
8348
8349 /* Negative counts are invalid and should not have been made (a
8350 programmer-specified negative count should have been handled
0f41302f 8351 above). */
230d793d
RS		 8352 else if (count < 0)
8353 abort ();
8354
312def2e
RK		 8355 /* An arithmetic right shift of a quantity known to be -1 or 0
8356 is a no-op. */
8357 if (code == ASHIFTRT
8358 && (num_sign_bit_copies (varop, shift_mode)
8359 == GET_MODE_BITSIZE (shift_mode)))
d0ab8cd3 8360 {
312def2e
RK		 8361 count = 0;
8362 break;
8363 }
d0ab8cd3 8364
312def2e
RK		 8365 /* If we are doing an arithmetic right shift and discarding all but
8366 the sign bit copies, this is equivalent to doing a shift by the
8367 bitsize minus one. Convert it into that shift because it will often
8368 allow other simplifications. */
500c518b 8369
312def2e
RK		 8370 if (code == ASHIFTRT
8371 && (count + num_sign_bit_copies (varop, shift_mode)
8372 >= GET_MODE_BITSIZE (shift_mode)))
8373 count = GET_MODE_BITSIZE (shift_mode) - 1;
500c518b 8374
230d793d
RS		 8375 /* We simplify the tests below and elsewhere by converting
8376 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8377 `make_compound_operation' will convert it to a ASHIFTRT for
8378 those machines (such as Vax) that don't have a LSHIFTRT. */
5f4f0e22 8379 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8380 && code == ASHIFTRT
951553af 8381 && ((nonzero_bits (varop, shift_mode)
5f4f0e22
CH		 8382 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8383 == 0))
230d793d
RS		 8384 code = LSHIFTRT;
8385
8386 switch (GET_CODE (varop))
8387 {
8388 case SIGN_EXTEND:
8389 case ZERO_EXTEND:
8390 case SIGN_EXTRACT:
8391 case ZERO_EXTRACT:
8392 new = expand_compound_operation (varop);
8393 if (new != varop)
8394 {
8395 varop = new;
8396 continue;
8397 }
8398 break;
8399
8400 case MEM:
8401 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8402 minus the width of a smaller mode, we can do this with a
8403 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8404 if ((code == ASHIFTRT || code == LSHIFTRT)
8405 && ! mode_dependent_address_p (XEXP (varop, 0))
8406 && ! MEM_VOLATILE_P (varop)
8407 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8408 MODE_INT, 1)) != BLKmode)
8409 {
f76b9db2 8410 if (BYTES_BIG_ENDIAN)
38a448ca 8411 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
f76b9db2 8412 else
38a448ca
RH		 8413 new = gen_rtx_MEM (tmode,
8414 plus_constant (XEXP (varop, 0),
8415 count / BITS_PER_UNIT));
e24b00c8
ILT		 8416 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8417 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8418 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
230d793d
RS		 8419 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8420 : ZERO_EXTEND, mode, new);
8421 count = 0;
8422 continue;
8423 }
8424 break;
8425
8426 case USE:
8427 /* Similar to the case above, except that we can only do this if
8428 the resulting mode is the same as that of the underlying
8429 MEM and adjust the address depending on the *bits* endianness
8430 because of the way that bit-field extract insns are defined. */
8431 if ((code == ASHIFTRT || code == LSHIFTRT)
8432 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8433 MODE_INT, 1)) != BLKmode
8434 && tmode == GET_MODE (XEXP (varop, 0)))
8435 {
f76b9db2
ILT		 8436 if (BITS_BIG_ENDIAN)
8437 new = XEXP (varop, 0);
8438 else
8439 {
8440 new = copy_rtx (XEXP (varop, 0));
8441 SUBST (XEXP (new, 0),
8442 plus_constant (XEXP (new, 0),
8443 count / BITS_PER_UNIT));
8444 }
230d793d
RS		 8445
8446 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8447 : ZERO_EXTEND, mode, new);
8448 count = 0;
8449 continue;
8450 }
8451 break;
8452
8453 case SUBREG:
8454 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8455 the same number of words as what we've seen so far. Then store
8456 the widest mode in MODE. */
f9e67232
RS		 8457 if (subreg_lowpart_p (varop)
8458 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8459 > GET_MODE_SIZE (GET_MODE (varop)))
230d793d
RS		 8460 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8461 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8462 == mode_words))
8463 {
8464 varop = SUBREG_REG (varop);
8465 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8466 mode = GET_MODE (varop);
8467 continue;
8468 }
8469 break;
8470
8471 case MULT:
8472 /* Some machines use MULT instead of ASHIFT because MULT
8473 is cheaper. But it is still better on those machines to
8474 merge two shifts into one. */
8475 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8476 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8477 {
8478 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8479 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
230d793d
RS		 8480 continue;
8481 }
8482 break;
8483
8484 case UDIV:
8485 /* Similar, for when divides are cheaper. */
8486 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8487 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8488 {
8489 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8490 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS		 8491 continue;
8492 }
8493 break;
8494
8495 case ASHIFTRT:
8496 /* If we are extracting just the sign bit of an arithmetic right
8497 shift, that shift is not needed. */
8498 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8499 {
8500 varop = XEXP (varop, 0);
8501 continue;
8502 }
8503
0f41302f 8504 /* ... fall through ... */
230d793d
RS		 8505
8506 case LSHIFTRT:
8507 case ASHIFT:
230d793d
RS		 8508 case ROTATE:
8509 /* Here we have two nested shifts. The result is usually the
8510 AND of a new shift with a mask. We compute the result below. */
8511 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8512 && INTVAL (XEXP (varop, 1)) >= 0
8513 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5f4f0e22
CH		 8514 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8515 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 8516 {
8517 enum rtx_code first_code = GET_CODE (varop);
8518 int first_count = INTVAL (XEXP (varop, 1));
5f4f0e22 8519 unsigned HOST_WIDE_INT mask;
230d793d 8520 rtx mask_rtx;
230d793d 8521
230d793d
RS		 8522 /* We have one common special case. We can't do any merging if
8523 the inner code is an ASHIFTRT of a smaller mode. However, if
8524 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8525 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8526 we can convert it to
8527 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8528 This simplifies certain SIGN_EXTEND operations. */
8529 if (code == ASHIFT && first_code == ASHIFTRT
8530 && (GET_MODE_BITSIZE (result_mode)
8531 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8532 {
8533 /* C3 has the low-order C1 bits zero. */
8534
5f4f0e22
CH		 8535 mask = (GET_MODE_MASK (mode)
8536 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
230d793d 8537
5f4f0e22 8538 varop = simplify_and_const_int (NULL_RTX, result_mode,
230d793d 8539 XEXP (varop, 0), mask);
5f4f0e22 8540 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
230d793d
RS		 8541 varop, count);
8542 count = first_count;
8543 code = ASHIFTRT;
8544 continue;
8545 }
8546
d0ab8cd3
RK		 8547 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8548 than C1 high-order bits equal to the sign bit, we can convert
8549 this to either an ASHIFT or a ASHIFTRT depending on the
8550 two counts.
230d793d
RS		 8551
8552 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8553
8554 if (code == ASHIFTRT && first_code == ASHIFT
8555 && GET_MODE (varop) == shift_mode
d0ab8cd3
RK		 8556 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8557 > first_count))
230d793d 8558 {
d0ab8cd3
RK		 8559 count -= first_count;
8560 if (count < 0)
8561 count = - count, code = ASHIFT;
8562 varop = XEXP (varop, 0);
8563 continue;
230d793d
RS		 8564 }
8565
8566 /* There are some cases we can't do. If CODE is ASHIFTRT,
8567 we can only do this if FIRST_CODE is also ASHIFTRT.
8568
8569 We can't do the case when CODE is ROTATE and FIRST_CODE is
8570 ASHIFTRT.
8571
8572 If the mode of this shift is not the mode of the outer shift,
bdaae9a0 8573 we can't do this if either shift is a right shift or ROTATE.
230d793d
RS		 8574
8575 Finally, we can't do any of these if the mode is too wide
8576 unless the codes are the same.
8577
8578 Handle the case where the shift codes are the same
8579 first. */
8580
8581 if (code == first_code)
8582 {
8583 if (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8584 && (code == ASHIFTRT || code == LSHIFTRT
8585 || code == ROTATE))
230d793d
RS		 8586 break;
8587
8588 count += first_count;
8589 varop = XEXP (varop, 0);
8590 continue;
8591 }
8592
8593 if (code == ASHIFTRT
8594 || (code == ROTATE && first_code == ASHIFTRT)
5f4f0e22 8595 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
230d793d 8596 || (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8597 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8598 || first_code == ROTATE
230d793d
RS		 8599 || code == ROTATE)))
8600 break;
8601
8602 /* To compute the mask to apply after the shift, shift the
951553af 8603 nonzero bits of the inner shift the same way the
230d793d
RS		 8604 outer shift will. */
8605
951553af 8606 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
230d793d
RS		 8607
8608 mask_rtx
8609 = simplify_binary_operation (code, result_mode, mask_rtx,
5f4f0e22 8610 GEN_INT (count));
230d793d
RS		 8611
8612 /* Give up if we can't compute an outer operation to use. */
8613 if (mask_rtx == 0
8614 || GET_CODE (mask_rtx) != CONST_INT
8615 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8616 INTVAL (mask_rtx),
8617 result_mode, &complement_p))
8618 break;
8619
8620 /* If the shifts are in the same direction, we add the
8621 counts. Otherwise, we subtract them. */
8622 if ((code == ASHIFTRT || code == LSHIFTRT)
8623 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8624 count += first_count;
8625 else
8626 count -= first_count;
8627
8628 /* If COUNT is positive, the new shift is usually CODE,
8629 except for the two exceptions below, in which case it is
8630 FIRST_CODE. If the count is negative, FIRST_CODE should
8631 always be used */
8632 if (count > 0
8633 && ((first_code == ROTATE && code == ASHIFT)
8634 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8635 code = first_code;
8636 else if (count < 0)
8637 code = first_code, count = - count;
8638
8639 varop = XEXP (varop, 0);
8640 continue;
8641 }
8642
8643 /* If we have (A << B << C) for any shift, we can convert this to
8644 (A << C << B). This wins if A is a constant. Only try this if
8645 B is not a constant. */
8646
8647 else if (GET_CODE (varop) == code
8648 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8649 && 0 != (new
8650 = simplify_binary_operation (code, mode,
8651 XEXP (varop, 0),
5f4f0e22 8652 GEN_INT (count))))
230d793d
RS		 8653 {
8654 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8655 count = 0;
8656 continue;
8657 }
8658 break;
8659
8660 case NOT:
8661 /* Make this fit the case below. */
8662 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5f4f0e22 8663 GEN_INT (GET_MODE_MASK (mode)));
230d793d
RS		 8664 continue;
8665
8666 case IOR:
8667 case AND:
8668 case XOR:
8669 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8670 with C the size of VAROP - 1 and the shift is logical if
8671 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8672 we have an (le X 0) operation. If we have an arithmetic shift
8673 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8674 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8675
8676 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8677 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8678 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8679 && (code == LSHIFTRT || code == ASHIFTRT)
8680 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8681 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8682 {
8683 count = 0;
8684 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8685 const0_rtx);
8686
8687 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8688 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8689
8690 continue;
8691 }
8692
8693 /* If we have (shift (logical)), move the logical to the outside
8694 to allow it to possibly combine with another logical and the
8695 shift to combine with another shift. This also canonicalizes to
8696 what a ZERO_EXTRACT looks like. Also, some machines have
8697 (and (shift)) insns. */
8698
8699 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8700 && (new = simplify_binary_operation (code, result_mode,
8701 XEXP (varop, 1),
5f4f0e22 8702 GEN_INT (count))) != 0
7d171a1e 8703 && GET_CODE(new) == CONST_INT
230d793d
RS		 8704 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8705 INTVAL (new), result_mode, &complement_p))
8706 {
8707 varop = XEXP (varop, 0);
8708 continue;
8709 }
8710
8711 /* If we can't do that, try to simplify the shift in each arm of the
8712 logical expression, make a new logical expression, and apply
8713 the inverse distributive law. */
8714 {
00d4ca1c 8715 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d 8716 XEXP (varop, 0), count);
00d4ca1c 8717 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d
RS		 8718 XEXP (varop, 1), count);
8719
21a64bf1 8720 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
230d793d
RS		 8721 varop = apply_distributive_law (varop);
8722
8723 count = 0;
8724 }
8725 break;
8726
8727 case EQ:
45620ed4 8728 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
230d793d 8729 says that the sign bit can be tested, FOO has mode MODE, C is
45620ed4
RK		 8730 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8731 that may be nonzero. */
8732 if (code == LSHIFTRT
230d793d
RS		 8733 && XEXP (varop, 1) == const0_rtx
8734 && GET_MODE (XEXP (varop, 0)) == result_mode
8735 && count == GET_MODE_BITSIZE (result_mode) - 1
5f4f0e22 8736 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8737 && ((STORE_FLAG_VALUE
5f4f0e22 8738 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
951553af 8739 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8740 && merge_outer_ops (&outer_op, &outer_const, XOR,
8741 (HOST_WIDE_INT) 1, result_mode,
8742 &complement_p))
230d793d
RS		 8743 {
8744 varop = XEXP (varop, 0);
8745 count = 0;
8746 continue;
8747 }
8748 break;
8749
8750 case NEG:
d0ab8cd3
RK		 8751 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8752 than the number of bits in the mode is equivalent to A. */
8753 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
951553af 8754 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
230d793d 8755 {
d0ab8cd3 8756 varop = XEXP (varop, 0);
230d793d
RS		 8757 count = 0;
8758 continue;
8759 }
8760
8761 /* NEG commutes with ASHIFT since it is multiplication. Move the
8762 NEG outside to allow shifts to combine. */
8763 if (code == ASHIFT
5f4f0e22
CH		 8764 && merge_outer_ops (&outer_op, &outer_const, NEG,
8765 (HOST_WIDE_INT) 0, result_mode,
8766 &complement_p))
230d793d
RS		 8767 {
8768 varop = XEXP (varop, 0);
8769 continue;
8770 }
8771 break;
8772
8773 case PLUS:
d0ab8cd3
RK		 8774 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8775 is one less than the number of bits in the mode is
8776 equivalent to (xor A 1). */
230d793d
RS		 8777 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8778 && XEXP (varop, 1) == constm1_rtx
951553af 8779 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8780 && merge_outer_ops (&outer_op, &outer_const, XOR,
8781 (HOST_WIDE_INT) 1, result_mode,
8782 &complement_p))
230d793d
RS		 8783 {
8784 count = 0;
8785 varop = XEXP (varop, 0);
8786 continue;
8787 }
8788
3f508eca 8789 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
951553af 8790 that might be nonzero in BAR are those being shifted out and those
3f508eca
RK		 8791 bits are known zero in FOO, we can replace the PLUS with FOO.
8792 Similarly in the other operand order. This code occurs when
8793 we are computing the size of a variable-size array. */
8794
8795 if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8796 && count < HOST_BITS_PER_WIDE_INT
951553af
RK		 8797 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8798 && (nonzero_bits (XEXP (varop, 1), result_mode)
8799 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
3f508eca
RK		 8800 {
8801 varop = XEXP (varop, 0);
8802 continue;
8803 }
8804 else if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8805 && count < HOST_BITS_PER_WIDE_INT
ac49a949 8806 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
951553af 8807 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
3f508eca 8808 >> count)
951553af
RK		 8809 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8810 & nonzero_bits (XEXP (varop, 1),
3f508eca
RK		 8811 result_mode)))
8812 {
8813 varop = XEXP (varop, 1);
8814 continue;
8815 }
8816
230d793d
RS		 8817 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8818 if (code == ASHIFT
8819 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8820 && (new = simplify_binary_operation (ASHIFT, result_mode,
8821 XEXP (varop, 1),
5f4f0e22 8822 GEN_INT (count))) != 0
7d171a1e 8823 && GET_CODE(new) == CONST_INT
230d793d
RS		 8824 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8825 INTVAL (new), result_mode, &complement_p))
8826 {
8827 varop = XEXP (varop, 0);
8828 continue;
8829 }
8830 break;
8831
8832 case MINUS:
8833 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8834 with C the size of VAROP - 1 and the shift is logical if
8835 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8836 we have a (gt X 0) operation. If the shift is arithmetic with
8837 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8838 we have a (neg (gt X 0)) operation. */
8839
0802d516
RK		 8840 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8841 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
230d793d 8842 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
230d793d
RS		 8843 && (code == LSHIFTRT || code == ASHIFTRT)
8844 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8845 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8846 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8847 {
8848 count = 0;
8849 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8850 const0_rtx);
8851
8852 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8853 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8854
8855 continue;
8856 }
8857 break;
6e0ef100
JC		 8858
8859 case TRUNCATE:
8860 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8861 if the truncate does not affect the value. */
8862 if (code == LSHIFTRT
8863 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8864 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8865 && (INTVAL (XEXP (XEXP (varop, 0), 1))
b577a8ff
JL		 8866 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8867 - GET_MODE_BITSIZE (GET_MODE (varop)))))
6e0ef100
JC		 8868 {
8869 rtx varop_inner = XEXP (varop, 0);
8870
8871 varop_inner = gen_rtx_combine (LSHIFTRT,
8872 GET_MODE (varop_inner),
8873 XEXP (varop_inner, 0),
8874 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8875 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8876 varop_inner);
8877 count = 0;
8878 continue;
8879 }
8880 break;
e9a25f70
JL		 8881
8882 default:
8883 break;
230d793d
RS		 8884 }
8885
8886 break;
8887 }
8888
8889 /* We need to determine what mode to do the shift in. If the shift is
f6789c77
RK		 8890 a right shift or ROTATE, we must always do it in the mode it was
8891 originally done in. Otherwise, we can do it in MODE, the widest mode
8892 encountered. The code we care about is that of the shift that will
8893 actually be done, not the shift that was originally requested. */
8894 shift_mode
8895 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8896 ? result_mode : mode);
230d793d
RS		 8897
8898 /* We have now finished analyzing the shift. The result should be
8899 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8900 OUTER_OP is non-NIL, it is an operation that needs to be applied
8901 to the result of the shift. OUTER_CONST is the relevant constant,
8902 but we must turn off all bits turned off in the shift.
8903
8904 If we were passed a value for X, see if we can use any pieces of
8905 it. If not, make new rtx. */
8906
8907 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8908 && GET_CODE (XEXP (x, 1)) == CONST_INT
8909 && INTVAL (XEXP (x, 1)) == count)
8910 const_rtx = XEXP (x, 1);
8911 else
5f4f0e22 8912 const_rtx = GEN_INT (count);
230d793d
RS		 8913
8914 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8915 && GET_MODE (XEXP (x, 0)) == shift_mode
8916 && SUBREG_REG (XEXP (x, 0)) == varop)
8917 varop = XEXP (x, 0);
8918 else if (GET_MODE (varop) != shift_mode)
8919 varop = gen_lowpart_for_combine (shift_mode, varop);
8920
0f41302f 8921 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 8922 if (GET_CODE (varop) == CLOBBER)
8923 return x ? x : varop;
8924
8925 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8926 if (new != 0)
8927 x = new;
8928 else
8929 {
8930 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8931 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8932
8933 SUBST (XEXP (x, 0), varop);
8934 SUBST (XEXP (x, 1), const_rtx);
8935 }
8936
224eeff2
RK		 8937 /* If we have an outer operation and we just made a shift, it is
8938 possible that we could have simplified the shift were it not
8939 for the outer operation. So try to do the simplification
8940 recursively. */
8941
8942 if (outer_op != NIL && GET_CODE (x) == code
8943 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8944 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8945 INTVAL (XEXP (x, 1)));
8946
230d793d
RS		 8947 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8948 turn off all the bits that the shift would have turned off. */
8949 if (orig_code == LSHIFTRT && result_mode != shift_mode)
5f4f0e22 8950 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
230d793d
RS		 8951 GET_MODE_MASK (result_mode) >> orig_count);
8952
8953 /* Do the remainder of the processing in RESULT_MODE. */
8954 x = gen_lowpart_for_combine (result_mode, x);
8955
8956 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8957 operation. */
8958 if (complement_p)
0c1c8ea6 8959 x = gen_unary (NOT, result_mode, result_mode, x);
230d793d
RS		 8960
8961 if (outer_op != NIL)
8962 {
5f4f0e22 8963 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9fa6d012
TG		 8964 {
8965 int width = GET_MODE_BITSIZE (result_mode);
8966
8967 outer_const &= GET_MODE_MASK (result_mode);
8968
8969 /* If this would be an entire word for the target, but is not for
8970 the host, then sign-extend on the host so that the number will
8971 look the same way on the host that it would on the target.
8972
8973 For example, when building a 64 bit alpha hosted 32 bit sparc
8974 targeted compiler, then we want the 32 bit unsigned value -1 to be
8975 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8976 The later confuses the sparc backend. */
8977
8978 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8979 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8980 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8981 }
230d793d
RS		 8982
8983 if (outer_op == AND)
5f4f0e22 8984 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
230d793d
RS		 8985 else if (outer_op == SET)
8986 /* This means that we have determined that the result is
8987 equivalent to a constant. This should be rare. */
5f4f0e22 8988 x = GEN_INT (outer_const);
230d793d 8989 else if (GET_RTX_CLASS (outer_op) == '1')
0c1c8ea6 8990 x = gen_unary (outer_op, result_mode, result_mode, x);
230d793d 8991 else
5f4f0e22 8992 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
230d793d
RS		 8993 }
8994
8995 return x;
8996}
8997\f
8998/* Like recog, but we receive the address of a pointer to a new pattern.
8999 We try to match the rtx that the pointer points to.
9000 If that fails, we may try to modify or replace the pattern,
9001 storing the replacement into the same pointer object.
9002
9003 Modifications include deletion or addition of CLOBBERs.
9004
9005 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9006 the CLOBBERs are placed.
9007
a29ca9db
RK		 9008 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
9009 we had to add.
9010
230d793d
RS		 9011 The value is the final insn code from the pattern ultimately matched,
9012 or -1. */
9013
9014static int
a29ca9db 9015recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
230d793d
RS		 9016 rtx *pnewpat;
9017 rtx insn;
9018 rtx *pnotes;
a29ca9db 9019 int *padded_scratches;
230d793d
RS		 9020{
9021 register rtx pat = *pnewpat;
9022 int insn_code_number;
9023 int num_clobbers_to_add = 0;
9024 int i;
9025 rtx notes = 0;
9026
a29ca9db
RK		 9027 *padded_scratches = 0;
9028
974f4146
RK		 9029 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9030 we use to indicate that something didn't match. If we find such a
9031 thing, force rejection. */
d96023cf 9032 if (GET_CODE (pat) == PARALLEL)
974f4146 9033 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
d96023cf
RK		 9034 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9035 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
974f4146
RK		 9036 return -1;
9037
230d793d
RS		 9038 /* Is the result of combination a valid instruction? */
9039 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9040
9041 /* If it isn't, there is the possibility that we previously had an insn
9042 that clobbered some register as a side effect, but the combined
9043 insn doesn't need to do that. So try once more without the clobbers
9044 unless this represents an ASM insn. */
9045
9046 if (insn_code_number < 0 && ! check_asm_operands (pat)
9047 && GET_CODE (pat) == PARALLEL)
9048 {
9049 int pos;
9050
9051 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9052 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9053 {
9054 if (i != pos)
9055 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9056 pos++;
9057 }
9058
9059 SUBST_INT (XVECLEN (pat, 0), pos);
9060
9061 if (pos == 1)
9062 pat = XVECEXP (pat, 0, 0);
9063
9064 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9065 }
9066
9067 /* If we had any clobbers to add, make a new pattern than contains
9068 them. Then check to make sure that all of them are dead. */
9069 if (num_clobbers_to_add)
9070 {
38a448ca
RH		 9071 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9072 gen_rtvec (GET_CODE (pat) == PARALLEL
9073 ? XVECLEN (pat, 0) + num_clobbers_to_add
9074 : num_clobbers_to_add + 1));
230d793d
RS		 9075
9076 if (GET_CODE (pat) == PARALLEL)
9077 for (i = 0; i < XVECLEN (pat, 0); i++)
9078 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9079 else
9080 XVECEXP (newpat, 0, 0) = pat;
9081
9082 add_clobbers (newpat, insn_code_number);
9083
9084 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9085 i < XVECLEN (newpat, 0); i++)
9086 {
9087 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9088 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9089 return -1;
a29ca9db
RK		 9090 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
9091 (*padded_scratches)++;
38a448ca
RH		 9092 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9093 XEXP (XVECEXP (newpat, 0, i), 0), notes);
230d793d
RS		 9094 }
9095 pat = newpat;
9096 }
9097
9098 *pnewpat = pat;
9099 *pnotes = notes;
9100
9101 return insn_code_number;
9102}
9103\f
9104/* Like gen_lowpart but for use by combine. In combine it is not possible
9105 to create any new pseudoregs. However, it is safe to create
9106 invalid memory addresses, because combine will try to recognize
9107 them and all they will do is make the combine attempt fail.
9108
9109 If for some reason this cannot do its job, an rtx
9110 (clobber (const_int 0)) is returned.
9111 An insn containing that will not be recognized. */
9112
9113#undef gen_lowpart
9114
9115static rtx
9116gen_lowpart_for_combine (mode, x)
9117 enum machine_mode mode;
9118 register rtx x;
9119{
9120 rtx result;
9121
9122 if (GET_MODE (x) == mode)
9123 return x;
9124
eae957a8
RK		 9125 /* We can only support MODE being wider than a word if X is a
9126 constant integer or has a mode the same size. */
9127
9128 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9129 && ! ((GET_MODE (x) == VOIDmode
9130 && (GET_CODE (x) == CONST_INT
9131 || GET_CODE (x) == CONST_DOUBLE))
9132 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
38a448ca 9133 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9134
9135 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9136 won't know what to do. So we will strip off the SUBREG here and
9137 process normally. */
9138 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9139 {
9140 x = SUBREG_REG (x);
9141 if (GET_MODE (x) == mode)
9142 return x;
9143 }
9144
9145 result = gen_lowpart_common (mode, x);
64bf47a2
RK		 9146 if (result != 0
9147 && GET_CODE (result) == SUBREG
9148 && GET_CODE (SUBREG_REG (result)) == REG
9149 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9150 && (GET_MODE_SIZE (GET_MODE (result))
9151 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
b1f21e0a 9152 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
64bf47a2 9153
230d793d
RS		 9154 if (result)
9155 return result;
9156
9157 if (GET_CODE (x) == MEM)
9158 {
9159 register int offset = 0;
9160 rtx new;
9161
9162 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9163 address. */
9164 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
38a448ca 9165 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9166
9167 /* If we want to refer to something bigger than the original memref,
9168 generate a perverse subreg instead. That will force a reload
9169 of the original memref X. */
9170 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
38a448ca 9171 return gen_rtx_SUBREG (mode, x, 0);
230d793d 9172
f76b9db2
ILT		 9173 if (WORDS_BIG_ENDIAN)
9174 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9175 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9176 if (BYTES_BIG_ENDIAN)
9177 {
9178 /* Adjust the address so that the address-after-the-data is
9179 unchanged. */
9180 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9181 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9182 }
38a448ca 9183 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
230d793d
RS		 9184 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9185 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9186 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9187 return new;
9188 }
9189
9190 /* If X is a comparison operator, rewrite it in a new mode. This
9191 probably won't match, but may allow further simplifications. */
9192 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9193 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9194
9195 /* If we couldn't simplify X any other way, just enclose it in a
9196 SUBREG. Normally, this SUBREG won't match, but some patterns may
a7c99304 9197 include an explicit SUBREG or we may simplify it further in combine. */
230d793d 9198 else
dfbe1b2f
RK		 9199 {
9200 int word = 0;
9201
9202 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9203 word = ((GET_MODE_SIZE (GET_MODE (x))
9204 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9205 / UNITS_PER_WORD);
38a448ca 9206 return gen_rtx_SUBREG (mode, x, word);
dfbe1b2f 9207 }
230d793d
RS		 9208}
9209\f
9210/* Make an rtx expression. This is a subset of gen_rtx and only supports
9211 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9212
9213 If the identical expression was previously in the insn (in the undobuf),
9214 it will be returned. Only if it is not found will a new expression
9215 be made. */
9216
9217/*VARARGS2*/
9218static rtx
4f90e4a0 9219gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
230d793d 9220{
4f90e4a0 9221#ifndef __STDC__
230d793d
RS		 9222 enum rtx_code code;
9223 enum machine_mode mode;
4f90e4a0
RK		 9224#endif
9225 va_list p;
230d793d
RS		 9226 int n_args;
9227 rtx args[3];
b729186a 9228 int j;
230d793d
RS		 9229 char *fmt;
9230 rtx rt;
241cea85 9231 struct undo *undo;
230d793d 9232
4f90e4a0
RK		 9233 VA_START (p, mode);
9234
9235#ifndef __STDC__
230d793d
RS		 9236 code = va_arg (p, enum rtx_code);
9237 mode = va_arg (p, enum machine_mode);
4f90e4a0
RK		 9238#endif
9239
230d793d
RS		 9240 n_args = GET_RTX_LENGTH (code);
9241 fmt = GET_RTX_FORMAT (code);
9242
9243 if (n_args == 0 || n_args > 3)
9244 abort ();
9245
9246 /* Get each arg and verify that it is supposed to be an expression. */
9247 for (j = 0; j < n_args; j++)
9248 {
9249 if (*fmt++ != 'e')
9250 abort ();
9251
9252 args[j] = va_arg (p, rtx);
9253 }
9254
9255 /* See if this is in undobuf. Be sure we don't use objects that came
9256 from another insn; this could produce circular rtl structures. */
9257
241cea85
RK		 9258 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9259 if (!undo->is_int
9260 && GET_CODE (undo->old_contents.r) == code
9261 && GET_MODE (undo->old_contents.r) == mode)
230d793d
RS		 9262 {
9263 for (j = 0; j < n_args; j++)
241cea85 9264 if (XEXP (undo->old_contents.r, j) != args[j])
230d793d
RS		 9265 break;
9266
9267 if (j == n_args)
241cea85 9268 return undo->old_contents.r;
230d793d
RS		 9269 }
9270
9271 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9272 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9273 rt = rtx_alloc (code);
9274 PUT_MODE (rt, mode);
9275 XEXP (rt, 0) = args[0];
9276 if (n_args > 1)
9277 {
9278 XEXP (rt, 1) = args[1];
9279 if (n_args > 2)
9280 XEXP (rt, 2) = args[2];
9281 }
9282 return rt;
9283}
9284
9285/* These routines make binary and unary operations by first seeing if they
9286 fold; if not, a new expression is allocated. */
9287
9288static rtx
9289gen_binary (code, mode, op0, op1)
9290 enum rtx_code code;
9291 enum machine_mode mode;
9292 rtx op0, op1;
9293{
9294 rtx result;
1a26b032
RK		 9295 rtx tem;
9296
9297 if (GET_RTX_CLASS (code) == 'c'
9298 && (GET_CODE (op0) == CONST_INT
9299 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9300 tem = op0, op0 = op1, op1 = tem;
230d793d
RS		 9301
9302 if (GET_RTX_CLASS (code) == '<')
9303 {
9304 enum machine_mode op_mode = GET_MODE (op0);
9210df58
RK		 9305
9306 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
0f41302f 9307 just (REL_OP X Y). */
9210df58
RK		 9308 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9309 {
9310 op1 = XEXP (op0, 1);
9311 op0 = XEXP (op0, 0);
9312 op_mode = GET_MODE (op0);
9313 }
9314
230d793d
RS		 9315 if (op_mode == VOIDmode)
9316 op_mode = GET_MODE (op1);
9317 result = simplify_relational_operation (code, op_mode, op0, op1);
9318 }
9319 else
9320 result = simplify_binary_operation (code, mode, op0, op1);
9321
9322 if (result)
9323 return result;
9324
9325 /* Put complex operands first and constants second. */
9326 if (GET_RTX_CLASS (code) == 'c'
9327 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9328 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9329 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9330 || (GET_CODE (op0) == SUBREG
9331 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9332 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9333 return gen_rtx_combine (code, mode, op1, op0);
9334
e5e809f4
JL		 9335 /* If we are turning off bits already known off in OP0, we need not do
9336 an AND. */
9337 else if (code == AND && GET_CODE (op1) == CONST_INT
9338 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9339 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9340 return op0;
9341
230d793d
RS		 9342 return gen_rtx_combine (code, mode, op0, op1);
9343}
9344
9345static rtx
0c1c8ea6 9346gen_unary (code, mode, op0_mode, op0)
230d793d 9347 enum rtx_code code;
0c1c8ea6 9348 enum machine_mode mode, op0_mode;
230d793d
RS		 9349 rtx op0;
9350{
0c1c8ea6 9351 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
230d793d
RS		 9352
9353 if (result)
9354 return result;
9355
9356 return gen_rtx_combine (code, mode, op0);
9357}
9358\f
9359/* Simplify a comparison between *POP0 and *POP1 where CODE is the
9360 comparison code that will be tested.
9361
9362 The result is a possibly different comparison code to use. *POP0 and
9363 *POP1 may be updated.
9364
9365 It is possible that we might detect that a comparison is either always
9366 true or always false. However, we do not perform general constant
5089e22e 9367 folding in combine, so this knowledge isn't useful. Such tautologies
230d793d
RS		 9368 should have been detected earlier. Hence we ignore all such cases. */
9369
9370static enum rtx_code
9371simplify_comparison (code, pop0, pop1)
9372 enum rtx_code code;
9373 rtx *pop0;
9374 rtx *pop1;
9375{
9376 rtx op0 = *pop0;
9377 rtx op1 = *pop1;
9378 rtx tem, tem1;
9379 int i;
9380 enum machine_mode mode, tmode;
9381
9382 /* Try a few ways of applying the same transformation to both operands. */
9383 while (1)
9384 {
3a19aabc
RK		 9385#ifndef WORD_REGISTER_OPERATIONS
9386 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9387 so check specially. */
9388 if (code != GTU && code != GEU && code != LTU && code != LEU
9389 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9390 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9391 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9392 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9393 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9394 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
ad25ba17 9395 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
3a19aabc
RK		 9396 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9397 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9398 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9399 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9400 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9401 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9402 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9403 && (INTVAL (XEXP (op0, 1))
9404 == (GET_MODE_BITSIZE (GET_MODE (op0))
9405 - (GET_MODE_BITSIZE
9406 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9407 {
9408 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9409 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9410 }
9411#endif
9412
230d793d
RS		 9413 /* If both operands are the same constant shift, see if we can ignore the
9414 shift. We can if the shift is a rotate or if the bits shifted out of
951553af 9415 this shift are known to be zero for both inputs and if the type of
230d793d 9416 comparison is compatible with the shift. */
67232b23
RK		 9417 if (GET_CODE (op0) == GET_CODE (op1)
9418 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9419 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
45620ed4 9420 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
67232b23
RK		 9421 && (code != GT && code != LT && code != GE && code != LE))
9422 || (GET_CODE (op0) == ASHIFTRT
9423 && (code != GTU && code != LTU
9424 && code != GEU && code != GEU)))
9425 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9426 && INTVAL (XEXP (op0, 1)) >= 0
9427 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9428 && XEXP (op0, 1) == XEXP (op1, 1))
230d793d
RS		 9429 {
9430 enum machine_mode mode = GET_MODE (op0);
5f4f0e22 9431 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9432 int shift_count = INTVAL (XEXP (op0, 1));
9433
9434 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9435 mask &= (mask >> shift_count) << shift_count;
45620ed4 9436 else if (GET_CODE (op0) == ASHIFT)
230d793d
RS		 9437 mask = (mask & (mask << shift_count)) >> shift_count;
9438
951553af
RK		 9439 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9440 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
230d793d
RS		 9441 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9442 else
9443 break;
9444 }
9445
9446 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9447 SUBREGs are of the same mode, and, in both cases, the AND would
9448 be redundant if the comparison was done in the narrower mode,
9449 do the comparison in the narrower mode (e.g., we are AND'ing with 1
951553af
RK		 9450 and the operand's possibly nonzero bits are 0xffffff01; in that case
9451 if we only care about QImode, we don't need the AND). This case
9452 occurs if the output mode of an scc insn is not SImode and
7e4dc511
RK		 9453 STORE_FLAG_VALUE == 1 (e.g., the 386).
9454
9455 Similarly, check for a case where the AND's are ZERO_EXTEND
9456 operations from some narrower mode even though a SUBREG is not
9457 present. */
230d793d
RS		 9458
9459 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9460 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7e4dc511 9461 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
230d793d 9462 {
7e4dc511
RK		 9463 rtx inner_op0 = XEXP (op0, 0);
9464 rtx inner_op1 = XEXP (op1, 0);
9465 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9466 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9467 int changed = 0;
9468
9469 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9470 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9471 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9472 && (GET_MODE (SUBREG_REG (inner_op0))
9473 == GET_MODE (SUBREG_REG (inner_op1)))
729a2bc6 9474 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
7e4dc511 9475 <= HOST_BITS_PER_WIDE_INT)
01c82bbb 9476 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
729a2bc6 9477 GET_MODE (SUBREG_REG (inner_op0)))))
01c82bbb
RK		 9478 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9479 GET_MODE (SUBREG_REG (inner_op1))))))
7e4dc511
RK		 9480 {
9481 op0 = SUBREG_REG (inner_op0);
9482 op1 = SUBREG_REG (inner_op1);
9483
9484 /* The resulting comparison is always unsigned since we masked
0f41302f 9485 off the original sign bit. */
7e4dc511
RK		 9486 code = unsigned_condition (code);
9487
9488 changed = 1;
9489 }
230d793d 9490
7e4dc511
RK		 9491 else if (c0 == c1)
9492 for (tmode = GET_CLASS_NARROWEST_MODE
9493 (GET_MODE_CLASS (GET_MODE (op0)));
9494 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9495 if (c0 == GET_MODE_MASK (tmode))
9496 {
9497 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9498 op1 = gen_lowpart_for_combine (tmode, inner_op1);
66415c8b 9499 code = unsigned_condition (code);
7e4dc511
RK		 9500 changed = 1;
9501 break;
9502 }
9503
9504 if (! changed)
9505 break;
230d793d 9506 }
3a19aabc 9507
ad25ba17
RK		 9508 /* If both operands are NOT, we can strip off the outer operation
9509 and adjust the comparison code for swapped operands; similarly for
9510 NEG, except that this must be an equality comparison. */
9511 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9512 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9513 && (code == EQ || code == NE)))
9514 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
3a19aabc 9515
230d793d
RS		 9516 else
9517 break;
9518 }
9519
9520 /* If the first operand is a constant, swap the operands and adjust the
3aceff0d
RK		 9521 comparison code appropriately, but don't do this if the second operand
9522 is already a constant integer. */
9523 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
230d793d
RS		 9524 {
9525 tem = op0, op0 = op1, op1 = tem;
9526 code = swap_condition (code);
9527 }
9528
9529 /* We now enter a loop during which we will try to simplify the comparison.
9530 For the most part, we only are concerned with comparisons with zero,
9531 but some things may really be comparisons with zero but not start
9532 out looking that way. */
9533
9534 while (GET_CODE (op1) == CONST_INT)
9535 {
9536 enum machine_mode mode = GET_MODE (op0);
9537 int mode_width = GET_MODE_BITSIZE (mode);
5f4f0e22 9538 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9539 int equality_comparison_p;
9540 int sign_bit_comparison_p;
9541 int unsigned_comparison_p;
5f4f0e22 9542 HOST_WIDE_INT const_op;
230d793d
RS		 9543
9544 /* We only want to handle integral modes. This catches VOIDmode,
9545 CCmode, and the floating-point modes. An exception is that we
9546 can handle VOIDmode if OP0 is a COMPARE or a comparison
9547 operation. */
9548
9549 if (GET_MODE_CLASS (mode) != MODE_INT
9550 && ! (mode == VOIDmode
9551 && (GET_CODE (op0) == COMPARE
9552 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9553 break;
9554
9555 /* Get the constant we are comparing against and turn off all bits
9556 not on in our mode. */
9557 const_op = INTVAL (op1);
5f4f0e22 9558 if (mode_width <= HOST_BITS_PER_WIDE_INT)
4803a34a 9559 const_op &= mask;
230d793d
RS		 9560
9561 /* If we are comparing against a constant power of two and the value
951553af 9562 being compared can only have that single bit nonzero (e.g., it was
230d793d
RS		 9563 `and'ed with that bit), we can replace this with a comparison
9564 with zero. */
9565 if (const_op
9566 && (code == EQ || code == NE || code == GE || code == GEU
9567 || code == LT || code == LTU)
5f4f0e22 9568 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 9569 && exact_log2 (const_op) >= 0
951553af 9570 && nonzero_bits (op0, mode) == const_op)
230d793d
RS		 9571 {
9572 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9573 op1 = const0_rtx, const_op = 0;
9574 }
9575
d0ab8cd3
RK		 9576 /* Similarly, if we are comparing a value known to be either -1 or
9577 0 with -1, change it to the opposite comparison against zero. */
9578
9579 if (const_op == -1
9580 && (code == EQ || code == NE || code == GT || code == LE
9581 || code == GEU || code == LTU)
9582 && num_sign_bit_copies (op0, mode) == mode_width)
9583 {
9584 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9585 op1 = const0_rtx, const_op = 0;
9586 }
9587
230d793d 9588 /* Do some canonicalizations based on the comparison code. We prefer
4803a34a
RK		 9589 comparisons against zero and then prefer equality comparisons.
9590 If we can reduce the size of a constant, we will do that too. */
230d793d
RS		 9591
9592 switch (code)
9593 {
9594 case LT:
4803a34a
RK		 9595 /* < C is equivalent to <= (C - 1) */
9596 if (const_op > 0)
230d793d 9597 {
4803a34a 9598 const_op -= 1;
5f4f0e22 9599 op1 = GEN_INT (const_op);
230d793d
RS		 9600 code = LE;
9601 /* ... fall through to LE case below. */
9602 }
9603 else
9604 break;
9605
9606 case LE:
4803a34a
RK		 9607 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9608 if (const_op < 0)
9609 {
9610 const_op += 1;
5f4f0e22 9611 op1 = GEN_INT (const_op);
4803a34a
RK		 9612 code = LT;
9613 }
230d793d
RS		 9614
9615 /* If we are doing a <= 0 comparison on a value known to have
9616 a zero sign bit, we can replace this with == 0. */
9617 else if (const_op == 0
5f4f0e22 9618 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9619 && (nonzero_bits (op0, mode)
5f4f0e22 9620 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9621 code = EQ;
9622 break;
9623
9624 case GE:
0f41302f 9625 /* >= C is equivalent to > (C - 1). */
4803a34a 9626 if (const_op > 0)
230d793d 9627 {
4803a34a 9628 const_op -= 1;
5f4f0e22 9629 op1 = GEN_INT (const_op);
230d793d
RS		 9630 code = GT;
9631 /* ... fall through to GT below. */
9632 }
9633 else
9634 break;
9635
9636 case GT:
4803a34a
RK		 9637 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9638 if (const_op < 0)
9639 {
9640 const_op += 1;
5f4f0e22 9641 op1 = GEN_INT (const_op);
4803a34a
RK		 9642 code = GE;
9643 }
230d793d
RS		 9644
9645 /* If we are doing a > 0 comparison on a value known to have
9646 a zero sign bit, we can replace this with != 0. */
9647 else if (const_op == 0
5f4f0e22 9648 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9649 && (nonzero_bits (op0, mode)
5f4f0e22 9650 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9651 code = NE;
9652 break;
9653
230d793d 9654 case LTU:
4803a34a
RK		 9655 /* < C is equivalent to <= (C - 1). */
9656 if (const_op > 0)
9657 {
9658 const_op -= 1;
5f4f0e22 9659 op1 = GEN_INT (const_op);
4803a34a 9660 code = LEU;
0f41302f 9661 /* ... fall through ... */
4803a34a 9662 }
d0ab8cd3
RK		 9663
9664 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
f77aada2
JW		 9665 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9666 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9667 {
9668 const_op = 0, op1 = const0_rtx;
9669 code = GE;
9670 break;
9671 }
4803a34a
RK		 9672 else
9673 break;
230d793d
RS		 9674
9675 case LEU:
9676 /* unsigned <= 0 is equivalent to == 0 */
9677 if (const_op == 0)
9678 code = EQ;
d0ab8cd3 9679
0f41302f 9680 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
f77aada2
JW		 9681 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9682 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9683 {
9684 const_op = 0, op1 = const0_rtx;
9685 code = GE;
9686 }
230d793d
RS		 9687 break;
9688
4803a34a
RK		 9689 case GEU:
9690 /* >= C is equivalent to < (C - 1). */
9691 if (const_op > 1)
9692 {
9693 const_op -= 1;
5f4f0e22 9694 op1 = GEN_INT (const_op);
4803a34a 9695 code = GTU;
0f41302f 9696 /* ... fall through ... */
4803a34a 9697 }
d0ab8cd3
RK		 9698
9699 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
f77aada2
JW		 9700 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9701 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9702 {
9703 const_op = 0, op1 = const0_rtx;
9704 code = LT;
8b2e69e1 9705 break;
d0ab8cd3 9706 }
4803a34a
RK		 9707 else
9708 break;
9709
230d793d
RS		 9710 case GTU:
9711 /* unsigned > 0 is equivalent to != 0 */
9712 if (const_op == 0)
9713 code = NE;
d0ab8cd3
RK		 9714
9715 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
f77aada2
JW		 9716 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9717 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9718 {
9719 const_op = 0, op1 = const0_rtx;
9720 code = LT;
9721 }
230d793d 9722 break;
e9a25f70
JL		 9723
9724 default:
9725 break;
230d793d
RS		 9726 }
9727
9728 /* Compute some predicates to simplify code below. */
9729
9730 equality_comparison_p = (code == EQ || code == NE);
9731 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9732 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9733 || code == LEU);
9734
6139ff20
RK		 9735 /* If this is a sign bit comparison and we can do arithmetic in
9736 MODE, say that we will only be needing the sign bit of OP0. */
9737 if (sign_bit_comparison_p
9738 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9739 op0 = force_to_mode (op0, mode,
9740 ((HOST_WIDE_INT) 1
9741 << (GET_MODE_BITSIZE (mode) - 1)),
e3d616e3 9742 NULL_RTX, 0);
6139ff20 9743
230d793d
RS		 9744 /* Now try cases based on the opcode of OP0. If none of the cases
9745 does a "continue", we exit this loop immediately after the
9746 switch. */
9747
9748 switch (GET_CODE (op0))
9749 {
9750 case ZERO_EXTRACT:
9751 /* If we are extracting a single bit from a variable position in
9752 a constant that has only a single bit set and are comparing it
9753 with zero, we can convert this into an equality comparison
d7cd794f 9754 between the position and the location of the single bit. */
230d793d 9755
230d793d
RS		 9756 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9757 && XEXP (op0, 1) == const1_rtx
9758 && equality_comparison_p && const_op == 0
d7cd794f 9759 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
230d793d 9760 {
f76b9db2 9761 if (BITS_BIG_ENDIAN)
d7cd794f 9762#ifdef HAVE_extzv
f76b9db2
ILT		 9763 i = (GET_MODE_BITSIZE
9764 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
d7cd794f
RK		 9765#else
9766 i = BITS_PER_WORD - 1 - i;
230d793d
RS		 9767#endif
9768
9769 op0 = XEXP (op0, 2);
5f4f0e22 9770 op1 = GEN_INT (i);
230d793d
RS		 9771 const_op = i;
9772
9773 /* Result is nonzero iff shift count is equal to I. */
9774 code = reverse_condition (code);
9775 continue;
9776 }
230d793d 9777
0f41302f 9778 /* ... fall through ... */
230d793d
RS		 9779
9780 case SIGN_EXTRACT:
9781 tem = expand_compound_operation (op0);
9782 if (tem != op0)
9783 {
9784 op0 = tem;
9785 continue;
9786 }
9787 break;
9788
9789 case NOT:
9790 /* If testing for equality, we can take the NOT of the constant. */
9791 if (equality_comparison_p
9792 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9793 {
9794 op0 = XEXP (op0, 0);
9795 op1 = tem;
9796 continue;
9797 }
9798
9799 /* If just looking at the sign bit, reverse the sense of the
9800 comparison. */
9801 if (sign_bit_comparison_p)
9802 {
9803 op0 = XEXP (op0, 0);
9804 code = (code == GE ? LT : GE);
9805 continue;
9806 }
9807 break;
9808
9809 case NEG:
9810 /* If testing for equality, we can take the NEG of the constant. */
9811 if (equality_comparison_p
9812 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9813 {
9814 op0 = XEXP (op0, 0);
9815 op1 = tem;
9816 continue;
9817 }
9818
9819 /* The remaining cases only apply to comparisons with zero. */
9820 if (const_op != 0)
9821 break;
9822
9823 /* When X is ABS or is known positive,
9824 (neg X) is < 0 if and only if X != 0. */
9825
9826 if (sign_bit_comparison_p
9827 && (GET_CODE (XEXP (op0, 0)) == ABS
5f4f0e22 9828 || (mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9829 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 9830 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
230d793d
RS		 9831 {
9832 op0 = XEXP (op0, 0);
9833 code = (code == LT ? NE : EQ);
9834 continue;
9835 }
9836
3bed8141 9837 /* If we have NEG of something whose two high-order bits are the
0f41302f 9838 same, we know that "(-a) < 0" is equivalent to "a > 0". */
3bed8141 9839 if (num_sign_bit_copies (op0, mode) >= 2)
230d793d
RS		 9840 {
9841 op0 = XEXP (op0, 0);
9842 code = swap_condition (code);
9843 continue;
9844 }
9845 break;
9846
9847 case ROTATE:
9848 /* If we are testing equality and our count is a constant, we
9849 can perform the inverse operation on our RHS. */
9850 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9851 && (tem = simplify_binary_operation (ROTATERT, mode,
9852 op1, XEXP (op0, 1))) != 0)
9853 {
9854 op0 = XEXP (op0, 0);
9855 op1 = tem;
9856 continue;
9857 }
9858
9859 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9860 a particular bit. Convert it to an AND of a constant of that
9861 bit. This will be converted into a ZERO_EXTRACT. */
9862 if (const_op == 0 && sign_bit_comparison_p
9863 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 9864 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 9865 {
5f4f0e22
CH		 9866 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9867 ((HOST_WIDE_INT) 1
9868 << (mode_width - 1
9869 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 9870 code = (code == LT ? NE : EQ);
9871 continue;
9872 }
9873
0f41302f 9874 /* ... fall through ... */
230d793d
RS		 9875
9876 case ABS:
9877 /* ABS is ignorable inside an equality comparison with zero. */
9878 if (const_op == 0 && equality_comparison_p)
9879 {
9880 op0 = XEXP (op0, 0);
9881 continue;
9882 }
9883 break;
9884
9885
9886 case SIGN_EXTEND:
9887 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9888 to (compare FOO CONST) if CONST fits in FOO's mode and we
9889 are either testing inequality or have an unsigned comparison
9890 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9891 if (! unsigned_comparison_p
9892 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9893 <= HOST_BITS_PER_WIDE_INT)
9894 && ((unsigned HOST_WIDE_INT) const_op
9895 < (((HOST_WIDE_INT) 1
9896 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
230d793d
RS		 9897 {
9898 op0 = XEXP (op0, 0);
9899 continue;
9900 }
9901 break;
9902
9903 case SUBREG:
a687e897 9904 /* Check for the case where we are comparing A - C1 with C2,
abc95ed3 9905 both constants are smaller than 1/2 the maximum positive
a687e897
RK		 9906 value in MODE, and the comparison is equality or unsigned.
9907 In that case, if A is either zero-extended to MODE or has
9908 sufficient sign bits so that the high-order bit in MODE
9909 is a copy of the sign in the inner mode, we can prove that it is
9910 safe to do the operation in the wider mode. This simplifies
9911 many range checks. */
9912
9913 if (mode_width <= HOST_BITS_PER_WIDE_INT
9914 && subreg_lowpart_p (op0)
9915 && GET_CODE (SUBREG_REG (op0)) == PLUS
9916 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9917 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9918 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9919 < GET_MODE_MASK (mode) / 2)
adb7a1cb 9920 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
951553af
RK		 9921 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9922 GET_MODE (SUBREG_REG (op0)))
a687e897
RK		 9923 & ~ GET_MODE_MASK (mode))
9924 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9925 GET_MODE (SUBREG_REG (op0)))
9926 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9927 - GET_MODE_BITSIZE (mode)))))
9928 {
9929 op0 = SUBREG_REG (op0);
9930 continue;
9931 }
9932
fe0cf571
RK		 9933 /* If the inner mode is narrower and we are extracting the low part,
9934 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9935 if (subreg_lowpart_p (op0)
89f1c7f2
RS		 9936 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9937 /* Fall through */ ;
9938 else
230d793d
RS		 9939 break;
9940
0f41302f 9941 /* ... fall through ... */
230d793d
RS		 9942
9943 case ZERO_EXTEND:
9944 if ((unsigned_comparison_p || equality_comparison_p)
9945 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9946 <= HOST_BITS_PER_WIDE_INT)
9947 && ((unsigned HOST_WIDE_INT) const_op
230d793d
RS		 9948 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9949 {
9950 op0 = XEXP (op0, 0);
9951 continue;
9952 }
9953 break;
9954
9955 case PLUS:
20fdd649 9956 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
5089e22e 9957 this for equality comparisons due to pathological cases involving
230d793d 9958 overflows. */
20fdd649
RK		 9959 if (equality_comparison_p
9960 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9961 op1, XEXP (op0, 1))))
230d793d
RS		 9962 {
9963 op0 = XEXP (op0, 0);
9964 op1 = tem;
9965 continue;
9966 }
9967
9968 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9969 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9970 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9971 {
9972 op0 = XEXP (XEXP (op0, 0), 0);
9973 code = (code == LT ? EQ : NE);
9974 continue;
9975 }
9976 break;
9977
9978 case MINUS:
20fdd649
RK		 9979 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9980 (eq B (minus A C)), whichever simplifies. We can only do
9981 this for equality comparisons due to pathological cases involving
9982 overflows. */
9983 if (equality_comparison_p
9984 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9985 XEXP (op0, 1), op1)))
9986 {
9987 op0 = XEXP (op0, 0);
9988 op1 = tem;
9989 continue;
9990 }
9991
9992 if (equality_comparison_p
9993 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9994 XEXP (op0, 0), op1)))
9995 {
9996 op0 = XEXP (op0, 1);
9997 op1 = tem;
9998 continue;
9999 }
10000
230d793d
RS		 10001 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10002 of bits in X minus 1, is one iff X > 0. */
10003 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10004 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10005 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10006 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10007 {
10008 op0 = XEXP (op0, 1);
10009 code = (code == GE ? LE : GT);
10010 continue;
10011 }
10012 break;
10013
10014 case XOR:
10015 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10016 if C is zero or B is a constant. */
10017 if (equality_comparison_p
10018 && 0 != (tem = simplify_binary_operation (XOR, mode,
10019 XEXP (op0, 1), op1)))
10020 {
10021 op0 = XEXP (op0, 0);
10022 op1 = tem;
10023 continue;
10024 }
10025 break;
10026
10027 case EQ: case NE:
10028 case LT: case LTU: case LE: case LEU:
10029 case GT: case GTU: case GE: case GEU:
10030 /* We can't do anything if OP0 is a condition code value, rather
10031 than an actual data value. */
10032 if (const_op != 0
10033#ifdef HAVE_cc0
10034 || XEXP (op0, 0) == cc0_rtx
10035#endif
10036 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10037 break;
10038
10039 /* Get the two operands being compared. */
10040 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10041 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10042 else
10043 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10044
10045 /* Check for the cases where we simply want the result of the
10046 earlier test or the opposite of that result. */
10047 if (code == NE
10048 || (code == EQ && reversible_comparison_p (op0))
5f4f0e22 10049 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
3f508eca 10050 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
230d793d 10051 && (STORE_FLAG_VALUE
5f4f0e22
CH		 10052 & (((HOST_WIDE_INT) 1
10053 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
230d793d
RS		 10054 && (code == LT
10055 || (code == GE && reversible_comparison_p (op0)))))
10056 {
10057 code = (code == LT || code == NE
10058 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10059 op0 = tem, op1 = tem1;
10060 continue;
10061 }
10062 break;
10063
10064 case IOR:
10065 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10066 iff X <= 0. */
10067 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10068 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10069 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10070 {
10071 op0 = XEXP (op0, 1);
10072 code = (code == GE ? GT : LE);
10073 continue;
10074 }
10075 break;
10076
10077 case AND:
10078 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10079 will be converted to a ZERO_EXTRACT later. */
10080 if (const_op == 0 && equality_comparison_p
45620ed4 10081 && GET_CODE (XEXP (op0, 0)) == ASHIFT
230d793d
RS		 10082 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10083 {
10084 op0 = simplify_and_const_int
10085 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10086 XEXP (op0, 1),
10087 XEXP (XEXP (op0, 0), 1)),
5f4f0e22 10088 (HOST_WIDE_INT) 1);
230d793d
RS		 10089 continue;
10090 }
10091
10092 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10093 zero and X is a comparison and C1 and C2 describe only bits set
10094 in STORE_FLAG_VALUE, we can compare with X. */
10095 if (const_op == 0 && equality_comparison_p
5f4f0e22 10096 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 10097 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10098 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10099 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10100 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
5f4f0e22 10101 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 10102 {
10103 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10104 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10105 if ((~ STORE_FLAG_VALUE & mask) == 0
10106 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10107 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10108 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10109 {
10110 op0 = XEXP (XEXP (op0, 0), 0);
10111 continue;
10112 }
10113 }
10114
10115 /* If we are doing an equality comparison of an AND of a bit equal
10116 to the sign bit, replace this with a LT or GE comparison of
10117 the underlying value. */
10118 if (equality_comparison_p
10119 && const_op == 0
10120 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10121 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 10122 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
5f4f0e22 10123 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
230d793d
RS		 10124 {
10125 op0 = XEXP (op0, 0);
10126 code = (code == EQ ? GE : LT);
10127 continue;
10128 }
10129
10130 /* If this AND operation is really a ZERO_EXTEND from a narrower
10131 mode, the constant fits within that mode, and this is either an
10132 equality or unsigned comparison, try to do this comparison in
10133 the narrower mode. */
10134 if ((equality_comparison_p || unsigned_comparison_p)
10135 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10136 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10137 & GET_MODE_MASK (mode))
10138 + 1)) >= 0
10139 && const_op >> i == 0
10140 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10141 {
10142 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10143 continue;
10144 }
e5e809f4
JL		 10145
10146 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10147 in both M1 and M2 and the SUBREG is either paradoxical or
10148 represents the low part, permute the SUBREG and the AND and
10149 try again. */
10150 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10151 && ((mode_width
10152 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
9ec36da5
JL		 10153#ifdef WORD_REGISTER_OPERATIONS
10154 || subreg_lowpart_p (XEXP (op0, 0))
10155#endif
10156 )
e5e809f4
JL		 10157 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10158 && mode_width <= HOST_BITS_PER_WIDE_INT
10159 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10160 <= HOST_BITS_PER_WIDE_INT)
10161 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10162 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
9ec36da5
JL		 10163 & INTVAL (XEXP (op0, 1)))
10164 && INTVAL (XEXP (op0, 1)) != mask
10165 && (INTVAL (XEXP (op0, 1))
10166 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
e5e809f4
JL		 10167
10168 {
10169 op0
10170 = gen_lowpart_for_combine
10171 (mode,
10172 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10173 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10174 continue;
10175 }
10176
230d793d
RS		 10177 break;
10178
10179 case ASHIFT:
45620ed4 10180 /* If we have (compare (ashift FOO N) (const_int C)) and
230d793d 10181 the high order N bits of FOO (N+1 if an inequality comparison)
951553af 10182 are known to be zero, we can do this by comparing FOO with C
230d793d
RS		 10183 shifted right N bits so long as the low-order N bits of C are
10184 zero. */
10185 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10186 && INTVAL (XEXP (op0, 1)) >= 0
10187 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
5f4f0e22
CH		 10188 < HOST_BITS_PER_WIDE_INT)
10189 && ((const_op
34785d05 10190 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
5f4f0e22 10191 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10192 && (nonzero_bits (XEXP (op0, 0), mode)
230d793d
RS		 10193 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10194 + ! equality_comparison_p))) == 0)
10195 {
10196 const_op >>= INTVAL (XEXP (op0, 1));
5f4f0e22 10197 op1 = GEN_INT (const_op);
230d793d
RS		 10198 op0 = XEXP (op0, 0);
10199 continue;
10200 }
10201
dfbe1b2f 10202 /* If we are doing a sign bit comparison, it means we are testing
230d793d 10203 a particular bit. Convert it to the appropriate AND. */
dfbe1b2f 10204 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10205 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 10206 {
5f4f0e22
CH		 10207 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10208 ((HOST_WIDE_INT) 1
10209 << (mode_width - 1
10210 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 10211 code = (code == LT ? NE : EQ);
10212 continue;
10213 }
dfbe1b2f
RK		 10214
10215 /* If this an equality comparison with zero and we are shifting
10216 the low bit to the sign bit, we can convert this to an AND of the
10217 low-order bit. */
10218 if (const_op == 0 && equality_comparison_p
10219 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10220 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10221 {
5f4f0e22
CH		 10222 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10223 (HOST_WIDE_INT) 1);
dfbe1b2f
RK		 10224 continue;
10225 }
230d793d
RS		 10226 break;
10227
10228 case ASHIFTRT:
d0ab8cd3
RK		 10229 /* If this is an equality comparison with zero, we can do this
10230 as a logical shift, which might be much simpler. */
10231 if (equality_comparison_p && const_op == 0
10232 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10233 {
10234 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10235 XEXP (op0, 0),
10236 INTVAL (XEXP (op0, 1)));
10237 continue;
10238 }
10239
230d793d
RS		 10240 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10241 do the comparison in a narrower mode. */
10242 if (! unsigned_comparison_p
10243 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10244 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10245 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10246 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
22331794 10247 MODE_INT, 1)) != BLKmode
5f4f0e22
CH		 10248 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10249 || ((unsigned HOST_WIDE_INT) - const_op
10250 <= GET_MODE_MASK (tmode))))
230d793d
RS		 10251 {
10252 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10253 continue;
10254 }
10255
0f41302f 10256 /* ... fall through ... */
230d793d
RS		 10257 case LSHIFTRT:
10258 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
951553af 10259 the low order N bits of FOO are known to be zero, we can do this
230d793d
RS		 10260 by comparing FOO with C shifted left N bits so long as no
10261 overflow occurs. */
10262 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10263 && INTVAL (XEXP (op0, 1)) >= 0
5f4f0e22
CH		 10264 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10265 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10266 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 10267 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
230d793d
RS		 10268 && (const_op == 0
10269 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10270 < mode_width)))
10271 {
10272 const_op <<= INTVAL (XEXP (op0, 1));
5f4f0e22 10273 op1 = GEN_INT (const_op);
230d793d
RS		 10274 op0 = XEXP (op0, 0);
10275 continue;
10276 }
10277
10278 /* If we are using this shift to extract just the sign bit, we
10279 can replace this with an LT or GE comparison. */
10280 if (const_op == 0
10281 && (equality_comparison_p || sign_bit_comparison_p)
10282 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10283 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10284 {
10285 op0 = XEXP (op0, 0);
10286 code = (code == NE || code == GT ? LT : GE);
10287 continue;
10288 }
10289 break;
e9a25f70
JL		 10290
10291 default:
10292 break;
230d793d
RS		 10293 }
10294
10295 break;
10296 }
10297
10298 /* Now make any compound operations involved in this comparison. Then,
76d31c63 10299 check for an outmost SUBREG on OP0 that is not doing anything or is
230d793d
RS		 10300 paradoxical. The latter case can only occur when it is known that the
10301 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10302 We can never remove a SUBREG for a non-equality comparison because the
10303 sign bit is in a different place in the underlying object. */
10304
10305 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10306 op1 = make_compound_operation (op1, SET);
10307
10308 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10309 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10310 && (code == NE || code == EQ)
10311 && ((GET_MODE_SIZE (GET_MODE (op0))
10312 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10313 {
10314 op0 = SUBREG_REG (op0);
10315 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10316 }
10317
10318 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10319 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10320 && (code == NE || code == EQ)
ac49a949
RS		 10321 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10322 <= HOST_BITS_PER_WIDE_INT)
951553af 10323 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10324 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10325 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10326 op1),
951553af 10327 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10328 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10329 op0 = SUBREG_REG (op0), op1 = tem;
10330
10331 /* We now do the opposite procedure: Some machines don't have compare
10332 insns in all modes. If OP0's mode is an integer mode smaller than a
10333 word and we can't do a compare in that mode, see if there is a larger
a687e897
RK		 10334 mode for which we can do the compare. There are a number of cases in
10335 which we can use the wider mode. */
230d793d
RS		 10336
10337 mode = GET_MODE (op0);
10338 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10339 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10340 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10341 for (tmode = GET_MODE_WIDER_MODE (mode);
5f4f0e22
CH		 10342 (tmode != VOIDmode
10343 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
230d793d 10344 tmode = GET_MODE_WIDER_MODE (tmode))
a687e897 10345 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
230d793d 10346 {
951553af 10347 /* If the only nonzero bits in OP0 and OP1 are those in the
a687e897
RK		 10348 narrower mode and this is an equality or unsigned comparison,
10349 we can use the wider mode. Similarly for sign-extended
7e4dc511 10350 values, in which case it is true for all comparisons. */
a687e897
RK		 10351 if (((code == EQ || code == NE
10352 || code == GEU || code == GTU || code == LEU || code == LTU)
951553af
RK		 10353 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10354 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
7e4dc511
RK		 10355 || ((num_sign_bit_copies (op0, tmode)
10356 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
a687e897 10357 && (num_sign_bit_copies (op1, tmode)
58744483 10358 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
a687e897
RK		 10359 {
10360 op0 = gen_lowpart_for_combine (tmode, op0);
10361 op1 = gen_lowpart_for_combine (tmode, op1);
10362 break;
10363 }
230d793d 10364
a687e897
RK		 10365 /* If this is a test for negative, we can make an explicit
10366 test of the sign bit. */
10367
10368 if (op1 == const0_rtx && (code == LT || code == GE)
10369 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d 10370 {
a687e897
RK		 10371 op0 = gen_binary (AND, tmode,
10372 gen_lowpart_for_combine (tmode, op0),
5f4f0e22
CH		 10373 GEN_INT ((HOST_WIDE_INT) 1
10374 << (GET_MODE_BITSIZE (mode) - 1)));
230d793d 10375 code = (code == LT) ? NE : EQ;
a687e897 10376 break;
230d793d 10377 }
230d793d
RS		 10378 }
10379
b7a775b2
RK		 10380#ifdef CANONICALIZE_COMPARISON
10381 /* If this machine only supports a subset of valid comparisons, see if we
10382 can convert an unsupported one into a supported one. */
10383 CANONICALIZE_COMPARISON (code, op0, op1);
10384#endif
10385
230d793d
RS		 10386 *pop0 = op0;
10387 *pop1 = op1;
10388
10389 return code;
10390}
10391\f
10392/* Return 1 if we know that X, a comparison operation, is not operating
10393 on a floating-point value or is EQ or NE, meaning that we can safely
10394 reverse it. */
10395
10396static int
10397reversible_comparison_p (x)
10398 rtx x;
10399{
10400 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e 10401 || flag_fast_math
230d793d
RS		 10402 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10403 return 1;
10404
10405 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10406 {
10407 case MODE_INT:
3ad2180a
RK		 10408 case MODE_PARTIAL_INT:
10409 case MODE_COMPLEX_INT:
230d793d
RS		 10410 return 1;
10411
10412 case MODE_CC:
9210df58
RK		 10413 /* If the mode of the condition codes tells us that this is safe,
10414 we need look no further. */
10415 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10416 return 1;
10417
10418 /* Otherwise try and find where the condition codes were last set and
10419 use that. */
230d793d
RS		 10420 x = get_last_value (XEXP (x, 0));
10421 return (x && GET_CODE (x) == COMPARE
3ad2180a 10422 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
e9a25f70
JL		 10423
10424 default:
10425 return 0;
230d793d 10426 }
230d793d
RS		 10427}
10428\f
10429/* Utility function for following routine. Called when X is part of a value
10430 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10431 for each register mentioned. Similar to mention_regs in cse.c */
10432
10433static void
10434update_table_tick (x)
10435 rtx x;
10436{
10437 register enum rtx_code code = GET_CODE (x);
10438 register char *fmt = GET_RTX_FORMAT (code);
10439 register int i;
10440
10441 if (code == REG)
10442 {
10443 int regno = REGNO (x);
10444 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10445 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10446
10447 for (i = regno; i < endregno; i++)
10448 reg_last_set_table_tick[i] = label_tick;
10449
10450 return;
10451 }
10452
10453 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10454 /* Note that we can't have an "E" in values stored; see
10455 get_last_value_validate. */
10456 if (fmt[i] == 'e')
10457 update_table_tick (XEXP (x, i));
10458}
10459
10460/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10461 are saying that the register is clobbered and we no longer know its
7988fd36
RK		 10462 value. If INSN is zero, don't update reg_last_set; this is only permitted
10463 with VALUE also zero and is used to invalidate the register. */
230d793d
RS		 10464
10465static void
10466record_value_for_reg (reg, insn, value)
10467 rtx reg;
10468 rtx insn;
10469 rtx value;
10470{
10471 int regno = REGNO (reg);
10472 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10473 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10474 int i;
10475
10476 /* If VALUE contains REG and we have a previous value for REG, substitute
10477 the previous value. */
10478 if (value && insn && reg_overlap_mentioned_p (reg, value))
10479 {
10480 rtx tem;
10481
10482 /* Set things up so get_last_value is allowed to see anything set up to
10483 our insn. */
10484 subst_low_cuid = INSN_CUID (insn);
10485 tem = get_last_value (reg);
10486
10487 if (tem)
10488 value = replace_rtx (copy_rtx (value), reg, tem);
10489 }
10490
10491 /* For each register modified, show we don't know its value, that
ef026f91
RS		 10492 we don't know about its bitwise content, that its value has been
10493 updated, and that we don't know the location of the death of the
10494 register. */
230d793d
RS		 10495 for (i = regno; i < endregno; i ++)
10496 {
10497 if (insn)
10498 reg_last_set[i] = insn;
10499 reg_last_set_value[i] = 0;
ef026f91
RS		 10500 reg_last_set_mode[i] = 0;
10501 reg_last_set_nonzero_bits[i] = 0;
10502 reg_last_set_sign_bit_copies[i] = 0;
230d793d
RS		 10503 reg_last_death[i] = 0;
10504 }
10505
10506 /* Mark registers that are being referenced in this value. */
10507 if (value)
10508 update_table_tick (value);
10509
10510 /* Now update the status of each register being set.
10511 If someone is using this register in this block, set this register
10512 to invalid since we will get confused between the two lives in this
10513 basic block. This makes using this register always invalid. In cse, we
10514 scan the table to invalidate all entries using this register, but this
10515 is too much work for us. */
10516
10517 for (i = regno; i < endregno; i++)
10518 {
10519 reg_last_set_label[i] = label_tick;
10520 if (value && reg_last_set_table_tick[i] == label_tick)
10521 reg_last_set_invalid[i] = 1;
10522 else
10523 reg_last_set_invalid[i] = 0;
10524 }
10525
10526 /* The value being assigned might refer to X (like in "x++;"). In that
10527 case, we must replace it with (clobber (const_int 0)) to prevent
10528 infinite loops. */
9a893315 10529 if (value && ! get_last_value_validate (&value, insn,
230d793d
RS		 10530 reg_last_set_label[regno], 0))
10531 {
10532 value = copy_rtx (value);
9a893315
JW		 10533 if (! get_last_value_validate (&value, insn,
10534 reg_last_set_label[regno], 1))
230d793d
RS		 10535 value = 0;
10536 }
10537
55310dad
RK		 10538 /* For the main register being modified, update the value, the mode, the
10539 nonzero bits, and the number of sign bit copies. */
10540
230d793d
RS		 10541 reg_last_set_value[regno] = value;
10542
55310dad
RK		 10543 if (value)
10544 {
2afabb48 10545 subst_low_cuid = INSN_CUID (insn);
55310dad
RK		 10546 reg_last_set_mode[regno] = GET_MODE (reg);
10547 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10548 reg_last_set_sign_bit_copies[regno]
10549 = num_sign_bit_copies (value, GET_MODE (reg));
10550 }
230d793d
RS		 10551}
10552
10553/* Used for communication between the following two routines. */
10554static rtx record_dead_insn;
10555
10556/* Called via note_stores from record_dead_and_set_regs to handle one
10557 SET or CLOBBER in an insn. */
10558
10559static void
10560record_dead_and_set_regs_1 (dest, setter)
10561 rtx dest, setter;
10562{
ca89d290
RK		 10563 if (GET_CODE (dest) == SUBREG)
10564 dest = SUBREG_REG (dest);
10565
230d793d
RS		 10566 if (GET_CODE (dest) == REG)
10567 {
10568 /* If we are setting the whole register, we know its value. Otherwise
10569 show that we don't know the value. We can handle SUBREG in
10570 some cases. */
10571 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10572 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10573 else if (GET_CODE (setter) == SET
10574 && GET_CODE (SET_DEST (setter)) == SUBREG
10575 && SUBREG_REG (SET_DEST (setter)) == dest
90bf8081 10576 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
230d793d 10577 && subreg_lowpart_p (SET_DEST (setter)))
d0ab8cd3
RK		 10578 record_value_for_reg (dest, record_dead_insn,
10579 gen_lowpart_for_combine (GET_MODE (dest),
10580 SET_SRC (setter)));
230d793d 10581 else
5f4f0e22 10582 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
230d793d
RS		 10583 }
10584 else if (GET_CODE (dest) == MEM
10585 /* Ignore pushes, they clobber nothing. */
10586 && ! push_operand (dest, GET_MODE (dest)))
10587 mem_last_set = INSN_CUID (record_dead_insn);
10588}
10589
10590/* Update the records of when each REG was most recently set or killed
10591 for the things done by INSN. This is the last thing done in processing
10592 INSN in the combiner loop.
10593
ef026f91
RS		 10594 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10595 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10596 and also the similar information mem_last_set (which insn most recently
10597 modified memory) and last_call_cuid (which insn was the most recent
10598 subroutine call). */
230d793d
RS		 10599
10600static void
10601record_dead_and_set_regs (insn)
10602 rtx insn;
10603{
10604 register rtx link;
55310dad
RK		 10605 int i;
10606
230d793d
RS		 10607 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10608 {
dbc131f3
RK		 10609 if (REG_NOTE_KIND (link) == REG_DEAD
10610 && GET_CODE (XEXP (link, 0)) == REG)
10611 {
10612 int regno = REGNO (XEXP (link, 0));
10613 int endregno
10614 = regno + (regno < FIRST_PSEUDO_REGISTER
10615 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10616 : 1);
dbc131f3
RK		 10617
10618 for (i = regno; i < endregno; i++)
10619 reg_last_death[i] = insn;
10620 }
230d793d 10621 else if (REG_NOTE_KIND (link) == REG_INC)
5f4f0e22 10622 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
230d793d
RS		 10623 }
10624
10625 if (GET_CODE (insn) == CALL_INSN)
55310dad
RK		 10626 {
10627 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10628 if (call_used_regs[i])
10629 {
10630 reg_last_set_value[i] = 0;
ef026f91
RS		 10631 reg_last_set_mode[i] = 0;
10632 reg_last_set_nonzero_bits[i] = 0;
10633 reg_last_set_sign_bit_copies[i] = 0;
55310dad
RK		 10634 reg_last_death[i] = 0;
10635 }
10636
10637 last_call_cuid = mem_last_set = INSN_CUID (insn);
10638 }
230d793d
RS		 10639
10640 record_dead_insn = insn;
10641 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10642}
10643\f
10644/* Utility routine for the following function. Verify that all the registers
10645 mentioned in *LOC are valid when *LOC was part of a value set when
10646 label_tick == TICK. Return 0 if some are not.
10647
10648 If REPLACE is non-zero, replace the invalid reference with
10649 (clobber (const_int 0)) and return 1. This replacement is useful because
10650 we often can get useful information about the form of a value (e.g., if
10651 it was produced by a shift that always produces -1 or 0) even though
10652 we don't know exactly what registers it was produced from. */
10653
10654static int
9a893315 10655get_last_value_validate (loc, insn, tick, replace)
230d793d 10656 rtx *loc;
9a893315 10657 rtx insn;
230d793d
RS		 10658 int tick;
10659 int replace;
10660{
10661 rtx x = *loc;
10662 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10663 int len = GET_RTX_LENGTH (GET_CODE (x));
10664 int i;
10665
10666 if (GET_CODE (x) == REG)
10667 {
10668 int regno = REGNO (x);
10669 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10670 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10671 int j;
10672
10673 for (j = regno; j < endregno; j++)
10674 if (reg_last_set_invalid[j]
10675 /* If this is a pseudo-register that was only set once, it is
10676 always valid. */
b1f21e0a 10677 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
230d793d
RS		 10678 && reg_last_set_label[j] > tick))
10679 {
10680 if (replace)
38a448ca 10681 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 10682 return replace;
10683 }
10684
10685 return 1;
10686 }
9a893315
JW		 10687 /* If this is a memory reference, make sure that there were
10688 no stores after it that might have clobbered the value. We don't
10689 have alias info, so we assume any store invalidates it. */
10690 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10691 && INSN_CUID (insn) <= mem_last_set)
10692 {
10693 if (replace)
38a448ca 10694 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9a893315
JW		 10695 return replace;
10696 }
230d793d
RS		 10697
10698 for (i = 0; i < len; i++)
10699 if ((fmt[i] == 'e'
9a893315 10700 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
230d793d
RS		 10701 /* Don't bother with these. They shouldn't occur anyway. */
10702 || fmt[i] == 'E')
10703 return 0;
10704
10705 /* If we haven't found a reason for it to be invalid, it is valid. */
10706 return 1;
10707}
10708
10709/* Get the last value assigned to X, if known. Some registers
10710 in the value may be replaced with (clobber (const_int 0)) if their value
10711 is known longer known reliably. */
10712
10713static rtx
10714get_last_value (x)
10715 rtx x;
10716{
10717 int regno;
10718 rtx value;
10719
10720 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10721 then convert it to the desired mode. If this is a paradoxical SUBREG,
0f41302f 10722 we cannot predict what values the "extra" bits might have. */
230d793d
RS		 10723 if (GET_CODE (x) == SUBREG
10724 && subreg_lowpart_p (x)
10725 && (GET_MODE_SIZE (GET_MODE (x))
10726 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10727 && (value = get_last_value (SUBREG_REG (x))) != 0)
10728 return gen_lowpart_for_combine (GET_MODE (x), value);
10729
10730 if (GET_CODE (x) != REG)
10731 return 0;
10732
10733 regno = REGNO (x);
10734 value = reg_last_set_value[regno];
10735
0f41302f
MS		 10736 /* If we don't have a value or if it isn't for this basic block,
10737 return 0. */
230d793d
RS		 10738
10739 if (value == 0
b1f21e0a 10740 || (REG_N_SETS (regno) != 1
55310dad 10741 && reg_last_set_label[regno] != label_tick))
230d793d
RS		 10742 return 0;
10743
4255220d 10744 /* If the value was set in a later insn than the ones we are processing,
4090a6b3
RK		 10745 we can't use it even if the register was only set once, but make a quick
10746 check to see if the previous insn set it to something. This is commonly
0d9641d1
JW		 10747 the case when the same pseudo is used by repeated insns.
10748
10749 This does not work if there exists an instruction which is temporarily
10750 not on the insn chain. */
d0ab8cd3 10751
bcd49eb7 10752 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
d0ab8cd3
RK		 10753 {
10754 rtx insn, set;
10755
bcd49eb7
JW		 10756 /* We can not do anything useful in this case, because there is
10757 an instruction which is not on the insn chain. */
10758 if (subst_prev_insn)
10759 return 0;
10760
4255220d
JW		 10761 /* Skip over USE insns. They are not useful here, and they may have
10762 been made by combine, in which case they do not have a INSN_CUID
d6c80562 10763 value. We can't use prev_real_insn, because that would incorrectly
e340018d
JW		 10764 take us backwards across labels. Skip over BARRIERs also, since
10765 they could have been made by combine. If we see one, we must be
10766 optimizing dead code, so it doesn't matter what we do. */
d6c80562
JW		 10767 for (insn = prev_nonnote_insn (subst_insn);
10768 insn && ((GET_CODE (insn) == INSN
10769 && GET_CODE (PATTERN (insn)) == USE)
e340018d 10770 || GET_CODE (insn) == BARRIER
4255220d 10771 || INSN_CUID (insn) >= subst_low_cuid);
d6c80562 10772 insn = prev_nonnote_insn (insn))
3adde2a5 10773 ;
d0ab8cd3
RK		 10774
10775 if (insn
10776 && (set = single_set (insn)) != 0
10777 && rtx_equal_p (SET_DEST (set), x))
10778 {
10779 value = SET_SRC (set);
10780
10781 /* Make sure that VALUE doesn't reference X. Replace any
ddd5a7c1 10782 explicit references with a CLOBBER. If there are any remaining
d0ab8cd3
RK		 10783 references (rare), don't use the value. */
10784
10785 if (reg_mentioned_p (x, value))
10786 value = replace_rtx (copy_rtx (value), x,
38a448ca 10787 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
d0ab8cd3
RK		 10788
10789 if (reg_overlap_mentioned_p (x, value))
10790 return 0;
10791 }
10792 else
10793 return 0;
10794 }
10795
10796 /* If the value has all its registers valid, return it. */
9a893315
JW		 10797 if (get_last_value_validate (&value, reg_last_set[regno],
10798 reg_last_set_label[regno], 0))
230d793d
RS		 10799 return value;
10800
10801 /* Otherwise, make a copy and replace any invalid register with
10802 (clobber (const_int 0)). If that fails for some reason, return 0. */
10803
10804 value = copy_rtx (value);
9a893315
JW		 10805 if (get_last_value_validate (&value, reg_last_set[regno],
10806 reg_last_set_label[regno], 1))
230d793d
RS		 10807 return value;
10808
10809 return 0;
10810}
10811\f
10812/* Return nonzero if expression X refers to a REG or to memory
10813 that is set in an instruction more recent than FROM_CUID. */
10814
10815static int
10816use_crosses_set_p (x, from_cuid)
10817 register rtx x;
10818 int from_cuid;
10819{
10820 register char *fmt;
10821 register int i;
10822 register enum rtx_code code = GET_CODE (x);
10823
10824 if (code == REG)
10825 {
10826 register int regno = REGNO (x);
e28f5732
RK		 10827 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10828 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10829
230d793d
RS		 10830#ifdef PUSH_ROUNDING
10831 /* Don't allow uses of the stack pointer to be moved,
10832 because we don't know whether the move crosses a push insn. */
10833 if (regno == STACK_POINTER_REGNUM)
10834 return 1;
10835#endif
e28f5732
RK		 10836 for (;regno < endreg; regno++)
10837 if (reg_last_set[regno]
10838 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10839 return 1;
10840 return 0;
230d793d
RS		 10841 }
10842
10843 if (code == MEM && mem_last_set > from_cuid)
10844 return 1;
10845
10846 fmt = GET_RTX_FORMAT (code);
10847
10848 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10849 {
10850 if (fmt[i] == 'E')
10851 {
10852 register int j;
10853 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10854 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10855 return 1;
10856 }
10857 else if (fmt[i] == 'e'
10858 && use_crosses_set_p (XEXP (x, i), from_cuid))
10859 return 1;
10860 }
10861 return 0;
10862}
10863\f
10864/* Define three variables used for communication between the following
10865 routines. */
10866
10867static int reg_dead_regno, reg_dead_endregno;
10868static int reg_dead_flag;
10869
10870/* Function called via note_stores from reg_dead_at_p.
10871
ddd5a7c1 10872 If DEST is within [reg_dead_regno, reg_dead_endregno), set
230d793d
RS		 10873 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10874
10875static void
10876reg_dead_at_p_1 (dest, x)
10877 rtx dest;
10878 rtx x;
10879{
10880 int regno, endregno;
10881
10882 if (GET_CODE (dest) != REG)
10883 return;
10884
10885 regno = REGNO (dest);
10886 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10887 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10888
10889 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10890 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10891}
10892
10893/* Return non-zero if REG is known to be dead at INSN.
10894
10895 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10896 referencing REG, it is dead. If we hit a SET referencing REG, it is
10897 live. Otherwise, see if it is live or dead at the start of the basic
6e25d159
RK		 10898 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10899 must be assumed to be always live. */
230d793d
RS		 10900
10901static int
10902reg_dead_at_p (reg, insn)
10903 rtx reg;
10904 rtx insn;
10905{
10906 int block, i;
10907
10908 /* Set variables for reg_dead_at_p_1. */
10909 reg_dead_regno = REGNO (reg);
10910 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10911 ? HARD_REGNO_NREGS (reg_dead_regno,
10912 GET_MODE (reg))
10913 : 1);
10914
10915 reg_dead_flag = 0;
10916
6e25d159
RK		 10917 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10918 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10919 {
10920 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10921 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10922 return 0;
10923 }
10924
230d793d
RS		 10925 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10926 beginning of function. */
60715d0b 10927 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
230d793d
RS		 10928 insn = prev_nonnote_insn (insn))
10929 {
10930 note_stores (PATTERN (insn), reg_dead_at_p_1);
10931 if (reg_dead_flag)
10932 return reg_dead_flag == 1 ? 1 : 0;
10933
10934 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10935 return 1;
10936 }
10937
10938 /* Get the basic block number that we were in. */
10939 if (insn == 0)
10940 block = 0;
10941 else
10942 {
10943 for (block = 0; block < n_basic_blocks; block++)
10944 if (insn == basic_block_head[block])
10945 break;
10946
10947 if (block == n_basic_blocks)
10948 return 0;
10949 }
10950
10951 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8e08106d 10952 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
230d793d
RS		 10953 return 0;
10954
10955 return 1;
10956}
6e25d159
RK		 10957\f
10958/* Note hard registers in X that are used. This code is similar to
10959 that in flow.c, but much simpler since we don't care about pseudos. */
10960
10961static void
10962mark_used_regs_combine (x)
10963 rtx x;
10964{
10965 register RTX_CODE code = GET_CODE (x);
10966 register int regno;
10967 int i;
10968
10969 switch (code)
10970 {
10971 case LABEL_REF:
10972 case SYMBOL_REF:
10973 case CONST_INT:
10974 case CONST:
10975 case CONST_DOUBLE:
10976 case PC:
10977 case ADDR_VEC:
10978 case ADDR_DIFF_VEC:
10979 case ASM_INPUT:
10980#ifdef HAVE_cc0
10981 /* CC0 must die in the insn after it is set, so we don't need to take
10982 special note of it here. */
10983 case CC0:
10984#endif
10985 return;
10986
10987 case CLOBBER:
10988 /* If we are clobbering a MEM, mark any hard registers inside the
10989 address as used. */
10990 if (GET_CODE (XEXP (x, 0)) == MEM)
10991 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10992 return;
10993
10994 case REG:
10995 regno = REGNO (x);
10996 /* A hard reg in a wide mode may really be multiple registers.
10997 If so, mark all of them just like the first. */
10998 if (regno < FIRST_PSEUDO_REGISTER)
10999 {
11000 /* None of this applies to the stack, frame or arg pointers */
11001 if (regno == STACK_POINTER_REGNUM
11002#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11003 || regno == HARD_FRAME_POINTER_REGNUM
11004#endif
11005#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11006 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11007#endif
11008 || regno == FRAME_POINTER_REGNUM)
11009 return;
11010
11011 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11012 while (i-- > 0)
11013 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11014 }
11015 return;
11016
11017 case SET:
11018 {
11019 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11020 the address. */
11021 register rtx testreg = SET_DEST (x);
11022
e048778f
RK		 11023 while (GET_CODE (testreg) == SUBREG
11024 || GET_CODE (testreg) == ZERO_EXTRACT
11025 || GET_CODE (testreg) == SIGN_EXTRACT
11026 || GET_CODE (testreg) == STRICT_LOW_PART)
6e25d159
RK		 11027 testreg = XEXP (testreg, 0);
11028
11029 if (GET_CODE (testreg) == MEM)
11030 mark_used_regs_combine (XEXP (testreg, 0));
11031
11032 mark_used_regs_combine (SET_SRC (x));
6e25d159 11033 }
e9a25f70
JL		 11034 return;
11035
11036 default:
11037 break;
6e25d159
RK		 11038 }
11039
11040 /* Recursively scan the operands of this expression. */
11041
11042 {
11043 register char *fmt = GET_RTX_FORMAT (code);
11044
11045 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11046 {
11047 if (fmt[i] == 'e')
11048 mark_used_regs_combine (XEXP (x, i));
11049 else if (fmt[i] == 'E')
11050 {
11051 register int j;
11052
11053 for (j = 0; j < XVECLEN (x, i); j++)
11054 mark_used_regs_combine (XVECEXP (x, i, j));
11055 }
11056 }
11057 }
11058}
11059
230d793d
RS		 11060\f
11061/* Remove register number REGNO from the dead registers list of INSN.
11062
11063 Return the note used to record the death, if there was one. */
11064
11065rtx
11066remove_death (regno, insn)
11067 int regno;
11068 rtx insn;
11069{
11070 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11071
11072 if (note)
1a26b032 11073 {
b1f21e0a 11074 REG_N_DEATHS (regno)--;
1a26b032
RK		 11075 remove_note (insn, note);
11076 }
230d793d
RS		 11077
11078 return note;
11079}
11080
11081/* For each register (hardware or pseudo) used within expression X, if its
11082 death is in an instruction with cuid between FROM_CUID (inclusive) and
11083 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11084 list headed by PNOTES.
11085
6eb12cef
RK		 11086 That said, don't move registers killed by maybe_kill_insn.
11087
230d793d
RS		 11088 This is done when X is being merged by combination into TO_INSN. These
11089 notes will then be distributed as needed. */
11090
11091static void
6eb12cef 11092move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
230d793d 11093 rtx x;
6eb12cef 11094 rtx maybe_kill_insn;
230d793d
RS		 11095 int from_cuid;
11096 rtx to_insn;
11097 rtx *pnotes;
11098{
11099 register char *fmt;
11100 register int len, i;
11101 register enum rtx_code code = GET_CODE (x);
11102
11103 if (code == REG)
11104 {
11105 register int regno = REGNO (x);
11106 register rtx where_dead = reg_last_death[regno];
e340018d
JW		 11107 register rtx before_dead, after_dead;
11108
6eb12cef
RK		 11109 /* Don't move the register if it gets killed in between from and to */
11110 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11111 && !reg_referenced_p (x, maybe_kill_insn))
11112 return;
11113
e340018d
JW		 11114 /* WHERE_DEAD could be a USE insn made by combine, so first we
11115 make sure that we have insns with valid INSN_CUID values. */
11116 before_dead = where_dead;
11117 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11118 before_dead = PREV_INSN (before_dead);
11119 after_dead = where_dead;
11120 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11121 after_dead = NEXT_INSN (after_dead);
11122
11123 if (before_dead && after_dead
11124 && INSN_CUID (before_dead) >= from_cuid
11125 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11126 || (where_dead != after_dead
11127 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
230d793d 11128 {
dbc131f3 11129 rtx note = remove_death (regno, where_dead);
230d793d
RS		 11130
11131 /* It is possible for the call above to return 0. This can occur
11132 when reg_last_death points to I2 or I1 that we combined with.
dbc131f3
RK		 11133 In that case make a new note.
11134
11135 We must also check for the case where X is a hard register
11136 and NOTE is a death note for a range of hard registers
11137 including X. In that case, we must put REG_DEAD notes for
11138 the remaining registers in place of NOTE. */
11139
11140 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11141 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
24e46fc4 11142 > GET_MODE_SIZE (GET_MODE (x))))
dbc131f3
RK		 11143 {
11144 int deadregno = REGNO (XEXP (note, 0));
11145 int deadend
11146 = (deadregno + HARD_REGNO_NREGS (deadregno,
11147 GET_MODE (XEXP (note, 0))));
11148 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11149 int i;
11150
11151 for (i = deadregno; i < deadend; i++)
11152 if (i < regno || i >= ourend)
11153 REG_NOTES (where_dead)
38a448ca
RH		 11154 = gen_rtx_EXPR_LIST (REG_DEAD,
11155 gen_rtx_REG (reg_raw_mode[i], i),
11156 REG_NOTES (where_dead));
dbc131f3 11157 }
24e46fc4
JW		 11158 /* If we didn't find any note, or if we found a REG_DEAD note that
11159 covers only part of the given reg, and we have a multi-reg hard
fabd69e8
RK		 11160 register, then to be safe we must check for REG_DEAD notes
11161 for each register other than the first. They could have
11162 their own REG_DEAD notes lying around. */
24e46fc4
JW		 11163 else if ((note == 0
11164 || (note != 0
11165 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11166 < GET_MODE_SIZE (GET_MODE (x)))))
11167 && regno < FIRST_PSEUDO_REGISTER
fabd69e8
RK		 11168 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11169 {
11170 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
24e46fc4 11171 int i, offset;
fabd69e8
RK		 11172 rtx oldnotes = 0;
11173
24e46fc4
JW		 11174 if (note)
11175 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11176 else
11177 offset = 1;
11178
11179 for (i = regno + offset; i < ourend; i++)
38a448ca 11180 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
6eb12cef 11181 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
fabd69e8 11182 }
230d793d 11183
dbc131f3 11184 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
230d793d
RS		 11185 {
11186 XEXP (note, 1) = *pnotes;
11187 *pnotes = note;
11188 }
11189 else
38a448ca 11190 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
1a26b032 11191
b1f21e0a 11192 REG_N_DEATHS (regno)++;
230d793d
RS		 11193 }
11194
11195 return;
11196 }
11197
11198 else if (GET_CODE (x) == SET)
11199 {
11200 rtx dest = SET_DEST (x);
11201
6eb12cef 11202 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d 11203
a7c99304
RK		 11204 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11205 that accesses one word of a multi-word item, some
11206 piece of everything register in the expression is used by
11207 this insn, so remove any old death. */
11208
11209 if (GET_CODE (dest) == ZERO_EXTRACT
11210 || GET_CODE (dest) == STRICT_LOW_PART
11211 || (GET_CODE (dest) == SUBREG
11212 && (((GET_MODE_SIZE (GET_MODE (dest))
11213 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11214 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11215 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
230d793d 11216 {
6eb12cef 11217 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
a7c99304 11218 return;
230d793d
RS		 11219 }
11220
a7c99304
RK		 11221 /* If this is some other SUBREG, we know it replaces the entire
11222 value, so use that as the destination. */
11223 if (GET_CODE (dest) == SUBREG)
11224 dest = SUBREG_REG (dest);
11225
11226 /* If this is a MEM, adjust deaths of anything used in the address.
11227 For a REG (the only other possibility), the entire value is
11228 being replaced so the old value is not used in this insn. */
230d793d
RS		 11229
11230 if (GET_CODE (dest) == MEM)
6eb12cef
RK		 11231 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11232 to_insn, pnotes);
230d793d
RS		 11233 return;
11234 }
11235
11236 else if (GET_CODE (x) == CLOBBER)
11237 return;
11238
11239 len = GET_RTX_LENGTH (code);
11240 fmt = GET_RTX_FORMAT (code);
11241
11242 for (i = 0; i < len; i++)
11243 {
11244 if (fmt[i] == 'E')
11245 {
11246 register int j;
11247 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6eb12cef
RK		 11248 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11249 to_insn, pnotes);
230d793d
RS		 11250 }
11251 else if (fmt[i] == 'e')
6eb12cef 11252 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d
RS		 11253 }
11254}
11255\f
a7c99304
RK		 11256/* Return 1 if X is the target of a bit-field assignment in BODY, the
11257 pattern of an insn. X must be a REG. */
230d793d
RS		 11258
11259static int
a7c99304
RK		 11260reg_bitfield_target_p (x, body)
11261 rtx x;
230d793d
RS		 11262 rtx body;
11263{
11264 int i;
11265
11266 if (GET_CODE (body) == SET)
a7c99304
RK		 11267 {
11268 rtx dest = SET_DEST (body);
11269 rtx target;
11270 int regno, tregno, endregno, endtregno;
11271
11272 if (GET_CODE (dest) == ZERO_EXTRACT)
11273 target = XEXP (dest, 0);
11274 else if (GET_CODE (dest) == STRICT_LOW_PART)
11275 target = SUBREG_REG (XEXP (dest, 0));
11276 else
11277 return 0;
11278
11279 if (GET_CODE (target) == SUBREG)
11280 target = SUBREG_REG (target);
11281
11282 if (GET_CODE (target) != REG)
11283 return 0;
11284
11285 tregno = REGNO (target), regno = REGNO (x);
11286 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11287 return target == x;
11288
11289 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11290 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11291
11292 return endregno > tregno && regno < endtregno;
11293 }
230d793d
RS		 11294
11295 else if (GET_CODE (body) == PARALLEL)
11296 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
a7c99304 11297 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
230d793d
RS		 11298 return 1;
11299
11300 return 0;
11301}
11302\f
11303/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11304 as appropriate. I3 and I2 are the insns resulting from the combination
11305 insns including FROM (I2 may be zero).
11306
11307 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11308 not need REG_DEAD notes because they are being substituted for. This
11309 saves searching in the most common cases.
11310
11311 Each note in the list is either ignored or placed on some insns, depending
11312 on the type of note. */
11313
11314static void
11315distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11316 rtx notes;
11317 rtx from_insn;
11318 rtx i3, i2;
11319 rtx elim_i2, elim_i1;
11320{
11321 rtx note, next_note;
11322 rtx tem;
11323
11324 for (note = notes; note; note = next_note)
11325 {
11326 rtx place = 0, place2 = 0;
11327
11328 /* If this NOTE references a pseudo register, ensure it references
11329 the latest copy of that register. */
11330 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11331 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11332 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11333
11334 next_note = XEXP (note, 1);
11335 switch (REG_NOTE_KIND (note))
11336 {
c9903b44
DE		 11337 case REG_BR_PROB:
11338 case REG_EXEC_COUNT:
11339 /* Doesn't matter much where we put this, as long as it's somewhere.
11340 It is preferable to keep these notes on branches, which is most
11341 likely to be i3. */
11342 place = i3;
11343 break;
11344
230d793d 11345 case REG_UNUSED:
07d0cbdd 11346 /* Any clobbers for i3 may still exist, and so we must process
176c9e6b
JW		 11347 REG_UNUSED notes from that insn.
11348
11349 Any clobbers from i2 or i1 can only exist if they were added by
11350 recog_for_combine. In that case, recog_for_combine created the
11351 necessary REG_UNUSED notes. Trying to keep any original
11352 REG_UNUSED notes from these insns can cause incorrect output
11353 if it is for the same register as the original i3 dest.
11354 In that case, we will notice that the register is set in i3,
11355 and then add a REG_UNUSED note for the destination of i3, which
07d0cbdd
JW		 11356 is wrong. However, it is possible to have REG_UNUSED notes from
11357 i2 or i1 for register which were both used and clobbered, so
11358 we keep notes from i2 or i1 if they will turn into REG_DEAD
11359 notes. */
176c9e6b 11360
230d793d
RS		 11361 /* If this register is set or clobbered in I3, put the note there
11362 unless there is one already. */
07d0cbdd 11363 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
230d793d 11364 {
07d0cbdd
JW		 11365 if (from_insn != i3)
11366 break;
11367
230d793d
RS		 11368 if (! (GET_CODE (XEXP (note, 0)) == REG
11369 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11370 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11371 place = i3;
11372 }
11373 /* Otherwise, if this register is used by I3, then this register
11374 now dies here, so we must put a REG_DEAD note here unless there
11375 is one already. */
11376 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11377 && ! (GET_CODE (XEXP (note, 0)) == REG
11378 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11379 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11380 {
11381 PUT_REG_NOTE_KIND (note, REG_DEAD);
11382 place = i3;
11383 }
11384 break;
11385
11386 case REG_EQUAL:
11387 case REG_EQUIV:
11388 case REG_NONNEG:
9ae8ffe7 11389 case REG_NOALIAS:
230d793d
RS		 11390 /* These notes say something about results of an insn. We can
11391 only support them if they used to be on I3 in which case they
a687e897
RK		 11392 remain on I3. Otherwise they are ignored.
11393
11394 If the note refers to an expression that is not a constant, we
11395 must also ignore the note since we cannot tell whether the
11396 equivalence is still true. It might be possible to do
11397 slightly better than this (we only have a problem if I2DEST
11398 or I1DEST is present in the expression), but it doesn't
11399 seem worth the trouble. */
11400
11401 if (from_insn == i3
11402 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
230d793d
RS		 11403 place = i3;
11404 break;
11405
11406 case REG_INC:
11407 case REG_NO_CONFLICT:
11408 case REG_LABEL:
11409 /* These notes say something about how a register is used. They must
11410 be present on any use of the register in I2 or I3. */
11411 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11412 place = i3;
11413
11414 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11415 {
11416 if (place)
11417 place2 = i2;
11418 else
11419 place = i2;
11420 }
11421 break;
11422
11423 case REG_WAS_0:
11424 /* It is too much trouble to try to see if this note is still
11425 correct in all situations. It is better to simply delete it. */
11426 break;
11427
11428 case REG_RETVAL:
11429 /* If the insn previously containing this note still exists,
11430 put it back where it was. Otherwise move it to the previous
11431 insn. Adjust the corresponding REG_LIBCALL note. */
11432 if (GET_CODE (from_insn) != NOTE)
11433 place = from_insn;
11434 else
11435 {
5f4f0e22 11436 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
230d793d
RS		 11437 place = prev_real_insn (from_insn);
11438 if (tem && place)
11439 XEXP (tem, 0) = place;
11440 }
11441 break;
11442
11443 case REG_LIBCALL:
11444 /* This is handled similarly to REG_RETVAL. */
11445 if (GET_CODE (from_insn) != NOTE)
11446 place = from_insn;
11447 else
11448 {
5f4f0e22 11449 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
230d793d
RS		 11450 place = next_real_insn (from_insn);
11451 if (tem && place)
11452 XEXP (tem, 0) = place;
11453 }
11454 break;
11455
11456 case REG_DEAD:
11457 /* If the register is used as an input in I3, it dies there.
11458 Similarly for I2, if it is non-zero and adjacent to I3.
11459
11460 If the register is not used as an input in either I3 or I2
11461 and it is not one of the registers we were supposed to eliminate,
11462 there are two possibilities. We might have a non-adjacent I2
11463 or we might have somehow eliminated an additional register
11464 from a computation. For example, we might have had A & B where
11465 we discover that B will always be zero. In this case we will
11466 eliminate the reference to A.
11467
11468 In both cases, we must search to see if we can find a previous
11469 use of A and put the death note there. */
11470
6e2d1486
RK		 11471 if (from_insn
11472 && GET_CODE (from_insn) == CALL_INSN
11473 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11474 place = from_insn;
11475 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
230d793d
RS		 11476 place = i3;
11477 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11478 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11479 place = i2;
11480
11481 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11482 break;
11483
510dd77e
RK		 11484 /* If the register is used in both I2 and I3 and it dies in I3,
11485 we might have added another reference to it. If reg_n_refs
11486 was 2, bump it to 3. This has to be correct since the
11487 register must have been set somewhere. The reason this is
11488 done is because local-alloc.c treats 2 references as a
11489 special case. */
11490
11491 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
b1f21e0a 11492 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
510dd77e 11493 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
b1f21e0a 11494 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
510dd77e 11495
230d793d 11496 if (place == 0)
38d8473f
RK		 11497 {
11498 for (tem = prev_nonnote_insn (i3);
11499 place == 0 && tem
11500 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11501 tem = prev_nonnote_insn (tem))
11502 {
11503 /* If the register is being set at TEM, see if that is all
11504 TEM is doing. If so, delete TEM. Otherwise, make this
11505 into a REG_UNUSED note instead. */
11506 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11507 {
11508 rtx set = single_set (tem);
e5e809f4
JL		 11509 rtx inner_dest = 0;
11510
11511 if (set != 0)
11512 for (inner_dest = SET_DEST (set);
11513 GET_CODE (inner_dest) == STRICT_LOW_PART
11514 || GET_CODE (inner_dest) == SUBREG
11515 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11516 inner_dest = XEXP (inner_dest, 0))
11517 ;
38d8473f
RK		 11518
11519 /* Verify that it was the set, and not a clobber that
11520 modified the register. */
11521
11522 if (set != 0 && ! side_effects_p (SET_SRC (set))
e5e809f4 11523 && rtx_equal_p (XEXP (note, 0), inner_dest))
38d8473f
RK		 11524 {
11525 /* Move the notes and links of TEM elsewhere.
11526 This might delete other dead insns recursively.
11527 First set the pattern to something that won't use
11528 any register. */
11529
11530 PATTERN (tem) = pc_rtx;
11531
11532 distribute_notes (REG_NOTES (tem), tem, tem,
11533 NULL_RTX, NULL_RTX, NULL_RTX);
11534 distribute_links (LOG_LINKS (tem));
11535
11536 PUT_CODE (tem, NOTE);
11537 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11538 NOTE_SOURCE_FILE (tem) = 0;
11539 }
e5e809f4
JL		 11540 /* If the register is both set and used here, put the
11541 REG_DEAD note here, but place a REG_UNUSED note
11542 here too unless there already is one. */
11543 else if (reg_referenced_p (XEXP (note, 0),
11544 PATTERN (tem)))
11545 {
11546 place = tem;
11547
11548 if (! find_regno_note (tem, REG_UNUSED,
11549 REGNO (XEXP (note, 0))))
11550 REG_NOTES (tem)
9e6a5703
JC		 11551 = gen_rtx_EXPR_LIST (REG_UNUSED,
11552 XEXP (note, 0),
11553 REG_NOTES (tem));
e5e809f4 11554 }
38d8473f
RK		 11555 else
11556 {
11557 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11558
11559 /* If there isn't already a REG_UNUSED note, put one
11560 here. */
11561 if (! find_regno_note (tem, REG_UNUSED,
11562 REGNO (XEXP (note, 0))))
11563 place = tem;
11564 break;
230d793d
RS		 11565 }
11566 }
13018fad
RE		 11567 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11568 || (GET_CODE (tem) == CALL_INSN
11569 && find_reg_fusage (tem, USE, XEXP (note, 0))))
230d793d
RS		 11570 {
11571 place = tem;
932d1119
RK		 11572
11573 /* If we are doing a 3->2 combination, and we have a
11574 register which formerly died in i3 and was not used
11575 by i2, which now no longer dies in i3 and is used in
11576 i2 but does not die in i2, and place is between i2
11577 and i3, then we may need to move a link from place to
11578 i2. */
a8908849
RK		 11579 if (i2 && INSN_UID (place) <= max_uid_cuid
11580 && INSN_CUID (place) > INSN_CUID (i2)
932d1119
RK		 11581 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11582 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11583 {
11584 rtx links = LOG_LINKS (place);
11585 LOG_LINKS (place) = 0;
11586 distribute_links (links);
11587 }
230d793d
RS		 11588 break;
11589 }
38d8473f
RK		 11590 }
11591
11592 /* If we haven't found an insn for the death note and it
11593 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11594 insert a USE insn for the register at that label and
11595 put the death node there. This prevents problems with
11596 call-state tracking in caller-save.c. */
11597 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
e2cce0cf
RK		 11598 {
11599 place
38a448ca 11600 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
e2cce0cf
RK		 11601 tem);
11602
11603 /* If this insn was emitted between blocks, then update
11604 basic_block_head of the current block to include it. */
11605 if (basic_block_end[this_basic_block - 1] == tem)
11606 basic_block_head[this_basic_block] = place;
11607 }
38d8473f 11608 }
230d793d
RS		 11609
11610 /* If the register is set or already dead at PLACE, we needn't do
e5e809f4
JL		 11611 anything with this note if it is still a REG_DEAD note.
11612 We can here if it is set at all, not if is it totally replace,
11613 which is what `dead_or_set_p' checks, so also check for it being
11614 set partially. */
11615
230d793d 11616
230d793d
RS		 11617 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11618 {
11619 int regno = REGNO (XEXP (note, 0));
11620
11621 if (dead_or_set_p (place, XEXP (note, 0))
11622 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11623 {
11624 /* Unless the register previously died in PLACE, clear
11625 reg_last_death. [I no longer understand why this is
11626 being done.] */
11627 if (reg_last_death[regno] != place)
11628 reg_last_death[regno] = 0;
11629 place = 0;
11630 }
11631 else
11632 reg_last_death[regno] = place;
11633
11634 /* If this is a death note for a hard reg that is occupying
11635 multiple registers, ensure that we are still using all
11636 parts of the object. If we find a piece of the object
11637 that is unused, we must add a USE for that piece before
11638 PLACE and put the appropriate REG_DEAD note on it.
11639
11640 An alternative would be to put a REG_UNUSED for the pieces
11641 on the insn that set the register, but that can't be done if
11642 it is not in the same block. It is simpler, though less
11643 efficient, to add the USE insns. */
11644
11645 if (place && regno < FIRST_PSEUDO_REGISTER
11646 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11647 {
11648 int endregno
11649 = regno + HARD_REGNO_NREGS (regno,
11650 GET_MODE (XEXP (note, 0)));
11651 int all_used = 1;
11652 int i;
11653
11654 for (i = regno; i < endregno; i++)
9fd5bb62
JW		 11655 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11656 && ! find_regno_fusage (place, USE, i))
230d793d 11657 {
38a448ca 11658 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
28f6d3af
RK		 11659 rtx p;
11660
11661 /* See if we already placed a USE note for this
11662 register in front of PLACE. */
11663 for (p = place;
11664 GET_CODE (PREV_INSN (p)) == INSN
11665 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11666 p = PREV_INSN (p))
11667 if (rtx_equal_p (piece,
11668 XEXP (PATTERN (PREV_INSN (p)), 0)))
11669 {
11670 p = 0;
11671 break;
11672 }
11673
11674 if (p)
11675 {
11676 rtx use_insn
38a448ca
RH		 11677 = emit_insn_before (gen_rtx_USE (VOIDmode,
11678 piece),
28f6d3af
RK		 11679 p);
11680 REG_NOTES (use_insn)
38a448ca
RH		 11681 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11682 REG_NOTES (use_insn));
28f6d3af 11683 }
230d793d 11684
5089e22e 11685 all_used = 0;
230d793d
RS		 11686 }
11687
a394b17b
JW		 11688 /* Check for the case where the register dying partially
11689 overlaps the register set by this insn. */
11690 if (all_used)
11691 for (i = regno; i < endregno; i++)
11692 if (dead_or_set_regno_p (place, i))
11693 {
11694 all_used = 0;
11695 break;
11696 }
11697
230d793d
RS		 11698 if (! all_used)
11699 {
11700 /* Put only REG_DEAD notes for pieces that are
11701 still used and that are not already dead or set. */
11702
11703 for (i = regno; i < endregno; i++)
11704 {
38a448ca 11705 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
230d793d 11706
17cbf358
JW		 11707 if ((reg_referenced_p (piece, PATTERN (place))
11708 || (GET_CODE (place) == CALL_INSN
11709 && find_reg_fusage (place, USE, piece)))
230d793d
RS		 11710 && ! dead_or_set_p (place, piece)
11711 && ! reg_bitfield_target_p (piece,
11712 PATTERN (place)))
38a448ca
RH		 11713 REG_NOTES (place)
11714 = gen_rtx_EXPR_LIST (REG_DEAD,
11715 piece, REG_NOTES (place));
230d793d
RS		 11716 }
11717
11718 place = 0;
11719 }
11720 }
11721 }
11722 break;
11723
11724 default:
11725 /* Any other notes should not be present at this point in the
11726 compilation. */
11727 abort ();
11728 }
11729
11730 if (place)
11731 {
11732 XEXP (note, 1) = REG_NOTES (place);
11733 REG_NOTES (place) = note;
11734 }
1a26b032
RK		 11735 else if ((REG_NOTE_KIND (note) == REG_DEAD
11736 || REG_NOTE_KIND (note) == REG_UNUSED)
11737 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11738 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
230d793d
RS		 11739
11740 if (place2)
1a26b032
RK		 11741 {
11742 if ((REG_NOTE_KIND (note) == REG_DEAD
11743 || REG_NOTE_KIND (note) == REG_UNUSED)
11744 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11745 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 11746
38a448ca
RH		 11747 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11748 REG_NOTE_KIND (note),
11749 XEXP (note, 0),
11750 REG_NOTES (place2));
1a26b032 11751 }
230d793d
RS		 11752 }
11753}
11754\f
11755/* Similarly to above, distribute the LOG_LINKS that used to be present on
5089e22e
RS		 11756 I3, I2, and I1 to new locations. This is also called in one case to
11757 add a link pointing at I3 when I3's destination is changed. */
230d793d
RS		 11758
11759static void
11760distribute_links (links)
11761 rtx links;
11762{
11763 rtx link, next_link;
11764
11765 for (link = links; link; link = next_link)
11766 {
11767 rtx place = 0;
11768 rtx insn;
11769 rtx set, reg;
11770
11771 next_link = XEXP (link, 1);
11772
11773 /* If the insn that this link points to is a NOTE or isn't a single
11774 set, ignore it. In the latter case, it isn't clear what we
11775 can do other than ignore the link, since we can't tell which
11776 register it was for. Such links wouldn't be used by combine
11777 anyway.
11778
11779 It is not possible for the destination of the target of the link to
11780 have been changed by combine. The only potential of this is if we
11781 replace I3, I2, and I1 by I3 and I2. But in that case the
11782 destination of I2 also remains unchanged. */
11783
11784 if (GET_CODE (XEXP (link, 0)) == NOTE
11785 || (set = single_set (XEXP (link, 0))) == 0)
11786 continue;
11787
11788 reg = SET_DEST (set);
11789 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11790 || GET_CODE (reg) == SIGN_EXTRACT
11791 || GET_CODE (reg) == STRICT_LOW_PART)
11792 reg = XEXP (reg, 0);
11793
11794 /* A LOG_LINK is defined as being placed on the first insn that uses
11795 a register and points to the insn that sets the register. Start
11796 searching at the next insn after the target of the link and stop
11797 when we reach a set of the register or the end of the basic block.
11798
11799 Note that this correctly handles the link that used to point from
5089e22e 11800 I3 to I2. Also note that not much searching is typically done here
230d793d
RS		 11801 since most links don't point very far away. */
11802
11803 for (insn = NEXT_INSN (XEXP (link, 0));
0d4d42c3
RK		 11804 (insn && (this_basic_block == n_basic_blocks - 1
11805 || basic_block_head[this_basic_block + 1] != insn));
230d793d
RS		 11806 insn = NEXT_INSN (insn))
11807 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11808 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11809 {
11810 if (reg_referenced_p (reg, PATTERN (insn)))
11811 place = insn;
11812 break;
11813 }
6e2d1486
RK		 11814 else if (GET_CODE (insn) == CALL_INSN
11815 && find_reg_fusage (insn, USE, reg))
11816 {
11817 place = insn;
11818 break;
11819 }
230d793d
RS		 11820
11821 /* If we found a place to put the link, place it there unless there
11822 is already a link to the same insn as LINK at that point. */
11823
11824 if (place)
11825 {
11826 rtx link2;
11827
11828 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11829 if (XEXP (link2, 0) == XEXP (link, 0))
11830 break;
11831
11832 if (link2 == 0)
11833 {
11834 XEXP (link, 1) = LOG_LINKS (place);
11835 LOG_LINKS (place) = link;
abe6e52f
RK		 11836
11837 /* Set added_links_insn to the earliest insn we added a
11838 link to. */
11839 if (added_links_insn == 0
11840 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11841 added_links_insn = place;
230d793d
RS		 11842 }
11843 }
11844 }
11845}
11846\f
1427d6d2
RK		 11847/* Compute INSN_CUID for INSN, which is an insn made by combine. */
11848
11849static int
11850insn_cuid (insn)
11851 rtx insn;
11852{
11853 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11854 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11855 insn = NEXT_INSN (insn);
11856
11857 if (INSN_UID (insn) > max_uid_cuid)
11858 abort ();
11859
11860 return INSN_CUID (insn);
11861}
11862\f
230d793d
RS		 11863void
11864dump_combine_stats (file)
11865 FILE *file;
11866{
11867 fprintf
11868 (file,
11869 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11870 combine_attempts, combine_merges, combine_extras, combine_successes);
11871}
11872
11873void
11874dump_combine_total_stats (file)
11875 FILE *file;
11876{
11877 fprintf
11878 (file,
11879 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11880 total_attempts, total_merges, total_extras, total_successes);
11881}
GNU Compiler Collection
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