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230d793d | 1 | /* Optimize by combining instructions for GNU compiler. |
3c71940f | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
ad616de1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
230d793d | 4 | |
1322177d | 5 | This file is part of GCC. |
230d793d | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
230d793d | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
230d793d RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d | 18 | along with GCC; see the file COPYING. If not, write to the Free |
366ccddb KC |
19 | Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
230d793d | 21 | |
230d793d RS |
22 | /* This module is essentially the "combiner" phase of the U. of Arizona |
23 | Portable Optimizer, but redone to work on our list-structured | |
24 | representation for RTL instead of their string representation. | |
25 | ||
26 | The LOG_LINKS of each insn identify the most recent assignment | |
27 | to each REG used in the insn. It is a list of previous insns, | |
28 | each of which contains a SET for a REG that is used in this insn | |
29 | and not used or set in between. LOG_LINKs never cross basic blocks. | |
30 | They were set up by the preceding pass (lifetime analysis). | |
31 | ||
32 | We try to combine each pair of insns joined by a logical link. | |
33 | We also try to combine triples of insns A, B and C when | |
34 | C has a link back to B and B has a link back to A. | |
35 | ||
36 | LOG_LINKS does not have links for use of the CC0. They don't | |
37 | need to, because the insn that sets the CC0 is always immediately | |
38 | before the insn that tests it. So we always regard a branch | |
39 | insn as having a logical link to the preceding insn. The same is true | |
40 | for an insn explicitly using CC0. | |
41 | ||
42 | We check (with use_crosses_set_p) to avoid combining in such a way | |
43 | as to move a computation to a place where its value would be different. | |
44 | ||
45 | Combination is done by mathematically substituting the previous | |
46 | insn(s) values for the regs they set into the expressions in | |
47 | the later insns that refer to these regs. If the result is a valid insn | |
48 | for our target machine, according to the machine description, | |
49 | we install it, delete the earlier insns, and update the data flow | |
50 | information (LOG_LINKS and REG_NOTES) for what we did. | |
51 | ||
52 | There are a few exceptions where the dataflow information created by | |
53 | flow.c aren't completely updated: | |
54 | ||
55 | - reg_live_length is not updated | |
4bbae09f ILT |
56 | - reg_n_refs is not adjusted in the rare case when a register is |
57 | no longer required in a computation | |
58 | - there are extremely rare cases (see distribute_regnotes) when a | |
59 | REG_DEAD note is lost | |
230d793d | 60 | - a LOG_LINKS entry that refers to an insn with multiple SETs may be |
663522cb | 61 | removed because there is no way to know which register it was |
230d793d RS |
62 | linking |
63 | ||
64 | To simplify substitution, we combine only when the earlier insn(s) | |
65 | consist of only a single assignment. To simplify updating afterward, | |
66 | we never combine when a subroutine call appears in the middle. | |
67 | ||
68 | Since we do not represent assignments to CC0 explicitly except when that | |
69 | is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
70 | the condition code for the insn that set the condition code. | |
71 | Fortunately, these two insns must be consecutive. | |
72 | Therefore, every JUMP_INSN is taken to have an implicit logical link | |
73 | to the preceding insn. This is not quite right, since non-jumps can | |
74 | also use the condition code; but in practice such insns would not | |
75 | combine anyway. */ | |
76 | ||
230d793d | 77 | #include "config.h" |
670ee920 | 78 | #include "system.h" |
4977bab6 ZW |
79 | #include "coretypes.h" |
80 | #include "tm.h" | |
c5c76735 | 81 | #include "rtl.h" |
61f71b34 | 82 | #include "tree.h" |
a091679a | 83 | #include "tm_p.h" |
230d793d RS |
84 | #include "flags.h" |
85 | #include "regs.h" | |
55310dad | 86 | #include "hard-reg-set.h" |
230d793d RS |
87 | #include "basic-block.h" |
88 | #include "insn-config.h" | |
49ad7cfa | 89 | #include "function.h" |
ec5c56db | 90 | /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ |
d6f4ec51 | 91 | #include "expr.h" |
230d793d RS |
92 | #include "insn-attr.h" |
93 | #include "recog.h" | |
94 | #include "real.h" | |
2e107e9e | 95 | #include "toplev.h" |
61f71b34 | 96 | #include "target.h" |
aa2d0bc3 AO |
97 | #include "optabs.h" |
98 | #include "insn-codes.h" | |
2f93eea8 | 99 | #include "rtlhooks-def.h" |
64b8935d RS |
100 | /* Include output.h for dump_file. */ |
101 | #include "output.h" | |
49c3b9a8 | 102 | #include "params.h" |
ef330312 PB |
103 | #include "timevar.h" |
104 | #include "tree-pass.h" | |
f73ad30e | 105 | |
230d793d RS |
106 | /* Number of attempts to combine instructions in this function. */ |
107 | ||
108 | static int combine_attempts; | |
109 | ||
110 | /* Number of attempts that got as far as substitution in this function. */ | |
111 | ||
112 | static int combine_merges; | |
113 | ||
114 | /* Number of instructions combined with added SETs in this function. */ | |
115 | ||
116 | static int combine_extras; | |
117 | ||
118 | /* Number of instructions combined in this function. */ | |
119 | ||
120 | static int combine_successes; | |
121 | ||
122 | /* Totals over entire compilation. */ | |
123 | ||
124 | static int total_attempts, total_merges, total_extras, total_successes; | |
9210df58 | 125 | |
230d793d RS |
126 | \f |
127 | /* Vector mapping INSN_UIDs to cuids. | |
5089e22e | 128 | The cuids are like uids but increase monotonically always. |
230d793d RS |
129 | Combine always uses cuids so that it can compare them. |
130 | But actually renumbering the uids, which we used to do, | |
131 | proves to be a bad idea because it makes it hard to compare | |
132 | the dumps produced by earlier passes with those from later passes. */ | |
133 | ||
134 | static int *uid_cuid; | |
4255220d | 135 | static int max_uid_cuid; |
230d793d RS |
136 | |
137 | /* Get the cuid of an insn. */ | |
138 | ||
1427d6d2 RK |
139 | #define INSN_CUID(INSN) \ |
140 | (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) | |
230d793d | 141 | |
42a6ff51 AO |
142 | /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by |
143 | BITS_PER_WORD would invoke undefined behavior. Work around it. */ | |
144 | ||
145 | #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \ | |
505ddab6 | 146 | (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1) |
42a6ff51 | 147 | |
230d793d RS |
148 | /* Maximum register number, which is the size of the tables below. */ |
149 | ||
770ae6cc | 150 | static unsigned int combine_max_regno; |
230d793d | 151 | |
5eaad481 PB |
152 | struct reg_stat { |
153 | /* Record last point of death of (hard or pseudo) register n. */ | |
154 | rtx last_death; | |
230d793d | 155 | |
5eaad481 PB |
156 | /* Record last point of modification of (hard or pseudo) register n. */ |
157 | rtx last_set; | |
230d793d | 158 | |
5eaad481 PB |
159 | /* The next group of fields allows the recording of the last value assigned |
160 | to (hard or pseudo) register n. We use this information to see if an | |
161 | operation being processed is redundant given a prior operation performed | |
162 | on the register. For example, an `and' with a constant is redundant if | |
163 | all the zero bits are already known to be turned off. | |
230d793d | 164 | |
5eaad481 PB |
165 | We use an approach similar to that used by cse, but change it in the |
166 | following ways: | |
167 | ||
168 | (1) We do not want to reinitialize at each label. | |
169 | (2) It is useful, but not critical, to know the actual value assigned | |
170 | to a register. Often just its form is helpful. | |
171 | ||
172 | Therefore, we maintain the following fields: | |
173 | ||
174 | last_set_value the last value assigned | |
175 | last_set_label records the value of label_tick when the | |
176 | register was assigned | |
177 | last_set_table_tick records the value of label_tick when a | |
178 | value using the register is assigned | |
179 | last_set_invalid set to nonzero when it is not valid | |
180 | to use the value of this register in some | |
181 | register's value | |
182 | ||
183 | To understand the usage of these tables, it is important to understand | |
184 | the distinction between the value in last_set_value being valid and | |
185 | the register being validly contained in some other expression in the | |
186 | table. | |
187 | ||
188 | (The next two parameters are out of date). | |
189 | ||
190 | reg_stat[i].last_set_value is valid if it is nonzero, and either | |
191 | reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. | |
192 | ||
193 | Register I may validly appear in any expression returned for the value | |
194 | of another register if reg_n_sets[i] is 1. It may also appear in the | |
195 | value for register J if reg_stat[j].last_set_invalid is zero, or | |
196 | reg_stat[i].last_set_label < reg_stat[j].last_set_label. | |
197 | ||
198 | If an expression is found in the table containing a register which may | |
199 | not validly appear in an expression, the register is replaced by | |
200 | something that won't match, (clobber (const_int 0)). */ | |
201 | ||
202 | /* Record last value assigned to (hard or pseudo) register n. */ | |
203 | ||
204 | rtx last_set_value; | |
205 | ||
206 | /* Record the value of label_tick when an expression involving register n | |
207 | is placed in last_set_value. */ | |
208 | ||
209 | int last_set_table_tick; | |
210 | ||
211 | /* Record the value of label_tick when the value for register n is placed in | |
212 | last_set_value. */ | |
213 | ||
214 | int last_set_label; | |
215 | ||
216 | /* These fields are maintained in parallel with last_set_value and are | |
324a6c95 | 217 | used to store the mode in which the register was last set, the bits |
5eaad481 PB |
218 | that were known to be zero when it was last set, and the number of |
219 | sign bits copies it was known to have when it was last set. */ | |
220 | ||
221 | unsigned HOST_WIDE_INT last_set_nonzero_bits; | |
222 | char last_set_sign_bit_copies; | |
223 | ENUM_BITFIELD(machine_mode) last_set_mode : 8; | |
224 | ||
225 | /* Set nonzero if references to register n in expressions should not be | |
226 | used. last_set_invalid is set nonzero when this register is being | |
227 | assigned to and last_set_table_tick == label_tick. */ | |
228 | ||
229 | char last_set_invalid; | |
230 | ||
231 | /* Some registers that are set more than once and used in more than one | |
232 | basic block are nevertheless always set in similar ways. For example, | |
233 | a QImode register may be loaded from memory in two places on a machine | |
234 | where byte loads zero extend. | |
235 | ||
236 | We record in the following fields if a register has some leading bits | |
237 | that are always equal to the sign bit, and what we know about the | |
238 | nonzero bits of a register, specifically which bits are known to be | |
239 | zero. | |
240 | ||
241 | If an entry is zero, it means that we don't know anything special. */ | |
242 | ||
243 | unsigned char sign_bit_copies; | |
244 | ||
245 | unsigned HOST_WIDE_INT nonzero_bits; | |
246 | }; | |
247 | ||
248 | static struct reg_stat *reg_stat; | |
230d793d RS |
249 | |
250 | /* Record the cuid of the last insn that invalidated memory | |
251 | (anything that writes memory, and subroutine calls, but not pushes). */ | |
252 | ||
253 | static int mem_last_set; | |
254 | ||
255 | /* Record the cuid of the last CALL_INSN | |
256 | so we can tell whether a potential combination crosses any calls. */ | |
257 | ||
258 | static int last_call_cuid; | |
259 | ||
260 | /* When `subst' is called, this is the insn that is being modified | |
261 | (by combining in a previous insn). The PATTERN of this insn | |
262 | is still the old pattern partially modified and it should not be | |
263 | looked at, but this may be used to examine the successors of the insn | |
264 | to judge whether a simplification is valid. */ | |
265 | ||
266 | static rtx subst_insn; | |
267 | ||
268 | /* This is the lowest CUID that `subst' is currently dealing with. | |
269 | get_last_value will not return a value if the register was set at or | |
270 | after this CUID. If not for this mechanism, we could get confused if | |
271 | I2 or I1 in try_combine were an insn that used the old value of a register | |
272 | to obtain a new value. In that case, we might erroneously get the | |
273 | new value of the register when we wanted the old one. */ | |
274 | ||
275 | static int subst_low_cuid; | |
276 | ||
6e25d159 RK |
277 | /* This contains any hard registers that are used in newpat; reg_dead_at_p |
278 | must consider all these registers to be always live. */ | |
279 | ||
280 | static HARD_REG_SET newpat_used_regs; | |
281 | ||
abe6e52f RK |
282 | /* This is an insn to which a LOG_LINKS entry has been added. If this |
283 | insn is the earlier than I2 or I3, combine should rescan starting at | |
284 | that location. */ | |
285 | ||
286 | static rtx added_links_insn; | |
287 | ||
f6366fc7 ZD |
288 | /* Basic block in which we are performing combines. */ |
289 | static basic_block this_basic_block; | |
715e7fbc | 290 | |
663522cb KH |
291 | /* A bitmap indicating which blocks had registers go dead at entry. |
292 | After combine, we'll need to re-do global life analysis with | |
715e7fbc RH |
293 | those blocks as starting points. */ |
294 | static sbitmap refresh_blocks; | |
230d793d | 295 | \f |
6fd21094 | 296 | /* The following array records the insn_rtx_cost for every insn |
64b8935d RS |
297 | in the instruction stream. */ |
298 | ||
299 | static int *uid_insn_cost; | |
300 | ||
301 | /* Length of the currently allocated uid_insn_cost array. */ | |
302 | ||
303 | static int last_insn_cost; | |
304 | ||
0f41302f | 305 | /* Incremented for each label. */ |
230d793d | 306 | |
568356af | 307 | static int label_tick; |
230d793d | 308 | |
5eaad481 PB |
309 | /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the |
310 | largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ | |
230d793d | 311 | |
951553af | 312 | static enum machine_mode nonzero_bits_mode; |
230d793d | 313 | |
5eaad481 PB |
314 | /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can |
315 | be safely used. It is zero while computing them and after combine has | |
316 | completed. This former test prevents propagating values based on | |
317 | previously set values, which can be incorrect if a variable is modified | |
318 | in a loop. */ | |
230d793d | 319 | |
951553af | 320 | static int nonzero_sign_valid; |
55310dad | 321 | |
230d793d RS |
322 | \f |
323 | /* Record one modification to rtl structure | |
324 | to be undone by storing old_contents into *where. | |
325 | is_int is 1 if the contents are an int. */ | |
326 | ||
327 | struct undo | |
328 | { | |
241cea85 | 329 | struct undo *next; |
230d793d | 330 | int is_int; |
3129af4c RS |
331 | union {rtx r; int i;} old_contents; |
332 | union {rtx *r; int *i;} where; | |
230d793d RS |
333 | }; |
334 | ||
335 | /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
336 | num_undo says how many are currently recorded. | |
337 | ||
230d793d | 338 | other_insn is nonzero if we have modified some other insn in the process |
f1c6ba8b | 339 | of working on subst_insn. It must be verified too. */ |
230d793d RS |
340 | |
341 | struct undobuf | |
342 | { | |
241cea85 RK |
343 | struct undo *undos; |
344 | struct undo *frees; | |
230d793d RS |
345 | rtx other_insn; |
346 | }; | |
347 | ||
348 | static struct undobuf undobuf; | |
349 | ||
230d793d RS |
350 | /* Number of times the pseudo being substituted for |
351 | was found and replaced. */ | |
352 | ||
353 | static int n_occurrences; | |
354 | ||
2f93eea8 PB |
355 | static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx, |
356 | enum machine_mode, | |
357 | unsigned HOST_WIDE_INT, | |
358 | unsigned HOST_WIDE_INT *); | |
359 | static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx, | |
360 | enum machine_mode, | |
361 | unsigned int, unsigned int *); | |
79a490a9 AJ |
362 | static void do_SUBST (rtx *, rtx); |
363 | static void do_SUBST_INT (int *, int); | |
5eaad481 | 364 | static void init_reg_last (void); |
79a490a9 AJ |
365 | static void setup_incoming_promotions (void); |
366 | static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *); | |
367 | static int cant_combine_insn_p (rtx); | |
368 | static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *); | |
79a490a9 AJ |
369 | static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *); |
370 | static int contains_muldiv (rtx); | |
371 | static rtx try_combine (rtx, rtx, rtx, int *); | |
372 | static void undo_all (void); | |
373 | static void undo_commit (void); | |
374 | static rtx *find_split_point (rtx *, rtx); | |
375 | static rtx subst (rtx, rtx, rtx, int, int); | |
6621d78e | 376 | static rtx combine_simplify_rtx (rtx, enum machine_mode, int); |
79a490a9 AJ |
377 | static rtx simplify_if_then_else (rtx); |
378 | static rtx simplify_set (rtx); | |
6621d78e | 379 | static rtx simplify_logical (rtx); |
79a490a9 AJ |
380 | static rtx expand_compound_operation (rtx); |
381 | static rtx expand_field_assignment (rtx); | |
382 | static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT, | |
383 | rtx, unsigned HOST_WIDE_INT, int, int, int); | |
384 | static rtx extract_left_shift (rtx, int); | |
385 | static rtx make_compound_operation (rtx, enum rtx_code); | |
386 | static int get_pos_from_mask (unsigned HOST_WIDE_INT, | |
387 | unsigned HOST_WIDE_INT *); | |
388 | static rtx force_to_mode (rtx, enum machine_mode, | |
389 | unsigned HOST_WIDE_INT, rtx, int); | |
390 | static rtx if_then_else_cond (rtx, rtx *, rtx *); | |
391 | static rtx known_cond (rtx, enum rtx_code, rtx, rtx); | |
392 | static int rtx_equal_for_field_assignment_p (rtx, rtx); | |
393 | static rtx make_field_assignment (rtx); | |
394 | static rtx apply_distributive_law (rtx); | |
bcb34aa3 | 395 | static rtx distribute_and_simplify_rtx (rtx, int); |
79a490a9 AJ |
396 | static rtx simplify_and_const_int (rtx, enum machine_mode, rtx, |
397 | unsigned HOST_WIDE_INT); | |
79a490a9 AJ |
398 | static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, |
399 | HOST_WIDE_INT, enum machine_mode, int *); | |
400 | static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx, | |
401 | int); | |
402 | static int recog_for_combine (rtx *, rtx, rtx *); | |
403 | static rtx gen_lowpart_for_combine (enum machine_mode, rtx); | |
79a490a9 AJ |
404 | static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); |
405 | static void update_table_tick (rtx); | |
406 | static void record_value_for_reg (rtx, rtx, rtx); | |
407 | static void check_promoted_subreg (rtx, rtx); | |
408 | static void record_dead_and_set_regs_1 (rtx, rtx, void *); | |
409 | static void record_dead_and_set_regs (rtx); | |
410 | static int get_last_value_validate (rtx *, rtx, int, int); | |
411 | static rtx get_last_value (rtx); | |
412 | static int use_crosses_set_p (rtx, int); | |
413 | static void reg_dead_at_p_1 (rtx, rtx, void *); | |
414 | static int reg_dead_at_p (rtx, rtx); | |
415 | static void move_deaths (rtx, rtx, int, rtx, rtx *); | |
416 | static int reg_bitfield_target_p (rtx, rtx); | |
4bbae09f | 417 | static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx); |
79a490a9 AJ |
418 | static void distribute_links (rtx); |
419 | static void mark_used_regs_combine (rtx); | |
420 | static int insn_cuid (rtx); | |
421 | static void record_promoted_value (rtx, rtx); | |
67962db5 RS |
422 | static int unmentioned_reg_p_1 (rtx *, void *); |
423 | static bool unmentioned_reg_p (rtx, rtx); | |
2f93eea8 PB |
424 | \f |
425 | ||
426 | /* It is not safe to use ordinary gen_lowpart in combine. | |
427 | See comments in gen_lowpart_for_combine. */ | |
428 | #undef RTL_HOOKS_GEN_LOWPART | |
429 | #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine | |
430 | ||
bf667275 PB |
431 | /* Our implementation of gen_lowpart never emits a new pseudo. */ |
432 | #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT | |
433 | #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine | |
434 | ||
2f93eea8 PB |
435 | #undef RTL_HOOKS_REG_NONZERO_REG_BITS |
436 | #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine | |
437 | ||
438 | #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES | |
439 | #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine | |
440 | ||
441 | static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; | |
442 | ||
230d793d | 443 | \f |
76095e2f RH |
444 | /* Substitute NEWVAL, an rtx expression, into INTO, a place in some |
445 | insn. The substitution can be undone by undo_all. If INTO is already | |
446 | set to NEWVAL, do not record this change. Because computing NEWVAL might | |
447 | also call SUBST, we have to compute it before we put anything into | |
448 | the undo table. */ | |
449 | ||
450 | static void | |
79a490a9 | 451 | do_SUBST (rtx *into, rtx newval) |
76095e2f RH |
452 | { |
453 | struct undo *buf; | |
454 | rtx oldval = *into; | |
455 | ||
456 | if (oldval == newval) | |
457 | return; | |
458 | ||
4161da12 AO |
459 | /* We'd like to catch as many invalid transformations here as |
460 | possible. Unfortunately, there are way too many mode changes | |
461 | that are perfectly valid, so we'd waste too much effort for | |
462 | little gain doing the checks here. Focus on catching invalid | |
463 | transformations involving integer constants. */ | |
464 | if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT | |
465 | && GET_CODE (newval) == CONST_INT) | |
466 | { | |
467 | /* Sanity check that we're replacing oldval with a CONST_INT | |
468 | that is a valid sign-extension for the original mode. */ | |
341c100f NS |
469 | gcc_assert (INTVAL (newval) |
470 | == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); | |
4161da12 AO |
471 | |
472 | /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a | |
473 | CONST_INT is not valid, because after the replacement, the | |
474 | original mode would be gone. Unfortunately, we can't tell | |
475 | when do_SUBST is called to replace the operand thereof, so we | |
476 | perform this test on oldval instead, checking whether an | |
477 | invalid replacement took place before we got here. */ | |
341c100f NS |
478 | gcc_assert (!(GET_CODE (oldval) == SUBREG |
479 | && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)); | |
480 | gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND | |
481 | && GET_CODE (XEXP (oldval, 0)) == CONST_INT)); | |
e869aa39 | 482 | } |
4161da12 | 483 | |
76095e2f RH |
484 | if (undobuf.frees) |
485 | buf = undobuf.frees, undobuf.frees = buf->next; | |
486 | else | |
703ad42b | 487 | buf = xmalloc (sizeof (struct undo)); |
76095e2f RH |
488 | |
489 | buf->is_int = 0; | |
490 | buf->where.r = into; | |
491 | buf->old_contents.r = oldval; | |
492 | *into = newval; | |
493 | ||
494 | buf->next = undobuf.undos, undobuf.undos = buf; | |
495 | } | |
496 | ||
497 | #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) | |
498 | ||
499 | /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution | |
500 | for the value of a HOST_WIDE_INT value (including CONST_INT) is | |
501 | not safe. */ | |
502 | ||
503 | static void | |
79a490a9 | 504 | do_SUBST_INT (int *into, int newval) |
76095e2f RH |
505 | { |
506 | struct undo *buf; | |
3129af4c | 507 | int oldval = *into; |
76095e2f RH |
508 | |
509 | if (oldval == newval) | |
510 | return; | |
511 | ||
512 | if (undobuf.frees) | |
513 | buf = undobuf.frees, undobuf.frees = buf->next; | |
514 | else | |
703ad42b | 515 | buf = xmalloc (sizeof (struct undo)); |
76095e2f RH |
516 | |
517 | buf->is_int = 1; | |
518 | buf->where.i = into; | |
519 | buf->old_contents.i = oldval; | |
520 | *into = newval; | |
521 | ||
522 | buf->next = undobuf.undos, undobuf.undos = buf; | |
523 | } | |
524 | ||
525 | #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) | |
526 | \f | |
64b8935d | 527 | /* Subroutine of try_combine. Determine whether the combine replacement |
6fd21094 | 528 | patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost |
64b8935d RS |
529 | that the original instruction sequence I1, I2 and I3. Note that I1 |
530 | and/or NEWI2PAT may be NULL_RTX. This function returns false, if the | |
531 | costs of all instructions can be estimated, and the replacements are | |
532 | more expensive than the original sequence. */ | |
533 | ||
534 | static bool | |
535 | combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat) | |
536 | { | |
537 | int i1_cost, i2_cost, i3_cost; | |
538 | int new_i2_cost, new_i3_cost; | |
539 | int old_cost, new_cost; | |
540 | ||
6fd21094 | 541 | /* Lookup the original insn_rtx_costs. */ |
64b8935d RS |
542 | i2_cost = INSN_UID (i2) <= last_insn_cost |
543 | ? uid_insn_cost[INSN_UID (i2)] : 0; | |
544 | i3_cost = INSN_UID (i3) <= last_insn_cost | |
545 | ? uid_insn_cost[INSN_UID (i3)] : 0; | |
546 | ||
547 | if (i1) | |
548 | { | |
549 | i1_cost = INSN_UID (i1) <= last_insn_cost | |
550 | ? uid_insn_cost[INSN_UID (i1)] : 0; | |
551 | old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0) | |
552 | ? i1_cost + i2_cost + i3_cost : 0; | |
553 | } | |
554 | else | |
555 | { | |
556 | old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; | |
557 | i1_cost = 0; | |
558 | } | |
559 | ||
6fd21094 RS |
560 | /* Calculate the replacement insn_rtx_costs. */ |
561 | new_i3_cost = insn_rtx_cost (newpat); | |
64b8935d RS |
562 | if (newi2pat) |
563 | { | |
6fd21094 | 564 | new_i2_cost = insn_rtx_cost (newi2pat); |
64b8935d RS |
565 | new_cost = (new_i2_cost > 0 && new_i3_cost > 0) |
566 | ? new_i2_cost + new_i3_cost : 0; | |
567 | } | |
568 | else | |
569 | { | |
570 | new_cost = new_i3_cost; | |
571 | new_i2_cost = 0; | |
572 | } | |
573 | ||
6bd26f0b ILT |
574 | if (undobuf.other_insn) |
575 | { | |
576 | int old_other_cost, new_other_cost; | |
577 | ||
578 | old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost | |
579 | ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0); | |
580 | new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn)); | |
581 | if (old_other_cost > 0 && new_other_cost > 0) | |
582 | { | |
583 | old_cost += old_other_cost; | |
584 | new_cost += new_other_cost; | |
585 | } | |
586 | else | |
587 | old_cost = 0; | |
588 | } | |
589 | ||
64b8935d RS |
590 | /* Disallow this recombination if both new_cost and old_cost are |
591 | greater than zero, and new_cost is greater than old cost. */ | |
6bd26f0b | 592 | if (old_cost > 0 |
64b8935d RS |
593 | && new_cost > old_cost) |
594 | { | |
595 | if (dump_file) | |
596 | { | |
597 | if (i1) | |
598 | { | |
599 | fprintf (dump_file, | |
600 | "rejecting combination of insns %d, %d and %d\n", | |
601 | INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
602 | fprintf (dump_file, "original costs %d + %d + %d = %d\n", | |
603 | i1_cost, i2_cost, i3_cost, old_cost); | |
604 | } | |
605 | else | |
606 | { | |
607 | fprintf (dump_file, | |
608 | "rejecting combination of insns %d and %d\n", | |
609 | INSN_UID (i2), INSN_UID (i3)); | |
610 | fprintf (dump_file, "original costs %d + %d = %d\n", | |
611 | i2_cost, i3_cost, old_cost); | |
612 | } | |
613 | ||
614 | if (newi2pat) | |
615 | { | |
616 | fprintf (dump_file, "replacement costs %d + %d = %d\n", | |
617 | new_i2_cost, new_i3_cost, new_cost); | |
618 | } | |
619 | else | |
620 | fprintf (dump_file, "replacement cost %d\n", new_cost); | |
621 | } | |
622 | ||
623 | return false; | |
624 | } | |
625 | ||
626 | /* Update the uid_insn_cost array with the replacement costs. */ | |
627 | uid_insn_cost[INSN_UID (i2)] = new_i2_cost; | |
628 | uid_insn_cost[INSN_UID (i3)] = new_i3_cost; | |
629 | if (i1) | |
630 | uid_insn_cost[INSN_UID (i1)] = 0; | |
631 | ||
632 | return true; | |
633 | } | |
634 | \f | |
230d793d | 635 | /* Main entry point for combiner. F is the first insn of the function. |
663522cb | 636 | NREGS is the first unused pseudo-reg number. |
230d793d | 637 | |
da7d8304 | 638 | Return nonzero if the combiner has turned an indirect jump |
44a76fc8 AG |
639 | instruction into a direct jump. */ |
640 | int | |
79a490a9 | 641 | combine_instructions (rtx f, unsigned int nregs) |
230d793d | 642 | { |
b3694847 | 643 | rtx insn, next; |
b729186a | 644 | #ifdef HAVE_cc0 |
b3694847 | 645 | rtx prev; |
b729186a | 646 | #endif |
b3694847 | 647 | int i; |
dfea6c85 | 648 | unsigned int j = 0; |
b3694847 | 649 | rtx links, nextlinks; |
b6e7e9af | 650 | sbitmap_iterator sbi; |
230d793d | 651 | |
44a76fc8 AG |
652 | int new_direct_jump_p = 0; |
653 | ||
230d793d RS |
654 | combine_attempts = 0; |
655 | combine_merges = 0; | |
656 | combine_extras = 0; | |
657 | combine_successes = 0; | |
658 | ||
659 | combine_max_regno = nregs; | |
660 | ||
2f93eea8 | 661 | rtl_hooks = combine_rtl_hooks; |
4de249d9 | 662 | |
5eaad481 | 663 | reg_stat = xcalloc (nregs, sizeof (struct reg_stat)); |
230d793d RS |
664 | |
665 | init_recog_no_volatile (); | |
666 | ||
667 | /* Compute maximum uid value so uid_cuid can be allocated. */ | |
668 | ||
669 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) | |
670 | if (INSN_UID (insn) > i) | |
671 | i = INSN_UID (insn); | |
672 | ||
703ad42b | 673 | uid_cuid = xmalloc ((i + 1) * sizeof (int)); |
4255220d | 674 | max_uid_cuid = i; |
230d793d | 675 | |
951553af | 676 | nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
230d793d | 677 | |
5eaad481 PB |
678 | /* Don't use reg_stat[].nonzero_bits when computing it. This can cause |
679 | problems when, for example, we have j <<= 1 in a loop. */ | |
230d793d | 680 | |
951553af | 681 | nonzero_sign_valid = 0; |
230d793d RS |
682 | |
683 | /* Compute the mapping from uids to cuids. | |
684 | Cuids are numbers assigned to insns, like uids, | |
663522cb | 685 | except that cuids increase monotonically through the code. |
230d793d RS |
686 | |
687 | Scan all SETs and see if we can deduce anything about what | |
951553af | 688 | bits are known to be zero for some registers and how many copies |
d79f08e0 RK |
689 | of the sign bit are known to exist for those registers. |
690 | ||
691 | Also set any known values so that we can use it while searching | |
692 | for what bits are known to be set. */ | |
693 | ||
694 | label_tick = 1; | |
230d793d | 695 | |
7988fd36 RK |
696 | setup_incoming_promotions (); |
697 | ||
d55bc081 | 698 | refresh_blocks = sbitmap_alloc (last_basic_block); |
715e7fbc | 699 | sbitmap_zero (refresh_blocks); |
715e7fbc | 700 | |
6fd21094 | 701 | /* Allocate array of current insn_rtx_costs. */ |
64b8935d RS |
702 | uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int)); |
703 | last_insn_cost = max_uid_cuid; | |
704 | ||
230d793d RS |
705 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) |
706 | { | |
4255220d | 707 | uid_cuid[INSN_UID (insn)] = ++i; |
d79f08e0 RK |
708 | subst_low_cuid = i; |
709 | subst_insn = insn; | |
710 | ||
2c3c49de | 711 | if (INSN_P (insn)) |
d79f08e0 | 712 | { |
663522cb | 713 | note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, |
84832317 | 714 | NULL); |
d79f08e0 | 715 | record_dead_and_set_regs (insn); |
2dab894a RK |
716 | |
717 | #ifdef AUTO_INC_DEC | |
718 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
719 | if (REG_NOTE_KIND (links) == REG_INC) | |
84832317 MM |
720 | set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, |
721 | NULL); | |
2dab894a | 722 | #endif |
64b8935d | 723 | |
6fd21094 RS |
724 | /* Record the current insn_rtx_cost of this instruction. */ |
725 | if (NONJUMP_INSN_P (insn)) | |
726 | uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn)); | |
64b8935d RS |
727 | if (dump_file) |
728 | fprintf(dump_file, "insn_cost %d: %d\n", | |
729 | INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]); | |
d79f08e0 RK |
730 | } |
731 | ||
4b4bf941 | 732 | if (LABEL_P (insn)) |
d79f08e0 | 733 | label_tick++; |
230d793d RS |
734 | } |
735 | ||
951553af | 736 | nonzero_sign_valid = 1; |
230d793d RS |
737 | |
738 | /* Now scan all the insns in forward order. */ | |
739 | ||
740 | label_tick = 1; | |
741 | last_call_cuid = 0; | |
742 | mem_last_set = 0; | |
5eaad481 | 743 | init_reg_last (); |
7988fd36 RK |
744 | setup_incoming_promotions (); |
745 | ||
e0082a72 | 746 | FOR_EACH_BB (this_basic_block) |
230d793d | 747 | { |
a813c111 SB |
748 | for (insn = BB_HEAD (this_basic_block); |
749 | insn != NEXT_INSN (BB_END (this_basic_block)); | |
e0082a72 | 750 | insn = next ? next : NEXT_INSN (insn)) |
230d793d | 751 | { |
e0082a72 | 752 | next = 0; |
aabb6c74 | 753 | |
4b4bf941 | 754 | if (LABEL_P (insn)) |
e0082a72 | 755 | label_tick++; |
aabb6c74 | 756 | |
e0082a72 | 757 | else if (INSN_P (insn)) |
0b17ab2f | 758 | { |
e0082a72 ZD |
759 | /* See if we know about function return values before this |
760 | insn based upon SUBREG flags. */ | |
761 | check_promoted_subreg (insn, PATTERN (insn)); | |
230d793d | 762 | |
e0082a72 | 763 | /* Try this insn with each insn it links back to. */ |
230d793d | 764 | |
e0082a72 ZD |
765 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) |
766 | if ((next = try_combine (insn, XEXP (links, 0), | |
767 | NULL_RTX, &new_direct_jump_p)) != 0) | |
230d793d | 768 | goto retry; |
0b17ab2f | 769 | |
e0082a72 ZD |
770 | /* Try each sequence of three linked insns ending with this one. */ |
771 | ||
772 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
773 | { | |
774 | rtx link = XEXP (links, 0); | |
775 | ||
776 | /* If the linked insn has been replaced by a note, then there | |
777 | is no point in pursuing this chain any further. */ | |
4b4bf941 | 778 | if (NOTE_P (link)) |
e0082a72 ZD |
779 | continue; |
780 | ||
781 | for (nextlinks = LOG_LINKS (link); | |
782 | nextlinks; | |
783 | nextlinks = XEXP (nextlinks, 1)) | |
784 | if ((next = try_combine (insn, link, | |
785 | XEXP (nextlinks, 0), | |
786 | &new_direct_jump_p)) != 0) | |
787 | goto retry; | |
788 | } | |
230d793d | 789 | |
9b89393b | 790 | #ifdef HAVE_cc0 |
e0082a72 ZD |
791 | /* Try to combine a jump insn that uses CC0 |
792 | with a preceding insn that sets CC0, and maybe with its | |
793 | logical predecessor as well. | |
794 | This is how we make decrement-and-branch insns. | |
795 | We need this special code because data flow connections | |
796 | via CC0 do not get entered in LOG_LINKS. */ | |
797 | ||
4b4bf941 | 798 | if (JUMP_P (insn) |
e0082a72 | 799 | && (prev = prev_nonnote_insn (insn)) != 0 |
4b4bf941 | 800 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
801 | && sets_cc0_p (PATTERN (prev))) |
802 | { | |
803 | if ((next = try_combine (insn, prev, | |
804 | NULL_RTX, &new_direct_jump_p)) != 0) | |
805 | goto retry; | |
806 | ||
807 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
808 | nextlinks = XEXP (nextlinks, 1)) | |
809 | if ((next = try_combine (insn, prev, | |
810 | XEXP (nextlinks, 0), | |
811 | &new_direct_jump_p)) != 0) | |
812 | goto retry; | |
813 | } | |
230d793d | 814 | |
e0082a72 | 815 | /* Do the same for an insn that explicitly references CC0. */ |
4b4bf941 | 816 | if (NONJUMP_INSN_P (insn) |
e0082a72 | 817 | && (prev = prev_nonnote_insn (insn)) != 0 |
4b4bf941 | 818 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
819 | && sets_cc0_p (PATTERN (prev)) |
820 | && GET_CODE (PATTERN (insn)) == SET | |
821 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
822 | { | |
823 | if ((next = try_combine (insn, prev, | |
824 | NULL_RTX, &new_direct_jump_p)) != 0) | |
825 | goto retry; | |
826 | ||
827 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
828 | nextlinks = XEXP (nextlinks, 1)) | |
829 | if ((next = try_combine (insn, prev, | |
830 | XEXP (nextlinks, 0), | |
831 | &new_direct_jump_p)) != 0) | |
832 | goto retry; | |
833 | } | |
230d793d | 834 | |
e0082a72 ZD |
835 | /* Finally, see if any of the insns that this insn links to |
836 | explicitly references CC0. If so, try this insn, that insn, | |
837 | and its predecessor if it sets CC0. */ | |
838 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
4b4bf941 | 839 | if (NONJUMP_INSN_P (XEXP (links, 0)) |
e0082a72 ZD |
840 | && GET_CODE (PATTERN (XEXP (links, 0))) == SET |
841 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) | |
842 | && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 | |
4b4bf941 | 843 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
844 | && sets_cc0_p (PATTERN (prev)) |
845 | && (next = try_combine (insn, XEXP (links, 0), | |
846 | prev, &new_direct_jump_p)) != 0) | |
847 | goto retry; | |
9b89393b | 848 | #endif |
e0082a72 ZD |
849 | |
850 | /* Try combining an insn with two different insns whose results it | |
851 | uses. */ | |
852 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
853 | for (nextlinks = XEXP (links, 1); nextlinks; | |
854 | nextlinks = XEXP (nextlinks, 1)) | |
855 | if ((next = try_combine (insn, XEXP (links, 0), | |
856 | XEXP (nextlinks, 0), | |
857 | &new_direct_jump_p)) != 0) | |
858 | goto retry; | |
859 | ||
67962db5 RS |
860 | /* Try this insn with each REG_EQUAL note it links back to. */ |
861 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
862 | { | |
863 | rtx set, note; | |
864 | rtx temp = XEXP (links, 0); | |
865 | if ((set = single_set (temp)) != 0 | |
866 | && (note = find_reg_equal_equiv_note (temp)) != 0 | |
65030b76 | 867 | && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST |
67962db5 RS |
868 | /* Avoid using a register that may already been marked |
869 | dead by an earlier instruction. */ | |
65030b76 RH |
870 | && ! unmentioned_reg_p (note, SET_SRC (set)) |
871 | && (GET_MODE (note) == VOIDmode | |
872 | ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set))) | |
873 | : GET_MODE (SET_DEST (set)) == GET_MODE (note))) | |
67962db5 RS |
874 | { |
875 | /* Temporarily replace the set's source with the | |
876 | contents of the REG_EQUAL note. The insn will | |
877 | be deleted or recognized by try_combine. */ | |
878 | rtx orig = SET_SRC (set); | |
65030b76 | 879 | SET_SRC (set) = note; |
67962db5 RS |
880 | next = try_combine (insn, temp, NULL_RTX, |
881 | &new_direct_jump_p); | |
882 | if (next) | |
883 | goto retry; | |
884 | SET_SRC (set) = orig; | |
885 | } | |
886 | } | |
887 | ||
4b4bf941 | 888 | if (!NOTE_P (insn)) |
e0082a72 ZD |
889 | record_dead_and_set_regs (insn); |
890 | ||
891 | retry: | |
892 | ; | |
893 | } | |
230d793d RS |
894 | } |
895 | } | |
c51d95ec | 896 | clear_bb_flags (); |
230d793d | 897 | |
b6e7e9af KH |
898 | EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi) |
899 | BASIC_BLOCK (j)->flags |= BB_DIRTY; | |
25cd19de | 900 | new_direct_jump_p |= purge_all_dead_edges (); |
827c06b6 | 901 | delete_noop_moves (); |
0005550b | 902 | |
c51d95ec JH |
903 | update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES, |
904 | PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE | |
905 | | PROP_KILL_DEAD_CODE); | |
c05ddfa7 MM |
906 | |
907 | /* Clean up. */ | |
715e7fbc | 908 | sbitmap_free (refresh_blocks); |
64b8935d | 909 | free (uid_insn_cost); |
5eaad481 | 910 | free (reg_stat); |
c05ddfa7 | 911 | free (uid_cuid); |
715e7fbc | 912 | |
e7749837 RH |
913 | { |
914 | struct undo *undo, *next; | |
915 | for (undo = undobuf.frees; undo; undo = next) | |
916 | { | |
917 | next = undo->next; | |
918 | free (undo); | |
919 | } | |
920 | undobuf.frees = 0; | |
921 | } | |
922 | ||
230d793d RS |
923 | total_attempts += combine_attempts; |
924 | total_merges += combine_merges; | |
925 | total_extras += combine_extras; | |
926 | total_successes += combine_successes; | |
1a26b032 | 927 | |
951553af | 928 | nonzero_sign_valid = 0; |
2f93eea8 | 929 | rtl_hooks = general_rtl_hooks; |
972b320c R |
930 | |
931 | /* Make recognizer allow volatile MEMs again. */ | |
932 | init_recog (); | |
44a76fc8 AG |
933 | |
934 | return new_direct_jump_p; | |
230d793d | 935 | } |
ef026f91 | 936 | |
5eaad481 | 937 | /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ |
ef026f91 RS |
938 | |
939 | static void | |
5eaad481 | 940 | init_reg_last (void) |
ef026f91 | 941 | { |
5eaad481 PB |
942 | unsigned int i; |
943 | for (i = 0; i < combine_max_regno; i++) | |
944 | memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies)); | |
ef026f91 | 945 | } |
230d793d | 946 | \f |
7988fd36 RK |
947 | /* Set up any promoted values for incoming argument registers. */ |
948 | ||
ee791cc3 | 949 | static void |
79a490a9 | 950 | setup_incoming_promotions (void) |
7988fd36 | 951 | { |
770ae6cc | 952 | unsigned int regno; |
7988fd36 RK |
953 | rtx reg; |
954 | enum machine_mode mode; | |
955 | int unsignedp; | |
956 | rtx first = get_insns (); | |
957 | ||
61f71b34 DD |
958 | if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl))) |
959 | { | |
61f71b34 DD |
960 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
961 | /* Check whether this register can hold an incoming pointer | |
962 | argument. FUNCTION_ARG_REGNO_P tests outgoing register | |
963 | numbers, so translate if necessary due to register windows. */ | |
964 | if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) | |
965 | && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) | |
966 | { | |
967 | record_value_for_reg | |
968 | (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND | |
969 | : SIGN_EXTEND), | |
970 | GET_MODE (reg), | |
971 | gen_rtx_CLOBBER (mode, const0_rtx))); | |
972 | } | |
973 | } | |
7988fd36 RK |
974 | } |
975 | \f | |
91102d5a RK |
976 | /* Called via note_stores. If X is a pseudo that is narrower than |
977 | HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. | |
230d793d RS |
978 | |
979 | If we are setting only a portion of X and we can't figure out what | |
980 | portion, assume all bits will be used since we don't know what will | |
d0ab8cd3 RK |
981 | be happening. |
982 | ||
983 | Similarly, set how many bits of X are known to be copies of the sign bit | |
663522cb | 984 | at all locations in the function. This is the smallest number implied |
d0ab8cd3 | 985 | by any set of X. */ |
230d793d RS |
986 | |
987 | static void | |
79a490a9 AJ |
988 | set_nonzero_bits_and_sign_copies (rtx x, rtx set, |
989 | void *data ATTRIBUTE_UNUSED) | |
230d793d | 990 | { |
770ae6cc | 991 | unsigned int num; |
d0ab8cd3 | 992 | |
f8cfc6aa | 993 | if (REG_P (x) |
230d793d | 994 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
e8095e80 RK |
995 | /* If this register is undefined at the start of the file, we can't |
996 | say what its contents were. */ | |
5e2d947c JH |
997 | && ! REGNO_REG_SET_P |
998 | (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x)) | |
5f4f0e22 | 999 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) |
230d793d | 1000 | { |
2dab894a | 1001 | if (set == 0 || GET_CODE (set) == CLOBBER) |
e8095e80 | 1002 | { |
5eaad481 PB |
1003 | reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1004 | reg_stat[REGNO (x)].sign_bit_copies = 1; | |
e8095e80 RK |
1005 | return; |
1006 | } | |
230d793d RS |
1007 | |
1008 | /* If this is a complex assignment, see if we can convert it into a | |
5089e22e | 1009 | simple assignment. */ |
230d793d | 1010 | set = expand_field_assignment (set); |
d79f08e0 RK |
1011 | |
1012 | /* If this is a simple assignment, or we have a paradoxical SUBREG, | |
1013 | set what we know about X. */ | |
1014 | ||
1015 | if (SET_DEST (set) == x | |
1016 | || (GET_CODE (SET_DEST (set)) == SUBREG | |
705c7b3b JW |
1017 | && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) |
1018 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) | |
d79f08e0 | 1019 | && SUBREG_REG (SET_DEST (set)) == x)) |
d0ab8cd3 | 1020 | { |
9afa3d54 RK |
1021 | rtx src = SET_SRC (set); |
1022 | ||
1023 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
1024 | /* If X is narrower than a word and SRC is a non-negative | |
1025 | constant that would appear negative in the mode of X, | |
5eaad481 | 1026 | sign-extend it for use in reg_stat[].nonzero_bits because some |
9afa3d54 | 1027 | machines (maybe most) will actually do the sign-extension |
663522cb | 1028 | and this is the conservative approach. |
9afa3d54 RK |
1029 | |
1030 | ??? For 2.5, try to tighten up the MD files in this regard | |
1031 | instead of this kludge. */ | |
1032 | ||
1033 | if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD | |
1034 | && GET_CODE (src) == CONST_INT | |
1035 | && INTVAL (src) > 0 | |
1036 | && 0 != (INTVAL (src) | |
1037 | & ((HOST_WIDE_INT) 1 | |
9e69be8c | 1038 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
9afa3d54 RK |
1039 | src = GEN_INT (INTVAL (src) |
1040 | | ((HOST_WIDE_INT) (-1) | |
1041 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
1042 | #endif | |
1043 | ||
0a0440c9 | 1044 | /* Don't call nonzero_bits if it cannot change anything. */ |
5eaad481 PB |
1045 | if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) |
1046 | reg_stat[REGNO (x)].nonzero_bits | |
0a0440c9 | 1047 | |= nonzero_bits (src, nonzero_bits_mode); |
d0ab8cd3 | 1048 | num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); |
5eaad481 PB |
1049 | if (reg_stat[REGNO (x)].sign_bit_copies == 0 |
1050 | || reg_stat[REGNO (x)].sign_bit_copies > num) | |
1051 | reg_stat[REGNO (x)].sign_bit_copies = num; | |
d0ab8cd3 | 1052 | } |
230d793d | 1053 | else |
d0ab8cd3 | 1054 | { |
5eaad481 PB |
1055 | reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1056 | reg_stat[REGNO (x)].sign_bit_copies = 1; | |
d0ab8cd3 | 1057 | } |
230d793d RS |
1058 | } |
1059 | } | |
1060 | \f | |
1061 | /* See if INSN can be combined into I3. PRED and SUCC are optionally | |
1062 | insns that were previously combined into I3 or that will be combined | |
1063 | into the merger of INSN and I3. | |
1064 | ||
1065 | Return 0 if the combination is not allowed for any reason. | |
1066 | ||
663522cb | 1067 | If the combination is allowed, *PDEST will be set to the single |
230d793d RS |
1068 | destination of INSN and *PSRC to the single source, and this function |
1069 | will return 1. */ | |
1070 | ||
1071 | static int | |
79a490a9 AJ |
1072 | can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ, |
1073 | rtx *pdest, rtx *psrc) | |
230d793d RS |
1074 | { |
1075 | int i; | |
1076 | rtx set = 0, src, dest; | |
b729186a JL |
1077 | rtx p; |
1078 | #ifdef AUTO_INC_DEC | |
76d31c63 | 1079 | rtx link; |
b729186a | 1080 | #endif |
230d793d RS |
1081 | int all_adjacent = (succ ? (next_active_insn (insn) == succ |
1082 | && next_active_insn (succ) == i3) | |
1083 | : next_active_insn (insn) == i3); | |
1084 | ||
1085 | /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. | |
663522cb | 1086 | or a PARALLEL consisting of such a SET and CLOBBERs. |
230d793d RS |
1087 | |
1088 | If INSN has CLOBBER parallel parts, ignore them for our processing. | |
1089 | By definition, these happen during the execution of the insn. When it | |
1090 | is merged with another insn, all bets are off. If they are, in fact, | |
1091 | needed and aren't also supplied in I3, they may be added by | |
663522cb | 1092 | recog_for_combine. Otherwise, it won't match. |
230d793d RS |
1093 | |
1094 | We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
1095 | note. | |
1096 | ||
663522cb | 1097 | Get the source and destination of INSN. If more than one, can't |
230d793d | 1098 | combine. */ |
663522cb | 1099 | |
230d793d RS |
1100 | if (GET_CODE (PATTERN (insn)) == SET) |
1101 | set = PATTERN (insn); | |
1102 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1103 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1104 | { | |
1105 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1106 | { | |
1107 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
da6fdad3 | 1108 | rtx note; |
230d793d RS |
1109 | |
1110 | switch (GET_CODE (elt)) | |
1111 | { | |
e3258cef R |
1112 | /* This is important to combine floating point insns |
1113 | for the SH4 port. */ | |
1114 | case USE: | |
1115 | /* Combining an isolated USE doesn't make sense. | |
d2604ae9 | 1116 | We depend here on combinable_i3pat to reject them. */ |
e3258cef R |
1117 | /* The code below this loop only verifies that the inputs of |
1118 | the SET in INSN do not change. We call reg_set_between_p | |
eaec9b3d | 1119 | to verify that the REG in the USE does not change between |
e3258cef R |
1120 | I3 and INSN. |
1121 | If the USE in INSN was for a pseudo register, the matching | |
1122 | insn pattern will likely match any register; combining this | |
1123 | with any other USE would only be safe if we knew that the | |
1124 | used registers have identical values, or if there was | |
1125 | something to tell them apart, e.g. different modes. For | |
eaec9b3d | 1126 | now, we forgo such complicated tests and simply disallow |
e3258cef | 1127 | combining of USES of pseudo registers with any other USE. */ |
f8cfc6aa | 1128 | if (REG_P (XEXP (elt, 0)) |
e3258cef R |
1129 | && GET_CODE (PATTERN (i3)) == PARALLEL) |
1130 | { | |
1131 | rtx i3pat = PATTERN (i3); | |
1132 | int i = XVECLEN (i3pat, 0) - 1; | |
770ae6cc RK |
1133 | unsigned int regno = REGNO (XEXP (elt, 0)); |
1134 | ||
e3258cef R |
1135 | do |
1136 | { | |
1137 | rtx i3elt = XVECEXP (i3pat, 0, i); | |
770ae6cc | 1138 | |
e3258cef | 1139 | if (GET_CODE (i3elt) == USE |
f8cfc6aa | 1140 | && REG_P (XEXP (i3elt, 0)) |
e3258cef R |
1141 | && (REGNO (XEXP (i3elt, 0)) == regno |
1142 | ? reg_set_between_p (XEXP (elt, 0), | |
1143 | PREV_INSN (insn), i3) | |
1144 | : regno >= FIRST_PSEUDO_REGISTER)) | |
1145 | return 0; | |
1146 | } | |
1147 | while (--i >= 0); | |
1148 | } | |
1149 | break; | |
1150 | ||
230d793d RS |
1151 | /* We can ignore CLOBBERs. */ |
1152 | case CLOBBER: | |
1153 | break; | |
1154 | ||
1155 | case SET: | |
1156 | /* Ignore SETs whose result isn't used but not those that | |
1157 | have side-effects. */ | |
1158 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
da6fdad3 AM |
1159 | && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX)) |
1160 | || INTVAL (XEXP (note, 0)) <= 0) | |
230d793d RS |
1161 | && ! side_effects_p (elt)) |
1162 | break; | |
1163 | ||
1164 | /* If we have already found a SET, this is a second one and | |
1165 | so we cannot combine with this insn. */ | |
1166 | if (set) | |
1167 | return 0; | |
1168 | ||
1169 | set = elt; | |
1170 | break; | |
1171 | ||
1172 | default: | |
1173 | /* Anything else means we can't combine. */ | |
1174 | return 0; | |
1175 | } | |
1176 | } | |
1177 | ||
1178 | if (set == 0 | |
1179 | /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
1180 | so don't do anything with it. */ | |
1181 | || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1182 | return 0; | |
1183 | } | |
1184 | else | |
1185 | return 0; | |
1186 | ||
1187 | if (set == 0) | |
1188 | return 0; | |
1189 | ||
1190 | set = expand_field_assignment (set); | |
1191 | src = SET_SRC (set), dest = SET_DEST (set); | |
1192 | ||
1193 | /* Don't eliminate a store in the stack pointer. */ | |
1194 | if (dest == stack_pointer_rtx | |
230d793d RS |
1195 | /* Don't combine with an insn that sets a register to itself if it has |
1196 | a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ | |
5f4f0e22 | 1197 | || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) |
62f7f1f5 GK |
1198 | /* Can't merge an ASM_OPERANDS. */ |
1199 | || GET_CODE (src) == ASM_OPERANDS | |
230d793d RS |
1200 | /* Can't merge a function call. */ |
1201 | || GET_CODE (src) == CALL | |
cd5e8f1f | 1202 | /* Don't eliminate a function call argument. */ |
4b4bf941 | 1203 | || (CALL_P (i3) |
4dca5ec5 | 1204 | && (find_reg_fusage (i3, USE, dest) |
f8cfc6aa | 1205 | || (REG_P (dest) |
4dca5ec5 RK |
1206 | && REGNO (dest) < FIRST_PSEUDO_REGISTER |
1207 | && global_regs[REGNO (dest)]))) | |
230d793d RS |
1208 | /* Don't substitute into an incremented register. */ |
1209 | || FIND_REG_INC_NOTE (i3, dest) | |
1210 | || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
2f39b6ca UW |
1211 | /* Don't substitute into a non-local goto, this confuses CFG. */ |
1212 | || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
ec35104c | 1213 | #if 0 |
230d793d | 1214 | /* Don't combine the end of a libcall into anything. */ |
ec35104c JL |
1215 | /* ??? This gives worse code, and appears to be unnecessary, since no |
1216 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does | |
1217 | use REG_RETVAL notes for noconflict blocks, but other code here | |
1218 | makes sure that those insns don't disappear. */ | |
5f4f0e22 | 1219 | || find_reg_note (insn, REG_RETVAL, NULL_RTX) |
ec35104c | 1220 | #endif |
230d793d RS |
1221 | /* Make sure that DEST is not used after SUCC but before I3. */ |
1222 | || (succ && ! all_adjacent | |
1223 | && reg_used_between_p (dest, succ, i3)) | |
1224 | /* Make sure that the value that is to be substituted for the register | |
1225 | does not use any registers whose values alter in between. However, | |
1226 | If the insns are adjacent, a use can't cross a set even though we | |
1227 | think it might (this can happen for a sequence of insns each setting | |
5eaad481 | 1228 | the same destination; last_set of that register might point to |
d81481d3 RK |
1229 | a NOTE). If INSN has a REG_EQUIV note, the register is always |
1230 | equivalent to the memory so the substitution is valid even if there | |
1231 | are intervening stores. Also, don't move a volatile asm or | |
1232 | UNSPEC_VOLATILE across any other insns. */ | |
230d793d | 1233 | || (! all_adjacent |
3c0cb5de | 1234 | && (((!MEM_P (src) |
d81481d3 RK |
1235 | || ! find_reg_note (insn, REG_EQUIV, src)) |
1236 | && use_crosses_set_p (src, INSN_CUID (insn))) | |
a66a10c7 RS |
1237 | || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) |
1238 | || GET_CODE (src) == UNSPEC_VOLATILE)) | |
230d793d RS |
1239 | /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get |
1240 | better register allocation by not doing the combine. */ | |
1241 | || find_reg_note (i3, REG_NO_CONFLICT, dest) | |
1242 | || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) | |
1243 | /* Don't combine across a CALL_INSN, because that would possibly | |
1244 | change whether the life span of some REGs crosses calls or not, | |
1245 | and it is a pain to update that information. | |
1246 | Exception: if source is a constant, moving it later can't hurt. | |
1247 | Accept that special case, because it helps -fforce-addr a lot. */ | |
1248 | || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) | |
1249 | return 0; | |
1250 | ||
1251 | /* DEST must either be a REG or CC0. */ | |
f8cfc6aa | 1252 | if (REG_P (dest)) |
230d793d RS |
1253 | { |
1254 | /* If register alignment is being enforced for multi-word items in all | |
1255 | cases except for parameters, it is possible to have a register copy | |
1256 | insn referencing a hard register that is not allowed to contain the | |
1257 | mode being copied and which would not be valid as an operand of most | |
1258 | insns. Eliminate this problem by not combining with such an insn. | |
1259 | ||
1260 | Also, on some machines we don't want to extend the life of a hard | |
53895717 | 1261 | register. */ |
230d793d | 1262 | |
f8cfc6aa | 1263 | if (REG_P (src) |
230d793d RS |
1264 | && ((REGNO (dest) < FIRST_PSEUDO_REGISTER |
1265 | && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
c448a43e RK |
1266 | /* Don't extend the life of a hard register unless it is |
1267 | user variable (if we have few registers) or it can't | |
1268 | fit into the desired register (meaning something special | |
ecd40809 RK |
1269 | is going on). |
1270 | Also avoid substituting a return register into I3, because | |
1271 | reload can't handle a conflict with constraints of other | |
1272 | inputs. */ | |
230d793d | 1273 | || (REGNO (src) < FIRST_PSEUDO_REGISTER |
53895717 | 1274 | && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) |
230d793d RS |
1275 | return 0; |
1276 | } | |
1277 | else if (GET_CODE (dest) != CC0) | |
1278 | return 0; | |
1279 | ||
45da19e3 | 1280 | |
230d793d RS |
1281 | if (GET_CODE (PATTERN (i3)) == PARALLEL) |
1282 | for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
45da19e3 UW |
1283 | if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) |
1284 | { | |
1285 | /* Don't substitute for a register intended as a clobberable | |
8c27b7d4 | 1286 | operand. */ |
45da19e3 UW |
1287 | rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); |
1288 | if (rtx_equal_p (reg, dest)) | |
1289 | return 0; | |
1290 | ||
1291 | /* If the clobber represents an earlyclobber operand, we must not | |
1292 | substitute an expression containing the clobbered register. | |
647eea9d | 1293 | As we do not analyze the constraint strings here, we have to |
45da19e3 UW |
1294 | make the conservative assumption. However, if the register is |
1295 | a fixed hard reg, the clobber cannot represent any operand; | |
1296 | we leave it up to the machine description to either accept or | |
1297 | reject use-and-clobber patterns. */ | |
1298 | if (!REG_P (reg) | |
1299 | || REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1300 | || !fixed_regs[REGNO (reg)]) | |
1301 | if (reg_overlap_mentioned_p (reg, src)) | |
1302 | return 0; | |
1303 | } | |
230d793d RS |
1304 | |
1305 | /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
d276f2bb | 1306 | or not), reject, unless nothing volatile comes between it and I3 */ |
230d793d RS |
1307 | |
1308 | if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
d276f2bb CM |
1309 | { |
1310 | /* Make sure succ doesn't contain a volatile reference. */ | |
1311 | if (succ != 0 && volatile_refs_p (PATTERN (succ))) | |
1312 | return 0; | |
663522cb | 1313 | |
d276f2bb | 1314 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) |
2c3c49de | 1315 | if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) |
cf0d9408 | 1316 | return 0; |
d276f2bb | 1317 | } |
230d793d | 1318 | |
b79ee7eb RH |
1319 | /* If INSN is an asm, and DEST is a hard register, reject, since it has |
1320 | to be an explicit register variable, and was chosen for a reason. */ | |
1321 | ||
1322 | if (GET_CODE (src) == ASM_OPERANDS | |
f8cfc6aa | 1323 | && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) |
b79ee7eb RH |
1324 | return 0; |
1325 | ||
4b2cb4a2 RS |
1326 | /* If there are any volatile insns between INSN and I3, reject, because |
1327 | they might affect machine state. */ | |
1328 | ||
1329 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
2c3c49de | 1330 | if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) |
4b2cb4a2 RS |
1331 | return 0; |
1332 | ||
17c9bcdd HPN |
1333 | /* If INSN contains an autoincrement or autodecrement, make sure that |
1334 | register is not used between there and I3, and not already used in | |
1335 | I3 either. Neither must it be used in PRED or SUCC, if they exist. | |
230d793d RS |
1336 | Also insist that I3 not be a jump; if it were one |
1337 | and the incremented register were spilled, we would lose. */ | |
1338 | ||
1339 | #ifdef AUTO_INC_DEC | |
1340 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1341 | if (REG_NOTE_KIND (link) == REG_INC | |
4b4bf941 | 1342 | && (JUMP_P (i3) |
230d793d | 1343 | || reg_used_between_p (XEXP (link, 0), insn, i3) |
17c9bcdd HPN |
1344 | || (pred != NULL_RTX |
1345 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) | |
1346 | || (succ != NULL_RTX | |
1347 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) | |
230d793d RS |
1348 | || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) |
1349 | return 0; | |
1350 | #endif | |
1351 | ||
1352 | #ifdef HAVE_cc0 | |
1353 | /* Don't combine an insn that follows a CC0-setting insn. | |
1354 | An insn that uses CC0 must not be separated from the one that sets it. | |
1355 | We do, however, allow I2 to follow a CC0-setting insn if that insn | |
1356 | is passed as I1; in that case it will be deleted also. | |
1357 | We also allow combining in this case if all the insns are adjacent | |
1358 | because that would leave the two CC0 insns adjacent as well. | |
1359 | It would be more logical to test whether CC0 occurs inside I1 or I2, | |
1360 | but that would be much slower, and this ought to be equivalent. */ | |
1361 | ||
1362 | p = prev_nonnote_insn (insn); | |
4b4bf941 | 1363 | if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) |
230d793d RS |
1364 | && ! all_adjacent) |
1365 | return 0; | |
1366 | #endif | |
1367 | ||
1368 | /* If we get here, we have passed all the tests and the combination is | |
1369 | to be allowed. */ | |
1370 | ||
1371 | *pdest = dest; | |
1372 | *psrc = src; | |
1373 | ||
1374 | return 1; | |
1375 | } | |
1376 | \f | |
1377 | /* LOC is the location within I3 that contains its pattern or the component | |
1378 | of a PARALLEL of the pattern. We validate that it is valid for combining. | |
1379 | ||
1380 | One problem is if I3 modifies its output, as opposed to replacing it | |
1381 | entirely, we can't allow the output to contain I2DEST or I1DEST as doing | |
1382 | so would produce an insn that is not equivalent to the original insns. | |
1383 | ||
1384 | Consider: | |
1385 | ||
1386 | (set (reg:DI 101) (reg:DI 100)) | |
1387 | (set (subreg:SI (reg:DI 101) 0) <foo>) | |
1388 | ||
1389 | This is NOT equivalent to: | |
1390 | ||
1391 | (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) | |
23190837 | 1392 | (set (reg:DI 101) (reg:DI 100))]) |
230d793d RS |
1393 | |
1394 | Not only does this modify 100 (in which case it might still be valid | |
663522cb | 1395 | if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. |
230d793d RS |
1396 | |
1397 | We can also run into a problem if I2 sets a register that I1 | |
1398 | uses and I1 gets directly substituted into I3 (not via I2). In that | |
1399 | case, we would be getting the wrong value of I2DEST into I3, so we | |
1400 | must reject the combination. This case occurs when I2 and I1 both | |
1401 | feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
da7d8304 | 1402 | If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source |
230d793d RS |
1403 | of a SET must prevent combination from occurring. |
1404 | ||
230d793d RS |
1405 | Before doing the above check, we first try to expand a field assignment |
1406 | into a set of logical operations. | |
1407 | ||
da7d8304 | 1408 | If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which |
230d793d RS |
1409 | we place a register that is both set and used within I3. If more than one |
1410 | such register is detected, we fail. | |
1411 | ||
1412 | Return 1 if the combination is valid, zero otherwise. */ | |
1413 | ||
1414 | static int | |
79a490a9 AJ |
1415 | combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, |
1416 | int i1_not_in_src, rtx *pi3dest_killed) | |
230d793d RS |
1417 | { |
1418 | rtx x = *loc; | |
1419 | ||
1420 | if (GET_CODE (x) == SET) | |
1421 | { | |
73a39fc4 | 1422 | rtx set = x ; |
230d793d RS |
1423 | rtx dest = SET_DEST (set); |
1424 | rtx src = SET_SRC (set); | |
29a82058 | 1425 | rtx inner_dest = dest; |
663522cb | 1426 | |
230d793d RS |
1427 | while (GET_CODE (inner_dest) == STRICT_LOW_PART |
1428 | || GET_CODE (inner_dest) == SUBREG | |
1429 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
1430 | inner_dest = XEXP (inner_dest, 0); | |
1431 | ||
0595d388 AO |
1432 | /* Check for the case where I3 modifies its output, as discussed |
1433 | above. We don't want to prevent pseudos from being combined | |
1434 | into the address of a MEM, so only prevent the combination if | |
1435 | i1 or i2 set the same MEM. */ | |
1436 | if ((inner_dest != dest && | |
3c0cb5de | 1437 | (!MEM_P (inner_dest) |
0595d388 AO |
1438 | || rtx_equal_p (i2dest, inner_dest) |
1439 | || (i1dest && rtx_equal_p (i1dest, inner_dest))) | |
230d793d RS |
1440 | && (reg_overlap_mentioned_p (i2dest, inner_dest) |
1441 | || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) | |
956d6950 | 1442 | |
53895717 BS |
1443 | /* This is the same test done in can_combine_p except we can't test |
1444 | all_adjacent; we don't have to, since this instruction will stay | |
1445 | in place, thus we are not considering increasing the lifetime of | |
1446 | INNER_DEST. | |
956d6950 JL |
1447 | |
1448 | Also, if this insn sets a function argument, combining it with | |
1449 | something that might need a spill could clobber a previous | |
1450 | function argument; the all_adjacent test in can_combine_p also | |
1451 | checks this; here, we do a more specific test for this case. */ | |
663522cb | 1452 | |
f8cfc6aa | 1453 | || (REG_P (inner_dest) |
dfbe1b2f | 1454 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER |
c448a43e | 1455 | && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), |
53895717 | 1456 | GET_MODE (inner_dest)))) |
230d793d RS |
1457 | || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) |
1458 | return 0; | |
1459 | ||
1460 | /* If DEST is used in I3, it is being killed in this insn, | |
663522cb | 1461 | so record that for later. |
36a9c2e9 JL |
1462 | Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the |
1463 | STACK_POINTER_REGNUM, since these are always considered to be | |
1464 | live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
f8cfc6aa | 1465 | if (pi3dest_killed && REG_P (dest) |
36a9c2e9 JL |
1466 | && reg_referenced_p (dest, PATTERN (i3)) |
1467 | && REGNO (dest) != FRAME_POINTER_REGNUM | |
6d7096b0 DE |
1468 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1469 | && REGNO (dest) != HARD_FRAME_POINTER_REGNUM | |
1470 | #endif | |
36a9c2e9 JL |
1471 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1472 | && (REGNO (dest) != ARG_POINTER_REGNUM | |
1473 | || ! fixed_regs [REGNO (dest)]) | |
1474 | #endif | |
1475 | && REGNO (dest) != STACK_POINTER_REGNUM) | |
230d793d RS |
1476 | { |
1477 | if (*pi3dest_killed) | |
1478 | return 0; | |
1479 | ||
1480 | *pi3dest_killed = dest; | |
1481 | } | |
1482 | } | |
1483 | ||
1484 | else if (GET_CODE (x) == PARALLEL) | |
1485 | { | |
1486 | int i; | |
1487 | ||
1488 | for (i = 0; i < XVECLEN (x, 0); i++) | |
1489 | if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, | |
1490 | i1_not_in_src, pi3dest_killed)) | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | return 1; | |
1495 | } | |
1496 | \f | |
14a774a9 RK |
1497 | /* Return 1 if X is an arithmetic expression that contains a multiplication |
1498 | and division. We don't count multiplications by powers of two here. */ | |
1499 | ||
1500 | static int | |
79a490a9 | 1501 | contains_muldiv (rtx x) |
14a774a9 RK |
1502 | { |
1503 | switch (GET_CODE (x)) | |
1504 | { | |
1505 | case MOD: case DIV: case UMOD: case UDIV: | |
1506 | return 1; | |
1507 | ||
1508 | case MULT: | |
1509 | return ! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1510 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); | |
1511 | default: | |
ec8e098d PB |
1512 | if (BINARY_P (x)) |
1513 | return contains_muldiv (XEXP (x, 0)) | |
14a774a9 RK |
1514 | || contains_muldiv (XEXP (x, 1)); |
1515 | ||
ec8e098d PB |
1516 | if (UNARY_P (x)) |
1517 | return contains_muldiv (XEXP (x, 0)); | |
14a774a9 | 1518 | |
ec8e098d | 1519 | return 0; |
14a774a9 RK |
1520 | } |
1521 | } | |
1522 | \f | |
c3410241 BS |
1523 | /* Determine whether INSN can be used in a combination. Return nonzero if |
1524 | not. This is used in try_combine to detect early some cases where we | |
1525 | can't perform combinations. */ | |
1526 | ||
1527 | static int | |
79a490a9 | 1528 | cant_combine_insn_p (rtx insn) |
c3410241 BS |
1529 | { |
1530 | rtx set; | |
1531 | rtx src, dest; | |
23190837 | 1532 | |
c3410241 BS |
1533 | /* If this isn't really an insn, we can't do anything. |
1534 | This can occur when flow deletes an insn that it has merged into an | |
1535 | auto-increment address. */ | |
1536 | if (! INSN_P (insn)) | |
1537 | return 1; | |
1538 | ||
7f0ea82e R |
1539 | /* Never combine loads and stores involving hard regs that are likely |
1540 | to be spilled. The register allocator can usually handle such | |
cafe096b | 1541 | reg-reg moves by tying. If we allow the combiner to make |
535a42b1 | 1542 | substitutions of likely-spilled regs, reload might die. |
c3410241 BS |
1543 | As an exception, we allow combinations involving fixed regs; these are |
1544 | not available to the register allocator so there's no risk involved. */ | |
1545 | ||
1546 | set = single_set (insn); | |
1547 | if (! set) | |
1548 | return 0; | |
1549 | src = SET_SRC (set); | |
1550 | dest = SET_DEST (set); | |
ad334b51 JH |
1551 | if (GET_CODE (src) == SUBREG) |
1552 | src = SUBREG_REG (src); | |
1553 | if (GET_CODE (dest) == SUBREG) | |
1554 | dest = SUBREG_REG (dest); | |
53895717 BS |
1555 | if (REG_P (src) && REG_P (dest) |
1556 | && ((REGNO (src) < FIRST_PSEUDO_REGISTER | |
7f0ea82e R |
1557 | && ! fixed_regs[REGNO (src)] |
1558 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src)))) | |
53895717 | 1559 | || (REGNO (dest) < FIRST_PSEUDO_REGISTER |
7f0ea82e R |
1560 | && ! fixed_regs[REGNO (dest)] |
1561 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest)))))) | |
c3410241 | 1562 | return 1; |
53895717 | 1563 | |
c3410241 BS |
1564 | return 0; |
1565 | } | |
1566 | ||
45002e59 R |
1567 | struct likely_spilled_retval_info |
1568 | { | |
1569 | unsigned regno, nregs; | |
1570 | unsigned mask; | |
1571 | }; | |
1572 | ||
1573 | /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask | |
1574 | hard registers that are known to be written to / clobbered in full. */ | |
1575 | static void | |
1576 | likely_spilled_retval_1 (rtx x, rtx set, void *data) | |
1577 | { | |
1578 | struct likely_spilled_retval_info *info = data; | |
1579 | unsigned regno, nregs; | |
1580 | unsigned new_mask; | |
1581 | ||
1582 | if (!REG_P (XEXP (set, 0))) | |
1583 | return; | |
1584 | regno = REGNO (x); | |
1585 | if (regno >= info->regno + info->nregs) | |
1586 | return; | |
1587 | nregs = hard_regno_nregs[regno][GET_MODE (x)]; | |
1588 | if (regno + nregs <= info->regno) | |
1589 | return; | |
1590 | new_mask = (2U << (nregs - 1)) - 1; | |
1591 | if (regno < info->regno) | |
1592 | new_mask >>= info->regno - regno; | |
1593 | else | |
1594 | new_mask <<= regno - info->regno; | |
1595 | info->mask &= new_mask; | |
1596 | } | |
1597 | ||
1598 | /* Return nonzero iff part of the return value is live during INSN, and | |
1599 | it is likely spilled. This can happen when more than one insn is needed | |
1600 | to copy the return value, e.g. when we consider to combine into the | |
1601 | second copy insn for a complex value. */ | |
1602 | ||
1603 | static int | |
1604 | likely_spilled_retval_p (rtx insn) | |
1605 | { | |
1606 | rtx use = BB_END (this_basic_block); | |
1607 | rtx reg, p; | |
1608 | unsigned regno, nregs; | |
1609 | /* We assume here that no machine mode needs more than | |
1610 | 32 hard registers when the value overlaps with a register | |
1611 | for which FUNCTION_VALUE_REGNO_P is true. */ | |
1612 | unsigned mask; | |
1613 | struct likely_spilled_retval_info info; | |
1614 | ||
1615 | if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use) | |
1616 | return 0; | |
1617 | reg = XEXP (PATTERN (use), 0); | |
1618 | if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg))) | |
1619 | return 0; | |
1620 | regno = REGNO (reg); | |
1621 | nregs = hard_regno_nregs[regno][GET_MODE (reg)]; | |
1622 | if (nregs == 1) | |
1623 | return 0; | |
1624 | mask = (2U << (nregs - 1)) - 1; | |
1625 | ||
1626 | /* Disregard parts of the return value that are set later. */ | |
1627 | info.regno = regno; | |
1628 | info.nregs = nregs; | |
1629 | info.mask = mask; | |
1630 | for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p)) | |
1631 | note_stores (PATTERN (insn), likely_spilled_retval_1, &info); | |
1632 | mask = info.mask; | |
1633 | ||
1634 | /* Check if any of the (probably) live return value registers is | |
1635 | likely spilled. */ | |
1636 | nregs --; | |
1637 | do | |
1638 | { | |
1639 | if ((mask & 1 << nregs) | |
1640 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs))) | |
1641 | return 1; | |
1642 | } while (nregs--); | |
1643 | return 0; | |
1644 | } | |
1645 | ||
8c03ca00 EB |
1646 | /* Adjust INSN after we made a change to its destination. |
1647 | ||
1648 | Changing the destination can invalidate notes that say something about | |
1649 | the results of the insn and a LOG_LINK pointing to the insn. */ | |
1650 | ||
1651 | static void | |
1652 | adjust_for_new_dest (rtx insn) | |
1653 | { | |
1654 | rtx *loc; | |
1655 | ||
1656 | /* For notes, be conservative and simply remove them. */ | |
1657 | loc = ®_NOTES (insn); | |
1658 | while (*loc) | |
1659 | { | |
1660 | enum reg_note kind = REG_NOTE_KIND (*loc); | |
1661 | if (kind == REG_EQUAL || kind == REG_EQUIV) | |
1662 | *loc = XEXP (*loc, 1); | |
1663 | else | |
1664 | loc = &XEXP (*loc, 1); | |
1665 | } | |
1666 | ||
1667 | /* The new insn will have a destination that was previously the destination | |
1668 | of an insn just above it. Call distribute_links to make a LOG_LINK from | |
1669 | the next use of that destination. */ | |
1670 | distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX)); | |
1671 | } | |
1672 | ||
4164b2fb PB |
1673 | /* Return TRUE if combine can reuse reg X in mode MODE. |
1674 | ADDED_SETS is nonzero if the original set is still required. */ | |
1675 | static bool | |
1676 | can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode) | |
1677 | { | |
1678 | unsigned int regno; | |
1679 | ||
1680 | if (!REG_P(x)) | |
1681 | return false; | |
1682 | ||
1683 | regno = REGNO (x); | |
1684 | /* Allow hard registers if the new mode is legal, and occupies no more | |
1685 | registers than the old mode. */ | |
1686 | if (regno < FIRST_PSEUDO_REGISTER) | |
1687 | return (HARD_REGNO_MODE_OK (regno, mode) | |
1688 | && (hard_regno_nregs[regno][GET_MODE (x)] | |
1689 | >= hard_regno_nregs[regno][mode])); | |
1690 | ||
1691 | /* Or a pseudo that is only used once. */ | |
1692 | return (REG_N_SETS (regno) == 1 && !added_sets | |
1693 | && !REG_USERVAR_P (x)); | |
1694 | } | |
1695 | ||
230d793d RS |
1696 | /* Try to combine the insns I1 and I2 into I3. |
1697 | Here I1 and I2 appear earlier than I3. | |
1698 | I1 can be zero; then we combine just I2 into I3. | |
663522cb | 1699 | |
04956a1a | 1700 | If we are combining three insns and the resulting insn is not recognized, |
230d793d RS |
1701 | try splitting it into two insns. If that happens, I2 and I3 are retained |
1702 | and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 | |
1703 | are pseudo-deleted. | |
1704 | ||
663522cb | 1705 | Return 0 if the combination does not work. Then nothing is changed. |
abe6e52f | 1706 | If we did the combination, return the insn at which combine should |
663522cb KH |
1707 | resume scanning. |
1708 | ||
da7d8304 | 1709 | Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a |
44a76fc8 | 1710 | new direct jump instruction. */ |
230d793d RS |
1711 | |
1712 | static rtx | |
79a490a9 | 1713 | try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p) |
230d793d | 1714 | { |
02359929 | 1715 | /* New patterns for I3 and I2, respectively. */ |
230d793d | 1716 | rtx newpat, newi2pat = 0; |
9b12dc4f | 1717 | rtvec newpat_vec_with_clobbers = 0; |
cddd8b72 | 1718 | int substed_i2 = 0, substed_i1 = 0; |
230d793d RS |
1719 | /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ |
1720 | int added_sets_1, added_sets_2; | |
1721 | /* Total number of SETs to put into I3. */ | |
1722 | int total_sets; | |
a1105617 | 1723 | /* Nonzero if I2's body now appears in I3. */ |
230d793d RS |
1724 | int i2_is_used; |
1725 | /* INSN_CODEs for new I3, new I2, and user of condition code. */ | |
6a651371 | 1726 | int insn_code_number, i2_code_number = 0, other_code_number = 0; |
230d793d RS |
1727 | /* Contains I3 if the destination of I3 is used in its source, which means |
1728 | that the old life of I3 is being killed. If that usage is placed into | |
1729 | I2 and not in I3, a REG_DEAD note must be made. */ | |
1730 | rtx i3dest_killed = 0; | |
1731 | /* SET_DEST and SET_SRC of I2 and I1. */ | |
1732 | rtx i2dest, i2src, i1dest = 0, i1src = 0; | |
1733 | /* PATTERN (I2), or a copy of it in certain cases. */ | |
1734 | rtx i2pat; | |
1735 | /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ | |
c4e861e8 | 1736 | int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; |
4bbae09f | 1737 | int i2dest_killed = 0, i1dest_killed = 0; |
230d793d RS |
1738 | int i1_feeds_i3 = 0; |
1739 | /* Notes that must be added to REG_NOTES in I3 and I2. */ | |
1740 | rtx new_i3_notes, new_i2_notes; | |
176c9e6b JW |
1741 | /* Notes that we substituted I3 into I2 instead of the normal case. */ |
1742 | int i3_subst_into_i2 = 0; | |
df7d75de RK |
1743 | /* Notes that I1, I2 or I3 is a MULT operation. */ |
1744 | int have_mult = 0; | |
9e42ab3e | 1745 | int swap_i2i3 = 0; |
230d793d RS |
1746 | |
1747 | int maxreg; | |
1748 | rtx temp; | |
b3694847 | 1749 | rtx link; |
230d793d RS |
1750 | int i; |
1751 | ||
c3410241 BS |
1752 | /* Exit early if one of the insns involved can't be used for |
1753 | combinations. */ | |
1754 | if (cant_combine_insn_p (i3) | |
1755 | || cant_combine_insn_p (i2) | |
1756 | || (i1 && cant_combine_insn_p (i1)) | |
45002e59 | 1757 | || likely_spilled_retval_p (i3) |
c3410241 BS |
1758 | /* We also can't do anything if I3 has a |
1759 | REG_LIBCALL note since we don't want to disrupt the contiguity of a | |
1760 | libcall. */ | |
ec35104c JL |
1761 | #if 0 |
1762 | /* ??? This gives worse code, and appears to be unnecessary, since no | |
1763 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ | |
1764 | || find_reg_note (i3, REG_LIBCALL, NULL_RTX) | |
1765 | #endif | |
663522cb | 1766 | ) |
230d793d RS |
1767 | return 0; |
1768 | ||
1769 | combine_attempts++; | |
230d793d RS |
1770 | undobuf.other_insn = 0; |
1771 | ||
6e25d159 RK |
1772 | /* Reset the hard register usage information. */ |
1773 | CLEAR_HARD_REG_SET (newpat_used_regs); | |
1774 | ||
230d793d RS |
1775 | /* If I1 and I2 both feed I3, they can be in any order. To simplify the |
1776 | code below, set I1 to be the earlier of the two insns. */ | |
1777 | if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) | |
1778 | temp = i1, i1 = i2, i2 = temp; | |
1779 | ||
abe6e52f | 1780 | added_links_insn = 0; |
137e889e | 1781 | |
230d793d | 1782 | /* First check for one important special-case that the code below will |
c7be4f66 | 1783 | not handle. Namely, the case where I1 is zero, I2 is a PARALLEL |
230d793d RS |
1784 | and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, |
1785 | we may be able to replace that destination with the destination of I3. | |
1786 | This occurs in the common code where we compute both a quotient and | |
1787 | remainder into a structure, in which case we want to do the computation | |
1788 | directly into the structure to avoid register-register copies. | |
1789 | ||
c7be4f66 RK |
1790 | Note that this case handles both multiple sets in I2 and also |
1791 | cases where I2 has a number of CLOBBER or PARALLELs. | |
1792 | ||
230d793d RS |
1793 | We make very conservative checks below and only try to handle the |
1794 | most common cases of this. For example, we only handle the case | |
1795 | where I2 and I3 are adjacent to avoid making difficult register | |
1796 | usage tests. */ | |
1797 | ||
4b4bf941 | 1798 | if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET |
f8cfc6aa | 1799 | && REG_P (SET_SRC (PATTERN (i3))) |
230d793d | 1800 | && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER |
230d793d RS |
1801 | && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) |
1802 | && GET_CODE (PATTERN (i2)) == PARALLEL | |
1803 | && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
5089e22e RS |
1804 | /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code |
1805 | below would need to check what is inside (and reg_overlap_mentioned_p | |
1806 | doesn't support those codes anyway). Don't allow those destinations; | |
1807 | the resulting insn isn't likely to be recognized anyway. */ | |
1808 | && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
1809 | && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
230d793d RS |
1810 | && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), |
1811 | SET_DEST (PATTERN (i3))) | |
1812 | && next_real_insn (i2) == i3) | |
5089e22e RS |
1813 | { |
1814 | rtx p2 = PATTERN (i2); | |
1815 | ||
1816 | /* Make sure that the destination of I3, | |
1817 | which we are going to substitute into one output of I2, | |
1818 | is not used within another output of I2. We must avoid making this: | |
1819 | (parallel [(set (mem (reg 69)) ...) | |
1820 | (set (reg 69) ...)]) | |
1821 | which is not well-defined as to order of actions. | |
1822 | (Besides, reload can't handle output reloads for this.) | |
1823 | ||
1824 | The problem can also happen if the dest of I3 is a memory ref, | |
1825 | if another dest in I2 is an indirect memory ref. */ | |
1826 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
7ca919b7 RK |
1827 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1828 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
5089e22e RS |
1829 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), |
1830 | SET_DEST (XVECEXP (p2, 0, i)))) | |
1831 | break; | |
230d793d | 1832 | |
5089e22e RS |
1833 | if (i == XVECLEN (p2, 0)) |
1834 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
481c7efa FS |
1835 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1836 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
1837 | && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) | |
5089e22e RS |
1838 | { |
1839 | combine_merges++; | |
230d793d | 1840 | |
5089e22e RS |
1841 | subst_insn = i3; |
1842 | subst_low_cuid = INSN_CUID (i2); | |
230d793d | 1843 | |
c4e861e8 | 1844 | added_sets_2 = added_sets_1 = 0; |
5089e22e | 1845 | i2dest = SET_SRC (PATTERN (i3)); |
4bbae09f | 1846 | i2dest_killed = dead_or_set_p (i2, i2dest); |
230d793d | 1847 | |
5089e22e RS |
1848 | /* Replace the dest in I2 with our dest and make the resulting |
1849 | insn the new pattern for I3. Then skip to where we | |
1850 | validate the pattern. Everything was set up above. */ | |
663522cb | 1851 | SUBST (SET_DEST (XVECEXP (p2, 0, i)), |
5089e22e RS |
1852 | SET_DEST (PATTERN (i3))); |
1853 | ||
1854 | newpat = p2; | |
176c9e6b | 1855 | i3_subst_into_i2 = 1; |
5089e22e RS |
1856 | goto validate_replacement; |
1857 | } | |
1858 | } | |
230d793d | 1859 | |
667c1c2c RK |
1860 | /* If I2 is setting a double-word pseudo to a constant and I3 is setting |
1861 | one of those words to another constant, merge them by making a new | |
1862 | constant. */ | |
1863 | if (i1 == 0 | |
1864 | && (temp = single_set (i2)) != 0 | |
1865 | && (GET_CODE (SET_SRC (temp)) == CONST_INT | |
1866 | || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) | |
f8cfc6aa | 1867 | && REG_P (SET_DEST (temp)) |
667c1c2c RK |
1868 | && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT |
1869 | && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD | |
1870 | && GET_CODE (PATTERN (i3)) == SET | |
1871 | && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG | |
1872 | && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp) | |
1873 | && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT | |
1874 | && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD | |
1875 | && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT) | |
1876 | { | |
1877 | HOST_WIDE_INT lo, hi; | |
1878 | ||
1879 | if (GET_CODE (SET_SRC (temp)) == CONST_INT) | |
1880 | lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0; | |
1881 | else | |
1882 | { | |
1883 | lo = CONST_DOUBLE_LOW (SET_SRC (temp)); | |
1884 | hi = CONST_DOUBLE_HIGH (SET_SRC (temp)); | |
1885 | } | |
1886 | ||
1887 | if (subreg_lowpart_p (SET_DEST (PATTERN (i3)))) | |
48b4d901 AO |
1888 | { |
1889 | /* We don't handle the case of the target word being wider | |
1890 | than a host wide int. */ | |
341c100f | 1891 | gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD); |
48b4d901 | 1892 | |
42a6ff51 | 1893 | lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1); |
73a39fc4 | 1894 | lo |= (INTVAL (SET_SRC (PATTERN (i3))) |
2ef1a7f9 | 1895 | & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); |
48b4d901 AO |
1896 | } |
1897 | else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
667c1c2c | 1898 | hi = INTVAL (SET_SRC (PATTERN (i3))); |
48b4d901 AO |
1899 | else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD) |
1900 | { | |
1901 | int sign = -(int) ((unsigned HOST_WIDE_INT) lo | |
1902 | >> (HOST_BITS_PER_WIDE_INT - 1)); | |
1903 | ||
42a6ff51 AO |
1904 | lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD |
1905 | (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); | |
1906 | lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD | |
1907 | (INTVAL (SET_SRC (PATTERN (i3))))); | |
48b4d901 AO |
1908 | if (hi == sign) |
1909 | hi = lo < 0 ? -1 : 0; | |
1910 | } | |
1911 | else | |
1912 | /* We don't handle the case of the higher word not fitting | |
1913 | entirely in either hi or lo. */ | |
341c100f | 1914 | gcc_unreachable (); |
667c1c2c RK |
1915 | |
1916 | combine_merges++; | |
1917 | subst_insn = i3; | |
1918 | subst_low_cuid = INSN_CUID (i2); | |
1919 | added_sets_2 = added_sets_1 = 0; | |
1920 | i2dest = SET_DEST (temp); | |
4bbae09f | 1921 | i2dest_killed = dead_or_set_p (i2, i2dest); |
667c1c2c RK |
1922 | |
1923 | SUBST (SET_SRC (temp), | |
1924 | immed_double_const (lo, hi, GET_MODE (SET_DEST (temp)))); | |
1925 | ||
1926 | newpat = PATTERN (i2); | |
667c1c2c RK |
1927 | goto validate_replacement; |
1928 | } | |
1929 | ||
230d793d RS |
1930 | #ifndef HAVE_cc0 |
1931 | /* If we have no I1 and I2 looks like: | |
1932 | (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
1933 | (set Y OP)]) | |
1934 | make up a dummy I1 that is | |
1935 | (set Y OP) | |
1936 | and change I2 to be | |
1937 | (set (reg:CC X) (compare:CC Y (const_int 0))) | |
1938 | ||
1939 | (We can ignore any trailing CLOBBERs.) | |
1940 | ||
1941 | This undoes a previous combination and allows us to match a branch-and- | |
1942 | decrement insn. */ | |
1943 | ||
1944 | if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
1945 | && XVECLEN (PATTERN (i2), 0) >= 2 | |
1946 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
1947 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
1948 | == MODE_CC) | |
1949 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
1950 | && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
1951 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
f8cfc6aa | 1952 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) |
230d793d RS |
1953 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), |
1954 | SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
1955 | { | |
663522cb | 1956 | for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) |
230d793d RS |
1957 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) |
1958 | break; | |
1959 | ||
1960 | if (i == 1) | |
1961 | { | |
1962 | /* We make I1 with the same INSN_UID as I2. This gives it | |
1963 | the same INSN_CUID for value tracking. Our fake I1 will | |
1964 | never appear in the insn stream so giving it the same INSN_UID | |
1965 | as I2 will not cause a problem. */ | |
1966 | ||
4977bab6 | 1967 | i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, |
0435312e | 1968 | BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2), |
4977bab6 ZW |
1969 | XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, |
1970 | NULL_RTX); | |
230d793d RS |
1971 | |
1972 | SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
1973 | SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
1974 | SET_DEST (PATTERN (i1))); | |
1975 | } | |
1976 | } | |
1977 | #endif | |
1978 | ||
1979 | /* Verify that I2 and I1 are valid for combining. */ | |
5f4f0e22 CH |
1980 | if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) |
1981 | || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) | |
230d793d RS |
1982 | { |
1983 | undo_all (); | |
1984 | return 0; | |
1985 | } | |
1986 | ||
1987 | /* Record whether I2DEST is used in I2SRC and similarly for the other | |
1988 | cases. Knowing this will help in register status updating below. */ | |
1989 | i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
1990 | i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
1991 | i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
4bbae09f ILT |
1992 | i2dest_killed = dead_or_set_p (i2, i2dest); |
1993 | i1dest_killed = i1 && dead_or_set_p (i1, i1dest); | |
230d793d | 1994 | |
916f14f1 | 1995 | /* See if I1 directly feeds into I3. It does if I1DEST is not used |
230d793d RS |
1996 | in I2SRC. */ |
1997 | i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); | |
1998 | ||
1999 | /* Ensure that I3's pattern can be the destination of combines. */ | |
2000 | if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, | |
2001 | i1 && i2dest_in_i1src && i1_feeds_i3, | |
2002 | &i3dest_killed)) | |
2003 | { | |
2004 | undo_all (); | |
2005 | return 0; | |
2006 | } | |
2007 | ||
df7d75de RK |
2008 | /* See if any of the insns is a MULT operation. Unless one is, we will |
2009 | reject a combination that is, since it must be slower. Be conservative | |
2010 | here. */ | |
2011 | if (GET_CODE (i2src) == MULT | |
2012 | || (i1 != 0 && GET_CODE (i1src) == MULT) | |
2013 | || (GET_CODE (PATTERN (i3)) == SET | |
2014 | && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) | |
2015 | have_mult = 1; | |
2016 | ||
230d793d RS |
2017 | /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. |
2018 | We used to do this EXCEPT in one case: I3 has a post-inc in an | |
2019 | output operand. However, that exception can give rise to insns like | |
23190837 | 2020 | mov r3,(r3)+ |
230d793d | 2021 | which is a famous insn on the PDP-11 where the value of r3 used as the |
5089e22e | 2022 | source was model-dependent. Avoid this sort of thing. */ |
230d793d RS |
2023 | |
2024 | #if 0 | |
2025 | if (!(GET_CODE (PATTERN (i3)) == SET | |
f8cfc6aa | 2026 | && REG_P (SET_SRC (PATTERN (i3))) |
3c0cb5de | 2027 | && MEM_P (SET_DEST (PATTERN (i3))) |
230d793d RS |
2028 | && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC |
2029 | || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
2030 | /* It's not the exception. */ | |
2031 | #endif | |
2032 | #ifdef AUTO_INC_DEC | |
2033 | for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
2034 | if (REG_NOTE_KIND (link) == REG_INC | |
2035 | && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
2036 | || (i1 != 0 | |
2037 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
2038 | { | |
2039 | undo_all (); | |
2040 | return 0; | |
2041 | } | |
2042 | #endif | |
2043 | ||
2044 | /* See if the SETs in I1 or I2 need to be kept around in the merged | |
2045 | instruction: whenever the value set there is still needed past I3. | |
2046 | For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. | |
2047 | ||
2048 | For the SET in I1, we have two cases: If I1 and I2 independently | |
2049 | feed into I3, the set in I1 needs to be kept around if I1DEST dies | |
2050 | or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set | |
2051 | in I1 needs to be kept around unless I1DEST dies or is set in either | |
2052 | I2 or I3. We can distinguish these cases by seeing if I2SRC mentions | |
2053 | I1DEST. If so, we know I1 feeds into I2. */ | |
2054 | ||
2055 | added_sets_2 = ! dead_or_set_p (i3, i2dest); | |
2056 | ||
2057 | added_sets_1 | |
2058 | = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | |
2059 | : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | |
2060 | ||
2061 | /* If the set in I2 needs to be kept around, we must make a copy of | |
2062 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
5089e22e | 2063 | PATTERN (I2), we are only substituting for the original I1DEST, not into |
230d793d RS |
2064 | an already-substituted copy. This also prevents making self-referential |
2065 | rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
2066 | I2DEST. */ | |
2067 | ||
2068 | i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL | |
38a448ca | 2069 | ? gen_rtx_SET (VOIDmode, i2dest, i2src) |
230d793d RS |
2070 | : PATTERN (i2)); |
2071 | ||
2072 | if (added_sets_2) | |
2073 | i2pat = copy_rtx (i2pat); | |
2074 | ||
2075 | combine_merges++; | |
2076 | ||
2077 | /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
2078 | ||
2079 | maxreg = max_reg_num (); | |
2080 | ||
2081 | subst_insn = i3; | |
230d793d | 2082 | |
230d793d RS |
2083 | #ifndef HAVE_cc0 |
2084 | /* Many machines that don't use CC0 have insns that can both perform an | |
2085 | arithmetic operation and set the condition code. These operations will | |
2086 | be represented as a PARALLEL with the first element of the vector | |
2087 | being a COMPARE of an arithmetic operation with the constant zero. | |
2088 | The second element of the vector will set some pseudo to the result | |
2089 | of the same arithmetic operation. If we simplify the COMPARE, we won't | |
2090 | match such a pattern and so will generate an extra insn. Here we test | |
2091 | for this case, where both the comparison and the operation result are | |
2092 | needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
2093 | I2SRC. Later we will make the PARALLEL that contains I2. */ | |
2094 | ||
2095 | if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
2096 | && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
2097 | && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx | |
2098 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) | |
2099 | { | |
94134f42 | 2100 | #ifdef SELECT_CC_MODE |
230d793d RS |
2101 | rtx *cc_use; |
2102 | enum machine_mode compare_mode; | |
081f5e7e | 2103 | #endif |
230d793d RS |
2104 | |
2105 | newpat = PATTERN (i3); | |
2106 | SUBST (XEXP (SET_SRC (newpat), 0), i2src); | |
2107 | ||
2108 | i2_is_used = 1; | |
2109 | ||
94134f42 | 2110 | #ifdef SELECT_CC_MODE |
230d793d RS |
2111 | /* See if a COMPARE with the operand we substituted in should be done |
2112 | with the mode that is currently being used. If not, do the same | |
2113 | processing we do in `subst' for a SET; namely, if the destination | |
2114 | is used only once, try to replace it with a register of the proper | |
2115 | mode and also replace the COMPARE. */ | |
2116 | if (undobuf.other_insn == 0 | |
2117 | && (cc_use = find_single_use (SET_DEST (newpat), i3, | |
2118 | &undobuf.other_insn)) | |
77fa0940 RK |
2119 | && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), |
2120 | i2src, const0_rtx)) | |
230d793d RS |
2121 | != GET_MODE (SET_DEST (newpat)))) |
2122 | { | |
4164b2fb PB |
2123 | if (can_change_dest_mode(SET_DEST (newpat), added_sets_2, |
2124 | compare_mode)) | |
230d793d | 2125 | { |
4164b2fb PB |
2126 | unsigned int regno = REGNO (SET_DEST (newpat)); |
2127 | rtx new_dest = gen_rtx_REG (compare_mode, regno); | |
2128 | ||
230d793d RS |
2129 | if (regno >= FIRST_PSEUDO_REGISTER) |
2130 | SUBST (regno_reg_rtx[regno], new_dest); | |
2131 | ||
2132 | SUBST (SET_DEST (newpat), new_dest); | |
2133 | SUBST (XEXP (*cc_use, 0), new_dest); | |
2134 | SUBST (SET_SRC (newpat), | |
f1c6ba8b | 2135 | gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); |
230d793d RS |
2136 | } |
2137 | else | |
2138 | undobuf.other_insn = 0; | |
2139 | } | |
663522cb | 2140 | #endif |
230d793d RS |
2141 | } |
2142 | else | |
2143 | #endif | |
2144 | { | |
7cf3d079 JM |
2145 | /* It is possible that the source of I2 or I1 may be performing |
2146 | an unneeded operation, such as a ZERO_EXTEND of something | |
2147 | that is known to have the high part zero. Handle that case | |
2148 | by letting subst look at the innermost one of them. | |
2149 | ||
2150 | Another way to do this would be to have a function that tries | |
2151 | to simplify a single insn instead of merging two or more | |
2152 | insns. We don't do this because of the potential of infinite | |
2153 | loops and because of the potential extra memory required. | |
2154 | However, doing it the way we are is a bit of a kludge and | |
2155 | doesn't catch all cases. | |
2156 | ||
2157 | But only do this if -fexpensive-optimizations since it slows | |
2158 | things down and doesn't usually win. | |
2159 | ||
2160 | This is not done in the COMPARE case above because the | |
2161 | unmodified I2PAT is used in the PARALLEL and so a pattern | |
2162 | with a modified I2SRC would not match. */ | |
2163 | ||
2164 | if (flag_expensive_optimizations) | |
2165 | { | |
2166 | /* Pass pc_rtx so no substitutions are done, just | |
2167 | simplifications. */ | |
2168 | if (i1) | |
2169 | { | |
2170 | subst_low_cuid = INSN_CUID (i1); | |
2171 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | |
2172 | } | |
2173 | else | |
2174 | { | |
2175 | subst_low_cuid = INSN_CUID (i2); | |
2176 | i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | |
2177 | } | |
2178 | } | |
2179 | ||
230d793d RS |
2180 | n_occurrences = 0; /* `subst' counts here */ |
2181 | ||
2182 | /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we | |
2183 | need to make a unique copy of I2SRC each time we substitute it | |
2184 | to avoid self-referential rtl. */ | |
2185 | ||
d0ab8cd3 | 2186 | subst_low_cuid = INSN_CUID (i2); |
230d793d RS |
2187 | newpat = subst (PATTERN (i3), i2dest, i2src, 0, |
2188 | ! i1_feeds_i3 && i1dest_in_i1src); | |
cddd8b72 | 2189 | substed_i2 = 1; |
230d793d RS |
2190 | |
2191 | /* Record whether i2's body now appears within i3's body. */ | |
2192 | i2_is_used = n_occurrences; | |
2193 | } | |
2194 | ||
2195 | /* If we already got a failure, don't try to do more. Otherwise, | |
2196 | try to substitute in I1 if we have it. */ | |
2197 | ||
2198 | if (i1 && GET_CODE (newpat) != CLOBBER) | |
2199 | { | |
2200 | /* Before we can do this substitution, we must redo the test done | |
2201 | above (see detailed comments there) that ensures that I1DEST | |
0f41302f | 2202 | isn't mentioned in any SETs in NEWPAT that are field assignments. */ |
230d793d | 2203 | |
5f4f0e22 | 2204 | if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, |
cf0d9408 | 2205 | 0, (rtx*) 0)) |
230d793d RS |
2206 | { |
2207 | undo_all (); | |
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | n_occurrences = 0; | |
d0ab8cd3 | 2212 | subst_low_cuid = INSN_CUID (i1); |
230d793d | 2213 | newpat = subst (newpat, i1dest, i1src, 0, 0); |
cddd8b72 | 2214 | substed_i1 = 1; |
230d793d RS |
2215 | } |
2216 | ||
916f14f1 RK |
2217 | /* Fail if an autoincrement side-effect has been duplicated. Be careful |
2218 | to count all the ways that I2SRC and I1SRC can be used. */ | |
5f4f0e22 | 2219 | if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 |
916f14f1 | 2220 | && i2_is_used + added_sets_2 > 1) |
5f4f0e22 | 2221 | || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 |
916f14f1 RK |
2222 | && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) |
2223 | > 1)) | |
535a42b1 | 2224 | /* Fail if we tried to make a new register. */ |
230d793d RS |
2225 | || max_reg_num () != maxreg |
2226 | /* Fail if we couldn't do something and have a CLOBBER. */ | |
df7d75de RK |
2227 | || GET_CODE (newpat) == CLOBBER |
2228 | /* Fail if this new pattern is a MULT and we didn't have one before | |
2229 | at the outer level. */ | |
2230 | || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT | |
2231 | && ! have_mult)) | |
230d793d RS |
2232 | { |
2233 | undo_all (); | |
2234 | return 0; | |
2235 | } | |
2236 | ||
2237 | /* If the actions of the earlier insns must be kept | |
2238 | in addition to substituting them into the latest one, | |
2239 | we must make a new PARALLEL for the latest insn | |
2240 | to hold additional the SETs. */ | |
2241 | ||
2242 | if (added_sets_1 || added_sets_2) | |
2243 | { | |
2244 | combine_extras++; | |
2245 | ||
2246 | if (GET_CODE (newpat) == PARALLEL) | |
2247 | { | |
2248 | rtvec old = XVEC (newpat, 0); | |
2249 | total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; | |
38a448ca | 2250 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
d38a30c9 KG |
2251 | memcpy (XVEC (newpat, 0)->elem, &old->elem[0], |
2252 | sizeof (old->elem[0]) * old->num_elem); | |
230d793d RS |
2253 | } |
2254 | else | |
2255 | { | |
2256 | rtx old = newpat; | |
2257 | total_sets = 1 + added_sets_1 + added_sets_2; | |
38a448ca | 2258 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
230d793d RS |
2259 | XVECEXP (newpat, 0, 0) = old; |
2260 | } | |
2261 | ||
cf0d9408 KH |
2262 | if (added_sets_1) |
2263 | XVECEXP (newpat, 0, --total_sets) | |
2264 | = (GET_CODE (PATTERN (i1)) == PARALLEL | |
2265 | ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); | |
2266 | ||
2267 | if (added_sets_2) | |
2268 | { | |
2269 | /* If there is no I1, use I2's body as is. We used to also not do | |
2270 | the subst call below if I2 was substituted into I3, | |
2271 | but that could lose a simplification. */ | |
2272 | if (i1 == 0) | |
2273 | XVECEXP (newpat, 0, --total_sets) = i2pat; | |
2274 | else | |
2275 | /* See comment where i2pat is assigned. */ | |
2276 | XVECEXP (newpat, 0, --total_sets) | |
2277 | = subst (i2pat, i1dest, i1src, 0, 0); | |
2278 | } | |
230d793d RS |
2279 | } |
2280 | ||
2281 | /* We come here when we are replacing a destination in I2 with the | |
2282 | destination of I3. */ | |
2283 | validate_replacement: | |
2284 | ||
6e25d159 RK |
2285 | /* Note which hard regs this insn has as inputs. */ |
2286 | mark_used_regs_combine (newpat); | |
2287 | ||
9b12dc4f R |
2288 | /* If recog_for_combine fails, it strips existing clobbers. If we'll |
2289 | consider splitting this pattern, we might need these clobbers. */ | |
2290 | if (i1 && GET_CODE (newpat) == PARALLEL | |
2291 | && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) | |
2292 | { | |
2293 | int len = XVECLEN (newpat, 0); | |
2294 | ||
2295 | newpat_vec_with_clobbers = rtvec_alloc (len); | |
2296 | for (i = 0; i < len; i++) | |
2297 | RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); | |
2298 | } | |
2299 | ||
230d793d | 2300 | /* Is the result of combination a valid instruction? */ |
8e2f6e35 | 2301 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2302 | |
2303 | /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
8051c2eb AM |
2304 | the second SET's destination is a register that is unused and isn't |
2305 | marked as an instruction that might trap in an EH region. In that case, | |
230d793d RS |
2306 | we just need the first SET. This can occur when simplifying a divmod |
2307 | insn. We *must* test for this case here because the code below that | |
2308 | splits two independent SETs doesn't handle this case correctly when it | |
da6fdad3 | 2309 | updates the register status. |
230d793d | 2310 | |
da6fdad3 AM |
2311 | It's pointless doing this if we originally had two sets, one from |
2312 | i3, and one from i2. Combining then splitting the parallel results | |
2313 | in the original i2 again plus an invalid insn (which we delete). | |
2314 | The net effect is only to move instructions around, which makes | |
2315 | debug info less accurate. | |
2316 | ||
2317 | Also check the case where the first SET's destination is unused. | |
2318 | That would not cause incorrect code, but does cause an unneeded | |
2319 | insn to remain. */ | |
2320 | ||
2321 | if (insn_code_number < 0 | |
2322 | && !(added_sets_2 && i1 == 0) | |
2323 | && GET_CODE (newpat) == PARALLEL | |
230d793d RS |
2324 | && XVECLEN (newpat, 0) == 2 |
2325 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2326 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
230d793d RS |
2327 | && asm_noperands (newpat) < 0) |
2328 | { | |
5c881655 KH |
2329 | rtx set0 = XVECEXP (newpat, 0, 0); |
2330 | rtx set1 = XVECEXP (newpat, 0, 1); | |
8051c2eb AM |
2331 | rtx note; |
2332 | ||
f8cfc6aa | 2333 | if (((REG_P (SET_DEST (set1)) |
8051c2eb AM |
2334 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) |
2335 | || (GET_CODE (SET_DEST (set1)) == SUBREG | |
2336 | && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) | |
2337 | && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2338 | || INTVAL (XEXP (note, 0)) <= 0) | |
2339 | && ! side_effects_p (SET_SRC (set1))) | |
2340 | { | |
2341 | newpat = set0; | |
2342 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2343 | } | |
2344 | ||
f8cfc6aa | 2345 | else if (((REG_P (SET_DEST (set0)) |
8051c2eb AM |
2346 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) |
2347 | || (GET_CODE (SET_DEST (set0)) == SUBREG | |
2348 | && find_reg_note (i3, REG_UNUSED, | |
2349 | SUBREG_REG (SET_DEST (set0))))) | |
2350 | && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2351 | || INTVAL (XEXP (note, 0)) <= 0) | |
2352 | && ! side_effects_p (SET_SRC (set0))) | |
2353 | { | |
2354 | newpat = set1; | |
2355 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2356 | ||
2357 | if (insn_code_number >= 0) | |
2358 | { | |
2359 | /* If we will be able to accept this, we have made a | |
2360 | change to the destination of I3. This requires us to | |
2361 | do a few adjustments. */ | |
2362 | ||
2363 | PATTERN (i3) = newpat; | |
2364 | adjust_for_new_dest (i3); | |
2365 | } | |
2366 | } | |
230d793d RS |
2367 | } |
2368 | ||
2369 | /* If we were combining three insns and the result is a simple SET | |
2370 | with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
663522cb | 2371 | insns. There are two ways to do this. It can be split using a |
916f14f1 RK |
2372 | machine-specific method (like when you have an addition of a large |
2373 | constant) or by combine in the function find_split_point. */ | |
2374 | ||
230d793d RS |
2375 | if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET |
2376 | && asm_noperands (newpat) < 0) | |
2377 | { | |
916f14f1 | 2378 | rtx m_split, *split; |
42495ca0 | 2379 | rtx ni2dest = i2dest; |
916f14f1 RK |
2380 | |
2381 | /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
42495ca0 RK |
2382 | use I2DEST as a scratch register will help. In the latter case, |
2383 | convert I2DEST to the mode of the source of NEWPAT if we can. */ | |
916f14f1 RK |
2384 | |
2385 | m_split = split_insns (newpat, i3); | |
a70c61d9 JW |
2386 | |
2387 | /* We can only use I2DEST as a scratch reg if it doesn't overlap any | |
2388 | inputs of NEWPAT. */ | |
2389 | ||
2390 | /* ??? If I2DEST is not safe, and I1DEST exists, then it would be | |
2391 | possible to try that as a scratch reg. This would require adding | |
2392 | more code to make it work though. */ | |
2393 | ||
2394 | if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) | |
42495ca0 | 2395 | { |
4164b2fb | 2396 | enum machine_mode new_mode = GET_MODE (SET_DEST (newpat)); |
42495ca0 RK |
2397 | /* If I2DEST is a hard register or the only use of a pseudo, |
2398 | we can change its mode. */ | |
4164b2fb PB |
2399 | if (new_mode != GET_MODE (i2dest) |
2400 | && new_mode != VOIDmode | |
2401 | && can_change_dest_mode (i2dest, added_sets_2, new_mode)) | |
38a448ca | 2402 | ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), |
c5c76735 JL |
2403 | REGNO (i2dest)); |
2404 | ||
2405 | m_split = split_insns (gen_rtx_PARALLEL | |
2406 | (VOIDmode, | |
2407 | gen_rtvec (2, newpat, | |
2408 | gen_rtx_CLOBBER (VOIDmode, | |
2409 | ni2dest))), | |
2410 | i3); | |
5dd3e650 R |
2411 | /* If the split with the mode-changed register didn't work, try |
2412 | the original register. */ | |
2413 | if (! m_split && ni2dest != i2dest) | |
c7ca5912 RK |
2414 | { |
2415 | ni2dest = i2dest; | |
2416 | m_split = split_insns (gen_rtx_PARALLEL | |
2417 | (VOIDmode, | |
2418 | gen_rtvec (2, newpat, | |
2419 | gen_rtx_CLOBBER (VOIDmode, | |
2420 | i2dest))), | |
2421 | i3); | |
2422 | } | |
42495ca0 | 2423 | } |
916f14f1 | 2424 | |
9b12dc4f R |
2425 | /* If recog_for_combine has discarded clobbers, try to use them |
2426 | again for the split. */ | |
2427 | if (m_split == 0 && newpat_vec_with_clobbers) | |
2428 | m_split | |
2429 | = split_insns (gen_rtx_PARALLEL (VOIDmode, | |
2430 | newpat_vec_with_clobbers), i3); | |
2431 | ||
2f937369 | 2432 | if (m_split && NEXT_INSN (m_split) == NULL_RTX) |
d340408c | 2433 | { |
2f937369 | 2434 | m_split = PATTERN (m_split); |
d340408c RH |
2435 | insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); |
2436 | if (insn_code_number >= 0) | |
2437 | newpat = m_split; | |
23190837 | 2438 | } |
2f937369 | 2439 | else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX |
d340408c | 2440 | && (next_real_insn (i2) == i3 |
2f937369 | 2441 | || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2)))) |
916f14f1 | 2442 | { |
1a26b032 | 2443 | rtx i2set, i3set; |
2f937369 DM |
2444 | rtx newi3pat = PATTERN (NEXT_INSN (m_split)); |
2445 | newi2pat = PATTERN (m_split); | |
916f14f1 | 2446 | |
2f937369 DM |
2447 | i3set = single_set (NEXT_INSN (m_split)); |
2448 | i2set = single_set (m_split); | |
1a26b032 | 2449 | |
42495ca0 RK |
2450 | /* In case we changed the mode of I2DEST, replace it in the |
2451 | pseudo-register table here. We can't do it above in case this | |
2452 | code doesn't get executed and we do a split the other way. */ | |
2453 | ||
2454 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2455 | SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); | |
2456 | ||
8e2f6e35 | 2457 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
1a26b032 RK |
2458 | |
2459 | /* If I2 or I3 has multiple SETs, we won't know how to track | |
9cc96794 RK |
2460 | register status, so don't use these insns. If I2's destination |
2461 | is used between I2 and I3, we also can't use these insns. */ | |
1a26b032 | 2462 | |
9cc96794 RK |
2463 | if (i2_code_number >= 0 && i2set && i3set |
2464 | && (next_real_insn (i2) == i3 | |
2465 | || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) | |
8e2f6e35 BS |
2466 | insn_code_number = recog_for_combine (&newi3pat, i3, |
2467 | &new_i3_notes); | |
d0ab8cd3 RK |
2468 | if (insn_code_number >= 0) |
2469 | newpat = newi3pat; | |
2470 | ||
c767f54b | 2471 | /* It is possible that both insns now set the destination of I3. |
22609cbf | 2472 | If so, we must show an extra use of it. */ |
c767f54b | 2473 | |
393de53f RK |
2474 | if (insn_code_number >= 0) |
2475 | { | |
2476 | rtx new_i3_dest = SET_DEST (i3set); | |
2477 | rtx new_i2_dest = SET_DEST (i2set); | |
2478 | ||
2479 | while (GET_CODE (new_i3_dest) == ZERO_EXTRACT | |
2480 | || GET_CODE (new_i3_dest) == STRICT_LOW_PART | |
2481 | || GET_CODE (new_i3_dest) == SUBREG) | |
2482 | new_i3_dest = XEXP (new_i3_dest, 0); | |
2483 | ||
d4096689 RK |
2484 | while (GET_CODE (new_i2_dest) == ZERO_EXTRACT |
2485 | || GET_CODE (new_i2_dest) == STRICT_LOW_PART | |
2486 | || GET_CODE (new_i2_dest) == SUBREG) | |
2487 | new_i2_dest = XEXP (new_i2_dest, 0); | |
2488 | ||
f8cfc6aa JQ |
2489 | if (REG_P (new_i3_dest) |
2490 | && REG_P (new_i2_dest) | |
393de53f | 2491 | && REGNO (new_i3_dest) == REGNO (new_i2_dest)) |
b1f21e0a | 2492 | REG_N_SETS (REGNO (new_i2_dest))++; |
393de53f | 2493 | } |
916f14f1 | 2494 | } |
230d793d RS |
2495 | |
2496 | /* If we can split it and use I2DEST, go ahead and see if that | |
2497 | helps things be recognized. Verify that none of the registers | |
2498 | are set between I2 and I3. */ | |
d0ab8cd3 | 2499 | if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 |
230d793d | 2500 | #ifdef HAVE_cc0 |
f8cfc6aa | 2501 | && REG_P (i2dest) |
230d793d RS |
2502 | #endif |
2503 | /* We need I2DEST in the proper mode. If it is a hard register | |
1ad93fbf BS |
2504 | or the only use of a pseudo, we can change its mode. |
2505 | Make sure we don't change a hard register to have a mode that | |
2506 | isn't valid for it, or change the number of registers. */ | |
230d793d RS |
2507 | && (GET_MODE (*split) == GET_MODE (i2dest) |
2508 | || GET_MODE (*split) == VOIDmode | |
4164b2fb PB |
2509 | || can_change_dest_mode (i2dest, added_sets_2, |
2510 | GET_MODE (*split))) | |
230d793d RS |
2511 | && (next_real_insn (i2) == i3 |
2512 | || ! use_crosses_set_p (*split, INSN_CUID (i2))) | |
2513 | /* We can't overwrite I2DEST if its value is still used by | |
2514 | NEWPAT. */ | |
2515 | && ! reg_referenced_p (i2dest, newpat)) | |
2516 | { | |
2517 | rtx newdest = i2dest; | |
df7d75de RK |
2518 | enum rtx_code split_code = GET_CODE (*split); |
2519 | enum machine_mode split_mode = GET_MODE (*split); | |
230d793d RS |
2520 | |
2521 | /* Get NEWDEST as a register in the proper mode. We have already | |
2522 | validated that we can do this. */ | |
df7d75de | 2523 | if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) |
230d793d | 2524 | { |
38a448ca | 2525 | newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); |
230d793d RS |
2526 | |
2527 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2528 | SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); | |
2529 | } | |
2530 | ||
2531 | /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
2532 | an ASHIFT. This can occur if it was inside a PLUS and hence | |
2533 | appeared to be a memory address. This is a kludge. */ | |
df7d75de | 2534 | if (split_code == MULT |
230d793d | 2535 | && GET_CODE (XEXP (*split, 1)) == CONST_INT |
1568d79b | 2536 | && INTVAL (XEXP (*split, 1)) > 0 |
230d793d | 2537 | && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) |
1dc8a823 | 2538 | { |
f1c6ba8b RK |
2539 | SUBST (*split, gen_rtx_ASHIFT (split_mode, |
2540 | XEXP (*split, 0), GEN_INT (i))); | |
1dc8a823 JW |
2541 | /* Update split_code because we may not have a multiply |
2542 | anymore. */ | |
2543 | split_code = GET_CODE (*split); | |
2544 | } | |
230d793d RS |
2545 | |
2546 | #ifdef INSN_SCHEDULING | |
2547 | /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
2548 | be written as a ZERO_EXTEND. */ | |
3c0cb5de | 2549 | if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) |
25c25947 R |
2550 | { |
2551 | #ifdef LOAD_EXTEND_OP | |
2552 | /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's | |
2553 | what it really is. */ | |
2554 | if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) | |
2555 | == SIGN_EXTEND) | |
2556 | SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, | |
2557 | SUBREG_REG (*split))); | |
2558 | else | |
2559 | #endif | |
2560 | SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, | |
2561 | SUBREG_REG (*split))); | |
2562 | } | |
230d793d RS |
2563 | #endif |
2564 | ||
f1c6ba8b | 2565 | newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); |
230d793d | 2566 | SUBST (*split, newdest); |
8e2f6e35 | 2567 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
df7d75de | 2568 | |
985f2d8f JJ |
2569 | /* recog_for_combine might have added CLOBBERs to newi2pat. |
2570 | Make sure NEWPAT does not depend on the clobbered regs. */ | |
2571 | if (GET_CODE (newi2pat) == PARALLEL) | |
2572 | for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) | |
2573 | if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) | |
2574 | { | |
2575 | rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); | |
2576 | if (reg_overlap_mentioned_p (reg, newpat)) | |
2577 | { | |
2578 | undo_all (); | |
2579 | return 0; | |
2580 | } | |
2581 | } | |
2582 | ||
df7d75de RK |
2583 | /* If the split point was a MULT and we didn't have one before, |
2584 | don't use one now. */ | |
2585 | if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) | |
8e2f6e35 | 2586 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2587 | } |
2588 | } | |
2589 | ||
2590 | /* Check for a case where we loaded from memory in a narrow mode and | |
2591 | then sign extended it, but we need both registers. In that case, | |
2592 | we have a PARALLEL with both loads from the same memory location. | |
2593 | We can split this into a load from memory followed by a register-register | |
2594 | copy. This saves at least one insn, more if register allocation can | |
f0343c74 RK |
2595 | eliminate the copy. |
2596 | ||
a9b2f059 JW |
2597 | We cannot do this if the destination of the first assignment is a |
2598 | condition code register or cc0. We eliminate this case by making sure | |
2599 | the SET_DEST and SET_SRC have the same mode. | |
2600 | ||
f0343c74 RK |
2601 | We cannot do this if the destination of the second assignment is |
2602 | a register that we have already assumed is zero-extended. Similarly | |
2603 | for a SUBREG of such a register. */ | |
230d793d RS |
2604 | |
2605 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2606 | && GET_CODE (newpat) == PARALLEL | |
2607 | && XVECLEN (newpat, 0) == 2 | |
2608 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2609 | && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
a9b2f059 JW |
2610 | && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) |
2611 | == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) | |
230d793d RS |
2612 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET |
2613 | && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2614 | XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
2615 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2616 | INSN_CUID (i2)) | |
2617 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2618 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
f0343c74 | 2619 | && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), |
f8cfc6aa | 2620 | (REG_P (temp) |
5eaad481 | 2621 | && reg_stat[REGNO (temp)].nonzero_bits != 0 |
f0343c74 RK |
2622 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD |
2623 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
5eaad481 | 2624 | && (reg_stat[REGNO (temp)].nonzero_bits |
f0343c74 RK |
2625 | != GET_MODE_MASK (word_mode)))) |
2626 | && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG | |
2627 | && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), | |
f8cfc6aa | 2628 | (REG_P (temp) |
5eaad481 | 2629 | && reg_stat[REGNO (temp)].nonzero_bits != 0 |
f0343c74 RK |
2630 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD |
2631 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
5eaad481 | 2632 | && (reg_stat[REGNO (temp)].nonzero_bits |
f0343c74 | 2633 | != GET_MODE_MASK (word_mode))))) |
230d793d RS |
2634 | && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), |
2635 | SET_SRC (XVECEXP (newpat, 0, 1))) | |
2636 | && ! find_reg_note (i3, REG_UNUSED, | |
2637 | SET_DEST (XVECEXP (newpat, 0, 0)))) | |
2638 | { | |
472fbdd1 RK |
2639 | rtx ni2dest; |
2640 | ||
230d793d | 2641 | newi2pat = XVECEXP (newpat, 0, 0); |
472fbdd1 | 2642 | ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); |
230d793d RS |
2643 | newpat = XVECEXP (newpat, 0, 1); |
2644 | SUBST (SET_SRC (newpat), | |
4de249d9 | 2645 | gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); |
8e2f6e35 | 2646 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2647 | |
230d793d | 2648 | if (i2_code_number >= 0) |
8e2f6e35 | 2649 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
5089e22e RS |
2650 | |
2651 | if (insn_code_number >= 0) | |
9e42ab3e | 2652 | swap_i2i3 = 1; |
230d793d | 2653 | } |
663522cb | 2654 | |
230d793d RS |
2655 | /* Similarly, check for a case where we have a PARALLEL of two independent |
2656 | SETs but we started with three insns. In this case, we can do the sets | |
2657 | as two separate insns. This case occurs when some SET allows two | |
2658 | other insns to combine, but the destination of that SET is still live. */ | |
2659 | ||
2660 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2661 | && GET_CODE (newpat) == PARALLEL | |
2662 | && XVECLEN (newpat, 0) == 2 | |
2663 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2664 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
2665 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
2666 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2667 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2668 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
2669 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2670 | INSN_CUID (i2)) | |
2671 | /* Don't pass sets with (USE (MEM ...)) dests to the following. */ | |
2672 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE | |
2673 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE | |
2674 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
2675 | XVECEXP (newpat, 0, 0)) | |
2676 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
14a774a9 RK |
2677 | XVECEXP (newpat, 0, 1)) |
2678 | && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) | |
2679 | && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) | |
230d793d | 2680 | { |
e9a25f70 JL |
2681 | /* Normally, it doesn't matter which of the two is done first, |
2682 | but it does if one references cc0. In that case, it has to | |
2683 | be first. */ | |
2684 | #ifdef HAVE_cc0 | |
2685 | if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) | |
2686 | { | |
2687 | newi2pat = XVECEXP (newpat, 0, 0); | |
2688 | newpat = XVECEXP (newpat, 0, 1); | |
2689 | } | |
2690 | else | |
2691 | #endif | |
2692 | { | |
2693 | newi2pat = XVECEXP (newpat, 0, 1); | |
2694 | newpat = XVECEXP (newpat, 0, 0); | |
2695 | } | |
230d793d | 2696 | |
8e2f6e35 | 2697 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2698 | |
230d793d | 2699 | if (i2_code_number >= 0) |
8e2f6e35 | 2700 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2701 | } |
2702 | ||
2703 | /* If it still isn't recognized, fail and change things back the way they | |
2704 | were. */ | |
2705 | if ((insn_code_number < 0 | |
2706 | /* Is the result a reasonable ASM_OPERANDS? */ | |
2707 | && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
2708 | { | |
2709 | undo_all (); | |
2710 | return 0; | |
2711 | } | |
2712 | ||
2713 | /* If we had to change another insn, make sure it is valid also. */ | |
2714 | if (undobuf.other_insn) | |
2715 | { | |
230d793d RS |
2716 | rtx other_pat = PATTERN (undobuf.other_insn); |
2717 | rtx new_other_notes; | |
2718 | rtx note, next; | |
2719 | ||
6e25d159 RK |
2720 | CLEAR_HARD_REG_SET (newpat_used_regs); |
2721 | ||
8e2f6e35 BS |
2722 | other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, |
2723 | &new_other_notes); | |
230d793d RS |
2724 | |
2725 | if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
2726 | { | |
2727 | undo_all (); | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | PATTERN (undobuf.other_insn) = other_pat; | |
2732 | ||
2733 | /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they | |
2734 | are still valid. Then add any non-duplicate notes added by | |
2735 | recog_for_combine. */ | |
2736 | for (note = REG_NOTES (undobuf.other_insn); note; note = next) | |
2737 | { | |
2738 | next = XEXP (note, 1); | |
2739 | ||
2740 | if (REG_NOTE_KIND (note) == REG_UNUSED | |
2741 | && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) | |
1a26b032 | 2742 | { |
f8cfc6aa | 2743 | if (REG_P (XEXP (note, 0))) |
b1f21e0a | 2744 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
1a26b032 RK |
2745 | |
2746 | remove_note (undobuf.other_insn, note); | |
2747 | } | |
230d793d RS |
2748 | } |
2749 | ||
1a26b032 | 2750 | for (note = new_other_notes; note; note = XEXP (note, 1)) |
f8cfc6aa | 2751 | if (REG_P (XEXP (note, 0))) |
b1f21e0a | 2752 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 2753 | |
230d793d | 2754 | distribute_notes (new_other_notes, undobuf.other_insn, |
4bbae09f | 2755 | undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX); |
230d793d | 2756 | } |
5ef17dd2 | 2757 | #ifdef HAVE_cc0 |
1f52178b | 2758 | /* If I2 is the CC0 setter and I3 is the CC0 user then check whether |
ec5c56db | 2759 | they are adjacent to each other or not. */ |
5ef17dd2 CC |
2760 | { |
2761 | rtx p = prev_nonnote_insn (i3); | |
4b4bf941 | 2762 | if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat |
663522cb | 2763 | && sets_cc0_p (newi2pat)) |
5ef17dd2 | 2764 | { |
663522cb KH |
2765 | undo_all (); |
2766 | return 0; | |
5ef17dd2 | 2767 | } |
663522cb KH |
2768 | } |
2769 | #endif | |
230d793d | 2770 | |
6fd21094 | 2771 | /* Only allow this combination if insn_rtx_costs reports that the |
64b8935d RS |
2772 | replacement instructions are cheaper than the originals. */ |
2773 | if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat)) | |
2774 | { | |
2775 | undo_all (); | |
2776 | return 0; | |
2777 | } | |
2778 | ||
663522cb | 2779 | /* We now know that we can do this combination. Merge the insns and |
230d793d RS |
2780 | update the status of registers and LOG_LINKS. */ |
2781 | ||
9e42ab3e RZ |
2782 | if (swap_i2i3) |
2783 | { | |
2784 | rtx insn; | |
2785 | rtx link; | |
2786 | rtx ni2dest; | |
2787 | ||
2788 | /* I3 now uses what used to be its destination and which is now | |
2789 | I2's destination. This requires us to do a few adjustments. */ | |
2790 | PATTERN (i3) = newpat; | |
2791 | adjust_for_new_dest (i3); | |
2792 | ||
2793 | /* We need a LOG_LINK from I3 to I2. But we used to have one, | |
2794 | so we still will. | |
2795 | ||
2796 | However, some later insn might be using I2's dest and have | |
2797 | a LOG_LINK pointing at I3. We must remove this link. | |
2798 | The simplest way to remove the link is to point it at I1, | |
2799 | which we know will be a NOTE. */ | |
2800 | ||
0b21d1dc UW |
2801 | /* newi2pat is usually a SET here; however, recog_for_combine might |
2802 | have added some clobbers. */ | |
2803 | if (GET_CODE (newi2pat) == PARALLEL) | |
2804 | ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); | |
2805 | else | |
2806 | ni2dest = SET_DEST (newi2pat); | |
2807 | ||
9e42ab3e RZ |
2808 | for (insn = NEXT_INSN (i3); |
2809 | insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR | |
2810 | || insn != BB_HEAD (this_basic_block->next_bb)); | |
2811 | insn = NEXT_INSN (insn)) | |
2812 | { | |
2813 | if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) | |
2814 | { | |
2815 | for (link = LOG_LINKS (insn); link; | |
2816 | link = XEXP (link, 1)) | |
2817 | if (XEXP (link, 0) == i3) | |
2818 | XEXP (link, 0) = i1; | |
2819 | ||
2820 | break; | |
2821 | } | |
2822 | } | |
2823 | } | |
2824 | ||
230d793d RS |
2825 | { |
2826 | rtx i3notes, i2notes, i1notes = 0; | |
2827 | rtx i3links, i2links, i1links = 0; | |
2828 | rtx midnotes = 0; | |
770ae6cc | 2829 | unsigned int regno; |
4bbae09f ILT |
2830 | /* Compute which registers we expect to eliminate. newi2pat may be setting |
2831 | either i3dest or i2dest, so we must check it. Also, i1dest may be the | |
2832 | same as i3dest, in which case newi2pat may be setting i1dest. */ | |
2833 | rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat)) | |
2834 | || i2dest_in_i2src || i2dest_in_i1src | |
2835 | || !i2dest_killed | |
2836 | ? 0 : i2dest); | |
2837 | rtx elim_i1 = (i1 == 0 || i1dest_in_i1src | |
2838 | || (newi2pat && reg_set_p (i1dest, newi2pat)) | |
2839 | || !i1dest_killed | |
2840 | ? 0 : i1dest); | |
230d793d RS |
2841 | |
2842 | /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
2843 | clear them. */ | |
2844 | i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
2845 | i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
2846 | if (i1) | |
2847 | i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
2848 | ||
2849 | /* Ensure that we do not have something that should not be shared but | |
2850 | occurs multiple times in the new insns. Check this by first | |
5089e22e | 2851 | resetting all the `used' flags and then copying anything is shared. */ |
230d793d RS |
2852 | |
2853 | reset_used_flags (i3notes); | |
2854 | reset_used_flags (i2notes); | |
2855 | reset_used_flags (i1notes); | |
2856 | reset_used_flags (newpat); | |
2857 | reset_used_flags (newi2pat); | |
2858 | if (undobuf.other_insn) | |
2859 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2860 | ||
2861 | i3notes = copy_rtx_if_shared (i3notes); | |
2862 | i2notes = copy_rtx_if_shared (i2notes); | |
2863 | i1notes = copy_rtx_if_shared (i1notes); | |
2864 | newpat = copy_rtx_if_shared (newpat); | |
2865 | newi2pat = copy_rtx_if_shared (newi2pat); | |
2866 | if (undobuf.other_insn) | |
2867 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2868 | ||
2869 | INSN_CODE (i3) = insn_code_number; | |
2870 | PATTERN (i3) = newpat; | |
cddd8b72 | 2871 | |
4b4bf941 | 2872 | if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) |
cddd8b72 AO |
2873 | { |
2874 | rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); | |
2875 | ||
2876 | reset_used_flags (call_usage); | |
2877 | call_usage = copy_rtx (call_usage); | |
2878 | ||
2879 | if (substed_i2) | |
2880 | replace_rtx (call_usage, i2dest, i2src); | |
2881 | ||
2882 | if (substed_i1) | |
2883 | replace_rtx (call_usage, i1dest, i1src); | |
2884 | ||
2885 | CALL_INSN_FUNCTION_USAGE (i3) = call_usage; | |
2886 | } | |
2887 | ||
230d793d RS |
2888 | if (undobuf.other_insn) |
2889 | INSN_CODE (undobuf.other_insn) = other_code_number; | |
2890 | ||
2891 | /* We had one special case above where I2 had more than one set and | |
2892 | we replaced a destination of one of those sets with the destination | |
2893 | of I3. In that case, we have to update LOG_LINKS of insns later | |
176c9e6b JW |
2894 | in this basic block. Note that this (expensive) case is rare. |
2895 | ||
2896 | Also, in this case, we must pretend that all REG_NOTEs for I2 | |
2897 | actually came from I3, so that REG_UNUSED notes from I2 will be | |
2898 | properly handled. */ | |
2899 | ||
c7be4f66 | 2900 | if (i3_subst_into_i2) |
176c9e6b | 2901 | { |
1786009e | 2902 | for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) |
95ac07b0 | 2903 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE |
f8cfc6aa | 2904 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) |
1786009e ZW |
2905 | && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest |
2906 | && ! find_reg_note (i2, REG_UNUSED, | |
2907 | SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
2908 | for (temp = NEXT_INSN (i2); | |
f6366fc7 | 2909 | temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
a813c111 | 2910 | || BB_HEAD (this_basic_block) != temp); |
1786009e ZW |
2911 | temp = NEXT_INSN (temp)) |
2912 | if (temp != i3 && INSN_P (temp)) | |
2913 | for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) | |
2914 | if (XEXP (link, 0) == i2) | |
2915 | XEXP (link, 0) = i3; | |
176c9e6b JW |
2916 | |
2917 | if (i3notes) | |
2918 | { | |
2919 | rtx link = i3notes; | |
2920 | while (XEXP (link, 1)) | |
2921 | link = XEXP (link, 1); | |
2922 | XEXP (link, 1) = i2notes; | |
2923 | } | |
2924 | else | |
2925 | i3notes = i2notes; | |
2926 | i2notes = 0; | |
2927 | } | |
230d793d RS |
2928 | |
2929 | LOG_LINKS (i3) = 0; | |
2930 | REG_NOTES (i3) = 0; | |
2931 | LOG_LINKS (i2) = 0; | |
2932 | REG_NOTES (i2) = 0; | |
2933 | ||
2934 | if (newi2pat) | |
2935 | { | |
2936 | INSN_CODE (i2) = i2_code_number; | |
2937 | PATTERN (i2) = newi2pat; | |
2938 | } | |
2939 | else | |
6773e15f | 2940 | SET_INSN_DELETED (i2); |
230d793d RS |
2941 | |
2942 | if (i1) | |
2943 | { | |
2944 | LOG_LINKS (i1) = 0; | |
2945 | REG_NOTES (i1) = 0; | |
6773e15f | 2946 | SET_INSN_DELETED (i1); |
230d793d RS |
2947 | } |
2948 | ||
2949 | /* Get death notes for everything that is now used in either I3 or | |
663522cb | 2950 | I2 and used to die in a previous insn. If we built two new |
6eb12cef RK |
2951 | patterns, move from I1 to I2 then I2 to I3 so that we get the |
2952 | proper movement on registers that I2 modifies. */ | |
230d793d | 2953 | |
230d793d | 2954 | if (newi2pat) |
6eb12cef RK |
2955 | { |
2956 | move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); | |
2957 | move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); | |
2958 | } | |
2959 | else | |
2960 | move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), | |
2961 | i3, &midnotes); | |
230d793d RS |
2962 | |
2963 | /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
2964 | if (i3notes) | |
4bbae09f ILT |
2965 | distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX, |
2966 | elim_i2, elim_i1); | |
230d793d | 2967 | if (i2notes) |
4bbae09f ILT |
2968 | distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX, |
2969 | elim_i2, elim_i1); | |
230d793d | 2970 | if (i1notes) |
4bbae09f ILT |
2971 | distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX, |
2972 | elim_i2, elim_i1); | |
230d793d | 2973 | if (midnotes) |
4bbae09f ILT |
2974 | distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
2975 | elim_i2, elim_i1); | |
230d793d RS |
2976 | |
2977 | /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
2978 | know these are REG_UNUSED and want them to go to the desired insn, | |
663522cb | 2979 | so we always pass it as i3. We have not counted the notes in |
1a26b032 RK |
2980 | reg_n_deaths yet, so we need to do so now. */ |
2981 | ||
230d793d | 2982 | if (newi2pat && new_i2_notes) |
1a26b032 RK |
2983 | { |
2984 | for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) | |
f8cfc6aa | 2985 | if (REG_P (XEXP (temp, 0))) |
b1f21e0a | 2986 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2987 | |
4bbae09f | 2988 | distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
1a26b032 RK |
2989 | } |
2990 | ||
230d793d | 2991 | if (new_i3_notes) |
1a26b032 RK |
2992 | { |
2993 | for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) | |
f8cfc6aa | 2994 | if (REG_P (XEXP (temp, 0))) |
b1f21e0a | 2995 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2996 | |
4bbae09f | 2997 | distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX); |
1a26b032 | 2998 | } |
230d793d RS |
2999 | |
3000 | /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
e9a25f70 JL |
3001 | put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets |
3002 | I3DEST, the death must be somewhere before I2, not I3. If we passed I3 | |
3003 | in that case, it might delete I2. Similarly for I2 and I1. | |
1a26b032 RK |
3004 | Show an additional death due to the REG_DEAD note we make here. If |
3005 | we discard it in distribute_notes, we will decrement it again. */ | |
d0ab8cd3 | 3006 | |
230d793d | 3007 | if (i3dest_killed) |
1a26b032 | 3008 | { |
f8cfc6aa | 3009 | if (REG_P (i3dest_killed)) |
b1f21e0a | 3010 | REG_N_DEATHS (REGNO (i3dest_killed))++; |
1a26b032 | 3011 | |
e9a25f70 | 3012 | if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) |
38a448ca RH |
3013 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
3014 | NULL_RTX), | |
4bbae09f | 3015 | NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1); |
e9a25f70 | 3016 | else |
38a448ca RH |
3017 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
3018 | NULL_RTX), | |
4bbae09f ILT |
3019 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
3020 | elim_i2, elim_i1); | |
1a26b032 | 3021 | } |
58c8c593 | 3022 | |
230d793d | 3023 | if (i2dest_in_i2src) |
58c8c593 | 3024 | { |
f8cfc6aa | 3025 | if (REG_P (i2dest)) |
b1f21e0a | 3026 | REG_N_DEATHS (REGNO (i2dest))++; |
1a26b032 | 3027 | |
58c8c593 | 3028 | if (newi2pat && reg_set_p (i2dest, newi2pat)) |
38a448ca | 3029 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
4bbae09f | 3030 | NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
58c8c593 | 3031 | else |
38a448ca | 3032 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
4bbae09f ILT |
3033 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
3034 | NULL_RTX, NULL_RTX); | |
58c8c593 RK |
3035 | } |
3036 | ||
230d793d | 3037 | if (i1dest_in_i1src) |
58c8c593 | 3038 | { |
f8cfc6aa | 3039 | if (REG_P (i1dest)) |
b1f21e0a | 3040 | REG_N_DEATHS (REGNO (i1dest))++; |
1a26b032 | 3041 | |
58c8c593 | 3042 | if (newi2pat && reg_set_p (i1dest, newi2pat)) |
38a448ca | 3043 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
4bbae09f | 3044 | NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX); |
58c8c593 | 3045 | else |
38a448ca | 3046 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
4bbae09f ILT |
3047 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX, |
3048 | NULL_RTX, NULL_RTX); | |
58c8c593 | 3049 | } |
230d793d RS |
3050 | |
3051 | distribute_links (i3links); | |
3052 | distribute_links (i2links); | |
3053 | distribute_links (i1links); | |
3054 | ||
f8cfc6aa | 3055 | if (REG_P (i2dest)) |
230d793d | 3056 | { |
d0ab8cd3 RK |
3057 | rtx link; |
3058 | rtx i2_insn = 0, i2_val = 0, set; | |
3059 | ||
3060 | /* The insn that used to set this register doesn't exist, and | |
3061 | this life of the register may not exist either. See if one of | |
663522cb | 3062 | I3's links points to an insn that sets I2DEST. If it does, |
d0ab8cd3 RK |
3063 | that is now the last known value for I2DEST. If we don't update |
3064 | this and I2 set the register to a value that depended on its old | |
230d793d RS |
3065 | contents, we will get confused. If this insn is used, thing |
3066 | will be set correctly in combine_instructions. */ | |
d0ab8cd3 RK |
3067 | |
3068 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
3069 | if ((set = single_set (XEXP (link, 0))) != 0 | |
3070 | && rtx_equal_p (i2dest, SET_DEST (set))) | |
3071 | i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); | |
3072 | ||
3073 | record_value_for_reg (i2dest, i2_insn, i2_val); | |
230d793d RS |
3074 | |
3075 | /* If the reg formerly set in I2 died only once and that was in I3, | |
3076 | zero its use count so it won't make `reload' do any work. */ | |
538fe8cd ILT |
3077 | if (! added_sets_2 |
3078 | && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) | |
3079 | && ! i2dest_in_i2src) | |
230d793d RS |
3080 | { |
3081 | regno = REGNO (i2dest); | |
b1f21e0a | 3082 | REG_N_SETS (regno)--; |
230d793d RS |
3083 | } |
3084 | } | |
3085 | ||
f8cfc6aa | 3086 | if (i1 && REG_P (i1dest)) |
230d793d | 3087 | { |
d0ab8cd3 RK |
3088 | rtx link; |
3089 | rtx i1_insn = 0, i1_val = 0, set; | |
3090 | ||
3091 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
3092 | if ((set = single_set (XEXP (link, 0))) != 0 | |
3093 | && rtx_equal_p (i1dest, SET_DEST (set))) | |
3094 | i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); | |
3095 | ||
3096 | record_value_for_reg (i1dest, i1_insn, i1_val); | |
3097 | ||
230d793d | 3098 | regno = REGNO (i1dest); |
5af91171 | 3099 | if (! added_sets_1 && ! i1dest_in_i1src) |
770ae6cc | 3100 | REG_N_SETS (regno)--; |
230d793d RS |
3101 | } |
3102 | ||
5eaad481 PB |
3103 | /* Update reg_stat[].nonzero_bits et al for any changes that may have |
3104 | been made to this insn. The order of | |
3105 | set_nonzero_bits_and_sign_copies() is important. Because newi2pat | |
3106 | can affect nonzero_bits of newpat */ | |
22609cbf | 3107 | if (newi2pat) |
84832317 | 3108 | note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); |
5fb7c247 | 3109 | note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); |
22609cbf | 3110 | |
44a76fc8 AG |
3111 | /* Set new_direct_jump_p if a new return or simple jump instruction |
3112 | has been created. | |
3113 | ||
663522cb | 3114 | If I3 is now an unconditional jump, ensure that it has a |
230d793d | 3115 | BARRIER following it since it may have initially been a |
381ee8af | 3116 | conditional jump. It may also be the last nonnote insn. */ |
663522cb | 3117 | |
f40f4c8e | 3118 | if (returnjump_p (i3) || any_uncondjump_p (i3)) |
44a76fc8 AG |
3119 | { |
3120 | *new_direct_jump_p = 1; | |
9143c6b7 | 3121 | mark_jump_label (PATTERN (i3), i3, 0); |
230d793d | 3122 | |
44a76fc8 | 3123 | if ((temp = next_nonnote_insn (i3)) == NULL_RTX |
4b4bf941 | 3124 | || !BARRIER_P (temp)) |
44a76fc8 AG |
3125 | emit_barrier_after (i3); |
3126 | } | |
f40f4c8e RS |
3127 | |
3128 | if (undobuf.other_insn != NULL_RTX | |
3129 | && (returnjump_p (undobuf.other_insn) | |
3130 | || any_uncondjump_p (undobuf.other_insn))) | |
3131 | { | |
3132 | *new_direct_jump_p = 1; | |
3133 | ||
3134 | if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX | |
4b4bf941 | 3135 | || !BARRIER_P (temp)) |
f40f4c8e RS |
3136 | emit_barrier_after (undobuf.other_insn); |
3137 | } | |
73a39fc4 | 3138 | |
592a6d1d JH |
3139 | /* An NOOP jump does not need barrier, but it does need cleaning up |
3140 | of CFG. */ | |
3141 | if (GET_CODE (newpat) == SET | |
3142 | && SET_SRC (newpat) == pc_rtx | |
3143 | && SET_DEST (newpat) == pc_rtx) | |
3144 | *new_direct_jump_p = 1; | |
230d793d RS |
3145 | } |
3146 | ||
3147 | combine_successes++; | |
e7749837 | 3148 | undo_commit (); |
230d793d | 3149 | |
abe6e52f RK |
3150 | if (added_links_insn |
3151 | && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) | |
3152 | && INSN_CUID (added_links_insn) < INSN_CUID (i3)) | |
3153 | return added_links_insn; | |
3154 | else | |
3155 | return newi2pat ? i2 : i3; | |
230d793d RS |
3156 | } |
3157 | \f | |
3158 | /* Undo all the modifications recorded in undobuf. */ | |
3159 | ||
3160 | static void | |
79a490a9 | 3161 | undo_all (void) |
230d793d | 3162 | { |
241cea85 RK |
3163 | struct undo *undo, *next; |
3164 | ||
3165 | for (undo = undobuf.undos; undo; undo = next) | |
7c046e4e | 3166 | { |
241cea85 RK |
3167 | next = undo->next; |
3168 | if (undo->is_int) | |
3169 | *undo->where.i = undo->old_contents.i; | |
7c046e4e | 3170 | else |
241cea85 RK |
3171 | *undo->where.r = undo->old_contents.r; |
3172 | ||
3173 | undo->next = undobuf.frees; | |
3174 | undobuf.frees = undo; | |
7c046e4e | 3175 | } |
230d793d | 3176 | |
f1c6ba8b | 3177 | undobuf.undos = 0; |
230d793d | 3178 | } |
e7749837 RH |
3179 | |
3180 | /* We've committed to accepting the changes we made. Move all | |
3181 | of the undos to the free list. */ | |
3182 | ||
3183 | static void | |
79a490a9 | 3184 | undo_commit (void) |
e7749837 RH |
3185 | { |
3186 | struct undo *undo, *next; | |
3187 | ||
3188 | for (undo = undobuf.undos; undo; undo = next) | |
3189 | { | |
3190 | next = undo->next; | |
3191 | undo->next = undobuf.frees; | |
3192 | undobuf.frees = undo; | |
3193 | } | |
f1c6ba8b | 3194 | undobuf.undos = 0; |
e7749837 RH |
3195 | } |
3196 | ||
230d793d RS |
3197 | \f |
3198 | /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
d0ab8cd3 RK |
3199 | where we have an arithmetic expression and return that point. LOC will |
3200 | be inside INSN. | |
230d793d RS |
3201 | |
3202 | try_combine will call this function to see if an insn can be split into | |
3203 | two insns. */ | |
3204 | ||
3205 | static rtx * | |
79a490a9 | 3206 | find_split_point (rtx *loc, rtx insn) |
230d793d RS |
3207 | { |
3208 | rtx x = *loc; | |
3209 | enum rtx_code code = GET_CODE (x); | |
3210 | rtx *split; | |
770ae6cc RK |
3211 | unsigned HOST_WIDE_INT len = 0; |
3212 | HOST_WIDE_INT pos = 0; | |
3213 | int unsignedp = 0; | |
6a651371 | 3214 | rtx inner = NULL_RTX; |
230d793d RS |
3215 | |
3216 | /* First special-case some codes. */ | |
3217 | switch (code) | |
3218 | { | |
3219 | case SUBREG: | |
3220 | #ifdef INSN_SCHEDULING | |
3221 | /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
3222 | point. */ | |
3c0cb5de | 3223 | if (MEM_P (SUBREG_REG (x))) |
230d793d RS |
3224 | return loc; |
3225 | #endif | |
d0ab8cd3 | 3226 | return find_split_point (&SUBREG_REG (x), insn); |
230d793d | 3227 | |
230d793d | 3228 | case MEM: |
916f14f1 | 3229 | #ifdef HAVE_lo_sum |
230d793d RS |
3230 | /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it |
3231 | using LO_SUM and HIGH. */ | |
3232 | if (GET_CODE (XEXP (x, 0)) == CONST | |
3233 | || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
3234 | { | |
3235 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
3236 | gen_rtx_LO_SUM (Pmode, |
3237 | gen_rtx_HIGH (Pmode, XEXP (x, 0)), | |
3238 | XEXP (x, 0))); | |
230d793d RS |
3239 | return &XEXP (XEXP (x, 0), 0); |
3240 | } | |
230d793d RS |
3241 | #endif |
3242 | ||
916f14f1 RK |
3243 | /* If we have a PLUS whose second operand is a constant and the |
3244 | address is not valid, perhaps will can split it up using | |
3245 | the machine-specific way to split large constants. We use | |
ddd5a7c1 | 3246 | the first pseudo-reg (one of the virtual regs) as a placeholder; |
916f14f1 RK |
3247 | it will not remain in the result. */ |
3248 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
3249 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3250 | && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
3251 | { | |
3252 | rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
38a448ca | 3253 | rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), |
916f14f1 RK |
3254 | subst_insn); |
3255 | ||
3256 | /* This should have produced two insns, each of which sets our | |
3257 | placeholder. If the source of the second is a valid address, | |
3258 | we can make put both sources together and make a split point | |
3259 | in the middle. */ | |
3260 | ||
2f937369 DM |
3261 | if (seq |
3262 | && NEXT_INSN (seq) != NULL_RTX | |
3263 | && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX | |
4b4bf941 | 3264 | && NONJUMP_INSN_P (seq) |
2f937369 DM |
3265 | && GET_CODE (PATTERN (seq)) == SET |
3266 | && SET_DEST (PATTERN (seq)) == reg | |
916f14f1 | 3267 | && ! reg_mentioned_p (reg, |
2f937369 | 3268 | SET_SRC (PATTERN (seq))) |
4b4bf941 | 3269 | && NONJUMP_INSN_P (NEXT_INSN (seq)) |
2f937369 DM |
3270 | && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET |
3271 | && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg | |
916f14f1 | 3272 | && memory_address_p (GET_MODE (x), |
2f937369 | 3273 | SET_SRC (PATTERN (NEXT_INSN (seq))))) |
916f14f1 | 3274 | { |
2f937369 DM |
3275 | rtx src1 = SET_SRC (PATTERN (seq)); |
3276 | rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); | |
916f14f1 RK |
3277 | |
3278 | /* Replace the placeholder in SRC2 with SRC1. If we can | |
3279 | find where in SRC2 it was placed, that can become our | |
3280 | split point and we can replace this address with SRC2. | |
3281 | Just try two obvious places. */ | |
3282 | ||
3283 | src2 = replace_rtx (src2, reg, src1); | |
3284 | split = 0; | |
3285 | if (XEXP (src2, 0) == src1) | |
3286 | split = &XEXP (src2, 0); | |
3287 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
3288 | && XEXP (XEXP (src2, 0), 0) == src1) | |
3289 | split = &XEXP (XEXP (src2, 0), 0); | |
3290 | ||
3291 | if (split) | |
3292 | { | |
3293 | SUBST (XEXP (x, 0), src2); | |
3294 | return split; | |
3295 | } | |
3296 | } | |
663522cb | 3297 | |
1a26b032 RK |
3298 | /* If that didn't work, perhaps the first operand is complex and |
3299 | needs to be computed separately, so make a split point there. | |
3300 | This will occur on machines that just support REG + CONST | |
3301 | and have a constant moved through some previous computation. */ | |
3302 | ||
ec8e098d | 3303 | else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) |
1a26b032 | 3304 | && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG |
ec8e098d | 3305 | && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) |
1a26b032 | 3306 | return &XEXP (XEXP (x, 0), 0); |
916f14f1 RK |
3307 | } |
3308 | break; | |
3309 | ||
230d793d RS |
3310 | case SET: |
3311 | #ifdef HAVE_cc0 | |
3312 | /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
3313 | ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
3314 | we need to put the operand into a register. So split at that | |
3315 | point. */ | |
3316 | ||
3317 | if (SET_DEST (x) == cc0_rtx | |
3318 | && GET_CODE (SET_SRC (x)) != COMPARE | |
3319 | && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
ec8e098d | 3320 | && !OBJECT_P (SET_SRC (x)) |
230d793d | 3321 | && ! (GET_CODE (SET_SRC (x)) == SUBREG |
ec8e098d | 3322 | && OBJECT_P (SUBREG_REG (SET_SRC (x))))) |
230d793d RS |
3323 | return &SET_SRC (x); |
3324 | #endif | |
3325 | ||
3326 | /* See if we can split SET_SRC as it stands. */ | |
d0ab8cd3 | 3327 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3328 | if (split && split != &SET_SRC (x)) |
3329 | return split; | |
3330 | ||
041d7180 JL |
3331 | /* See if we can split SET_DEST as it stands. */ |
3332 | split = find_split_point (&SET_DEST (x), insn); | |
3333 | if (split && split != &SET_DEST (x)) | |
3334 | return split; | |
3335 | ||
230d793d RS |
3336 | /* See if this is a bitfield assignment with everything constant. If |
3337 | so, this is an IOR of an AND, so split it into that. */ | |
3338 | if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
3339 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) | |
5f4f0e22 | 3340 | <= HOST_BITS_PER_WIDE_INT) |
230d793d RS |
3341 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT |
3342 | && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT | |
3343 | && GET_CODE (SET_SRC (x)) == CONST_INT | |
3344 | && ((INTVAL (XEXP (SET_DEST (x), 1)) | |
cf0d9408 | 3345 | + INTVAL (XEXP (SET_DEST (x), 2))) |
230d793d RS |
3346 | <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) |
3347 | && ! side_effects_p (XEXP (SET_DEST (x), 0))) | |
3348 | { | |
770ae6cc RK |
3349 | HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); |
3350 | unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); | |
3351 | unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); | |
230d793d RS |
3352 | rtx dest = XEXP (SET_DEST (x), 0); |
3353 | enum machine_mode mode = GET_MODE (dest); | |
5f4f0e22 | 3354 | unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; |
230d793d | 3355 | |
f76b9db2 ILT |
3356 | if (BITS_BIG_ENDIAN) |
3357 | pos = GET_MODE_BITSIZE (mode) - len - pos; | |
230d793d | 3358 | |
770ae6cc | 3359 | if (src == mask) |
230d793d | 3360 | SUBST (SET_SRC (x), |
bcb34aa3 | 3361 | simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos))); |
230d793d | 3362 | else |
bcb34aa3 PB |
3363 | { |
3364 | rtx negmask = gen_int_mode (~(mask << pos), mode); | |
3365 | SUBST (SET_SRC (x), | |
3366 | simplify_gen_binary (IOR, mode, | |
3367 | simplify_gen_binary (AND, mode, | |
3368 | dest, negmask), | |
3369 | GEN_INT (src << pos))); | |
3370 | } | |
230d793d RS |
3371 | |
3372 | SUBST (SET_DEST (x), dest); | |
3373 | ||
d0ab8cd3 | 3374 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3375 | if (split && split != &SET_SRC (x)) |
3376 | return split; | |
3377 | } | |
3378 | ||
3379 | /* Otherwise, see if this is an operation that we can split into two. | |
3380 | If so, try to split that. */ | |
3381 | code = GET_CODE (SET_SRC (x)); | |
3382 | ||
3383 | switch (code) | |
3384 | { | |
d0ab8cd3 RK |
3385 | case AND: |
3386 | /* If we are AND'ing with a large constant that is only a single | |
3387 | bit and the result is only being used in a context where we | |
da7d8304 | 3388 | need to know if it is zero or nonzero, replace it with a bit |
d0ab8cd3 RK |
3389 | extraction. This will avoid the large constant, which might |
3390 | have taken more than one insn to make. If the constant were | |
3391 | not a valid argument to the AND but took only one insn to make, | |
3392 | this is no worse, but if it took more than one insn, it will | |
3393 | be better. */ | |
3394 | ||
3395 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
f8cfc6aa | 3396 | && REG_P (XEXP (SET_SRC (x), 0)) |
d0ab8cd3 | 3397 | && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 |
f8cfc6aa | 3398 | && REG_P (SET_DEST (x)) |
cf0d9408 | 3399 | && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 |
d0ab8cd3 RK |
3400 | && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) |
3401 | && XEXP (*split, 0) == SET_DEST (x) | |
3402 | && XEXP (*split, 1) == const0_rtx) | |
3403 | { | |
76184def DE |
3404 | rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), |
3405 | XEXP (SET_SRC (x), 0), | |
3406 | pos, NULL_RTX, 1, 1, 0, 0); | |
3407 | if (extraction != 0) | |
3408 | { | |
3409 | SUBST (SET_SRC (x), extraction); | |
3410 | return find_split_point (loc, insn); | |
3411 | } | |
d0ab8cd3 RK |
3412 | } |
3413 | break; | |
3414 | ||
1a6ec070 | 3415 | case NE: |
938d968e | 3416 | /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X |
ec5c56db | 3417 | is known to be on, this can be converted into a NEG of a shift. */ |
1a6ec070 RK |
3418 | if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx |
3419 | && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) | |
4eb2cb10 | 3420 | && 1 <= (pos = exact_log2 |
1a6ec070 RK |
3421 | (nonzero_bits (XEXP (SET_SRC (x), 0), |
3422 | GET_MODE (XEXP (SET_SRC (x), 0)))))) | |
3423 | { | |
3424 | enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); | |
3425 | ||
3426 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3427 | gen_rtx_NEG (mode, |
3428 | gen_rtx_LSHIFTRT (mode, | |
3429 | XEXP (SET_SRC (x), 0), | |
3430 | GEN_INT (pos)))); | |
1a6ec070 RK |
3431 | |
3432 | split = find_split_point (&SET_SRC (x), insn); | |
3433 | if (split && split != &SET_SRC (x)) | |
3434 | return split; | |
3435 | } | |
3436 | break; | |
3437 | ||
230d793d RS |
3438 | case SIGN_EXTEND: |
3439 | inner = XEXP (SET_SRC (x), 0); | |
101c1a3d JL |
3440 | |
3441 | /* We can't optimize if either mode is a partial integer | |
3442 | mode as we don't know how many bits are significant | |
3443 | in those modes. */ | |
3444 | if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT | |
3445 | || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) | |
3446 | break; | |
3447 | ||
230d793d RS |
3448 | pos = 0; |
3449 | len = GET_MODE_BITSIZE (GET_MODE (inner)); | |
3450 | unsignedp = 0; | |
3451 | break; | |
3452 | ||
3453 | case SIGN_EXTRACT: | |
3454 | case ZERO_EXTRACT: | |
3455 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
3456 | && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) | |
3457 | { | |
3458 | inner = XEXP (SET_SRC (x), 0); | |
3459 | len = INTVAL (XEXP (SET_SRC (x), 1)); | |
3460 | pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
3461 | ||
f76b9db2 ILT |
3462 | if (BITS_BIG_ENDIAN) |
3463 | pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; | |
230d793d RS |
3464 | unsignedp = (code == ZERO_EXTRACT); |
3465 | } | |
3466 | break; | |
e9a25f70 JL |
3467 | |
3468 | default: | |
3469 | break; | |
230d793d RS |
3470 | } |
3471 | ||
3472 | if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) | |
3473 | { | |
3474 | enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
3475 | ||
d0ab8cd3 RK |
3476 | /* For unsigned, we have a choice of a shift followed by an |
3477 | AND or two shifts. Use two shifts for field sizes where the | |
3478 | constant might be too large. We assume here that we can | |
3479 | always at least get 8-bit constants in an AND insn, which is | |
3480 | true for every current RISC. */ | |
3481 | ||
3482 | if (unsignedp && len <= 8) | |
230d793d RS |
3483 | { |
3484 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3485 | gen_rtx_AND (mode, |
3486 | gen_rtx_LSHIFTRT | |
4de249d9 | 3487 | (mode, gen_lowpart (mode, inner), |
f1c6ba8b RK |
3488 | GEN_INT (pos)), |
3489 | GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); | |
230d793d | 3490 | |
d0ab8cd3 | 3491 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3492 | if (split && split != &SET_SRC (x)) |
3493 | return split; | |
3494 | } | |
3495 | else | |
3496 | { | |
3497 | SUBST (SET_SRC (x), | |
f1c6ba8b | 3498 | gen_rtx_fmt_ee |
d0ab8cd3 | 3499 | (unsignedp ? LSHIFTRT : ASHIFTRT, mode, |
f1c6ba8b | 3500 | gen_rtx_ASHIFT (mode, |
4de249d9 | 3501 | gen_lowpart (mode, inner), |
f1c6ba8b RK |
3502 | GEN_INT (GET_MODE_BITSIZE (mode) |
3503 | - len - pos)), | |
5f4f0e22 | 3504 | GEN_INT (GET_MODE_BITSIZE (mode) - len))); |
230d793d | 3505 | |
d0ab8cd3 | 3506 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3507 | if (split && split != &SET_SRC (x)) |
3508 | return split; | |
3509 | } | |
3510 | } | |
3511 | ||
3512 | /* See if this is a simple operation with a constant as the second | |
3513 | operand. It might be that this constant is out of range and hence | |
3514 | could be used as a split point. */ | |
ec8e098d | 3515 | if (BINARY_P (SET_SRC (x)) |
230d793d | 3516 | && CONSTANT_P (XEXP (SET_SRC (x), 1)) |
ec8e098d | 3517 | && (OBJECT_P (XEXP (SET_SRC (x), 0)) |
230d793d | 3518 | || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG |
ec8e098d | 3519 | && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) |
230d793d RS |
3520 | return &XEXP (SET_SRC (x), 1); |
3521 | ||
3522 | /* Finally, see if this is a simple operation with its first operand | |
3523 | not in a register. The operation might require this operand in a | |
3524 | register, so return it as a split point. We can always do this | |
3525 | because if the first operand were another operation, we would have | |
3526 | already found it as a split point. */ | |
ec8e098d | 3527 | if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) |
230d793d RS |
3528 | && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) |
3529 | return &XEXP (SET_SRC (x), 0); | |
3530 | ||
3531 | return 0; | |
3532 | ||
3533 | case AND: | |
3534 | case IOR: | |
3535 | /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
3536 | it is better to write this as (not (ior A B)) so we can split it. | |
3537 | Similarly for IOR. */ | |
3538 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
3539 | { | |
3540 | SUBST (*loc, | |
f1c6ba8b RK |
3541 | gen_rtx_NOT (GET_MODE (x), |
3542 | gen_rtx_fmt_ee (code == IOR ? AND : IOR, | |
3543 | GET_MODE (x), | |
3544 | XEXP (XEXP (x, 0), 0), | |
3545 | XEXP (XEXP (x, 1), 0)))); | |
d0ab8cd3 | 3546 | return find_split_point (loc, insn); |
230d793d RS |
3547 | } |
3548 | ||
3549 | /* Many RISC machines have a large set of logical insns. If the | |
3550 | second operand is a NOT, put it first so we will try to split the | |
3551 | other operand first. */ | |
3552 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
3553 | { | |
3554 | rtx tem = XEXP (x, 0); | |
3555 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3556 | SUBST (XEXP (x, 1), tem); | |
3557 | } | |
3558 | break; | |
e9a25f70 JL |
3559 | |
3560 | default: | |
3561 | break; | |
230d793d RS |
3562 | } |
3563 | ||
3564 | /* Otherwise, select our actions depending on our rtx class. */ | |
3565 | switch (GET_RTX_CLASS (code)) | |
3566 | { | |
ec8e098d PB |
3567 | case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ |
3568 | case RTX_TERNARY: | |
d0ab8cd3 | 3569 | split = find_split_point (&XEXP (x, 2), insn); |
230d793d RS |
3570 | if (split) |
3571 | return split; | |
0f41302f | 3572 | /* ... fall through ... */ |
ec8e098d PB |
3573 | case RTX_BIN_ARITH: |
3574 | case RTX_COMM_ARITH: | |
3575 | case RTX_COMPARE: | |
3576 | case RTX_COMM_COMPARE: | |
d0ab8cd3 | 3577 | split = find_split_point (&XEXP (x, 1), insn); |
230d793d RS |
3578 | if (split) |
3579 | return split; | |
0f41302f | 3580 | /* ... fall through ... */ |
ec8e098d | 3581 | case RTX_UNARY: |
230d793d RS |
3582 | /* Some machines have (and (shift ...) ...) insns. If X is not |
3583 | an AND, but XEXP (X, 0) is, use it as our split point. */ | |
3584 | if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
3585 | return &XEXP (x, 0); | |
3586 | ||
d0ab8cd3 | 3587 | split = find_split_point (&XEXP (x, 0), insn); |
230d793d RS |
3588 | if (split) |
3589 | return split; | |
3590 | return loc; | |
230d793d | 3591 | |
ec8e098d PB |
3592 | default: |
3593 | /* Otherwise, we don't have a split point. */ | |
3594 | return 0; | |
3595 | } | |
230d793d RS |
3596 | } |
3597 | \f | |
3598 | /* Throughout X, replace FROM with TO, and return the result. | |
3599 | The result is TO if X is FROM; | |
3600 | otherwise the result is X, but its contents may have been modified. | |
3601 | If they were modified, a record was made in undobuf so that | |
3602 | undo_all will (among other things) return X to its original state. | |
3603 | ||
3604 | If the number of changes necessary is too much to record to undo, | |
3605 | the excess changes are not made, so the result is invalid. | |
3606 | The changes already made can still be undone. | |
3607 | undobuf.num_undo is incremented for such changes, so by testing that | |
3608 | the caller can tell whether the result is valid. | |
3609 | ||
3610 | `n_occurrences' is incremented each time FROM is replaced. | |
663522cb | 3611 | |
da7d8304 | 3612 | IN_DEST is nonzero if we are processing the SET_DEST of a SET. |
230d793d | 3613 | |
da7d8304 KH |
3614 | UNIQUE_COPY is nonzero if each substitution must be unique. We do this |
3615 | by copying if `n_occurrences' is nonzero. */ | |
230d793d RS |
3616 | |
3617 | static rtx | |
79a490a9 | 3618 | subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) |
230d793d | 3619 | { |
b3694847 | 3620 | enum rtx_code code = GET_CODE (x); |
230d793d | 3621 | enum machine_mode op0_mode = VOIDmode; |
b3694847 SS |
3622 | const char *fmt; |
3623 | int len, i; | |
8079805d | 3624 | rtx new; |
230d793d RS |
3625 | |
3626 | /* Two expressions are equal if they are identical copies of a shared | |
3627 | RTX or if they are both registers with the same register number | |
3628 | and mode. */ | |
3629 | ||
3630 | #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
3631 | ((X) == (Y) \ | |
f8cfc6aa | 3632 | || (REG_P (X) && REG_P (Y) \ |
230d793d RS |
3633 | && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) |
3634 | ||
3635 | if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) | |
3636 | { | |
3637 | n_occurrences++; | |
3638 | return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
3639 | } | |
3640 | ||
3641 | /* If X and FROM are the same register but different modes, they will | |
663522cb | 3642 | not have been seen as equal above. However, flow.c will make a |
230d793d RS |
3643 | LOG_LINKS entry for that case. If we do nothing, we will try to |
3644 | rerecognize our original insn and, when it succeeds, we will | |
3645 | delete the feeding insn, which is incorrect. | |
3646 | ||
3647 | So force this insn not to match in this (rare) case. */ | |
f8cfc6aa | 3648 | if (! in_dest && code == REG && REG_P (from) |
230d793d | 3649 | && REGNO (x) == REGNO (from)) |
38a448ca | 3650 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
3651 | |
3652 | /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
3653 | of which may contain things that can be combined. */ | |
ec8e098d | 3654 | if (code != MEM && code != LO_SUM && OBJECT_P (x)) |
230d793d RS |
3655 | return x; |
3656 | ||
3657 | /* It is possible to have a subexpression appear twice in the insn. | |
3658 | Suppose that FROM is a register that appears within TO. | |
3659 | Then, after that subexpression has been scanned once by `subst', | |
3660 | the second time it is scanned, TO may be found. If we were | |
3661 | to scan TO here, we would find FROM within it and create a | |
3662 | self-referent rtl structure which is completely wrong. */ | |
3663 | if (COMBINE_RTX_EQUAL_P (x, to)) | |
3664 | return to; | |
3665 | ||
4f4b3679 RH |
3666 | /* Parallel asm_operands need special attention because all of the |
3667 | inputs are shared across the arms. Furthermore, unsharing the | |
3668 | rtl results in recognition failures. Failure to handle this case | |
3669 | specially can result in circular rtl. | |
3670 | ||
3671 | Solve this by doing a normal pass across the first entry of the | |
3672 | parallel, and only processing the SET_DESTs of the subsequent | |
3673 | entries. Ug. */ | |
3674 | ||
3675 | if (code == PARALLEL | |
3676 | && GET_CODE (XVECEXP (x, 0, 0)) == SET | |
3677 | && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | |
230d793d | 3678 | { |
4f4b3679 RH |
3679 | new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); |
3680 | ||
3681 | /* If this substitution failed, this whole thing fails. */ | |
3682 | if (GET_CODE (new) == CLOBBER | |
3683 | && XEXP (new, 0) == const0_rtx) | |
3684 | return new; | |
3685 | ||
3686 | SUBST (XVECEXP (x, 0, 0), new); | |
3687 | ||
3688 | for (i = XVECLEN (x, 0) - 1; i >= 1; i--) | |
230d793d | 3689 | { |
4f4b3679 | 3690 | rtx dest = SET_DEST (XVECEXP (x, 0, i)); |
663522cb | 3691 | |
f8cfc6aa | 3692 | if (!REG_P (dest) |
4f4b3679 RH |
3693 | && GET_CODE (dest) != CC0 |
3694 | && GET_CODE (dest) != PC) | |
230d793d | 3695 | { |
4f4b3679 | 3696 | new = subst (dest, from, to, 0, unique_copy); |
230d793d | 3697 | |
4f4b3679 RH |
3698 | /* If this substitution failed, this whole thing fails. */ |
3699 | if (GET_CODE (new) == CLOBBER | |
3700 | && XEXP (new, 0) == const0_rtx) | |
3701 | return new; | |
230d793d | 3702 | |
4f4b3679 | 3703 | SUBST (SET_DEST (XVECEXP (x, 0, i)), new); |
230d793d RS |
3704 | } |
3705 | } | |
4f4b3679 RH |
3706 | } |
3707 | else | |
3708 | { | |
3709 | len = GET_RTX_LENGTH (code); | |
3710 | fmt = GET_RTX_FORMAT (code); | |
3711 | ||
3712 | /* We don't need to process a SET_DEST that is a register, CC0, | |
3713 | or PC, so set up to skip this common case. All other cases | |
3714 | where we want to suppress replacing something inside a | |
3715 | SET_SRC are handled via the IN_DEST operand. */ | |
3716 | if (code == SET | |
f8cfc6aa | 3717 | && (REG_P (SET_DEST (x)) |
4f4b3679 RH |
3718 | || GET_CODE (SET_DEST (x)) == CC0 |
3719 | || GET_CODE (SET_DEST (x)) == PC)) | |
3720 | fmt = "ie"; | |
3721 | ||
3722 | /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a | |
3723 | constant. */ | |
3724 | if (fmt[0] == 'e') | |
3725 | op0_mode = GET_MODE (XEXP (x, 0)); | |
3726 | ||
3727 | for (i = 0; i < len; i++) | |
230d793d | 3728 | { |
4f4b3679 | 3729 | if (fmt[i] == 'E') |
230d793d | 3730 | { |
b3694847 | 3731 | int j; |
4f4b3679 RH |
3732 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3733 | { | |
3734 | if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
3735 | { | |
3736 | new = (unique_copy && n_occurrences | |
3737 | ? copy_rtx (to) : to); | |
3738 | n_occurrences++; | |
3739 | } | |
3740 | else | |
3741 | { | |
3742 | new = subst (XVECEXP (x, i, j), from, to, 0, | |
3743 | unique_copy); | |
3744 | ||
3745 | /* If this substitution failed, this whole thing | |
3746 | fails. */ | |
3747 | if (GET_CODE (new) == CLOBBER | |
3748 | && XEXP (new, 0) == const0_rtx) | |
3749 | return new; | |
3750 | } | |
3751 | ||
3752 | SUBST (XVECEXP (x, i, j), new); | |
3753 | } | |
3754 | } | |
3755 | else if (fmt[i] == 'e') | |
3756 | { | |
0a33d11e RH |
3757 | /* If this is a register being set, ignore it. */ |
3758 | new = XEXP (x, i); | |
3759 | if (in_dest | |
0a33d11e | 3760 | && i == 0 |
b78b8bd8 JJ |
3761 | && (((code == SUBREG || code == ZERO_EXTRACT) |
3762 | && REG_P (new)) | |
3763 | || code == STRICT_LOW_PART)) | |
0a33d11e RH |
3764 | ; |
3765 | ||
3766 | else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
4f4b3679 RH |
3767 | { |
3768 | /* In general, don't install a subreg involving two | |
3769 | modes not tieable. It can worsen register | |
3770 | allocation, and can even make invalid reload | |
3771 | insns, since the reg inside may need to be copied | |
3772 | from in the outside mode, and that may be invalid | |
3773 | if it is an fp reg copied in integer mode. | |
3774 | ||
3775 | We allow two exceptions to this: It is valid if | |
3776 | it is inside another SUBREG and the mode of that | |
3777 | SUBREG and the mode of the inside of TO is | |
3778 | tieable and it is valid if X is a SET that copies | |
3779 | FROM to CC0. */ | |
3780 | ||
3781 | if (GET_CODE (to) == SUBREG | |
3782 | && ! MODES_TIEABLE_P (GET_MODE (to), | |
3783 | GET_MODE (SUBREG_REG (to))) | |
3784 | && ! (code == SUBREG | |
3785 | && MODES_TIEABLE_P (GET_MODE (x), | |
3786 | GET_MODE (SUBREG_REG (to)))) | |
42301240 | 3787 | #ifdef HAVE_cc0 |
4f4b3679 | 3788 | && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) |
42301240 | 3789 | #endif |
4f4b3679 RH |
3790 | ) |
3791 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
42301240 | 3792 | |
cff9f8d5 | 3793 | #ifdef CANNOT_CHANGE_MODE_CLASS |
ed8afe3a | 3794 | if (code == SUBREG |
f8cfc6aa | 3795 | && REG_P (to) |
ed8afe3a | 3796 | && REGNO (to) < FIRST_PSEUDO_REGISTER |
cff9f8d5 AH |
3797 | && REG_CANNOT_CHANGE_MODE_P (REGNO (to), |
3798 | GET_MODE (to), | |
3799 | GET_MODE (x))) | |
ed8afe3a GK |
3800 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); |
3801 | #endif | |
3802 | ||
4f4b3679 RH |
3803 | new = (unique_copy && n_occurrences ? copy_rtx (to) : to); |
3804 | n_occurrences++; | |
3805 | } | |
3806 | else | |
3807 | /* If we are in a SET_DEST, suppress most cases unless we | |
3808 | have gone inside a MEM, in which case we want to | |
3809 | simplify the address. We assume here that things that | |
3810 | are actually part of the destination have their inner | |
663522cb | 3811 | parts in the first expression. This is true for SUBREG, |
4f4b3679 RH |
3812 | STRICT_LOW_PART, and ZERO_EXTRACT, which are the only |
3813 | things aside from REG and MEM that should appear in a | |
3814 | SET_DEST. */ | |
3815 | new = subst (XEXP (x, i), from, to, | |
3816 | (((in_dest | |
3817 | && (code == SUBREG || code == STRICT_LOW_PART | |
3818 | || code == ZERO_EXTRACT)) | |
3819 | || code == SET) | |
3820 | && i == 0), unique_copy); | |
3821 | ||
3822 | /* If we found that we will have to reject this combination, | |
3823 | indicate that by returning the CLOBBER ourselves, rather than | |
3824 | an expression containing it. This will speed things up as | |
3825 | well as prevent accidents where two CLOBBERs are considered | |
3826 | to be equal, thus producing an incorrect simplification. */ | |
3827 | ||
3828 | if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) | |
3829 | return new; | |
3830 | ||
cc8c96fd RS |
3831 | if (GET_CODE (x) == SUBREG |
3832 | && (GET_CODE (new) == CONST_INT | |
3833 | || GET_CODE (new) == CONST_DOUBLE)) | |
4161da12 | 3834 | { |
b0dd4808 | 3835 | enum machine_mode mode = GET_MODE (x); |
2e676d78 | 3836 | |
4161da12 AO |
3837 | x = simplify_subreg (GET_MODE (x), new, |
3838 | GET_MODE (SUBREG_REG (x)), | |
3839 | SUBREG_BYTE (x)); | |
3840 | if (! x) | |
b0dd4808 | 3841 | x = gen_rtx_CLOBBER (mode, const0_rtx); |
4161da12 AO |
3842 | } |
3843 | else if (GET_CODE (new) == CONST_INT | |
3844 | && GET_CODE (x) == ZERO_EXTEND) | |
3845 | { | |
3846 | x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
3847 | new, GET_MODE (XEXP (x, 0))); | |
341c100f | 3848 | gcc_assert (x); |
4161da12 AO |
3849 | } |
3850 | else | |
3851 | SUBST (XEXP (x, i), new); | |
230d793d | 3852 | } |
230d793d RS |
3853 | } |
3854 | } | |
3855 | ||
8079805d RK |
3856 | /* Try to simplify X. If the simplification changed the code, it is likely |
3857 | that further simplification will help, so loop, but limit the number | |
3858 | of repetitions that will be performed. */ | |
3859 | ||
3860 | for (i = 0; i < 4; i++) | |
3861 | { | |
3862 | /* If X is sufficiently simple, don't bother trying to do anything | |
3863 | with it. */ | |
3864 | if (code != CONST_INT && code != REG && code != CLOBBER) | |
6621d78e | 3865 | x = combine_simplify_rtx (x, op0_mode, in_dest); |
d0ab8cd3 | 3866 | |
8079805d RK |
3867 | if (GET_CODE (x) == code) |
3868 | break; | |
d0ab8cd3 | 3869 | |
8079805d | 3870 | code = GET_CODE (x); |
eeb43d32 | 3871 | |
8079805d RK |
3872 | /* We no longer know the original mode of operand 0 since we |
3873 | have changed the form of X) */ | |
3874 | op0_mode = VOIDmode; | |
3875 | } | |
eeb43d32 | 3876 | |
8079805d RK |
3877 | return x; |
3878 | } | |
3879 | \f | |
3880 | /* Simplify X, a piece of RTL. We just operate on the expression at the | |
3881 | outer level; call `subst' to simplify recursively. Return the new | |
3882 | expression. | |
3883 | ||
6621d78e PB |
3884 | OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero |
3885 | if we are inside a SET_DEST. */ | |
eeb43d32 | 3886 | |
8079805d | 3887 | static rtx |
6621d78e | 3888 | combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) |
8079805d RK |
3889 | { |
3890 | enum rtx_code code = GET_CODE (x); | |
3891 | enum machine_mode mode = GET_MODE (x); | |
3892 | rtx temp; | |
9a915772 | 3893 | rtx reversed; |
8079805d | 3894 | int i; |
d0ab8cd3 | 3895 | |
230d793d RS |
3896 | /* If this is a commutative operation, put a constant last and a complex |
3897 | expression first. We don't need to do this for comparisons here. */ | |
ec8e098d | 3898 | if (COMMUTATIVE_ARITH_P (x) |
e5c56fd9 | 3899 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) |
230d793d RS |
3900 | { |
3901 | temp = XEXP (x, 0); | |
3902 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3903 | SUBST (XEXP (x, 1), temp); | |
3904 | } | |
3905 | ||
663522cb | 3906 | /* If this is a simple operation applied to an IF_THEN_ELSE, try |
d0ab8cd3 | 3907 | applying it to the arms of the IF_THEN_ELSE. This often simplifies |
abe6e52f RK |
3908 | things. Check for cases where both arms are testing the same |
3909 | condition. | |
3910 | ||
3911 | Don't do anything if all operands are very simple. */ | |
3912 | ||
ec8e098d PB |
3913 | if ((BINARY_P (x) |
3914 | && ((!OBJECT_P (XEXP (x, 0)) | |
abe6e52f | 3915 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
ec8e098d PB |
3916 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) |
3917 | || (!OBJECT_P (XEXP (x, 1)) | |
abe6e52f | 3918 | && ! (GET_CODE (XEXP (x, 1)) == SUBREG |
ec8e098d PB |
3919 | && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) |
3920 | || (UNARY_P (x) | |
3921 | && (!OBJECT_P (XEXP (x, 0)) | |
abe6e52f | 3922 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
ec8e098d | 3923 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) |
d0ab8cd3 | 3924 | { |
d6edb99e | 3925 | rtx cond, true_rtx, false_rtx; |
abe6e52f | 3926 | |
d6edb99e | 3927 | cond = if_then_else_cond (x, &true_rtx, &false_rtx); |
0802d516 RK |
3928 | if (cond != 0 |
3929 | /* If everything is a comparison, what we have is highly unlikely | |
3930 | to be simpler, so don't use it. */ | |
ec8e098d PB |
3931 | && ! (COMPARISON_P (x) |
3932 | && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) | |
abe6e52f RK |
3933 | { |
3934 | rtx cop1 = const0_rtx; | |
3935 | enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); | |
3936 | ||
ec8e098d | 3937 | if (cond_code == NE && COMPARISON_P (cond)) |
15448afc RK |
3938 | return x; |
3939 | ||
663522cb | 3940 | /* Simplify the alternative arms; this may collapse the true and |
c6279378 UW |
3941 | false arms to store-flag values. Be careful to use copy_rtx |
3942 | here since true_rtx or false_rtx might share RTL with x as a | |
3943 | result of the if_then_else_cond call above. */ | |
3944 | true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); | |
3945 | false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); | |
9210df58 | 3946 | |
d6edb99e | 3947 | /* If true_rtx and false_rtx are not general_operands, an if_then_else |
085f1714 | 3948 | is unlikely to be simpler. */ |
d6edb99e ZW |
3949 | if (general_operand (true_rtx, VOIDmode) |
3950 | && general_operand (false_rtx, VOIDmode)) | |
085f1714 | 3951 | { |
434c87d4 JH |
3952 | enum rtx_code reversed; |
3953 | ||
085f1714 RH |
3954 | /* Restarting if we generate a store-flag expression will cause |
3955 | us to loop. Just drop through in this case. */ | |
3956 | ||
3957 | /* If the result values are STORE_FLAG_VALUE and zero, we can | |
3958 | just make the comparison operation. */ | |
d6edb99e | 3959 | if (true_rtx == const_true_rtx && false_rtx == const0_rtx) |
bcb34aa3 PB |
3960 | x = simplify_gen_relational (cond_code, mode, VOIDmode, |
3961 | cond, cop1); | |
fa4e13e0 | 3962 | else if (true_rtx == const0_rtx && false_rtx == const_true_rtx |
434c87d4 | 3963 | && ((reversed = reversed_comparison_code_parts |
79a490a9 | 3964 | (cond_code, cond, cop1, NULL)) |
434c87d4 | 3965 | != UNKNOWN)) |
bcb34aa3 PB |
3966 | x = simplify_gen_relational (reversed, mode, VOIDmode, |
3967 | cond, cop1); | |
085f1714 RH |
3968 | |
3969 | /* Likewise, we can make the negate of a comparison operation | |
3970 | if the result values are - STORE_FLAG_VALUE and zero. */ | |
d6edb99e ZW |
3971 | else if (GET_CODE (true_rtx) == CONST_INT |
3972 | && INTVAL (true_rtx) == - STORE_FLAG_VALUE | |
3973 | && false_rtx == const0_rtx) | |
f1c6ba8b | 3974 | x = simplify_gen_unary (NEG, mode, |
bcb34aa3 PB |
3975 | simplify_gen_relational (cond_code, |
3976 | mode, VOIDmode, | |
3977 | cond, cop1), | |
f1c6ba8b | 3978 | mode); |
d6edb99e ZW |
3979 | else if (GET_CODE (false_rtx) == CONST_INT |
3980 | && INTVAL (false_rtx) == - STORE_FLAG_VALUE | |
434c87d4 JH |
3981 | && true_rtx == const0_rtx |
3982 | && ((reversed = reversed_comparison_code_parts | |
79a490a9 | 3983 | (cond_code, cond, cop1, NULL)) |
434c87d4 | 3984 | != UNKNOWN)) |
f1c6ba8b | 3985 | x = simplify_gen_unary (NEG, mode, |
bcb34aa3 PB |
3986 | simplify_gen_relational (reversed, |
3987 | mode, VOIDmode, | |
3988 | cond, cop1), | |
f1c6ba8b | 3989 | mode); |
085f1714 RH |
3990 | else |
3991 | return gen_rtx_IF_THEN_ELSE (mode, | |
bcb34aa3 PB |
3992 | simplify_gen_relational (cond_code, |
3993 | mode, | |
3994 | VOIDmode, | |
3995 | cond, | |
3996 | cop1), | |
d6edb99e | 3997 | true_rtx, false_rtx); |
5109d49f | 3998 | |
085f1714 RH |
3999 | code = GET_CODE (x); |
4000 | op0_mode = VOIDmode; | |
4001 | } | |
abe6e52f | 4002 | } |
d0ab8cd3 RK |
4003 | } |
4004 | ||
230d793d RS |
4005 | /* Try to fold this expression in case we have constants that weren't |
4006 | present before. */ | |
4007 | temp = 0; | |
4008 | switch (GET_RTX_CLASS (code)) | |
4009 | { | |
ec8e098d | 4010 | case RTX_UNARY: |
c0657872 RS |
4011 | if (op0_mode == VOIDmode) |
4012 | op0_mode = GET_MODE (XEXP (x, 0)); | |
230d793d RS |
4013 | temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); |
4014 | break; | |
ec8e098d PB |
4015 | case RTX_COMPARE: |
4016 | case RTX_COMM_COMPARE: | |
47b1e19b JH |
4017 | { |
4018 | enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
4019 | if (cmp_mode == VOIDmode) | |
1cac8785 DD |
4020 | { |
4021 | cmp_mode = GET_MODE (XEXP (x, 1)); | |
4022 | if (cmp_mode == VOIDmode) | |
4023 | cmp_mode = op0_mode; | |
4024 | } | |
7ce3e360 | 4025 | temp = simplify_relational_operation (code, mode, cmp_mode, |
47b1e19b JH |
4026 | XEXP (x, 0), XEXP (x, 1)); |
4027 | } | |
230d793d | 4028 | break; |
ec8e098d PB |
4029 | case RTX_COMM_ARITH: |
4030 | case RTX_BIN_ARITH: | |
230d793d RS |
4031 | temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); |
4032 | break; | |
ec8e098d PB |
4033 | case RTX_BITFIELD_OPS: |
4034 | case RTX_TERNARY: | |
230d793d RS |
4035 | temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), |
4036 | XEXP (x, 1), XEXP (x, 2)); | |
4037 | break; | |
ec8e098d PB |
4038 | default: |
4039 | break; | |
230d793d RS |
4040 | } |
4041 | ||
4042 | if (temp) | |
4531c1c7 DN |
4043 | { |
4044 | x = temp; | |
4045 | code = GET_CODE (temp); | |
4046 | op0_mode = VOIDmode; | |
4047 | mode = GET_MODE (temp); | |
4048 | } | |
230d793d | 4049 | |
230d793d | 4050 | /* First see if we can apply the inverse distributive law. */ |
224eeff2 RK |
4051 | if (code == PLUS || code == MINUS |
4052 | || code == AND || code == IOR || code == XOR) | |
230d793d RS |
4053 | { |
4054 | x = apply_distributive_law (x); | |
4055 | code = GET_CODE (x); | |
6e20204f | 4056 | op0_mode = VOIDmode; |
230d793d RS |
4057 | } |
4058 | ||
4059 | /* If CODE is an associative operation not otherwise handled, see if we | |
4060 | can associate some operands. This can win if they are constants or | |
e0e08ac2 | 4061 | if they are logically related (i.e. (a & b) & a). */ |
493efd37 TM |
4062 | if ((code == PLUS || code == MINUS || code == MULT || code == DIV |
4063 | || code == AND || code == IOR || code == XOR | |
230d793d | 4064 | || code == SMAX || code == SMIN || code == UMAX || code == UMIN) |
493efd37 | 4065 | && ((INTEGRAL_MODE_P (mode) && code != DIV) |
4ba5f925 | 4066 | || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) |
230d793d RS |
4067 | { |
4068 | if (GET_CODE (XEXP (x, 0)) == code) | |
4069 | { | |
4070 | rtx other = XEXP (XEXP (x, 0), 0); | |
4071 | rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
4072 | rtx inner_op1 = XEXP (x, 1); | |
4073 | rtx inner; | |
663522cb | 4074 | |
230d793d RS |
4075 | /* Make sure we pass the constant operand if any as the second |
4076 | one if this is a commutative operation. */ | |
ec8e098d | 4077 | if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) |
230d793d RS |
4078 | { |
4079 | rtx tem = inner_op0; | |
4080 | inner_op0 = inner_op1; | |
4081 | inner_op1 = tem; | |
4082 | } | |
4083 | inner = simplify_binary_operation (code == MINUS ? PLUS | |
4084 | : code == DIV ? MULT | |
230d793d RS |
4085 | : code, |
4086 | mode, inner_op0, inner_op1); | |
4087 | ||
4088 | /* For commutative operations, try the other pair if that one | |
4089 | didn't simplify. */ | |
ec8e098d | 4090 | if (inner == 0 && COMMUTATIVE_ARITH_P (x)) |
230d793d RS |
4091 | { |
4092 | other = XEXP (XEXP (x, 0), 1); | |
4093 | inner = simplify_binary_operation (code, mode, | |
4094 | XEXP (XEXP (x, 0), 0), | |
4095 | XEXP (x, 1)); | |
4096 | } | |
4097 | ||
4098 | if (inner) | |
bcb34aa3 | 4099 | return simplify_gen_binary (code, mode, other, inner); |
230d793d RS |
4100 | } |
4101 | } | |
4102 | ||
4103 | /* A little bit of algebraic simplification here. */ | |
4104 | switch (code) | |
4105 | { | |
4106 | case MEM: | |
4107 | /* Ensure that our address has any ASHIFTs converted to MULT in case | |
4108 | address-recognizing predicates are called later. */ | |
4109 | temp = make_compound_operation (XEXP (x, 0), MEM); | |
4110 | SUBST (XEXP (x, 0), temp); | |
4111 | break; | |
4112 | ||
4113 | case SUBREG: | |
eea50aa0 JH |
4114 | if (op0_mode == VOIDmode) |
4115 | op0_mode = GET_MODE (SUBREG_REG (x)); | |
230d793d | 4116 | |
4de249d9 | 4117 | /* See if this can be moved to simplify_subreg. */ |
3c99d5ff | 4118 | if (CONSTANT_P (SUBREG_REG (x)) |
156755ac | 4119 | && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) |
4de249d9 | 4120 | /* Don't call gen_lowpart if the inner mode |
156755ac JJ |
4121 | is VOIDmode and we cannot simplify it, as SUBREG without |
4122 | inner mode is invalid. */ | |
4123 | && (GET_MODE (SUBREG_REG (x)) != VOIDmode | |
4124 | || gen_lowpart_common (mode, SUBREG_REG (x)))) | |
4de249d9 | 4125 | return gen_lowpart (mode, SUBREG_REG (x)); |
230d793d | 4126 | |
a13287e1 AM |
4127 | if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) |
4128 | break; | |
eea50aa0 JH |
4129 | { |
4130 | rtx temp; | |
4131 | temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, | |
23190837 | 4132 | SUBREG_BYTE (x)); |
eea50aa0 JH |
4133 | if (temp) |
4134 | return temp; | |
4135 | } | |
b65c1b5b | 4136 | |
30984c57 | 4137 | /* Don't change the mode of the MEM if that would change the meaning |
3eacd71f | 4138 | of the address. */ |
3c0cb5de | 4139 | if (MEM_P (SUBREG_REG (x)) |
30984c57 | 4140 | && (MEM_VOLATILE_P (SUBREG_REG (x)) |
3eacd71f | 4141 | || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) |
30984c57 JJ |
4142 | return gen_rtx_CLOBBER (mode, const0_rtx); |
4143 | ||
87e3e0c1 RK |
4144 | /* Note that we cannot do any narrowing for non-constants since |
4145 | we might have been counting on using the fact that some bits were | |
4146 | zero. We now do this in the SET. */ | |
4147 | ||
230d793d RS |
4148 | break; |
4149 | ||
4150 | case NOT: | |
230d793d RS |
4151 | if (GET_CODE (XEXP (x, 0)) == SUBREG |
4152 | && subreg_lowpart_p (XEXP (x, 0)) | |
4153 | && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) | |
4154 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) | |
4155 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT | |
4156 | && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) | |
4157 | { | |
4158 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); | |
4159 | ||
38a448ca | 4160 | x = gen_rtx_ROTATE (inner_mode, |
f1c6ba8b RK |
4161 | simplify_gen_unary (NOT, inner_mode, const1_rtx, |
4162 | inner_mode), | |
38a448ca | 4163 | XEXP (SUBREG_REG (XEXP (x, 0)), 1)); |
4de249d9 | 4164 | return gen_lowpart (mode, x); |
230d793d | 4165 | } |
663522cb | 4166 | |
230d793d | 4167 | /* Apply De Morgan's laws to reduce number of patterns for machines |
23190837 AJ |
4168 | with negating logical insns (and-not, nand, etc.). If result has |
4169 | only one NOT, put it first, since that is how the patterns are | |
4170 | coded. */ | |
230d793d RS |
4171 | |
4172 | if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) | |
23190837 | 4173 | { |
663522cb | 4174 | rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); |
5bd60ce6 | 4175 | enum machine_mode op_mode; |
230d793d | 4176 | |
5bd60ce6 | 4177 | op_mode = GET_MODE (in1); |
f1c6ba8b | 4178 | in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode); |
230d793d | 4179 | |
5bd60ce6 RH |
4180 | op_mode = GET_MODE (in2); |
4181 | if (op_mode == VOIDmode) | |
4182 | op_mode = mode; | |
f1c6ba8b | 4183 | in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode); |
663522cb | 4184 | |
5bd60ce6 | 4185 | if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT) |
663522cb KH |
4186 | { |
4187 | rtx tem = in2; | |
4188 | in2 = in1; in1 = tem; | |
4189 | } | |
4190 | ||
f1c6ba8b RK |
4191 | return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, |
4192 | mode, in1, in2); | |
663522cb | 4193 | } |
230d793d RS |
4194 | break; |
4195 | ||
4196 | case NEG: | |
0f41302f | 4197 | /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ |
4f61b3b7 RS |
4198 | if (GET_CODE (XEXP (x, 0)) == XOR |
4199 | && XEXP (XEXP (x, 0), 1) == const1_rtx | |
951553af | 4200 | && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) |
bcb34aa3 PB |
4201 | return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), |
4202 | constm1_rtx); | |
d0ab8cd3 | 4203 | |
230d793d RS |
4204 | temp = expand_compound_operation (XEXP (x, 0)); |
4205 | ||
4206 | /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
23190837 | 4207 | replaced by (lshiftrt X C). This will convert |
230d793d RS |
4208 | (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ |
4209 | ||
4210 | if (GET_CODE (temp) == ASHIFTRT | |
4211 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
4212 | && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
8079805d RK |
4213 | return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), |
4214 | INTVAL (XEXP (temp, 1))); | |
230d793d | 4215 | |
951553af | 4216 | /* If X has only a single bit that might be nonzero, say, bit I, convert |
230d793d RS |
4217 | (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of |
4218 | MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
4219 | (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
4220 | or a SUBREG of one since we'd be making the expression more | |
4221 | complex if it was just a register. */ | |
4222 | ||
f8cfc6aa | 4223 | if (!REG_P (temp) |
230d793d | 4224 | && ! (GET_CODE (temp) == SUBREG |
f8cfc6aa | 4225 | && REG_P (SUBREG_REG (temp))) |
951553af | 4226 | && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) |
230d793d RS |
4227 | { |
4228 | rtx temp1 = simplify_shift_const | |
5f4f0e22 CH |
4229 | (NULL_RTX, ASHIFTRT, mode, |
4230 | simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, | |
230d793d RS |
4231 | GET_MODE_BITSIZE (mode) - 1 - i), |
4232 | GET_MODE_BITSIZE (mode) - 1 - i); | |
4233 | ||
4234 | /* If all we did was surround TEMP with the two shifts, we | |
4235 | haven't improved anything, so don't use it. Otherwise, | |
4236 | we are better off with TEMP1. */ | |
4237 | if (GET_CODE (temp1) != ASHIFTRT | |
4238 | || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
4239 | || XEXP (XEXP (temp1, 0), 0) != temp) | |
8079805d | 4240 | return temp1; |
230d793d RS |
4241 | } |
4242 | break; | |
4243 | ||
2ca9ae17 | 4244 | case TRUNCATE: |
e30fb98f JL |
4245 | /* We can't handle truncation to a partial integer mode here |
4246 | because we don't know the real bitsize of the partial | |
4247 | integer mode. */ | |
4248 | if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
4249 | break; | |
4250 | ||
80608e27 JL |
4251 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
4252 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
4253 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) | |
2ca9ae17 JW |
4254 | SUBST (XEXP (x, 0), |
4255 | force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), | |
4256 | GET_MODE_MASK (mode), NULL_RTX, 0)); | |
0f13a422 ILT |
4257 | |
4258 | /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ | |
4259 | if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4260 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4261 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
4262 | return XEXP (XEXP (x, 0), 0); | |
4263 | ||
4264 | /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is | |
4265 | (OP:SI foo:SI) if OP is NEG or ABS. */ | |
4266 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4267 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4268 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND | |
4269 | || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) | |
4270 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4271 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4272 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
0f13a422 ILT |
4273 | |
4274 | /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is | |
4275 | (truncate:SI x). */ | |
4276 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4277 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE | |
4278 | && subreg_lowpart_p (XEXP (x, 0))) | |
4279 | return SUBREG_REG (XEXP (x, 0)); | |
4280 | ||
4281 | /* If we know that the value is already truncated, we can | |
14a774a9 RK |
4282 | replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION |
4283 | is nonzero for the corresponding modes. But don't do this | |
4284 | for an (LSHIFTRT (MULT ...)) since this will cause problems | |
4285 | with the umulXi3_highpart patterns. */ | |
6a992214 JL |
4286 | if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
4287 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
4288 | && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
26c34780 | 4289 | >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1) |
14a774a9 | 4290 | && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
23190837 | 4291 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)) |
4de249d9 | 4292 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 ILT |
4293 | |
4294 | /* A truncate of a comparison can be replaced with a subreg if | |
4295 | STORE_FLAG_VALUE permits. This is like the previous test, | |
4296 | but it works even if the comparison is done in a mode larger | |
4297 | than HOST_BITS_PER_WIDE_INT. */ | |
4298 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
ec8e098d | 4299 | && COMPARISON_P (XEXP (x, 0)) |
663522cb | 4300 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) |
4de249d9 | 4301 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 ILT |
4302 | |
4303 | /* Similarly, a truncate of a register whose value is a | |
4304 | comparison can be replaced with a subreg if STORE_FLAG_VALUE | |
4305 | permits. */ | |
4306 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
663522cb | 4307 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 |
0f13a422 | 4308 | && (temp = get_last_value (XEXP (x, 0))) |
ec8e098d | 4309 | && COMPARISON_P (temp)) |
4de249d9 | 4310 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 | 4311 | |
2ca9ae17 JW |
4312 | break; |
4313 | ||
230d793d RS |
4314 | case FLOAT_TRUNCATE: |
4315 | /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ | |
4316 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
4317 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
663522cb | 4318 | return XEXP (XEXP (x, 0), 0); |
4635f748 | 4319 | |
73a39fc4 EC |
4320 | /* (float_truncate:SF (float_truncate:DF foo:XF)) |
4321 | = (float_truncate:SF foo:XF). | |
e0bb17a8 | 4322 | This may eliminate double rounding, so it is unsafe. |
949824fe | 4323 | |
73a39fc4 EC |
4324 | (float_truncate:SF (float_extend:XF foo:DF)) |
4325 | = (float_truncate:SF foo:DF). | |
949824fe | 4326 | |
73a39fc4 | 4327 | (float_truncate:DF (float_extend:XF foo:SF)) |
3dc575ff | 4328 | = (float_extend:SF foo:DF). */ |
949824fe JH |
4329 | if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE |
4330 | && flag_unsafe_math_optimizations) | |
4331 | || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND) | |
4332 | return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), | |
79a490a9 AJ |
4333 | 0))) |
4334 | > GET_MODE_SIZE (mode) | |
949824fe | 4335 | ? FLOAT_TRUNCATE : FLOAT_EXTEND, |
79a490a9 | 4336 | mode, |
cb119f82 | 4337 | XEXP (XEXP (x, 0), 0), mode); |
949824fe JH |
4338 | |
4339 | /* (float_truncate (float x)) is (float x) */ | |
4340 | if (GET_CODE (XEXP (x, 0)) == FLOAT | |
4341 | && (flag_unsafe_math_optimizations | |
4342 | || ((unsigned)significand_size (GET_MODE (XEXP (x, 0))) | |
4343 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) | |
4344 | - num_sign_bit_copies (XEXP (XEXP (x, 0), 0), | |
4345 | GET_MODE (XEXP (XEXP (x, 0), 0))))))) | |
4346 | return simplify_gen_unary (FLOAT, mode, | |
4347 | XEXP (XEXP (x, 0), 0), | |
4348 | GET_MODE (XEXP (XEXP (x, 0), 0))); | |
4349 | ||
4635f748 RK |
4350 | /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is |
4351 | (OP:SF foo:SF) if OP is NEG or ABS. */ | |
4352 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4353 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4354 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND | |
4355 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4356 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4357 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
1d12df72 RK |
4358 | |
4359 | /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) | |
4360 | is (float_truncate:SF x). */ | |
4361 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4362 | && subreg_lowpart_p (XEXP (x, 0)) | |
4363 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) | |
4364 | return SUBREG_REG (XEXP (x, 0)); | |
663522cb | 4365 | break; |
949824fe JH |
4366 | case FLOAT_EXTEND: |
4367 | /* (float_extend (float_extend x)) is (float_extend x) | |
73a39fc4 | 4368 | |
949824fe | 4369 | (float_extend (float x)) is (float x) assuming that double |
73a39fc4 | 4370 | rounding can't happen. |
949824fe JH |
4371 | */ |
4372 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
4373 | || (GET_CODE (XEXP (x, 0)) == FLOAT | |
4374 | && ((unsigned)significand_size (GET_MODE (XEXP (x, 0))) | |
4375 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) | |
4376 | - num_sign_bit_copies (XEXP (XEXP (x, 0), 0), | |
4377 | GET_MODE (XEXP (XEXP (x, 0), 0))))))) | |
4378 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, | |
4379 | XEXP (XEXP (x, 0), 0), | |
4380 | GET_MODE (XEXP (XEXP (x, 0), 0))); | |
230d793d | 4381 | |
949824fe | 4382 | break; |
230d793d RS |
4383 | #ifdef HAVE_cc0 |
4384 | case COMPARE: | |
4385 | /* Convert (compare FOO (const_int 0)) to FOO unless we aren't | |
4386 | using cc0, in which case we want to leave it as a COMPARE | |
4387 | so we can distinguish it from a register-register-copy. */ | |
4388 | if (XEXP (x, 1) == const0_rtx) | |
4389 | return XEXP (x, 0); | |
4390 | ||
71925bc0 RS |
4391 | /* x - 0 is the same as x unless x's mode has signed zeros and |
4392 | allows rounding towards -infinity. Under those conditions, | |
4393 | 0 - 0 is -0. */ | |
4394 | if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0))) | |
4395 | && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0)))) | |
230d793d RS |
4396 | && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) |
4397 | return XEXP (x, 0); | |
4398 | break; | |
4399 | #endif | |
4400 | ||
4401 | case CONST: | |
4402 | /* (const (const X)) can become (const X). Do it this way rather than | |
4403 | returning the inner CONST since CONST can be shared with a | |
4404 | REG_EQUAL note. */ | |
4405 | if (GET_CODE (XEXP (x, 0)) == CONST) | |
4406 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4407 | break; | |
4408 | ||
4409 | #ifdef HAVE_lo_sum | |
4410 | case LO_SUM: | |
4411 | /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
4412 | can add in an offset. find_split_point will split this address up | |
4413 | again if it doesn't match. */ | |
4414 | if (GET_CODE (XEXP (x, 0)) == HIGH | |
4415 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
4416 | return XEXP (x, 1); | |
4417 | break; | |
4418 | #endif | |
4419 | ||
4420 | case PLUS: | |
16823694 GK |
4421 | /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). |
4422 | */ | |
73a39fc4 | 4423 | if (GET_CODE (XEXP (x, 0)) == MULT |
16823694 GK |
4424 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG) |
4425 | { | |
4426 | rtx in1, in2; | |
73a39fc4 | 4427 | |
16823694 GK |
4428 | in1 = XEXP (XEXP (XEXP (x, 0), 0), 0); |
4429 | in2 = XEXP (XEXP (x, 0), 1); | |
bcb34aa3 PB |
4430 | return simplify_gen_binary (MINUS, mode, XEXP (x, 1), |
4431 | simplify_gen_binary (MULT, mode, | |
4432 | in1, in2)); | |
16823694 GK |
4433 | } |
4434 | ||
230d793d RS |
4435 | /* If we have (plus (plus (A const) B)), associate it so that CONST is |
4436 | outermost. That's because that's the way indexed addresses are | |
4437 | supposed to appear. This code used to check many more cases, but | |
4438 | they are now checked elsewhere. */ | |
4439 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
4440 | && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) | |
bcb34aa3 PB |
4441 | return simplify_gen_binary (PLUS, mode, |
4442 | simplify_gen_binary (PLUS, mode, | |
4443 | XEXP (XEXP (x, 0), 0), | |
4444 | XEXP (x, 1)), | |
4445 | XEXP (XEXP (x, 0), 1)); | |
230d793d RS |
4446 | |
4447 | /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) | |
4448 | when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
4449 | bit-field and can be replaced by either a sign_extend or a | |
e6380233 JL |
4450 | sign_extract. The `and' may be a zero_extend and the two |
4451 | <c>, -<c> constants may be reversed. */ | |
230d793d RS |
4452 | if (GET_CODE (XEXP (x, 0)) == XOR |
4453 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4454 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
663522cb | 4455 | && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) |
e6380233 JL |
4456 | && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 |
4457 | || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
5f4f0e22 | 4458 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
4459 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND |
4460 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
4461 | && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
5f4f0e22 | 4462 | == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) |
230d793d RS |
4463 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND |
4464 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) | |
770ae6cc | 4465 | == (unsigned int) i + 1)))) |
8079805d RK |
4466 | return simplify_shift_const |
4467 | (NULL_RTX, ASHIFTRT, mode, | |
4468 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4469 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
4470 | GET_MODE_BITSIZE (mode) - (i + 1)), | |
4471 | GET_MODE_BITSIZE (mode) - (i + 1)); | |
230d793d | 4472 | |
bc0776c6 RK |
4473 | /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if |
4474 | C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE | |
4475 | is 1. This produces better code than the alternative immediately | |
4476 | below. */ | |
ec8e098d | 4477 | if (COMPARISON_P (XEXP (x, 0)) |
bc0776c6 | 4478 | && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) |
9a915772 | 4479 | || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)) |
14f02e73 | 4480 | && (reversed = reversed_comparison (XEXP (x, 0), mode))) |
8079805d | 4481 | return |
f1c6ba8b | 4482 | simplify_gen_unary (NEG, mode, reversed, mode); |
bc0776c6 RK |
4483 | |
4484 | /* If only the low-order bit of X is possibly nonzero, (plus x -1) | |
230d793d RS |
4485 | can become (ashiftrt (ashift (xor x 1) C) C) where C is |
4486 | the bitsize of the mode - 1. This allows simplification of | |
4487 | "a = (b & 8) == 0;" */ | |
4488 | if (XEXP (x, 1) == constm1_rtx | |
f8cfc6aa | 4489 | && !REG_P (XEXP (x, 0)) |
e869aa39 | 4490 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
f8cfc6aa | 4491 | && REG_P (SUBREG_REG (XEXP (x, 0)))) |
951553af | 4492 | && nonzero_bits (XEXP (x, 0), mode) == 1) |
8079805d RK |
4493 | return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, |
4494 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
f1c6ba8b | 4495 | gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), |
8079805d RK |
4496 | GET_MODE_BITSIZE (mode) - 1), |
4497 | GET_MODE_BITSIZE (mode) - 1); | |
02f4ada4 RK |
4498 | |
4499 | /* If we are adding two things that have no bits in common, convert | |
4500 | the addition into an IOR. This will often be further simplified, | |
4501 | for example in cases like ((a & 1) + (a & 2)), which can | |
4502 | become a & 3. */ | |
4503 | ||
ac49a949 | 4504 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
951553af RK |
4505 | && (nonzero_bits (XEXP (x, 0), mode) |
4506 | & nonzero_bits (XEXP (x, 1), mode)) == 0) | |
085f1714 RH |
4507 | { |
4508 | /* Try to simplify the expression further. */ | |
bcb34aa3 | 4509 | rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); |
6621d78e | 4510 | temp = combine_simplify_rtx (tor, mode, in_dest); |
085f1714 RH |
4511 | |
4512 | /* If we could, great. If not, do not go ahead with the IOR | |
4513 | replacement, since PLUS appears in many special purpose | |
4514 | address arithmetic instructions. */ | |
4515 | if (GET_CODE (temp) != CLOBBER && temp != tor) | |
4516 | return temp; | |
4517 | } | |
230d793d RS |
4518 | break; |
4519 | ||
4520 | case MINUS: | |
0802d516 RK |
4521 | /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done |
4522 | by reversing the comparison code if valid. */ | |
4523 | if (STORE_FLAG_VALUE == 1 | |
4524 | && XEXP (x, 0) == const1_rtx | |
ec8e098d | 4525 | && COMPARISON_P (XEXP (x, 1)) |
14f02e73 | 4526 | && (reversed = reversed_comparison (XEXP (x, 1), mode))) |
9a915772 | 4527 | return reversed; |
5109d49f | 4528 | |
230d793d RS |
4529 | /* (minus <foo> (and <foo> (const_int -pow2))) becomes |
4530 | (and <foo> (const_int pow2-1)) */ | |
4531 | if (GET_CODE (XEXP (x, 1)) == AND | |
4532 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
663522cb | 4533 | && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 |
230d793d | 4534 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
8079805d | 4535 | return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), |
663522cb | 4536 | -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); |
7bef8680 | 4537 | |
16823694 GK |
4538 | /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). |
4539 | */ | |
73a39fc4 | 4540 | if (GET_CODE (XEXP (x, 1)) == MULT |
16823694 GK |
4541 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG) |
4542 | { | |
4543 | rtx in1, in2; | |
73a39fc4 | 4544 | |
16823694 GK |
4545 | in1 = XEXP (XEXP (XEXP (x, 1), 0), 0); |
4546 | in2 = XEXP (XEXP (x, 1), 1); | |
bcb34aa3 PB |
4547 | return simplify_gen_binary (PLUS, mode, |
4548 | simplify_gen_binary (MULT, mode, | |
4549 | in1, in2), | |
4550 | XEXP (x, 0)); | |
16823694 GK |
4551 | } |
4552 | ||
73a39fc4 | 4553 | /* Canonicalize (minus (neg A) (mult B C)) to |
e869aa39 | 4554 | (minus (mult (neg B) C) A). */ |
73a39fc4 | 4555 | if (GET_CODE (XEXP (x, 1)) == MULT |
16823694 GK |
4556 | && GET_CODE (XEXP (x, 0)) == NEG) |
4557 | { | |
4558 | rtx in1, in2; | |
73a39fc4 | 4559 | |
16823694 GK |
4560 | in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode); |
4561 | in2 = XEXP (XEXP (x, 1), 1); | |
bcb34aa3 PB |
4562 | return simplify_gen_binary (MINUS, mode, |
4563 | simplify_gen_binary (MULT, mode, | |
4564 | in1, in2), | |
4565 | XEXP (XEXP (x, 0), 0)); | |
16823694 GK |
4566 | } |
4567 | ||
7bef8680 RK |
4568 | /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for |
4569 | integers. */ | |
4570 | if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) | |
bcb34aa3 PB |
4571 | return simplify_gen_binary (MINUS, mode, |
4572 | simplify_gen_binary (MINUS, mode, | |
4573 | XEXP (x, 0), | |
4574 | XEXP (XEXP (x, 1), 0)), | |
4575 | XEXP (XEXP (x, 1), 1)); | |
230d793d RS |
4576 | break; |
4577 | ||
4578 | case MULT: | |
4579 | /* If we have (mult (plus A B) C), apply the distributive law and then | |
4580 | the inverse distributive law to see if things simplify. This | |
4581 | occurs mostly in addresses, often when unrolling loops. */ | |
4582 | ||
4583 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
4584 | { | |
bcb34aa3 PB |
4585 | rtx result = distribute_and_simplify_rtx (x, 0); |
4586 | if (result) | |
4587 | return result; | |
230d793d | 4588 | } |
bcb34aa3 | 4589 | |
4ba5f925 JH |
4590 | /* Try simplify a*(b/c) as (a*b)/c. */ |
4591 | if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations | |
4592 | && GET_CODE (XEXP (x, 0)) == DIV) | |
4593 | { | |
4594 | rtx tem = simplify_binary_operation (MULT, mode, | |
4595 | XEXP (XEXP (x, 0), 0), | |
4596 | XEXP (x, 1)); | |
4597 | if (tem) | |
bcb34aa3 | 4598 | return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); |
4ba5f925 | 4599 | } |
230d793d RS |
4600 | break; |
4601 | ||
4602 | case UDIV: | |
4603 | /* If this is a divide by a power of two, treat it as a shift if | |
4604 | its first operand is a shift. */ | |
4605 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
4606 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
4607 | && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
4608 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
4609 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
4610 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
4611 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
8079805d | 4612 | return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); |
230d793d RS |
4613 | break; |
4614 | ||
4615 | case EQ: case NE: | |
4616 | case GT: case GTU: case GE: case GEU: | |
4617 | case LT: case LTU: case LE: case LEU: | |
69bc0a1f | 4618 | case UNEQ: case LTGT: |
23190837 AJ |
4619 | case UNGT: case UNGE: |
4620 | case UNLT: case UNLE: | |
69bc0a1f | 4621 | case UNORDERED: case ORDERED: |
230d793d RS |
4622 | /* If the first operand is a condition code, we can't do anything |
4623 | with it. */ | |
4624 | if (GET_CODE (XEXP (x, 0)) == COMPARE | |
4625 | || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
8beccec8 | 4626 | && ! CC0_P (XEXP (x, 0)))) |
230d793d RS |
4627 | { |
4628 | rtx op0 = XEXP (x, 0); | |
4629 | rtx op1 = XEXP (x, 1); | |
4630 | enum rtx_code new_code; | |
4631 | ||
4632 | if (GET_CODE (op0) == COMPARE) | |
4633 | op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4634 | ||
4635 | /* Simplify our comparison, if possible. */ | |
4636 | new_code = simplify_comparison (code, &op0, &op1); | |
4637 | ||
230d793d | 4638 | /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X |
951553af | 4639 | if only the low-order bit is possibly nonzero in X (such as when |
5109d49f RK |
4640 | X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to |
4641 | (xor X 1) or (minus 1 X); we use the former. Finally, if X is | |
4642 | known to be either 0 or -1, NE becomes a NEG and EQ becomes | |
4643 | (plus X 1). | |
4644 | ||
4645 | Remove any ZERO_EXTRACT we made when thinking this was a | |
4646 | comparison. It may now be simpler to use, e.g., an AND. If a | |
4647 | ZERO_EXTRACT is indeed appropriate, it will be placed back by | |
4648 | the call to make_compound_operation in the SET case. */ | |
4649 | ||
0802d516 RK |
4650 | if (STORE_FLAG_VALUE == 1 |
4651 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
a191f0ee RH |
4652 | && op1 == const0_rtx |
4653 | && mode == GET_MODE (op0) | |
4654 | && nonzero_bits (op0, mode) == 1) | |
4de249d9 PB |
4655 | return gen_lowpart (mode, |
4656 | expand_compound_operation (op0)); | |
5109d49f | 4657 | |
0802d516 RK |
4658 | else if (STORE_FLAG_VALUE == 1 |
4659 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4660 | && op1 == const0_rtx |
a191f0ee | 4661 | && mode == GET_MODE (op0) |
5109d49f RK |
4662 | && (num_sign_bit_copies (op0, mode) |
4663 | == GET_MODE_BITSIZE (mode))) | |
4664 | { | |
4665 | op0 = expand_compound_operation (op0); | |
f1c6ba8b | 4666 | return simplify_gen_unary (NEG, mode, |
4de249d9 | 4667 | gen_lowpart (mode, op0), |
f1c6ba8b | 4668 | mode); |
5109d49f RK |
4669 | } |
4670 | ||
0802d516 RK |
4671 | else if (STORE_FLAG_VALUE == 1 |
4672 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4673 | && op1 == const0_rtx |
a191f0ee | 4674 | && mode == GET_MODE (op0) |
5109d49f | 4675 | && nonzero_bits (op0, mode) == 1) |
818b11b9 RK |
4676 | { |
4677 | op0 = expand_compound_operation (op0); | |
bcb34aa3 PB |
4678 | return simplify_gen_binary (XOR, mode, |
4679 | gen_lowpart (mode, op0), | |
4680 | const1_rtx); | |
5109d49f | 4681 | } |
818b11b9 | 4682 | |
0802d516 RK |
4683 | else if (STORE_FLAG_VALUE == 1 |
4684 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4685 | && op1 == const0_rtx |
a191f0ee | 4686 | && mode == GET_MODE (op0) |
5109d49f RK |
4687 | && (num_sign_bit_copies (op0, mode) |
4688 | == GET_MODE_BITSIZE (mode))) | |
4689 | { | |
4690 | op0 = expand_compound_operation (op0); | |
4de249d9 | 4691 | return plus_constant (gen_lowpart (mode, op0), 1); |
818b11b9 | 4692 | } |
230d793d | 4693 | |
5109d49f RK |
4694 | /* If STORE_FLAG_VALUE is -1, we have cases similar to |
4695 | those above. */ | |
0802d516 RK |
4696 | if (STORE_FLAG_VALUE == -1 |
4697 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4698 | && op1 == const0_rtx |
5109d49f RK |
4699 | && (num_sign_bit_copies (op0, mode) |
4700 | == GET_MODE_BITSIZE (mode))) | |
4de249d9 PB |
4701 | return gen_lowpart (mode, |
4702 | expand_compound_operation (op0)); | |
5109d49f | 4703 | |
0802d516 RK |
4704 | else if (STORE_FLAG_VALUE == -1 |
4705 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4706 | && op1 == const0_rtx |
a191f0ee | 4707 | && mode == GET_MODE (op0) |
5109d49f RK |
4708 | && nonzero_bits (op0, mode) == 1) |
4709 | { | |
4710 | op0 = expand_compound_operation (op0); | |
f1c6ba8b | 4711 | return simplify_gen_unary (NEG, mode, |
4de249d9 | 4712 | gen_lowpart (mode, op0), |
f1c6ba8b | 4713 | mode); |
5109d49f RK |
4714 | } |
4715 | ||
0802d516 RK |
4716 | else if (STORE_FLAG_VALUE == -1 |
4717 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4718 | && op1 == const0_rtx |
a191f0ee | 4719 | && mode == GET_MODE (op0) |
5109d49f RK |
4720 | && (num_sign_bit_copies (op0, mode) |
4721 | == GET_MODE_BITSIZE (mode))) | |
230d793d | 4722 | { |
818b11b9 | 4723 | op0 = expand_compound_operation (op0); |
f1c6ba8b | 4724 | return simplify_gen_unary (NOT, mode, |
4de249d9 | 4725 | gen_lowpart (mode, op0), |
f1c6ba8b | 4726 | mode); |
5109d49f RK |
4727 | } |
4728 | ||
4729 | /* If X is 0/1, (eq X 0) is X-1. */ | |
0802d516 RK |
4730 | else if (STORE_FLAG_VALUE == -1 |
4731 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4732 | && op1 == const0_rtx |
a191f0ee | 4733 | && mode == GET_MODE (op0) |
5109d49f RK |
4734 | && nonzero_bits (op0, mode) == 1) |
4735 | { | |
4736 | op0 = expand_compound_operation (op0); | |
4de249d9 | 4737 | return plus_constant (gen_lowpart (mode, op0), -1); |
230d793d | 4738 | } |
230d793d RS |
4739 | |
4740 | /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
951553af RK |
4741 | one bit that might be nonzero, we can convert (ne x 0) to |
4742 | (ashift x c) where C puts the bit in the sign bit. Remove any | |
4743 | AND with STORE_FLAG_VALUE when we are done, since we are only | |
4744 | going to test the sign bit. */ | |
3f508eca | 4745 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
5f4f0e22 | 4746 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 4747 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e869aa39 | 4748 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) |
230d793d RS |
4749 | && op1 == const0_rtx |
4750 | && mode == GET_MODE (op0) | |
5109d49f | 4751 | && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) |
230d793d | 4752 | { |
818b11b9 RK |
4753 | x = simplify_shift_const (NULL_RTX, ASHIFT, mode, |
4754 | expand_compound_operation (op0), | |
230d793d RS |
4755 | GET_MODE_BITSIZE (mode) - 1 - i); |
4756 | if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) | |
4757 | return XEXP (x, 0); | |
4758 | else | |
4759 | return x; | |
4760 | } | |
4761 | ||
4762 | /* If the code changed, return a whole new comparison. */ | |
4763 | if (new_code != code) | |
f1c6ba8b | 4764 | return gen_rtx_fmt_ee (new_code, mode, op0, op1); |
230d793d | 4765 | |
663522cb | 4766 | /* Otherwise, keep this operation, but maybe change its operands. |
230d793d RS |
4767 | This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ |
4768 | SUBST (XEXP (x, 0), op0); | |
4769 | SUBST (XEXP (x, 1), op1); | |
4770 | } | |
4771 | break; | |
663522cb | 4772 | |
230d793d | 4773 | case IF_THEN_ELSE: |
8079805d | 4774 | return simplify_if_then_else (x); |
9210df58 | 4775 | |
8079805d RK |
4776 | case ZERO_EXTRACT: |
4777 | case SIGN_EXTRACT: | |
4778 | case ZERO_EXTEND: | |
4779 | case SIGN_EXTEND: | |
0f41302f | 4780 | /* If we are processing SET_DEST, we are done. */ |
8079805d RK |
4781 | if (in_dest) |
4782 | return x; | |
d0ab8cd3 | 4783 | |
8079805d | 4784 | return expand_compound_operation (x); |
d0ab8cd3 | 4785 | |
8079805d RK |
4786 | case SET: |
4787 | return simplify_set (x); | |
1a26b032 | 4788 | |
8079805d RK |
4789 | case AND: |
4790 | case IOR: | |
4791 | case XOR: | |
6621d78e | 4792 | return simplify_logical (x); |
d0ab8cd3 | 4793 | |
663522cb | 4794 | case ABS: |
8079805d RK |
4795 | /* (abs (neg <foo>)) -> (abs <foo>) */ |
4796 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
4797 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
1a26b032 | 4798 | |
b472527b JL |
4799 | /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), |
4800 | do nothing. */ | |
4801 | if (GET_MODE (XEXP (x, 0)) == VOIDmode) | |
4802 | break; | |
f40421ce | 4803 | |
8079805d RK |
4804 | /* If operand is something known to be positive, ignore the ABS. */ |
4805 | if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS | |
4806 | || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
4807 | <= HOST_BITS_PER_WIDE_INT) | |
4808 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
4809 | & ((HOST_WIDE_INT) 1 | |
4810 | << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) | |
4811 | == 0))) | |
4812 | return XEXP (x, 0); | |
1a26b032 | 4813 | |
8079805d RK |
4814 | /* If operand is known to be only -1 or 0, convert ABS to NEG. */ |
4815 | if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) | |
f1c6ba8b | 4816 | return gen_rtx_NEG (mode, XEXP (x, 0)); |
1a26b032 | 4817 | |
8079805d | 4818 | break; |
1a26b032 | 4819 | |
8079805d RK |
4820 | case FFS: |
4821 | /* (ffs (*_extend <X>)) = (ffs <X>) */ | |
4822 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4823 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4824 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4825 | break; | |
1a26b032 | 4826 | |
2928cd7a RH |
4827 | case POPCOUNT: |
4828 | case PARITY: | |
4829 | /* (pop* (zero_extend <X>)) = (pop* <X>) */ | |
4830 | if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4831 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4832 | break; | |
4833 | ||
8079805d RK |
4834 | case FLOAT: |
4835 | /* (float (sign_extend <X>)) = (float <X>). */ | |
4836 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
4837 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4838 | break; | |
1a26b032 | 4839 | |
8079805d RK |
4840 | case ASHIFT: |
4841 | case LSHIFTRT: | |
4842 | case ASHIFTRT: | |
4843 | case ROTATE: | |
4844 | case ROTATERT: | |
4845 | /* If this is a shift by a constant amount, simplify it. */ | |
4846 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
663522cb | 4847 | return simplify_shift_const (x, code, mode, XEXP (x, 0), |
8079805d RK |
4848 | INTVAL (XEXP (x, 1))); |
4849 | ||
f8cfc6aa | 4850 | else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) |
8079805d | 4851 | SUBST (XEXP (x, 1), |
f1b1186f | 4852 | force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), |
663522cb | 4853 | ((HOST_WIDE_INT) 1 |
8079805d RK |
4854 | << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) |
4855 | - 1, | |
4856 | NULL_RTX, 0)); | |
8079805d | 4857 | break; |
e9a25f70 | 4858 | |
82be40f7 BS |
4859 | case VEC_SELECT: |
4860 | { | |
4861 | rtx op0 = XEXP (x, 0); | |
4862 | rtx op1 = XEXP (x, 1); | |
4863 | int len; | |
4864 | ||
341c100f | 4865 | gcc_assert (GET_CODE (op1) == PARALLEL); |
82be40f7 BS |
4866 | len = XVECLEN (op1, 0); |
4867 | if (len == 1 | |
4868 | && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT | |
4869 | && GET_CODE (op0) == VEC_CONCAT) | |
4870 | { | |
4871 | int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x)); | |
4872 | ||
4873 | /* Try to find the element in the VEC_CONCAT. */ | |
4874 | for (;;) | |
4875 | { | |
4876 | if (GET_MODE (op0) == GET_MODE (x)) | |
4877 | return op0; | |
4878 | if (GET_CODE (op0) == VEC_CONCAT) | |
4879 | { | |
4880 | HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))); | |
125886c7 | 4881 | if (offset < op0_size) |
82be40f7 BS |
4882 | op0 = XEXP (op0, 0); |
4883 | else | |
4884 | { | |
4885 | offset -= op0_size; | |
4886 | op0 = XEXP (op0, 1); | |
4887 | } | |
4888 | } | |
4889 | else | |
4890 | break; | |
4891 | } | |
4892 | } | |
4893 | } | |
4894 | ||
4895 | break; | |
23190837 | 4896 | |
e9a25f70 JL |
4897 | default: |
4898 | break; | |
8079805d RK |
4899 | } |
4900 | ||
4901 | return x; | |
4902 | } | |
4903 | \f | |
4904 | /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ | |
5109d49f | 4905 | |
8079805d | 4906 | static rtx |
79a490a9 | 4907 | simplify_if_then_else (rtx x) |
8079805d RK |
4908 | { |
4909 | enum machine_mode mode = GET_MODE (x); | |
4910 | rtx cond = XEXP (x, 0); | |
d6edb99e ZW |
4911 | rtx true_rtx = XEXP (x, 1); |
4912 | rtx false_rtx = XEXP (x, 2); | |
8079805d | 4913 | enum rtx_code true_code = GET_CODE (cond); |
ec8e098d | 4914 | int comparison_p = COMPARISON_P (cond); |
8079805d RK |
4915 | rtx temp; |
4916 | int i; | |
9a915772 JH |
4917 | enum rtx_code false_code; |
4918 | rtx reversed; | |
8079805d | 4919 | |
0f41302f | 4920 | /* Simplify storing of the truth value. */ |
d6edb99e | 4921 | if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) |
bcb34aa3 PB |
4922 | return simplify_gen_relational (true_code, mode, VOIDmode, |
4923 | XEXP (cond, 0), XEXP (cond, 1)); | |
663522cb | 4924 | |
0f41302f | 4925 | /* Also when the truth value has to be reversed. */ |
9a915772 | 4926 | if (comparison_p |
d6edb99e | 4927 | && true_rtx == const0_rtx && false_rtx == const_true_rtx |
14f02e73 | 4928 | && (reversed = reversed_comparison (cond, mode))) |
9a915772 | 4929 | return reversed; |
8079805d RK |
4930 | |
4931 | /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used | |
4932 | in it is being compared against certain values. Get the true and false | |
4933 | comparisons and see if that says anything about the value of each arm. */ | |
4934 | ||
9a915772 | 4935 | if (comparison_p |
14f02e73 | 4936 | && ((false_code = reversed_comparison_code (cond, NULL)) |
9a915772 | 4937 | != UNKNOWN) |
f8cfc6aa | 4938 | && REG_P (XEXP (cond, 0))) |
8079805d RK |
4939 | { |
4940 | HOST_WIDE_INT nzb; | |
4941 | rtx from = XEXP (cond, 0); | |
8079805d RK |
4942 | rtx true_val = XEXP (cond, 1); |
4943 | rtx false_val = true_val; | |
4944 | int swapped = 0; | |
9210df58 | 4945 | |
8079805d | 4946 | /* If FALSE_CODE is EQ, swap the codes and arms. */ |
5109d49f | 4947 | |
8079805d | 4948 | if (false_code == EQ) |
1a26b032 | 4949 | { |
8079805d | 4950 | swapped = 1, true_code = EQ, false_code = NE; |
d6edb99e | 4951 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
8079805d | 4952 | } |
5109d49f | 4953 | |
8079805d RK |
4954 | /* If we are comparing against zero and the expression being tested has |
4955 | only a single bit that might be nonzero, that is its value when it is | |
4956 | not equal to zero. Similarly if it is known to be -1 or 0. */ | |
4957 | ||
4958 | if (true_code == EQ && true_val == const0_rtx | |
4959 | && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) | |
4960 | false_code = EQ, false_val = GEN_INT (nzb); | |
4961 | else if (true_code == EQ && true_val == const0_rtx | |
4962 | && (num_sign_bit_copies (from, GET_MODE (from)) | |
4963 | == GET_MODE_BITSIZE (GET_MODE (from)))) | |
4964 | false_code = EQ, false_val = constm1_rtx; | |
4965 | ||
4966 | /* Now simplify an arm if we know the value of the register in the | |
4967 | branch and it is used in the arm. Be careful due to the potential | |
4968 | of locally-shared RTL. */ | |
4969 | ||
d6edb99e ZW |
4970 | if (reg_mentioned_p (from, true_rtx)) |
4971 | true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | |
4972 | from, true_val), | |
8079805d | 4973 | pc_rtx, pc_rtx, 0, 0); |
d6edb99e ZW |
4974 | if (reg_mentioned_p (from, false_rtx)) |
4975 | false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | |
8079805d RK |
4976 | from, false_val), |
4977 | pc_rtx, pc_rtx, 0, 0); | |
4978 | ||
d6edb99e ZW |
4979 | SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); |
4980 | SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | |
8079805d | 4981 | |
d6edb99e ZW |
4982 | true_rtx = XEXP (x, 1); |
4983 | false_rtx = XEXP (x, 2); | |
4984 | true_code = GET_CODE (cond); | |
8079805d | 4985 | } |
5109d49f | 4986 | |
8079805d RK |
4987 | /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be |
4988 | reversed, do so to avoid needing two sets of patterns for | |
4989 | subtract-and-branch insns. Similarly if we have a constant in the true | |
4990 | arm, the false arm is the same as the first operand of the comparison, or | |
4991 | the false arm is more complicated than the true arm. */ | |
4992 | ||
9a915772 | 4993 | if (comparison_p |
14f02e73 | 4994 | && reversed_comparison_code (cond, NULL) != UNKNOWN |
d6edb99e ZW |
4995 | && (true_rtx == pc_rtx |
4996 | || (CONSTANT_P (true_rtx) | |
4997 | && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) | |
4998 | || true_rtx == const0_rtx | |
ec8e098d PB |
4999 | || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) |
5000 | || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) | |
5001 | && !OBJECT_P (false_rtx)) | |
d6edb99e ZW |
5002 | || reg_mentioned_p (true_rtx, false_rtx) |
5003 | || rtx_equal_p (false_rtx, XEXP (cond, 0)))) | |
8079805d | 5004 | { |
9a915772 | 5005 | true_code = reversed_comparison_code (cond, NULL); |
14f02e73 | 5006 | SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); |
d6edb99e ZW |
5007 | SUBST (XEXP (x, 1), false_rtx); |
5008 | SUBST (XEXP (x, 2), true_rtx); | |
1a26b032 | 5009 | |
d6edb99e ZW |
5010 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
5011 | cond = XEXP (x, 0); | |
bb821298 | 5012 | |
0f41302f | 5013 | /* It is possible that the conditional has been simplified out. */ |
bb821298 | 5014 | true_code = GET_CODE (cond); |
ec8e098d | 5015 | comparison_p = COMPARISON_P (cond); |
8079805d | 5016 | } |
abe6e52f | 5017 | |
8079805d | 5018 | /* If the two arms are identical, we don't need the comparison. */ |
1a26b032 | 5019 | |
d6edb99e ZW |
5020 | if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) |
5021 | return true_rtx; | |
1a26b032 | 5022 | |
5be669c7 RK |
5023 | /* Convert a == b ? b : a to "a". */ |
5024 | if (true_code == EQ && ! side_effects_p (cond) | |
73e42cf3 | 5025 | && !HONOR_NANS (mode) |
d6edb99e ZW |
5026 | && rtx_equal_p (XEXP (cond, 0), false_rtx) |
5027 | && rtx_equal_p (XEXP (cond, 1), true_rtx)) | |
5028 | return false_rtx; | |
5be669c7 | 5029 | else if (true_code == NE && ! side_effects_p (cond) |
73e42cf3 | 5030 | && !HONOR_NANS (mode) |
d6edb99e ZW |
5031 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
5032 | && rtx_equal_p (XEXP (cond, 1), false_rtx)) | |
5033 | return true_rtx; | |
5be669c7 | 5034 | |
8079805d RK |
5035 | /* Look for cases where we have (abs x) or (neg (abs X)). */ |
5036 | ||
5037 | if (GET_MODE_CLASS (mode) == MODE_INT | |
d6edb99e ZW |
5038 | && GET_CODE (false_rtx) == NEG |
5039 | && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) | |
8079805d | 5040 | && comparison_p |
d6edb99e ZW |
5041 | && rtx_equal_p (true_rtx, XEXP (cond, 0)) |
5042 | && ! side_effects_p (true_rtx)) | |
8079805d RK |
5043 | switch (true_code) |
5044 | { | |
5045 | case GT: | |
5046 | case GE: | |
f1c6ba8b | 5047 | return simplify_gen_unary (ABS, mode, true_rtx, mode); |
8079805d RK |
5048 | case LT: |
5049 | case LE: | |
f1c6ba8b RK |
5050 | return |
5051 | simplify_gen_unary (NEG, mode, | |
5052 | simplify_gen_unary (ABS, mode, true_rtx, mode), | |
5053 | mode); | |
cf0d9408 KH |
5054 | default: |
5055 | break; | |
8079805d RK |
5056 | } |
5057 | ||
5058 | /* Look for MIN or MAX. */ | |
5059 | ||
de6c5979 | 5060 | if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) |
8079805d | 5061 | && comparison_p |
d6edb99e ZW |
5062 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
5063 | && rtx_equal_p (XEXP (cond, 1), false_rtx) | |
8079805d RK |
5064 | && ! side_effects_p (cond)) |
5065 | switch (true_code) | |
5066 | { | |
5067 | case GE: | |
5068 | case GT: | |
bcb34aa3 | 5069 | return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); |
8079805d RK |
5070 | case LE: |
5071 | case LT: | |
bcb34aa3 | 5072 | return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); |
8079805d RK |
5073 | case GEU: |
5074 | case GTU: | |
bcb34aa3 | 5075 | return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); |
8079805d RK |
5076 | case LEU: |
5077 | case LTU: | |
bcb34aa3 | 5078 | return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); |
e9a25f70 JL |
5079 | default: |
5080 | break; | |
8079805d | 5081 | } |
663522cb | 5082 | |
8079805d RK |
5083 | /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its |
5084 | second operand is zero, this can be done as (OP Z (mult COND C2)) where | |
5085 | C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or | |
5086 | SIGN_EXTEND as long as Z is already extended (so we don't destroy it). | |
5087 | We can do this kind of thing in some cases when STORE_FLAG_VALUE is | |
0802d516 | 5088 | neither 1 or -1, but it isn't worth checking for. */ |
8079805d | 5089 | |
0802d516 | 5090 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
02484af9 EB |
5091 | && comparison_p |
5092 | && GET_MODE_CLASS (mode) == MODE_INT | |
5093 | && ! side_effects_p (x)) | |
8079805d | 5094 | { |
d6edb99e ZW |
5095 | rtx t = make_compound_operation (true_rtx, SET); |
5096 | rtx f = make_compound_operation (false_rtx, SET); | |
8079805d RK |
5097 | rtx cond_op0 = XEXP (cond, 0); |
5098 | rtx cond_op1 = XEXP (cond, 1); | |
f822d252 | 5099 | enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; |
8079805d | 5100 | enum machine_mode m = mode; |
6a651371 | 5101 | rtx z = 0, c1 = NULL_RTX; |
8079805d | 5102 | |
8079805d RK |
5103 | if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS |
5104 | || GET_CODE (t) == IOR || GET_CODE (t) == XOR | |
5105 | || GET_CODE (t) == ASHIFT | |
5106 | || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) | |
5107 | && rtx_equal_p (XEXP (t, 0), f)) | |
5108 | c1 = XEXP (t, 1), op = GET_CODE (t), z = f; | |
5109 | ||
5110 | /* If an identity-zero op is commutative, check whether there | |
0f41302f | 5111 | would be a match if we swapped the operands. */ |
8079805d RK |
5112 | else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR |
5113 | || GET_CODE (t) == XOR) | |
5114 | && rtx_equal_p (XEXP (t, 1), f)) | |
5115 | c1 = XEXP (t, 0), op = GET_CODE (t), z = f; | |
5116 | else if (GET_CODE (t) == SIGN_EXTEND | |
5117 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5118 | || GET_CODE (XEXP (t, 0)) == MINUS | |
5119 | || GET_CODE (XEXP (t, 0)) == IOR | |
5120 | || GET_CODE (XEXP (t, 0)) == XOR | |
5121 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
5122 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
5123 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
5124 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
5125 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
5126 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
5127 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
5128 | > (unsigned int) |
5129 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
5130 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) |
5131 | { | |
5132 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
5133 | extend_op = SIGN_EXTEND; | |
5134 | m = GET_MODE (XEXP (t, 0)); | |
1a26b032 | 5135 | } |
8079805d RK |
5136 | else if (GET_CODE (t) == SIGN_EXTEND |
5137 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5138 | || GET_CODE (XEXP (t, 0)) == IOR | |
5139 | || GET_CODE (XEXP (t, 0)) == XOR) | |
5140 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5141 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5142 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5143 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
5144 | > (unsigned int) |
5145 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
5146 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) |
5147 | { | |
5148 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5149 | extend_op = SIGN_EXTEND; | |
5150 | m = GET_MODE (XEXP (t, 0)); | |
5151 | } | |
5152 | else if (GET_CODE (t) == ZERO_EXTEND | |
5153 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5154 | || GET_CODE (XEXP (t, 0)) == MINUS | |
5155 | || GET_CODE (XEXP (t, 0)) == IOR | |
5156 | || GET_CODE (XEXP (t, 0)) == XOR | |
5157 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
5158 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
5159 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
5160 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
5161 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5162 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
5163 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
5164 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 5165 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) |
8079805d RK |
5166 | == 0)) |
5167 | { | |
5168 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
5169 | extend_op = ZERO_EXTEND; | |
5170 | m = GET_MODE (XEXP (t, 0)); | |
5171 | } | |
5172 | else if (GET_CODE (t) == ZERO_EXTEND | |
5173 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5174 | || GET_CODE (XEXP (t, 0)) == IOR | |
5175 | || GET_CODE (XEXP (t, 0)) == XOR) | |
5176 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5177 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5178 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5179 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5180 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 5181 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) |
8079805d RK |
5182 | == 0)) |
5183 | { | |
5184 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5185 | extend_op = ZERO_EXTEND; | |
5186 | m = GET_MODE (XEXP (t, 0)); | |
5187 | } | |
663522cb | 5188 | |
8079805d RK |
5189 | if (z) |
5190 | { | |
bcb34aa3 PB |
5191 | temp = subst (simplify_gen_relational (true_code, m, VOIDmode, |
5192 | cond_op0, cond_op1), | |
8079805d | 5193 | pc_rtx, pc_rtx, 0, 0); |
bcb34aa3 PB |
5194 | temp = simplify_gen_binary (MULT, m, temp, |
5195 | simplify_gen_binary (MULT, m, c1, | |
5196 | const_true_rtx)); | |
8079805d | 5197 | temp = subst (temp, pc_rtx, pc_rtx, 0, 0); |
bcb34aa3 | 5198 | temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); |
8079805d | 5199 | |
f822d252 | 5200 | if (extend_op != UNKNOWN) |
f1c6ba8b | 5201 | temp = simplify_gen_unary (extend_op, mode, temp, m); |
8079805d RK |
5202 | |
5203 | return temp; | |
5204 | } | |
5205 | } | |
224eeff2 | 5206 | |
8079805d RK |
5207 | /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or |
5208 | 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the | |
5209 | negation of a single bit, we can convert this operation to a shift. We | |
5210 | can actually do this more generally, but it doesn't seem worth it. */ | |
5211 | ||
5212 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
d6edb99e | 5213 | && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT |
8079805d | 5214 | && ((1 == nonzero_bits (XEXP (cond, 0), mode) |
d6edb99e | 5215 | && (i = exact_log2 (INTVAL (true_rtx))) >= 0) |
8079805d RK |
5216 | || ((num_sign_bit_copies (XEXP (cond, 0), mode) |
5217 | == GET_MODE_BITSIZE (mode)) | |
d6edb99e | 5218 | && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) |
8079805d RK |
5219 | return |
5220 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4de249d9 | 5221 | gen_lowpart (mode, XEXP (cond, 0)), i); |
230d793d | 5222 | |
83588a9d JH |
5223 | /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ |
5224 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
5225 | && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT | |
db33236e | 5226 | && GET_MODE (XEXP (cond, 0)) == mode |
83588a9d JH |
5227 | && (INTVAL (true_rtx) & GET_MODE_MASK (mode)) |
5228 | == nonzero_bits (XEXP (cond, 0), mode) | |
5229 | && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) | |
5230 | return XEXP (cond, 0); | |
5231 | ||
8079805d RK |
5232 | return x; |
5233 | } | |
5234 | \f | |
5235 | /* Simplify X, a SET expression. Return the new expression. */ | |
230d793d | 5236 | |
8079805d | 5237 | static rtx |
79a490a9 | 5238 | simplify_set (rtx x) |
8079805d RK |
5239 | { |
5240 | rtx src = SET_SRC (x); | |
5241 | rtx dest = SET_DEST (x); | |
5242 | enum machine_mode mode | |
5243 | = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); | |
5244 | rtx other_insn; | |
5245 | rtx *cc_use; | |
5246 | ||
5247 | /* (set (pc) (return)) gets written as (return). */ | |
5248 | if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) | |
5249 | return src; | |
230d793d | 5250 | |
87e3e0c1 RK |
5251 | /* Now that we know for sure which bits of SRC we are using, see if we can |
5252 | simplify the expression for the object knowing that we only need the | |
5253 | low-order bits. */ | |
5254 | ||
855c3a2e IS |
5255 | if (GET_MODE_CLASS (mode) == MODE_INT |
5256 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
c5c76735 | 5257 | { |
e8dc6d50 | 5258 | src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0); |
c5c76735 JL |
5259 | SUBST (SET_SRC (x), src); |
5260 | } | |
87e3e0c1 | 5261 | |
8079805d RK |
5262 | /* If we are setting CC0 or if the source is a COMPARE, look for the use of |
5263 | the comparison result and try to simplify it unless we already have used | |
5264 | undobuf.other_insn. */ | |
dbf4f1a2 RS |
5265 | if ((GET_MODE_CLASS (mode) == MODE_CC |
5266 | || GET_CODE (src) == COMPARE | |
5267 | || CC0_P (dest)) | |
8079805d RK |
5268 | && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 |
5269 | && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
ec8e098d | 5270 | && COMPARISON_P (*cc_use) |
c0d3ac4d | 5271 | && rtx_equal_p (XEXP (*cc_use, 0), dest)) |
8079805d RK |
5272 | { |
5273 | enum rtx_code old_code = GET_CODE (*cc_use); | |
5274 | enum rtx_code new_code; | |
f40f4c8e | 5275 | rtx op0, op1, tmp; |
8079805d RK |
5276 | int other_changed = 0; |
5277 | enum machine_mode compare_mode = GET_MODE (dest); | |
5278 | ||
5279 | if (GET_CODE (src) == COMPARE) | |
5280 | op0 = XEXP (src, 0), op1 = XEXP (src, 1); | |
5281 | else | |
8abcb0f7 | 5282 | op0 = src, op1 = CONST0_RTX (GET_MODE (src)); |
230d793d | 5283 | |
c6fb08ad PB |
5284 | tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, |
5285 | op0, op1); | |
5286 | if (!tmp) | |
5287 | new_code = old_code; | |
5288 | else if (!CONSTANT_P (tmp)) | |
5289 | { | |
5290 | new_code = GET_CODE (tmp); | |
5291 | op0 = XEXP (tmp, 0); | |
5292 | op1 = XEXP (tmp, 1); | |
5293 | } | |
f40f4c8e | 5294 | else |
f40f4c8e RS |
5295 | { |
5296 | rtx pat = PATTERN (other_insn); | |
5297 | undobuf.other_insn = other_insn; | |
5298 | SUBST (*cc_use, tmp); | |
5299 | ||
5300 | /* Attempt to simplify CC user. */ | |
5301 | if (GET_CODE (pat) == SET) | |
5302 | { | |
5303 | rtx new = simplify_rtx (SET_SRC (pat)); | |
5304 | if (new != NULL_RTX) | |
5305 | SUBST (SET_SRC (pat), new); | |
5306 | } | |
5307 | ||
5308 | /* Convert X into a no-op move. */ | |
5309 | SUBST (SET_DEST (x), pc_rtx); | |
5310 | SUBST (SET_SRC (x), pc_rtx); | |
5311 | return x; | |
5312 | } | |
5313 | ||
8079805d | 5314 | /* Simplify our comparison, if possible. */ |
c6fb08ad | 5315 | new_code = simplify_comparison (new_code, &op0, &op1); |
230d793d | 5316 | |
94134f42 | 5317 | #ifdef SELECT_CC_MODE |
8079805d RK |
5318 | /* If this machine has CC modes other than CCmode, check to see if we |
5319 | need to use a different CC mode here. */ | |
c6fb08ad PB |
5320 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
5321 | compare_mode = GET_MODE (op0); | |
5322 | else | |
5323 | compare_mode = SELECT_CC_MODE (new_code, op0, op1); | |
230d793d | 5324 | |
94134f42 | 5325 | #ifndef HAVE_cc0 |
8079805d RK |
5326 | /* If the mode changed, we have to change SET_DEST, the mode in the |
5327 | compare, and the mode in the place SET_DEST is used. If SET_DEST is | |
5328 | a hard register, just build new versions with the proper mode. If it | |
5329 | is a pseudo, we lose unless it is only time we set the pseudo, in | |
5330 | which case we can safely change its mode. */ | |
5331 | if (compare_mode != GET_MODE (dest)) | |
5332 | { | |
4164b2fb | 5333 | if (can_change_dest_mode (dest, 0, compare_mode)) |
230d793d | 5334 | { |
4164b2fb PB |
5335 | unsigned int regno = REGNO (dest); |
5336 | rtx new_dest = gen_rtx_REG (compare_mode, regno); | |
5337 | ||
8079805d RK |
5338 | if (regno >= FIRST_PSEUDO_REGISTER) |
5339 | SUBST (regno_reg_rtx[regno], new_dest); | |
230d793d | 5340 | |
8079805d RK |
5341 | SUBST (SET_DEST (x), new_dest); |
5342 | SUBST (XEXP (*cc_use, 0), new_dest); | |
5343 | other_changed = 1; | |
230d793d | 5344 | |
8079805d | 5345 | dest = new_dest; |
230d793d | 5346 | } |
8079805d | 5347 | } |
94134f42 ZW |
5348 | #endif /* cc0 */ |
5349 | #endif /* SELECT_CC_MODE */ | |
230d793d | 5350 | |
8079805d RK |
5351 | /* If the code changed, we have to build a new comparison in |
5352 | undobuf.other_insn. */ | |
5353 | if (new_code != old_code) | |
5354 | { | |
2051c897 | 5355 | int other_changed_previously = other_changed; |
8079805d RK |
5356 | unsigned HOST_WIDE_INT mask; |
5357 | ||
f1c6ba8b RK |
5358 | SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), |
5359 | dest, const0_rtx)); | |
2051c897 | 5360 | other_changed = 1; |
8079805d RK |
5361 | |
5362 | /* If the only change we made was to change an EQ into an NE or | |
5363 | vice versa, OP0 has only one bit that might be nonzero, and OP1 | |
5364 | is zero, check if changing the user of the condition code will | |
5365 | produce a valid insn. If it won't, we can keep the original code | |
5366 | in that insn by surrounding our operation with an XOR. */ | |
5367 | ||
5368 | if (((old_code == NE && new_code == EQ) | |
5369 | || (old_code == EQ && new_code == NE)) | |
2051c897 | 5370 | && ! other_changed_previously && op1 == const0_rtx |
8079805d RK |
5371 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT |
5372 | && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) | |
230d793d | 5373 | { |
8079805d | 5374 | rtx pat = PATTERN (other_insn), note = 0; |
230d793d | 5375 | |
8e2f6e35 | 5376 | if ((recog_for_combine (&pat, other_insn, ¬e) < 0 |
8079805d RK |
5377 | && ! check_asm_operands (pat))) |
5378 | { | |
5379 | PUT_CODE (*cc_use, old_code); | |
2051c897 | 5380 | other_changed = 0; |
230d793d | 5381 | |
bcb34aa3 PB |
5382 | op0 = simplify_gen_binary (XOR, GET_MODE (op0), |
5383 | op0, GEN_INT (mask)); | |
230d793d | 5384 | } |
230d793d | 5385 | } |
8079805d RK |
5386 | } |
5387 | ||
5388 | if (other_changed) | |
5389 | undobuf.other_insn = other_insn; | |
230d793d RS |
5390 | |
5391 | #ifdef HAVE_cc0 | |
8079805d RK |
5392 | /* If we are now comparing against zero, change our source if |
5393 | needed. If we do not use cc0, we always have a COMPARE. */ | |
5394 | if (op1 == const0_rtx && dest == cc0_rtx) | |
5395 | { | |
5396 | SUBST (SET_SRC (x), op0); | |
5397 | src = op0; | |
5398 | } | |
5399 | else | |
230d793d RS |
5400 | #endif |
5401 | ||
8079805d RK |
5402 | /* Otherwise, if we didn't previously have a COMPARE in the |
5403 | correct mode, we need one. */ | |
5404 | if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) | |
5405 | { | |
f1c6ba8b | 5406 | SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); |
8079805d | 5407 | src = SET_SRC (x); |
230d793d | 5408 | } |
8c98e9d0 FJ |
5409 | else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx) |
5410 | { | |
5411 | SUBST(SET_SRC (x), op0); | |
5412 | src = SET_SRC (x); | |
5413 | } | |
230d793d RS |
5414 | else |
5415 | { | |
8079805d RK |
5416 | /* Otherwise, update the COMPARE if needed. */ |
5417 | SUBST (XEXP (src, 0), op0); | |
5418 | SUBST (XEXP (src, 1), op1); | |
230d793d | 5419 | } |
8079805d RK |
5420 | } |
5421 | else | |
5422 | { | |
5423 | /* Get SET_SRC in a form where we have placed back any | |
5424 | compound expressions. Then do the checks below. */ | |
5425 | src = make_compound_operation (src, SET); | |
5426 | SUBST (SET_SRC (x), src); | |
5427 | } | |
230d793d | 5428 | |
8079805d RK |
5429 | /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, |
5430 | and X being a REG or (subreg (reg)), we may be able to convert this to | |
663522cb | 5431 | (set (subreg:m2 x) (op)). |
df62f951 | 5432 | |
5c881655 KH |
5433 | We can always do this if M1 is narrower than M2 because that means that |
5434 | we only care about the low bits of the result. | |
df62f951 | 5435 | |
5c881655 KH |
5436 | However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot |
5437 | perform a narrower operation than requested since the high-order bits will | |
5438 | be undefined. On machine where it is defined, this transformation is safe | |
5439 | as long as M1 and M2 have the same number of words. */ | |
663522cb | 5440 | |
8079805d | 5441 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) |
ec8e098d | 5442 | && !OBJECT_P (SUBREG_REG (src)) |
8079805d RK |
5443 | && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) |
5444 | / UNITS_PER_WORD) | |
5445 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) | |
5446 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
5c881655 KH |
5447 | #ifndef WORD_REGISTER_OPERATIONS |
5448 | && (GET_MODE_SIZE (GET_MODE (src)) | |
5449 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
5450 | #endif | |
cff9f8d5 | 5451 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 5452 | && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER |
cff9f8d5 | 5453 | && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), |
73a39fc4 | 5454 | GET_MODE (SUBREG_REG (src)), |
b0c42aed | 5455 | GET_MODE (src))) |
663522cb | 5456 | #endif |
f8cfc6aa | 5457 | && (REG_P (dest) |
8079805d | 5458 | || (GET_CODE (dest) == SUBREG |
f8cfc6aa | 5459 | && REG_P (SUBREG_REG (dest))))) |
8079805d RK |
5460 | { |
5461 | SUBST (SET_DEST (x), | |
4de249d9 | 5462 | gen_lowpart (GET_MODE (SUBREG_REG (src)), |
8079805d RK |
5463 | dest)); |
5464 | SUBST (SET_SRC (x), SUBREG_REG (src)); | |
5465 | ||
5466 | src = SET_SRC (x), dest = SET_DEST (x); | |
5467 | } | |
df62f951 | 5468 | |
8c1d52a3 KH |
5469 | #ifdef HAVE_cc0 |
5470 | /* If we have (set (cc0) (subreg ...)), we try to remove the subreg | |
5471 | in SRC. */ | |
5472 | if (dest == cc0_rtx | |
5473 | && GET_CODE (src) == SUBREG | |
5474 | && subreg_lowpart_p (src) | |
5475 | && (GET_MODE_BITSIZE (GET_MODE (src)) | |
5476 | < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src))))) | |
5477 | { | |
5478 | rtx inner = SUBREG_REG (src); | |
5479 | enum machine_mode inner_mode = GET_MODE (inner); | |
5480 | ||
5481 | /* Here we make sure that we don't have a sign bit on. */ | |
5482 | if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT | |
5483 | && (nonzero_bits (inner, inner_mode) | |
5484 | < ((unsigned HOST_WIDE_INT) 1 | |
ff076520 | 5485 | << (GET_MODE_BITSIZE (GET_MODE (src)) - 1)))) |
8c1d52a3 KH |
5486 | { |
5487 | SUBST (SET_SRC (x), inner); | |
5488 | src = SET_SRC (x); | |
5489 | } | |
5490 | } | |
5491 | #endif | |
5492 | ||
8baf60bb | 5493 | #ifdef LOAD_EXTEND_OP |
8079805d RK |
5494 | /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this |
5495 | would require a paradoxical subreg. Replace the subreg with a | |
0f41302f | 5496 | zero_extend to avoid the reload that would otherwise be required. */ |
8079805d RK |
5497 | |
5498 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
f822d252 | 5499 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN |
ddef6bc7 | 5500 | && SUBREG_BYTE (src) == 0 |
8079805d RK |
5501 | && (GET_MODE_SIZE (GET_MODE (src)) |
5502 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
3c0cb5de | 5503 | && MEM_P (SUBREG_REG (src))) |
8079805d RK |
5504 | { |
5505 | SUBST (SET_SRC (x), | |
2fb00d7f KH |
5506 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), |
5507 | GET_MODE (src), SUBREG_REG (src))); | |
8079805d RK |
5508 | |
5509 | src = SET_SRC (x); | |
5510 | } | |
230d793d RS |
5511 | #endif |
5512 | ||
8079805d RK |
5513 | /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we |
5514 | are comparing an item known to be 0 or -1 against 0, use a logical | |
5515 | operation instead. Check for one of the arms being an IOR of the other | |
5516 | arm with some value. We compute three terms to be IOR'ed together. In | |
5517 | practice, at most two will be nonzero. Then we do the IOR's. */ | |
5518 | ||
5519 | if (GET_CODE (dest) != PC | |
5520 | && GET_CODE (src) == IF_THEN_ELSE | |
36b8d792 | 5521 | && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT |
8079805d RK |
5522 | && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) |
5523 | && XEXP (XEXP (src, 0), 1) == const0_rtx | |
6dd49058 | 5524 | && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) |
ea414472 DE |
5525 | #ifdef HAVE_conditional_move |
5526 | && ! can_conditionally_move_p (GET_MODE (src)) | |
5527 | #endif | |
8079805d RK |
5528 | && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), |
5529 | GET_MODE (XEXP (XEXP (src, 0), 0))) | |
5530 | == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) | |
5531 | && ! side_effects_p (src)) | |
5532 | { | |
d6edb99e | 5533 | rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d | 5534 | ? XEXP (src, 1) : XEXP (src, 2)); |
d6edb99e | 5535 | rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d RK |
5536 | ? XEXP (src, 2) : XEXP (src, 1)); |
5537 | rtx term1 = const0_rtx, term2, term3; | |
5538 | ||
d6edb99e ZW |
5539 | if (GET_CODE (true_rtx) == IOR |
5540 | && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) | |
e869aa39 | 5541 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; |
d6edb99e ZW |
5542 | else if (GET_CODE (true_rtx) == IOR |
5543 | && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) | |
e869aa39 | 5544 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; |
d6edb99e ZW |
5545 | else if (GET_CODE (false_rtx) == IOR |
5546 | && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) | |
e869aa39 | 5547 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; |
d6edb99e ZW |
5548 | else if (GET_CODE (false_rtx) == IOR |
5549 | && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) | |
e869aa39 | 5550 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; |
d6edb99e | 5551 | |
bcb34aa3 PB |
5552 | term2 = simplify_gen_binary (AND, GET_MODE (src), |
5553 | XEXP (XEXP (src, 0), 0), true_rtx); | |
5554 | term3 = simplify_gen_binary (AND, GET_MODE (src), | |
5555 | simplify_gen_unary (NOT, GET_MODE (src), | |
5556 | XEXP (XEXP (src, 0), 0), | |
5557 | GET_MODE (src)), | |
5558 | false_rtx); | |
8079805d RK |
5559 | |
5560 | SUBST (SET_SRC (x), | |
bcb34aa3 PB |
5561 | simplify_gen_binary (IOR, GET_MODE (src), |
5562 | simplify_gen_binary (IOR, GET_MODE (src), | |
5563 | term1, term2), | |
5564 | term3)); | |
8079805d RK |
5565 | |
5566 | src = SET_SRC (x); | |
5567 | } | |
230d793d | 5568 | |
246e00f2 RK |
5569 | /* If either SRC or DEST is a CLOBBER of (const_int 0), make this |
5570 | whole thing fail. */ | |
5571 | if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) | |
5572 | return src; | |
5573 | else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) | |
5574 | return dest; | |
5575 | else | |
5576 | /* Convert this into a field assignment operation, if possible. */ | |
5577 | return make_field_assignment (x); | |
8079805d RK |
5578 | } |
5579 | \f | |
5580 | /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified | |
6621d78e | 5581 | result. */ |
8079805d RK |
5582 | |
5583 | static rtx | |
6621d78e | 5584 | simplify_logical (rtx x) |
8079805d RK |
5585 | { |
5586 | enum machine_mode mode = GET_MODE (x); | |
5587 | rtx op0 = XEXP (x, 0); | |
5588 | rtx op1 = XEXP (x, 1); | |
9a915772 | 5589 | rtx reversed; |
8079805d RK |
5590 | |
5591 | switch (GET_CODE (x)) | |
5592 | { | |
230d793d | 5593 | case AND: |
663522cb | 5594 | /* Convert (A ^ B) & A to A & (~B) since the latter is often a single |
8079805d RK |
5595 | insn (and may simplify more). */ |
5596 | if (GET_CODE (op0) == XOR | |
5597 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5598 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5599 | x = simplify_gen_binary (AND, mode, |
5600 | simplify_gen_unary (NOT, mode, | |
5601 | XEXP (op0, 1), mode), | |
5602 | op1); | |
8079805d RK |
5603 | |
5604 | if (GET_CODE (op0) == XOR | |
5605 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5606 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5607 | x = simplify_gen_binary (AND, mode, |
5608 | simplify_gen_unary (NOT, mode, | |
5609 | XEXP (op0, 0), mode), | |
5610 | op1); | |
8079805d | 5611 | |
663522cb | 5612 | /* Similarly for (~(A ^ B)) & A. */ |
8079805d RK |
5613 | if (GET_CODE (op0) == NOT |
5614 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5615 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) | |
5616 | && ! side_effects_p (op1)) | |
bcb34aa3 | 5617 | x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); |
8079805d RK |
5618 | |
5619 | if (GET_CODE (op0) == NOT | |
5620 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5621 | && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) | |
5622 | && ! side_effects_p (op1)) | |
bcb34aa3 | 5623 | x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); |
8079805d | 5624 | |
2e8f9abf DM |
5625 | /* We can call simplify_and_const_int only if we don't lose |
5626 | any (sign) bits when converting INTVAL (op1) to | |
5627 | "unsigned HOST_WIDE_INT". */ | |
5628 | if (GET_CODE (op1) == CONST_INT | |
5629 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5630 | || INTVAL (op1) > 0)) | |
230d793d | 5631 | { |
8079805d | 5632 | x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); |
230d793d RS |
5633 | |
5634 | /* If we have (ior (and (X C1) C2)) and the next restart would be | |
5635 | the last, simplify this by making C1 as small as possible | |
6621d78e PB |
5636 | and then exit. Only do this if C1 actually changes: for now |
5637 | this only saves memory but, should this transformation be | |
5638 | moved to simplify-rtx.c, we'd risk unbounded recursion there. */ | |
5639 | if (GET_CODE (x) == IOR && GET_CODE (op0) == AND | |
8079805d | 5640 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
6621d78e PB |
5641 | && GET_CODE (op1) == CONST_INT |
5642 | && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0) | |
bcb34aa3 PB |
5643 | return simplify_gen_binary (IOR, mode, |
5644 | simplify_gen_binary | |
5645 | (AND, mode, XEXP (op0, 0), | |
8079805d | 5646 | GEN_INT (INTVAL (XEXP (op0, 1)) |
663522cb | 5647 | & ~INTVAL (op1))), op1); |
230d793d RS |
5648 | |
5649 | if (GET_CODE (x) != AND) | |
8079805d | 5650 | return x; |
0e32506c | 5651 | |
ec8e098d PB |
5652 | op0 = XEXP (x, 0); |
5653 | op1 = XEXP (x, 1); | |
230d793d RS |
5654 | } |
5655 | ||
5656 | /* Convert (A | B) & A to A. */ | |
8079805d RK |
5657 | if (GET_CODE (op0) == IOR |
5658 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5659 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5660 | && ! side_effects_p (XEXP (op0, 0)) | |
5661 | && ! side_effects_p (XEXP (op0, 1))) | |
5662 | return op1; | |
230d793d | 5663 | |
bcb34aa3 PB |
5664 | /* If we have any of (and (ior A B) C) or (and (xor A B) C), |
5665 | apply the distributive law and then the inverse distributive | |
5666 | law to see if things simplify. */ | |
1999435c | 5667 | if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) |
230d793d | 5668 | { |
bcb34aa3 PB |
5669 | rtx result = distribute_and_simplify_rtx (x, 0); |
5670 | if (result) | |
5671 | return result; | |
230d793d | 5672 | } |
1999435c | 5673 | if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) |
bcb34aa3 PB |
5674 | { |
5675 | rtx result = distribute_and_simplify_rtx (x, 1); | |
5676 | if (result) | |
5677 | return result; | |
5678 | } | |
230d793d RS |
5679 | break; |
5680 | ||
5681 | case IOR: | |
951553af | 5682 | /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ |
8079805d | 5683 | if (GET_CODE (op1) == CONST_INT |
ac49a949 | 5684 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
663522cb | 5685 | && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) |
8079805d | 5686 | return op1; |
d0ab8cd3 | 5687 | |
230d793d | 5688 | /* Convert (A & B) | A to A. */ |
8079805d RK |
5689 | if (GET_CODE (op0) == AND |
5690 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5691 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5692 | && ! side_effects_p (XEXP (op0, 0)) | |
5693 | && ! side_effects_p (XEXP (op0, 1))) | |
5694 | return op1; | |
230d793d RS |
5695 | |
5696 | /* If we have (ior (and A B) C), apply the distributive law and then | |
5697 | the inverse distributive law to see if things simplify. */ | |
5698 | ||
1999435c PB |
5699 | if (GET_CODE (op0) == AND) |
5700 | { | |
bcb34aa3 PB |
5701 | rtx result = distribute_and_simplify_rtx (x, 0); |
5702 | if (result) | |
5703 | return result; | |
1999435c PB |
5704 | } |
5705 | ||
5706 | if (GET_CODE (op1) == AND) | |
230d793d | 5707 | { |
bcb34aa3 PB |
5708 | rtx result = distribute_and_simplify_rtx (x, 1); |
5709 | if (result) | |
5710 | return result; | |
230d793d RS |
5711 | } |
5712 | ||
5713 | /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the | |
5714 | mode size to (rotate A CX). */ | |
5715 | ||
8079805d RK |
5716 | if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) |
5717 | || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) | |
5718 | && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) | |
5719 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5720 | && GET_CODE (XEXP (op1, 1)) == CONST_INT | |
5721 | && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) | |
230d793d | 5722 | == GET_MODE_BITSIZE (mode))) |
38a448ca RH |
5723 | return gen_rtx_ROTATE (mode, XEXP (op0, 0), |
5724 | (GET_CODE (op0) == ASHIFT | |
5725 | ? XEXP (op0, 1) : XEXP (op1, 1))); | |
230d793d | 5726 | |
71923da7 RK |
5727 | /* If OP0 is (ashiftrt (plus ...) C), it might actually be |
5728 | a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS | |
5729 | does not affect any of the bits in OP1, it can really be done | |
5730 | as a PLUS and we can associate. We do this by seeing if OP1 | |
5731 | can be safely shifted left C bits. */ | |
5732 | if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT | |
5733 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
5734 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
5735 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5736 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) | |
5737 | { | |
5738 | int count = INTVAL (XEXP (op0, 1)); | |
5739 | HOST_WIDE_INT mask = INTVAL (op1) << count; | |
5740 | ||
5741 | if (mask >> count == INTVAL (op1) | |
5742 | && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) | |
5743 | { | |
5744 | SUBST (XEXP (XEXP (op0, 0), 1), | |
5745 | GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); | |
5746 | return op0; | |
5747 | } | |
5748 | } | |
230d793d RS |
5749 | break; |
5750 | ||
5751 | case XOR: | |
79e8185c JH |
5752 | /* If we are XORing two things that have no bits in common, |
5753 | convert them into an IOR. This helps to detect rotation encoded | |
5754 | using those methods and possibly other simplifications. */ | |
5755 | ||
5756 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5757 | && (nonzero_bits (op0, mode) | |
5758 | & nonzero_bits (op1, mode)) == 0) | |
bcb34aa3 | 5759 | return (simplify_gen_binary (IOR, mode, op0, op1)); |
79e8185c | 5760 | |
230d793d RS |
5761 | /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). |
5762 | Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for | |
5763 | (NOT y). */ | |
5764 | { | |
5765 | int num_negated = 0; | |
230d793d | 5766 | |
8079805d RK |
5767 | if (GET_CODE (op0) == NOT) |
5768 | num_negated++, op0 = XEXP (op0, 0); | |
5769 | if (GET_CODE (op1) == NOT) | |
5770 | num_negated++, op1 = XEXP (op1, 0); | |
230d793d RS |
5771 | |
5772 | if (num_negated == 2) | |
5773 | { | |
8079805d RK |
5774 | SUBST (XEXP (x, 0), op0); |
5775 | SUBST (XEXP (x, 1), op1); | |
230d793d RS |
5776 | } |
5777 | else if (num_negated == 1) | |
f1c6ba8b | 5778 | return |
bcb34aa3 PB |
5779 | simplify_gen_unary (NOT, mode, |
5780 | simplify_gen_binary (XOR, mode, op0, op1), | |
f1c6ba8b | 5781 | mode); |
230d793d RS |
5782 | } |
5783 | ||
5784 | /* Convert (xor (and A B) B) to (and (not A) B). The latter may | |
5785 | correspond to a machine insn or result in further simplifications | |
5786 | if B is a constant. */ | |
5787 | ||
8079805d RK |
5788 | if (GET_CODE (op0) == AND |
5789 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5790 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5791 | return simplify_gen_binary (AND, mode, |
5792 | simplify_gen_unary (NOT, mode, | |
5793 | XEXP (op0, 0), mode), | |
5794 | op1); | |
230d793d | 5795 | |
8079805d RK |
5796 | else if (GET_CODE (op0) == AND |
5797 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5798 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5799 | return simplify_gen_binary (AND, mode, |
5800 | simplify_gen_unary (NOT, mode, | |
5801 | XEXP (op0, 1), mode), | |
5802 | op1); | |
230d793d | 5803 | |
230d793d | 5804 | /* (xor (comparison foo bar) (const_int 1)) can become the reversed |
0802d516 RK |
5805 | comparison if STORE_FLAG_VALUE is 1. */ |
5806 | if (STORE_FLAG_VALUE == 1 | |
5807 | && op1 == const1_rtx | |
ec8e098d | 5808 | && COMPARISON_P (op0) |
14f02e73 | 5809 | && (reversed = reversed_comparison (op0, mode))) |
9a915772 | 5810 | return reversed; |
500c518b RK |
5811 | |
5812 | /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 | |
5813 | is (lt foo (const_int 0)), so we can perform the above | |
0802d516 | 5814 | simplification if STORE_FLAG_VALUE is 1. */ |
500c518b | 5815 | |
0802d516 RK |
5816 | if (STORE_FLAG_VALUE == 1 |
5817 | && op1 == const1_rtx | |
8079805d RK |
5818 | && GET_CODE (op0) == LSHIFTRT |
5819 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5820 | && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
f1c6ba8b | 5821 | return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); |
230d793d RS |
5822 | |
5823 | /* (xor (comparison foo bar) (const_int sign-bit)) | |
5824 | when STORE_FLAG_VALUE is the sign bit. */ | |
5f4f0e22 | 5825 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 5826 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e51712db | 5827 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) |
8079805d | 5828 | && op1 == const_true_rtx |
ec8e098d | 5829 | && COMPARISON_P (op0) |
14f02e73 | 5830 | && (reversed = reversed_comparison (op0, mode))) |
9a915772 | 5831 | return reversed; |
0918eca0 | 5832 | |
230d793d | 5833 | break; |
e9a25f70 JL |
5834 | |
5835 | default: | |
341c100f | 5836 | gcc_unreachable (); |
230d793d RS |
5837 | } |
5838 | ||
5839 | return x; | |
5840 | } | |
5841 | \f | |
5842 | /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
5843 | operations" because they can be replaced with two more basic operations. | |
5844 | ZERO_EXTEND is also considered "compound" because it can be replaced with | |
5845 | an AND operation, which is simpler, though only one operation. | |
5846 | ||
5847 | The function expand_compound_operation is called with an rtx expression | |
663522cb | 5848 | and will convert it to the appropriate shifts and AND operations, |
230d793d RS |
5849 | simplifying at each stage. |
5850 | ||
5851 | The function make_compound_operation is called to convert an expression | |
5852 | consisting of shifts and ANDs into the equivalent compound expression. | |
5853 | It is the inverse of this function, loosely speaking. */ | |
5854 | ||
5855 | static rtx | |
79a490a9 | 5856 | expand_compound_operation (rtx x) |
230d793d | 5857 | { |
770ae6cc | 5858 | unsigned HOST_WIDE_INT pos = 0, len; |
230d793d | 5859 | int unsignedp = 0; |
770ae6cc | 5860 | unsigned int modewidth; |
230d793d RS |
5861 | rtx tem; |
5862 | ||
5863 | switch (GET_CODE (x)) | |
5864 | { | |
5865 | case ZERO_EXTEND: | |
5866 | unsignedp = 1; | |
5867 | case SIGN_EXTEND: | |
75473182 RS |
5868 | /* We can't necessarily use a const_int for a multiword mode; |
5869 | it depends on implicitly extending the value. | |
5870 | Since we don't know the right way to extend it, | |
5871 | we can't tell whether the implicit way is right. | |
5872 | ||
5873 | Even for a mode that is no wider than a const_int, | |
5874 | we can't win, because we need to sign extend one of its bits through | |
5875 | the rest of it, and we don't know which bit. */ | |
230d793d | 5876 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
75473182 | 5877 | return x; |
230d793d | 5878 | |
8079805d RK |
5879 | /* Return if (subreg:MODE FROM 0) is not a safe replacement for |
5880 | (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM | |
5881 | because (SUBREG (MEM...)) is guaranteed to cause the MEM to be | |
5882 | reloaded. If not for that, MEM's would very rarely be safe. | |
5883 | ||
5884 | Reject MODEs bigger than a word, because we might not be able | |
5885 | to reference a two-register group starting with an arbitrary register | |
5886 | (and currently gen_lowpart might crash for a SUBREG). */ | |
663522cb | 5887 | |
8079805d | 5888 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) |
230d793d RS |
5889 | return x; |
5890 | ||
71012d97 GK |
5891 | /* Reject MODEs that aren't scalar integers because turning vector |
5892 | or complex modes into shifts causes problems. */ | |
5893 | ||
5894 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5895 | return x; | |
5896 | ||
230d793d RS |
5897 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); |
5898 | /* If the inner object has VOIDmode (the only way this can happen | |
e0a2f705 | 5899 | is if it is an ASM_OPERANDS), we can't do anything since we don't |
230d793d RS |
5900 | know how much masking to do. */ |
5901 | if (len == 0) | |
5902 | return x; | |
5903 | ||
5904 | break; | |
5905 | ||
5906 | case ZERO_EXTRACT: | |
5907 | unsignedp = 1; | |
46d096a3 SB |
5908 | |
5909 | /* ... fall through ... */ | |
5910 | ||
230d793d RS |
5911 | case SIGN_EXTRACT: |
5912 | /* If the operand is a CLOBBER, just return it. */ | |
5913 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
5914 | return XEXP (x, 0); | |
5915 | ||
5916 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5917 | || GET_CODE (XEXP (x, 2)) != CONST_INT | |
5918 | || GET_MODE (XEXP (x, 0)) == VOIDmode) | |
5919 | return x; | |
5920 | ||
71012d97 GK |
5921 | /* Reject MODEs that aren't scalar integers because turning vector |
5922 | or complex modes into shifts causes problems. */ | |
5923 | ||
5924 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5925 | return x; | |
5926 | ||
230d793d RS |
5927 | len = INTVAL (XEXP (x, 1)); |
5928 | pos = INTVAL (XEXP (x, 2)); | |
5929 | ||
5930 | /* If this goes outside the object being extracted, replace the object | |
5931 | with a (use (mem ...)) construct that only combine understands | |
5932 | and is used only for this purpose. */ | |
5933 | if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
38a448ca | 5934 | SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); |
230d793d | 5935 | |
f76b9db2 ILT |
5936 | if (BITS_BIG_ENDIAN) |
5937 | pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; | |
5938 | ||
230d793d RS |
5939 | break; |
5940 | ||
5941 | default: | |
5942 | return x; | |
5943 | } | |
0f808b6f JH |
5944 | /* Convert sign extension to zero extension, if we know that the high |
5945 | bit is not set, as this is easier to optimize. It will be converted | |
5946 | back to cheaper alternative in make_extraction. */ | |
5947 | if (GET_CODE (x) == SIGN_EXTEND | |
5948 | && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5949 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
663522cb | 5950 | & ~(((unsigned HOST_WIDE_INT) |
0f808b6f JH |
5951 | GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) |
5952 | >> 1)) | |
5953 | == 0))) | |
5954 | { | |
5955 | rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); | |
3dcd7d45 EC |
5956 | rtx temp2 = expand_compound_operation (temp); |
5957 | ||
5958 | /* Make sure this is a profitable operation. */ | |
5959 | if (rtx_cost (x, SET) > rtx_cost (temp2, SET)) | |
5960 | return temp2; | |
5961 | else if (rtx_cost (x, SET) > rtx_cost (temp, SET)) | |
5962 | return temp; | |
5963 | else | |
5964 | return x; | |
0f808b6f | 5965 | } |
230d793d | 5966 | |
0f13a422 ILT |
5967 | /* We can optimize some special cases of ZERO_EXTEND. */ |
5968 | if (GET_CODE (x) == ZERO_EXTEND) | |
5969 | { | |
5970 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we | |
5971 | know that the last value didn't have any inappropriate bits | |
5972 | set. */ | |
5973 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5974 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
5975 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5976 | && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) | |
663522cb | 5977 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5978 | return XEXP (XEXP (x, 0), 0); |
5979 | ||
5980 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
5981 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
5982 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
5983 | && subreg_lowpart_p (XEXP (x, 0)) | |
5984 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5985 | && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) | |
663522cb | 5986 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5987 | return SUBREG_REG (XEXP (x, 0)); |
5988 | ||
5989 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo | |
5990 | is a comparison and STORE_FLAG_VALUE permits. This is like | |
5991 | the first case, but it works even when GET_MODE (x) is larger | |
5992 | than HOST_WIDE_INT. */ | |
5993 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5994 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
ec8e098d | 5995 | && COMPARISON_P (XEXP (XEXP (x, 0), 0)) |
0f13a422 ILT |
5996 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
5997 | <= HOST_BITS_PER_WIDE_INT) | |
23190837 | 5998 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE |
663522cb | 5999 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
6000 | return XEXP (XEXP (x, 0), 0); |
6001 | ||
6002 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
6003 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6004 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
6005 | && subreg_lowpart_p (XEXP (x, 0)) | |
ec8e098d | 6006 | && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) |
0f13a422 ILT |
6007 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
6008 | <= HOST_BITS_PER_WIDE_INT) | |
6009 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE | |
663522cb | 6010 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
6011 | return SUBREG_REG (XEXP (x, 0)); |
6012 | ||
0f13a422 ILT |
6013 | } |
6014 | ||
230d793d RS |
6015 | /* If we reach here, we want to return a pair of shifts. The inner |
6016 | shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
6017 | shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
6018 | logical depending on the value of UNSIGNEDP. | |
6019 | ||
6020 | If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
6021 | converted into an AND of a shift. | |
6022 | ||
6023 | We must check for the case where the left shift would have a negative | |
6024 | count. This can happen in a case like (x >> 31) & 255 on machines | |
6025 | that can't shift by a constant. On those machines, we would first | |
663522cb | 6026 | combine the shift with the AND to produce a variable-position |
230d793d RS |
6027 | extraction. Then the constant of 31 would be substituted in to produce |
6028 | a such a position. */ | |
6029 | ||
6030 | modewidth = GET_MODE_BITSIZE (GET_MODE (x)); | |
770ae6cc | 6031 | if (modewidth + len >= pos) |
5f4f0e22 | 6032 | tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, |
230d793d | 6033 | GET_MODE (x), |
5f4f0e22 CH |
6034 | simplify_shift_const (NULL_RTX, ASHIFT, |
6035 | GET_MODE (x), | |
230d793d RS |
6036 | XEXP (x, 0), |
6037 | modewidth - pos - len), | |
6038 | modewidth - len); | |
6039 | ||
5f4f0e22 CH |
6040 | else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) |
6041 | tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), | |
6042 | simplify_shift_const (NULL_RTX, LSHIFTRT, | |
230d793d RS |
6043 | GET_MODE (x), |
6044 | XEXP (x, 0), pos), | |
5f4f0e22 | 6045 | ((HOST_WIDE_INT) 1 << len) - 1); |
230d793d RS |
6046 | else |
6047 | /* Any other cases we can't handle. */ | |
6048 | return x; | |
230d793d RS |
6049 | |
6050 | /* If we couldn't do this for some reason, return the original | |
6051 | expression. */ | |
6052 | if (GET_CODE (tem) == CLOBBER) | |
6053 | return x; | |
6054 | ||
6055 | return tem; | |
6056 | } | |
6057 | \f | |
6058 | /* X is a SET which contains an assignment of one object into | |
6059 | a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
6060 | or certain SUBREGS). If possible, convert it into a series of | |
6061 | logical operations. | |
6062 | ||
6063 | We half-heartedly support variable positions, but do not at all | |
6064 | support variable lengths. */ | |
6065 | ||
6066 | static rtx | |
79a490a9 | 6067 | expand_field_assignment (rtx x) |
230d793d RS |
6068 | { |
6069 | rtx inner; | |
0f41302f | 6070 | rtx pos; /* Always counts from low bit. */ |
230d793d | 6071 | int len; |
bcb34aa3 | 6072 | rtx mask, cleared, masked; |
230d793d RS |
6073 | enum machine_mode compute_mode; |
6074 | ||
6075 | /* Loop until we find something we can't simplify. */ | |
6076 | while (1) | |
6077 | { | |
6078 | if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
6079 | && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
6080 | { | |
6081 | inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
6082 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); | |
47073a38 | 6083 | pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); |
230d793d RS |
6084 | } |
6085 | else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
6086 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) | |
6087 | { | |
6088 | inner = XEXP (SET_DEST (x), 0); | |
6089 | len = INTVAL (XEXP (SET_DEST (x), 1)); | |
6090 | pos = XEXP (SET_DEST (x), 2); | |
6091 | ||
6092 | /* If the position is constant and spans the width of INNER, | |
6093 | surround INNER with a USE to indicate this. */ | |
6094 | if (GET_CODE (pos) == CONST_INT | |
6095 | && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) | |
38a448ca | 6096 | inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); |
230d793d | 6097 | |
f76b9db2 ILT |
6098 | if (BITS_BIG_ENDIAN) |
6099 | { | |
6100 | if (GET_CODE (pos) == CONST_INT) | |
6101 | pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len | |
6102 | - INTVAL (pos)); | |
6103 | else if (GET_CODE (pos) == MINUS | |
6104 | && GET_CODE (XEXP (pos, 1)) == CONST_INT | |
6105 | && (INTVAL (XEXP (pos, 1)) | |
6106 | == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) | |
6107 | /* If position is ADJUST - X, new position is X. */ | |
6108 | pos = XEXP (pos, 0); | |
6109 | else | |
bcb34aa3 PB |
6110 | pos = simplify_gen_binary (MINUS, GET_MODE (pos), |
6111 | GEN_INT (GET_MODE_BITSIZE ( | |
6112 | GET_MODE (inner)) | |
6113 | - len), | |
6114 | pos); | |
f76b9db2 | 6115 | } |
230d793d RS |
6116 | } |
6117 | ||
6118 | /* A SUBREG between two modes that occupy the same numbers of words | |
6119 | can be done by moving the SUBREG to the source. */ | |
6120 | else if (GET_CODE (SET_DEST (x)) == SUBREG | |
b1e9c8a9 AO |
6121 | /* We need SUBREGs to compute nonzero_bits properly. */ |
6122 | && nonzero_sign_valid | |
230d793d RS |
6123 | && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) |
6124 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
6125 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
6126 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
6127 | { | |
38a448ca | 6128 | x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), |
4de249d9 | 6129 | gen_lowpart |
c5c76735 JL |
6130 | (GET_MODE (SUBREG_REG (SET_DEST (x))), |
6131 | SET_SRC (x))); | |
230d793d RS |
6132 | continue; |
6133 | } | |
6134 | else | |
6135 | break; | |
6136 | ||
6137 | while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
6138 | inner = SUBREG_REG (inner); | |
6139 | ||
6140 | compute_mode = GET_MODE (inner); | |
6141 | ||
71012d97 GK |
6142 | /* Don't attempt bitwise arithmetic on non scalar integer modes. */ |
6143 | if (! SCALAR_INT_MODE_P (compute_mode)) | |
861556b4 RH |
6144 | { |
6145 | enum machine_mode imode; | |
6146 | ||
71012d97 | 6147 | /* Don't do anything for vector or complex integral types. */ |
861556b4 RH |
6148 | if (! FLOAT_MODE_P (compute_mode)) |
6149 | break; | |
6150 | ||
6151 | /* Try to find an integral mode to pun with. */ | |
6152 | imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); | |
6153 | if (imode == BLKmode) | |
6154 | break; | |
6155 | ||
6156 | compute_mode = imode; | |
4de249d9 | 6157 | inner = gen_lowpart (imode, inner); |
861556b4 RH |
6158 | } |
6159 | ||
230d793d | 6160 | /* Compute a mask of LEN bits, if we can do this on the host machine. */ |
bcb34aa3 | 6161 | if (len >= HOST_BITS_PER_WIDE_INT) |
230d793d RS |
6162 | break; |
6163 | ||
6164 | /* Now compute the equivalent expression. Make a copy of INNER | |
6165 | for the SET_DEST in case it is a MEM into which we will substitute; | |
6166 | we don't want shared RTL in that case. */ | |
bcb34aa3 PB |
6167 | mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); |
6168 | cleared = simplify_gen_binary (AND, compute_mode, | |
6169 | simplify_gen_unary (NOT, compute_mode, | |
6170 | simplify_gen_binary (ASHIFT, | |
6171 | compute_mode, | |
6172 | mask, pos), | |
6173 | compute_mode), | |
6174 | inner); | |
6175 | masked = simplify_gen_binary (ASHIFT, compute_mode, | |
6176 | simplify_gen_binary ( | |
6177 | AND, compute_mode, | |
6178 | gen_lowpart (compute_mode, SET_SRC (x)), | |
6179 | mask), | |
6180 | pos); | |
6181 | ||
6182 | x = gen_rtx_SET (VOIDmode, copy_rtx (inner), | |
6183 | simplify_gen_binary (IOR, compute_mode, | |
6184 | cleared, masked)); | |
230d793d RS |
6185 | } |
6186 | ||
6187 | return x; | |
6188 | } | |
6189 | \f | |
8999a12e RK |
6190 | /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, |
6191 | it is an RTX that represents a variable starting position; otherwise, | |
6192 | POS is the (constant) starting bit position (counted from the LSB). | |
230d793d RS |
6193 | |
6194 | INNER may be a USE. This will occur when we started with a bitfield | |
6195 | that went outside the boundary of the object in memory, which is | |
6196 | allowed on most machines. To isolate this case, we produce a USE | |
6197 | whose mode is wide enough and surround the MEM with it. The only | |
6198 | code that understands the USE is this routine. If it is not removed, | |
6199 | it will cause the resulting insn not to match. | |
6200 | ||
da7d8304 | 6201 | UNSIGNEDP is nonzero for an unsigned reference and zero for a |
230d793d RS |
6202 | signed reference. |
6203 | ||
da7d8304 KH |
6204 | IN_DEST is nonzero if this is a reference in the destination of a |
6205 | SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, | |
230d793d RS |
6206 | a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will |
6207 | be used. | |
6208 | ||
da7d8304 | 6209 | IN_COMPARE is nonzero if we are in a COMPARE. This means that a |
230d793d RS |
6210 | ZERO_EXTRACT should be built even for bits starting at bit 0. |
6211 | ||
76184def DE |
6212 | MODE is the desired mode of the result (if IN_DEST == 0). |
6213 | ||
6214 | The result is an RTX for the extraction or NULL_RTX if the target | |
6215 | can't handle it. */ | |
230d793d RS |
6216 | |
6217 | static rtx | |
79a490a9 AJ |
6218 | make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos, |
6219 | rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, | |
6220 | int in_dest, int in_compare) | |
230d793d | 6221 | { |
94b4b17a RS |
6222 | /* This mode describes the size of the storage area |
6223 | to fetch the overall value from. Within that, we | |
6224 | ignore the POS lowest bits, etc. */ | |
230d793d RS |
6225 | enum machine_mode is_mode = GET_MODE (inner); |
6226 | enum machine_mode inner_mode; | |
d7cd794f RK |
6227 | enum machine_mode wanted_inner_mode = byte_mode; |
6228 | enum machine_mode wanted_inner_reg_mode = word_mode; | |
230d793d RS |
6229 | enum machine_mode pos_mode = word_mode; |
6230 | enum machine_mode extraction_mode = word_mode; | |
6231 | enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
6232 | int spans_byte = 0; | |
6233 | rtx new = 0; | |
8999a12e | 6234 | rtx orig_pos_rtx = pos_rtx; |
770ae6cc | 6235 | HOST_WIDE_INT orig_pos; |
230d793d RS |
6236 | |
6237 | /* Get some information about INNER and get the innermost object. */ | |
6238 | if (GET_CODE (inner) == USE) | |
94b4b17a | 6239 | /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ |
230d793d RS |
6240 | /* We don't need to adjust the position because we set up the USE |
6241 | to pretend that it was a full-word object. */ | |
6242 | spans_byte = 1, inner = XEXP (inner, 0); | |
6243 | else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
94b4b17a RS |
6244 | { |
6245 | /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), | |
6246 | consider just the QI as the memory to extract from. | |
6247 | The subreg adds or removes high bits; its mode is | |
6248 | irrelevant to the meaning of this extraction, | |
6249 | since POS and LEN count from the lsb. */ | |
3c0cb5de | 6250 | if (MEM_P (SUBREG_REG (inner))) |
94b4b17a RS |
6251 | is_mode = GET_MODE (SUBREG_REG (inner)); |
6252 | inner = SUBREG_REG (inner); | |
6253 | } | |
988ef418 RS |
6254 | else if (GET_CODE (inner) == ASHIFT |
6255 | && GET_CODE (XEXP (inner, 1)) == CONST_INT | |
6256 | && pos_rtx == 0 && pos == 0 | |
3129af4c | 6257 | && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1))) |
988ef418 RS |
6258 | { |
6259 | /* We're extracting the least significant bits of an rtx | |
6260 | (ashift X (const_int C)), where LEN > C. Extract the | |
6261 | least significant (LEN - C) bits of X, giving an rtx | |
6262 | whose mode is MODE, then shift it left C times. */ | |
6263 | new = make_extraction (mode, XEXP (inner, 0), | |
6264 | 0, 0, len - INTVAL (XEXP (inner, 1)), | |
6265 | unsignedp, in_dest, in_compare); | |
6266 | if (new != 0) | |
6267 | return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1)); | |
6268 | } | |
230d793d RS |
6269 | |
6270 | inner_mode = GET_MODE (inner); | |
6271 | ||
6272 | if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) | |
8999a12e | 6273 | pos = INTVAL (pos_rtx), pos_rtx = 0; |
230d793d RS |
6274 | |
6275 | /* See if this can be done without an extraction. We never can if the | |
6276 | width of the field is not the same as that of some integer mode. For | |
6277 | registers, we can only avoid the extraction if the position is at the | |
6278 | low-order bit and this is either not in the destination or we have the | |
6279 | appropriate STRICT_LOW_PART operation available. | |
6280 | ||
6281 | For MEM, we can avoid an extract if the field starts on an appropriate | |
6282 | boundary and we can change the mode of the memory reference. However, | |
6283 | we cannot directly access the MEM if we have a USE and the underlying | |
6284 | MEM is not TMODE. This combination means that MEM was being used in a | |
6285 | context where bits outside its mode were being referenced; that is only | |
6286 | valid in bit-field insns. */ | |
6287 | ||
6288 | if (tmode != BLKmode | |
6289 | && ! (spans_byte && inner_mode != tmode) | |
4d9cfc7b | 6290 | && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 |
3c0cb5de | 6291 | && !MEM_P (inner) |
230d793d | 6292 | && (! in_dest |
f8cfc6aa | 6293 | || (REG_P (inner) |
ef89d648 | 6294 | && have_insn_for (STRICT_LOW_PART, tmode)))) |
3c0cb5de | 6295 | || (MEM_P (inner) && pos_rtx == 0 |
dfbe1b2f RK |
6296 | && (pos |
6297 | % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
6298 | : BITS_PER_UNIT)) == 0 | |
230d793d RS |
6299 | /* We can't do this if we are widening INNER_MODE (it |
6300 | may not be aligned, for one thing). */ | |
6301 | && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) | |
6302 | && (inner_mode == tmode | |
6303 | || (! mode_dependent_address_p (XEXP (inner, 0)) | |
6304 | && ! MEM_VOLATILE_P (inner)))))) | |
6305 | { | |
230d793d RS |
6306 | /* If INNER is a MEM, make a new MEM that encompasses just the desired |
6307 | field. If the original and current mode are the same, we need not | |
663522cb | 6308 | adjust the offset. Otherwise, we do if bytes big endian. |
230d793d | 6309 | |
4d9cfc7b RK |
6310 | If INNER is not a MEM, get a piece consisting of just the field |
6311 | of interest (in this case POS % BITS_PER_WORD must be 0). */ | |
230d793d | 6312 | |
3c0cb5de | 6313 | if (MEM_P (inner)) |
230d793d | 6314 | { |
f1ec5147 RK |
6315 | HOST_WIDE_INT offset; |
6316 | ||
94b4b17a RS |
6317 | /* POS counts from lsb, but make OFFSET count in memory order. */ |
6318 | if (BYTES_BIG_ENDIAN) | |
6319 | offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; | |
6320 | else | |
6321 | offset = pos / BITS_PER_UNIT; | |
230d793d | 6322 | |
f1ec5147 | 6323 | new = adjust_address_nv (inner, tmode, offset); |
230d793d | 6324 | } |
f8cfc6aa | 6325 | else if (REG_P (inner)) |
c0d3ac4d | 6326 | { |
c0d3ac4d | 6327 | if (tmode != inner_mode) |
ddef6bc7 | 6328 | { |
4de249d9 | 6329 | /* We can't call gen_lowpart in a DEST since we |
91f8389c EB |
6330 | always want a SUBREG (see below) and it would sometimes |
6331 | return a new hard register. */ | |
6332 | if (pos || in_dest) | |
54c2fc72 | 6333 | { |
54c2fc72 JW |
6334 | HOST_WIDE_INT final_word = pos / BITS_PER_WORD; |
6335 | ||
6336 | if (WORDS_BIG_ENDIAN | |
6337 | && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) | |
6338 | final_word = ((GET_MODE_SIZE (inner_mode) | |
6339 | - GET_MODE_SIZE (tmode)) | |
6340 | / UNITS_PER_WORD) - final_word; | |
6341 | ||
6342 | final_word *= UNITS_PER_WORD; | |
6343 | if (BYTES_BIG_ENDIAN && | |
6344 | GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) | |
6345 | final_word += (GET_MODE_SIZE (inner_mode) | |
6346 | - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; | |
6347 | ||
6348 | /* Avoid creating invalid subregs, for example when | |
6349 | simplifying (x>>32)&255. */ | |
b166bfd2 | 6350 | if (!validate_subreg (tmode, inner_mode, inner, final_word)) |
54c2fc72 JW |
6351 | return NULL_RTX; |
6352 | ||
6353 | new = gen_rtx_SUBREG (tmode, inner, final_word); | |
6354 | } | |
6355 | else | |
4de249d9 | 6356 | new = gen_lowpart (tmode, inner); |
ddef6bc7 | 6357 | } |
23190837 AJ |
6358 | else |
6359 | new = inner; | |
6360 | } | |
230d793d | 6361 | else |
6139ff20 RK |
6362 | new = force_to_mode (inner, tmode, |
6363 | len >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6364 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 6365 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 6366 | NULL_RTX, 0); |
230d793d | 6367 | |
663522cb | 6368 | /* If this extraction is going into the destination of a SET, |
230d793d RS |
6369 | make a STRICT_LOW_PART unless we made a MEM. */ |
6370 | ||
6371 | if (in_dest) | |
3c0cb5de | 6372 | return (MEM_P (new) ? new |
77fa0940 | 6373 | : (GET_CODE (new) != SUBREG |
38a448ca | 6374 | ? gen_rtx_CLOBBER (tmode, const0_rtx) |
f1c6ba8b | 6375 | : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); |
230d793d | 6376 | |
0f808b6f JH |
6377 | if (mode == tmode) |
6378 | return new; | |
6379 | ||
0a7ec763 | 6380 | if (GET_CODE (new) == CONST_INT) |
2496c7bd | 6381 | return gen_int_mode (INTVAL (new), mode); |
0a7ec763 | 6382 | |
0f808b6f JH |
6383 | /* If we know that no extraneous bits are set, and that the high |
6384 | bit is not set, convert the extraction to the cheaper of | |
6385 | sign and zero extension, that are equivalent in these cases. */ | |
6386 | if (flag_expensive_optimizations | |
6387 | && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
6388 | && ((nonzero_bits (new, tmode) | |
663522cb KH |
6389 | & ~(((unsigned HOST_WIDE_INT) |
6390 | GET_MODE_MASK (tmode)) | |
6391 | >> 1)) | |
0f808b6f JH |
6392 | == 0))) |
6393 | { | |
6394 | rtx temp = gen_rtx_ZERO_EXTEND (mode, new); | |
6395 | rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); | |
6396 | ||
6397 | /* Prefer ZERO_EXTENSION, since it gives more information to | |
6398 | backends. */ | |
25ffb1f6 | 6399 | if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) |
0f808b6f JH |
6400 | return temp; |
6401 | return temp1; | |
6402 | } | |
6403 | ||
230d793d RS |
6404 | /* Otherwise, sign- or zero-extend unless we already are in the |
6405 | proper mode. */ | |
6406 | ||
f1c6ba8b RK |
6407 | return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, |
6408 | mode, new)); | |
230d793d RS |
6409 | } |
6410 | ||
cc471082 RS |
6411 | /* Unless this is a COMPARE or we have a funny memory reference, |
6412 | don't do anything with zero-extending field extracts starting at | |
6413 | the low-order bit since they are simple AND operations. */ | |
8999a12e RK |
6414 | if (pos_rtx == 0 && pos == 0 && ! in_dest |
6415 | && ! in_compare && ! spans_byte && unsignedp) | |
230d793d RS |
6416 | return 0; |
6417 | ||
c5c76735 JL |
6418 | /* Unless we are allowed to span bytes or INNER is not MEM, reject this if |
6419 | we would be spanning bytes or if the position is not a constant and the | |
6420 | length is not 1. In all other cases, we would only be going outside | |
6421 | our object in cases when an original shift would have been | |
e7373556 | 6422 | undefined. */ |
3c0cb5de | 6423 | if (! spans_byte && MEM_P (inner) |
e7373556 RK |
6424 | && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) |
6425 | || (pos_rtx != 0 && len != 1))) | |
6426 | return 0; | |
6427 | ||
d7cd794f | 6428 | /* Get the mode to use should INNER not be a MEM, the mode for the position, |
230d793d | 6429 | and the mode for the result. */ |
505ddab6 | 6430 | if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) |
230d793d | 6431 | { |
da920570 ZW |
6432 | wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); |
6433 | pos_mode = mode_for_extraction (EP_insv, 2); | |
6434 | extraction_mode = mode_for_extraction (EP_insv, 3); | |
230d793d | 6435 | } |
230d793d | 6436 | |
da920570 ZW |
6437 | if (! in_dest && unsignedp |
6438 | && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6439 | { |
da920570 ZW |
6440 | wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); |
6441 | pos_mode = mode_for_extraction (EP_extzv, 3); | |
6442 | extraction_mode = mode_for_extraction (EP_extzv, 0); | |
230d793d | 6443 | } |
230d793d | 6444 | |
da920570 ZW |
6445 | if (! in_dest && ! unsignedp |
6446 | && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6447 | { |
da920570 ZW |
6448 | wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); |
6449 | pos_mode = mode_for_extraction (EP_extv, 3); | |
6450 | extraction_mode = mode_for_extraction (EP_extv, 0); | |
230d793d | 6451 | } |
230d793d RS |
6452 | |
6453 | /* Never narrow an object, since that might not be safe. */ | |
6454 | ||
6455 | if (mode != VOIDmode | |
6456 | && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
6457 | extraction_mode = mode; | |
6458 | ||
6459 | if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode | |
6460 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6461 | pos_mode = GET_MODE (pos_rtx); | |
6462 | ||
d7cd794f RK |
6463 | /* If this is not from memory, the desired mode is wanted_inner_reg_mode; |
6464 | if we have to change the mode of memory and cannot, the desired mode is | |
6465 | EXTRACTION_MODE. */ | |
3c0cb5de | 6466 | if (!MEM_P (inner)) |
d7cd794f RK |
6467 | wanted_inner_mode = wanted_inner_reg_mode; |
6468 | else if (inner_mode != wanted_inner_mode | |
6469 | && (mode_dependent_address_p (XEXP (inner, 0)) | |
6470 | || MEM_VOLATILE_P (inner))) | |
6471 | wanted_inner_mode = extraction_mode; | |
230d793d | 6472 | |
6139ff20 RK |
6473 | orig_pos = pos; |
6474 | ||
f76b9db2 ILT |
6475 | if (BITS_BIG_ENDIAN) |
6476 | { | |
cf54c2cd DE |
6477 | /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to |
6478 | BITS_BIG_ENDIAN style. If position is constant, compute new | |
6479 | position. Otherwise, build subtraction. | |
6480 | Note that POS is relative to the mode of the original argument. | |
6481 | If it's a MEM we need to recompute POS relative to that. | |
6482 | However, if we're extracting from (or inserting into) a register, | |
6483 | we want to recompute POS relative to wanted_inner_mode. */ | |
3c0cb5de | 6484 | int width = (MEM_P (inner) |
cf54c2cd DE |
6485 | ? GET_MODE_BITSIZE (is_mode) |
6486 | : GET_MODE_BITSIZE (wanted_inner_mode)); | |
6487 | ||
f76b9db2 | 6488 | if (pos_rtx == 0) |
cf54c2cd | 6489 | pos = width - len - pos; |
f76b9db2 ILT |
6490 | else |
6491 | pos_rtx | |
f1c6ba8b | 6492 | = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); |
cf54c2cd | 6493 | /* POS may be less than 0 now, but we check for that below. |
3c0cb5de | 6494 | Note that it can only be less than 0 if !MEM_P (inner). */ |
f76b9db2 | 6495 | } |
230d793d RS |
6496 | |
6497 | /* If INNER has a wider mode, make it smaller. If this is a constant | |
6498 | extract, try to adjust the byte to point to the byte containing | |
6499 | the value. */ | |
d7cd794f RK |
6500 | if (wanted_inner_mode != VOIDmode |
6501 | && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) | |
3c0cb5de | 6502 | && ((MEM_P (inner) |
d7cd794f | 6503 | && (inner_mode == wanted_inner_mode |
230d793d RS |
6504 | || (! mode_dependent_address_p (XEXP (inner, 0)) |
6505 | && ! MEM_VOLATILE_P (inner)))))) | |
6506 | { | |
6507 | int offset = 0; | |
6508 | ||
6509 | /* The computations below will be correct if the machine is big | |
6510 | endian in both bits and bytes or little endian in bits and bytes. | |
6511 | If it is mixed, we must adjust. */ | |
663522cb | 6512 | |
230d793d | 6513 | /* If bytes are big endian and we had a paradoxical SUBREG, we must |
0f41302f | 6514 | adjust OFFSET to compensate. */ |
f76b9db2 ILT |
6515 | if (BYTES_BIG_ENDIAN |
6516 | && ! spans_byte | |
230d793d RS |
6517 | && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) |
6518 | offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
230d793d | 6519 | |
8f34bde6 | 6520 | /* If this is a constant position, we can move to the desired byte. |
8adac335 AS |
6521 | Be careful not to go beyond the original object and maintain the |
6522 | natural alignment of the memory. */ | |
8999a12e | 6523 | if (pos_rtx == 0) |
230d793d | 6524 | { |
8f34bde6 | 6525 | enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT); |
8adac335 | 6526 | offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode); |
8f34bde6 | 6527 | pos %= GET_MODE_BITSIZE (bfmode); |
230d793d RS |
6528 | } |
6529 | ||
f76b9db2 ILT |
6530 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN |
6531 | && ! spans_byte | |
d7cd794f | 6532 | && is_mode != wanted_inner_mode) |
c6b3f1f2 | 6533 | offset = (GET_MODE_SIZE (is_mode) |
d7cd794f | 6534 | - GET_MODE_SIZE (wanted_inner_mode) - offset); |
c6b3f1f2 | 6535 | |
d7cd794f | 6536 | if (offset != 0 || inner_mode != wanted_inner_mode) |
f1ec5147 | 6537 | inner = adjust_address_nv (inner, wanted_inner_mode, offset); |
230d793d RS |
6538 | } |
6539 | ||
9e74dc41 RK |
6540 | /* If INNER is not memory, we can always get it into the proper mode. If we |
6541 | are changing its mode, POS must be a constant and smaller than the size | |
6542 | of the new mode. */ | |
3c0cb5de | 6543 | else if (!MEM_P (inner)) |
9e74dc41 RK |
6544 | { |
6545 | if (GET_MODE (inner) != wanted_inner_mode | |
6546 | && (pos_rtx != 0 | |
6547 | || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) | |
6548 | return 0; | |
6549 | ||
6550 | inner = force_to_mode (inner, wanted_inner_mode, | |
6551 | pos_rtx | |
6552 | || len + orig_pos >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6553 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 RK |
6554 | : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) |
6555 | << orig_pos), | |
9e74dc41 RK |
6556 | NULL_RTX, 0); |
6557 | } | |
230d793d RS |
6558 | |
6559 | /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
6560 | have to zero extend. Otherwise, we can just use a SUBREG. */ | |
8999a12e | 6561 | if (pos_rtx != 0 |
230d793d | 6562 | && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) |
0f808b6f | 6563 | { |
f1c6ba8b | 6564 | rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); |
0f808b6f JH |
6565 | |
6566 | /* If we know that no extraneous bits are set, and that the high | |
eaec9b3d | 6567 | bit is not set, convert extraction to cheaper one - either |
0f808b6f JH |
6568 | SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these |
6569 | cases. */ | |
6570 | if (flag_expensive_optimizations | |
6571 | && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT | |
6572 | && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) | |
663522cb KH |
6573 | & ~(((unsigned HOST_WIDE_INT) |
6574 | GET_MODE_MASK (GET_MODE (pos_rtx))) | |
6575 | >> 1)) | |
0f808b6f JH |
6576 | == 0))) |
6577 | { | |
6578 | rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); | |
6579 | ||
25ffb1f6 | 6580 | /* Prefer ZERO_EXTENSION, since it gives more information to |
0f808b6f JH |
6581 | backends. */ |
6582 | if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) | |
6583 | temp = temp1; | |
6584 | } | |
6585 | pos_rtx = temp; | |
6586 | } | |
8999a12e | 6587 | else if (pos_rtx != 0 |
230d793d | 6588 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) |
4de249d9 | 6589 | pos_rtx = gen_lowpart (pos_mode, pos_rtx); |
230d793d | 6590 | |
8999a12e RK |
6591 | /* Make POS_RTX unless we already have it and it is correct. If we don't |
6592 | have a POS_RTX but we do have an ORIG_POS_RTX, the latter must | |
0f41302f | 6593 | be a CONST_INT. */ |
8999a12e RK |
6594 | if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) |
6595 | pos_rtx = orig_pos_rtx; | |
6596 | ||
6597 | else if (pos_rtx == 0) | |
5f4f0e22 | 6598 | pos_rtx = GEN_INT (pos); |
230d793d RS |
6599 | |
6600 | /* Make the required operation. See if we can use existing rtx. */ | |
f1c6ba8b | 6601 | new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, |
5f4f0e22 | 6602 | extraction_mode, inner, GEN_INT (len), pos_rtx); |
230d793d | 6603 | if (! in_dest) |
4de249d9 | 6604 | new = gen_lowpart (mode, new); |
230d793d RS |
6605 | |
6606 | return new; | |
6607 | } | |
6608 | \f | |
71923da7 RK |
6609 | /* See if X contains an ASHIFT of COUNT or more bits that can be commuted |
6610 | with any other operations in X. Return X without that shift if so. */ | |
6611 | ||
6612 | static rtx | |
79a490a9 | 6613 | extract_left_shift (rtx x, int count) |
71923da7 RK |
6614 | { |
6615 | enum rtx_code code = GET_CODE (x); | |
6616 | enum machine_mode mode = GET_MODE (x); | |
6617 | rtx tem; | |
6618 | ||
6619 | switch (code) | |
6620 | { | |
6621 | case ASHIFT: | |
6622 | /* This is the shift itself. If it is wide enough, we will return | |
6623 | either the value being shifted if the shift count is equal to | |
6624 | COUNT or a shift for the difference. */ | |
6625 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6626 | && INTVAL (XEXP (x, 1)) >= count) | |
6627 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), | |
6628 | INTVAL (XEXP (x, 1)) - count); | |
6629 | break; | |
6630 | ||
6631 | case NEG: case NOT: | |
6632 | if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
f1c6ba8b | 6633 | return simplify_gen_unary (code, mode, tem, mode); |
71923da7 RK |
6634 | |
6635 | break; | |
6636 | ||
6637 | case PLUS: case IOR: case XOR: case AND: | |
6638 | /* If we can safely shift this constant and we find the inner shift, | |
6639 | make a new operation. */ | |
e869aa39 | 6640 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
b729186a | 6641 | && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 |
71923da7 | 6642 | && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) |
bcb34aa3 PB |
6643 | return simplify_gen_binary (code, mode, tem, |
6644 | GEN_INT (INTVAL (XEXP (x, 1)) >> count)); | |
71923da7 RK |
6645 | |
6646 | break; | |
663522cb | 6647 | |
e9a25f70 JL |
6648 | default: |
6649 | break; | |
71923da7 RK |
6650 | } |
6651 | ||
6652 | return 0; | |
6653 | } | |
6654 | \f | |
230d793d RS |
6655 | /* Look at the expression rooted at X. Look for expressions |
6656 | equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
6657 | Form these expressions. | |
6658 | ||
6659 | Return the new rtx, usually just X. | |
6660 | ||
8aeea6e6 | 6661 | Also, for machines like the VAX that don't have logical shift insns, |
230d793d RS |
6662 | try to convert logical to arithmetic shift operations in cases where |
6663 | they are equivalent. This undoes the canonicalizations to logical | |
6664 | shifts done elsewhere. | |
6665 | ||
6666 | We try, as much as possible, to re-use rtl expressions to save memory. | |
6667 | ||
6668 | IN_CODE says what kind of expression we are processing. Normally, it is | |
42495ca0 RK |
6669 | SET. In a memory address (inside a MEM, PLUS or minus, the latter two |
6670 | being kludges), it is MEM. When processing the arguments of a comparison | |
230d793d RS |
6671 | or a COMPARE against zero, it is COMPARE. */ |
6672 | ||
6673 | static rtx | |
79a490a9 | 6674 | make_compound_operation (rtx x, enum rtx_code in_code) |
230d793d RS |
6675 | { |
6676 | enum rtx_code code = GET_CODE (x); | |
6677 | enum machine_mode mode = GET_MODE (x); | |
6678 | int mode_width = GET_MODE_BITSIZE (mode); | |
71923da7 | 6679 | rtx rhs, lhs; |
230d793d | 6680 | enum rtx_code next_code; |
f24ad0e4 | 6681 | int i; |
230d793d | 6682 | rtx new = 0; |
280f58ba | 6683 | rtx tem; |
6f7d635c | 6684 | const char *fmt; |
230d793d RS |
6685 | |
6686 | /* Select the code to be used in recursive calls. Once we are inside an | |
6687 | address, we stay there. If we have a comparison, set to COMPARE, | |
6688 | but once inside, go back to our default of SET. */ | |
6689 | ||
42495ca0 | 6690 | next_code = (code == MEM || code == PLUS || code == MINUS ? MEM |
ec8e098d | 6691 | : ((code == COMPARE || COMPARISON_P (x)) |
230d793d RS |
6692 | && XEXP (x, 1) == const0_rtx) ? COMPARE |
6693 | : in_code == COMPARE ? SET : in_code); | |
6694 | ||
6695 | /* Process depending on the code of this operation. If NEW is set | |
da7d8304 | 6696 | nonzero, it will be returned. */ |
230d793d RS |
6697 | |
6698 | switch (code) | |
6699 | { | |
6700 | case ASHIFT: | |
230d793d RS |
6701 | /* Convert shifts by constants into multiplications if inside |
6702 | an address. */ | |
6703 | if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5f4f0e22 | 6704 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
230d793d | 6705 | && INTVAL (XEXP (x, 1)) >= 0) |
280f58ba RK |
6706 | { |
6707 | new = make_compound_operation (XEXP (x, 0), next_code); | |
f1c6ba8b RK |
6708 | new = gen_rtx_MULT (mode, new, |
6709 | GEN_INT ((HOST_WIDE_INT) 1 | |
6710 | << INTVAL (XEXP (x, 1)))); | |
280f58ba | 6711 | } |
230d793d RS |
6712 | break; |
6713 | ||
6714 | case AND: | |
6715 | /* If the second operand is not a constant, we can't do anything | |
6716 | with it. */ | |
6717 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6718 | break; | |
6719 | ||
6720 | /* If the constant is a power of two minus one and the first operand | |
6721 | is a logical right shift, make an extraction. */ | |
6722 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
6723 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6724 | { |
6725 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6726 | new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, | |
6727 | 0, in_code == COMPARE); | |
6728 | } | |
dfbe1b2f | 6729 | |
230d793d RS |
6730 | /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ |
6731 | else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6732 | && subreg_lowpart_p (XEXP (x, 0)) | |
6733 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
6734 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6735 | { |
6736 | new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), | |
6737 | next_code); | |
2f99f437 | 6738 | new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, |
280f58ba RK |
6739 | XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, |
6740 | 0, in_code == COMPARE); | |
6741 | } | |
45620ed4 | 6742 | /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ |
c2f9f64e JW |
6743 | else if ((GET_CODE (XEXP (x, 0)) == XOR |
6744 | || GET_CODE (XEXP (x, 0)) == IOR) | |
6745 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT | |
6746 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT | |
6747 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6748 | { | |
6749 | /* Apply the distributive law, and then try to make extractions. */ | |
f1c6ba8b RK |
6750 | new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, |
6751 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), | |
6752 | XEXP (x, 1)), | |
6753 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), | |
6754 | XEXP (x, 1))); | |
c2f9f64e JW |
6755 | new = make_compound_operation (new, in_code); |
6756 | } | |
a7c99304 RK |
6757 | |
6758 | /* If we are have (and (rotate X C) M) and C is larger than the number | |
6759 | of bits in M, this is an extraction. */ | |
6760 | ||
6761 | else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
6762 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
6763 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 | |
6764 | && i <= INTVAL (XEXP (XEXP (x, 0), 1))) | |
280f58ba RK |
6765 | { |
6766 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6767 | new = make_extraction (mode, new, | |
6768 | (GET_MODE_BITSIZE (mode) | |
6769 | - INTVAL (XEXP (XEXP (x, 0), 1))), | |
6770 | NULL_RTX, i, 1, 0, in_code == COMPARE); | |
6771 | } | |
a7c99304 RK |
6772 | |
6773 | /* On machines without logical shifts, if the operand of the AND is | |
230d793d RS |
6774 | a logical shift and our mask turns off all the propagated sign |
6775 | bits, we can replace the logical shift with an arithmetic shift. */ | |
ef89d648 ZW |
6776 | else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
6777 | && !have_insn_for (LSHIFTRT, mode) | |
6778 | && have_insn_for (ASHIFTRT, mode) | |
230d793d RS |
6779 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT |
6780 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
5f4f0e22 CH |
6781 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT |
6782 | && mode_width <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 6783 | { |
5f4f0e22 | 6784 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
6785 | |
6786 | mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
6787 | if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
6788 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
6789 | gen_rtx_ASHIFTRT (mode, |
6790 | make_compound_operation | |
6791 | (XEXP (XEXP (x, 0), 0), next_code), | |
6792 | XEXP (XEXP (x, 0), 1))); | |
230d793d RS |
6793 | } |
6794 | ||
6795 | /* If the constant is one less than a power of two, this might be | |
6796 | representable by an extraction even if no shift is present. | |
6797 | If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
6798 | we are in a COMPARE. */ | |
6799 | else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6800 | new = make_extraction (mode, |
6801 | make_compound_operation (XEXP (x, 0), | |
6802 | next_code), | |
6803 | 0, NULL_RTX, i, 1, 0, in_code == COMPARE); | |
230d793d RS |
6804 | |
6805 | /* If we are in a comparison and this is an AND with a power of two, | |
6806 | convert this into the appropriate bit extract. */ | |
6807 | else if (in_code == COMPARE | |
6808 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
280f58ba RK |
6809 | new = make_extraction (mode, |
6810 | make_compound_operation (XEXP (x, 0), | |
6811 | next_code), | |
6812 | i, NULL_RTX, 1, 1, 0, 1); | |
230d793d RS |
6813 | |
6814 | break; | |
6815 | ||
6816 | case LSHIFTRT: | |
6817 | /* If the sign bit is known to be zero, replace this with an | |
6818 | arithmetic shift. */ | |
ef89d648 ZW |
6819 | if (have_insn_for (ASHIFTRT, mode) |
6820 | && ! have_insn_for (LSHIFTRT, mode) | |
5f4f0e22 | 6821 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 6822 | && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) |
230d793d | 6823 | { |
f1c6ba8b RK |
6824 | new = gen_rtx_ASHIFTRT (mode, |
6825 | make_compound_operation (XEXP (x, 0), | |
6826 | next_code), | |
6827 | XEXP (x, 1)); | |
230d793d RS |
6828 | break; |
6829 | } | |
6830 | ||
0f41302f | 6831 | /* ... fall through ... */ |
230d793d RS |
6832 | |
6833 | case ASHIFTRT: | |
71923da7 RK |
6834 | lhs = XEXP (x, 0); |
6835 | rhs = XEXP (x, 1); | |
6836 | ||
230d793d RS |
6837 | /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, |
6838 | this is a SIGN_EXTRACT. */ | |
71923da7 RK |
6839 | if (GET_CODE (rhs) == CONST_INT |
6840 | && GET_CODE (lhs) == ASHIFT | |
6841 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
6842 | && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) | |
280f58ba | 6843 | { |
71923da7 | 6844 | new = make_compound_operation (XEXP (lhs, 0), next_code); |
280f58ba | 6845 | new = make_extraction (mode, new, |
71923da7 RK |
6846 | INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), |
6847 | NULL_RTX, mode_width - INTVAL (rhs), | |
d0ab8cd3 | 6848 | code == LSHIFTRT, 0, in_code == COMPARE); |
8231ad94 | 6849 | break; |
d0ab8cd3 RK |
6850 | } |
6851 | ||
71923da7 RK |
6852 | /* See if we have operations between an ASHIFTRT and an ASHIFT. |
6853 | If so, try to merge the shifts into a SIGN_EXTEND. We could | |
6854 | also do this for some cases of SIGN_EXTRACT, but it doesn't | |
6855 | seem worth the effort; the case checked for occurs on Alpha. */ | |
663522cb | 6856 | |
ec8e098d | 6857 | if (!OBJECT_P (lhs) |
71923da7 | 6858 | && ! (GET_CODE (lhs) == SUBREG |
ec8e098d | 6859 | && (OBJECT_P (SUBREG_REG (lhs)))) |
71923da7 RK |
6860 | && GET_CODE (rhs) == CONST_INT |
6861 | && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT | |
6862 | && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) | |
6863 | new = make_extraction (mode, make_compound_operation (new, next_code), | |
6864 | 0, NULL_RTX, mode_width - INTVAL (rhs), | |
6865 | code == LSHIFTRT, 0, in_code == COMPARE); | |
663522cb | 6866 | |
230d793d | 6867 | break; |
280f58ba RK |
6868 | |
6869 | case SUBREG: | |
6870 | /* Call ourselves recursively on the inner expression. If we are | |
6871 | narrowing the object and it has a different RTL code from | |
6872 | what it originally did, do this SUBREG as a force_to_mode. */ | |
6873 | ||
0a5cbff6 | 6874 | tem = make_compound_operation (SUBREG_REG (x), in_code); |
0a5cbff6 | 6875 | |
966b148a AK |
6876 | { |
6877 | rtx simplified; | |
6878 | simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem), | |
6879 | SUBREG_BYTE (x)); | |
0a5cbff6 | 6880 | |
966b148a AK |
6881 | if (simplified) |
6882 | tem = simplified; | |
6f28d3e9 | 6883 | |
966b148a AK |
6884 | if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) |
6885 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) | |
6886 | && subreg_lowpart_p (x)) | |
6887 | { | |
6888 | rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, | |
6889 | NULL_RTX, 0); | |
6890 | ||
6891 | /* If we have something other than a SUBREG, we might have | |
6892 | done an expansion, so rerun ourselves. */ | |
6893 | if (GET_CODE (newer) != SUBREG) | |
6894 | newer = make_compound_operation (newer, in_code); | |
6895 | ||
6896 | return newer; | |
6897 | } | |
6898 | ||
6899 | if (simplified) | |
6f28d3e9 | 6900 | return tem; |
966b148a | 6901 | } |
e9a25f70 | 6902 | break; |
663522cb | 6903 | |
e9a25f70 JL |
6904 | default: |
6905 | break; | |
230d793d RS |
6906 | } |
6907 | ||
6908 | if (new) | |
6909 | { | |
4de249d9 | 6910 | x = gen_lowpart (mode, new); |
230d793d RS |
6911 | code = GET_CODE (x); |
6912 | } | |
6913 | ||
6914 | /* Now recursively process each operand of this operation. */ | |
6915 | fmt = GET_RTX_FORMAT (code); | |
6916 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6917 | if (fmt[i] == 'e') | |
6918 | { | |
6919 | new = make_compound_operation (XEXP (x, i), next_code); | |
6920 | SUBST (XEXP (x, i), new); | |
6921 | } | |
6922 | ||
756191b7 JM |
6923 | /* If this is a commutative operation, the changes to the operands |
6924 | may have made it noncanonical. */ | |
6925 | if (COMMUTATIVE_ARITH_P (x) | |
6926 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) | |
6927 | { | |
6928 | tem = XEXP (x, 0); | |
6929 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
6930 | SUBST (XEXP (x, 1), tem); | |
6931 | } | |
6932 | ||
230d793d RS |
6933 | return x; |
6934 | } | |
6935 | \f | |
6936 | /* Given M see if it is a value that would select a field of bits | |
663522cb KH |
6937 | within an item, but not the entire word. Return -1 if not. |
6938 | Otherwise, return the starting position of the field, where 0 is the | |
6939 | low-order bit. | |
230d793d RS |
6940 | |
6941 | *PLEN is set to the length of the field. */ | |
6942 | ||
6943 | static int | |
79a490a9 | 6944 | get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) |
230d793d RS |
6945 | { |
6946 | /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
663522cb | 6947 | int pos = exact_log2 (m & -m); |
6de9cd9a | 6948 | int len = 0; |
230d793d | 6949 | |
6de9cd9a DN |
6950 | if (pos >= 0) |
6951 | /* Now shift off the low-order zero bits and see if we have a | |
6952 | power of two minus 1. */ | |
6953 | len = exact_log2 ((m >> pos) + 1); | |
230d793d | 6954 | |
d3bc8938 | 6955 | if (len <= 0) |
6de9cd9a | 6956 | pos = -1; |
230d793d | 6957 | |
d3bc8938 | 6958 | *plen = len; |
230d793d RS |
6959 | return pos; |
6960 | } | |
6961 | \f | |
6139ff20 RK |
6962 | /* See if X can be simplified knowing that we will only refer to it in |
6963 | MODE and will only refer to those bits that are nonzero in MASK. | |
6964 | If other bits are being computed or if masking operations are done | |
6965 | that select a superset of the bits in MASK, they can sometimes be | |
6966 | ignored. | |
6967 | ||
6968 | Return a possibly simplified expression, but always convert X to | |
6969 | MODE. If X is a CONST_INT, AND the CONST_INT with MASK. | |
dfbe1b2f | 6970 | |
da7d8304 | 6971 | Also, if REG is nonzero and X is a register equal in value to REG, |
e3d616e3 RK |
6972 | replace X with REG. |
6973 | ||
6974 | If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK | |
6975 | are all off in X. This is used when X will be complemented, by either | |
180b8e4b | 6976 | NOT, NEG, or XOR. */ |
dfbe1b2f RK |
6977 | |
6978 | static rtx | |
79a490a9 AJ |
6979 | force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, |
6980 | rtx reg, int just_select) | |
dfbe1b2f RK |
6981 | { |
6982 | enum rtx_code code = GET_CODE (x); | |
180b8e4b | 6983 | int next_select = just_select || code == XOR || code == NOT || code == NEG; |
ef026f91 RS |
6984 | enum machine_mode op_mode; |
6985 | unsigned HOST_WIDE_INT fuller_mask, nonzero; | |
6139ff20 RK |
6986 | rtx op0, op1, temp; |
6987 | ||
132d2040 RK |
6988 | /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the |
6989 | code below will do the wrong thing since the mode of such an | |
663522cb | 6990 | expression is VOIDmode. |
be3d27d6 CI |
6991 | |
6992 | Also do nothing if X is a CLOBBER; this can happen if X was | |
4de249d9 | 6993 | the return value from a call to gen_lowpart. */ |
be3d27d6 | 6994 | if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) |
246e00f2 RK |
6995 | return x; |
6996 | ||
6139ff20 RK |
6997 | /* We want to perform the operation is its present mode unless we know |
6998 | that the operation is valid in MODE, in which case we do the operation | |
6999 | in MODE. */ | |
1c75dfa4 | 7000 | op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) |
ef89d648 | 7001 | && have_insn_for (code, mode)) |
ef026f91 | 7002 | ? mode : GET_MODE (x)); |
e3d616e3 | 7003 | |
aa988991 RS |
7004 | /* It is not valid to do a right-shift in a narrower mode |
7005 | than the one it came in with. */ | |
7006 | if ((code == LSHIFTRT || code == ASHIFTRT) | |
7007 | && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) | |
7008 | op_mode = GET_MODE (x); | |
ef026f91 RS |
7009 | |
7010 | /* Truncate MASK to fit OP_MODE. */ | |
7011 | if (op_mode) | |
7012 | mask &= GET_MODE_MASK (op_mode); | |
6139ff20 RK |
7013 | |
7014 | /* When we have an arithmetic operation, or a shift whose count we | |
50b29dbb | 7015 | do not know, we need to assume that all bits up to the highest-order |
6139ff20 | 7016 | bit in MASK will be needed. This is how we form such a mask. */ |
50b29dbb ILT |
7017 | if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) |
7018 | fuller_mask = ~(unsigned HOST_WIDE_INT) 0; | |
ef026f91 | 7019 | else |
50b29dbb ILT |
7020 | fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) |
7021 | - 1); | |
ef026f91 RS |
7022 | |
7023 | /* Determine what bits of X are guaranteed to be (non)zero. */ | |
7024 | nonzero = nonzero_bits (x, mode); | |
6139ff20 RK |
7025 | |
7026 | /* If none of the bits in X are needed, return a zero. */ | |
e3d616e3 | 7027 | if (! just_select && (nonzero & mask) == 0) |
ccf7aef4 | 7028 | x = const0_rtx; |
dfbe1b2f | 7029 | |
6139ff20 RK |
7030 | /* If X is a CONST_INT, return a new one. Do this here since the |
7031 | test below will fail. */ | |
7032 | if (GET_CODE (x) == CONST_INT) | |
ccf7aef4 RH |
7033 | { |
7034 | if (SCALAR_INT_MODE_P (mode)) | |
7035 | return gen_int_mode (INTVAL (x) & mask, mode); | |
7036 | else | |
7037 | { | |
7038 | x = GEN_INT (INTVAL (x) & mask); | |
7039 | return gen_lowpart_common (mode, x); | |
7040 | } | |
7041 | } | |
dfbe1b2f | 7042 | |
180b8e4b RK |
7043 | /* If X is narrower than MODE and we want all the bits in X's mode, just |
7044 | get X in the proper mode. */ | |
7045 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
663522cb | 7046 | && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) |
4de249d9 | 7047 | return gen_lowpart (mode, x); |
dfbe1b2f RK |
7048 | |
7049 | switch (code) | |
7050 | { | |
6139ff20 RK |
7051 | case CLOBBER: |
7052 | /* If X is a (clobber (const_int)), return it since we know we are | |
0f41302f | 7053 | generating something that won't match. */ |
6139ff20 RK |
7054 | return x; |
7055 | ||
6139ff20 RK |
7056 | case USE: |
7057 | /* X is a (use (mem ..)) that was made from a bit-field extraction that | |
7058 | spanned the boundary of the MEM. If we are now masking so it is | |
7059 | within that boundary, we don't need the USE any more. */ | |
f76b9db2 | 7060 | if (! BITS_BIG_ENDIAN |
663522cb | 7061 | && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
e3d616e3 | 7062 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
f76b9db2 | 7063 | break; |
6139ff20 | 7064 | |
dfbe1b2f RK |
7065 | case SIGN_EXTEND: |
7066 | case ZERO_EXTEND: | |
7067 | case ZERO_EXTRACT: | |
7068 | case SIGN_EXTRACT: | |
7069 | x = expand_compound_operation (x); | |
7070 | if (GET_CODE (x) != code) | |
e3d616e3 | 7071 | return force_to_mode (x, mode, mask, reg, next_select); |
dfbe1b2f RK |
7072 | break; |
7073 | ||
7074 | case REG: | |
7075 | if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) | |
7076 | || rtx_equal_p (reg, get_last_value (x)))) | |
7077 | x = reg; | |
7078 | break; | |
7079 | ||
dfbe1b2f | 7080 | case SUBREG: |
6139ff20 | 7081 | if (subreg_lowpart_p (x) |
180b8e4b RK |
7082 | /* We can ignore the effect of this SUBREG if it narrows the mode or |
7083 | if the constant masks to zero all the bits the mode doesn't | |
7084 | have. */ | |
6139ff20 RK |
7085 | && ((GET_MODE_SIZE (GET_MODE (x)) |
7086 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
6139ff20 RK |
7087 | || (0 == (mask |
7088 | & GET_MODE_MASK (GET_MODE (x)) | |
663522cb | 7089 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) |
e3d616e3 | 7090 | return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); |
dfbe1b2f RK |
7091 | break; |
7092 | ||
7093 | case AND: | |
6139ff20 RK |
7094 | /* If this is an AND with a constant, convert it into an AND |
7095 | whose constant is the AND of that constant with MASK. If it | |
7096 | remains an AND of MASK, delete it since it is redundant. */ | |
dfbe1b2f | 7097 | |
2ca9ae17 | 7098 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
dfbe1b2f | 7099 | { |
6139ff20 RK |
7100 | x = simplify_and_const_int (x, op_mode, XEXP (x, 0), |
7101 | mask & INTVAL (XEXP (x, 1))); | |
dfbe1b2f RK |
7102 | |
7103 | /* If X is still an AND, see if it is an AND with a mask that | |
71923da7 RK |
7104 | is just some low-order bits. If so, and it is MASK, we don't |
7105 | need it. */ | |
dfbe1b2f RK |
7106 | |
7107 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0c9db30 | 7108 | && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) |
3129af4c | 7109 | == mask)) |
dfbe1b2f | 7110 | x = XEXP (x, 0); |
d0ab8cd3 | 7111 | |
71923da7 RK |
7112 | /* If it remains an AND, try making another AND with the bits |
7113 | in the mode mask that aren't in MASK turned on. If the | |
7114 | constant in the AND is wide enough, this might make a | |
7115 | cheaper constant. */ | |
7116 | ||
7117 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2ca9ae17 JW |
7118 | && GET_MODE_MASK (GET_MODE (x)) != mask |
7119 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) | |
71923da7 RK |
7120 | { |
7121 | HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) | |
663522cb | 7122 | | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); |
71923da7 RK |
7123 | int width = GET_MODE_BITSIZE (GET_MODE (x)); |
7124 | rtx y; | |
7125 | ||
71cc389b | 7126 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative |
71923da7 RK |
7127 | number, sign extend it. */ |
7128 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
7129 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
7130 | cval |= (HOST_WIDE_INT) -1 << width; | |
7131 | ||
bcb34aa3 PB |
7132 | y = simplify_gen_binary (AND, GET_MODE (x), |
7133 | XEXP (x, 0), GEN_INT (cval)); | |
71923da7 RK |
7134 | if (rtx_cost (y, SET) < rtx_cost (x, SET)) |
7135 | x = y; | |
7136 | } | |
7137 | ||
d0ab8cd3 | 7138 | break; |
dfbe1b2f RK |
7139 | } |
7140 | ||
6139ff20 | 7141 | goto binop; |
dfbe1b2f RK |
7142 | |
7143 | case PLUS: | |
6139ff20 RK |
7144 | /* In (and (plus FOO C1) M), if M is a mask that just turns off |
7145 | low-order bits (as in an alignment operation) and FOO is already | |
7146 | aligned to that boundary, mask C1 to that boundary as well. | |
7147 | This may eliminate that PLUS and, later, the AND. */ | |
9fa6d012 TG |
7148 | |
7149 | { | |
770ae6cc | 7150 | unsigned int width = GET_MODE_BITSIZE (mode); |
9fa6d012 TG |
7151 | unsigned HOST_WIDE_INT smask = mask; |
7152 | ||
7153 | /* If MODE is narrower than HOST_WIDE_INT and mask is a negative | |
7154 | number, sign extend it. */ | |
7155 | ||
7156 | if (width < HOST_BITS_PER_WIDE_INT | |
7157 | && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
7158 | smask |= (HOST_WIDE_INT) -1 << width; | |
7159 | ||
7160 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
563c12b0 RH |
7161 | && exact_log2 (- smask) >= 0 |
7162 | && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 | |
7163 | && (INTVAL (XEXP (x, 1)) & ~smask) != 0) | |
7164 | return force_to_mode (plus_constant (XEXP (x, 0), | |
7165 | (INTVAL (XEXP (x, 1)) & smask)), | |
7166 | mode, smask, reg, next_select); | |
9fa6d012 | 7167 | } |
6139ff20 | 7168 | |
0f41302f | 7169 | /* ... fall through ... */ |
6139ff20 | 7170 | |
dfbe1b2f | 7171 | case MULT: |
6139ff20 RK |
7172 | /* For PLUS, MINUS and MULT, we need any bits less significant than the |
7173 | most significant bit in MASK since carries from those bits will | |
7174 | affect the bits we are interested in. */ | |
7175 | mask = fuller_mask; | |
7176 | goto binop; | |
7177 | ||
d41638e4 RH |
7178 | case MINUS: |
7179 | /* If X is (minus C Y) where C's least set bit is larger than any bit | |
7180 | in the mask, then we may replace with (neg Y). */ | |
7181 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
0345195a RK |
7182 | && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) |
7183 | & -INTVAL (XEXP (x, 0)))) | |
7184 | > mask)) | |
d41638e4 | 7185 | { |
f1c6ba8b RK |
7186 | x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), |
7187 | GET_MODE (x)); | |
d41638e4 RH |
7188 | return force_to_mode (x, mode, mask, reg, next_select); |
7189 | } | |
7190 | ||
bc02f8d3 | 7191 | /* Similarly, if C contains every bit in the fuller_mask, then we may |
d41638e4 RH |
7192 | replace with (not Y). */ |
7193 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
bc02f8d3 | 7194 | && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask) |
0345195a | 7195 | == INTVAL (XEXP (x, 0)))) |
d41638e4 | 7196 | { |
f1c6ba8b RK |
7197 | x = simplify_gen_unary (NOT, GET_MODE (x), |
7198 | XEXP (x, 1), GET_MODE (x)); | |
d41638e4 RH |
7199 | return force_to_mode (x, mode, mask, reg, next_select); |
7200 | } | |
7201 | ||
7202 | mask = fuller_mask; | |
7203 | goto binop; | |
7204 | ||
dfbe1b2f RK |
7205 | case IOR: |
7206 | case XOR: | |
6139ff20 RK |
7207 | /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and |
7208 | LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
7209 | operation which may be a bitfield extraction. Ensure that the | |
7210 | constant we form is not wider than the mode of X. */ | |
7211 | ||
7212 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7213 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7214 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7215 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
7216 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7217 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) | |
7218 | + floor_log2 (INTVAL (XEXP (x, 1)))) | |
7219 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7220 | && (INTVAL (XEXP (x, 1)) | |
663522cb | 7221 | & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) |
6139ff20 RK |
7222 | { |
7223 | temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) | |
663522cb | 7224 | << INTVAL (XEXP (XEXP (x, 0), 1))); |
bcb34aa3 PB |
7225 | temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), |
7226 | XEXP (XEXP (x, 0), 0), temp); | |
7227 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, | |
7228 | XEXP (XEXP (x, 0), 1)); | |
e3d616e3 | 7229 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7230 | } |
7231 | ||
7232 | binop: | |
dfbe1b2f | 7233 | /* For most binary operations, just propagate into the operation and |
6d2f8887 | 7234 | change the mode if we have an operation of that mode. */ |
6139ff20 | 7235 | |
4de249d9 PB |
7236 | op0 = gen_lowpart (op_mode, |
7237 | force_to_mode (XEXP (x, 0), mode, mask, | |
7238 | reg, next_select)); | |
7239 | op1 = gen_lowpart (op_mode, | |
7240 | force_to_mode (XEXP (x, 1), mode, mask, | |
7241 | reg, next_select)); | |
6139ff20 RK |
7242 | |
7243 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
bcb34aa3 | 7244 | x = simplify_gen_binary (code, op_mode, op0, op1); |
d0ab8cd3 | 7245 | break; |
dfbe1b2f RK |
7246 | |
7247 | case ASHIFT: | |
dfbe1b2f | 7248 | /* For left shifts, do the same, but just for the first operand. |
f6785026 RK |
7249 | However, we cannot do anything with shifts where we cannot |
7250 | guarantee that the counts are smaller than the size of the mode | |
7251 | because such a count will have a different meaning in a | |
6139ff20 | 7252 | wider mode. */ |
f6785026 RK |
7253 | |
7254 | if (! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6139ff20 | 7255 | && INTVAL (XEXP (x, 1)) >= 0 |
f6785026 RK |
7256 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) |
7257 | && ! (GET_MODE (XEXP (x, 1)) != VOIDmode | |
7258 | && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) | |
adb7a1cb | 7259 | < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) |
f6785026 | 7260 | break; |
663522cb | 7261 | |
6139ff20 RK |
7262 | /* If the shift count is a constant and we can do arithmetic in |
7263 | the mode of the shift, refine which bits we need. Otherwise, use the | |
7264 | conservative form of the mask. */ | |
7265 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7266 | && INTVAL (XEXP (x, 1)) >= 0 | |
7267 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) | |
7268 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) | |
7269 | mask >>= INTVAL (XEXP (x, 1)); | |
7270 | else | |
7271 | mask = fuller_mask; | |
7272 | ||
4de249d9 PB |
7273 | op0 = gen_lowpart (op_mode, |
7274 | force_to_mode (XEXP (x, 0), op_mode, | |
7275 | mask, reg, next_select)); | |
6139ff20 RK |
7276 | |
7277 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
bcb34aa3 | 7278 | x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); |
d0ab8cd3 | 7279 | break; |
dfbe1b2f RK |
7280 | |
7281 | case LSHIFTRT: | |
1347292b JW |
7282 | /* Here we can only do something if the shift count is a constant, |
7283 | this shift constant is valid for the host, and we can do arithmetic | |
7284 | in OP_MODE. */ | |
dfbe1b2f RK |
7285 | |
7286 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1347292b | 7287 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
6139ff20 | 7288 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) |
d0ab8cd3 | 7289 | { |
6139ff20 | 7290 | rtx inner = XEXP (x, 0); |
402b6c2a | 7291 | unsigned HOST_WIDE_INT inner_mask; |
6139ff20 RK |
7292 | |
7293 | /* Select the mask of the bits we need for the shift operand. */ | |
402b6c2a | 7294 | inner_mask = mask << INTVAL (XEXP (x, 1)); |
d0ab8cd3 | 7295 | |
6139ff20 | 7296 | /* We can only change the mode of the shift if we can do arithmetic |
402b6c2a | 7297 | in the mode of the shift and INNER_MASK is no wider than the |
f3b2657c JJ |
7298 | width of X's mode. */ |
7299 | if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) | |
d0ab8cd3 RK |
7300 | op_mode = GET_MODE (x); |
7301 | ||
402b6c2a | 7302 | inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select); |
6139ff20 RK |
7303 | |
7304 | if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) | |
bcb34aa3 | 7305 | x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); |
d0ab8cd3 | 7306 | } |
6139ff20 RK |
7307 | |
7308 | /* If we have (and (lshiftrt FOO C1) C2) where the combination of the | |
7309 | shift and AND produces only copies of the sign bit (C2 is one less | |
7310 | than a power of two), we can do this with just a shift. */ | |
7311 | ||
7312 | if (GET_CODE (x) == LSHIFTRT | |
7313 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
cfff35c1 JW |
7314 | /* The shift puts one of the sign bit copies in the least significant |
7315 | bit. */ | |
6139ff20 RK |
7316 | && ((INTVAL (XEXP (x, 1)) |
7317 | + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) | |
7318 | >= GET_MODE_BITSIZE (GET_MODE (x))) | |
7319 | && exact_log2 (mask + 1) >= 0 | |
cfff35c1 JW |
7320 | /* Number of bits left after the shift must be more than the mask |
7321 | needs. */ | |
7322 | && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) | |
7323 | <= GET_MODE_BITSIZE (GET_MODE (x))) | |
7324 | /* Must be more sign bit copies than the mask needs. */ | |
770ae6cc | 7325 | && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) |
6139ff20 | 7326 | >= exact_log2 (mask + 1))) |
bcb34aa3 PB |
7327 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), |
7328 | GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) | |
7329 | - exact_log2 (mask + 1))); | |
fae2db47 JW |
7330 | |
7331 | goto shiftrt; | |
d0ab8cd3 RK |
7332 | |
7333 | case ASHIFTRT: | |
6139ff20 RK |
7334 | /* If we are just looking for the sign bit, we don't need this shift at |
7335 | all, even if it has a variable count. */ | |
9bf22b75 | 7336 | if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT |
e51712db | 7337 | && (mask == ((unsigned HOST_WIDE_INT) 1 |
9bf22b75 | 7338 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
e3d616e3 | 7339 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 RK |
7340 | |
7341 | /* If this is a shift by a constant, get a mask that contains those bits | |
7342 | that are not copies of the sign bit. We then have two cases: If | |
7343 | MASK only includes those bits, this can be a logical shift, which may | |
7344 | allow simplifications. If MASK is a single-bit field not within | |
7345 | those bits, we are requesting a copy of the sign bit and hence can | |
7346 | shift the sign bit to the appropriate location. */ | |
7347 | ||
7348 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 | |
7349 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) | |
7350 | { | |
7351 | int i = -1; | |
7352 | ||
3e92902c | 7353 | /* If the considered data is wider than HOST_WIDE_INT, we can't |
b69960ac RK |
7354 | represent a mask for all its bits in a single scalar. |
7355 | But we only care about the lower bits, so calculate these. */ | |
7356 | ||
6a11342f | 7357 | if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) |
b69960ac | 7358 | { |
663522cb | 7359 | nonzero = ~(HOST_WIDE_INT) 0; |
b69960ac RK |
7360 | |
7361 | /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7362 | is the number of bits a full-width mask would have set. | |
7363 | We need only shift if these are fewer than nonzero can | |
7364 | hold. If not, we must keep all bits set in nonzero. */ | |
7365 | ||
7366 | if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7367 | < HOST_BITS_PER_WIDE_INT) | |
7368 | nonzero >>= INTVAL (XEXP (x, 1)) | |
7369 | + HOST_BITS_PER_WIDE_INT | |
7370 | - GET_MODE_BITSIZE (GET_MODE (x)) ; | |
7371 | } | |
7372 | else | |
7373 | { | |
7374 | nonzero = GET_MODE_MASK (GET_MODE (x)); | |
7375 | nonzero >>= INTVAL (XEXP (x, 1)); | |
7376 | } | |
6139ff20 | 7377 | |
663522cb | 7378 | if ((mask & ~nonzero) == 0 |
6139ff20 RK |
7379 | || (i = exact_log2 (mask)) >= 0) |
7380 | { | |
7381 | x = simplify_shift_const | |
7382 | (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7383 | i < 0 ? INTVAL (XEXP (x, 1)) | |
7384 | : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); | |
7385 | ||
7386 | if (GET_CODE (x) != ASHIFTRT) | |
e3d616e3 | 7387 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7388 | } |
7389 | } | |
7390 | ||
e0a2f705 | 7391 | /* If MASK is 1, convert this to an LSHIFTRT. This can be done |
6139ff20 RK |
7392 | even if the shift count isn't a constant. */ |
7393 | if (mask == 1) | |
bcb34aa3 PB |
7394 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), |
7395 | XEXP (x, 0), XEXP (x, 1)); | |
6139ff20 | 7396 | |
fae2db47 JW |
7397 | shiftrt: |
7398 | ||
7399 | /* If this is a zero- or sign-extension operation that just affects bits | |
4c002f29 RK |
7400 | we don't care about, remove it. Be sure the call above returned |
7401 | something that is still a shift. */ | |
d0ab8cd3 | 7402 | |
4c002f29 RK |
7403 | if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) |
7404 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0ab8cd3 | 7405 | && INTVAL (XEXP (x, 1)) >= 0 |
6139ff20 RK |
7406 | && (INTVAL (XEXP (x, 1)) |
7407 | <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) | |
d0ab8cd3 | 7408 | && GET_CODE (XEXP (x, 0)) == ASHIFT |
fa9ea255 | 7409 | && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) |
e3d616e3 RK |
7410 | return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, |
7411 | reg, next_select); | |
6139ff20 | 7412 | |
dfbe1b2f RK |
7413 | break; |
7414 | ||
6139ff20 RK |
7415 | case ROTATE: |
7416 | case ROTATERT: | |
7417 | /* If the shift count is constant and we can do computations | |
7418 | in the mode of X, compute where the bits we care about are. | |
7419 | Otherwise, we can't do anything. Don't change the mode of | |
7420 | the shift or propagate MODE into the shift, though. */ | |
7421 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7422 | && INTVAL (XEXP (x, 1)) >= 0) | |
7423 | { | |
7424 | temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, | |
7425 | GET_MODE (x), GEN_INT (mask), | |
7426 | XEXP (x, 1)); | |
e869aa39 | 7427 | if (temp && GET_CODE (temp) == CONST_INT) |
6139ff20 RK |
7428 | SUBST (XEXP (x, 0), |
7429 | force_to_mode (XEXP (x, 0), GET_MODE (x), | |
e3d616e3 | 7430 | INTVAL (temp), reg, next_select)); |
6139ff20 RK |
7431 | } |
7432 | break; | |
663522cb | 7433 | |
dfbe1b2f | 7434 | case NEG: |
180b8e4b | 7435 | /* If we just want the low-order bit, the NEG isn't needed since it |
3ef42a0c | 7436 | won't change the low-order bit. */ |
180b8e4b RK |
7437 | if (mask == 1) |
7438 | return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); | |
7439 | ||
6139ff20 RK |
7440 | /* We need any bits less significant than the most significant bit in |
7441 | MASK since carries from those bits will affect the bits we are | |
7442 | interested in. */ | |
7443 | mask = fuller_mask; | |
7444 | goto unop; | |
7445 | ||
dfbe1b2f | 7446 | case NOT: |
6139ff20 RK |
7447 | /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the |
7448 | same as the XOR case above. Ensure that the constant we form is not | |
7449 | wider than the mode of X. */ | |
7450 | ||
7451 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7452 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7453 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7454 | && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) | |
7455 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7456 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) | |
7457 | { | |
6a04f4e0 AM |
7458 | temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), |
7459 | GET_MODE (x)); | |
bcb34aa3 PB |
7460 | temp = simplify_gen_binary (XOR, GET_MODE (x), |
7461 | XEXP (XEXP (x, 0), 0), temp); | |
7462 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), | |
7463 | temp, XEXP (XEXP (x, 0), 1)); | |
6139ff20 | 7464 | |
e3d616e3 | 7465 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7466 | } |
7467 | ||
f82da7d2 JW |
7468 | /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must |
7469 | use the full mask inside the NOT. */ | |
7470 | mask = fuller_mask; | |
7471 | ||
6139ff20 | 7472 | unop: |
4de249d9 PB |
7473 | op0 = gen_lowpart (op_mode, |
7474 | force_to_mode (XEXP (x, 0), mode, mask, | |
7475 | reg, next_select)); | |
6139ff20 | 7476 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) |
f1c6ba8b | 7477 | x = simplify_gen_unary (code, op_mode, op0, op_mode); |
6139ff20 RK |
7478 | break; |
7479 | ||
7480 | case NE: | |
7481 | /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included | |
3aceff0d | 7482 | in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, |
1a6ec070 | 7483 | which is equal to STORE_FLAG_VALUE. */ |
663522cb | 7484 | if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx |
7d103eb5 | 7485 | && GET_MODE (XEXP (x, 0)) == mode |
3aceff0d | 7486 | && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 |
43196589 AS |
7487 | && (nonzero_bits (XEXP (x, 0), mode) |
7488 | == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) | |
e3d616e3 | 7489 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 | 7490 | |
d0ab8cd3 RK |
7491 | break; |
7492 | ||
7493 | case IF_THEN_ELSE: | |
7494 | /* We have no way of knowing if the IF_THEN_ELSE can itself be | |
7495 | written in a narrower mode. We play it safe and do not do so. */ | |
7496 | ||
7497 | SUBST (XEXP (x, 1), | |
4de249d9 | 7498 | gen_lowpart (GET_MODE (x), |
d0ab8cd3 | 7499 | force_to_mode (XEXP (x, 1), mode, |
e3d616e3 | 7500 | mask, reg, next_select))); |
d0ab8cd3 | 7501 | SUBST (XEXP (x, 2), |
4de249d9 | 7502 | gen_lowpart (GET_MODE (x), |
d0ab8cd3 | 7503 | force_to_mode (XEXP (x, 2), mode, |
e869aa39 | 7504 | mask, reg, next_select))); |
d0ab8cd3 | 7505 | break; |
663522cb | 7506 | |
e9a25f70 JL |
7507 | default: |
7508 | break; | |
dfbe1b2f RK |
7509 | } |
7510 | ||
d0ab8cd3 | 7511 | /* Ensure we return a value of the proper mode. */ |
4de249d9 | 7512 | return gen_lowpart (mode, x); |
dfbe1b2f RK |
7513 | } |
7514 | \f | |
abe6e52f RK |
7515 | /* Return nonzero if X is an expression that has one of two values depending on |
7516 | whether some other value is zero or nonzero. In that case, we return the | |
7517 | value that is being tested, *PTRUE is set to the value if the rtx being | |
7518 | returned has a nonzero value, and *PFALSE is set to the other alternative. | |
7519 | ||
7520 | If we return zero, we set *PTRUE and *PFALSE to X. */ | |
7521 | ||
7522 | static rtx | |
79a490a9 | 7523 | if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) |
abe6e52f RK |
7524 | { |
7525 | enum machine_mode mode = GET_MODE (x); | |
7526 | enum rtx_code code = GET_CODE (x); | |
abe6e52f RK |
7527 | rtx cond0, cond1, true0, true1, false0, false1; |
7528 | unsigned HOST_WIDE_INT nz; | |
7529 | ||
14a774a9 RK |
7530 | /* If we are comparing a value against zero, we are done. */ |
7531 | if ((code == NE || code == EQ) | |
87d9741e | 7532 | && XEXP (x, 1) == const0_rtx) |
14a774a9 | 7533 | { |
e8758a3a JL |
7534 | *ptrue = (code == NE) ? const_true_rtx : const0_rtx; |
7535 | *pfalse = (code == NE) ? const0_rtx : const_true_rtx; | |
14a774a9 RK |
7536 | return XEXP (x, 0); |
7537 | } | |
7538 | ||
abe6e52f RK |
7539 | /* If this is a unary operation whose operand has one of two values, apply |
7540 | our opcode to compute those values. */ | |
ec8e098d | 7541 | else if (UNARY_P (x) |
14a774a9 | 7542 | && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) |
abe6e52f | 7543 | { |
f1c6ba8b RK |
7544 | *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); |
7545 | *pfalse = simplify_gen_unary (code, mode, false0, | |
7546 | GET_MODE (XEXP (x, 0))); | |
abe6e52f RK |
7547 | return cond0; |
7548 | } | |
7549 | ||
3a19aabc | 7550 | /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would |
ddd5a7c1 | 7551 | make can't possibly match and would suppress other optimizations. */ |
3a19aabc RK |
7552 | else if (code == COMPARE) |
7553 | ; | |
7554 | ||
abe6e52f RK |
7555 | /* If this is a binary operation, see if either side has only one of two |
7556 | values. If either one does or if both do and they are conditional on | |
7557 | the same value, compute the new true and false values. */ | |
ec8e098d | 7558 | else if (BINARY_P (x)) |
abe6e52f RK |
7559 | { |
7560 | cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); | |
7561 | cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); | |
7562 | ||
7563 | if ((cond0 != 0 || cond1 != 0) | |
7564 | && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) | |
7565 | { | |
987e845a JW |
7566 | /* If if_then_else_cond returned zero, then true/false are the |
7567 | same rtl. We must copy one of them to prevent invalid rtl | |
7568 | sharing. */ | |
7569 | if (cond0 == 0) | |
7570 | true0 = copy_rtx (true0); | |
7571 | else if (cond1 == 0) | |
7572 | true1 = copy_rtx (true1); | |
7573 | ||
bcb34aa3 PB |
7574 | if (COMPARISON_P (x)) |
7575 | { | |
7576 | *ptrue = simplify_gen_relational (code, mode, VOIDmode, | |
7577 | true0, true1); | |
7578 | *pfalse = simplify_gen_relational (code, mode, VOIDmode, | |
7579 | false0, false1); | |
7580 | } | |
7581 | else | |
7582 | { | |
7583 | *ptrue = simplify_gen_binary (code, mode, true0, true1); | |
7584 | *pfalse = simplify_gen_binary (code, mode, false0, false1); | |
7585 | } | |
7586 | ||
abe6e52f RK |
7587 | return cond0 ? cond0 : cond1; |
7588 | } | |
9210df58 | 7589 | |
9210df58 | 7590 | /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the |
da7d8304 | 7591 | operands is zero when the other is nonzero, and vice-versa, |
0802d516 | 7592 | and STORE_FLAG_VALUE is 1 or -1. */ |
9210df58 | 7593 | |
0802d516 RK |
7594 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7595 | && (code == PLUS || code == IOR || code == XOR || code == MINUS | |
663522cb | 7596 | || code == UMAX) |
9210df58 RK |
7597 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7598 | { | |
7599 | rtx op0 = XEXP (XEXP (x, 0), 1); | |
7600 | rtx op1 = XEXP (XEXP (x, 1), 1); | |
7601 | ||
7602 | cond0 = XEXP (XEXP (x, 0), 0); | |
7603 | cond1 = XEXP (XEXP (x, 1), 0); | |
7604 | ||
ec8e098d PB |
7605 | if (COMPARISON_P (cond0) |
7606 | && COMPARISON_P (cond1) | |
14f02e73 | 7607 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
9210df58 RK |
7608 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7609 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7610 | || ((swap_condition (GET_CODE (cond0)) | |
14f02e73 | 7611 | == reversed_comparison_code (cond1, NULL)) |
9210df58 RK |
7612 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7613 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7614 | && ! side_effects_p (x)) | |
7615 | { | |
bcb34aa3 PB |
7616 | *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); |
7617 | *pfalse = simplify_gen_binary (MULT, mode, | |
7618 | (code == MINUS | |
7619 | ? simplify_gen_unary (NEG, mode, | |
7620 | op1, mode) | |
7621 | : op1), | |
7622 | const_true_rtx); | |
9210df58 RK |
7623 | return cond0; |
7624 | } | |
7625 | } | |
7626 | ||
eaec9b3d | 7627 | /* Similarly for MULT, AND and UMIN, except that for these the result |
9210df58 | 7628 | is always zero. */ |
0802d516 RK |
7629 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7630 | && (code == MULT || code == AND || code == UMIN) | |
9210df58 RK |
7631 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7632 | { | |
7633 | cond0 = XEXP (XEXP (x, 0), 0); | |
7634 | cond1 = XEXP (XEXP (x, 1), 0); | |
7635 | ||
ec8e098d PB |
7636 | if (COMPARISON_P (cond0) |
7637 | && COMPARISON_P (cond1) | |
14f02e73 | 7638 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
9210df58 RK |
7639 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7640 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7641 | || ((swap_condition (GET_CODE (cond0)) | |
14f02e73 | 7642 | == reversed_comparison_code (cond1, NULL)) |
9210df58 RK |
7643 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7644 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7645 | && ! side_effects_p (x)) | |
7646 | { | |
7647 | *ptrue = *pfalse = const0_rtx; | |
7648 | return cond0; | |
7649 | } | |
7650 | } | |
abe6e52f RK |
7651 | } |
7652 | ||
7653 | else if (code == IF_THEN_ELSE) | |
7654 | { | |
7655 | /* If we have IF_THEN_ELSE already, extract the condition and | |
7656 | canonicalize it if it is NE or EQ. */ | |
7657 | cond0 = XEXP (x, 0); | |
7658 | *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); | |
7659 | if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) | |
7660 | return XEXP (cond0, 0); | |
7661 | else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) | |
7662 | { | |
7663 | *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); | |
7664 | return XEXP (cond0, 0); | |
7665 | } | |
7666 | else | |
7667 | return cond0; | |
7668 | } | |
7669 | ||
0631e0bf JH |
7670 | /* If X is a SUBREG, we can narrow both the true and false values |
7671 | if the inner expression, if there is a condition. */ | |
7672 | else if (code == SUBREG | |
abe6e52f RK |
7673 | && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), |
7674 | &true0, &false0))) | |
7675 | { | |
bbe708a3 UW |
7676 | true0 = simplify_gen_subreg (mode, true0, |
7677 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
7678 | false0 = simplify_gen_subreg (mode, false0, | |
0631e0bf | 7679 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); |
bbe708a3 UW |
7680 | if (true0 && false0) |
7681 | { | |
7682 | *ptrue = true0; | |
7683 | *pfalse = false0; | |
7684 | return cond0; | |
7685 | } | |
abe6e52f RK |
7686 | } |
7687 | ||
7688 | /* If X is a constant, this isn't special and will cause confusions | |
7689 | if we treat it as such. Likewise if it is equivalent to a constant. */ | |
7690 | else if (CONSTANT_P (x) | |
7691 | || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) | |
7692 | ; | |
7693 | ||
1f3f36d1 RH |
7694 | /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that |
7695 | will be least confusing to the rest of the compiler. */ | |
7696 | else if (mode == BImode) | |
7697 | { | |
7698 | *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; | |
7699 | return x; | |
7700 | } | |
7701 | ||
663522cb | 7702 | /* If X is known to be either 0 or -1, those are the true and |
abe6e52f | 7703 | false values when testing X. */ |
49219895 JH |
7704 | else if (x == constm1_rtx || x == const0_rtx |
7705 | || (mode != VOIDmode | |
7706 | && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) | |
abe6e52f RK |
7707 | { |
7708 | *ptrue = constm1_rtx, *pfalse = const0_rtx; | |
7709 | return x; | |
7710 | } | |
7711 | ||
7712 | /* Likewise for 0 or a single bit. */ | |
9eb54558 | 7713 | else if (SCALAR_INT_MODE_P (mode) |
49219895 JH |
7714 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
7715 | && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) | |
abe6e52f | 7716 | { |
578fc63d | 7717 | *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; |
abe6e52f RK |
7718 | return x; |
7719 | } | |
7720 | ||
7721 | /* Otherwise fail; show no condition with true and false values the same. */ | |
7722 | *ptrue = *pfalse = x; | |
7723 | return 0; | |
7724 | } | |
7725 | \f | |
1a26b032 RK |
7726 | /* Return the value of expression X given the fact that condition COND |
7727 | is known to be true when applied to REG as its first operand and VAL | |
7728 | as its second. X is known to not be shared and so can be modified in | |
7729 | place. | |
7730 | ||
7731 | We only handle the simplest cases, and specifically those cases that | |
7732 | arise with IF_THEN_ELSE expressions. */ | |
7733 | ||
7734 | static rtx | |
79a490a9 | 7735 | known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) |
1a26b032 RK |
7736 | { |
7737 | enum rtx_code code = GET_CODE (x); | |
f24ad0e4 | 7738 | rtx temp; |
6f7d635c | 7739 | const char *fmt; |
1a26b032 RK |
7740 | int i, j; |
7741 | ||
7742 | if (side_effects_p (x)) | |
7743 | return x; | |
7744 | ||
805f1694 JL |
7745 | /* If either operand of the condition is a floating point value, |
7746 | then we have to avoid collapsing an EQ comparison. */ | |
7747 | if (cond == EQ | |
7748 | && rtx_equal_p (x, reg) | |
7749 | && ! FLOAT_MODE_P (GET_MODE (x)) | |
7750 | && ! FLOAT_MODE_P (GET_MODE (val))) | |
69bc0a1f | 7751 | return val; |
805f1694 | 7752 | |
69bc0a1f | 7753 | if (cond == UNEQ && rtx_equal_p (x, reg)) |
1a26b032 RK |
7754 | return val; |
7755 | ||
7756 | /* If X is (abs REG) and we know something about REG's relationship | |
7757 | with zero, we may be able to simplify this. */ | |
7758 | ||
7759 | if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) | |
7760 | switch (cond) | |
7761 | { | |
7762 | case GE: case GT: case EQ: | |
7763 | return XEXP (x, 0); | |
7764 | case LT: case LE: | |
f1c6ba8b RK |
7765 | return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), |
7766 | XEXP (x, 0), | |
7767 | GET_MODE (XEXP (x, 0))); | |
e9a25f70 JL |
7768 | default: |
7769 | break; | |
1a26b032 RK |
7770 | } |
7771 | ||
7772 | /* The only other cases we handle are MIN, MAX, and comparisons if the | |
7773 | operands are the same as REG and VAL. */ | |
7774 | ||
ec8e098d | 7775 | else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) |
1a26b032 RK |
7776 | { |
7777 | if (rtx_equal_p (XEXP (x, 0), val)) | |
7778 | cond = swap_condition (cond), temp = val, val = reg, reg = temp; | |
7779 | ||
7780 | if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) | |
7781 | { | |
ec8e098d | 7782 | if (COMPARISON_P (x)) |
1eb8759b RH |
7783 | { |
7784 | if (comparison_dominates_p (cond, code)) | |
7785 | return const_true_rtx; | |
1a26b032 | 7786 | |
14f02e73 | 7787 | code = reversed_comparison_code (x, NULL); |
1eb8759b RH |
7788 | if (code != UNKNOWN |
7789 | && comparison_dominates_p (cond, code)) | |
7790 | return const0_rtx; | |
7791 | else | |
7792 | return x; | |
7793 | } | |
1a26b032 RK |
7794 | else if (code == SMAX || code == SMIN |
7795 | || code == UMIN || code == UMAX) | |
7796 | { | |
7797 | int unsignedp = (code == UMIN || code == UMAX); | |
7798 | ||
ac4cdf40 JE |
7799 | /* Do not reverse the condition when it is NE or EQ. |
7800 | This is because we cannot conclude anything about | |
7801 | the value of 'SMAX (x, y)' when x is not equal to y, | |
23190837 | 7802 | but we can when x equals y. */ |
ac4cdf40 JE |
7803 | if ((code == SMAX || code == UMAX) |
7804 | && ! (cond == EQ || cond == NE)) | |
1a26b032 RK |
7805 | cond = reverse_condition (cond); |
7806 | ||
7807 | switch (cond) | |
7808 | { | |
7809 | case GE: case GT: | |
7810 | return unsignedp ? x : XEXP (x, 1); | |
7811 | case LE: case LT: | |
7812 | return unsignedp ? x : XEXP (x, 0); | |
7813 | case GEU: case GTU: | |
7814 | return unsignedp ? XEXP (x, 1) : x; | |
7815 | case LEU: case LTU: | |
7816 | return unsignedp ? XEXP (x, 0) : x; | |
e9a25f70 JL |
7817 | default: |
7818 | break; | |
1a26b032 RK |
7819 | } |
7820 | } | |
7821 | } | |
7822 | } | |
9a360704 AO |
7823 | else if (code == SUBREG) |
7824 | { | |
7825 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); | |
7826 | rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val); | |
7827 | ||
7828 | if (SUBREG_REG (x) != r) | |
7829 | { | |
7830 | /* We must simplify subreg here, before we lose track of the | |
7831 | original inner_mode. */ | |
7832 | new = simplify_subreg (GET_MODE (x), r, | |
7833 | inner_mode, SUBREG_BYTE (x)); | |
7834 | if (new) | |
7835 | return new; | |
7836 | else | |
7837 | SUBST (SUBREG_REG (x), r); | |
7838 | } | |
7839 | ||
7840 | return x; | |
7841 | } | |
4161da12 AO |
7842 | /* We don't have to handle SIGN_EXTEND here, because even in the |
7843 | case of replacing something with a modeless CONST_INT, a | |
7844 | CONST_INT is already (supposed to be) a valid sign extension for | |
7845 | its narrower mode, which implies it's already properly | |
7846 | sign-extended for the wider mode. Now, for ZERO_EXTEND, the | |
7847 | story is different. */ | |
7848 | else if (code == ZERO_EXTEND) | |
7849 | { | |
7850 | enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); | |
7851 | rtx new, r = known_cond (XEXP (x, 0), cond, reg, val); | |
7852 | ||
7853 | if (XEXP (x, 0) != r) | |
7854 | { | |
7855 | /* We must simplify the zero_extend here, before we lose | |
7856 | track of the original inner_mode. */ | |
7857 | new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
7858 | r, inner_mode); | |
7859 | if (new) | |
7860 | return new; | |
7861 | else | |
7862 | SUBST (XEXP (x, 0), r); | |
7863 | } | |
7864 | ||
7865 | return x; | |
7866 | } | |
1a26b032 RK |
7867 | |
7868 | fmt = GET_RTX_FORMAT (code); | |
7869 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7870 | { | |
7871 | if (fmt[i] == 'e') | |
7872 | SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); | |
7873 | else if (fmt[i] == 'E') | |
7874 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7875 | SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), | |
7876 | cond, reg, val)); | |
7877 | } | |
7878 | ||
7879 | return x; | |
7880 | } | |
7881 | \f | |
e11fa86f RK |
7882 | /* See if X and Y are equal for the purposes of seeing if we can rewrite an |
7883 | assignment as a field assignment. */ | |
7884 | ||
7885 | static int | |
79a490a9 | 7886 | rtx_equal_for_field_assignment_p (rtx x, rtx y) |
e11fa86f | 7887 | { |
e11fa86f RK |
7888 | if (x == y || rtx_equal_p (x, y)) |
7889 | return 1; | |
7890 | ||
7891 | if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) | |
7892 | return 0; | |
7893 | ||
7894 | /* Check for a paradoxical SUBREG of a MEM compared with the MEM. | |
7895 | Note that all SUBREGs of MEM are paradoxical; otherwise they | |
7896 | would have been rewritten. */ | |
3c0cb5de JQ |
7897 | if (MEM_P (x) && GET_CODE (y) == SUBREG |
7898 | && MEM_P (SUBREG_REG (y)) | |
e11fa86f | 7899 | && rtx_equal_p (SUBREG_REG (y), |
4de249d9 | 7900 | gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) |
e11fa86f RK |
7901 | return 1; |
7902 | ||
3c0cb5de JQ |
7903 | if (MEM_P (y) && GET_CODE (x) == SUBREG |
7904 | && MEM_P (SUBREG_REG (x)) | |
e11fa86f | 7905 | && rtx_equal_p (SUBREG_REG (x), |
4de249d9 | 7906 | gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) |
e11fa86f RK |
7907 | return 1; |
7908 | ||
9ec36da5 JL |
7909 | /* We used to see if get_last_value of X and Y were the same but that's |
7910 | not correct. In one direction, we'll cause the assignment to have | |
7911 | the wrong destination and in the case, we'll import a register into this | |
7912 | insn that might have already have been dead. So fail if none of the | |
7913 | above cases are true. */ | |
7914 | return 0; | |
e11fa86f RK |
7915 | } |
7916 | \f | |
230d793d RS |
7917 | /* See if X, a SET operation, can be rewritten as a bit-field assignment. |
7918 | Return that assignment if so. | |
7919 | ||
7920 | We only handle the most common cases. */ | |
7921 | ||
7922 | static rtx | |
79a490a9 | 7923 | make_field_assignment (rtx x) |
230d793d RS |
7924 | { |
7925 | rtx dest = SET_DEST (x); | |
7926 | rtx src = SET_SRC (x); | |
dfbe1b2f | 7927 | rtx assign; |
e11fa86f | 7928 | rtx rhs, lhs; |
5f4f0e22 | 7929 | HOST_WIDE_INT c1; |
770ae6cc RK |
7930 | HOST_WIDE_INT pos; |
7931 | unsigned HOST_WIDE_INT len; | |
dfbe1b2f RK |
7932 | rtx other; |
7933 | enum machine_mode mode; | |
230d793d RS |
7934 | |
7935 | /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
7936 | a clear of a one-bit field. We will have changed it to | |
7937 | (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
7938 | for a SUBREG. */ | |
7939 | ||
7940 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
7941 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT | |
7942 | && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 | |
e11fa86f | 7943 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
230d793d | 7944 | { |
8999a12e | 7945 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7946 | 1, 1, 1, 0); |
76184def | 7947 | if (assign != 0) |
38a448ca | 7948 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7949 | return x; |
230d793d RS |
7950 | } |
7951 | ||
55e79aef RH |
7952 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG |
7953 | && subreg_lowpart_p (XEXP (src, 0)) | |
7954 | && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) | |
7955 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) | |
7956 | && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
7957 | && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT | |
7958 | && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 | |
7959 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
230d793d | 7960 | { |
8999a12e | 7961 | assign = make_extraction (VOIDmode, dest, 0, |
230d793d RS |
7962 | XEXP (SUBREG_REG (XEXP (src, 0)), 1), |
7963 | 1, 1, 1, 0); | |
76184def | 7964 | if (assign != 0) |
38a448ca | 7965 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7966 | return x; |
230d793d RS |
7967 | } |
7968 | ||
9dd11dcb | 7969 | /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a |
230d793d | 7970 | one-bit field. */ |
55e79aef RH |
7971 | if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT |
7972 | && XEXP (XEXP (src, 0), 0) == const1_rtx | |
7973 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
230d793d | 7974 | { |
8999a12e | 7975 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7976 | 1, 1, 1, 0); |
76184def | 7977 | if (assign != 0) |
38a448ca | 7978 | return gen_rtx_SET (VOIDmode, assign, const1_rtx); |
76184def | 7979 | return x; |
230d793d RS |
7980 | } |
7981 | ||
55e79aef RH |
7982 | /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the |
7983 | SRC is an AND with all bits of that field set, then we can discard | |
7984 | the AND. */ | |
7985 | if (GET_CODE (dest) == ZERO_EXTRACT | |
7986 | && GET_CODE (XEXP (dest, 1)) == CONST_INT | |
7987 | && GET_CODE (src) == AND | |
7988 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
7989 | { | |
7990 | HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); | |
7991 | unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); | |
7992 | unsigned HOST_WIDE_INT ze_mask; | |
7993 | ||
7994 | if (width >= HOST_BITS_PER_WIDE_INT) | |
7995 | ze_mask = -1; | |
7996 | else | |
7997 | ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; | |
7998 | ||
7999 | /* Complete overlap. We can remove the source AND. */ | |
8000 | if ((and_mask & ze_mask) == ze_mask) | |
8001 | return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); | |
8002 | ||
8003 | /* Partial overlap. We can reduce the source AND. */ | |
8004 | if ((and_mask & ze_mask) != and_mask) | |
8005 | { | |
8006 | mode = GET_MODE (src); | |
8007 | src = gen_rtx_AND (mode, XEXP (src, 0), | |
eb2ab511 | 8008 | gen_int_mode (and_mask & ze_mask, mode)); |
55e79aef RH |
8009 | return gen_rtx_SET (VOIDmode, dest, src); |
8010 | } | |
8011 | } | |
8012 | ||
dfbe1b2f | 8013 | /* The other case we handle is assignments into a constant-position |
9dd11dcb | 8014 | field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents |
dfbe1b2f RK |
8015 | a mask that has all one bits except for a group of zero bits and |
8016 | OTHER is known to have zeros where C1 has ones, this is such an | |
8017 | assignment. Compute the position and length from C1. Shift OTHER | |
8018 | to the appropriate position, force it to the required mode, and | |
8019 | make the extraction. Check for the AND in both operands. */ | |
8020 | ||
9dd11dcb | 8021 | if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) |
e11fa86f RK |
8022 | return x; |
8023 | ||
8024 | rhs = expand_compound_operation (XEXP (src, 0)); | |
8025 | lhs = expand_compound_operation (XEXP (src, 1)); | |
8026 | ||
8027 | if (GET_CODE (rhs) == AND | |
8028 | && GET_CODE (XEXP (rhs, 1)) == CONST_INT | |
8029 | && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) | |
8030 | c1 = INTVAL (XEXP (rhs, 1)), other = lhs; | |
8031 | else if (GET_CODE (lhs) == AND | |
8032 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
8033 | && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) | |
8034 | c1 = INTVAL (XEXP (lhs, 1)), other = rhs; | |
dfbe1b2f RK |
8035 | else |
8036 | return x; | |
230d793d | 8037 | |
663522cb | 8038 | pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); |
dfbe1b2f | 8039 | if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) |
e5e809f4 JL |
8040 | || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT |
8041 | || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) | |
dfbe1b2f | 8042 | return x; |
230d793d | 8043 | |
5f4f0e22 | 8044 | assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); |
76184def DE |
8045 | if (assign == 0) |
8046 | return x; | |
230d793d | 8047 | |
dfbe1b2f RK |
8048 | /* The mode to use for the source is the mode of the assignment, or of |
8049 | what is inside a possible STRICT_LOW_PART. */ | |
663522cb | 8050 | mode = (GET_CODE (assign) == STRICT_LOW_PART |
dfbe1b2f | 8051 | ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); |
230d793d | 8052 | |
dfbe1b2f RK |
8053 | /* Shift OTHER right POS places and make it the source, restricting it |
8054 | to the proper length and mode. */ | |
230d793d | 8055 | |
5f4f0e22 CH |
8056 | src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, |
8057 | GET_MODE (src), other, pos), | |
6139ff20 RK |
8058 | mode, |
8059 | GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT | |
0345195a | 8060 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 8061 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 8062 | dest, 0); |
230d793d | 8063 | |
6e814b8d KH |
8064 | /* If SRC is masked by an AND that does not make a difference in |
8065 | the value being stored, strip it. */ | |
8066 | if (GET_CODE (assign) == ZERO_EXTRACT | |
8067 | && GET_CODE (XEXP (assign, 1)) == CONST_INT | |
8068 | && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT | |
8069 | && GET_CODE (src) == AND | |
8070 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
c5c15353 | 8071 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1)) |
6e814b8d KH |
8072 | == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)) |
8073 | src = XEXP (src, 0); | |
8074 | ||
f1c6ba8b | 8075 | return gen_rtx_SET (VOIDmode, assign, src); |
230d793d RS |
8076 | } |
8077 | \f | |
8078 | /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
8079 | if so. */ | |
8080 | ||
8081 | static rtx | |
79a490a9 | 8082 | apply_distributive_law (rtx x) |
230d793d RS |
8083 | { |
8084 | enum rtx_code code = GET_CODE (x); | |
2981fafe | 8085 | enum rtx_code inner_code; |
230d793d RS |
8086 | rtx lhs, rhs, other; |
8087 | rtx tem; | |
230d793d | 8088 | |
2981fafe RS |
8089 | /* Distributivity is not true for floating point as it can change the |
8090 | value. So we don't do it unless -funsafe-math-optimizations. */ | |
8091 | if (FLOAT_MODE_P (GET_MODE (x)) | |
8092 | && ! flag_unsafe_math_optimizations) | |
d8a8a4da RS |
8093 | return x; |
8094 | ||
230d793d RS |
8095 | /* The outer operation can only be one of the following: */ |
8096 | if (code != IOR && code != AND && code != XOR | |
8097 | && code != PLUS && code != MINUS) | |
8098 | return x; | |
8099 | ||
2981fafe RS |
8100 | lhs = XEXP (x, 0); |
8101 | rhs = XEXP (x, 1); | |
230d793d | 8102 | |
0f41302f MS |
8103 | /* If either operand is a primitive we can't do anything, so get out |
8104 | fast. */ | |
ec8e098d | 8105 | if (OBJECT_P (lhs) || OBJECT_P (rhs)) |
230d793d RS |
8106 | return x; |
8107 | ||
8108 | lhs = expand_compound_operation (lhs); | |
8109 | rhs = expand_compound_operation (rhs); | |
8110 | inner_code = GET_CODE (lhs); | |
8111 | if (inner_code != GET_CODE (rhs)) | |
8112 | return x; | |
8113 | ||
8114 | /* See if the inner and outer operations distribute. */ | |
8115 | switch (inner_code) | |
8116 | { | |
8117 | case LSHIFTRT: | |
8118 | case ASHIFTRT: | |
8119 | case AND: | |
8120 | case IOR: | |
8121 | /* These all distribute except over PLUS. */ | |
8122 | if (code == PLUS || code == MINUS) | |
8123 | return x; | |
8124 | break; | |
8125 | ||
8126 | case MULT: | |
8127 | if (code != PLUS && code != MINUS) | |
8128 | return x; | |
8129 | break; | |
8130 | ||
8131 | case ASHIFT: | |
45620ed4 | 8132 | /* This is also a multiply, so it distributes over everything. */ |
230d793d RS |
8133 | break; |
8134 | ||
8135 | case SUBREG: | |
1f2a3c8f ILT |
8136 | /* Non-paradoxical SUBREGs distributes over all operations, |
8137 | provided the inner modes and byte offsets are the same, this | |
8138 | is an extraction of a low-order part, we don't convert an fp | |
8139 | operation to int or vice versa, this is not a vector mode, | |
8140 | and we would not be converting a single-word operation into a | |
8141 | multi-word operation. The latter test is not required, but | |
8142 | it prevents generating unneeded multi-word operations. Some | |
8143 | of the previous tests are redundant given the latter test, | |
8144 | but are retained because they are required for correctness. | |
dfbe1b2f RK |
8145 | |
8146 | We produce the result slightly differently in this case. */ | |
8147 | ||
8148 | if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) | |
ddef6bc7 | 8149 | || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) |
dfbe1b2f | 8150 | || ! subreg_lowpart_p (lhs) |
2b4bd1bc JW |
8151 | || (GET_MODE_CLASS (GET_MODE (lhs)) |
8152 | != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) | |
dfbe1b2f | 8153 | || (GET_MODE_SIZE (GET_MODE (lhs)) |
8af24e26 | 8154 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) |
1f2a3c8f | 8155 | || VECTOR_MODE_P (GET_MODE (lhs)) |
dfbe1b2f | 8156 | || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) |
230d793d RS |
8157 | return x; |
8158 | ||
bcb34aa3 PB |
8159 | tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)), |
8160 | SUBREG_REG (lhs), SUBREG_REG (rhs)); | |
4de249d9 | 8161 | return gen_lowpart (GET_MODE (x), tem); |
230d793d RS |
8162 | |
8163 | default: | |
8164 | return x; | |
8165 | } | |
8166 | ||
8167 | /* Set LHS and RHS to the inner operands (A and B in the example | |
8168 | above) and set OTHER to the common operand (C in the example). | |
ec8e098d | 8169 | There is only one way to do this unless the inner operation is |
230d793d | 8170 | commutative. */ |
ec8e098d | 8171 | if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8172 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) |
8173 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
ec8e098d | 8174 | else if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8175 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) |
8176 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
ec8e098d | 8177 | else if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8178 | && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) |
8179 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
8180 | else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
8181 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
8182 | else | |
8183 | return x; | |
8184 | ||
8185 | /* Form the new inner operation, seeing if it simplifies first. */ | |
bcb34aa3 | 8186 | tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); |
230d793d RS |
8187 | |
8188 | /* There is one exception to the general way of distributing: | |
a0209ac2 | 8189 | (a | c) ^ (b | c) -> (a ^ b) & ~c */ |
230d793d RS |
8190 | if (code == XOR && inner_code == IOR) |
8191 | { | |
8192 | inner_code = AND; | |
f1c6ba8b | 8193 | other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); |
230d793d RS |
8194 | } |
8195 | ||
8196 | /* We may be able to continuing distributing the result, so call | |
8197 | ourselves recursively on the inner operation before forming the | |
8198 | outer operation, which we return. */ | |
bcb34aa3 PB |
8199 | return simplify_gen_binary (inner_code, GET_MODE (x), |
8200 | apply_distributive_law (tem), other); | |
8201 | } | |
8202 | ||
8203 | /* See if X is of the form (* (+ A B) C), and if so convert to | |
8204 | (+ (* A C) (* B C)) and try to simplify. | |
8205 | ||
8206 | Most of the time, this results in no change. However, if some of | |
8207 | the operands are the same or inverses of each other, simplifications | |
8208 | will result. | |
8209 | ||
8210 | For example, (and (ior A B) (not B)) can occur as the result of | |
8211 | expanding a bit field assignment. When we apply the distributive | |
8212 | law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
8213 | which then simplifies to (and (A (not B))). | |
8214 | ||
8215 | Note that no checks happen on the validity of applying the inverse | |
8216 | distributive law. This is pointless since we can do it in the | |
8217 | few places where this routine is called. | |
8218 | ||
8219 | N is the index of the term that is decomposed (the arithmetic operation, | |
8220 | i.e. (+ A B) in the first example above). !N is the index of the term that | |
8221 | is distributed, i.e. of C in the first example above. */ | |
8222 | static rtx | |
8223 | distribute_and_simplify_rtx (rtx x, int n) | |
8224 | { | |
8225 | enum machine_mode mode; | |
8226 | enum rtx_code outer_code, inner_code; | |
8227 | rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; | |
8228 | ||
8229 | decomposed = XEXP (x, n); | |
8230 | if (!ARITHMETIC_P (decomposed)) | |
8231 | return NULL_RTX; | |
8232 | ||
8233 | mode = GET_MODE (x); | |
8234 | outer_code = GET_CODE (x); | |
8235 | distributed = XEXP (x, !n); | |
8236 | ||
8237 | inner_code = GET_CODE (decomposed); | |
8238 | inner_op0 = XEXP (decomposed, 0); | |
8239 | inner_op1 = XEXP (decomposed, 1); | |
8240 | ||
8241 | /* Special case (and (xor B C) (not A)), which is equivalent to | |
8242 | (xor (ior A B) (ior A C)) */ | |
8243 | if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) | |
8244 | { | |
8245 | distributed = XEXP (distributed, 0); | |
8246 | outer_code = IOR; | |
8247 | } | |
8248 | ||
8249 | if (n == 0) | |
8250 | { | |
8251 | /* Distribute the second term. */ | |
8252 | new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); | |
8253 | new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); | |
8254 | } | |
8255 | else | |
8256 | { | |
8257 | /* Distribute the first term. */ | |
8258 | new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); | |
8259 | new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); | |
8260 | } | |
8261 | ||
8262 | tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, | |
8263 | new_op0, new_op1)); | |
8264 | if (GET_CODE (tmp) != outer_code | |
8265 | && rtx_cost (tmp, SET) < rtx_cost (x, SET)) | |
8266 | return tmp; | |
8267 | ||
8268 | return NULL_RTX; | |
230d793d RS |
8269 | } |
8270 | \f | |
8271 | /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
8272 | in MODE. | |
8273 | ||
8274 | Return an equivalent form, if different from X. Otherwise, return X. If | |
8275 | X is zero, we are to always construct the equivalent form. */ | |
8276 | ||
8277 | static rtx | |
79a490a9 AJ |
8278 | simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop, |
8279 | unsigned HOST_WIDE_INT constop) | |
230d793d | 8280 | { |
951553af | 8281 | unsigned HOST_WIDE_INT nonzero; |
42301240 | 8282 | int i; |
230d793d | 8283 | |
6139ff20 | 8284 | /* Simplify VAROP knowing that we will be only looking at some of the |
8bc52806 JL |
8285 | bits in it. |
8286 | ||
8287 | Note by passing in CONSTOP, we guarantee that the bits not set in | |
8288 | CONSTOP are not significant and will never be examined. We must | |
8289 | ensure that is the case by explicitly masking out those bits | |
8290 | before returning. */ | |
e3d616e3 | 8291 | varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); |
230d793d | 8292 | |
8bc52806 JL |
8293 | /* If VAROP is a CLOBBER, we will fail so return it. */ |
8294 | if (GET_CODE (varop) == CLOBBER) | |
6139ff20 | 8295 | return varop; |
230d793d | 8296 | |
8bc52806 JL |
8297 | /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP |
8298 | to VAROP and return the new constant. */ | |
8299 | if (GET_CODE (varop) == CONST_INT) | |
bb80db7b | 8300 | return gen_int_mode (INTVAL (varop) & constop, mode); |
8bc52806 | 8301 | |
fc06d7aa RK |
8302 | /* See what bits may be nonzero in VAROP. Unlike the general case of |
8303 | a call to nonzero_bits, here we don't care about bits outside | |
8304 | MODE. */ | |
8305 | ||
8306 | nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); | |
9fa6d012 | 8307 | |
230d793d | 8308 | /* Turn off all bits in the constant that are known to already be zero. |
951553af | 8309 | Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS |
230d793d RS |
8310 | which is tested below. */ |
8311 | ||
951553af | 8312 | constop &= nonzero; |
230d793d RS |
8313 | |
8314 | /* If we don't have any bits left, return zero. */ | |
8315 | if (constop == 0) | |
8316 | return const0_rtx; | |
8317 | ||
42301240 | 8318 | /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is |
e0a2f705 | 8319 | a power of two, we can replace this with an ASHIFT. */ |
42301240 RK |
8320 | if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 |
8321 | && (i = exact_log2 (constop)) >= 0) | |
8322 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); | |
663522cb | 8323 | |
6139ff20 RK |
8324 | /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR |
8325 | or XOR, then try to apply the distributive law. This may eliminate | |
8326 | operations if either branch can be simplified because of the AND. | |
8327 | It may also make some cases more complex, but those cases probably | |
8328 | won't match a pattern either with or without this. */ | |
8329 | ||
8330 | if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) | |
8331 | return | |
4de249d9 | 8332 | gen_lowpart |
6139ff20 RK |
8333 | (mode, |
8334 | apply_distributive_law | |
bcb34aa3 PB |
8335 | (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), |
8336 | simplify_and_const_int (NULL_RTX, | |
8337 | GET_MODE (varop), | |
8338 | XEXP (varop, 0), | |
8339 | constop), | |
8340 | simplify_and_const_int (NULL_RTX, | |
8341 | GET_MODE (varop), | |
8342 | XEXP (varop, 1), | |
8343 | constop)))); | |
6139ff20 | 8344 | |
8deb7514 RH |
8345 | /* If VAROP is PLUS, and the constant is a mask of low bite, distribute |
8346 | the AND and see if one of the operands simplifies to zero. If so, we | |
8347 | may eliminate it. */ | |
8348 | ||
8349 | if (GET_CODE (varop) == PLUS | |
8350 | && exact_log2 (constop + 1) >= 0) | |
8351 | { | |
8352 | rtx o0, o1; | |
8353 | ||
8354 | o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); | |
8355 | o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); | |
8356 | if (o0 == const0_rtx) | |
8357 | return o1; | |
8358 | if (o1 == const0_rtx) | |
8359 | return o0; | |
8360 | } | |
8361 | ||
230d793d RS |
8362 | /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG |
8363 | if we already had one (just check for the simplest cases). */ | |
8364 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
8365 | && GET_MODE (XEXP (x, 0)) == mode | |
8366 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
8367 | varop = XEXP (x, 0); | |
8368 | else | |
4de249d9 | 8369 | varop = gen_lowpart (mode, varop); |
230d793d | 8370 | |
0f41302f | 8371 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
8372 | if (GET_CODE (varop) == CLOBBER) |
8373 | return x ? x : varop; | |
8374 | ||
8375 | /* If we are only masking insignificant bits, return VAROP. */ | |
951553af | 8376 | if (constop == nonzero) |
230d793d | 8377 | x = varop; |
230d793d RS |
8378 | else |
8379 | { | |
d0c9db30 | 8380 | /* Otherwise, return an AND. */ |
3b5708e7 | 8381 | constop = trunc_int_for_mode (constop, mode); |
d0c9db30 AM |
8382 | /* See how much, if any, of X we can use. */ |
8383 | if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) | |
bcb34aa3 | 8384 | x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop)); |
230d793d | 8385 | |
d0c9db30 AM |
8386 | else |
8387 | { | |
8388 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
8389 | || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) | |
8390 | SUBST (XEXP (x, 1), GEN_INT (constop)); | |
8391 | ||
8392 | SUBST (XEXP (x, 0), varop); | |
8393 | } | |
230d793d RS |
8394 | } |
8395 | ||
8396 | return x; | |
8397 | } | |
8398 | \f | |
2f93eea8 | 8399 | /* Given a REG, X, compute which bits in X can be nonzero. |
230d793d RS |
8400 | We don't care about bits outside of those defined in MODE. |
8401 | ||
8402 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
8403 | a shift, AND, or zero_extract, we can do better. */ | |
8404 | ||
2f93eea8 PB |
8405 | static rtx |
8406 | reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode, | |
8407 | rtx known_x ATTRIBUTE_UNUSED, | |
8408 | enum machine_mode known_mode ATTRIBUTE_UNUSED, | |
8409 | unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, | |
8410 | unsigned HOST_WIDE_INT *nonzero) | |
230d793d | 8411 | { |
230d793d RS |
8412 | rtx tem; |
8413 | ||
2f93eea8 PB |
8414 | /* If X is a register whose nonzero bits value is current, use it. |
8415 | Otherwise, if X is a register whose value we can find, use that | |
8416 | value. Otherwise, use the previously-computed global nonzero bits | |
8417 | for this register. */ | |
8418 | ||
8419 | if (reg_stat[REGNO (x)].last_set_value != 0 | |
8420 | && (reg_stat[REGNO (x)].last_set_mode == mode | |
8421 | || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT | |
8422 | && GET_MODE_CLASS (mode) == MODE_INT)) | |
8423 | && (reg_stat[REGNO (x)].last_set_label == label_tick | |
8424 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8425 | && REG_N_SETS (REGNO (x)) == 1 | |
5e2d947c JH |
8426 | && ! REGNO_REG_SET_P |
8427 | (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, | |
8428 | REGNO (x)))) | |
2f93eea8 | 8429 | && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) |
230d793d | 8430 | { |
2f93eea8 PB |
8431 | *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits; |
8432 | return NULL; | |
230d793d RS |
8433 | } |
8434 | ||
2f93eea8 | 8435 | tem = get_last_value (x); |
230d793d | 8436 | |
2f93eea8 | 8437 | if (tem) |
0840fd91 | 8438 | { |
9afa3d54 | 8439 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND |
2f93eea8 PB |
8440 | /* If X is narrower than MODE and TEM is a non-negative |
8441 | constant that would appear negative in the mode of X, | |
8442 | sign-extend it for use in reg_nonzero_bits because some | |
8443 | machines (maybe most) will actually do the sign-extension | |
8444 | and this is the conservative approach. | |
8445 | ||
8446 | ??? For 2.5, try to tighten up the MD files in this regard | |
8447 | instead of this kludge. */ | |
8448 | ||
8449 | if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode) | |
8450 | && GET_CODE (tem) == CONST_INT | |
8451 | && INTVAL (tem) > 0 | |
8452 | && 0 != (INTVAL (tem) | |
8453 | & ((HOST_WIDE_INT) 1 | |
8454 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) | |
8455 | tem = GEN_INT (INTVAL (tem) | |
8456 | | ((HOST_WIDE_INT) (-1) | |
8457 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
230d793d | 8458 | #endif |
2f93eea8 | 8459 | return tem; |
230d793d | 8460 | } |
2f93eea8 | 8461 | else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits) |
8fd73754 | 8462 | { |
2f93eea8 | 8463 | unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits; |
8fd73754 | 8464 | |
2f93eea8 PB |
8465 | if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)) |
8466 | /* We don't know anything about the upper bits. */ | |
8467 | mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); | |
8468 | *nonzero &= mask; | |
8fd73754 AN |
8469 | } |
8470 | ||
2f93eea8 | 8471 | return NULL; |
8fd73754 AN |
8472 | } |
8473 | ||
d0ab8cd3 | 8474 | /* Return the number of bits at the high-order end of X that are known to |
5109d49f RK |
8475 | be equal to the sign bit. X will be used in mode MODE; if MODE is |
8476 | VOIDmode, X will be used in its own mode. The returned value will always | |
8477 | be between 1 and the number of bits in MODE. */ | |
d0ab8cd3 | 8478 | |
2f93eea8 PB |
8479 | static rtx |
8480 | reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode, | |
8481 | rtx known_x ATTRIBUTE_UNUSED, | |
8482 | enum machine_mode known_mode | |
8483 | ATTRIBUTE_UNUSED, | |
8484 | unsigned int known_ret ATTRIBUTE_UNUSED, | |
8485 | unsigned int *result) | |
d0ab8cd3 | 8486 | { |
d0ab8cd3 RK |
8487 | rtx tem; |
8488 | ||
2f93eea8 PB |
8489 | if (reg_stat[REGNO (x)].last_set_value != 0 |
8490 | && reg_stat[REGNO (x)].last_set_mode == mode | |
8491 | && (reg_stat[REGNO (x)].last_set_label == label_tick | |
8492 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8493 | && REG_N_SETS (REGNO (x)) == 1 | |
5e2d947c JH |
8494 | && ! REGNO_REG_SET_P |
8495 | (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, | |
8496 | REGNO (x)))) | |
2f93eea8 | 8497 | && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) |
770ae6cc | 8498 | { |
2f93eea8 PB |
8499 | *result = reg_stat[REGNO (x)].last_set_sign_bit_copies; |
8500 | return NULL; | |
d0ab8cd3 RK |
8501 | } |
8502 | ||
2f93eea8 PB |
8503 | tem = get_last_value (x); |
8504 | if (tem != 0) | |
8505 | return tem; | |
d0ab8cd3 | 8506 | |
2f93eea8 PB |
8507 | if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0 |
8508 | && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode)) | |
8509 | *result = reg_stat[REGNO (x)].sign_bit_copies; | |
8510 | ||
8511 | return NULL; | |
d0ab8cd3 RK |
8512 | } |
8513 | \f | |
1a26b032 RK |
8514 | /* Return the number of "extended" bits there are in X, when interpreted |
8515 | as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For | |
8516 | unsigned quantities, this is the number of high-order zero bits. | |
8517 | For signed quantities, this is the number of copies of the sign bit | |
8518 | minus 1. In both case, this function returns the number of "spare" | |
8519 | bits. For example, if two quantities for which this function returns | |
8520 | at least 1 are added, the addition is known not to overflow. | |
8521 | ||
8522 | This function will always return 0 unless called during combine, which | |
8523 | implies that it must be called from a define_split. */ | |
8524 | ||
770ae6cc | 8525 | unsigned int |
79a490a9 | 8526 | extended_count (rtx x, enum machine_mode mode, int unsignedp) |
1a26b032 | 8527 | { |
951553af | 8528 | if (nonzero_sign_valid == 0) |
1a26b032 RK |
8529 | return 0; |
8530 | ||
8531 | return (unsignedp | |
ac49a949 | 8532 | ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
26c34780 RS |
8533 | ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1 |
8534 | - floor_log2 (nonzero_bits (x, mode))) | |
770ae6cc | 8535 | : 0) |
1a26b032 RK |
8536 | : num_sign_bit_copies (x, mode) - 1); |
8537 | } | |
8538 | \f | |
230d793d RS |
8539 | /* This function is called from `simplify_shift_const' to merge two |
8540 | outer operations. Specifically, we have already found that we need | |
8541 | to perform operation *POP0 with constant *PCONST0 at the outermost | |
8542 | position. We would now like to also perform OP1 with constant CONST1 | |
8543 | (with *POP0 being done last). | |
8544 | ||
8545 | Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
663522cb | 8546 | the resulting operation. *PCOMP_P is set to 1 if we would need to |
230d793d RS |
8547 | complement the innermost operand, otherwise it is unchanged. |
8548 | ||
8549 | MODE is the mode in which the operation will be done. No bits outside | |
8550 | the width of this mode matter. It is assumed that the width of this mode | |
5f4f0e22 | 8551 | is smaller than or equal to HOST_BITS_PER_WIDE_INT. |
230d793d | 8552 | |
f822d252 | 8553 | If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, |
230d793d RS |
8554 | IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper |
8555 | result is simply *PCONST0. | |
8556 | ||
8557 | If the resulting operation cannot be expressed as one operation, we | |
8558 | return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
8559 | ||
8560 | static int | |
79a490a9 | 8561 | merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p) |
230d793d RS |
8562 | { |
8563 | enum rtx_code op0 = *pop0; | |
5f4f0e22 | 8564 | HOST_WIDE_INT const0 = *pconst0; |
230d793d RS |
8565 | |
8566 | const0 &= GET_MODE_MASK (mode); | |
8567 | const1 &= GET_MODE_MASK (mode); | |
8568 | ||
8569 | /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
8570 | if (op0 == AND) | |
8571 | const1 &= const0; | |
8572 | ||
f822d252 | 8573 | /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or |
230d793d RS |
8574 | if OP0 is SET. */ |
8575 | ||
f822d252 | 8576 | if (op1 == UNKNOWN || op0 == SET) |
230d793d RS |
8577 | return 1; |
8578 | ||
f822d252 | 8579 | else if (op0 == UNKNOWN) |
230d793d RS |
8580 | op0 = op1, const0 = const1; |
8581 | ||
8582 | else if (op0 == op1) | |
8583 | { | |
8584 | switch (op0) | |
8585 | { | |
8586 | case AND: | |
8587 | const0 &= const1; | |
8588 | break; | |
8589 | case IOR: | |
8590 | const0 |= const1; | |
8591 | break; | |
8592 | case XOR: | |
8593 | const0 ^= const1; | |
8594 | break; | |
8595 | case PLUS: | |
8596 | const0 += const1; | |
8597 | break; | |
8598 | case NEG: | |
f822d252 | 8599 | op0 = UNKNOWN; |
230d793d | 8600 | break; |
e9a25f70 JL |
8601 | default: |
8602 | break; | |
230d793d RS |
8603 | } |
8604 | } | |
8605 | ||
8606 | /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
8607 | else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
8608 | return 0; | |
8609 | ||
8610 | /* If the two constants aren't the same, we can't do anything. The | |
8611 | remaining six cases can all be done. */ | |
8612 | else if (const0 != const1) | |
8613 | return 0; | |
8614 | ||
8615 | else | |
8616 | switch (op0) | |
8617 | { | |
8618 | case IOR: | |
8619 | if (op1 == AND) | |
8620 | /* (a & b) | b == b */ | |
8621 | op0 = SET; | |
8622 | else /* op1 == XOR */ | |
8623 | /* (a ^ b) | b == a | b */ | |
b729186a | 8624 | {;} |
230d793d RS |
8625 | break; |
8626 | ||
8627 | case XOR: | |
8628 | if (op1 == AND) | |
8629 | /* (a & b) ^ b == (~a) & b */ | |
8630 | op0 = AND, *pcomp_p = 1; | |
8631 | else /* op1 == IOR */ | |
8632 | /* (a | b) ^ b == a & ~b */ | |
7d4444ea | 8633 | op0 = AND, const0 = ~const0; |
230d793d RS |
8634 | break; |
8635 | ||
8636 | case AND: | |
8637 | if (op1 == IOR) | |
8638 | /* (a | b) & b == b */ | |
8639 | op0 = SET; | |
8640 | else /* op1 == XOR */ | |
8641 | /* (a ^ b) & b) == (~a) & b */ | |
8642 | *pcomp_p = 1; | |
8643 | break; | |
e9a25f70 JL |
8644 | default: |
8645 | break; | |
230d793d RS |
8646 | } |
8647 | ||
8648 | /* Check for NO-OP cases. */ | |
8649 | const0 &= GET_MODE_MASK (mode); | |
8650 | if (const0 == 0 | |
8651 | && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
f822d252 | 8652 | op0 = UNKNOWN; |
230d793d RS |
8653 | else if (const0 == 0 && op0 == AND) |
8654 | op0 = SET; | |
e51712db KG |
8655 | else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) |
8656 | && op0 == AND) | |
f822d252 | 8657 | op0 = UNKNOWN; |
230d793d | 8658 | |
7e4ce834 RH |
8659 | /* ??? Slightly redundant with the above mask, but not entirely. |
8660 | Moving this above means we'd have to sign-extend the mode mask | |
8661 | for the final test. */ | |
8662 | const0 = trunc_int_for_mode (const0, mode); | |
9fa6d012 | 8663 | |
230d793d RS |
8664 | *pop0 = op0; |
8665 | *pconst0 = const0; | |
8666 | ||
8667 | return 1; | |
8668 | } | |
8669 | \f | |
8670 | /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
da7d8304 | 8671 | The result of the shift is RESULT_MODE. X, if nonzero, is an expression |
230d793d RS |
8672 | that we started with. |
8673 | ||
8674 | The shift is normally computed in the widest mode we find in VAROP, as | |
8675 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
8676 | are ASHIFTRT and ROTATE, which are always done in their original mode, */ | |
8677 | ||
8678 | static rtx | |
79a490a9 AJ |
8679 | simplify_shift_const (rtx x, enum rtx_code code, |
8680 | enum machine_mode result_mode, rtx varop, | |
8681 | int orig_count) | |
230d793d RS |
8682 | { |
8683 | enum rtx_code orig_code = code; | |
770ae6cc RK |
8684 | unsigned int count; |
8685 | int signed_count; | |
230d793d RS |
8686 | enum machine_mode mode = result_mode; |
8687 | enum machine_mode shift_mode, tmode; | |
770ae6cc | 8688 | unsigned int mode_words |
230d793d RS |
8689 | = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; |
8690 | /* We form (outer_op (code varop count) (outer_const)). */ | |
f822d252 | 8691 | enum rtx_code outer_op = UNKNOWN; |
c4e861e8 | 8692 | HOST_WIDE_INT outer_const = 0; |
230d793d RS |
8693 | rtx const_rtx; |
8694 | int complement_p = 0; | |
8695 | rtx new; | |
8696 | ||
0051b6ca RH |
8697 | /* Make sure and truncate the "natural" shift on the way in. We don't |
8698 | want to do this inside the loop as it makes it more difficult to | |
8699 | combine shifts. */ | |
0051b6ca RH |
8700 | if (SHIFT_COUNT_TRUNCATED) |
8701 | orig_count &= GET_MODE_BITSIZE (mode) - 1; | |
0051b6ca | 8702 | |
230d793d RS |
8703 | /* If we were given an invalid count, don't do anything except exactly |
8704 | what was requested. */ | |
8705 | ||
0051b6ca | 8706 | if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) |
230d793d RS |
8707 | { |
8708 | if (x) | |
8709 | return x; | |
8710 | ||
0051b6ca | 8711 | return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count)); |
230d793d RS |
8712 | } |
8713 | ||
0051b6ca | 8714 | count = orig_count; |
853d8828 | 8715 | |
230d793d RS |
8716 | /* Unless one of the branches of the `if' in this loop does a `continue', |
8717 | we will `break' the loop after the `if'. */ | |
8718 | ||
8719 | while (count != 0) | |
8720 | { | |
8721 | /* If we have an operand of (clobber (const_int 0)), just return that | |
8722 | value. */ | |
8723 | if (GET_CODE (varop) == CLOBBER) | |
8724 | return varop; | |
8725 | ||
8726 | /* If we discovered we had to complement VAROP, leave. Making a NOT | |
8727 | here would cause an infinite loop. */ | |
8728 | if (complement_p) | |
8729 | break; | |
8730 | ||
abc95ed3 | 8731 | /* Convert ROTATERT to ROTATE. */ |
230d793d | 8732 | if (code == ROTATERT) |
ad9df12f IS |
8733 | { |
8734 | unsigned int bitsize = GET_MODE_BITSIZE (result_mode);; | |
8735 | code = ROTATE; | |
8736 | if (VECTOR_MODE_P (result_mode)) | |
8737 | count = bitsize / GET_MODE_NUNITS (result_mode) - count; | |
8738 | else | |
8739 | count = bitsize - count; | |
8740 | } | |
230d793d | 8741 | |
230d793d | 8742 | /* We need to determine what mode we will do the shift in. If the |
f6789c77 RK |
8743 | shift is a right shift or a ROTATE, we must always do it in the mode |
8744 | it was originally done in. Otherwise, we can do it in MODE, the | |
0f41302f | 8745 | widest mode encountered. */ |
f6789c77 RK |
8746 | shift_mode |
8747 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
8748 | ? result_mode : mode); | |
230d793d RS |
8749 | |
8750 | /* Handle cases where the count is greater than the size of the mode | |
853d8828 RH |
8751 | minus 1. For ASHIFT, use the size minus one as the count (this can |
8752 | occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
8753 | take the count modulo the size. For other shifts, the result is | |
8754 | zero. | |
230d793d RS |
8755 | |
8756 | Since these shifts are being produced by the compiler by combining | |
8757 | multiple operations, each of which are defined, we know what the | |
8758 | result is supposed to be. */ | |
663522cb | 8759 | |
26c34780 | 8760 | if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1)) |
230d793d RS |
8761 | { |
8762 | if (code == ASHIFTRT) | |
8763 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
8764 | else if (code == ROTATE || code == ROTATERT) | |
8765 | count %= GET_MODE_BITSIZE (shift_mode); | |
8766 | else | |
8767 | { | |
8768 | /* We can't simply return zero because there may be an | |
8769 | outer op. */ | |
8770 | varop = const0_rtx; | |
8771 | count = 0; | |
8772 | break; | |
8773 | } | |
8774 | } | |
8775 | ||
312def2e RK |
8776 | /* An arithmetic right shift of a quantity known to be -1 or 0 |
8777 | is a no-op. */ | |
8778 | if (code == ASHIFTRT | |
8779 | && (num_sign_bit_copies (varop, shift_mode) | |
8780 | == GET_MODE_BITSIZE (shift_mode))) | |
d0ab8cd3 | 8781 | { |
312def2e RK |
8782 | count = 0; |
8783 | break; | |
8784 | } | |
d0ab8cd3 | 8785 | |
312def2e RK |
8786 | /* If we are doing an arithmetic right shift and discarding all but |
8787 | the sign bit copies, this is equivalent to doing a shift by the | |
8788 | bitsize minus one. Convert it into that shift because it will often | |
8789 | allow other simplifications. */ | |
500c518b | 8790 | |
312def2e RK |
8791 | if (code == ASHIFTRT |
8792 | && (count + num_sign_bit_copies (varop, shift_mode) | |
8793 | >= GET_MODE_BITSIZE (shift_mode))) | |
8794 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
500c518b | 8795 | |
230d793d RS |
8796 | /* We simplify the tests below and elsewhere by converting |
8797 | ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
e0a2f705 KH |
8798 | `make_compound_operation' will convert it to an ASHIFTRT for |
8799 | those machines (such as VAX) that don't have an LSHIFTRT. */ | |
5f4f0e22 | 8800 | if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 8801 | && code == ASHIFTRT |
951553af | 8802 | && ((nonzero_bits (varop, shift_mode) |
5f4f0e22 CH |
8803 | & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) |
8804 | == 0)) | |
230d793d RS |
8805 | code = LSHIFTRT; |
8806 | ||
b9422b69 JH |
8807 | if (code == LSHIFTRT |
8808 | && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
8809 | && !(nonzero_bits (varop, shift_mode) >> count)) | |
2d21f7d6 | 8810 | varop = const0_rtx; |
b9422b69 JH |
8811 | if (code == ASHIFT |
8812 | && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
8813 | && !((nonzero_bits (varop, shift_mode) << count) | |
8814 | & GET_MODE_MASK (shift_mode))) | |
2d21f7d6 | 8815 | varop = const0_rtx; |
b9422b69 | 8816 | |
230d793d RS |
8817 | switch (GET_CODE (varop)) |
8818 | { | |
8819 | case SIGN_EXTEND: | |
8820 | case ZERO_EXTEND: | |
8821 | case SIGN_EXTRACT: | |
8822 | case ZERO_EXTRACT: | |
8823 | new = expand_compound_operation (varop); | |
8824 | if (new != varop) | |
8825 | { | |
8826 | varop = new; | |
8827 | continue; | |
8828 | } | |
8829 | break; | |
8830 | ||
8831 | case MEM: | |
8832 | /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
8833 | minus the width of a smaller mode, we can do this with a | |
8834 | SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
8835 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
8836 | && ! mode_dependent_address_p (XEXP (varop, 0)) | |
8837 | && ! MEM_VOLATILE_P (varop) | |
8838 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
8839 | MODE_INT, 1)) != BLKmode) | |
8840 | { | |
f1ec5147 RK |
8841 | new = adjust_address_nv (varop, tmode, |
8842 | BYTES_BIG_ENDIAN ? 0 | |
8843 | : count / BITS_PER_UNIT); | |
bf49b139 | 8844 | |
f1c6ba8b RK |
8845 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
8846 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
8847 | count = 0; |
8848 | continue; | |
8849 | } | |
8850 | break; | |
8851 | ||
8852 | case USE: | |
8853 | /* Similar to the case above, except that we can only do this if | |
8854 | the resulting mode is the same as that of the underlying | |
8855 | MEM and adjust the address depending on the *bits* endianness | |
8856 | because of the way that bit-field extract insns are defined. */ | |
8857 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
8858 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
8859 | MODE_INT, 1)) != BLKmode | |
8860 | && tmode == GET_MODE (XEXP (varop, 0))) | |
8861 | { | |
f76b9db2 ILT |
8862 | if (BITS_BIG_ENDIAN) |
8863 | new = XEXP (varop, 0); | |
8864 | else | |
8865 | { | |
8866 | new = copy_rtx (XEXP (varop, 0)); | |
663522cb | 8867 | SUBST (XEXP (new, 0), |
f76b9db2 ILT |
8868 | plus_constant (XEXP (new, 0), |
8869 | count / BITS_PER_UNIT)); | |
8870 | } | |
230d793d | 8871 | |
f1c6ba8b RK |
8872 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
8873 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
8874 | count = 0; |
8875 | continue; | |
8876 | } | |
8877 | break; | |
8878 | ||
8879 | case SUBREG: | |
8880 | /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
8881 | the same number of words as what we've seen so far. Then store | |
8882 | the widest mode in MODE. */ | |
f9e67232 RS |
8883 | if (subreg_lowpart_p (varop) |
8884 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
8885 | > GET_MODE_SIZE (GET_MODE (varop))) | |
26c34780 RS |
8886 | && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) |
8887 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
8888 | == mode_words) | |
230d793d RS |
8889 | { |
8890 | varop = SUBREG_REG (varop); | |
8891 | if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
8892 | mode = GET_MODE (varop); | |
8893 | continue; | |
8894 | } | |
8895 | break; | |
8896 | ||
8897 | case MULT: | |
8898 | /* Some machines use MULT instead of ASHIFT because MULT | |
8899 | is cheaper. But it is still better on those machines to | |
8900 | merge two shifts into one. */ | |
8901 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8902 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
8903 | { | |
770ae6cc | 8904 | varop |
bcb34aa3 PB |
8905 | = simplify_gen_binary (ASHIFT, GET_MODE (varop), |
8906 | XEXP (varop, 0), | |
8907 | GEN_INT (exact_log2 ( | |
8908 | INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
8909 | continue; |
8910 | } | |
8911 | break; | |
8912 | ||
8913 | case UDIV: | |
8914 | /* Similar, for when divides are cheaper. */ | |
8915 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8916 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
8917 | { | |
770ae6cc | 8918 | varop |
bcb34aa3 PB |
8919 | = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), |
8920 | XEXP (varop, 0), | |
8921 | GEN_INT (exact_log2 ( | |
8922 | INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
8923 | continue; |
8924 | } | |
8925 | break; | |
8926 | ||
8927 | case ASHIFTRT: | |
8f8d8d6e AO |
8928 | /* If we are extracting just the sign bit of an arithmetic |
8929 | right shift, that shift is not needed. However, the sign | |
8930 | bit of a wider mode may be different from what would be | |
8931 | interpreted as the sign bit in a narrower mode, so, if | |
8932 | the result is narrower, don't discard the shift. */ | |
26c34780 RS |
8933 | if (code == LSHIFTRT |
8934 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
8f8d8d6e AO |
8935 | && (GET_MODE_BITSIZE (result_mode) |
8936 | >= GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
8937 | { |
8938 | varop = XEXP (varop, 0); | |
8939 | continue; | |
8940 | } | |
8941 | ||
0f41302f | 8942 | /* ... fall through ... */ |
230d793d RS |
8943 | |
8944 | case LSHIFTRT: | |
8945 | case ASHIFT: | |
230d793d RS |
8946 | case ROTATE: |
8947 | /* Here we have two nested shifts. The result is usually the | |
8948 | AND of a new shift with a mask. We compute the result below. */ | |
8949 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8950 | && INTVAL (XEXP (varop, 1)) >= 0 | |
8951 | && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) | |
5f4f0e22 CH |
8952 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
8953 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d RS |
8954 | { |
8955 | enum rtx_code first_code = GET_CODE (varop); | |
770ae6cc | 8956 | unsigned int first_count = INTVAL (XEXP (varop, 1)); |
5f4f0e22 | 8957 | unsigned HOST_WIDE_INT mask; |
230d793d | 8958 | rtx mask_rtx; |
230d793d | 8959 | |
230d793d RS |
8960 | /* We have one common special case. We can't do any merging if |
8961 | the inner code is an ASHIFTRT of a smaller mode. However, if | |
8962 | we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
8963 | with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
8964 | we can convert it to | |
8965 | (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). | |
8966 | This simplifies certain SIGN_EXTEND operations. */ | |
8967 | if (code == ASHIFT && first_code == ASHIFTRT | |
26c34780 RS |
8968 | && count == (unsigned int) |
8969 | (GET_MODE_BITSIZE (result_mode) | |
8970 | - GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
8971 | { |
8972 | /* C3 has the low-order C1 bits zero. */ | |
663522cb | 8973 | |
5f4f0e22 | 8974 | mask = (GET_MODE_MASK (mode) |
663522cb | 8975 | & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); |
230d793d | 8976 | |
5f4f0e22 | 8977 | varop = simplify_and_const_int (NULL_RTX, result_mode, |
230d793d | 8978 | XEXP (varop, 0), mask); |
5f4f0e22 | 8979 | varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, |
230d793d RS |
8980 | varop, count); |
8981 | count = first_count; | |
8982 | code = ASHIFTRT; | |
8983 | continue; | |
8984 | } | |
663522cb | 8985 | |
d0ab8cd3 RK |
8986 | /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more |
8987 | than C1 high-order bits equal to the sign bit, we can convert | |
e0a2f705 | 8988 | this to either an ASHIFT or an ASHIFTRT depending on the |
663522cb | 8989 | two counts. |
230d793d RS |
8990 | |
8991 | We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
8992 | ||
8993 | if (code == ASHIFTRT && first_code == ASHIFT | |
8994 | && GET_MODE (varop) == shift_mode | |
d0ab8cd3 RK |
8995 | && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) |
8996 | > first_count)) | |
230d793d | 8997 | { |
d0ab8cd3 | 8998 | varop = XEXP (varop, 0); |
770ae6cc RK |
8999 | |
9000 | signed_count = count - first_count; | |
9001 | if (signed_count < 0) | |
663522cb | 9002 | count = -signed_count, code = ASHIFT; |
770ae6cc RK |
9003 | else |
9004 | count = signed_count; | |
9005 | ||
d0ab8cd3 | 9006 | continue; |
230d793d RS |
9007 | } |
9008 | ||
9009 | /* There are some cases we can't do. If CODE is ASHIFTRT, | |
9010 | we can only do this if FIRST_CODE is also ASHIFTRT. | |
9011 | ||
9012 | We can't do the case when CODE is ROTATE and FIRST_CODE is | |
9013 | ASHIFTRT. | |
9014 | ||
9015 | If the mode of this shift is not the mode of the outer shift, | |
bdaae9a0 | 9016 | we can't do this if either shift is a right shift or ROTATE. |
230d793d RS |
9017 | |
9018 | Finally, we can't do any of these if the mode is too wide | |
9019 | unless the codes are the same. | |
9020 | ||
9021 | Handle the case where the shift codes are the same | |
9022 | first. */ | |
9023 | ||
9024 | if (code == first_code) | |
9025 | { | |
9026 | if (GET_MODE (varop) != result_mode | |
bdaae9a0 RK |
9027 | && (code == ASHIFTRT || code == LSHIFTRT |
9028 | || code == ROTATE)) | |
230d793d RS |
9029 | break; |
9030 | ||
9031 | count += first_count; | |
9032 | varop = XEXP (varop, 0); | |
9033 | continue; | |
9034 | } | |
9035 | ||
9036 | if (code == ASHIFTRT | |
9037 | || (code == ROTATE && first_code == ASHIFTRT) | |
5f4f0e22 | 9038 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT |
230d793d | 9039 | || (GET_MODE (varop) != result_mode |
bdaae9a0 RK |
9040 | && (first_code == ASHIFTRT || first_code == LSHIFTRT |
9041 | || first_code == ROTATE | |
230d793d RS |
9042 | || code == ROTATE))) |
9043 | break; | |
9044 | ||
9045 | /* To compute the mask to apply after the shift, shift the | |
663522cb | 9046 | nonzero bits of the inner shift the same way the |
230d793d RS |
9047 | outer shift will. */ |
9048 | ||
951553af | 9049 | mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); |
230d793d RS |
9050 | |
9051 | mask_rtx | |
9052 | = simplify_binary_operation (code, result_mode, mask_rtx, | |
5f4f0e22 | 9053 | GEN_INT (count)); |
663522cb | 9054 | |
230d793d RS |
9055 | /* Give up if we can't compute an outer operation to use. */ |
9056 | if (mask_rtx == 0 | |
9057 | || GET_CODE (mask_rtx) != CONST_INT | |
9058 | || ! merge_outer_ops (&outer_op, &outer_const, AND, | |
9059 | INTVAL (mask_rtx), | |
9060 | result_mode, &complement_p)) | |
9061 | break; | |
9062 | ||
9063 | /* If the shifts are in the same direction, we add the | |
9064 | counts. Otherwise, we subtract them. */ | |
770ae6cc | 9065 | signed_count = count; |
230d793d RS |
9066 | if ((code == ASHIFTRT || code == LSHIFTRT) |
9067 | == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
770ae6cc | 9068 | signed_count += first_count; |
230d793d | 9069 | else |
770ae6cc | 9070 | signed_count -= first_count; |
230d793d | 9071 | |
663522cb | 9072 | /* If COUNT is positive, the new shift is usually CODE, |
230d793d RS |
9073 | except for the two exceptions below, in which case it is |
9074 | FIRST_CODE. If the count is negative, FIRST_CODE should | |
9075 | always be used */ | |
770ae6cc | 9076 | if (signed_count > 0 |
230d793d RS |
9077 | && ((first_code == ROTATE && code == ASHIFT) |
9078 | || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
770ae6cc RK |
9079 | code = first_code, count = signed_count; |
9080 | else if (signed_count < 0) | |
663522cb | 9081 | code = first_code, count = -signed_count; |
770ae6cc RK |
9082 | else |
9083 | count = signed_count; | |
230d793d RS |
9084 | |
9085 | varop = XEXP (varop, 0); | |
9086 | continue; | |
9087 | } | |
9088 | ||
9089 | /* If we have (A << B << C) for any shift, we can convert this to | |
9090 | (A << C << B). This wins if A is a constant. Only try this if | |
9091 | B is not a constant. */ | |
9092 | ||
9093 | else if (GET_CODE (varop) == code | |
9094 | && GET_CODE (XEXP (varop, 1)) != CONST_INT | |
9095 | && 0 != (new | |
9096 | = simplify_binary_operation (code, mode, | |
9097 | XEXP (varop, 0), | |
5f4f0e22 | 9098 | GEN_INT (count)))) |
230d793d | 9099 | { |
f1c6ba8b | 9100 | varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); |
230d793d RS |
9101 | count = 0; |
9102 | continue; | |
9103 | } | |
9104 | break; | |
9105 | ||
9106 | case NOT: | |
9107 | /* Make this fit the case below. */ | |
f1c6ba8b RK |
9108 | varop = gen_rtx_XOR (mode, XEXP (varop, 0), |
9109 | GEN_INT (GET_MODE_MASK (mode))); | |
230d793d RS |
9110 | continue; |
9111 | ||
9112 | case IOR: | |
9113 | case AND: | |
9114 | case XOR: | |
9115 | /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
9116 | with C the size of VAROP - 1 and the shift is logical if | |
9117 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9118 | we have an (le X 0) operation. If we have an arithmetic shift | |
9119 | and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
9120 | STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
9121 | ||
9122 | if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
9123 | && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
9124 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
9125 | && (code == LSHIFTRT || code == ASHIFTRT) | |
26c34780 RS |
9126 | && count == (unsigned int) |
9127 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
9128 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
9129 | { | |
9130 | count = 0; | |
f1c6ba8b RK |
9131 | varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), |
9132 | const0_rtx); | |
230d793d RS |
9133 | |
9134 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 9135 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
9136 | |
9137 | continue; | |
9138 | } | |
9139 | ||
9140 | /* If we have (shift (logical)), move the logical to the outside | |
9141 | to allow it to possibly combine with another logical and the | |
9142 | shift to combine with another shift. This also canonicalizes to | |
9143 | what a ZERO_EXTRACT looks like. Also, some machines have | |
9144 | (and (shift)) insns. */ | |
9145 | ||
9146 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
39a44a4e RK |
9147 | /* We can't do this if we have (ashiftrt (xor)) and the |
9148 | constant has its sign bit set in shift_mode. */ | |
9149 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9150 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9151 | shift_mode)) | |
230d793d RS |
9152 | && (new = simplify_binary_operation (code, result_mode, |
9153 | XEXP (varop, 1), | |
5f4f0e22 | 9154 | GEN_INT (count))) != 0 |
663522cb | 9155 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9156 | && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), |
9157 | INTVAL (new), result_mode, &complement_p)) | |
9158 | { | |
9159 | varop = XEXP (varop, 0); | |
9160 | continue; | |
9161 | } | |
9162 | ||
9163 | /* If we can't do that, try to simplify the shift in each arm of the | |
9164 | logical expression, make a new logical expression, and apply | |
39a44a4e RK |
9165 | the inverse distributive law. This also can't be done |
9166 | for some (ashiftrt (xor)). */ | |
446f52f4 GS |
9167 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT |
9168 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9169 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9170 | shift_mode))) | |
39a44a4e RK |
9171 | { |
9172 | rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9173 | XEXP (varop, 0), count); | |
9174 | rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9175 | XEXP (varop, 1), count); | |
230d793d | 9176 | |
bcb34aa3 PB |
9177 | varop = simplify_gen_binary (GET_CODE (varop), shift_mode, |
9178 | lhs, rhs); | |
39a44a4e | 9179 | varop = apply_distributive_law (varop); |
230d793d | 9180 | |
39a44a4e | 9181 | count = 0; |
446f52f4 | 9182 | continue; |
39a44a4e | 9183 | } |
230d793d RS |
9184 | break; |
9185 | ||
9186 | case EQ: | |
beb235f8 | 9187 | /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE |
230d793d | 9188 | says that the sign bit can be tested, FOO has mode MODE, C is |
45620ed4 RK |
9189 | GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit |
9190 | that may be nonzero. */ | |
9191 | if (code == LSHIFTRT | |
230d793d RS |
9192 | && XEXP (varop, 1) == const0_rtx |
9193 | && GET_MODE (XEXP (varop, 0)) == result_mode | |
26c34780 | 9194 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) |
5f4f0e22 | 9195 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 9196 | && ((STORE_FLAG_VALUE |
663522cb | 9197 | & ((HOST_WIDE_INT) 1 |
770ae6cc | 9198 | < (GET_MODE_BITSIZE (result_mode) - 1)))) |
951553af | 9199 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9200 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9201 | (HOST_WIDE_INT) 1, result_mode, | |
9202 | &complement_p)) | |
230d793d RS |
9203 | { |
9204 | varop = XEXP (varop, 0); | |
9205 | count = 0; | |
9206 | continue; | |
9207 | } | |
9208 | break; | |
9209 | ||
9210 | case NEG: | |
d0ab8cd3 RK |
9211 | /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less |
9212 | than the number of bits in the mode is equivalent to A. */ | |
26c34780 RS |
9213 | if (code == LSHIFTRT |
9214 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
951553af | 9215 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1) |
230d793d | 9216 | { |
d0ab8cd3 | 9217 | varop = XEXP (varop, 0); |
230d793d RS |
9218 | count = 0; |
9219 | continue; | |
9220 | } | |
9221 | ||
9222 | /* NEG commutes with ASHIFT since it is multiplication. Move the | |
9223 | NEG outside to allow shifts to combine. */ | |
9224 | if (code == ASHIFT | |
5f4f0e22 CH |
9225 | && merge_outer_ops (&outer_op, &outer_const, NEG, |
9226 | (HOST_WIDE_INT) 0, result_mode, | |
9227 | &complement_p)) | |
230d793d RS |
9228 | { |
9229 | varop = XEXP (varop, 0); | |
9230 | continue; | |
9231 | } | |
9232 | break; | |
9233 | ||
9234 | case PLUS: | |
d0ab8cd3 RK |
9235 | /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C |
9236 | is one less than the number of bits in the mode is | |
9237 | equivalent to (xor A 1). */ | |
26c34780 RS |
9238 | if (code == LSHIFTRT |
9239 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
230d793d | 9240 | && XEXP (varop, 1) == constm1_rtx |
951553af | 9241 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9242 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9243 | (HOST_WIDE_INT) 1, result_mode, | |
9244 | &complement_p)) | |
230d793d RS |
9245 | { |
9246 | count = 0; | |
9247 | varop = XEXP (varop, 0); | |
9248 | continue; | |
9249 | } | |
9250 | ||
3f508eca | 9251 | /* If we have (xshiftrt (plus FOO BAR) C), and the only bits |
951553af | 9252 | that might be nonzero in BAR are those being shifted out and those |
3f508eca RK |
9253 | bits are known zero in FOO, we can replace the PLUS with FOO. |
9254 | Similarly in the other operand order. This code occurs when | |
9255 | we are computing the size of a variable-size array. */ | |
9256 | ||
9257 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9258 | && count < HOST_BITS_PER_WIDE_INT |
951553af RK |
9259 | && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 |
9260 | && (nonzero_bits (XEXP (varop, 1), result_mode) | |
9261 | & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) | |
3f508eca RK |
9262 | { |
9263 | varop = XEXP (varop, 0); | |
9264 | continue; | |
9265 | } | |
9266 | else if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9267 | && count < HOST_BITS_PER_WIDE_INT |
ac49a949 | 9268 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
951553af | 9269 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
3f508eca | 9270 | >> count) |
951553af RK |
9271 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
9272 | & nonzero_bits (XEXP (varop, 1), | |
3f508eca RK |
9273 | result_mode))) |
9274 | { | |
9275 | varop = XEXP (varop, 1); | |
9276 | continue; | |
9277 | } | |
9278 | ||
230d793d RS |
9279 | /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ |
9280 | if (code == ASHIFT | |
9281 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9282 | && (new = simplify_binary_operation (ASHIFT, result_mode, | |
9283 | XEXP (varop, 1), | |
5f4f0e22 | 9284 | GEN_INT (count))) != 0 |
770ae6cc | 9285 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9286 | && merge_outer_ops (&outer_op, &outer_const, PLUS, |
9287 | INTVAL (new), result_mode, &complement_p)) | |
9288 | { | |
9289 | varop = XEXP (varop, 0); | |
9290 | continue; | |
9291 | } | |
b757b9f8 PH |
9292 | |
9293 | /* Check for 'PLUS signbit', which is the canonical form of 'XOR | |
9294 | signbit', and attempt to change the PLUS to an XOR and move it to | |
9295 | the outer operation as is done above in the AND/IOR/XOR case | |
9296 | leg for shift(logical). See details in logical handling above | |
471854f8 | 9297 | for reasoning in doing so. */ |
b757b9f8 PH |
9298 | if (code == LSHIFTRT |
9299 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9300 | && mode_signbit_p (result_mode, XEXP (varop, 1)) | |
9301 | && (new = simplify_binary_operation (code, result_mode, | |
9302 | XEXP (varop, 1), | |
9303 | GEN_INT (count))) != 0 | |
9304 | && GET_CODE (new) == CONST_INT | |
9305 | && merge_outer_ops (&outer_op, &outer_const, XOR, | |
9306 | INTVAL (new), result_mode, &complement_p)) | |
9307 | { | |
9308 | varop = XEXP (varop, 0); | |
9309 | continue; | |
9310 | } | |
9311 | ||
230d793d RS |
9312 | break; |
9313 | ||
9314 | case MINUS: | |
9315 | /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
9316 | with C the size of VAROP - 1 and the shift is logical if | |
9317 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9318 | we have a (gt X 0) operation. If the shift is arithmetic with | |
9319 | STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
9320 | we have a (neg (gt X 0)) operation. */ | |
9321 | ||
0802d516 RK |
9322 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
9323 | && GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
26c34780 RS |
9324 | && count == (unsigned int) |
9325 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
9326 | && (code == LSHIFTRT || code == ASHIFTRT) |
9327 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
26c34780 RS |
9328 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1)) |
9329 | == count | |
230d793d RS |
9330 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
9331 | { | |
9332 | count = 0; | |
f1c6ba8b RK |
9333 | varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), |
9334 | const0_rtx); | |
230d793d RS |
9335 | |
9336 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 9337 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
9338 | |
9339 | continue; | |
9340 | } | |
9341 | break; | |
6e0ef100 JC |
9342 | |
9343 | case TRUNCATE: | |
9344 | /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) | |
9345 | if the truncate does not affect the value. */ | |
9346 | if (code == LSHIFTRT | |
9347 | && GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
9348 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
9349 | && (INTVAL (XEXP (XEXP (varop, 0), 1)) | |
b577a8ff JL |
9350 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) |
9351 | - GET_MODE_BITSIZE (GET_MODE (varop))))) | |
6e0ef100 JC |
9352 | { |
9353 | rtx varop_inner = XEXP (varop, 0); | |
9354 | ||
770ae6cc | 9355 | varop_inner |
f1c6ba8b RK |
9356 | = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), |
9357 | XEXP (varop_inner, 0), | |
9358 | GEN_INT | |
9359 | (count + INTVAL (XEXP (varop_inner, 1)))); | |
9360 | varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); | |
6e0ef100 JC |
9361 | count = 0; |
9362 | continue; | |
9363 | } | |
9364 | break; | |
663522cb | 9365 | |
e9a25f70 JL |
9366 | default: |
9367 | break; | |
230d793d RS |
9368 | } |
9369 | ||
9370 | break; | |
9371 | } | |
9372 | ||
9373 | /* We need to determine what mode to do the shift in. If the shift is | |
f6789c77 RK |
9374 | a right shift or ROTATE, we must always do it in the mode it was |
9375 | originally done in. Otherwise, we can do it in MODE, the widest mode | |
9376 | encountered. The code we care about is that of the shift that will | |
9377 | actually be done, not the shift that was originally requested. */ | |
9378 | shift_mode | |
9379 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9380 | ? result_mode : mode); | |
230d793d RS |
9381 | |
9382 | /* We have now finished analyzing the shift. The result should be | |
9383 | a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
f822d252 | 9384 | OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied |
230d793d RS |
9385 | to the result of the shift. OUTER_CONST is the relevant constant, |
9386 | but we must turn off all bits turned off in the shift. | |
9387 | ||
9388 | If we were passed a value for X, see if we can use any pieces of | |
9389 | it. If not, make new rtx. */ | |
9390 | ||
ec8e098d | 9391 | if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH |
230d793d | 9392 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
26c34780 | 9393 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count) |
230d793d RS |
9394 | const_rtx = XEXP (x, 1); |
9395 | else | |
5f4f0e22 | 9396 | const_rtx = GEN_INT (count); |
230d793d RS |
9397 | |
9398 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
9399 | && GET_MODE (XEXP (x, 0)) == shift_mode | |
9400 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
9401 | varop = XEXP (x, 0); | |
9402 | else if (GET_MODE (varop) != shift_mode) | |
4de249d9 | 9403 | varop = gen_lowpart (shift_mode, varop); |
230d793d | 9404 | |
0f41302f | 9405 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
9406 | if (GET_CODE (varop) == CLOBBER) |
9407 | return x ? x : varop; | |
9408 | ||
9409 | new = simplify_binary_operation (code, shift_mode, varop, const_rtx); | |
9410 | if (new != 0) | |
9411 | x = new; | |
9412 | else | |
6c2d03d0 | 9413 | x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx); |
230d793d | 9414 | |
224eeff2 RK |
9415 | /* If we have an outer operation and we just made a shift, it is |
9416 | possible that we could have simplified the shift were it not | |
9417 | for the outer operation. So try to do the simplification | |
9418 | recursively. */ | |
9419 | ||
f822d252 | 9420 | if (outer_op != UNKNOWN && GET_CODE (x) == code |
224eeff2 RK |
9421 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
9422 | x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), | |
9423 | INTVAL (XEXP (x, 1))); | |
9424 | ||
e0a2f705 | 9425 | /* If we were doing an LSHIFTRT in a wider mode than it was originally, |
230d793d RS |
9426 | turn off all the bits that the shift would have turned off. */ |
9427 | if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
5f4f0e22 | 9428 | x = simplify_and_const_int (NULL_RTX, shift_mode, x, |
230d793d | 9429 | GET_MODE_MASK (result_mode) >> orig_count); |
663522cb | 9430 | |
230d793d | 9431 | /* Do the remainder of the processing in RESULT_MODE. */ |
4de249d9 | 9432 | x = gen_lowpart (result_mode, x); |
230d793d RS |
9433 | |
9434 | /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
9435 | operation. */ | |
9436 | if (complement_p) | |
e869aa39 | 9437 | x = simplify_gen_unary (NOT, result_mode, x, result_mode); |
230d793d | 9438 | |
f822d252 | 9439 | if (outer_op != UNKNOWN) |
230d793d | 9440 | { |
5f4f0e22 | 9441 | if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) |
7e4ce834 | 9442 | outer_const = trunc_int_for_mode (outer_const, result_mode); |
230d793d RS |
9443 | |
9444 | if (outer_op == AND) | |
5f4f0e22 | 9445 | x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); |
230d793d RS |
9446 | else if (outer_op == SET) |
9447 | /* This means that we have determined that the result is | |
9448 | equivalent to a constant. This should be rare. */ | |
5f4f0e22 | 9449 | x = GEN_INT (outer_const); |
ec8e098d | 9450 | else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) |
f1c6ba8b | 9451 | x = simplify_gen_unary (outer_op, result_mode, x, result_mode); |
230d793d | 9452 | else |
bcb34aa3 PB |
9453 | x = simplify_gen_binary (outer_op, result_mode, x, |
9454 | GEN_INT (outer_const)); | |
230d793d RS |
9455 | } |
9456 | ||
9457 | return x; | |
663522cb | 9458 | } |
230d793d RS |
9459 | \f |
9460 | /* Like recog, but we receive the address of a pointer to a new pattern. | |
9461 | We try to match the rtx that the pointer points to. | |
9462 | If that fails, we may try to modify or replace the pattern, | |
9463 | storing the replacement into the same pointer object. | |
9464 | ||
9465 | Modifications include deletion or addition of CLOBBERs. | |
9466 | ||
9467 | PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
9468 | the CLOBBERs are placed. | |
9469 | ||
9470 | The value is the final insn code from the pattern ultimately matched, | |
9471 | or -1. */ | |
9472 | ||
9473 | static int | |
79a490a9 | 9474 | recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes) |
230d793d | 9475 | { |
b3694847 | 9476 | rtx pat = *pnewpat; |
230d793d RS |
9477 | int insn_code_number; |
9478 | int num_clobbers_to_add = 0; | |
9479 | int i; | |
9480 | rtx notes = 0; | |
e6d83128 | 9481 | rtx old_notes, old_pat; |
230d793d | 9482 | |
974f4146 RK |
9483 | /* If PAT is a PARALLEL, check to see if it contains the CLOBBER |
9484 | we use to indicate that something didn't match. If we find such a | |
9485 | thing, force rejection. */ | |
d96023cf | 9486 | if (GET_CODE (pat) == PARALLEL) |
974f4146 | 9487 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
d96023cf RK |
9488 | if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER |
9489 | && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) | |
974f4146 RK |
9490 | return -1; |
9491 | ||
e6d83128 JH |
9492 | old_pat = PATTERN (insn); |
9493 | old_notes = REG_NOTES (insn); | |
9494 | PATTERN (insn) = pat; | |
9495 | REG_NOTES (insn) = 0; | |
c1194d74 | 9496 | |
e6d83128 | 9497 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); |
230d793d RS |
9498 | |
9499 | /* If it isn't, there is the possibility that we previously had an insn | |
9500 | that clobbered some register as a side effect, but the combined | |
9501 | insn doesn't need to do that. So try once more without the clobbers | |
9502 | unless this represents an ASM insn. */ | |
9503 | ||
9504 | if (insn_code_number < 0 && ! check_asm_operands (pat) | |
9505 | && GET_CODE (pat) == PARALLEL) | |
9506 | { | |
9507 | int pos; | |
9508 | ||
9509 | for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
9510 | if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
9511 | { | |
9512 | if (i != pos) | |
9513 | SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
9514 | pos++; | |
9515 | } | |
9516 | ||
9517 | SUBST_INT (XVECLEN (pat, 0), pos); | |
9518 | ||
9519 | if (pos == 1) | |
9520 | pat = XVECEXP (pat, 0, 0); | |
9521 | ||
e6d83128 JH |
9522 | PATTERN (insn) = pat; |
9523 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
230d793d | 9524 | } |
e6d83128 JH |
9525 | PATTERN (insn) = old_pat; |
9526 | REG_NOTES (insn) = old_notes; | |
230d793d | 9527 | |
b5832b43 JH |
9528 | /* Recognize all noop sets, these will be killed by followup pass. */ |
9529 | if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) | |
9530 | insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; | |
9531 | ||
230d793d RS |
9532 | /* If we had any clobbers to add, make a new pattern than contains |
9533 | them. Then check to make sure that all of them are dead. */ | |
9534 | if (num_clobbers_to_add) | |
9535 | { | |
38a448ca | 9536 | rtx newpat = gen_rtx_PARALLEL (VOIDmode, |
bf103ec2 R |
9537 | rtvec_alloc (GET_CODE (pat) == PARALLEL |
9538 | ? (XVECLEN (pat, 0) | |
9539 | + num_clobbers_to_add) | |
9540 | : num_clobbers_to_add + 1)); | |
230d793d RS |
9541 | |
9542 | if (GET_CODE (pat) == PARALLEL) | |
9543 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
9544 | XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
9545 | else | |
9546 | XVECEXP (newpat, 0, 0) = pat; | |
9547 | ||
9548 | add_clobbers (newpat, insn_code_number); | |
9549 | ||
9550 | for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
9551 | i < XVECLEN (newpat, 0); i++) | |
9552 | { | |
f8cfc6aa | 9553 | if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) |
230d793d RS |
9554 | && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) |
9555 | return -1; | |
38a448ca RH |
9556 | notes = gen_rtx_EXPR_LIST (REG_UNUSED, |
9557 | XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
230d793d RS |
9558 | } |
9559 | pat = newpat; | |
9560 | } | |
9561 | ||
9562 | *pnewpat = pat; | |
9563 | *pnotes = notes; | |
9564 | ||
9565 | return insn_code_number; | |
9566 | } | |
9567 | \f | |
4de249d9 PB |
9568 | /* Like gen_lowpart_general but for use by combine. In combine it |
9569 | is not possible to create any new pseudoregs. However, it is | |
9570 | safe to create invalid memory addresses, because combine will | |
9571 | try to recognize them and all they will do is make the combine | |
9572 | attempt fail. | |
230d793d RS |
9573 | |
9574 | If for some reason this cannot do its job, an rtx | |
9575 | (clobber (const_int 0)) is returned. | |
9576 | An insn containing that will not be recognized. */ | |
9577 | ||
230d793d | 9578 | static rtx |
7a32a925 | 9579 | gen_lowpart_for_combine (enum machine_mode omode, rtx x) |
230d793d | 9580 | { |
7a32a925 RH |
9581 | enum machine_mode imode = GET_MODE (x); |
9582 | unsigned int osize = GET_MODE_SIZE (omode); | |
9583 | unsigned int isize = GET_MODE_SIZE (imode); | |
230d793d RS |
9584 | rtx result; |
9585 | ||
7a32a925 | 9586 | if (omode == imode) |
230d793d RS |
9587 | return x; |
9588 | ||
7a32a925 RH |
9589 | /* Return identity if this is a CONST or symbolic reference. */ |
9590 | if (omode == Pmode | |
cafe096b EC |
9591 | && (GET_CODE (x) == CONST |
9592 | || GET_CODE (x) == SYMBOL_REF | |
9593 | || GET_CODE (x) == LABEL_REF)) | |
9594 | return x; | |
9595 | ||
eae957a8 RK |
9596 | /* We can only support MODE being wider than a word if X is a |
9597 | constant integer or has a mode the same size. */ | |
7a32a925 RH |
9598 | if (GET_MODE_SIZE (omode) > UNITS_PER_WORD |
9599 | && ! ((imode == VOIDmode | |
eae957a8 RK |
9600 | && (GET_CODE (x) == CONST_INT |
9601 | || GET_CODE (x) == CONST_DOUBLE)) | |
7a32a925 RH |
9602 | || isize == osize)) |
9603 | goto fail; | |
230d793d RS |
9604 | |
9605 | /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
9606 | won't know what to do. So we will strip off the SUBREG here and | |
9607 | process normally. */ | |
3c0cb5de | 9608 | if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) |
230d793d RS |
9609 | { |
9610 | x = SUBREG_REG (x); | |
32f2ce02 HPN |
9611 | |
9612 | /* For use in case we fall down into the address adjustments | |
9613 | further below, we need to adjust the known mode and size of | |
9614 | x; imode and isize, since we just adjusted x. */ | |
9615 | imode = GET_MODE (x); | |
9616 | ||
9617 | if (imode == omode) | |
230d793d | 9618 | return x; |
32f2ce02 HPN |
9619 | |
9620 | isize = GET_MODE_SIZE (imode); | |
230d793d RS |
9621 | } |
9622 | ||
7a32a925 RH |
9623 | result = gen_lowpart_common (omode, x); |
9624 | ||
cff9f8d5 | 9625 | #ifdef CANNOT_CHANGE_MODE_CLASS |
41bf2a8b RH |
9626 | if (result != 0 && GET_CODE (result) == SUBREG) |
9627 | record_subregs_of_mode (result); | |
02188693 | 9628 | #endif |
64bf47a2 | 9629 | |
230d793d RS |
9630 | if (result) |
9631 | return result; | |
9632 | ||
3c0cb5de | 9633 | if (MEM_P (x)) |
230d793d | 9634 | { |
b3694847 | 9635 | int offset = 0; |
230d793d RS |
9636 | |
9637 | /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
9638 | address. */ | |
9639 | if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) | |
7a32a925 | 9640 | goto fail; |
230d793d RS |
9641 | |
9642 | /* If we want to refer to something bigger than the original memref, | |
9a5a17f3 | 9643 | generate a paradoxical subreg instead. That will force a reload |
230d793d | 9644 | of the original memref X. */ |
7a32a925 RH |
9645 | if (isize < osize) |
9646 | return gen_rtx_SUBREG (omode, x, 0); | |
230d793d | 9647 | |
f76b9db2 | 9648 | if (WORDS_BIG_ENDIAN) |
7a32a925 | 9649 | offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); |
c5c76735 | 9650 | |
6c6cfbfd KH |
9651 | /* Adjust the address so that the address-after-the-data is |
9652 | unchanged. */ | |
f76b9db2 | 9653 | if (BYTES_BIG_ENDIAN) |
7a32a925 | 9654 | offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); |
f1ec5147 | 9655 | |
7a32a925 | 9656 | return adjust_address_nv (x, omode, offset); |
230d793d RS |
9657 | } |
9658 | ||
9659 | /* If X is a comparison operator, rewrite it in a new mode. This | |
9660 | probably won't match, but may allow further simplifications. */ | |
ec8e098d | 9661 | else if (COMPARISON_P (x)) |
7a32a925 | 9662 | return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); |
230d793d RS |
9663 | |
9664 | /* If we couldn't simplify X any other way, just enclose it in a | |
9665 | SUBREG. Normally, this SUBREG won't match, but some patterns may | |
a7c99304 | 9666 | include an explicit SUBREG or we may simplify it further in combine. */ |
230d793d | 9667 | else |
dfbe1b2f | 9668 | { |
ddef6bc7 | 9669 | int offset = 0; |
e0e08ac2 | 9670 | rtx res; |
dfbe1b2f | 9671 | |
7a32a925 RH |
9672 | offset = subreg_lowpart_offset (omode, imode); |
9673 | if (imode == VOIDmode) | |
80ba02b1 | 9674 | { |
7a32a925 RH |
9675 | imode = int_mode_for_mode (omode); |
9676 | x = gen_lowpart_common (imode, x); | |
9677 | if (x == NULL) | |
9678 | goto fail; | |
80ba02b1 | 9679 | } |
7a32a925 | 9680 | res = simplify_gen_subreg (omode, x, imode, offset); |
e0e08ac2 JH |
9681 | if (res) |
9682 | return res; | |
dfbe1b2f | 9683 | } |
7a32a925 RH |
9684 | |
9685 | fail: | |
9686 | return gen_rtx_CLOBBER (imode, const0_rtx); | |
230d793d RS |
9687 | } |
9688 | \f | |
230d793d RS |
9689 | /* Simplify a comparison between *POP0 and *POP1 where CODE is the |
9690 | comparison code that will be tested. | |
9691 | ||
9692 | The result is a possibly different comparison code to use. *POP0 and | |
9693 | *POP1 may be updated. | |
9694 | ||
9695 | It is possible that we might detect that a comparison is either always | |
9696 | true or always false. However, we do not perform general constant | |
5089e22e | 9697 | folding in combine, so this knowledge isn't useful. Such tautologies |
230d793d RS |
9698 | should have been detected earlier. Hence we ignore all such cases. */ |
9699 | ||
9700 | static enum rtx_code | |
79a490a9 | 9701 | simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) |
230d793d RS |
9702 | { |
9703 | rtx op0 = *pop0; | |
9704 | rtx op1 = *pop1; | |
9705 | rtx tem, tem1; | |
9706 | int i; | |
9707 | enum machine_mode mode, tmode; | |
9708 | ||
9709 | /* Try a few ways of applying the same transformation to both operands. */ | |
9710 | while (1) | |
9711 | { | |
3a19aabc RK |
9712 | #ifndef WORD_REGISTER_OPERATIONS |
9713 | /* The test below this one won't handle SIGN_EXTENDs on these machines, | |
9714 | so check specially. */ | |
9715 | if (code != GTU && code != GEU && code != LTU && code != LEU | |
9716 | && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT | |
9717 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
9718 | && GET_CODE (XEXP (op1, 0)) == ASHIFT | |
9719 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG | |
9720 | && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG | |
9721 | && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) | |
ad25ba17 | 9722 | == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) |
3a19aabc | 9723 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
fa9ea255 KH |
9724 | && XEXP (op0, 1) == XEXP (op1, 1) |
9725 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
9726 | && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) | |
3a19aabc RK |
9727 | && (INTVAL (XEXP (op0, 1)) |
9728 | == (GET_MODE_BITSIZE (GET_MODE (op0)) | |
9729 | - (GET_MODE_BITSIZE | |
9730 | (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) | |
9731 | { | |
9732 | op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); | |
9733 | op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); | |
9734 | } | |
9735 | #endif | |
9736 | ||
230d793d RS |
9737 | /* If both operands are the same constant shift, see if we can ignore the |
9738 | shift. We can if the shift is a rotate or if the bits shifted out of | |
951553af | 9739 | this shift are known to be zero for both inputs and if the type of |
230d793d | 9740 | comparison is compatible with the shift. */ |
67232b23 RK |
9741 | if (GET_CODE (op0) == GET_CODE (op1) |
9742 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
9743 | && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) | |
45620ed4 | 9744 | || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) |
67232b23 RK |
9745 | && (code != GT && code != LT && code != GE && code != LE)) |
9746 | || (GET_CODE (op0) == ASHIFTRT | |
9747 | && (code != GTU && code != LTU | |
99dc5306 | 9748 | && code != GEU && code != LEU))) |
67232b23 RK |
9749 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
9750 | && INTVAL (XEXP (op0, 1)) >= 0 | |
9751 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
9752 | && XEXP (op0, 1) == XEXP (op1, 1)) | |
230d793d RS |
9753 | { |
9754 | enum machine_mode mode = GET_MODE (op0); | |
5f4f0e22 | 9755 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
9756 | int shift_count = INTVAL (XEXP (op0, 1)); |
9757 | ||
9758 | if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
9759 | mask &= (mask >> shift_count) << shift_count; | |
45620ed4 | 9760 | else if (GET_CODE (op0) == ASHIFT) |
230d793d RS |
9761 | mask = (mask & (mask << shift_count)) >> shift_count; |
9762 | ||
663522cb KH |
9763 | if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 |
9764 | && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) | |
230d793d RS |
9765 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); |
9766 | else | |
9767 | break; | |
9768 | } | |
9769 | ||
9770 | /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
9771 | SUBREGs are of the same mode, and, in both cases, the AND would | |
9772 | be redundant if the comparison was done in the narrower mode, | |
9773 | do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
951553af RK |
9774 | and the operand's possibly nonzero bits are 0xffffff01; in that case |
9775 | if we only care about QImode, we don't need the AND). This case | |
9776 | occurs if the output mode of an scc insn is not SImode and | |
7e4dc511 RK |
9777 | STORE_FLAG_VALUE == 1 (e.g., the 386). |
9778 | ||
9779 | Similarly, check for a case where the AND's are ZERO_EXTEND | |
9780 | operations from some narrower mode even though a SUBREG is not | |
9781 | present. */ | |
230d793d | 9782 | |
663522cb KH |
9783 | else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND |
9784 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
9785 | && GET_CODE (XEXP (op1, 1)) == CONST_INT) | |
230d793d | 9786 | { |
7e4dc511 RK |
9787 | rtx inner_op0 = XEXP (op0, 0); |
9788 | rtx inner_op1 = XEXP (op1, 0); | |
9789 | HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); | |
9790 | HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); | |
9791 | int changed = 0; | |
663522cb | 9792 | |
7e4dc511 RK |
9793 | if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG |
9794 | && (GET_MODE_SIZE (GET_MODE (inner_op0)) | |
9795 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) | |
9796 | && (GET_MODE (SUBREG_REG (inner_op0)) | |
9797 | == GET_MODE (SUBREG_REG (inner_op1))) | |
729a2bc6 | 9798 | && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) |
7e4dc511 | 9799 | <= HOST_BITS_PER_WIDE_INT) |
01c82bbb | 9800 | && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), |
729a2bc6 | 9801 | GET_MODE (SUBREG_REG (inner_op0))))) |
01c82bbb RK |
9802 | && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), |
9803 | GET_MODE (SUBREG_REG (inner_op1)))))) | |
7e4dc511 RK |
9804 | { |
9805 | op0 = SUBREG_REG (inner_op0); | |
9806 | op1 = SUBREG_REG (inner_op1); | |
9807 | ||
9808 | /* The resulting comparison is always unsigned since we masked | |
0f41302f | 9809 | off the original sign bit. */ |
7e4dc511 RK |
9810 | code = unsigned_condition (code); |
9811 | ||
9812 | changed = 1; | |
9813 | } | |
230d793d | 9814 | |
7e4dc511 RK |
9815 | else if (c0 == c1) |
9816 | for (tmode = GET_CLASS_NARROWEST_MODE | |
9817 | (GET_MODE_CLASS (GET_MODE (op0))); | |
9818 | tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) | |
e51712db | 9819 | if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) |
7e4dc511 | 9820 | { |
4de249d9 PB |
9821 | op0 = gen_lowpart (tmode, inner_op0); |
9822 | op1 = gen_lowpart (tmode, inner_op1); | |
66415c8b | 9823 | code = unsigned_condition (code); |
7e4dc511 RK |
9824 | changed = 1; |
9825 | break; | |
9826 | } | |
9827 | ||
9828 | if (! changed) | |
9829 | break; | |
230d793d | 9830 | } |
3a19aabc | 9831 | |
ad25ba17 RK |
9832 | /* If both operands are NOT, we can strip off the outer operation |
9833 | and adjust the comparison code for swapped operands; similarly for | |
9834 | NEG, except that this must be an equality comparison. */ | |
9835 | else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) | |
9836 | || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG | |
9837 | && (code == EQ || code == NE))) | |
9838 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); | |
3a19aabc | 9839 | |
230d793d RS |
9840 | else |
9841 | break; | |
9842 | } | |
663522cb | 9843 | |
230d793d | 9844 | /* If the first operand is a constant, swap the operands and adjust the |
3aceff0d RK |
9845 | comparison code appropriately, but don't do this if the second operand |
9846 | is already a constant integer. */ | |
8c9864f3 | 9847 | if (swap_commutative_operands_p (op0, op1)) |
230d793d RS |
9848 | { |
9849 | tem = op0, op0 = op1, op1 = tem; | |
9850 | code = swap_condition (code); | |
9851 | } | |
9852 | ||
9853 | /* We now enter a loop during which we will try to simplify the comparison. | |
9854 | For the most part, we only are concerned with comparisons with zero, | |
9855 | but some things may really be comparisons with zero but not start | |
9856 | out looking that way. */ | |
9857 | ||
9858 | while (GET_CODE (op1) == CONST_INT) | |
9859 | { | |
9860 | enum machine_mode mode = GET_MODE (op0); | |
770ae6cc | 9861 | unsigned int mode_width = GET_MODE_BITSIZE (mode); |
5f4f0e22 | 9862 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
9863 | int equality_comparison_p; |
9864 | int sign_bit_comparison_p; | |
9865 | int unsigned_comparison_p; | |
5f4f0e22 | 9866 | HOST_WIDE_INT const_op; |
230d793d RS |
9867 | |
9868 | /* We only want to handle integral modes. This catches VOIDmode, | |
9869 | CCmode, and the floating-point modes. An exception is that we | |
9870 | can handle VOIDmode if OP0 is a COMPARE or a comparison | |
9871 | operation. */ | |
9872 | ||
9873 | if (GET_MODE_CLASS (mode) != MODE_INT | |
9874 | && ! (mode == VOIDmode | |
ec8e098d | 9875 | && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) |
230d793d RS |
9876 | break; |
9877 | ||
9878 | /* Get the constant we are comparing against and turn off all bits | |
9879 | not on in our mode. */ | |
71012d97 GK |
9880 | const_op = INTVAL (op1); |
9881 | if (mode != VOIDmode) | |
9882 | const_op = trunc_int_for_mode (const_op, mode); | |
b4fbaca7 | 9883 | op1 = GEN_INT (const_op); |
230d793d RS |
9884 | |
9885 | /* If we are comparing against a constant power of two and the value | |
951553af | 9886 | being compared can only have that single bit nonzero (e.g., it was |
230d793d RS |
9887 | `and'ed with that bit), we can replace this with a comparison |
9888 | with zero. */ | |
9889 | if (const_op | |
9890 | && (code == EQ || code == NE || code == GE || code == GEU | |
9891 | || code == LT || code == LTU) | |
5f4f0e22 | 9892 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 9893 | && exact_log2 (const_op) >= 0 |
e51712db | 9894 | && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) |
230d793d RS |
9895 | { |
9896 | code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
9897 | op1 = const0_rtx, const_op = 0; | |
9898 | } | |
9899 | ||
d0ab8cd3 RK |
9900 | /* Similarly, if we are comparing a value known to be either -1 or |
9901 | 0 with -1, change it to the opposite comparison against zero. */ | |
9902 | ||
9903 | if (const_op == -1 | |
9904 | && (code == EQ || code == NE || code == GT || code == LE | |
9905 | || code == GEU || code == LTU) | |
9906 | && num_sign_bit_copies (op0, mode) == mode_width) | |
9907 | { | |
9908 | code = (code == EQ || code == LE || code == GEU ? NE : EQ); | |
9909 | op1 = const0_rtx, const_op = 0; | |
9910 | } | |
9911 | ||
230d793d | 9912 | /* Do some canonicalizations based on the comparison code. We prefer |
663522cb | 9913 | comparisons against zero and then prefer equality comparisons. |
4803a34a | 9914 | If we can reduce the size of a constant, we will do that too. */ |
230d793d RS |
9915 | |
9916 | switch (code) | |
9917 | { | |
9918 | case LT: | |
4803a34a RK |
9919 | /* < C is equivalent to <= (C - 1) */ |
9920 | if (const_op > 0) | |
230d793d | 9921 | { |
4803a34a | 9922 | const_op -= 1; |
5f4f0e22 | 9923 | op1 = GEN_INT (const_op); |
230d793d RS |
9924 | code = LE; |
9925 | /* ... fall through to LE case below. */ | |
9926 | } | |
9927 | else | |
9928 | break; | |
9929 | ||
9930 | case LE: | |
4803a34a RK |
9931 | /* <= C is equivalent to < (C + 1); we do this for C < 0 */ |
9932 | if (const_op < 0) | |
9933 | { | |
9934 | const_op += 1; | |
5f4f0e22 | 9935 | op1 = GEN_INT (const_op); |
4803a34a RK |
9936 | code = LT; |
9937 | } | |
230d793d RS |
9938 | |
9939 | /* If we are doing a <= 0 comparison on a value known to have | |
9940 | a zero sign bit, we can replace this with == 0. */ | |
9941 | else if (const_op == 0 | |
5f4f0e22 | 9942 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 9943 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 9944 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
9945 | code = EQ; |
9946 | break; | |
9947 | ||
9948 | case GE: | |
0f41302f | 9949 | /* >= C is equivalent to > (C - 1). */ |
4803a34a | 9950 | if (const_op > 0) |
230d793d | 9951 | { |
4803a34a | 9952 | const_op -= 1; |
5f4f0e22 | 9953 | op1 = GEN_INT (const_op); |
230d793d RS |
9954 | code = GT; |
9955 | /* ... fall through to GT below. */ | |
9956 | } | |
9957 | else | |
9958 | break; | |
9959 | ||
9960 | case GT: | |
663522cb | 9961 | /* > C is equivalent to >= (C + 1); we do this for C < 0. */ |
4803a34a RK |
9962 | if (const_op < 0) |
9963 | { | |
9964 | const_op += 1; | |
5f4f0e22 | 9965 | op1 = GEN_INT (const_op); |
4803a34a RK |
9966 | code = GE; |
9967 | } | |
230d793d RS |
9968 | |
9969 | /* If we are doing a > 0 comparison on a value known to have | |
9970 | a zero sign bit, we can replace this with != 0. */ | |
9971 | else if (const_op == 0 | |
5f4f0e22 | 9972 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 9973 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 9974 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
9975 | code = NE; |
9976 | break; | |
9977 | ||
230d793d | 9978 | case LTU: |
4803a34a RK |
9979 | /* < C is equivalent to <= (C - 1). */ |
9980 | if (const_op > 0) | |
9981 | { | |
9982 | const_op -= 1; | |
5f4f0e22 | 9983 | op1 = GEN_INT (const_op); |
4803a34a | 9984 | code = LEU; |
0f41302f | 9985 | /* ... fall through ... */ |
4803a34a | 9986 | } |
d0ab8cd3 RK |
9987 | |
9988 | /* (unsigned) < 0x80000000 is equivalent to >= 0. */ | |
f77aada2 JW |
9989 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
9990 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
9991 | { |
9992 | const_op = 0, op1 = const0_rtx; | |
9993 | code = GE; | |
9994 | break; | |
9995 | } | |
4803a34a RK |
9996 | else |
9997 | break; | |
230d793d RS |
9998 | |
9999 | case LEU: | |
10000 | /* unsigned <= 0 is equivalent to == 0 */ | |
10001 | if (const_op == 0) | |
10002 | code = EQ; | |
d0ab8cd3 | 10003 | |
0f41302f | 10004 | /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ |
f77aada2 JW |
10005 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10006 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
d0ab8cd3 RK |
10007 | { |
10008 | const_op = 0, op1 = const0_rtx; | |
10009 | code = GE; | |
10010 | } | |
230d793d RS |
10011 | break; |
10012 | ||
4803a34a | 10013 | case GEU: |
b8ff6ca0 | 10014 | /* >= C is equivalent to > (C - 1). */ |
4803a34a RK |
10015 | if (const_op > 1) |
10016 | { | |
10017 | const_op -= 1; | |
5f4f0e22 | 10018 | op1 = GEN_INT (const_op); |
4803a34a | 10019 | code = GTU; |
0f41302f | 10020 | /* ... fall through ... */ |
4803a34a | 10021 | } |
d0ab8cd3 RK |
10022 | |
10023 | /* (unsigned) >= 0x80000000 is equivalent to < 0. */ | |
f77aada2 JW |
10024 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
10025 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
10026 | { |
10027 | const_op = 0, op1 = const0_rtx; | |
10028 | code = LT; | |
8b2e69e1 | 10029 | break; |
d0ab8cd3 | 10030 | } |
4803a34a RK |
10031 | else |
10032 | break; | |
10033 | ||
230d793d RS |
10034 | case GTU: |
10035 | /* unsigned > 0 is equivalent to != 0 */ | |
10036 | if (const_op == 0) | |
10037 | code = NE; | |
d0ab8cd3 RK |
10038 | |
10039 | /* (unsigned) > 0x7fffffff is equivalent to < 0. */ | |
f77aada2 | 10040 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
e869aa39 | 10041 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) |
d0ab8cd3 RK |
10042 | { |
10043 | const_op = 0, op1 = const0_rtx; | |
10044 | code = LT; | |
10045 | } | |
230d793d | 10046 | break; |
e9a25f70 JL |
10047 | |
10048 | default: | |
10049 | break; | |
230d793d RS |
10050 | } |
10051 | ||
10052 | /* Compute some predicates to simplify code below. */ | |
10053 | ||
10054 | equality_comparison_p = (code == EQ || code == NE); | |
10055 | sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
10056 | unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
d5010e66 | 10057 | || code == GEU); |
230d793d | 10058 | |
6139ff20 RK |
10059 | /* If this is a sign bit comparison and we can do arithmetic in |
10060 | MODE, say that we will only be needing the sign bit of OP0. */ | |
10061 | if (sign_bit_comparison_p | |
10062 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10063 | op0 = force_to_mode (op0, mode, | |
10064 | ((HOST_WIDE_INT) 1 | |
10065 | << (GET_MODE_BITSIZE (mode) - 1)), | |
e3d616e3 | 10066 | NULL_RTX, 0); |
6139ff20 | 10067 | |
230d793d RS |
10068 | /* Now try cases based on the opcode of OP0. If none of the cases |
10069 | does a "continue", we exit this loop immediately after the | |
10070 | switch. */ | |
10071 | ||
10072 | switch (GET_CODE (op0)) | |
10073 | { | |
10074 | case ZERO_EXTRACT: | |
10075 | /* If we are extracting a single bit from a variable position in | |
10076 | a constant that has only a single bit set and are comparing it | |
663522cb | 10077 | with zero, we can convert this into an equality comparison |
d7cd794f | 10078 | between the position and the location of the single bit. */ |
a475bff7 RH |
10079 | /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might |
10080 | have already reduced the shift count modulo the word size. */ | |
10081 | if (!SHIFT_COUNT_TRUNCATED | |
10082 | && GET_CODE (XEXP (op0, 0)) == CONST_INT | |
230d793d RS |
10083 | && XEXP (op0, 1) == const1_rtx |
10084 | && equality_comparison_p && const_op == 0 | |
d7cd794f | 10085 | && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) |
230d793d | 10086 | { |
f76b9db2 | 10087 | if (BITS_BIG_ENDIAN) |
0d8e55d8 | 10088 | { |
da920570 ZW |
10089 | enum machine_mode new_mode |
10090 | = mode_for_extraction (EP_extzv, 1); | |
10091 | if (new_mode == MAX_MACHINE_MODE) | |
10092 | i = BITS_PER_WORD - 1 - i; | |
10093 | else | |
10094 | { | |
10095 | mode = new_mode; | |
10096 | i = (GET_MODE_BITSIZE (mode) - 1 - i); | |
10097 | } | |
0d8e55d8 | 10098 | } |
230d793d RS |
10099 | |
10100 | op0 = XEXP (op0, 2); | |
5f4f0e22 | 10101 | op1 = GEN_INT (i); |
230d793d RS |
10102 | const_op = i; |
10103 | ||
10104 | /* Result is nonzero iff shift count is equal to I. */ | |
10105 | code = reverse_condition (code); | |
10106 | continue; | |
10107 | } | |
230d793d | 10108 | |
0f41302f | 10109 | /* ... fall through ... */ |
230d793d RS |
10110 | |
10111 | case SIGN_EXTRACT: | |
10112 | tem = expand_compound_operation (op0); | |
10113 | if (tem != op0) | |
10114 | { | |
10115 | op0 = tem; | |
10116 | continue; | |
10117 | } | |
10118 | break; | |
10119 | ||
10120 | case NOT: | |
10121 | /* If testing for equality, we can take the NOT of the constant. */ | |
10122 | if (equality_comparison_p | |
10123 | && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
10124 | { | |
10125 | op0 = XEXP (op0, 0); | |
10126 | op1 = tem; | |
10127 | continue; | |
10128 | } | |
10129 | ||
10130 | /* If just looking at the sign bit, reverse the sense of the | |
10131 | comparison. */ | |
10132 | if (sign_bit_comparison_p) | |
10133 | { | |
10134 | op0 = XEXP (op0, 0); | |
10135 | code = (code == GE ? LT : GE); | |
10136 | continue; | |
10137 | } | |
10138 | break; | |
10139 | ||
10140 | case NEG: | |
10141 | /* If testing for equality, we can take the NEG of the constant. */ | |
10142 | if (equality_comparison_p | |
10143 | && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
10144 | { | |
10145 | op0 = XEXP (op0, 0); | |
10146 | op1 = tem; | |
10147 | continue; | |
10148 | } | |
10149 | ||
10150 | /* The remaining cases only apply to comparisons with zero. */ | |
10151 | if (const_op != 0) | |
10152 | break; | |
10153 | ||
10154 | /* When X is ABS or is known positive, | |
10155 | (neg X) is < 0 if and only if X != 0. */ | |
10156 | ||
10157 | if (sign_bit_comparison_p | |
10158 | && (GET_CODE (XEXP (op0, 0)) == ABS | |
5f4f0e22 | 10159 | || (mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10160 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 10161 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) |
230d793d RS |
10162 | { |
10163 | op0 = XEXP (op0, 0); | |
10164 | code = (code == LT ? NE : EQ); | |
10165 | continue; | |
10166 | } | |
10167 | ||
3bed8141 | 10168 | /* If we have NEG of something whose two high-order bits are the |
0f41302f | 10169 | same, we know that "(-a) < 0" is equivalent to "a > 0". */ |
3bed8141 | 10170 | if (num_sign_bit_copies (op0, mode) >= 2) |
230d793d RS |
10171 | { |
10172 | op0 = XEXP (op0, 0); | |
10173 | code = swap_condition (code); | |
10174 | continue; | |
10175 | } | |
10176 | break; | |
10177 | ||
10178 | case ROTATE: | |
10179 | /* If we are testing equality and our count is a constant, we | |
10180 | can perform the inverse operation on our RHS. */ | |
10181 | if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10182 | && (tem = simplify_binary_operation (ROTATERT, mode, | |
10183 | op1, XEXP (op0, 1))) != 0) | |
10184 | { | |
10185 | op0 = XEXP (op0, 0); | |
10186 | op1 = tem; | |
10187 | continue; | |
10188 | } | |
10189 | ||
10190 | /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
10191 | a particular bit. Convert it to an AND of a constant of that | |
10192 | bit. This will be converted into a ZERO_EXTRACT. */ | |
10193 | if (const_op == 0 && sign_bit_comparison_p | |
10194 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10195 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10196 | { |
5f4f0e22 CH |
10197 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10198 | ((HOST_WIDE_INT) 1 | |
10199 | << (mode_width - 1 | |
10200 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10201 | code = (code == LT ? NE : EQ); |
10202 | continue; | |
10203 | } | |
10204 | ||
663522cb | 10205 | /* Fall through. */ |
230d793d RS |
10206 | |
10207 | case ABS: | |
10208 | /* ABS is ignorable inside an equality comparison with zero. */ | |
10209 | if (const_op == 0 && equality_comparison_p) | |
10210 | { | |
10211 | op0 = XEXP (op0, 0); | |
10212 | continue; | |
10213 | } | |
10214 | break; | |
230d793d RS |
10215 | |
10216 | case SIGN_EXTEND: | |
aa2d0bc3 AO |
10217 | /* Can simplify (compare (zero/sign_extend FOO) CONST) to |
10218 | (compare FOO CONST) if CONST fits in FOO's mode and we | |
10219 | are either testing inequality or have an unsigned | |
10220 | comparison with ZERO_EXTEND or a signed comparison with | |
10221 | SIGN_EXTEND. But don't do it if we don't have a compare | |
10222 | insn of the given mode, since we'd have to revert it | |
10223 | later on, and then we wouldn't know whether to sign- or | |
10224 | zero-extend. */ | |
10225 | mode = GET_MODE (XEXP (op0, 0)); | |
10226 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10227 | && ! unsigned_comparison_p | |
10228 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
5f4f0e22 | 10229 | && ((unsigned HOST_WIDE_INT) const_op |
aa2d0bc3 AO |
10230 | < (((unsigned HOST_WIDE_INT) 1 |
10231 | << (GET_MODE_BITSIZE (mode) - 1)))) | |
10232 | && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
230d793d RS |
10233 | { |
10234 | op0 = XEXP (op0, 0); | |
10235 | continue; | |
10236 | } | |
10237 | break; | |
10238 | ||
10239 | case SUBREG: | |
f917ae96 EB |
10240 | /* Check for the case where we are comparing A - C1 with C2, that is |
10241 | ||
10242 | (subreg:MODE (plus (A) (-C1))) op (C2) | |
10243 | ||
10244 | with C1 a constant, and try to lift the SUBREG, i.e. to do the | |
10245 | comparison in the wider mode. One of the following two conditions | |
10246 | must be true in order for this to be valid: | |
10247 | ||
10248 | 1. The mode extension results in the same bit pattern being added | |
10249 | on both sides and the comparison is equality or unsigned. As | |
10250 | C2 has been truncated to fit in MODE, the pattern can only be | |
10251 | all 0s or all 1s. | |
10252 | ||
10253 | 2. The mode extension results in the sign bit being copied on | |
10254 | each side. | |
10255 | ||
10256 | The difficulty here is that we have predicates for A but not for | |
10257 | (A - C1) so we need to check that C1 is within proper bounds so | |
10258 | as to perturbate A as little as possible. */ | |
a687e897 RK |
10259 | |
10260 | if (mode_width <= HOST_BITS_PER_WIDE_INT | |
10261 | && subreg_lowpart_p (op0) | |
f917ae96 | 10262 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width |
a687e897 | 10263 | && GET_CODE (SUBREG_REG (op0)) == PLUS |
f917ae96 | 10264 | && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT) |
a687e897 | 10265 | { |
f917ae96 EB |
10266 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
10267 | rtx a = XEXP (SUBREG_REG (op0), 0); | |
10268 | HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); | |
10269 | ||
10270 | if ((c1 > 0 | |
10271 | && (unsigned HOST_WIDE_INT) c1 | |
10272 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) | |
10273 | && (equality_comparison_p || unsigned_comparison_p) | |
10274 | /* (A - C1) zero-extends if it is positive and sign-extends | |
10275 | if it is negative, C2 both zero- and sign-extends. */ | |
10276 | && ((0 == (nonzero_bits (a, inner_mode) | |
10277 | & ~GET_MODE_MASK (mode)) | |
10278 | && const_op >= 0) | |
10279 | /* (A - C1) sign-extends if it is positive and 1-extends | |
10280 | if it is negative, C2 both sign- and 1-extends. */ | |
10281 | || (num_sign_bit_copies (a, inner_mode) | |
10282 | > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
10283 | - mode_width) | |
10284 | && const_op < 0))) | |
10285 | || ((unsigned HOST_WIDE_INT) c1 | |
10286 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) | |
10287 | /* (A - C1) always sign-extends, like C2. */ | |
10288 | && num_sign_bit_copies (a, inner_mode) | |
10289 | > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
2d88fcc2 | 10290 | - (mode_width - 1)))) |
f917ae96 EB |
10291 | { |
10292 | op0 = SUBREG_REG (op0); | |
10293 | continue; | |
10294 | } | |
a687e897 RK |
10295 | } |
10296 | ||
fe0cf571 RK |
10297 | /* If the inner mode is narrower and we are extracting the low part, |
10298 | we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
10299 | if (subreg_lowpart_p (op0) | |
89f1c7f2 RS |
10300 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) |
10301 | /* Fall through */ ; | |
10302 | else | |
230d793d RS |
10303 | break; |
10304 | ||
0f41302f | 10305 | /* ... fall through ... */ |
230d793d RS |
10306 | |
10307 | case ZERO_EXTEND: | |
aa2d0bc3 AO |
10308 | mode = GET_MODE (XEXP (op0, 0)); |
10309 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10310 | && (unsigned_comparison_p || equality_comparison_p) | |
10311 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10312 | && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode)) | |
10313 | && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
230d793d RS |
10314 | { |
10315 | op0 = XEXP (op0, 0); | |
10316 | continue; | |
10317 | } | |
10318 | break; | |
10319 | ||
10320 | case PLUS: | |
20fdd649 | 10321 | /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do |
5089e22e | 10322 | this for equality comparisons due to pathological cases involving |
230d793d | 10323 | overflows. */ |
20fdd649 RK |
10324 | if (equality_comparison_p |
10325 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10326 | op1, XEXP (op0, 1)))) | |
230d793d RS |
10327 | { |
10328 | op0 = XEXP (op0, 0); | |
10329 | op1 = tem; | |
10330 | continue; | |
10331 | } | |
10332 | ||
10333 | /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
10334 | if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
10335 | && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
10336 | { | |
10337 | op0 = XEXP (XEXP (op0, 0), 0); | |
10338 | code = (code == LT ? EQ : NE); | |
10339 | continue; | |
10340 | } | |
10341 | break; | |
10342 | ||
10343 | case MINUS: | |
65945ec1 HPN |
10344 | /* We used to optimize signed comparisons against zero, but that |
10345 | was incorrect. Unsigned comparisons against zero (GTU, LEU) | |
10346 | arrive here as equality comparisons, or (GEU, LTU) are | |
10347 | optimized away. No need to special-case them. */ | |
0bd4b461 | 10348 | |
20fdd649 RK |
10349 | /* (eq (minus A B) C) -> (eq A (plus B C)) or |
10350 | (eq B (minus A C)), whichever simplifies. We can only do | |
10351 | this for equality comparisons due to pathological cases involving | |
10352 | overflows. */ | |
10353 | if (equality_comparison_p | |
10354 | && 0 != (tem = simplify_binary_operation (PLUS, mode, | |
10355 | XEXP (op0, 1), op1))) | |
10356 | { | |
10357 | op0 = XEXP (op0, 0); | |
10358 | op1 = tem; | |
10359 | continue; | |
10360 | } | |
10361 | ||
10362 | if (equality_comparison_p | |
10363 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10364 | XEXP (op0, 0), op1))) | |
10365 | { | |
10366 | op0 = XEXP (op0, 1); | |
10367 | op1 = tem; | |
10368 | continue; | |
10369 | } | |
10370 | ||
230d793d RS |
10371 | /* The sign bit of (minus (ashiftrt X C) X), where C is the number |
10372 | of bits in X minus 1, is one iff X > 0. */ | |
10373 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
10374 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
26c34780 RS |
10375 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1)) |
10376 | == mode_width - 1 | |
230d793d RS |
10377 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) |
10378 | { | |
10379 | op0 = XEXP (op0, 1); | |
10380 | code = (code == GE ? LE : GT); | |
10381 | continue; | |
10382 | } | |
10383 | break; | |
10384 | ||
10385 | case XOR: | |
10386 | /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
10387 | if C is zero or B is a constant. */ | |
10388 | if (equality_comparison_p | |
10389 | && 0 != (tem = simplify_binary_operation (XOR, mode, | |
10390 | XEXP (op0, 1), op1))) | |
10391 | { | |
10392 | op0 = XEXP (op0, 0); | |
10393 | op1 = tem; | |
10394 | continue; | |
10395 | } | |
10396 | break; | |
10397 | ||
10398 | case EQ: case NE: | |
69bc0a1f JH |
10399 | case UNEQ: case LTGT: |
10400 | case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: | |
10401 | case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: | |
10402 | case UNORDERED: case ORDERED: | |
230d793d RS |
10403 | /* We can't do anything if OP0 is a condition code value, rather |
10404 | than an actual data value. */ | |
10405 | if (const_op != 0 | |
8beccec8 | 10406 | || CC0_P (XEXP (op0, 0)) |
230d793d RS |
10407 | || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) |
10408 | break; | |
10409 | ||
10410 | /* Get the two operands being compared. */ | |
10411 | if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
10412 | tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
10413 | else | |
10414 | tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
10415 | ||
10416 | /* Check for the cases where we simply want the result of the | |
10417 | earlier test or the opposite of that result. */ | |
9a915772 | 10418 | if (code == NE || code == EQ |
5f4f0e22 | 10419 | || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT |
3f508eca | 10420 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT |
230d793d | 10421 | && (STORE_FLAG_VALUE |
5f4f0e22 CH |
10422 | & (((HOST_WIDE_INT) 1 |
10423 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
aa6683f7 | 10424 | && (code == LT || code == GE))) |
230d793d | 10425 | { |
aa6683f7 GK |
10426 | enum rtx_code new_code; |
10427 | if (code == LT || code == NE) | |
10428 | new_code = GET_CODE (op0); | |
10429 | else | |
14f02e73 | 10430 | new_code = reversed_comparison_code (op0, NULL); |
23190837 | 10431 | |
aa6683f7 | 10432 | if (new_code != UNKNOWN) |
9a915772 | 10433 | { |
aa6683f7 GK |
10434 | code = new_code; |
10435 | op0 = tem; | |
10436 | op1 = tem1; | |
9a915772 JH |
10437 | continue; |
10438 | } | |
230d793d RS |
10439 | } |
10440 | break; | |
10441 | ||
10442 | case IOR: | |
da7d8304 | 10443 | /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero |
230d793d RS |
10444 | iff X <= 0. */ |
10445 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
10446 | && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
10447 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
10448 | { | |
10449 | op0 = XEXP (op0, 1); | |
10450 | code = (code == GE ? GT : LE); | |
10451 | continue; | |
10452 | } | |
10453 | break; | |
10454 | ||
10455 | case AND: | |
10456 | /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
10457 | will be converted to a ZERO_EXTRACT later. */ | |
10458 | if (const_op == 0 && equality_comparison_p | |
45620ed4 | 10459 | && GET_CODE (XEXP (op0, 0)) == ASHIFT |
230d793d RS |
10460 | && XEXP (XEXP (op0, 0), 0) == const1_rtx) |
10461 | { | |
10462 | op0 = simplify_and_const_int | |
f1c6ba8b RK |
10463 | (op0, mode, gen_rtx_LSHIFTRT (mode, |
10464 | XEXP (op0, 1), | |
10465 | XEXP (XEXP (op0, 0), 1)), | |
5f4f0e22 | 10466 | (HOST_WIDE_INT) 1); |
230d793d RS |
10467 | continue; |
10468 | } | |
10469 | ||
10470 | /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
10471 | zero and X is a comparison and C1 and C2 describe only bits set | |
10472 | in STORE_FLAG_VALUE, we can compare with X. */ | |
10473 | if (const_op == 0 && equality_comparison_p | |
5f4f0e22 | 10474 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
10475 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10476 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
10477 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10478 | && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 | |
5f4f0e22 | 10479 | && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) |
230d793d RS |
10480 | { |
10481 | mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
10482 | << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
663522cb | 10483 | if ((~STORE_FLAG_VALUE & mask) == 0 |
ec8e098d | 10484 | && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) |
230d793d | 10485 | || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 |
ec8e098d | 10486 | && COMPARISON_P (tem)))) |
230d793d RS |
10487 | { |
10488 | op0 = XEXP (XEXP (op0, 0), 0); | |
10489 | continue; | |
10490 | } | |
10491 | } | |
10492 | ||
10493 | /* If we are doing an equality comparison of an AND of a bit equal | |
10494 | to the sign bit, replace this with a LT or GE comparison of | |
10495 | the underlying value. */ | |
10496 | if (equality_comparison_p | |
10497 | && const_op == 0 | |
10498 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10499 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 10500 | && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) |
e51712db | 10501 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) |
230d793d RS |
10502 | { |
10503 | op0 = XEXP (op0, 0); | |
10504 | code = (code == EQ ? GE : LT); | |
10505 | continue; | |
10506 | } | |
10507 | ||
10508 | /* If this AND operation is really a ZERO_EXTEND from a narrower | |
10509 | mode, the constant fits within that mode, and this is either an | |
10510 | equality or unsigned comparison, try to do this comparison in | |
10511 | the narrower mode. */ | |
10512 | if ((equality_comparison_p || unsigned_comparison_p) | |
10513 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10514 | && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) | |
10515 | & GET_MODE_MASK (mode)) | |
10516 | + 1)) >= 0 | |
10517 | && const_op >> i == 0 | |
10518 | && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) | |
10519 | { | |
4de249d9 | 10520 | op0 = gen_lowpart (tmode, XEXP (op0, 0)); |
230d793d RS |
10521 | continue; |
10522 | } | |
e5e809f4 | 10523 | |
70e1b8fc AM |
10524 | /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 |
10525 | fits in both M1 and M2 and the SUBREG is either paradoxical | |
10526 | or represents the low part, permute the SUBREG and the AND | |
10527 | and try again. */ | |
10528 | if (GET_CODE (XEXP (op0, 0)) == SUBREG) | |
10529 | { | |
10530 | unsigned HOST_WIDE_INT c1; | |
10531 | tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); | |
678e68fc JW |
10532 | /* Require an integral mode, to avoid creating something like |
10533 | (AND:SF ...). */ | |
70e1b8fc AM |
10534 | if (SCALAR_INT_MODE_P (tmode) |
10535 | /* It is unsafe to commute the AND into the SUBREG if the | |
10536 | SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is | |
10537 | not defined. As originally written the upper bits | |
10538 | have a defined value due to the AND operation. | |
10539 | However, if we commute the AND inside the SUBREG then | |
10540 | they no longer have defined values and the meaning of | |
10541 | the code has been changed. */ | |
10542 | && (0 | |
9ec36da5 | 10543 | #ifdef WORD_REGISTER_OPERATIONS |
70e1b8fc AM |
10544 | || (mode_width > GET_MODE_BITSIZE (tmode) |
10545 | && mode_width <= BITS_PER_WORD) | |
9ec36da5 | 10546 | #endif |
70e1b8fc AM |
10547 | || (mode_width <= GET_MODE_BITSIZE (tmode) |
10548 | && subreg_lowpart_p (XEXP (op0, 0)))) | |
10549 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10550 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
10551 | && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
10552 | && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0 | |
10553 | && (c1 & ~GET_MODE_MASK (tmode)) == 0 | |
10554 | && c1 != mask | |
10555 | && c1 != GET_MODE_MASK (tmode)) | |
10556 | { | |
bcb34aa3 PB |
10557 | op0 = simplify_gen_binary (AND, tmode, |
10558 | SUBREG_REG (XEXP (op0, 0)), | |
10559 | gen_int_mode (c1, tmode)); | |
4de249d9 | 10560 | op0 = gen_lowpart (mode, op0); |
70e1b8fc AM |
10561 | continue; |
10562 | } | |
e5e809f4 JL |
10563 | } |
10564 | ||
34ed3bb0 KH |
10565 | /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ |
10566 | if (const_op == 0 && equality_comparison_p | |
10567 | && XEXP (op0, 1) == const1_rtx | |
10568 | && GET_CODE (XEXP (op0, 0)) == NOT) | |
10569 | { | |
10570 | op0 = simplify_and_const_int | |
e5686da7 | 10571 | (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1); |
34ed3bb0 KH |
10572 | code = (code == NE ? EQ : NE); |
10573 | continue; | |
10574 | } | |
10575 | ||
9f8e169e | 10576 | /* Convert (ne (and (lshiftrt (not X)) 1) 0) to |
5565e874 KH |
10577 | (eq (and (lshiftrt X) 1) 0). |
10578 | Also handle the case where (not X) is expressed using xor. */ | |
9f8e169e RH |
10579 | if (const_op == 0 && equality_comparison_p |
10580 | && XEXP (op0, 1) == const1_rtx | |
5565e874 | 10581 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) |
9f8e169e | 10582 | { |
5565e874 KH |
10583 | rtx shift_op = XEXP (XEXP (op0, 0), 0); |
10584 | rtx shift_count = XEXP (XEXP (op0, 0), 1); | |
10585 | ||
10586 | if (GET_CODE (shift_op) == NOT | |
10587 | || (GET_CODE (shift_op) == XOR | |
10588 | && GET_CODE (XEXP (shift_op, 1)) == CONST_INT | |
10589 | && GET_CODE (shift_count) == CONST_INT | |
10590 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
10591 | && (INTVAL (XEXP (shift_op, 1)) | |
10592 | == (HOST_WIDE_INT) 1 << INTVAL (shift_count)))) | |
10593 | { | |
10594 | op0 = simplify_and_const_int | |
10595 | (NULL_RTX, mode, | |
10596 | gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count), | |
10597 | (HOST_WIDE_INT) 1); | |
10598 | code = (code == NE ? EQ : NE); | |
10599 | continue; | |
10600 | } | |
9f8e169e | 10601 | } |
230d793d RS |
10602 | break; |
10603 | ||
10604 | case ASHIFT: | |
45620ed4 | 10605 | /* If we have (compare (ashift FOO N) (const_int C)) and |
230d793d | 10606 | the high order N bits of FOO (N+1 if an inequality comparison) |
951553af | 10607 | are known to be zero, we can do this by comparing FOO with C |
230d793d RS |
10608 | shifted right N bits so long as the low-order N bits of C are |
10609 | zero. */ | |
10610 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10611 | && INTVAL (XEXP (op0, 1)) >= 0 | |
10612 | && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
5f4f0e22 CH |
10613 | < HOST_BITS_PER_WIDE_INT) |
10614 | && ((const_op | |
34785d05 | 10615 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) |
5f4f0e22 | 10616 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10617 | && (nonzero_bits (XEXP (op0, 0), mode) |
663522cb KH |
10618 | & ~(mask >> (INTVAL (XEXP (op0, 1)) |
10619 | + ! equality_comparison_p))) == 0) | |
230d793d | 10620 | { |
7ce787fe NC |
10621 | /* We must perform a logical shift, not an arithmetic one, |
10622 | as we want the top N bits of C to be zero. */ | |
aaaec114 | 10623 | unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); |
663522cb | 10624 | |
7ce787fe | 10625 | temp >>= INTVAL (XEXP (op0, 1)); |
2496c7bd | 10626 | op1 = gen_int_mode (temp, mode); |
230d793d RS |
10627 | op0 = XEXP (op0, 0); |
10628 | continue; | |
10629 | } | |
10630 | ||
dfbe1b2f | 10631 | /* If we are doing a sign bit comparison, it means we are testing |
230d793d | 10632 | a particular bit. Convert it to the appropriate AND. */ |
dfbe1b2f | 10633 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT |
5f4f0e22 | 10634 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10635 | { |
5f4f0e22 CH |
10636 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10637 | ((HOST_WIDE_INT) 1 | |
10638 | << (mode_width - 1 | |
10639 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10640 | code = (code == LT ? NE : EQ); |
10641 | continue; | |
10642 | } | |
dfbe1b2f RK |
10643 | |
10644 | /* If this an equality comparison with zero and we are shifting | |
10645 | the low bit to the sign bit, we can convert this to an AND of the | |
10646 | low-order bit. */ | |
10647 | if (const_op == 0 && equality_comparison_p | |
10648 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
10649 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
10650 | == mode_width - 1) | |
dfbe1b2f | 10651 | { |
5f4f0e22 CH |
10652 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10653 | (HOST_WIDE_INT) 1); | |
dfbe1b2f RK |
10654 | continue; |
10655 | } | |
230d793d RS |
10656 | break; |
10657 | ||
10658 | case ASHIFTRT: | |
d0ab8cd3 RK |
10659 | /* If this is an equality comparison with zero, we can do this |
10660 | as a logical shift, which might be much simpler. */ | |
10661 | if (equality_comparison_p && const_op == 0 | |
10662 | && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
10663 | { | |
10664 | op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, | |
10665 | XEXP (op0, 0), | |
10666 | INTVAL (XEXP (op0, 1))); | |
10667 | continue; | |
10668 | } | |
10669 | ||
230d793d RS |
10670 | /* If OP0 is a sign extension and CODE is not an unsigned comparison, |
10671 | do the comparison in a narrower mode. */ | |
10672 | if (! unsigned_comparison_p | |
10673 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10674 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10675 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
10676 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
22331794 | 10677 | MODE_INT, 1)) != BLKmode |
67e469d7 AM |
10678 | && (((unsigned HOST_WIDE_INT) const_op |
10679 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
10680 | <= GET_MODE_MASK (tmode))) | |
230d793d | 10681 | { |
4de249d9 | 10682 | op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); |
230d793d RS |
10683 | continue; |
10684 | } | |
10685 | ||
14a774a9 RK |
10686 | /* Likewise if OP0 is a PLUS of a sign extension with a |
10687 | constant, which is usually represented with the PLUS | |
10688 | between the shifts. */ | |
10689 | if (! unsigned_comparison_p | |
10690 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10691 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
10692 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10693 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT | |
10694 | && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) | |
10695 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
10696 | MODE_INT, 1)) != BLKmode | |
67e469d7 AM |
10697 | && (((unsigned HOST_WIDE_INT) const_op |
10698 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
10699 | <= GET_MODE_MASK (tmode))) | |
14a774a9 RK |
10700 | { |
10701 | rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); | |
10702 | rtx add_const = XEXP (XEXP (op0, 0), 1); | |
bcb34aa3 PB |
10703 | rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), |
10704 | add_const, XEXP (op0, 1)); | |
14a774a9 | 10705 | |
bcb34aa3 PB |
10706 | op0 = simplify_gen_binary (PLUS, tmode, |
10707 | gen_lowpart (tmode, inner), | |
10708 | new_const); | |
14a774a9 RK |
10709 | continue; |
10710 | } | |
10711 | ||
0f41302f | 10712 | /* ... fall through ... */ |
230d793d RS |
10713 | case LSHIFTRT: |
10714 | /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
951553af | 10715 | the low order N bits of FOO are known to be zero, we can do this |
230d793d RS |
10716 | by comparing FOO with C shifted left N bits so long as no |
10717 | overflow occurs. */ | |
10718 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10719 | && INTVAL (XEXP (op0, 1)) >= 0 | |
5f4f0e22 CH |
10720 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT |
10721 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
951553af | 10722 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 10723 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 |
67e469d7 AM |
10724 | && (((unsigned HOST_WIDE_INT) const_op |
10725 | + (GET_CODE (op0) != LSHIFTRT | |
10726 | ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) | |
10727 | + 1) | |
10728 | : 0)) | |
10729 | <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) | |
230d793d | 10730 | { |
145d3bf2 RE |
10731 | /* If the shift was logical, then we must make the condition |
10732 | unsigned. */ | |
10733 | if (GET_CODE (op0) == LSHIFTRT) | |
10734 | code = unsigned_condition (code); | |
10735 | ||
230d793d | 10736 | const_op <<= INTVAL (XEXP (op0, 1)); |
5f4f0e22 | 10737 | op1 = GEN_INT (const_op); |
230d793d RS |
10738 | op0 = XEXP (op0, 0); |
10739 | continue; | |
10740 | } | |
10741 | ||
10742 | /* If we are using this shift to extract just the sign bit, we | |
10743 | can replace this with an LT or GE comparison. */ | |
10744 | if (const_op == 0 | |
10745 | && (equality_comparison_p || sign_bit_comparison_p) | |
10746 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
10747 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
10748 | == mode_width - 1) | |
230d793d RS |
10749 | { |
10750 | op0 = XEXP (op0, 0); | |
10751 | code = (code == NE || code == GT ? LT : GE); | |
10752 | continue; | |
10753 | } | |
10754 | break; | |
663522cb | 10755 | |
e9a25f70 JL |
10756 | default: |
10757 | break; | |
230d793d RS |
10758 | } |
10759 | ||
10760 | break; | |
10761 | } | |
10762 | ||
10763 | /* Now make any compound operations involved in this comparison. Then, | |
76d31c63 | 10764 | check for an outmost SUBREG on OP0 that is not doing anything or is |
5add6d1a JL |
10765 | paradoxical. The latter transformation must only be performed when |
10766 | it is known that the "extra" bits will be the same in op0 and op1 or | |
10767 | that they don't matter. There are three cases to consider: | |
10768 | ||
10769 | 1. SUBREG_REG (op0) is a register. In this case the bits are don't | |
10770 | care bits and we can assume they have any convenient value. So | |
10771 | making the transformation is safe. | |
10772 | ||
10773 | 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. | |
10774 | In this case the upper bits of op0 are undefined. We should not make | |
10775 | the simplification in that case as we do not know the contents of | |
10776 | those bits. | |
10777 | ||
10778 | 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not | |
f822d252 | 10779 | UNKNOWN. In that case we know those bits are zeros or ones. We must |
5add6d1a JL |
10780 | also be sure that they are the same as the upper bits of op1. |
10781 | ||
10782 | We can never remove a SUBREG for a non-equality comparison because | |
10783 | the sign bit is in a different place in the underlying object. */ | |
230d793d RS |
10784 | |
10785 | op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
10786 | op1 = make_compound_operation (op1, SET); | |
10787 | ||
10788 | if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
10789 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
fa4e13e0 | 10790 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT |
5add6d1a | 10791 | && (code == NE || code == EQ)) |
230d793d | 10792 | { |
5add6d1a JL |
10793 | if (GET_MODE_SIZE (GET_MODE (op0)) |
10794 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) | |
10795 | { | |
dc5c3188 UW |
10796 | /* For paradoxical subregs, allow case 1 as above. Case 3 isn't |
10797 | implemented. */ | |
f8cfc6aa | 10798 | if (REG_P (SUBREG_REG (op0))) |
dc5c3188 UW |
10799 | { |
10800 | op0 = SUBREG_REG (op0); | |
4de249d9 | 10801 | op1 = gen_lowpart (GET_MODE (op0), op1); |
dc5c3188 | 10802 | } |
5add6d1a JL |
10803 | } |
10804 | else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) | |
10805 | <= HOST_BITS_PER_WIDE_INT) | |
10806 | && (nonzero_bits (SUBREG_REG (op0), | |
10807 | GET_MODE (SUBREG_REG (op0))) | |
10808 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
10809 | { | |
4de249d9 | 10810 | tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); |
230d793d | 10811 | |
5add6d1a JL |
10812 | if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) |
10813 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
10814 | op0 = SUBREG_REG (op0), op1 = tem; | |
10815 | } | |
10816 | } | |
230d793d RS |
10817 | |
10818 | /* We now do the opposite procedure: Some machines don't have compare | |
10819 | insns in all modes. If OP0's mode is an integer mode smaller than a | |
10820 | word and we can't do a compare in that mode, see if there is a larger | |
a687e897 RK |
10821 | mode for which we can do the compare. There are a number of cases in |
10822 | which we can use the wider mode. */ | |
230d793d RS |
10823 | |
10824 | mode = GET_MODE (op0); | |
10825 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10826 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
ef89d648 | 10827 | && ! have_insn_for (COMPARE, mode)) |
230d793d | 10828 | for (tmode = GET_MODE_WIDER_MODE (mode); |
5f4f0e22 CH |
10829 | (tmode != VOIDmode |
10830 | && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); | |
230d793d | 10831 | tmode = GET_MODE_WIDER_MODE (tmode)) |
ef89d648 | 10832 | if (have_insn_for (COMPARE, tmode)) |
230d793d | 10833 | { |
d4c5ac1f AM |
10834 | int zero_extended; |
10835 | ||
951553af | 10836 | /* If the only nonzero bits in OP0 and OP1 are those in the |
a687e897 RK |
10837 | narrower mode and this is an equality or unsigned comparison, |
10838 | we can use the wider mode. Similarly for sign-extended | |
7e4dc511 | 10839 | values, in which case it is true for all comparisons. */ |
d4c5ac1f AM |
10840 | zero_extended = ((code == EQ || code == NE |
10841 | || code == GEU || code == GTU | |
10842 | || code == LEU || code == LTU) | |
10843 | && (nonzero_bits (op0, tmode) | |
10844 | & ~GET_MODE_MASK (mode)) == 0 | |
10845 | && ((GET_CODE (op1) == CONST_INT | |
10846 | || (nonzero_bits (op1, tmode) | |
10847 | & ~GET_MODE_MASK (mode)) == 0))); | |
10848 | ||
10849 | if (zero_extended | |
7e4dc511 | 10850 | || ((num_sign_bit_copies (op0, tmode) |
26c34780 RS |
10851 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
10852 | - GET_MODE_BITSIZE (mode))) | |
a687e897 | 10853 | && (num_sign_bit_copies (op1, tmode) |
26c34780 RS |
10854 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
10855 | - GET_MODE_BITSIZE (mode))))) | |
a687e897 | 10856 | { |
14a774a9 RK |
10857 | /* If OP0 is an AND and we don't have an AND in MODE either, |
10858 | make a new AND in the proper mode. */ | |
10859 | if (GET_CODE (op0) == AND | |
ef89d648 | 10860 | && !have_insn_for (AND, mode)) |
bcb34aa3 PB |
10861 | op0 = simplify_gen_binary (AND, tmode, |
10862 | gen_lowpart (tmode, | |
10863 | XEXP (op0, 0)), | |
10864 | gen_lowpart (tmode, | |
10865 | XEXP (op0, 1))); | |
14a774a9 | 10866 | |
4de249d9 | 10867 | op0 = gen_lowpart (tmode, op0); |
d4c5ac1f AM |
10868 | if (zero_extended && GET_CODE (op1) == CONST_INT) |
10869 | op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); | |
4de249d9 | 10870 | op1 = gen_lowpart (tmode, op1); |
a687e897 RK |
10871 | break; |
10872 | } | |
230d793d | 10873 | |
a687e897 RK |
10874 | /* If this is a test for negative, we can make an explicit |
10875 | test of the sign bit. */ | |
10876 | ||
10877 | if (op1 == const0_rtx && (code == LT || code == GE) | |
10878 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 10879 | { |
bcb34aa3 PB |
10880 | op0 = simplify_gen_binary (AND, tmode, |
10881 | gen_lowpart (tmode, op0), | |
10882 | GEN_INT ((HOST_WIDE_INT) 1 | |
10883 | << (GET_MODE_BITSIZE (mode) | |
10884 | - 1))); | |
230d793d | 10885 | code = (code == LT) ? NE : EQ; |
a687e897 | 10886 | break; |
230d793d | 10887 | } |
230d793d RS |
10888 | } |
10889 | ||
b7a775b2 RK |
10890 | #ifdef CANONICALIZE_COMPARISON |
10891 | /* If this machine only supports a subset of valid comparisons, see if we | |
10892 | can convert an unsupported one into a supported one. */ | |
10893 | CANONICALIZE_COMPARISON (code, op0, op1); | |
10894 | #endif | |
10895 | ||
230d793d RS |
10896 | *pop0 = op0; |
10897 | *pop1 = op1; | |
10898 | ||
10899 | return code; | |
10900 | } | |
10901 | \f | |
49c3b9a8 JJ |
10902 | /* Utility function for record_value_for_reg. Count number of |
10903 | rtxs in X. */ | |
10904 | static int | |
10905 | count_rtxs (rtx x) | |
10906 | { | |
10907 | enum rtx_code code = GET_CODE (x); | |
10908 | const char *fmt; | |
10909 | int i, ret = 1; | |
10910 | ||
10911 | if (GET_RTX_CLASS (code) == '2' | |
10912 | || GET_RTX_CLASS (code) == 'c') | |
10913 | { | |
10914 | rtx x0 = XEXP (x, 0); | |
10915 | rtx x1 = XEXP (x, 1); | |
10916 | ||
10917 | if (x0 == x1) | |
10918 | return 1 + 2 * count_rtxs (x0); | |
10919 | ||
10920 | if ((GET_RTX_CLASS (GET_CODE (x1)) == '2' | |
10921 | || GET_RTX_CLASS (GET_CODE (x1)) == 'c') | |
10922 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
10923 | return 2 + 2 * count_rtxs (x0) | |
10924 | + count_rtxs (x == XEXP (x1, 0) | |
10925 | ? XEXP (x1, 1) : XEXP (x1, 0)); | |
10926 | ||
10927 | if ((GET_RTX_CLASS (GET_CODE (x0)) == '2' | |
10928 | || GET_RTX_CLASS (GET_CODE (x0)) == 'c') | |
10929 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
10930 | return 2 + 2 * count_rtxs (x1) | |
10931 | + count_rtxs (x == XEXP (x0, 0) | |
10932 | ? XEXP (x0, 1) : XEXP (x0, 0)); | |
10933 | } | |
10934 | ||
10935 | fmt = GET_RTX_FORMAT (code); | |
10936 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
10937 | if (fmt[i] == 'e') | |
10938 | ret += count_rtxs (XEXP (x, i)); | |
10939 | ||
10940 | return ret; | |
10941 | } | |
10942 | \f | |
230d793d | 10943 | /* Utility function for following routine. Called when X is part of a value |
5eaad481 | 10944 | being stored into last_set_value. Sets last_set_table_tick |
230d793d RS |
10945 | for each register mentioned. Similar to mention_regs in cse.c */ |
10946 | ||
10947 | static void | |
79a490a9 | 10948 | update_table_tick (rtx x) |
230d793d | 10949 | { |
b3694847 SS |
10950 | enum rtx_code code = GET_CODE (x); |
10951 | const char *fmt = GET_RTX_FORMAT (code); | |
10952 | int i; | |
230d793d RS |
10953 | |
10954 | if (code == REG) | |
10955 | { | |
770ae6cc RK |
10956 | unsigned int regno = REGNO (x); |
10957 | unsigned int endregno | |
10958 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 10959 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
770ae6cc | 10960 | unsigned int r; |
230d793d | 10961 | |
770ae6cc | 10962 | for (r = regno; r < endregno; r++) |
5eaad481 | 10963 | reg_stat[r].last_set_table_tick = label_tick; |
230d793d RS |
10964 | |
10965 | return; | |
10966 | } | |
663522cb | 10967 | |
230d793d RS |
10968 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
10969 | /* Note that we can't have an "E" in values stored; see | |
10970 | get_last_value_validate. */ | |
10971 | if (fmt[i] == 'e') | |
8fd73754 AN |
10972 | { |
10973 | /* Check for identical subexpressions. If x contains | |
10974 | identical subexpression we only have to traverse one of | |
10975 | them. */ | |
ec8e098d | 10976 | if (i == 0 && ARITHMETIC_P (x)) |
8fd73754 AN |
10977 | { |
10978 | /* Note that at this point x1 has already been | |
10979 | processed. */ | |
10980 | rtx x0 = XEXP (x, 0); | |
10981 | rtx x1 = XEXP (x, 1); | |
10982 | ||
10983 | /* If x0 and x1 are identical then there is no need to | |
10984 | process x0. */ | |
10985 | if (x0 == x1) | |
10986 | break; | |
10987 | ||
10988 | /* If x0 is identical to a subexpression of x1 then while | |
10989 | processing x1, x0 has already been processed. Thus we | |
10990 | are done with x. */ | |
ec8e098d | 10991 | if (ARITHMETIC_P (x1) |
8fd73754 AN |
10992 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
10993 | break; | |
10994 | ||
10995 | /* If x1 is identical to a subexpression of x0 then we | |
10996 | still have to process the rest of x0. */ | |
ec8e098d | 10997 | if (ARITHMETIC_P (x0) |
8fd73754 AN |
10998 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
10999 | { | |
11000 | update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); | |
11001 | break; | |
11002 | } | |
11003 | } | |
73a39fc4 | 11004 | |
8fd73754 AN |
11005 | update_table_tick (XEXP (x, i)); |
11006 | } | |
230d793d RS |
11007 | } |
11008 | ||
11009 | /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
11010 | are saying that the register is clobbered and we no longer know its | |
5eaad481 PB |
11011 | value. If INSN is zero, don't update reg_stat[].last_set; this is |
11012 | only permitted with VALUE also zero and is used to invalidate the | |
11013 | register. */ | |
230d793d RS |
11014 | |
11015 | static void | |
79a490a9 | 11016 | record_value_for_reg (rtx reg, rtx insn, rtx value) |
230d793d | 11017 | { |
770ae6cc RK |
11018 | unsigned int regno = REGNO (reg); |
11019 | unsigned int endregno | |
11020 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11021 | ? hard_regno_nregs[regno][GET_MODE (reg)] : 1); |
770ae6cc | 11022 | unsigned int i; |
230d793d RS |
11023 | |
11024 | /* If VALUE contains REG and we have a previous value for REG, substitute | |
11025 | the previous value. */ | |
11026 | if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
11027 | { | |
11028 | rtx tem; | |
11029 | ||
11030 | /* Set things up so get_last_value is allowed to see anything set up to | |
11031 | our insn. */ | |
11032 | subst_low_cuid = INSN_CUID (insn); | |
663522cb | 11033 | tem = get_last_value (reg); |
230d793d | 11034 | |
14a774a9 RK |
11035 | /* If TEM is simply a binary operation with two CLOBBERs as operands, |
11036 | it isn't going to be useful and will take a lot of time to process, | |
11037 | so just use the CLOBBER. */ | |
11038 | ||
230d793d | 11039 | if (tem) |
14a774a9 | 11040 | { |
ec8e098d | 11041 | if (ARITHMETIC_P (tem) |
14a774a9 RK |
11042 | && GET_CODE (XEXP (tem, 0)) == CLOBBER |
11043 | && GET_CODE (XEXP (tem, 1)) == CLOBBER) | |
11044 | tem = XEXP (tem, 0); | |
49c3b9a8 JJ |
11045 | else if (count_occurrences (value, reg, 1) >= 2) |
11046 | { | |
11047 | /* If there are two or more occurrences of REG in VALUE, | |
11048 | prevent the value from growing too much. */ | |
11049 | if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) | |
11050 | tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); | |
11051 | } | |
14a774a9 RK |
11052 | |
11053 | value = replace_rtx (copy_rtx (value), reg, tem); | |
11054 | } | |
230d793d RS |
11055 | } |
11056 | ||
11057 | /* For each register modified, show we don't know its value, that | |
ef026f91 RS |
11058 | we don't know about its bitwise content, that its value has been |
11059 | updated, and that we don't know the location of the death of the | |
11060 | register. */ | |
770ae6cc | 11061 | for (i = regno; i < endregno; i++) |
230d793d RS |
11062 | { |
11063 | if (insn) | |
5eaad481 | 11064 | reg_stat[i].last_set = insn; |
770ae6cc | 11065 | |
5eaad481 PB |
11066 | reg_stat[i].last_set_value = 0; |
11067 | reg_stat[i].last_set_mode = 0; | |
11068 | reg_stat[i].last_set_nonzero_bits = 0; | |
11069 | reg_stat[i].last_set_sign_bit_copies = 0; | |
11070 | reg_stat[i].last_death = 0; | |
230d793d RS |
11071 | } |
11072 | ||
11073 | /* Mark registers that are being referenced in this value. */ | |
11074 | if (value) | |
11075 | update_table_tick (value); | |
11076 | ||
11077 | /* Now update the status of each register being set. | |
11078 | If someone is using this register in this block, set this register | |
11079 | to invalid since we will get confused between the two lives in this | |
11080 | basic block. This makes using this register always invalid. In cse, we | |
11081 | scan the table to invalidate all entries using this register, but this | |
11082 | is too much work for us. */ | |
11083 | ||
11084 | for (i = regno; i < endregno; i++) | |
11085 | { | |
5eaad481 PB |
11086 | reg_stat[i].last_set_label = label_tick; |
11087 | if (value && reg_stat[i].last_set_table_tick == label_tick) | |
11088 | reg_stat[i].last_set_invalid = 1; | |
230d793d | 11089 | else |
5eaad481 | 11090 | reg_stat[i].last_set_invalid = 0; |
230d793d RS |
11091 | } |
11092 | ||
11093 | /* The value being assigned might refer to X (like in "x++;"). In that | |
11094 | case, we must replace it with (clobber (const_int 0)) to prevent | |
11095 | infinite loops. */ | |
9a893315 | 11096 | if (value && ! get_last_value_validate (&value, insn, |
5eaad481 | 11097 | reg_stat[regno].last_set_label, 0)) |
230d793d RS |
11098 | { |
11099 | value = copy_rtx (value); | |
9a893315 | 11100 | if (! get_last_value_validate (&value, insn, |
5eaad481 | 11101 | reg_stat[regno].last_set_label, 1)) |
230d793d RS |
11102 | value = 0; |
11103 | } | |
11104 | ||
55310dad RK |
11105 | /* For the main register being modified, update the value, the mode, the |
11106 | nonzero bits, and the number of sign bit copies. */ | |
11107 | ||
5eaad481 | 11108 | reg_stat[regno].last_set_value = value; |
230d793d | 11109 | |
55310dad RK |
11110 | if (value) |
11111 | { | |
0a0440c9 | 11112 | enum machine_mode mode = GET_MODE (reg); |
2afabb48 | 11113 | subst_low_cuid = INSN_CUID (insn); |
5eaad481 | 11114 | reg_stat[regno].last_set_mode = mode; |
0a0440c9 JJ |
11115 | if (GET_MODE_CLASS (mode) == MODE_INT |
11116 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
11117 | mode = nonzero_bits_mode; | |
5eaad481 PB |
11118 | reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode); |
11119 | reg_stat[regno].last_set_sign_bit_copies | |
55310dad RK |
11120 | = num_sign_bit_copies (value, GET_MODE (reg)); |
11121 | } | |
230d793d RS |
11122 | } |
11123 | ||
230d793d | 11124 | /* Called via note_stores from record_dead_and_set_regs to handle one |
84832317 MM |
11125 | SET or CLOBBER in an insn. DATA is the instruction in which the |
11126 | set is occurring. */ | |
230d793d RS |
11127 | |
11128 | static void | |
79a490a9 | 11129 | record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data) |
230d793d | 11130 | { |
84832317 MM |
11131 | rtx record_dead_insn = (rtx) data; |
11132 | ||
ca89d290 RK |
11133 | if (GET_CODE (dest) == SUBREG) |
11134 | dest = SUBREG_REG (dest); | |
11135 | ||
f8cfc6aa | 11136 | if (REG_P (dest)) |
230d793d RS |
11137 | { |
11138 | /* If we are setting the whole register, we know its value. Otherwise | |
11139 | show that we don't know the value. We can handle SUBREG in | |
11140 | some cases. */ | |
11141 | if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
11142 | record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
11143 | else if (GET_CODE (setter) == SET | |
11144 | && GET_CODE (SET_DEST (setter)) == SUBREG | |
11145 | && SUBREG_REG (SET_DEST (setter)) == dest | |
90bf8081 | 11146 | && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD |
230d793d | 11147 | && subreg_lowpart_p (SET_DEST (setter))) |
d0ab8cd3 | 11148 | record_value_for_reg (dest, record_dead_insn, |
4de249d9 | 11149 | gen_lowpart (GET_MODE (dest), |
d0ab8cd3 | 11150 | SET_SRC (setter))); |
230d793d | 11151 | else |
5f4f0e22 | 11152 | record_value_for_reg (dest, record_dead_insn, NULL_RTX); |
230d793d | 11153 | } |
3c0cb5de | 11154 | else if (MEM_P (dest) |
230d793d RS |
11155 | /* Ignore pushes, they clobber nothing. */ |
11156 | && ! push_operand (dest, GET_MODE (dest))) | |
11157 | mem_last_set = INSN_CUID (record_dead_insn); | |
11158 | } | |
11159 | ||
11160 | /* Update the records of when each REG was most recently set or killed | |
11161 | for the things done by INSN. This is the last thing done in processing | |
11162 | INSN in the combiner loop. | |
11163 | ||
5eaad481 PB |
11164 | We update reg_stat[], in particular fields last_set, last_set_value, |
11165 | last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, | |
11166 | last_death, and also the similar information mem_last_set (which insn | |
11167 | most recently modified memory) and last_call_cuid (which insn was the | |
11168 | most recent subroutine call). */ | |
230d793d RS |
11169 | |
11170 | static void | |
79a490a9 | 11171 | record_dead_and_set_regs (rtx insn) |
230d793d | 11172 | { |
b3694847 | 11173 | rtx link; |
770ae6cc | 11174 | unsigned int i; |
55310dad | 11175 | |
230d793d RS |
11176 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
11177 | { | |
dbc131f3 | 11178 | if (REG_NOTE_KIND (link) == REG_DEAD |
f8cfc6aa | 11179 | && REG_P (XEXP (link, 0))) |
dbc131f3 | 11180 | { |
770ae6cc RK |
11181 | unsigned int regno = REGNO (XEXP (link, 0)); |
11182 | unsigned int endregno | |
dbc131f3 | 11183 | = regno + (regno < FIRST_PSEUDO_REGISTER |
66fd46b6 | 11184 | ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))] |
dbc131f3 | 11185 | : 1); |
dbc131f3 RK |
11186 | |
11187 | for (i = regno; i < endregno; i++) | |
5eaad481 | 11188 | reg_stat[i].last_death = insn; |
dbc131f3 | 11189 | } |
230d793d | 11190 | else if (REG_NOTE_KIND (link) == REG_INC) |
5f4f0e22 | 11191 | record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); |
230d793d RS |
11192 | } |
11193 | ||
4b4bf941 | 11194 | if (CALL_P (insn)) |
55310dad RK |
11195 | { |
11196 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
29655d3d | 11197 | if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) |
55310dad | 11198 | { |
5eaad481 PB |
11199 | reg_stat[i].last_set_value = 0; |
11200 | reg_stat[i].last_set_mode = 0; | |
11201 | reg_stat[i].last_set_nonzero_bits = 0; | |
11202 | reg_stat[i].last_set_sign_bit_copies = 0; | |
11203 | reg_stat[i].last_death = 0; | |
55310dad RK |
11204 | } |
11205 | ||
11206 | last_call_cuid = mem_last_set = INSN_CUID (insn); | |
29655d3d ZW |
11207 | |
11208 | /* Don't bother recording what this insn does. It might set the | |
11209 | return value register, but we can't combine into a call | |
11210 | pattern anyway, so there's no point trying (and it may cause | |
11211 | a crash, if e.g. we wind up asking for last_set_value of a | |
11212 | SUBREG of the return value register). */ | |
11213 | return; | |
55310dad | 11214 | } |
230d793d | 11215 | |
84832317 | 11216 | note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); |
230d793d | 11217 | } |
732f2ac9 | 11218 | |
732f2ac9 JJ |
11219 | /* If a SUBREG has the promoted bit set, it is in fact a property of the |
11220 | register present in the SUBREG, so for each such SUBREG go back and | |
11221 | adjust nonzero and sign bit information of the registers that are | |
11222 | known to have some zero/sign bits set. | |
11223 | ||
11224 | This is needed because when combine blows the SUBREGs away, the | |
11225 | information on zero/sign bits is lost and further combines can be | |
11226 | missed because of that. */ | |
11227 | ||
11228 | static void | |
79a490a9 | 11229 | record_promoted_value (rtx insn, rtx subreg) |
732f2ac9 | 11230 | { |
4a71b24f | 11231 | rtx links, set; |
770ae6cc | 11232 | unsigned int regno = REGNO (SUBREG_REG (subreg)); |
732f2ac9 JJ |
11233 | enum machine_mode mode = GET_MODE (subreg); |
11234 | ||
25af74a0 | 11235 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
732f2ac9 JJ |
11236 | return; |
11237 | ||
663522cb | 11238 | for (links = LOG_LINKS (insn); links;) |
732f2ac9 JJ |
11239 | { |
11240 | insn = XEXP (links, 0); | |
11241 | set = single_set (insn); | |
11242 | ||
f8cfc6aa | 11243 | if (! set || !REG_P (SET_DEST (set)) |
732f2ac9 JJ |
11244 | || REGNO (SET_DEST (set)) != regno |
11245 | || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) | |
11246 | { | |
11247 | links = XEXP (links, 1); | |
11248 | continue; | |
11249 | } | |
11250 | ||
5eaad481 | 11251 | if (reg_stat[regno].last_set == insn) |
663522cb | 11252 | { |
7879b81e | 11253 | if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0) |
5eaad481 | 11254 | reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode); |
663522cb | 11255 | } |
732f2ac9 | 11256 | |
f8cfc6aa | 11257 | if (REG_P (SET_SRC (set))) |
732f2ac9 JJ |
11258 | { |
11259 | regno = REGNO (SET_SRC (set)); | |
11260 | links = LOG_LINKS (insn); | |
11261 | } | |
11262 | else | |
11263 | break; | |
11264 | } | |
11265 | } | |
11266 | ||
11267 | /* Scan X for promoted SUBREGs. For each one found, | |
11268 | note what it implies to the registers used in it. */ | |
11269 | ||
11270 | static void | |
79a490a9 | 11271 | check_promoted_subreg (rtx insn, rtx x) |
732f2ac9 JJ |
11272 | { |
11273 | if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) | |
f8cfc6aa | 11274 | && REG_P (SUBREG_REG (x))) |
732f2ac9 JJ |
11275 | record_promoted_value (insn, x); |
11276 | else | |
11277 | { | |
11278 | const char *format = GET_RTX_FORMAT (GET_CODE (x)); | |
11279 | int i, j; | |
11280 | ||
11281 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) | |
663522cb | 11282 | switch (format[i]) |
732f2ac9 JJ |
11283 | { |
11284 | case 'e': | |
11285 | check_promoted_subreg (insn, XEXP (x, i)); | |
11286 | break; | |
11287 | case 'V': | |
11288 | case 'E': | |
11289 | if (XVEC (x, i) != 0) | |
11290 | for (j = 0; j < XVECLEN (x, i); j++) | |
11291 | check_promoted_subreg (insn, XVECEXP (x, i, j)); | |
11292 | break; | |
11293 | } | |
11294 | } | |
11295 | } | |
230d793d RS |
11296 | \f |
11297 | /* Utility routine for the following function. Verify that all the registers | |
11298 | mentioned in *LOC are valid when *LOC was part of a value set when | |
11299 | label_tick == TICK. Return 0 if some are not. | |
11300 | ||
da7d8304 | 11301 | If REPLACE is nonzero, replace the invalid reference with |
230d793d RS |
11302 | (clobber (const_int 0)) and return 1. This replacement is useful because |
11303 | we often can get useful information about the form of a value (e.g., if | |
11304 | it was produced by a shift that always produces -1 or 0) even though | |
11305 | we don't know exactly what registers it was produced from. */ | |
11306 | ||
11307 | static int | |
79a490a9 | 11308 | get_last_value_validate (rtx *loc, rtx insn, int tick, int replace) |
230d793d RS |
11309 | { |
11310 | rtx x = *loc; | |
6f7d635c | 11311 | const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); |
230d793d RS |
11312 | int len = GET_RTX_LENGTH (GET_CODE (x)); |
11313 | int i; | |
11314 | ||
f8cfc6aa | 11315 | if (REG_P (x)) |
230d793d | 11316 | { |
770ae6cc RK |
11317 | unsigned int regno = REGNO (x); |
11318 | unsigned int endregno | |
11319 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11320 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
770ae6cc | 11321 | unsigned int j; |
230d793d RS |
11322 | |
11323 | for (j = regno; j < endregno; j++) | |
5eaad481 | 11324 | if (reg_stat[j].last_set_invalid |
57cf50a4 GRK |
11325 | /* If this is a pseudo-register that was only set once and not |
11326 | live at the beginning of the function, it is always valid. */ | |
663522cb | 11327 | || (! (regno >= FIRST_PSEUDO_REGISTER |
57cf50a4 | 11328 | && REG_N_SETS (regno) == 1 |
770ae6cc | 11329 | && (! REGNO_REG_SET_P |
5e2d947c JH |
11330 | (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, |
11331 | regno))) | |
5eaad481 | 11332 | && reg_stat[j].last_set_label > tick)) |
230d793d RS |
11333 | { |
11334 | if (replace) | |
38a448ca | 11335 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
11336 | return replace; |
11337 | } | |
11338 | ||
11339 | return 1; | |
11340 | } | |
9a893315 JW |
11341 | /* If this is a memory reference, make sure that there were |
11342 | no stores after it that might have clobbered the value. We don't | |
11343 | have alias info, so we assume any store invalidates it. */ | |
389fdba0 | 11344 | else if (MEM_P (x) && !MEM_READONLY_P (x) |
9a893315 JW |
11345 | && INSN_CUID (insn) <= mem_last_set) |
11346 | { | |
11347 | if (replace) | |
38a448ca | 11348 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
9a893315 JW |
11349 | return replace; |
11350 | } | |
230d793d RS |
11351 | |
11352 | for (i = 0; i < len; i++) | |
8fd73754 AN |
11353 | { |
11354 | if (fmt[i] == 'e') | |
11355 | { | |
11356 | /* Check for identical subexpressions. If x contains | |
11357 | identical subexpression we only have to traverse one of | |
11358 | them. */ | |
ec8e098d | 11359 | if (i == 1 && ARITHMETIC_P (x)) |
8fd73754 AN |
11360 | { |
11361 | /* Note that at this point x0 has already been checked | |
11362 | and found valid. */ | |
11363 | rtx x0 = XEXP (x, 0); | |
11364 | rtx x1 = XEXP (x, 1); | |
11365 | ||
11366 | /* If x0 and x1 are identical then x is also valid. */ | |
11367 | if (x0 == x1) | |
11368 | return 1; | |
11369 | ||
11370 | /* If x1 is identical to a subexpression of x0 then | |
11371 | while checking x0, x1 has already been checked. Thus | |
11372 | it is valid and so as x. */ | |
ec8e098d | 11373 | if (ARITHMETIC_P (x0) |
8fd73754 AN |
11374 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
11375 | return 1; | |
11376 | ||
11377 | /* If x0 is identical to a subexpression of x1 then x is | |
11378 | valid iff the rest of x1 is valid. */ | |
ec8e098d | 11379 | if (ARITHMETIC_P (x1) |
8fd73754 AN |
11380 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
11381 | return | |
11382 | get_last_value_validate (&XEXP (x1, | |
11383 | x0 == XEXP (x1, 0) ? 1 : 0), | |
11384 | insn, tick, replace); | |
11385 | } | |
11386 | ||
11387 | if (get_last_value_validate (&XEXP (x, i), insn, tick, | |
11388 | replace) == 0) | |
11389 | return 0; | |
11390 | } | |
11391 | /* Don't bother with these. They shouldn't occur anyway. */ | |
11392 | else if (fmt[i] == 'E') | |
11393 | return 0; | |
11394 | } | |
230d793d RS |
11395 | |
11396 | /* If we haven't found a reason for it to be invalid, it is valid. */ | |
11397 | return 1; | |
11398 | } | |
11399 | ||
11400 | /* Get the last value assigned to X, if known. Some registers | |
11401 | in the value may be replaced with (clobber (const_int 0)) if their value | |
11402 | is known longer known reliably. */ | |
11403 | ||
11404 | static rtx | |
79a490a9 | 11405 | get_last_value (rtx x) |
230d793d | 11406 | { |
770ae6cc | 11407 | unsigned int regno; |
230d793d RS |
11408 | rtx value; |
11409 | ||
11410 | /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
11411 | then convert it to the desired mode. If this is a paradoxical SUBREG, | |
0f41302f | 11412 | we cannot predict what values the "extra" bits might have. */ |
230d793d RS |
11413 | if (GET_CODE (x) == SUBREG |
11414 | && subreg_lowpart_p (x) | |
11415 | && (GET_MODE_SIZE (GET_MODE (x)) | |
11416 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
11417 | && (value = get_last_value (SUBREG_REG (x))) != 0) | |
4de249d9 | 11418 | return gen_lowpart (GET_MODE (x), value); |
230d793d | 11419 | |
f8cfc6aa | 11420 | if (!REG_P (x)) |
230d793d RS |
11421 | return 0; |
11422 | ||
11423 | regno = REGNO (x); | |
5eaad481 | 11424 | value = reg_stat[regno].last_set_value; |
230d793d | 11425 | |
57cf50a4 GRK |
11426 | /* If we don't have a value, or if it isn't for this basic block and |
11427 | it's either a hard register, set more than once, or it's a live | |
663522cb | 11428 | at the beginning of the function, return 0. |
57cf50a4 | 11429 | |
eaec9b3d | 11430 | Because if it's not live at the beginning of the function then the reg |
57cf50a4 GRK |
11431 | is always set before being used (is never used without being set). |
11432 | And, if it's set only once, and it's always set before use, then all | |
11433 | uses must have the same last value, even if it's not from this basic | |
11434 | block. */ | |
230d793d RS |
11435 | |
11436 | if (value == 0 | |
5eaad481 | 11437 | || (reg_stat[regno].last_set_label != label_tick |
57cf50a4 GRK |
11438 | && (regno < FIRST_PSEUDO_REGISTER |
11439 | || REG_N_SETS (regno) != 1 | |
770ae6cc | 11440 | || (REGNO_REG_SET_P |
5e2d947c JH |
11441 | (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, |
11442 | regno))))) | |
230d793d RS |
11443 | return 0; |
11444 | ||
4255220d | 11445 | /* If the value was set in a later insn than the ones we are processing, |
ca4cd906 | 11446 | we can't use it even if the register was only set once. */ |
5eaad481 | 11447 | if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid) |
ca4cd906 | 11448 | return 0; |
d0ab8cd3 RK |
11449 | |
11450 | /* If the value has all its registers valid, return it. */ | |
5eaad481 PB |
11451 | if (get_last_value_validate (&value, reg_stat[regno].last_set, |
11452 | reg_stat[regno].last_set_label, 0)) | |
230d793d RS |
11453 | return value; |
11454 | ||
11455 | /* Otherwise, make a copy and replace any invalid register with | |
11456 | (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
11457 | ||
11458 | value = copy_rtx (value); | |
5eaad481 PB |
11459 | if (get_last_value_validate (&value, reg_stat[regno].last_set, |
11460 | reg_stat[regno].last_set_label, 1)) | |
230d793d RS |
11461 | return value; |
11462 | ||
11463 | return 0; | |
11464 | } | |
11465 | \f | |
11466 | /* Return nonzero if expression X refers to a REG or to memory | |
11467 | that is set in an instruction more recent than FROM_CUID. */ | |
11468 | ||
11469 | static int | |
79a490a9 | 11470 | use_crosses_set_p (rtx x, int from_cuid) |
230d793d | 11471 | { |
b3694847 SS |
11472 | const char *fmt; |
11473 | int i; | |
11474 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
11475 | |
11476 | if (code == REG) | |
11477 | { | |
770ae6cc RK |
11478 | unsigned int regno = REGNO (x); |
11479 | unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11480 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
663522cb | 11481 | |
230d793d RS |
11482 | #ifdef PUSH_ROUNDING |
11483 | /* Don't allow uses of the stack pointer to be moved, | |
11484 | because we don't know whether the move crosses a push insn. */ | |
f73ad30e | 11485 | if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) |
230d793d RS |
11486 | return 1; |
11487 | #endif | |
770ae6cc | 11488 | for (; regno < endreg; regno++) |
5eaad481 PB |
11489 | if (reg_stat[regno].last_set |
11490 | && INSN_CUID (reg_stat[regno].last_set) > from_cuid) | |
e28f5732 RK |
11491 | return 1; |
11492 | return 0; | |
230d793d RS |
11493 | } |
11494 | ||
11495 | if (code == MEM && mem_last_set > from_cuid) | |
11496 | return 1; | |
11497 | ||
11498 | fmt = GET_RTX_FORMAT (code); | |
11499 | ||
11500 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11501 | { | |
11502 | if (fmt[i] == 'E') | |
11503 | { | |
b3694847 | 11504 | int j; |
230d793d RS |
11505 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
11506 | if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) | |
11507 | return 1; | |
11508 | } | |
11509 | else if (fmt[i] == 'e' | |
11510 | && use_crosses_set_p (XEXP (x, i), from_cuid)) | |
11511 | return 1; | |
11512 | } | |
11513 | return 0; | |
11514 | } | |
11515 | \f | |
11516 | /* Define three variables used for communication between the following | |
11517 | routines. */ | |
11518 | ||
770ae6cc | 11519 | static unsigned int reg_dead_regno, reg_dead_endregno; |
230d793d RS |
11520 | static int reg_dead_flag; |
11521 | ||
11522 | /* Function called via note_stores from reg_dead_at_p. | |
11523 | ||
663522cb | 11524 | If DEST is within [reg_dead_regno, reg_dead_endregno), set |
230d793d RS |
11525 | reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ |
11526 | ||
11527 | static void | |
79a490a9 | 11528 | reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) |
230d793d | 11529 | { |
770ae6cc | 11530 | unsigned int regno, endregno; |
230d793d | 11531 | |
f8cfc6aa | 11532 | if (!REG_P (dest)) |
230d793d RS |
11533 | return; |
11534 | ||
11535 | regno = REGNO (dest); | |
663522cb | 11536 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
66fd46b6 | 11537 | ? hard_regno_nregs[regno][GET_MODE (dest)] : 1); |
230d793d RS |
11538 | |
11539 | if (reg_dead_endregno > regno && reg_dead_regno < endregno) | |
11540 | reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
11541 | } | |
11542 | ||
da7d8304 | 11543 | /* Return nonzero if REG is known to be dead at INSN. |
230d793d RS |
11544 | |
11545 | We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
11546 | referencing REG, it is dead. If we hit a SET referencing REG, it is | |
11547 | live. Otherwise, see if it is live or dead at the start of the basic | |
6e25d159 RK |
11548 | block we are in. Hard regs marked as being live in NEWPAT_USED_REGS |
11549 | must be assumed to be always live. */ | |
230d793d RS |
11550 | |
11551 | static int | |
79a490a9 | 11552 | reg_dead_at_p (rtx reg, rtx insn) |
230d793d | 11553 | { |
e0082a72 | 11554 | basic_block block; |
770ae6cc | 11555 | unsigned int i; |
230d793d RS |
11556 | |
11557 | /* Set variables for reg_dead_at_p_1. */ | |
11558 | reg_dead_regno = REGNO (reg); | |
11559 | reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 JH |
11560 | ? hard_regno_nregs[reg_dead_regno] |
11561 | [GET_MODE (reg)] | |
230d793d RS |
11562 | : 1); |
11563 | ||
11564 | reg_dead_flag = 0; | |
11565 | ||
45da19e3 UW |
11566 | /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers |
11567 | we allow the machine description to decide whether use-and-clobber | |
11568 | patterns are OK. */ | |
6e25d159 RK |
11569 | if (reg_dead_regno < FIRST_PSEUDO_REGISTER) |
11570 | { | |
11571 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
45da19e3 | 11572 | if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) |
6e25d159 RK |
11573 | return 0; |
11574 | } | |
11575 | ||
230d793d RS |
11576 | /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or |
11577 | beginning of function. */ | |
4b4bf941 | 11578 | for (; insn && !LABEL_P (insn) && !BARRIER_P (insn); |
230d793d RS |
11579 | insn = prev_nonnote_insn (insn)) |
11580 | { | |
84832317 | 11581 | note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); |
230d793d RS |
11582 | if (reg_dead_flag) |
11583 | return reg_dead_flag == 1 ? 1 : 0; | |
11584 | ||
11585 | if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) | |
11586 | return 1; | |
11587 | } | |
11588 | ||
e0082a72 | 11589 | /* Get the basic block that we were in. */ |
230d793d | 11590 | if (insn == 0) |
e0082a72 | 11591 | block = ENTRY_BLOCK_PTR->next_bb; |
230d793d RS |
11592 | else |
11593 | { | |
e0082a72 | 11594 | FOR_EACH_BB (block) |
a813c111 | 11595 | if (insn == BB_HEAD (block)) |
230d793d RS |
11596 | break; |
11597 | ||
e0082a72 | 11598 | if (block == EXIT_BLOCK_PTR) |
230d793d RS |
11599 | return 0; |
11600 | } | |
11601 | ||
11602 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
5e2d947c | 11603 | if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i)) |
230d793d RS |
11604 | return 0; |
11605 | ||
11606 | return 1; | |
11607 | } | |
6e25d159 RK |
11608 | \f |
11609 | /* Note hard registers in X that are used. This code is similar to | |
11610 | that in flow.c, but much simpler since we don't care about pseudos. */ | |
11611 | ||
11612 | static void | |
79a490a9 | 11613 | mark_used_regs_combine (rtx x) |
6e25d159 | 11614 | { |
770ae6cc RK |
11615 | RTX_CODE code = GET_CODE (x); |
11616 | unsigned int regno; | |
6e25d159 RK |
11617 | int i; |
11618 | ||
11619 | switch (code) | |
11620 | { | |
11621 | case LABEL_REF: | |
11622 | case SYMBOL_REF: | |
11623 | case CONST_INT: | |
11624 | case CONST: | |
11625 | case CONST_DOUBLE: | |
69ef87e2 | 11626 | case CONST_VECTOR: |
6e25d159 RK |
11627 | case PC: |
11628 | case ADDR_VEC: | |
11629 | case ADDR_DIFF_VEC: | |
11630 | case ASM_INPUT: | |
11631 | #ifdef HAVE_cc0 | |
11632 | /* CC0 must die in the insn after it is set, so we don't need to take | |
11633 | special note of it here. */ | |
11634 | case CC0: | |
11635 | #endif | |
11636 | return; | |
11637 | ||
11638 | case CLOBBER: | |
11639 | /* If we are clobbering a MEM, mark any hard registers inside the | |
11640 | address as used. */ | |
3c0cb5de | 11641 | if (MEM_P (XEXP (x, 0))) |
6e25d159 RK |
11642 | mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); |
11643 | return; | |
11644 | ||
11645 | case REG: | |
11646 | regno = REGNO (x); | |
11647 | /* A hard reg in a wide mode may really be multiple registers. | |
11648 | If so, mark all of them just like the first. */ | |
11649 | if (regno < FIRST_PSEUDO_REGISTER) | |
11650 | { | |
770ae6cc RK |
11651 | unsigned int endregno, r; |
11652 | ||
3eae4643 | 11653 | /* None of this applies to the stack, frame or arg pointers. */ |
6e25d159 RK |
11654 | if (regno == STACK_POINTER_REGNUM |
11655 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
11656 | || regno == HARD_FRAME_POINTER_REGNUM | |
11657 | #endif | |
11658 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
11659 | || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
11660 | #endif | |
11661 | || regno == FRAME_POINTER_REGNUM) | |
11662 | return; | |
11663 | ||
66fd46b6 | 11664 | endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc RK |
11665 | for (r = regno; r < endregno; r++) |
11666 | SET_HARD_REG_BIT (newpat_used_regs, r); | |
6e25d159 RK |
11667 | } |
11668 | return; | |
11669 | ||
11670 | case SET: | |
11671 | { | |
11672 | /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in | |
11673 | the address. */ | |
b3694847 | 11674 | rtx testreg = SET_DEST (x); |
6e25d159 | 11675 | |
e048778f RK |
11676 | while (GET_CODE (testreg) == SUBREG |
11677 | || GET_CODE (testreg) == ZERO_EXTRACT | |
e048778f | 11678 | || GET_CODE (testreg) == STRICT_LOW_PART) |
6e25d159 RK |
11679 | testreg = XEXP (testreg, 0); |
11680 | ||
3c0cb5de | 11681 | if (MEM_P (testreg)) |
6e25d159 RK |
11682 | mark_used_regs_combine (XEXP (testreg, 0)); |
11683 | ||
11684 | mark_used_regs_combine (SET_SRC (x)); | |
6e25d159 | 11685 | } |
e9a25f70 JL |
11686 | return; |
11687 | ||
11688 | default: | |
11689 | break; | |
6e25d159 RK |
11690 | } |
11691 | ||
11692 | /* Recursively scan the operands of this expression. */ | |
11693 | ||
11694 | { | |
b3694847 | 11695 | const char *fmt = GET_RTX_FORMAT (code); |
6e25d159 RK |
11696 | |
11697 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11698 | { | |
663522cb | 11699 | if (fmt[i] == 'e') |
6e25d159 | 11700 | mark_used_regs_combine (XEXP (x, i)); |
663522cb KH |
11701 | else if (fmt[i] == 'E') |
11702 | { | |
b3694847 | 11703 | int j; |
6e25d159 | 11704 | |
663522cb KH |
11705 | for (j = 0; j < XVECLEN (x, i); j++) |
11706 | mark_used_regs_combine (XVECEXP (x, i, j)); | |
11707 | } | |
6e25d159 RK |
11708 | } |
11709 | } | |
11710 | } | |
230d793d RS |
11711 | \f |
11712 | /* Remove register number REGNO from the dead registers list of INSN. | |
11713 | ||
11714 | Return the note used to record the death, if there was one. */ | |
11715 | ||
11716 | rtx | |
79a490a9 | 11717 | remove_death (unsigned int regno, rtx insn) |
230d793d | 11718 | { |
b3694847 | 11719 | rtx note = find_regno_note (insn, REG_DEAD, regno); |
230d793d RS |
11720 | |
11721 | if (note) | |
1a26b032 | 11722 | { |
b1f21e0a | 11723 | REG_N_DEATHS (regno)--; |
1a26b032 RK |
11724 | remove_note (insn, note); |
11725 | } | |
230d793d RS |
11726 | |
11727 | return note; | |
11728 | } | |
11729 | ||
11730 | /* For each register (hardware or pseudo) used within expression X, if its | |
11731 | death is in an instruction with cuid between FROM_CUID (inclusive) and | |
11732 | TO_INSN (exclusive), put a REG_DEAD note for that register in the | |
663522cb | 11733 | list headed by PNOTES. |
230d793d | 11734 | |
6eb12cef RK |
11735 | That said, don't move registers killed by maybe_kill_insn. |
11736 | ||
230d793d RS |
11737 | This is done when X is being merged by combination into TO_INSN. These |
11738 | notes will then be distributed as needed. */ | |
11739 | ||
11740 | static void | |
79a490a9 AJ |
11741 | move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn, |
11742 | rtx *pnotes) | |
230d793d | 11743 | { |
b3694847 SS |
11744 | const char *fmt; |
11745 | int len, i; | |
11746 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
11747 | |
11748 | if (code == REG) | |
11749 | { | |
770ae6cc | 11750 | unsigned int regno = REGNO (x); |
5eaad481 | 11751 | rtx where_dead = reg_stat[regno].last_death; |
b3694847 | 11752 | rtx before_dead, after_dead; |
e340018d | 11753 | |
3eae4643 | 11754 | /* Don't move the register if it gets killed in between from and to. */ |
6eb12cef | 11755 | if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) |
770ae6cc | 11756 | && ! reg_referenced_p (x, maybe_kill_insn)) |
6eb12cef RK |
11757 | return; |
11758 | ||
e340018d JW |
11759 | /* WHERE_DEAD could be a USE insn made by combine, so first we |
11760 | make sure that we have insns with valid INSN_CUID values. */ | |
11761 | before_dead = where_dead; | |
11762 | while (before_dead && INSN_UID (before_dead) > max_uid_cuid) | |
11763 | before_dead = PREV_INSN (before_dead); | |
770ae6cc | 11764 | |
e340018d JW |
11765 | after_dead = where_dead; |
11766 | while (after_dead && INSN_UID (after_dead) > max_uid_cuid) | |
11767 | after_dead = NEXT_INSN (after_dead); | |
11768 | ||
11769 | if (before_dead && after_dead | |
11770 | && INSN_CUID (before_dead) >= from_cuid | |
11771 | && (INSN_CUID (after_dead) < INSN_CUID (to_insn) | |
11772 | || (where_dead != after_dead | |
11773 | && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) | |
230d793d | 11774 | { |
dbc131f3 | 11775 | rtx note = remove_death (regno, where_dead); |
230d793d RS |
11776 | |
11777 | /* It is possible for the call above to return 0. This can occur | |
5eaad481 | 11778 | when last_death points to I2 or I1 that we combined with. |
dbc131f3 RK |
11779 | In that case make a new note. |
11780 | ||
11781 | We must also check for the case where X is a hard register | |
11782 | and NOTE is a death note for a range of hard registers | |
11783 | including X. In that case, we must put REG_DEAD notes for | |
11784 | the remaining registers in place of NOTE. */ | |
11785 | ||
11786 | if (note != 0 && regno < FIRST_PSEUDO_REGISTER | |
11787 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
24e46fc4 | 11788 | > GET_MODE_SIZE (GET_MODE (x)))) |
dbc131f3 | 11789 | { |
770ae6cc RK |
11790 | unsigned int deadregno = REGNO (XEXP (note, 0)); |
11791 | unsigned int deadend | |
66fd46b6 JH |
11792 | = (deadregno + hard_regno_nregs[deadregno] |
11793 | [GET_MODE (XEXP (note, 0))]); | |
770ae6cc | 11794 | unsigned int ourend |
66fd46b6 | 11795 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 11796 | unsigned int i; |
dbc131f3 RK |
11797 | |
11798 | for (i = deadregno; i < deadend; i++) | |
11799 | if (i < regno || i >= ourend) | |
11800 | REG_NOTES (where_dead) | |
38a448ca | 11801 | = gen_rtx_EXPR_LIST (REG_DEAD, |
e50126e8 | 11802 | regno_reg_rtx[i], |
38a448ca | 11803 | REG_NOTES (where_dead)); |
dbc131f3 | 11804 | } |
770ae6cc | 11805 | |
24e46fc4 JW |
11806 | /* If we didn't find any note, or if we found a REG_DEAD note that |
11807 | covers only part of the given reg, and we have a multi-reg hard | |
fabd69e8 RK |
11808 | register, then to be safe we must check for REG_DEAD notes |
11809 | for each register other than the first. They could have | |
11810 | their own REG_DEAD notes lying around. */ | |
24e46fc4 JW |
11811 | else if ((note == 0 |
11812 | || (note != 0 | |
11813 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
11814 | < GET_MODE_SIZE (GET_MODE (x))))) | |
11815 | && regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11816 | && hard_regno_nregs[regno][GET_MODE (x)] > 1) |
fabd69e8 | 11817 | { |
770ae6cc | 11818 | unsigned int ourend |
66fd46b6 | 11819 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 11820 | unsigned int i, offset; |
fabd69e8 RK |
11821 | rtx oldnotes = 0; |
11822 | ||
24e46fc4 | 11823 | if (note) |
66fd46b6 | 11824 | offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; |
24e46fc4 JW |
11825 | else |
11826 | offset = 1; | |
11827 | ||
11828 | for (i = regno + offset; i < ourend; i++) | |
e50126e8 | 11829 | move_deaths (regno_reg_rtx[i], |
6eb12cef | 11830 | maybe_kill_insn, from_cuid, to_insn, &oldnotes); |
fabd69e8 | 11831 | } |
230d793d | 11832 | |
dbc131f3 | 11833 | if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) |
230d793d RS |
11834 | { |
11835 | XEXP (note, 1) = *pnotes; | |
11836 | *pnotes = note; | |
11837 | } | |
11838 | else | |
38a448ca | 11839 | *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); |
1a26b032 | 11840 | |
b1f21e0a | 11841 | REG_N_DEATHS (regno)++; |
230d793d RS |
11842 | } |
11843 | ||
11844 | return; | |
11845 | } | |
11846 | ||
11847 | else if (GET_CODE (x) == SET) | |
11848 | { | |
11849 | rtx dest = SET_DEST (x); | |
11850 | ||
6eb12cef | 11851 | move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d | 11852 | |
a7c99304 RK |
11853 | /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG |
11854 | that accesses one word of a multi-word item, some | |
11855 | piece of everything register in the expression is used by | |
11856 | this insn, so remove any old death. */ | |
ddef6bc7 | 11857 | /* ??? So why do we test for equality of the sizes? */ |
a7c99304 RK |
11858 | |
11859 | if (GET_CODE (dest) == ZERO_EXTRACT | |
11860 | || GET_CODE (dest) == STRICT_LOW_PART | |
11861 | || (GET_CODE (dest) == SUBREG | |
11862 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
11863 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
11864 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
11865 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
230d793d | 11866 | { |
6eb12cef | 11867 | move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); |
a7c99304 | 11868 | return; |
230d793d RS |
11869 | } |
11870 | ||
a7c99304 RK |
11871 | /* If this is some other SUBREG, we know it replaces the entire |
11872 | value, so use that as the destination. */ | |
11873 | if (GET_CODE (dest) == SUBREG) | |
11874 | dest = SUBREG_REG (dest); | |
11875 | ||
11876 | /* If this is a MEM, adjust deaths of anything used in the address. | |
11877 | For a REG (the only other possibility), the entire value is | |
11878 | being replaced so the old value is not used in this insn. */ | |
230d793d | 11879 | |
3c0cb5de | 11880 | if (MEM_P (dest)) |
6eb12cef RK |
11881 | move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, |
11882 | to_insn, pnotes); | |
230d793d RS |
11883 | return; |
11884 | } | |
11885 | ||
11886 | else if (GET_CODE (x) == CLOBBER) | |
11887 | return; | |
11888 | ||
11889 | len = GET_RTX_LENGTH (code); | |
11890 | fmt = GET_RTX_FORMAT (code); | |
11891 | ||
11892 | for (i = 0; i < len; i++) | |
11893 | { | |
11894 | if (fmt[i] == 'E') | |
11895 | { | |
b3694847 | 11896 | int j; |
230d793d | 11897 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
6eb12cef RK |
11898 | move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, |
11899 | to_insn, pnotes); | |
230d793d RS |
11900 | } |
11901 | else if (fmt[i] == 'e') | |
6eb12cef | 11902 | move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d RS |
11903 | } |
11904 | } | |
11905 | \f | |
a7c99304 RK |
11906 | /* Return 1 if X is the target of a bit-field assignment in BODY, the |
11907 | pattern of an insn. X must be a REG. */ | |
230d793d RS |
11908 | |
11909 | static int | |
79a490a9 | 11910 | reg_bitfield_target_p (rtx x, rtx body) |
230d793d RS |
11911 | { |
11912 | int i; | |
11913 | ||
11914 | if (GET_CODE (body) == SET) | |
a7c99304 RK |
11915 | { |
11916 | rtx dest = SET_DEST (body); | |
11917 | rtx target; | |
770ae6cc | 11918 | unsigned int regno, tregno, endregno, endtregno; |
a7c99304 RK |
11919 | |
11920 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
11921 | target = XEXP (dest, 0); | |
11922 | else if (GET_CODE (dest) == STRICT_LOW_PART) | |
11923 | target = SUBREG_REG (XEXP (dest, 0)); | |
11924 | else | |
11925 | return 0; | |
11926 | ||
11927 | if (GET_CODE (target) == SUBREG) | |
11928 | target = SUBREG_REG (target); | |
11929 | ||
f8cfc6aa | 11930 | if (!REG_P (target)) |
a7c99304 RK |
11931 | return 0; |
11932 | ||
11933 | tregno = REGNO (target), regno = REGNO (x); | |
11934 | if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
11935 | return target == x; | |
11936 | ||
66fd46b6 JH |
11937 | endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)]; |
11938 | endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; | |
a7c99304 RK |
11939 | |
11940 | return endregno > tregno && regno < endtregno; | |
11941 | } | |
230d793d RS |
11942 | |
11943 | else if (GET_CODE (body) == PARALLEL) | |
11944 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
a7c99304 | 11945 | if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) |
230d793d RS |
11946 | return 1; |
11947 | ||
11948 | return 0; | |
663522cb | 11949 | } |
230d793d RS |
11950 | \f |
11951 | /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
11952 | as appropriate. I3 and I2 are the insns resulting from the combination | |
11953 | insns including FROM (I2 may be zero). | |
11954 | ||
4bbae09f ILT |
11955 | ELIM_I2 and ELIM_I1 are either zero or registers that we know will |
11956 | not need REG_DEAD notes because they are being substituted for. This | |
11957 | saves searching in the most common cases. | |
11958 | ||
230d793d RS |
11959 | Each note in the list is either ignored or placed on some insns, depending |
11960 | on the type of note. */ | |
11961 | ||
11962 | static void | |
4bbae09f ILT |
11963 | distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2, |
11964 | rtx elim_i1) | |
230d793d RS |
11965 | { |
11966 | rtx note, next_note; | |
11967 | rtx tem; | |
11968 | ||
11969 | for (note = notes; note; note = next_note) | |
11970 | { | |
11971 | rtx place = 0, place2 = 0; | |
11972 | ||
11973 | /* If this NOTE references a pseudo register, ensure it references | |
11974 | the latest copy of that register. */ | |
f8cfc6aa | 11975 | if (XEXP (note, 0) && REG_P (XEXP (note, 0)) |
230d793d RS |
11976 | && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) |
11977 | XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; | |
11978 | ||
11979 | next_note = XEXP (note, 1); | |
11980 | switch (REG_NOTE_KIND (note)) | |
11981 | { | |
c9903b44 | 11982 | case REG_BR_PROB: |
4db384c9 | 11983 | case REG_BR_PRED: |
c9903b44 DE |
11984 | /* Doesn't matter much where we put this, as long as it's somewhere. |
11985 | It is preferable to keep these notes on branches, which is most | |
11986 | likely to be i3. */ | |
4a8d0c9c RH |
11987 | place = i3; |
11988 | break; | |
11989 | ||
6e885ee3 ZD |
11990 | case REG_VALUE_PROFILE: |
11991 | /* Just get rid of this note, as it is unused later anyway. */ | |
11992 | break; | |
11993 | ||
f7cfa78d | 11994 | case REG_NON_LOCAL_GOTO: |
4b4bf941 | 11995 | if (JUMP_P (i3)) |
f7cfa78d | 11996 | place = i3; |
f7cfa78d | 11997 | else |
341c100f NS |
11998 | { |
11999 | gcc_assert (i2 && JUMP_P (i2)); | |
12000 | place = i2; | |
12001 | } | |
f7cfa78d GS |
12002 | break; |
12003 | ||
4b7c585f | 12004 | case REG_EH_REGION: |
662795a8 | 12005 | /* These notes must remain with the call or trapping instruction. */ |
4b4bf941 | 12006 | if (CALL_P (i3)) |
662795a8 | 12007 | place = i3; |
4b4bf941 | 12008 | else if (i2 && CALL_P (i2)) |
662795a8 | 12009 | place = i2; |
341c100f | 12010 | else |
662795a8 | 12011 | { |
341c100f | 12012 | gcc_assert (flag_non_call_exceptions); |
662795a8 RH |
12013 | if (may_trap_p (i3)) |
12014 | place = i3; | |
12015 | else if (i2 && may_trap_p (i2)) | |
12016 | place = i2; | |
12017 | /* ??? Otherwise assume we've combined things such that we | |
12018 | can now prove that the instructions can't trap. Drop the | |
12019 | note in this case. */ | |
12020 | } | |
662795a8 RH |
12021 | break; |
12022 | ||
ca3920ad | 12023 | case REG_NORETURN: |
ab61c93f | 12024 | case REG_SETJMP: |
0e403ec3 AS |
12025 | /* These notes must remain with the call. It should not be |
12026 | possible for both I2 and I3 to be a call. */ | |
4b4bf941 | 12027 | if (CALL_P (i3)) |
4b7c585f | 12028 | place = i3; |
4b7c585f | 12029 | else |
341c100f NS |
12030 | { |
12031 | gcc_assert (i2 && CALL_P (i2)); | |
12032 | place = i2; | |
12033 | } | |
4b7c585f JL |
12034 | break; |
12035 | ||
230d793d | 12036 | case REG_UNUSED: |
07d0cbdd | 12037 | /* Any clobbers for i3 may still exist, and so we must process |
176c9e6b JW |
12038 | REG_UNUSED notes from that insn. |
12039 | ||
12040 | Any clobbers from i2 or i1 can only exist if they were added by | |
12041 | recog_for_combine. In that case, recog_for_combine created the | |
12042 | necessary REG_UNUSED notes. Trying to keep any original | |
12043 | REG_UNUSED notes from these insns can cause incorrect output | |
12044 | if it is for the same register as the original i3 dest. | |
12045 | In that case, we will notice that the register is set in i3, | |
12046 | and then add a REG_UNUSED note for the destination of i3, which | |
07d0cbdd JW |
12047 | is wrong. However, it is possible to have REG_UNUSED notes from |
12048 | i2 or i1 for register which were both used and clobbered, so | |
12049 | we keep notes from i2 or i1 if they will turn into REG_DEAD | |
12050 | notes. */ | |
176c9e6b | 12051 | |
230d793d RS |
12052 | /* If this register is set or clobbered in I3, put the note there |
12053 | unless there is one already. */ | |
07d0cbdd | 12054 | if (reg_set_p (XEXP (note, 0), PATTERN (i3))) |
230d793d | 12055 | { |
07d0cbdd JW |
12056 | if (from_insn != i3) |
12057 | break; | |
12058 | ||
f8cfc6aa | 12059 | if (! (REG_P (XEXP (note, 0)) |
230d793d RS |
12060 | ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) |
12061 | : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
12062 | place = i3; | |
12063 | } | |
12064 | /* Otherwise, if this register is used by I3, then this register | |
12065 | now dies here, so we must put a REG_DEAD note here unless there | |
12066 | is one already. */ | |
12067 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
f8cfc6aa | 12068 | && ! (REG_P (XEXP (note, 0)) |
770ae6cc RK |
12069 | ? find_regno_note (i3, REG_DEAD, |
12070 | REGNO (XEXP (note, 0))) | |
230d793d RS |
12071 | : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) |
12072 | { | |
12073 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
12074 | place = i3; | |
12075 | } | |
12076 | break; | |
12077 | ||
12078 | case REG_EQUAL: | |
12079 | case REG_EQUIV: | |
9ae8ffe7 | 12080 | case REG_NOALIAS: |
230d793d RS |
12081 | /* These notes say something about results of an insn. We can |
12082 | only support them if they used to be on I3 in which case they | |
a687e897 RK |
12083 | remain on I3. Otherwise they are ignored. |
12084 | ||
12085 | If the note refers to an expression that is not a constant, we | |
12086 | must also ignore the note since we cannot tell whether the | |
12087 | equivalence is still true. It might be possible to do | |
12088 | slightly better than this (we only have a problem if I2DEST | |
12089 | or I1DEST is present in the expression), but it doesn't | |
12090 | seem worth the trouble. */ | |
12091 | ||
12092 | if (from_insn == i3 | |
12093 | && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) | |
230d793d RS |
12094 | place = i3; |
12095 | break; | |
12096 | ||
12097 | case REG_INC: | |
12098 | case REG_NO_CONFLICT: | |
230d793d RS |
12099 | /* These notes say something about how a register is used. They must |
12100 | be present on any use of the register in I2 or I3. */ | |
12101 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
12102 | place = i3; | |
12103 | ||
12104 | if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
12105 | { | |
12106 | if (place) | |
12107 | place2 = i2; | |
12108 | else | |
12109 | place = i2; | |
12110 | } | |
12111 | break; | |
12112 | ||
e55b4486 RH |
12113 | case REG_LABEL: |
12114 | /* This can show up in several ways -- either directly in the | |
12115 | pattern, or hidden off in the constant pool with (or without?) | |
12116 | a REG_EQUAL note. */ | |
12117 | /* ??? Ignore the without-reg_equal-note problem for now. */ | |
12118 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) | |
12119 | || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) | |
12120 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF | |
12121 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) | |
12122 | place = i3; | |
12123 | ||
12124 | if (i2 | |
12125 | && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) | |
663522cb | 12126 | || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) |
e55b4486 RH |
12127 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF |
12128 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) | |
12129 | { | |
12130 | if (place) | |
12131 | place2 = i2; | |
12132 | else | |
12133 | place = i2; | |
12134 | } | |
2a3b43b6 | 12135 | |
b54567e2 RZ |
12136 | /* Don't attach REG_LABEL note to a JUMP_INSN. Add |
12137 | a JUMP_LABEL instead or decrement LABEL_NUSES. */ | |
12138 | if (place && JUMP_P (place)) | |
2a3b43b6 | 12139 | { |
341c100f NS |
12140 | rtx label = JUMP_LABEL (place); |
12141 | ||
12142 | if (!label) | |
b54567e2 | 12143 | JUMP_LABEL (place) = XEXP (note, 0); |
341c100f NS |
12144 | else |
12145 | { | |
12146 | gcc_assert (label == XEXP (note, 0)); | |
12147 | if (LABEL_P (label)) | |
12148 | LABEL_NUSES (label)--; | |
12149 | } | |
2a3b43b6 JJ |
12150 | place = 0; |
12151 | } | |
b54567e2 | 12152 | if (place2 && JUMP_P (place2)) |
2a3b43b6 | 12153 | { |
341c100f NS |
12154 | rtx label = JUMP_LABEL (place2); |
12155 | ||
12156 | if (!label) | |
b54567e2 | 12157 | JUMP_LABEL (place2) = XEXP (note, 0); |
341c100f NS |
12158 | else |
12159 | { | |
12160 | gcc_assert (label == XEXP (note, 0)); | |
12161 | if (LABEL_P (label)) | |
12162 | LABEL_NUSES (label)--; | |
12163 | } | |
2a3b43b6 JJ |
12164 | place2 = 0; |
12165 | } | |
e55b4486 RH |
12166 | break; |
12167 | ||
c1194d74 | 12168 | case REG_NONNEG: |
6001794d | 12169 | /* This note says something about the value of a register prior |
c1194d74 JW |
12170 | to the execution of an insn. It is too much trouble to see |
12171 | if the note is still correct in all situations. It is better | |
12172 | to simply delete it. */ | |
230d793d RS |
12173 | break; |
12174 | ||
12175 | case REG_RETVAL: | |
12176 | /* If the insn previously containing this note still exists, | |
12177 | put it back where it was. Otherwise move it to the previous | |
12178 | insn. Adjust the corresponding REG_LIBCALL note. */ | |
4b4bf941 | 12179 | if (!NOTE_P (from_insn)) |
230d793d RS |
12180 | place = from_insn; |
12181 | else | |
12182 | { | |
5f4f0e22 | 12183 | tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); |
230d793d RS |
12184 | place = prev_real_insn (from_insn); |
12185 | if (tem && place) | |
12186 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12187 | /* If we're deleting the last remaining instruction of a |
12188 | libcall sequence, don't add the notes. */ | |
12189 | else if (XEXP (note, 0) == from_insn) | |
12190 | tem = place = 0; | |
e51f9159 KK |
12191 | /* Don't add the dangling REG_RETVAL note. */ |
12192 | else if (! tem) | |
12193 | place = 0; | |
230d793d RS |
12194 | } |
12195 | break; | |
12196 | ||
12197 | case REG_LIBCALL: | |
12198 | /* This is handled similarly to REG_RETVAL. */ | |
4b4bf941 | 12199 | if (!NOTE_P (from_insn)) |
230d793d RS |
12200 | place = from_insn; |
12201 | else | |
12202 | { | |
5f4f0e22 | 12203 | tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); |
230d793d RS |
12204 | place = next_real_insn (from_insn); |
12205 | if (tem && place) | |
12206 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12207 | /* If we're deleting the last remaining instruction of a |
12208 | libcall sequence, don't add the notes. */ | |
12209 | else if (XEXP (note, 0) == from_insn) | |
12210 | tem = place = 0; | |
e51f9159 KK |
12211 | /* Don't add the dangling REG_LIBCALL note. */ |
12212 | else if (! tem) | |
12213 | place = 0; | |
230d793d RS |
12214 | } |
12215 | break; | |
12216 | ||
12217 | case REG_DEAD: | |
12218 | /* If the register is used as an input in I3, it dies there. | |
da7d8304 | 12219 | Similarly for I2, if it is nonzero and adjacent to I3. |
230d793d RS |
12220 | |
12221 | If the register is not used as an input in either I3 or I2 | |
12222 | and it is not one of the registers we were supposed to eliminate, | |
12223 | there are two possibilities. We might have a non-adjacent I2 | |
12224 | or we might have somehow eliminated an additional register | |
12225 | from a computation. For example, we might have had A & B where | |
12226 | we discover that B will always be zero. In this case we will | |
12227 | eliminate the reference to A. | |
12228 | ||
12229 | In both cases, we must search to see if we can find a previous | |
12230 | use of A and put the death note there. */ | |
12231 | ||
6e2d1486 | 12232 | if (from_insn |
4b4bf941 | 12233 | && CALL_P (from_insn) |
663522cb | 12234 | && find_reg_fusage (from_insn, USE, XEXP (note, 0))) |
6e2d1486 RK |
12235 | place = from_insn; |
12236 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
230d793d RS |
12237 | place = i3; |
12238 | else if (i2 != 0 && next_nonnote_insn (i2) == i3 | |
12239 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
12240 | place = i2; | |
12241 | ||
4bbae09f ILT |
12242 | if (place == 0 |
12243 | && (rtx_equal_p (XEXP (note, 0), elim_i2) | |
12244 | || rtx_equal_p (XEXP (note, 0), elim_i1))) | |
12245 | break; | |
12246 | ||
230d793d | 12247 | if (place == 0) |
38d8473f | 12248 | { |
f6366fc7 | 12249 | basic_block bb = this_basic_block; |
d3a923ee | 12250 | |
46de9b3c AM |
12251 | /* You might think you could search back from FROM_INSN |
12252 | rather than from I3, but combine tries to split invalid | |
12253 | combined instructions. This can result in the old I2 | |
12254 | or I1 moving later in the insn sequence. */ | |
d3a923ee | 12255 | for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem)) |
38d8473f | 12256 | { |
2c3c49de | 12257 | if (! INSN_P (tem)) |
d3a923ee | 12258 | { |
a813c111 | 12259 | if (tem == BB_HEAD (bb)) |
d3a923ee RH |
12260 | break; |
12261 | continue; | |
12262 | } | |
12263 | ||
38d8473f RK |
12264 | /* If the register is being set at TEM, see if that is all |
12265 | TEM is doing. If so, delete TEM. Otherwise, make this | |
de7c79cc EC |
12266 | into a REG_UNUSED note instead. Don't delete sets to |
12267 | global register vars. */ | |
2cd54c2a ZW |
12268 | if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER |
12269 | || !global_regs[REGNO (XEXP (note, 0))]) | |
12270 | && reg_set_p (XEXP (note, 0), PATTERN (tem))) | |
38d8473f RK |
12271 | { |
12272 | rtx set = single_set (tem); | |
e5e809f4 | 12273 | rtx inner_dest = 0; |
e51712db | 12274 | #ifdef HAVE_cc0 |
f5c97640 | 12275 | rtx cc0_setter = NULL_RTX; |
e51712db | 12276 | #endif |
e5e809f4 JL |
12277 | |
12278 | if (set != 0) | |
12279 | for (inner_dest = SET_DEST (set); | |
663522cb KH |
12280 | (GET_CODE (inner_dest) == STRICT_LOW_PART |
12281 | || GET_CODE (inner_dest) == SUBREG | |
12282 | || GET_CODE (inner_dest) == ZERO_EXTRACT); | |
e5e809f4 JL |
12283 | inner_dest = XEXP (inner_dest, 0)) |
12284 | ; | |
38d8473f RK |
12285 | |
12286 | /* Verify that it was the set, and not a clobber that | |
663522cb | 12287 | modified the register. |
f5c97640 RH |
12288 | |
12289 | CC0 targets must be careful to maintain setter/user | |
12290 | pairs. If we cannot delete the setter due to side | |
12291 | effects, mark the user with an UNUSED note instead | |
12292 | of deleting it. */ | |
38d8473f RK |
12293 | |
12294 | if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
f5c97640 RH |
12295 | && rtx_equal_p (XEXP (note, 0), inner_dest) |
12296 | #ifdef HAVE_cc0 | |
12297 | && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) | |
12298 | || ((cc0_setter = prev_cc0_setter (tem)) != NULL | |
12299 | && sets_cc0_p (PATTERN (cc0_setter)) > 0)) | |
12300 | #endif | |
12301 | ) | |
38d8473f RK |
12302 | { |
12303 | /* Move the notes and links of TEM elsewhere. | |
663522cb | 12304 | This might delete other dead insns recursively. |
38d8473f RK |
12305 | First set the pattern to something that won't use |
12306 | any register. */ | |
f9af39d0 | 12307 | rtx old_notes = REG_NOTES (tem); |
38d8473f RK |
12308 | |
12309 | PATTERN (tem) = pc_rtx; | |
f9af39d0 | 12310 | REG_NOTES (tem) = NULL; |
38d8473f | 12311 | |
4bbae09f ILT |
12312 | distribute_notes (old_notes, tem, tem, NULL_RTX, |
12313 | NULL_RTX, NULL_RTX); | |
38d8473f RK |
12314 | distribute_links (LOG_LINKS (tem)); |
12315 | ||
6773e15f | 12316 | SET_INSN_DELETED (tem); |
f5c97640 RH |
12317 | |
12318 | #ifdef HAVE_cc0 | |
12319 | /* Delete the setter too. */ | |
12320 | if (cc0_setter) | |
12321 | { | |
12322 | PATTERN (cc0_setter) = pc_rtx; | |
f9af39d0 RE |
12323 | old_notes = REG_NOTES (cc0_setter); |
12324 | REG_NOTES (cc0_setter) = NULL; | |
f5c97640 | 12325 | |
f9af39d0 | 12326 | distribute_notes (old_notes, cc0_setter, |
4bbae09f ILT |
12327 | cc0_setter, NULL_RTX, |
12328 | NULL_RTX, NULL_RTX); | |
f5c97640 RH |
12329 | distribute_links (LOG_LINKS (cc0_setter)); |
12330 | ||
6773e15f | 12331 | SET_INSN_DELETED (cc0_setter); |
f5c97640 RH |
12332 | } |
12333 | #endif | |
38d8473f RK |
12334 | } |
12335 | else | |
12336 | { | |
12337 | PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
663522cb | 12338 | |
38d8473f | 12339 | /* If there isn't already a REG_UNUSED note, put one |
b30e1617 DJ |
12340 | here. Do not place a REG_DEAD note, even if |
12341 | the register is also used here; that would not | |
12342 | match the algorithm used in lifetime analysis | |
12343 | and can cause the consistency check in the | |
12344 | scheduler to fail. */ | |
38d8473f RK |
12345 | if (! find_regno_note (tem, REG_UNUSED, |
12346 | REGNO (XEXP (note, 0)))) | |
12347 | place = tem; | |
12348 | break; | |
d3a923ee RH |
12349 | } |
12350 | } | |
12351 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) | |
4b4bf941 | 12352 | || (CALL_P (tem) |
d3a923ee RH |
12353 | && find_reg_fusage (tem, USE, XEXP (note, 0)))) |
12354 | { | |
46de9b3c AM |
12355 | /* This may not be the correct place for the death |
12356 | note if FROM_INSN is before TEM, and the reg is | |
12357 | set between FROM_INSN and TEM. The reg might | |
12358 | die two or more times. An existing death note | |
12359 | means we are looking at the wrong live range. */ | |
12360 | if (from_insn | |
12361 | && INSN_CUID (from_insn) < INSN_CUID (tem) | |
12362 | && find_regno_note (tem, REG_DEAD, | |
12363 | REGNO (XEXP (note, 0)))) | |
12364 | { | |
12365 | tem = from_insn; | |
12366 | if (tem == BB_HEAD (bb)) | |
12367 | break; | |
12368 | continue; | |
12369 | } | |
12370 | ||
d3a923ee RH |
12371 | place = tem; |
12372 | ||
12373 | /* If we are doing a 3->2 combination, and we have a | |
12374 | register which formerly died in i3 and was not used | |
12375 | by i2, which now no longer dies in i3 and is used in | |
12376 | i2 but does not die in i2, and place is between i2 | |
12377 | and i3, then we may need to move a link from place to | |
12378 | i2. */ | |
12379 | if (i2 && INSN_UID (place) <= max_uid_cuid | |
12380 | && INSN_CUID (place) > INSN_CUID (i2) | |
663522cb KH |
12381 | && from_insn |
12382 | && INSN_CUID (from_insn) > INSN_CUID (i2) | |
d3a923ee RH |
12383 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) |
12384 | { | |
12385 | rtx links = LOG_LINKS (place); | |
12386 | LOG_LINKS (place) = 0; | |
12387 | distribute_links (links); | |
12388 | } | |
12389 | break; | |
12390 | } | |
12391 | ||
a813c111 | 12392 | if (tem == BB_HEAD (bb)) |
230d793d | 12393 | break; |
38d8473f | 12394 | } |
663522cb | 12395 | |
d3a923ee RH |
12396 | /* We haven't found an insn for the death note and it |
12397 | is still a REG_DEAD note, but we have hit the beginning | |
12398 | of the block. If the existing life info says the reg | |
715e7fbc | 12399 | was dead, there's nothing left to do. Otherwise, we'll |
e7139885 RH |
12400 | need to do a global life update after combine. */ |
12401 | if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 | |
5e2d947c | 12402 | && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start, |
e7139885 | 12403 | REGNO (XEXP (note, 0)))) |
4977bab6 | 12404 | SET_BIT (refresh_blocks, this_basic_block->index); |
38d8473f | 12405 | } |
230d793d RS |
12406 | |
12407 | /* If the register is set or already dead at PLACE, we needn't do | |
e5e809f4 | 12408 | anything with this note if it is still a REG_DEAD note. |
e8679703 | 12409 | We check here if it is set at all, not if is it totally replaced, |
e5e809f4 JL |
12410 | which is what `dead_or_set_p' checks, so also check for it being |
12411 | set partially. */ | |
12412 | ||
230d793d RS |
12413 | if (place && REG_NOTE_KIND (note) == REG_DEAD) |
12414 | { | |
770ae6cc | 12415 | unsigned int regno = REGNO (XEXP (note, 0)); |
230d793d | 12416 | |
e7139885 RH |
12417 | /* Similarly, if the instruction on which we want to place |
12418 | the note is a noop, we'll need do a global live update | |
12419 | after we remove them in delete_noop_moves. */ | |
12420 | if (noop_move_p (place)) | |
4977bab6 | 12421 | SET_BIT (refresh_blocks, this_basic_block->index); |
e7139885 | 12422 | |
230d793d RS |
12423 | if (dead_or_set_p (place, XEXP (note, 0)) |
12424 | || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
12425 | { | |
12426 | /* Unless the register previously died in PLACE, clear | |
5eaad481 | 12427 | last_death. [I no longer understand why this is |
230d793d | 12428 | being done.] */ |
5eaad481 PB |
12429 | if (reg_stat[regno].last_death != place) |
12430 | reg_stat[regno].last_death = 0; | |
230d793d RS |
12431 | place = 0; |
12432 | } | |
12433 | else | |
5eaad481 | 12434 | reg_stat[regno].last_death = place; |
230d793d RS |
12435 | |
12436 | /* If this is a death note for a hard reg that is occupying | |
12437 | multiple registers, ensure that we are still using all | |
12438 | parts of the object. If we find a piece of the object | |
03afaf36 R |
12439 | that is unused, we must arrange for an appropriate REG_DEAD |
12440 | note to be added for it. However, we can't just emit a USE | |
12441 | and tag the note to it, since the register might actually | |
12442 | be dead; so we recourse, and the recursive call then finds | |
12443 | the previous insn that used this register. */ | |
230d793d RS |
12444 | |
12445 | if (place && regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 12446 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) |
230d793d | 12447 | { |
770ae6cc | 12448 | unsigned int endregno |
66fd46b6 JH |
12449 | = regno + hard_regno_nregs[regno] |
12450 | [GET_MODE (XEXP (note, 0))]; | |
230d793d | 12451 | int all_used = 1; |
770ae6cc | 12452 | unsigned int i; |
230d793d RS |
12453 | |
12454 | for (i = regno; i < endregno; i++) | |
03afaf36 R |
12455 | if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) |
12456 | && ! find_regno_fusage (place, USE, i)) | |
12457 | || dead_or_set_regno_p (place, i)) | |
12458 | all_used = 0; | |
a394b17b | 12459 | |
230d793d RS |
12460 | if (! all_used) |
12461 | { | |
12462 | /* Put only REG_DEAD notes for pieces that are | |
03afaf36 | 12463 | not already dead or set. */ |
230d793d | 12464 | |
03afaf36 | 12465 | for (i = regno; i < endregno; |
66fd46b6 | 12466 | i += hard_regno_nregs[i][reg_raw_mode[i]]) |
230d793d | 12467 | { |
e50126e8 | 12468 | rtx piece = regno_reg_rtx[i]; |
f6366fc7 | 12469 | basic_block bb = this_basic_block; |
230d793d | 12470 | |
03afaf36 | 12471 | if (! dead_or_set_p (place, piece) |
230d793d RS |
12472 | && ! reg_bitfield_target_p (piece, |
12473 | PATTERN (place))) | |
03afaf36 R |
12474 | { |
12475 | rtx new_note | |
12476 | = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); | |
12477 | ||
12478 | distribute_notes (new_note, place, place, | |
4bbae09f | 12479 | NULL_RTX, NULL_RTX, NULL_RTX); |
03afaf36 | 12480 | } |
c762163e R |
12481 | else if (! refers_to_regno_p (i, i + 1, |
12482 | PATTERN (place), 0) | |
12483 | && ! find_regno_fusage (place, USE, i)) | |
12484 | for (tem = PREV_INSN (place); ; | |
12485 | tem = PREV_INSN (tem)) | |
12486 | { | |
12487 | if (! INSN_P (tem)) | |
12488 | { | |
a813c111 | 12489 | if (tem == BB_HEAD (bb)) |
c762163e R |
12490 | { |
12491 | SET_BIT (refresh_blocks, | |
f6366fc7 | 12492 | this_basic_block->index); |
c762163e R |
12493 | break; |
12494 | } | |
12495 | continue; | |
12496 | } | |
12497 | if (dead_or_set_p (tem, piece) | |
12498 | || reg_bitfield_target_p (piece, | |
12499 | PATTERN (tem))) | |
12500 | { | |
12501 | REG_NOTES (tem) | |
71fd5a51 | 12502 | = gen_rtx_EXPR_LIST (REG_UNUSED, piece, |
c762163e R |
12503 | REG_NOTES (tem)); |
12504 | break; | |
12505 | } | |
12506 | } | |
12507 | ||
230d793d RS |
12508 | } |
12509 | ||
12510 | place = 0; | |
12511 | } | |
12512 | } | |
12513 | } | |
12514 | break; | |
12515 | ||
12516 | default: | |
12517 | /* Any other notes should not be present at this point in the | |
12518 | compilation. */ | |
341c100f | 12519 | gcc_unreachable (); |
230d793d RS |
12520 | } |
12521 | ||
12522 | if (place) | |
12523 | { | |
12524 | XEXP (note, 1) = REG_NOTES (place); | |
12525 | REG_NOTES (place) = note; | |
12526 | } | |
1a26b032 RK |
12527 | else if ((REG_NOTE_KIND (note) == REG_DEAD |
12528 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
f8cfc6aa | 12529 | && REG_P (XEXP (note, 0))) |
b1f21e0a | 12530 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
230d793d RS |
12531 | |
12532 | if (place2) | |
1a26b032 RK |
12533 | { |
12534 | if ((REG_NOTE_KIND (note) == REG_DEAD | |
12535 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
f8cfc6aa | 12536 | && REG_P (XEXP (note, 0))) |
b1f21e0a | 12537 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 12538 | |
38a448ca RH |
12539 | REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), |
12540 | REG_NOTE_KIND (note), | |
12541 | XEXP (note, 0), | |
12542 | REG_NOTES (place2)); | |
1a26b032 | 12543 | } |
230d793d RS |
12544 | } |
12545 | } | |
12546 | \f | |
12547 | /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
8c03ca00 EB |
12548 | I3, I2, and I1 to new locations. This is also called to add a link |
12549 | pointing at I3 when I3's destination is changed. */ | |
230d793d RS |
12550 | |
12551 | static void | |
79a490a9 | 12552 | distribute_links (rtx links) |
230d793d RS |
12553 | { |
12554 | rtx link, next_link; | |
12555 | ||
12556 | for (link = links; link; link = next_link) | |
12557 | { | |
12558 | rtx place = 0; | |
12559 | rtx insn; | |
12560 | rtx set, reg; | |
12561 | ||
12562 | next_link = XEXP (link, 1); | |
12563 | ||
12564 | /* If the insn that this link points to is a NOTE or isn't a single | |
12565 | set, ignore it. In the latter case, it isn't clear what we | |
663522cb | 12566 | can do other than ignore the link, since we can't tell which |
230d793d RS |
12567 | register it was for. Such links wouldn't be used by combine |
12568 | anyway. | |
12569 | ||
12570 | It is not possible for the destination of the target of the link to | |
12571 | have been changed by combine. The only potential of this is if we | |
12572 | replace I3, I2, and I1 by I3 and I2. But in that case the | |
12573 | destination of I2 also remains unchanged. */ | |
12574 | ||
4b4bf941 | 12575 | if (NOTE_P (XEXP (link, 0)) |
230d793d RS |
12576 | || (set = single_set (XEXP (link, 0))) == 0) |
12577 | continue; | |
12578 | ||
12579 | reg = SET_DEST (set); | |
12580 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
230d793d RS |
12581 | || GET_CODE (reg) == STRICT_LOW_PART) |
12582 | reg = XEXP (reg, 0); | |
12583 | ||
12584 | /* A LOG_LINK is defined as being placed on the first insn that uses | |
12585 | a register and points to the insn that sets the register. Start | |
12586 | searching at the next insn after the target of the link and stop | |
12587 | when we reach a set of the register or the end of the basic block. | |
12588 | ||
12589 | Note that this correctly handles the link that used to point from | |
5089e22e | 12590 | I3 to I2. Also note that not much searching is typically done here |
230d793d RS |
12591 | since most links don't point very far away. */ |
12592 | ||
12593 | for (insn = NEXT_INSN (XEXP (link, 0)); | |
f6366fc7 | 12594 | (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
a813c111 | 12595 | || BB_HEAD (this_basic_block->next_bb) != insn)); |
230d793d | 12596 | insn = NEXT_INSN (insn)) |
2c3c49de | 12597 | if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) |
230d793d RS |
12598 | { |
12599 | if (reg_referenced_p (reg, PATTERN (insn))) | |
12600 | place = insn; | |
12601 | break; | |
12602 | } | |
4b4bf941 | 12603 | else if (CALL_P (insn) |
663522cb | 12604 | && find_reg_fusage (insn, USE, reg)) |
6e2d1486 RK |
12605 | { |
12606 | place = insn; | |
12607 | break; | |
12608 | } | |
892c9f1f RK |
12609 | else if (INSN_P (insn) && reg_set_p (reg, insn)) |
12610 | break; | |
230d793d RS |
12611 | |
12612 | /* If we found a place to put the link, place it there unless there | |
12613 | is already a link to the same insn as LINK at that point. */ | |
12614 | ||
12615 | if (place) | |
12616 | { | |
12617 | rtx link2; | |
12618 | ||
12619 | for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) | |
12620 | if (XEXP (link2, 0) == XEXP (link, 0)) | |
12621 | break; | |
12622 | ||
12623 | if (link2 == 0) | |
12624 | { | |
12625 | XEXP (link, 1) = LOG_LINKS (place); | |
12626 | LOG_LINKS (place) = link; | |
abe6e52f RK |
12627 | |
12628 | /* Set added_links_insn to the earliest insn we added a | |
12629 | link to. */ | |
663522cb | 12630 | if (added_links_insn == 0 |
abe6e52f RK |
12631 | || INSN_CUID (added_links_insn) > INSN_CUID (place)) |
12632 | added_links_insn = place; | |
230d793d RS |
12633 | } |
12634 | } | |
12635 | } | |
12636 | } | |
12637 | \f | |
67962db5 RS |
12638 | /* Subroutine of unmentioned_reg_p and callback from for_each_rtx. |
12639 | Check whether the expression pointer to by LOC is a register or | |
12640 | memory, and if so return 1 if it isn't mentioned in the rtx EXPR. | |
12641 | Otherwise return zero. */ | |
12642 | ||
12643 | static int | |
12644 | unmentioned_reg_p_1 (rtx *loc, void *expr) | |
12645 | { | |
12646 | rtx x = *loc; | |
12647 | ||
12648 | if (x != NULL_RTX | |
3c0cb5de | 12649 | && (REG_P (x) || MEM_P (x)) |
67962db5 RS |
12650 | && ! reg_mentioned_p (x, (rtx) expr)) |
12651 | return 1; | |
12652 | return 0; | |
12653 | } | |
12654 | ||
12655 | /* Check for any register or memory mentioned in EQUIV that is not | |
12656 | mentioned in EXPR. This is used to restrict EQUIV to "specializations" | |
12657 | of EXPR where some registers may have been replaced by constants. */ | |
12658 | ||
12659 | static bool | |
12660 | unmentioned_reg_p (rtx equiv, rtx expr) | |
12661 | { | |
12662 | return for_each_rtx (&equiv, unmentioned_reg_p_1, expr); | |
12663 | } | |
12664 | \f | |
1427d6d2 RK |
12665 | /* Compute INSN_CUID for INSN, which is an insn made by combine. */ |
12666 | ||
12667 | static int | |
79a490a9 | 12668 | insn_cuid (rtx insn) |
1427d6d2 RK |
12669 | { |
12670 | while (insn != 0 && INSN_UID (insn) > max_uid_cuid | |
4b4bf941 | 12671 | && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE) |
1427d6d2 RK |
12672 | insn = NEXT_INSN (insn); |
12673 | ||
341c100f | 12674 | gcc_assert (INSN_UID (insn) <= max_uid_cuid); |
1427d6d2 RK |
12675 | |
12676 | return INSN_CUID (insn); | |
12677 | } | |
12678 | \f | |
230d793d | 12679 | void |
79a490a9 | 12680 | dump_combine_stats (FILE *file) |
230d793d | 12681 | { |
ab532386 | 12682 | fprintf |
230d793d RS |
12683 | (file, |
12684 | ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
12685 | combine_attempts, combine_merges, combine_extras, combine_successes); | |
12686 | } | |
12687 | ||
12688 | void | |
79a490a9 | 12689 | dump_combine_total_stats (FILE *file) |
230d793d | 12690 | { |
ab532386 | 12691 | fprintf |
230d793d RS |
12692 | (file, |
12693 | "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
12694 | total_attempts, total_merges, total_extras, total_successes); | |
12695 | } | |
ef330312 PB |
12696 | \f |
12697 | ||
12698 | static bool | |
12699 | gate_handle_combine (void) | |
12700 | { | |
12701 | return (optimize > 0); | |
12702 | } | |
12703 | ||
12704 | /* Try combining insns through substitution. */ | |
12705 | static void | |
12706 | rest_of_handle_combine (void) | |
12707 | { | |
12708 | int rebuild_jump_labels_after_combine | |
12709 | = combine_instructions (get_insns (), max_reg_num ()); | |
12710 | ||
12711 | /* Combining insns may have turned an indirect jump into a | |
12712 | direct jump. Rebuild the JUMP_LABEL fields of jumping | |
12713 | instructions. */ | |
12714 | if (rebuild_jump_labels_after_combine) | |
12715 | { | |
12716 | timevar_push (TV_JUMP); | |
12717 | rebuild_jump_labels (get_insns ()); | |
12718 | timevar_pop (TV_JUMP); | |
12719 | ||
12720 | delete_dead_jumptables (); | |
12721 | cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE); | |
12722 | } | |
12723 | } | |
12724 | ||
12725 | struct tree_opt_pass pass_combine = | |
12726 | { | |
12727 | "combine", /* name */ | |
12728 | gate_handle_combine, /* gate */ | |
12729 | rest_of_handle_combine, /* execute */ | |
12730 | NULL, /* sub */ | |
12731 | NULL, /* next */ | |
12732 | 0, /* static_pass_number */ | |
12733 | TV_COMBINE, /* tv_id */ | |
12734 | 0, /* properties_required */ | |
12735 | 0, /* properties_provided */ | |
12736 | 0, /* properties_destroyed */ | |
12737 | 0, /* todo_flags_start */ | |
12738 | TODO_dump_func | | |
12739 | TODO_ggc_collect, /* todo_flags_finish */ | |
12740 | 'c' /* letter */ | |
12741 | }; | |
12742 |