]> gcc.gnu.org Git - gcc.git/blame - gcc/combine.c
git://gcc.gnu.org / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
c-lex.c: Include <stdlib.h> and <string.h>/<strings.h>.
[gcc.git] / gcc / combine.c
CommitLineData
230d793d 1/* Optimize by combining instructions for GNU compiler.
c85f7c16 2 Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
230d793d
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
940d9d63
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
230d793d
RS		 20
21
22/* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
230d793d 77#include "config.h"
4f90e4a0 78#ifdef __STDC__
04fe4385 79#include <stdarg.h>
4f90e4a0 80#else
04fe4385 81#include <varargs.h>
4f90e4a0 82#endif
dfa3449b 83
9c3b4c8b
RS		 84/* Must precede rtl.h for FFS. */
85#include <stdio.h>
86
230d793d
RS		 87#include "rtl.h"
88#include "flags.h"
89#include "regs.h"
55310dad 90#include "hard-reg-set.h"
230d793d
RS		 91#include "expr.h"
92#include "basic-block.h"
93#include "insn-config.h"
94#include "insn-flags.h"
95#include "insn-codes.h"
96#include "insn-attr.h"
97#include "recog.h"
98#include "real.h"
99
100/* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102#define gen_lowpart dont_use_gen_lowpart_you_dummy
103
104/* Number of attempts to combine instructions in this function. */
105
106static int combine_attempts;
107
108/* Number of attempts that got as far as substitution in this function. */
109
110static int combine_merges;
111
112/* Number of instructions combined with added SETs in this function. */
113
114static int combine_extras;
115
116/* Number of instructions combined in this function. */
117
118static int combine_successes;
119
120/* Totals over entire compilation. */
121
122static int total_attempts, total_merges, total_extras, total_successes;
9210df58 123
ddd5a7c1 124/* Define a default value for REVERSIBLE_CC_MODE.
9210df58
RK		 125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127#ifndef REVERSIBLE_CC_MODE
128#define REVERSIBLE_CC_MODE(MODE) 0
129#endif
230d793d
RS		 130\f
131/* Vector mapping INSN_UIDs to cuids.
5089e22e 132 The cuids are like uids but increase monotonically always.
230d793d
RS		 133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
137
138static int *uid_cuid;
4255220d 139static int max_uid_cuid;
230d793d
RS		 140
141/* Get the cuid of an insn. */
142
1427d6d2
RK		 143#define INSN_CUID(INSN) \
144(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
230d793d
RS		 145
146/* Maximum register number, which is the size of the tables below. */
147
148static int combine_max_regno;
149
150/* Record last point of death of (hard or pseudo) register n. */
151
152static rtx *reg_last_death;
153
154/* Record last point of modification of (hard or pseudo) register n. */
155
156static rtx *reg_last_set;
157
158/* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
160
161static int mem_last_set;
162
163/* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
165
166static int last_call_cuid;
167
168/* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
173
174static rtx subst_insn;
175
0d9641d1
JW		 176/* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
178
179static rtx subst_prev_insn;
180
230d793d
RS		 181/* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
187
188static int subst_low_cuid;
189
6e25d159
RK		 190/* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
192
193static HARD_REG_SET newpat_used_regs;
194
abe6e52f
RK		 195/* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
197 that location. */
198
199static rtx added_links_insn;
200
0d4d42c3
RK		 201/* Basic block number of the block in which we are performing combines. */
202static int this_basic_block;
230d793d
RS		 203\f
204/* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
5089e22e 206 operation being processed is redundant given a prior operation performed
230d793d
RS		 207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
209
210 We use an approach similar to that used by cse, but change it in the
211 following ways:
212
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
216
217 Therefore, we maintain the following arrays:
218
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
226 register's value
227
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
231 table.
232
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
235
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
240
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
244
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
247
0f41302f 248/* Record last value assigned to (hard or pseudo) register n. */
230d793d
RS		 249
250static rtx *reg_last_set_value;
251
252/* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
254
568356af 255static int *reg_last_set_label;
230d793d
RS		 256
257/* Record the value of label_tick when an expression involving register n
0f41302f 258 is placed in reg_last_set_value. */
230d793d 259
568356af 260static int *reg_last_set_table_tick;
230d793d
RS		 261
262/* Set non-zero if references to register n in expressions should not be
263 used. */
264
265static char *reg_last_set_invalid;
266
0f41302f 267/* Incremented for each label. */
230d793d 268
568356af 269static int label_tick;
230d793d
RS		 270
271/* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
275
951553af 276 We record in the following array what we know about the nonzero
230d793d
RS		 277 bits of a register, specifically which bits are known to be zero.
278
279 If an entry is zero, it means that we don't know anything special. */
280
55310dad 281static unsigned HOST_WIDE_INT *reg_nonzero_bits;
230d793d 282
951553af 283/* Mode used to compute significance in reg_nonzero_bits. It is the largest
5f4f0e22 284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
230d793d 285
951553af 286static enum machine_mode nonzero_bits_mode;
230d793d 287
d0ab8cd3
RK		 288/* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
290
291static char *reg_sign_bit_copies;
292
951553af 293/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
1a26b032
RK		 294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
230d793d 297
951553af 298static int nonzero_sign_valid;
55310dad
RK		 299
300/* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
304
305static enum machine_mode *reg_last_set_mode;
306static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307static char *reg_last_set_sign_bit_copies;
230d793d
RS		 308\f
309/* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
312
313struct undo
314{
241cea85 315 struct undo *next;
230d793d 316 int is_int;
f5393ab9
RS		 317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
230d793d
RS		 319};
320
321/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
323
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
326
327 other_insn is nonzero if we have modified some other insn in the process
241cea85 328 of working on subst_insn. It must be verified too.
230d793d 329
241cea85
RK		 330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
333 structures. */
230d793d
RS		 334
335struct undobuf
336{
230d793d 337 char *storage;
241cea85
RK		 338 struct undo *undos;
339 struct undo *frees;
340 struct undo *previous_undos;
230d793d
RS		 341 rtx other_insn;
342};
343
344static struct undobuf undobuf;
345
cc876596 346/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
230d793d 347 insn. The substitution can be undone by undo_all. If INTO is already
cc876596
RK		 348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
350 the undo table. */
230d793d
RS		 351
352#define SUBST(INTO, NEWVAL) \
241cea85
RK		 353 do { rtx _new = (NEWVAL); \
354 struct undo *_buf; \
355 \
356 if (undobuf.frees) \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
358 else \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
360 \
361 _buf->is_int = 0; \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
364 INTO = _new; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
367 else \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 369 } while (0)
370
241cea85
RK		 371/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
373 not safe. */
230d793d
RS		 374
375#define SUBST_INT(INTO, NEWVAL) \
241cea85
RK		 376 do { struct undo *_buf; \
377 \
378 if (undobuf.frees) \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
380 else \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
382 \
383 _buf->is_int = 1; \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
386 INTO = NEWVAL; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
389 else \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 391 } while (0)
392
393/* Number of times the pseudo being substituted for
394 was found and replaced. */
395
396static int n_occurrences;
397
c5ad722c
RK		 398static void init_reg_last_arrays PROTO((void));
399static void setup_incoming_promotions PROTO((void));
fe2db4fb
RK		 400static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403static rtx try_combine PROTO((rtx, rtx, rtx));
404static void undo_all PROTO((void));
405static rtx *find_split_point PROTO((rtx *, rtx));
406static rtx subst PROTO((rtx, rtx, rtx, int, int));
8079805d
RK		 407static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408static rtx simplify_if_then_else PROTO((rtx));
409static rtx simplify_set PROTO((rtx));
410static rtx simplify_logical PROTO((rtx, int));
fe2db4fb
RK		 411static rtx expand_compound_operation PROTO((rtx));
412static rtx expand_field_assignment PROTO((rtx));
413static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
414 int, int, int));
71923da7 415static rtx extract_left_shift PROTO((rtx, int));
fe2db4fb
RK		 416static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
6139ff20 418static rtx force_to_mode PROTO((rtx, enum machine_mode,
e3d616e3 419 unsigned HOST_WIDE_INT, rtx, int));
abe6e52f 420static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
fe2db4fb 421static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
e11fa86f 422static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
fe2db4fb
RK		 423static rtx make_field_assignment PROTO((rtx));
424static rtx apply_distributive_law PROTO((rtx));
425static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
433 rtx, int));
a29ca9db 434static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
fe2db4fb 435static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
d18225c4 436static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
4f90e4a0 437 ...));
fe2db4fb
RK		 438static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
439 rtx, rtx));
0c1c8ea6
RK		 440static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
fe2db4fb
RK		 442static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443static int reversible_comparison_p PROTO((rtx));
444static void update_table_tick PROTO((rtx));
445static void record_value_for_reg PROTO((rtx, rtx, rtx));
446static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447static void record_dead_and_set_regs PROTO((rtx));
9a893315 448static int get_last_value_validate PROTO((rtx *, rtx, int, int));
fe2db4fb
RK		 449static rtx get_last_value PROTO((rtx));
450static int use_crosses_set_p PROTO((rtx, int));
451static void reg_dead_at_p_1 PROTO((rtx, rtx));
452static int reg_dead_at_p PROTO((rtx, rtx));
6eb12cef 453static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
fe2db4fb
RK		 454static int reg_bitfield_target_p PROTO((rtx, rtx));
455static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456static void distribute_links PROTO((rtx));
6e25d159 457static void mark_used_regs_combine PROTO((rtx));
1427d6d2 458static int insn_cuid PROTO((rtx));
230d793d
RS		 459\f
460/* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
462
463void
464combine_instructions (f, nregs)
465 rtx f;
466 int nregs;
467{
468 register rtx insn, next, prev;
469 register int i;
470 register rtx links, nextlinks;
471
472 combine_attempts = 0;
473 combine_merges = 0;
474 combine_extras = 0;
475 combine_successes = 0;
241cea85 476 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 477
478 combine_max_regno = nregs;
479
ef026f91
RS		 480 reg_nonzero_bits
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
483
4c9a05bc 484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
486
230d793d
RS		 487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
568356af
RK		 490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
5f4f0e22 492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
55310dad
RK		 493 reg_last_set_mode
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
499
ef026f91 500 init_reg_last_arrays ();
230d793d
RS		 501
502 init_recog_no_volatile ();
503
504 /* Compute maximum uid value so uid_cuid can be allocated. */
505
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
508 i = INSN_UID (insn);
509
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
4255220d 511 max_uid_cuid = i;
230d793d 512
951553af 513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
230d793d 514
951553af 515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
230d793d
RS		 516 when, for example, we have j <<= 1 in a loop. */
517
951553af 518 nonzero_sign_valid = 0;
230d793d
RS		 519
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
523
524 Scan all SETs and see if we can deduce anything about what
951553af 525 bits are known to be zero for some registers and how many copies
d79f08e0
RK		 526 of the sign bit are known to exist for those registers.
527
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
530
531 label_tick = 1;
230d793d 532
bcd49eb7
JW		 533 /* We need to initialize it here, because record_dead_and_set_regs may call
534 get_last_value. */
535 subst_prev_insn = NULL_RTX;
536
7988fd36
RK		 537 setup_incoming_promotions ();
538
230d793d
RS		 539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
540 {
4255220d 541 uid_cuid[INSN_UID (insn)] = ++i;
d79f08e0
RK		 542 subst_low_cuid = i;
543 subst_insn = insn;
544
230d793d 545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
d79f08e0
RK		 546 {
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
2dab894a
RK		 549
550#ifdef AUTO_INC_DEC
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
554#endif
d79f08e0
RK		 555 }
556
557 if (GET_CODE (insn) == CODE_LABEL)
558 label_tick++;
230d793d
RS		 559 }
560
951553af 561 nonzero_sign_valid = 1;
230d793d
RS		 562
563 /* Now scan all the insns in forward order. */
564
0d4d42c3 565 this_basic_block = -1;
230d793d
RS		 566 label_tick = 1;
567 last_call_cuid = 0;
568 mem_last_set = 0;
ef026f91 569 init_reg_last_arrays ();
7988fd36
RK		 570 setup_incoming_promotions ();
571
230d793d
RS		 572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
573 {
574 next = 0;
575
0d4d42c3 576 /* If INSN starts a new basic block, update our basic block number. */
f085c9cd 577 if (this_basic_block + 1 < n_basic_blocks
0d4d42c3
RK		 578 && basic_block_head[this_basic_block + 1] == insn)
579 this_basic_block++;
580
230d793d
RS		 581 if (GET_CODE (insn) == CODE_LABEL)
582 label_tick++;
583
0d4d42c3 584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
230d793d
RS		 585 {
586 /* Try this insn with each insn it links back to. */
587
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
5f4f0e22 589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
230d793d
RS		 590 goto retry;
591
592 /* Try each sequence of three linked insns ending with this one. */
593
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
599 goto retry;
600
601#ifdef HAVE_cc0
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
608
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
613 {
5f4f0e22 614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 615 goto retry;
616
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
621 goto retry;
622 }
623
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
631 {
5f4f0e22 632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 633 goto retry;
634
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
639 goto retry;
640 }
641
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
5089e22e 644 and its predecessor if it sets CC0. */
230d793d
RS		 645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
653 goto retry;
654#endif
655
656 /* Try combining an insn with two different insns whose results it
657 uses. */
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
663 goto retry;
664
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
667
668 retry:
669 ;
670 }
671 }
672
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
1a26b032 677
951553af 678 nonzero_sign_valid = 0;
230d793d 679}
ef026f91
RS		 680
681/* Wipe the reg_last_xxx arrays in preparation for another pass. */
682
683static void
684init_reg_last_arrays ()
685{
686 int nregs = combine_max_regno;
687
4c9a05bc
RK		 688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
ef026f91 693 bzero (reg_last_set_invalid, nregs * sizeof (char));
4c9a05bc
RK		 694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
697}
230d793d 698\f
7988fd36
RK		 699/* Set up any promoted values for incoming argument registers. */
700
ee791cc3 701static void
7988fd36
RK		 702setup_incoming_promotions ()
703{
704#ifdef PROMOTE_FUNCTION_ARGS
705 int regno;
706 rtx reg;
707 enum machine_mode mode;
708 int unsignedp;
709 rtx first = get_insns ();
710
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
38a448ca
RH		 714 {
715 record_value_for_reg
716 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
717 : SIGN_EXTEND),
718 GET_MODE (reg),
719 gen_rtx_CLOBBER (mode, const0_rtx)));
720 }
7988fd36
RK		 721#endif
722}
723\f
91102d5a
RK		 724/* Called via note_stores. If X is a pseudo that is narrower than
725 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
230d793d
RS		 726
727 If we are setting only a portion of X and we can't figure out what
728 portion, assume all bits will be used since we don't know what will
d0ab8cd3
RK		 729 be happening.
730
731 Similarly, set how many bits of X are known to be copies of the sign bit
732 at all locations in the function. This is the smallest number implied
733 by any set of X. */
230d793d
RS		 734
735static void
951553af 736set_nonzero_bits_and_sign_copies (x, set)
230d793d
RS		 737 rtx x;
738 rtx set;
739{
d0ab8cd3
RK		 740 int num;
741
230d793d
RS		 742 if (GET_CODE (x) == REG
743 && REGNO (x) >= FIRST_PSEUDO_REGISTER
e8095e80
RK		 744 /* If this register is undefined at the start of the file, we can't
745 say what its contents were. */
8e08106d 746 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
5f4f0e22 747 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
230d793d 748 {
2dab894a 749 if (set == 0 || GET_CODE (set) == CLOBBER)
e8095e80
RK		 750 {
751 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 752 reg_sign_bit_copies[REGNO (x)] = 1;
e8095e80
RK		 753 return;
754 }
230d793d
RS		 755
756 /* If this is a complex assignment, see if we can convert it into a
5089e22e 757 simple assignment. */
230d793d 758 set = expand_field_assignment (set);
d79f08e0
RK		 759
760 /* If this is a simple assignment, or we have a paradoxical SUBREG,
761 set what we know about X. */
762
763 if (SET_DEST (set) == x
764 || (GET_CODE (SET_DEST (set)) == SUBREG
705c7b3b
JW		 765 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
766 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
d79f08e0 767 && SUBREG_REG (SET_DEST (set)) == x))
d0ab8cd3 768 {
9afa3d54
RK		 769 rtx src = SET_SRC (set);
770
771#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
772 /* If X is narrower than a word and SRC is a non-negative
773 constant that would appear negative in the mode of X,
774 sign-extend it for use in reg_nonzero_bits because some
775 machines (maybe most) will actually do the sign-extension
776 and this is the conservative approach.
777
778 ??? For 2.5, try to tighten up the MD files in this regard
779 instead of this kludge. */
780
781 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
782 && GET_CODE (src) == CONST_INT
783 && INTVAL (src) > 0
784 && 0 != (INTVAL (src)
785 & ((HOST_WIDE_INT) 1
9e69be8c 786 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 787 src = GEN_INT (INTVAL (src)
788 | ((HOST_WIDE_INT) (-1)
789 << GET_MODE_BITSIZE (GET_MODE (x))));
790#endif
791
951553af 792 reg_nonzero_bits[REGNO (x)]
9afa3d54 793 |= nonzero_bits (src, nonzero_bits_mode);
d0ab8cd3
RK		 794 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
795 if (reg_sign_bit_copies[REGNO (x)] == 0
796 || reg_sign_bit_copies[REGNO (x)] > num)
797 reg_sign_bit_copies[REGNO (x)] = num;
798 }
230d793d 799 else
d0ab8cd3 800 {
951553af 801 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 802 reg_sign_bit_copies[REGNO (x)] = 1;
d0ab8cd3 803 }
230d793d
RS		 804 }
805}
806\f
807/* See if INSN can be combined into I3. PRED and SUCC are optionally
808 insns that were previously combined into I3 or that will be combined
809 into the merger of INSN and I3.
810
811 Return 0 if the combination is not allowed for any reason.
812
813 If the combination is allowed, *PDEST will be set to the single
814 destination of INSN and *PSRC to the single source, and this function
815 will return 1. */
816
817static int
818can_combine_p (insn, i3, pred, succ, pdest, psrc)
819 rtx insn;
820 rtx i3;
821 rtx pred, succ;
822 rtx *pdest, *psrc;
823{
824 int i;
825 rtx set = 0, src, dest;
826 rtx p, link;
827 int all_adjacent = (succ ? (next_active_insn (insn) == succ
828 && next_active_insn (succ) == i3)
829 : next_active_insn (insn) == i3);
830
831 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
832 or a PARALLEL consisting of such a SET and CLOBBERs.
833
834 If INSN has CLOBBER parallel parts, ignore them for our processing.
835 By definition, these happen during the execution of the insn. When it
836 is merged with another insn, all bets are off. If they are, in fact,
837 needed and aren't also supplied in I3, they may be added by
838 recog_for_combine. Otherwise, it won't match.
839
840 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
841 note.
842
843 Get the source and destination of INSN. If more than one, can't
844 combine. */
845
846 if (GET_CODE (PATTERN (insn)) == SET)
847 set = PATTERN (insn);
848 else if (GET_CODE (PATTERN (insn)) == PARALLEL
849 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
850 {
851 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
852 {
853 rtx elt = XVECEXP (PATTERN (insn), 0, i);
854
855 switch (GET_CODE (elt))
856 {
857 /* We can ignore CLOBBERs. */
858 case CLOBBER:
859 break;
860
861 case SET:
862 /* Ignore SETs whose result isn't used but not those that
863 have side-effects. */
864 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
865 && ! side_effects_p (elt))
866 break;
867
868 /* If we have already found a SET, this is a second one and
869 so we cannot combine with this insn. */
870 if (set)
871 return 0;
872
873 set = elt;
874 break;
875
876 default:
877 /* Anything else means we can't combine. */
878 return 0;
879 }
880 }
881
882 if (set == 0
883 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
884 so don't do anything with it. */
885 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
886 return 0;
887 }
888 else
889 return 0;
890
891 if (set == 0)
892 return 0;
893
894 set = expand_field_assignment (set);
895 src = SET_SRC (set), dest = SET_DEST (set);
896
897 /* Don't eliminate a store in the stack pointer. */
898 if (dest == stack_pointer_rtx
230d793d
RS		 899 /* If we couldn't eliminate a field assignment, we can't combine. */
900 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
901 /* Don't combine with an insn that sets a register to itself if it has
902 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
5f4f0e22 903 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
230d793d
RS		 904 /* Can't merge a function call. */
905 || GET_CODE (src) == CALL
cd5e8f1f 906 /* Don't eliminate a function call argument. */
4dca5ec5
RK		 907 || (GET_CODE (i3) == CALL_INSN
908 && (find_reg_fusage (i3, USE, dest)
909 || (GET_CODE (dest) == REG
910 && REGNO (dest) < FIRST_PSEUDO_REGISTER
911 && global_regs[REGNO (dest)])))
230d793d
RS		 912 /* Don't substitute into an incremented register. */
913 || FIND_REG_INC_NOTE (i3, dest)
914 || (succ && FIND_REG_INC_NOTE (succ, dest))
915 /* Don't combine the end of a libcall into anything. */
5f4f0e22 916 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
230d793d
RS		 917 /* Make sure that DEST is not used after SUCC but before I3. */
918 || (succ && ! all_adjacent
919 && reg_used_between_p (dest, succ, i3))
920 /* Make sure that the value that is to be substituted for the register
921 does not use any registers whose values alter in between. However,
922 If the insns are adjacent, a use can't cross a set even though we
923 think it might (this can happen for a sequence of insns each setting
924 the same destination; reg_last_set of that register might point to
d81481d3
RK		 925 a NOTE). If INSN has a REG_EQUIV note, the register is always
926 equivalent to the memory so the substitution is valid even if there
927 are intervening stores. Also, don't move a volatile asm or
928 UNSPEC_VOLATILE across any other insns. */
230d793d 929 || (! all_adjacent
d81481d3
RK		 930 && (((GET_CODE (src) != MEM
931 || ! find_reg_note (insn, REG_EQUIV, src))
932 && use_crosses_set_p (src, INSN_CUID (insn)))
a66a10c7
RS		 933 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
934 || GET_CODE (src) == UNSPEC_VOLATILE))
230d793d
RS		 935 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
936 better register allocation by not doing the combine. */
937 || find_reg_note (i3, REG_NO_CONFLICT, dest)
938 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
939 /* Don't combine across a CALL_INSN, because that would possibly
940 change whether the life span of some REGs crosses calls or not,
941 and it is a pain to update that information.
942 Exception: if source is a constant, moving it later can't hurt.
943 Accept that special case, because it helps -fforce-addr a lot. */
944 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
945 return 0;
946
947 /* DEST must either be a REG or CC0. */
948 if (GET_CODE (dest) == REG)
949 {
950 /* If register alignment is being enforced for multi-word items in all
951 cases except for parameters, it is possible to have a register copy
952 insn referencing a hard register that is not allowed to contain the
953 mode being copied and which would not be valid as an operand of most
954 insns. Eliminate this problem by not combining with such an insn.
955
956 Also, on some machines we don't want to extend the life of a hard
4d2c432d
RK		 957 register.
958
959 This is the same test done in can_combine except that we don't test
960 if SRC is a CALL operation to permit a hard register with
961 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
962 into account. */
230d793d
RS		 963
964 if (GET_CODE (src) == REG
965 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
966 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
c448a43e
RK		 967 /* Don't extend the life of a hard register unless it is
968 user variable (if we have few registers) or it can't
969 fit into the desired register (meaning something special
ecd40809
RK		 970 is going on).
971 Also avoid substituting a return register into I3, because
972 reload can't handle a conflict with constraints of other
973 inputs. */
230d793d 974 || (REGNO (src) < FIRST_PSEUDO_REGISTER
c448a43e 975 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
f95182a4
ILT		 976 || (SMALL_REGISTER_CLASSES
977 && ((! all_adjacent && ! REG_USERVAR_P (src))
978 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
e9a25f70 979 && ! REG_USERVAR_P (src))))))))
230d793d
RS		 980 return 0;
981 }
982 else if (GET_CODE (dest) != CC0)
983 return 0;
984
5f96750d
RS		 985 /* Don't substitute for a register intended as a clobberable operand.
986 Similarly, don't substitute an expression containing a register that
987 will be clobbered in I3. */
230d793d
RS		 988 if (GET_CODE (PATTERN (i3)) == PARALLEL)
989 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
990 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
5f96750d
RS		 991 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
992 src)
993 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
230d793d
RS		 994 return 0;
995
996 /* If INSN contains anything volatile, or is an `asm' (whether volatile
997 or not), reject, unless nothing volatile comes between it and I3,
998 with the exception of SUCC. */
999
1000 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1001 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1002 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1003 && p != succ && volatile_refs_p (PATTERN (p)))
1004 return 0;
1005
b79ee7eb
RH		 1006 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1007 to be an explicit register variable, and was chosen for a reason. */
1008
1009 if (GET_CODE (src) == ASM_OPERANDS
1010 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1011 return 0;
1012
4b2cb4a2
RS		 1013 /* If there are any volatile insns between INSN and I3, reject, because
1014 they might affect machine state. */
1015
1016 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1017 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1018 && p != succ && volatile_insn_p (PATTERN (p)))
1019 return 0;
1020
230d793d
RS		 1021 /* If INSN or I2 contains an autoincrement or autodecrement,
1022 make sure that register is not used between there and I3,
1023 and not already used in I3 either.
1024 Also insist that I3 not be a jump; if it were one
1025 and the incremented register were spilled, we would lose. */
1026
1027#ifdef AUTO_INC_DEC
1028 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1029 if (REG_NOTE_KIND (link) == REG_INC
1030 && (GET_CODE (i3) == JUMP_INSN
1031 || reg_used_between_p (XEXP (link, 0), insn, i3)
1032 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1033 return 0;
1034#endif
1035
1036#ifdef HAVE_cc0
1037 /* Don't combine an insn that follows a CC0-setting insn.
1038 An insn that uses CC0 must not be separated from the one that sets it.
1039 We do, however, allow I2 to follow a CC0-setting insn if that insn
1040 is passed as I1; in that case it will be deleted also.
1041 We also allow combining in this case if all the insns are adjacent
1042 because that would leave the two CC0 insns adjacent as well.
1043 It would be more logical to test whether CC0 occurs inside I1 or I2,
1044 but that would be much slower, and this ought to be equivalent. */
1045
1046 p = prev_nonnote_insn (insn);
1047 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1048 && ! all_adjacent)
1049 return 0;
1050#endif
1051
1052 /* If we get here, we have passed all the tests and the combination is
1053 to be allowed. */
1054
1055 *pdest = dest;
1056 *psrc = src;
1057
1058 return 1;
1059}
1060\f
956d6950
JL		 1061/* Check if PAT is an insn - or a part of it - used to set up an
1062 argument for a function in a hard register. */
1063
1064static int
1065sets_function_arg_p (pat)
1066 rtx pat;
1067{
1068 int i;
1069 rtx inner_dest;
1070
1071 switch (GET_CODE (pat))
1072 {
1073 case INSN:
1074 return sets_function_arg_p (PATTERN (pat));
1075
1076 case PARALLEL:
1077 for (i = XVECLEN (pat, 0); --i >= 0;)
1078 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1079 return 1;
1080
1081 break;
1082
1083 case SET:
1084 inner_dest = SET_DEST (pat);
1085 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1086 || GET_CODE (inner_dest) == SUBREG
1087 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1088 inner_dest = XEXP (inner_dest, 0);
1089
1090 return (GET_CODE (inner_dest) == REG
1091 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1092 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1d300e19
KG		 1093
1094 default:
1095 break;
956d6950
JL		 1096 }
1097
1098 return 0;
1099}
1100
230d793d
RS		 1101/* LOC is the location within I3 that contains its pattern or the component
1102 of a PARALLEL of the pattern. We validate that it is valid for combining.
1103
1104 One problem is if I3 modifies its output, as opposed to replacing it
1105 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1106 so would produce an insn that is not equivalent to the original insns.
1107
1108 Consider:
1109
1110 (set (reg:DI 101) (reg:DI 100))
1111 (set (subreg:SI (reg:DI 101) 0) <foo>)
1112
1113 This is NOT equivalent to:
1114
1115 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1116 (set (reg:DI 101) (reg:DI 100))])
1117
1118 Not only does this modify 100 (in which case it might still be valid
1119 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1120
1121 We can also run into a problem if I2 sets a register that I1
1122 uses and I1 gets directly substituted into I3 (not via I2). In that
1123 case, we would be getting the wrong value of I2DEST into I3, so we
1124 must reject the combination. This case occurs when I2 and I1 both
1125 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1126 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1127 of a SET must prevent combination from occurring.
1128
e9a25f70 1129 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
c448a43e
RK		 1130 if the destination of a SET is a hard register that isn't a user
1131 variable.
230d793d
RS		 1132
1133 Before doing the above check, we first try to expand a field assignment
1134 into a set of logical operations.
1135
1136 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1137 we place a register that is both set and used within I3. If more than one
1138 such register is detected, we fail.
1139
1140 Return 1 if the combination is valid, zero otherwise. */
1141
1142static int
1143combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1144 rtx i3;
1145 rtx *loc;
1146 rtx i2dest;
1147 rtx i1dest;
1148 int i1_not_in_src;
1149 rtx *pi3dest_killed;
1150{
1151 rtx x = *loc;
1152
1153 if (GET_CODE (x) == SET)
1154 {
1155 rtx set = expand_field_assignment (x);
1156 rtx dest = SET_DEST (set);
1157 rtx src = SET_SRC (set);
1158 rtx inner_dest = dest, inner_src = src;
1159
1160 SUBST (*loc, set);
1161
1162 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1163 || GET_CODE (inner_dest) == SUBREG
1164 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1165 inner_dest = XEXP (inner_dest, 0);
1166
1167 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1168 was added. */
1169#if 0
1170 while (GET_CODE (inner_src) == STRICT_LOW_PART
1171 || GET_CODE (inner_src) == SUBREG
1172 || GET_CODE (inner_src) == ZERO_EXTRACT)
1173 inner_src = XEXP (inner_src, 0);
1174
1175 /* If it is better that two different modes keep two different pseudos,
1176 avoid combining them. This avoids producing the following pattern
1177 on a 386:
1178 (set (subreg:SI (reg/v:QI 21) 0)
1179 (lshiftrt:SI (reg/v:SI 20)
1180 (const_int 24)))
1181 If that were made, reload could not handle the pair of
1182 reg 20/21, since it would try to get any GENERAL_REGS
1183 but some of them don't handle QImode. */
1184
1185 if (rtx_equal_p (inner_src, i2dest)
1186 && GET_CODE (inner_dest) == REG
1187 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1188 return 0;
1189#endif
1190
1191 /* Check for the case where I3 modifies its output, as
1192 discussed above. */
1193 if ((inner_dest != dest
1194 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1195 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
956d6950 1196
3f508eca
RK		 1197 /* This is the same test done in can_combine_p except that we
1198 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
956d6950
JL		 1199 CALL operation. Moreover, we can't test all_adjacent; we don't
1200 have to, since this instruction will stay in place, thus we are
1201 not considering increasing the lifetime of INNER_DEST.
1202
1203 Also, if this insn sets a function argument, combining it with
1204 something that might need a spill could clobber a previous
1205 function argument; the all_adjacent test in can_combine_p also
1206 checks this; here, we do a more specific test for this case. */
1207
230d793d 1208 || (GET_CODE (inner_dest) == REG
dfbe1b2f 1209 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
c448a43e
RK		 1210 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1211 GET_MODE (inner_dest))
e9a25f70
JL		 1212 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1213 && ! REG_USERVAR_P (inner_dest)
956d6950
JL		 1214 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1215 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1216 && i3 != 0
1217 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
230d793d
RS		 1218 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1219 return 0;
1220
1221 /* If DEST is used in I3, it is being killed in this insn,
36a9c2e9
JL		 1222 so record that for later.
1223 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1224 STACK_POINTER_REGNUM, since these are always considered to be
1225 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
230d793d 1226 if (pi3dest_killed && GET_CODE (dest) == REG
36a9c2e9
JL		 1227 && reg_referenced_p (dest, PATTERN (i3))
1228 && REGNO (dest) != FRAME_POINTER_REGNUM
6d7096b0
DE		 1229#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1230 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1231#endif
36a9c2e9
JL		 1232#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1233 && (REGNO (dest) != ARG_POINTER_REGNUM
1234 || ! fixed_regs [REGNO (dest)])
1235#endif
1236 && REGNO (dest) != STACK_POINTER_REGNUM)
230d793d
RS		 1237 {
1238 if (*pi3dest_killed)
1239 return 0;
1240
1241 *pi3dest_killed = dest;
1242 }
1243 }
1244
1245 else if (GET_CODE (x) == PARALLEL)
1246 {
1247 int i;
1248
1249 for (i = 0; i < XVECLEN (x, 0); i++)
1250 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1251 i1_not_in_src, pi3dest_killed))
1252 return 0;
1253 }
1254
1255 return 1;
1256}
1257\f
1258/* Try to combine the insns I1 and I2 into I3.
1259 Here I1 and I2 appear earlier than I3.
1260 I1 can be zero; then we combine just I2 into I3.
1261
1262 It we are combining three insns and the resulting insn is not recognized,
1263 try splitting it into two insns. If that happens, I2 and I3 are retained
1264 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1265 are pseudo-deleted.
1266
abe6e52f
RK		 1267 Return 0 if the combination does not work. Then nothing is changed.
1268 If we did the combination, return the insn at which combine should
1269 resume scanning. */
230d793d
RS		 1270
1271static rtx
1272try_combine (i3, i2, i1)
1273 register rtx i3, i2, i1;
1274{
1275 /* New patterns for I3 and I3, respectively. */
1276 rtx newpat, newi2pat = 0;
1277 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1278 int added_sets_1, added_sets_2;
1279 /* Total number of SETs to put into I3. */
1280 int total_sets;
1281 /* Nonzero is I2's body now appears in I3. */
1282 int i2_is_used;
1283 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1284 int insn_code_number, i2_code_number, other_code_number;
1285 /* Contains I3 if the destination of I3 is used in its source, which means
1286 that the old life of I3 is being killed. If that usage is placed into
1287 I2 and not in I3, a REG_DEAD note must be made. */
1288 rtx i3dest_killed = 0;
1289 /* SET_DEST and SET_SRC of I2 and I1. */
1290 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1291 /* PATTERN (I2), or a copy of it in certain cases. */
1292 rtx i2pat;
1293 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
c4e861e8 1294 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
230d793d
RS		 1295 int i1_feeds_i3 = 0;
1296 /* Notes that must be added to REG_NOTES in I3 and I2. */
1297 rtx new_i3_notes, new_i2_notes;
176c9e6b
JW		 1298 /* Notes that we substituted I3 into I2 instead of the normal case. */
1299 int i3_subst_into_i2 = 0;
df7d75de
RK		 1300 /* Notes that I1, I2 or I3 is a MULT operation. */
1301 int have_mult = 0;
a29ca9db
RK		 1302 /* Number of clobbers of SCRATCH we had to add. */
1303 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
230d793d
RS		 1304
1305 int maxreg;
1306 rtx temp;
1307 register rtx link;
1308 int i;
1309
1310 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1311 This can occur when flow deletes an insn that it has merged into an
1312 auto-increment address. We also can't do anything if I3 has a
1313 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1314 libcall. */
1315
1316 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1317 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1318 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
5f4f0e22 1319 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
230d793d
RS		 1320 return 0;
1321
1322 combine_attempts++;
1323
241cea85 1324 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 1325 undobuf.other_insn = 0;
1326
1327 /* Save the current high-water-mark so we can free storage if we didn't
1328 accept this combination. */
1329 undobuf.storage = (char *) oballoc (0);
1330
6e25d159
RK		 1331 /* Reset the hard register usage information. */
1332 CLEAR_HARD_REG_SET (newpat_used_regs);
1333
230d793d
RS		 1334 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1335 code below, set I1 to be the earlier of the two insns. */
1336 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1337 temp = i1, i1 = i2, i2 = temp;
1338
abe6e52f 1339 added_links_insn = 0;
137e889e 1340
230d793d
RS		 1341 /* First check for one important special-case that the code below will
1342 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1343 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1344 we may be able to replace that destination with the destination of I3.
1345 This occurs in the common code where we compute both a quotient and
1346 remainder into a structure, in which case we want to do the computation
1347 directly into the structure to avoid register-register copies.
1348
1349 We make very conservative checks below and only try to handle the
1350 most common cases of this. For example, we only handle the case
1351 where I2 and I3 are adjacent to avoid making difficult register
1352 usage tests. */
1353
1354 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1355 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1356 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
f95182a4 1357 && (! SMALL_REGISTER_CLASSES
e9a25f70
JL		 1358 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1359 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1360 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
230d793d
RS		 1361 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1362 && GET_CODE (PATTERN (i2)) == PARALLEL
1363 && ! side_effects_p (SET_DEST (PATTERN (i3)))
5089e22e
RS		 1364 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1365 below would need to check what is inside (and reg_overlap_mentioned_p
1366 doesn't support those codes anyway). Don't allow those destinations;
1367 the resulting insn isn't likely to be recognized anyway. */
1368 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1369 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
230d793d
RS		 1370 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1371 SET_DEST (PATTERN (i3)))
1372 && next_real_insn (i2) == i3)
5089e22e
RS		 1373 {
1374 rtx p2 = PATTERN (i2);
1375
1376 /* Make sure that the destination of I3,
1377 which we are going to substitute into one output of I2,
1378 is not used within another output of I2. We must avoid making this:
1379 (parallel [(set (mem (reg 69)) ...)
1380 (set (reg 69) ...)])
1381 which is not well-defined as to order of actions.
1382 (Besides, reload can't handle output reloads for this.)
1383
1384 The problem can also happen if the dest of I3 is a memory ref,
1385 if another dest in I2 is an indirect memory ref. */
1386 for (i = 0; i < XVECLEN (p2, 0); i++)
7ca919b7
RK		 1387 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1388 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
5089e22e
RS		 1389 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1390 SET_DEST (XVECEXP (p2, 0, i))))
1391 break;
230d793d 1392
5089e22e
RS		 1393 if (i == XVECLEN (p2, 0))
1394 for (i = 0; i < XVECLEN (p2, 0); i++)
1395 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1396 {
1397 combine_merges++;
230d793d 1398
5089e22e
RS		 1399 subst_insn = i3;
1400 subst_low_cuid = INSN_CUID (i2);
230d793d 1401
c4e861e8 1402 added_sets_2 = added_sets_1 = 0;
5089e22e 1403 i2dest = SET_SRC (PATTERN (i3));
230d793d 1404
5089e22e
RS		 1405 /* Replace the dest in I2 with our dest and make the resulting
1406 insn the new pattern for I3. Then skip to where we
1407 validate the pattern. Everything was set up above. */
1408 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1409 SET_DEST (PATTERN (i3)));
1410
1411 newpat = p2;
176c9e6b 1412 i3_subst_into_i2 = 1;
5089e22e
RS		 1413 goto validate_replacement;
1414 }
1415 }
230d793d
RS		 1416
1417#ifndef HAVE_cc0
1418 /* If we have no I1 and I2 looks like:
1419 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1420 (set Y OP)])
1421 make up a dummy I1 that is
1422 (set Y OP)
1423 and change I2 to be
1424 (set (reg:CC X) (compare:CC Y (const_int 0)))
1425
1426 (We can ignore any trailing CLOBBERs.)
1427
1428 This undoes a previous combination and allows us to match a branch-and-
1429 decrement insn. */
1430
1431 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1432 && XVECLEN (PATTERN (i2), 0) >= 2
1433 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1434 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1435 == MODE_CC)
1436 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1437 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1438 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1439 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1440 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1441 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1442 {
1443 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1444 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1445 break;
1446
1447 if (i == 1)
1448 {
1449 /* We make I1 with the same INSN_UID as I2. This gives it
1450 the same INSN_CUID for value tracking. Our fake I1 will
1451 never appear in the insn stream so giving it the same INSN_UID
1452 as I2 will not cause a problem. */
1453
0d9641d1 1454 subst_prev_insn = i1
38a448ca
RH		 1455 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1456 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1457 NULL_RTX);
230d793d
RS		 1458
1459 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1460 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1461 SET_DEST (PATTERN (i1)));
1462 }
1463 }
1464#endif
1465
1466 /* Verify that I2 and I1 are valid for combining. */
5f4f0e22
CH		 1467 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1468 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
230d793d
RS		 1469 {
1470 undo_all ();
1471 return 0;
1472 }
1473
1474 /* Record whether I2DEST is used in I2SRC and similarly for the other
1475 cases. Knowing this will help in register status updating below. */
1476 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1477 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1478 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1479
916f14f1 1480 /* See if I1 directly feeds into I3. It does if I1DEST is not used
230d793d
RS		 1481 in I2SRC. */
1482 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1483
1484 /* Ensure that I3's pattern can be the destination of combines. */
1485 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1486 i1 && i2dest_in_i1src && i1_feeds_i3,
1487 &i3dest_killed))
1488 {
1489 undo_all ();
1490 return 0;
1491 }
1492
df7d75de
RK		 1493 /* See if any of the insns is a MULT operation. Unless one is, we will
1494 reject a combination that is, since it must be slower. Be conservative
1495 here. */
1496 if (GET_CODE (i2src) == MULT
1497 || (i1 != 0 && GET_CODE (i1src) == MULT)
1498 || (GET_CODE (PATTERN (i3)) == SET
1499 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1500 have_mult = 1;
1501
230d793d
RS		 1502 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1503 We used to do this EXCEPT in one case: I3 has a post-inc in an
1504 output operand. However, that exception can give rise to insns like
1505 mov r3,(r3)+
1506 which is a famous insn on the PDP-11 where the value of r3 used as the
5089e22e 1507 source was model-dependent. Avoid this sort of thing. */
230d793d
RS		 1508
1509#if 0
1510 if (!(GET_CODE (PATTERN (i3)) == SET
1511 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1512 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1513 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1514 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1515 /* It's not the exception. */
1516#endif
1517#ifdef AUTO_INC_DEC
1518 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1519 if (REG_NOTE_KIND (link) == REG_INC
1520 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1521 || (i1 != 0
1522 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1523 {
1524 undo_all ();
1525 return 0;
1526 }
1527#endif
1528
1529 /* See if the SETs in I1 or I2 need to be kept around in the merged
1530 instruction: whenever the value set there is still needed past I3.
1531 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1532
1533 For the SET in I1, we have two cases: If I1 and I2 independently
1534 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1535 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1536 in I1 needs to be kept around unless I1DEST dies or is set in either
1537 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1538 I1DEST. If so, we know I1 feeds into I2. */
1539
1540 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1541
1542 added_sets_1
1543 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1544 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1545
1546 /* If the set in I2 needs to be kept around, we must make a copy of
1547 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
5089e22e 1548 PATTERN (I2), we are only substituting for the original I1DEST, not into
230d793d
RS		 1549 an already-substituted copy. This also prevents making self-referential
1550 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1551 I2DEST. */
1552
1553 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
38a448ca 1554 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
230d793d
RS		 1555 : PATTERN (i2));
1556
1557 if (added_sets_2)
1558 i2pat = copy_rtx (i2pat);
1559
1560 combine_merges++;
1561
1562 /* Substitute in the latest insn for the regs set by the earlier ones. */
1563
1564 maxreg = max_reg_num ();
1565
1566 subst_insn = i3;
230d793d
RS		 1567
1568 /* It is possible that the source of I2 or I1 may be performing an
1569 unneeded operation, such as a ZERO_EXTEND of something that is known
1570 to have the high part zero. Handle that case by letting subst look at
1571 the innermost one of them.
1572
1573 Another way to do this would be to have a function that tries to
1574 simplify a single insn instead of merging two or more insns. We don't
1575 do this because of the potential of infinite loops and because
1576 of the potential extra memory required. However, doing it the way
1577 we are is a bit of a kludge and doesn't catch all cases.
1578
1579 But only do this if -fexpensive-optimizations since it slows things down
1580 and doesn't usually win. */
1581
1582 if (flag_expensive_optimizations)
1583 {
1584 /* Pass pc_rtx so no substitutions are done, just simplifications.
1585 The cases that we are interested in here do not involve the few
1586 cases were is_replaced is checked. */
1587 if (i1)
d0ab8cd3
RK		 1588 {
1589 subst_low_cuid = INSN_CUID (i1);
1590 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1591 }
230d793d 1592 else
d0ab8cd3
RK		 1593 {
1594 subst_low_cuid = INSN_CUID (i2);
1595 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1596 }
230d793d 1597
241cea85 1598 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1599 }
1600
1601#ifndef HAVE_cc0
1602 /* Many machines that don't use CC0 have insns that can both perform an
1603 arithmetic operation and set the condition code. These operations will
1604 be represented as a PARALLEL with the first element of the vector
1605 being a COMPARE of an arithmetic operation with the constant zero.
1606 The second element of the vector will set some pseudo to the result
1607 of the same arithmetic operation. If we simplify the COMPARE, we won't
1608 match such a pattern and so will generate an extra insn. Here we test
1609 for this case, where both the comparison and the operation result are
1610 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1611 I2SRC. Later we will make the PARALLEL that contains I2. */
1612
1613 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1614 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1615 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1616 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1617 {
1618 rtx *cc_use;
1619 enum machine_mode compare_mode;
1620
1621 newpat = PATTERN (i3);
1622 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1623
1624 i2_is_used = 1;
1625
1626#ifdef EXTRA_CC_MODES
1627 /* See if a COMPARE with the operand we substituted in should be done
1628 with the mode that is currently being used. If not, do the same
1629 processing we do in `subst' for a SET; namely, if the destination
1630 is used only once, try to replace it with a register of the proper
1631 mode and also replace the COMPARE. */
1632 if (undobuf.other_insn == 0
1633 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1634 &undobuf.other_insn))
77fa0940
RK		 1635 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1636 i2src, const0_rtx))
230d793d
RS		 1637 != GET_MODE (SET_DEST (newpat))))
1638 {
1639 int regno = REGNO (SET_DEST (newpat));
38a448ca 1640 rtx new_dest = gen_rtx_REG (compare_mode, regno);
230d793d
RS		 1641
1642 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 1643 || (REG_N_SETS (regno) == 1 && ! added_sets_2
230d793d
RS		 1644 && ! REG_USERVAR_P (SET_DEST (newpat))))
1645 {
1646 if (regno >= FIRST_PSEUDO_REGISTER)
1647 SUBST (regno_reg_rtx[regno], new_dest);
1648
1649 SUBST (SET_DEST (newpat), new_dest);
1650 SUBST (XEXP (*cc_use, 0), new_dest);
1651 SUBST (SET_SRC (newpat),
1652 gen_rtx_combine (COMPARE, compare_mode,
1653 i2src, const0_rtx));
1654 }
1655 else
1656 undobuf.other_insn = 0;
1657 }
1658#endif
1659 }
1660 else
1661#endif
1662 {
1663 n_occurrences = 0; /* `subst' counts here */
1664
1665 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1666 need to make a unique copy of I2SRC each time we substitute it
1667 to avoid self-referential rtl. */
1668
d0ab8cd3 1669 subst_low_cuid = INSN_CUID (i2);
230d793d
RS		 1670 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1671 ! i1_feeds_i3 && i1dest_in_i1src);
241cea85 1672 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1673
1674 /* Record whether i2's body now appears within i3's body. */
1675 i2_is_used = n_occurrences;
1676 }
1677
1678 /* If we already got a failure, don't try to do more. Otherwise,
1679 try to substitute in I1 if we have it. */
1680
1681 if (i1 && GET_CODE (newpat) != CLOBBER)
1682 {
1683 /* Before we can do this substitution, we must redo the test done
1684 above (see detailed comments there) that ensures that I1DEST
0f41302f 1685 isn't mentioned in any SETs in NEWPAT that are field assignments. */
230d793d 1686
5f4f0e22
CH		 1687 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1688 0, NULL_PTR))
230d793d
RS		 1689 {
1690 undo_all ();
1691 return 0;
1692 }
1693
1694 n_occurrences = 0;
d0ab8cd3 1695 subst_low_cuid = INSN_CUID (i1);
230d793d 1696 newpat = subst (newpat, i1dest, i1src, 0, 0);
241cea85 1697 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1698 }
1699
916f14f1
RK		 1700 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1701 to count all the ways that I2SRC and I1SRC can be used. */
5f4f0e22 1702 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
916f14f1 1703 && i2_is_used + added_sets_2 > 1)
5f4f0e22 1704 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
916f14f1
RK		 1705 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1706 > 1))
230d793d
RS		 1707 /* Fail if we tried to make a new register (we used to abort, but there's
1708 really no reason to). */
1709 || max_reg_num () != maxreg
1710 /* Fail if we couldn't do something and have a CLOBBER. */
df7d75de
RK		 1711 || GET_CODE (newpat) == CLOBBER
1712 /* Fail if this new pattern is a MULT and we didn't have one before
1713 at the outer level. */
1714 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1715 && ! have_mult))
230d793d
RS		 1716 {
1717 undo_all ();
1718 return 0;
1719 }
1720
1721 /* If the actions of the earlier insns must be kept
1722 in addition to substituting them into the latest one,
1723 we must make a new PARALLEL for the latest insn
1724 to hold additional the SETs. */
1725
1726 if (added_sets_1 || added_sets_2)
1727 {
1728 combine_extras++;
1729
1730 if (GET_CODE (newpat) == PARALLEL)
1731 {
1732 rtvec old = XVEC (newpat, 0);
1733 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
38a448ca 1734 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
59888de2 1735 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
230d793d
RS		 1736 sizeof (old->elem[0]) * old->num_elem);
1737 }
1738 else
1739 {
1740 rtx old = newpat;
1741 total_sets = 1 + added_sets_1 + added_sets_2;
38a448ca 1742 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
230d793d
RS		 1743 XVECEXP (newpat, 0, 0) = old;
1744 }
1745
1746 if (added_sets_1)
1747 XVECEXP (newpat, 0, --total_sets)
1748 = (GET_CODE (PATTERN (i1)) == PARALLEL
38a448ca 1749 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
230d793d
RS		 1750
1751 if (added_sets_2)
1752 {
1753 /* If there is no I1, use I2's body as is. We used to also not do
1754 the subst call below if I2 was substituted into I3,
1755 but that could lose a simplification. */
1756 if (i1 == 0)
1757 XVECEXP (newpat, 0, --total_sets) = i2pat;
1758 else
1759 /* See comment where i2pat is assigned. */
1760 XVECEXP (newpat, 0, --total_sets)
1761 = subst (i2pat, i1dest, i1src, 0, 0);
1762 }
1763 }
1764
1765 /* We come here when we are replacing a destination in I2 with the
1766 destination of I3. */
1767 validate_replacement:
1768
6e25d159
RK		 1769 /* Note which hard regs this insn has as inputs. */
1770 mark_used_regs_combine (newpat);
1771
230d793d 1772 /* Is the result of combination a valid instruction? */
a29ca9db
RK		 1773 insn_code_number
1774 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1775
1776 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1777 the second SET's destination is a register that is unused. In that case,
1778 we just need the first SET. This can occur when simplifying a divmod
1779 insn. We *must* test for this case here because the code below that
1780 splits two independent SETs doesn't handle this case correctly when it
1781 updates the register status. Also check the case where the first
1782 SET's destination is unused. That would not cause incorrect code, but
1783 does cause an unneeded insn to remain. */
1784
1785 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1786 && XVECLEN (newpat, 0) == 2
1787 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1788 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1789 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1790 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1791 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1792 && asm_noperands (newpat) < 0)
1793 {
1794 newpat = XVECEXP (newpat, 0, 0);
a29ca9db
RK		 1795 insn_code_number
1796 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1797 }
1798
1799 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1800 && XVECLEN (newpat, 0) == 2
1801 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1802 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1803 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1804 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1805 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1806 && asm_noperands (newpat) < 0)
1807 {
1808 newpat = XVECEXP (newpat, 0, 1);
a29ca9db
RK		 1809 insn_code_number
1810 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1811 }
1812
1813 /* If we were combining three insns and the result is a simple SET
1814 with no ASM_OPERANDS that wasn't recognized, try to split it into two
916f14f1
RK		 1815 insns. There are two ways to do this. It can be split using a
1816 machine-specific method (like when you have an addition of a large
1817 constant) or by combine in the function find_split_point. */
1818
230d793d
RS		 1819 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1820 && asm_noperands (newpat) < 0)
1821 {
916f14f1 1822 rtx m_split, *split;
42495ca0 1823 rtx ni2dest = i2dest;
916f14f1
RK		 1824
1825 /* See if the MD file can split NEWPAT. If it can't, see if letting it
42495ca0
RK		 1826 use I2DEST as a scratch register will help. In the latter case,
1827 convert I2DEST to the mode of the source of NEWPAT if we can. */
916f14f1
RK		 1828
1829 m_split = split_insns (newpat, i3);
a70c61d9
JW		 1830
1831 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1832 inputs of NEWPAT. */
1833
1834 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1835 possible to try that as a scratch reg. This would require adding
1836 more code to make it work though. */
1837
1838 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
42495ca0
RK		 1839 {
1840 /* If I2DEST is a hard register or the only use of a pseudo,
1841 we can change its mode. */
1842 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
02f4ada4 1843 && GET_MODE (SET_DEST (newpat)) != VOIDmode
60654f77 1844 && GET_CODE (i2dest) == REG
42495ca0 1845 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1846 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
42495ca0 1847 && ! REG_USERVAR_P (i2dest))))
38a448ca 1848 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
42495ca0
RK		 1849 REGNO (i2dest));
1850
38a448ca
RH		 1851 m_split = split_insns
1852 (gen_rtx_PARALLEL (VOIDmode,
1853 gen_rtvec (2, newpat,
1854 gen_rtx_CLOBBER (VOIDmode,
1855 ni2dest))),
1856 i3);
42495ca0 1857 }
916f14f1
RK		 1858
1859 if (m_split && GET_CODE (m_split) == SEQUENCE
3f508eca
RK		 1860 && XVECLEN (m_split, 0) == 2
1861 && (next_real_insn (i2) == i3
1862 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1863 INSN_CUID (i2))))
916f14f1 1864 {
1a26b032 1865 rtx i2set, i3set;
d0ab8cd3 1866 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
916f14f1 1867 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
916f14f1 1868
e4ba89be
RK		 1869 i3set = single_set (XVECEXP (m_split, 0, 1));
1870 i2set = single_set (XVECEXP (m_split, 0, 0));
1a26b032 1871
42495ca0
RK		 1872 /* In case we changed the mode of I2DEST, replace it in the
1873 pseudo-register table here. We can't do it above in case this
1874 code doesn't get executed and we do a split the other way. */
1875
1876 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1877 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1878
a29ca9db
RK		 1879 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1880 &i2_scratches);
1a26b032
RK		 1881
1882 /* If I2 or I3 has multiple SETs, we won't know how to track
9cc96794
RK		 1883 register status, so don't use these insns. If I2's destination
1884 is used between I2 and I3, we also can't use these insns. */
1a26b032 1885
9cc96794
RK		 1886 if (i2_code_number >= 0 && i2set && i3set
1887 && (next_real_insn (i2) == i3
1888 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
a29ca9db
RK		 1889 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1890 &i3_scratches);
d0ab8cd3
RK		 1891 if (insn_code_number >= 0)
1892 newpat = newi3pat;
1893
c767f54b 1894 /* It is possible that both insns now set the destination of I3.
22609cbf 1895 If so, we must show an extra use of it. */
c767f54b 1896
393de53f
RK		 1897 if (insn_code_number >= 0)
1898 {
1899 rtx new_i3_dest = SET_DEST (i3set);
1900 rtx new_i2_dest = SET_DEST (i2set);
1901
1902 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1903 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1904 || GET_CODE (new_i3_dest) == SUBREG)
1905 new_i3_dest = XEXP (new_i3_dest, 0);
1906
d4096689
RK		 1907 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1908 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1909 || GET_CODE (new_i2_dest) == SUBREG)
1910 new_i2_dest = XEXP (new_i2_dest, 0);
1911
393de53f
RK		 1912 if (GET_CODE (new_i3_dest) == REG
1913 && GET_CODE (new_i2_dest) == REG
1914 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
b1f21e0a 1915 REG_N_SETS (REGNO (new_i2_dest))++;
393de53f 1916 }
916f14f1 1917 }
230d793d
RS		 1918
1919 /* If we can split it and use I2DEST, go ahead and see if that
1920 helps things be recognized. Verify that none of the registers
1921 are set between I2 and I3. */
d0ab8cd3 1922 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
230d793d
RS		 1923#ifdef HAVE_cc0
1924 && GET_CODE (i2dest) == REG
1925#endif
1926 /* We need I2DEST in the proper mode. If it is a hard register
1927 or the only use of a pseudo, we can change its mode. */
1928 && (GET_MODE (*split) == GET_MODE (i2dest)
1929 || GET_MODE (*split) == VOIDmode
1930 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1931 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
230d793d
RS		 1932 && ! REG_USERVAR_P (i2dest)))
1933 && (next_real_insn (i2) == i3
1934 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1935 /* We can't overwrite I2DEST if its value is still used by
1936 NEWPAT. */
1937 && ! reg_referenced_p (i2dest, newpat))
1938 {
1939 rtx newdest = i2dest;
df7d75de
RK		 1940 enum rtx_code split_code = GET_CODE (*split);
1941 enum machine_mode split_mode = GET_MODE (*split);
230d793d
RS		 1942
1943 /* Get NEWDEST as a register in the proper mode. We have already
1944 validated that we can do this. */
df7d75de 1945 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
230d793d 1946 {
38a448ca 1947 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
230d793d
RS		 1948
1949 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1950 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1951 }
1952
1953 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1954 an ASHIFT. This can occur if it was inside a PLUS and hence
1955 appeared to be a memory address. This is a kludge. */
df7d75de 1956 if (split_code == MULT
230d793d
RS		 1957 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1958 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1dc8a823
JW		 1959 {
1960 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1961 XEXP (*split, 0), GEN_INT (i)));
1962 /* Update split_code because we may not have a multiply
1963 anymore. */
1964 split_code = GET_CODE (*split);
1965 }
230d793d
RS		 1966
1967#ifdef INSN_SCHEDULING
1968 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1969 be written as a ZERO_EXTEND. */
df7d75de
RK		 1970 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1971 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
230d793d
RS		 1972 XEXP (*split, 0)));
1973#endif
1974
1975 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1976 SUBST (*split, newdest);
a29ca9db
RK		 1977 i2_code_number
1978 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
df7d75de
RK		 1979
1980 /* If the split point was a MULT and we didn't have one before,
1981 don't use one now. */
1982 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
a29ca9db
RK		 1983 insn_code_number
1984 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 1985 }
1986 }
1987
1988 /* Check for a case where we loaded from memory in a narrow mode and
1989 then sign extended it, but we need both registers. In that case,
1990 we have a PARALLEL with both loads from the same memory location.
1991 We can split this into a load from memory followed by a register-register
1992 copy. This saves at least one insn, more if register allocation can
f0343c74
RK		 1993 eliminate the copy.
1994
1995 We cannot do this if the destination of the second assignment is
1996 a register that we have already assumed is zero-extended. Similarly
1997 for a SUBREG of such a register. */
230d793d
RS		 1998
1999 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2000 && GET_CODE (newpat) == PARALLEL
2001 && XVECLEN (newpat, 0) == 2
2002 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2003 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2004 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2005 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2006 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2007 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2008 INSN_CUID (i2))
2009 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2010 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
f0343c74
RK		 2011 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2012 (GET_CODE (temp) == REG
2013 && reg_nonzero_bits[REGNO (temp)] != 0
2014 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2015 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2016 && (reg_nonzero_bits[REGNO (temp)]
2017 != GET_MODE_MASK (word_mode))))
2018 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2019 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2020 (GET_CODE (temp) == REG
2021 && reg_nonzero_bits[REGNO (temp)] != 0
2022 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2023 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2024 && (reg_nonzero_bits[REGNO (temp)]
2025 != GET_MODE_MASK (word_mode)))))
230d793d
RS		 2026 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2027 SET_SRC (XVECEXP (newpat, 0, 1)))
2028 && ! find_reg_note (i3, REG_UNUSED,
2029 SET_DEST (XVECEXP (newpat, 0, 0))))
2030 {
472fbdd1
RK		 2031 rtx ni2dest;
2032
230d793d 2033 newi2pat = XVECEXP (newpat, 0, 0);
472fbdd1 2034 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
230d793d
RS		 2035 newpat = XVECEXP (newpat, 0, 1);
2036 SUBST (SET_SRC (newpat),
472fbdd1 2037 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
a29ca9db
RK		 2038 i2_code_number
2039 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2040
230d793d 2041 if (i2_code_number >= 0)
a29ca9db
RK		 2042 insn_code_number
2043 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
5089e22e
RS		 2044
2045 if (insn_code_number >= 0)
2046 {
2047 rtx insn;
2048 rtx link;
2049
2050 /* If we will be able to accept this, we have made a change to the
2051 destination of I3. This can invalidate a LOG_LINKS pointing
2052 to I3. No other part of combine.c makes such a transformation.
2053
2054 The new I3 will have a destination that was previously the
2055 destination of I1 or I2 and which was used in i2 or I3. Call
2056 distribute_links to make a LOG_LINK from the next use of
2057 that destination. */
2058
2059 PATTERN (i3) = newpat;
38a448ca 2060 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
5089e22e
RS		 2061
2062 /* I3 now uses what used to be its destination and which is
2063 now I2's destination. That means we need a LOG_LINK from
2064 I3 to I2. But we used to have one, so we still will.
2065
2066 However, some later insn might be using I2's dest and have
2067 a LOG_LINK pointing at I3. We must remove this link.
2068 The simplest way to remove the link is to point it at I1,
2069 which we know will be a NOTE. */
2070
2071 for (insn = NEXT_INSN (i3);
0d4d42c3
RK		 2072 insn && (this_basic_block == n_basic_blocks - 1
2073 || insn != basic_block_head[this_basic_block + 1]);
5089e22e
RS		 2074 insn = NEXT_INSN (insn))
2075 {
2076 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
472fbdd1 2077 && reg_referenced_p (ni2dest, PATTERN (insn)))
5089e22e
RS		 2078 {
2079 for (link = LOG_LINKS (insn); link;
2080 link = XEXP (link, 1))
2081 if (XEXP (link, 0) == i3)
2082 XEXP (link, 0) = i1;
2083
2084 break;
2085 }
2086 }
2087 }
230d793d
RS		 2088 }
2089
2090 /* Similarly, check for a case where we have a PARALLEL of two independent
2091 SETs but we started with three insns. In this case, we can do the sets
2092 as two separate insns. This case occurs when some SET allows two
2093 other insns to combine, but the destination of that SET is still live. */
2094
2095 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2096 && GET_CODE (newpat) == PARALLEL
2097 && XVECLEN (newpat, 0) == 2
2098 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2099 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2100 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2101 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2104 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2105 INSN_CUID (i2))
2106 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2107 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2108 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2109 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2110 XVECEXP (newpat, 0, 0))
2111 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2112 XVECEXP (newpat, 0, 1)))
2113 {
e9a25f70
JL		 2114 /* Normally, it doesn't matter which of the two is done first,
2115 but it does if one references cc0. In that case, it has to
2116 be first. */
2117#ifdef HAVE_cc0
2118 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2119 {
2120 newi2pat = XVECEXP (newpat, 0, 0);
2121 newpat = XVECEXP (newpat, 0, 1);
2122 }
2123 else
2124#endif
2125 {
2126 newi2pat = XVECEXP (newpat, 0, 1);
2127 newpat = XVECEXP (newpat, 0, 0);
2128 }
230d793d 2129
a29ca9db
RK		 2130 i2_code_number
2131 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2132
230d793d 2133 if (i2_code_number >= 0)
a29ca9db
RK		 2134 insn_code_number
2135 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
230d793d
RS		 2136 }
2137
2138 /* If it still isn't recognized, fail and change things back the way they
2139 were. */
2140 if ((insn_code_number < 0
2141 /* Is the result a reasonable ASM_OPERANDS? */
2142 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2143 {
2144 undo_all ();
2145 return 0;
2146 }
2147
2148 /* If we had to change another insn, make sure it is valid also. */
2149 if (undobuf.other_insn)
2150 {
230d793d
RS		 2151 rtx other_pat = PATTERN (undobuf.other_insn);
2152 rtx new_other_notes;
2153 rtx note, next;
2154
6e25d159
RK		 2155 CLEAR_HARD_REG_SET (newpat_used_regs);
2156
a29ca9db
RK		 2157 other_code_number
2158 = recog_for_combine (&other_pat, undobuf.other_insn,
2159 &new_other_notes, &other_scratches);
230d793d
RS		 2160
2161 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2162 {
2163 undo_all ();
2164 return 0;
2165 }
2166
2167 PATTERN (undobuf.other_insn) = other_pat;
2168
2169 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2170 are still valid. Then add any non-duplicate notes added by
2171 recog_for_combine. */
2172 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2173 {
2174 next = XEXP (note, 1);
2175
2176 if (REG_NOTE_KIND (note) == REG_UNUSED
2177 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1a26b032
RK		 2178 {
2179 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2180 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
1a26b032
RK		 2181
2182 remove_note (undobuf.other_insn, note);
2183 }
230d793d
RS		 2184 }
2185
1a26b032
RK		 2186 for (note = new_other_notes; note; note = XEXP (note, 1))
2187 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2188 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 2189
230d793d 2190 distribute_notes (new_other_notes, undobuf.other_insn,
5f4f0e22 2191 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
230d793d
RS		 2192 }
2193
2194 /* We now know that we can do this combination. Merge the insns and
2195 update the status of registers and LOG_LINKS. */
2196
2197 {
2198 rtx i3notes, i2notes, i1notes = 0;
2199 rtx i3links, i2links, i1links = 0;
2200 rtx midnotes = 0;
230d793d 2201 register int regno;
ff3467a9
JW		 2202 /* Compute which registers we expect to eliminate. newi2pat may be setting
2203 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2204 same as i3dest, in which case newi2pat may be setting i1dest. */
2205 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2206 || i2dest_in_i2src || i2dest_in_i1src
230d793d 2207 ? 0 : i2dest);
ff3467a9
JW		 2208 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2209 || (newi2pat && reg_set_p (i1dest, newi2pat))
2210 ? 0 : i1dest);
230d793d
RS		 2211
2212 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2213 clear them. */
2214 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2215 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2216 if (i1)
2217 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2218
2219 /* Ensure that we do not have something that should not be shared but
2220 occurs multiple times in the new insns. Check this by first
5089e22e 2221 resetting all the `used' flags and then copying anything is shared. */
230d793d
RS		 2222
2223 reset_used_flags (i3notes);
2224 reset_used_flags (i2notes);
2225 reset_used_flags (i1notes);
2226 reset_used_flags (newpat);
2227 reset_used_flags (newi2pat);
2228 if (undobuf.other_insn)
2229 reset_used_flags (PATTERN (undobuf.other_insn));
2230
2231 i3notes = copy_rtx_if_shared (i3notes);
2232 i2notes = copy_rtx_if_shared (i2notes);
2233 i1notes = copy_rtx_if_shared (i1notes);
2234 newpat = copy_rtx_if_shared (newpat);
2235 newi2pat = copy_rtx_if_shared (newi2pat);
2236 if (undobuf.other_insn)
2237 reset_used_flags (PATTERN (undobuf.other_insn));
2238
2239 INSN_CODE (i3) = insn_code_number;
2240 PATTERN (i3) = newpat;
2241 if (undobuf.other_insn)
2242 INSN_CODE (undobuf.other_insn) = other_code_number;
2243
2244 /* We had one special case above where I2 had more than one set and
2245 we replaced a destination of one of those sets with the destination
2246 of I3. In that case, we have to update LOG_LINKS of insns later
176c9e6b
JW		 2247 in this basic block. Note that this (expensive) case is rare.
2248
2249 Also, in this case, we must pretend that all REG_NOTEs for I2
2250 actually came from I3, so that REG_UNUSED notes from I2 will be
2251 properly handled. */
2252
2253 if (i3_subst_into_i2)
2254 {
2255 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2256 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2257 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2258 && ! find_reg_note (i2, REG_UNUSED,
2259 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2260 for (temp = NEXT_INSN (i2);
2261 temp && (this_basic_block == n_basic_blocks - 1
2262 || basic_block_head[this_basic_block] != temp);
2263 temp = NEXT_INSN (temp))
2264 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2265 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2266 if (XEXP (link, 0) == i2)
2267 XEXP (link, 0) = i3;
2268
2269 if (i3notes)
2270 {
2271 rtx link = i3notes;
2272 while (XEXP (link, 1))
2273 link = XEXP (link, 1);
2274 XEXP (link, 1) = i2notes;
2275 }
2276 else
2277 i3notes = i2notes;
2278 i2notes = 0;
2279 }
230d793d
RS		 2280
2281 LOG_LINKS (i3) = 0;
2282 REG_NOTES (i3) = 0;
2283 LOG_LINKS (i2) = 0;
2284 REG_NOTES (i2) = 0;
2285
2286 if (newi2pat)
2287 {
2288 INSN_CODE (i2) = i2_code_number;
2289 PATTERN (i2) = newi2pat;
2290 }
2291 else
2292 {
2293 PUT_CODE (i2, NOTE);
2294 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2295 NOTE_SOURCE_FILE (i2) = 0;
2296 }
2297
2298 if (i1)
2299 {
2300 LOG_LINKS (i1) = 0;
2301 REG_NOTES (i1) = 0;
2302 PUT_CODE (i1, NOTE);
2303 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2304 NOTE_SOURCE_FILE (i1) = 0;
2305 }
2306
2307 /* Get death notes for everything that is now used in either I3 or
6eb12cef
RK		 2308 I2 and used to die in a previous insn. If we built two new
2309 patterns, move from I1 to I2 then I2 to I3 so that we get the
2310 proper movement on registers that I2 modifies. */
230d793d 2311
230d793d 2312 if (newi2pat)
6eb12cef
RK		 2313 {
2314 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2315 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2316 }
2317 else
2318 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2319 i3, &midnotes);
230d793d
RS		 2320
2321 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2322 if (i3notes)
5f4f0e22
CH		 2323 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2324 elim_i2, elim_i1);
230d793d 2325 if (i2notes)
5f4f0e22
CH		 2326 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2327 elim_i2, elim_i1);
230d793d 2328 if (i1notes)
5f4f0e22
CH		 2329 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2330 elim_i2, elim_i1);
230d793d 2331 if (midnotes)
5f4f0e22
CH		 2332 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2333 elim_i2, elim_i1);
230d793d
RS		 2334
2335 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2336 know these are REG_UNUSED and want them to go to the desired insn,
1a26b032
RK		 2337 so we always pass it as i3. We have not counted the notes in
2338 reg_n_deaths yet, so we need to do so now. */
2339
230d793d 2340 if (newi2pat && new_i2_notes)
1a26b032
RK		 2341 {
2342 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2343 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2344 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2345
2346 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2347 }
2348
230d793d 2349 if (new_i3_notes)
1a26b032
RK		 2350 {
2351 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2352 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2353 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2354
2355 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2356 }
230d793d
RS		 2357
2358 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
e9a25f70
JL		 2359 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2360 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2361 in that case, it might delete I2. Similarly for I2 and I1.
1a26b032
RK		 2362 Show an additional death due to the REG_DEAD note we make here. If
2363 we discard it in distribute_notes, we will decrement it again. */
d0ab8cd3 2364
230d793d 2365 if (i3dest_killed)
1a26b032
RK		 2366 {
2367 if (GET_CODE (i3dest_killed) == REG)
b1f21e0a 2368 REG_N_DEATHS (REGNO (i3dest_killed))++;
1a26b032 2369
e9a25f70 2370 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
38a448ca
RH		 2371 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2372 NULL_RTX),
ff3467a9 2373 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
e9a25f70 2374 else
38a448ca
RH		 2375 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2376 NULL_RTX),
e9a25f70 2377 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
ff3467a9 2378 elim_i2, elim_i1);
1a26b032 2379 }
58c8c593 2380
230d793d 2381 if (i2dest_in_i2src)
58c8c593 2382 {
1a26b032 2383 if (GET_CODE (i2dest) == REG)
b1f21e0a 2384 REG_N_DEATHS (REGNO (i2dest))++;
1a26b032 2385
58c8c593 2386 if (newi2pat && reg_set_p (i2dest, newi2pat))
38a448ca 2387 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2388 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2389 else
38a448ca 2390 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2391 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2392 NULL_RTX, NULL_RTX);
2393 }
2394
230d793d 2395 if (i1dest_in_i1src)
58c8c593 2396 {
1a26b032 2397 if (GET_CODE (i1dest) == REG)
b1f21e0a 2398 REG_N_DEATHS (REGNO (i1dest))++;
1a26b032 2399
58c8c593 2400 if (newi2pat && reg_set_p (i1dest, newi2pat))
38a448ca 2401 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2402 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2403 else
38a448ca 2404 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2405 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2406 NULL_RTX, NULL_RTX);
2407 }
230d793d
RS		 2408
2409 distribute_links (i3links);
2410 distribute_links (i2links);
2411 distribute_links (i1links);
2412
2413 if (GET_CODE (i2dest) == REG)
2414 {
d0ab8cd3
RK		 2415 rtx link;
2416 rtx i2_insn = 0, i2_val = 0, set;
2417
2418 /* The insn that used to set this register doesn't exist, and
2419 this life of the register may not exist either. See if one of
2420 I3's links points to an insn that sets I2DEST. If it does,
2421 that is now the last known value for I2DEST. If we don't update
2422 this and I2 set the register to a value that depended on its old
230d793d
RS		 2423 contents, we will get confused. If this insn is used, thing
2424 will be set correctly in combine_instructions. */
d0ab8cd3
RK		 2425
2426 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2427 if ((set = single_set (XEXP (link, 0))) != 0
2428 && rtx_equal_p (i2dest, SET_DEST (set)))
2429 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2430
2431 record_value_for_reg (i2dest, i2_insn, i2_val);
230d793d
RS		 2432
2433 /* If the reg formerly set in I2 died only once and that was in I3,
2434 zero its use count so it won't make `reload' do any work. */
538fe8cd
ILT		 2435 if (! added_sets_2
2436 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2437 && ! i2dest_in_i2src)
230d793d
RS		 2438 {
2439 regno = REGNO (i2dest);
b1f21e0a
MM		 2440 REG_N_SETS (regno)--;
2441 if (REG_N_SETS (regno) == 0
8e08106d 2442 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2443 REG_N_REFS (regno) = 0;
230d793d
RS		 2444 }
2445 }
2446
2447 if (i1 && GET_CODE (i1dest) == REG)
2448 {
d0ab8cd3
RK		 2449 rtx link;
2450 rtx i1_insn = 0, i1_val = 0, set;
2451
2452 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2453 if ((set = single_set (XEXP (link, 0))) != 0
2454 && rtx_equal_p (i1dest, SET_DEST (set)))
2455 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2456
2457 record_value_for_reg (i1dest, i1_insn, i1_val);
2458
230d793d 2459 regno = REGNO (i1dest);
5af91171 2460 if (! added_sets_1 && ! i1dest_in_i1src)
230d793d 2461 {
b1f21e0a
MM		 2462 REG_N_SETS (regno)--;
2463 if (REG_N_SETS (regno) == 0
8e08106d 2464 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2465 REG_N_REFS (regno) = 0;
230d793d
RS		 2466 }
2467 }
2468
951553af 2469 /* Update reg_nonzero_bits et al for any changes that may have been made
22609cbf
RK		 2470 to this insn. */
2471
951553af 2472 note_stores (newpat, set_nonzero_bits_and_sign_copies);
22609cbf 2473 if (newi2pat)
951553af 2474 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
22609cbf 2475
a29ca9db
RK		 2476 /* If we added any (clobber (scratch)), add them to the max for a
2477 block. This is a very pessimistic calculation, since we might
2478 have had them already and this might not be the worst block, but
2479 it's not worth doing any better. */
2480 max_scratch += i3_scratches + i2_scratches + other_scratches;
2481
230d793d
RS		 2482 /* If I3 is now an unconditional jump, ensure that it has a
2483 BARRIER following it since it may have initially been a
381ee8af 2484 conditional jump. It may also be the last nonnote insn. */
230d793d
RS		 2485
2486 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
381ee8af
TW		 2487 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2488 || GET_CODE (temp) != BARRIER))
230d793d
RS		 2489 emit_barrier_after (i3);
2490 }
2491
2492 combine_successes++;
2493
bcd49eb7
JW		 2494 /* Clear this here, so that subsequent get_last_value calls are not
2495 affected. */
2496 subst_prev_insn = NULL_RTX;
2497
abe6e52f
RK		 2498 if (added_links_insn
2499 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2500 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2501 return added_links_insn;
2502 else
2503 return newi2pat ? i2 : i3;
230d793d
RS		 2504}
2505\f
2506/* Undo all the modifications recorded in undobuf. */
2507
2508static void
2509undo_all ()
2510{
241cea85
RK		 2511 struct undo *undo, *next;
2512
2513 for (undo = undobuf.undos; undo; undo = next)
7c046e4e 2514 {
241cea85
RK		 2515 next = undo->next;
2516 if (undo->is_int)
2517 *undo->where.i = undo->old_contents.i;
7c046e4e 2518 else
241cea85
RK		 2519 *undo->where.r = undo->old_contents.r;
2520
2521 undo->next = undobuf.frees;
2522 undobuf.frees = undo;
7c046e4e 2523 }
230d793d
RS		 2524
2525 obfree (undobuf.storage);
845fc875 2526 undobuf.undos = undobuf.previous_undos = 0;
bcd49eb7
JW		 2527
2528 /* Clear this here, so that subsequent get_last_value calls are not
2529 affected. */
2530 subst_prev_insn = NULL_RTX;
230d793d
RS		 2531}
2532\f
2533/* Find the innermost point within the rtx at LOC, possibly LOC itself,
d0ab8cd3
RK		 2534 where we have an arithmetic expression and return that point. LOC will
2535 be inside INSN.
230d793d
RS		 2536
2537 try_combine will call this function to see if an insn can be split into
2538 two insns. */
2539
2540static rtx *
d0ab8cd3 2541find_split_point (loc, insn)
230d793d 2542 rtx *loc;
d0ab8cd3 2543 rtx insn;
230d793d
RS		 2544{
2545 rtx x = *loc;
2546 enum rtx_code code = GET_CODE (x);
2547 rtx *split;
2548 int len = 0, pos, unsignedp;
2549 rtx inner;
2550
2551 /* First special-case some codes. */
2552 switch (code)
2553 {
2554 case SUBREG:
2555#ifdef INSN_SCHEDULING
2556 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2557 point. */
2558 if (GET_CODE (SUBREG_REG (x)) == MEM)
2559 return loc;
2560#endif
d0ab8cd3 2561 return find_split_point (&SUBREG_REG (x), insn);
230d793d 2562
230d793d 2563 case MEM:
916f14f1 2564#ifdef HAVE_lo_sum
230d793d
RS		 2565 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2566 using LO_SUM and HIGH. */
2567 if (GET_CODE (XEXP (x, 0)) == CONST
2568 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2569 {
2570 SUBST (XEXP (x, 0),
2571 gen_rtx_combine (LO_SUM, Pmode,
2572 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2573 XEXP (x, 0)));
2574 return &XEXP (XEXP (x, 0), 0);
2575 }
230d793d
RS		 2576#endif
2577
916f14f1
RK		 2578 /* If we have a PLUS whose second operand is a constant and the
2579 address is not valid, perhaps will can split it up using
2580 the machine-specific way to split large constants. We use
ddd5a7c1 2581 the first pseudo-reg (one of the virtual regs) as a placeholder;
916f14f1
RK		 2582 it will not remain in the result. */
2583 if (GET_CODE (XEXP (x, 0)) == PLUS
2584 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2585 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2586 {
2587 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
38a448ca 2588 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
916f14f1
RK		 2589 subst_insn);
2590
2591 /* This should have produced two insns, each of which sets our
2592 placeholder. If the source of the second is a valid address,
2593 we can make put both sources together and make a split point
2594 in the middle. */
2595
2596 if (seq && XVECLEN (seq, 0) == 2
2597 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2598 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2599 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2600 && ! reg_mentioned_p (reg,
2601 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2602 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2603 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2604 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2605 && memory_address_p (GET_MODE (x),
2606 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2607 {
2608 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2609 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2610
2611 /* Replace the placeholder in SRC2 with SRC1. If we can
2612 find where in SRC2 it was placed, that can become our
2613 split point and we can replace this address with SRC2.
2614 Just try two obvious places. */
2615
2616 src2 = replace_rtx (src2, reg, src1);
2617 split = 0;
2618 if (XEXP (src2, 0) == src1)
2619 split = &XEXP (src2, 0);
2620 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2621 && XEXP (XEXP (src2, 0), 0) == src1)
2622 split = &XEXP (XEXP (src2, 0), 0);
2623
2624 if (split)
2625 {
2626 SUBST (XEXP (x, 0), src2);
2627 return split;
2628 }
2629 }
1a26b032
RK		 2630
2631 /* If that didn't work, perhaps the first operand is complex and
2632 needs to be computed separately, so make a split point there.
2633 This will occur on machines that just support REG + CONST
2634 and have a constant moved through some previous computation. */
2635
2636 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2637 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2638 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2639 == 'o')))
2640 return &XEXP (XEXP (x, 0), 0);
916f14f1
RK		 2641 }
2642 break;
2643
230d793d
RS		 2644 case SET:
2645#ifdef HAVE_cc0
2646 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2647 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2648 we need to put the operand into a register. So split at that
2649 point. */
2650
2651 if (SET_DEST (x) == cc0_rtx
2652 && GET_CODE (SET_SRC (x)) != COMPARE
2653 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2654 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2655 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2656 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2657 return &SET_SRC (x);
2658#endif
2659
2660 /* See if we can split SET_SRC as it stands. */
d0ab8cd3 2661 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2662 if (split && split != &SET_SRC (x))
2663 return split;
2664
041d7180
JL		 2665 /* See if we can split SET_DEST as it stands. */
2666 split = find_split_point (&SET_DEST (x), insn);
2667 if (split && split != &SET_DEST (x))
2668 return split;
2669
230d793d
RS		 2670 /* See if this is a bitfield assignment with everything constant. If
2671 so, this is an IOR of an AND, so split it into that. */
2672 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2673 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
5f4f0e22 2674 <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 2675 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2676 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2677 && GET_CODE (SET_SRC (x)) == CONST_INT
2678 && ((INTVAL (XEXP (SET_DEST (x), 1))
2679 + INTVAL (XEXP (SET_DEST (x), 2)))
2680 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2681 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2682 {
2683 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2684 int len = INTVAL (XEXP (SET_DEST (x), 1));
2685 int src = INTVAL (SET_SRC (x));
2686 rtx dest = XEXP (SET_DEST (x), 0);
2687 enum machine_mode mode = GET_MODE (dest);
5f4f0e22 2688 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
230d793d 2689
f76b9db2
ILT		 2690 if (BITS_BIG_ENDIAN)
2691 pos = GET_MODE_BITSIZE (mode) - len - pos;
230d793d
RS		 2692
2693 if (src == mask)
2694 SUBST (SET_SRC (x),
5f4f0e22 2695 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
230d793d
RS		 2696 else
2697 SUBST (SET_SRC (x),
2698 gen_binary (IOR, mode,
2699 gen_binary (AND, mode, dest,
5f4f0e22
CH		 2700 GEN_INT (~ (mask << pos)
2701 & GET_MODE_MASK (mode))),
2702 GEN_INT (src << pos)));
230d793d
RS		 2703
2704 SUBST (SET_DEST (x), dest);
2705
d0ab8cd3 2706 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2707 if (split && split != &SET_SRC (x))
2708 return split;
2709 }
2710
2711 /* Otherwise, see if this is an operation that we can split into two.
2712 If so, try to split that. */
2713 code = GET_CODE (SET_SRC (x));
2714
2715 switch (code)
2716 {
d0ab8cd3
RK		 2717 case AND:
2718 /* If we are AND'ing with a large constant that is only a single
2719 bit and the result is only being used in a context where we
2720 need to know if it is zero or non-zero, replace it with a bit
2721 extraction. This will avoid the large constant, which might
2722 have taken more than one insn to make. If the constant were
2723 not a valid argument to the AND but took only one insn to make,
2724 this is no worse, but if it took more than one insn, it will
2725 be better. */
2726
2727 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2728 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2729 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2730 && GET_CODE (SET_DEST (x)) == REG
2731 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2732 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2733 && XEXP (*split, 0) == SET_DEST (x)
2734 && XEXP (*split, 1) == const0_rtx)
2735 {
76184def
DE		 2736 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2737 XEXP (SET_SRC (x), 0),
2738 pos, NULL_RTX, 1, 1, 0, 0);
2739 if (extraction != 0)
2740 {
2741 SUBST (SET_SRC (x), extraction);
2742 return find_split_point (loc, insn);
2743 }
d0ab8cd3
RK		 2744 }
2745 break;
2746
1a6ec070
RK		 2747 case NE:
2748 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2749 is known to be on, this can be converted into a NEG of a shift. */
2750 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2751 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4eb2cb10 2752 && 1 <= (pos = exact_log2
1a6ec070
RK		 2753 (nonzero_bits (XEXP (SET_SRC (x), 0),
2754 GET_MODE (XEXP (SET_SRC (x), 0))))))
2755 {
2756 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2757
2758 SUBST (SET_SRC (x),
2759 gen_rtx_combine (NEG, mode,
2760 gen_rtx_combine (LSHIFTRT, mode,
2761 XEXP (SET_SRC (x), 0),
4eb2cb10 2762 GEN_INT (pos))));
1a6ec070
RK		 2763
2764 split = find_split_point (&SET_SRC (x), insn);
2765 if (split && split != &SET_SRC (x))
2766 return split;
2767 }
2768 break;
2769
230d793d
RS		 2770 case SIGN_EXTEND:
2771 inner = XEXP (SET_SRC (x), 0);
101c1a3d
JL		 2772
2773 /* We can't optimize if either mode is a partial integer
2774 mode as we don't know how many bits are significant
2775 in those modes. */
2776 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2777 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2778 break;
2779
230d793d
RS		 2780 pos = 0;
2781 len = GET_MODE_BITSIZE (GET_MODE (inner));
2782 unsignedp = 0;
2783 break;
2784
2785 case SIGN_EXTRACT:
2786 case ZERO_EXTRACT:
2787 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2788 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2789 {
2790 inner = XEXP (SET_SRC (x), 0);
2791 len = INTVAL (XEXP (SET_SRC (x), 1));
2792 pos = INTVAL (XEXP (SET_SRC (x), 2));
2793
f76b9db2
ILT		 2794 if (BITS_BIG_ENDIAN)
2795 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
230d793d
RS		 2796 unsignedp = (code == ZERO_EXTRACT);
2797 }
2798 break;
e9a25f70
JL		 2799
2800 default:
2801 break;
230d793d
RS		 2802 }
2803
2804 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2805 {
2806 enum machine_mode mode = GET_MODE (SET_SRC (x));
2807
d0ab8cd3
RK		 2808 /* For unsigned, we have a choice of a shift followed by an
2809 AND or two shifts. Use two shifts for field sizes where the
2810 constant might be too large. We assume here that we can
2811 always at least get 8-bit constants in an AND insn, which is
2812 true for every current RISC. */
2813
2814 if (unsignedp && len <= 8)
230d793d
RS		 2815 {
2816 SUBST (SET_SRC (x),
2817 gen_rtx_combine
2818 (AND, mode,
2819 gen_rtx_combine (LSHIFTRT, mode,
2820 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2821 GEN_INT (pos)),
2822 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
230d793d 2823
d0ab8cd3 2824 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2825 if (split && split != &SET_SRC (x))
2826 return split;
2827 }
2828 else
2829 {
2830 SUBST (SET_SRC (x),
2831 gen_rtx_combine
d0ab8cd3 2832 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
230d793d
RS		 2833 gen_rtx_combine (ASHIFT, mode,
2834 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2835 GEN_INT (GET_MODE_BITSIZE (mode)
2836 - len - pos)),
2837 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
230d793d 2838
d0ab8cd3 2839 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2840 if (split && split != &SET_SRC (x))
2841 return split;
2842 }
2843 }
2844
2845 /* See if this is a simple operation with a constant as the second
2846 operand. It might be that this constant is out of range and hence
2847 could be used as a split point. */
2848 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2849 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2850 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2851 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2852 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2853 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2854 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2855 == 'o'))))
2856 return &XEXP (SET_SRC (x), 1);
2857
2858 /* Finally, see if this is a simple operation with its first operand
2859 not in a register. The operation might require this operand in a
2860 register, so return it as a split point. We can always do this
2861 because if the first operand were another operation, we would have
2862 already found it as a split point. */
2863 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2864 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2865 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2866 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2867 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2868 return &XEXP (SET_SRC (x), 0);
2869
2870 return 0;
2871
2872 case AND:
2873 case IOR:
2874 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2875 it is better to write this as (not (ior A B)) so we can split it.
2876 Similarly for IOR. */
2877 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2878 {
2879 SUBST (*loc,
2880 gen_rtx_combine (NOT, GET_MODE (x),
2881 gen_rtx_combine (code == IOR ? AND : IOR,
2882 GET_MODE (x),
2883 XEXP (XEXP (x, 0), 0),
2884 XEXP (XEXP (x, 1), 0))));
d0ab8cd3 2885 return find_split_point (loc, insn);
230d793d
RS		 2886 }
2887
2888 /* Many RISC machines have a large set of logical insns. If the
2889 second operand is a NOT, put it first so we will try to split the
2890 other operand first. */
2891 if (GET_CODE (XEXP (x, 1)) == NOT)
2892 {
2893 rtx tem = XEXP (x, 0);
2894 SUBST (XEXP (x, 0), XEXP (x, 1));
2895 SUBST (XEXP (x, 1), tem);
2896 }
2897 break;
e9a25f70
JL		 2898
2899 default:
2900 break;
230d793d
RS		 2901 }
2902
2903 /* Otherwise, select our actions depending on our rtx class. */
2904 switch (GET_RTX_CLASS (code))
2905 {
2906 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2907 case '3':
d0ab8cd3 2908 split = find_split_point (&XEXP (x, 2), insn);
230d793d
RS		 2909 if (split)
2910 return split;
0f41302f 2911 /* ... fall through ... */
230d793d
RS		 2912 case '2':
2913 case 'c':
2914 case '<':
d0ab8cd3 2915 split = find_split_point (&XEXP (x, 1), insn);
230d793d
RS		 2916 if (split)
2917 return split;
0f41302f 2918 /* ... fall through ... */
230d793d
RS		 2919 case '1':
2920 /* Some machines have (and (shift ...) ...) insns. If X is not
2921 an AND, but XEXP (X, 0) is, use it as our split point. */
2922 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2923 return &XEXP (x, 0);
2924
d0ab8cd3 2925 split = find_split_point (&XEXP (x, 0), insn);
230d793d
RS		 2926 if (split)
2927 return split;
2928 return loc;
2929 }
2930
2931 /* Otherwise, we don't have a split point. */
2932 return 0;
2933}
2934\f
2935/* Throughout X, replace FROM with TO, and return the result.
2936 The result is TO if X is FROM;
2937 otherwise the result is X, but its contents may have been modified.
2938 If they were modified, a record was made in undobuf so that
2939 undo_all will (among other things) return X to its original state.
2940
2941 If the number of changes necessary is too much to record to undo,
2942 the excess changes are not made, so the result is invalid.
2943 The changes already made can still be undone.
2944 undobuf.num_undo is incremented for such changes, so by testing that
2945 the caller can tell whether the result is valid.
2946
2947 `n_occurrences' is incremented each time FROM is replaced.
2948
2949 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2950
5089e22e 2951 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
230d793d
RS		 2952 by copying if `n_occurrences' is non-zero. */
2953
2954static rtx
2955subst (x, from, to, in_dest, unique_copy)
2956 register rtx x, from, to;
2957 int in_dest;
2958 int unique_copy;
2959{
f24ad0e4 2960 register enum rtx_code code = GET_CODE (x);
230d793d 2961 enum machine_mode op0_mode = VOIDmode;
8079805d
RK		 2962 register char *fmt;
2963 register int len, i;
2964 rtx new;
230d793d
RS		 2965
2966/* Two expressions are equal if they are identical copies of a shared
2967 RTX or if they are both registers with the same register number
2968 and mode. */
2969
2970#define COMBINE_RTX_EQUAL_P(X,Y) \
2971 ((X) == (Y) \
2972 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2973 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2974
2975 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2976 {
2977 n_occurrences++;
2978 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2979 }
2980
2981 /* If X and FROM are the same register but different modes, they will
2982 not have been seen as equal above. However, flow.c will make a
2983 LOG_LINKS entry for that case. If we do nothing, we will try to
2984 rerecognize our original insn and, when it succeeds, we will
2985 delete the feeding insn, which is incorrect.
2986
2987 So force this insn not to match in this (rare) case. */
2988 if (! in_dest && code == REG && GET_CODE (from) == REG
2989 && REGNO (x) == REGNO (from))
38a448ca 2990 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 2991
2992 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2993 of which may contain things that can be combined. */
2994 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2995 return x;
2996
2997 /* It is possible to have a subexpression appear twice in the insn.
2998 Suppose that FROM is a register that appears within TO.
2999 Then, after that subexpression has been scanned once by `subst',
3000 the second time it is scanned, TO may be found. If we were
3001 to scan TO here, we would find FROM within it and create a
3002 self-referent rtl structure which is completely wrong. */
3003 if (COMBINE_RTX_EQUAL_P (x, to))
3004 return to;
3005
3006 len = GET_RTX_LENGTH (code);
3007 fmt = GET_RTX_FORMAT (code);
3008
3009 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
3010 set up to skip this common case. All other cases where we want to
3011 suppress replacing something inside a SET_SRC are handled via the
3012 IN_DEST operand. */
3013 if (code == SET
3014 && (GET_CODE (SET_DEST (x)) == REG
3015 || GET_CODE (SET_DEST (x)) == CC0
3016 || GET_CODE (SET_DEST (x)) == PC))
3017 fmt = "ie";
3018
0f41302f
MS		 3019 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3020 constant. */
230d793d
RS		 3021 if (fmt[0] == 'e')
3022 op0_mode = GET_MODE (XEXP (x, 0));
3023
3024 for (i = 0; i < len; i++)
3025 {
3026 if (fmt[i] == 'E')
3027 {
3028 register int j;
3029 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3030 {
230d793d
RS		 3031 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3032 {
3033 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3034 n_occurrences++;
3035 }
3036 else
3037 {
3038 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
3039
3040 /* If this substitution failed, this whole thing fails. */
3041 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3042 return new;
3043 }
3044
3045 SUBST (XVECEXP (x, i, j), new);
3046 }
3047 }
3048 else if (fmt[i] == 'e')
3049 {
230d793d
RS		 3050 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3051 {
42301240
RK		 3052 /* In general, don't install a subreg involving two modes not
3053 tieable. It can worsen register allocation, and can even
3054 make invalid reload insns, since the reg inside may need to
3055 be copied from in the outside mode, and that may be invalid
3056 if it is an fp reg copied in integer mode.
3057
3058 We allow two exceptions to this: It is valid if it is inside
3059 another SUBREG and the mode of that SUBREG and the mode of
3060 the inside of TO is tieable and it is valid if X is a SET
3061 that copies FROM to CC0. */
3062 if (GET_CODE (to) == SUBREG
3063 && ! MODES_TIEABLE_P (GET_MODE (to),
3064 GET_MODE (SUBREG_REG (to)))
3065 && ! (code == SUBREG
8079805d
RK		 3066 && MODES_TIEABLE_P (GET_MODE (x),
3067 GET_MODE (SUBREG_REG (to))))
42301240
RK		 3068#ifdef HAVE_cc0
3069 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3070#endif
3071 )
38a448ca 3072 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
42301240 3073
230d793d
RS		 3074 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3075 n_occurrences++;
3076 }
3077 else
3078 /* If we are in a SET_DEST, suppress most cases unless we
3079 have gone inside a MEM, in which case we want to
3080 simplify the address. We assume here that things that
3081 are actually part of the destination have their inner
3082 parts in the first expression. This is true for SUBREG,
3083 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3084 things aside from REG and MEM that should appear in a
3085 SET_DEST. */
3086 new = subst (XEXP (x, i), from, to,
3087 (((in_dest
3088 && (code == SUBREG || code == STRICT_LOW_PART
3089 || code == ZERO_EXTRACT))
3090 || code == SET)
3091 && i == 0), unique_copy);
3092
3093 /* If we found that we will have to reject this combination,
3094 indicate that by returning the CLOBBER ourselves, rather than
3095 an expression containing it. This will speed things up as
3096 well as prevent accidents where two CLOBBERs are considered
3097 to be equal, thus producing an incorrect simplification. */
3098
3099 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3100 return new;
3101
3102 SUBST (XEXP (x, i), new);
3103 }
3104 }
3105
8079805d
RK		 3106 /* Try to simplify X. If the simplification changed the code, it is likely
3107 that further simplification will help, so loop, but limit the number
3108 of repetitions that will be performed. */
3109
3110 for (i = 0; i < 4; i++)
3111 {
3112 /* If X is sufficiently simple, don't bother trying to do anything
3113 with it. */
3114 if (code != CONST_INT && code != REG && code != CLOBBER)
3115 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
d0ab8cd3 3116
8079805d
RK		 3117 if (GET_CODE (x) == code)
3118 break;
d0ab8cd3 3119
8079805d 3120 code = GET_CODE (x);
eeb43d32 3121
8079805d
RK		 3122 /* We no longer know the original mode of operand 0 since we
3123 have changed the form of X) */
3124 op0_mode = VOIDmode;
3125 }
eeb43d32 3126
8079805d
RK		 3127 return x;
3128}
3129\f
3130/* Simplify X, a piece of RTL. We just operate on the expression at the
3131 outer level; call `subst' to simplify recursively. Return the new
3132 expression.
3133
3134 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3135 will be the iteration even if an expression with a code different from
3136 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
eeb43d32 3137
8079805d
RK		 3138static rtx
3139simplify_rtx (x, op0_mode, last, in_dest)
3140 rtx x;
3141 enum machine_mode op0_mode;
3142 int last;
3143 int in_dest;
3144{
3145 enum rtx_code code = GET_CODE (x);
3146 enum machine_mode mode = GET_MODE (x);
3147 rtx temp;
3148 int i;
d0ab8cd3 3149
230d793d
RS		 3150 /* If this is a commutative operation, put a constant last and a complex
3151 expression first. We don't need to do this for comparisons here. */
3152 if (GET_RTX_CLASS (code) == 'c'
3153 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3154 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3155 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3156 || (GET_CODE (XEXP (x, 0)) == SUBREG
3157 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3158 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3159 {
3160 temp = XEXP (x, 0);
3161 SUBST (XEXP (x, 0), XEXP (x, 1));
3162 SUBST (XEXP (x, 1), temp);
3163 }
3164
22609cbf
RK		 3165 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3166 sign extension of a PLUS with a constant, reverse the order of the sign
3167 extension and the addition. Note that this not the same as the original
3168 code, but overflow is undefined for signed values. Also note that the
3169 PLUS will have been partially moved "inside" the sign-extension, so that
3170 the first operand of X will really look like:
3171 (ashiftrt (plus (ashift A C4) C5) C4).
3172 We convert this to
3173 (plus (ashiftrt (ashift A C4) C2) C4)
3174 and replace the first operand of X with that expression. Later parts
3175 of this function may simplify the expression further.
3176
3177 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3178 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3179 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3180
3181 We do this to simplify address expressions. */
3182
3183 if ((code == PLUS || code == MINUS || code == MULT)
3184 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3185 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3186 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3187 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3188 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3189 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3190 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3191 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3192 XEXP (XEXP (XEXP (x, 0), 0), 1),
3193 XEXP (XEXP (x, 0), 1))) != 0)
3194 {
3195 rtx new
3196 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3197 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3198 INTVAL (XEXP (XEXP (x, 0), 1)));
3199
3200 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3201 INTVAL (XEXP (XEXP (x, 0), 1)));
3202
3203 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3204 }
3205
d0ab8cd3
RK		 3206 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3207 applying it to the arms of the IF_THEN_ELSE. This often simplifies
abe6e52f
RK		 3208 things. Check for cases where both arms are testing the same
3209 condition.
3210
3211 Don't do anything if all operands are very simple. */
3212
3213 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3214 || GET_RTX_CLASS (code) == '<')
3215 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3216 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3217 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3218 == 'o')))
3219 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3220 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3221 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3222 == 'o')))))
3223 || (GET_RTX_CLASS (code) == '1'
3224 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3225 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3226 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3227 == 'o'))))))
d0ab8cd3 3228 {
abe6e52f
RK		 3229 rtx cond, true, false;
3230
3231 cond = if_then_else_cond (x, &true, &false);
0802d516
RK		 3232 if (cond != 0
3233 /* If everything is a comparison, what we have is highly unlikely
3234 to be simpler, so don't use it. */
3235 && ! (GET_RTX_CLASS (code) == '<'
3236 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3237 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
abe6e52f
RK		 3238 {
3239 rtx cop1 = const0_rtx;
3240 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3241
15448afc
RK		 3242 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3243 return x;
3244
9210df58
RK		 3245 /* Simplify the alternative arms; this may collapse the true and
3246 false arms to store-flag values. */
3247 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3248 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3249
3250 /* Restarting if we generate a store-flag expression will cause
3251 us to loop. Just drop through in this case. */
3252
abe6e52f
RK		 3253 /* If the result values are STORE_FLAG_VALUE and zero, we can
3254 just make the comparison operation. */
3255 if (true == const_true_rtx && false == const0_rtx)
3256 x = gen_binary (cond_code, mode, cond, cop1);
3257 else if (true == const0_rtx && false == const_true_rtx)
3258 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3259
3260 /* Likewise, we can make the negate of a comparison operation
3261 if the result values are - STORE_FLAG_VALUE and zero. */
3262 else if (GET_CODE (true) == CONST_INT
3263 && INTVAL (true) == - STORE_FLAG_VALUE
3264 && false == const0_rtx)
0c1c8ea6 3265 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3266 gen_binary (cond_code, mode, cond, cop1));
3267 else if (GET_CODE (false) == CONST_INT
3268 && INTVAL (false) == - STORE_FLAG_VALUE
3269 && true == const0_rtx)
0c1c8ea6 3270 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3271 gen_binary (reverse_condition (cond_code),
3272 mode, cond, cop1));
3273 else
38a448ca
RH		 3274 return gen_rtx_IF_THEN_ELSE (mode,
3275 gen_binary (cond_code, VOIDmode,
3276 cond, cop1),
3277 true, false);
5109d49f 3278
9210df58
RK		 3279 code = GET_CODE (x);
3280 op0_mode = VOIDmode;
abe6e52f 3281 }
d0ab8cd3
RK		 3282 }
3283
230d793d
RS		 3284 /* Try to fold this expression in case we have constants that weren't
3285 present before. */
3286 temp = 0;
3287 switch (GET_RTX_CLASS (code))
3288 {
3289 case '1':
3290 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3291 break;
3292 case '<':
3293 temp = simplify_relational_operation (code, op0_mode,
3294 XEXP (x, 0), XEXP (x, 1));
77fa0940
RK		 3295#ifdef FLOAT_STORE_FLAG_VALUE
3296 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3297 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3298 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3299#endif
230d793d
RS		 3300 break;
3301 case 'c':
3302 case '2':
3303 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3304 break;
3305 case 'b':
3306 case '3':
3307 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3308 XEXP (x, 1), XEXP (x, 2));
3309 break;
3310 }
3311
3312 if (temp)
d0ab8cd3 3313 x = temp, code = GET_CODE (temp);
230d793d 3314
230d793d 3315 /* First see if we can apply the inverse distributive law. */
224eeff2
RK		 3316 if (code == PLUS || code == MINUS
3317 || code == AND || code == IOR || code == XOR)
230d793d
RS		 3318 {
3319 x = apply_distributive_law (x);
3320 code = GET_CODE (x);
3321 }
3322
3323 /* If CODE is an associative operation not otherwise handled, see if we
3324 can associate some operands. This can win if they are constants or
3325 if they are logically related (i.e. (a & b) & a. */
3326 if ((code == PLUS || code == MINUS
3327 || code == MULT || code == AND || code == IOR || code == XOR
3328 || code == DIV || code == UDIV
3329 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3ad2180a 3330 && INTEGRAL_MODE_P (mode))
230d793d
RS		 3331 {
3332 if (GET_CODE (XEXP (x, 0)) == code)
3333 {
3334 rtx other = XEXP (XEXP (x, 0), 0);
3335 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3336 rtx inner_op1 = XEXP (x, 1);
3337 rtx inner;
3338
3339 /* Make sure we pass the constant operand if any as the second
3340 one if this is a commutative operation. */
3341 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3342 {
3343 rtx tem = inner_op0;
3344 inner_op0 = inner_op1;
3345 inner_op1 = tem;
3346 }
3347 inner = simplify_binary_operation (code == MINUS ? PLUS
3348 : code == DIV ? MULT
3349 : code == UDIV ? MULT
3350 : code,
3351 mode, inner_op0, inner_op1);
3352
3353 /* For commutative operations, try the other pair if that one
3354 didn't simplify. */
3355 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3356 {
3357 other = XEXP (XEXP (x, 0), 1);
3358 inner = simplify_binary_operation (code, mode,
3359 XEXP (XEXP (x, 0), 0),
3360 XEXP (x, 1));
3361 }
3362
3363 if (inner)
8079805d 3364 return gen_binary (code, mode, other, inner);
230d793d
RS		 3365 }
3366 }
3367
3368 /* A little bit of algebraic simplification here. */
3369 switch (code)
3370 {
3371 case MEM:
3372 /* Ensure that our address has any ASHIFTs converted to MULT in case
3373 address-recognizing predicates are called later. */
3374 temp = make_compound_operation (XEXP (x, 0), MEM);
3375 SUBST (XEXP (x, 0), temp);
3376 break;
3377
3378 case SUBREG:
3379 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3380 is paradoxical. If we can't do that safely, then it becomes
3381 something nonsensical so that this combination won't take place. */
3382
3383 if (GET_CODE (SUBREG_REG (x)) == MEM
3384 && (GET_MODE_SIZE (mode)
3385 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3386 {
3387 rtx inner = SUBREG_REG (x);
3388 int endian_offset = 0;
3389 /* Don't change the mode of the MEM
3390 if that would change the meaning of the address. */
3391 if (MEM_VOLATILE_P (SUBREG_REG (x))
3392 || mode_dependent_address_p (XEXP (inner, 0)))
38a448ca 3393 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d 3394
f76b9db2
ILT		 3395 if (BYTES_BIG_ENDIAN)
3396 {
3397 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3398 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3399 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3400 endian_offset -= (UNITS_PER_WORD
3401 - GET_MODE_SIZE (GET_MODE (inner)));
3402 }
230d793d
RS		 3403 /* Note if the plus_constant doesn't make a valid address
3404 then this combination won't be accepted. */
38a448ca
RH		 3405 x = gen_rtx_MEM (mode,
3406 plus_constant (XEXP (inner, 0),
3407 (SUBREG_WORD (x) * UNITS_PER_WORD
3408 + endian_offset)));
230d793d
RS		 3409 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3410 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3411 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3412 return x;
3413 }
3414
3415 /* If we are in a SET_DEST, these other cases can't apply. */
3416 if (in_dest)
3417 return x;
3418
3419 /* Changing mode twice with SUBREG => just change it once,
3420 or not at all if changing back to starting mode. */
3421 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3422 {
3423 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3424 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3425 return SUBREG_REG (SUBREG_REG (x));
3426
3427 SUBST_INT (SUBREG_WORD (x),
3428 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3429 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3430 }
3431
3432 /* SUBREG of a hard register => just change the register number
3433 and/or mode. If the hard register is not valid in that mode,
26ecfc76
RK		 3434 suppress this combination. If the hard register is the stack,
3435 frame, or argument pointer, leave this as a SUBREG. */
230d793d
RS		 3436
3437 if (GET_CODE (SUBREG_REG (x)) == REG
26ecfc76
RK		 3438 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3439 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
6d7096b0
DE		 3440#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3441 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3442#endif
26ecfc76
RK		 3443#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3444 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3445#endif
3446 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
230d793d
RS		 3447 {
3448 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3449 mode))
38a448ca
RH		 3450 return gen_rtx_REG (mode,
3451 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
230d793d 3452 else
38a448ca 3453 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d
RS		 3454 }
3455
3456 /* For a constant, try to pick up the part we want. Handle a full
a4bde0b1
RK		 3457 word and low-order part. Only do this if we are narrowing
3458 the constant; if it is being widened, we have no idea what
3459 the extra bits will have been set to. */
230d793d
RS		 3460
3461 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3462 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3c99d5ff 3463 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
230d793d
RS		 3464 && GET_MODE_CLASS (mode) == MODE_INT)
3465 {
3466 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
5f4f0e22 3467 0, op0_mode);
230d793d
RS		 3468 if (temp)
3469 return temp;
3470 }
3471
19808e22
RS		 3472 /* If we want a subreg of a constant, at offset 0,
3473 take the low bits. On a little-endian machine, that's
3474 always valid. On a big-endian machine, it's valid
3c99d5ff 3475 only if the constant's mode fits in one word. Note that we
61b1bece 3476 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3c99d5ff
RK		 3477 if (CONSTANT_P (SUBREG_REG (x))
3478 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3479 || ! WORDS_BIG_ENDIAN)
3480 ? SUBREG_WORD (x) == 0
3481 : (SUBREG_WORD (x)
3482 == ((GET_MODE_SIZE (op0_mode)
3483 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3484 / UNITS_PER_WORD)))
f82da7d2 3485 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
f76b9db2
ILT		 3486 && (! WORDS_BIG_ENDIAN
3487 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
230d793d
RS		 3488 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3489
b65c1b5b
RK		 3490 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3491 since we are saying that the high bits don't matter. */
3492 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3493 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3494 return SUBREG_REG (x);
3495
87e3e0c1
RK		 3496 /* Note that we cannot do any narrowing for non-constants since
3497 we might have been counting on using the fact that some bits were
3498 zero. We now do this in the SET. */
3499
230d793d
RS		 3500 break;
3501
3502 case NOT:
3503 /* (not (plus X -1)) can become (neg X). */
3504 if (GET_CODE (XEXP (x, 0)) == PLUS
3505 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
8079805d 3506 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3507
3508 /* Similarly, (not (neg X)) is (plus X -1). */
3509 if (GET_CODE (XEXP (x, 0)) == NEG)
8079805d
RK		 3510 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3511 constm1_rtx);
230d793d 3512
d0ab8cd3
RK		 3513 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3514 if (GET_CODE (XEXP (x, 0)) == XOR
3515 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3516 && (temp = simplify_unary_operation (NOT, mode,
3517 XEXP (XEXP (x, 0), 1),
3518 mode)) != 0)
787745f5 3519 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
d0ab8cd3 3520
230d793d
RS		 3521 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3522 other than 1, but that is not valid. We could do a similar
3523 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3524 but this doesn't seem common enough to bother with. */
3525 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3526 && XEXP (XEXP (x, 0), 0) == const1_rtx)
38a448ca
RH		 3527 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3528 XEXP (XEXP (x, 0), 1));
230d793d
RS		 3529
3530 if (GET_CODE (XEXP (x, 0)) == SUBREG
3531 && subreg_lowpart_p (XEXP (x, 0))
3532 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3533 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3534 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3535 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3536 {
3537 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3538
38a448ca
RH		 3539 x = gen_rtx_ROTATE (inner_mode,
3540 gen_unary (NOT, inner_mode, inner_mode,
3541 const1_rtx),
3542 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
8079805d 3543 return gen_lowpart_for_combine (mode, x);
230d793d
RS		 3544 }
3545
0802d516
RK		 3546 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3547 reversing the comparison code if valid. */
3548 if (STORE_FLAG_VALUE == -1
3549 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
230d793d
RS		 3550 && reversible_comparison_p (XEXP (x, 0)))
3551 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3552 mode, XEXP (XEXP (x, 0), 0),
3553 XEXP (XEXP (x, 0), 1));
500c518b
RK		 3554
3555 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
0802d516
RK		 3556 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3557 perform the above simplification. */
500c518b 3558
0802d516
RK		 3559 if (STORE_FLAG_VALUE == -1
3560 && XEXP (x, 1) == const1_rtx
500c518b
RK		 3561 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3562 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3563 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3564 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
230d793d
RS		 3565
3566 /* Apply De Morgan's laws to reduce number of patterns for machines
3567 with negating logical insns (and-not, nand, etc.). If result has
3568 only one NOT, put it first, since that is how the patterns are
3569 coded. */
3570
3571 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3572 {
3573 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3574
3575 if (GET_CODE (in1) == NOT)
3576 in1 = XEXP (in1, 0);
3577 else
3578 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3579
3580 if (GET_CODE (in2) == NOT)
3581 in2 = XEXP (in2, 0);
3582 else if (GET_CODE (in2) == CONST_INT
5f4f0e22
CH		 3583 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3584 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
230d793d
RS		 3585 else
3586 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3587
3588 if (GET_CODE (in2) == NOT)
3589 {
3590 rtx tem = in2;
3591 in2 = in1; in1 = tem;
3592 }
3593
8079805d
RK		 3594 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3595 mode, in1, in2);
230d793d
RS		 3596 }
3597 break;
3598
3599 case NEG:
3600 /* (neg (plus X 1)) can become (not X). */
3601 if (GET_CODE (XEXP (x, 0)) == PLUS
3602 && XEXP (XEXP (x, 0), 1) == const1_rtx)
8079805d 3603 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3604
3605 /* Similarly, (neg (not X)) is (plus X 1). */
3606 if (GET_CODE (XEXP (x, 0)) == NOT)
8079805d 3607 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
230d793d 3608
230d793d
RS		 3609 /* (neg (minus X Y)) can become (minus Y X). */
3610 if (GET_CODE (XEXP (x, 0)) == MINUS
3ad2180a 3611 && (! FLOAT_MODE_P (mode)
0f41302f 3612 /* x-y != -(y-x) with IEEE floating point. */
7e2a0d8e
RK		 3613 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3614 || flag_fast_math))
8079805d
RK		 3615 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3616 XEXP (XEXP (x, 0), 0));
230d793d 3617
0f41302f 3618 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
d0ab8cd3 3619 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
951553af 3620 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
8079805d 3621 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
d0ab8cd3 3622
230d793d
RS		 3623 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3624 if we can then eliminate the NEG (e.g.,
3625 if the operand is a constant). */
3626
3627 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3628 {
3629 temp = simplify_unary_operation (NEG, mode,
3630 XEXP (XEXP (x, 0), 0), mode);
3631 if (temp)
3632 {
3633 SUBST (XEXP (XEXP (x, 0), 0), temp);
3634 return XEXP (x, 0);
3635 }
3636 }
3637
3638 temp = expand_compound_operation (XEXP (x, 0));
3639
3640 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3641 replaced by (lshiftrt X C). This will convert
3642 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3643
3644 if (GET_CODE (temp) == ASHIFTRT
3645 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3646 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
8079805d
RK		 3647 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3648 INTVAL (XEXP (temp, 1)));
230d793d 3649
951553af 3650 /* If X has only a single bit that might be nonzero, say, bit I, convert
230d793d
RS		 3651 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3652 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3653 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3654 or a SUBREG of one since we'd be making the expression more
3655 complex if it was just a register. */
3656
3657 if (GET_CODE (temp) != REG
3658 && ! (GET_CODE (temp) == SUBREG
3659 && GET_CODE (SUBREG_REG (temp)) == REG)
951553af 3660 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
230d793d
RS		 3661 {
3662 rtx temp1 = simplify_shift_const
5f4f0e22
CH		 3663 (NULL_RTX, ASHIFTRT, mode,
3664 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
230d793d
RS		 3665 GET_MODE_BITSIZE (mode) - 1 - i),
3666 GET_MODE_BITSIZE (mode) - 1 - i);
3667
3668 /* If all we did was surround TEMP with the two shifts, we
3669 haven't improved anything, so don't use it. Otherwise,
3670 we are better off with TEMP1. */
3671 if (GET_CODE (temp1) != ASHIFTRT
3672 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3673 || XEXP (XEXP (temp1, 0), 0) != temp)
8079805d 3674 return temp1;
230d793d
RS		 3675 }
3676 break;
3677
2ca9ae17 3678 case TRUNCATE:
e30fb98f
JL		 3679 /* We can't handle truncation to a partial integer mode here
3680 because we don't know the real bitsize of the partial
3681 integer mode. */
3682 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3683 break;
3684
2ca9ae17
JW		 3685 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3686 SUBST (XEXP (x, 0),
3687 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3688 GET_MODE_MASK (mode), NULL_RTX, 0));
0f13a422
ILT		 3689
3690 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3691 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3692 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3693 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3694 return XEXP (XEXP (x, 0), 0);
3695
3696 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3697 (OP:SI foo:SI) if OP is NEG or ABS. */
3698 if ((GET_CODE (XEXP (x, 0)) == ABS
3699 || GET_CODE (XEXP (x, 0)) == NEG)
3700 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3701 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3702 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3703 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3704 XEXP (XEXP (XEXP (x, 0), 0), 0));
3705
3706 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3707 (truncate:SI x). */
3708 if (GET_CODE (XEXP (x, 0)) == SUBREG
3709 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3710 && subreg_lowpart_p (XEXP (x, 0)))
3711 return SUBREG_REG (XEXP (x, 0));
3712
3713 /* If we know that the value is already truncated, we can
3714 replace the TRUNCATE with a SUBREG. */
3715 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3716 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3717 &~ GET_MODE_MASK (mode)) == 0)
3718 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3719
3720 /* A truncate of a comparison can be replaced with a subreg if
3721 STORE_FLAG_VALUE permits. This is like the previous test,
3722 but it works even if the comparison is done in a mode larger
3723 than HOST_BITS_PER_WIDE_INT. */
3724 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3725 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3726 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3727 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3728
3729 /* Similarly, a truncate of a register whose value is a
3730 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3731 permits. */
3732 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3733 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3734 && (temp = get_last_value (XEXP (x, 0)))
3735 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3736 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3737
2ca9ae17
JW		 3738 break;
3739
230d793d
RS		 3740 case FLOAT_TRUNCATE:
3741 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3742 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3743 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3744 return XEXP (XEXP (x, 0), 0);
4635f748
RK		 3745
3746 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3747 (OP:SF foo:SF) if OP is NEG or ABS. */
3748 if ((GET_CODE (XEXP (x, 0)) == ABS
3749 || GET_CODE (XEXP (x, 0)) == NEG)
3750 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3751 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
0c1c8ea6
RK		 3752 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3753 XEXP (XEXP (XEXP (x, 0), 0), 0));
1d12df72
RK		 3754
3755 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3756 is (float_truncate:SF x). */
3757 if (GET_CODE (XEXP (x, 0)) == SUBREG
3758 && subreg_lowpart_p (XEXP (x, 0))
3759 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3760 return SUBREG_REG (XEXP (x, 0));
230d793d
RS		 3761 break;
3762
3763#ifdef HAVE_cc0
3764 case COMPARE:
3765 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3766 using cc0, in which case we want to leave it as a COMPARE
3767 so we can distinguish it from a register-register-copy. */
3768 if (XEXP (x, 1) == const0_rtx)
3769 return XEXP (x, 0);
3770
3771 /* In IEEE floating point, x-0 is not the same as x. */
3772 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e
RK		 3773 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3774 || flag_fast_math)
230d793d
RS		 3775 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3776 return XEXP (x, 0);
3777 break;
3778#endif
3779
3780 case CONST:
3781 /* (const (const X)) can become (const X). Do it this way rather than
3782 returning the inner CONST since CONST can be shared with a
3783 REG_EQUAL note. */
3784 if (GET_CODE (XEXP (x, 0)) == CONST)
3785 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3786 break;
3787
3788#ifdef HAVE_lo_sum
3789 case LO_SUM:
3790 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3791 can add in an offset. find_split_point will split this address up
3792 again if it doesn't match. */
3793 if (GET_CODE (XEXP (x, 0)) == HIGH
3794 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3795 return XEXP (x, 1);
3796 break;
3797#endif
3798
3799 case PLUS:
3800 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3801 outermost. That's because that's the way indexed addresses are
3802 supposed to appear. This code used to check many more cases, but
3803 they are now checked elsewhere. */
3804 if (GET_CODE (XEXP (x, 0)) == PLUS
3805 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3806 return gen_binary (PLUS, mode,
3807 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3808 XEXP (x, 1)),
3809 XEXP (XEXP (x, 0), 1));
3810
3811 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3812 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3813 bit-field and can be replaced by either a sign_extend or a
3814 sign_extract. The `and' may be a zero_extend. */
3815 if (GET_CODE (XEXP (x, 0)) == XOR
3816 && GET_CODE (XEXP (x, 1)) == CONST_INT
3817 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3818 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3819 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5f4f0e22 3820 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 3821 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3822 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3823 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5f4f0e22 3824 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
230d793d
RS		 3825 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3826 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3827 == i + 1))))
8079805d
RK		 3828 return simplify_shift_const
3829 (NULL_RTX, ASHIFTRT, mode,
3830 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3831 XEXP (XEXP (XEXP (x, 0), 0), 0),
3832 GET_MODE_BITSIZE (mode) - (i + 1)),
3833 GET_MODE_BITSIZE (mode) - (i + 1));
230d793d 3834
bc0776c6
RK		 3835 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3836 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3837 is 1. This produces better code than the alternative immediately
3838 below. */
3839 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3840 && reversible_comparison_p (XEXP (x, 0))
3841 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3842 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
8079805d 3843 return
0c1c8ea6 3844 gen_unary (NEG, mode, mode,
8079805d
RK		 3845 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3846 mode, XEXP (XEXP (x, 0), 0),
3847 XEXP (XEXP (x, 0), 1)));
bc0776c6
RK		 3848
3849 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
230d793d
RS		 3850 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3851 the bitsize of the mode - 1. This allows simplification of
3852 "a = (b & 8) == 0;" */
3853 if (XEXP (x, 1) == constm1_rtx
3854 && GET_CODE (XEXP (x, 0)) != REG
3855 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3856 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
951553af 3857 && nonzero_bits (XEXP (x, 0), mode) == 1)
8079805d
RK		 3858 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3859 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3860 gen_rtx_combine (XOR, mode,
3861 XEXP (x, 0), const1_rtx),
3862 GET_MODE_BITSIZE (mode) - 1),
3863 GET_MODE_BITSIZE (mode) - 1);
02f4ada4
RK		 3864
3865 /* If we are adding two things that have no bits in common, convert
3866 the addition into an IOR. This will often be further simplified,
3867 for example in cases like ((a & 1) + (a & 2)), which can
3868 become a & 3. */
3869
ac49a949 3870 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
951553af
RK		 3871 && (nonzero_bits (XEXP (x, 0), mode)
3872 & nonzero_bits (XEXP (x, 1), mode)) == 0)
8079805d 3873 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
230d793d
RS		 3874 break;
3875
3876 case MINUS:
0802d516
RK		 3877 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3878 by reversing the comparison code if valid. */
3879 if (STORE_FLAG_VALUE == 1
3880 && XEXP (x, 0) == const1_rtx
5109d49f
RK		 3881 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3882 && reversible_comparison_p (XEXP (x, 1)))
3883 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3884 mode, XEXP (XEXP (x, 1), 0),
3885 XEXP (XEXP (x, 1), 1));
5109d49f 3886
230d793d
RS		 3887 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3888 (and <foo> (const_int pow2-1)) */
3889 if (GET_CODE (XEXP (x, 1)) == AND
3890 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3891 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3892 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8079805d
RK		 3893 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3894 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
7bef8680
RK		 3895
3896 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3897 integers. */
3898 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
8079805d
RK		 3899 return gen_binary (MINUS, mode,
3900 gen_binary (MINUS, mode, XEXP (x, 0),
3901 XEXP (XEXP (x, 1), 0)),
3902 XEXP (XEXP (x, 1), 1));
230d793d
RS		 3903 break;
3904
3905 case MULT:
3906 /* If we have (mult (plus A B) C), apply the distributive law and then
3907 the inverse distributive law to see if things simplify. This
3908 occurs mostly in addresses, often when unrolling loops. */
3909
3910 if (GET_CODE (XEXP (x, 0)) == PLUS)
3911 {
3912 x = apply_distributive_law
3913 (gen_binary (PLUS, mode,
3914 gen_binary (MULT, mode,
3915 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3916 gen_binary (MULT, mode,
3917 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3918
3919 if (GET_CODE (x) != MULT)
8079805d 3920 return x;
230d793d 3921 }
230d793d
RS		 3922 break;
3923
3924 case UDIV:
3925 /* If this is a divide by a power of two, treat it as a shift if
3926 its first operand is a shift. */
3927 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3928 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3929 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3930 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3931 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3932 || GET_CODE (XEXP (x, 0)) == ROTATE
3933 || GET_CODE (XEXP (x, 0)) == ROTATERT))
8079805d 3934 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
230d793d
RS		 3935 break;
3936
3937 case EQ: case NE:
3938 case GT: case GTU: case GE: case GEU:
3939 case LT: case LTU: case LE: case LEU:
3940 /* If the first operand is a condition code, we can't do anything
3941 with it. */
3942 if (GET_CODE (XEXP (x, 0)) == COMPARE
3943 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3944#ifdef HAVE_cc0
3945 && XEXP (x, 0) != cc0_rtx
3946#endif
3947 ))
3948 {
3949 rtx op0 = XEXP (x, 0);
3950 rtx op1 = XEXP (x, 1);
3951 enum rtx_code new_code;
3952
3953 if (GET_CODE (op0) == COMPARE)
3954 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3955
3956 /* Simplify our comparison, if possible. */
3957 new_code = simplify_comparison (code, &op0, &op1);
3958
230d793d 3959 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
951553af 3960 if only the low-order bit is possibly nonzero in X (such as when
5109d49f
RK		 3961 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3962 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3963 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3964 (plus X 1).
3965
3966 Remove any ZERO_EXTRACT we made when thinking this was a
3967 comparison. It may now be simpler to use, e.g., an AND. If a
3968 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3969 the call to make_compound_operation in the SET case. */
3970
0802d516
RK		 3971 if (STORE_FLAG_VALUE == 1
3972 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3973 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 3974 return gen_lowpart_for_combine (mode,
3975 expand_compound_operation (op0));
5109d49f 3976
0802d516
RK		 3977 else if (STORE_FLAG_VALUE == 1
3978 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 3979 && op1 == const0_rtx
3980 && (num_sign_bit_copies (op0, mode)
3981 == GET_MODE_BITSIZE (mode)))
3982 {
3983 op0 = expand_compound_operation (op0);
0c1c8ea6 3984 return gen_unary (NEG, mode, mode,
8079805d 3985 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 3986 }
3987
0802d516
RK		 3988 else if (STORE_FLAG_VALUE == 1
3989 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
230d793d 3990 && op1 == const0_rtx
5109d49f 3991 && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 3992 {
3993 op0 = expand_compound_operation (op0);
8079805d
RK		 3994 return gen_binary (XOR, mode,
3995 gen_lowpart_for_combine (mode, op0),
3996 const1_rtx);
5109d49f 3997 }
818b11b9 3998
0802d516
RK		 3999 else if (STORE_FLAG_VALUE == 1
4000 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4001 && op1 == const0_rtx
4002 && (num_sign_bit_copies (op0, mode)
4003 == GET_MODE_BITSIZE (mode)))
4004 {
4005 op0 = expand_compound_operation (op0);
8079805d 4006 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
818b11b9 4007 }
230d793d 4008
5109d49f
RK		 4009 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4010 those above. */
0802d516
RK		 4011 if (STORE_FLAG_VALUE == -1
4012 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4013 && op1 == const0_rtx
5109d49f
RK		 4014 && (num_sign_bit_copies (op0, mode)
4015 == GET_MODE_BITSIZE (mode)))
4016 return gen_lowpart_for_combine (mode,
4017 expand_compound_operation (op0));
4018
0802d516
RK		 4019 else if (STORE_FLAG_VALUE == -1
4020 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4021 && op1 == const0_rtx
4022 && nonzero_bits (op0, mode) == 1)
4023 {
4024 op0 = expand_compound_operation (op0);
0c1c8ea6 4025 return gen_unary (NEG, mode, mode,
8079805d 4026 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4027 }
4028
0802d516
RK		 4029 else if (STORE_FLAG_VALUE == -1
4030 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4031 && op1 == const0_rtx
4032 && (num_sign_bit_copies (op0, mode)
4033 == GET_MODE_BITSIZE (mode)))
230d793d 4034 {
818b11b9 4035 op0 = expand_compound_operation (op0);
0c1c8ea6 4036 return gen_unary (NOT, mode, mode,
8079805d 4037 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4038 }
4039
4040 /* If X is 0/1, (eq X 0) is X-1. */
0802d516
RK		 4041 else if (STORE_FLAG_VALUE == -1
4042 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4043 && op1 == const0_rtx
4044 && nonzero_bits (op0, mode) == 1)
4045 {
4046 op0 = expand_compound_operation (op0);
8079805d 4047 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
230d793d 4048 }
230d793d
RS		 4049
4050 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
951553af
RK		 4051 one bit that might be nonzero, we can convert (ne x 0) to
4052 (ashift x c) where C puts the bit in the sign bit. Remove any
4053 AND with STORE_FLAG_VALUE when we are done, since we are only
4054 going to test the sign bit. */
3f508eca 4055 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5f4f0e22 4056 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 4057 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5f4f0e22 4058 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
230d793d
RS		 4059 && op1 == const0_rtx
4060 && mode == GET_MODE (op0)
5109d49f 4061 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
230d793d 4062 {
818b11b9
RK		 4063 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4064 expand_compound_operation (op0),
230d793d
RS		 4065 GET_MODE_BITSIZE (mode) - 1 - i);
4066 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4067 return XEXP (x, 0);
4068 else
4069 return x;
4070 }
4071
4072 /* If the code changed, return a whole new comparison. */
4073 if (new_code != code)
4074 return gen_rtx_combine (new_code, mode, op0, op1);
4075
4076 /* Otherwise, keep this operation, but maybe change its operands.
4077 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4078 SUBST (XEXP (x, 0), op0);
4079 SUBST (XEXP (x, 1), op1);
4080 }
4081 break;
4082
4083 case IF_THEN_ELSE:
8079805d 4084 return simplify_if_then_else (x);
9210df58 4085
8079805d
RK		 4086 case ZERO_EXTRACT:
4087 case SIGN_EXTRACT:
4088 case ZERO_EXTEND:
4089 case SIGN_EXTEND:
0f41302f 4090 /* If we are processing SET_DEST, we are done. */
8079805d
RK		 4091 if (in_dest)
4092 return x;
d0ab8cd3 4093
8079805d 4094 return expand_compound_operation (x);
d0ab8cd3 4095
8079805d
RK		 4096 case SET:
4097 return simplify_set (x);
1a26b032 4098
8079805d
RK		 4099 case AND:
4100 case IOR:
4101 case XOR:
4102 return simplify_logical (x, last);
d0ab8cd3 4103
b472527b 4104 case ABS:
8079805d
RK		 4105 /* (abs (neg <foo>)) -> (abs <foo>) */
4106 if (GET_CODE (XEXP (x, 0)) == NEG)
4107 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
1a26b032 4108
b472527b
JL		 4109 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4110 do nothing. */
4111 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4112 break;
f40421ce 4113
8079805d
RK		 4114 /* If operand is something known to be positive, ignore the ABS. */
4115 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4116 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4117 <= HOST_BITS_PER_WIDE_INT)
4118 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4119 & ((HOST_WIDE_INT) 1
4120 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4121 == 0)))
4122 return XEXP (x, 0);
1a26b032 4123
1a26b032 4124
8079805d
RK		 4125 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4126 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4127 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
1a26b032 4128
8079805d 4129 break;
1a26b032 4130
8079805d
RK		 4131 case FFS:
4132 /* (ffs (*_extend <X>)) = (ffs <X>) */
4133 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4134 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4135 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4136 break;
1a26b032 4137
8079805d
RK		 4138 case FLOAT:
4139 /* (float (sign_extend <X>)) = (float <X>). */
4140 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4141 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4142 break;
1a26b032 4143
8079805d
RK		 4144 case ASHIFT:
4145 case LSHIFTRT:
4146 case ASHIFTRT:
4147 case ROTATE:
4148 case ROTATERT:
4149 /* If this is a shift by a constant amount, simplify it. */
4150 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4151 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4152 INTVAL (XEXP (x, 1)));
4153
4154#ifdef SHIFT_COUNT_TRUNCATED
4155 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4156 SUBST (XEXP (x, 1),
4157 force_to_mode (XEXP (x, 1), GET_MODE (x),
4158 ((HOST_WIDE_INT) 1
4159 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4160 - 1,
4161 NULL_RTX, 0));
4162#endif
4163
4164 break;
e9a25f70
JL		 4165
4166 default:
4167 break;
8079805d
RK		 4168 }
4169
4170 return x;
4171}
4172\f
4173/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5109d49f 4174
8079805d
RK		 4175static rtx
4176simplify_if_then_else (x)
4177 rtx x;
4178{
4179 enum machine_mode mode = GET_MODE (x);
4180 rtx cond = XEXP (x, 0);
4181 rtx true = XEXP (x, 1);
4182 rtx false = XEXP (x, 2);
4183 enum rtx_code true_code = GET_CODE (cond);
4184 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4185 rtx temp;
4186 int i;
4187
0f41302f 4188 /* Simplify storing of the truth value. */
8079805d
RK		 4189 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4190 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4191
0f41302f 4192 /* Also when the truth value has to be reversed. */
8079805d
RK		 4193 if (comparison_p && reversible_comparison_p (cond)
4194 && true == const0_rtx && false == const_true_rtx)
4195 return gen_binary (reverse_condition (true_code),
4196 mode, XEXP (cond, 0), XEXP (cond, 1));
4197
4198 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4199 in it is being compared against certain values. Get the true and false
4200 comparisons and see if that says anything about the value of each arm. */
4201
4202 if (comparison_p && reversible_comparison_p (cond)
4203 && GET_CODE (XEXP (cond, 0)) == REG)
4204 {
4205 HOST_WIDE_INT nzb;
4206 rtx from = XEXP (cond, 0);
4207 enum rtx_code false_code = reverse_condition (true_code);
4208 rtx true_val = XEXP (cond, 1);
4209 rtx false_val = true_val;
4210 int swapped = 0;
9210df58 4211
8079805d 4212 /* If FALSE_CODE is EQ, swap the codes and arms. */
5109d49f 4213
8079805d 4214 if (false_code == EQ)
1a26b032 4215 {
8079805d
RK		 4216 swapped = 1, true_code = EQ, false_code = NE;
4217 temp = true, true = false, false = temp;
4218 }
5109d49f 4219
8079805d
RK		 4220 /* If we are comparing against zero and the expression being tested has
4221 only a single bit that might be nonzero, that is its value when it is
4222 not equal to zero. Similarly if it is known to be -1 or 0. */
4223
4224 if (true_code == EQ && true_val == const0_rtx
4225 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4226 false_code = EQ, false_val = GEN_INT (nzb);
4227 else if (true_code == EQ && true_val == const0_rtx
4228 && (num_sign_bit_copies (from, GET_MODE (from))
4229 == GET_MODE_BITSIZE (GET_MODE (from))))
4230 false_code = EQ, false_val = constm1_rtx;
4231
4232 /* Now simplify an arm if we know the value of the register in the
4233 branch and it is used in the arm. Be careful due to the potential
4234 of locally-shared RTL. */
4235
4236 if (reg_mentioned_p (from, true))
4237 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4238 pc_rtx, pc_rtx, 0, 0);
4239 if (reg_mentioned_p (from, false))
4240 false = subst (known_cond (copy_rtx (false), false_code,
4241 from, false_val),
4242 pc_rtx, pc_rtx, 0, 0);
4243
4244 SUBST (XEXP (x, 1), swapped ? false : true);
4245 SUBST (XEXP (x, 2), swapped ? true : false);
4246
4247 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4248 }
5109d49f 4249
8079805d
RK		 4250 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4251 reversed, do so to avoid needing two sets of patterns for
4252 subtract-and-branch insns. Similarly if we have a constant in the true
4253 arm, the false arm is the same as the first operand of the comparison, or
4254 the false arm is more complicated than the true arm. */
4255
4256 if (comparison_p && reversible_comparison_p (cond)
4257 && (true == pc_rtx
4258 || (CONSTANT_P (true)
4259 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4260 || true == const0_rtx
4261 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4262 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4263 || (GET_CODE (true) == SUBREG
4264 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4265 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4266 || reg_mentioned_p (true, false)
4267 || rtx_equal_p (false, XEXP (cond, 0))))
4268 {
4269 true_code = reverse_condition (true_code);
4270 SUBST (XEXP (x, 0),
4271 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4272 XEXP (cond, 1)));
5109d49f 4273
8079805d
RK		 4274 SUBST (XEXP (x, 1), false);
4275 SUBST (XEXP (x, 2), true);
1a26b032 4276
8079805d 4277 temp = true, true = false, false = temp, cond = XEXP (x, 0);
bb821298 4278
0f41302f 4279 /* It is possible that the conditional has been simplified out. */
bb821298
RK		 4280 true_code = GET_CODE (cond);
4281 comparison_p = GET_RTX_CLASS (true_code) == '<';
8079805d 4282 }
abe6e52f 4283
8079805d 4284 /* If the two arms are identical, we don't need the comparison. */
1a26b032 4285
8079805d
RK		 4286 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4287 return true;
1a26b032 4288
5be669c7
RK		 4289 /* Convert a == b ? b : a to "a". */
4290 if (true_code == EQ && ! side_effects_p (cond)
4291 && rtx_equal_p (XEXP (cond, 0), false)
4292 && rtx_equal_p (XEXP (cond, 1), true))
4293 return false;
4294 else if (true_code == NE && ! side_effects_p (cond)
4295 && rtx_equal_p (XEXP (cond, 0), true)
4296 && rtx_equal_p (XEXP (cond, 1), false))
4297 return true;
4298
8079805d
RK		 4299 /* Look for cases where we have (abs x) or (neg (abs X)). */
4300
4301 if (GET_MODE_CLASS (mode) == MODE_INT
4302 && GET_CODE (false) == NEG
4303 && rtx_equal_p (true, XEXP (false, 0))
4304 && comparison_p
4305 && rtx_equal_p (true, XEXP (cond, 0))
4306 && ! side_effects_p (true))
4307 switch (true_code)
4308 {
4309 case GT:
4310 case GE:
0c1c8ea6 4311 return gen_unary (ABS, mode, mode, true);
8079805d
RK		 4312 case LT:
4313 case LE:
0c1c8ea6 4314 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
e9a25f70
JL		 4315 default:
4316 break;
8079805d
RK		 4317 }
4318
4319 /* Look for MIN or MAX. */
4320
34c8be72 4321 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
8079805d
RK		 4322 && comparison_p
4323 && rtx_equal_p (XEXP (cond, 0), true)
4324 && rtx_equal_p (XEXP (cond, 1), false)
4325 && ! side_effects_p (cond))
4326 switch (true_code)
4327 {
4328 case GE:
4329 case GT:
4330 return gen_binary (SMAX, mode, true, false);
4331 case LE:
4332 case LT:
4333 return gen_binary (SMIN, mode, true, false);
4334 case GEU:
4335 case GTU:
4336 return gen_binary (UMAX, mode, true, false);
4337 case LEU:
4338 case LTU:
4339 return gen_binary (UMIN, mode, true, false);
e9a25f70
JL		 4340 default:
4341 break;
8079805d
RK		 4342 }
4343
8079805d
RK		 4344 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4345 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4346 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4347 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4348 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
0802d516 4349 neither 1 or -1, but it isn't worth checking for. */
8079805d 4350
0802d516
RK		 4351 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4352 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
8079805d
RK		 4353 {
4354 rtx t = make_compound_operation (true, SET);
4355 rtx f = make_compound_operation (false, SET);
4356 rtx cond_op0 = XEXP (cond, 0);
4357 rtx cond_op1 = XEXP (cond, 1);
4358 enum rtx_code op, extend_op = NIL;
4359 enum machine_mode m = mode;
f24ad0e4 4360 rtx z = 0, c1;
8079805d 4361
8079805d
RK		 4362 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4363 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4364 || GET_CODE (t) == ASHIFT
4365 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4366 && rtx_equal_p (XEXP (t, 0), f))
4367 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4368
4369 /* If an identity-zero op is commutative, check whether there
0f41302f 4370 would be a match if we swapped the operands. */
8079805d
RK		 4371 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4372 || GET_CODE (t) == XOR)
4373 && rtx_equal_p (XEXP (t, 1), f))
4374 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4375 else if (GET_CODE (t) == SIGN_EXTEND
4376 && (GET_CODE (XEXP (t, 0)) == PLUS
4377 || GET_CODE (XEXP (t, 0)) == MINUS
4378 || GET_CODE (XEXP (t, 0)) == IOR
4379 || GET_CODE (XEXP (t, 0)) == XOR
4380 || GET_CODE (XEXP (t, 0)) == ASHIFT
4381 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4382 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4383 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4384 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4385 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4386 && (num_sign_bit_copies (f, GET_MODE (f))
4387 > (GET_MODE_BITSIZE (mode)
4388 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4389 {
4390 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4391 extend_op = SIGN_EXTEND;
4392 m = GET_MODE (XEXP (t, 0));
1a26b032 4393 }
8079805d
RK		 4394 else if (GET_CODE (t) == SIGN_EXTEND
4395 && (GET_CODE (XEXP (t, 0)) == PLUS
4396 || GET_CODE (XEXP (t, 0)) == IOR
4397 || GET_CODE (XEXP (t, 0)) == XOR)
4398 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4399 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4400 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4401 && (num_sign_bit_copies (f, GET_MODE (f))
4402 > (GET_MODE_BITSIZE (mode)
4403 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4404 {
4405 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4406 extend_op = SIGN_EXTEND;
4407 m = GET_MODE (XEXP (t, 0));
4408 }
4409 else if (GET_CODE (t) == ZERO_EXTEND
4410 && (GET_CODE (XEXP (t, 0)) == PLUS
4411 || GET_CODE (XEXP (t, 0)) == MINUS
4412 || GET_CODE (XEXP (t, 0)) == IOR
4413 || GET_CODE (XEXP (t, 0)) == XOR
4414 || GET_CODE (XEXP (t, 0)) == ASHIFT
4415 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4416 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4417 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4418 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4419 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4420 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4421 && ((nonzero_bits (f, GET_MODE (f))
4422 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4423 == 0))
4424 {
4425 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4426 extend_op = ZERO_EXTEND;
4427 m = GET_MODE (XEXP (t, 0));
4428 }
4429 else if (GET_CODE (t) == ZERO_EXTEND
4430 && (GET_CODE (XEXP (t, 0)) == PLUS
4431 || GET_CODE (XEXP (t, 0)) == IOR
4432 || GET_CODE (XEXP (t, 0)) == XOR)
4433 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4434 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4435 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4436 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4437 && ((nonzero_bits (f, GET_MODE (f))
4438 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4439 == 0))
4440 {
4441 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4442 extend_op = ZERO_EXTEND;
4443 m = GET_MODE (XEXP (t, 0));
4444 }
4445
4446 if (z)
4447 {
4448 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4449 pc_rtx, pc_rtx, 0, 0);
4450 temp = gen_binary (MULT, m, temp,
4451 gen_binary (MULT, m, c1, const_true_rtx));
4452 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4453 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4454
4455 if (extend_op != NIL)
0c1c8ea6 4456 temp = gen_unary (extend_op, mode, m, temp);
8079805d
RK		 4457
4458 return temp;
4459 }
4460 }
224eeff2 4461
8079805d
RK		 4462 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4463 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4464 negation of a single bit, we can convert this operation to a shift. We
4465 can actually do this more generally, but it doesn't seem worth it. */
4466
4467 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4468 && false == const0_rtx && GET_CODE (true) == CONST_INT
4469 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4470 && (i = exact_log2 (INTVAL (true))) >= 0)
4471 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4472 == GET_MODE_BITSIZE (mode))
4473 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4474 return
4475 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4476 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
230d793d 4477
8079805d
RK		 4478 return x;
4479}
4480\f
4481/* Simplify X, a SET expression. Return the new expression. */
230d793d 4482
8079805d
RK		 4483static rtx
4484simplify_set (x)
4485 rtx x;
4486{
4487 rtx src = SET_SRC (x);
4488 rtx dest = SET_DEST (x);
4489 enum machine_mode mode
4490 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4491 rtx other_insn;
4492 rtx *cc_use;
4493
4494 /* (set (pc) (return)) gets written as (return). */
4495 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4496 return src;
230d793d 4497
87e3e0c1
RK		 4498 /* Now that we know for sure which bits of SRC we are using, see if we can
4499 simplify the expression for the object knowing that we only need the
4500 low-order bits. */
4501
4502 if (GET_MODE_CLASS (mode) == MODE_INT)
4503 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4504
8079805d
RK		 4505 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4506 the comparison result and try to simplify it unless we already have used
4507 undobuf.other_insn. */
4508 if ((GET_CODE (src) == COMPARE
230d793d 4509#ifdef HAVE_cc0
8079805d 4510 || dest == cc0_rtx
230d793d 4511#endif
8079805d
RK		 4512 )
4513 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4514 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4515 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
c0d3ac4d 4516 && rtx_equal_p (XEXP (*cc_use, 0), dest))
8079805d
RK		 4517 {
4518 enum rtx_code old_code = GET_CODE (*cc_use);
4519 enum rtx_code new_code;
4520 rtx op0, op1;
4521 int other_changed = 0;
4522 enum machine_mode compare_mode = GET_MODE (dest);
4523
4524 if (GET_CODE (src) == COMPARE)
4525 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4526 else
4527 op0 = src, op1 = const0_rtx;
230d793d 4528
8079805d
RK		 4529 /* Simplify our comparison, if possible. */
4530 new_code = simplify_comparison (old_code, &op0, &op1);
230d793d 4531
c141a106 4532#ifdef EXTRA_CC_MODES
8079805d
RK		 4533 /* If this machine has CC modes other than CCmode, check to see if we
4534 need to use a different CC mode here. */
4535 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
c141a106 4536#endif /* EXTRA_CC_MODES */
230d793d 4537
c141a106 4538#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
8079805d
RK		 4539 /* If the mode changed, we have to change SET_DEST, the mode in the
4540 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4541 a hard register, just build new versions with the proper mode. If it
4542 is a pseudo, we lose unless it is only time we set the pseudo, in
4543 which case we can safely change its mode. */
4544 if (compare_mode != GET_MODE (dest))
4545 {
4546 int regno = REGNO (dest);
38a448ca 4547 rtx new_dest = gen_rtx_REG (compare_mode, regno);
8079805d
RK		 4548
4549 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 4550 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
230d793d 4551 {
8079805d
RK		 4552 if (regno >= FIRST_PSEUDO_REGISTER)
4553 SUBST (regno_reg_rtx[regno], new_dest);
230d793d 4554
8079805d
RK		 4555 SUBST (SET_DEST (x), new_dest);
4556 SUBST (XEXP (*cc_use, 0), new_dest);
4557 other_changed = 1;
230d793d 4558
8079805d 4559 dest = new_dest;
230d793d 4560 }
8079805d 4561 }
230d793d
RS		 4562#endif
4563
8079805d
RK		 4564 /* If the code changed, we have to build a new comparison in
4565 undobuf.other_insn. */
4566 if (new_code != old_code)
4567 {
4568 unsigned HOST_WIDE_INT mask;
4569
4570 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4571 dest, const0_rtx));
4572
4573 /* If the only change we made was to change an EQ into an NE or
4574 vice versa, OP0 has only one bit that might be nonzero, and OP1
4575 is zero, check if changing the user of the condition code will
4576 produce a valid insn. If it won't, we can keep the original code
4577 in that insn by surrounding our operation with an XOR. */
4578
4579 if (((old_code == NE && new_code == EQ)
4580 || (old_code == EQ && new_code == NE))
4581 && ! other_changed && op1 == const0_rtx
4582 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4583 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
230d793d 4584 {
8079805d 4585 rtx pat = PATTERN (other_insn), note = 0;
a29ca9db 4586 int scratches;
230d793d 4587
a29ca9db 4588 if ((recog_for_combine (&pat, other_insn, &note, &scratches) < 0
8079805d
RK		 4589 && ! check_asm_operands (pat)))
4590 {
4591 PUT_CODE (*cc_use, old_code);
4592 other_insn = 0;
230d793d 4593
8079805d 4594 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
230d793d 4595 }
230d793d
RS		 4596 }
4597
8079805d
RK		 4598 other_changed = 1;
4599 }
4600
4601 if (other_changed)
4602 undobuf.other_insn = other_insn;
230d793d
RS		 4603
4604#ifdef HAVE_cc0
8079805d
RK		 4605 /* If we are now comparing against zero, change our source if
4606 needed. If we do not use cc0, we always have a COMPARE. */
4607 if (op1 == const0_rtx && dest == cc0_rtx)
4608 {
4609 SUBST (SET_SRC (x), op0);
4610 src = op0;
4611 }
4612 else
230d793d
RS		 4613#endif
4614
8079805d
RK		 4615 /* Otherwise, if we didn't previously have a COMPARE in the
4616 correct mode, we need one. */
4617 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4618 {
4619 SUBST (SET_SRC (x),
4620 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4621 src = SET_SRC (x);
230d793d
RS		 4622 }
4623 else
4624 {
8079805d
RK		 4625 /* Otherwise, update the COMPARE if needed. */
4626 SUBST (XEXP (src, 0), op0);
4627 SUBST (XEXP (src, 1), op1);
230d793d 4628 }
8079805d
RK		 4629 }
4630 else
4631 {
4632 /* Get SET_SRC in a form where we have placed back any
4633 compound expressions. Then do the checks below. */
4634 src = make_compound_operation (src, SET);
4635 SUBST (SET_SRC (x), src);
4636 }
230d793d 4637
8079805d
RK		 4638 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4639 and X being a REG or (subreg (reg)), we may be able to convert this to
4640 (set (subreg:m2 x) (op)).
df62f951 4641
8079805d
RK		 4642 We can always do this if M1 is narrower than M2 because that means that
4643 we only care about the low bits of the result.
df62f951 4644
8079805d
RK		 4645 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4646 perform a narrower operation that requested since the high-order bits will
4647 be undefined. On machine where it is defined, this transformation is safe
4648 as long as M1 and M2 have the same number of words. */
df62f951 4649
8079805d
RK		 4650 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4651 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4652 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4653 / UNITS_PER_WORD)
4654 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4655 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
8baf60bb 4656#ifndef WORD_REGISTER_OPERATIONS
8079805d
RK		 4657 && (GET_MODE_SIZE (GET_MODE (src))
4658 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
df62f951 4659#endif
f507a070
RK		 4660#ifdef CLASS_CANNOT_CHANGE_SIZE
4661 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4662 && (TEST_HARD_REG_BIT
4663 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4664 REGNO (dest)))
4665 && (GET_MODE_SIZE (GET_MODE (src))
4666 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4667#endif
8079805d
RK		 4668 && (GET_CODE (dest) == REG
4669 || (GET_CODE (dest) == SUBREG
4670 && GET_CODE (SUBREG_REG (dest)) == REG)))
4671 {
4672 SUBST (SET_DEST (x),
4673 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4674 dest));
4675 SUBST (SET_SRC (x), SUBREG_REG (src));
4676
4677 src = SET_SRC (x), dest = SET_DEST (x);
4678 }
df62f951 4679
8baf60bb 4680#ifdef LOAD_EXTEND_OP
8079805d
RK		 4681 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4682 would require a paradoxical subreg. Replace the subreg with a
0f41302f 4683 zero_extend to avoid the reload that would otherwise be required. */
8079805d
RK		 4684
4685 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4686 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4687 && SUBREG_WORD (src) == 0
4688 && (GET_MODE_SIZE (GET_MODE (src))
4689 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4690 && GET_CODE (SUBREG_REG (src)) == MEM)
4691 {
4692 SUBST (SET_SRC (x),
4693 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4694 GET_MODE (src), XEXP (src, 0)));
4695
4696 src = SET_SRC (x);
4697 }
230d793d
RS		 4698#endif
4699
8079805d
RK		 4700 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4701 are comparing an item known to be 0 or -1 against 0, use a logical
4702 operation instead. Check for one of the arms being an IOR of the other
4703 arm with some value. We compute three terms to be IOR'ed together. In
4704 practice, at most two will be nonzero. Then we do the IOR's. */
4705
4706 if (GET_CODE (dest) != PC
4707 && GET_CODE (src) == IF_THEN_ELSE
36b8d792 4708 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
8079805d
RK		 4709 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4710 && XEXP (XEXP (src, 0), 1) == const0_rtx
6dd49058 4711 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
ea414472
DE		 4712#ifdef HAVE_conditional_move
4713 && ! can_conditionally_move_p (GET_MODE (src))
4714#endif
8079805d
RK		 4715 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4716 GET_MODE (XEXP (XEXP (src, 0), 0)))
4717 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4718 && ! side_effects_p (src))
4719 {
4720 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4721 ? XEXP (src, 1) : XEXP (src, 2));
4722 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4723 ? XEXP (src, 2) : XEXP (src, 1));
4724 rtx term1 = const0_rtx, term2, term3;
4725
4726 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4727 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4728 else if (GET_CODE (true) == IOR
4729 && rtx_equal_p (XEXP (true, 1), false))
4730 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4731 else if (GET_CODE (false) == IOR
4732 && rtx_equal_p (XEXP (false, 0), true))
4733 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4734 else if (GET_CODE (false) == IOR
4735 && rtx_equal_p (XEXP (false, 1), true))
4736 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4737
4738 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4739 term3 = gen_binary (AND, GET_MODE (src),
0c1c8ea6 4740 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
8079805d
RK		 4741 XEXP (XEXP (src, 0), 0)),
4742 false);
4743
4744 SUBST (SET_SRC (x),
4745 gen_binary (IOR, GET_MODE (src),
4746 gen_binary (IOR, GET_MODE (src), term1, term2),
4747 term3));
4748
4749 src = SET_SRC (x);
4750 }
230d793d 4751
246e00f2
RK		 4752 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4753 whole thing fail. */
4754 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4755 return src;
4756 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4757 return dest;
4758 else
4759 /* Convert this into a field assignment operation, if possible. */
4760 return make_field_assignment (x);
8079805d
RK		 4761}
4762\f
4763/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4764 result. LAST is nonzero if this is the last retry. */
4765
4766static rtx
4767simplify_logical (x, last)
4768 rtx x;
4769 int last;
4770{
4771 enum machine_mode mode = GET_MODE (x);
4772 rtx op0 = XEXP (x, 0);
4773 rtx op1 = XEXP (x, 1);
4774
4775 switch (GET_CODE (x))
4776 {
230d793d 4777 case AND:
8079805d
RK		 4778 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4779 insn (and may simplify more). */
4780 if (GET_CODE (op0) == XOR
4781 && rtx_equal_p (XEXP (op0, 0), op1)
4782 && ! side_effects_p (op1))
0c1c8ea6
RK		 4783 x = gen_binary (AND, mode,
4784 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
8079805d
RK		 4785
4786 if (GET_CODE (op0) == XOR
4787 && rtx_equal_p (XEXP (op0, 1), op1)
4788 && ! side_effects_p (op1))
0c1c8ea6
RK		 4789 x = gen_binary (AND, mode,
4790 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
8079805d
RK		 4791
4792 /* Similarly for (~ (A ^ B)) & A. */
4793 if (GET_CODE (op0) == NOT
4794 && GET_CODE (XEXP (op0, 0)) == XOR
4795 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4796 && ! side_effects_p (op1))
4797 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4798
4799 if (GET_CODE (op0) == NOT
4800 && GET_CODE (XEXP (op0, 0)) == XOR
4801 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4802 && ! side_effects_p (op1))
4803 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4804
4805 if (GET_CODE (op1) == CONST_INT)
230d793d 4806 {
8079805d 4807 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
230d793d
RS		 4808
4809 /* If we have (ior (and (X C1) C2)) and the next restart would be
4810 the last, simplify this by making C1 as small as possible
0f41302f 4811 and then exit. */
8079805d
RK		 4812 if (last
4813 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4814 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4815 && GET_CODE (op1) == CONST_INT)
4816 return gen_binary (IOR, mode,
4817 gen_binary (AND, mode, XEXP (op0, 0),
4818 GEN_INT (INTVAL (XEXP (op0, 1))
4819 & ~ INTVAL (op1))), op1);
230d793d
RS		 4820
4821 if (GET_CODE (x) != AND)
8079805d 4822 return x;
0e32506c
RK		 4823
4824 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4825 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4826 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
230d793d
RS		 4827 }
4828
4829 /* Convert (A | B) & A to A. */
8079805d
RK		 4830 if (GET_CODE (op0) == IOR
4831 && (rtx_equal_p (XEXP (op0, 0), op1)
4832 || rtx_equal_p (XEXP (op0, 1), op1))
4833 && ! side_effects_p (XEXP (op0, 0))
4834 && ! side_effects_p (XEXP (op0, 1)))
4835 return op1;
230d793d 4836
d0ab8cd3 4837 /* In the following group of tests (and those in case IOR below),
230d793d
RS		 4838 we start with some combination of logical operations and apply
4839 the distributive law followed by the inverse distributive law.
4840 Most of the time, this results in no change. However, if some of
4841 the operands are the same or inverses of each other, simplifications
4842 will result.
4843
4844 For example, (and (ior A B) (not B)) can occur as the result of
4845 expanding a bit field assignment. When we apply the distributive
4846 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8079805d 4847 which then simplifies to (and (A (not B))).
230d793d 4848
8079805d 4849 If we have (and (ior A B) C), apply the distributive law and then
230d793d
RS		 4850 the inverse distributive law to see if things simplify. */
4851
8079805d 4852 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
230d793d
RS		 4853 {
4854 x = apply_distributive_law
8079805d
RK		 4855 (gen_binary (GET_CODE (op0), mode,
4856 gen_binary (AND, mode, XEXP (op0, 0), op1),
4857 gen_binary (AND, mode, XEXP (op0, 1), op1)));
230d793d 4858 if (GET_CODE (x) != AND)
8079805d 4859 return x;
230d793d
RS		 4860 }
4861
8079805d
RK		 4862 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4863 return apply_distributive_law
4864 (gen_binary (GET_CODE (op1), mode,
4865 gen_binary (AND, mode, XEXP (op1, 0), op0),
4866 gen_binary (AND, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4867
4868 /* Similarly, taking advantage of the fact that
4869 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4870
8079805d
RK		 4871 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4872 return apply_distributive_law
4873 (gen_binary (XOR, mode,
4874 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4875 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
230d793d 4876
8079805d
RK		 4877 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4878 return apply_distributive_law
4879 (gen_binary (XOR, mode,
4880 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4881 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
230d793d
RS		 4882 break;
4883
4884 case IOR:
951553af 4885 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
8079805d 4886 if (GET_CODE (op1) == CONST_INT
ac49a949 4887 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8079805d
RK		 4888 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4889 return op1;
d0ab8cd3 4890
230d793d 4891 /* Convert (A & B) | A to A. */
8079805d
RK		 4892 if (GET_CODE (op0) == AND
4893 && (rtx_equal_p (XEXP (op0, 0), op1)
4894 || rtx_equal_p (XEXP (op0, 1), op1))
4895 && ! side_effects_p (XEXP (op0, 0))
4896 && ! side_effects_p (XEXP (op0, 1)))
4897 return op1;
230d793d
RS		 4898
4899 /* If we have (ior (and A B) C), apply the distributive law and then
4900 the inverse distributive law to see if things simplify. */
4901
8079805d 4902 if (GET_CODE (op0) == AND)
230d793d
RS		 4903 {
4904 x = apply_distributive_law
4905 (gen_binary (AND, mode,
8079805d
RK		 4906 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4907 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
230d793d
RS		 4908
4909 if (GET_CODE (x) != IOR)
8079805d 4910 return x;
230d793d
RS		 4911 }
4912
8079805d 4913 if (GET_CODE (op1) == AND)
230d793d
RS		 4914 {
4915 x = apply_distributive_law
4916 (gen_binary (AND, mode,
8079805d
RK		 4917 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4918 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4919
4920 if (GET_CODE (x) != IOR)
8079805d 4921 return x;
230d793d
RS		 4922 }
4923
4924 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4925 mode size to (rotate A CX). */
4926
8079805d
RK		 4927 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4928 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4929 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4930 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4931 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4932 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
230d793d 4933 == GET_MODE_BITSIZE (mode)))
38a448ca
RH		 4934 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
4935 (GET_CODE (op0) == ASHIFT
4936 ? XEXP (op0, 1) : XEXP (op1, 1)));
230d793d 4937
71923da7
RK		 4938 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4939 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4940 does not affect any of the bits in OP1, it can really be done
4941 as a PLUS and we can associate. We do this by seeing if OP1
4942 can be safely shifted left C bits. */
4943 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4944 && GET_CODE (XEXP (op0, 0)) == PLUS
4945 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4946 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4947 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4948 {
4949 int count = INTVAL (XEXP (op0, 1));
4950 HOST_WIDE_INT mask = INTVAL (op1) << count;
4951
4952 if (mask >> count == INTVAL (op1)
4953 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4954 {
4955 SUBST (XEXP (XEXP (op0, 0), 1),
4956 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4957 return op0;
4958 }
4959 }
230d793d
RS		 4960 break;
4961
4962 case XOR:
4963 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4964 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4965 (NOT y). */
4966 {
4967 int num_negated = 0;
230d793d 4968
8079805d
RK		 4969 if (GET_CODE (op0) == NOT)
4970 num_negated++, op0 = XEXP (op0, 0);
4971 if (GET_CODE (op1) == NOT)
4972 num_negated++, op1 = XEXP (op1, 0);
230d793d
RS		 4973
4974 if (num_negated == 2)
4975 {
8079805d
RK		 4976 SUBST (XEXP (x, 0), op0);
4977 SUBST (XEXP (x, 1), op1);
230d793d
RS		 4978 }
4979 else if (num_negated == 1)
0c1c8ea6 4980 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
230d793d
RS		 4981 }
4982
4983 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4984 correspond to a machine insn or result in further simplifications
4985 if B is a constant. */
4986
8079805d
RK		 4987 if (GET_CODE (op0) == AND
4988 && rtx_equal_p (XEXP (op0, 1), op1)
4989 && ! side_effects_p (op1))
0c1c8ea6
RK		 4990 return gen_binary (AND, mode,
4991 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
8079805d 4992 op1);
230d793d 4993
8079805d
RK		 4994 else if (GET_CODE (op0) == AND
4995 && rtx_equal_p (XEXP (op0, 0), op1)
4996 && ! side_effects_p (op1))
0c1c8ea6
RK		 4997 return gen_binary (AND, mode,
4998 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
8079805d 4999 op1);
230d793d 5000
230d793d 5001 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
0802d516
RK		 5002 comparison if STORE_FLAG_VALUE is 1. */
5003 if (STORE_FLAG_VALUE == 1
5004 && op1 == const1_rtx
8079805d
RK		 5005 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5006 && reversible_comparison_p (op0))
5007 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5008 mode, XEXP (op0, 0), XEXP (op0, 1));
500c518b
RK		 5009
5010 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5011 is (lt foo (const_int 0)), so we can perform the above
0802d516 5012 simplification if STORE_FLAG_VALUE is 1. */
500c518b 5013
0802d516
RK		 5014 if (STORE_FLAG_VALUE == 1
5015 && op1 == const1_rtx
8079805d
RK		 5016 && GET_CODE (op0) == LSHIFTRT
5017 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5018 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5019 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
230d793d
RS		 5020
5021 /* (xor (comparison foo bar) (const_int sign-bit))
5022 when STORE_FLAG_VALUE is the sign bit. */
5f4f0e22 5023 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 5024 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5f4f0e22 5025 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
8079805d
RK		 5026 && op1 == const_true_rtx
5027 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5028 && reversible_comparison_p (op0))
5029 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5030 mode, XEXP (op0, 0), XEXP (op0, 1));
230d793d 5031 break;
e9a25f70
JL		 5032
5033 default:
5034 abort ();
230d793d
RS		 5035 }
5036
5037 return x;
5038}
5039\f
5040/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5041 operations" because they can be replaced with two more basic operations.
5042 ZERO_EXTEND is also considered "compound" because it can be replaced with
5043 an AND operation, which is simpler, though only one operation.
5044
5045 The function expand_compound_operation is called with an rtx expression
5046 and will convert it to the appropriate shifts and AND operations,
5047 simplifying at each stage.
5048
5049 The function make_compound_operation is called to convert an expression
5050 consisting of shifts and ANDs into the equivalent compound expression.
5051 It is the inverse of this function, loosely speaking. */
5052
5053static rtx
5054expand_compound_operation (x)
5055 rtx x;
5056{
5057 int pos = 0, len;
5058 int unsignedp = 0;
5059 int modewidth;
5060 rtx tem;
5061
5062 switch (GET_CODE (x))
5063 {
5064 case ZERO_EXTEND:
5065 unsignedp = 1;
5066 case SIGN_EXTEND:
75473182
RS		 5067 /* We can't necessarily use a const_int for a multiword mode;
5068 it depends on implicitly extending the value.
5069 Since we don't know the right way to extend it,
5070 we can't tell whether the implicit way is right.
5071
5072 Even for a mode that is no wider than a const_int,
5073 we can't win, because we need to sign extend one of its bits through
5074 the rest of it, and we don't know which bit. */
230d793d 5075 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
75473182 5076 return x;
230d793d 5077
8079805d
RK		 5078 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5079 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5080 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5081 reloaded. If not for that, MEM's would very rarely be safe.
5082
5083 Reject MODEs bigger than a word, because we might not be able
5084 to reference a two-register group starting with an arbitrary register
5085 (and currently gen_lowpart might crash for a SUBREG). */
5086
5087 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
230d793d
RS		 5088 return x;
5089
5090 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5091 /* If the inner object has VOIDmode (the only way this can happen
5092 is if it is a ASM_OPERANDS), we can't do anything since we don't
5093 know how much masking to do. */
5094 if (len == 0)
5095 return x;
5096
5097 break;
5098
5099 case ZERO_EXTRACT:
5100 unsignedp = 1;
5101 case SIGN_EXTRACT:
5102 /* If the operand is a CLOBBER, just return it. */
5103 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5104 return XEXP (x, 0);
5105
5106 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5107 || GET_CODE (XEXP (x, 2)) != CONST_INT
5108 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5109 return x;
5110
5111 len = INTVAL (XEXP (x, 1));
5112 pos = INTVAL (XEXP (x, 2));
5113
5114 /* If this goes outside the object being extracted, replace the object
5115 with a (use (mem ...)) construct that only combine understands
5116 and is used only for this purpose. */
5117 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
38a448ca 5118 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
230d793d 5119
f76b9db2
ILT		 5120 if (BITS_BIG_ENDIAN)
5121 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5122
230d793d
RS		 5123 break;
5124
5125 default:
5126 return x;
5127 }
5128
0f13a422
ILT		 5129 /* We can optimize some special cases of ZERO_EXTEND. */
5130 if (GET_CODE (x) == ZERO_EXTEND)
5131 {
5132 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5133 know that the last value didn't have any inappropriate bits
5134 set. */
5135 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5136 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5137 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5138 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5139 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5140 return XEXP (XEXP (x, 0), 0);
5141
5142 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5143 if (GET_CODE (XEXP (x, 0)) == SUBREG
5144 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5145 && subreg_lowpart_p (XEXP (x, 0))
5146 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5147 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5148 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5149 return SUBREG_REG (XEXP (x, 0));
5150
5151 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5152 is a comparison and STORE_FLAG_VALUE permits. This is like
5153 the first case, but it works even when GET_MODE (x) is larger
5154 than HOST_WIDE_INT. */
5155 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5156 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5157 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5158 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5159 <= HOST_BITS_PER_WIDE_INT)
5160 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5161 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5162 return XEXP (XEXP (x, 0), 0);
5163
5164 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5165 if (GET_CODE (XEXP (x, 0)) == SUBREG
5166 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5167 && subreg_lowpart_p (XEXP (x, 0))
5168 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5169 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5170 <= HOST_BITS_PER_WIDE_INT)
5171 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5172 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5173 return SUBREG_REG (XEXP (x, 0));
5174
5175 /* If sign extension is cheaper than zero extension, then use it
5176 if we know that no extraneous bits are set, and that the high
5177 bit is not set. */
5178 if (flag_expensive_optimizations
5179 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5180 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5181 & ~ (((unsigned HOST_WIDE_INT)
5182 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5183 >> 1))
5184 == 0))
5185 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5186 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5187 <= HOST_BITS_PER_WIDE_INT)
5188 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5189 & ~ (((unsigned HOST_WIDE_INT)
5190 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5191 >> 1))
5192 == 0))))
5193 {
38a448ca 5194 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
0f13a422
ILT		 5195
5196 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5197 return expand_compound_operation (temp);
5198 }
5199 }
5200
230d793d
RS		 5201 /* If we reach here, we want to return a pair of shifts. The inner
5202 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5203 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5204 logical depending on the value of UNSIGNEDP.
5205
5206 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5207 converted into an AND of a shift.
5208
5209 We must check for the case where the left shift would have a negative
5210 count. This can happen in a case like (x >> 31) & 255 on machines
5211 that can't shift by a constant. On those machines, we would first
5212 combine the shift with the AND to produce a variable-position
5213 extraction. Then the constant of 31 would be substituted in to produce
5214 a such a position. */
5215
5216 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5217 if (modewidth >= pos - len)
5f4f0e22 5218 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
230d793d 5219 GET_MODE (x),
5f4f0e22
CH		 5220 simplify_shift_const (NULL_RTX, ASHIFT,
5221 GET_MODE (x),
230d793d
RS		 5222 XEXP (x, 0),
5223 modewidth - pos - len),
5224 modewidth - len);
5225
5f4f0e22
CH		 5226 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5227 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5228 simplify_shift_const (NULL_RTX, LSHIFTRT,
230d793d
RS		 5229 GET_MODE (x),
5230 XEXP (x, 0), pos),
5f4f0e22 5231 ((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5232 else
5233 /* Any other cases we can't handle. */
5234 return x;
5235
5236
5237 /* If we couldn't do this for some reason, return the original
5238 expression. */
5239 if (GET_CODE (tem) == CLOBBER)
5240 return x;
5241
5242 return tem;
5243}
5244\f
5245/* X is a SET which contains an assignment of one object into
5246 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5247 or certain SUBREGS). If possible, convert it into a series of
5248 logical operations.
5249
5250 We half-heartedly support variable positions, but do not at all
5251 support variable lengths. */
5252
5253static rtx
5254expand_field_assignment (x)
5255 rtx x;
5256{
5257 rtx inner;
0f41302f 5258 rtx pos; /* Always counts from low bit. */
230d793d
RS		 5259 int len;
5260 rtx mask;
5261 enum machine_mode compute_mode;
5262
5263 /* Loop until we find something we can't simplify. */
5264 while (1)
5265 {
5266 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5267 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5268 {
5269 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5270 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4d9cfc7b 5271 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
230d793d
RS		 5272 }
5273 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5274 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5275 {
5276 inner = XEXP (SET_DEST (x), 0);
5277 len = INTVAL (XEXP (SET_DEST (x), 1));
5278 pos = XEXP (SET_DEST (x), 2);
5279
5280 /* If the position is constant and spans the width of INNER,
5281 surround INNER with a USE to indicate this. */
5282 if (GET_CODE (pos) == CONST_INT
5283 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
38a448ca 5284 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
230d793d 5285
f76b9db2
ILT		 5286 if (BITS_BIG_ENDIAN)
5287 {
5288 if (GET_CODE (pos) == CONST_INT)
5289 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5290 - INTVAL (pos));
5291 else if (GET_CODE (pos) == MINUS
5292 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5293 && (INTVAL (XEXP (pos, 1))
5294 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5295 /* If position is ADJUST - X, new position is X. */
5296 pos = XEXP (pos, 0);
5297 else
5298 pos = gen_binary (MINUS, GET_MODE (pos),
5299 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5300 - len),
5301 pos);
5302 }
230d793d
RS		 5303 }
5304
5305 /* A SUBREG between two modes that occupy the same numbers of words
5306 can be done by moving the SUBREG to the source. */
5307 else if (GET_CODE (SET_DEST (x)) == SUBREG
5308 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5309 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5310 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5311 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5312 {
38a448ca
RH		 5313 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5314 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5315 SET_SRC (x)));
230d793d
RS		 5316 continue;
5317 }
5318 else
5319 break;
5320
5321 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5322 inner = SUBREG_REG (inner);
5323
5324 compute_mode = GET_MODE (inner);
5325
5326 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5f4f0e22
CH		 5327 if (len < HOST_BITS_PER_WIDE_INT)
5328 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5329 else
5330 break;
5331
5332 /* Now compute the equivalent expression. Make a copy of INNER
5333 for the SET_DEST in case it is a MEM into which we will substitute;
5334 we don't want shared RTL in that case. */
38a448ca
RH		 5335 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5336 gen_binary (IOR, compute_mode,
5337 gen_binary (AND, compute_mode,
5338 gen_unary (NOT, compute_mode,
5339 compute_mode,
5340 gen_binary (ASHIFT,
5341 compute_mode,
5342 mask, pos)),
5343 inner),
5344 gen_binary (ASHIFT, compute_mode,
5345 gen_binary (AND, compute_mode,
5346 gen_lowpart_for_combine
5347 (compute_mode,
5348 SET_SRC (x)),
5349 mask),
5350 pos)));
230d793d
RS		 5351 }
5352
5353 return x;
5354}
5355\f
8999a12e
RK		 5356/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5357 it is an RTX that represents a variable starting position; otherwise,
5358 POS is the (constant) starting bit position (counted from the LSB).
230d793d
RS		 5359
5360 INNER may be a USE. This will occur when we started with a bitfield
5361 that went outside the boundary of the object in memory, which is
5362 allowed on most machines. To isolate this case, we produce a USE
5363 whose mode is wide enough and surround the MEM with it. The only
5364 code that understands the USE is this routine. If it is not removed,
5365 it will cause the resulting insn not to match.
5366
5367 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5368 signed reference.
5369
5370 IN_DEST is non-zero if this is a reference in the destination of a
5371 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5372 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5373 be used.
5374
5375 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5376 ZERO_EXTRACT should be built even for bits starting at bit 0.
5377
76184def
DE		 5378 MODE is the desired mode of the result (if IN_DEST == 0).
5379
5380 The result is an RTX for the extraction or NULL_RTX if the target
5381 can't handle it. */
230d793d
RS		 5382
5383static rtx
5384make_extraction (mode, inner, pos, pos_rtx, len,
5385 unsignedp, in_dest, in_compare)
5386 enum machine_mode mode;
5387 rtx inner;
5388 int pos;
5389 rtx pos_rtx;
5390 int len;
5391 int unsignedp;
5392 int in_dest, in_compare;
5393{
94b4b17a
RS		 5394 /* This mode describes the size of the storage area
5395 to fetch the overall value from. Within that, we
5396 ignore the POS lowest bits, etc. */
230d793d
RS		 5397 enum machine_mode is_mode = GET_MODE (inner);
5398 enum machine_mode inner_mode;
d7cd794f
RK		 5399 enum machine_mode wanted_inner_mode = byte_mode;
5400 enum machine_mode wanted_inner_reg_mode = word_mode;
230d793d
RS		 5401 enum machine_mode pos_mode = word_mode;
5402 enum machine_mode extraction_mode = word_mode;
5403 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5404 int spans_byte = 0;
5405 rtx new = 0;
8999a12e 5406 rtx orig_pos_rtx = pos_rtx;
6139ff20 5407 int orig_pos;
230d793d
RS		 5408
5409 /* Get some information about INNER and get the innermost object. */
5410 if (GET_CODE (inner) == USE)
94b4b17a 5411 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
230d793d
RS		 5412 /* We don't need to adjust the position because we set up the USE
5413 to pretend that it was a full-word object. */
5414 spans_byte = 1, inner = XEXP (inner, 0);
5415 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
94b4b17a
RS		 5416 {
5417 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5418 consider just the QI as the memory to extract from.
5419 The subreg adds or removes high bits; its mode is
5420 irrelevant to the meaning of this extraction,
5421 since POS and LEN count from the lsb. */
5422 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5423 is_mode = GET_MODE (SUBREG_REG (inner));
5424 inner = SUBREG_REG (inner);
5425 }
230d793d
RS		 5426
5427 inner_mode = GET_MODE (inner);
5428
5429 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
8999a12e 5430 pos = INTVAL (pos_rtx), pos_rtx = 0;
230d793d
RS		 5431
5432 /* See if this can be done without an extraction. We never can if the
5433 width of the field is not the same as that of some integer mode. For
5434 registers, we can only avoid the extraction if the position is at the
5435 low-order bit and this is either not in the destination or we have the
5436 appropriate STRICT_LOW_PART operation available.
5437
5438 For MEM, we can avoid an extract if the field starts on an appropriate
5439 boundary and we can change the mode of the memory reference. However,
5440 we cannot directly access the MEM if we have a USE and the underlying
5441 MEM is not TMODE. This combination means that MEM was being used in a
5442 context where bits outside its mode were being referenced; that is only
5443 valid in bit-field insns. */
5444
5445 if (tmode != BLKmode
5446 && ! (spans_byte && inner_mode != tmode)
4d9cfc7b
RK		 5447 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5448 && GET_CODE (inner) != MEM
230d793d 5449 && (! in_dest
df62f951
RK		 5450 || (GET_CODE (inner) == REG
5451 && (movstrict_optab->handlers[(int) tmode].insn_code
5452 != CODE_FOR_nothing))))
8999a12e 5453 || (GET_CODE (inner) == MEM && pos_rtx == 0
dfbe1b2f
RK		 5454 && (pos
5455 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5456 : BITS_PER_UNIT)) == 0
230d793d
RS		 5457 /* We can't do this if we are widening INNER_MODE (it
5458 may not be aligned, for one thing). */
5459 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5460 && (inner_mode == tmode
5461 || (! mode_dependent_address_p (XEXP (inner, 0))
5462 && ! MEM_VOLATILE_P (inner))))))
5463 {
230d793d
RS		 5464 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5465 field. If the original and current mode are the same, we need not
5466 adjust the offset. Otherwise, we do if bytes big endian.
5467
4d9cfc7b
RK		 5468 If INNER is not a MEM, get a piece consisting of just the field
5469 of interest (in this case POS % BITS_PER_WORD must be 0). */
230d793d
RS		 5470
5471 if (GET_CODE (inner) == MEM)
5472 {
94b4b17a
RS		 5473 int offset;
5474 /* POS counts from lsb, but make OFFSET count in memory order. */
5475 if (BYTES_BIG_ENDIAN)
5476 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5477 else
5478 offset = pos / BITS_PER_UNIT;
230d793d 5479
38a448ca 5480 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5481 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5482 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5483 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5484 }
df62f951 5485 else if (GET_CODE (inner) == REG)
c0d3ac4d
RK		 5486 {
5487 /* We can't call gen_lowpart_for_combine here since we always want
5488 a SUBREG and it would sometimes return a new hard register. */
5489 if (tmode != inner_mode)
38a448ca
RH		 5490 new = gen_rtx_SUBREG (tmode, inner,
5491 (WORDS_BIG_ENDIAN
5492 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5493 ? (((GET_MODE_SIZE (inner_mode)
5494 - GET_MODE_SIZE (tmode))
5495 / UNITS_PER_WORD)
5496 - pos / BITS_PER_WORD)
5497 : pos / BITS_PER_WORD));
c0d3ac4d
RK		 5498 else
5499 new = inner;
5500 }
230d793d 5501 else
6139ff20
RK		 5502 new = force_to_mode (inner, tmode,
5503 len >= HOST_BITS_PER_WIDE_INT
5504 ? GET_MODE_MASK (tmode)
5505 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 5506 NULL_RTX, 0);
230d793d
RS		 5507
5508 /* If this extraction is going into the destination of a SET,
5509 make a STRICT_LOW_PART unless we made a MEM. */
5510
5511 if (in_dest)
5512 return (GET_CODE (new) == MEM ? new
77fa0940 5513 : (GET_CODE (new) != SUBREG
38a448ca 5514 ? gen_rtx_CLOBBER (tmode, const0_rtx)
77fa0940 5515 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
230d793d
RS		 5516
5517 /* Otherwise, sign- or zero-extend unless we already are in the
5518 proper mode. */
5519
5520 return (mode == tmode ? new
5521 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5522 mode, new));
5523 }
5524
cc471082
RS		 5525 /* Unless this is a COMPARE or we have a funny memory reference,
5526 don't do anything with zero-extending field extracts starting at
5527 the low-order bit since they are simple AND operations. */
8999a12e
RK		 5528 if (pos_rtx == 0 && pos == 0 && ! in_dest
5529 && ! in_compare && ! spans_byte && unsignedp)
230d793d
RS		 5530 return 0;
5531
e7373556
RK		 5532 /* Unless we are allowed to span bytes, reject this if we would be
5533 spanning bytes or if the position is not a constant and the length
5534 is not 1. In all other cases, we would only be going outside
5535 out object in cases when an original shift would have been
5536 undefined. */
5537 if (! spans_byte
5538 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5539 || (pos_rtx != 0 && len != 1)))
5540 return 0;
5541
d7cd794f 5542 /* Get the mode to use should INNER not be a MEM, the mode for the position,
230d793d
RS		 5543 and the mode for the result. */
5544#ifdef HAVE_insv
5545 if (in_dest)
5546 {
d7cd794f 5547 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
230d793d
RS		 5548 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5549 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5550 }
5551#endif
5552
5553#ifdef HAVE_extzv
5554 if (! in_dest && unsignedp)
5555 {
d7cd794f 5556 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
230d793d
RS		 5557 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5558 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5559 }
5560#endif
5561
5562#ifdef HAVE_extv
5563 if (! in_dest && ! unsignedp)
5564 {
d7cd794f 5565 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
230d793d
RS		 5566 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5567 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5568 }
5569#endif
5570
5571 /* Never narrow an object, since that might not be safe. */
5572
5573 if (mode != VOIDmode
5574 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5575 extraction_mode = mode;
5576
5577 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5578 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5579 pos_mode = GET_MODE (pos_rtx);
5580
d7cd794f
RK		 5581 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5582 if we have to change the mode of memory and cannot, the desired mode is
5583 EXTRACTION_MODE. */
5584 if (GET_CODE (inner) != MEM)
5585 wanted_inner_mode = wanted_inner_reg_mode;
5586 else if (inner_mode != wanted_inner_mode
5587 && (mode_dependent_address_p (XEXP (inner, 0))
5588 || MEM_VOLATILE_P (inner)))
5589 wanted_inner_mode = extraction_mode;
230d793d 5590
6139ff20
RK		 5591 orig_pos = pos;
5592
f76b9db2
ILT		 5593 if (BITS_BIG_ENDIAN)
5594 {
cf54c2cd
DE		 5595 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5596 BITS_BIG_ENDIAN style. If position is constant, compute new
5597 position. Otherwise, build subtraction.
5598 Note that POS is relative to the mode of the original argument.
5599 If it's a MEM we need to recompute POS relative to that.
5600 However, if we're extracting from (or inserting into) a register,
5601 we want to recompute POS relative to wanted_inner_mode. */
5602 int width = (GET_CODE (inner) == MEM
5603 ? GET_MODE_BITSIZE (is_mode)
5604 : GET_MODE_BITSIZE (wanted_inner_mode));
5605
f76b9db2 5606 if (pos_rtx == 0)
cf54c2cd 5607 pos = width - len - pos;
f76b9db2
ILT		 5608 else
5609 pos_rtx
5610 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
cf54c2cd
DE		 5611 GEN_INT (width - len), pos_rtx);
5612 /* POS may be less than 0 now, but we check for that below.
5613 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
f76b9db2 5614 }
230d793d
RS		 5615
5616 /* If INNER has a wider mode, make it smaller. If this is a constant
5617 extract, try to adjust the byte to point to the byte containing
5618 the value. */
d7cd794f
RK		 5619 if (wanted_inner_mode != VOIDmode
5620 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
230d793d 5621 && ((GET_CODE (inner) == MEM
d7cd794f 5622 && (inner_mode == wanted_inner_mode
230d793d
RS		 5623 || (! mode_dependent_address_p (XEXP (inner, 0))
5624 && ! MEM_VOLATILE_P (inner))))))
5625 {
5626 int offset = 0;
5627
5628 /* The computations below will be correct if the machine is big
5629 endian in both bits and bytes or little endian in bits and bytes.
5630 If it is mixed, we must adjust. */
5631
230d793d 5632 /* If bytes are big endian and we had a paradoxical SUBREG, we must
0f41302f 5633 adjust OFFSET to compensate. */
f76b9db2
ILT		 5634 if (BYTES_BIG_ENDIAN
5635 && ! spans_byte
230d793d
RS		 5636 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5637 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
230d793d
RS		 5638
5639 /* If this is a constant position, we can move to the desired byte. */
8999a12e 5640 if (pos_rtx == 0)
230d793d
RS		 5641 {
5642 offset += pos / BITS_PER_UNIT;
d7cd794f 5643 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
230d793d
RS		 5644 }
5645
f76b9db2
ILT		 5646 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5647 && ! spans_byte
d7cd794f 5648 && is_mode != wanted_inner_mode)
c6b3f1f2 5649 offset = (GET_MODE_SIZE (is_mode)
d7cd794f 5650 - GET_MODE_SIZE (wanted_inner_mode) - offset);
c6b3f1f2 5651
d7cd794f 5652 if (offset != 0 || inner_mode != wanted_inner_mode)
230d793d 5653 {
38a448ca
RH		 5654 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5655 plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5656 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5657 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5658 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5659 inner = newmem;
5660 }
5661 }
5662
9e74dc41
RK		 5663 /* If INNER is not memory, we can always get it into the proper mode. If we
5664 are changing its mode, POS must be a constant and smaller than the size
5665 of the new mode. */
230d793d 5666 else if (GET_CODE (inner) != MEM)
9e74dc41
RK		 5667 {
5668 if (GET_MODE (inner) != wanted_inner_mode
5669 && (pos_rtx != 0
5670 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5671 return 0;
5672
5673 inner = force_to_mode (inner, wanted_inner_mode,
5674 pos_rtx
5675 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5676 ? GET_MODE_MASK (wanted_inner_mode)
5677 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5678 NULL_RTX, 0);
5679 }
230d793d
RS		 5680
5681 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5682 have to zero extend. Otherwise, we can just use a SUBREG. */
8999a12e 5683 if (pos_rtx != 0
230d793d
RS		 5684 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5685 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
8999a12e 5686 else if (pos_rtx != 0
230d793d
RS		 5687 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5688 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5689
8999a12e
RK		 5690 /* Make POS_RTX unless we already have it and it is correct. If we don't
5691 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
0f41302f 5692 be a CONST_INT. */
8999a12e
RK		 5693 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5694 pos_rtx = orig_pos_rtx;
5695
5696 else if (pos_rtx == 0)
5f4f0e22 5697 pos_rtx = GEN_INT (pos);
230d793d
RS		 5698
5699 /* Make the required operation. See if we can use existing rtx. */
5700 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5f4f0e22 5701 extraction_mode, inner, GEN_INT (len), pos_rtx);
230d793d
RS		 5702 if (! in_dest)
5703 new = gen_lowpart_for_combine (mode, new);
5704
5705 return new;
5706}
5707\f
71923da7
RK		 5708/* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5709 with any other operations in X. Return X without that shift if so. */
5710
5711static rtx
5712extract_left_shift (x, count)
5713 rtx x;
5714 int count;
5715{
5716 enum rtx_code code = GET_CODE (x);
5717 enum machine_mode mode = GET_MODE (x);
5718 rtx tem;
5719
5720 switch (code)
5721 {
5722 case ASHIFT:
5723 /* This is the shift itself. If it is wide enough, we will return
5724 either the value being shifted if the shift count is equal to
5725 COUNT or a shift for the difference. */
5726 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5727 && INTVAL (XEXP (x, 1)) >= count)
5728 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5729 INTVAL (XEXP (x, 1)) - count);
5730 break;
5731
5732 case NEG: case NOT:
5733 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
0c1c8ea6 5734 return gen_unary (code, mode, mode, tem);
71923da7
RK		 5735
5736 break;
5737
5738 case PLUS: case IOR: case XOR: case AND:
5739 /* If we can safely shift this constant and we find the inner shift,
5740 make a new operation. */
5741 if (GET_CODE (XEXP (x,1)) == CONST_INT
5742 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5743 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5744 return gen_binary (code, mode, tem,
5745 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5746
5747 break;
e9a25f70
JL		 5748
5749 default:
5750 break;
71923da7
RK		 5751 }
5752
5753 return 0;
5754}
5755\f
230d793d
RS		 5756/* Look at the expression rooted at X. Look for expressions
5757 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5758 Form these expressions.
5759
5760 Return the new rtx, usually just X.
5761
5762 Also, for machines like the Vax that don't have logical shift insns,
5763 try to convert logical to arithmetic shift operations in cases where
5764 they are equivalent. This undoes the canonicalizations to logical
5765 shifts done elsewhere.
5766
5767 We try, as much as possible, to re-use rtl expressions to save memory.
5768
5769 IN_CODE says what kind of expression we are processing. Normally, it is
42495ca0
RK		 5770 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5771 being kludges), it is MEM. When processing the arguments of a comparison
230d793d
RS		 5772 or a COMPARE against zero, it is COMPARE. */
5773
5774static rtx
5775make_compound_operation (x, in_code)
5776 rtx x;
5777 enum rtx_code in_code;
5778{
5779 enum rtx_code code = GET_CODE (x);
5780 enum machine_mode mode = GET_MODE (x);
5781 int mode_width = GET_MODE_BITSIZE (mode);
71923da7 5782 rtx rhs, lhs;
230d793d 5783 enum rtx_code next_code;
f24ad0e4 5784 int i;
230d793d 5785 rtx new = 0;
280f58ba 5786 rtx tem;
230d793d
RS		 5787 char *fmt;
5788
5789 /* Select the code to be used in recursive calls. Once we are inside an
5790 address, we stay there. If we have a comparison, set to COMPARE,
5791 but once inside, go back to our default of SET. */
5792
42495ca0 5793 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
230d793d
RS		 5794 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5795 && XEXP (x, 1) == const0_rtx) ? COMPARE
5796 : in_code == COMPARE ? SET : in_code);
5797
5798 /* Process depending on the code of this operation. If NEW is set
5799 non-zero, it will be returned. */
5800
5801 switch (code)
5802 {
5803 case ASHIFT:
230d793d
RS		 5804 /* Convert shifts by constants into multiplications if inside
5805 an address. */
5806 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 5807 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
230d793d 5808 && INTVAL (XEXP (x, 1)) >= 0)
280f58ba
RK		 5809 {
5810 new = make_compound_operation (XEXP (x, 0), next_code);
5811 new = gen_rtx_combine (MULT, mode, new,
5812 GEN_INT ((HOST_WIDE_INT) 1
5813 << INTVAL (XEXP (x, 1))));
5814 }
230d793d
RS		 5815 break;
5816
5817 case AND:
5818 /* If the second operand is not a constant, we can't do anything
5819 with it. */
5820 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5821 break;
5822
5823 /* If the constant is a power of two minus one and the first operand
5824 is a logical right shift, make an extraction. */
5825 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5826 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5827 {
5828 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5829 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5830 0, in_code == COMPARE);
5831 }
dfbe1b2f 5832
230d793d
RS		 5833 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5834 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5835 && subreg_lowpart_p (XEXP (x, 0))
5836 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5837 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5838 {
5839 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5840 next_code);
2f99f437 5841 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
280f58ba
RK		 5842 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5843 0, in_code == COMPARE);
5844 }
45620ed4 5845 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
c2f9f64e
JW		 5846 else if ((GET_CODE (XEXP (x, 0)) == XOR
5847 || GET_CODE (XEXP (x, 0)) == IOR)
5848 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5849 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5850 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5851 {
5852 /* Apply the distributive law, and then try to make extractions. */
5853 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
38a448ca
RH		 5854 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5855 XEXP (x, 1)),
5856 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5857 XEXP (x, 1)));
c2f9f64e
JW		 5858 new = make_compound_operation (new, in_code);
5859 }
a7c99304
RK		 5860
5861 /* If we are have (and (rotate X C) M) and C is larger than the number
5862 of bits in M, this is an extraction. */
5863
5864 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5865 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5866 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5867 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
280f58ba
RK		 5868 {
5869 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5870 new = make_extraction (mode, new,
5871 (GET_MODE_BITSIZE (mode)
5872 - INTVAL (XEXP (XEXP (x, 0), 1))),
5873 NULL_RTX, i, 1, 0, in_code == COMPARE);
5874 }
a7c99304
RK		 5875
5876 /* On machines without logical shifts, if the operand of the AND is
230d793d
RS		 5877 a logical shift and our mask turns off all the propagated sign
5878 bits, we can replace the logical shift with an arithmetic shift. */
d0ab8cd3
RK		 5879 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5880 && (lshr_optab->handlers[(int) mode].insn_code
5881 == CODE_FOR_nothing)
230d793d
RS		 5882 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5883 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5884 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5f4f0e22
CH		 5885 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5886 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 5887 {
5f4f0e22 5888 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 5889
5890 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5891 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5892 SUBST (XEXP (x, 0),
280f58ba
RK		 5893 gen_rtx_combine (ASHIFTRT, mode,
5894 make_compound_operation (XEXP (XEXP (x, 0), 0),
5895 next_code),
230d793d
RS		 5896 XEXP (XEXP (x, 0), 1)));
5897 }
5898
5899 /* If the constant is one less than a power of two, this might be
5900 representable by an extraction even if no shift is present.
5901 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5902 we are in a COMPARE. */
5903 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5904 new = make_extraction (mode,
5905 make_compound_operation (XEXP (x, 0),
5906 next_code),
5907 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
230d793d
RS		 5908
5909 /* If we are in a comparison and this is an AND with a power of two,
5910 convert this into the appropriate bit extract. */
5911 else if (in_code == COMPARE
5912 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
280f58ba
RK		 5913 new = make_extraction (mode,
5914 make_compound_operation (XEXP (x, 0),
5915 next_code),
5916 i, NULL_RTX, 1, 1, 0, 1);
230d793d
RS		 5917
5918 break;
5919
5920 case LSHIFTRT:
5921 /* If the sign bit is known to be zero, replace this with an
5922 arithmetic shift. */
d0ab8cd3
RK		 5923 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5924 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5f4f0e22 5925 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 5926 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
230d793d 5927 {
280f58ba
RK		 5928 new = gen_rtx_combine (ASHIFTRT, mode,
5929 make_compound_operation (XEXP (x, 0),
5930 next_code),
5931 XEXP (x, 1));
230d793d
RS		 5932 break;
5933 }
5934
0f41302f 5935 /* ... fall through ... */
230d793d
RS		 5936
5937 case ASHIFTRT:
71923da7
RK		 5938 lhs = XEXP (x, 0);
5939 rhs = XEXP (x, 1);
5940
230d793d
RS		 5941 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5942 this is a SIGN_EXTRACT. */
71923da7
RK		 5943 if (GET_CODE (rhs) == CONST_INT
5944 && GET_CODE (lhs) == ASHIFT
5945 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5946 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
280f58ba 5947 {
71923da7 5948 new = make_compound_operation (XEXP (lhs, 0), next_code);
280f58ba 5949 new = make_extraction (mode, new,
71923da7
RK		 5950 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5951 NULL_RTX, mode_width - INTVAL (rhs),
d0ab8cd3
RK		 5952 code == LSHIFTRT, 0, in_code == COMPARE);
5953 }
5954
71923da7
RK		 5955 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5956 If so, try to merge the shifts into a SIGN_EXTEND. We could
5957 also do this for some cases of SIGN_EXTRACT, but it doesn't
5958 seem worth the effort; the case checked for occurs on Alpha. */
5959
5960 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5961 && ! (GET_CODE (lhs) == SUBREG
5962 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5963 && GET_CODE (rhs) == CONST_INT
5964 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5965 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5966 new = make_extraction (mode, make_compound_operation (new, next_code),
5967 0, NULL_RTX, mode_width - INTVAL (rhs),
5968 code == LSHIFTRT, 0, in_code == COMPARE);
5969
230d793d 5970 break;
280f58ba
RK		 5971
5972 case SUBREG:
5973 /* Call ourselves recursively on the inner expression. If we are
5974 narrowing the object and it has a different RTL code from
5975 what it originally did, do this SUBREG as a force_to_mode. */
5976
0a5cbff6 5977 tem = make_compound_operation (SUBREG_REG (x), in_code);
280f58ba
RK		 5978 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5979 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5980 && subreg_lowpart_p (x))
0a5cbff6
RK		 5981 {
5982 rtx newer = force_to_mode (tem, mode,
e3d616e3 5983 GET_MODE_MASK (mode), NULL_RTX, 0);
0a5cbff6
RK		 5984
5985 /* If we have something other than a SUBREG, we might have
5986 done an expansion, so rerun outselves. */
5987 if (GET_CODE (newer) != SUBREG)
5988 newer = make_compound_operation (newer, in_code);
5989
5990 return newer;
5991 }
e9a25f70
JL		 5992 break;
5993
5994 default:
5995 break;
230d793d
RS		 5996 }
5997
5998 if (new)
5999 {
df62f951 6000 x = gen_lowpart_for_combine (mode, new);
230d793d
RS		 6001 code = GET_CODE (x);
6002 }
6003
6004 /* Now recursively process each operand of this operation. */
6005 fmt = GET_RTX_FORMAT (code);
6006 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6007 if (fmt[i] == 'e')
6008 {
6009 new = make_compound_operation (XEXP (x, i), next_code);
6010 SUBST (XEXP (x, i), new);
6011 }
6012
6013 return x;
6014}
6015\f
6016/* Given M see if it is a value that would select a field of bits
6017 within an item, but not the entire word. Return -1 if not.
6018 Otherwise, return the starting position of the field, where 0 is the
6019 low-order bit.
6020
6021 *PLEN is set to the length of the field. */
6022
6023static int
6024get_pos_from_mask (m, plen)
5f4f0e22 6025 unsigned HOST_WIDE_INT m;
230d793d
RS		 6026 int *plen;
6027{
6028 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6029 int pos = exact_log2 (m & - m);
6030
6031 if (pos < 0)
6032 return -1;
6033
6034 /* Now shift off the low-order zero bits and see if we have a power of
6035 two minus 1. */
6036 *plen = exact_log2 ((m >> pos) + 1);
6037
6038 if (*plen <= 0)
6039 return -1;
6040
6041 return pos;
6042}
6043\f
6139ff20
RK		 6044/* See if X can be simplified knowing that we will only refer to it in
6045 MODE and will only refer to those bits that are nonzero in MASK.
6046 If other bits are being computed or if masking operations are done
6047 that select a superset of the bits in MASK, they can sometimes be
6048 ignored.
6049
6050 Return a possibly simplified expression, but always convert X to
6051 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
dfbe1b2f
RK		 6052
6053 Also, if REG is non-zero and X is a register equal in value to REG,
e3d616e3
RK		 6054 replace X with REG.
6055
6056 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6057 are all off in X. This is used when X will be complemented, by either
180b8e4b 6058 NOT, NEG, or XOR. */
dfbe1b2f
RK		 6059
6060static rtx
e3d616e3 6061force_to_mode (x, mode, mask, reg, just_select)
dfbe1b2f
RK		 6062 rtx x;
6063 enum machine_mode mode;
6139ff20 6064 unsigned HOST_WIDE_INT mask;
dfbe1b2f 6065 rtx reg;
e3d616e3 6066 int just_select;
dfbe1b2f
RK		 6067{
6068 enum rtx_code code = GET_CODE (x);
180b8e4b 6069 int next_select = just_select || code == XOR || code == NOT || code == NEG;
ef026f91
RS		 6070 enum machine_mode op_mode;
6071 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6139ff20
RK		 6072 rtx op0, op1, temp;
6073
132d2040
RK		 6074 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6075 code below will do the wrong thing since the mode of such an
be3d27d6
CI		 6076 expression is VOIDmode.
6077
6078 Also do nothing if X is a CLOBBER; this can happen if X was
6079 the return value from a call to gen_lowpart_for_combine. */
6080 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
246e00f2
RK		 6081 return x;
6082
6139ff20
RK		 6083 /* We want to perform the operation is its present mode unless we know
6084 that the operation is valid in MODE, in which case we do the operation
6085 in MODE. */
1c75dfa4
RK		 6086 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6087 && code_to_optab[(int) code] != 0
ef026f91
RS		 6088 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6089 != CODE_FOR_nothing))
6090 ? mode : GET_MODE (x));
e3d616e3 6091
aa988991
RS		 6092 /* It is not valid to do a right-shift in a narrower mode
6093 than the one it came in with. */
6094 if ((code == LSHIFTRT || code == ASHIFTRT)
6095 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6096 op_mode = GET_MODE (x);
ef026f91
RS		 6097
6098 /* Truncate MASK to fit OP_MODE. */
6099 if (op_mode)
6100 mask &= GET_MODE_MASK (op_mode);
6139ff20
RK		 6101
6102 /* When we have an arithmetic operation, or a shift whose count we
6103 do not know, we need to assume that all bit the up to the highest-order
6104 bit in MASK will be needed. This is how we form such a mask. */
ef026f91
RS		 6105 if (op_mode)
6106 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6107 ? GET_MODE_MASK (op_mode)
6108 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6109 else
6110 fuller_mask = ~ (HOST_WIDE_INT) 0;
6111
6112 /* Determine what bits of X are guaranteed to be (non)zero. */
6113 nonzero = nonzero_bits (x, mode);
6139ff20
RK		 6114
6115 /* If none of the bits in X are needed, return a zero. */
e3d616e3 6116 if (! just_select && (nonzero & mask) == 0)
6139ff20 6117 return const0_rtx;
dfbe1b2f 6118
6139ff20
RK		 6119 /* If X is a CONST_INT, return a new one. Do this here since the
6120 test below will fail. */
6121 if (GET_CODE (x) == CONST_INT)
ceb7983c
RK		 6122 {
6123 HOST_WIDE_INT cval = INTVAL (x) & mask;
6124 int width = GET_MODE_BITSIZE (mode);
6125
6126 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6127 number, sign extend it. */
6128 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6129 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6130 cval |= (HOST_WIDE_INT) -1 << width;
6131
6132 return GEN_INT (cval);
6133 }
dfbe1b2f 6134
180b8e4b
RK		 6135 /* If X is narrower than MODE and we want all the bits in X's mode, just
6136 get X in the proper mode. */
6137 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6138 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
dfbe1b2f
RK		 6139 return gen_lowpart_for_combine (mode, x);
6140
71923da7
RK		 6141 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6142 MASK are already known to be zero in X, we need not do anything. */
6143 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6139ff20
RK		 6144 return x;
6145
dfbe1b2f
RK		 6146 switch (code)
6147 {
6139ff20
RK		 6148 case CLOBBER:
6149 /* If X is a (clobber (const_int)), return it since we know we are
0f41302f 6150 generating something that won't match. */
6139ff20
RK		 6151 return x;
6152
6139ff20
RK		 6153 case USE:
6154 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6155 spanned the boundary of the MEM. If we are now masking so it is
6156 within that boundary, we don't need the USE any more. */
f76b9db2
ILT		 6157 if (! BITS_BIG_ENDIAN
6158 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
e3d616e3 6159 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
f76b9db2 6160 break;
6139ff20 6161
dfbe1b2f
RK		 6162 case SIGN_EXTEND:
6163 case ZERO_EXTEND:
6164 case ZERO_EXTRACT:
6165 case SIGN_EXTRACT:
6166 x = expand_compound_operation (x);
6167 if (GET_CODE (x) != code)
e3d616e3 6168 return force_to_mode (x, mode, mask, reg, next_select);
dfbe1b2f
RK		 6169 break;
6170
6171 case REG:
6172 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6173 || rtx_equal_p (reg, get_last_value (x))))
6174 x = reg;
6175 break;
6176
dfbe1b2f 6177 case SUBREG:
6139ff20 6178 if (subreg_lowpart_p (x)
180b8e4b
RK		 6179 /* We can ignore the effect of this SUBREG if it narrows the mode or
6180 if the constant masks to zero all the bits the mode doesn't
6181 have. */
6139ff20
RK		 6182 && ((GET_MODE_SIZE (GET_MODE (x))
6183 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6139ff20
RK		 6184 || (0 == (mask
6185 & GET_MODE_MASK (GET_MODE (x))
180b8e4b 6186 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
e3d616e3 6187 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
dfbe1b2f
RK		 6188 break;
6189
6190 case AND:
6139ff20
RK		 6191 /* If this is an AND with a constant, convert it into an AND
6192 whose constant is the AND of that constant with MASK. If it
6193 remains an AND of MASK, delete it since it is redundant. */
dfbe1b2f 6194
2ca9ae17 6195 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
dfbe1b2f 6196 {
6139ff20
RK		 6197 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6198 mask & INTVAL (XEXP (x, 1)));
dfbe1b2f
RK		 6199
6200 /* If X is still an AND, see if it is an AND with a mask that
71923da7
RK		 6201 is just some low-order bits. If so, and it is MASK, we don't
6202 need it. */
dfbe1b2f
RK		 6203
6204 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6205 && INTVAL (XEXP (x, 1)) == mask)
dfbe1b2f 6206 x = XEXP (x, 0);
d0ab8cd3 6207
71923da7
RK		 6208 /* If it remains an AND, try making another AND with the bits
6209 in the mode mask that aren't in MASK turned on. If the
6210 constant in the AND is wide enough, this might make a
6211 cheaper constant. */
6212
6213 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
2ca9ae17
JW		 6214 && GET_MODE_MASK (GET_MODE (x)) != mask
6215 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
71923da7
RK		 6216 {
6217 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6218 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6219 int width = GET_MODE_BITSIZE (GET_MODE (x));
6220 rtx y;
6221
6222 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6223 number, sign extend it. */
6224 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6225 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6226 cval |= (HOST_WIDE_INT) -1 << width;
6227
6228 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6229 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6230 x = y;
6231 }
6232
d0ab8cd3 6233 break;
dfbe1b2f
RK		 6234 }
6235
6139ff20 6236 goto binop;
dfbe1b2f
RK		 6237
6238 case PLUS:
6139ff20
RK		 6239 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6240 low-order bits (as in an alignment operation) and FOO is already
6241 aligned to that boundary, mask C1 to that boundary as well.
6242 This may eliminate that PLUS and, later, the AND. */
9fa6d012
TG		 6243
6244 {
6245 int width = GET_MODE_BITSIZE (mode);
6246 unsigned HOST_WIDE_INT smask = mask;
6247
6248 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6249 number, sign extend it. */
6250
6251 if (width < HOST_BITS_PER_WIDE_INT
6252 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6253 smask |= (HOST_WIDE_INT) -1 << width;
6254
6255 if (GET_CODE (XEXP (x, 1)) == CONST_INT
0e9ff885
DM		 6256 && exact_log2 (- smask) >= 0)
6257 {
6258#ifdef STACK_BIAS
6259 if (STACK_BIAS
6260 && (XEXP (x, 0) == stack_pointer_rtx
6261 || XEXP (x, 0) == frame_pointer_rtx))
6262 {
6263 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6264 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6265
6266 sp_mask &= ~ (sp_alignment - 1);
6267 if ((sp_mask & ~ mask) == 0
6268 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6269 return force_to_mode (plus_constant (XEXP (x, 0),
6270 ((INTVAL (XEXP (x, 1)) -
6271 STACK_BIAS) & mask)
6272 + STACK_BIAS),
6273 mode, mask, reg, next_select);
6274 }
6275#endif
6276 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6277 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6278 return force_to_mode (plus_constant (XEXP (x, 0),
6279 INTVAL (XEXP (x, 1)) & mask),
6280 mode, mask, reg, next_select);
6281 }
9fa6d012 6282 }
6139ff20 6283
0f41302f 6284 /* ... fall through ... */
6139ff20 6285
dfbe1b2f
RK		 6286 case MINUS:
6287 case MULT:
6139ff20
RK		 6288 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6289 most significant bit in MASK since carries from those bits will
6290 affect the bits we are interested in. */
6291 mask = fuller_mask;
6292 goto binop;
6293
dfbe1b2f
RK		 6294 case IOR:
6295 case XOR:
6139ff20
RK		 6296 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6297 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6298 operation which may be a bitfield extraction. Ensure that the
6299 constant we form is not wider than the mode of X. */
6300
6301 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6302 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6303 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6304 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6305 && GET_CODE (XEXP (x, 1)) == CONST_INT
6306 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6307 + floor_log2 (INTVAL (XEXP (x, 1))))
6308 < GET_MODE_BITSIZE (GET_MODE (x)))
6309 && (INTVAL (XEXP (x, 1))
01c82bbb 6310 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6139ff20
RK		 6311 {
6312 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6313 << INTVAL (XEXP (XEXP (x, 0), 1)));
6314 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6315 XEXP (XEXP (x, 0), 0), temp);
d4d2b13f
RK		 6316 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6317 XEXP (XEXP (x, 0), 1));
e3d616e3 6318 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6319 }
6320
6321 binop:
dfbe1b2f 6322 /* For most binary operations, just propagate into the operation and
6139ff20
RK		 6323 change the mode if we have an operation of that mode. */
6324
e3d616e3
RK		 6325 op0 = gen_lowpart_for_combine (op_mode,
6326 force_to_mode (XEXP (x, 0), mode, mask,
6327 reg, next_select));
6328 op1 = gen_lowpart_for_combine (op_mode,
6329 force_to_mode (XEXP (x, 1), mode, mask,
6330 reg, next_select));
6139ff20 6331
2dd484ed
RK		 6332 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6333 MASK since OP1 might have been sign-extended but we never want
6334 to turn on extra bits, since combine might have previously relied
6335 on them being off. */
6336 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6337 && (INTVAL (op1) & mask) != 0)
6338 op1 = GEN_INT (INTVAL (op1) & mask);
6339
6139ff20
RK		 6340 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6341 x = gen_binary (code, op_mode, op0, op1);
d0ab8cd3 6342 break;
dfbe1b2f
RK		 6343
6344 case ASHIFT:
dfbe1b2f 6345 /* For left shifts, do the same, but just for the first operand.
f6785026
RK		 6346 However, we cannot do anything with shifts where we cannot
6347 guarantee that the counts are smaller than the size of the mode
6348 because such a count will have a different meaning in a
6139ff20 6349 wider mode. */
f6785026
RK		 6350
6351 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6352 && INTVAL (XEXP (x, 1)) >= 0
f6785026
RK		 6353 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6354 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6355 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
adb7a1cb 6356 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
f6785026
RK		 6357 break;
6358
6139ff20
RK		 6359 /* If the shift count is a constant and we can do arithmetic in
6360 the mode of the shift, refine which bits we need. Otherwise, use the
6361 conservative form of the mask. */
6362 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6363 && INTVAL (XEXP (x, 1)) >= 0
6364 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6365 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6366 mask >>= INTVAL (XEXP (x, 1));
6367 else
6368 mask = fuller_mask;
6369
6370 op0 = gen_lowpart_for_combine (op_mode,
6371 force_to_mode (XEXP (x, 0), op_mode,
e3d616e3 6372 mask, reg, next_select));
6139ff20
RK		 6373
6374 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6375 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
d0ab8cd3 6376 break;
dfbe1b2f
RK		 6377
6378 case LSHIFTRT:
1347292b
JW		 6379 /* Here we can only do something if the shift count is a constant,
6380 this shift constant is valid for the host, and we can do arithmetic
6381 in OP_MODE. */
dfbe1b2f
RK		 6382
6383 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1347292b 6384 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6139ff20 6385 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 6386 {
6139ff20
RK		 6387 rtx inner = XEXP (x, 0);
6388
6389 /* Select the mask of the bits we need for the shift operand. */
6390 mask <<= INTVAL (XEXP (x, 1));
d0ab8cd3 6391
6139ff20
RK		 6392 /* We can only change the mode of the shift if we can do arithmetic
6393 in the mode of the shift and MASK is no wider than the width of
6394 OP_MODE. */
6395 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6396 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
d0ab8cd3
RK		 6397 op_mode = GET_MODE (x);
6398
e3d616e3 6399 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6139ff20
RK		 6400
6401 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6402 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
d0ab8cd3 6403 }
6139ff20
RK		 6404
6405 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6406 shift and AND produces only copies of the sign bit (C2 is one less
6407 than a power of two), we can do this with just a shift. */
6408
6409 if (GET_CODE (x) == LSHIFTRT
6410 && GET_CODE (XEXP (x, 1)) == CONST_INT
6411 && ((INTVAL (XEXP (x, 1))
6412 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6413 >= GET_MODE_BITSIZE (GET_MODE (x)))
6414 && exact_log2 (mask + 1) >= 0
6415 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6416 >= exact_log2 (mask + 1)))
6417 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6418 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6419 - exact_log2 (mask + 1)));
d0ab8cd3
RK		 6420 break;
6421
6422 case ASHIFTRT:
6139ff20
RK		 6423 /* If we are just looking for the sign bit, we don't need this shift at
6424 all, even if it has a variable count. */
9bf22b75
RK		 6425 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6426 && (mask == ((HOST_WIDE_INT) 1
6427 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
e3d616e3 6428 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20
RK		 6429
6430 /* If this is a shift by a constant, get a mask that contains those bits
6431 that are not copies of the sign bit. We then have two cases: If
6432 MASK only includes those bits, this can be a logical shift, which may
6433 allow simplifications. If MASK is a single-bit field not within
6434 those bits, we are requesting a copy of the sign bit and hence can
6435 shift the sign bit to the appropriate location. */
6436
6437 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6438 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6439 {
6440 int i = -1;
6441
b69960ac
RK		 6442 /* If the considered data is wider then HOST_WIDE_INT, we can't
6443 represent a mask for all its bits in a single scalar.
6444 But we only care about the lower bits, so calculate these. */
6445
6a11342f 6446 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
b69960ac 6447 {
0f41302f 6448 nonzero = ~ (HOST_WIDE_INT) 0;
b69960ac
RK		 6449
6450 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6451 is the number of bits a full-width mask would have set.
6452 We need only shift if these are fewer than nonzero can
6453 hold. If not, we must keep all bits set in nonzero. */
6454
6455 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6456 < HOST_BITS_PER_WIDE_INT)
6457 nonzero >>= INTVAL (XEXP (x, 1))
6458 + HOST_BITS_PER_WIDE_INT
6459 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6460 }
6461 else
6462 {
6463 nonzero = GET_MODE_MASK (GET_MODE (x));
6464 nonzero >>= INTVAL (XEXP (x, 1));
6465 }
6139ff20
RK		 6466
6467 if ((mask & ~ nonzero) == 0
6468 || (i = exact_log2 (mask)) >= 0)
6469 {
6470 x = simplify_shift_const
6471 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6472 i < 0 ? INTVAL (XEXP (x, 1))
6473 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6474
6475 if (GET_CODE (x) != ASHIFTRT)
e3d616e3 6476 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6477 }
6478 }
6479
6480 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6481 even if the shift count isn't a constant. */
6482 if (mask == 1)
6483 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6484
d0ab8cd3 6485 /* If this is a sign-extension operation that just affects bits
4c002f29
RK		 6486 we don't care about, remove it. Be sure the call above returned
6487 something that is still a shift. */
d0ab8cd3 6488
4c002f29
RK		 6489 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6490 && GET_CODE (XEXP (x, 1)) == CONST_INT
d0ab8cd3 6491 && INTVAL (XEXP (x, 1)) >= 0
6139ff20
RK		 6492 && (INTVAL (XEXP (x, 1))
6493 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
d0ab8cd3
RK		 6494 && GET_CODE (XEXP (x, 0)) == ASHIFT
6495 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6496 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
e3d616e3
RK		 6497 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6498 reg, next_select);
6139ff20 6499
dfbe1b2f
RK		 6500 break;
6501
6139ff20
RK		 6502 case ROTATE:
6503 case ROTATERT:
6504 /* If the shift count is constant and we can do computations
6505 in the mode of X, compute where the bits we care about are.
6506 Otherwise, we can't do anything. Don't change the mode of
6507 the shift or propagate MODE into the shift, though. */
6508 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6509 && INTVAL (XEXP (x, 1)) >= 0)
6510 {
6511 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6512 GET_MODE (x), GEN_INT (mask),
6513 XEXP (x, 1));
7d171a1e 6514 if (temp && GET_CODE(temp) == CONST_INT)
6139ff20
RK		 6515 SUBST (XEXP (x, 0),
6516 force_to_mode (XEXP (x, 0), GET_MODE (x),
e3d616e3 6517 INTVAL (temp), reg, next_select));
6139ff20
RK		 6518 }
6519 break;
6520
dfbe1b2f 6521 case NEG:
180b8e4b
RK		 6522 /* If we just want the low-order bit, the NEG isn't needed since it
6523 won't change the low-order bit. */
6524 if (mask == 1)
6525 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6526
6139ff20
RK		 6527 /* We need any bits less significant than the most significant bit in
6528 MASK since carries from those bits will affect the bits we are
6529 interested in. */
6530 mask = fuller_mask;
6531 goto unop;
6532
dfbe1b2f 6533 case NOT:
6139ff20
RK		 6534 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6535 same as the XOR case above. Ensure that the constant we form is not
6536 wider than the mode of X. */
6537
6538 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6539 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6540 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6541 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6542 < GET_MODE_BITSIZE (GET_MODE (x)))
6543 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6544 {
6545 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6546 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6547 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6548
e3d616e3 6549 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6550 }
6551
f82da7d2
JW		 6552 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6553 use the full mask inside the NOT. */
6554 mask = fuller_mask;
6555
6139ff20 6556 unop:
e3d616e3
RK		 6557 op0 = gen_lowpart_for_combine (op_mode,
6558 force_to_mode (XEXP (x, 0), mode, mask,
6559 reg, next_select));
6139ff20 6560 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
0c1c8ea6 6561 x = gen_unary (code, op_mode, op_mode, op0);
6139ff20
RK		 6562 break;
6563
6564 case NE:
6565 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
3aceff0d 6566 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
1a6ec070 6567 which is equal to STORE_FLAG_VALUE. */
3aceff0d
RK		 6568 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6569 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
1a6ec070 6570 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
e3d616e3 6571 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20 6572
d0ab8cd3
RK		 6573 break;
6574
6575 case IF_THEN_ELSE:
6576 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6577 written in a narrower mode. We play it safe and do not do so. */
6578
6579 SUBST (XEXP (x, 1),
6580 gen_lowpart_for_combine (GET_MODE (x),
6581 force_to_mode (XEXP (x, 1), mode,
e3d616e3 6582 mask, reg, next_select)));
d0ab8cd3
RK		 6583 SUBST (XEXP (x, 2),
6584 gen_lowpart_for_combine (GET_MODE (x),
6585 force_to_mode (XEXP (x, 2), mode,
e3d616e3 6586 mask, reg,next_select)));
d0ab8cd3 6587 break;
e9a25f70
JL		 6588
6589 default:
6590 break;
dfbe1b2f
RK		 6591 }
6592
d0ab8cd3 6593 /* Ensure we return a value of the proper mode. */
dfbe1b2f
RK		 6594 return gen_lowpart_for_combine (mode, x);
6595}
6596\f
abe6e52f
RK		 6597/* Return nonzero if X is an expression that has one of two values depending on
6598 whether some other value is zero or nonzero. In that case, we return the
6599 value that is being tested, *PTRUE is set to the value if the rtx being
6600 returned has a nonzero value, and *PFALSE is set to the other alternative.
6601
6602 If we return zero, we set *PTRUE and *PFALSE to X. */
6603
6604static rtx
6605if_then_else_cond (x, ptrue, pfalse)
6606 rtx x;
6607 rtx *ptrue, *pfalse;
6608{
6609 enum machine_mode mode = GET_MODE (x);
6610 enum rtx_code code = GET_CODE (x);
6611 int size = GET_MODE_BITSIZE (mode);
6612 rtx cond0, cond1, true0, true1, false0, false1;
6613 unsigned HOST_WIDE_INT nz;
6614
6615 /* If this is a unary operation whose operand has one of two values, apply
6616 our opcode to compute those values. */
6617 if (GET_RTX_CLASS (code) == '1'
6618 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6619 {
0c1c8ea6
RK		 6620 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6621 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
abe6e52f
RK		 6622 return cond0;
6623 }
6624
3a19aabc 6625 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
ddd5a7c1 6626 make can't possibly match and would suppress other optimizations. */
3a19aabc
RK		 6627 else if (code == COMPARE)
6628 ;
6629
abe6e52f
RK		 6630 /* If this is a binary operation, see if either side has only one of two
6631 values. If either one does or if both do and they are conditional on
6632 the same value, compute the new true and false values. */
6633 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6634 || GET_RTX_CLASS (code) == '<')
6635 {
6636 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6637 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6638
6639 if ((cond0 != 0 || cond1 != 0)
6640 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6641 {
987e845a
JW		 6642 /* If if_then_else_cond returned zero, then true/false are the
6643 same rtl. We must copy one of them to prevent invalid rtl
6644 sharing. */
6645 if (cond0 == 0)
6646 true0 = copy_rtx (true0);
6647 else if (cond1 == 0)
6648 true1 = copy_rtx (true1);
6649
abe6e52f
RK		 6650 *ptrue = gen_binary (code, mode, true0, true1);
6651 *pfalse = gen_binary (code, mode, false0, false1);
6652 return cond0 ? cond0 : cond1;
6653 }
9210df58 6654
9210df58 6655 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
0802d516
RK		 6656 operands is zero when the other is non-zero, and vice-versa,
6657 and STORE_FLAG_VALUE is 1 or -1. */
9210df58 6658
0802d516
RK		 6659 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6660 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9210df58
RK		 6661 || code == UMAX)
6662 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6663 {
6664 rtx op0 = XEXP (XEXP (x, 0), 1);
6665 rtx op1 = XEXP (XEXP (x, 1), 1);
6666
6667 cond0 = XEXP (XEXP (x, 0), 0);
6668 cond1 = XEXP (XEXP (x, 1), 0);
6669
6670 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6671 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6672 && reversible_comparison_p (cond1)
6673 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6674 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6675 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6676 || ((swap_condition (GET_CODE (cond0))
6677 == reverse_condition (GET_CODE (cond1)))
6678 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6679 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6680 && ! side_effects_p (x))
6681 {
6682 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6683 *pfalse = gen_binary (MULT, mode,
6684 (code == MINUS
0c1c8ea6 6685 ? gen_unary (NEG, mode, mode, op1) : op1),
9210df58
RK		 6686 const_true_rtx);
6687 return cond0;
6688 }
6689 }
6690
6691 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6692 is always zero. */
0802d516
RK		 6693 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6694 && (code == MULT || code == AND || code == UMIN)
9210df58
RK		 6695 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6696 {
6697 cond0 = XEXP (XEXP (x, 0), 0);
6698 cond1 = XEXP (XEXP (x, 1), 0);
6699
6700 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6701 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6702 && reversible_comparison_p (cond1)
6703 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6704 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6705 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6706 || ((swap_condition (GET_CODE (cond0))
6707 == reverse_condition (GET_CODE (cond1)))
6708 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6709 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6710 && ! side_effects_p (x))
6711 {
6712 *ptrue = *pfalse = const0_rtx;
6713 return cond0;
6714 }
6715 }
abe6e52f
RK		 6716 }
6717
6718 else if (code == IF_THEN_ELSE)
6719 {
6720 /* If we have IF_THEN_ELSE already, extract the condition and
6721 canonicalize it if it is NE or EQ. */
6722 cond0 = XEXP (x, 0);
6723 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6724 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6725 return XEXP (cond0, 0);
6726 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6727 {
6728 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6729 return XEXP (cond0, 0);
6730 }
6731 else
6732 return cond0;
6733 }
6734
6735 /* If X is a normal SUBREG with both inner and outer modes integral,
6736 we can narrow both the true and false values of the inner expression,
6737 if there is a condition. */
6738 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6739 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6740 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6741 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6742 &true0, &false0)))
6743 {
00244e6b
RK		 6744 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6745 *pfalse
6746 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
abe6e52f 6747
abe6e52f
RK		 6748 return cond0;
6749 }
6750
6751 /* If X is a constant, this isn't special and will cause confusions
6752 if we treat it as such. Likewise if it is equivalent to a constant. */
6753 else if (CONSTANT_P (x)
6754 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6755 ;
6756
6757 /* If X is known to be either 0 or -1, those are the true and
6758 false values when testing X. */
6759 else if (num_sign_bit_copies (x, mode) == size)
6760 {
6761 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6762 return x;
6763 }
6764
6765 /* Likewise for 0 or a single bit. */
6766 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6767 {
6768 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6769 return x;
6770 }
6771
6772 /* Otherwise fail; show no condition with true and false values the same. */
6773 *ptrue = *pfalse = x;
6774 return 0;
6775}
6776\f
1a26b032
RK		 6777/* Return the value of expression X given the fact that condition COND
6778 is known to be true when applied to REG as its first operand and VAL
6779 as its second. X is known to not be shared and so can be modified in
6780 place.
6781
6782 We only handle the simplest cases, and specifically those cases that
6783 arise with IF_THEN_ELSE expressions. */
6784
6785static rtx
6786known_cond (x, cond, reg, val)
6787 rtx x;
6788 enum rtx_code cond;
6789 rtx reg, val;
6790{
6791 enum rtx_code code = GET_CODE (x);
f24ad0e4 6792 rtx temp;
1a26b032
RK		 6793 char *fmt;
6794 int i, j;
6795
6796 if (side_effects_p (x))
6797 return x;
6798
6799 if (cond == EQ && rtx_equal_p (x, reg))
6800 return val;
6801
6802 /* If X is (abs REG) and we know something about REG's relationship
6803 with zero, we may be able to simplify this. */
6804
6805 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6806 switch (cond)
6807 {
6808 case GE: case GT: case EQ:
6809 return XEXP (x, 0);
6810 case LT: case LE:
0c1c8ea6
RK		 6811 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6812 XEXP (x, 0));
e9a25f70
JL		 6813 default:
6814 break;
1a26b032
RK		 6815 }
6816
6817 /* The only other cases we handle are MIN, MAX, and comparisons if the
6818 operands are the same as REG and VAL. */
6819
6820 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6821 {
6822 if (rtx_equal_p (XEXP (x, 0), val))
6823 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6824
6825 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6826 {
6827 if (GET_RTX_CLASS (code) == '<')
6828 return (comparison_dominates_p (cond, code) ? const_true_rtx
6829 : (comparison_dominates_p (cond,
6830 reverse_condition (code))
6831 ? const0_rtx : x));
6832
6833 else if (code == SMAX || code == SMIN
6834 || code == UMIN || code == UMAX)
6835 {
6836 int unsignedp = (code == UMIN || code == UMAX);
6837
6838 if (code == SMAX || code == UMAX)
6839 cond = reverse_condition (cond);
6840
6841 switch (cond)
6842 {
6843 case GE: case GT:
6844 return unsignedp ? x : XEXP (x, 1);
6845 case LE: case LT:
6846 return unsignedp ? x : XEXP (x, 0);
6847 case GEU: case GTU:
6848 return unsignedp ? XEXP (x, 1) : x;
6849 case LEU: case LTU:
6850 return unsignedp ? XEXP (x, 0) : x;
e9a25f70
JL		 6851 default:
6852 break;
1a26b032
RK		 6853 }
6854 }
6855 }
6856 }
6857
6858 fmt = GET_RTX_FORMAT (code);
6859 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6860 {
6861 if (fmt[i] == 'e')
6862 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6863 else if (fmt[i] == 'E')
6864 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6865 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6866 cond, reg, val));
6867 }
6868
6869 return x;
6870}
6871\f
e11fa86f
RK		 6872/* See if X and Y are equal for the purposes of seeing if we can rewrite an
6873 assignment as a field assignment. */
6874
6875static int
6876rtx_equal_for_field_assignment_p (x, y)
6877 rtx x;
6878 rtx y;
6879{
6880 rtx last_x, last_y;
6881
6882 if (x == y || rtx_equal_p (x, y))
6883 return 1;
6884
6885 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6886 return 0;
6887
6888 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6889 Note that all SUBREGs of MEM are paradoxical; otherwise they
6890 would have been rewritten. */
6891 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6892 && GET_CODE (SUBREG_REG (y)) == MEM
6893 && rtx_equal_p (SUBREG_REG (y),
6894 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6895 return 1;
6896
6897 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6898 && GET_CODE (SUBREG_REG (x)) == MEM
6899 && rtx_equal_p (SUBREG_REG (x),
6900 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6901 return 1;
6902
6903 last_x = get_last_value (x);
6904 last_y = get_last_value (y);
6905
0f47edd3
JL		 6906 return ((last_x != 0
6907 && GET_CODE (last_x) != CLOBBER
6908 && rtx_equal_for_field_assignment_p (last_x, y))
6909 || (last_y != 0
6910 && GET_CODE (last_y) != CLOBBER
6911 && rtx_equal_for_field_assignment_p (x, last_y))
e11fa86f 6912 || (last_x != 0 && last_y != 0
0f47edd3
JL		 6913 && GET_CODE (last_x) != CLOBBER
6914 && GET_CODE (last_y) != CLOBBER
e11fa86f
RK		 6915 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6916}
6917\f
230d793d
RS		 6918/* See if X, a SET operation, can be rewritten as a bit-field assignment.
6919 Return that assignment if so.
6920
6921 We only handle the most common cases. */
6922
6923static rtx
6924make_field_assignment (x)
6925 rtx x;
6926{
6927 rtx dest = SET_DEST (x);
6928 rtx src = SET_SRC (x);
dfbe1b2f 6929 rtx assign;
e11fa86f 6930 rtx rhs, lhs;
5f4f0e22
CH		 6931 HOST_WIDE_INT c1;
6932 int pos, len;
dfbe1b2f
RK		 6933 rtx other;
6934 enum machine_mode mode;
230d793d
RS		 6935
6936 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6937 a clear of a one-bit field. We will have changed it to
6938 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6939 for a SUBREG. */
6940
6941 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6942 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6943 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
e11fa86f 6944 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 6945 {
8999a12e 6946 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 6947 1, 1, 1, 0);
76184def 6948 if (assign != 0)
38a448ca 6949 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 6950 return x;
230d793d
RS		 6951 }
6952
6953 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6954 && subreg_lowpart_p (XEXP (src, 0))
6955 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6956 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6957 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6958 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
e11fa86f 6959 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 6960 {
8999a12e 6961 assign = make_extraction (VOIDmode, dest, 0,
230d793d
RS		 6962 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6963 1, 1, 1, 0);
76184def 6964 if (assign != 0)
38a448ca 6965 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 6966 return x;
230d793d
RS		 6967 }
6968
9dd11dcb 6969 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
230d793d
RS		 6970 one-bit field. */
6971 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6972 && XEXP (XEXP (src, 0), 0) == const1_rtx
e11fa86f 6973 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 6974 {
8999a12e 6975 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 6976 1, 1, 1, 0);
76184def 6977 if (assign != 0)
38a448ca 6978 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
76184def 6979 return x;
230d793d
RS		 6980 }
6981
dfbe1b2f 6982 /* The other case we handle is assignments into a constant-position
9dd11dcb 6983 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
dfbe1b2f
RK		 6984 a mask that has all one bits except for a group of zero bits and
6985 OTHER is known to have zeros where C1 has ones, this is such an
6986 assignment. Compute the position and length from C1. Shift OTHER
6987 to the appropriate position, force it to the required mode, and
6988 make the extraction. Check for the AND in both operands. */
6989
9dd11dcb 6990 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
e11fa86f
RK		 6991 return x;
6992
6993 rhs = expand_compound_operation (XEXP (src, 0));
6994 lhs = expand_compound_operation (XEXP (src, 1));
6995
6996 if (GET_CODE (rhs) == AND
6997 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6998 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6999 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7000 else if (GET_CODE (lhs) == AND
7001 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7002 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7003 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
dfbe1b2f
RK		 7004 else
7005 return x;
230d793d 7006
e11fa86f 7007 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
dfbe1b2f 7008 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
ac49a949 7009 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
951553af 7010 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
dfbe1b2f 7011 return x;
230d793d 7012
5f4f0e22 7013 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
76184def
DE		 7014 if (assign == 0)
7015 return x;
230d793d 7016
dfbe1b2f
RK		 7017 /* The mode to use for the source is the mode of the assignment, or of
7018 what is inside a possible STRICT_LOW_PART. */
7019 mode = (GET_CODE (assign) == STRICT_LOW_PART
7020 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
230d793d 7021
dfbe1b2f
RK		 7022 /* Shift OTHER right POS places and make it the source, restricting it
7023 to the proper length and mode. */
230d793d 7024
5f4f0e22
CH		 7025 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7026 GET_MODE (src), other, pos),
6139ff20
RK		 7027 mode,
7028 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7029 ? GET_MODE_MASK (mode)
7030 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 7031 dest, 0);
230d793d 7032
dfbe1b2f 7033 return gen_rtx_combine (SET, VOIDmode, assign, src);
230d793d
RS		 7034}
7035\f
7036/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7037 if so. */
7038
7039static rtx
7040apply_distributive_law (x)
7041 rtx x;
7042{
7043 enum rtx_code code = GET_CODE (x);
7044 rtx lhs, rhs, other;
7045 rtx tem;
7046 enum rtx_code inner_code;
7047
d8a8a4da
RS		 7048 /* Distributivity is not true for floating point.
7049 It can change the value. So don't do it.
7050 -- rms and moshier@world.std.com. */
3ad2180a 7051 if (FLOAT_MODE_P (GET_MODE (x)))
d8a8a4da
RS		 7052 return x;
7053
230d793d
RS		 7054 /* The outer operation can only be one of the following: */
7055 if (code != IOR && code != AND && code != XOR
7056 && code != PLUS && code != MINUS)
7057 return x;
7058
7059 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7060
0f41302f
MS		 7061 /* If either operand is a primitive we can't do anything, so get out
7062 fast. */
230d793d 7063 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
dfbe1b2f 7064 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
230d793d
RS		 7065 return x;
7066
7067 lhs = expand_compound_operation (lhs);
7068 rhs = expand_compound_operation (rhs);
7069 inner_code = GET_CODE (lhs);
7070 if (inner_code != GET_CODE (rhs))
7071 return x;
7072
7073 /* See if the inner and outer operations distribute. */
7074 switch (inner_code)
7075 {
7076 case LSHIFTRT:
7077 case ASHIFTRT:
7078 case AND:
7079 case IOR:
7080 /* These all distribute except over PLUS. */
7081 if (code == PLUS || code == MINUS)
7082 return x;
7083 break;
7084
7085 case MULT:
7086 if (code != PLUS && code != MINUS)
7087 return x;
7088 break;
7089
7090 case ASHIFT:
45620ed4 7091 /* This is also a multiply, so it distributes over everything. */
230d793d
RS		 7092 break;
7093
7094 case SUBREG:
dfbe1b2f
RK		 7095 /* Non-paradoxical SUBREGs distributes over all operations, provided
7096 the inner modes and word numbers are the same, this is an extraction
2b4bd1bc
JW		 7097 of a low-order part, we don't convert an fp operation to int or
7098 vice versa, and we would not be converting a single-word
dfbe1b2f 7099 operation into a multi-word operation. The latter test is not
2b4bd1bc 7100 required, but it prevents generating unneeded multi-word operations.
dfbe1b2f
RK		 7101 Some of the previous tests are redundant given the latter test, but
7102 are retained because they are required for correctness.
7103
7104 We produce the result slightly differently in this case. */
7105
7106 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7107 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7108 || ! subreg_lowpart_p (lhs)
2b4bd1bc
JW		 7109 || (GET_MODE_CLASS (GET_MODE (lhs))
7110 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7111 || (GET_MODE_SIZE (GET_MODE (lhs))
8af24e26 7112 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7113 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
230d793d
RS		 7114 return x;
7115
7116 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7117 SUBREG_REG (lhs), SUBREG_REG (rhs));
7118 return gen_lowpart_for_combine (GET_MODE (x), tem);
7119
7120 default:
7121 return x;
7122 }
7123
7124 /* Set LHS and RHS to the inner operands (A and B in the example
7125 above) and set OTHER to the common operand (C in the example).
7126 These is only one way to do this unless the inner operation is
7127 commutative. */
7128 if (GET_RTX_CLASS (inner_code) == 'c'
7129 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7130 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7131 else if (GET_RTX_CLASS (inner_code) == 'c'
7132 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7133 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7134 else if (GET_RTX_CLASS (inner_code) == 'c'
7135 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7136 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7137 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7138 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7139 else
7140 return x;
7141
7142 /* Form the new inner operation, seeing if it simplifies first. */
7143 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7144
7145 /* There is one exception to the general way of distributing:
7146 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7147 if (code == XOR && inner_code == IOR)
7148 {
7149 inner_code = AND;
0c1c8ea6 7150 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
230d793d
RS		 7151 }
7152
7153 /* We may be able to continuing distributing the result, so call
7154 ourselves recursively on the inner operation before forming the
7155 outer operation, which we return. */
7156 return gen_binary (inner_code, GET_MODE (x),
7157 apply_distributive_law (tem), other);
7158}
7159\f
7160/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7161 in MODE.
7162
7163 Return an equivalent form, if different from X. Otherwise, return X. If
7164 X is zero, we are to always construct the equivalent form. */
7165
7166static rtx
7167simplify_and_const_int (x, mode, varop, constop)
7168 rtx x;
7169 enum machine_mode mode;
7170 rtx varop;
5f4f0e22 7171 unsigned HOST_WIDE_INT constop;
230d793d 7172{
951553af 7173 unsigned HOST_WIDE_INT nonzero;
9fa6d012 7174 int width = GET_MODE_BITSIZE (mode);
42301240 7175 int i;
230d793d 7176
6139ff20
RK		 7177 /* Simplify VAROP knowing that we will be only looking at some of the
7178 bits in it. */
e3d616e3 7179 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
230d793d 7180
6139ff20
RK		 7181 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7182 CONST_INT, we are done. */
7183 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7184 return varop;
230d793d 7185
fc06d7aa
RK		 7186 /* See what bits may be nonzero in VAROP. Unlike the general case of
7187 a call to nonzero_bits, here we don't care about bits outside
7188 MODE. */
7189
7190 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
230d793d 7191
9fa6d012
TG		 7192 /* If this would be an entire word for the target, but is not for
7193 the host, then sign-extend on the host so that the number will look
7194 the same way on the host that it would on the target.
7195
7196 For example, when building a 64 bit alpha hosted 32 bit sparc
7197 targeted compiler, then we want the 32 bit unsigned value -1 to be
7198 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7199 The later confuses the sparc backend. */
7200
7201 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7202 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7203 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7204
230d793d 7205 /* Turn off all bits in the constant that are known to already be zero.
951553af 7206 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
230d793d
RS		 7207 which is tested below. */
7208
951553af 7209 constop &= nonzero;
230d793d
RS		 7210
7211 /* If we don't have any bits left, return zero. */
7212 if (constop == 0)
7213 return const0_rtx;
7214
42301240
RK		 7215 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7216 a power of two, we can replace this with a ASHIFT. */
7217 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7218 && (i = exact_log2 (constop)) >= 0)
7219 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7220
6139ff20
RK		 7221 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7222 or XOR, then try to apply the distributive law. This may eliminate
7223 operations if either branch can be simplified because of the AND.
7224 It may also make some cases more complex, but those cases probably
7225 won't match a pattern either with or without this. */
7226
7227 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7228 return
7229 gen_lowpart_for_combine
7230 (mode,
7231 apply_distributive_law
7232 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7233 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7234 XEXP (varop, 0), constop),
7235 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7236 XEXP (varop, 1), constop))));
7237
230d793d
RS		 7238 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7239 if we already had one (just check for the simplest cases). */
7240 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7241 && GET_MODE (XEXP (x, 0)) == mode
7242 && SUBREG_REG (XEXP (x, 0)) == varop)
7243 varop = XEXP (x, 0);
7244 else
7245 varop = gen_lowpart_for_combine (mode, varop);
7246
0f41302f 7247 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 7248 if (GET_CODE (varop) == CLOBBER)
7249 return x ? x : varop;
7250
7251 /* If we are only masking insignificant bits, return VAROP. */
951553af 7252 if (constop == nonzero)
230d793d
RS		 7253 x = varop;
7254
7255 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7256 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6139ff20 7257 x = gen_binary (AND, mode, varop, GEN_INT (constop));
230d793d
RS		 7258
7259 else
7260 {
7261 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7262 || INTVAL (XEXP (x, 1)) != constop)
5f4f0e22 7263 SUBST (XEXP (x, 1), GEN_INT (constop));
230d793d
RS		 7264
7265 SUBST (XEXP (x, 0), varop);
7266 }
7267
7268 return x;
7269}
7270\f
b3728b0e
JW		 7271/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7272 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7273 is less useful. We can't allow both, because that results in exponential
956d6950 7274 run time recursion. There is a nullstone testcase that triggered
b3728b0e
JW		 7275 this. This macro avoids accidental uses of num_sign_bit_copies. */
7276#define num_sign_bit_copies()
7277
230d793d
RS		 7278/* Given an expression, X, compute which bits in X can be non-zero.
7279 We don't care about bits outside of those defined in MODE.
7280
7281 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7282 a shift, AND, or zero_extract, we can do better. */
7283
5f4f0e22 7284static unsigned HOST_WIDE_INT
951553af 7285nonzero_bits (x, mode)
230d793d
RS		 7286 rtx x;
7287 enum machine_mode mode;
7288{
951553af
RK		 7289 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7290 unsigned HOST_WIDE_INT inner_nz;
230d793d
RS		 7291 enum rtx_code code;
7292 int mode_width = GET_MODE_BITSIZE (mode);
7293 rtx tem;
7294
1c75dfa4
RK		 7295 /* For floating-point values, assume all bits are needed. */
7296 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7297 return nonzero;
7298
230d793d
RS		 7299 /* If X is wider than MODE, use its mode instead. */
7300 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7301 {
7302 mode = GET_MODE (x);
951553af 7303 nonzero = GET_MODE_MASK (mode);
230d793d
RS		 7304 mode_width = GET_MODE_BITSIZE (mode);
7305 }
7306
5f4f0e22 7307 if (mode_width > HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7308 /* Our only callers in this case look for single bit values. So
7309 just return the mode mask. Those tests will then be false. */
951553af 7310 return nonzero;
230d793d 7311
8baf60bb 7312#ifndef WORD_REGISTER_OPERATIONS
c6965c0f 7313 /* If MODE is wider than X, but both are a single word for both the host
0840fd91
RK		 7314 and target machines, we can compute this from which bits of the
7315 object might be nonzero in its own mode, taking into account the fact
7316 that on many CISC machines, accessing an object in a wider mode
7317 causes the high-order bits to become undefined. So they are
7318 not known to be zero. */
7319
7320 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7321 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7322 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
c6965c0f 7323 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
0840fd91
RK		 7324 {
7325 nonzero &= nonzero_bits (x, GET_MODE (x));
7326 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7327 return nonzero;
7328 }
7329#endif
7330
230d793d
RS		 7331 code = GET_CODE (x);
7332 switch (code)
7333 {
7334 case REG:
320dd7a7
RK		 7335#ifdef POINTERS_EXTEND_UNSIGNED
7336 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7337 all the bits above ptr_mode are known to be zero. */
7338 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7339 && REGNO_POINTER_FLAG (REGNO (x)))
7340 nonzero &= GET_MODE_MASK (ptr_mode);
7341#endif
7342
b0d71df9
RK		 7343#ifdef STACK_BOUNDARY
7344 /* If this is the stack pointer, we may know something about its
7345 alignment. If PUSH_ROUNDING is defined, it is possible for the
230d793d
RS		 7346 stack to be momentarily aligned only to that amount, so we pick
7347 the least alignment. */
7348
ee49a9c7
JW		 7349 /* We can't check for arg_pointer_rtx here, because it is not
7350 guaranteed to have as much alignment as the stack pointer.
7351 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7352 alignment but the argument pointer has only 64 bit alignment. */
7353
0e9ff885
DM		 7354 if ((x == frame_pointer_rtx
7355 || x == stack_pointer_rtx
7356 || x == hard_frame_pointer_rtx
7357 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7358 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7359#ifdef STACK_BIAS
7360 && !STACK_BIAS
7361#endif
7362 )
230d793d 7363 {
b0d71df9 7364 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
230d793d
RS		 7365
7366#ifdef PUSH_ROUNDING
91102d5a 7367 if (REGNO (x) == STACK_POINTER_REGNUM)
b0d71df9 7368 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
230d793d
RS		 7369#endif
7370
320dd7a7
RK		 7371 /* We must return here, otherwise we may get a worse result from
7372 one of the choices below. There is nothing useful below as
7373 far as the stack pointer is concerned. */
b0d71df9 7374 return nonzero &= ~ (sp_alignment - 1);
230d793d 7375 }
b0d71df9 7376#endif
230d793d 7377
55310dad
RK		 7378 /* If X is a register whose nonzero bits value is current, use it.
7379 Otherwise, if X is a register whose value we can find, use that
7380 value. Otherwise, use the previously-computed global nonzero bits
7381 for this register. */
7382
7383 if (reg_last_set_value[REGNO (x)] != 0
7384 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7385 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7386 || reg_last_set_label[REGNO (x)] == label_tick)
7387 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7388 return reg_last_set_nonzero_bits[REGNO (x)];
230d793d
RS		 7389
7390 tem = get_last_value (x);
9afa3d54 7391
230d793d 7392 if (tem)
9afa3d54
RK		 7393 {
7394#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7395 /* If X is narrower than MODE and TEM is a non-negative
7396 constant that would appear negative in the mode of X,
7397 sign-extend it for use in reg_nonzero_bits because some
7398 machines (maybe most) will actually do the sign-extension
7399 and this is the conservative approach.
7400
7401 ??? For 2.5, try to tighten up the MD files in this regard
7402 instead of this kludge. */
7403
7404 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7405 && GET_CODE (tem) == CONST_INT
7406 && INTVAL (tem) > 0
7407 && 0 != (INTVAL (tem)
7408 & ((HOST_WIDE_INT) 1
9e69be8c 7409 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 7410 tem = GEN_INT (INTVAL (tem)
7411 | ((HOST_WIDE_INT) (-1)
7412 << GET_MODE_BITSIZE (GET_MODE (x))));
7413#endif
7414 return nonzero_bits (tem, mode);
7415 }
951553af
RK		 7416 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7417 return reg_nonzero_bits[REGNO (x)] & nonzero;
230d793d 7418 else
951553af 7419 return nonzero;
230d793d
RS		 7420
7421 case CONST_INT:
9afa3d54
RK		 7422#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7423 /* If X is negative in MODE, sign-extend the value. */
9e69be8c
RK		 7424 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7425 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7426 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
9afa3d54
RK		 7427#endif
7428
230d793d
RS		 7429 return INTVAL (x);
7430
230d793d 7431 case MEM:
8baf60bb 7432#ifdef LOAD_EXTEND_OP
230d793d
RS		 7433 /* In many, if not most, RISC machines, reading a byte from memory
7434 zeros the rest of the register. Noticing that fact saves a lot
7435 of extra zero-extends. */
8baf60bb
RK		 7436 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7437 nonzero &= GET_MODE_MASK (GET_MODE (x));
230d793d 7438#endif
8baf60bb 7439 break;
230d793d 7440
230d793d
RS		 7441 case EQ: case NE:
7442 case GT: case GTU:
7443 case LT: case LTU:
7444 case GE: case GEU:
7445 case LE: case LEU:
3f508eca 7446
c6965c0f
RK		 7447 /* If this produces an integer result, we know which bits are set.
7448 Code here used to clear bits outside the mode of X, but that is
7449 now done above. */
230d793d 7450
c6965c0f
RK		 7451 if (GET_MODE_CLASS (mode) == MODE_INT
7452 && mode_width <= HOST_BITS_PER_WIDE_INT)
7453 nonzero = STORE_FLAG_VALUE;
230d793d 7454 break;
230d793d 7455
230d793d 7456 case NEG:
b3728b0e
JW		 7457#if 0
7458 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7459 and num_sign_bit_copies. */
d0ab8cd3
RK		 7460 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7461 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7462 nonzero = 1;
b3728b0e 7463#endif
230d793d
RS		 7464
7465 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
951553af 7466 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
230d793d 7467 break;
d0ab8cd3
RK		 7468
7469 case ABS:
b3728b0e
JW		 7470#if 0
7471 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7472 and num_sign_bit_copies. */
d0ab8cd3
RK		 7473 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7474 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7475 nonzero = 1;
b3728b0e 7476#endif
d0ab8cd3 7477 break;
230d793d
RS		 7478
7479 case TRUNCATE:
951553af 7480 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
230d793d
RS		 7481 break;
7482
7483 case ZERO_EXTEND:
951553af 7484 nonzero &= nonzero_bits (XEXP (x, 0), mode);
230d793d 7485 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
951553af 7486 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
230d793d
RS		 7487 break;
7488
7489 case SIGN_EXTEND:
7490 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7491 Otherwise, show all the bits in the outer mode but not the inner
7492 may be non-zero. */
951553af 7493 inner_nz = nonzero_bits (XEXP (x, 0), mode);
230d793d
RS		 7494 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7495 {
951553af 7496 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
e3da301d
MS		 7497 if (inner_nz
7498 & (((HOST_WIDE_INT) 1
7499 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
951553af 7500 inner_nz |= (GET_MODE_MASK (mode)
230d793d
RS		 7501 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7502 }
7503
951553af 7504 nonzero &= inner_nz;
230d793d
RS		 7505 break;
7506
7507 case AND:
951553af
RK		 7508 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7509 & nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7510 break;
7511
d0ab8cd3
RK		 7512 case XOR: case IOR:
7513 case UMIN: case UMAX: case SMIN: case SMAX:
951553af
RK		 7514 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7515 | nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7516 break;
7517
7518 case PLUS: case MINUS:
7519 case MULT:
7520 case DIV: case UDIV:
7521 case MOD: case UMOD:
7522 /* We can apply the rules of arithmetic to compute the number of
7523 high- and low-order zero bits of these operations. We start by
7524 computing the width (position of the highest-order non-zero bit)
7525 and the number of low-order zero bits for each value. */
7526 {
951553af
RK		 7527 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7528 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7529 int width0 = floor_log2 (nz0) + 1;
7530 int width1 = floor_log2 (nz1) + 1;
7531 int low0 = floor_log2 (nz0 & -nz0);
7532 int low1 = floor_log2 (nz1 & -nz1);
318b149c
RK		 7533 HOST_WIDE_INT op0_maybe_minusp
7534 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7535 HOST_WIDE_INT op1_maybe_minusp
7536 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
230d793d
RS		 7537 int result_width = mode_width;
7538 int result_low = 0;
7539
7540 switch (code)
7541 {
7542 case PLUS:
0e9ff885
DM		 7543#ifdef STACK_BIAS
7544 if (STACK_BIAS
7545 && (XEXP (x, 0) == stack_pointer_rtx
7546 || XEXP (x, 0) == frame_pointer_rtx)
7547 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7548 {
7549 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7550
7551 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7552 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7553 width0 = floor_log2 (nz0) + 1;
7554 width1 = floor_log2 (nz1) + 1;
7555 low0 = floor_log2 (nz0 & -nz0);
7556 low1 = floor_log2 (nz1 & -nz1);
7557 }
7558#endif
230d793d
RS		 7559 result_width = MAX (width0, width1) + 1;
7560 result_low = MIN (low0, low1);
7561 break;
7562 case MINUS:
7563 result_low = MIN (low0, low1);
7564 break;
7565 case MULT:
7566 result_width = width0 + width1;
7567 result_low = low0 + low1;
7568 break;
7569 case DIV:
7570 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7571 result_width = width0;
7572 break;
7573 case UDIV:
7574 result_width = width0;
7575 break;
7576 case MOD:
7577 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7578 result_width = MIN (width0, width1);
7579 result_low = MIN (low0, low1);
7580 break;
7581 case UMOD:
7582 result_width = MIN (width0, width1);
7583 result_low = MIN (low0, low1);
7584 break;
e9a25f70
JL		 7585 default:
7586 abort ();
230d793d
RS		 7587 }
7588
7589 if (result_width < mode_width)
951553af 7590 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
230d793d
RS		 7591
7592 if (result_low > 0)
951553af 7593 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
230d793d
RS		 7594 }
7595 break;
7596
7597 case ZERO_EXTRACT:
7598 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 7599 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
951553af 7600 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
230d793d
RS		 7601 break;
7602
7603 case SUBREG:
c3c2cb37
RK		 7604 /* If this is a SUBREG formed for a promoted variable that has
7605 been zero-extended, we know that at least the high-order bits
7606 are zero, though others might be too. */
7607
7608 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
951553af
RK		 7609 nonzero = (GET_MODE_MASK (GET_MODE (x))
7610 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
c3c2cb37 7611
230d793d
RS		 7612 /* If the inner mode is a single word for both the host and target
7613 machines, we can compute this from which bits of the inner
951553af 7614 object might be nonzero. */
230d793d 7615 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5f4f0e22
CH		 7616 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7617 <= HOST_BITS_PER_WIDE_INT))
230d793d 7618 {
951553af 7619 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8baf60bb
RK		 7620
7621#ifndef WORD_REGISTER_OPERATIONS
230d793d
RS		 7622 /* On many CISC machines, accessing an object in a wider mode
7623 causes the high-order bits to become undefined. So they are
7624 not known to be zero. */
7625 if (GET_MODE_SIZE (GET_MODE (x))
7626 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
951553af
RK		 7627 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7628 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
230d793d
RS		 7629#endif
7630 }
7631 break;
7632
7633 case ASHIFTRT:
7634 case LSHIFTRT:
7635 case ASHIFT:
230d793d 7636 case ROTATE:
951553af 7637 /* The nonzero bits are in two classes: any bits within MODE
230d793d 7638 that aren't in GET_MODE (x) are always significant. The rest of the
951553af 7639 nonzero bits are those that are significant in the operand of
230d793d
RS		 7640 the shift when shifted the appropriate number of bits. This
7641 shows that high-order bits are cleared by the right shift and
7642 low-order bits by left shifts. */
7643 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7644 && INTVAL (XEXP (x, 1)) >= 0
5f4f0e22 7645 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7646 {
7647 enum machine_mode inner_mode = GET_MODE (x);
7648 int width = GET_MODE_BITSIZE (inner_mode);
7649 int count = INTVAL (XEXP (x, 1));
5f4f0e22 7650 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
951553af
RK		 7651 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7652 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5f4f0e22 7653 unsigned HOST_WIDE_INT outer = 0;
230d793d
RS		 7654
7655 if (mode_width > width)
951553af 7656 outer = (op_nonzero & nonzero & ~ mode_mask);
230d793d
RS		 7657
7658 if (code == LSHIFTRT)
7659 inner >>= count;
7660 else if (code == ASHIFTRT)
7661 {
7662 inner >>= count;
7663
951553af 7664 /* If the sign bit may have been nonzero before the shift, we
230d793d 7665 need to mark all the places it could have been copied to
951553af 7666 by the shift as possibly nonzero. */
5f4f0e22
CH		 7667 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7668 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
230d793d 7669 }
45620ed4 7670 else if (code == ASHIFT)
230d793d
RS		 7671 inner <<= count;
7672 else
7673 inner = ((inner << (count % width)
7674 | (inner >> (width - (count % width)))) & mode_mask);
7675
951553af 7676 nonzero &= (outer | inner);
230d793d
RS		 7677 }
7678 break;
7679
7680 case FFS:
7681 /* This is at most the number of bits in the mode. */
951553af 7682 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
230d793d 7683 break;
d0ab8cd3
RK		 7684
7685 case IF_THEN_ELSE:
951553af
RK		 7686 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7687 | nonzero_bits (XEXP (x, 2), mode));
d0ab8cd3 7688 break;
e9a25f70
JL		 7689
7690 default:
7691 break;
230d793d
RS		 7692 }
7693
951553af 7694 return nonzero;
230d793d 7695}
b3728b0e
JW		 7696
7697/* See the macro definition above. */
7698#undef num_sign_bit_copies
230d793d 7699\f
d0ab8cd3 7700/* Return the number of bits at the high-order end of X that are known to
5109d49f
RK		 7701 be equal to the sign bit. X will be used in mode MODE; if MODE is
7702 VOIDmode, X will be used in its own mode. The returned value will always
7703 be between 1 and the number of bits in MODE. */
d0ab8cd3
RK		 7704
7705static int
7706num_sign_bit_copies (x, mode)
7707 rtx x;
7708 enum machine_mode mode;
7709{
7710 enum rtx_code code = GET_CODE (x);
7711 int bitwidth;
7712 int num0, num1, result;
951553af 7713 unsigned HOST_WIDE_INT nonzero;
d0ab8cd3
RK		 7714 rtx tem;
7715
7716 /* If we weren't given a mode, use the mode of X. If the mode is still
1c75dfa4
RK		 7717 VOIDmode, we don't know anything. Likewise if one of the modes is
7718 floating-point. */
d0ab8cd3
RK		 7719
7720 if (mode == VOIDmode)
7721 mode = GET_MODE (x);
7722
1c75dfa4 7723 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
6752e8d2 7724 return 1;
d0ab8cd3
RK		 7725
7726 bitwidth = GET_MODE_BITSIZE (mode);
7727
0f41302f 7728 /* For a smaller object, just ignore the high bits. */
312def2e
RK		 7729 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7730 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7731 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7732
e9a25f70
JL		 7733 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7734 {
0c314d1a
RK		 7735#ifndef WORD_REGISTER_OPERATIONS
7736 /* If this machine does not do all register operations on the entire
7737 register and MODE is wider than the mode of X, we can say nothing
7738 at all about the high-order bits. */
e9a25f70
JL		 7739 return 1;
7740#else
7741 /* Likewise on machines that do, if the mode of the object is smaller
7742 than a word and loads of that size don't sign extend, we can say
7743 nothing about the high order bits. */
7744 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7745#ifdef LOAD_EXTEND_OP
7746 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7747#endif
7748 )
7749 return 1;
0c314d1a 7750#endif
e9a25f70 7751 }
0c314d1a 7752
d0ab8cd3
RK		 7753 switch (code)
7754 {
7755 case REG:
55310dad 7756
ff0dbdd1
RK		 7757#ifdef POINTERS_EXTEND_UNSIGNED
7758 /* If pointers extend signed and this is a pointer in Pmode, say that
7759 all the bits above ptr_mode are known to be sign bit copies. */
7760 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7761 && REGNO_POINTER_FLAG (REGNO (x)))
7762 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7763#endif
7764
55310dad
RK		 7765 if (reg_last_set_value[REGNO (x)] != 0
7766 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7767 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7768 || reg_last_set_label[REGNO (x)] == label_tick)
7769 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7770 return reg_last_set_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7771
7772 tem = get_last_value (x);
7773 if (tem != 0)
7774 return num_sign_bit_copies (tem, mode);
55310dad
RK		 7775
7776 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7777 return reg_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7778 break;
7779
457816e2 7780 case MEM:
8baf60bb 7781#ifdef LOAD_EXTEND_OP
457816e2 7782 /* Some RISC machines sign-extend all loads of smaller than a word. */
8baf60bb
RK		 7783 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7784 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
457816e2 7785#endif
8baf60bb 7786 break;
457816e2 7787
d0ab8cd3
RK		 7788 case CONST_INT:
7789 /* If the constant is negative, take its 1's complement and remask.
7790 Then see how many zero bits we have. */
951553af 7791 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
ac49a949 7792 if (bitwidth <= HOST_BITS_PER_WIDE_INT
951553af
RK		 7793 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7794 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
d0ab8cd3 7795
951553af 7796 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7797
7798 case SUBREG:
c3c2cb37
RK		 7799 /* If this is a SUBREG for a promoted object that is sign-extended
7800 and we are looking at it in a wider mode, we know that at least the
7801 high-order bits are known to be sign bit copies. */
7802
7803 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
dc3e17ad
RK		 7804 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7805 num_sign_bit_copies (SUBREG_REG (x), mode));
c3c2cb37 7806
0f41302f 7807 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7808 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7809 {
7810 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7811 return MAX (1, (num0
7812 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7813 - bitwidth)));
7814 }
457816e2 7815
8baf60bb 7816#ifdef WORD_REGISTER_OPERATIONS
2aec5b7a 7817#ifdef LOAD_EXTEND_OP
8baf60bb
RK		 7818 /* For paradoxical SUBREGs on machines where all register operations
7819 affect the entire register, just look inside. Note that we are
7820 passing MODE to the recursive call, so the number of sign bit copies
7821 will remain relative to that mode, not the inner mode. */
457816e2 7822
2aec5b7a
JW		 7823 /* This works only if loads sign extend. Otherwise, if we get a
7824 reload for the inner part, it may be loaded from the stack, and
7825 then we lose all sign bit copies that existed before the store
7826 to the stack. */
7827
7828 if ((GET_MODE_SIZE (GET_MODE (x))
7829 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7830 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
457816e2 7831 return num_sign_bit_copies (SUBREG_REG (x), mode);
2aec5b7a 7832#endif
457816e2 7833#endif
d0ab8cd3
RK		 7834 break;
7835
7836 case SIGN_EXTRACT:
7837 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7838 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7839 break;
7840
7841 case SIGN_EXTEND:
7842 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7843 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7844
7845 case TRUNCATE:
0f41302f 7846 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7847 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7848 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7849 - bitwidth)));
7850
7851 case NOT:
7852 return num_sign_bit_copies (XEXP (x, 0), mode);
7853
7854 case ROTATE: case ROTATERT:
7855 /* If we are rotating left by a number of bits less than the number
7856 of sign bit copies, we can just subtract that amount from the
7857 number. */
7858 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7859 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7860 {
7861 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7862 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7863 : bitwidth - INTVAL (XEXP (x, 1))));
7864 }
7865 break;
7866
7867 case NEG:
7868 /* In general, this subtracts one sign bit copy. But if the value
7869 is known to be positive, the number of sign bit copies is the
951553af
RK		 7870 same as that of the input. Finally, if the input has just one bit
7871 that might be nonzero, all the bits are copies of the sign bit. */
7872 nonzero = nonzero_bits (XEXP (x, 0), mode);
7873 if (nonzero == 1)
d0ab8cd3
RK		 7874 return bitwidth;
7875
7876 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7877 if (num0 > 1
ac49a949 7878 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7879 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
d0ab8cd3
RK		 7880 num0--;
7881
7882 return num0;
7883
7884 case IOR: case AND: case XOR:
7885 case SMIN: case SMAX: case UMIN: case UMAX:
7886 /* Logical operations will preserve the number of sign-bit copies.
7887 MIN and MAX operations always return one of the operands. */
7888 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7889 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7890 return MIN (num0, num1);
7891
7892 case PLUS: case MINUS:
7893 /* For addition and subtraction, we can have a 1-bit carry. However,
7894 if we are subtracting 1 from a positive number, there will not
7895 be such a carry. Furthermore, if the positive number is known to
7896 be 0 or 1, we know the result is either -1 or 0. */
7897
3e3ea975 7898 if (code == PLUS && XEXP (x, 1) == constm1_rtx
9295e6af 7899 && bitwidth <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 7900 {
951553af
RK		 7901 nonzero = nonzero_bits (XEXP (x, 0), mode);
7902 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7903 return (nonzero == 1 || nonzero == 0 ? bitwidth
7904 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7905 }
7906
7907 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7908 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7909 return MAX (1, MIN (num0, num1) - 1);
7910
7911 case MULT:
7912 /* The number of bits of the product is the sum of the number of
7913 bits of both terms. However, unless one of the terms if known
7914 to be positive, we must allow for an additional bit since negating
7915 a negative number can remove one sign bit copy. */
7916
7917 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7918 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7919
7920 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7921 if (result > 0
9295e6af 7922 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7923 && ((nonzero_bits (XEXP (x, 0), mode)
d0ab8cd3 7924 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
01c82bbb
RK		 7925 && ((nonzero_bits (XEXP (x, 1), mode)
7926 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
d0ab8cd3
RK		 7927 result--;
7928
7929 return MAX (1, result);
7930
7931 case UDIV:
7932 /* The result must be <= the first operand. */
7933 return num_sign_bit_copies (XEXP (x, 0), mode);
7934
7935 case UMOD:
7936 /* The result must be <= the scond operand. */
7937 return num_sign_bit_copies (XEXP (x, 1), mode);
7938
7939 case DIV:
7940 /* Similar to unsigned division, except that we have to worry about
7941 the case where the divisor is negative, in which case we have
7942 to add 1. */
7943 result = num_sign_bit_copies (XEXP (x, 0), mode);
7944 if (result > 1
ac49a949 7945 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7946 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 7947 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7948 result --;
7949
7950 return result;
7951
7952 case MOD:
7953 result = num_sign_bit_copies (XEXP (x, 1), mode);
7954 if (result > 1
ac49a949 7955 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 7956 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 7957 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7958 result --;
7959
7960 return result;
7961
7962 case ASHIFTRT:
7963 /* Shifts by a constant add to the number of bits equal to the
7964 sign bit. */
7965 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7966 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7967 && INTVAL (XEXP (x, 1)) > 0)
7968 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7969
7970 return num0;
7971
7972 case ASHIFT:
d0ab8cd3
RK		 7973 /* Left shifts destroy copies. */
7974 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7975 || INTVAL (XEXP (x, 1)) < 0
7976 || INTVAL (XEXP (x, 1)) >= bitwidth)
7977 return 1;
7978
7979 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7980 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7981
7982 case IF_THEN_ELSE:
7983 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7984 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7985 return MIN (num0, num1);
7986
d0ab8cd3
RK		 7987 case EQ: case NE: case GE: case GT: case LE: case LT:
7988 case GEU: case GTU: case LEU: case LTU:
0802d516
RK		 7989 if (STORE_FLAG_VALUE == -1)
7990 return bitwidth;
e9a25f70
JL		 7991 break;
7992
7993 default:
7994 break;
d0ab8cd3
RK		 7995 }
7996
7997 /* If we haven't been able to figure it out by one of the above rules,
7998 see if some of the high-order bits are known to be zero. If so,
ac49a949
RS		 7999 count those bits and return one less than that amount. If we can't
8000 safely compute the mask for this mode, always return BITWIDTH. */
8001
8002 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6752e8d2 8003 return 1;
d0ab8cd3 8004
951553af 8005 nonzero = nonzero_bits (x, mode);
df6f4086 8006 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
951553af 8007 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8008}
8009\f
1a26b032
RK		 8010/* Return the number of "extended" bits there are in X, when interpreted
8011 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8012 unsigned quantities, this is the number of high-order zero bits.
8013 For signed quantities, this is the number of copies of the sign bit
8014 minus 1. In both case, this function returns the number of "spare"
8015 bits. For example, if two quantities for which this function returns
8016 at least 1 are added, the addition is known not to overflow.
8017
8018 This function will always return 0 unless called during combine, which
8019 implies that it must be called from a define_split. */
8020
8021int
8022extended_count (x, mode, unsignedp)
8023 rtx x;
8024 enum machine_mode mode;
8025 int unsignedp;
8026{
951553af 8027 if (nonzero_sign_valid == 0)
1a26b032
RK		 8028 return 0;
8029
8030 return (unsignedp
ac49a949
RS		 8031 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8032 && (GET_MODE_BITSIZE (mode) - 1
951553af 8033 - floor_log2 (nonzero_bits (x, mode))))
1a26b032
RK		 8034 : num_sign_bit_copies (x, mode) - 1);
8035}
8036\f
230d793d
RS		 8037/* This function is called from `simplify_shift_const' to merge two
8038 outer operations. Specifically, we have already found that we need
8039 to perform operation *POP0 with constant *PCONST0 at the outermost
8040 position. We would now like to also perform OP1 with constant CONST1
8041 (with *POP0 being done last).
8042
8043 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8044 the resulting operation. *PCOMP_P is set to 1 if we would need to
8045 complement the innermost operand, otherwise it is unchanged.
8046
8047 MODE is the mode in which the operation will be done. No bits outside
8048 the width of this mode matter. It is assumed that the width of this mode
5f4f0e22 8049 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
230d793d
RS		 8050
8051 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8052 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8053 result is simply *PCONST0.
8054
8055 If the resulting operation cannot be expressed as one operation, we
8056 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8057
8058static int
8059merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8060 enum rtx_code *pop0;
5f4f0e22 8061 HOST_WIDE_INT *pconst0;
230d793d 8062 enum rtx_code op1;
5f4f0e22 8063 HOST_WIDE_INT const1;
230d793d
RS		 8064 enum machine_mode mode;
8065 int *pcomp_p;
8066{
8067 enum rtx_code op0 = *pop0;
5f4f0e22 8068 HOST_WIDE_INT const0 = *pconst0;
9fa6d012 8069 int width = GET_MODE_BITSIZE (mode);
230d793d
RS		 8070
8071 const0 &= GET_MODE_MASK (mode);
8072 const1 &= GET_MODE_MASK (mode);
8073
8074 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8075 if (op0 == AND)
8076 const1 &= const0;
8077
8078 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8079 if OP0 is SET. */
8080
8081 if (op1 == NIL || op0 == SET)
8082 return 1;
8083
8084 else if (op0 == NIL)
8085 op0 = op1, const0 = const1;
8086
8087 else if (op0 == op1)
8088 {
8089 switch (op0)
8090 {
8091 case AND:
8092 const0 &= const1;
8093 break;
8094 case IOR:
8095 const0 |= const1;
8096 break;
8097 case XOR:
8098 const0 ^= const1;
8099 break;
8100 case PLUS:
8101 const0 += const1;
8102 break;
8103 case NEG:
8104 op0 = NIL;
8105 break;
e9a25f70
JL		 8106 default:
8107 break;
230d793d
RS		 8108 }
8109 }
8110
8111 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8112 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8113 return 0;
8114
8115 /* If the two constants aren't the same, we can't do anything. The
8116 remaining six cases can all be done. */
8117 else if (const0 != const1)
8118 return 0;
8119
8120 else
8121 switch (op0)
8122 {
8123 case IOR:
8124 if (op1 == AND)
8125 /* (a & b) | b == b */
8126 op0 = SET;
8127 else /* op1 == XOR */
8128 /* (a ^ b) | b == a | b */
8129 ;
8130 break;
8131
8132 case XOR:
8133 if (op1 == AND)
8134 /* (a & b) ^ b == (~a) & b */
8135 op0 = AND, *pcomp_p = 1;
8136 else /* op1 == IOR */
8137 /* (a | b) ^ b == a & ~b */
8138 op0 = AND, *pconst0 = ~ const0;
8139 break;
8140
8141 case AND:
8142 if (op1 == IOR)
8143 /* (a | b) & b == b */
8144 op0 = SET;
8145 else /* op1 == XOR */
8146 /* (a ^ b) & b) == (~a) & b */
8147 *pcomp_p = 1;
8148 break;
e9a25f70
JL		 8149 default:
8150 break;
230d793d
RS		 8151 }
8152
8153 /* Check for NO-OP cases. */
8154 const0 &= GET_MODE_MASK (mode);
8155 if (const0 == 0
8156 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8157 op0 = NIL;
8158 else if (const0 == 0 && op0 == AND)
8159 op0 = SET;
8160 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8161 op0 = NIL;
8162
9fa6d012
TG		 8163 /* If this would be an entire word for the target, but is not for
8164 the host, then sign-extend on the host so that the number will look
8165 the same way on the host that it would on the target.
8166
8167 For example, when building a 64 bit alpha hosted 32 bit sparc
8168 targeted compiler, then we want the 32 bit unsigned value -1 to be
8169 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8170 The later confuses the sparc backend. */
8171
8172 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8173 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8174 const0 |= ((HOST_WIDE_INT) (-1) << width);
8175
230d793d
RS		 8176 *pop0 = op0;
8177 *pconst0 = const0;
8178
8179 return 1;
8180}
8181\f
8182/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8183 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8184 that we started with.
8185
8186 The shift is normally computed in the widest mode we find in VAROP, as
8187 long as it isn't a different number of words than RESULT_MODE. Exceptions
8188 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8189
8190static rtx
8191simplify_shift_const (x, code, result_mode, varop, count)
8192 rtx x;
8193 enum rtx_code code;
8194 enum machine_mode result_mode;
8195 rtx varop;
8196 int count;
8197{
8198 enum rtx_code orig_code = code;
8199 int orig_count = count;
8200 enum machine_mode mode = result_mode;
8201 enum machine_mode shift_mode, tmode;
8202 int mode_words
8203 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8204 /* We form (outer_op (code varop count) (outer_const)). */
8205 enum rtx_code outer_op = NIL;
c4e861e8 8206 HOST_WIDE_INT outer_const = 0;
230d793d
RS		 8207 rtx const_rtx;
8208 int complement_p = 0;
8209 rtx new;
8210
8211 /* If we were given an invalid count, don't do anything except exactly
8212 what was requested. */
8213
8214 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8215 {
8216 if (x)
8217 return x;
8218
38a448ca 8219 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
230d793d
RS		 8220 }
8221
8222 /* Unless one of the branches of the `if' in this loop does a `continue',
8223 we will `break' the loop after the `if'. */
8224
8225 while (count != 0)
8226 {
8227 /* If we have an operand of (clobber (const_int 0)), just return that
8228 value. */
8229 if (GET_CODE (varop) == CLOBBER)
8230 return varop;
8231
8232 /* If we discovered we had to complement VAROP, leave. Making a NOT
8233 here would cause an infinite loop. */
8234 if (complement_p)
8235 break;
8236
abc95ed3 8237 /* Convert ROTATERT to ROTATE. */
230d793d
RS		 8238 if (code == ROTATERT)
8239 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8240
230d793d 8241 /* We need to determine what mode we will do the shift in. If the
f6789c77
RK		 8242 shift is a right shift or a ROTATE, we must always do it in the mode
8243 it was originally done in. Otherwise, we can do it in MODE, the
0f41302f 8244 widest mode encountered. */
f6789c77
RK		 8245 shift_mode
8246 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8247 ? result_mode : mode);
230d793d
RS		 8248
8249 /* Handle cases where the count is greater than the size of the mode
8250 minus 1. For ASHIFT, use the size minus one as the count (this can
8251 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8252 take the count modulo the size. For other shifts, the result is
8253 zero.
8254
8255 Since these shifts are being produced by the compiler by combining
8256 multiple operations, each of which are defined, we know what the
8257 result is supposed to be. */
8258
8259 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8260 {
8261 if (code == ASHIFTRT)
8262 count = GET_MODE_BITSIZE (shift_mode) - 1;
8263 else if (code == ROTATE || code == ROTATERT)
8264 count %= GET_MODE_BITSIZE (shift_mode);
8265 else
8266 {
8267 /* We can't simply return zero because there may be an
8268 outer op. */
8269 varop = const0_rtx;
8270 count = 0;
8271 break;
8272 }
8273 }
8274
8275 /* Negative counts are invalid and should not have been made (a
8276 programmer-specified negative count should have been handled
0f41302f 8277 above). */
230d793d
RS		 8278 else if (count < 0)
8279 abort ();
8280
312def2e
RK		 8281 /* An arithmetic right shift of a quantity known to be -1 or 0
8282 is a no-op. */
8283 if (code == ASHIFTRT
8284 && (num_sign_bit_copies (varop, shift_mode)
8285 == GET_MODE_BITSIZE (shift_mode)))
d0ab8cd3 8286 {
312def2e
RK		 8287 count = 0;
8288 break;
8289 }
d0ab8cd3 8290
312def2e
RK		 8291 /* If we are doing an arithmetic right shift and discarding all but
8292 the sign bit copies, this is equivalent to doing a shift by the
8293 bitsize minus one. Convert it into that shift because it will often
8294 allow other simplifications. */
500c518b 8295
312def2e
RK		 8296 if (code == ASHIFTRT
8297 && (count + num_sign_bit_copies (varop, shift_mode)
8298 >= GET_MODE_BITSIZE (shift_mode)))
8299 count = GET_MODE_BITSIZE (shift_mode) - 1;
500c518b 8300
230d793d
RS		 8301 /* We simplify the tests below and elsewhere by converting
8302 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8303 `make_compound_operation' will convert it to a ASHIFTRT for
8304 those machines (such as Vax) that don't have a LSHIFTRT. */
5f4f0e22 8305 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8306 && code == ASHIFTRT
951553af 8307 && ((nonzero_bits (varop, shift_mode)
5f4f0e22
CH		 8308 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8309 == 0))
230d793d
RS		 8310 code = LSHIFTRT;
8311
8312 switch (GET_CODE (varop))
8313 {
8314 case SIGN_EXTEND:
8315 case ZERO_EXTEND:
8316 case SIGN_EXTRACT:
8317 case ZERO_EXTRACT:
8318 new = expand_compound_operation (varop);
8319 if (new != varop)
8320 {
8321 varop = new;
8322 continue;
8323 }
8324 break;
8325
8326 case MEM:
8327 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8328 minus the width of a smaller mode, we can do this with a
8329 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8330 if ((code == ASHIFTRT || code == LSHIFTRT)
8331 && ! mode_dependent_address_p (XEXP (varop, 0))
8332 && ! MEM_VOLATILE_P (varop)
8333 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8334 MODE_INT, 1)) != BLKmode)
8335 {
f76b9db2 8336 if (BYTES_BIG_ENDIAN)
38a448ca 8337 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
f76b9db2 8338 else
38a448ca
RH		 8339 new = gen_rtx_MEM (tmode,
8340 plus_constant (XEXP (varop, 0),
8341 count / BITS_PER_UNIT));
e24b00c8
ILT		 8342 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8343 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8344 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
230d793d
RS		 8345 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8346 : ZERO_EXTEND, mode, new);
8347 count = 0;
8348 continue;
8349 }
8350 break;
8351
8352 case USE:
8353 /* Similar to the case above, except that we can only do this if
8354 the resulting mode is the same as that of the underlying
8355 MEM and adjust the address depending on the *bits* endianness
8356 because of the way that bit-field extract insns are defined. */
8357 if ((code == ASHIFTRT || code == LSHIFTRT)
8358 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8359 MODE_INT, 1)) != BLKmode
8360 && tmode == GET_MODE (XEXP (varop, 0)))
8361 {
f76b9db2
ILT		 8362 if (BITS_BIG_ENDIAN)
8363 new = XEXP (varop, 0);
8364 else
8365 {
8366 new = copy_rtx (XEXP (varop, 0));
8367 SUBST (XEXP (new, 0),
8368 plus_constant (XEXP (new, 0),
8369 count / BITS_PER_UNIT));
8370 }
230d793d
RS		 8371
8372 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8373 : ZERO_EXTEND, mode, new);
8374 count = 0;
8375 continue;
8376 }
8377 break;
8378
8379 case SUBREG:
8380 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8381 the same number of words as what we've seen so far. Then store
8382 the widest mode in MODE. */
f9e67232
RS		 8383 if (subreg_lowpart_p (varop)
8384 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8385 > GET_MODE_SIZE (GET_MODE (varop)))
230d793d
RS		 8386 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8387 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8388 == mode_words))
8389 {
8390 varop = SUBREG_REG (varop);
8391 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8392 mode = GET_MODE (varop);
8393 continue;
8394 }
8395 break;
8396
8397 case MULT:
8398 /* Some machines use MULT instead of ASHIFT because MULT
8399 is cheaper. But it is still better on those machines to
8400 merge two shifts into one. */
8401 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8402 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8403 {
8404 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8405 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
230d793d
RS		 8406 continue;
8407 }
8408 break;
8409
8410 case UDIV:
8411 /* Similar, for when divides are cheaper. */
8412 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8413 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8414 {
8415 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8416 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS		 8417 continue;
8418 }
8419 break;
8420
8421 case ASHIFTRT:
8422 /* If we are extracting just the sign bit of an arithmetic right
8423 shift, that shift is not needed. */
8424 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8425 {
8426 varop = XEXP (varop, 0);
8427 continue;
8428 }
8429
0f41302f 8430 /* ... fall through ... */
230d793d
RS		 8431
8432 case LSHIFTRT:
8433 case ASHIFT:
230d793d
RS		 8434 case ROTATE:
8435 /* Here we have two nested shifts. The result is usually the
8436 AND of a new shift with a mask. We compute the result below. */
8437 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8438 && INTVAL (XEXP (varop, 1)) >= 0
8439 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5f4f0e22
CH		 8440 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8441 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 8442 {
8443 enum rtx_code first_code = GET_CODE (varop);
8444 int first_count = INTVAL (XEXP (varop, 1));
5f4f0e22 8445 unsigned HOST_WIDE_INT mask;
230d793d 8446 rtx mask_rtx;
230d793d 8447
230d793d
RS		 8448 /* We have one common special case. We can't do any merging if
8449 the inner code is an ASHIFTRT of a smaller mode. However, if
8450 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8451 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8452 we can convert it to
8453 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8454 This simplifies certain SIGN_EXTEND operations. */
8455 if (code == ASHIFT && first_code == ASHIFTRT
8456 && (GET_MODE_BITSIZE (result_mode)
8457 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8458 {
8459 /* C3 has the low-order C1 bits zero. */
8460
5f4f0e22
CH		 8461 mask = (GET_MODE_MASK (mode)
8462 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
230d793d 8463
5f4f0e22 8464 varop = simplify_and_const_int (NULL_RTX, result_mode,
230d793d 8465 XEXP (varop, 0), mask);
5f4f0e22 8466 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
230d793d
RS		 8467 varop, count);
8468 count = first_count;
8469 code = ASHIFTRT;
8470 continue;
8471 }
8472
d0ab8cd3
RK		 8473 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8474 than C1 high-order bits equal to the sign bit, we can convert
8475 this to either an ASHIFT or a ASHIFTRT depending on the
8476 two counts.
230d793d
RS		 8477
8478 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8479
8480 if (code == ASHIFTRT && first_code == ASHIFT
8481 && GET_MODE (varop) == shift_mode
d0ab8cd3
RK		 8482 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8483 > first_count))
230d793d 8484 {
d0ab8cd3
RK		 8485 count -= first_count;
8486 if (count < 0)
8487 count = - count, code = ASHIFT;
8488 varop = XEXP (varop, 0);
8489 continue;
230d793d
RS		 8490 }
8491
8492 /* There are some cases we can't do. If CODE is ASHIFTRT,
8493 we can only do this if FIRST_CODE is also ASHIFTRT.
8494
8495 We can't do the case when CODE is ROTATE and FIRST_CODE is
8496 ASHIFTRT.
8497
8498 If the mode of this shift is not the mode of the outer shift,
bdaae9a0 8499 we can't do this if either shift is a right shift or ROTATE.
230d793d
RS		 8500
8501 Finally, we can't do any of these if the mode is too wide
8502 unless the codes are the same.
8503
8504 Handle the case where the shift codes are the same
8505 first. */
8506
8507 if (code == first_code)
8508 {
8509 if (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8510 && (code == ASHIFTRT || code == LSHIFTRT
8511 || code == ROTATE))
230d793d
RS		 8512 break;
8513
8514 count += first_count;
8515 varop = XEXP (varop, 0);
8516 continue;
8517 }
8518
8519 if (code == ASHIFTRT
8520 || (code == ROTATE && first_code == ASHIFTRT)
5f4f0e22 8521 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
230d793d 8522 || (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8523 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8524 || first_code == ROTATE
230d793d
RS		 8525 || code == ROTATE)))
8526 break;
8527
8528 /* To compute the mask to apply after the shift, shift the
951553af 8529 nonzero bits of the inner shift the same way the
230d793d
RS		 8530 outer shift will. */
8531
951553af 8532 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
230d793d
RS		 8533
8534 mask_rtx
8535 = simplify_binary_operation (code, result_mode, mask_rtx,
5f4f0e22 8536 GEN_INT (count));
230d793d
RS		 8537
8538 /* Give up if we can't compute an outer operation to use. */
8539 if (mask_rtx == 0
8540 || GET_CODE (mask_rtx) != CONST_INT
8541 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8542 INTVAL (mask_rtx),
8543 result_mode, &complement_p))
8544 break;
8545
8546 /* If the shifts are in the same direction, we add the
8547 counts. Otherwise, we subtract them. */
8548 if ((code == ASHIFTRT || code == LSHIFTRT)
8549 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8550 count += first_count;
8551 else
8552 count -= first_count;
8553
8554 /* If COUNT is positive, the new shift is usually CODE,
8555 except for the two exceptions below, in which case it is
8556 FIRST_CODE. If the count is negative, FIRST_CODE should
8557 always be used */
8558 if (count > 0
8559 && ((first_code == ROTATE && code == ASHIFT)
8560 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8561 code = first_code;
8562 else if (count < 0)
8563 code = first_code, count = - count;
8564
8565 varop = XEXP (varop, 0);
8566 continue;
8567 }
8568
8569 /* If we have (A << B << C) for any shift, we can convert this to
8570 (A << C << B). This wins if A is a constant. Only try this if
8571 B is not a constant. */
8572
8573 else if (GET_CODE (varop) == code
8574 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8575 && 0 != (new
8576 = simplify_binary_operation (code, mode,
8577 XEXP (varop, 0),
5f4f0e22 8578 GEN_INT (count))))
230d793d
RS		 8579 {
8580 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8581 count = 0;
8582 continue;
8583 }
8584 break;
8585
8586 case NOT:
8587 /* Make this fit the case below. */
8588 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5f4f0e22 8589 GEN_INT (GET_MODE_MASK (mode)));
230d793d
RS		 8590 continue;
8591
8592 case IOR:
8593 case AND:
8594 case XOR:
8595 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8596 with C the size of VAROP - 1 and the shift is logical if
8597 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8598 we have an (le X 0) operation. If we have an arithmetic shift
8599 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8600 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8601
8602 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8603 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8604 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8605 && (code == LSHIFTRT || code == ASHIFTRT)
8606 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8607 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8608 {
8609 count = 0;
8610 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8611 const0_rtx);
8612
8613 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8614 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8615
8616 continue;
8617 }
8618
8619 /* If we have (shift (logical)), move the logical to the outside
8620 to allow it to possibly combine with another logical and the
8621 shift to combine with another shift. This also canonicalizes to
8622 what a ZERO_EXTRACT looks like. Also, some machines have
8623 (and (shift)) insns. */
8624
8625 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8626 && (new = simplify_binary_operation (code, result_mode,
8627 XEXP (varop, 1),
5f4f0e22 8628 GEN_INT (count))) != 0
7d171a1e 8629 && GET_CODE(new) == CONST_INT
230d793d
RS		 8630 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8631 INTVAL (new), result_mode, &complement_p))
8632 {
8633 varop = XEXP (varop, 0);
8634 continue;
8635 }
8636
8637 /* If we can't do that, try to simplify the shift in each arm of the
8638 logical expression, make a new logical expression, and apply
8639 the inverse distributive law. */
8640 {
00d4ca1c 8641 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d 8642 XEXP (varop, 0), count);
00d4ca1c 8643 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d
RS		 8644 XEXP (varop, 1), count);
8645
21a64bf1 8646 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
230d793d
RS		 8647 varop = apply_distributive_law (varop);
8648
8649 count = 0;
8650 }
8651 break;
8652
8653 case EQ:
45620ed4 8654 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
230d793d 8655 says that the sign bit can be tested, FOO has mode MODE, C is
45620ed4
RK		 8656 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8657 that may be nonzero. */
8658 if (code == LSHIFTRT
230d793d
RS		 8659 && XEXP (varop, 1) == const0_rtx
8660 && GET_MODE (XEXP (varop, 0)) == result_mode
8661 && count == GET_MODE_BITSIZE (result_mode) - 1
5f4f0e22 8662 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8663 && ((STORE_FLAG_VALUE
5f4f0e22 8664 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
951553af 8665 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8666 && merge_outer_ops (&outer_op, &outer_const, XOR,
8667 (HOST_WIDE_INT) 1, result_mode,
8668 &complement_p))
230d793d
RS		 8669 {
8670 varop = XEXP (varop, 0);
8671 count = 0;
8672 continue;
8673 }
8674 break;
8675
8676 case NEG:
d0ab8cd3
RK		 8677 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8678 than the number of bits in the mode is equivalent to A. */
8679 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
951553af 8680 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
230d793d 8681 {
d0ab8cd3 8682 varop = XEXP (varop, 0);
230d793d
RS		 8683 count = 0;
8684 continue;
8685 }
8686
8687 /* NEG commutes with ASHIFT since it is multiplication. Move the
8688 NEG outside to allow shifts to combine. */
8689 if (code == ASHIFT
5f4f0e22
CH		 8690 && merge_outer_ops (&outer_op, &outer_const, NEG,
8691 (HOST_WIDE_INT) 0, result_mode,
8692 &complement_p))
230d793d
RS		 8693 {
8694 varop = XEXP (varop, 0);
8695 continue;
8696 }
8697 break;
8698
8699 case PLUS:
d0ab8cd3
RK		 8700 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8701 is one less than the number of bits in the mode is
8702 equivalent to (xor A 1). */
230d793d
RS		 8703 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8704 && XEXP (varop, 1) == constm1_rtx
951553af 8705 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8706 && merge_outer_ops (&outer_op, &outer_const, XOR,
8707 (HOST_WIDE_INT) 1, result_mode,
8708 &complement_p))
230d793d
RS		 8709 {
8710 count = 0;
8711 varop = XEXP (varop, 0);
8712 continue;
8713 }
8714
3f508eca 8715 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
951553af 8716 that might be nonzero in BAR are those being shifted out and those
3f508eca
RK		 8717 bits are known zero in FOO, we can replace the PLUS with FOO.
8718 Similarly in the other operand order. This code occurs when
8719 we are computing the size of a variable-size array. */
8720
8721 if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8722 && count < HOST_BITS_PER_WIDE_INT
951553af
RK		 8723 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8724 && (nonzero_bits (XEXP (varop, 1), result_mode)
8725 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
3f508eca
RK		 8726 {
8727 varop = XEXP (varop, 0);
8728 continue;
8729 }
8730 else if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8731 && count < HOST_BITS_PER_WIDE_INT
ac49a949 8732 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
951553af 8733 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
3f508eca 8734 >> count)
951553af
RK		 8735 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8736 & nonzero_bits (XEXP (varop, 1),
3f508eca
RK		 8737 result_mode)))
8738 {
8739 varop = XEXP (varop, 1);
8740 continue;
8741 }
8742
230d793d
RS		 8743 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8744 if (code == ASHIFT
8745 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8746 && (new = simplify_binary_operation (ASHIFT, result_mode,
8747 XEXP (varop, 1),
5f4f0e22 8748 GEN_INT (count))) != 0
7d171a1e 8749 && GET_CODE(new) == CONST_INT
230d793d
RS		 8750 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8751 INTVAL (new), result_mode, &complement_p))
8752 {
8753 varop = XEXP (varop, 0);
8754 continue;
8755 }
8756 break;
8757
8758 case MINUS:
8759 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8760 with C the size of VAROP - 1 and the shift is logical if
8761 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8762 we have a (gt X 0) operation. If the shift is arithmetic with
8763 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8764 we have a (neg (gt X 0)) operation. */
8765
0802d516
RK		 8766 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8767 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
230d793d 8768 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
230d793d
RS		 8769 && (code == LSHIFTRT || code == ASHIFTRT)
8770 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8771 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8772 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8773 {
8774 count = 0;
8775 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8776 const0_rtx);
8777
8778 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8779 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8780
8781 continue;
8782 }
8783 break;
e9a25f70
JL		 8784
8785 default:
8786 break;
230d793d
RS		 8787 }
8788
8789 break;
8790 }
8791
8792 /* We need to determine what mode to do the shift in. If the shift is
f6789c77
RK		 8793 a right shift or ROTATE, we must always do it in the mode it was
8794 originally done in. Otherwise, we can do it in MODE, the widest mode
8795 encountered. The code we care about is that of the shift that will
8796 actually be done, not the shift that was originally requested. */
8797 shift_mode
8798 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8799 ? result_mode : mode);
230d793d
RS		 8800
8801 /* We have now finished analyzing the shift. The result should be
8802 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8803 OUTER_OP is non-NIL, it is an operation that needs to be applied
8804 to the result of the shift. OUTER_CONST is the relevant constant,
8805 but we must turn off all bits turned off in the shift.
8806
8807 If we were passed a value for X, see if we can use any pieces of
8808 it. If not, make new rtx. */
8809
8810 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8811 && GET_CODE (XEXP (x, 1)) == CONST_INT
8812 && INTVAL (XEXP (x, 1)) == count)
8813 const_rtx = XEXP (x, 1);
8814 else
5f4f0e22 8815 const_rtx = GEN_INT (count);
230d793d
RS		 8816
8817 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8818 && GET_MODE (XEXP (x, 0)) == shift_mode
8819 && SUBREG_REG (XEXP (x, 0)) == varop)
8820 varop = XEXP (x, 0);
8821 else if (GET_MODE (varop) != shift_mode)
8822 varop = gen_lowpart_for_combine (shift_mode, varop);
8823
0f41302f 8824 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 8825 if (GET_CODE (varop) == CLOBBER)
8826 return x ? x : varop;
8827
8828 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8829 if (new != 0)
8830 x = new;
8831 else
8832 {
8833 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8834 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8835
8836 SUBST (XEXP (x, 0), varop);
8837 SUBST (XEXP (x, 1), const_rtx);
8838 }
8839
224eeff2
RK		 8840 /* If we have an outer operation and we just made a shift, it is
8841 possible that we could have simplified the shift were it not
8842 for the outer operation. So try to do the simplification
8843 recursively. */
8844
8845 if (outer_op != NIL && GET_CODE (x) == code
8846 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8847 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8848 INTVAL (XEXP (x, 1)));
8849
230d793d
RS		 8850 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8851 turn off all the bits that the shift would have turned off. */
8852 if (orig_code == LSHIFTRT && result_mode != shift_mode)
5f4f0e22 8853 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
230d793d
RS		 8854 GET_MODE_MASK (result_mode) >> orig_count);
8855
8856 /* Do the remainder of the processing in RESULT_MODE. */
8857 x = gen_lowpart_for_combine (result_mode, x);
8858
8859 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8860 operation. */
8861 if (complement_p)
0c1c8ea6 8862 x = gen_unary (NOT, result_mode, result_mode, x);
230d793d
RS		 8863
8864 if (outer_op != NIL)
8865 {
5f4f0e22 8866 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9fa6d012
TG		 8867 {
8868 int width = GET_MODE_BITSIZE (result_mode);
8869
8870 outer_const &= GET_MODE_MASK (result_mode);
8871
8872 /* If this would be an entire word for the target, but is not for
8873 the host, then sign-extend on the host so that the number will
8874 look the same way on the host that it would on the target.
8875
8876 For example, when building a 64 bit alpha hosted 32 bit sparc
8877 targeted compiler, then we want the 32 bit unsigned value -1 to be
8878 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8879 The later confuses the sparc backend. */
8880
8881 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8882 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8883 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8884 }
230d793d
RS		 8885
8886 if (outer_op == AND)
5f4f0e22 8887 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
230d793d
RS		 8888 else if (outer_op == SET)
8889 /* This means that we have determined that the result is
8890 equivalent to a constant. This should be rare. */
5f4f0e22 8891 x = GEN_INT (outer_const);
230d793d 8892 else if (GET_RTX_CLASS (outer_op) == '1')
0c1c8ea6 8893 x = gen_unary (outer_op, result_mode, result_mode, x);
230d793d 8894 else
5f4f0e22 8895 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
230d793d
RS		 8896 }
8897
8898 return x;
8899}
8900\f
8901/* Like recog, but we receive the address of a pointer to a new pattern.
8902 We try to match the rtx that the pointer points to.
8903 If that fails, we may try to modify or replace the pattern,
8904 storing the replacement into the same pointer object.
8905
8906 Modifications include deletion or addition of CLOBBERs.
8907
8908 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8909 the CLOBBERs are placed.
8910
a29ca9db
RK		 8911 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8912 we had to add.
8913
230d793d
RS		 8914 The value is the final insn code from the pattern ultimately matched,
8915 or -1. */
8916
8917static int
a29ca9db 8918recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
230d793d
RS		 8919 rtx *pnewpat;
8920 rtx insn;
8921 rtx *pnotes;
a29ca9db 8922 int *padded_scratches;
230d793d
RS		 8923{
8924 register rtx pat = *pnewpat;
8925 int insn_code_number;
8926 int num_clobbers_to_add = 0;
8927 int i;
8928 rtx notes = 0;
8929
a29ca9db
RK		 8930 *padded_scratches = 0;
8931
974f4146
RK		 8932 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8933 we use to indicate that something didn't match. If we find such a
8934 thing, force rejection. */
d96023cf 8935 if (GET_CODE (pat) == PARALLEL)
974f4146 8936 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
d96023cf
RK		 8937 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8938 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
974f4146
RK		 8939 return -1;
8940
230d793d
RS		 8941 /* Is the result of combination a valid instruction? */
8942 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8943
8944 /* If it isn't, there is the possibility that we previously had an insn
8945 that clobbered some register as a side effect, but the combined
8946 insn doesn't need to do that. So try once more without the clobbers
8947 unless this represents an ASM insn. */
8948
8949 if (insn_code_number < 0 && ! check_asm_operands (pat)
8950 && GET_CODE (pat) == PARALLEL)
8951 {
8952 int pos;
8953
8954 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8955 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8956 {
8957 if (i != pos)
8958 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8959 pos++;
8960 }
8961
8962 SUBST_INT (XVECLEN (pat, 0), pos);
8963
8964 if (pos == 1)
8965 pat = XVECEXP (pat, 0, 0);
8966
8967 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8968 }
8969
8970 /* If we had any clobbers to add, make a new pattern than contains
8971 them. Then check to make sure that all of them are dead. */
8972 if (num_clobbers_to_add)
8973 {
38a448ca
RH		 8974 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
8975 gen_rtvec (GET_CODE (pat) == PARALLEL
8976 ? XVECLEN (pat, 0) + num_clobbers_to_add
8977 : num_clobbers_to_add + 1));
230d793d
RS		 8978
8979 if (GET_CODE (pat) == PARALLEL)
8980 for (i = 0; i < XVECLEN (pat, 0); i++)
8981 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8982 else
8983 XVECEXP (newpat, 0, 0) = pat;
8984
8985 add_clobbers (newpat, insn_code_number);
8986
8987 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8988 i < XVECLEN (newpat, 0); i++)
8989 {
8990 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8991 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8992 return -1;
a29ca9db
RK		 8993 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8994 (*padded_scratches)++;
38a448ca
RH		 8995 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
8996 XEXP (XVECEXP (newpat, 0, i), 0), notes);
230d793d
RS		 8997 }
8998 pat = newpat;
8999 }
9000
9001 *pnewpat = pat;
9002 *pnotes = notes;
9003
9004 return insn_code_number;
9005}
9006\f
9007/* Like gen_lowpart but for use by combine. In combine it is not possible
9008 to create any new pseudoregs. However, it is safe to create
9009 invalid memory addresses, because combine will try to recognize
9010 them and all they will do is make the combine attempt fail.
9011
9012 If for some reason this cannot do its job, an rtx
9013 (clobber (const_int 0)) is returned.
9014 An insn containing that will not be recognized. */
9015
9016#undef gen_lowpart
9017
9018static rtx
9019gen_lowpart_for_combine (mode, x)
9020 enum machine_mode mode;
9021 register rtx x;
9022{
9023 rtx result;
9024
9025 if (GET_MODE (x) == mode)
9026 return x;
9027
eae957a8
RK		 9028 /* We can only support MODE being wider than a word if X is a
9029 constant integer or has a mode the same size. */
9030
9031 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9032 && ! ((GET_MODE (x) == VOIDmode
9033 && (GET_CODE (x) == CONST_INT
9034 || GET_CODE (x) == CONST_DOUBLE))
9035 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
38a448ca 9036 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9037
9038 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9039 won't know what to do. So we will strip off the SUBREG here and
9040 process normally. */
9041 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9042 {
9043 x = SUBREG_REG (x);
9044 if (GET_MODE (x) == mode)
9045 return x;
9046 }
9047
9048 result = gen_lowpart_common (mode, x);
64bf47a2
RK		 9049 if (result != 0
9050 && GET_CODE (result) == SUBREG
9051 && GET_CODE (SUBREG_REG (result)) == REG
9052 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9053 && (GET_MODE_SIZE (GET_MODE (result))
9054 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
b1f21e0a 9055 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
64bf47a2 9056
230d793d
RS		 9057 if (result)
9058 return result;
9059
9060 if (GET_CODE (x) == MEM)
9061 {
9062 register int offset = 0;
9063 rtx new;
9064
9065 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9066 address. */
9067 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
38a448ca 9068 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9069
9070 /* If we want to refer to something bigger than the original memref,
9071 generate a perverse subreg instead. That will force a reload
9072 of the original memref X. */
9073 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
38a448ca 9074 return gen_rtx_SUBREG (mode, x, 0);
230d793d 9075
f76b9db2
ILT		 9076 if (WORDS_BIG_ENDIAN)
9077 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9078 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9079 if (BYTES_BIG_ENDIAN)
9080 {
9081 /* Adjust the address so that the address-after-the-data is
9082 unchanged. */
9083 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9084 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9085 }
38a448ca 9086 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
230d793d
RS		 9087 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9088 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9089 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9090 return new;
9091 }
9092
9093 /* If X is a comparison operator, rewrite it in a new mode. This
9094 probably won't match, but may allow further simplifications. */
9095 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9096 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9097
9098 /* If we couldn't simplify X any other way, just enclose it in a
9099 SUBREG. Normally, this SUBREG won't match, but some patterns may
a7c99304 9100 include an explicit SUBREG or we may simplify it further in combine. */
230d793d 9101 else
dfbe1b2f
RK		 9102 {
9103 int word = 0;
9104
9105 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9106 word = ((GET_MODE_SIZE (GET_MODE (x))
9107 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9108 / UNITS_PER_WORD);
38a448ca 9109 return gen_rtx_SUBREG (mode, x, word);
dfbe1b2f 9110 }
230d793d
RS		 9111}
9112\f
9113/* Make an rtx expression. This is a subset of gen_rtx and only supports
9114 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9115
9116 If the identical expression was previously in the insn (in the undobuf),
9117 it will be returned. Only if it is not found will a new expression
9118 be made. */
9119
9120/*VARARGS2*/
9121static rtx
4f90e4a0 9122gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
230d793d 9123{
4f90e4a0 9124#ifndef __STDC__
230d793d
RS		 9125 enum rtx_code code;
9126 enum machine_mode mode;
4f90e4a0
RK		 9127#endif
9128 va_list p;
230d793d
RS		 9129 int n_args;
9130 rtx args[3];
9131 int i, j;
9132 char *fmt;
9133 rtx rt;
241cea85 9134 struct undo *undo;
230d793d 9135
4f90e4a0
RK		 9136 VA_START (p, mode);
9137
9138#ifndef __STDC__
230d793d
RS		 9139 code = va_arg (p, enum rtx_code);
9140 mode = va_arg (p, enum machine_mode);
4f90e4a0
RK		 9141#endif
9142
230d793d
RS		 9143 n_args = GET_RTX_LENGTH (code);
9144 fmt = GET_RTX_FORMAT (code);
9145
9146 if (n_args == 0 || n_args > 3)
9147 abort ();
9148
9149 /* Get each arg and verify that it is supposed to be an expression. */
9150 for (j = 0; j < n_args; j++)
9151 {
9152 if (*fmt++ != 'e')
9153 abort ();
9154
9155 args[j] = va_arg (p, rtx);
9156 }
9157
9158 /* See if this is in undobuf. Be sure we don't use objects that came
9159 from another insn; this could produce circular rtl structures. */
9160
241cea85
RK		 9161 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9162 if (!undo->is_int
9163 && GET_CODE (undo->old_contents.r) == code
9164 && GET_MODE (undo->old_contents.r) == mode)
230d793d
RS		 9165 {
9166 for (j = 0; j < n_args; j++)
241cea85 9167 if (XEXP (undo->old_contents.r, j) != args[j])
230d793d
RS		 9168 break;
9169
9170 if (j == n_args)
241cea85 9171 return undo->old_contents.r;
230d793d
RS		 9172 }
9173
9174 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9175 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9176 rt = rtx_alloc (code);
9177 PUT_MODE (rt, mode);
9178 XEXP (rt, 0) = args[0];
9179 if (n_args > 1)
9180 {
9181 XEXP (rt, 1) = args[1];
9182 if (n_args > 2)
9183 XEXP (rt, 2) = args[2];
9184 }
9185 return rt;
9186}
9187
9188/* These routines make binary and unary operations by first seeing if they
9189 fold; if not, a new expression is allocated. */
9190
9191static rtx
9192gen_binary (code, mode, op0, op1)
9193 enum rtx_code code;
9194 enum machine_mode mode;
9195 rtx op0, op1;
9196{
9197 rtx result;
1a26b032
RK		 9198 rtx tem;
9199
9200 if (GET_RTX_CLASS (code) == 'c'
9201 && (GET_CODE (op0) == CONST_INT
9202 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9203 tem = op0, op0 = op1, op1 = tem;
230d793d
RS		 9204
9205 if (GET_RTX_CLASS (code) == '<')
9206 {
9207 enum machine_mode op_mode = GET_MODE (op0);
9210df58
RK		 9208
9209 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
0f41302f 9210 just (REL_OP X Y). */
9210df58
RK		 9211 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9212 {
9213 op1 = XEXP (op0, 1);
9214 op0 = XEXP (op0, 0);
9215 op_mode = GET_MODE (op0);
9216 }
9217
230d793d
RS		 9218 if (op_mode == VOIDmode)
9219 op_mode = GET_MODE (op1);
9220 result = simplify_relational_operation (code, op_mode, op0, op1);
9221 }
9222 else
9223 result = simplify_binary_operation (code, mode, op0, op1);
9224
9225 if (result)
9226 return result;
9227
9228 /* Put complex operands first and constants second. */
9229 if (GET_RTX_CLASS (code) == 'c'
9230 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9231 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9232 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9233 || (GET_CODE (op0) == SUBREG
9234 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9235 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9236 return gen_rtx_combine (code, mode, op1, op0);
9237
9238 return gen_rtx_combine (code, mode, op0, op1);
9239}
9240
9241static rtx
0c1c8ea6 9242gen_unary (code, mode, op0_mode, op0)
230d793d 9243 enum rtx_code code;
0c1c8ea6 9244 enum machine_mode mode, op0_mode;
230d793d
RS		 9245 rtx op0;
9246{
0c1c8ea6 9247 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
230d793d
RS		 9248
9249 if (result)
9250 return result;
9251
9252 return gen_rtx_combine (code, mode, op0);
9253}
9254\f
9255/* Simplify a comparison between *POP0 and *POP1 where CODE is the
9256 comparison code that will be tested.
9257
9258 The result is a possibly different comparison code to use. *POP0 and
9259 *POP1 may be updated.
9260
9261 It is possible that we might detect that a comparison is either always
9262 true or always false. However, we do not perform general constant
5089e22e 9263 folding in combine, so this knowledge isn't useful. Such tautologies
230d793d
RS		 9264 should have been detected earlier. Hence we ignore all such cases. */
9265
9266static enum rtx_code
9267simplify_comparison (code, pop0, pop1)
9268 enum rtx_code code;
9269 rtx *pop0;
9270 rtx *pop1;
9271{
9272 rtx op0 = *pop0;
9273 rtx op1 = *pop1;
9274 rtx tem, tem1;
9275 int i;
9276 enum machine_mode mode, tmode;
9277
9278 /* Try a few ways of applying the same transformation to both operands. */
9279 while (1)
9280 {
3a19aabc
RK		 9281#ifndef WORD_REGISTER_OPERATIONS
9282 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9283 so check specially. */
9284 if (code != GTU && code != GEU && code != LTU && code != LEU
9285 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9286 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9287 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9288 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9289 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9290 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
ad25ba17 9291 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
3a19aabc
RK		 9292 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9293 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9294 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9295 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9296 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9297 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9298 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9299 && (INTVAL (XEXP (op0, 1))
9300 == (GET_MODE_BITSIZE (GET_MODE (op0))
9301 - (GET_MODE_BITSIZE
9302 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9303 {
9304 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9305 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9306 }
9307#endif
9308
230d793d
RS		 9309 /* If both operands are the same constant shift, see if we can ignore the
9310 shift. We can if the shift is a rotate or if the bits shifted out of
951553af 9311 this shift are known to be zero for both inputs and if the type of
230d793d 9312 comparison is compatible with the shift. */
67232b23
RK		 9313 if (GET_CODE (op0) == GET_CODE (op1)
9314 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9315 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
45620ed4 9316 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
67232b23
RK		 9317 && (code != GT && code != LT && code != GE && code != LE))
9318 || (GET_CODE (op0) == ASHIFTRT
9319 && (code != GTU && code != LTU
9320 && code != GEU && code != GEU)))
9321 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9322 && INTVAL (XEXP (op0, 1)) >= 0
9323 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9324 && XEXP (op0, 1) == XEXP (op1, 1))
230d793d
RS		 9325 {
9326 enum machine_mode mode = GET_MODE (op0);
5f4f0e22 9327 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9328 int shift_count = INTVAL (XEXP (op0, 1));
9329
9330 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9331 mask &= (mask >> shift_count) << shift_count;
45620ed4 9332 else if (GET_CODE (op0) == ASHIFT)
230d793d
RS		 9333 mask = (mask & (mask << shift_count)) >> shift_count;
9334
951553af
RK		 9335 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9336 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
230d793d
RS		 9337 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9338 else
9339 break;
9340 }
9341
9342 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9343 SUBREGs are of the same mode, and, in both cases, the AND would
9344 be redundant if the comparison was done in the narrower mode,
9345 do the comparison in the narrower mode (e.g., we are AND'ing with 1
951553af
RK		 9346 and the operand's possibly nonzero bits are 0xffffff01; in that case
9347 if we only care about QImode, we don't need the AND). This case
9348 occurs if the output mode of an scc insn is not SImode and
7e4dc511
RK		 9349 STORE_FLAG_VALUE == 1 (e.g., the 386).
9350
9351 Similarly, check for a case where the AND's are ZERO_EXTEND
9352 operations from some narrower mode even though a SUBREG is not
9353 present. */
230d793d
RS		 9354
9355 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9356 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7e4dc511 9357 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
230d793d 9358 {
7e4dc511
RK		 9359 rtx inner_op0 = XEXP (op0, 0);
9360 rtx inner_op1 = XEXP (op1, 0);
9361 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9362 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9363 int changed = 0;
9364
9365 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9366 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9367 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9368 && (GET_MODE (SUBREG_REG (inner_op0))
9369 == GET_MODE (SUBREG_REG (inner_op1)))
9370 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9371 <= HOST_BITS_PER_WIDE_INT)
01c82bbb
RK		 9372 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9373 GET_MODE (SUBREG_REG (op0)))))
9374 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9375 GET_MODE (SUBREG_REG (inner_op1))))))
7e4dc511
RK		 9376 {
9377 op0 = SUBREG_REG (inner_op0);
9378 op1 = SUBREG_REG (inner_op1);
9379
9380 /* The resulting comparison is always unsigned since we masked
0f41302f 9381 off the original sign bit. */
7e4dc511
RK		 9382 code = unsigned_condition (code);
9383
9384 changed = 1;
9385 }
230d793d 9386
7e4dc511
RK		 9387 else if (c0 == c1)
9388 for (tmode = GET_CLASS_NARROWEST_MODE
9389 (GET_MODE_CLASS (GET_MODE (op0)));
9390 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9391 if (c0 == GET_MODE_MASK (tmode))
9392 {
9393 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9394 op1 = gen_lowpart_for_combine (tmode, inner_op1);
66415c8b 9395 code = unsigned_condition (code);
7e4dc511
RK		 9396 changed = 1;
9397 break;
9398 }
9399
9400 if (! changed)
9401 break;
230d793d 9402 }
3a19aabc 9403
ad25ba17
RK		 9404 /* If both operands are NOT, we can strip off the outer operation
9405 and adjust the comparison code for swapped operands; similarly for
9406 NEG, except that this must be an equality comparison. */
9407 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9408 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9409 && (code == EQ || code == NE)))
9410 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
3a19aabc 9411
230d793d
RS		 9412 else
9413 break;
9414 }
9415
9416 /* If the first operand is a constant, swap the operands and adjust the
3aceff0d
RK		 9417 comparison code appropriately, but don't do this if the second operand
9418 is already a constant integer. */
9419 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
230d793d
RS		 9420 {
9421 tem = op0, op0 = op1, op1 = tem;
9422 code = swap_condition (code);
9423 }
9424
9425 /* We now enter a loop during which we will try to simplify the comparison.
9426 For the most part, we only are concerned with comparisons with zero,
9427 but some things may really be comparisons with zero but not start
9428 out looking that way. */
9429
9430 while (GET_CODE (op1) == CONST_INT)
9431 {
9432 enum machine_mode mode = GET_MODE (op0);
9433 int mode_width = GET_MODE_BITSIZE (mode);
5f4f0e22 9434 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9435 int equality_comparison_p;
9436 int sign_bit_comparison_p;
9437 int unsigned_comparison_p;
5f4f0e22 9438 HOST_WIDE_INT const_op;
230d793d
RS		 9439
9440 /* We only want to handle integral modes. This catches VOIDmode,
9441 CCmode, and the floating-point modes. An exception is that we
9442 can handle VOIDmode if OP0 is a COMPARE or a comparison
9443 operation. */
9444
9445 if (GET_MODE_CLASS (mode) != MODE_INT
9446 && ! (mode == VOIDmode
9447 && (GET_CODE (op0) == COMPARE
9448 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9449 break;
9450
9451 /* Get the constant we are comparing against and turn off all bits
9452 not on in our mode. */
9453 const_op = INTVAL (op1);
5f4f0e22 9454 if (mode_width <= HOST_BITS_PER_WIDE_INT)
4803a34a 9455 const_op &= mask;
230d793d
RS		 9456
9457 /* If we are comparing against a constant power of two and the value
951553af 9458 being compared can only have that single bit nonzero (e.g., it was
230d793d
RS		 9459 `and'ed with that bit), we can replace this with a comparison
9460 with zero. */
9461 if (const_op
9462 && (code == EQ || code == NE || code == GE || code == GEU
9463 || code == LT || code == LTU)
5f4f0e22 9464 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 9465 && exact_log2 (const_op) >= 0
951553af 9466 && nonzero_bits (op0, mode) == const_op)
230d793d
RS		 9467 {
9468 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9469 op1 = const0_rtx, const_op = 0;
9470 }
9471
d0ab8cd3
RK		 9472 /* Similarly, if we are comparing a value known to be either -1 or
9473 0 with -1, change it to the opposite comparison against zero. */
9474
9475 if (const_op == -1
9476 && (code == EQ || code == NE || code == GT || code == LE
9477 || code == GEU || code == LTU)
9478 && num_sign_bit_copies (op0, mode) == mode_width)
9479 {
9480 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9481 op1 = const0_rtx, const_op = 0;
9482 }
9483
230d793d 9484 /* Do some canonicalizations based on the comparison code. We prefer
4803a34a
RK		 9485 comparisons against zero and then prefer equality comparisons.
9486 If we can reduce the size of a constant, we will do that too. */
230d793d
RS		 9487
9488 switch (code)
9489 {
9490 case LT:
4803a34a
RK		 9491 /* < C is equivalent to <= (C - 1) */
9492 if (const_op > 0)
230d793d 9493 {
4803a34a 9494 const_op -= 1;
5f4f0e22 9495 op1 = GEN_INT (const_op);
230d793d
RS		 9496 code = LE;
9497 /* ... fall through to LE case below. */
9498 }
9499 else
9500 break;
9501
9502 case LE:
4803a34a
RK		 9503 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9504 if (const_op < 0)
9505 {
9506 const_op += 1;
5f4f0e22 9507 op1 = GEN_INT (const_op);
4803a34a
RK		 9508 code = LT;
9509 }
230d793d
RS		 9510
9511 /* If we are doing a <= 0 comparison on a value known to have
9512 a zero sign bit, we can replace this with == 0. */
9513 else if (const_op == 0
5f4f0e22 9514 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9515 && (nonzero_bits (op0, mode)
5f4f0e22 9516 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9517 code = EQ;
9518 break;
9519
9520 case GE:
0f41302f 9521 /* >= C is equivalent to > (C - 1). */
4803a34a 9522 if (const_op > 0)
230d793d 9523 {
4803a34a 9524 const_op -= 1;
5f4f0e22 9525 op1 = GEN_INT (const_op);
230d793d
RS		 9526 code = GT;
9527 /* ... fall through to GT below. */
9528 }
9529 else
9530 break;
9531
9532 case GT:
4803a34a
RK		 9533 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9534 if (const_op < 0)
9535 {
9536 const_op += 1;
5f4f0e22 9537 op1 = GEN_INT (const_op);
4803a34a
RK		 9538 code = GE;
9539 }
230d793d
RS		 9540
9541 /* If we are doing a > 0 comparison on a value known to have
9542 a zero sign bit, we can replace this with != 0. */
9543 else if (const_op == 0
5f4f0e22 9544 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9545 && (nonzero_bits (op0, mode)
5f4f0e22 9546 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9547 code = NE;
9548 break;
9549
230d793d 9550 case LTU:
4803a34a
RK		 9551 /* < C is equivalent to <= (C - 1). */
9552 if (const_op > 0)
9553 {
9554 const_op -= 1;
5f4f0e22 9555 op1 = GEN_INT (const_op);
4803a34a 9556 code = LEU;
0f41302f 9557 /* ... fall through ... */
4803a34a 9558 }
d0ab8cd3
RK		 9559
9560 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
f77aada2
JW		 9561 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9562 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9563 {
9564 const_op = 0, op1 = const0_rtx;
9565 code = GE;
9566 break;
9567 }
4803a34a
RK		 9568 else
9569 break;
230d793d
RS		 9570
9571 case LEU:
9572 /* unsigned <= 0 is equivalent to == 0 */
9573 if (const_op == 0)
9574 code = EQ;
d0ab8cd3 9575
0f41302f 9576 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
f77aada2
JW		 9577 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9578 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9579 {
9580 const_op = 0, op1 = const0_rtx;
9581 code = GE;
9582 }
230d793d
RS		 9583 break;
9584
4803a34a
RK		 9585 case GEU:
9586 /* >= C is equivalent to < (C - 1). */
9587 if (const_op > 1)
9588 {
9589 const_op -= 1;
5f4f0e22 9590 op1 = GEN_INT (const_op);
4803a34a 9591 code = GTU;
0f41302f 9592 /* ... fall through ... */
4803a34a 9593 }
d0ab8cd3
RK		 9594
9595 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
f77aada2
JW		 9596 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9597 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9598 {
9599 const_op = 0, op1 = const0_rtx;
9600 code = LT;
8b2e69e1 9601 break;
d0ab8cd3 9602 }
4803a34a
RK		 9603 else
9604 break;
9605
230d793d
RS		 9606 case GTU:
9607 /* unsigned > 0 is equivalent to != 0 */
9608 if (const_op == 0)
9609 code = NE;
d0ab8cd3
RK		 9610
9611 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
f77aada2
JW		 9612 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9613 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9614 {
9615 const_op = 0, op1 = const0_rtx;
9616 code = LT;
9617 }
230d793d 9618 break;
e9a25f70
JL		 9619
9620 default:
9621 break;
230d793d
RS		 9622 }
9623
9624 /* Compute some predicates to simplify code below. */
9625
9626 equality_comparison_p = (code == EQ || code == NE);
9627 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9628 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9629 || code == LEU);
9630
6139ff20
RK		 9631 /* If this is a sign bit comparison and we can do arithmetic in
9632 MODE, say that we will only be needing the sign bit of OP0. */
9633 if (sign_bit_comparison_p
9634 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9635 op0 = force_to_mode (op0, mode,
9636 ((HOST_WIDE_INT) 1
9637 << (GET_MODE_BITSIZE (mode) - 1)),
e3d616e3 9638 NULL_RTX, 0);
6139ff20 9639
230d793d
RS		 9640 /* Now try cases based on the opcode of OP0. If none of the cases
9641 does a "continue", we exit this loop immediately after the
9642 switch. */
9643
9644 switch (GET_CODE (op0))
9645 {
9646 case ZERO_EXTRACT:
9647 /* If we are extracting a single bit from a variable position in
9648 a constant that has only a single bit set and are comparing it
9649 with zero, we can convert this into an equality comparison
d7cd794f 9650 between the position and the location of the single bit. */
230d793d 9651
230d793d
RS		 9652 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9653 && XEXP (op0, 1) == const1_rtx
9654 && equality_comparison_p && const_op == 0
d7cd794f 9655 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
230d793d 9656 {
f76b9db2 9657 if (BITS_BIG_ENDIAN)
d7cd794f 9658#ifdef HAVE_extzv
f76b9db2
ILT		 9659 i = (GET_MODE_BITSIZE
9660 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
d7cd794f
RK		 9661#else
9662 i = BITS_PER_WORD - 1 - i;
230d793d
RS		 9663#endif
9664
9665 op0 = XEXP (op0, 2);
5f4f0e22 9666 op1 = GEN_INT (i);
230d793d
RS		 9667 const_op = i;
9668
9669 /* Result is nonzero iff shift count is equal to I. */
9670 code = reverse_condition (code);
9671 continue;
9672 }
230d793d 9673
0f41302f 9674 /* ... fall through ... */
230d793d
RS		 9675
9676 case SIGN_EXTRACT:
9677 tem = expand_compound_operation (op0);
9678 if (tem != op0)
9679 {
9680 op0 = tem;
9681 continue;
9682 }
9683 break;
9684
9685 case NOT:
9686 /* If testing for equality, we can take the NOT of the constant. */
9687 if (equality_comparison_p
9688 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9689 {
9690 op0 = XEXP (op0, 0);
9691 op1 = tem;
9692 continue;
9693 }
9694
9695 /* If just looking at the sign bit, reverse the sense of the
9696 comparison. */
9697 if (sign_bit_comparison_p)
9698 {
9699 op0 = XEXP (op0, 0);
9700 code = (code == GE ? LT : GE);
9701 continue;
9702 }
9703 break;
9704
9705 case NEG:
9706 /* If testing for equality, we can take the NEG of the constant. */
9707 if (equality_comparison_p
9708 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9709 {
9710 op0 = XEXP (op0, 0);
9711 op1 = tem;
9712 continue;
9713 }
9714
9715 /* The remaining cases only apply to comparisons with zero. */
9716 if (const_op != 0)
9717 break;
9718
9719 /* When X is ABS or is known positive,
9720 (neg X) is < 0 if and only if X != 0. */
9721
9722 if (sign_bit_comparison_p
9723 && (GET_CODE (XEXP (op0, 0)) == ABS
5f4f0e22 9724 || (mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9725 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 9726 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
230d793d
RS		 9727 {
9728 op0 = XEXP (op0, 0);
9729 code = (code == LT ? NE : EQ);
9730 continue;
9731 }
9732
3bed8141 9733 /* If we have NEG of something whose two high-order bits are the
0f41302f 9734 same, we know that "(-a) < 0" is equivalent to "a > 0". */
3bed8141 9735 if (num_sign_bit_copies (op0, mode) >= 2)
230d793d
RS		 9736 {
9737 op0 = XEXP (op0, 0);
9738 code = swap_condition (code);
9739 continue;
9740 }
9741 break;
9742
9743 case ROTATE:
9744 /* If we are testing equality and our count is a constant, we
9745 can perform the inverse operation on our RHS. */
9746 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9747 && (tem = simplify_binary_operation (ROTATERT, mode,
9748 op1, XEXP (op0, 1))) != 0)
9749 {
9750 op0 = XEXP (op0, 0);
9751 op1 = tem;
9752 continue;
9753 }
9754
9755 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9756 a particular bit. Convert it to an AND of a constant of that
9757 bit. This will be converted into a ZERO_EXTRACT. */
9758 if (const_op == 0 && sign_bit_comparison_p
9759 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 9760 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 9761 {
5f4f0e22
CH		 9762 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9763 ((HOST_WIDE_INT) 1
9764 << (mode_width - 1
9765 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 9766 code = (code == LT ? NE : EQ);
9767 continue;
9768 }
9769
0f41302f 9770 /* ... fall through ... */
230d793d
RS		 9771
9772 case ABS:
9773 /* ABS is ignorable inside an equality comparison with zero. */
9774 if (const_op == 0 && equality_comparison_p)
9775 {
9776 op0 = XEXP (op0, 0);
9777 continue;
9778 }
9779 break;
9780
9781
9782 case SIGN_EXTEND:
9783 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9784 to (compare FOO CONST) if CONST fits in FOO's mode and we
9785 are either testing inequality or have an unsigned comparison
9786 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9787 if (! unsigned_comparison_p
9788 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9789 <= HOST_BITS_PER_WIDE_INT)
9790 && ((unsigned HOST_WIDE_INT) const_op
9791 < (((HOST_WIDE_INT) 1
9792 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
230d793d
RS		 9793 {
9794 op0 = XEXP (op0, 0);
9795 continue;
9796 }
9797 break;
9798
9799 case SUBREG:
a687e897 9800 /* Check for the case where we are comparing A - C1 with C2,
abc95ed3 9801 both constants are smaller than 1/2 the maximum positive
a687e897
RK		 9802 value in MODE, and the comparison is equality or unsigned.
9803 In that case, if A is either zero-extended to MODE or has
9804 sufficient sign bits so that the high-order bit in MODE
9805 is a copy of the sign in the inner mode, we can prove that it is
9806 safe to do the operation in the wider mode. This simplifies
9807 many range checks. */
9808
9809 if (mode_width <= HOST_BITS_PER_WIDE_INT
9810 && subreg_lowpart_p (op0)
9811 && GET_CODE (SUBREG_REG (op0)) == PLUS
9812 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9813 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9814 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9815 < GET_MODE_MASK (mode) / 2)
adb7a1cb 9816 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
951553af
RK		 9817 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9818 GET_MODE (SUBREG_REG (op0)))
a687e897
RK		 9819 & ~ GET_MODE_MASK (mode))
9820 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9821 GET_MODE (SUBREG_REG (op0)))
9822 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9823 - GET_MODE_BITSIZE (mode)))))
9824 {
9825 op0 = SUBREG_REG (op0);
9826 continue;
9827 }
9828
fe0cf571
RK		 9829 /* If the inner mode is narrower and we are extracting the low part,
9830 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9831 if (subreg_lowpart_p (op0)
89f1c7f2
RS		 9832 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9833 /* Fall through */ ;
9834 else
230d793d
RS		 9835 break;
9836
0f41302f 9837 /* ... fall through ... */
230d793d
RS		 9838
9839 case ZERO_EXTEND:
9840 if ((unsigned_comparison_p || equality_comparison_p)
9841 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9842 <= HOST_BITS_PER_WIDE_INT)
9843 && ((unsigned HOST_WIDE_INT) const_op
230d793d
RS		 9844 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9845 {
9846 op0 = XEXP (op0, 0);
9847 continue;
9848 }
9849 break;
9850
9851 case PLUS:
20fdd649 9852 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
5089e22e 9853 this for equality comparisons due to pathological cases involving
230d793d 9854 overflows. */
20fdd649
RK		 9855 if (equality_comparison_p
9856 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9857 op1, XEXP (op0, 1))))
230d793d
RS		 9858 {
9859 op0 = XEXP (op0, 0);
9860 op1 = tem;
9861 continue;
9862 }
9863
9864 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9865 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9866 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9867 {
9868 op0 = XEXP (XEXP (op0, 0), 0);
9869 code = (code == LT ? EQ : NE);
9870 continue;
9871 }
9872 break;
9873
9874 case MINUS:
20fdd649
RK		 9875 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9876 (eq B (minus A C)), whichever simplifies. We can only do
9877 this for equality comparisons due to pathological cases involving
9878 overflows. */
9879 if (equality_comparison_p
9880 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9881 XEXP (op0, 1), op1)))
9882 {
9883 op0 = XEXP (op0, 0);
9884 op1 = tem;
9885 continue;
9886 }
9887
9888 if (equality_comparison_p
9889 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9890 XEXP (op0, 0), op1)))
9891 {
9892 op0 = XEXP (op0, 1);
9893 op1 = tem;
9894 continue;
9895 }
9896
230d793d
RS		 9897 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9898 of bits in X minus 1, is one iff X > 0. */
9899 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9900 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9901 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9902 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9903 {
9904 op0 = XEXP (op0, 1);
9905 code = (code == GE ? LE : GT);
9906 continue;
9907 }
9908 break;
9909
9910 case XOR:
9911 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9912 if C is zero or B is a constant. */
9913 if (equality_comparison_p
9914 && 0 != (tem = simplify_binary_operation (XOR, mode,
9915 XEXP (op0, 1), op1)))
9916 {
9917 op0 = XEXP (op0, 0);
9918 op1 = tem;
9919 continue;
9920 }
9921 break;
9922
9923 case EQ: case NE:
9924 case LT: case LTU: case LE: case LEU:
9925 case GT: case GTU: case GE: case GEU:
9926 /* We can't do anything if OP0 is a condition code value, rather
9927 than an actual data value. */
9928 if (const_op != 0
9929#ifdef HAVE_cc0
9930 || XEXP (op0, 0) == cc0_rtx
9931#endif
9932 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9933 break;
9934
9935 /* Get the two operands being compared. */
9936 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9937 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9938 else
9939 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9940
9941 /* Check for the cases where we simply want the result of the
9942 earlier test or the opposite of that result. */
9943 if (code == NE
9944 || (code == EQ && reversible_comparison_p (op0))
5f4f0e22 9945 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
3f508eca 9946 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
230d793d 9947 && (STORE_FLAG_VALUE
5f4f0e22
CH		 9948 & (((HOST_WIDE_INT) 1
9949 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
230d793d
RS		 9950 && (code == LT
9951 || (code == GE && reversible_comparison_p (op0)))))
9952 {
9953 code = (code == LT || code == NE
9954 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9955 op0 = tem, op1 = tem1;
9956 continue;
9957 }
9958 break;
9959
9960 case IOR:
9961 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9962 iff X <= 0. */
9963 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9964 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9965 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9966 {
9967 op0 = XEXP (op0, 1);
9968 code = (code == GE ? GT : LE);
9969 continue;
9970 }
9971 break;
9972
9973 case AND:
9974 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9975 will be converted to a ZERO_EXTRACT later. */
9976 if (const_op == 0 && equality_comparison_p
45620ed4 9977 && GET_CODE (XEXP (op0, 0)) == ASHIFT
230d793d
RS		 9978 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9979 {
9980 op0 = simplify_and_const_int
9981 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9982 XEXP (op0, 1),
9983 XEXP (XEXP (op0, 0), 1)),
5f4f0e22 9984 (HOST_WIDE_INT) 1);
230d793d
RS		 9985 continue;
9986 }
9987
9988 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9989 zero and X is a comparison and C1 and C2 describe only bits set
9990 in STORE_FLAG_VALUE, we can compare with X. */
9991 if (const_op == 0 && equality_comparison_p
5f4f0e22 9992 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 9993 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9994 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9995 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9996 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
5f4f0e22 9997 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 9998 {
9999 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10000 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10001 if ((~ STORE_FLAG_VALUE & mask) == 0
10002 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10003 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10004 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10005 {
10006 op0 = XEXP (XEXP (op0, 0), 0);
10007 continue;
10008 }
10009 }
10010
10011 /* If we are doing an equality comparison of an AND of a bit equal
10012 to the sign bit, replace this with a LT or GE comparison of
10013 the underlying value. */
10014 if (equality_comparison_p
10015 && const_op == 0
10016 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10017 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 10018 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
5f4f0e22 10019 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
230d793d
RS		 10020 {
10021 op0 = XEXP (op0, 0);
10022 code = (code == EQ ? GE : LT);
10023 continue;
10024 }
10025
10026 /* If this AND operation is really a ZERO_EXTEND from a narrower
10027 mode, the constant fits within that mode, and this is either an
10028 equality or unsigned comparison, try to do this comparison in
10029 the narrower mode. */
10030 if ((equality_comparison_p || unsigned_comparison_p)
10031 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10032 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10033 & GET_MODE_MASK (mode))
10034 + 1)) >= 0
10035 && const_op >> i == 0
10036 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10037 {
10038 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10039 continue;
10040 }
10041 break;
10042
10043 case ASHIFT:
45620ed4 10044 /* If we have (compare (ashift FOO N) (const_int C)) and
230d793d 10045 the high order N bits of FOO (N+1 if an inequality comparison)
951553af 10046 are known to be zero, we can do this by comparing FOO with C
230d793d
RS		 10047 shifted right N bits so long as the low-order N bits of C are
10048 zero. */
10049 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10050 && INTVAL (XEXP (op0, 1)) >= 0
10051 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
5f4f0e22
CH		 10052 < HOST_BITS_PER_WIDE_INT)
10053 && ((const_op
34785d05 10054 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
5f4f0e22 10055 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10056 && (nonzero_bits (XEXP (op0, 0), mode)
230d793d
RS		 10057 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10058 + ! equality_comparison_p))) == 0)
10059 {
10060 const_op >>= INTVAL (XEXP (op0, 1));
5f4f0e22 10061 op1 = GEN_INT (const_op);
230d793d
RS		 10062 op0 = XEXP (op0, 0);
10063 continue;
10064 }
10065
dfbe1b2f 10066 /* If we are doing a sign bit comparison, it means we are testing
230d793d 10067 a particular bit. Convert it to the appropriate AND. */
dfbe1b2f 10068 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10069 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 10070 {
5f4f0e22
CH		 10071 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10072 ((HOST_WIDE_INT) 1
10073 << (mode_width - 1
10074 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 10075 code = (code == LT ? NE : EQ);
10076 continue;
10077 }
dfbe1b2f
RK		 10078
10079 /* If this an equality comparison with zero and we are shifting
10080 the low bit to the sign bit, we can convert this to an AND of the
10081 low-order bit. */
10082 if (const_op == 0 && equality_comparison_p
10083 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10084 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10085 {
5f4f0e22
CH		 10086 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10087 (HOST_WIDE_INT) 1);
dfbe1b2f
RK		 10088 continue;
10089 }
230d793d
RS		 10090 break;
10091
10092 case ASHIFTRT:
d0ab8cd3
RK		 10093 /* If this is an equality comparison with zero, we can do this
10094 as a logical shift, which might be much simpler. */
10095 if (equality_comparison_p && const_op == 0
10096 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10097 {
10098 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10099 XEXP (op0, 0),
10100 INTVAL (XEXP (op0, 1)));
10101 continue;
10102 }
10103
230d793d
RS		 10104 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10105 do the comparison in a narrower mode. */
10106 if (! unsigned_comparison_p
10107 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10108 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10109 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10110 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
22331794 10111 MODE_INT, 1)) != BLKmode
5f4f0e22
CH		 10112 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10113 || ((unsigned HOST_WIDE_INT) - const_op
10114 <= GET_MODE_MASK (tmode))))
230d793d
RS		 10115 {
10116 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10117 continue;
10118 }
10119
0f41302f 10120 /* ... fall through ... */
230d793d
RS		 10121 case LSHIFTRT:
10122 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
951553af 10123 the low order N bits of FOO are known to be zero, we can do this
230d793d
RS		 10124 by comparing FOO with C shifted left N bits so long as no
10125 overflow occurs. */
10126 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10127 && INTVAL (XEXP (op0, 1)) >= 0
5f4f0e22
CH		 10128 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10129 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10130 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 10131 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
230d793d
RS		 10132 && (const_op == 0
10133 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10134 < mode_width)))
10135 {
10136 const_op <<= INTVAL (XEXP (op0, 1));
5f4f0e22 10137 op1 = GEN_INT (const_op);
230d793d
RS		 10138 op0 = XEXP (op0, 0);
10139 continue;
10140 }
10141
10142 /* If we are using this shift to extract just the sign bit, we
10143 can replace this with an LT or GE comparison. */
10144 if (const_op == 0
10145 && (equality_comparison_p || sign_bit_comparison_p)
10146 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10147 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10148 {
10149 op0 = XEXP (op0, 0);
10150 code = (code == NE || code == GT ? LT : GE);
10151 continue;
10152 }
10153 break;
e9a25f70
JL		 10154
10155 default:
10156 break;
230d793d
RS		 10157 }
10158
10159 break;
10160 }
10161
10162 /* Now make any compound operations involved in this comparison. Then,
10163 check for an outmost SUBREG on OP0 that isn't doing anything or is
10164 paradoxical. The latter case can only occur when it is known that the
10165 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10166 We can never remove a SUBREG for a non-equality comparison because the
10167 sign bit is in a different place in the underlying object. */
10168
10169 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10170 op1 = make_compound_operation (op1, SET);
10171
10172 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10173 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10174 && (code == NE || code == EQ)
10175 && ((GET_MODE_SIZE (GET_MODE (op0))
10176 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10177 {
10178 op0 = SUBREG_REG (op0);
10179 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10180 }
10181
10182 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10183 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10184 && (code == NE || code == EQ)
ac49a949
RS		 10185 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10186 <= HOST_BITS_PER_WIDE_INT)
951553af 10187 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10188 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10189 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10190 op1),
951553af 10191 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10192 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10193 op0 = SUBREG_REG (op0), op1 = tem;
10194
10195 /* We now do the opposite procedure: Some machines don't have compare
10196 insns in all modes. If OP0's mode is an integer mode smaller than a
10197 word and we can't do a compare in that mode, see if there is a larger
a687e897
RK		 10198 mode for which we can do the compare. There are a number of cases in
10199 which we can use the wider mode. */
230d793d
RS		 10200
10201 mode = GET_MODE (op0);
10202 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10203 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10204 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10205 for (tmode = GET_MODE_WIDER_MODE (mode);
5f4f0e22
CH		 10206 (tmode != VOIDmode
10207 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
230d793d 10208 tmode = GET_MODE_WIDER_MODE (tmode))
a687e897 10209 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
230d793d 10210 {
951553af 10211 /* If the only nonzero bits in OP0 and OP1 are those in the
a687e897
RK		 10212 narrower mode and this is an equality or unsigned comparison,
10213 we can use the wider mode. Similarly for sign-extended
7e4dc511 10214 values, in which case it is true for all comparisons. */
a687e897
RK		 10215 if (((code == EQ || code == NE
10216 || code == GEU || code == GTU || code == LEU || code == LTU)
951553af
RK		 10217 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10218 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
7e4dc511
RK		 10219 || ((num_sign_bit_copies (op0, tmode)
10220 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
a687e897 10221 && (num_sign_bit_copies (op1, tmode)
58744483 10222 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
a687e897
RK		 10223 {
10224 op0 = gen_lowpart_for_combine (tmode, op0);
10225 op1 = gen_lowpart_for_combine (tmode, op1);
10226 break;
10227 }
230d793d 10228
a687e897
RK		 10229 /* If this is a test for negative, we can make an explicit
10230 test of the sign bit. */
10231
10232 if (op1 == const0_rtx && (code == LT || code == GE)
10233 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d 10234 {
a687e897
RK		 10235 op0 = gen_binary (AND, tmode,
10236 gen_lowpart_for_combine (tmode, op0),
5f4f0e22
CH		 10237 GEN_INT ((HOST_WIDE_INT) 1
10238 << (GET_MODE_BITSIZE (mode) - 1)));
230d793d 10239 code = (code == LT) ? NE : EQ;
a687e897 10240 break;
230d793d 10241 }
230d793d
RS		 10242 }
10243
b7a775b2
RK		 10244#ifdef CANONICALIZE_COMPARISON
10245 /* If this machine only supports a subset of valid comparisons, see if we
10246 can convert an unsupported one into a supported one. */
10247 CANONICALIZE_COMPARISON (code, op0, op1);
10248#endif
10249
230d793d
RS		 10250 *pop0 = op0;
10251 *pop1 = op1;
10252
10253 return code;
10254}
10255\f
10256/* Return 1 if we know that X, a comparison operation, is not operating
10257 on a floating-point value or is EQ or NE, meaning that we can safely
10258 reverse it. */
10259
10260static int
10261reversible_comparison_p (x)
10262 rtx x;
10263{
10264 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e 10265 || flag_fast_math
230d793d
RS		 10266 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10267 return 1;
10268
10269 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10270 {
10271 case MODE_INT:
3ad2180a
RK		 10272 case MODE_PARTIAL_INT:
10273 case MODE_COMPLEX_INT:
230d793d
RS		 10274 return 1;
10275
10276 case MODE_CC:
9210df58
RK		 10277 /* If the mode of the condition codes tells us that this is safe,
10278 we need look no further. */
10279 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10280 return 1;
10281
10282 /* Otherwise try and find where the condition codes were last set and
10283 use that. */
230d793d
RS		 10284 x = get_last_value (XEXP (x, 0));
10285 return (x && GET_CODE (x) == COMPARE
3ad2180a 10286 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
e9a25f70
JL		 10287
10288 default:
10289 return 0;
230d793d 10290 }
230d793d
RS		 10291}
10292\f
10293/* Utility function for following routine. Called when X is part of a value
10294 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10295 for each register mentioned. Similar to mention_regs in cse.c */
10296
10297static void
10298update_table_tick (x)
10299 rtx x;
10300{
10301 register enum rtx_code code = GET_CODE (x);
10302 register char *fmt = GET_RTX_FORMAT (code);
10303 register int i;
10304
10305 if (code == REG)
10306 {
10307 int regno = REGNO (x);
10308 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10309 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10310
10311 for (i = regno; i < endregno; i++)
10312 reg_last_set_table_tick[i] = label_tick;
10313
10314 return;
10315 }
10316
10317 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10318 /* Note that we can't have an "E" in values stored; see
10319 get_last_value_validate. */
10320 if (fmt[i] == 'e')
10321 update_table_tick (XEXP (x, i));
10322}
10323
10324/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10325 are saying that the register is clobbered and we no longer know its
7988fd36
RK		 10326 value. If INSN is zero, don't update reg_last_set; this is only permitted
10327 with VALUE also zero and is used to invalidate the register. */
230d793d
RS		 10328
10329static void
10330record_value_for_reg (reg, insn, value)
10331 rtx reg;
10332 rtx insn;
10333 rtx value;
10334{
10335 int regno = REGNO (reg);
10336 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10337 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10338 int i;
10339
10340 /* If VALUE contains REG and we have a previous value for REG, substitute
10341 the previous value. */
10342 if (value && insn && reg_overlap_mentioned_p (reg, value))
10343 {
10344 rtx tem;
10345
10346 /* Set things up so get_last_value is allowed to see anything set up to
10347 our insn. */
10348 subst_low_cuid = INSN_CUID (insn);
10349 tem = get_last_value (reg);
10350
10351 if (tem)
10352 value = replace_rtx (copy_rtx (value), reg, tem);
10353 }
10354
10355 /* For each register modified, show we don't know its value, that
ef026f91
RS		 10356 we don't know about its bitwise content, that its value has been
10357 updated, and that we don't know the location of the death of the
10358 register. */
230d793d
RS		 10359 for (i = regno; i < endregno; i ++)
10360 {
10361 if (insn)
10362 reg_last_set[i] = insn;
10363 reg_last_set_value[i] = 0;
ef026f91
RS		 10364 reg_last_set_mode[i] = 0;
10365 reg_last_set_nonzero_bits[i] = 0;
10366 reg_last_set_sign_bit_copies[i] = 0;
230d793d
RS		 10367 reg_last_death[i] = 0;
10368 }
10369
10370 /* Mark registers that are being referenced in this value. */
10371 if (value)
10372 update_table_tick (value);
10373
10374 /* Now update the status of each register being set.
10375 If someone is using this register in this block, set this register
10376 to invalid since we will get confused between the two lives in this
10377 basic block. This makes using this register always invalid. In cse, we
10378 scan the table to invalidate all entries using this register, but this
10379 is too much work for us. */
10380
10381 for (i = regno; i < endregno; i++)
10382 {
10383 reg_last_set_label[i] = label_tick;
10384 if (value && reg_last_set_table_tick[i] == label_tick)
10385 reg_last_set_invalid[i] = 1;
10386 else
10387 reg_last_set_invalid[i] = 0;
10388 }
10389
10390 /* The value being assigned might refer to X (like in "x++;"). In that
10391 case, we must replace it with (clobber (const_int 0)) to prevent
10392 infinite loops. */
9a893315 10393 if (value && ! get_last_value_validate (&value, insn,
230d793d
RS		 10394 reg_last_set_label[regno], 0))
10395 {
10396 value = copy_rtx (value);
9a893315
JW		 10397 if (! get_last_value_validate (&value, insn,
10398 reg_last_set_label[regno], 1))
230d793d
RS		 10399 value = 0;
10400 }
10401
55310dad
RK		 10402 /* For the main register being modified, update the value, the mode, the
10403 nonzero bits, and the number of sign bit copies. */
10404
230d793d
RS		 10405 reg_last_set_value[regno] = value;
10406
55310dad
RK		 10407 if (value)
10408 {
2afabb48 10409 subst_low_cuid = INSN_CUID (insn);
55310dad
RK		 10410 reg_last_set_mode[regno] = GET_MODE (reg);
10411 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10412 reg_last_set_sign_bit_copies[regno]
10413 = num_sign_bit_copies (value, GET_MODE (reg));
10414 }
230d793d
RS		 10415}
10416
10417/* Used for communication between the following two routines. */
10418static rtx record_dead_insn;
10419
10420/* Called via note_stores from record_dead_and_set_regs to handle one
10421 SET or CLOBBER in an insn. */
10422
10423static void
10424record_dead_and_set_regs_1 (dest, setter)
10425 rtx dest, setter;
10426{
ca89d290
RK		 10427 if (GET_CODE (dest) == SUBREG)
10428 dest = SUBREG_REG (dest);
10429
230d793d
RS		 10430 if (GET_CODE (dest) == REG)
10431 {
10432 /* If we are setting the whole register, we know its value. Otherwise
10433 show that we don't know the value. We can handle SUBREG in
10434 some cases. */
10435 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10436 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10437 else if (GET_CODE (setter) == SET
10438 && GET_CODE (SET_DEST (setter)) == SUBREG
10439 && SUBREG_REG (SET_DEST (setter)) == dest
90bf8081 10440 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
230d793d 10441 && subreg_lowpart_p (SET_DEST (setter)))
d0ab8cd3
RK		 10442 record_value_for_reg (dest, record_dead_insn,
10443 gen_lowpart_for_combine (GET_MODE (dest),
10444 SET_SRC (setter)));
230d793d 10445 else
5f4f0e22 10446 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
230d793d
RS		 10447 }
10448 else if (GET_CODE (dest) == MEM
10449 /* Ignore pushes, they clobber nothing. */
10450 && ! push_operand (dest, GET_MODE (dest)))
10451 mem_last_set = INSN_CUID (record_dead_insn);
10452}
10453
10454/* Update the records of when each REG was most recently set or killed
10455 for the things done by INSN. This is the last thing done in processing
10456 INSN in the combiner loop.
10457
ef026f91
RS		 10458 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10459 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10460 and also the similar information mem_last_set (which insn most recently
10461 modified memory) and last_call_cuid (which insn was the most recent
10462 subroutine call). */
230d793d
RS		 10463
10464static void
10465record_dead_and_set_regs (insn)
10466 rtx insn;
10467{
10468 register rtx link;
55310dad
RK		 10469 int i;
10470
230d793d
RS		 10471 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10472 {
dbc131f3
RK		 10473 if (REG_NOTE_KIND (link) == REG_DEAD
10474 && GET_CODE (XEXP (link, 0)) == REG)
10475 {
10476 int regno = REGNO (XEXP (link, 0));
10477 int endregno
10478 = regno + (regno < FIRST_PSEUDO_REGISTER
10479 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10480 : 1);
dbc131f3
RK		 10481
10482 for (i = regno; i < endregno; i++)
10483 reg_last_death[i] = insn;
10484 }
230d793d 10485 else if (REG_NOTE_KIND (link) == REG_INC)
5f4f0e22 10486 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
230d793d
RS		 10487 }
10488
10489 if (GET_CODE (insn) == CALL_INSN)
55310dad
RK		 10490 {
10491 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10492 if (call_used_regs[i])
10493 {
10494 reg_last_set_value[i] = 0;
ef026f91
RS		 10495 reg_last_set_mode[i] = 0;
10496 reg_last_set_nonzero_bits[i] = 0;
10497 reg_last_set_sign_bit_copies[i] = 0;
55310dad
RK		 10498 reg_last_death[i] = 0;
10499 }
10500
10501 last_call_cuid = mem_last_set = INSN_CUID (insn);
10502 }
230d793d
RS		 10503
10504 record_dead_insn = insn;
10505 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10506}
10507\f
10508/* Utility routine for the following function. Verify that all the registers
10509 mentioned in *LOC are valid when *LOC was part of a value set when
10510 label_tick == TICK. Return 0 if some are not.
10511
10512 If REPLACE is non-zero, replace the invalid reference with
10513 (clobber (const_int 0)) and return 1. This replacement is useful because
10514 we often can get useful information about the form of a value (e.g., if
10515 it was produced by a shift that always produces -1 or 0) even though
10516 we don't know exactly what registers it was produced from. */
10517
10518static int
9a893315 10519get_last_value_validate (loc, insn, tick, replace)
230d793d 10520 rtx *loc;
9a893315 10521 rtx insn;
230d793d
RS		 10522 int tick;
10523 int replace;
10524{
10525 rtx x = *loc;
10526 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10527 int len = GET_RTX_LENGTH (GET_CODE (x));
10528 int i;
10529
10530 if (GET_CODE (x) == REG)
10531 {
10532 int regno = REGNO (x);
10533 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10534 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10535 int j;
10536
10537 for (j = regno; j < endregno; j++)
10538 if (reg_last_set_invalid[j]
10539 /* If this is a pseudo-register that was only set once, it is
10540 always valid. */
b1f21e0a 10541 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
230d793d
RS		 10542 && reg_last_set_label[j] > tick))
10543 {
10544 if (replace)
38a448ca 10545 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 10546 return replace;
10547 }
10548
10549 return 1;
10550 }
9a893315
JW		 10551 /* If this is a memory reference, make sure that there were
10552 no stores after it that might have clobbered the value. We don't
10553 have alias info, so we assume any store invalidates it. */
10554 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10555 && INSN_CUID (insn) <= mem_last_set)
10556 {
10557 if (replace)
38a448ca 10558 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9a893315
JW		 10559 return replace;
10560 }
230d793d
RS		 10561
10562 for (i = 0; i < len; i++)
10563 if ((fmt[i] == 'e'
9a893315 10564 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
230d793d
RS		 10565 /* Don't bother with these. They shouldn't occur anyway. */
10566 || fmt[i] == 'E')
10567 return 0;
10568
10569 /* If we haven't found a reason for it to be invalid, it is valid. */
10570 return 1;
10571}
10572
10573/* Get the last value assigned to X, if known. Some registers
10574 in the value may be replaced with (clobber (const_int 0)) if their value
10575 is known longer known reliably. */
10576
10577static rtx
10578get_last_value (x)
10579 rtx x;
10580{
10581 int regno;
10582 rtx value;
10583
10584 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10585 then convert it to the desired mode. If this is a paradoxical SUBREG,
0f41302f 10586 we cannot predict what values the "extra" bits might have. */
230d793d
RS		 10587 if (GET_CODE (x) == SUBREG
10588 && subreg_lowpart_p (x)
10589 && (GET_MODE_SIZE (GET_MODE (x))
10590 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10591 && (value = get_last_value (SUBREG_REG (x))) != 0)
10592 return gen_lowpart_for_combine (GET_MODE (x), value);
10593
10594 if (GET_CODE (x) != REG)
10595 return 0;
10596
10597 regno = REGNO (x);
10598 value = reg_last_set_value[regno];
10599
0f41302f
MS		 10600 /* If we don't have a value or if it isn't for this basic block,
10601 return 0. */
230d793d
RS		 10602
10603 if (value == 0
b1f21e0a 10604 || (REG_N_SETS (regno) != 1
55310dad 10605 && reg_last_set_label[regno] != label_tick))
230d793d
RS		 10606 return 0;
10607
4255220d 10608 /* If the value was set in a later insn than the ones we are processing,
4090a6b3
RK		 10609 we can't use it even if the register was only set once, but make a quick
10610 check to see if the previous insn set it to something. This is commonly
0d9641d1
JW		 10611 the case when the same pseudo is used by repeated insns.
10612
10613 This does not work if there exists an instruction which is temporarily
10614 not on the insn chain. */
d0ab8cd3 10615
bcd49eb7 10616 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
d0ab8cd3
RK		 10617 {
10618 rtx insn, set;
10619
bcd49eb7
JW		 10620 /* We can not do anything useful in this case, because there is
10621 an instruction which is not on the insn chain. */
10622 if (subst_prev_insn)
10623 return 0;
10624
4255220d
JW		 10625 /* Skip over USE insns. They are not useful here, and they may have
10626 been made by combine, in which case they do not have a INSN_CUID
d6c80562 10627 value. We can't use prev_real_insn, because that would incorrectly
e340018d
JW		 10628 take us backwards across labels. Skip over BARRIERs also, since
10629 they could have been made by combine. If we see one, we must be
10630 optimizing dead code, so it doesn't matter what we do. */
d6c80562
JW		 10631 for (insn = prev_nonnote_insn (subst_insn);
10632 insn && ((GET_CODE (insn) == INSN
10633 && GET_CODE (PATTERN (insn)) == USE)
e340018d 10634 || GET_CODE (insn) == BARRIER
4255220d 10635 || INSN_CUID (insn) >= subst_low_cuid);
d6c80562 10636 insn = prev_nonnote_insn (insn))
3adde2a5 10637 ;
d0ab8cd3
RK		 10638
10639 if (insn
10640 && (set = single_set (insn)) != 0
10641 && rtx_equal_p (SET_DEST (set), x))
10642 {
10643 value = SET_SRC (set);
10644
10645 /* Make sure that VALUE doesn't reference X. Replace any
ddd5a7c1 10646 explicit references with a CLOBBER. If there are any remaining
d0ab8cd3
RK		 10647 references (rare), don't use the value. */
10648
10649 if (reg_mentioned_p (x, value))
10650 value = replace_rtx (copy_rtx (value), x,
38a448ca 10651 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
d0ab8cd3
RK		 10652
10653 if (reg_overlap_mentioned_p (x, value))
10654 return 0;
10655 }
10656 else
10657 return 0;
10658 }
10659
10660 /* If the value has all its registers valid, return it. */
9a893315
JW		 10661 if (get_last_value_validate (&value, reg_last_set[regno],
10662 reg_last_set_label[regno], 0))
230d793d
RS		 10663 return value;
10664
10665 /* Otherwise, make a copy and replace any invalid register with
10666 (clobber (const_int 0)). If that fails for some reason, return 0. */
10667
10668 value = copy_rtx (value);
9a893315
JW		 10669 if (get_last_value_validate (&value, reg_last_set[regno],
10670 reg_last_set_label[regno], 1))
230d793d
RS		 10671 return value;
10672
10673 return 0;
10674}
10675\f
10676/* Return nonzero if expression X refers to a REG or to memory
10677 that is set in an instruction more recent than FROM_CUID. */
10678
10679static int
10680use_crosses_set_p (x, from_cuid)
10681 register rtx x;
10682 int from_cuid;
10683{
10684 register char *fmt;
10685 register int i;
10686 register enum rtx_code code = GET_CODE (x);
10687
10688 if (code == REG)
10689 {
10690 register int regno = REGNO (x);
e28f5732
RK		 10691 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10692 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10693
230d793d
RS		 10694#ifdef PUSH_ROUNDING
10695 /* Don't allow uses of the stack pointer to be moved,
10696 because we don't know whether the move crosses a push insn. */
10697 if (regno == STACK_POINTER_REGNUM)
10698 return 1;
10699#endif
e28f5732
RK		 10700 for (;regno < endreg; regno++)
10701 if (reg_last_set[regno]
10702 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10703 return 1;
10704 return 0;
230d793d
RS		 10705 }
10706
10707 if (code == MEM && mem_last_set > from_cuid)
10708 return 1;
10709
10710 fmt = GET_RTX_FORMAT (code);
10711
10712 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10713 {
10714 if (fmt[i] == 'E')
10715 {
10716 register int j;
10717 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10718 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10719 return 1;
10720 }
10721 else if (fmt[i] == 'e'
10722 && use_crosses_set_p (XEXP (x, i), from_cuid))
10723 return 1;
10724 }
10725 return 0;
10726}
10727\f
10728/* Define three variables used for communication between the following
10729 routines. */
10730
10731static int reg_dead_regno, reg_dead_endregno;
10732static int reg_dead_flag;
10733
10734/* Function called via note_stores from reg_dead_at_p.
10735
ddd5a7c1 10736 If DEST is within [reg_dead_regno, reg_dead_endregno), set
230d793d
RS		 10737 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10738
10739static void
10740reg_dead_at_p_1 (dest, x)
10741 rtx dest;
10742 rtx x;
10743{
10744 int regno, endregno;
10745
10746 if (GET_CODE (dest) != REG)
10747 return;
10748
10749 regno = REGNO (dest);
10750 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10751 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10752
10753 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10754 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10755}
10756
10757/* Return non-zero if REG is known to be dead at INSN.
10758
10759 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10760 referencing REG, it is dead. If we hit a SET referencing REG, it is
10761 live. Otherwise, see if it is live or dead at the start of the basic
6e25d159
RK		 10762 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10763 must be assumed to be always live. */
230d793d
RS		 10764
10765static int
10766reg_dead_at_p (reg, insn)
10767 rtx reg;
10768 rtx insn;
10769{
10770 int block, i;
10771
10772 /* Set variables for reg_dead_at_p_1. */
10773 reg_dead_regno = REGNO (reg);
10774 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10775 ? HARD_REGNO_NREGS (reg_dead_regno,
10776 GET_MODE (reg))
10777 : 1);
10778
10779 reg_dead_flag = 0;
10780
6e25d159
RK		 10781 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10782 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10783 {
10784 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10785 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10786 return 0;
10787 }
10788
230d793d
RS		 10789 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10790 beginning of function. */
60715d0b 10791 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
230d793d
RS		 10792 insn = prev_nonnote_insn (insn))
10793 {
10794 note_stores (PATTERN (insn), reg_dead_at_p_1);
10795 if (reg_dead_flag)
10796 return reg_dead_flag == 1 ? 1 : 0;
10797
10798 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10799 return 1;
10800 }
10801
10802 /* Get the basic block number that we were in. */
10803 if (insn == 0)
10804 block = 0;
10805 else
10806 {
10807 for (block = 0; block < n_basic_blocks; block++)
10808 if (insn == basic_block_head[block])
10809 break;
10810
10811 if (block == n_basic_blocks)
10812 return 0;
10813 }
10814
10815 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8e08106d 10816 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
230d793d
RS		 10817 return 0;
10818
10819 return 1;
10820}
6e25d159
RK		 10821\f
10822/* Note hard registers in X that are used. This code is similar to
10823 that in flow.c, but much simpler since we don't care about pseudos. */
10824
10825static void
10826mark_used_regs_combine (x)
10827 rtx x;
10828{
10829 register RTX_CODE code = GET_CODE (x);
10830 register int regno;
10831 int i;
10832
10833 switch (code)
10834 {
10835 case LABEL_REF:
10836 case SYMBOL_REF:
10837 case CONST_INT:
10838 case CONST:
10839 case CONST_DOUBLE:
10840 case PC:
10841 case ADDR_VEC:
10842 case ADDR_DIFF_VEC:
10843 case ASM_INPUT:
10844#ifdef HAVE_cc0
10845 /* CC0 must die in the insn after it is set, so we don't need to take
10846 special note of it here. */
10847 case CC0:
10848#endif
10849 return;
10850
10851 case CLOBBER:
10852 /* If we are clobbering a MEM, mark any hard registers inside the
10853 address as used. */
10854 if (GET_CODE (XEXP (x, 0)) == MEM)
10855 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10856 return;
10857
10858 case REG:
10859 regno = REGNO (x);
10860 /* A hard reg in a wide mode may really be multiple registers.
10861 If so, mark all of them just like the first. */
10862 if (regno < FIRST_PSEUDO_REGISTER)
10863 {
10864 /* None of this applies to the stack, frame or arg pointers */
10865 if (regno == STACK_POINTER_REGNUM
10866#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10867 || regno == HARD_FRAME_POINTER_REGNUM
10868#endif
10869#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10870 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10871#endif
10872 || regno == FRAME_POINTER_REGNUM)
10873 return;
10874
10875 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10876 while (i-- > 0)
10877 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10878 }
10879 return;
10880
10881 case SET:
10882 {
10883 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10884 the address. */
10885 register rtx testreg = SET_DEST (x);
10886
e048778f
RK		 10887 while (GET_CODE (testreg) == SUBREG
10888 || GET_CODE (testreg) == ZERO_EXTRACT
10889 || GET_CODE (testreg) == SIGN_EXTRACT
10890 || GET_CODE (testreg) == STRICT_LOW_PART)
6e25d159
RK		 10891 testreg = XEXP (testreg, 0);
10892
10893 if (GET_CODE (testreg) == MEM)
10894 mark_used_regs_combine (XEXP (testreg, 0));
10895
10896 mark_used_regs_combine (SET_SRC (x));
6e25d159 10897 }
e9a25f70
JL		 10898 return;
10899
10900 default:
10901 break;
6e25d159
RK		 10902 }
10903
10904 /* Recursively scan the operands of this expression. */
10905
10906 {
10907 register char *fmt = GET_RTX_FORMAT (code);
10908
10909 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10910 {
10911 if (fmt[i] == 'e')
10912 mark_used_regs_combine (XEXP (x, i));
10913 else if (fmt[i] == 'E')
10914 {
10915 register int j;
10916
10917 for (j = 0; j < XVECLEN (x, i); j++)
10918 mark_used_regs_combine (XVECEXP (x, i, j));
10919 }
10920 }
10921 }
10922}
10923
230d793d
RS		 10924\f
10925/* Remove register number REGNO from the dead registers list of INSN.
10926
10927 Return the note used to record the death, if there was one. */
10928
10929rtx
10930remove_death (regno, insn)
10931 int regno;
10932 rtx insn;
10933{
10934 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10935
10936 if (note)
1a26b032 10937 {
b1f21e0a 10938 REG_N_DEATHS (regno)--;
1a26b032
RK		 10939 remove_note (insn, note);
10940 }
230d793d
RS		 10941
10942 return note;
10943}
10944
10945/* For each register (hardware or pseudo) used within expression X, if its
10946 death is in an instruction with cuid between FROM_CUID (inclusive) and
10947 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10948 list headed by PNOTES.
10949
6eb12cef
RK		 10950 That said, don't move registers killed by maybe_kill_insn.
10951
230d793d
RS		 10952 This is done when X is being merged by combination into TO_INSN. These
10953 notes will then be distributed as needed. */
10954
10955static void
6eb12cef 10956move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
230d793d 10957 rtx x;
6eb12cef 10958 rtx maybe_kill_insn;
230d793d
RS		 10959 int from_cuid;
10960 rtx to_insn;
10961 rtx *pnotes;
10962{
10963 register char *fmt;
10964 register int len, i;
10965 register enum rtx_code code = GET_CODE (x);
10966
10967 if (code == REG)
10968 {
10969 register int regno = REGNO (x);
10970 register rtx where_dead = reg_last_death[regno];
e340018d
JW		 10971 register rtx before_dead, after_dead;
10972
6eb12cef
RK		 10973 /* Don't move the register if it gets killed in between from and to */
10974 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10975 && !reg_referenced_p (x, maybe_kill_insn))
10976 return;
10977
e340018d
JW		 10978 /* WHERE_DEAD could be a USE insn made by combine, so first we
10979 make sure that we have insns with valid INSN_CUID values. */
10980 before_dead = where_dead;
10981 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10982 before_dead = PREV_INSN (before_dead);
10983 after_dead = where_dead;
10984 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10985 after_dead = NEXT_INSN (after_dead);
10986
10987 if (before_dead && after_dead
10988 && INSN_CUID (before_dead) >= from_cuid
10989 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10990 || (where_dead != after_dead
10991 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
230d793d 10992 {
dbc131f3 10993 rtx note = remove_death (regno, where_dead);
230d793d
RS		 10994
10995 /* It is possible for the call above to return 0. This can occur
10996 when reg_last_death points to I2 or I1 that we combined with.
dbc131f3
RK		 10997 In that case make a new note.
10998
10999 We must also check for the case where X is a hard register
11000 and NOTE is a death note for a range of hard registers
11001 including X. In that case, we must put REG_DEAD notes for
11002 the remaining registers in place of NOTE. */
11003
11004 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11005 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
24e46fc4 11006 > GET_MODE_SIZE (GET_MODE (x))))
dbc131f3
RK		 11007 {
11008 int deadregno = REGNO (XEXP (note, 0));
11009 int deadend
11010 = (deadregno + HARD_REGNO_NREGS (deadregno,
11011 GET_MODE (XEXP (note, 0))));
11012 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11013 int i;
11014
11015 for (i = deadregno; i < deadend; i++)
11016 if (i < regno || i >= ourend)
11017 REG_NOTES (where_dead)
38a448ca
RH		 11018 = gen_rtx_EXPR_LIST (REG_DEAD,
11019 gen_rtx_REG (reg_raw_mode[i], i),
11020 REG_NOTES (where_dead));
dbc131f3 11021 }
24e46fc4
JW		 11022 /* If we didn't find any note, or if we found a REG_DEAD note that
11023 covers only part of the given reg, and we have a multi-reg hard
fabd69e8
RK		 11024 register, then to be safe we must check for REG_DEAD notes
11025 for each register other than the first. They could have
11026 their own REG_DEAD notes lying around. */
24e46fc4
JW		 11027 else if ((note == 0
11028 || (note != 0
11029 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11030 < GET_MODE_SIZE (GET_MODE (x)))))
11031 && regno < FIRST_PSEUDO_REGISTER
fabd69e8
RK		 11032 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11033 {
11034 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
24e46fc4 11035 int i, offset;
fabd69e8
RK		 11036 rtx oldnotes = 0;
11037
24e46fc4
JW		 11038 if (note)
11039 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11040 else
11041 offset = 1;
11042
11043 for (i = regno + offset; i < ourend; i++)
38a448ca 11044 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
6eb12cef 11045 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
fabd69e8 11046 }
230d793d 11047
dbc131f3 11048 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
230d793d
RS		 11049 {
11050 XEXP (note, 1) = *pnotes;
11051 *pnotes = note;
11052 }
11053 else
38a448ca 11054 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
1a26b032 11055
b1f21e0a 11056 REG_N_DEATHS (regno)++;
230d793d
RS		 11057 }
11058
11059 return;
11060 }
11061
11062 else if (GET_CODE (x) == SET)
11063 {
11064 rtx dest = SET_DEST (x);
11065
6eb12cef 11066 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d 11067
a7c99304
RK		 11068 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11069 that accesses one word of a multi-word item, some
11070 piece of everything register in the expression is used by
11071 this insn, so remove any old death. */
11072
11073 if (GET_CODE (dest) == ZERO_EXTRACT
11074 || GET_CODE (dest) == STRICT_LOW_PART
11075 || (GET_CODE (dest) == SUBREG
11076 && (((GET_MODE_SIZE (GET_MODE (dest))
11077 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11078 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11079 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
230d793d 11080 {
6eb12cef 11081 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
a7c99304 11082 return;
230d793d
RS		 11083 }
11084
a7c99304
RK		 11085 /* If this is some other SUBREG, we know it replaces the entire
11086 value, so use that as the destination. */
11087 if (GET_CODE (dest) == SUBREG)
11088 dest = SUBREG_REG (dest);
11089
11090 /* If this is a MEM, adjust deaths of anything used in the address.
11091 For a REG (the only other possibility), the entire value is
11092 being replaced so the old value is not used in this insn. */
230d793d
RS		 11093
11094 if (GET_CODE (dest) == MEM)
6eb12cef
RK		 11095 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11096 to_insn, pnotes);
230d793d
RS		 11097 return;
11098 }
11099
11100 else if (GET_CODE (x) == CLOBBER)
11101 return;
11102
11103 len = GET_RTX_LENGTH (code);
11104 fmt = GET_RTX_FORMAT (code);
11105
11106 for (i = 0; i < len; i++)
11107 {
11108 if (fmt[i] == 'E')
11109 {
11110 register int j;
11111 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6eb12cef
RK		 11112 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11113 to_insn, pnotes);
230d793d
RS		 11114 }
11115 else if (fmt[i] == 'e')
6eb12cef 11116 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d
RS		 11117 }
11118}
11119\f
a7c99304
RK		 11120/* Return 1 if X is the target of a bit-field assignment in BODY, the
11121 pattern of an insn. X must be a REG. */
230d793d
RS		 11122
11123static int
a7c99304
RK		 11124reg_bitfield_target_p (x, body)
11125 rtx x;
230d793d
RS		 11126 rtx body;
11127{
11128 int i;
11129
11130 if (GET_CODE (body) == SET)
a7c99304
RK		 11131 {
11132 rtx dest = SET_DEST (body);
11133 rtx target;
11134 int regno, tregno, endregno, endtregno;
11135
11136 if (GET_CODE (dest) == ZERO_EXTRACT)
11137 target = XEXP (dest, 0);
11138 else if (GET_CODE (dest) == STRICT_LOW_PART)
11139 target = SUBREG_REG (XEXP (dest, 0));
11140 else
11141 return 0;
11142
11143 if (GET_CODE (target) == SUBREG)
11144 target = SUBREG_REG (target);
11145
11146 if (GET_CODE (target) != REG)
11147 return 0;
11148
11149 tregno = REGNO (target), regno = REGNO (x);
11150 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11151 return target == x;
11152
11153 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11154 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11155
11156 return endregno > tregno && regno < endtregno;
11157 }
230d793d
RS		 11158
11159 else if (GET_CODE (body) == PARALLEL)
11160 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
a7c99304 11161 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
230d793d
RS		 11162 return 1;
11163
11164 return 0;
11165}
11166\f
11167/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11168 as appropriate. I3 and I2 are the insns resulting from the combination
11169 insns including FROM (I2 may be zero).
11170
11171 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11172 not need REG_DEAD notes because they are being substituted for. This
11173 saves searching in the most common cases.
11174
11175 Each note in the list is either ignored or placed on some insns, depending
11176 on the type of note. */
11177
11178static void
11179distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11180 rtx notes;
11181 rtx from_insn;
11182 rtx i3, i2;
11183 rtx elim_i2, elim_i1;
11184{
11185 rtx note, next_note;
11186 rtx tem;
11187
11188 for (note = notes; note; note = next_note)
11189 {
11190 rtx place = 0, place2 = 0;
11191
11192 /* If this NOTE references a pseudo register, ensure it references
11193 the latest copy of that register. */
11194 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11195 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11196 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11197
11198 next_note = XEXP (note, 1);
11199 switch (REG_NOTE_KIND (note))
11200 {
c9903b44
DE		 11201 case REG_BR_PROB:
11202 case REG_EXEC_COUNT:
11203 /* Doesn't matter much where we put this, as long as it's somewhere.
11204 It is preferable to keep these notes on branches, which is most
11205 likely to be i3. */
11206 place = i3;
11207 break;
11208
230d793d 11209 case REG_UNUSED:
07d0cbdd 11210 /* Any clobbers for i3 may still exist, and so we must process
176c9e6b
JW		 11211 REG_UNUSED notes from that insn.
11212
11213 Any clobbers from i2 or i1 can only exist if they were added by
11214 recog_for_combine. In that case, recog_for_combine created the
11215 necessary REG_UNUSED notes. Trying to keep any original
11216 REG_UNUSED notes from these insns can cause incorrect output
11217 if it is for the same register as the original i3 dest.
11218 In that case, we will notice that the register is set in i3,
11219 and then add a REG_UNUSED note for the destination of i3, which
07d0cbdd
JW		 11220 is wrong. However, it is possible to have REG_UNUSED notes from
11221 i2 or i1 for register which were both used and clobbered, so
11222 we keep notes from i2 or i1 if they will turn into REG_DEAD
11223 notes. */
176c9e6b 11224
230d793d
RS		 11225 /* If this register is set or clobbered in I3, put the note there
11226 unless there is one already. */
07d0cbdd 11227 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
230d793d 11228 {
07d0cbdd
JW		 11229 if (from_insn != i3)
11230 break;
11231
230d793d
RS		 11232 if (! (GET_CODE (XEXP (note, 0)) == REG
11233 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11234 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11235 place = i3;
11236 }
11237 /* Otherwise, if this register is used by I3, then this register
11238 now dies here, so we must put a REG_DEAD note here unless there
11239 is one already. */
11240 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11241 && ! (GET_CODE (XEXP (note, 0)) == REG
11242 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11243 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11244 {
11245 PUT_REG_NOTE_KIND (note, REG_DEAD);
11246 place = i3;
11247 }
11248 break;
11249
11250 case REG_EQUAL:
11251 case REG_EQUIV:
11252 case REG_NONNEG:
9ae8ffe7 11253 case REG_NOALIAS:
230d793d
RS		 11254 /* These notes say something about results of an insn. We can
11255 only support them if they used to be on I3 in which case they
a687e897
RK		 11256 remain on I3. Otherwise they are ignored.
11257
11258 If the note refers to an expression that is not a constant, we
11259 must also ignore the note since we cannot tell whether the
11260 equivalence is still true. It might be possible to do
11261 slightly better than this (we only have a problem if I2DEST
11262 or I1DEST is present in the expression), but it doesn't
11263 seem worth the trouble. */
11264
11265 if (from_insn == i3
11266 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
230d793d
RS		 11267 place = i3;
11268 break;
11269
11270 case REG_INC:
11271 case REG_NO_CONFLICT:
11272 case REG_LABEL:
11273 /* These notes say something about how a register is used. They must
11274 be present on any use of the register in I2 or I3. */
11275 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11276 place = i3;
11277
11278 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11279 {
11280 if (place)
11281 place2 = i2;
11282 else
11283 place = i2;
11284 }
11285 break;
11286
11287 case REG_WAS_0:
11288 /* It is too much trouble to try to see if this note is still
11289 correct in all situations. It is better to simply delete it. */
11290 break;
11291
11292 case REG_RETVAL:
11293 /* If the insn previously containing this note still exists,
11294 put it back where it was. Otherwise move it to the previous
11295 insn. Adjust the corresponding REG_LIBCALL note. */
11296 if (GET_CODE (from_insn) != NOTE)
11297 place = from_insn;
11298 else
11299 {
5f4f0e22 11300 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
230d793d
RS		 11301 place = prev_real_insn (from_insn);
11302 if (tem && place)
11303 XEXP (tem, 0) = place;
11304 }
11305 break;
11306
11307 case REG_LIBCALL:
11308 /* This is handled similarly to REG_RETVAL. */
11309 if (GET_CODE (from_insn) != NOTE)
11310 place = from_insn;
11311 else
11312 {
5f4f0e22 11313 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
230d793d
RS		 11314 place = next_real_insn (from_insn);
11315 if (tem && place)
11316 XEXP (tem, 0) = place;
11317 }
11318 break;
11319
11320 case REG_DEAD:
11321 /* If the register is used as an input in I3, it dies there.
11322 Similarly for I2, if it is non-zero and adjacent to I3.
11323
11324 If the register is not used as an input in either I3 or I2
11325 and it is not one of the registers we were supposed to eliminate,
11326 there are two possibilities. We might have a non-adjacent I2
11327 or we might have somehow eliminated an additional register
11328 from a computation. For example, we might have had A & B where
11329 we discover that B will always be zero. In this case we will
11330 eliminate the reference to A.
11331
11332 In both cases, we must search to see if we can find a previous
11333 use of A and put the death note there. */
11334
6e2d1486
RK		 11335 if (from_insn
11336 && GET_CODE (from_insn) == CALL_INSN
11337 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11338 place = from_insn;
11339 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
230d793d
RS		 11340 place = i3;
11341 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11342 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11343 place = i2;
11344
11345 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11346 break;
11347
510dd77e
RK		 11348 /* If the register is used in both I2 and I3 and it dies in I3,
11349 we might have added another reference to it. If reg_n_refs
11350 was 2, bump it to 3. This has to be correct since the
11351 register must have been set somewhere. The reason this is
11352 done is because local-alloc.c treats 2 references as a
11353 special case. */
11354
11355 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
b1f21e0a 11356 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
510dd77e 11357 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
b1f21e0a 11358 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
510dd77e 11359
230d793d 11360 if (place == 0)
38d8473f
RK		 11361 {
11362 for (tem = prev_nonnote_insn (i3);
11363 place == 0 && tem
11364 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11365 tem = prev_nonnote_insn (tem))
11366 {
11367 /* If the register is being set at TEM, see if that is all
11368 TEM is doing. If so, delete TEM. Otherwise, make this
11369 into a REG_UNUSED note instead. */
11370 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11371 {
11372 rtx set = single_set (tem);
11373
11374 /* Verify that it was the set, and not a clobber that
11375 modified the register. */
11376
11377 if (set != 0 && ! side_effects_p (SET_SRC (set))
d02089a5
RK		 11378 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11379 || (GET_CODE (SET_DEST (set)) == SUBREG
11380 && rtx_equal_p (XEXP (note, 0),
11381 XEXP (SET_DEST (set), 0)))))
38d8473f
RK		 11382 {
11383 /* Move the notes and links of TEM elsewhere.
11384 This might delete other dead insns recursively.
11385 First set the pattern to something that won't use
11386 any register. */
11387
11388 PATTERN (tem) = pc_rtx;
11389
11390 distribute_notes (REG_NOTES (tem), tem, tem,
11391 NULL_RTX, NULL_RTX, NULL_RTX);
11392 distribute_links (LOG_LINKS (tem));
11393
11394 PUT_CODE (tem, NOTE);
11395 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11396 NOTE_SOURCE_FILE (tem) = 0;
11397 }
11398 else
11399 {
11400 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11401
11402 /* If there isn't already a REG_UNUSED note, put one
11403 here. */
11404 if (! find_regno_note (tem, REG_UNUSED,
11405 REGNO (XEXP (note, 0))))
11406 place = tem;
11407 break;
230d793d
RS		 11408 }
11409 }
13018fad
RE		 11410 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11411 || (GET_CODE (tem) == CALL_INSN
11412 && find_reg_fusage (tem, USE, XEXP (note, 0))))
230d793d
RS		 11413 {
11414 place = tem;
932d1119
RK		 11415
11416 /* If we are doing a 3->2 combination, and we have a
11417 register which formerly died in i3 and was not used
11418 by i2, which now no longer dies in i3 and is used in
11419 i2 but does not die in i2, and place is between i2
11420 and i3, then we may need to move a link from place to
11421 i2. */
a8908849
RK		 11422 if (i2 && INSN_UID (place) <= max_uid_cuid
11423 && INSN_CUID (place) > INSN_CUID (i2)
932d1119
RK		 11424 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11425 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11426 {
11427 rtx links = LOG_LINKS (place);
11428 LOG_LINKS (place) = 0;
11429 distribute_links (links);
11430 }
230d793d
RS		 11431 break;
11432 }
38d8473f
RK		 11433 }
11434
11435 /* If we haven't found an insn for the death note and it
11436 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11437 insert a USE insn for the register at that label and
11438 put the death node there. This prevents problems with
11439 call-state tracking in caller-save.c. */
11440 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
e2cce0cf
RK		 11441 {
11442 place
38a448ca 11443 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
e2cce0cf
RK		 11444 tem);
11445
11446 /* If this insn was emitted between blocks, then update
11447 basic_block_head of the current block to include it. */
11448 if (basic_block_end[this_basic_block - 1] == tem)
11449 basic_block_head[this_basic_block] = place;
11450 }
38d8473f 11451 }
230d793d
RS		 11452
11453 /* If the register is set or already dead at PLACE, we needn't do
11454 anything with this note if it is still a REG_DEAD note.
11455
11456 Note that we cannot use just `dead_or_set_p' here since we can
11457 convert an assignment to a register into a bit-field assignment.
11458 Therefore, we must also omit the note if the register is the
11459 target of a bitfield assignment. */
11460
11461 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11462 {
11463 int regno = REGNO (XEXP (note, 0));
11464
11465 if (dead_or_set_p (place, XEXP (note, 0))
11466 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11467 {
11468 /* Unless the register previously died in PLACE, clear
11469 reg_last_death. [I no longer understand why this is
11470 being done.] */
11471 if (reg_last_death[regno] != place)
11472 reg_last_death[regno] = 0;
11473 place = 0;
11474 }
11475 else
11476 reg_last_death[regno] = place;
11477
11478 /* If this is a death note for a hard reg that is occupying
11479 multiple registers, ensure that we are still using all
11480 parts of the object. If we find a piece of the object
11481 that is unused, we must add a USE for that piece before
11482 PLACE and put the appropriate REG_DEAD note on it.
11483
11484 An alternative would be to put a REG_UNUSED for the pieces
11485 on the insn that set the register, but that can't be done if
11486 it is not in the same block. It is simpler, though less
11487 efficient, to add the USE insns. */
11488
11489 if (place && regno < FIRST_PSEUDO_REGISTER
11490 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11491 {
11492 int endregno
11493 = regno + HARD_REGNO_NREGS (regno,
11494 GET_MODE (XEXP (note, 0)));
11495 int all_used = 1;
11496 int i;
11497
11498 for (i = regno; i < endregno; i++)
9fd5bb62
JW		 11499 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11500 && ! find_regno_fusage (place, USE, i))
230d793d 11501 {
38a448ca 11502 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
28f6d3af
RK		 11503 rtx p;
11504
11505 /* See if we already placed a USE note for this
11506 register in front of PLACE. */
11507 for (p = place;
11508 GET_CODE (PREV_INSN (p)) == INSN
11509 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11510 p = PREV_INSN (p))
11511 if (rtx_equal_p (piece,
11512 XEXP (PATTERN (PREV_INSN (p)), 0)))
11513 {
11514 p = 0;
11515 break;
11516 }
11517
11518 if (p)
11519 {
11520 rtx use_insn
38a448ca
RH		 11521 = emit_insn_before (gen_rtx_USE (VOIDmode,
11522 piece),
28f6d3af
RK		 11523 p);
11524 REG_NOTES (use_insn)
38a448ca
RH		 11525 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11526 REG_NOTES (use_insn));
28f6d3af 11527 }
230d793d 11528
5089e22e 11529 all_used = 0;
230d793d
RS		 11530 }
11531
a394b17b
JW		 11532 /* Check for the case where the register dying partially
11533 overlaps the register set by this insn. */
11534 if (all_used)
11535 for (i = regno; i < endregno; i++)
11536 if (dead_or_set_regno_p (place, i))
11537 {
11538 all_used = 0;
11539 break;
11540 }
11541
230d793d
RS		 11542 if (! all_used)
11543 {
11544 /* Put only REG_DEAD notes for pieces that are
11545 still used and that are not already dead or set. */
11546
11547 for (i = regno; i < endregno; i++)
11548 {
38a448ca 11549 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
230d793d 11550
17cbf358
JW		 11551 if ((reg_referenced_p (piece, PATTERN (place))
11552 || (GET_CODE (place) == CALL_INSN
11553 && find_reg_fusage (place, USE, piece)))
230d793d
RS		 11554 && ! dead_or_set_p (place, piece)
11555 && ! reg_bitfield_target_p (piece,
11556 PATTERN (place)))
38a448ca
RH		 11557 REG_NOTES (place)
11558 = gen_rtx_EXPR_LIST (REG_DEAD,
11559 piece, REG_NOTES (place));
230d793d
RS		 11560 }
11561
11562 place = 0;
11563 }
11564 }
11565 }
11566 break;
11567
11568 default:
11569 /* Any other notes should not be present at this point in the
11570 compilation. */
11571 abort ();
11572 }
11573
11574 if (place)
11575 {
11576 XEXP (note, 1) = REG_NOTES (place);
11577 REG_NOTES (place) = note;
11578 }
1a26b032
RK		 11579 else if ((REG_NOTE_KIND (note) == REG_DEAD
11580 || REG_NOTE_KIND (note) == REG_UNUSED)
11581 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11582 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
230d793d
RS		 11583
11584 if (place2)
1a26b032
RK		 11585 {
11586 if ((REG_NOTE_KIND (note) == REG_DEAD
11587 || REG_NOTE_KIND (note) == REG_UNUSED)
11588 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11589 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 11590
38a448ca
RH		 11591 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11592 REG_NOTE_KIND (note),
11593 XEXP (note, 0),
11594 REG_NOTES (place2));
1a26b032 11595 }
230d793d
RS		 11596 }
11597}
11598\f
11599/* Similarly to above, distribute the LOG_LINKS that used to be present on
5089e22e
RS		 11600 I3, I2, and I1 to new locations. This is also called in one case to
11601 add a link pointing at I3 when I3's destination is changed. */
230d793d
RS		 11602
11603static void
11604distribute_links (links)
11605 rtx links;
11606{
11607 rtx link, next_link;
11608
11609 for (link = links; link; link = next_link)
11610 {
11611 rtx place = 0;
11612 rtx insn;
11613 rtx set, reg;
11614
11615 next_link = XEXP (link, 1);
11616
11617 /* If the insn that this link points to is a NOTE or isn't a single
11618 set, ignore it. In the latter case, it isn't clear what we
11619 can do other than ignore the link, since we can't tell which
11620 register it was for. Such links wouldn't be used by combine
11621 anyway.
11622
11623 It is not possible for the destination of the target of the link to
11624 have been changed by combine. The only potential of this is if we
11625 replace I3, I2, and I1 by I3 and I2. But in that case the
11626 destination of I2 also remains unchanged. */
11627
11628 if (GET_CODE (XEXP (link, 0)) == NOTE
11629 || (set = single_set (XEXP (link, 0))) == 0)
11630 continue;
11631
11632 reg = SET_DEST (set);
11633 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11634 || GET_CODE (reg) == SIGN_EXTRACT
11635 || GET_CODE (reg) == STRICT_LOW_PART)
11636 reg = XEXP (reg, 0);
11637
11638 /* A LOG_LINK is defined as being placed on the first insn that uses
11639 a register and points to the insn that sets the register. Start
11640 searching at the next insn after the target of the link and stop
11641 when we reach a set of the register or the end of the basic block.
11642
11643 Note that this correctly handles the link that used to point from
5089e22e 11644 I3 to I2. Also note that not much searching is typically done here
230d793d
RS		 11645 since most links don't point very far away. */
11646
11647 for (insn = NEXT_INSN (XEXP (link, 0));
0d4d42c3
RK		 11648 (insn && (this_basic_block == n_basic_blocks - 1
11649 || basic_block_head[this_basic_block + 1] != insn));
230d793d
RS		 11650 insn = NEXT_INSN (insn))
11651 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11652 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11653 {
11654 if (reg_referenced_p (reg, PATTERN (insn)))
11655 place = insn;
11656 break;
11657 }
6e2d1486
RK		 11658 else if (GET_CODE (insn) == CALL_INSN
11659 && find_reg_fusage (insn, USE, reg))
11660 {
11661 place = insn;
11662 break;
11663 }
230d793d
RS		 11664
11665 /* If we found a place to put the link, place it there unless there
11666 is already a link to the same insn as LINK at that point. */
11667
11668 if (place)
11669 {
11670 rtx link2;
11671
11672 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11673 if (XEXP (link2, 0) == XEXP (link, 0))
11674 break;
11675
11676 if (link2 == 0)
11677 {
11678 XEXP (link, 1) = LOG_LINKS (place);
11679 LOG_LINKS (place) = link;
abe6e52f
RK		 11680
11681 /* Set added_links_insn to the earliest insn we added a
11682 link to. */
11683 if (added_links_insn == 0
11684 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11685 added_links_insn = place;
230d793d
RS		 11686 }
11687 }
11688 }
11689}
11690\f
1427d6d2
RK		 11691/* Compute INSN_CUID for INSN, which is an insn made by combine. */
11692
11693static int
11694insn_cuid (insn)
11695 rtx insn;
11696{
11697 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11698 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11699 insn = NEXT_INSN (insn);
11700
11701 if (INSN_UID (insn) > max_uid_cuid)
11702 abort ();
11703
11704 return INSN_CUID (insn);
11705}
11706\f
230d793d
RS		 11707void
11708dump_combine_stats (file)
11709 FILE *file;
11710{
11711 fprintf
11712 (file,
11713 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11714 combine_attempts, combine_merges, combine_extras, combine_successes);
11715}
11716
11717void
11718dump_combine_total_stats (file)
11719 FILE *file;
11720{
11721 fprintf
11722 (file,
11723 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11724 total_attempts, total_merges, total_extras, total_successes);
11725}
GNU Compiler Collection
This page took 2.250921 seconds and 5 git commands to generate.