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230d793d | 1 | /* Optimize by combining instructions for GNU compiler. |
3c71940f | 2 | Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
ad616de1 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
230d793d | 4 | |
1322177d | 5 | This file is part of GCC. |
230d793d | 6 | |
1322177d LB |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 2, or (at your option) any later | |
10 | version. | |
230d793d | 11 | |
1322177d LB |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
230d793d RS |
16 | |
17 | You should have received a copy of the GNU General Public License | |
1322177d LB |
18 | along with GCC; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
230d793d | 21 | |
230d793d RS |
22 | /* This module is essentially the "combiner" phase of the U. of Arizona |
23 | Portable Optimizer, but redone to work on our list-structured | |
24 | representation for RTL instead of their string representation. | |
25 | ||
26 | The LOG_LINKS of each insn identify the most recent assignment | |
27 | to each REG used in the insn. It is a list of previous insns, | |
28 | each of which contains a SET for a REG that is used in this insn | |
29 | and not used or set in between. LOG_LINKs never cross basic blocks. | |
30 | They were set up by the preceding pass (lifetime analysis). | |
31 | ||
32 | We try to combine each pair of insns joined by a logical link. | |
33 | We also try to combine triples of insns A, B and C when | |
34 | C has a link back to B and B has a link back to A. | |
35 | ||
36 | LOG_LINKS does not have links for use of the CC0. They don't | |
37 | need to, because the insn that sets the CC0 is always immediately | |
38 | before the insn that tests it. So we always regard a branch | |
39 | insn as having a logical link to the preceding insn. The same is true | |
40 | for an insn explicitly using CC0. | |
41 | ||
42 | We check (with use_crosses_set_p) to avoid combining in such a way | |
43 | as to move a computation to a place where its value would be different. | |
44 | ||
45 | Combination is done by mathematically substituting the previous | |
46 | insn(s) values for the regs they set into the expressions in | |
47 | the later insns that refer to these regs. If the result is a valid insn | |
48 | for our target machine, according to the machine description, | |
49 | we install it, delete the earlier insns, and update the data flow | |
50 | information (LOG_LINKS and REG_NOTES) for what we did. | |
51 | ||
52 | There are a few exceptions where the dataflow information created by | |
53 | flow.c aren't completely updated: | |
54 | ||
55 | - reg_live_length is not updated | |
230d793d | 56 | - a LOG_LINKS entry that refers to an insn with multiple SETs may be |
663522cb | 57 | removed because there is no way to know which register it was |
230d793d RS |
58 | linking |
59 | ||
60 | To simplify substitution, we combine only when the earlier insn(s) | |
61 | consist of only a single assignment. To simplify updating afterward, | |
62 | we never combine when a subroutine call appears in the middle. | |
63 | ||
64 | Since we do not represent assignments to CC0 explicitly except when that | |
65 | is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
66 | the condition code for the insn that set the condition code. | |
67 | Fortunately, these two insns must be consecutive. | |
68 | Therefore, every JUMP_INSN is taken to have an implicit logical link | |
69 | to the preceding insn. This is not quite right, since non-jumps can | |
70 | also use the condition code; but in practice such insns would not | |
71 | combine anyway. */ | |
72 | ||
230d793d | 73 | #include "config.h" |
670ee920 | 74 | #include "system.h" |
4977bab6 ZW |
75 | #include "coretypes.h" |
76 | #include "tm.h" | |
c5c76735 | 77 | #include "rtl.h" |
61f71b34 | 78 | #include "tree.h" |
a091679a | 79 | #include "tm_p.h" |
230d793d RS |
80 | #include "flags.h" |
81 | #include "regs.h" | |
55310dad | 82 | #include "hard-reg-set.h" |
230d793d RS |
83 | #include "basic-block.h" |
84 | #include "insn-config.h" | |
49ad7cfa | 85 | #include "function.h" |
ec5c56db | 86 | /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */ |
d6f4ec51 | 87 | #include "expr.h" |
230d793d RS |
88 | #include "insn-attr.h" |
89 | #include "recog.h" | |
90 | #include "real.h" | |
2e107e9e | 91 | #include "toplev.h" |
61f71b34 | 92 | #include "target.h" |
aa2d0bc3 AO |
93 | #include "optabs.h" |
94 | #include "insn-codes.h" | |
2f93eea8 | 95 | #include "rtlhooks-def.h" |
64b8935d RS |
96 | /* Include output.h for dump_file. */ |
97 | #include "output.h" | |
49c3b9a8 | 98 | #include "params.h" |
f73ad30e | 99 | |
230d793d RS |
100 | /* Number of attempts to combine instructions in this function. */ |
101 | ||
102 | static int combine_attempts; | |
103 | ||
104 | /* Number of attempts that got as far as substitution in this function. */ | |
105 | ||
106 | static int combine_merges; | |
107 | ||
108 | /* Number of instructions combined with added SETs in this function. */ | |
109 | ||
110 | static int combine_extras; | |
111 | ||
112 | /* Number of instructions combined in this function. */ | |
113 | ||
114 | static int combine_successes; | |
115 | ||
116 | /* Totals over entire compilation. */ | |
117 | ||
118 | static int total_attempts, total_merges, total_extras, total_successes; | |
9210df58 | 119 | |
230d793d RS |
120 | \f |
121 | /* Vector mapping INSN_UIDs to cuids. | |
5089e22e | 122 | The cuids are like uids but increase monotonically always. |
230d793d RS |
123 | Combine always uses cuids so that it can compare them. |
124 | But actually renumbering the uids, which we used to do, | |
125 | proves to be a bad idea because it makes it hard to compare | |
126 | the dumps produced by earlier passes with those from later passes. */ | |
127 | ||
128 | static int *uid_cuid; | |
4255220d | 129 | static int max_uid_cuid; |
230d793d RS |
130 | |
131 | /* Get the cuid of an insn. */ | |
132 | ||
1427d6d2 RK |
133 | #define INSN_CUID(INSN) \ |
134 | (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)]) | |
230d793d | 135 | |
42a6ff51 AO |
136 | /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by |
137 | BITS_PER_WORD would invoke undefined behavior. Work around it. */ | |
138 | ||
139 | #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \ | |
505ddab6 | 140 | (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1) |
42a6ff51 | 141 | |
230d793d RS |
142 | /* Maximum register number, which is the size of the tables below. */ |
143 | ||
770ae6cc | 144 | static unsigned int combine_max_regno; |
230d793d | 145 | |
5eaad481 PB |
146 | struct reg_stat { |
147 | /* Record last point of death of (hard or pseudo) register n. */ | |
148 | rtx last_death; | |
230d793d | 149 | |
5eaad481 PB |
150 | /* Record last point of modification of (hard or pseudo) register n. */ |
151 | rtx last_set; | |
230d793d | 152 | |
5eaad481 PB |
153 | /* The next group of fields allows the recording of the last value assigned |
154 | to (hard or pseudo) register n. We use this information to see if an | |
155 | operation being processed is redundant given a prior operation performed | |
156 | on the register. For example, an `and' with a constant is redundant if | |
157 | all the zero bits are already known to be turned off. | |
230d793d | 158 | |
5eaad481 PB |
159 | We use an approach similar to that used by cse, but change it in the |
160 | following ways: | |
161 | ||
162 | (1) We do not want to reinitialize at each label. | |
163 | (2) It is useful, but not critical, to know the actual value assigned | |
164 | to a register. Often just its form is helpful. | |
165 | ||
166 | Therefore, we maintain the following fields: | |
167 | ||
168 | last_set_value the last value assigned | |
169 | last_set_label records the value of label_tick when the | |
170 | register was assigned | |
171 | last_set_table_tick records the value of label_tick when a | |
172 | value using the register is assigned | |
173 | last_set_invalid set to nonzero when it is not valid | |
174 | to use the value of this register in some | |
175 | register's value | |
176 | ||
177 | To understand the usage of these tables, it is important to understand | |
178 | the distinction between the value in last_set_value being valid and | |
179 | the register being validly contained in some other expression in the | |
180 | table. | |
181 | ||
182 | (The next two parameters are out of date). | |
183 | ||
184 | reg_stat[i].last_set_value is valid if it is nonzero, and either | |
185 | reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick. | |
186 | ||
187 | Register I may validly appear in any expression returned for the value | |
188 | of another register if reg_n_sets[i] is 1. It may also appear in the | |
189 | value for register J if reg_stat[j].last_set_invalid is zero, or | |
190 | reg_stat[i].last_set_label < reg_stat[j].last_set_label. | |
191 | ||
192 | If an expression is found in the table containing a register which may | |
193 | not validly appear in an expression, the register is replaced by | |
194 | something that won't match, (clobber (const_int 0)). */ | |
195 | ||
196 | /* Record last value assigned to (hard or pseudo) register n. */ | |
197 | ||
198 | rtx last_set_value; | |
199 | ||
200 | /* Record the value of label_tick when an expression involving register n | |
201 | is placed in last_set_value. */ | |
202 | ||
203 | int last_set_table_tick; | |
204 | ||
205 | /* Record the value of label_tick when the value for register n is placed in | |
206 | last_set_value. */ | |
207 | ||
208 | int last_set_label; | |
209 | ||
210 | /* These fields are maintained in parallel with last_set_value and are | |
324a6c95 | 211 | used to store the mode in which the register was last set, the bits |
5eaad481 PB |
212 | that were known to be zero when it was last set, and the number of |
213 | sign bits copies it was known to have when it was last set. */ | |
214 | ||
215 | unsigned HOST_WIDE_INT last_set_nonzero_bits; | |
216 | char last_set_sign_bit_copies; | |
217 | ENUM_BITFIELD(machine_mode) last_set_mode : 8; | |
218 | ||
219 | /* Set nonzero if references to register n in expressions should not be | |
220 | used. last_set_invalid is set nonzero when this register is being | |
221 | assigned to and last_set_table_tick == label_tick. */ | |
222 | ||
223 | char last_set_invalid; | |
224 | ||
225 | /* Some registers that are set more than once and used in more than one | |
226 | basic block are nevertheless always set in similar ways. For example, | |
227 | a QImode register may be loaded from memory in two places on a machine | |
228 | where byte loads zero extend. | |
229 | ||
230 | We record in the following fields if a register has some leading bits | |
231 | that are always equal to the sign bit, and what we know about the | |
232 | nonzero bits of a register, specifically which bits are known to be | |
233 | zero. | |
234 | ||
235 | If an entry is zero, it means that we don't know anything special. */ | |
236 | ||
237 | unsigned char sign_bit_copies; | |
238 | ||
239 | unsigned HOST_WIDE_INT nonzero_bits; | |
240 | }; | |
241 | ||
242 | static struct reg_stat *reg_stat; | |
230d793d RS |
243 | |
244 | /* Record the cuid of the last insn that invalidated memory | |
245 | (anything that writes memory, and subroutine calls, but not pushes). */ | |
246 | ||
247 | static int mem_last_set; | |
248 | ||
249 | /* Record the cuid of the last CALL_INSN | |
250 | so we can tell whether a potential combination crosses any calls. */ | |
251 | ||
252 | static int last_call_cuid; | |
253 | ||
254 | /* When `subst' is called, this is the insn that is being modified | |
255 | (by combining in a previous insn). The PATTERN of this insn | |
256 | is still the old pattern partially modified and it should not be | |
257 | looked at, but this may be used to examine the successors of the insn | |
258 | to judge whether a simplification is valid. */ | |
259 | ||
260 | static rtx subst_insn; | |
261 | ||
262 | /* This is the lowest CUID that `subst' is currently dealing with. | |
263 | get_last_value will not return a value if the register was set at or | |
264 | after this CUID. If not for this mechanism, we could get confused if | |
265 | I2 or I1 in try_combine were an insn that used the old value of a register | |
266 | to obtain a new value. In that case, we might erroneously get the | |
267 | new value of the register when we wanted the old one. */ | |
268 | ||
269 | static int subst_low_cuid; | |
270 | ||
6e25d159 RK |
271 | /* This contains any hard registers that are used in newpat; reg_dead_at_p |
272 | must consider all these registers to be always live. */ | |
273 | ||
274 | static HARD_REG_SET newpat_used_regs; | |
275 | ||
abe6e52f RK |
276 | /* This is an insn to which a LOG_LINKS entry has been added. If this |
277 | insn is the earlier than I2 or I3, combine should rescan starting at | |
278 | that location. */ | |
279 | ||
280 | static rtx added_links_insn; | |
281 | ||
f6366fc7 ZD |
282 | /* Basic block in which we are performing combines. */ |
283 | static basic_block this_basic_block; | |
715e7fbc | 284 | |
663522cb KH |
285 | /* A bitmap indicating which blocks had registers go dead at entry. |
286 | After combine, we'll need to re-do global life analysis with | |
715e7fbc RH |
287 | those blocks as starting points. */ |
288 | static sbitmap refresh_blocks; | |
230d793d | 289 | \f |
6fd21094 | 290 | /* The following array records the insn_rtx_cost for every insn |
64b8935d RS |
291 | in the instruction stream. */ |
292 | ||
293 | static int *uid_insn_cost; | |
294 | ||
295 | /* Length of the currently allocated uid_insn_cost array. */ | |
296 | ||
297 | static int last_insn_cost; | |
298 | ||
0f41302f | 299 | /* Incremented for each label. */ |
230d793d | 300 | |
568356af | 301 | static int label_tick; |
230d793d | 302 | |
5eaad481 PB |
303 | /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the |
304 | largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */ | |
230d793d | 305 | |
951553af | 306 | static enum machine_mode nonzero_bits_mode; |
230d793d | 307 | |
5eaad481 PB |
308 | /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can |
309 | be safely used. It is zero while computing them and after combine has | |
310 | completed. This former test prevents propagating values based on | |
311 | previously set values, which can be incorrect if a variable is modified | |
312 | in a loop. */ | |
230d793d | 313 | |
951553af | 314 | static int nonzero_sign_valid; |
55310dad | 315 | |
230d793d RS |
316 | \f |
317 | /* Record one modification to rtl structure | |
318 | to be undone by storing old_contents into *where. | |
319 | is_int is 1 if the contents are an int. */ | |
320 | ||
321 | struct undo | |
322 | { | |
241cea85 | 323 | struct undo *next; |
230d793d | 324 | int is_int; |
3129af4c RS |
325 | union {rtx r; int i;} old_contents; |
326 | union {rtx *r; int *i;} where; | |
230d793d RS |
327 | }; |
328 | ||
329 | /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
330 | num_undo says how many are currently recorded. | |
331 | ||
230d793d | 332 | other_insn is nonzero if we have modified some other insn in the process |
f1c6ba8b | 333 | of working on subst_insn. It must be verified too. */ |
230d793d RS |
334 | |
335 | struct undobuf | |
336 | { | |
241cea85 RK |
337 | struct undo *undos; |
338 | struct undo *frees; | |
230d793d RS |
339 | rtx other_insn; |
340 | }; | |
341 | ||
342 | static struct undobuf undobuf; | |
343 | ||
230d793d RS |
344 | /* Number of times the pseudo being substituted for |
345 | was found and replaced. */ | |
346 | ||
347 | static int n_occurrences; | |
348 | ||
2f93eea8 PB |
349 | static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx, |
350 | enum machine_mode, | |
351 | unsigned HOST_WIDE_INT, | |
352 | unsigned HOST_WIDE_INT *); | |
353 | static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx, | |
354 | enum machine_mode, | |
355 | unsigned int, unsigned int *); | |
79a490a9 AJ |
356 | static void do_SUBST (rtx *, rtx); |
357 | static void do_SUBST_INT (int *, int); | |
5eaad481 | 358 | static void init_reg_last (void); |
79a490a9 AJ |
359 | static void setup_incoming_promotions (void); |
360 | static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *); | |
361 | static int cant_combine_insn_p (rtx); | |
362 | static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *); | |
79a490a9 AJ |
363 | static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *); |
364 | static int contains_muldiv (rtx); | |
365 | static rtx try_combine (rtx, rtx, rtx, int *); | |
366 | static void undo_all (void); | |
367 | static void undo_commit (void); | |
368 | static rtx *find_split_point (rtx *, rtx); | |
369 | static rtx subst (rtx, rtx, rtx, int, int); | |
6621d78e | 370 | static rtx combine_simplify_rtx (rtx, enum machine_mode, int); |
79a490a9 AJ |
371 | static rtx simplify_if_then_else (rtx); |
372 | static rtx simplify_set (rtx); | |
6621d78e | 373 | static rtx simplify_logical (rtx); |
79a490a9 AJ |
374 | static rtx expand_compound_operation (rtx); |
375 | static rtx expand_field_assignment (rtx); | |
376 | static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT, | |
377 | rtx, unsigned HOST_WIDE_INT, int, int, int); | |
378 | static rtx extract_left_shift (rtx, int); | |
379 | static rtx make_compound_operation (rtx, enum rtx_code); | |
380 | static int get_pos_from_mask (unsigned HOST_WIDE_INT, | |
381 | unsigned HOST_WIDE_INT *); | |
382 | static rtx force_to_mode (rtx, enum machine_mode, | |
383 | unsigned HOST_WIDE_INT, rtx, int); | |
384 | static rtx if_then_else_cond (rtx, rtx *, rtx *); | |
385 | static rtx known_cond (rtx, enum rtx_code, rtx, rtx); | |
386 | static int rtx_equal_for_field_assignment_p (rtx, rtx); | |
387 | static rtx make_field_assignment (rtx); | |
388 | static rtx apply_distributive_law (rtx); | |
bcb34aa3 | 389 | static rtx distribute_and_simplify_rtx (rtx, int); |
79a490a9 AJ |
390 | static rtx simplify_and_const_int (rtx, enum machine_mode, rtx, |
391 | unsigned HOST_WIDE_INT); | |
79a490a9 AJ |
392 | static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code, |
393 | HOST_WIDE_INT, enum machine_mode, int *); | |
394 | static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx, | |
395 | int); | |
396 | static int recog_for_combine (rtx *, rtx, rtx *); | |
397 | static rtx gen_lowpart_for_combine (enum machine_mode, rtx); | |
79a490a9 AJ |
398 | static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *); |
399 | static void update_table_tick (rtx); | |
400 | static void record_value_for_reg (rtx, rtx, rtx); | |
401 | static void check_promoted_subreg (rtx, rtx); | |
402 | static void record_dead_and_set_regs_1 (rtx, rtx, void *); | |
403 | static void record_dead_and_set_regs (rtx); | |
404 | static int get_last_value_validate (rtx *, rtx, int, int); | |
405 | static rtx get_last_value (rtx); | |
406 | static int use_crosses_set_p (rtx, int); | |
407 | static void reg_dead_at_p_1 (rtx, rtx, void *); | |
408 | static int reg_dead_at_p (rtx, rtx); | |
409 | static void move_deaths (rtx, rtx, int, rtx, rtx *); | |
410 | static int reg_bitfield_target_p (rtx, rtx); | |
411 | static void distribute_notes (rtx, rtx, rtx, rtx); | |
412 | static void distribute_links (rtx); | |
413 | static void mark_used_regs_combine (rtx); | |
414 | static int insn_cuid (rtx); | |
415 | static void record_promoted_value (rtx, rtx); | |
67962db5 RS |
416 | static int unmentioned_reg_p_1 (rtx *, void *); |
417 | static bool unmentioned_reg_p (rtx, rtx); | |
2f93eea8 PB |
418 | \f |
419 | ||
420 | /* It is not safe to use ordinary gen_lowpart in combine. | |
421 | See comments in gen_lowpart_for_combine. */ | |
422 | #undef RTL_HOOKS_GEN_LOWPART | |
423 | #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine | |
424 | ||
bf667275 PB |
425 | /* Our implementation of gen_lowpart never emits a new pseudo. */ |
426 | #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT | |
427 | #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine | |
428 | ||
2f93eea8 PB |
429 | #undef RTL_HOOKS_REG_NONZERO_REG_BITS |
430 | #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine | |
431 | ||
432 | #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES | |
433 | #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine | |
434 | ||
435 | static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER; | |
436 | ||
230d793d | 437 | \f |
76095e2f RH |
438 | /* Substitute NEWVAL, an rtx expression, into INTO, a place in some |
439 | insn. The substitution can be undone by undo_all. If INTO is already | |
440 | set to NEWVAL, do not record this change. Because computing NEWVAL might | |
441 | also call SUBST, we have to compute it before we put anything into | |
442 | the undo table. */ | |
443 | ||
444 | static void | |
79a490a9 | 445 | do_SUBST (rtx *into, rtx newval) |
76095e2f RH |
446 | { |
447 | struct undo *buf; | |
448 | rtx oldval = *into; | |
449 | ||
450 | if (oldval == newval) | |
451 | return; | |
452 | ||
4161da12 AO |
453 | /* We'd like to catch as many invalid transformations here as |
454 | possible. Unfortunately, there are way too many mode changes | |
455 | that are perfectly valid, so we'd waste too much effort for | |
456 | little gain doing the checks here. Focus on catching invalid | |
457 | transformations involving integer constants. */ | |
458 | if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT | |
459 | && GET_CODE (newval) == CONST_INT) | |
460 | { | |
461 | /* Sanity check that we're replacing oldval with a CONST_INT | |
462 | that is a valid sign-extension for the original mode. */ | |
341c100f NS |
463 | gcc_assert (INTVAL (newval) |
464 | == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval))); | |
4161da12 AO |
465 | |
466 | /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a | |
467 | CONST_INT is not valid, because after the replacement, the | |
468 | original mode would be gone. Unfortunately, we can't tell | |
469 | when do_SUBST is called to replace the operand thereof, so we | |
470 | perform this test on oldval instead, checking whether an | |
471 | invalid replacement took place before we got here. */ | |
341c100f NS |
472 | gcc_assert (!(GET_CODE (oldval) == SUBREG |
473 | && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)); | |
474 | gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND | |
475 | && GET_CODE (XEXP (oldval, 0)) == CONST_INT)); | |
e869aa39 | 476 | } |
4161da12 | 477 | |
76095e2f RH |
478 | if (undobuf.frees) |
479 | buf = undobuf.frees, undobuf.frees = buf->next; | |
480 | else | |
703ad42b | 481 | buf = xmalloc (sizeof (struct undo)); |
76095e2f RH |
482 | |
483 | buf->is_int = 0; | |
484 | buf->where.r = into; | |
485 | buf->old_contents.r = oldval; | |
486 | *into = newval; | |
487 | ||
488 | buf->next = undobuf.undos, undobuf.undos = buf; | |
489 | } | |
490 | ||
491 | #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL)) | |
492 | ||
493 | /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution | |
494 | for the value of a HOST_WIDE_INT value (including CONST_INT) is | |
495 | not safe. */ | |
496 | ||
497 | static void | |
79a490a9 | 498 | do_SUBST_INT (int *into, int newval) |
76095e2f RH |
499 | { |
500 | struct undo *buf; | |
3129af4c | 501 | int oldval = *into; |
76095e2f RH |
502 | |
503 | if (oldval == newval) | |
504 | return; | |
505 | ||
506 | if (undobuf.frees) | |
507 | buf = undobuf.frees, undobuf.frees = buf->next; | |
508 | else | |
703ad42b | 509 | buf = xmalloc (sizeof (struct undo)); |
76095e2f RH |
510 | |
511 | buf->is_int = 1; | |
512 | buf->where.i = into; | |
513 | buf->old_contents.i = oldval; | |
514 | *into = newval; | |
515 | ||
516 | buf->next = undobuf.undos, undobuf.undos = buf; | |
517 | } | |
518 | ||
519 | #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL)) | |
520 | \f | |
64b8935d | 521 | /* Subroutine of try_combine. Determine whether the combine replacement |
6fd21094 | 522 | patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost |
64b8935d RS |
523 | that the original instruction sequence I1, I2 and I3. Note that I1 |
524 | and/or NEWI2PAT may be NULL_RTX. This function returns false, if the | |
525 | costs of all instructions can be estimated, and the replacements are | |
526 | more expensive than the original sequence. */ | |
527 | ||
528 | static bool | |
529 | combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat) | |
530 | { | |
531 | int i1_cost, i2_cost, i3_cost; | |
532 | int new_i2_cost, new_i3_cost; | |
533 | int old_cost, new_cost; | |
534 | ||
6fd21094 | 535 | /* Lookup the original insn_rtx_costs. */ |
64b8935d RS |
536 | i2_cost = INSN_UID (i2) <= last_insn_cost |
537 | ? uid_insn_cost[INSN_UID (i2)] : 0; | |
538 | i3_cost = INSN_UID (i3) <= last_insn_cost | |
539 | ? uid_insn_cost[INSN_UID (i3)] : 0; | |
540 | ||
541 | if (i1) | |
542 | { | |
543 | i1_cost = INSN_UID (i1) <= last_insn_cost | |
544 | ? uid_insn_cost[INSN_UID (i1)] : 0; | |
545 | old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0) | |
546 | ? i1_cost + i2_cost + i3_cost : 0; | |
547 | } | |
548 | else | |
549 | { | |
550 | old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0; | |
551 | i1_cost = 0; | |
552 | } | |
553 | ||
6fd21094 RS |
554 | /* Calculate the replacement insn_rtx_costs. */ |
555 | new_i3_cost = insn_rtx_cost (newpat); | |
64b8935d RS |
556 | if (newi2pat) |
557 | { | |
6fd21094 | 558 | new_i2_cost = insn_rtx_cost (newi2pat); |
64b8935d RS |
559 | new_cost = (new_i2_cost > 0 && new_i3_cost > 0) |
560 | ? new_i2_cost + new_i3_cost : 0; | |
561 | } | |
562 | else | |
563 | { | |
564 | new_cost = new_i3_cost; | |
565 | new_i2_cost = 0; | |
566 | } | |
567 | ||
6bd26f0b ILT |
568 | if (undobuf.other_insn) |
569 | { | |
570 | int old_other_cost, new_other_cost; | |
571 | ||
572 | old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost | |
573 | ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0); | |
574 | new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn)); | |
575 | if (old_other_cost > 0 && new_other_cost > 0) | |
576 | { | |
577 | old_cost += old_other_cost; | |
578 | new_cost += new_other_cost; | |
579 | } | |
580 | else | |
581 | old_cost = 0; | |
582 | } | |
583 | ||
64b8935d RS |
584 | /* Disallow this recombination if both new_cost and old_cost are |
585 | greater than zero, and new_cost is greater than old cost. */ | |
6bd26f0b | 586 | if (old_cost > 0 |
64b8935d RS |
587 | && new_cost > old_cost) |
588 | { | |
589 | if (dump_file) | |
590 | { | |
591 | if (i1) | |
592 | { | |
593 | fprintf (dump_file, | |
594 | "rejecting combination of insns %d, %d and %d\n", | |
595 | INSN_UID (i1), INSN_UID (i2), INSN_UID (i3)); | |
596 | fprintf (dump_file, "original costs %d + %d + %d = %d\n", | |
597 | i1_cost, i2_cost, i3_cost, old_cost); | |
598 | } | |
599 | else | |
600 | { | |
601 | fprintf (dump_file, | |
602 | "rejecting combination of insns %d and %d\n", | |
603 | INSN_UID (i2), INSN_UID (i3)); | |
604 | fprintf (dump_file, "original costs %d + %d = %d\n", | |
605 | i2_cost, i3_cost, old_cost); | |
606 | } | |
607 | ||
608 | if (newi2pat) | |
609 | { | |
610 | fprintf (dump_file, "replacement costs %d + %d = %d\n", | |
611 | new_i2_cost, new_i3_cost, new_cost); | |
612 | } | |
613 | else | |
614 | fprintf (dump_file, "replacement cost %d\n", new_cost); | |
615 | } | |
616 | ||
617 | return false; | |
618 | } | |
619 | ||
620 | /* Update the uid_insn_cost array with the replacement costs. */ | |
621 | uid_insn_cost[INSN_UID (i2)] = new_i2_cost; | |
622 | uid_insn_cost[INSN_UID (i3)] = new_i3_cost; | |
623 | if (i1) | |
624 | uid_insn_cost[INSN_UID (i1)] = 0; | |
625 | ||
626 | return true; | |
627 | } | |
628 | \f | |
230d793d | 629 | /* Main entry point for combiner. F is the first insn of the function. |
663522cb | 630 | NREGS is the first unused pseudo-reg number. |
230d793d | 631 | |
da7d8304 | 632 | Return nonzero if the combiner has turned an indirect jump |
44a76fc8 AG |
633 | instruction into a direct jump. */ |
634 | int | |
79a490a9 | 635 | combine_instructions (rtx f, unsigned int nregs) |
230d793d | 636 | { |
b3694847 | 637 | rtx insn, next; |
b729186a | 638 | #ifdef HAVE_cc0 |
b3694847 | 639 | rtx prev; |
b729186a | 640 | #endif |
b3694847 SS |
641 | int i; |
642 | rtx links, nextlinks; | |
230d793d | 643 | |
44a76fc8 AG |
644 | int new_direct_jump_p = 0; |
645 | ||
230d793d RS |
646 | combine_attempts = 0; |
647 | combine_merges = 0; | |
648 | combine_extras = 0; | |
649 | combine_successes = 0; | |
650 | ||
651 | combine_max_regno = nregs; | |
652 | ||
2f93eea8 | 653 | rtl_hooks = combine_rtl_hooks; |
4de249d9 | 654 | |
5eaad481 | 655 | reg_stat = xcalloc (nregs, sizeof (struct reg_stat)); |
230d793d RS |
656 | |
657 | init_recog_no_volatile (); | |
658 | ||
659 | /* Compute maximum uid value so uid_cuid can be allocated. */ | |
660 | ||
661 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) | |
662 | if (INSN_UID (insn) > i) | |
663 | i = INSN_UID (insn); | |
664 | ||
703ad42b | 665 | uid_cuid = xmalloc ((i + 1) * sizeof (int)); |
4255220d | 666 | max_uid_cuid = i; |
230d793d | 667 | |
951553af | 668 | nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0); |
230d793d | 669 | |
5eaad481 PB |
670 | /* Don't use reg_stat[].nonzero_bits when computing it. This can cause |
671 | problems when, for example, we have j <<= 1 in a loop. */ | |
230d793d | 672 | |
951553af | 673 | nonzero_sign_valid = 0; |
230d793d RS |
674 | |
675 | /* Compute the mapping from uids to cuids. | |
676 | Cuids are numbers assigned to insns, like uids, | |
663522cb | 677 | except that cuids increase monotonically through the code. |
230d793d RS |
678 | |
679 | Scan all SETs and see if we can deduce anything about what | |
951553af | 680 | bits are known to be zero for some registers and how many copies |
d79f08e0 RK |
681 | of the sign bit are known to exist for those registers. |
682 | ||
683 | Also set any known values so that we can use it while searching | |
684 | for what bits are known to be set. */ | |
685 | ||
686 | label_tick = 1; | |
230d793d | 687 | |
7988fd36 RK |
688 | setup_incoming_promotions (); |
689 | ||
d55bc081 | 690 | refresh_blocks = sbitmap_alloc (last_basic_block); |
715e7fbc | 691 | sbitmap_zero (refresh_blocks); |
715e7fbc | 692 | |
6fd21094 | 693 | /* Allocate array of current insn_rtx_costs. */ |
64b8935d RS |
694 | uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int)); |
695 | last_insn_cost = max_uid_cuid; | |
696 | ||
230d793d RS |
697 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) |
698 | { | |
4255220d | 699 | uid_cuid[INSN_UID (insn)] = ++i; |
d79f08e0 RK |
700 | subst_low_cuid = i; |
701 | subst_insn = insn; | |
702 | ||
2c3c49de | 703 | if (INSN_P (insn)) |
d79f08e0 | 704 | { |
663522cb | 705 | note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies, |
84832317 | 706 | NULL); |
d79f08e0 | 707 | record_dead_and_set_regs (insn); |
2dab894a RK |
708 | |
709 | #ifdef AUTO_INC_DEC | |
710 | for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) | |
711 | if (REG_NOTE_KIND (links) == REG_INC) | |
84832317 MM |
712 | set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX, |
713 | NULL); | |
2dab894a | 714 | #endif |
64b8935d | 715 | |
6fd21094 RS |
716 | /* Record the current insn_rtx_cost of this instruction. */ |
717 | if (NONJUMP_INSN_P (insn)) | |
718 | uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn)); | |
64b8935d RS |
719 | if (dump_file) |
720 | fprintf(dump_file, "insn_cost %d: %d\n", | |
721 | INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]); | |
d79f08e0 RK |
722 | } |
723 | ||
4b4bf941 | 724 | if (LABEL_P (insn)) |
d79f08e0 | 725 | label_tick++; |
230d793d RS |
726 | } |
727 | ||
951553af | 728 | nonzero_sign_valid = 1; |
230d793d RS |
729 | |
730 | /* Now scan all the insns in forward order. */ | |
731 | ||
732 | label_tick = 1; | |
733 | last_call_cuid = 0; | |
734 | mem_last_set = 0; | |
5eaad481 | 735 | init_reg_last (); |
7988fd36 RK |
736 | setup_incoming_promotions (); |
737 | ||
e0082a72 | 738 | FOR_EACH_BB (this_basic_block) |
230d793d | 739 | { |
a813c111 SB |
740 | for (insn = BB_HEAD (this_basic_block); |
741 | insn != NEXT_INSN (BB_END (this_basic_block)); | |
e0082a72 | 742 | insn = next ? next : NEXT_INSN (insn)) |
230d793d | 743 | { |
e0082a72 | 744 | next = 0; |
aabb6c74 | 745 | |
4b4bf941 | 746 | if (LABEL_P (insn)) |
e0082a72 | 747 | label_tick++; |
aabb6c74 | 748 | |
e0082a72 | 749 | else if (INSN_P (insn)) |
0b17ab2f | 750 | { |
e0082a72 ZD |
751 | /* See if we know about function return values before this |
752 | insn based upon SUBREG flags. */ | |
753 | check_promoted_subreg (insn, PATTERN (insn)); | |
230d793d | 754 | |
e0082a72 | 755 | /* Try this insn with each insn it links back to. */ |
230d793d | 756 | |
e0082a72 ZD |
757 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) |
758 | if ((next = try_combine (insn, XEXP (links, 0), | |
759 | NULL_RTX, &new_direct_jump_p)) != 0) | |
230d793d | 760 | goto retry; |
0b17ab2f | 761 | |
e0082a72 ZD |
762 | /* Try each sequence of three linked insns ending with this one. */ |
763 | ||
764 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
765 | { | |
766 | rtx link = XEXP (links, 0); | |
767 | ||
768 | /* If the linked insn has been replaced by a note, then there | |
769 | is no point in pursuing this chain any further. */ | |
4b4bf941 | 770 | if (NOTE_P (link)) |
e0082a72 ZD |
771 | continue; |
772 | ||
773 | for (nextlinks = LOG_LINKS (link); | |
774 | nextlinks; | |
775 | nextlinks = XEXP (nextlinks, 1)) | |
776 | if ((next = try_combine (insn, link, | |
777 | XEXP (nextlinks, 0), | |
778 | &new_direct_jump_p)) != 0) | |
779 | goto retry; | |
780 | } | |
230d793d | 781 | |
9b89393b | 782 | #ifdef HAVE_cc0 |
e0082a72 ZD |
783 | /* Try to combine a jump insn that uses CC0 |
784 | with a preceding insn that sets CC0, and maybe with its | |
785 | logical predecessor as well. | |
786 | This is how we make decrement-and-branch insns. | |
787 | We need this special code because data flow connections | |
788 | via CC0 do not get entered in LOG_LINKS. */ | |
789 | ||
4b4bf941 | 790 | if (JUMP_P (insn) |
e0082a72 | 791 | && (prev = prev_nonnote_insn (insn)) != 0 |
4b4bf941 | 792 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
793 | && sets_cc0_p (PATTERN (prev))) |
794 | { | |
795 | if ((next = try_combine (insn, prev, | |
796 | NULL_RTX, &new_direct_jump_p)) != 0) | |
797 | goto retry; | |
798 | ||
799 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
800 | nextlinks = XEXP (nextlinks, 1)) | |
801 | if ((next = try_combine (insn, prev, | |
802 | XEXP (nextlinks, 0), | |
803 | &new_direct_jump_p)) != 0) | |
804 | goto retry; | |
805 | } | |
230d793d | 806 | |
e0082a72 | 807 | /* Do the same for an insn that explicitly references CC0. */ |
4b4bf941 | 808 | if (NONJUMP_INSN_P (insn) |
e0082a72 | 809 | && (prev = prev_nonnote_insn (insn)) != 0 |
4b4bf941 | 810 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
811 | && sets_cc0_p (PATTERN (prev)) |
812 | && GET_CODE (PATTERN (insn)) == SET | |
813 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
814 | { | |
815 | if ((next = try_combine (insn, prev, | |
816 | NULL_RTX, &new_direct_jump_p)) != 0) | |
817 | goto retry; | |
818 | ||
819 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
820 | nextlinks = XEXP (nextlinks, 1)) | |
821 | if ((next = try_combine (insn, prev, | |
822 | XEXP (nextlinks, 0), | |
823 | &new_direct_jump_p)) != 0) | |
824 | goto retry; | |
825 | } | |
230d793d | 826 | |
e0082a72 ZD |
827 | /* Finally, see if any of the insns that this insn links to |
828 | explicitly references CC0. If so, try this insn, that insn, | |
829 | and its predecessor if it sets CC0. */ | |
830 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
4b4bf941 | 831 | if (NONJUMP_INSN_P (XEXP (links, 0)) |
e0082a72 ZD |
832 | && GET_CODE (PATTERN (XEXP (links, 0))) == SET |
833 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) | |
834 | && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 | |
4b4bf941 | 835 | && NONJUMP_INSN_P (prev) |
e0082a72 ZD |
836 | && sets_cc0_p (PATTERN (prev)) |
837 | && (next = try_combine (insn, XEXP (links, 0), | |
838 | prev, &new_direct_jump_p)) != 0) | |
839 | goto retry; | |
9b89393b | 840 | #endif |
e0082a72 ZD |
841 | |
842 | /* Try combining an insn with two different insns whose results it | |
843 | uses. */ | |
844 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
845 | for (nextlinks = XEXP (links, 1); nextlinks; | |
846 | nextlinks = XEXP (nextlinks, 1)) | |
847 | if ((next = try_combine (insn, XEXP (links, 0), | |
848 | XEXP (nextlinks, 0), | |
849 | &new_direct_jump_p)) != 0) | |
850 | goto retry; | |
851 | ||
67962db5 RS |
852 | /* Try this insn with each REG_EQUAL note it links back to. */ |
853 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
854 | { | |
855 | rtx set, note; | |
856 | rtx temp = XEXP (links, 0); | |
857 | if ((set = single_set (temp)) != 0 | |
858 | && (note = find_reg_equal_equiv_note (temp)) != 0 | |
859 | && GET_CODE (XEXP (note, 0)) != EXPR_LIST | |
860 | /* Avoid using a register that may already been marked | |
861 | dead by an earlier instruction. */ | |
862 | && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set))) | |
863 | { | |
864 | /* Temporarily replace the set's source with the | |
865 | contents of the REG_EQUAL note. The insn will | |
866 | be deleted or recognized by try_combine. */ | |
867 | rtx orig = SET_SRC (set); | |
868 | SET_SRC (set) = XEXP (note, 0); | |
869 | next = try_combine (insn, temp, NULL_RTX, | |
870 | &new_direct_jump_p); | |
871 | if (next) | |
872 | goto retry; | |
873 | SET_SRC (set) = orig; | |
874 | } | |
875 | } | |
876 | ||
4b4bf941 | 877 | if (!NOTE_P (insn)) |
e0082a72 ZD |
878 | record_dead_and_set_regs (insn); |
879 | ||
880 | retry: | |
881 | ; | |
882 | } | |
230d793d RS |
883 | } |
884 | } | |
c51d95ec | 885 | clear_bb_flags (); |
230d793d | 886 | |
f6366fc7 ZD |
887 | EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i, |
888 | BASIC_BLOCK (i)->flags |= BB_DIRTY); | |
25cd19de | 889 | new_direct_jump_p |= purge_all_dead_edges (); |
827c06b6 | 890 | delete_noop_moves (); |
0005550b | 891 | |
c51d95ec JH |
892 | update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES, |
893 | PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE | |
894 | | PROP_KILL_DEAD_CODE); | |
c05ddfa7 MM |
895 | |
896 | /* Clean up. */ | |
715e7fbc | 897 | sbitmap_free (refresh_blocks); |
64b8935d | 898 | free (uid_insn_cost); |
5eaad481 | 899 | free (reg_stat); |
c05ddfa7 | 900 | free (uid_cuid); |
715e7fbc | 901 | |
e7749837 RH |
902 | { |
903 | struct undo *undo, *next; | |
904 | for (undo = undobuf.frees; undo; undo = next) | |
905 | { | |
906 | next = undo->next; | |
907 | free (undo); | |
908 | } | |
909 | undobuf.frees = 0; | |
910 | } | |
911 | ||
230d793d RS |
912 | total_attempts += combine_attempts; |
913 | total_merges += combine_merges; | |
914 | total_extras += combine_extras; | |
915 | total_successes += combine_successes; | |
1a26b032 | 916 | |
951553af | 917 | nonzero_sign_valid = 0; |
2f93eea8 | 918 | rtl_hooks = general_rtl_hooks; |
972b320c R |
919 | |
920 | /* Make recognizer allow volatile MEMs again. */ | |
921 | init_recog (); | |
44a76fc8 AG |
922 | |
923 | return new_direct_jump_p; | |
230d793d | 924 | } |
ef026f91 | 925 | |
5eaad481 | 926 | /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */ |
ef026f91 RS |
927 | |
928 | static void | |
5eaad481 | 929 | init_reg_last (void) |
ef026f91 | 930 | { |
5eaad481 PB |
931 | unsigned int i; |
932 | for (i = 0; i < combine_max_regno; i++) | |
933 | memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies)); | |
ef026f91 | 934 | } |
230d793d | 935 | \f |
7988fd36 RK |
936 | /* Set up any promoted values for incoming argument registers. */ |
937 | ||
ee791cc3 | 938 | static void |
79a490a9 | 939 | setup_incoming_promotions (void) |
7988fd36 | 940 | { |
770ae6cc | 941 | unsigned int regno; |
7988fd36 RK |
942 | rtx reg; |
943 | enum machine_mode mode; | |
944 | int unsignedp; | |
945 | rtx first = get_insns (); | |
946 | ||
61f71b34 DD |
947 | if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl))) |
948 | { | |
61f71b34 DD |
949 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) |
950 | /* Check whether this register can hold an incoming pointer | |
951 | argument. FUNCTION_ARG_REGNO_P tests outgoing register | |
952 | numbers, so translate if necessary due to register windows. */ | |
953 | if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno)) | |
954 | && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0) | |
955 | { | |
956 | record_value_for_reg | |
957 | (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND | |
958 | : SIGN_EXTEND), | |
959 | GET_MODE (reg), | |
960 | gen_rtx_CLOBBER (mode, const0_rtx))); | |
961 | } | |
962 | } | |
7988fd36 RK |
963 | } |
964 | \f | |
91102d5a RK |
965 | /* Called via note_stores. If X is a pseudo that is narrower than |
966 | HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero. | |
230d793d RS |
967 | |
968 | If we are setting only a portion of X and we can't figure out what | |
969 | portion, assume all bits will be used since we don't know what will | |
d0ab8cd3 RK |
970 | be happening. |
971 | ||
972 | Similarly, set how many bits of X are known to be copies of the sign bit | |
663522cb | 973 | at all locations in the function. This is the smallest number implied |
d0ab8cd3 | 974 | by any set of X. */ |
230d793d RS |
975 | |
976 | static void | |
79a490a9 AJ |
977 | set_nonzero_bits_and_sign_copies (rtx x, rtx set, |
978 | void *data ATTRIBUTE_UNUSED) | |
230d793d | 979 | { |
770ae6cc | 980 | unsigned int num; |
d0ab8cd3 | 981 | |
f8cfc6aa | 982 | if (REG_P (x) |
230d793d | 983 | && REGNO (x) >= FIRST_PSEUDO_REGISTER |
e8095e80 RK |
984 | /* If this register is undefined at the start of the file, we can't |
985 | say what its contents were. */ | |
f6366fc7 | 986 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x)) |
5f4f0e22 | 987 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) |
230d793d | 988 | { |
2dab894a | 989 | if (set == 0 || GET_CODE (set) == CLOBBER) |
e8095e80 | 990 | { |
5eaad481 PB |
991 | reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
992 | reg_stat[REGNO (x)].sign_bit_copies = 1; | |
e8095e80 RK |
993 | return; |
994 | } | |
230d793d RS |
995 | |
996 | /* If this is a complex assignment, see if we can convert it into a | |
5089e22e | 997 | simple assignment. */ |
230d793d | 998 | set = expand_field_assignment (set); |
d79f08e0 RK |
999 | |
1000 | /* If this is a simple assignment, or we have a paradoxical SUBREG, | |
1001 | set what we know about X. */ | |
1002 | ||
1003 | if (SET_DEST (set) == x | |
1004 | || (GET_CODE (SET_DEST (set)) == SUBREG | |
705c7b3b JW |
1005 | && (GET_MODE_SIZE (GET_MODE (SET_DEST (set))) |
1006 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set))))) | |
d79f08e0 | 1007 | && SUBREG_REG (SET_DEST (set)) == x)) |
d0ab8cd3 | 1008 | { |
9afa3d54 RK |
1009 | rtx src = SET_SRC (set); |
1010 | ||
1011 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND | |
1012 | /* If X is narrower than a word and SRC is a non-negative | |
1013 | constant that would appear negative in the mode of X, | |
5eaad481 | 1014 | sign-extend it for use in reg_stat[].nonzero_bits because some |
9afa3d54 | 1015 | machines (maybe most) will actually do the sign-extension |
663522cb | 1016 | and this is the conservative approach. |
9afa3d54 RK |
1017 | |
1018 | ??? For 2.5, try to tighten up the MD files in this regard | |
1019 | instead of this kludge. */ | |
1020 | ||
1021 | if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD | |
1022 | && GET_CODE (src) == CONST_INT | |
1023 | && INTVAL (src) > 0 | |
1024 | && 0 != (INTVAL (src) | |
1025 | & ((HOST_WIDE_INT) 1 | |
9e69be8c | 1026 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
9afa3d54 RK |
1027 | src = GEN_INT (INTVAL (src) |
1028 | | ((HOST_WIDE_INT) (-1) | |
1029 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
1030 | #endif | |
1031 | ||
0a0440c9 | 1032 | /* Don't call nonzero_bits if it cannot change anything. */ |
5eaad481 PB |
1033 | if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0) |
1034 | reg_stat[REGNO (x)].nonzero_bits | |
0a0440c9 | 1035 | |= nonzero_bits (src, nonzero_bits_mode); |
d0ab8cd3 | 1036 | num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x)); |
5eaad481 PB |
1037 | if (reg_stat[REGNO (x)].sign_bit_copies == 0 |
1038 | || reg_stat[REGNO (x)].sign_bit_copies > num) | |
1039 | reg_stat[REGNO (x)].sign_bit_copies = num; | |
d0ab8cd3 | 1040 | } |
230d793d | 1041 | else |
d0ab8cd3 | 1042 | { |
5eaad481 PB |
1043 | reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x)); |
1044 | reg_stat[REGNO (x)].sign_bit_copies = 1; | |
d0ab8cd3 | 1045 | } |
230d793d RS |
1046 | } |
1047 | } | |
1048 | \f | |
1049 | /* See if INSN can be combined into I3. PRED and SUCC are optionally | |
1050 | insns that were previously combined into I3 or that will be combined | |
1051 | into the merger of INSN and I3. | |
1052 | ||
1053 | Return 0 if the combination is not allowed for any reason. | |
1054 | ||
663522cb | 1055 | If the combination is allowed, *PDEST will be set to the single |
230d793d RS |
1056 | destination of INSN and *PSRC to the single source, and this function |
1057 | will return 1. */ | |
1058 | ||
1059 | static int | |
79a490a9 AJ |
1060 | can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ, |
1061 | rtx *pdest, rtx *psrc) | |
230d793d RS |
1062 | { |
1063 | int i; | |
1064 | rtx set = 0, src, dest; | |
b729186a JL |
1065 | rtx p; |
1066 | #ifdef AUTO_INC_DEC | |
76d31c63 | 1067 | rtx link; |
b729186a | 1068 | #endif |
230d793d RS |
1069 | int all_adjacent = (succ ? (next_active_insn (insn) == succ |
1070 | && next_active_insn (succ) == i3) | |
1071 | : next_active_insn (insn) == i3); | |
1072 | ||
1073 | /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. | |
663522cb | 1074 | or a PARALLEL consisting of such a SET and CLOBBERs. |
230d793d RS |
1075 | |
1076 | If INSN has CLOBBER parallel parts, ignore them for our processing. | |
1077 | By definition, these happen during the execution of the insn. When it | |
1078 | is merged with another insn, all bets are off. If they are, in fact, | |
1079 | needed and aren't also supplied in I3, they may be added by | |
663522cb | 1080 | recog_for_combine. Otherwise, it won't match. |
230d793d RS |
1081 | |
1082 | We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
1083 | note. | |
1084 | ||
663522cb | 1085 | Get the source and destination of INSN. If more than one, can't |
230d793d | 1086 | combine. */ |
663522cb | 1087 | |
230d793d RS |
1088 | if (GET_CODE (PATTERN (insn)) == SET) |
1089 | set = PATTERN (insn); | |
1090 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
1091 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
1092 | { | |
1093 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1094 | { | |
1095 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
da6fdad3 | 1096 | rtx note; |
230d793d RS |
1097 | |
1098 | switch (GET_CODE (elt)) | |
1099 | { | |
e3258cef R |
1100 | /* This is important to combine floating point insns |
1101 | for the SH4 port. */ | |
1102 | case USE: | |
1103 | /* Combining an isolated USE doesn't make sense. | |
d2604ae9 | 1104 | We depend here on combinable_i3pat to reject them. */ |
e3258cef R |
1105 | /* The code below this loop only verifies that the inputs of |
1106 | the SET in INSN do not change. We call reg_set_between_p | |
eaec9b3d | 1107 | to verify that the REG in the USE does not change between |
e3258cef R |
1108 | I3 and INSN. |
1109 | If the USE in INSN was for a pseudo register, the matching | |
1110 | insn pattern will likely match any register; combining this | |
1111 | with any other USE would only be safe if we knew that the | |
1112 | used registers have identical values, or if there was | |
1113 | something to tell them apart, e.g. different modes. For | |
eaec9b3d | 1114 | now, we forgo such complicated tests and simply disallow |
e3258cef | 1115 | combining of USES of pseudo registers with any other USE. */ |
f8cfc6aa | 1116 | if (REG_P (XEXP (elt, 0)) |
e3258cef R |
1117 | && GET_CODE (PATTERN (i3)) == PARALLEL) |
1118 | { | |
1119 | rtx i3pat = PATTERN (i3); | |
1120 | int i = XVECLEN (i3pat, 0) - 1; | |
770ae6cc RK |
1121 | unsigned int regno = REGNO (XEXP (elt, 0)); |
1122 | ||
e3258cef R |
1123 | do |
1124 | { | |
1125 | rtx i3elt = XVECEXP (i3pat, 0, i); | |
770ae6cc | 1126 | |
e3258cef | 1127 | if (GET_CODE (i3elt) == USE |
f8cfc6aa | 1128 | && REG_P (XEXP (i3elt, 0)) |
e3258cef R |
1129 | && (REGNO (XEXP (i3elt, 0)) == regno |
1130 | ? reg_set_between_p (XEXP (elt, 0), | |
1131 | PREV_INSN (insn), i3) | |
1132 | : regno >= FIRST_PSEUDO_REGISTER)) | |
1133 | return 0; | |
1134 | } | |
1135 | while (--i >= 0); | |
1136 | } | |
1137 | break; | |
1138 | ||
230d793d RS |
1139 | /* We can ignore CLOBBERs. */ |
1140 | case CLOBBER: | |
1141 | break; | |
1142 | ||
1143 | case SET: | |
1144 | /* Ignore SETs whose result isn't used but not those that | |
1145 | have side-effects. */ | |
1146 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
da6fdad3 AM |
1147 | && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX)) |
1148 | || INTVAL (XEXP (note, 0)) <= 0) | |
230d793d RS |
1149 | && ! side_effects_p (elt)) |
1150 | break; | |
1151 | ||
1152 | /* If we have already found a SET, this is a second one and | |
1153 | so we cannot combine with this insn. */ | |
1154 | if (set) | |
1155 | return 0; | |
1156 | ||
1157 | set = elt; | |
1158 | break; | |
1159 | ||
1160 | default: | |
1161 | /* Anything else means we can't combine. */ | |
1162 | return 0; | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | if (set == 0 | |
1167 | /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
1168 | so don't do anything with it. */ | |
1169 | || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
1170 | return 0; | |
1171 | } | |
1172 | else | |
1173 | return 0; | |
1174 | ||
1175 | if (set == 0) | |
1176 | return 0; | |
1177 | ||
1178 | set = expand_field_assignment (set); | |
1179 | src = SET_SRC (set), dest = SET_DEST (set); | |
1180 | ||
1181 | /* Don't eliminate a store in the stack pointer. */ | |
1182 | if (dest == stack_pointer_rtx | |
230d793d RS |
1183 | /* Don't combine with an insn that sets a register to itself if it has |
1184 | a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ | |
5f4f0e22 | 1185 | || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX)) |
62f7f1f5 GK |
1186 | /* Can't merge an ASM_OPERANDS. */ |
1187 | || GET_CODE (src) == ASM_OPERANDS | |
230d793d RS |
1188 | /* Can't merge a function call. */ |
1189 | || GET_CODE (src) == CALL | |
cd5e8f1f | 1190 | /* Don't eliminate a function call argument. */ |
4b4bf941 | 1191 | || (CALL_P (i3) |
4dca5ec5 | 1192 | && (find_reg_fusage (i3, USE, dest) |
f8cfc6aa | 1193 | || (REG_P (dest) |
4dca5ec5 RK |
1194 | && REGNO (dest) < FIRST_PSEUDO_REGISTER |
1195 | && global_regs[REGNO (dest)]))) | |
230d793d RS |
1196 | /* Don't substitute into an incremented register. */ |
1197 | || FIND_REG_INC_NOTE (i3, dest) | |
1198 | || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
2f39b6ca UW |
1199 | /* Don't substitute into a non-local goto, this confuses CFG. */ |
1200 | || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX)) | |
ec35104c | 1201 | #if 0 |
230d793d | 1202 | /* Don't combine the end of a libcall into anything. */ |
ec35104c JL |
1203 | /* ??? This gives worse code, and appears to be unnecessary, since no |
1204 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does | |
1205 | use REG_RETVAL notes for noconflict blocks, but other code here | |
1206 | makes sure that those insns don't disappear. */ | |
5f4f0e22 | 1207 | || find_reg_note (insn, REG_RETVAL, NULL_RTX) |
ec35104c | 1208 | #endif |
230d793d RS |
1209 | /* Make sure that DEST is not used after SUCC but before I3. */ |
1210 | || (succ && ! all_adjacent | |
1211 | && reg_used_between_p (dest, succ, i3)) | |
1212 | /* Make sure that the value that is to be substituted for the register | |
1213 | does not use any registers whose values alter in between. However, | |
1214 | If the insns are adjacent, a use can't cross a set even though we | |
1215 | think it might (this can happen for a sequence of insns each setting | |
5eaad481 | 1216 | the same destination; last_set of that register might point to |
d81481d3 RK |
1217 | a NOTE). If INSN has a REG_EQUIV note, the register is always |
1218 | equivalent to the memory so the substitution is valid even if there | |
1219 | are intervening stores. Also, don't move a volatile asm or | |
1220 | UNSPEC_VOLATILE across any other insns. */ | |
230d793d | 1221 | || (! all_adjacent |
3c0cb5de | 1222 | && (((!MEM_P (src) |
d81481d3 RK |
1223 | || ! find_reg_note (insn, REG_EQUIV, src)) |
1224 | && use_crosses_set_p (src, INSN_CUID (insn))) | |
a66a10c7 RS |
1225 | || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)) |
1226 | || GET_CODE (src) == UNSPEC_VOLATILE)) | |
230d793d RS |
1227 | /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get |
1228 | better register allocation by not doing the combine. */ | |
1229 | || find_reg_note (i3, REG_NO_CONFLICT, dest) | |
1230 | || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) | |
1231 | /* Don't combine across a CALL_INSN, because that would possibly | |
1232 | change whether the life span of some REGs crosses calls or not, | |
1233 | and it is a pain to update that information. | |
1234 | Exception: if source is a constant, moving it later can't hurt. | |
1235 | Accept that special case, because it helps -fforce-addr a lot. */ | |
1236 | || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) | |
1237 | return 0; | |
1238 | ||
1239 | /* DEST must either be a REG or CC0. */ | |
f8cfc6aa | 1240 | if (REG_P (dest)) |
230d793d RS |
1241 | { |
1242 | /* If register alignment is being enforced for multi-word items in all | |
1243 | cases except for parameters, it is possible to have a register copy | |
1244 | insn referencing a hard register that is not allowed to contain the | |
1245 | mode being copied and which would not be valid as an operand of most | |
1246 | insns. Eliminate this problem by not combining with such an insn. | |
1247 | ||
1248 | Also, on some machines we don't want to extend the life of a hard | |
53895717 | 1249 | register. */ |
230d793d | 1250 | |
f8cfc6aa | 1251 | if (REG_P (src) |
230d793d RS |
1252 | && ((REGNO (dest) < FIRST_PSEUDO_REGISTER |
1253 | && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
c448a43e RK |
1254 | /* Don't extend the life of a hard register unless it is |
1255 | user variable (if we have few registers) or it can't | |
1256 | fit into the desired register (meaning something special | |
ecd40809 RK |
1257 | is going on). |
1258 | Also avoid substituting a return register into I3, because | |
1259 | reload can't handle a conflict with constraints of other | |
1260 | inputs. */ | |
230d793d | 1261 | || (REGNO (src) < FIRST_PSEUDO_REGISTER |
53895717 | 1262 | && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))))) |
230d793d RS |
1263 | return 0; |
1264 | } | |
1265 | else if (GET_CODE (dest) != CC0) | |
1266 | return 0; | |
1267 | ||
45da19e3 | 1268 | |
230d793d RS |
1269 | if (GET_CODE (PATTERN (i3)) == PARALLEL) |
1270 | for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
45da19e3 UW |
1271 | if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER) |
1272 | { | |
1273 | /* Don't substitute for a register intended as a clobberable | |
8c27b7d4 | 1274 | operand. */ |
45da19e3 UW |
1275 | rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0); |
1276 | if (rtx_equal_p (reg, dest)) | |
1277 | return 0; | |
1278 | ||
1279 | /* If the clobber represents an earlyclobber operand, we must not | |
1280 | substitute an expression containing the clobbered register. | |
647eea9d | 1281 | As we do not analyze the constraint strings here, we have to |
45da19e3 UW |
1282 | make the conservative assumption. However, if the register is |
1283 | a fixed hard reg, the clobber cannot represent any operand; | |
1284 | we leave it up to the machine description to either accept or | |
1285 | reject use-and-clobber patterns. */ | |
1286 | if (!REG_P (reg) | |
1287 | || REGNO (reg) >= FIRST_PSEUDO_REGISTER | |
1288 | || !fixed_regs[REGNO (reg)]) | |
1289 | if (reg_overlap_mentioned_p (reg, src)) | |
1290 | return 0; | |
1291 | } | |
230d793d RS |
1292 | |
1293 | /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
d276f2bb | 1294 | or not), reject, unless nothing volatile comes between it and I3 */ |
230d793d RS |
1295 | |
1296 | if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
d276f2bb CM |
1297 | { |
1298 | /* Make sure succ doesn't contain a volatile reference. */ | |
1299 | if (succ != 0 && volatile_refs_p (PATTERN (succ))) | |
1300 | return 0; | |
663522cb | 1301 | |
d276f2bb | 1302 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) |
2c3c49de | 1303 | if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p))) |
cf0d9408 | 1304 | return 0; |
d276f2bb | 1305 | } |
230d793d | 1306 | |
b79ee7eb RH |
1307 | /* If INSN is an asm, and DEST is a hard register, reject, since it has |
1308 | to be an explicit register variable, and was chosen for a reason. */ | |
1309 | ||
1310 | if (GET_CODE (src) == ASM_OPERANDS | |
f8cfc6aa | 1311 | && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER) |
b79ee7eb RH |
1312 | return 0; |
1313 | ||
4b2cb4a2 RS |
1314 | /* If there are any volatile insns between INSN and I3, reject, because |
1315 | they might affect machine state. */ | |
1316 | ||
1317 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
2c3c49de | 1318 | if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p))) |
4b2cb4a2 RS |
1319 | return 0; |
1320 | ||
17c9bcdd HPN |
1321 | /* If INSN contains an autoincrement or autodecrement, make sure that |
1322 | register is not used between there and I3, and not already used in | |
1323 | I3 either. Neither must it be used in PRED or SUCC, if they exist. | |
230d793d RS |
1324 | Also insist that I3 not be a jump; if it were one |
1325 | and the incremented register were spilled, we would lose. */ | |
1326 | ||
1327 | #ifdef AUTO_INC_DEC | |
1328 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
1329 | if (REG_NOTE_KIND (link) == REG_INC | |
4b4bf941 | 1330 | && (JUMP_P (i3) |
230d793d | 1331 | || reg_used_between_p (XEXP (link, 0), insn, i3) |
17c9bcdd HPN |
1332 | || (pred != NULL_RTX |
1333 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) | |
1334 | || (succ != NULL_RTX | |
1335 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ))) | |
230d793d RS |
1336 | || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) |
1337 | return 0; | |
1338 | #endif | |
1339 | ||
1340 | #ifdef HAVE_cc0 | |
1341 | /* Don't combine an insn that follows a CC0-setting insn. | |
1342 | An insn that uses CC0 must not be separated from the one that sets it. | |
1343 | We do, however, allow I2 to follow a CC0-setting insn if that insn | |
1344 | is passed as I1; in that case it will be deleted also. | |
1345 | We also allow combining in this case if all the insns are adjacent | |
1346 | because that would leave the two CC0 insns adjacent as well. | |
1347 | It would be more logical to test whether CC0 occurs inside I1 or I2, | |
1348 | but that would be much slower, and this ought to be equivalent. */ | |
1349 | ||
1350 | p = prev_nonnote_insn (insn); | |
4b4bf941 | 1351 | if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p)) |
230d793d RS |
1352 | && ! all_adjacent) |
1353 | return 0; | |
1354 | #endif | |
1355 | ||
1356 | /* If we get here, we have passed all the tests and the combination is | |
1357 | to be allowed. */ | |
1358 | ||
1359 | *pdest = dest; | |
1360 | *psrc = src; | |
1361 | ||
1362 | return 1; | |
1363 | } | |
1364 | \f | |
1365 | /* LOC is the location within I3 that contains its pattern or the component | |
1366 | of a PARALLEL of the pattern. We validate that it is valid for combining. | |
1367 | ||
1368 | One problem is if I3 modifies its output, as opposed to replacing it | |
1369 | entirely, we can't allow the output to contain I2DEST or I1DEST as doing | |
1370 | so would produce an insn that is not equivalent to the original insns. | |
1371 | ||
1372 | Consider: | |
1373 | ||
1374 | (set (reg:DI 101) (reg:DI 100)) | |
1375 | (set (subreg:SI (reg:DI 101) 0) <foo>) | |
1376 | ||
1377 | This is NOT equivalent to: | |
1378 | ||
1379 | (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) | |
23190837 | 1380 | (set (reg:DI 101) (reg:DI 100))]) |
230d793d RS |
1381 | |
1382 | Not only does this modify 100 (in which case it might still be valid | |
663522cb | 1383 | if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. |
230d793d RS |
1384 | |
1385 | We can also run into a problem if I2 sets a register that I1 | |
1386 | uses and I1 gets directly substituted into I3 (not via I2). In that | |
1387 | case, we would be getting the wrong value of I2DEST into I3, so we | |
1388 | must reject the combination. This case occurs when I2 and I1 both | |
1389 | feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
da7d8304 | 1390 | If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source |
230d793d RS |
1391 | of a SET must prevent combination from occurring. |
1392 | ||
230d793d RS |
1393 | Before doing the above check, we first try to expand a field assignment |
1394 | into a set of logical operations. | |
1395 | ||
da7d8304 | 1396 | If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which |
230d793d RS |
1397 | we place a register that is both set and used within I3. If more than one |
1398 | such register is detected, we fail. | |
1399 | ||
1400 | Return 1 if the combination is valid, zero otherwise. */ | |
1401 | ||
1402 | static int | |
79a490a9 AJ |
1403 | combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, |
1404 | int i1_not_in_src, rtx *pi3dest_killed) | |
230d793d RS |
1405 | { |
1406 | rtx x = *loc; | |
1407 | ||
1408 | if (GET_CODE (x) == SET) | |
1409 | { | |
73a39fc4 | 1410 | rtx set = x ; |
230d793d RS |
1411 | rtx dest = SET_DEST (set); |
1412 | rtx src = SET_SRC (set); | |
29a82058 | 1413 | rtx inner_dest = dest; |
663522cb | 1414 | |
230d793d RS |
1415 | while (GET_CODE (inner_dest) == STRICT_LOW_PART |
1416 | || GET_CODE (inner_dest) == SUBREG | |
1417 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
1418 | inner_dest = XEXP (inner_dest, 0); | |
1419 | ||
0595d388 AO |
1420 | /* Check for the case where I3 modifies its output, as discussed |
1421 | above. We don't want to prevent pseudos from being combined | |
1422 | into the address of a MEM, so only prevent the combination if | |
1423 | i1 or i2 set the same MEM. */ | |
1424 | if ((inner_dest != dest && | |
3c0cb5de | 1425 | (!MEM_P (inner_dest) |
0595d388 AO |
1426 | || rtx_equal_p (i2dest, inner_dest) |
1427 | || (i1dest && rtx_equal_p (i1dest, inner_dest))) | |
230d793d RS |
1428 | && (reg_overlap_mentioned_p (i2dest, inner_dest) |
1429 | || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) | |
956d6950 | 1430 | |
53895717 BS |
1431 | /* This is the same test done in can_combine_p except we can't test |
1432 | all_adjacent; we don't have to, since this instruction will stay | |
1433 | in place, thus we are not considering increasing the lifetime of | |
1434 | INNER_DEST. | |
956d6950 JL |
1435 | |
1436 | Also, if this insn sets a function argument, combining it with | |
1437 | something that might need a spill could clobber a previous | |
1438 | function argument; the all_adjacent test in can_combine_p also | |
1439 | checks this; here, we do a more specific test for this case. */ | |
663522cb | 1440 | |
f8cfc6aa | 1441 | || (REG_P (inner_dest) |
dfbe1b2f | 1442 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER |
c448a43e | 1443 | && (! HARD_REGNO_MODE_OK (REGNO (inner_dest), |
53895717 | 1444 | GET_MODE (inner_dest)))) |
230d793d RS |
1445 | || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) |
1446 | return 0; | |
1447 | ||
1448 | /* If DEST is used in I3, it is being killed in this insn, | |
663522cb | 1449 | so record that for later. |
36a9c2e9 JL |
1450 | Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the |
1451 | STACK_POINTER_REGNUM, since these are always considered to be | |
1452 | live. Similarly for ARG_POINTER_REGNUM if it is fixed. */ | |
f8cfc6aa | 1453 | if (pi3dest_killed && REG_P (dest) |
36a9c2e9 JL |
1454 | && reg_referenced_p (dest, PATTERN (i3)) |
1455 | && REGNO (dest) != FRAME_POINTER_REGNUM | |
6d7096b0 DE |
1456 | #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1457 | && REGNO (dest) != HARD_FRAME_POINTER_REGNUM | |
1458 | #endif | |
36a9c2e9 JL |
1459 | #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM |
1460 | && (REGNO (dest) != ARG_POINTER_REGNUM | |
1461 | || ! fixed_regs [REGNO (dest)]) | |
1462 | #endif | |
1463 | && REGNO (dest) != STACK_POINTER_REGNUM) | |
230d793d RS |
1464 | { |
1465 | if (*pi3dest_killed) | |
1466 | return 0; | |
1467 | ||
1468 | *pi3dest_killed = dest; | |
1469 | } | |
1470 | } | |
1471 | ||
1472 | else if (GET_CODE (x) == PARALLEL) | |
1473 | { | |
1474 | int i; | |
1475 | ||
1476 | for (i = 0; i < XVECLEN (x, 0); i++) | |
1477 | if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, | |
1478 | i1_not_in_src, pi3dest_killed)) | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | return 1; | |
1483 | } | |
1484 | \f | |
14a774a9 RK |
1485 | /* Return 1 if X is an arithmetic expression that contains a multiplication |
1486 | and division. We don't count multiplications by powers of two here. */ | |
1487 | ||
1488 | static int | |
79a490a9 | 1489 | contains_muldiv (rtx x) |
14a774a9 RK |
1490 | { |
1491 | switch (GET_CODE (x)) | |
1492 | { | |
1493 | case MOD: case DIV: case UMOD: case UDIV: | |
1494 | return 1; | |
1495 | ||
1496 | case MULT: | |
1497 | return ! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1498 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0); | |
1499 | default: | |
ec8e098d PB |
1500 | if (BINARY_P (x)) |
1501 | return contains_muldiv (XEXP (x, 0)) | |
14a774a9 RK |
1502 | || contains_muldiv (XEXP (x, 1)); |
1503 | ||
ec8e098d PB |
1504 | if (UNARY_P (x)) |
1505 | return contains_muldiv (XEXP (x, 0)); | |
14a774a9 | 1506 | |
ec8e098d | 1507 | return 0; |
14a774a9 RK |
1508 | } |
1509 | } | |
1510 | \f | |
c3410241 BS |
1511 | /* Determine whether INSN can be used in a combination. Return nonzero if |
1512 | not. This is used in try_combine to detect early some cases where we | |
1513 | can't perform combinations. */ | |
1514 | ||
1515 | static int | |
79a490a9 | 1516 | cant_combine_insn_p (rtx insn) |
c3410241 BS |
1517 | { |
1518 | rtx set; | |
1519 | rtx src, dest; | |
23190837 | 1520 | |
c3410241 BS |
1521 | /* If this isn't really an insn, we can't do anything. |
1522 | This can occur when flow deletes an insn that it has merged into an | |
1523 | auto-increment address. */ | |
1524 | if (! INSN_P (insn)) | |
1525 | return 1; | |
1526 | ||
7f0ea82e R |
1527 | /* Never combine loads and stores involving hard regs that are likely |
1528 | to be spilled. The register allocator can usually handle such | |
cafe096b | 1529 | reg-reg moves by tying. If we allow the combiner to make |
535a42b1 | 1530 | substitutions of likely-spilled regs, reload might die. |
c3410241 BS |
1531 | As an exception, we allow combinations involving fixed regs; these are |
1532 | not available to the register allocator so there's no risk involved. */ | |
1533 | ||
1534 | set = single_set (insn); | |
1535 | if (! set) | |
1536 | return 0; | |
1537 | src = SET_SRC (set); | |
1538 | dest = SET_DEST (set); | |
ad334b51 JH |
1539 | if (GET_CODE (src) == SUBREG) |
1540 | src = SUBREG_REG (src); | |
1541 | if (GET_CODE (dest) == SUBREG) | |
1542 | dest = SUBREG_REG (dest); | |
53895717 BS |
1543 | if (REG_P (src) && REG_P (dest) |
1544 | && ((REGNO (src) < FIRST_PSEUDO_REGISTER | |
7f0ea82e R |
1545 | && ! fixed_regs[REGNO (src)] |
1546 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src)))) | |
53895717 | 1547 | || (REGNO (dest) < FIRST_PSEUDO_REGISTER |
7f0ea82e R |
1548 | && ! fixed_regs[REGNO (dest)] |
1549 | && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest)))))) | |
c3410241 | 1550 | return 1; |
53895717 | 1551 | |
c3410241 BS |
1552 | return 0; |
1553 | } | |
1554 | ||
8c03ca00 EB |
1555 | /* Adjust INSN after we made a change to its destination. |
1556 | ||
1557 | Changing the destination can invalidate notes that say something about | |
1558 | the results of the insn and a LOG_LINK pointing to the insn. */ | |
1559 | ||
1560 | static void | |
1561 | adjust_for_new_dest (rtx insn) | |
1562 | { | |
1563 | rtx *loc; | |
1564 | ||
1565 | /* For notes, be conservative and simply remove them. */ | |
1566 | loc = ®_NOTES (insn); | |
1567 | while (*loc) | |
1568 | { | |
1569 | enum reg_note kind = REG_NOTE_KIND (*loc); | |
1570 | if (kind == REG_EQUAL || kind == REG_EQUIV) | |
1571 | *loc = XEXP (*loc, 1); | |
1572 | else | |
1573 | loc = &XEXP (*loc, 1); | |
1574 | } | |
1575 | ||
1576 | /* The new insn will have a destination that was previously the destination | |
1577 | of an insn just above it. Call distribute_links to make a LOG_LINK from | |
1578 | the next use of that destination. */ | |
1579 | distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX)); | |
1580 | } | |
1581 | ||
230d793d RS |
1582 | /* Try to combine the insns I1 and I2 into I3. |
1583 | Here I1 and I2 appear earlier than I3. | |
1584 | I1 can be zero; then we combine just I2 into I3. | |
663522cb | 1585 | |
04956a1a | 1586 | If we are combining three insns and the resulting insn is not recognized, |
230d793d RS |
1587 | try splitting it into two insns. If that happens, I2 and I3 are retained |
1588 | and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 | |
1589 | are pseudo-deleted. | |
1590 | ||
663522cb | 1591 | Return 0 if the combination does not work. Then nothing is changed. |
abe6e52f | 1592 | If we did the combination, return the insn at which combine should |
663522cb KH |
1593 | resume scanning. |
1594 | ||
da7d8304 | 1595 | Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a |
44a76fc8 | 1596 | new direct jump instruction. */ |
230d793d RS |
1597 | |
1598 | static rtx | |
79a490a9 | 1599 | try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p) |
230d793d | 1600 | { |
02359929 | 1601 | /* New patterns for I3 and I2, respectively. */ |
230d793d | 1602 | rtx newpat, newi2pat = 0; |
9b12dc4f | 1603 | rtvec newpat_vec_with_clobbers = 0; |
cddd8b72 | 1604 | int substed_i2 = 0, substed_i1 = 0; |
230d793d RS |
1605 | /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ |
1606 | int added_sets_1, added_sets_2; | |
1607 | /* Total number of SETs to put into I3. */ | |
1608 | int total_sets; | |
a1105617 | 1609 | /* Nonzero if I2's body now appears in I3. */ |
230d793d RS |
1610 | int i2_is_used; |
1611 | /* INSN_CODEs for new I3, new I2, and user of condition code. */ | |
6a651371 | 1612 | int insn_code_number, i2_code_number = 0, other_code_number = 0; |
230d793d RS |
1613 | /* Contains I3 if the destination of I3 is used in its source, which means |
1614 | that the old life of I3 is being killed. If that usage is placed into | |
1615 | I2 and not in I3, a REG_DEAD note must be made. */ | |
1616 | rtx i3dest_killed = 0; | |
1617 | /* SET_DEST and SET_SRC of I2 and I1. */ | |
1618 | rtx i2dest, i2src, i1dest = 0, i1src = 0; | |
1619 | /* PATTERN (I2), or a copy of it in certain cases. */ | |
1620 | rtx i2pat; | |
1621 | /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ | |
c4e861e8 | 1622 | int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0; |
230d793d RS |
1623 | int i1_feeds_i3 = 0; |
1624 | /* Notes that must be added to REG_NOTES in I3 and I2. */ | |
1625 | rtx new_i3_notes, new_i2_notes; | |
176c9e6b JW |
1626 | /* Notes that we substituted I3 into I2 instead of the normal case. */ |
1627 | int i3_subst_into_i2 = 0; | |
df7d75de RK |
1628 | /* Notes that I1, I2 or I3 is a MULT operation. */ |
1629 | int have_mult = 0; | |
9e42ab3e | 1630 | int swap_i2i3 = 0; |
230d793d RS |
1631 | |
1632 | int maxreg; | |
1633 | rtx temp; | |
b3694847 | 1634 | rtx link; |
230d793d RS |
1635 | int i; |
1636 | ||
c3410241 BS |
1637 | /* Exit early if one of the insns involved can't be used for |
1638 | combinations. */ | |
1639 | if (cant_combine_insn_p (i3) | |
1640 | || cant_combine_insn_p (i2) | |
1641 | || (i1 && cant_combine_insn_p (i1)) | |
1642 | /* We also can't do anything if I3 has a | |
1643 | REG_LIBCALL note since we don't want to disrupt the contiguity of a | |
1644 | libcall. */ | |
ec35104c JL |
1645 | #if 0 |
1646 | /* ??? This gives worse code, and appears to be unnecessary, since no | |
1647 | pass after flow uses REG_LIBCALL/REG_RETVAL notes. */ | |
1648 | || find_reg_note (i3, REG_LIBCALL, NULL_RTX) | |
1649 | #endif | |
663522cb | 1650 | ) |
230d793d RS |
1651 | return 0; |
1652 | ||
1653 | combine_attempts++; | |
230d793d RS |
1654 | undobuf.other_insn = 0; |
1655 | ||
6e25d159 RK |
1656 | /* Reset the hard register usage information. */ |
1657 | CLEAR_HARD_REG_SET (newpat_used_regs); | |
1658 | ||
230d793d RS |
1659 | /* If I1 and I2 both feed I3, they can be in any order. To simplify the |
1660 | code below, set I1 to be the earlier of the two insns. */ | |
1661 | if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) | |
1662 | temp = i1, i1 = i2, i2 = temp; | |
1663 | ||
abe6e52f | 1664 | added_links_insn = 0; |
137e889e | 1665 | |
230d793d | 1666 | /* First check for one important special-case that the code below will |
c7be4f66 | 1667 | not handle. Namely, the case where I1 is zero, I2 is a PARALLEL |
230d793d RS |
1668 | and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, |
1669 | we may be able to replace that destination with the destination of I3. | |
1670 | This occurs in the common code where we compute both a quotient and | |
1671 | remainder into a structure, in which case we want to do the computation | |
1672 | directly into the structure to avoid register-register copies. | |
1673 | ||
c7be4f66 RK |
1674 | Note that this case handles both multiple sets in I2 and also |
1675 | cases where I2 has a number of CLOBBER or PARALLELs. | |
1676 | ||
230d793d RS |
1677 | We make very conservative checks below and only try to handle the |
1678 | most common cases of this. For example, we only handle the case | |
1679 | where I2 and I3 are adjacent to avoid making difficult register | |
1680 | usage tests. */ | |
1681 | ||
4b4bf941 | 1682 | if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET |
f8cfc6aa | 1683 | && REG_P (SET_SRC (PATTERN (i3))) |
230d793d | 1684 | && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER |
230d793d RS |
1685 | && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) |
1686 | && GET_CODE (PATTERN (i2)) == PARALLEL | |
1687 | && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
5089e22e RS |
1688 | /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code |
1689 | below would need to check what is inside (and reg_overlap_mentioned_p | |
1690 | doesn't support those codes anyway). Don't allow those destinations; | |
1691 | the resulting insn isn't likely to be recognized anyway. */ | |
1692 | && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
1693 | && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
230d793d RS |
1694 | && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), |
1695 | SET_DEST (PATTERN (i3))) | |
1696 | && next_real_insn (i2) == i3) | |
5089e22e RS |
1697 | { |
1698 | rtx p2 = PATTERN (i2); | |
1699 | ||
1700 | /* Make sure that the destination of I3, | |
1701 | which we are going to substitute into one output of I2, | |
1702 | is not used within another output of I2. We must avoid making this: | |
1703 | (parallel [(set (mem (reg 69)) ...) | |
1704 | (set (reg 69) ...)]) | |
1705 | which is not well-defined as to order of actions. | |
1706 | (Besides, reload can't handle output reloads for this.) | |
1707 | ||
1708 | The problem can also happen if the dest of I3 is a memory ref, | |
1709 | if another dest in I2 is an indirect memory ref. */ | |
1710 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
7ca919b7 RK |
1711 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1712 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
5089e22e RS |
1713 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), |
1714 | SET_DEST (XVECEXP (p2, 0, i)))) | |
1715 | break; | |
230d793d | 1716 | |
5089e22e RS |
1717 | if (i == XVECLEN (p2, 0)) |
1718 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
481c7efa FS |
1719 | if ((GET_CODE (XVECEXP (p2, 0, i)) == SET |
1720 | || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) | |
1721 | && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) | |
5089e22e RS |
1722 | { |
1723 | combine_merges++; | |
230d793d | 1724 | |
5089e22e RS |
1725 | subst_insn = i3; |
1726 | subst_low_cuid = INSN_CUID (i2); | |
230d793d | 1727 | |
c4e861e8 | 1728 | added_sets_2 = added_sets_1 = 0; |
5089e22e | 1729 | i2dest = SET_SRC (PATTERN (i3)); |
230d793d | 1730 | |
5089e22e RS |
1731 | /* Replace the dest in I2 with our dest and make the resulting |
1732 | insn the new pattern for I3. Then skip to where we | |
1733 | validate the pattern. Everything was set up above. */ | |
663522cb | 1734 | SUBST (SET_DEST (XVECEXP (p2, 0, i)), |
5089e22e RS |
1735 | SET_DEST (PATTERN (i3))); |
1736 | ||
1737 | newpat = p2; | |
176c9e6b | 1738 | i3_subst_into_i2 = 1; |
5089e22e RS |
1739 | goto validate_replacement; |
1740 | } | |
1741 | } | |
230d793d | 1742 | |
667c1c2c RK |
1743 | /* If I2 is setting a double-word pseudo to a constant and I3 is setting |
1744 | one of those words to another constant, merge them by making a new | |
1745 | constant. */ | |
1746 | if (i1 == 0 | |
1747 | && (temp = single_set (i2)) != 0 | |
1748 | && (GET_CODE (SET_SRC (temp)) == CONST_INT | |
1749 | || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE) | |
f8cfc6aa | 1750 | && REG_P (SET_DEST (temp)) |
667c1c2c RK |
1751 | && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT |
1752 | && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD | |
1753 | && GET_CODE (PATTERN (i3)) == SET | |
1754 | && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG | |
1755 | && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp) | |
1756 | && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT | |
1757 | && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD | |
1758 | && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT) | |
1759 | { | |
1760 | HOST_WIDE_INT lo, hi; | |
1761 | ||
1762 | if (GET_CODE (SET_SRC (temp)) == CONST_INT) | |
1763 | lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0; | |
1764 | else | |
1765 | { | |
1766 | lo = CONST_DOUBLE_LOW (SET_SRC (temp)); | |
1767 | hi = CONST_DOUBLE_HIGH (SET_SRC (temp)); | |
1768 | } | |
1769 | ||
1770 | if (subreg_lowpart_p (SET_DEST (PATTERN (i3)))) | |
48b4d901 AO |
1771 | { |
1772 | /* We don't handle the case of the target word being wider | |
1773 | than a host wide int. */ | |
341c100f | 1774 | gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD); |
48b4d901 | 1775 | |
42a6ff51 | 1776 | lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1); |
73a39fc4 | 1777 | lo |= (INTVAL (SET_SRC (PATTERN (i3))) |
2ef1a7f9 | 1778 | & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); |
48b4d901 AO |
1779 | } |
1780 | else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD) | |
667c1c2c | 1781 | hi = INTVAL (SET_SRC (PATTERN (i3))); |
48b4d901 AO |
1782 | else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD) |
1783 | { | |
1784 | int sign = -(int) ((unsigned HOST_WIDE_INT) lo | |
1785 | >> (HOST_BITS_PER_WIDE_INT - 1)); | |
1786 | ||
42a6ff51 AO |
1787 | lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD |
1788 | (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1)); | |
1789 | lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD | |
1790 | (INTVAL (SET_SRC (PATTERN (i3))))); | |
48b4d901 AO |
1791 | if (hi == sign) |
1792 | hi = lo < 0 ? -1 : 0; | |
1793 | } | |
1794 | else | |
1795 | /* We don't handle the case of the higher word not fitting | |
1796 | entirely in either hi or lo. */ | |
341c100f | 1797 | gcc_unreachable (); |
667c1c2c RK |
1798 | |
1799 | combine_merges++; | |
1800 | subst_insn = i3; | |
1801 | subst_low_cuid = INSN_CUID (i2); | |
1802 | added_sets_2 = added_sets_1 = 0; | |
1803 | i2dest = SET_DEST (temp); | |
1804 | ||
1805 | SUBST (SET_SRC (temp), | |
1806 | immed_double_const (lo, hi, GET_MODE (SET_DEST (temp)))); | |
1807 | ||
1808 | newpat = PATTERN (i2); | |
667c1c2c RK |
1809 | goto validate_replacement; |
1810 | } | |
1811 | ||
230d793d RS |
1812 | #ifndef HAVE_cc0 |
1813 | /* If we have no I1 and I2 looks like: | |
1814 | (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
1815 | (set Y OP)]) | |
1816 | make up a dummy I1 that is | |
1817 | (set Y OP) | |
1818 | and change I2 to be | |
1819 | (set (reg:CC X) (compare:CC Y (const_int 0))) | |
1820 | ||
1821 | (We can ignore any trailing CLOBBERs.) | |
1822 | ||
1823 | This undoes a previous combination and allows us to match a branch-and- | |
1824 | decrement insn. */ | |
1825 | ||
1826 | if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
1827 | && XVECLEN (PATTERN (i2), 0) >= 2 | |
1828 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
1829 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
1830 | == MODE_CC) | |
1831 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
1832 | && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
1833 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
f8cfc6aa | 1834 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) |
230d793d RS |
1835 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), |
1836 | SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
1837 | { | |
663522cb | 1838 | for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) |
230d793d RS |
1839 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) |
1840 | break; | |
1841 | ||
1842 | if (i == 1) | |
1843 | { | |
1844 | /* We make I1 with the same INSN_UID as I2. This gives it | |
1845 | the same INSN_CUID for value tracking. Our fake I1 will | |
1846 | never appear in the insn stream so giving it the same INSN_UID | |
1847 | as I2 will not cause a problem. */ | |
1848 | ||
4977bab6 | 1849 | i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2, |
0435312e | 1850 | BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2), |
4977bab6 ZW |
1851 | XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, |
1852 | NULL_RTX); | |
230d793d RS |
1853 | |
1854 | SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
1855 | SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
1856 | SET_DEST (PATTERN (i1))); | |
1857 | } | |
1858 | } | |
1859 | #endif | |
1860 | ||
1861 | /* Verify that I2 and I1 are valid for combining. */ | |
5f4f0e22 CH |
1862 | if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src) |
1863 | || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src))) | |
230d793d RS |
1864 | { |
1865 | undo_all (); | |
1866 | return 0; | |
1867 | } | |
1868 | ||
1869 | /* Record whether I2DEST is used in I2SRC and similarly for the other | |
1870 | cases. Knowing this will help in register status updating below. */ | |
1871 | i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
1872 | i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
1873 | i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
1874 | ||
916f14f1 | 1875 | /* See if I1 directly feeds into I3. It does if I1DEST is not used |
230d793d RS |
1876 | in I2SRC. */ |
1877 | i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); | |
1878 | ||
1879 | /* Ensure that I3's pattern can be the destination of combines. */ | |
1880 | if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, | |
1881 | i1 && i2dest_in_i1src && i1_feeds_i3, | |
1882 | &i3dest_killed)) | |
1883 | { | |
1884 | undo_all (); | |
1885 | return 0; | |
1886 | } | |
1887 | ||
df7d75de RK |
1888 | /* See if any of the insns is a MULT operation. Unless one is, we will |
1889 | reject a combination that is, since it must be slower. Be conservative | |
1890 | here. */ | |
1891 | if (GET_CODE (i2src) == MULT | |
1892 | || (i1 != 0 && GET_CODE (i1src) == MULT) | |
1893 | || (GET_CODE (PATTERN (i3)) == SET | |
1894 | && GET_CODE (SET_SRC (PATTERN (i3))) == MULT)) | |
1895 | have_mult = 1; | |
1896 | ||
230d793d RS |
1897 | /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. |
1898 | We used to do this EXCEPT in one case: I3 has a post-inc in an | |
1899 | output operand. However, that exception can give rise to insns like | |
23190837 | 1900 | mov r3,(r3)+ |
230d793d | 1901 | which is a famous insn on the PDP-11 where the value of r3 used as the |
5089e22e | 1902 | source was model-dependent. Avoid this sort of thing. */ |
230d793d RS |
1903 | |
1904 | #if 0 | |
1905 | if (!(GET_CODE (PATTERN (i3)) == SET | |
f8cfc6aa | 1906 | && REG_P (SET_SRC (PATTERN (i3))) |
3c0cb5de | 1907 | && MEM_P (SET_DEST (PATTERN (i3))) |
230d793d RS |
1908 | && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC |
1909 | || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
1910 | /* It's not the exception. */ | |
1911 | #endif | |
1912 | #ifdef AUTO_INC_DEC | |
1913 | for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
1914 | if (REG_NOTE_KIND (link) == REG_INC | |
1915 | && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
1916 | || (i1 != 0 | |
1917 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
1918 | { | |
1919 | undo_all (); | |
1920 | return 0; | |
1921 | } | |
1922 | #endif | |
1923 | ||
1924 | /* See if the SETs in I1 or I2 need to be kept around in the merged | |
1925 | instruction: whenever the value set there is still needed past I3. | |
1926 | For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. | |
1927 | ||
1928 | For the SET in I1, we have two cases: If I1 and I2 independently | |
1929 | feed into I3, the set in I1 needs to be kept around if I1DEST dies | |
1930 | or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set | |
1931 | in I1 needs to be kept around unless I1DEST dies or is set in either | |
1932 | I2 or I3. We can distinguish these cases by seeing if I2SRC mentions | |
1933 | I1DEST. If so, we know I1 feeds into I2. */ | |
1934 | ||
1935 | added_sets_2 = ! dead_or_set_p (i3, i2dest); | |
1936 | ||
1937 | added_sets_1 | |
1938 | = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | |
1939 | : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | |
1940 | ||
1941 | /* If the set in I2 needs to be kept around, we must make a copy of | |
1942 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
5089e22e | 1943 | PATTERN (I2), we are only substituting for the original I1DEST, not into |
230d793d RS |
1944 | an already-substituted copy. This also prevents making self-referential |
1945 | rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
1946 | I2DEST. */ | |
1947 | ||
1948 | i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL | |
38a448ca | 1949 | ? gen_rtx_SET (VOIDmode, i2dest, i2src) |
230d793d RS |
1950 | : PATTERN (i2)); |
1951 | ||
1952 | if (added_sets_2) | |
1953 | i2pat = copy_rtx (i2pat); | |
1954 | ||
1955 | combine_merges++; | |
1956 | ||
1957 | /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
1958 | ||
1959 | maxreg = max_reg_num (); | |
1960 | ||
1961 | subst_insn = i3; | |
230d793d RS |
1962 | |
1963 | /* It is possible that the source of I2 or I1 may be performing an | |
1964 | unneeded operation, such as a ZERO_EXTEND of something that is known | |
1965 | to have the high part zero. Handle that case by letting subst look at | |
1966 | the innermost one of them. | |
1967 | ||
1968 | Another way to do this would be to have a function that tries to | |
1969 | simplify a single insn instead of merging two or more insns. We don't | |
1970 | do this because of the potential of infinite loops and because | |
1971 | of the potential extra memory required. However, doing it the way | |
1972 | we are is a bit of a kludge and doesn't catch all cases. | |
1973 | ||
1974 | But only do this if -fexpensive-optimizations since it slows things down | |
1975 | and doesn't usually win. */ | |
1976 | ||
1977 | if (flag_expensive_optimizations) | |
1978 | { | |
9a5a17f3 | 1979 | /* Pass pc_rtx so no substitutions are done, just simplifications. */ |
230d793d | 1980 | if (i1) |
d0ab8cd3 RK |
1981 | { |
1982 | subst_low_cuid = INSN_CUID (i1); | |
1983 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | |
1984 | } | |
230d793d | 1985 | else |
d0ab8cd3 RK |
1986 | { |
1987 | subst_low_cuid = INSN_CUID (i2); | |
1988 | i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | |
1989 | } | |
230d793d RS |
1990 | } |
1991 | ||
1992 | #ifndef HAVE_cc0 | |
1993 | /* Many machines that don't use CC0 have insns that can both perform an | |
1994 | arithmetic operation and set the condition code. These operations will | |
1995 | be represented as a PARALLEL with the first element of the vector | |
1996 | being a COMPARE of an arithmetic operation with the constant zero. | |
1997 | The second element of the vector will set some pseudo to the result | |
1998 | of the same arithmetic operation. If we simplify the COMPARE, we won't | |
1999 | match such a pattern and so will generate an extra insn. Here we test | |
2000 | for this case, where both the comparison and the operation result are | |
2001 | needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
2002 | I2SRC. Later we will make the PARALLEL that contains I2. */ | |
2003 | ||
2004 | if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
2005 | && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
2006 | && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx | |
2007 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) | |
2008 | { | |
94134f42 | 2009 | #ifdef SELECT_CC_MODE |
230d793d RS |
2010 | rtx *cc_use; |
2011 | enum machine_mode compare_mode; | |
081f5e7e | 2012 | #endif |
230d793d RS |
2013 | |
2014 | newpat = PATTERN (i3); | |
2015 | SUBST (XEXP (SET_SRC (newpat), 0), i2src); | |
2016 | ||
2017 | i2_is_used = 1; | |
2018 | ||
94134f42 | 2019 | #ifdef SELECT_CC_MODE |
230d793d RS |
2020 | /* See if a COMPARE with the operand we substituted in should be done |
2021 | with the mode that is currently being used. If not, do the same | |
2022 | processing we do in `subst' for a SET; namely, if the destination | |
2023 | is used only once, try to replace it with a register of the proper | |
2024 | mode and also replace the COMPARE. */ | |
2025 | if (undobuf.other_insn == 0 | |
2026 | && (cc_use = find_single_use (SET_DEST (newpat), i3, | |
2027 | &undobuf.other_insn)) | |
77fa0940 RK |
2028 | && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), |
2029 | i2src, const0_rtx)) | |
230d793d RS |
2030 | != GET_MODE (SET_DEST (newpat)))) |
2031 | { | |
770ae6cc | 2032 | unsigned int regno = REGNO (SET_DEST (newpat)); |
38a448ca | 2033 | rtx new_dest = gen_rtx_REG (compare_mode, regno); |
230d793d RS |
2034 | |
2035 | if (regno < FIRST_PSEUDO_REGISTER | |
b1f21e0a | 2036 | || (REG_N_SETS (regno) == 1 && ! added_sets_2 |
230d793d RS |
2037 | && ! REG_USERVAR_P (SET_DEST (newpat)))) |
2038 | { | |
2039 | if (regno >= FIRST_PSEUDO_REGISTER) | |
2040 | SUBST (regno_reg_rtx[regno], new_dest); | |
2041 | ||
2042 | SUBST (SET_DEST (newpat), new_dest); | |
2043 | SUBST (XEXP (*cc_use, 0), new_dest); | |
2044 | SUBST (SET_SRC (newpat), | |
f1c6ba8b | 2045 | gen_rtx_COMPARE (compare_mode, i2src, const0_rtx)); |
230d793d RS |
2046 | } |
2047 | else | |
2048 | undobuf.other_insn = 0; | |
2049 | } | |
663522cb | 2050 | #endif |
230d793d RS |
2051 | } |
2052 | else | |
2053 | #endif | |
2054 | { | |
2055 | n_occurrences = 0; /* `subst' counts here */ | |
2056 | ||
2057 | /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we | |
2058 | need to make a unique copy of I2SRC each time we substitute it | |
2059 | to avoid self-referential rtl. */ | |
2060 | ||
d0ab8cd3 | 2061 | subst_low_cuid = INSN_CUID (i2); |
230d793d RS |
2062 | newpat = subst (PATTERN (i3), i2dest, i2src, 0, |
2063 | ! i1_feeds_i3 && i1dest_in_i1src); | |
cddd8b72 | 2064 | substed_i2 = 1; |
230d793d RS |
2065 | |
2066 | /* Record whether i2's body now appears within i3's body. */ | |
2067 | i2_is_used = n_occurrences; | |
2068 | } | |
2069 | ||
2070 | /* If we already got a failure, don't try to do more. Otherwise, | |
2071 | try to substitute in I1 if we have it. */ | |
2072 | ||
2073 | if (i1 && GET_CODE (newpat) != CLOBBER) | |
2074 | { | |
2075 | /* Before we can do this substitution, we must redo the test done | |
2076 | above (see detailed comments there) that ensures that I1DEST | |
0f41302f | 2077 | isn't mentioned in any SETs in NEWPAT that are field assignments. */ |
230d793d | 2078 | |
5f4f0e22 | 2079 | if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, |
cf0d9408 | 2080 | 0, (rtx*) 0)) |
230d793d RS |
2081 | { |
2082 | undo_all (); | |
2083 | return 0; | |
2084 | } | |
2085 | ||
2086 | n_occurrences = 0; | |
d0ab8cd3 | 2087 | subst_low_cuid = INSN_CUID (i1); |
230d793d | 2088 | newpat = subst (newpat, i1dest, i1src, 0, 0); |
cddd8b72 | 2089 | substed_i1 = 1; |
230d793d RS |
2090 | } |
2091 | ||
916f14f1 RK |
2092 | /* Fail if an autoincrement side-effect has been duplicated. Be careful |
2093 | to count all the ways that I2SRC and I1SRC can be used. */ | |
5f4f0e22 | 2094 | if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0 |
916f14f1 | 2095 | && i2_is_used + added_sets_2 > 1) |
5f4f0e22 | 2096 | || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0 |
916f14f1 RK |
2097 | && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) |
2098 | > 1)) | |
535a42b1 | 2099 | /* Fail if we tried to make a new register. */ |
230d793d RS |
2100 | || max_reg_num () != maxreg |
2101 | /* Fail if we couldn't do something and have a CLOBBER. */ | |
df7d75de RK |
2102 | || GET_CODE (newpat) == CLOBBER |
2103 | /* Fail if this new pattern is a MULT and we didn't have one before | |
2104 | at the outer level. */ | |
2105 | || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT | |
2106 | && ! have_mult)) | |
230d793d RS |
2107 | { |
2108 | undo_all (); | |
2109 | return 0; | |
2110 | } | |
2111 | ||
2112 | /* If the actions of the earlier insns must be kept | |
2113 | in addition to substituting them into the latest one, | |
2114 | we must make a new PARALLEL for the latest insn | |
2115 | to hold additional the SETs. */ | |
2116 | ||
2117 | if (added_sets_1 || added_sets_2) | |
2118 | { | |
2119 | combine_extras++; | |
2120 | ||
2121 | if (GET_CODE (newpat) == PARALLEL) | |
2122 | { | |
2123 | rtvec old = XVEC (newpat, 0); | |
2124 | total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; | |
38a448ca | 2125 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
d38a30c9 KG |
2126 | memcpy (XVEC (newpat, 0)->elem, &old->elem[0], |
2127 | sizeof (old->elem[0]) * old->num_elem); | |
230d793d RS |
2128 | } |
2129 | else | |
2130 | { | |
2131 | rtx old = newpat; | |
2132 | total_sets = 1 + added_sets_1 + added_sets_2; | |
38a448ca | 2133 | newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets)); |
230d793d RS |
2134 | XVECEXP (newpat, 0, 0) = old; |
2135 | } | |
2136 | ||
cf0d9408 KH |
2137 | if (added_sets_1) |
2138 | XVECEXP (newpat, 0, --total_sets) | |
2139 | = (GET_CODE (PATTERN (i1)) == PARALLEL | |
2140 | ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1)); | |
2141 | ||
2142 | if (added_sets_2) | |
2143 | { | |
2144 | /* If there is no I1, use I2's body as is. We used to also not do | |
2145 | the subst call below if I2 was substituted into I3, | |
2146 | but that could lose a simplification. */ | |
2147 | if (i1 == 0) | |
2148 | XVECEXP (newpat, 0, --total_sets) = i2pat; | |
2149 | else | |
2150 | /* See comment where i2pat is assigned. */ | |
2151 | XVECEXP (newpat, 0, --total_sets) | |
2152 | = subst (i2pat, i1dest, i1src, 0, 0); | |
2153 | } | |
230d793d RS |
2154 | } |
2155 | ||
2156 | /* We come here when we are replacing a destination in I2 with the | |
2157 | destination of I3. */ | |
2158 | validate_replacement: | |
2159 | ||
6e25d159 RK |
2160 | /* Note which hard regs this insn has as inputs. */ |
2161 | mark_used_regs_combine (newpat); | |
2162 | ||
9b12dc4f R |
2163 | /* If recog_for_combine fails, it strips existing clobbers. If we'll |
2164 | consider splitting this pattern, we might need these clobbers. */ | |
2165 | if (i1 && GET_CODE (newpat) == PARALLEL | |
2166 | && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER) | |
2167 | { | |
2168 | int len = XVECLEN (newpat, 0); | |
2169 | ||
2170 | newpat_vec_with_clobbers = rtvec_alloc (len); | |
2171 | for (i = 0; i < len; i++) | |
2172 | RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i); | |
2173 | } | |
2174 | ||
230d793d | 2175 | /* Is the result of combination a valid instruction? */ |
8e2f6e35 | 2176 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2177 | |
2178 | /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
8051c2eb AM |
2179 | the second SET's destination is a register that is unused and isn't |
2180 | marked as an instruction that might trap in an EH region. In that case, | |
230d793d RS |
2181 | we just need the first SET. This can occur when simplifying a divmod |
2182 | insn. We *must* test for this case here because the code below that | |
2183 | splits two independent SETs doesn't handle this case correctly when it | |
da6fdad3 | 2184 | updates the register status. |
230d793d | 2185 | |
da6fdad3 AM |
2186 | It's pointless doing this if we originally had two sets, one from |
2187 | i3, and one from i2. Combining then splitting the parallel results | |
2188 | in the original i2 again plus an invalid insn (which we delete). | |
2189 | The net effect is only to move instructions around, which makes | |
2190 | debug info less accurate. | |
2191 | ||
2192 | Also check the case where the first SET's destination is unused. | |
2193 | That would not cause incorrect code, but does cause an unneeded | |
2194 | insn to remain. */ | |
2195 | ||
2196 | if (insn_code_number < 0 | |
2197 | && !(added_sets_2 && i1 == 0) | |
2198 | && GET_CODE (newpat) == PARALLEL | |
230d793d RS |
2199 | && XVECLEN (newpat, 0) == 2 |
2200 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2201 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
230d793d RS |
2202 | && asm_noperands (newpat) < 0) |
2203 | { | |
5c881655 KH |
2204 | rtx set0 = XVECEXP (newpat, 0, 0); |
2205 | rtx set1 = XVECEXP (newpat, 0, 1); | |
8051c2eb AM |
2206 | rtx note; |
2207 | ||
f8cfc6aa | 2208 | if (((REG_P (SET_DEST (set1)) |
8051c2eb AM |
2209 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set1))) |
2210 | || (GET_CODE (SET_DEST (set1)) == SUBREG | |
2211 | && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1))))) | |
2212 | && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2213 | || INTVAL (XEXP (note, 0)) <= 0) | |
2214 | && ! side_effects_p (SET_SRC (set1))) | |
2215 | { | |
2216 | newpat = set0; | |
2217 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2218 | } | |
2219 | ||
f8cfc6aa | 2220 | else if (((REG_P (SET_DEST (set0)) |
8051c2eb AM |
2221 | && find_reg_note (i3, REG_UNUSED, SET_DEST (set0))) |
2222 | || (GET_CODE (SET_DEST (set0)) == SUBREG | |
2223 | && find_reg_note (i3, REG_UNUSED, | |
2224 | SUBREG_REG (SET_DEST (set0))))) | |
2225 | && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX)) | |
2226 | || INTVAL (XEXP (note, 0)) <= 0) | |
2227 | && ! side_effects_p (SET_SRC (set0))) | |
2228 | { | |
2229 | newpat = set1; | |
2230 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
2231 | ||
2232 | if (insn_code_number >= 0) | |
2233 | { | |
2234 | /* If we will be able to accept this, we have made a | |
2235 | change to the destination of I3. This requires us to | |
2236 | do a few adjustments. */ | |
2237 | ||
2238 | PATTERN (i3) = newpat; | |
2239 | adjust_for_new_dest (i3); | |
2240 | } | |
2241 | } | |
230d793d RS |
2242 | } |
2243 | ||
2244 | /* If we were combining three insns and the result is a simple SET | |
2245 | with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
663522cb | 2246 | insns. There are two ways to do this. It can be split using a |
916f14f1 RK |
2247 | machine-specific method (like when you have an addition of a large |
2248 | constant) or by combine in the function find_split_point. */ | |
2249 | ||
230d793d RS |
2250 | if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET |
2251 | && asm_noperands (newpat) < 0) | |
2252 | { | |
916f14f1 | 2253 | rtx m_split, *split; |
42495ca0 | 2254 | rtx ni2dest = i2dest; |
916f14f1 RK |
2255 | |
2256 | /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
42495ca0 RK |
2257 | use I2DEST as a scratch register will help. In the latter case, |
2258 | convert I2DEST to the mode of the source of NEWPAT if we can. */ | |
916f14f1 RK |
2259 | |
2260 | m_split = split_insns (newpat, i3); | |
a70c61d9 JW |
2261 | |
2262 | /* We can only use I2DEST as a scratch reg if it doesn't overlap any | |
2263 | inputs of NEWPAT. */ | |
2264 | ||
2265 | /* ??? If I2DEST is not safe, and I1DEST exists, then it would be | |
2266 | possible to try that as a scratch reg. This would require adding | |
2267 | more code to make it work though. */ | |
2268 | ||
2269 | if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat)) | |
42495ca0 RK |
2270 | { |
2271 | /* If I2DEST is a hard register or the only use of a pseudo, | |
2272 | we can change its mode. */ | |
2273 | if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest) | |
02f4ada4 | 2274 | && GET_MODE (SET_DEST (newpat)) != VOIDmode |
f8cfc6aa | 2275 | && REG_P (i2dest) |
42495ca0 | 2276 | && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER |
b1f21e0a | 2277 | || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 |
42495ca0 | 2278 | && ! REG_USERVAR_P (i2dest)))) |
38a448ca | 2279 | ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)), |
c5c76735 JL |
2280 | REGNO (i2dest)); |
2281 | ||
2282 | m_split = split_insns (gen_rtx_PARALLEL | |
2283 | (VOIDmode, | |
2284 | gen_rtvec (2, newpat, | |
2285 | gen_rtx_CLOBBER (VOIDmode, | |
2286 | ni2dest))), | |
2287 | i3); | |
5dd3e650 R |
2288 | /* If the split with the mode-changed register didn't work, try |
2289 | the original register. */ | |
2290 | if (! m_split && ni2dest != i2dest) | |
c7ca5912 RK |
2291 | { |
2292 | ni2dest = i2dest; | |
2293 | m_split = split_insns (gen_rtx_PARALLEL | |
2294 | (VOIDmode, | |
2295 | gen_rtvec (2, newpat, | |
2296 | gen_rtx_CLOBBER (VOIDmode, | |
2297 | i2dest))), | |
2298 | i3); | |
2299 | } | |
42495ca0 | 2300 | } |
916f14f1 | 2301 | |
9b12dc4f R |
2302 | /* If recog_for_combine has discarded clobbers, try to use them |
2303 | again for the split. */ | |
2304 | if (m_split == 0 && newpat_vec_with_clobbers) | |
2305 | m_split | |
2306 | = split_insns (gen_rtx_PARALLEL (VOIDmode, | |
2307 | newpat_vec_with_clobbers), i3); | |
2308 | ||
2f937369 | 2309 | if (m_split && NEXT_INSN (m_split) == NULL_RTX) |
d340408c | 2310 | { |
2f937369 | 2311 | m_split = PATTERN (m_split); |
d340408c RH |
2312 | insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes); |
2313 | if (insn_code_number >= 0) | |
2314 | newpat = m_split; | |
23190837 | 2315 | } |
2f937369 | 2316 | else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX |
d340408c | 2317 | && (next_real_insn (i2) == i3 |
2f937369 | 2318 | || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2)))) |
916f14f1 | 2319 | { |
1a26b032 | 2320 | rtx i2set, i3set; |
2f937369 DM |
2321 | rtx newi3pat = PATTERN (NEXT_INSN (m_split)); |
2322 | newi2pat = PATTERN (m_split); | |
916f14f1 | 2323 | |
2f937369 DM |
2324 | i3set = single_set (NEXT_INSN (m_split)); |
2325 | i2set = single_set (m_split); | |
1a26b032 | 2326 | |
42495ca0 RK |
2327 | /* In case we changed the mode of I2DEST, replace it in the |
2328 | pseudo-register table here. We can't do it above in case this | |
2329 | code doesn't get executed and we do a split the other way. */ | |
2330 | ||
2331 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2332 | SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest); | |
2333 | ||
8e2f6e35 | 2334 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
1a26b032 RK |
2335 | |
2336 | /* If I2 or I3 has multiple SETs, we won't know how to track | |
9cc96794 RK |
2337 | register status, so don't use these insns. If I2's destination |
2338 | is used between I2 and I3, we also can't use these insns. */ | |
1a26b032 | 2339 | |
9cc96794 RK |
2340 | if (i2_code_number >= 0 && i2set && i3set |
2341 | && (next_real_insn (i2) == i3 | |
2342 | || ! reg_used_between_p (SET_DEST (i2set), i2, i3))) | |
8e2f6e35 BS |
2343 | insn_code_number = recog_for_combine (&newi3pat, i3, |
2344 | &new_i3_notes); | |
d0ab8cd3 RK |
2345 | if (insn_code_number >= 0) |
2346 | newpat = newi3pat; | |
2347 | ||
c767f54b | 2348 | /* It is possible that both insns now set the destination of I3. |
22609cbf | 2349 | If so, we must show an extra use of it. */ |
c767f54b | 2350 | |
393de53f RK |
2351 | if (insn_code_number >= 0) |
2352 | { | |
2353 | rtx new_i3_dest = SET_DEST (i3set); | |
2354 | rtx new_i2_dest = SET_DEST (i2set); | |
2355 | ||
2356 | while (GET_CODE (new_i3_dest) == ZERO_EXTRACT | |
2357 | || GET_CODE (new_i3_dest) == STRICT_LOW_PART | |
2358 | || GET_CODE (new_i3_dest) == SUBREG) | |
2359 | new_i3_dest = XEXP (new_i3_dest, 0); | |
2360 | ||
d4096689 RK |
2361 | while (GET_CODE (new_i2_dest) == ZERO_EXTRACT |
2362 | || GET_CODE (new_i2_dest) == STRICT_LOW_PART | |
2363 | || GET_CODE (new_i2_dest) == SUBREG) | |
2364 | new_i2_dest = XEXP (new_i2_dest, 0); | |
2365 | ||
f8cfc6aa JQ |
2366 | if (REG_P (new_i3_dest) |
2367 | && REG_P (new_i2_dest) | |
393de53f | 2368 | && REGNO (new_i3_dest) == REGNO (new_i2_dest)) |
b1f21e0a | 2369 | REG_N_SETS (REGNO (new_i2_dest))++; |
393de53f | 2370 | } |
916f14f1 | 2371 | } |
230d793d RS |
2372 | |
2373 | /* If we can split it and use I2DEST, go ahead and see if that | |
2374 | helps things be recognized. Verify that none of the registers | |
2375 | are set between I2 and I3. */ | |
d0ab8cd3 | 2376 | if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0 |
230d793d | 2377 | #ifdef HAVE_cc0 |
f8cfc6aa | 2378 | && REG_P (i2dest) |
230d793d RS |
2379 | #endif |
2380 | /* We need I2DEST in the proper mode. If it is a hard register | |
1ad93fbf BS |
2381 | or the only use of a pseudo, we can change its mode. |
2382 | Make sure we don't change a hard register to have a mode that | |
2383 | isn't valid for it, or change the number of registers. */ | |
230d793d RS |
2384 | && (GET_MODE (*split) == GET_MODE (i2dest) |
2385 | || GET_MODE (*split) == VOIDmode | |
1ad93fbf BS |
2386 | || (REGNO (i2dest) < FIRST_PSEUDO_REGISTER |
2387 | && HARD_REGNO_MODE_OK (REGNO (i2dest), GET_MODE (*split)) | |
2388 | && (HARD_REGNO_NREGS (REGNO (i2dest), GET_MODE (i2dest)) | |
2389 | == HARD_REGNO_NREGS (REGNO (i2dest), GET_MODE (*split)))) | |
2390 | || (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER | |
2391 | && REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2 | |
230d793d RS |
2392 | && ! REG_USERVAR_P (i2dest))) |
2393 | && (next_real_insn (i2) == i3 | |
2394 | || ! use_crosses_set_p (*split, INSN_CUID (i2))) | |
2395 | /* We can't overwrite I2DEST if its value is still used by | |
2396 | NEWPAT. */ | |
2397 | && ! reg_referenced_p (i2dest, newpat)) | |
2398 | { | |
2399 | rtx newdest = i2dest; | |
df7d75de RK |
2400 | enum rtx_code split_code = GET_CODE (*split); |
2401 | enum machine_mode split_mode = GET_MODE (*split); | |
230d793d RS |
2402 | |
2403 | /* Get NEWDEST as a register in the proper mode. We have already | |
2404 | validated that we can do this. */ | |
df7d75de | 2405 | if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode) |
230d793d | 2406 | { |
38a448ca | 2407 | newdest = gen_rtx_REG (split_mode, REGNO (i2dest)); |
230d793d RS |
2408 | |
2409 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
2410 | SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); | |
2411 | } | |
2412 | ||
2413 | /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
2414 | an ASHIFT. This can occur if it was inside a PLUS and hence | |
2415 | appeared to be a memory address. This is a kludge. */ | |
df7d75de | 2416 | if (split_code == MULT |
230d793d | 2417 | && GET_CODE (XEXP (*split, 1)) == CONST_INT |
1568d79b | 2418 | && INTVAL (XEXP (*split, 1)) > 0 |
230d793d | 2419 | && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) |
1dc8a823 | 2420 | { |
f1c6ba8b RK |
2421 | SUBST (*split, gen_rtx_ASHIFT (split_mode, |
2422 | XEXP (*split, 0), GEN_INT (i))); | |
1dc8a823 JW |
2423 | /* Update split_code because we may not have a multiply |
2424 | anymore. */ | |
2425 | split_code = GET_CODE (*split); | |
2426 | } | |
230d793d RS |
2427 | |
2428 | #ifdef INSN_SCHEDULING | |
2429 | /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
2430 | be written as a ZERO_EXTEND. */ | |
3c0cb5de | 2431 | if (split_code == SUBREG && MEM_P (SUBREG_REG (*split))) |
25c25947 R |
2432 | { |
2433 | #ifdef LOAD_EXTEND_OP | |
2434 | /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's | |
2435 | what it really is. */ | |
2436 | if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split))) | |
2437 | == SIGN_EXTEND) | |
2438 | SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode, | |
2439 | SUBREG_REG (*split))); | |
2440 | else | |
2441 | #endif | |
2442 | SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode, | |
2443 | SUBREG_REG (*split))); | |
2444 | } | |
230d793d RS |
2445 | #endif |
2446 | ||
f1c6ba8b | 2447 | newi2pat = gen_rtx_SET (VOIDmode, newdest, *split); |
230d793d | 2448 | SUBST (*split, newdest); |
8e2f6e35 | 2449 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
df7d75de | 2450 | |
985f2d8f JJ |
2451 | /* recog_for_combine might have added CLOBBERs to newi2pat. |
2452 | Make sure NEWPAT does not depend on the clobbered regs. */ | |
2453 | if (GET_CODE (newi2pat) == PARALLEL) | |
2454 | for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--) | |
2455 | if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER) | |
2456 | { | |
2457 | rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0); | |
2458 | if (reg_overlap_mentioned_p (reg, newpat)) | |
2459 | { | |
2460 | undo_all (); | |
2461 | return 0; | |
2462 | } | |
2463 | } | |
2464 | ||
df7d75de RK |
2465 | /* If the split point was a MULT and we didn't have one before, |
2466 | don't use one now. */ | |
2467 | if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult)) | |
8e2f6e35 | 2468 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2469 | } |
2470 | } | |
2471 | ||
2472 | /* Check for a case where we loaded from memory in a narrow mode and | |
2473 | then sign extended it, but we need both registers. In that case, | |
2474 | we have a PARALLEL with both loads from the same memory location. | |
2475 | We can split this into a load from memory followed by a register-register | |
2476 | copy. This saves at least one insn, more if register allocation can | |
f0343c74 RK |
2477 | eliminate the copy. |
2478 | ||
a9b2f059 JW |
2479 | We cannot do this if the destination of the first assignment is a |
2480 | condition code register or cc0. We eliminate this case by making sure | |
2481 | the SET_DEST and SET_SRC have the same mode. | |
2482 | ||
f0343c74 RK |
2483 | We cannot do this if the destination of the second assignment is |
2484 | a register that we have already assumed is zero-extended. Similarly | |
2485 | for a SUBREG of such a register. */ | |
230d793d RS |
2486 | |
2487 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2488 | && GET_CODE (newpat) == PARALLEL | |
2489 | && XVECLEN (newpat, 0) == 2 | |
2490 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2491 | && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
a9b2f059 JW |
2492 | && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))) |
2493 | == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0)))) | |
230d793d RS |
2494 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET |
2495 | && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2496 | XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
2497 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2498 | INSN_CUID (i2)) | |
2499 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2500 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
f0343c74 | 2501 | && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)), |
f8cfc6aa | 2502 | (REG_P (temp) |
5eaad481 | 2503 | && reg_stat[REGNO (temp)].nonzero_bits != 0 |
f0343c74 RK |
2504 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD |
2505 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
5eaad481 | 2506 | && (reg_stat[REGNO (temp)].nonzero_bits |
f0343c74 RK |
2507 | != GET_MODE_MASK (word_mode)))) |
2508 | && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG | |
2509 | && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))), | |
f8cfc6aa | 2510 | (REG_P (temp) |
5eaad481 | 2511 | && reg_stat[REGNO (temp)].nonzero_bits != 0 |
f0343c74 RK |
2512 | && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD |
2513 | && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT | |
5eaad481 | 2514 | && (reg_stat[REGNO (temp)].nonzero_bits |
f0343c74 | 2515 | != GET_MODE_MASK (word_mode))))) |
230d793d RS |
2516 | && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), |
2517 | SET_SRC (XVECEXP (newpat, 0, 1))) | |
2518 | && ! find_reg_note (i3, REG_UNUSED, | |
2519 | SET_DEST (XVECEXP (newpat, 0, 0)))) | |
2520 | { | |
472fbdd1 RK |
2521 | rtx ni2dest; |
2522 | ||
230d793d | 2523 | newi2pat = XVECEXP (newpat, 0, 0); |
472fbdd1 | 2524 | ni2dest = SET_DEST (XVECEXP (newpat, 0, 0)); |
230d793d RS |
2525 | newpat = XVECEXP (newpat, 0, 1); |
2526 | SUBST (SET_SRC (newpat), | |
4de249d9 | 2527 | gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest)); |
8e2f6e35 | 2528 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2529 | |
230d793d | 2530 | if (i2_code_number >= 0) |
8e2f6e35 | 2531 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
5089e22e RS |
2532 | |
2533 | if (insn_code_number >= 0) | |
9e42ab3e | 2534 | swap_i2i3 = 1; |
230d793d | 2535 | } |
663522cb | 2536 | |
230d793d RS |
2537 | /* Similarly, check for a case where we have a PARALLEL of two independent |
2538 | SETs but we started with three insns. In this case, we can do the sets | |
2539 | as two separate insns. This case occurs when some SET allows two | |
2540 | other insns to combine, but the destination of that SET is still live. */ | |
2541 | ||
2542 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
2543 | && GET_CODE (newpat) == PARALLEL | |
2544 | && XVECLEN (newpat, 0) == 2 | |
2545 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
2546 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
2547 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
2548 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
2549 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
2550 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
2551 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
2552 | INSN_CUID (i2)) | |
2553 | /* Don't pass sets with (USE (MEM ...)) dests to the following. */ | |
2554 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE | |
2555 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE | |
2556 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
2557 | XVECEXP (newpat, 0, 0)) | |
2558 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
14a774a9 RK |
2559 | XVECEXP (newpat, 0, 1)) |
2560 | && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0))) | |
2561 | && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))) | |
230d793d | 2562 | { |
e9a25f70 JL |
2563 | /* Normally, it doesn't matter which of the two is done first, |
2564 | but it does if one references cc0. In that case, it has to | |
2565 | be first. */ | |
2566 | #ifdef HAVE_cc0 | |
2567 | if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))) | |
2568 | { | |
2569 | newi2pat = XVECEXP (newpat, 0, 0); | |
2570 | newpat = XVECEXP (newpat, 0, 1); | |
2571 | } | |
2572 | else | |
2573 | #endif | |
2574 | { | |
2575 | newi2pat = XVECEXP (newpat, 0, 1); | |
2576 | newpat = XVECEXP (newpat, 0, 0); | |
2577 | } | |
230d793d | 2578 | |
8e2f6e35 | 2579 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); |
a29ca9db | 2580 | |
230d793d | 2581 | if (i2_code_number >= 0) |
8e2f6e35 | 2582 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); |
230d793d RS |
2583 | } |
2584 | ||
2585 | /* If it still isn't recognized, fail and change things back the way they | |
2586 | were. */ | |
2587 | if ((insn_code_number < 0 | |
2588 | /* Is the result a reasonable ASM_OPERANDS? */ | |
2589 | && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
2590 | { | |
2591 | undo_all (); | |
2592 | return 0; | |
2593 | } | |
2594 | ||
2595 | /* If we had to change another insn, make sure it is valid also. */ | |
2596 | if (undobuf.other_insn) | |
2597 | { | |
230d793d RS |
2598 | rtx other_pat = PATTERN (undobuf.other_insn); |
2599 | rtx new_other_notes; | |
2600 | rtx note, next; | |
2601 | ||
6e25d159 RK |
2602 | CLEAR_HARD_REG_SET (newpat_used_regs); |
2603 | ||
8e2f6e35 BS |
2604 | other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, |
2605 | &new_other_notes); | |
230d793d RS |
2606 | |
2607 | if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
2608 | { | |
2609 | undo_all (); | |
2610 | return 0; | |
2611 | } | |
2612 | ||
2613 | PATTERN (undobuf.other_insn) = other_pat; | |
2614 | ||
2615 | /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they | |
2616 | are still valid. Then add any non-duplicate notes added by | |
2617 | recog_for_combine. */ | |
2618 | for (note = REG_NOTES (undobuf.other_insn); note; note = next) | |
2619 | { | |
2620 | next = XEXP (note, 1); | |
2621 | ||
2622 | if (REG_NOTE_KIND (note) == REG_UNUSED | |
2623 | && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) | |
1a26b032 | 2624 | { |
f8cfc6aa | 2625 | if (REG_P (XEXP (note, 0))) |
b1f21e0a | 2626 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
1a26b032 RK |
2627 | |
2628 | remove_note (undobuf.other_insn, note); | |
2629 | } | |
230d793d RS |
2630 | } |
2631 | ||
1a26b032 | 2632 | for (note = new_other_notes; note; note = XEXP (note, 1)) |
f8cfc6aa | 2633 | if (REG_P (XEXP (note, 0))) |
b1f21e0a | 2634 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 2635 | |
230d793d | 2636 | distribute_notes (new_other_notes, undobuf.other_insn, |
72531479 | 2637 | undobuf.other_insn, NULL_RTX); |
230d793d | 2638 | } |
5ef17dd2 | 2639 | #ifdef HAVE_cc0 |
1f52178b | 2640 | /* If I2 is the CC0 setter and I3 is the CC0 user then check whether |
ec5c56db | 2641 | they are adjacent to each other or not. */ |
5ef17dd2 CC |
2642 | { |
2643 | rtx p = prev_nonnote_insn (i3); | |
4b4bf941 | 2644 | if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat |
663522cb | 2645 | && sets_cc0_p (newi2pat)) |
5ef17dd2 | 2646 | { |
663522cb KH |
2647 | undo_all (); |
2648 | return 0; | |
5ef17dd2 | 2649 | } |
663522cb KH |
2650 | } |
2651 | #endif | |
230d793d | 2652 | |
6fd21094 | 2653 | /* Only allow this combination if insn_rtx_costs reports that the |
64b8935d RS |
2654 | replacement instructions are cheaper than the originals. */ |
2655 | if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat)) | |
2656 | { | |
2657 | undo_all (); | |
2658 | return 0; | |
2659 | } | |
2660 | ||
663522cb | 2661 | /* We now know that we can do this combination. Merge the insns and |
230d793d RS |
2662 | update the status of registers and LOG_LINKS. */ |
2663 | ||
9e42ab3e RZ |
2664 | if (swap_i2i3) |
2665 | { | |
2666 | rtx insn; | |
2667 | rtx link; | |
2668 | rtx ni2dest; | |
2669 | ||
2670 | /* I3 now uses what used to be its destination and which is now | |
2671 | I2's destination. This requires us to do a few adjustments. */ | |
2672 | PATTERN (i3) = newpat; | |
2673 | adjust_for_new_dest (i3); | |
2674 | ||
2675 | /* We need a LOG_LINK from I3 to I2. But we used to have one, | |
2676 | so we still will. | |
2677 | ||
2678 | However, some later insn might be using I2's dest and have | |
2679 | a LOG_LINK pointing at I3. We must remove this link. | |
2680 | The simplest way to remove the link is to point it at I1, | |
2681 | which we know will be a NOTE. */ | |
2682 | ||
0b21d1dc UW |
2683 | /* newi2pat is usually a SET here; however, recog_for_combine might |
2684 | have added some clobbers. */ | |
2685 | if (GET_CODE (newi2pat) == PARALLEL) | |
2686 | ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0)); | |
2687 | else | |
2688 | ni2dest = SET_DEST (newi2pat); | |
2689 | ||
9e42ab3e RZ |
2690 | for (insn = NEXT_INSN (i3); |
2691 | insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR | |
2692 | || insn != BB_HEAD (this_basic_block->next_bb)); | |
2693 | insn = NEXT_INSN (insn)) | |
2694 | { | |
2695 | if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn))) | |
2696 | { | |
2697 | for (link = LOG_LINKS (insn); link; | |
2698 | link = XEXP (link, 1)) | |
2699 | if (XEXP (link, 0) == i3) | |
2700 | XEXP (link, 0) = i1; | |
2701 | ||
2702 | break; | |
2703 | } | |
2704 | } | |
2705 | } | |
2706 | ||
230d793d RS |
2707 | { |
2708 | rtx i3notes, i2notes, i1notes = 0; | |
2709 | rtx i3links, i2links, i1links = 0; | |
2710 | rtx midnotes = 0; | |
770ae6cc | 2711 | unsigned int regno; |
230d793d RS |
2712 | |
2713 | /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
2714 | clear them. */ | |
2715 | i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
2716 | i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
2717 | if (i1) | |
2718 | i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
2719 | ||
2720 | /* Ensure that we do not have something that should not be shared but | |
2721 | occurs multiple times in the new insns. Check this by first | |
5089e22e | 2722 | resetting all the `used' flags and then copying anything is shared. */ |
230d793d RS |
2723 | |
2724 | reset_used_flags (i3notes); | |
2725 | reset_used_flags (i2notes); | |
2726 | reset_used_flags (i1notes); | |
2727 | reset_used_flags (newpat); | |
2728 | reset_used_flags (newi2pat); | |
2729 | if (undobuf.other_insn) | |
2730 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2731 | ||
2732 | i3notes = copy_rtx_if_shared (i3notes); | |
2733 | i2notes = copy_rtx_if_shared (i2notes); | |
2734 | i1notes = copy_rtx_if_shared (i1notes); | |
2735 | newpat = copy_rtx_if_shared (newpat); | |
2736 | newi2pat = copy_rtx_if_shared (newi2pat); | |
2737 | if (undobuf.other_insn) | |
2738 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
2739 | ||
2740 | INSN_CODE (i3) = insn_code_number; | |
2741 | PATTERN (i3) = newpat; | |
cddd8b72 | 2742 | |
4b4bf941 | 2743 | if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3)) |
cddd8b72 AO |
2744 | { |
2745 | rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3); | |
2746 | ||
2747 | reset_used_flags (call_usage); | |
2748 | call_usage = copy_rtx (call_usage); | |
2749 | ||
2750 | if (substed_i2) | |
2751 | replace_rtx (call_usage, i2dest, i2src); | |
2752 | ||
2753 | if (substed_i1) | |
2754 | replace_rtx (call_usage, i1dest, i1src); | |
2755 | ||
2756 | CALL_INSN_FUNCTION_USAGE (i3) = call_usage; | |
2757 | } | |
2758 | ||
230d793d RS |
2759 | if (undobuf.other_insn) |
2760 | INSN_CODE (undobuf.other_insn) = other_code_number; | |
2761 | ||
2762 | /* We had one special case above where I2 had more than one set and | |
2763 | we replaced a destination of one of those sets with the destination | |
2764 | of I3. In that case, we have to update LOG_LINKS of insns later | |
176c9e6b JW |
2765 | in this basic block. Note that this (expensive) case is rare. |
2766 | ||
2767 | Also, in this case, we must pretend that all REG_NOTEs for I2 | |
2768 | actually came from I3, so that REG_UNUSED notes from I2 will be | |
2769 | properly handled. */ | |
2770 | ||
c7be4f66 | 2771 | if (i3_subst_into_i2) |
176c9e6b | 2772 | { |
1786009e | 2773 | for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) |
95ac07b0 | 2774 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE |
f8cfc6aa | 2775 | && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) |
1786009e ZW |
2776 | && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest |
2777 | && ! find_reg_note (i2, REG_UNUSED, | |
2778 | SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
2779 | for (temp = NEXT_INSN (i2); | |
f6366fc7 | 2780 | temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
a813c111 | 2781 | || BB_HEAD (this_basic_block) != temp); |
1786009e ZW |
2782 | temp = NEXT_INSN (temp)) |
2783 | if (temp != i3 && INSN_P (temp)) | |
2784 | for (link = LOG_LINKS (temp); link; link = XEXP (link, 1)) | |
2785 | if (XEXP (link, 0) == i2) | |
2786 | XEXP (link, 0) = i3; | |
176c9e6b JW |
2787 | |
2788 | if (i3notes) | |
2789 | { | |
2790 | rtx link = i3notes; | |
2791 | while (XEXP (link, 1)) | |
2792 | link = XEXP (link, 1); | |
2793 | XEXP (link, 1) = i2notes; | |
2794 | } | |
2795 | else | |
2796 | i3notes = i2notes; | |
2797 | i2notes = 0; | |
2798 | } | |
230d793d RS |
2799 | |
2800 | LOG_LINKS (i3) = 0; | |
2801 | REG_NOTES (i3) = 0; | |
2802 | LOG_LINKS (i2) = 0; | |
2803 | REG_NOTES (i2) = 0; | |
2804 | ||
2805 | if (newi2pat) | |
2806 | { | |
2807 | INSN_CODE (i2) = i2_code_number; | |
2808 | PATTERN (i2) = newi2pat; | |
2809 | } | |
2810 | else | |
6773e15f | 2811 | SET_INSN_DELETED (i2); |
230d793d RS |
2812 | |
2813 | if (i1) | |
2814 | { | |
2815 | LOG_LINKS (i1) = 0; | |
2816 | REG_NOTES (i1) = 0; | |
6773e15f | 2817 | SET_INSN_DELETED (i1); |
230d793d RS |
2818 | } |
2819 | ||
2820 | /* Get death notes for everything that is now used in either I3 or | |
663522cb | 2821 | I2 and used to die in a previous insn. If we built two new |
6eb12cef RK |
2822 | patterns, move from I1 to I2 then I2 to I3 so that we get the |
2823 | proper movement on registers that I2 modifies. */ | |
230d793d | 2824 | |
230d793d | 2825 | if (newi2pat) |
6eb12cef RK |
2826 | { |
2827 | move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes); | |
2828 | move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes); | |
2829 | } | |
2830 | else | |
2831 | move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2), | |
2832 | i3, &midnotes); | |
230d793d RS |
2833 | |
2834 | /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
2835 | if (i3notes) | |
72531479 | 2836 | distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX); |
230d793d | 2837 | if (i2notes) |
72531479 | 2838 | distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX); |
230d793d | 2839 | if (i1notes) |
72531479 | 2840 | distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX); |
230d793d | 2841 | if (midnotes) |
72531479 | 2842 | distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX); |
230d793d RS |
2843 | |
2844 | /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
2845 | know these are REG_UNUSED and want them to go to the desired insn, | |
663522cb | 2846 | so we always pass it as i3. We have not counted the notes in |
1a26b032 RK |
2847 | reg_n_deaths yet, so we need to do so now. */ |
2848 | ||
230d793d | 2849 | if (newi2pat && new_i2_notes) |
1a26b032 RK |
2850 | { |
2851 | for (temp = new_i2_notes; temp; temp = XEXP (temp, 1)) | |
f8cfc6aa | 2852 | if (REG_P (XEXP (temp, 0))) |
b1f21e0a | 2853 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2854 | |
72531479 | 2855 | distribute_notes (new_i2_notes, i2, i2, NULL_RTX); |
1a26b032 RK |
2856 | } |
2857 | ||
230d793d | 2858 | if (new_i3_notes) |
1a26b032 RK |
2859 | { |
2860 | for (temp = new_i3_notes; temp; temp = XEXP (temp, 1)) | |
f8cfc6aa | 2861 | if (REG_P (XEXP (temp, 0))) |
b1f21e0a | 2862 | REG_N_DEATHS (REGNO (XEXP (temp, 0)))++; |
663522cb | 2863 | |
72531479 | 2864 | distribute_notes (new_i3_notes, i3, i3, NULL_RTX); |
1a26b032 | 2865 | } |
230d793d RS |
2866 | |
2867 | /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
e9a25f70 JL |
2868 | put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets |
2869 | I3DEST, the death must be somewhere before I2, not I3. If we passed I3 | |
2870 | in that case, it might delete I2. Similarly for I2 and I1. | |
1a26b032 RK |
2871 | Show an additional death due to the REG_DEAD note we make here. If |
2872 | we discard it in distribute_notes, we will decrement it again. */ | |
d0ab8cd3 | 2873 | |
230d793d | 2874 | if (i3dest_killed) |
1a26b032 | 2875 | { |
f8cfc6aa | 2876 | if (REG_P (i3dest_killed)) |
b1f21e0a | 2877 | REG_N_DEATHS (REGNO (i3dest_killed))++; |
1a26b032 | 2878 | |
e9a25f70 | 2879 | if (newi2pat && reg_set_p (i3dest_killed, newi2pat)) |
38a448ca RH |
2880 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
2881 | NULL_RTX), | |
72531479 | 2882 | NULL_RTX, i2, NULL_RTX); |
e9a25f70 | 2883 | else |
38a448ca RH |
2884 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed, |
2885 | NULL_RTX), | |
72531479 | 2886 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX); |
1a26b032 | 2887 | } |
58c8c593 | 2888 | |
230d793d | 2889 | if (i2dest_in_i2src) |
58c8c593 | 2890 | { |
f8cfc6aa | 2891 | if (REG_P (i2dest)) |
b1f21e0a | 2892 | REG_N_DEATHS (REGNO (i2dest))++; |
1a26b032 | 2893 | |
58c8c593 | 2894 | if (newi2pat && reg_set_p (i2dest, newi2pat)) |
38a448ca | 2895 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
72531479 | 2896 | NULL_RTX, i2, NULL_RTX); |
58c8c593 | 2897 | else |
38a448ca | 2898 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX), |
72531479 | 2899 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX); |
58c8c593 RK |
2900 | } |
2901 | ||
230d793d | 2902 | if (i1dest_in_i1src) |
58c8c593 | 2903 | { |
f8cfc6aa | 2904 | if (REG_P (i1dest)) |
b1f21e0a | 2905 | REG_N_DEATHS (REGNO (i1dest))++; |
1a26b032 | 2906 | |
58c8c593 | 2907 | if (newi2pat && reg_set_p (i1dest, newi2pat)) |
38a448ca | 2908 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
72531479 | 2909 | NULL_RTX, i2, NULL_RTX); |
58c8c593 | 2910 | else |
38a448ca | 2911 | distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX), |
72531479 | 2912 | NULL_RTX, i3, newi2pat ? i2 : NULL_RTX); |
58c8c593 | 2913 | } |
230d793d RS |
2914 | |
2915 | distribute_links (i3links); | |
2916 | distribute_links (i2links); | |
2917 | distribute_links (i1links); | |
2918 | ||
f8cfc6aa | 2919 | if (REG_P (i2dest)) |
230d793d | 2920 | { |
d0ab8cd3 RK |
2921 | rtx link; |
2922 | rtx i2_insn = 0, i2_val = 0, set; | |
2923 | ||
2924 | /* The insn that used to set this register doesn't exist, and | |
2925 | this life of the register may not exist either. See if one of | |
663522cb | 2926 | I3's links points to an insn that sets I2DEST. If it does, |
d0ab8cd3 RK |
2927 | that is now the last known value for I2DEST. If we don't update |
2928 | this and I2 set the register to a value that depended on its old | |
230d793d RS |
2929 | contents, we will get confused. If this insn is used, thing |
2930 | will be set correctly in combine_instructions. */ | |
d0ab8cd3 RK |
2931 | |
2932 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
2933 | if ((set = single_set (XEXP (link, 0))) != 0 | |
2934 | && rtx_equal_p (i2dest, SET_DEST (set))) | |
2935 | i2_insn = XEXP (link, 0), i2_val = SET_SRC (set); | |
2936 | ||
2937 | record_value_for_reg (i2dest, i2_insn, i2_val); | |
230d793d RS |
2938 | |
2939 | /* If the reg formerly set in I2 died only once and that was in I3, | |
2940 | zero its use count so it won't make `reload' do any work. */ | |
538fe8cd ILT |
2941 | if (! added_sets_2 |
2942 | && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat)) | |
2943 | && ! i2dest_in_i2src) | |
230d793d RS |
2944 | { |
2945 | regno = REGNO (i2dest); | |
b1f21e0a | 2946 | REG_N_SETS (regno)--; |
230d793d RS |
2947 | } |
2948 | } | |
2949 | ||
f8cfc6aa | 2950 | if (i1 && REG_P (i1dest)) |
230d793d | 2951 | { |
d0ab8cd3 RK |
2952 | rtx link; |
2953 | rtx i1_insn = 0, i1_val = 0, set; | |
2954 | ||
2955 | for (link = LOG_LINKS (i3); link; link = XEXP (link, 1)) | |
2956 | if ((set = single_set (XEXP (link, 0))) != 0 | |
2957 | && rtx_equal_p (i1dest, SET_DEST (set))) | |
2958 | i1_insn = XEXP (link, 0), i1_val = SET_SRC (set); | |
2959 | ||
2960 | record_value_for_reg (i1dest, i1_insn, i1_val); | |
2961 | ||
230d793d | 2962 | regno = REGNO (i1dest); |
5af91171 | 2963 | if (! added_sets_1 && ! i1dest_in_i1src) |
770ae6cc | 2964 | REG_N_SETS (regno)--; |
230d793d RS |
2965 | } |
2966 | ||
5eaad481 PB |
2967 | /* Update reg_stat[].nonzero_bits et al for any changes that may have |
2968 | been made to this insn. The order of | |
2969 | set_nonzero_bits_and_sign_copies() is important. Because newi2pat | |
2970 | can affect nonzero_bits of newpat */ | |
22609cbf | 2971 | if (newi2pat) |
84832317 | 2972 | note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL); |
5fb7c247 | 2973 | note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL); |
22609cbf | 2974 | |
44a76fc8 AG |
2975 | /* Set new_direct_jump_p if a new return or simple jump instruction |
2976 | has been created. | |
2977 | ||
663522cb | 2978 | If I3 is now an unconditional jump, ensure that it has a |
230d793d | 2979 | BARRIER following it since it may have initially been a |
381ee8af | 2980 | conditional jump. It may also be the last nonnote insn. */ |
663522cb | 2981 | |
f40f4c8e | 2982 | if (returnjump_p (i3) || any_uncondjump_p (i3)) |
44a76fc8 AG |
2983 | { |
2984 | *new_direct_jump_p = 1; | |
9143c6b7 | 2985 | mark_jump_label (PATTERN (i3), i3, 0); |
230d793d | 2986 | |
44a76fc8 | 2987 | if ((temp = next_nonnote_insn (i3)) == NULL_RTX |
4b4bf941 | 2988 | || !BARRIER_P (temp)) |
44a76fc8 AG |
2989 | emit_barrier_after (i3); |
2990 | } | |
f40f4c8e RS |
2991 | |
2992 | if (undobuf.other_insn != NULL_RTX | |
2993 | && (returnjump_p (undobuf.other_insn) | |
2994 | || any_uncondjump_p (undobuf.other_insn))) | |
2995 | { | |
2996 | *new_direct_jump_p = 1; | |
2997 | ||
2998 | if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX | |
4b4bf941 | 2999 | || !BARRIER_P (temp)) |
f40f4c8e RS |
3000 | emit_barrier_after (undobuf.other_insn); |
3001 | } | |
73a39fc4 | 3002 | |
592a6d1d JH |
3003 | /* An NOOP jump does not need barrier, but it does need cleaning up |
3004 | of CFG. */ | |
3005 | if (GET_CODE (newpat) == SET | |
3006 | && SET_SRC (newpat) == pc_rtx | |
3007 | && SET_DEST (newpat) == pc_rtx) | |
3008 | *new_direct_jump_p = 1; | |
230d793d RS |
3009 | } |
3010 | ||
3011 | combine_successes++; | |
e7749837 | 3012 | undo_commit (); |
230d793d | 3013 | |
abe6e52f RK |
3014 | if (added_links_insn |
3015 | && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2)) | |
3016 | && INSN_CUID (added_links_insn) < INSN_CUID (i3)) | |
3017 | return added_links_insn; | |
3018 | else | |
3019 | return newi2pat ? i2 : i3; | |
230d793d RS |
3020 | } |
3021 | \f | |
3022 | /* Undo all the modifications recorded in undobuf. */ | |
3023 | ||
3024 | static void | |
79a490a9 | 3025 | undo_all (void) |
230d793d | 3026 | { |
241cea85 RK |
3027 | struct undo *undo, *next; |
3028 | ||
3029 | for (undo = undobuf.undos; undo; undo = next) | |
7c046e4e | 3030 | { |
241cea85 RK |
3031 | next = undo->next; |
3032 | if (undo->is_int) | |
3033 | *undo->where.i = undo->old_contents.i; | |
7c046e4e | 3034 | else |
241cea85 RK |
3035 | *undo->where.r = undo->old_contents.r; |
3036 | ||
3037 | undo->next = undobuf.frees; | |
3038 | undobuf.frees = undo; | |
7c046e4e | 3039 | } |
230d793d | 3040 | |
f1c6ba8b | 3041 | undobuf.undos = 0; |
230d793d | 3042 | } |
e7749837 RH |
3043 | |
3044 | /* We've committed to accepting the changes we made. Move all | |
3045 | of the undos to the free list. */ | |
3046 | ||
3047 | static void | |
79a490a9 | 3048 | undo_commit (void) |
e7749837 RH |
3049 | { |
3050 | struct undo *undo, *next; | |
3051 | ||
3052 | for (undo = undobuf.undos; undo; undo = next) | |
3053 | { | |
3054 | next = undo->next; | |
3055 | undo->next = undobuf.frees; | |
3056 | undobuf.frees = undo; | |
3057 | } | |
f1c6ba8b | 3058 | undobuf.undos = 0; |
e7749837 RH |
3059 | } |
3060 | ||
230d793d RS |
3061 | \f |
3062 | /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
d0ab8cd3 RK |
3063 | where we have an arithmetic expression and return that point. LOC will |
3064 | be inside INSN. | |
230d793d RS |
3065 | |
3066 | try_combine will call this function to see if an insn can be split into | |
3067 | two insns. */ | |
3068 | ||
3069 | static rtx * | |
79a490a9 | 3070 | find_split_point (rtx *loc, rtx insn) |
230d793d RS |
3071 | { |
3072 | rtx x = *loc; | |
3073 | enum rtx_code code = GET_CODE (x); | |
3074 | rtx *split; | |
770ae6cc RK |
3075 | unsigned HOST_WIDE_INT len = 0; |
3076 | HOST_WIDE_INT pos = 0; | |
3077 | int unsignedp = 0; | |
6a651371 | 3078 | rtx inner = NULL_RTX; |
230d793d RS |
3079 | |
3080 | /* First special-case some codes. */ | |
3081 | switch (code) | |
3082 | { | |
3083 | case SUBREG: | |
3084 | #ifdef INSN_SCHEDULING | |
3085 | /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
3086 | point. */ | |
3c0cb5de | 3087 | if (MEM_P (SUBREG_REG (x))) |
230d793d RS |
3088 | return loc; |
3089 | #endif | |
d0ab8cd3 | 3090 | return find_split_point (&SUBREG_REG (x), insn); |
230d793d | 3091 | |
230d793d | 3092 | case MEM: |
916f14f1 | 3093 | #ifdef HAVE_lo_sum |
230d793d RS |
3094 | /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it |
3095 | using LO_SUM and HIGH. */ | |
3096 | if (GET_CODE (XEXP (x, 0)) == CONST | |
3097 | || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
3098 | { | |
3099 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
3100 | gen_rtx_LO_SUM (Pmode, |
3101 | gen_rtx_HIGH (Pmode, XEXP (x, 0)), | |
3102 | XEXP (x, 0))); | |
230d793d RS |
3103 | return &XEXP (XEXP (x, 0), 0); |
3104 | } | |
230d793d RS |
3105 | #endif |
3106 | ||
916f14f1 RK |
3107 | /* If we have a PLUS whose second operand is a constant and the |
3108 | address is not valid, perhaps will can split it up using | |
3109 | the machine-specific way to split large constants. We use | |
ddd5a7c1 | 3110 | the first pseudo-reg (one of the virtual regs) as a placeholder; |
916f14f1 RK |
3111 | it will not remain in the result. */ |
3112 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
3113 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3114 | && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
3115 | { | |
3116 | rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
38a448ca | 3117 | rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)), |
916f14f1 RK |
3118 | subst_insn); |
3119 | ||
3120 | /* This should have produced two insns, each of which sets our | |
3121 | placeholder. If the source of the second is a valid address, | |
3122 | we can make put both sources together and make a split point | |
3123 | in the middle. */ | |
3124 | ||
2f937369 DM |
3125 | if (seq |
3126 | && NEXT_INSN (seq) != NULL_RTX | |
3127 | && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX | |
4b4bf941 | 3128 | && NONJUMP_INSN_P (seq) |
2f937369 DM |
3129 | && GET_CODE (PATTERN (seq)) == SET |
3130 | && SET_DEST (PATTERN (seq)) == reg | |
916f14f1 | 3131 | && ! reg_mentioned_p (reg, |
2f937369 | 3132 | SET_SRC (PATTERN (seq))) |
4b4bf941 | 3133 | && NONJUMP_INSN_P (NEXT_INSN (seq)) |
2f937369 DM |
3134 | && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET |
3135 | && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg | |
916f14f1 | 3136 | && memory_address_p (GET_MODE (x), |
2f937369 | 3137 | SET_SRC (PATTERN (NEXT_INSN (seq))))) |
916f14f1 | 3138 | { |
2f937369 DM |
3139 | rtx src1 = SET_SRC (PATTERN (seq)); |
3140 | rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq))); | |
916f14f1 RK |
3141 | |
3142 | /* Replace the placeholder in SRC2 with SRC1. If we can | |
3143 | find where in SRC2 it was placed, that can become our | |
3144 | split point and we can replace this address with SRC2. | |
3145 | Just try two obvious places. */ | |
3146 | ||
3147 | src2 = replace_rtx (src2, reg, src1); | |
3148 | split = 0; | |
3149 | if (XEXP (src2, 0) == src1) | |
3150 | split = &XEXP (src2, 0); | |
3151 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
3152 | && XEXP (XEXP (src2, 0), 0) == src1) | |
3153 | split = &XEXP (XEXP (src2, 0), 0); | |
3154 | ||
3155 | if (split) | |
3156 | { | |
3157 | SUBST (XEXP (x, 0), src2); | |
3158 | return split; | |
3159 | } | |
3160 | } | |
663522cb | 3161 | |
1a26b032 RK |
3162 | /* If that didn't work, perhaps the first operand is complex and |
3163 | needs to be computed separately, so make a split point there. | |
3164 | This will occur on machines that just support REG + CONST | |
3165 | and have a constant moved through some previous computation. */ | |
3166 | ||
ec8e098d | 3167 | else if (!OBJECT_P (XEXP (XEXP (x, 0), 0)) |
1a26b032 | 3168 | && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG |
ec8e098d | 3169 | && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0))))) |
1a26b032 | 3170 | return &XEXP (XEXP (x, 0), 0); |
916f14f1 RK |
3171 | } |
3172 | break; | |
3173 | ||
230d793d RS |
3174 | case SET: |
3175 | #ifdef HAVE_cc0 | |
3176 | /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
3177 | ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
3178 | we need to put the operand into a register. So split at that | |
3179 | point. */ | |
3180 | ||
3181 | if (SET_DEST (x) == cc0_rtx | |
3182 | && GET_CODE (SET_SRC (x)) != COMPARE | |
3183 | && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
ec8e098d | 3184 | && !OBJECT_P (SET_SRC (x)) |
230d793d | 3185 | && ! (GET_CODE (SET_SRC (x)) == SUBREG |
ec8e098d | 3186 | && OBJECT_P (SUBREG_REG (SET_SRC (x))))) |
230d793d RS |
3187 | return &SET_SRC (x); |
3188 | #endif | |
3189 | ||
3190 | /* See if we can split SET_SRC as it stands. */ | |
d0ab8cd3 | 3191 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3192 | if (split && split != &SET_SRC (x)) |
3193 | return split; | |
3194 | ||
041d7180 JL |
3195 | /* See if we can split SET_DEST as it stands. */ |
3196 | split = find_split_point (&SET_DEST (x), insn); | |
3197 | if (split && split != &SET_DEST (x)) | |
3198 | return split; | |
3199 | ||
230d793d RS |
3200 | /* See if this is a bitfield assignment with everything constant. If |
3201 | so, this is an IOR of an AND, so split it into that. */ | |
3202 | if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
3203 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) | |
5f4f0e22 | 3204 | <= HOST_BITS_PER_WIDE_INT) |
230d793d RS |
3205 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT |
3206 | && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT | |
3207 | && GET_CODE (SET_SRC (x)) == CONST_INT | |
3208 | && ((INTVAL (XEXP (SET_DEST (x), 1)) | |
cf0d9408 | 3209 | + INTVAL (XEXP (SET_DEST (x), 2))) |
230d793d RS |
3210 | <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) |
3211 | && ! side_effects_p (XEXP (SET_DEST (x), 0))) | |
3212 | { | |
770ae6cc RK |
3213 | HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2)); |
3214 | unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1)); | |
3215 | unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)); | |
230d793d RS |
3216 | rtx dest = XEXP (SET_DEST (x), 0); |
3217 | enum machine_mode mode = GET_MODE (dest); | |
5f4f0e22 | 3218 | unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1; |
230d793d | 3219 | |
f76b9db2 ILT |
3220 | if (BITS_BIG_ENDIAN) |
3221 | pos = GET_MODE_BITSIZE (mode) - len - pos; | |
230d793d | 3222 | |
770ae6cc | 3223 | if (src == mask) |
230d793d | 3224 | SUBST (SET_SRC (x), |
bcb34aa3 | 3225 | simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos))); |
230d793d | 3226 | else |
bcb34aa3 PB |
3227 | { |
3228 | rtx negmask = gen_int_mode (~(mask << pos), mode); | |
3229 | SUBST (SET_SRC (x), | |
3230 | simplify_gen_binary (IOR, mode, | |
3231 | simplify_gen_binary (AND, mode, | |
3232 | dest, negmask), | |
3233 | GEN_INT (src << pos))); | |
3234 | } | |
230d793d RS |
3235 | |
3236 | SUBST (SET_DEST (x), dest); | |
3237 | ||
d0ab8cd3 | 3238 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3239 | if (split && split != &SET_SRC (x)) |
3240 | return split; | |
3241 | } | |
3242 | ||
3243 | /* Otherwise, see if this is an operation that we can split into two. | |
3244 | If so, try to split that. */ | |
3245 | code = GET_CODE (SET_SRC (x)); | |
3246 | ||
3247 | switch (code) | |
3248 | { | |
d0ab8cd3 RK |
3249 | case AND: |
3250 | /* If we are AND'ing with a large constant that is only a single | |
3251 | bit and the result is only being used in a context where we | |
da7d8304 | 3252 | need to know if it is zero or nonzero, replace it with a bit |
d0ab8cd3 RK |
3253 | extraction. This will avoid the large constant, which might |
3254 | have taken more than one insn to make. If the constant were | |
3255 | not a valid argument to the AND but took only one insn to make, | |
3256 | this is no worse, but if it took more than one insn, it will | |
3257 | be better. */ | |
3258 | ||
3259 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
f8cfc6aa | 3260 | && REG_P (XEXP (SET_SRC (x), 0)) |
d0ab8cd3 | 3261 | && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7 |
f8cfc6aa | 3262 | && REG_P (SET_DEST (x)) |
cf0d9408 | 3263 | && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0 |
d0ab8cd3 RK |
3264 | && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE) |
3265 | && XEXP (*split, 0) == SET_DEST (x) | |
3266 | && XEXP (*split, 1) == const0_rtx) | |
3267 | { | |
76184def DE |
3268 | rtx extraction = make_extraction (GET_MODE (SET_DEST (x)), |
3269 | XEXP (SET_SRC (x), 0), | |
3270 | pos, NULL_RTX, 1, 1, 0, 0); | |
3271 | if (extraction != 0) | |
3272 | { | |
3273 | SUBST (SET_SRC (x), extraction); | |
3274 | return find_split_point (loc, insn); | |
3275 | } | |
d0ab8cd3 RK |
3276 | } |
3277 | break; | |
3278 | ||
1a6ec070 | 3279 | case NE: |
938d968e | 3280 | /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X |
ec5c56db | 3281 | is known to be on, this can be converted into a NEG of a shift. */ |
1a6ec070 RK |
3282 | if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx |
3283 | && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0)) | |
4eb2cb10 | 3284 | && 1 <= (pos = exact_log2 |
1a6ec070 RK |
3285 | (nonzero_bits (XEXP (SET_SRC (x), 0), |
3286 | GET_MODE (XEXP (SET_SRC (x), 0)))))) | |
3287 | { | |
3288 | enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0)); | |
3289 | ||
3290 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3291 | gen_rtx_NEG (mode, |
3292 | gen_rtx_LSHIFTRT (mode, | |
3293 | XEXP (SET_SRC (x), 0), | |
3294 | GEN_INT (pos)))); | |
1a6ec070 RK |
3295 | |
3296 | split = find_split_point (&SET_SRC (x), insn); | |
3297 | if (split && split != &SET_SRC (x)) | |
3298 | return split; | |
3299 | } | |
3300 | break; | |
3301 | ||
230d793d RS |
3302 | case SIGN_EXTEND: |
3303 | inner = XEXP (SET_SRC (x), 0); | |
101c1a3d JL |
3304 | |
3305 | /* We can't optimize if either mode is a partial integer | |
3306 | mode as we don't know how many bits are significant | |
3307 | in those modes. */ | |
3308 | if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT | |
3309 | || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT) | |
3310 | break; | |
3311 | ||
230d793d RS |
3312 | pos = 0; |
3313 | len = GET_MODE_BITSIZE (GET_MODE (inner)); | |
3314 | unsignedp = 0; | |
3315 | break; | |
3316 | ||
3317 | case SIGN_EXTRACT: | |
3318 | case ZERO_EXTRACT: | |
3319 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
3320 | && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) | |
3321 | { | |
3322 | inner = XEXP (SET_SRC (x), 0); | |
3323 | len = INTVAL (XEXP (SET_SRC (x), 1)); | |
3324 | pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
3325 | ||
f76b9db2 ILT |
3326 | if (BITS_BIG_ENDIAN) |
3327 | pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; | |
230d793d RS |
3328 | unsignedp = (code == ZERO_EXTRACT); |
3329 | } | |
3330 | break; | |
e9a25f70 JL |
3331 | |
3332 | default: | |
3333 | break; | |
230d793d RS |
3334 | } |
3335 | ||
3336 | if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) | |
3337 | { | |
3338 | enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
3339 | ||
d0ab8cd3 RK |
3340 | /* For unsigned, we have a choice of a shift followed by an |
3341 | AND or two shifts. Use two shifts for field sizes where the | |
3342 | constant might be too large. We assume here that we can | |
3343 | always at least get 8-bit constants in an AND insn, which is | |
3344 | true for every current RISC. */ | |
3345 | ||
3346 | if (unsignedp && len <= 8) | |
230d793d RS |
3347 | { |
3348 | SUBST (SET_SRC (x), | |
f1c6ba8b RK |
3349 | gen_rtx_AND (mode, |
3350 | gen_rtx_LSHIFTRT | |
4de249d9 | 3351 | (mode, gen_lowpart (mode, inner), |
f1c6ba8b RK |
3352 | GEN_INT (pos)), |
3353 | GEN_INT (((HOST_WIDE_INT) 1 << len) - 1))); | |
230d793d | 3354 | |
d0ab8cd3 | 3355 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3356 | if (split && split != &SET_SRC (x)) |
3357 | return split; | |
3358 | } | |
3359 | else | |
3360 | { | |
3361 | SUBST (SET_SRC (x), | |
f1c6ba8b | 3362 | gen_rtx_fmt_ee |
d0ab8cd3 | 3363 | (unsignedp ? LSHIFTRT : ASHIFTRT, mode, |
f1c6ba8b | 3364 | gen_rtx_ASHIFT (mode, |
4de249d9 | 3365 | gen_lowpart (mode, inner), |
f1c6ba8b RK |
3366 | GEN_INT (GET_MODE_BITSIZE (mode) |
3367 | - len - pos)), | |
5f4f0e22 | 3368 | GEN_INT (GET_MODE_BITSIZE (mode) - len))); |
230d793d | 3369 | |
d0ab8cd3 | 3370 | split = find_split_point (&SET_SRC (x), insn); |
230d793d RS |
3371 | if (split && split != &SET_SRC (x)) |
3372 | return split; | |
3373 | } | |
3374 | } | |
3375 | ||
3376 | /* See if this is a simple operation with a constant as the second | |
3377 | operand. It might be that this constant is out of range and hence | |
3378 | could be used as a split point. */ | |
ec8e098d | 3379 | if (BINARY_P (SET_SRC (x)) |
230d793d | 3380 | && CONSTANT_P (XEXP (SET_SRC (x), 1)) |
ec8e098d | 3381 | && (OBJECT_P (XEXP (SET_SRC (x), 0)) |
230d793d | 3382 | || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG |
ec8e098d | 3383 | && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0)))))) |
230d793d RS |
3384 | return &XEXP (SET_SRC (x), 1); |
3385 | ||
3386 | /* Finally, see if this is a simple operation with its first operand | |
3387 | not in a register. The operation might require this operand in a | |
3388 | register, so return it as a split point. We can always do this | |
3389 | because if the first operand were another operation, we would have | |
3390 | already found it as a split point. */ | |
ec8e098d | 3391 | if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x))) |
230d793d RS |
3392 | && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) |
3393 | return &XEXP (SET_SRC (x), 0); | |
3394 | ||
3395 | return 0; | |
3396 | ||
3397 | case AND: | |
3398 | case IOR: | |
3399 | /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
3400 | it is better to write this as (not (ior A B)) so we can split it. | |
3401 | Similarly for IOR. */ | |
3402 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
3403 | { | |
3404 | SUBST (*loc, | |
f1c6ba8b RK |
3405 | gen_rtx_NOT (GET_MODE (x), |
3406 | gen_rtx_fmt_ee (code == IOR ? AND : IOR, | |
3407 | GET_MODE (x), | |
3408 | XEXP (XEXP (x, 0), 0), | |
3409 | XEXP (XEXP (x, 1), 0)))); | |
d0ab8cd3 | 3410 | return find_split_point (loc, insn); |
230d793d RS |
3411 | } |
3412 | ||
3413 | /* Many RISC machines have a large set of logical insns. If the | |
3414 | second operand is a NOT, put it first so we will try to split the | |
3415 | other operand first. */ | |
3416 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
3417 | { | |
3418 | rtx tem = XEXP (x, 0); | |
3419 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3420 | SUBST (XEXP (x, 1), tem); | |
3421 | } | |
3422 | break; | |
e9a25f70 JL |
3423 | |
3424 | default: | |
3425 | break; | |
230d793d RS |
3426 | } |
3427 | ||
3428 | /* Otherwise, select our actions depending on our rtx class. */ | |
3429 | switch (GET_RTX_CLASS (code)) | |
3430 | { | |
ec8e098d PB |
3431 | case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ |
3432 | case RTX_TERNARY: | |
d0ab8cd3 | 3433 | split = find_split_point (&XEXP (x, 2), insn); |
230d793d RS |
3434 | if (split) |
3435 | return split; | |
0f41302f | 3436 | /* ... fall through ... */ |
ec8e098d PB |
3437 | case RTX_BIN_ARITH: |
3438 | case RTX_COMM_ARITH: | |
3439 | case RTX_COMPARE: | |
3440 | case RTX_COMM_COMPARE: | |
d0ab8cd3 | 3441 | split = find_split_point (&XEXP (x, 1), insn); |
230d793d RS |
3442 | if (split) |
3443 | return split; | |
0f41302f | 3444 | /* ... fall through ... */ |
ec8e098d | 3445 | case RTX_UNARY: |
230d793d RS |
3446 | /* Some machines have (and (shift ...) ...) insns. If X is not |
3447 | an AND, but XEXP (X, 0) is, use it as our split point. */ | |
3448 | if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
3449 | return &XEXP (x, 0); | |
3450 | ||
d0ab8cd3 | 3451 | split = find_split_point (&XEXP (x, 0), insn); |
230d793d RS |
3452 | if (split) |
3453 | return split; | |
3454 | return loc; | |
230d793d | 3455 | |
ec8e098d PB |
3456 | default: |
3457 | /* Otherwise, we don't have a split point. */ | |
3458 | return 0; | |
3459 | } | |
230d793d RS |
3460 | } |
3461 | \f | |
3462 | /* Throughout X, replace FROM with TO, and return the result. | |
3463 | The result is TO if X is FROM; | |
3464 | otherwise the result is X, but its contents may have been modified. | |
3465 | If they were modified, a record was made in undobuf so that | |
3466 | undo_all will (among other things) return X to its original state. | |
3467 | ||
3468 | If the number of changes necessary is too much to record to undo, | |
3469 | the excess changes are not made, so the result is invalid. | |
3470 | The changes already made can still be undone. | |
3471 | undobuf.num_undo is incremented for such changes, so by testing that | |
3472 | the caller can tell whether the result is valid. | |
3473 | ||
3474 | `n_occurrences' is incremented each time FROM is replaced. | |
663522cb | 3475 | |
da7d8304 | 3476 | IN_DEST is nonzero if we are processing the SET_DEST of a SET. |
230d793d | 3477 | |
da7d8304 KH |
3478 | UNIQUE_COPY is nonzero if each substitution must be unique. We do this |
3479 | by copying if `n_occurrences' is nonzero. */ | |
230d793d RS |
3480 | |
3481 | static rtx | |
79a490a9 | 3482 | subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy) |
230d793d | 3483 | { |
b3694847 | 3484 | enum rtx_code code = GET_CODE (x); |
230d793d | 3485 | enum machine_mode op0_mode = VOIDmode; |
b3694847 SS |
3486 | const char *fmt; |
3487 | int len, i; | |
8079805d | 3488 | rtx new; |
230d793d RS |
3489 | |
3490 | /* Two expressions are equal if they are identical copies of a shared | |
3491 | RTX or if they are both registers with the same register number | |
3492 | and mode. */ | |
3493 | ||
3494 | #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
3495 | ((X) == (Y) \ | |
f8cfc6aa | 3496 | || (REG_P (X) && REG_P (Y) \ |
230d793d RS |
3497 | && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) |
3498 | ||
3499 | if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) | |
3500 | { | |
3501 | n_occurrences++; | |
3502 | return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
3503 | } | |
3504 | ||
3505 | /* If X and FROM are the same register but different modes, they will | |
663522cb | 3506 | not have been seen as equal above. However, flow.c will make a |
230d793d RS |
3507 | LOG_LINKS entry for that case. If we do nothing, we will try to |
3508 | rerecognize our original insn and, when it succeeds, we will | |
3509 | delete the feeding insn, which is incorrect. | |
3510 | ||
3511 | So force this insn not to match in this (rare) case. */ | |
f8cfc6aa | 3512 | if (! in_dest && code == REG && REG_P (from) |
230d793d | 3513 | && REGNO (x) == REGNO (from)) |
38a448ca | 3514 | return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
3515 | |
3516 | /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
3517 | of which may contain things that can be combined. */ | |
ec8e098d | 3518 | if (code != MEM && code != LO_SUM && OBJECT_P (x)) |
230d793d RS |
3519 | return x; |
3520 | ||
3521 | /* It is possible to have a subexpression appear twice in the insn. | |
3522 | Suppose that FROM is a register that appears within TO. | |
3523 | Then, after that subexpression has been scanned once by `subst', | |
3524 | the second time it is scanned, TO may be found. If we were | |
3525 | to scan TO here, we would find FROM within it and create a | |
3526 | self-referent rtl structure which is completely wrong. */ | |
3527 | if (COMBINE_RTX_EQUAL_P (x, to)) | |
3528 | return to; | |
3529 | ||
4f4b3679 RH |
3530 | /* Parallel asm_operands need special attention because all of the |
3531 | inputs are shared across the arms. Furthermore, unsharing the | |
3532 | rtl results in recognition failures. Failure to handle this case | |
3533 | specially can result in circular rtl. | |
3534 | ||
3535 | Solve this by doing a normal pass across the first entry of the | |
3536 | parallel, and only processing the SET_DESTs of the subsequent | |
3537 | entries. Ug. */ | |
3538 | ||
3539 | if (code == PARALLEL | |
3540 | && GET_CODE (XVECEXP (x, 0, 0)) == SET | |
3541 | && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS) | |
230d793d | 3542 | { |
4f4b3679 RH |
3543 | new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy); |
3544 | ||
3545 | /* If this substitution failed, this whole thing fails. */ | |
3546 | if (GET_CODE (new) == CLOBBER | |
3547 | && XEXP (new, 0) == const0_rtx) | |
3548 | return new; | |
3549 | ||
3550 | SUBST (XVECEXP (x, 0, 0), new); | |
3551 | ||
3552 | for (i = XVECLEN (x, 0) - 1; i >= 1; i--) | |
230d793d | 3553 | { |
4f4b3679 | 3554 | rtx dest = SET_DEST (XVECEXP (x, 0, i)); |
663522cb | 3555 | |
f8cfc6aa | 3556 | if (!REG_P (dest) |
4f4b3679 RH |
3557 | && GET_CODE (dest) != CC0 |
3558 | && GET_CODE (dest) != PC) | |
230d793d | 3559 | { |
4f4b3679 | 3560 | new = subst (dest, from, to, 0, unique_copy); |
230d793d | 3561 | |
4f4b3679 RH |
3562 | /* If this substitution failed, this whole thing fails. */ |
3563 | if (GET_CODE (new) == CLOBBER | |
3564 | && XEXP (new, 0) == const0_rtx) | |
3565 | return new; | |
230d793d | 3566 | |
4f4b3679 | 3567 | SUBST (SET_DEST (XVECEXP (x, 0, i)), new); |
230d793d RS |
3568 | } |
3569 | } | |
4f4b3679 RH |
3570 | } |
3571 | else | |
3572 | { | |
3573 | len = GET_RTX_LENGTH (code); | |
3574 | fmt = GET_RTX_FORMAT (code); | |
3575 | ||
3576 | /* We don't need to process a SET_DEST that is a register, CC0, | |
3577 | or PC, so set up to skip this common case. All other cases | |
3578 | where we want to suppress replacing something inside a | |
3579 | SET_SRC are handled via the IN_DEST operand. */ | |
3580 | if (code == SET | |
f8cfc6aa | 3581 | && (REG_P (SET_DEST (x)) |
4f4b3679 RH |
3582 | || GET_CODE (SET_DEST (x)) == CC0 |
3583 | || GET_CODE (SET_DEST (x)) == PC)) | |
3584 | fmt = "ie"; | |
3585 | ||
3586 | /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a | |
3587 | constant. */ | |
3588 | if (fmt[0] == 'e') | |
3589 | op0_mode = GET_MODE (XEXP (x, 0)); | |
3590 | ||
3591 | for (i = 0; i < len; i++) | |
230d793d | 3592 | { |
4f4b3679 | 3593 | if (fmt[i] == 'E') |
230d793d | 3594 | { |
b3694847 | 3595 | int j; |
4f4b3679 RH |
3596 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
3597 | { | |
3598 | if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
3599 | { | |
3600 | new = (unique_copy && n_occurrences | |
3601 | ? copy_rtx (to) : to); | |
3602 | n_occurrences++; | |
3603 | } | |
3604 | else | |
3605 | { | |
3606 | new = subst (XVECEXP (x, i, j), from, to, 0, | |
3607 | unique_copy); | |
3608 | ||
3609 | /* If this substitution failed, this whole thing | |
3610 | fails. */ | |
3611 | if (GET_CODE (new) == CLOBBER | |
3612 | && XEXP (new, 0) == const0_rtx) | |
3613 | return new; | |
3614 | } | |
3615 | ||
3616 | SUBST (XVECEXP (x, i, j), new); | |
3617 | } | |
3618 | } | |
3619 | else if (fmt[i] == 'e') | |
3620 | { | |
0a33d11e RH |
3621 | /* If this is a register being set, ignore it. */ |
3622 | new = XEXP (x, i); | |
3623 | if (in_dest | |
0a33d11e | 3624 | && i == 0 |
b78b8bd8 JJ |
3625 | && (((code == SUBREG || code == ZERO_EXTRACT) |
3626 | && REG_P (new)) | |
3627 | || code == STRICT_LOW_PART)) | |
0a33d11e RH |
3628 | ; |
3629 | ||
3630 | else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
4f4b3679 RH |
3631 | { |
3632 | /* In general, don't install a subreg involving two | |
3633 | modes not tieable. It can worsen register | |
3634 | allocation, and can even make invalid reload | |
3635 | insns, since the reg inside may need to be copied | |
3636 | from in the outside mode, and that may be invalid | |
3637 | if it is an fp reg copied in integer mode. | |
3638 | ||
3639 | We allow two exceptions to this: It is valid if | |
3640 | it is inside another SUBREG and the mode of that | |
3641 | SUBREG and the mode of the inside of TO is | |
3642 | tieable and it is valid if X is a SET that copies | |
3643 | FROM to CC0. */ | |
3644 | ||
3645 | if (GET_CODE (to) == SUBREG | |
3646 | && ! MODES_TIEABLE_P (GET_MODE (to), | |
3647 | GET_MODE (SUBREG_REG (to))) | |
3648 | && ! (code == SUBREG | |
3649 | && MODES_TIEABLE_P (GET_MODE (x), | |
3650 | GET_MODE (SUBREG_REG (to)))) | |
42301240 | 3651 | #ifdef HAVE_cc0 |
4f4b3679 | 3652 | && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx) |
42301240 | 3653 | #endif |
4f4b3679 RH |
3654 | ) |
3655 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); | |
42301240 | 3656 | |
cff9f8d5 | 3657 | #ifdef CANNOT_CHANGE_MODE_CLASS |
ed8afe3a | 3658 | if (code == SUBREG |
f8cfc6aa | 3659 | && REG_P (to) |
ed8afe3a | 3660 | && REGNO (to) < FIRST_PSEUDO_REGISTER |
cff9f8d5 AH |
3661 | && REG_CANNOT_CHANGE_MODE_P (REGNO (to), |
3662 | GET_MODE (to), | |
3663 | GET_MODE (x))) | |
ed8afe3a GK |
3664 | return gen_rtx_CLOBBER (VOIDmode, const0_rtx); |
3665 | #endif | |
3666 | ||
4f4b3679 RH |
3667 | new = (unique_copy && n_occurrences ? copy_rtx (to) : to); |
3668 | n_occurrences++; | |
3669 | } | |
3670 | else | |
3671 | /* If we are in a SET_DEST, suppress most cases unless we | |
3672 | have gone inside a MEM, in which case we want to | |
3673 | simplify the address. We assume here that things that | |
3674 | are actually part of the destination have their inner | |
663522cb | 3675 | parts in the first expression. This is true for SUBREG, |
4f4b3679 RH |
3676 | STRICT_LOW_PART, and ZERO_EXTRACT, which are the only |
3677 | things aside from REG and MEM that should appear in a | |
3678 | SET_DEST. */ | |
3679 | new = subst (XEXP (x, i), from, to, | |
3680 | (((in_dest | |
3681 | && (code == SUBREG || code == STRICT_LOW_PART | |
3682 | || code == ZERO_EXTRACT)) | |
3683 | || code == SET) | |
3684 | && i == 0), unique_copy); | |
3685 | ||
3686 | /* If we found that we will have to reject this combination, | |
3687 | indicate that by returning the CLOBBER ourselves, rather than | |
3688 | an expression containing it. This will speed things up as | |
3689 | well as prevent accidents where two CLOBBERs are considered | |
3690 | to be equal, thus producing an incorrect simplification. */ | |
3691 | ||
3692 | if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) | |
3693 | return new; | |
3694 | ||
cc8c96fd RS |
3695 | if (GET_CODE (x) == SUBREG |
3696 | && (GET_CODE (new) == CONST_INT | |
3697 | || GET_CODE (new) == CONST_DOUBLE)) | |
4161da12 | 3698 | { |
b0dd4808 | 3699 | enum machine_mode mode = GET_MODE (x); |
2e676d78 | 3700 | |
4161da12 AO |
3701 | x = simplify_subreg (GET_MODE (x), new, |
3702 | GET_MODE (SUBREG_REG (x)), | |
3703 | SUBREG_BYTE (x)); | |
3704 | if (! x) | |
b0dd4808 | 3705 | x = gen_rtx_CLOBBER (mode, const0_rtx); |
4161da12 AO |
3706 | } |
3707 | else if (GET_CODE (new) == CONST_INT | |
3708 | && GET_CODE (x) == ZERO_EXTEND) | |
3709 | { | |
3710 | x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
3711 | new, GET_MODE (XEXP (x, 0))); | |
341c100f | 3712 | gcc_assert (x); |
4161da12 AO |
3713 | } |
3714 | else | |
3715 | SUBST (XEXP (x, i), new); | |
230d793d | 3716 | } |
230d793d RS |
3717 | } |
3718 | } | |
3719 | ||
8079805d RK |
3720 | /* Try to simplify X. If the simplification changed the code, it is likely |
3721 | that further simplification will help, so loop, but limit the number | |
3722 | of repetitions that will be performed. */ | |
3723 | ||
3724 | for (i = 0; i < 4; i++) | |
3725 | { | |
3726 | /* If X is sufficiently simple, don't bother trying to do anything | |
3727 | with it. */ | |
3728 | if (code != CONST_INT && code != REG && code != CLOBBER) | |
6621d78e | 3729 | x = combine_simplify_rtx (x, op0_mode, in_dest); |
d0ab8cd3 | 3730 | |
8079805d RK |
3731 | if (GET_CODE (x) == code) |
3732 | break; | |
d0ab8cd3 | 3733 | |
8079805d | 3734 | code = GET_CODE (x); |
eeb43d32 | 3735 | |
8079805d RK |
3736 | /* We no longer know the original mode of operand 0 since we |
3737 | have changed the form of X) */ | |
3738 | op0_mode = VOIDmode; | |
3739 | } | |
eeb43d32 | 3740 | |
8079805d RK |
3741 | return x; |
3742 | } | |
3743 | \f | |
3744 | /* Simplify X, a piece of RTL. We just operate on the expression at the | |
3745 | outer level; call `subst' to simplify recursively. Return the new | |
3746 | expression. | |
3747 | ||
6621d78e PB |
3748 | OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero |
3749 | if we are inside a SET_DEST. */ | |
eeb43d32 | 3750 | |
8079805d | 3751 | static rtx |
6621d78e | 3752 | combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest) |
8079805d RK |
3753 | { |
3754 | enum rtx_code code = GET_CODE (x); | |
3755 | enum machine_mode mode = GET_MODE (x); | |
3756 | rtx temp; | |
9a915772 | 3757 | rtx reversed; |
8079805d | 3758 | int i; |
d0ab8cd3 | 3759 | |
230d793d RS |
3760 | /* If this is a commutative operation, put a constant last and a complex |
3761 | expression first. We don't need to do this for comparisons here. */ | |
ec8e098d | 3762 | if (COMMUTATIVE_ARITH_P (x) |
e5c56fd9 | 3763 | && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) |
230d793d RS |
3764 | { |
3765 | temp = XEXP (x, 0); | |
3766 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
3767 | SUBST (XEXP (x, 1), temp); | |
3768 | } | |
3769 | ||
663522cb | 3770 | /* If this is a simple operation applied to an IF_THEN_ELSE, try |
d0ab8cd3 | 3771 | applying it to the arms of the IF_THEN_ELSE. This often simplifies |
abe6e52f RK |
3772 | things. Check for cases where both arms are testing the same |
3773 | condition. | |
3774 | ||
3775 | Don't do anything if all operands are very simple. */ | |
3776 | ||
ec8e098d PB |
3777 | if ((BINARY_P (x) |
3778 | && ((!OBJECT_P (XEXP (x, 0)) | |
abe6e52f | 3779 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
ec8e098d PB |
3780 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))) |
3781 | || (!OBJECT_P (XEXP (x, 1)) | |
abe6e52f | 3782 | && ! (GET_CODE (XEXP (x, 1)) == SUBREG |
ec8e098d PB |
3783 | && OBJECT_P (SUBREG_REG (XEXP (x, 1))))))) |
3784 | || (UNARY_P (x) | |
3785 | && (!OBJECT_P (XEXP (x, 0)) | |
abe6e52f | 3786 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
ec8e098d | 3787 | && OBJECT_P (SUBREG_REG (XEXP (x, 0))))))) |
d0ab8cd3 | 3788 | { |
d6edb99e | 3789 | rtx cond, true_rtx, false_rtx; |
abe6e52f | 3790 | |
d6edb99e | 3791 | cond = if_then_else_cond (x, &true_rtx, &false_rtx); |
0802d516 RK |
3792 | if (cond != 0 |
3793 | /* If everything is a comparison, what we have is highly unlikely | |
3794 | to be simpler, so don't use it. */ | |
ec8e098d PB |
3795 | && ! (COMPARISON_P (x) |
3796 | && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))) | |
abe6e52f RK |
3797 | { |
3798 | rtx cop1 = const0_rtx; | |
3799 | enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1); | |
3800 | ||
ec8e098d | 3801 | if (cond_code == NE && COMPARISON_P (cond)) |
15448afc RK |
3802 | return x; |
3803 | ||
663522cb | 3804 | /* Simplify the alternative arms; this may collapse the true and |
c6279378 UW |
3805 | false arms to store-flag values. Be careful to use copy_rtx |
3806 | here since true_rtx or false_rtx might share RTL with x as a | |
3807 | result of the if_then_else_cond call above. */ | |
3808 | true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0); | |
3809 | false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0); | |
9210df58 | 3810 | |
d6edb99e | 3811 | /* If true_rtx and false_rtx are not general_operands, an if_then_else |
085f1714 | 3812 | is unlikely to be simpler. */ |
d6edb99e ZW |
3813 | if (general_operand (true_rtx, VOIDmode) |
3814 | && general_operand (false_rtx, VOIDmode)) | |
085f1714 | 3815 | { |
434c87d4 JH |
3816 | enum rtx_code reversed; |
3817 | ||
085f1714 RH |
3818 | /* Restarting if we generate a store-flag expression will cause |
3819 | us to loop. Just drop through in this case. */ | |
3820 | ||
3821 | /* If the result values are STORE_FLAG_VALUE and zero, we can | |
3822 | just make the comparison operation. */ | |
d6edb99e | 3823 | if (true_rtx == const_true_rtx && false_rtx == const0_rtx) |
bcb34aa3 PB |
3824 | x = simplify_gen_relational (cond_code, mode, VOIDmode, |
3825 | cond, cop1); | |
fa4e13e0 | 3826 | else if (true_rtx == const0_rtx && false_rtx == const_true_rtx |
434c87d4 | 3827 | && ((reversed = reversed_comparison_code_parts |
79a490a9 | 3828 | (cond_code, cond, cop1, NULL)) |
434c87d4 | 3829 | != UNKNOWN)) |
bcb34aa3 PB |
3830 | x = simplify_gen_relational (reversed, mode, VOIDmode, |
3831 | cond, cop1); | |
085f1714 RH |
3832 | |
3833 | /* Likewise, we can make the negate of a comparison operation | |
3834 | if the result values are - STORE_FLAG_VALUE and zero. */ | |
d6edb99e ZW |
3835 | else if (GET_CODE (true_rtx) == CONST_INT |
3836 | && INTVAL (true_rtx) == - STORE_FLAG_VALUE | |
3837 | && false_rtx == const0_rtx) | |
f1c6ba8b | 3838 | x = simplify_gen_unary (NEG, mode, |
bcb34aa3 PB |
3839 | simplify_gen_relational (cond_code, |
3840 | mode, VOIDmode, | |
3841 | cond, cop1), | |
f1c6ba8b | 3842 | mode); |
d6edb99e ZW |
3843 | else if (GET_CODE (false_rtx) == CONST_INT |
3844 | && INTVAL (false_rtx) == - STORE_FLAG_VALUE | |
434c87d4 JH |
3845 | && true_rtx == const0_rtx |
3846 | && ((reversed = reversed_comparison_code_parts | |
79a490a9 | 3847 | (cond_code, cond, cop1, NULL)) |
434c87d4 | 3848 | != UNKNOWN)) |
f1c6ba8b | 3849 | x = simplify_gen_unary (NEG, mode, |
bcb34aa3 PB |
3850 | simplify_gen_relational (reversed, |
3851 | mode, VOIDmode, | |
3852 | cond, cop1), | |
f1c6ba8b | 3853 | mode); |
085f1714 RH |
3854 | else |
3855 | return gen_rtx_IF_THEN_ELSE (mode, | |
bcb34aa3 PB |
3856 | simplify_gen_relational (cond_code, |
3857 | mode, | |
3858 | VOIDmode, | |
3859 | cond, | |
3860 | cop1), | |
d6edb99e | 3861 | true_rtx, false_rtx); |
5109d49f | 3862 | |
085f1714 RH |
3863 | code = GET_CODE (x); |
3864 | op0_mode = VOIDmode; | |
3865 | } | |
abe6e52f | 3866 | } |
d0ab8cd3 RK |
3867 | } |
3868 | ||
230d793d RS |
3869 | /* Try to fold this expression in case we have constants that weren't |
3870 | present before. */ | |
3871 | temp = 0; | |
3872 | switch (GET_RTX_CLASS (code)) | |
3873 | { | |
ec8e098d | 3874 | case RTX_UNARY: |
c0657872 RS |
3875 | if (op0_mode == VOIDmode) |
3876 | op0_mode = GET_MODE (XEXP (x, 0)); | |
230d793d RS |
3877 | temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); |
3878 | break; | |
ec8e098d PB |
3879 | case RTX_COMPARE: |
3880 | case RTX_COMM_COMPARE: | |
47b1e19b JH |
3881 | { |
3882 | enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0)); | |
3883 | if (cmp_mode == VOIDmode) | |
1cac8785 DD |
3884 | { |
3885 | cmp_mode = GET_MODE (XEXP (x, 1)); | |
3886 | if (cmp_mode == VOIDmode) | |
3887 | cmp_mode = op0_mode; | |
3888 | } | |
7ce3e360 | 3889 | temp = simplify_relational_operation (code, mode, cmp_mode, |
47b1e19b JH |
3890 | XEXP (x, 0), XEXP (x, 1)); |
3891 | } | |
230d793d | 3892 | break; |
ec8e098d PB |
3893 | case RTX_COMM_ARITH: |
3894 | case RTX_BIN_ARITH: | |
230d793d RS |
3895 | temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); |
3896 | break; | |
ec8e098d PB |
3897 | case RTX_BITFIELD_OPS: |
3898 | case RTX_TERNARY: | |
230d793d RS |
3899 | temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), |
3900 | XEXP (x, 1), XEXP (x, 2)); | |
3901 | break; | |
ec8e098d PB |
3902 | default: |
3903 | break; | |
230d793d RS |
3904 | } |
3905 | ||
3906 | if (temp) | |
4531c1c7 DN |
3907 | { |
3908 | x = temp; | |
3909 | code = GET_CODE (temp); | |
3910 | op0_mode = VOIDmode; | |
3911 | mode = GET_MODE (temp); | |
3912 | } | |
230d793d | 3913 | |
230d793d | 3914 | /* First see if we can apply the inverse distributive law. */ |
224eeff2 RK |
3915 | if (code == PLUS || code == MINUS |
3916 | || code == AND || code == IOR || code == XOR) | |
230d793d RS |
3917 | { |
3918 | x = apply_distributive_law (x); | |
3919 | code = GET_CODE (x); | |
6e20204f | 3920 | op0_mode = VOIDmode; |
230d793d RS |
3921 | } |
3922 | ||
3923 | /* If CODE is an associative operation not otherwise handled, see if we | |
3924 | can associate some operands. This can win if they are constants or | |
e0e08ac2 | 3925 | if they are logically related (i.e. (a & b) & a). */ |
493efd37 TM |
3926 | if ((code == PLUS || code == MINUS || code == MULT || code == DIV |
3927 | || code == AND || code == IOR || code == XOR | |
230d793d | 3928 | || code == SMAX || code == SMIN || code == UMAX || code == UMIN) |
493efd37 | 3929 | && ((INTEGRAL_MODE_P (mode) && code != DIV) |
4ba5f925 | 3930 | || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode)))) |
230d793d RS |
3931 | { |
3932 | if (GET_CODE (XEXP (x, 0)) == code) | |
3933 | { | |
3934 | rtx other = XEXP (XEXP (x, 0), 0); | |
3935 | rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
3936 | rtx inner_op1 = XEXP (x, 1); | |
3937 | rtx inner; | |
663522cb | 3938 | |
230d793d RS |
3939 | /* Make sure we pass the constant operand if any as the second |
3940 | one if this is a commutative operation. */ | |
ec8e098d | 3941 | if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x)) |
230d793d RS |
3942 | { |
3943 | rtx tem = inner_op0; | |
3944 | inner_op0 = inner_op1; | |
3945 | inner_op1 = tem; | |
3946 | } | |
3947 | inner = simplify_binary_operation (code == MINUS ? PLUS | |
3948 | : code == DIV ? MULT | |
230d793d RS |
3949 | : code, |
3950 | mode, inner_op0, inner_op1); | |
3951 | ||
3952 | /* For commutative operations, try the other pair if that one | |
3953 | didn't simplify. */ | |
ec8e098d | 3954 | if (inner == 0 && COMMUTATIVE_ARITH_P (x)) |
230d793d RS |
3955 | { |
3956 | other = XEXP (XEXP (x, 0), 1); | |
3957 | inner = simplify_binary_operation (code, mode, | |
3958 | XEXP (XEXP (x, 0), 0), | |
3959 | XEXP (x, 1)); | |
3960 | } | |
3961 | ||
3962 | if (inner) | |
bcb34aa3 | 3963 | return simplify_gen_binary (code, mode, other, inner); |
230d793d RS |
3964 | } |
3965 | } | |
3966 | ||
3967 | /* A little bit of algebraic simplification here. */ | |
3968 | switch (code) | |
3969 | { | |
3970 | case MEM: | |
3971 | /* Ensure that our address has any ASHIFTs converted to MULT in case | |
3972 | address-recognizing predicates are called later. */ | |
3973 | temp = make_compound_operation (XEXP (x, 0), MEM); | |
3974 | SUBST (XEXP (x, 0), temp); | |
3975 | break; | |
3976 | ||
3977 | case SUBREG: | |
eea50aa0 JH |
3978 | if (op0_mode == VOIDmode) |
3979 | op0_mode = GET_MODE (SUBREG_REG (x)); | |
230d793d | 3980 | |
4de249d9 | 3981 | /* See if this can be moved to simplify_subreg. */ |
3c99d5ff | 3982 | if (CONSTANT_P (SUBREG_REG (x)) |
156755ac | 3983 | && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x) |
4de249d9 | 3984 | /* Don't call gen_lowpart if the inner mode |
156755ac JJ |
3985 | is VOIDmode and we cannot simplify it, as SUBREG without |
3986 | inner mode is invalid. */ | |
3987 | && (GET_MODE (SUBREG_REG (x)) != VOIDmode | |
3988 | || gen_lowpart_common (mode, SUBREG_REG (x)))) | |
4de249d9 | 3989 | return gen_lowpart (mode, SUBREG_REG (x)); |
230d793d | 3990 | |
a13287e1 AM |
3991 | if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC) |
3992 | break; | |
eea50aa0 JH |
3993 | { |
3994 | rtx temp; | |
3995 | temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode, | |
23190837 | 3996 | SUBREG_BYTE (x)); |
eea50aa0 JH |
3997 | if (temp) |
3998 | return temp; | |
3999 | } | |
b65c1b5b | 4000 | |
30984c57 | 4001 | /* Don't change the mode of the MEM if that would change the meaning |
3eacd71f | 4002 | of the address. */ |
3c0cb5de | 4003 | if (MEM_P (SUBREG_REG (x)) |
30984c57 | 4004 | && (MEM_VOLATILE_P (SUBREG_REG (x)) |
3eacd71f | 4005 | || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0)))) |
30984c57 JJ |
4006 | return gen_rtx_CLOBBER (mode, const0_rtx); |
4007 | ||
87e3e0c1 RK |
4008 | /* Note that we cannot do any narrowing for non-constants since |
4009 | we might have been counting on using the fact that some bits were | |
4010 | zero. We now do this in the SET. */ | |
4011 | ||
230d793d RS |
4012 | break; |
4013 | ||
4014 | case NOT: | |
230d793d RS |
4015 | if (GET_CODE (XEXP (x, 0)) == SUBREG |
4016 | && subreg_lowpart_p (XEXP (x, 0)) | |
4017 | && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) | |
4018 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) | |
4019 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT | |
4020 | && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) | |
4021 | { | |
4022 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); | |
4023 | ||
38a448ca | 4024 | x = gen_rtx_ROTATE (inner_mode, |
f1c6ba8b RK |
4025 | simplify_gen_unary (NOT, inner_mode, const1_rtx, |
4026 | inner_mode), | |
38a448ca | 4027 | XEXP (SUBREG_REG (XEXP (x, 0)), 1)); |
4de249d9 | 4028 | return gen_lowpart (mode, x); |
230d793d | 4029 | } |
663522cb | 4030 | |
230d793d | 4031 | /* Apply De Morgan's laws to reduce number of patterns for machines |
23190837 AJ |
4032 | with negating logical insns (and-not, nand, etc.). If result has |
4033 | only one NOT, put it first, since that is how the patterns are | |
4034 | coded. */ | |
230d793d RS |
4035 | |
4036 | if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) | |
23190837 | 4037 | { |
663522cb | 4038 | rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); |
5bd60ce6 | 4039 | enum machine_mode op_mode; |
230d793d | 4040 | |
5bd60ce6 | 4041 | op_mode = GET_MODE (in1); |
f1c6ba8b | 4042 | in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode); |
230d793d | 4043 | |
5bd60ce6 RH |
4044 | op_mode = GET_MODE (in2); |
4045 | if (op_mode == VOIDmode) | |
4046 | op_mode = mode; | |
f1c6ba8b | 4047 | in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode); |
663522cb | 4048 | |
5bd60ce6 | 4049 | if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT) |
663522cb KH |
4050 | { |
4051 | rtx tem = in2; | |
4052 | in2 = in1; in1 = tem; | |
4053 | } | |
4054 | ||
f1c6ba8b RK |
4055 | return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, |
4056 | mode, in1, in2); | |
663522cb | 4057 | } |
230d793d RS |
4058 | break; |
4059 | ||
4060 | case NEG: | |
0f41302f | 4061 | /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */ |
4f61b3b7 RS |
4062 | if (GET_CODE (XEXP (x, 0)) == XOR |
4063 | && XEXP (XEXP (x, 0), 1) == const1_rtx | |
951553af | 4064 | && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1) |
bcb34aa3 PB |
4065 | return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), |
4066 | constm1_rtx); | |
d0ab8cd3 | 4067 | |
230d793d RS |
4068 | temp = expand_compound_operation (XEXP (x, 0)); |
4069 | ||
4070 | /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
23190837 | 4071 | replaced by (lshiftrt X C). This will convert |
230d793d RS |
4072 | (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ |
4073 | ||
4074 | if (GET_CODE (temp) == ASHIFTRT | |
4075 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
4076 | && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
8079805d RK |
4077 | return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), |
4078 | INTVAL (XEXP (temp, 1))); | |
230d793d | 4079 | |
951553af | 4080 | /* If X has only a single bit that might be nonzero, say, bit I, convert |
230d793d RS |
4081 | (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of |
4082 | MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
4083 | (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
4084 | or a SUBREG of one since we'd be making the expression more | |
4085 | complex if it was just a register. */ | |
4086 | ||
f8cfc6aa | 4087 | if (!REG_P (temp) |
230d793d | 4088 | && ! (GET_CODE (temp) == SUBREG |
f8cfc6aa | 4089 | && REG_P (SUBREG_REG (temp))) |
951553af | 4090 | && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0) |
230d793d RS |
4091 | { |
4092 | rtx temp1 = simplify_shift_const | |
5f4f0e22 CH |
4093 | (NULL_RTX, ASHIFTRT, mode, |
4094 | simplify_shift_const (NULL_RTX, ASHIFT, mode, temp, | |
230d793d RS |
4095 | GET_MODE_BITSIZE (mode) - 1 - i), |
4096 | GET_MODE_BITSIZE (mode) - 1 - i); | |
4097 | ||
4098 | /* If all we did was surround TEMP with the two shifts, we | |
4099 | haven't improved anything, so don't use it. Otherwise, | |
4100 | we are better off with TEMP1. */ | |
4101 | if (GET_CODE (temp1) != ASHIFTRT | |
4102 | || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
4103 | || XEXP (XEXP (temp1, 0), 0) != temp) | |
8079805d | 4104 | return temp1; |
230d793d RS |
4105 | } |
4106 | break; | |
4107 | ||
2ca9ae17 | 4108 | case TRUNCATE: |
e30fb98f JL |
4109 | /* We can't handle truncation to a partial integer mode here |
4110 | because we don't know the real bitsize of the partial | |
4111 | integer mode. */ | |
4112 | if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT) | |
4113 | break; | |
4114 | ||
80608e27 JL |
4115 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
4116 | && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), | |
4117 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))) | |
2ca9ae17 JW |
4118 | SUBST (XEXP (x, 0), |
4119 | force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)), | |
4120 | GET_MODE_MASK (mode), NULL_RTX, 0)); | |
0f13a422 ILT |
4121 | |
4122 | /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */ | |
4123 | if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4124 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4125 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
4126 | return XEXP (XEXP (x, 0), 0); | |
4127 | ||
4128 | /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is | |
4129 | (OP:SI foo:SI) if OP is NEG or ABS. */ | |
4130 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4131 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4132 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND | |
4133 | || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND) | |
4134 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4135 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4136 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
0f13a422 ILT |
4137 | |
4138 | /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is | |
4139 | (truncate:SI x). */ | |
4140 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4141 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE | |
4142 | && subreg_lowpart_p (XEXP (x, 0))) | |
4143 | return SUBREG_REG (XEXP (x, 0)); | |
4144 | ||
4145 | /* If we know that the value is already truncated, we can | |
14a774a9 RK |
4146 | replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION |
4147 | is nonzero for the corresponding modes. But don't do this | |
4148 | for an (LSHIFTRT (MULT ...)) since this will cause problems | |
4149 | with the umulXi3_highpart patterns. */ | |
6a992214 JL |
4150 | if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), |
4151 | GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
4152 | && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
26c34780 | 4153 | >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1) |
14a774a9 | 4154 | && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
23190837 | 4155 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)) |
4de249d9 | 4156 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 ILT |
4157 | |
4158 | /* A truncate of a comparison can be replaced with a subreg if | |
4159 | STORE_FLAG_VALUE permits. This is like the previous test, | |
4160 | but it works even if the comparison is done in a mode larger | |
4161 | than HOST_BITS_PER_WIDE_INT. */ | |
4162 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
ec8e098d | 4163 | && COMPARISON_P (XEXP (x, 0)) |
663522cb | 4164 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0) |
4de249d9 | 4165 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 ILT |
4166 | |
4167 | /* Similarly, a truncate of a register whose value is a | |
4168 | comparison can be replaced with a subreg if STORE_FLAG_VALUE | |
4169 | permits. */ | |
4170 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
663522cb | 4171 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0 |
0f13a422 | 4172 | && (temp = get_last_value (XEXP (x, 0))) |
ec8e098d | 4173 | && COMPARISON_P (temp)) |
4de249d9 | 4174 | return gen_lowpart (mode, XEXP (x, 0)); |
0f13a422 | 4175 | |
2ca9ae17 JW |
4176 | break; |
4177 | ||
230d793d RS |
4178 | case FLOAT_TRUNCATE: |
4179 | /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ | |
4180 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
4181 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
663522cb | 4182 | return XEXP (XEXP (x, 0), 0); |
4635f748 | 4183 | |
73a39fc4 EC |
4184 | /* (float_truncate:SF (float_truncate:DF foo:XF)) |
4185 | = (float_truncate:SF foo:XF). | |
e0bb17a8 | 4186 | This may eliminate double rounding, so it is unsafe. |
949824fe | 4187 | |
73a39fc4 EC |
4188 | (float_truncate:SF (float_extend:XF foo:DF)) |
4189 | = (float_truncate:SF foo:DF). | |
949824fe | 4190 | |
73a39fc4 | 4191 | (float_truncate:DF (float_extend:XF foo:SF)) |
3dc575ff | 4192 | = (float_extend:SF foo:DF). */ |
949824fe JH |
4193 | if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE |
4194 | && flag_unsafe_math_optimizations) | |
4195 | || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND) | |
4196 | return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), | |
79a490a9 AJ |
4197 | 0))) |
4198 | > GET_MODE_SIZE (mode) | |
949824fe | 4199 | ? FLOAT_TRUNCATE : FLOAT_EXTEND, |
79a490a9 | 4200 | mode, |
cb119f82 | 4201 | XEXP (XEXP (x, 0), 0), mode); |
949824fe JH |
4202 | |
4203 | /* (float_truncate (float x)) is (float x) */ | |
4204 | if (GET_CODE (XEXP (x, 0)) == FLOAT | |
4205 | && (flag_unsafe_math_optimizations | |
4206 | || ((unsigned)significand_size (GET_MODE (XEXP (x, 0))) | |
4207 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) | |
4208 | - num_sign_bit_copies (XEXP (XEXP (x, 0), 0), | |
4209 | GET_MODE (XEXP (XEXP (x, 0), 0))))))) | |
4210 | return simplify_gen_unary (FLOAT, mode, | |
4211 | XEXP (XEXP (x, 0), 0), | |
4212 | GET_MODE (XEXP (XEXP (x, 0), 0))); | |
4213 | ||
4635f748 RK |
4214 | /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is |
4215 | (OP:SF foo:SF) if OP is NEG or ABS. */ | |
4216 | if ((GET_CODE (XEXP (x, 0)) == ABS | |
4217 | || GET_CODE (XEXP (x, 0)) == NEG) | |
4218 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND | |
4219 | && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode) | |
f1c6ba8b RK |
4220 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, |
4221 | XEXP (XEXP (XEXP (x, 0), 0), 0), mode); | |
1d12df72 RK |
4222 | |
4223 | /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0)) | |
4224 | is (float_truncate:SF x). */ | |
4225 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4226 | && subreg_lowpart_p (XEXP (x, 0)) | |
4227 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE) | |
4228 | return SUBREG_REG (XEXP (x, 0)); | |
663522cb | 4229 | break; |
949824fe JH |
4230 | case FLOAT_EXTEND: |
4231 | /* (float_extend (float_extend x)) is (float_extend x) | |
73a39fc4 | 4232 | |
949824fe | 4233 | (float_extend (float x)) is (float x) assuming that double |
73a39fc4 | 4234 | rounding can't happen. |
949824fe JH |
4235 | */ |
4236 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
4237 | || (GET_CODE (XEXP (x, 0)) == FLOAT | |
4238 | && ((unsigned)significand_size (GET_MODE (XEXP (x, 0))) | |
4239 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) | |
4240 | - num_sign_bit_copies (XEXP (XEXP (x, 0), 0), | |
4241 | GET_MODE (XEXP (XEXP (x, 0), 0))))))) | |
4242 | return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode, | |
4243 | XEXP (XEXP (x, 0), 0), | |
4244 | GET_MODE (XEXP (XEXP (x, 0), 0))); | |
230d793d | 4245 | |
949824fe | 4246 | break; |
230d793d RS |
4247 | #ifdef HAVE_cc0 |
4248 | case COMPARE: | |
4249 | /* Convert (compare FOO (const_int 0)) to FOO unless we aren't | |
4250 | using cc0, in which case we want to leave it as a COMPARE | |
4251 | so we can distinguish it from a register-register-copy. */ | |
4252 | if (XEXP (x, 1) == const0_rtx) | |
4253 | return XEXP (x, 0); | |
4254 | ||
71925bc0 RS |
4255 | /* x - 0 is the same as x unless x's mode has signed zeros and |
4256 | allows rounding towards -infinity. Under those conditions, | |
4257 | 0 - 0 is -0. */ | |
4258 | if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0))) | |
4259 | && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0)))) | |
230d793d RS |
4260 | && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) |
4261 | return XEXP (x, 0); | |
4262 | break; | |
4263 | #endif | |
4264 | ||
4265 | case CONST: | |
4266 | /* (const (const X)) can become (const X). Do it this way rather than | |
4267 | returning the inner CONST since CONST can be shared with a | |
4268 | REG_EQUAL note. */ | |
4269 | if (GET_CODE (XEXP (x, 0)) == CONST) | |
4270 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4271 | break; | |
4272 | ||
4273 | #ifdef HAVE_lo_sum | |
4274 | case LO_SUM: | |
4275 | /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
4276 | can add in an offset. find_split_point will split this address up | |
4277 | again if it doesn't match. */ | |
4278 | if (GET_CODE (XEXP (x, 0)) == HIGH | |
4279 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
4280 | return XEXP (x, 1); | |
4281 | break; | |
4282 | #endif | |
4283 | ||
4284 | case PLUS: | |
16823694 GK |
4285 | /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). |
4286 | */ | |
73a39fc4 | 4287 | if (GET_CODE (XEXP (x, 0)) == MULT |
16823694 GK |
4288 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG) |
4289 | { | |
4290 | rtx in1, in2; | |
73a39fc4 | 4291 | |
16823694 GK |
4292 | in1 = XEXP (XEXP (XEXP (x, 0), 0), 0); |
4293 | in2 = XEXP (XEXP (x, 0), 1); | |
bcb34aa3 PB |
4294 | return simplify_gen_binary (MINUS, mode, XEXP (x, 1), |
4295 | simplify_gen_binary (MULT, mode, | |
4296 | in1, in2)); | |
16823694 GK |
4297 | } |
4298 | ||
230d793d RS |
4299 | /* If we have (plus (plus (A const) B)), associate it so that CONST is |
4300 | outermost. That's because that's the way indexed addresses are | |
4301 | supposed to appear. This code used to check many more cases, but | |
4302 | they are now checked elsewhere. */ | |
4303 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
4304 | && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) | |
bcb34aa3 PB |
4305 | return simplify_gen_binary (PLUS, mode, |
4306 | simplify_gen_binary (PLUS, mode, | |
4307 | XEXP (XEXP (x, 0), 0), | |
4308 | XEXP (x, 1)), | |
4309 | XEXP (XEXP (x, 0), 1)); | |
230d793d RS |
4310 | |
4311 | /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) | |
4312 | when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
4313 | bit-field and can be replaced by either a sign_extend or a | |
e6380233 JL |
4314 | sign_extract. The `and' may be a zero_extend and the two |
4315 | <c>, -<c> constants may be reversed. */ | |
230d793d RS |
4316 | if (GET_CODE (XEXP (x, 0)) == XOR |
4317 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4318 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
663522cb | 4319 | && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1)) |
e6380233 JL |
4320 | && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 |
4321 | || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
5f4f0e22 | 4322 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
4323 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND |
4324 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
4325 | && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
5f4f0e22 | 4326 | == ((HOST_WIDE_INT) 1 << (i + 1)) - 1)) |
230d793d RS |
4327 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND |
4328 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) | |
770ae6cc | 4329 | == (unsigned int) i + 1)))) |
8079805d RK |
4330 | return simplify_shift_const |
4331 | (NULL_RTX, ASHIFTRT, mode, | |
4332 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4333 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
4334 | GET_MODE_BITSIZE (mode) - (i + 1)), | |
4335 | GET_MODE_BITSIZE (mode) - (i + 1)); | |
230d793d | 4336 | |
bc0776c6 RK |
4337 | /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if |
4338 | C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE | |
4339 | is 1. This produces better code than the alternative immediately | |
4340 | below. */ | |
ec8e098d | 4341 | if (COMPARISON_P (XEXP (x, 0)) |
bc0776c6 | 4342 | && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx) |
9a915772 | 4343 | || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)) |
14f02e73 | 4344 | && (reversed = reversed_comparison (XEXP (x, 0), mode))) |
8079805d | 4345 | return |
f1c6ba8b | 4346 | simplify_gen_unary (NEG, mode, reversed, mode); |
bc0776c6 RK |
4347 | |
4348 | /* If only the low-order bit of X is possibly nonzero, (plus x -1) | |
230d793d RS |
4349 | can become (ashiftrt (ashift (xor x 1) C) C) where C is |
4350 | the bitsize of the mode - 1. This allows simplification of | |
4351 | "a = (b & 8) == 0;" */ | |
4352 | if (XEXP (x, 1) == constm1_rtx | |
f8cfc6aa | 4353 | && !REG_P (XEXP (x, 0)) |
e869aa39 | 4354 | && ! (GET_CODE (XEXP (x, 0)) == SUBREG |
f8cfc6aa | 4355 | && REG_P (SUBREG_REG (XEXP (x, 0)))) |
951553af | 4356 | && nonzero_bits (XEXP (x, 0), mode) == 1) |
8079805d RK |
4357 | return simplify_shift_const (NULL_RTX, ASHIFTRT, mode, |
4358 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
f1c6ba8b | 4359 | gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx), |
8079805d RK |
4360 | GET_MODE_BITSIZE (mode) - 1), |
4361 | GET_MODE_BITSIZE (mode) - 1); | |
02f4ada4 RK |
4362 | |
4363 | /* If we are adding two things that have no bits in common, convert | |
4364 | the addition into an IOR. This will often be further simplified, | |
4365 | for example in cases like ((a & 1) + (a & 2)), which can | |
4366 | become a & 3. */ | |
4367 | ||
ac49a949 | 4368 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
951553af RK |
4369 | && (nonzero_bits (XEXP (x, 0), mode) |
4370 | & nonzero_bits (XEXP (x, 1), mode)) == 0) | |
085f1714 RH |
4371 | { |
4372 | /* Try to simplify the expression further. */ | |
bcb34aa3 | 4373 | rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1)); |
6621d78e | 4374 | temp = combine_simplify_rtx (tor, mode, in_dest); |
085f1714 RH |
4375 | |
4376 | /* If we could, great. If not, do not go ahead with the IOR | |
4377 | replacement, since PLUS appears in many special purpose | |
4378 | address arithmetic instructions. */ | |
4379 | if (GET_CODE (temp) != CLOBBER && temp != tor) | |
4380 | return temp; | |
4381 | } | |
230d793d RS |
4382 | break; |
4383 | ||
4384 | case MINUS: | |
0802d516 RK |
4385 | /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done |
4386 | by reversing the comparison code if valid. */ | |
4387 | if (STORE_FLAG_VALUE == 1 | |
4388 | && XEXP (x, 0) == const1_rtx | |
ec8e098d | 4389 | && COMPARISON_P (XEXP (x, 1)) |
14f02e73 | 4390 | && (reversed = reversed_comparison (XEXP (x, 1), mode))) |
9a915772 | 4391 | return reversed; |
5109d49f | 4392 | |
230d793d RS |
4393 | /* (minus <foo> (and <foo> (const_int -pow2))) becomes |
4394 | (and <foo> (const_int pow2-1)) */ | |
4395 | if (GET_CODE (XEXP (x, 1)) == AND | |
4396 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
663522cb | 4397 | && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 |
230d793d | 4398 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) |
8079805d | 4399 | return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0), |
663522cb | 4400 | -INTVAL (XEXP (XEXP (x, 1), 1)) - 1); |
7bef8680 | 4401 | |
16823694 GK |
4402 | /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). |
4403 | */ | |
73a39fc4 | 4404 | if (GET_CODE (XEXP (x, 1)) == MULT |
16823694 GK |
4405 | && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG) |
4406 | { | |
4407 | rtx in1, in2; | |
73a39fc4 | 4408 | |
16823694 GK |
4409 | in1 = XEXP (XEXP (XEXP (x, 1), 0), 0); |
4410 | in2 = XEXP (XEXP (x, 1), 1); | |
bcb34aa3 PB |
4411 | return simplify_gen_binary (PLUS, mode, |
4412 | simplify_gen_binary (MULT, mode, | |
4413 | in1, in2), | |
4414 | XEXP (x, 0)); | |
16823694 GK |
4415 | } |
4416 | ||
73a39fc4 | 4417 | /* Canonicalize (minus (neg A) (mult B C)) to |
e869aa39 | 4418 | (minus (mult (neg B) C) A). */ |
73a39fc4 | 4419 | if (GET_CODE (XEXP (x, 1)) == MULT |
16823694 GK |
4420 | && GET_CODE (XEXP (x, 0)) == NEG) |
4421 | { | |
4422 | rtx in1, in2; | |
73a39fc4 | 4423 | |
16823694 GK |
4424 | in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode); |
4425 | in2 = XEXP (XEXP (x, 1), 1); | |
bcb34aa3 PB |
4426 | return simplify_gen_binary (MINUS, mode, |
4427 | simplify_gen_binary (MULT, mode, | |
4428 | in1, in2), | |
4429 | XEXP (XEXP (x, 0), 0)); | |
16823694 GK |
4430 | } |
4431 | ||
7bef8680 RK |
4432 | /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for |
4433 | integers. */ | |
4434 | if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode)) | |
bcb34aa3 PB |
4435 | return simplify_gen_binary (MINUS, mode, |
4436 | simplify_gen_binary (MINUS, mode, | |
4437 | XEXP (x, 0), | |
4438 | XEXP (XEXP (x, 1), 0)), | |
4439 | XEXP (XEXP (x, 1), 1)); | |
230d793d RS |
4440 | break; |
4441 | ||
4442 | case MULT: | |
4443 | /* If we have (mult (plus A B) C), apply the distributive law and then | |
4444 | the inverse distributive law to see if things simplify. This | |
4445 | occurs mostly in addresses, often when unrolling loops. */ | |
4446 | ||
4447 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
4448 | { | |
bcb34aa3 PB |
4449 | rtx result = distribute_and_simplify_rtx (x, 0); |
4450 | if (result) | |
4451 | return result; | |
230d793d | 4452 | } |
bcb34aa3 | 4453 | |
4ba5f925 JH |
4454 | /* Try simplify a*(b/c) as (a*b)/c. */ |
4455 | if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations | |
4456 | && GET_CODE (XEXP (x, 0)) == DIV) | |
4457 | { | |
4458 | rtx tem = simplify_binary_operation (MULT, mode, | |
4459 | XEXP (XEXP (x, 0), 0), | |
4460 | XEXP (x, 1)); | |
4461 | if (tem) | |
bcb34aa3 | 4462 | return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1)); |
4ba5f925 | 4463 | } |
230d793d RS |
4464 | break; |
4465 | ||
4466 | case UDIV: | |
4467 | /* If this is a divide by a power of two, treat it as a shift if | |
4468 | its first operand is a shift. */ | |
4469 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
4470 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
4471 | && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
4472 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
4473 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
4474 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
4475 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
8079805d | 4476 | return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i); |
230d793d RS |
4477 | break; |
4478 | ||
4479 | case EQ: case NE: | |
4480 | case GT: case GTU: case GE: case GEU: | |
4481 | case LT: case LTU: case LE: case LEU: | |
69bc0a1f | 4482 | case UNEQ: case LTGT: |
23190837 AJ |
4483 | case UNGT: case UNGE: |
4484 | case UNLT: case UNLE: | |
69bc0a1f | 4485 | case UNORDERED: case ORDERED: |
230d793d RS |
4486 | /* If the first operand is a condition code, we can't do anything |
4487 | with it. */ | |
4488 | if (GET_CODE (XEXP (x, 0)) == COMPARE | |
4489 | || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
8beccec8 | 4490 | && ! CC0_P (XEXP (x, 0)))) |
230d793d RS |
4491 | { |
4492 | rtx op0 = XEXP (x, 0); | |
4493 | rtx op1 = XEXP (x, 1); | |
4494 | enum rtx_code new_code; | |
4495 | ||
4496 | if (GET_CODE (op0) == COMPARE) | |
4497 | op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
4498 | ||
4499 | /* Simplify our comparison, if possible. */ | |
4500 | new_code = simplify_comparison (code, &op0, &op1); | |
4501 | ||
230d793d | 4502 | /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X |
951553af | 4503 | if only the low-order bit is possibly nonzero in X (such as when |
5109d49f RK |
4504 | X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to |
4505 | (xor X 1) or (minus 1 X); we use the former. Finally, if X is | |
4506 | known to be either 0 or -1, NE becomes a NEG and EQ becomes | |
4507 | (plus X 1). | |
4508 | ||
4509 | Remove any ZERO_EXTRACT we made when thinking this was a | |
4510 | comparison. It may now be simpler to use, e.g., an AND. If a | |
4511 | ZERO_EXTRACT is indeed appropriate, it will be placed back by | |
4512 | the call to make_compound_operation in the SET case. */ | |
4513 | ||
0802d516 RK |
4514 | if (STORE_FLAG_VALUE == 1 |
4515 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
a191f0ee RH |
4516 | && op1 == const0_rtx |
4517 | && mode == GET_MODE (op0) | |
4518 | && nonzero_bits (op0, mode) == 1) | |
4de249d9 PB |
4519 | return gen_lowpart (mode, |
4520 | expand_compound_operation (op0)); | |
5109d49f | 4521 | |
0802d516 RK |
4522 | else if (STORE_FLAG_VALUE == 1 |
4523 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4524 | && op1 == const0_rtx |
a191f0ee | 4525 | && mode == GET_MODE (op0) |
5109d49f RK |
4526 | && (num_sign_bit_copies (op0, mode) |
4527 | == GET_MODE_BITSIZE (mode))) | |
4528 | { | |
4529 | op0 = expand_compound_operation (op0); | |
f1c6ba8b | 4530 | return simplify_gen_unary (NEG, mode, |
4de249d9 | 4531 | gen_lowpart (mode, op0), |
f1c6ba8b | 4532 | mode); |
5109d49f RK |
4533 | } |
4534 | ||
0802d516 RK |
4535 | else if (STORE_FLAG_VALUE == 1 |
4536 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4537 | && op1 == const0_rtx |
a191f0ee | 4538 | && mode == GET_MODE (op0) |
5109d49f | 4539 | && nonzero_bits (op0, mode) == 1) |
818b11b9 RK |
4540 | { |
4541 | op0 = expand_compound_operation (op0); | |
bcb34aa3 PB |
4542 | return simplify_gen_binary (XOR, mode, |
4543 | gen_lowpart (mode, op0), | |
4544 | const1_rtx); | |
5109d49f | 4545 | } |
818b11b9 | 4546 | |
0802d516 RK |
4547 | else if (STORE_FLAG_VALUE == 1 |
4548 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4549 | && op1 == const0_rtx |
a191f0ee | 4550 | && mode == GET_MODE (op0) |
5109d49f RK |
4551 | && (num_sign_bit_copies (op0, mode) |
4552 | == GET_MODE_BITSIZE (mode))) | |
4553 | { | |
4554 | op0 = expand_compound_operation (op0); | |
4de249d9 | 4555 | return plus_constant (gen_lowpart (mode, op0), 1); |
818b11b9 | 4556 | } |
230d793d | 4557 | |
5109d49f RK |
4558 | /* If STORE_FLAG_VALUE is -1, we have cases similar to |
4559 | those above. */ | |
0802d516 RK |
4560 | if (STORE_FLAG_VALUE == -1 |
4561 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
230d793d | 4562 | && op1 == const0_rtx |
5109d49f RK |
4563 | && (num_sign_bit_copies (op0, mode) |
4564 | == GET_MODE_BITSIZE (mode))) | |
4de249d9 PB |
4565 | return gen_lowpart (mode, |
4566 | expand_compound_operation (op0)); | |
5109d49f | 4567 | |
0802d516 RK |
4568 | else if (STORE_FLAG_VALUE == -1 |
4569 | && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4570 | && op1 == const0_rtx |
a191f0ee | 4571 | && mode == GET_MODE (op0) |
5109d49f RK |
4572 | && nonzero_bits (op0, mode) == 1) |
4573 | { | |
4574 | op0 = expand_compound_operation (op0); | |
f1c6ba8b | 4575 | return simplify_gen_unary (NEG, mode, |
4de249d9 | 4576 | gen_lowpart (mode, op0), |
f1c6ba8b | 4577 | mode); |
5109d49f RK |
4578 | } |
4579 | ||
0802d516 RK |
4580 | else if (STORE_FLAG_VALUE == -1 |
4581 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4582 | && op1 == const0_rtx |
a191f0ee | 4583 | && mode == GET_MODE (op0) |
5109d49f RK |
4584 | && (num_sign_bit_copies (op0, mode) |
4585 | == GET_MODE_BITSIZE (mode))) | |
230d793d | 4586 | { |
818b11b9 | 4587 | op0 = expand_compound_operation (op0); |
f1c6ba8b | 4588 | return simplify_gen_unary (NOT, mode, |
4de249d9 | 4589 | gen_lowpart (mode, op0), |
f1c6ba8b | 4590 | mode); |
5109d49f RK |
4591 | } |
4592 | ||
4593 | /* If X is 0/1, (eq X 0) is X-1. */ | |
0802d516 RK |
4594 | else if (STORE_FLAG_VALUE == -1 |
4595 | && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT | |
5109d49f | 4596 | && op1 == const0_rtx |
a191f0ee | 4597 | && mode == GET_MODE (op0) |
5109d49f RK |
4598 | && nonzero_bits (op0, mode) == 1) |
4599 | { | |
4600 | op0 = expand_compound_operation (op0); | |
4de249d9 | 4601 | return plus_constant (gen_lowpart (mode, op0), -1); |
230d793d | 4602 | } |
230d793d RS |
4603 | |
4604 | /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
951553af RK |
4605 | one bit that might be nonzero, we can convert (ne x 0) to |
4606 | (ashift x c) where C puts the bit in the sign bit. Remove any | |
4607 | AND with STORE_FLAG_VALUE when we are done, since we are only | |
4608 | going to test the sign bit. */ | |
3f508eca | 4609 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
5f4f0e22 | 4610 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 4611 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e869aa39 | 4612 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) |
230d793d RS |
4613 | && op1 == const0_rtx |
4614 | && mode == GET_MODE (op0) | |
5109d49f | 4615 | && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0) |
230d793d | 4616 | { |
818b11b9 RK |
4617 | x = simplify_shift_const (NULL_RTX, ASHIFT, mode, |
4618 | expand_compound_operation (op0), | |
230d793d RS |
4619 | GET_MODE_BITSIZE (mode) - 1 - i); |
4620 | if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) | |
4621 | return XEXP (x, 0); | |
4622 | else | |
4623 | return x; | |
4624 | } | |
4625 | ||
4626 | /* If the code changed, return a whole new comparison. */ | |
4627 | if (new_code != code) | |
f1c6ba8b | 4628 | return gen_rtx_fmt_ee (new_code, mode, op0, op1); |
230d793d | 4629 | |
663522cb | 4630 | /* Otherwise, keep this operation, but maybe change its operands. |
230d793d RS |
4631 | This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ |
4632 | SUBST (XEXP (x, 0), op0); | |
4633 | SUBST (XEXP (x, 1), op1); | |
4634 | } | |
4635 | break; | |
663522cb | 4636 | |
230d793d | 4637 | case IF_THEN_ELSE: |
8079805d | 4638 | return simplify_if_then_else (x); |
9210df58 | 4639 | |
8079805d RK |
4640 | case ZERO_EXTRACT: |
4641 | case SIGN_EXTRACT: | |
4642 | case ZERO_EXTEND: | |
4643 | case SIGN_EXTEND: | |
0f41302f | 4644 | /* If we are processing SET_DEST, we are done. */ |
8079805d RK |
4645 | if (in_dest) |
4646 | return x; | |
d0ab8cd3 | 4647 | |
8079805d | 4648 | return expand_compound_operation (x); |
d0ab8cd3 | 4649 | |
8079805d RK |
4650 | case SET: |
4651 | return simplify_set (x); | |
1a26b032 | 4652 | |
8079805d RK |
4653 | case AND: |
4654 | case IOR: | |
4655 | case XOR: | |
6621d78e | 4656 | return simplify_logical (x); |
d0ab8cd3 | 4657 | |
663522cb | 4658 | case ABS: |
8079805d RK |
4659 | /* (abs (neg <foo>)) -> (abs <foo>) */ |
4660 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
4661 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
1a26b032 | 4662 | |
b472527b JL |
4663 | /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS), |
4664 | do nothing. */ | |
4665 | if (GET_MODE (XEXP (x, 0)) == VOIDmode) | |
4666 | break; | |
f40421ce | 4667 | |
8079805d RK |
4668 | /* If operand is something known to be positive, ignore the ABS. */ |
4669 | if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS | |
4670 | || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) | |
4671 | <= HOST_BITS_PER_WIDE_INT) | |
4672 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
4673 | & ((HOST_WIDE_INT) 1 | |
4674 | << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) | |
4675 | == 0))) | |
4676 | return XEXP (x, 0); | |
1a26b032 | 4677 | |
8079805d RK |
4678 | /* If operand is known to be only -1 or 0, convert ABS to NEG. */ |
4679 | if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode)) | |
f1c6ba8b | 4680 | return gen_rtx_NEG (mode, XEXP (x, 0)); |
1a26b032 | 4681 | |
8079805d | 4682 | break; |
1a26b032 | 4683 | |
8079805d RK |
4684 | case FFS: |
4685 | /* (ffs (*_extend <X>)) = (ffs <X>) */ | |
4686 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
4687 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4688 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4689 | break; | |
1a26b032 | 4690 | |
2928cd7a RH |
4691 | case POPCOUNT: |
4692 | case PARITY: | |
4693 | /* (pop* (zero_extend <X>)) = (pop* <X>) */ | |
4694 | if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
4695 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4696 | break; | |
4697 | ||
8079805d RK |
4698 | case FLOAT: |
4699 | /* (float (sign_extend <X>)) = (float <X>). */ | |
4700 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
4701 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
4702 | break; | |
1a26b032 | 4703 | |
8079805d RK |
4704 | case ASHIFT: |
4705 | case LSHIFTRT: | |
4706 | case ASHIFTRT: | |
4707 | case ROTATE: | |
4708 | case ROTATERT: | |
4709 | /* If this is a shift by a constant amount, simplify it. */ | |
4710 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
663522cb | 4711 | return simplify_shift_const (x, code, mode, XEXP (x, 0), |
8079805d RK |
4712 | INTVAL (XEXP (x, 1))); |
4713 | ||
f8cfc6aa | 4714 | else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1))) |
8079805d | 4715 | SUBST (XEXP (x, 1), |
f1b1186f | 4716 | force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)), |
663522cb | 4717 | ((HOST_WIDE_INT) 1 |
8079805d RK |
4718 | << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x)))) |
4719 | - 1, | |
4720 | NULL_RTX, 0)); | |
8079805d | 4721 | break; |
e9a25f70 | 4722 | |
82be40f7 BS |
4723 | case VEC_SELECT: |
4724 | { | |
4725 | rtx op0 = XEXP (x, 0); | |
4726 | rtx op1 = XEXP (x, 1); | |
4727 | int len; | |
4728 | ||
341c100f | 4729 | gcc_assert (GET_CODE (op1) == PARALLEL); |
82be40f7 BS |
4730 | len = XVECLEN (op1, 0); |
4731 | if (len == 1 | |
4732 | && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT | |
4733 | && GET_CODE (op0) == VEC_CONCAT) | |
4734 | { | |
4735 | int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x)); | |
4736 | ||
4737 | /* Try to find the element in the VEC_CONCAT. */ | |
4738 | for (;;) | |
4739 | { | |
4740 | if (GET_MODE (op0) == GET_MODE (x)) | |
4741 | return op0; | |
4742 | if (GET_CODE (op0) == VEC_CONCAT) | |
4743 | { | |
4744 | HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))); | |
125886c7 | 4745 | if (offset < op0_size) |
82be40f7 BS |
4746 | op0 = XEXP (op0, 0); |
4747 | else | |
4748 | { | |
4749 | offset -= op0_size; | |
4750 | op0 = XEXP (op0, 1); | |
4751 | } | |
4752 | } | |
4753 | else | |
4754 | break; | |
4755 | } | |
4756 | } | |
4757 | } | |
4758 | ||
4759 | break; | |
23190837 | 4760 | |
e9a25f70 JL |
4761 | default: |
4762 | break; | |
8079805d RK |
4763 | } |
4764 | ||
4765 | return x; | |
4766 | } | |
4767 | \f | |
4768 | /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */ | |
5109d49f | 4769 | |
8079805d | 4770 | static rtx |
79a490a9 | 4771 | simplify_if_then_else (rtx x) |
8079805d RK |
4772 | { |
4773 | enum machine_mode mode = GET_MODE (x); | |
4774 | rtx cond = XEXP (x, 0); | |
d6edb99e ZW |
4775 | rtx true_rtx = XEXP (x, 1); |
4776 | rtx false_rtx = XEXP (x, 2); | |
8079805d | 4777 | enum rtx_code true_code = GET_CODE (cond); |
ec8e098d | 4778 | int comparison_p = COMPARISON_P (cond); |
8079805d RK |
4779 | rtx temp; |
4780 | int i; | |
9a915772 JH |
4781 | enum rtx_code false_code; |
4782 | rtx reversed; | |
8079805d | 4783 | |
0f41302f | 4784 | /* Simplify storing of the truth value. */ |
d6edb99e | 4785 | if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx) |
bcb34aa3 PB |
4786 | return simplify_gen_relational (true_code, mode, VOIDmode, |
4787 | XEXP (cond, 0), XEXP (cond, 1)); | |
663522cb | 4788 | |
0f41302f | 4789 | /* Also when the truth value has to be reversed. */ |
9a915772 | 4790 | if (comparison_p |
d6edb99e | 4791 | && true_rtx == const0_rtx && false_rtx == const_true_rtx |
14f02e73 | 4792 | && (reversed = reversed_comparison (cond, mode))) |
9a915772 | 4793 | return reversed; |
8079805d RK |
4794 | |
4795 | /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used | |
4796 | in it is being compared against certain values. Get the true and false | |
4797 | comparisons and see if that says anything about the value of each arm. */ | |
4798 | ||
9a915772 | 4799 | if (comparison_p |
14f02e73 | 4800 | && ((false_code = reversed_comparison_code (cond, NULL)) |
9a915772 | 4801 | != UNKNOWN) |
f8cfc6aa | 4802 | && REG_P (XEXP (cond, 0))) |
8079805d RK |
4803 | { |
4804 | HOST_WIDE_INT nzb; | |
4805 | rtx from = XEXP (cond, 0); | |
8079805d RK |
4806 | rtx true_val = XEXP (cond, 1); |
4807 | rtx false_val = true_val; | |
4808 | int swapped = 0; | |
9210df58 | 4809 | |
8079805d | 4810 | /* If FALSE_CODE is EQ, swap the codes and arms. */ |
5109d49f | 4811 | |
8079805d | 4812 | if (false_code == EQ) |
1a26b032 | 4813 | { |
8079805d | 4814 | swapped = 1, true_code = EQ, false_code = NE; |
d6edb99e | 4815 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
8079805d | 4816 | } |
5109d49f | 4817 | |
8079805d RK |
4818 | /* If we are comparing against zero and the expression being tested has |
4819 | only a single bit that might be nonzero, that is its value when it is | |
4820 | not equal to zero. Similarly if it is known to be -1 or 0. */ | |
4821 | ||
4822 | if (true_code == EQ && true_val == const0_rtx | |
4823 | && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0) | |
4824 | false_code = EQ, false_val = GEN_INT (nzb); | |
4825 | else if (true_code == EQ && true_val == const0_rtx | |
4826 | && (num_sign_bit_copies (from, GET_MODE (from)) | |
4827 | == GET_MODE_BITSIZE (GET_MODE (from)))) | |
4828 | false_code = EQ, false_val = constm1_rtx; | |
4829 | ||
4830 | /* Now simplify an arm if we know the value of the register in the | |
4831 | branch and it is used in the arm. Be careful due to the potential | |
4832 | of locally-shared RTL. */ | |
4833 | ||
d6edb99e ZW |
4834 | if (reg_mentioned_p (from, true_rtx)) |
4835 | true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code, | |
4836 | from, true_val), | |
8079805d | 4837 | pc_rtx, pc_rtx, 0, 0); |
d6edb99e ZW |
4838 | if (reg_mentioned_p (from, false_rtx)) |
4839 | false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code, | |
8079805d RK |
4840 | from, false_val), |
4841 | pc_rtx, pc_rtx, 0, 0); | |
4842 | ||
d6edb99e ZW |
4843 | SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx); |
4844 | SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx); | |
8079805d | 4845 | |
d6edb99e ZW |
4846 | true_rtx = XEXP (x, 1); |
4847 | false_rtx = XEXP (x, 2); | |
4848 | true_code = GET_CODE (cond); | |
8079805d | 4849 | } |
5109d49f | 4850 | |
8079805d RK |
4851 | /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be |
4852 | reversed, do so to avoid needing two sets of patterns for | |
4853 | subtract-and-branch insns. Similarly if we have a constant in the true | |
4854 | arm, the false arm is the same as the first operand of the comparison, or | |
4855 | the false arm is more complicated than the true arm. */ | |
4856 | ||
9a915772 | 4857 | if (comparison_p |
14f02e73 | 4858 | && reversed_comparison_code (cond, NULL) != UNKNOWN |
d6edb99e ZW |
4859 | && (true_rtx == pc_rtx |
4860 | || (CONSTANT_P (true_rtx) | |
4861 | && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx) | |
4862 | || true_rtx == const0_rtx | |
ec8e098d PB |
4863 | || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx)) |
4864 | || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx)) | |
4865 | && !OBJECT_P (false_rtx)) | |
d6edb99e ZW |
4866 | || reg_mentioned_p (true_rtx, false_rtx) |
4867 | || rtx_equal_p (false_rtx, XEXP (cond, 0)))) | |
8079805d | 4868 | { |
9a915772 | 4869 | true_code = reversed_comparison_code (cond, NULL); |
14f02e73 | 4870 | SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond))); |
d6edb99e ZW |
4871 | SUBST (XEXP (x, 1), false_rtx); |
4872 | SUBST (XEXP (x, 2), true_rtx); | |
1a26b032 | 4873 | |
d6edb99e ZW |
4874 | temp = true_rtx, true_rtx = false_rtx, false_rtx = temp; |
4875 | cond = XEXP (x, 0); | |
bb821298 | 4876 | |
0f41302f | 4877 | /* It is possible that the conditional has been simplified out. */ |
bb821298 | 4878 | true_code = GET_CODE (cond); |
ec8e098d | 4879 | comparison_p = COMPARISON_P (cond); |
8079805d | 4880 | } |
abe6e52f | 4881 | |
8079805d | 4882 | /* If the two arms are identical, we don't need the comparison. */ |
1a26b032 | 4883 | |
d6edb99e ZW |
4884 | if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond)) |
4885 | return true_rtx; | |
1a26b032 | 4886 | |
5be669c7 RK |
4887 | /* Convert a == b ? b : a to "a". */ |
4888 | if (true_code == EQ && ! side_effects_p (cond) | |
73e42cf3 | 4889 | && !HONOR_NANS (mode) |
d6edb99e ZW |
4890 | && rtx_equal_p (XEXP (cond, 0), false_rtx) |
4891 | && rtx_equal_p (XEXP (cond, 1), true_rtx)) | |
4892 | return false_rtx; | |
5be669c7 | 4893 | else if (true_code == NE && ! side_effects_p (cond) |
73e42cf3 | 4894 | && !HONOR_NANS (mode) |
d6edb99e ZW |
4895 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
4896 | && rtx_equal_p (XEXP (cond, 1), false_rtx)) | |
4897 | return true_rtx; | |
5be669c7 | 4898 | |
8079805d RK |
4899 | /* Look for cases where we have (abs x) or (neg (abs X)). */ |
4900 | ||
4901 | if (GET_MODE_CLASS (mode) == MODE_INT | |
d6edb99e ZW |
4902 | && GET_CODE (false_rtx) == NEG |
4903 | && rtx_equal_p (true_rtx, XEXP (false_rtx, 0)) | |
8079805d | 4904 | && comparison_p |
d6edb99e ZW |
4905 | && rtx_equal_p (true_rtx, XEXP (cond, 0)) |
4906 | && ! side_effects_p (true_rtx)) | |
8079805d RK |
4907 | switch (true_code) |
4908 | { | |
4909 | case GT: | |
4910 | case GE: | |
f1c6ba8b | 4911 | return simplify_gen_unary (ABS, mode, true_rtx, mode); |
8079805d RK |
4912 | case LT: |
4913 | case LE: | |
f1c6ba8b RK |
4914 | return |
4915 | simplify_gen_unary (NEG, mode, | |
4916 | simplify_gen_unary (ABS, mode, true_rtx, mode), | |
4917 | mode); | |
cf0d9408 KH |
4918 | default: |
4919 | break; | |
8079805d RK |
4920 | } |
4921 | ||
4922 | /* Look for MIN or MAX. */ | |
4923 | ||
de6c5979 | 4924 | if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations) |
8079805d | 4925 | && comparison_p |
d6edb99e ZW |
4926 | && rtx_equal_p (XEXP (cond, 0), true_rtx) |
4927 | && rtx_equal_p (XEXP (cond, 1), false_rtx) | |
8079805d RK |
4928 | && ! side_effects_p (cond)) |
4929 | switch (true_code) | |
4930 | { | |
4931 | case GE: | |
4932 | case GT: | |
bcb34aa3 | 4933 | return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx); |
8079805d RK |
4934 | case LE: |
4935 | case LT: | |
bcb34aa3 | 4936 | return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx); |
8079805d RK |
4937 | case GEU: |
4938 | case GTU: | |
bcb34aa3 | 4939 | return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx); |
8079805d RK |
4940 | case LEU: |
4941 | case LTU: | |
bcb34aa3 | 4942 | return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx); |
e9a25f70 JL |
4943 | default: |
4944 | break; | |
8079805d | 4945 | } |
663522cb | 4946 | |
8079805d RK |
4947 | /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its |
4948 | second operand is zero, this can be done as (OP Z (mult COND C2)) where | |
4949 | C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or | |
4950 | SIGN_EXTEND as long as Z is already extended (so we don't destroy it). | |
4951 | We can do this kind of thing in some cases when STORE_FLAG_VALUE is | |
0802d516 | 4952 | neither 1 or -1, but it isn't worth checking for. */ |
8079805d | 4953 | |
0802d516 | 4954 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
02484af9 EB |
4955 | && comparison_p |
4956 | && GET_MODE_CLASS (mode) == MODE_INT | |
4957 | && ! side_effects_p (x)) | |
8079805d | 4958 | { |
d6edb99e ZW |
4959 | rtx t = make_compound_operation (true_rtx, SET); |
4960 | rtx f = make_compound_operation (false_rtx, SET); | |
8079805d RK |
4961 | rtx cond_op0 = XEXP (cond, 0); |
4962 | rtx cond_op1 = XEXP (cond, 1); | |
f822d252 | 4963 | enum rtx_code op = UNKNOWN, extend_op = UNKNOWN; |
8079805d | 4964 | enum machine_mode m = mode; |
6a651371 | 4965 | rtx z = 0, c1 = NULL_RTX; |
8079805d | 4966 | |
8079805d RK |
4967 | if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS |
4968 | || GET_CODE (t) == IOR || GET_CODE (t) == XOR | |
4969 | || GET_CODE (t) == ASHIFT | |
4970 | || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT) | |
4971 | && rtx_equal_p (XEXP (t, 0), f)) | |
4972 | c1 = XEXP (t, 1), op = GET_CODE (t), z = f; | |
4973 | ||
4974 | /* If an identity-zero op is commutative, check whether there | |
0f41302f | 4975 | would be a match if we swapped the operands. */ |
8079805d RK |
4976 | else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR |
4977 | || GET_CODE (t) == XOR) | |
4978 | && rtx_equal_p (XEXP (t, 1), f)) | |
4979 | c1 = XEXP (t, 0), op = GET_CODE (t), z = f; | |
4980 | else if (GET_CODE (t) == SIGN_EXTEND | |
4981 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
4982 | || GET_CODE (XEXP (t, 0)) == MINUS | |
4983 | || GET_CODE (XEXP (t, 0)) == IOR | |
4984 | || GET_CODE (XEXP (t, 0)) == XOR | |
4985 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
4986 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
4987 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
4988 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
4989 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
4990 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
4991 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
4992 | > (unsigned int) |
4993 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
4994 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0)))))) |
4995 | { | |
4996 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
4997 | extend_op = SIGN_EXTEND; | |
4998 | m = GET_MODE (XEXP (t, 0)); | |
1a26b032 | 4999 | } |
8079805d RK |
5000 | else if (GET_CODE (t) == SIGN_EXTEND |
5001 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5002 | || GET_CODE (XEXP (t, 0)) == IOR | |
5003 | || GET_CODE (XEXP (t, 0)) == XOR) | |
5004 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5005 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5006 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5007 | && (num_sign_bit_copies (f, GET_MODE (f)) | |
26c34780 RS |
5008 | > (unsigned int) |
5009 | (GET_MODE_BITSIZE (mode) | |
8079805d RK |
5010 | - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1)))))) |
5011 | { | |
5012 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5013 | extend_op = SIGN_EXTEND; | |
5014 | m = GET_MODE (XEXP (t, 0)); | |
5015 | } | |
5016 | else if (GET_CODE (t) == ZERO_EXTEND | |
5017 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5018 | || GET_CODE (XEXP (t, 0)) == MINUS | |
5019 | || GET_CODE (XEXP (t, 0)) == IOR | |
5020 | || GET_CODE (XEXP (t, 0)) == XOR | |
5021 | || GET_CODE (XEXP (t, 0)) == ASHIFT | |
5022 | || GET_CODE (XEXP (t, 0)) == LSHIFTRT | |
5023 | || GET_CODE (XEXP (t, 0)) == ASHIFTRT) | |
5024 | && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG | |
5025 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5026 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 0)) | |
5027 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f) | |
5028 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 5029 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0)))) |
8079805d RK |
5030 | == 0)) |
5031 | { | |
5032 | c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0)); | |
5033 | extend_op = ZERO_EXTEND; | |
5034 | m = GET_MODE (XEXP (t, 0)); | |
5035 | } | |
5036 | else if (GET_CODE (t) == ZERO_EXTEND | |
5037 | && (GET_CODE (XEXP (t, 0)) == PLUS | |
5038 | || GET_CODE (XEXP (t, 0)) == IOR | |
5039 | || GET_CODE (XEXP (t, 0)) == XOR) | |
5040 | && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG | |
5041 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5042 | && subreg_lowpart_p (XEXP (XEXP (t, 0), 1)) | |
5043 | && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f) | |
5044 | && ((nonzero_bits (f, GET_MODE (f)) | |
663522cb | 5045 | & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1)))) |
8079805d RK |
5046 | == 0)) |
5047 | { | |
5048 | c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0)); | |
5049 | extend_op = ZERO_EXTEND; | |
5050 | m = GET_MODE (XEXP (t, 0)); | |
5051 | } | |
663522cb | 5052 | |
8079805d RK |
5053 | if (z) |
5054 | { | |
bcb34aa3 PB |
5055 | temp = subst (simplify_gen_relational (true_code, m, VOIDmode, |
5056 | cond_op0, cond_op1), | |
8079805d | 5057 | pc_rtx, pc_rtx, 0, 0); |
bcb34aa3 PB |
5058 | temp = simplify_gen_binary (MULT, m, temp, |
5059 | simplify_gen_binary (MULT, m, c1, | |
5060 | const_true_rtx)); | |
8079805d | 5061 | temp = subst (temp, pc_rtx, pc_rtx, 0, 0); |
bcb34aa3 | 5062 | temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp); |
8079805d | 5063 | |
f822d252 | 5064 | if (extend_op != UNKNOWN) |
f1c6ba8b | 5065 | temp = simplify_gen_unary (extend_op, mode, temp, m); |
8079805d RK |
5066 | |
5067 | return temp; | |
5068 | } | |
5069 | } | |
224eeff2 | 5070 | |
8079805d RK |
5071 | /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or |
5072 | 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the | |
5073 | negation of a single bit, we can convert this operation to a shift. We | |
5074 | can actually do this more generally, but it doesn't seem worth it. */ | |
5075 | ||
5076 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
d6edb99e | 5077 | && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT |
8079805d | 5078 | && ((1 == nonzero_bits (XEXP (cond, 0), mode) |
d6edb99e | 5079 | && (i = exact_log2 (INTVAL (true_rtx))) >= 0) |
8079805d RK |
5080 | || ((num_sign_bit_copies (XEXP (cond, 0), mode) |
5081 | == GET_MODE_BITSIZE (mode)) | |
d6edb99e | 5082 | && (i = exact_log2 (-INTVAL (true_rtx))) >= 0))) |
8079805d RK |
5083 | return |
5084 | simplify_shift_const (NULL_RTX, ASHIFT, mode, | |
4de249d9 | 5085 | gen_lowpart (mode, XEXP (cond, 0)), i); |
230d793d | 5086 | |
83588a9d JH |
5087 | /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ |
5088 | if (true_code == NE && XEXP (cond, 1) == const0_rtx | |
5089 | && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT | |
db33236e | 5090 | && GET_MODE (XEXP (cond, 0)) == mode |
83588a9d JH |
5091 | && (INTVAL (true_rtx) & GET_MODE_MASK (mode)) |
5092 | == nonzero_bits (XEXP (cond, 0), mode) | |
5093 | && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) | |
5094 | return XEXP (cond, 0); | |
5095 | ||
8079805d RK |
5096 | return x; |
5097 | } | |
5098 | \f | |
5099 | /* Simplify X, a SET expression. Return the new expression. */ | |
230d793d | 5100 | |
8079805d | 5101 | static rtx |
79a490a9 | 5102 | simplify_set (rtx x) |
8079805d RK |
5103 | { |
5104 | rtx src = SET_SRC (x); | |
5105 | rtx dest = SET_DEST (x); | |
5106 | enum machine_mode mode | |
5107 | = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest); | |
5108 | rtx other_insn; | |
5109 | rtx *cc_use; | |
5110 | ||
5111 | /* (set (pc) (return)) gets written as (return). */ | |
5112 | if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN) | |
5113 | return src; | |
230d793d | 5114 | |
87e3e0c1 RK |
5115 | /* Now that we know for sure which bits of SRC we are using, see if we can |
5116 | simplify the expression for the object knowing that we only need the | |
5117 | low-order bits. */ | |
5118 | ||
855c3a2e IS |
5119 | if (GET_MODE_CLASS (mode) == MODE_INT |
5120 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
c5c76735 | 5121 | { |
e8dc6d50 | 5122 | src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0); |
c5c76735 JL |
5123 | SUBST (SET_SRC (x), src); |
5124 | } | |
87e3e0c1 | 5125 | |
8079805d RK |
5126 | /* If we are setting CC0 or if the source is a COMPARE, look for the use of |
5127 | the comparison result and try to simplify it unless we already have used | |
5128 | undobuf.other_insn. */ | |
dbf4f1a2 RS |
5129 | if ((GET_MODE_CLASS (mode) == MODE_CC |
5130 | || GET_CODE (src) == COMPARE | |
5131 | || CC0_P (dest)) | |
8079805d RK |
5132 | && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0 |
5133 | && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
ec8e098d | 5134 | && COMPARISON_P (*cc_use) |
c0d3ac4d | 5135 | && rtx_equal_p (XEXP (*cc_use, 0), dest)) |
8079805d RK |
5136 | { |
5137 | enum rtx_code old_code = GET_CODE (*cc_use); | |
5138 | enum rtx_code new_code; | |
f40f4c8e | 5139 | rtx op0, op1, tmp; |
8079805d RK |
5140 | int other_changed = 0; |
5141 | enum machine_mode compare_mode = GET_MODE (dest); | |
5142 | ||
5143 | if (GET_CODE (src) == COMPARE) | |
5144 | op0 = XEXP (src, 0), op1 = XEXP (src, 1); | |
5145 | else | |
8abcb0f7 | 5146 | op0 = src, op1 = CONST0_RTX (GET_MODE (src)); |
230d793d | 5147 | |
c6fb08ad PB |
5148 | tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode, |
5149 | op0, op1); | |
5150 | if (!tmp) | |
5151 | new_code = old_code; | |
5152 | else if (!CONSTANT_P (tmp)) | |
5153 | { | |
5154 | new_code = GET_CODE (tmp); | |
5155 | op0 = XEXP (tmp, 0); | |
5156 | op1 = XEXP (tmp, 1); | |
5157 | } | |
f40f4c8e | 5158 | else |
f40f4c8e RS |
5159 | { |
5160 | rtx pat = PATTERN (other_insn); | |
5161 | undobuf.other_insn = other_insn; | |
5162 | SUBST (*cc_use, tmp); | |
5163 | ||
5164 | /* Attempt to simplify CC user. */ | |
5165 | if (GET_CODE (pat) == SET) | |
5166 | { | |
5167 | rtx new = simplify_rtx (SET_SRC (pat)); | |
5168 | if (new != NULL_RTX) | |
5169 | SUBST (SET_SRC (pat), new); | |
5170 | } | |
5171 | ||
5172 | /* Convert X into a no-op move. */ | |
5173 | SUBST (SET_DEST (x), pc_rtx); | |
5174 | SUBST (SET_SRC (x), pc_rtx); | |
5175 | return x; | |
5176 | } | |
5177 | ||
8079805d | 5178 | /* Simplify our comparison, if possible. */ |
c6fb08ad | 5179 | new_code = simplify_comparison (new_code, &op0, &op1); |
230d793d | 5180 | |
94134f42 | 5181 | #ifdef SELECT_CC_MODE |
8079805d RK |
5182 | /* If this machine has CC modes other than CCmode, check to see if we |
5183 | need to use a different CC mode here. */ | |
c6fb08ad PB |
5184 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
5185 | compare_mode = GET_MODE (op0); | |
5186 | else | |
5187 | compare_mode = SELECT_CC_MODE (new_code, op0, op1); | |
230d793d | 5188 | |
94134f42 | 5189 | #ifndef HAVE_cc0 |
8079805d RK |
5190 | /* If the mode changed, we have to change SET_DEST, the mode in the |
5191 | compare, and the mode in the place SET_DEST is used. If SET_DEST is | |
5192 | a hard register, just build new versions with the proper mode. If it | |
5193 | is a pseudo, we lose unless it is only time we set the pseudo, in | |
5194 | which case we can safely change its mode. */ | |
5195 | if (compare_mode != GET_MODE (dest)) | |
5196 | { | |
770ae6cc | 5197 | unsigned int regno = REGNO (dest); |
38a448ca | 5198 | rtx new_dest = gen_rtx_REG (compare_mode, regno); |
8079805d RK |
5199 | |
5200 | if (regno < FIRST_PSEUDO_REGISTER | |
b1f21e0a | 5201 | || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest))) |
230d793d | 5202 | { |
8079805d RK |
5203 | if (regno >= FIRST_PSEUDO_REGISTER) |
5204 | SUBST (regno_reg_rtx[regno], new_dest); | |
230d793d | 5205 | |
8079805d RK |
5206 | SUBST (SET_DEST (x), new_dest); |
5207 | SUBST (XEXP (*cc_use, 0), new_dest); | |
5208 | other_changed = 1; | |
230d793d | 5209 | |
8079805d | 5210 | dest = new_dest; |
230d793d | 5211 | } |
8079805d | 5212 | } |
94134f42 ZW |
5213 | #endif /* cc0 */ |
5214 | #endif /* SELECT_CC_MODE */ | |
230d793d | 5215 | |
8079805d RK |
5216 | /* If the code changed, we have to build a new comparison in |
5217 | undobuf.other_insn. */ | |
5218 | if (new_code != old_code) | |
5219 | { | |
2051c897 | 5220 | int other_changed_previously = other_changed; |
8079805d RK |
5221 | unsigned HOST_WIDE_INT mask; |
5222 | ||
f1c6ba8b RK |
5223 | SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use), |
5224 | dest, const0_rtx)); | |
2051c897 | 5225 | other_changed = 1; |
8079805d RK |
5226 | |
5227 | /* If the only change we made was to change an EQ into an NE or | |
5228 | vice versa, OP0 has only one bit that might be nonzero, and OP1 | |
5229 | is zero, check if changing the user of the condition code will | |
5230 | produce a valid insn. If it won't, we can keep the original code | |
5231 | in that insn by surrounding our operation with an XOR. */ | |
5232 | ||
5233 | if (((old_code == NE && new_code == EQ) | |
5234 | || (old_code == EQ && new_code == NE)) | |
2051c897 | 5235 | && ! other_changed_previously && op1 == const0_rtx |
8079805d RK |
5236 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT |
5237 | && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0) | |
230d793d | 5238 | { |
8079805d | 5239 | rtx pat = PATTERN (other_insn), note = 0; |
230d793d | 5240 | |
8e2f6e35 | 5241 | if ((recog_for_combine (&pat, other_insn, ¬e) < 0 |
8079805d RK |
5242 | && ! check_asm_operands (pat))) |
5243 | { | |
5244 | PUT_CODE (*cc_use, old_code); | |
2051c897 | 5245 | other_changed = 0; |
230d793d | 5246 | |
bcb34aa3 PB |
5247 | op0 = simplify_gen_binary (XOR, GET_MODE (op0), |
5248 | op0, GEN_INT (mask)); | |
230d793d | 5249 | } |
230d793d | 5250 | } |
8079805d RK |
5251 | } |
5252 | ||
5253 | if (other_changed) | |
5254 | undobuf.other_insn = other_insn; | |
230d793d RS |
5255 | |
5256 | #ifdef HAVE_cc0 | |
8079805d RK |
5257 | /* If we are now comparing against zero, change our source if |
5258 | needed. If we do not use cc0, we always have a COMPARE. */ | |
5259 | if (op1 == const0_rtx && dest == cc0_rtx) | |
5260 | { | |
5261 | SUBST (SET_SRC (x), op0); | |
5262 | src = op0; | |
5263 | } | |
5264 | else | |
230d793d RS |
5265 | #endif |
5266 | ||
8079805d RK |
5267 | /* Otherwise, if we didn't previously have a COMPARE in the |
5268 | correct mode, we need one. */ | |
5269 | if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode) | |
5270 | { | |
f1c6ba8b | 5271 | SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1)); |
8079805d | 5272 | src = SET_SRC (x); |
230d793d RS |
5273 | } |
5274 | else | |
5275 | { | |
8079805d RK |
5276 | /* Otherwise, update the COMPARE if needed. */ |
5277 | SUBST (XEXP (src, 0), op0); | |
5278 | SUBST (XEXP (src, 1), op1); | |
230d793d | 5279 | } |
8079805d RK |
5280 | } |
5281 | else | |
5282 | { | |
5283 | /* Get SET_SRC in a form where we have placed back any | |
5284 | compound expressions. Then do the checks below. */ | |
5285 | src = make_compound_operation (src, SET); | |
5286 | SUBST (SET_SRC (x), src); | |
5287 | } | |
230d793d | 5288 | |
8079805d RK |
5289 | /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation, |
5290 | and X being a REG or (subreg (reg)), we may be able to convert this to | |
663522cb | 5291 | (set (subreg:m2 x) (op)). |
df62f951 | 5292 | |
5c881655 KH |
5293 | We can always do this if M1 is narrower than M2 because that means that |
5294 | we only care about the low bits of the result. | |
df62f951 | 5295 | |
5c881655 KH |
5296 | However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot |
5297 | perform a narrower operation than requested since the high-order bits will | |
5298 | be undefined. On machine where it is defined, this transformation is safe | |
5299 | as long as M1 and M2 have the same number of words. */ | |
663522cb | 5300 | |
8079805d | 5301 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) |
ec8e098d | 5302 | && !OBJECT_P (SUBREG_REG (src)) |
8079805d RK |
5303 | && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1)) |
5304 | / UNITS_PER_WORD) | |
5305 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))) | |
5306 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
5c881655 KH |
5307 | #ifndef WORD_REGISTER_OPERATIONS |
5308 | && (GET_MODE_SIZE (GET_MODE (src)) | |
5309 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
5310 | #endif | |
cff9f8d5 | 5311 | #ifdef CANNOT_CHANGE_MODE_CLASS |
f8cfc6aa | 5312 | && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER |
cff9f8d5 | 5313 | && REG_CANNOT_CHANGE_MODE_P (REGNO (dest), |
73a39fc4 | 5314 | GET_MODE (SUBREG_REG (src)), |
b0c42aed | 5315 | GET_MODE (src))) |
663522cb | 5316 | #endif |
f8cfc6aa | 5317 | && (REG_P (dest) |
8079805d | 5318 | || (GET_CODE (dest) == SUBREG |
f8cfc6aa | 5319 | && REG_P (SUBREG_REG (dest))))) |
8079805d RK |
5320 | { |
5321 | SUBST (SET_DEST (x), | |
4de249d9 | 5322 | gen_lowpart (GET_MODE (SUBREG_REG (src)), |
8079805d RK |
5323 | dest)); |
5324 | SUBST (SET_SRC (x), SUBREG_REG (src)); | |
5325 | ||
5326 | src = SET_SRC (x), dest = SET_DEST (x); | |
5327 | } | |
df62f951 | 5328 | |
8c1d52a3 KH |
5329 | #ifdef HAVE_cc0 |
5330 | /* If we have (set (cc0) (subreg ...)), we try to remove the subreg | |
5331 | in SRC. */ | |
5332 | if (dest == cc0_rtx | |
5333 | && GET_CODE (src) == SUBREG | |
5334 | && subreg_lowpart_p (src) | |
5335 | && (GET_MODE_BITSIZE (GET_MODE (src)) | |
5336 | < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src))))) | |
5337 | { | |
5338 | rtx inner = SUBREG_REG (src); | |
5339 | enum machine_mode inner_mode = GET_MODE (inner); | |
5340 | ||
5341 | /* Here we make sure that we don't have a sign bit on. */ | |
5342 | if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT | |
5343 | && (nonzero_bits (inner, inner_mode) | |
5344 | < ((unsigned HOST_WIDE_INT) 1 | |
ff076520 | 5345 | << (GET_MODE_BITSIZE (GET_MODE (src)) - 1)))) |
8c1d52a3 KH |
5346 | { |
5347 | SUBST (SET_SRC (x), inner); | |
5348 | src = SET_SRC (x); | |
5349 | } | |
5350 | } | |
5351 | #endif | |
5352 | ||
8baf60bb | 5353 | #ifdef LOAD_EXTEND_OP |
8079805d RK |
5354 | /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this |
5355 | would require a paradoxical subreg. Replace the subreg with a | |
0f41302f | 5356 | zero_extend to avoid the reload that would otherwise be required. */ |
8079805d RK |
5357 | |
5358 | if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src) | |
f822d252 | 5359 | && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN |
ddef6bc7 | 5360 | && SUBREG_BYTE (src) == 0 |
8079805d RK |
5361 | && (GET_MODE_SIZE (GET_MODE (src)) |
5362 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))) | |
3c0cb5de | 5363 | && MEM_P (SUBREG_REG (src))) |
8079805d RK |
5364 | { |
5365 | SUBST (SET_SRC (x), | |
2fb00d7f KH |
5366 | gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))), |
5367 | GET_MODE (src), SUBREG_REG (src))); | |
8079805d RK |
5368 | |
5369 | src = SET_SRC (x); | |
5370 | } | |
230d793d RS |
5371 | #endif |
5372 | ||
8079805d RK |
5373 | /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we |
5374 | are comparing an item known to be 0 or -1 against 0, use a logical | |
5375 | operation instead. Check for one of the arms being an IOR of the other | |
5376 | arm with some value. We compute three terms to be IOR'ed together. In | |
5377 | practice, at most two will be nonzero. Then we do the IOR's. */ | |
5378 | ||
5379 | if (GET_CODE (dest) != PC | |
5380 | && GET_CODE (src) == IF_THEN_ELSE | |
36b8d792 | 5381 | && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT |
8079805d RK |
5382 | && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE) |
5383 | && XEXP (XEXP (src, 0), 1) == const0_rtx | |
6dd49058 | 5384 | && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0)) |
ea414472 DE |
5385 | #ifdef HAVE_conditional_move |
5386 | && ! can_conditionally_move_p (GET_MODE (src)) | |
5387 | #endif | |
8079805d RK |
5388 | && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), |
5389 | GET_MODE (XEXP (XEXP (src, 0), 0))) | |
5390 | == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0)))) | |
5391 | && ! side_effects_p (src)) | |
5392 | { | |
d6edb99e | 5393 | rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d | 5394 | ? XEXP (src, 1) : XEXP (src, 2)); |
d6edb99e | 5395 | rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE |
8079805d RK |
5396 | ? XEXP (src, 2) : XEXP (src, 1)); |
5397 | rtx term1 = const0_rtx, term2, term3; | |
5398 | ||
d6edb99e ZW |
5399 | if (GET_CODE (true_rtx) == IOR |
5400 | && rtx_equal_p (XEXP (true_rtx, 0), false_rtx)) | |
e869aa39 | 5401 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx; |
d6edb99e ZW |
5402 | else if (GET_CODE (true_rtx) == IOR |
5403 | && rtx_equal_p (XEXP (true_rtx, 1), false_rtx)) | |
e869aa39 | 5404 | term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx; |
d6edb99e ZW |
5405 | else if (GET_CODE (false_rtx) == IOR |
5406 | && rtx_equal_p (XEXP (false_rtx, 0), true_rtx)) | |
e869aa39 | 5407 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx; |
d6edb99e ZW |
5408 | else if (GET_CODE (false_rtx) == IOR |
5409 | && rtx_equal_p (XEXP (false_rtx, 1), true_rtx)) | |
e869aa39 | 5410 | term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx; |
d6edb99e | 5411 | |
bcb34aa3 PB |
5412 | term2 = simplify_gen_binary (AND, GET_MODE (src), |
5413 | XEXP (XEXP (src, 0), 0), true_rtx); | |
5414 | term3 = simplify_gen_binary (AND, GET_MODE (src), | |
5415 | simplify_gen_unary (NOT, GET_MODE (src), | |
5416 | XEXP (XEXP (src, 0), 0), | |
5417 | GET_MODE (src)), | |
5418 | false_rtx); | |
8079805d RK |
5419 | |
5420 | SUBST (SET_SRC (x), | |
bcb34aa3 PB |
5421 | simplify_gen_binary (IOR, GET_MODE (src), |
5422 | simplify_gen_binary (IOR, GET_MODE (src), | |
5423 | term1, term2), | |
5424 | term3)); | |
8079805d RK |
5425 | |
5426 | src = SET_SRC (x); | |
5427 | } | |
230d793d | 5428 | |
246e00f2 RK |
5429 | /* If either SRC or DEST is a CLOBBER of (const_int 0), make this |
5430 | whole thing fail. */ | |
5431 | if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx) | |
5432 | return src; | |
5433 | else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx) | |
5434 | return dest; | |
5435 | else | |
5436 | /* Convert this into a field assignment operation, if possible. */ | |
5437 | return make_field_assignment (x); | |
8079805d RK |
5438 | } |
5439 | \f | |
5440 | /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified | |
6621d78e | 5441 | result. */ |
8079805d RK |
5442 | |
5443 | static rtx | |
6621d78e | 5444 | simplify_logical (rtx x) |
8079805d RK |
5445 | { |
5446 | enum machine_mode mode = GET_MODE (x); | |
5447 | rtx op0 = XEXP (x, 0); | |
5448 | rtx op1 = XEXP (x, 1); | |
9a915772 | 5449 | rtx reversed; |
8079805d RK |
5450 | |
5451 | switch (GET_CODE (x)) | |
5452 | { | |
230d793d | 5453 | case AND: |
663522cb | 5454 | /* Convert (A ^ B) & A to A & (~B) since the latter is often a single |
8079805d RK |
5455 | insn (and may simplify more). */ |
5456 | if (GET_CODE (op0) == XOR | |
5457 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5458 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5459 | x = simplify_gen_binary (AND, mode, |
5460 | simplify_gen_unary (NOT, mode, | |
5461 | XEXP (op0, 1), mode), | |
5462 | op1); | |
8079805d RK |
5463 | |
5464 | if (GET_CODE (op0) == XOR | |
5465 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5466 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5467 | x = simplify_gen_binary (AND, mode, |
5468 | simplify_gen_unary (NOT, mode, | |
5469 | XEXP (op0, 0), mode), | |
5470 | op1); | |
8079805d | 5471 | |
663522cb | 5472 | /* Similarly for (~(A ^ B)) & A. */ |
8079805d RK |
5473 | if (GET_CODE (op0) == NOT |
5474 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5475 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1) | |
5476 | && ! side_effects_p (op1)) | |
bcb34aa3 | 5477 | x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1); |
8079805d RK |
5478 | |
5479 | if (GET_CODE (op0) == NOT | |
5480 | && GET_CODE (XEXP (op0, 0)) == XOR | |
5481 | && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1) | |
5482 | && ! side_effects_p (op1)) | |
bcb34aa3 | 5483 | x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1); |
8079805d | 5484 | |
2e8f9abf DM |
5485 | /* We can call simplify_and_const_int only if we don't lose |
5486 | any (sign) bits when converting INTVAL (op1) to | |
5487 | "unsigned HOST_WIDE_INT". */ | |
5488 | if (GET_CODE (op1) == CONST_INT | |
5489 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5490 | || INTVAL (op1) > 0)) | |
230d793d | 5491 | { |
8079805d | 5492 | x = simplify_and_const_int (x, mode, op0, INTVAL (op1)); |
230d793d RS |
5493 | |
5494 | /* If we have (ior (and (X C1) C2)) and the next restart would be | |
5495 | the last, simplify this by making C1 as small as possible | |
6621d78e PB |
5496 | and then exit. Only do this if C1 actually changes: for now |
5497 | this only saves memory but, should this transformation be | |
5498 | moved to simplify-rtx.c, we'd risk unbounded recursion there. */ | |
5499 | if (GET_CODE (x) == IOR && GET_CODE (op0) == AND | |
8079805d | 5500 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
6621d78e PB |
5501 | && GET_CODE (op1) == CONST_INT |
5502 | && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0) | |
bcb34aa3 PB |
5503 | return simplify_gen_binary (IOR, mode, |
5504 | simplify_gen_binary | |
5505 | (AND, mode, XEXP (op0, 0), | |
8079805d | 5506 | GEN_INT (INTVAL (XEXP (op0, 1)) |
663522cb | 5507 | & ~INTVAL (op1))), op1); |
230d793d RS |
5508 | |
5509 | if (GET_CODE (x) != AND) | |
8079805d | 5510 | return x; |
0e32506c | 5511 | |
ec8e098d PB |
5512 | op0 = XEXP (x, 0); |
5513 | op1 = XEXP (x, 1); | |
230d793d RS |
5514 | } |
5515 | ||
5516 | /* Convert (A | B) & A to A. */ | |
8079805d RK |
5517 | if (GET_CODE (op0) == IOR |
5518 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5519 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5520 | && ! side_effects_p (XEXP (op0, 0)) | |
5521 | && ! side_effects_p (XEXP (op0, 1))) | |
5522 | return op1; | |
230d793d | 5523 | |
bcb34aa3 PB |
5524 | /* If we have any of (and (ior A B) C) or (and (xor A B) C), |
5525 | apply the distributive law and then the inverse distributive | |
5526 | law to see if things simplify. */ | |
1999435c | 5527 | if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR) |
230d793d | 5528 | { |
bcb34aa3 PB |
5529 | rtx result = distribute_and_simplify_rtx (x, 0); |
5530 | if (result) | |
5531 | return result; | |
230d793d | 5532 | } |
1999435c | 5533 | if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR) |
bcb34aa3 PB |
5534 | { |
5535 | rtx result = distribute_and_simplify_rtx (x, 1); | |
5536 | if (result) | |
5537 | return result; | |
5538 | } | |
230d793d RS |
5539 | break; |
5540 | ||
5541 | case IOR: | |
951553af | 5542 | /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ |
8079805d | 5543 | if (GET_CODE (op1) == CONST_INT |
ac49a949 | 5544 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
663522cb | 5545 | && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0) |
8079805d | 5546 | return op1; |
d0ab8cd3 | 5547 | |
230d793d | 5548 | /* Convert (A & B) | A to A. */ |
8079805d RK |
5549 | if (GET_CODE (op0) == AND |
5550 | && (rtx_equal_p (XEXP (op0, 0), op1) | |
5551 | || rtx_equal_p (XEXP (op0, 1), op1)) | |
5552 | && ! side_effects_p (XEXP (op0, 0)) | |
5553 | && ! side_effects_p (XEXP (op0, 1))) | |
5554 | return op1; | |
230d793d RS |
5555 | |
5556 | /* If we have (ior (and A B) C), apply the distributive law and then | |
5557 | the inverse distributive law to see if things simplify. */ | |
5558 | ||
1999435c PB |
5559 | if (GET_CODE (op0) == AND) |
5560 | { | |
bcb34aa3 PB |
5561 | rtx result = distribute_and_simplify_rtx (x, 0); |
5562 | if (result) | |
5563 | return result; | |
1999435c PB |
5564 | } |
5565 | ||
5566 | if (GET_CODE (op1) == AND) | |
230d793d | 5567 | { |
bcb34aa3 PB |
5568 | rtx result = distribute_and_simplify_rtx (x, 1); |
5569 | if (result) | |
5570 | return result; | |
230d793d RS |
5571 | } |
5572 | ||
5573 | /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the | |
5574 | mode size to (rotate A CX). */ | |
5575 | ||
8079805d RK |
5576 | if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT) |
5577 | || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT)) | |
5578 | && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0)) | |
5579 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5580 | && GET_CODE (XEXP (op1, 1)) == CONST_INT | |
5581 | && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1)) | |
230d793d | 5582 | == GET_MODE_BITSIZE (mode))) |
38a448ca RH |
5583 | return gen_rtx_ROTATE (mode, XEXP (op0, 0), |
5584 | (GET_CODE (op0) == ASHIFT | |
5585 | ? XEXP (op0, 1) : XEXP (op1, 1))); | |
230d793d | 5586 | |
71923da7 RK |
5587 | /* If OP0 is (ashiftrt (plus ...) C), it might actually be |
5588 | a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS | |
5589 | does not affect any of the bits in OP1, it can really be done | |
5590 | as a PLUS and we can associate. We do this by seeing if OP1 | |
5591 | can be safely shifted left C bits. */ | |
5592 | if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT | |
5593 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
5594 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
5595 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5596 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT) | |
5597 | { | |
5598 | int count = INTVAL (XEXP (op0, 1)); | |
5599 | HOST_WIDE_INT mask = INTVAL (op1) << count; | |
5600 | ||
5601 | if (mask >> count == INTVAL (op1) | |
5602 | && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0) | |
5603 | { | |
5604 | SUBST (XEXP (XEXP (op0, 0), 1), | |
5605 | GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask)); | |
5606 | return op0; | |
5607 | } | |
5608 | } | |
230d793d RS |
5609 | break; |
5610 | ||
5611 | case XOR: | |
79e8185c JH |
5612 | /* If we are XORing two things that have no bits in common, |
5613 | convert them into an IOR. This helps to detect rotation encoded | |
5614 | using those methods and possibly other simplifications. */ | |
5615 | ||
5616 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
5617 | && (nonzero_bits (op0, mode) | |
5618 | & nonzero_bits (op1, mode)) == 0) | |
bcb34aa3 | 5619 | return (simplify_gen_binary (IOR, mode, op0, op1)); |
79e8185c | 5620 | |
230d793d RS |
5621 | /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). |
5622 | Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for | |
5623 | (NOT y). */ | |
5624 | { | |
5625 | int num_negated = 0; | |
230d793d | 5626 | |
8079805d RK |
5627 | if (GET_CODE (op0) == NOT) |
5628 | num_negated++, op0 = XEXP (op0, 0); | |
5629 | if (GET_CODE (op1) == NOT) | |
5630 | num_negated++, op1 = XEXP (op1, 0); | |
230d793d RS |
5631 | |
5632 | if (num_negated == 2) | |
5633 | { | |
8079805d RK |
5634 | SUBST (XEXP (x, 0), op0); |
5635 | SUBST (XEXP (x, 1), op1); | |
230d793d RS |
5636 | } |
5637 | else if (num_negated == 1) | |
f1c6ba8b | 5638 | return |
bcb34aa3 PB |
5639 | simplify_gen_unary (NOT, mode, |
5640 | simplify_gen_binary (XOR, mode, op0, op1), | |
f1c6ba8b | 5641 | mode); |
230d793d RS |
5642 | } |
5643 | ||
5644 | /* Convert (xor (and A B) B) to (and (not A) B). The latter may | |
5645 | correspond to a machine insn or result in further simplifications | |
5646 | if B is a constant. */ | |
5647 | ||
8079805d RK |
5648 | if (GET_CODE (op0) == AND |
5649 | && rtx_equal_p (XEXP (op0, 1), op1) | |
5650 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5651 | return simplify_gen_binary (AND, mode, |
5652 | simplify_gen_unary (NOT, mode, | |
5653 | XEXP (op0, 0), mode), | |
5654 | op1); | |
230d793d | 5655 | |
8079805d RK |
5656 | else if (GET_CODE (op0) == AND |
5657 | && rtx_equal_p (XEXP (op0, 0), op1) | |
5658 | && ! side_effects_p (op1)) | |
bcb34aa3 PB |
5659 | return simplify_gen_binary (AND, mode, |
5660 | simplify_gen_unary (NOT, mode, | |
5661 | XEXP (op0, 1), mode), | |
5662 | op1); | |
230d793d | 5663 | |
230d793d | 5664 | /* (xor (comparison foo bar) (const_int 1)) can become the reversed |
0802d516 RK |
5665 | comparison if STORE_FLAG_VALUE is 1. */ |
5666 | if (STORE_FLAG_VALUE == 1 | |
5667 | && op1 == const1_rtx | |
ec8e098d | 5668 | && COMPARISON_P (op0) |
14f02e73 | 5669 | && (reversed = reversed_comparison (op0, mode))) |
9a915772 | 5670 | return reversed; |
500c518b RK |
5671 | |
5672 | /* (lshiftrt foo C) where C is the number of bits in FOO minus 1 | |
5673 | is (lt foo (const_int 0)), so we can perform the above | |
0802d516 | 5674 | simplification if STORE_FLAG_VALUE is 1. */ |
500c518b | 5675 | |
0802d516 RK |
5676 | if (STORE_FLAG_VALUE == 1 |
5677 | && op1 == const1_rtx | |
8079805d RK |
5678 | && GET_CODE (op0) == LSHIFTRT |
5679 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5680 | && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
f1c6ba8b | 5681 | return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx); |
230d793d RS |
5682 | |
5683 | /* (xor (comparison foo bar) (const_int sign-bit)) | |
5684 | when STORE_FLAG_VALUE is the sign bit. */ | |
5f4f0e22 | 5685 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
0802d516 | 5686 | && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode)) |
e51712db | 5687 | == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)) |
8079805d | 5688 | && op1 == const_true_rtx |
ec8e098d | 5689 | && COMPARISON_P (op0) |
14f02e73 | 5690 | && (reversed = reversed_comparison (op0, mode))) |
9a915772 | 5691 | return reversed; |
0918eca0 | 5692 | |
230d793d | 5693 | break; |
e9a25f70 JL |
5694 | |
5695 | default: | |
341c100f | 5696 | gcc_unreachable (); |
230d793d RS |
5697 | } |
5698 | ||
5699 | return x; | |
5700 | } | |
5701 | \f | |
5702 | /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
5703 | operations" because they can be replaced with two more basic operations. | |
5704 | ZERO_EXTEND is also considered "compound" because it can be replaced with | |
5705 | an AND operation, which is simpler, though only one operation. | |
5706 | ||
5707 | The function expand_compound_operation is called with an rtx expression | |
663522cb | 5708 | and will convert it to the appropriate shifts and AND operations, |
230d793d RS |
5709 | simplifying at each stage. |
5710 | ||
5711 | The function make_compound_operation is called to convert an expression | |
5712 | consisting of shifts and ANDs into the equivalent compound expression. | |
5713 | It is the inverse of this function, loosely speaking. */ | |
5714 | ||
5715 | static rtx | |
79a490a9 | 5716 | expand_compound_operation (rtx x) |
230d793d | 5717 | { |
770ae6cc | 5718 | unsigned HOST_WIDE_INT pos = 0, len; |
230d793d | 5719 | int unsignedp = 0; |
770ae6cc | 5720 | unsigned int modewidth; |
230d793d RS |
5721 | rtx tem; |
5722 | ||
5723 | switch (GET_CODE (x)) | |
5724 | { | |
5725 | case ZERO_EXTEND: | |
5726 | unsignedp = 1; | |
5727 | case SIGN_EXTEND: | |
75473182 RS |
5728 | /* We can't necessarily use a const_int for a multiword mode; |
5729 | it depends on implicitly extending the value. | |
5730 | Since we don't know the right way to extend it, | |
5731 | we can't tell whether the implicit way is right. | |
5732 | ||
5733 | Even for a mode that is no wider than a const_int, | |
5734 | we can't win, because we need to sign extend one of its bits through | |
5735 | the rest of it, and we don't know which bit. */ | |
230d793d | 5736 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
75473182 | 5737 | return x; |
230d793d | 5738 | |
8079805d RK |
5739 | /* Return if (subreg:MODE FROM 0) is not a safe replacement for |
5740 | (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM | |
5741 | because (SUBREG (MEM...)) is guaranteed to cause the MEM to be | |
5742 | reloaded. If not for that, MEM's would very rarely be safe. | |
5743 | ||
5744 | Reject MODEs bigger than a word, because we might not be able | |
5745 | to reference a two-register group starting with an arbitrary register | |
5746 | (and currently gen_lowpart might crash for a SUBREG). */ | |
663522cb | 5747 | |
8079805d | 5748 | if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD) |
230d793d RS |
5749 | return x; |
5750 | ||
71012d97 GK |
5751 | /* Reject MODEs that aren't scalar integers because turning vector |
5752 | or complex modes into shifts causes problems. */ | |
5753 | ||
5754 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5755 | return x; | |
5756 | ||
230d793d RS |
5757 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); |
5758 | /* If the inner object has VOIDmode (the only way this can happen | |
e0a2f705 | 5759 | is if it is an ASM_OPERANDS), we can't do anything since we don't |
230d793d RS |
5760 | know how much masking to do. */ |
5761 | if (len == 0) | |
5762 | return x; | |
5763 | ||
5764 | break; | |
5765 | ||
5766 | case ZERO_EXTRACT: | |
5767 | unsignedp = 1; | |
46d096a3 SB |
5768 | |
5769 | /* ... fall through ... */ | |
5770 | ||
230d793d RS |
5771 | case SIGN_EXTRACT: |
5772 | /* If the operand is a CLOBBER, just return it. */ | |
5773 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
5774 | return XEXP (x, 0); | |
5775 | ||
5776 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5777 | || GET_CODE (XEXP (x, 2)) != CONST_INT | |
5778 | || GET_MODE (XEXP (x, 0)) == VOIDmode) | |
5779 | return x; | |
5780 | ||
71012d97 GK |
5781 | /* Reject MODEs that aren't scalar integers because turning vector |
5782 | or complex modes into shifts causes problems. */ | |
5783 | ||
5784 | if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0)))) | |
5785 | return x; | |
5786 | ||
230d793d RS |
5787 | len = INTVAL (XEXP (x, 1)); |
5788 | pos = INTVAL (XEXP (x, 2)); | |
5789 | ||
5790 | /* If this goes outside the object being extracted, replace the object | |
5791 | with a (use (mem ...)) construct that only combine understands | |
5792 | and is used only for this purpose. */ | |
5793 | if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
38a448ca | 5794 | SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0))); |
230d793d | 5795 | |
f76b9db2 ILT |
5796 | if (BITS_BIG_ENDIAN) |
5797 | pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; | |
5798 | ||
230d793d RS |
5799 | break; |
5800 | ||
5801 | default: | |
5802 | return x; | |
5803 | } | |
0f808b6f JH |
5804 | /* Convert sign extension to zero extension, if we know that the high |
5805 | bit is not set, as this is easier to optimize. It will be converted | |
5806 | back to cheaper alternative in make_extraction. */ | |
5807 | if (GET_CODE (x) == SIGN_EXTEND | |
5808 | && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5809 | && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
663522cb | 5810 | & ~(((unsigned HOST_WIDE_INT) |
0f808b6f JH |
5811 | GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) |
5812 | >> 1)) | |
5813 | == 0))) | |
5814 | { | |
5815 | rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0)); | |
3dcd7d45 EC |
5816 | rtx temp2 = expand_compound_operation (temp); |
5817 | ||
5818 | /* Make sure this is a profitable operation. */ | |
5819 | if (rtx_cost (x, SET) > rtx_cost (temp2, SET)) | |
5820 | return temp2; | |
5821 | else if (rtx_cost (x, SET) > rtx_cost (temp, SET)) | |
5822 | return temp; | |
5823 | else | |
5824 | return x; | |
0f808b6f | 5825 | } |
230d793d | 5826 | |
0f13a422 ILT |
5827 | /* We can optimize some special cases of ZERO_EXTEND. */ |
5828 | if (GET_CODE (x) == ZERO_EXTEND) | |
5829 | { | |
5830 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we | |
5831 | know that the last value didn't have any inappropriate bits | |
5832 | set. */ | |
5833 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5834 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
5835 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5836 | && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x)) | |
663522cb | 5837 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5838 | return XEXP (XEXP (x, 0), 0); |
5839 | ||
5840 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
5841 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
5842 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
5843 | && subreg_lowpart_p (XEXP (x, 0)) | |
5844 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT | |
5845 | && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x)) | |
663522cb | 5846 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5847 | return SUBREG_REG (XEXP (x, 0)); |
5848 | ||
5849 | /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo | |
5850 | is a comparison and STORE_FLAG_VALUE permits. This is like | |
5851 | the first case, but it works even when GET_MODE (x) is larger | |
5852 | than HOST_WIDE_INT. */ | |
5853 | if (GET_CODE (XEXP (x, 0)) == TRUNCATE | |
5854 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x) | |
ec8e098d | 5855 | && COMPARISON_P (XEXP (XEXP (x, 0), 0)) |
0f13a422 ILT |
5856 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
5857 | <= HOST_BITS_PER_WIDE_INT) | |
23190837 | 5858 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE |
663522cb | 5859 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5860 | return XEXP (XEXP (x, 0), 0); |
5861 | ||
5862 | /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */ | |
5863 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
5864 | && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x) | |
5865 | && subreg_lowpart_p (XEXP (x, 0)) | |
ec8e098d | 5866 | && COMPARISON_P (SUBREG_REG (XEXP (x, 0))) |
0f13a422 ILT |
5867 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) |
5868 | <= HOST_BITS_PER_WIDE_INT) | |
5869 | && ((HOST_WIDE_INT) STORE_FLAG_VALUE | |
663522cb | 5870 | & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
0f13a422 ILT |
5871 | return SUBREG_REG (XEXP (x, 0)); |
5872 | ||
0f13a422 ILT |
5873 | } |
5874 | ||
230d793d RS |
5875 | /* If we reach here, we want to return a pair of shifts. The inner |
5876 | shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
5877 | shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
5878 | logical depending on the value of UNSIGNEDP. | |
5879 | ||
5880 | If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
5881 | converted into an AND of a shift. | |
5882 | ||
5883 | We must check for the case where the left shift would have a negative | |
5884 | count. This can happen in a case like (x >> 31) & 255 on machines | |
5885 | that can't shift by a constant. On those machines, we would first | |
663522cb | 5886 | combine the shift with the AND to produce a variable-position |
230d793d RS |
5887 | extraction. Then the constant of 31 would be substituted in to produce |
5888 | a such a position. */ | |
5889 | ||
5890 | modewidth = GET_MODE_BITSIZE (GET_MODE (x)); | |
770ae6cc | 5891 | if (modewidth + len >= pos) |
5f4f0e22 | 5892 | tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT, |
230d793d | 5893 | GET_MODE (x), |
5f4f0e22 CH |
5894 | simplify_shift_const (NULL_RTX, ASHIFT, |
5895 | GET_MODE (x), | |
230d793d RS |
5896 | XEXP (x, 0), |
5897 | modewidth - pos - len), | |
5898 | modewidth - len); | |
5899 | ||
5f4f0e22 CH |
5900 | else if (unsignedp && len < HOST_BITS_PER_WIDE_INT) |
5901 | tem = simplify_and_const_int (NULL_RTX, GET_MODE (x), | |
5902 | simplify_shift_const (NULL_RTX, LSHIFTRT, | |
230d793d RS |
5903 | GET_MODE (x), |
5904 | XEXP (x, 0), pos), | |
5f4f0e22 | 5905 | ((HOST_WIDE_INT) 1 << len) - 1); |
230d793d RS |
5906 | else |
5907 | /* Any other cases we can't handle. */ | |
5908 | return x; | |
230d793d RS |
5909 | |
5910 | /* If we couldn't do this for some reason, return the original | |
5911 | expression. */ | |
5912 | if (GET_CODE (tem) == CLOBBER) | |
5913 | return x; | |
5914 | ||
5915 | return tem; | |
5916 | } | |
5917 | \f | |
5918 | /* X is a SET which contains an assignment of one object into | |
5919 | a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
5920 | or certain SUBREGS). If possible, convert it into a series of | |
5921 | logical operations. | |
5922 | ||
5923 | We half-heartedly support variable positions, but do not at all | |
5924 | support variable lengths. */ | |
5925 | ||
5926 | static rtx | |
79a490a9 | 5927 | expand_field_assignment (rtx x) |
230d793d RS |
5928 | { |
5929 | rtx inner; | |
0f41302f | 5930 | rtx pos; /* Always counts from low bit. */ |
230d793d | 5931 | int len; |
bcb34aa3 | 5932 | rtx mask, cleared, masked; |
230d793d RS |
5933 | enum machine_mode compute_mode; |
5934 | ||
5935 | /* Loop until we find something we can't simplify. */ | |
5936 | while (1) | |
5937 | { | |
5938 | if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
5939 | && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
5940 | { | |
5941 | inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
5942 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); | |
47073a38 | 5943 | pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0))); |
230d793d RS |
5944 | } |
5945 | else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
5946 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) | |
5947 | { | |
5948 | inner = XEXP (SET_DEST (x), 0); | |
5949 | len = INTVAL (XEXP (SET_DEST (x), 1)); | |
5950 | pos = XEXP (SET_DEST (x), 2); | |
5951 | ||
5952 | /* If the position is constant and spans the width of INNER, | |
5953 | surround INNER with a USE to indicate this. */ | |
5954 | if (GET_CODE (pos) == CONST_INT | |
5955 | && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) | |
38a448ca | 5956 | inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner); |
230d793d | 5957 | |
f76b9db2 ILT |
5958 | if (BITS_BIG_ENDIAN) |
5959 | { | |
5960 | if (GET_CODE (pos) == CONST_INT) | |
5961 | pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len | |
5962 | - INTVAL (pos)); | |
5963 | else if (GET_CODE (pos) == MINUS | |
5964 | && GET_CODE (XEXP (pos, 1)) == CONST_INT | |
5965 | && (INTVAL (XEXP (pos, 1)) | |
5966 | == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) | |
5967 | /* If position is ADJUST - X, new position is X. */ | |
5968 | pos = XEXP (pos, 0); | |
5969 | else | |
bcb34aa3 PB |
5970 | pos = simplify_gen_binary (MINUS, GET_MODE (pos), |
5971 | GEN_INT (GET_MODE_BITSIZE ( | |
5972 | GET_MODE (inner)) | |
5973 | - len), | |
5974 | pos); | |
f76b9db2 | 5975 | } |
230d793d RS |
5976 | } |
5977 | ||
5978 | /* A SUBREG between two modes that occupy the same numbers of words | |
5979 | can be done by moving the SUBREG to the source. */ | |
5980 | else if (GET_CODE (SET_DEST (x)) == SUBREG | |
b1e9c8a9 AO |
5981 | /* We need SUBREGs to compute nonzero_bits properly. */ |
5982 | && nonzero_sign_valid | |
230d793d RS |
5983 | && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) |
5984 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
5985 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
5986 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
5987 | { | |
38a448ca | 5988 | x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)), |
4de249d9 | 5989 | gen_lowpart |
c5c76735 JL |
5990 | (GET_MODE (SUBREG_REG (SET_DEST (x))), |
5991 | SET_SRC (x))); | |
230d793d RS |
5992 | continue; |
5993 | } | |
5994 | else | |
5995 | break; | |
5996 | ||
5997 | while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
5998 | inner = SUBREG_REG (inner); | |
5999 | ||
6000 | compute_mode = GET_MODE (inner); | |
6001 | ||
71012d97 GK |
6002 | /* Don't attempt bitwise arithmetic on non scalar integer modes. */ |
6003 | if (! SCALAR_INT_MODE_P (compute_mode)) | |
861556b4 RH |
6004 | { |
6005 | enum machine_mode imode; | |
6006 | ||
71012d97 | 6007 | /* Don't do anything for vector or complex integral types. */ |
861556b4 RH |
6008 | if (! FLOAT_MODE_P (compute_mode)) |
6009 | break; | |
6010 | ||
6011 | /* Try to find an integral mode to pun with. */ | |
6012 | imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0); | |
6013 | if (imode == BLKmode) | |
6014 | break; | |
6015 | ||
6016 | compute_mode = imode; | |
4de249d9 | 6017 | inner = gen_lowpart (imode, inner); |
861556b4 RH |
6018 | } |
6019 | ||
230d793d | 6020 | /* Compute a mask of LEN bits, if we can do this on the host machine. */ |
bcb34aa3 | 6021 | if (len >= HOST_BITS_PER_WIDE_INT) |
230d793d RS |
6022 | break; |
6023 | ||
6024 | /* Now compute the equivalent expression. Make a copy of INNER | |
6025 | for the SET_DEST in case it is a MEM into which we will substitute; | |
6026 | we don't want shared RTL in that case. */ | |
bcb34aa3 PB |
6027 | mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1); |
6028 | cleared = simplify_gen_binary (AND, compute_mode, | |
6029 | simplify_gen_unary (NOT, compute_mode, | |
6030 | simplify_gen_binary (ASHIFT, | |
6031 | compute_mode, | |
6032 | mask, pos), | |
6033 | compute_mode), | |
6034 | inner); | |
6035 | masked = simplify_gen_binary (ASHIFT, compute_mode, | |
6036 | simplify_gen_binary ( | |
6037 | AND, compute_mode, | |
6038 | gen_lowpart (compute_mode, SET_SRC (x)), | |
6039 | mask), | |
6040 | pos); | |
6041 | ||
6042 | x = gen_rtx_SET (VOIDmode, copy_rtx (inner), | |
6043 | simplify_gen_binary (IOR, compute_mode, | |
6044 | cleared, masked)); | |
230d793d RS |
6045 | } |
6046 | ||
6047 | return x; | |
6048 | } | |
6049 | \f | |
8999a12e RK |
6050 | /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero, |
6051 | it is an RTX that represents a variable starting position; otherwise, | |
6052 | POS is the (constant) starting bit position (counted from the LSB). | |
230d793d RS |
6053 | |
6054 | INNER may be a USE. This will occur when we started with a bitfield | |
6055 | that went outside the boundary of the object in memory, which is | |
6056 | allowed on most machines. To isolate this case, we produce a USE | |
6057 | whose mode is wide enough and surround the MEM with it. The only | |
6058 | code that understands the USE is this routine. If it is not removed, | |
6059 | it will cause the resulting insn not to match. | |
6060 | ||
da7d8304 | 6061 | UNSIGNEDP is nonzero for an unsigned reference and zero for a |
230d793d RS |
6062 | signed reference. |
6063 | ||
da7d8304 KH |
6064 | IN_DEST is nonzero if this is a reference in the destination of a |
6065 | SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero, | |
230d793d RS |
6066 | a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will |
6067 | be used. | |
6068 | ||
da7d8304 | 6069 | IN_COMPARE is nonzero if we are in a COMPARE. This means that a |
230d793d RS |
6070 | ZERO_EXTRACT should be built even for bits starting at bit 0. |
6071 | ||
76184def DE |
6072 | MODE is the desired mode of the result (if IN_DEST == 0). |
6073 | ||
6074 | The result is an RTX for the extraction or NULL_RTX if the target | |
6075 | can't handle it. */ | |
230d793d RS |
6076 | |
6077 | static rtx | |
79a490a9 AJ |
6078 | make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos, |
6079 | rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp, | |
6080 | int in_dest, int in_compare) | |
230d793d | 6081 | { |
94b4b17a RS |
6082 | /* This mode describes the size of the storage area |
6083 | to fetch the overall value from. Within that, we | |
6084 | ignore the POS lowest bits, etc. */ | |
230d793d RS |
6085 | enum machine_mode is_mode = GET_MODE (inner); |
6086 | enum machine_mode inner_mode; | |
d7cd794f RK |
6087 | enum machine_mode wanted_inner_mode = byte_mode; |
6088 | enum machine_mode wanted_inner_reg_mode = word_mode; | |
230d793d RS |
6089 | enum machine_mode pos_mode = word_mode; |
6090 | enum machine_mode extraction_mode = word_mode; | |
6091 | enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
6092 | int spans_byte = 0; | |
6093 | rtx new = 0; | |
8999a12e | 6094 | rtx orig_pos_rtx = pos_rtx; |
770ae6cc | 6095 | HOST_WIDE_INT orig_pos; |
230d793d RS |
6096 | |
6097 | /* Get some information about INNER and get the innermost object. */ | |
6098 | if (GET_CODE (inner) == USE) | |
94b4b17a | 6099 | /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */ |
230d793d RS |
6100 | /* We don't need to adjust the position because we set up the USE |
6101 | to pretend that it was a full-word object. */ | |
6102 | spans_byte = 1, inner = XEXP (inner, 0); | |
6103 | else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
94b4b17a RS |
6104 | { |
6105 | /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...), | |
6106 | consider just the QI as the memory to extract from. | |
6107 | The subreg adds or removes high bits; its mode is | |
6108 | irrelevant to the meaning of this extraction, | |
6109 | since POS and LEN count from the lsb. */ | |
3c0cb5de | 6110 | if (MEM_P (SUBREG_REG (inner))) |
94b4b17a RS |
6111 | is_mode = GET_MODE (SUBREG_REG (inner)); |
6112 | inner = SUBREG_REG (inner); | |
6113 | } | |
988ef418 RS |
6114 | else if (GET_CODE (inner) == ASHIFT |
6115 | && GET_CODE (XEXP (inner, 1)) == CONST_INT | |
6116 | && pos_rtx == 0 && pos == 0 | |
3129af4c | 6117 | && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1))) |
988ef418 RS |
6118 | { |
6119 | /* We're extracting the least significant bits of an rtx | |
6120 | (ashift X (const_int C)), where LEN > C. Extract the | |
6121 | least significant (LEN - C) bits of X, giving an rtx | |
6122 | whose mode is MODE, then shift it left C times. */ | |
6123 | new = make_extraction (mode, XEXP (inner, 0), | |
6124 | 0, 0, len - INTVAL (XEXP (inner, 1)), | |
6125 | unsignedp, in_dest, in_compare); | |
6126 | if (new != 0) | |
6127 | return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1)); | |
6128 | } | |
230d793d RS |
6129 | |
6130 | inner_mode = GET_MODE (inner); | |
6131 | ||
6132 | if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) | |
8999a12e | 6133 | pos = INTVAL (pos_rtx), pos_rtx = 0; |
230d793d RS |
6134 | |
6135 | /* See if this can be done without an extraction. We never can if the | |
6136 | width of the field is not the same as that of some integer mode. For | |
6137 | registers, we can only avoid the extraction if the position is at the | |
6138 | low-order bit and this is either not in the destination or we have the | |
6139 | appropriate STRICT_LOW_PART operation available. | |
6140 | ||
6141 | For MEM, we can avoid an extract if the field starts on an appropriate | |
6142 | boundary and we can change the mode of the memory reference. However, | |
6143 | we cannot directly access the MEM if we have a USE and the underlying | |
6144 | MEM is not TMODE. This combination means that MEM was being used in a | |
6145 | context where bits outside its mode were being referenced; that is only | |
6146 | valid in bit-field insns. */ | |
6147 | ||
6148 | if (tmode != BLKmode | |
6149 | && ! (spans_byte && inner_mode != tmode) | |
4d9cfc7b | 6150 | && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0 |
3c0cb5de | 6151 | && !MEM_P (inner) |
230d793d | 6152 | && (! in_dest |
f8cfc6aa | 6153 | || (REG_P (inner) |
ef89d648 | 6154 | && have_insn_for (STRICT_LOW_PART, tmode)))) |
3c0cb5de | 6155 | || (MEM_P (inner) && pos_rtx == 0 |
dfbe1b2f RK |
6156 | && (pos |
6157 | % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
6158 | : BITS_PER_UNIT)) == 0 | |
230d793d RS |
6159 | /* We can't do this if we are widening INNER_MODE (it |
6160 | may not be aligned, for one thing). */ | |
6161 | && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) | |
6162 | && (inner_mode == tmode | |
6163 | || (! mode_dependent_address_p (XEXP (inner, 0)) | |
6164 | && ! MEM_VOLATILE_P (inner)))))) | |
6165 | { | |
230d793d RS |
6166 | /* If INNER is a MEM, make a new MEM that encompasses just the desired |
6167 | field. If the original and current mode are the same, we need not | |
663522cb | 6168 | adjust the offset. Otherwise, we do if bytes big endian. |
230d793d | 6169 | |
4d9cfc7b RK |
6170 | If INNER is not a MEM, get a piece consisting of just the field |
6171 | of interest (in this case POS % BITS_PER_WORD must be 0). */ | |
230d793d | 6172 | |
3c0cb5de | 6173 | if (MEM_P (inner)) |
230d793d | 6174 | { |
f1ec5147 RK |
6175 | HOST_WIDE_INT offset; |
6176 | ||
94b4b17a RS |
6177 | /* POS counts from lsb, but make OFFSET count in memory order. */ |
6178 | if (BYTES_BIG_ENDIAN) | |
6179 | offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT; | |
6180 | else | |
6181 | offset = pos / BITS_PER_UNIT; | |
230d793d | 6182 | |
f1ec5147 | 6183 | new = adjust_address_nv (inner, tmode, offset); |
230d793d | 6184 | } |
f8cfc6aa | 6185 | else if (REG_P (inner)) |
c0d3ac4d | 6186 | { |
c0d3ac4d | 6187 | if (tmode != inner_mode) |
ddef6bc7 | 6188 | { |
4de249d9 | 6189 | /* We can't call gen_lowpart in a DEST since we |
91f8389c EB |
6190 | always want a SUBREG (see below) and it would sometimes |
6191 | return a new hard register. */ | |
6192 | if (pos || in_dest) | |
54c2fc72 | 6193 | { |
54c2fc72 JW |
6194 | HOST_WIDE_INT final_word = pos / BITS_PER_WORD; |
6195 | ||
6196 | if (WORDS_BIG_ENDIAN | |
6197 | && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD) | |
6198 | final_word = ((GET_MODE_SIZE (inner_mode) | |
6199 | - GET_MODE_SIZE (tmode)) | |
6200 | / UNITS_PER_WORD) - final_word; | |
6201 | ||
6202 | final_word *= UNITS_PER_WORD; | |
6203 | if (BYTES_BIG_ENDIAN && | |
6204 | GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode)) | |
6205 | final_word += (GET_MODE_SIZE (inner_mode) | |
6206 | - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD; | |
6207 | ||
6208 | /* Avoid creating invalid subregs, for example when | |
6209 | simplifying (x>>32)&255. */ | |
6210 | if (final_word >= GET_MODE_SIZE (inner_mode)) | |
6211 | return NULL_RTX; | |
6212 | ||
6213 | new = gen_rtx_SUBREG (tmode, inner, final_word); | |
6214 | } | |
6215 | else | |
4de249d9 | 6216 | new = gen_lowpart (tmode, inner); |
ddef6bc7 | 6217 | } |
23190837 AJ |
6218 | else |
6219 | new = inner; | |
6220 | } | |
230d793d | 6221 | else |
6139ff20 RK |
6222 | new = force_to_mode (inner, tmode, |
6223 | len >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6224 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 6225 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 6226 | NULL_RTX, 0); |
230d793d | 6227 | |
663522cb | 6228 | /* If this extraction is going into the destination of a SET, |
230d793d RS |
6229 | make a STRICT_LOW_PART unless we made a MEM. */ |
6230 | ||
6231 | if (in_dest) | |
3c0cb5de | 6232 | return (MEM_P (new) ? new |
77fa0940 | 6233 | : (GET_CODE (new) != SUBREG |
38a448ca | 6234 | ? gen_rtx_CLOBBER (tmode, const0_rtx) |
f1c6ba8b | 6235 | : gen_rtx_STRICT_LOW_PART (VOIDmode, new))); |
230d793d | 6236 | |
0f808b6f JH |
6237 | if (mode == tmode) |
6238 | return new; | |
6239 | ||
0a7ec763 | 6240 | if (GET_CODE (new) == CONST_INT) |
2496c7bd | 6241 | return gen_int_mode (INTVAL (new), mode); |
0a7ec763 | 6242 | |
0f808b6f JH |
6243 | /* If we know that no extraneous bits are set, and that the high |
6244 | bit is not set, convert the extraction to the cheaper of | |
6245 | sign and zero extension, that are equivalent in these cases. */ | |
6246 | if (flag_expensive_optimizations | |
6247 | && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
6248 | && ((nonzero_bits (new, tmode) | |
663522cb KH |
6249 | & ~(((unsigned HOST_WIDE_INT) |
6250 | GET_MODE_MASK (tmode)) | |
6251 | >> 1)) | |
0f808b6f JH |
6252 | == 0))) |
6253 | { | |
6254 | rtx temp = gen_rtx_ZERO_EXTEND (mode, new); | |
6255 | rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new); | |
6256 | ||
6257 | /* Prefer ZERO_EXTENSION, since it gives more information to | |
6258 | backends. */ | |
25ffb1f6 | 6259 | if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET)) |
0f808b6f JH |
6260 | return temp; |
6261 | return temp1; | |
6262 | } | |
6263 | ||
230d793d RS |
6264 | /* Otherwise, sign- or zero-extend unless we already are in the |
6265 | proper mode. */ | |
6266 | ||
f1c6ba8b RK |
6267 | return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, |
6268 | mode, new)); | |
230d793d RS |
6269 | } |
6270 | ||
cc471082 RS |
6271 | /* Unless this is a COMPARE or we have a funny memory reference, |
6272 | don't do anything with zero-extending field extracts starting at | |
6273 | the low-order bit since they are simple AND operations. */ | |
8999a12e RK |
6274 | if (pos_rtx == 0 && pos == 0 && ! in_dest |
6275 | && ! in_compare && ! spans_byte && unsignedp) | |
230d793d RS |
6276 | return 0; |
6277 | ||
c5c76735 JL |
6278 | /* Unless we are allowed to span bytes or INNER is not MEM, reject this if |
6279 | we would be spanning bytes or if the position is not a constant and the | |
6280 | length is not 1. In all other cases, we would only be going outside | |
6281 | our object in cases when an original shift would have been | |
e7373556 | 6282 | undefined. */ |
3c0cb5de | 6283 | if (! spans_byte && MEM_P (inner) |
e7373556 RK |
6284 | && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode)) |
6285 | || (pos_rtx != 0 && len != 1))) | |
6286 | return 0; | |
6287 | ||
d7cd794f | 6288 | /* Get the mode to use should INNER not be a MEM, the mode for the position, |
230d793d | 6289 | and the mode for the result. */ |
505ddab6 | 6290 | if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE) |
230d793d | 6291 | { |
da920570 ZW |
6292 | wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0); |
6293 | pos_mode = mode_for_extraction (EP_insv, 2); | |
6294 | extraction_mode = mode_for_extraction (EP_insv, 3); | |
230d793d | 6295 | } |
230d793d | 6296 | |
da920570 ZW |
6297 | if (! in_dest && unsignedp |
6298 | && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6299 | { |
da920570 ZW |
6300 | wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1); |
6301 | pos_mode = mode_for_extraction (EP_extzv, 3); | |
6302 | extraction_mode = mode_for_extraction (EP_extzv, 0); | |
230d793d | 6303 | } |
230d793d | 6304 | |
da920570 ZW |
6305 | if (! in_dest && ! unsignedp |
6306 | && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE) | |
230d793d | 6307 | { |
da920570 ZW |
6308 | wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1); |
6309 | pos_mode = mode_for_extraction (EP_extv, 3); | |
6310 | extraction_mode = mode_for_extraction (EP_extv, 0); | |
230d793d | 6311 | } |
230d793d RS |
6312 | |
6313 | /* Never narrow an object, since that might not be safe. */ | |
6314 | ||
6315 | if (mode != VOIDmode | |
6316 | && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
6317 | extraction_mode = mode; | |
6318 | ||
6319 | if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode | |
6320 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
6321 | pos_mode = GET_MODE (pos_rtx); | |
6322 | ||
d7cd794f RK |
6323 | /* If this is not from memory, the desired mode is wanted_inner_reg_mode; |
6324 | if we have to change the mode of memory and cannot, the desired mode is | |
6325 | EXTRACTION_MODE. */ | |
3c0cb5de | 6326 | if (!MEM_P (inner)) |
d7cd794f RK |
6327 | wanted_inner_mode = wanted_inner_reg_mode; |
6328 | else if (inner_mode != wanted_inner_mode | |
6329 | && (mode_dependent_address_p (XEXP (inner, 0)) | |
6330 | || MEM_VOLATILE_P (inner))) | |
6331 | wanted_inner_mode = extraction_mode; | |
230d793d | 6332 | |
6139ff20 RK |
6333 | orig_pos = pos; |
6334 | ||
f76b9db2 ILT |
6335 | if (BITS_BIG_ENDIAN) |
6336 | { | |
cf54c2cd DE |
6337 | /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to |
6338 | BITS_BIG_ENDIAN style. If position is constant, compute new | |
6339 | position. Otherwise, build subtraction. | |
6340 | Note that POS is relative to the mode of the original argument. | |
6341 | If it's a MEM we need to recompute POS relative to that. | |
6342 | However, if we're extracting from (or inserting into) a register, | |
6343 | we want to recompute POS relative to wanted_inner_mode. */ | |
3c0cb5de | 6344 | int width = (MEM_P (inner) |
cf54c2cd DE |
6345 | ? GET_MODE_BITSIZE (is_mode) |
6346 | : GET_MODE_BITSIZE (wanted_inner_mode)); | |
6347 | ||
f76b9db2 | 6348 | if (pos_rtx == 0) |
cf54c2cd | 6349 | pos = width - len - pos; |
f76b9db2 ILT |
6350 | else |
6351 | pos_rtx | |
f1c6ba8b | 6352 | = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx); |
cf54c2cd | 6353 | /* POS may be less than 0 now, but we check for that below. |
3c0cb5de | 6354 | Note that it can only be less than 0 if !MEM_P (inner). */ |
f76b9db2 | 6355 | } |
230d793d RS |
6356 | |
6357 | /* If INNER has a wider mode, make it smaller. If this is a constant | |
6358 | extract, try to adjust the byte to point to the byte containing | |
6359 | the value. */ | |
d7cd794f RK |
6360 | if (wanted_inner_mode != VOIDmode |
6361 | && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode) | |
3c0cb5de | 6362 | && ((MEM_P (inner) |
d7cd794f | 6363 | && (inner_mode == wanted_inner_mode |
230d793d RS |
6364 | || (! mode_dependent_address_p (XEXP (inner, 0)) |
6365 | && ! MEM_VOLATILE_P (inner)))))) | |
6366 | { | |
6367 | int offset = 0; | |
6368 | ||
6369 | /* The computations below will be correct if the machine is big | |
6370 | endian in both bits and bytes or little endian in bits and bytes. | |
6371 | If it is mixed, we must adjust. */ | |
663522cb | 6372 | |
230d793d | 6373 | /* If bytes are big endian and we had a paradoxical SUBREG, we must |
0f41302f | 6374 | adjust OFFSET to compensate. */ |
f76b9db2 ILT |
6375 | if (BYTES_BIG_ENDIAN |
6376 | && ! spans_byte | |
230d793d RS |
6377 | && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) |
6378 | offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
230d793d RS |
6379 | |
6380 | /* If this is a constant position, we can move to the desired byte. */ | |
8999a12e | 6381 | if (pos_rtx == 0) |
230d793d RS |
6382 | { |
6383 | offset += pos / BITS_PER_UNIT; | |
d7cd794f | 6384 | pos %= GET_MODE_BITSIZE (wanted_inner_mode); |
230d793d RS |
6385 | } |
6386 | ||
f76b9db2 ILT |
6387 | if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN |
6388 | && ! spans_byte | |
d7cd794f | 6389 | && is_mode != wanted_inner_mode) |
c6b3f1f2 | 6390 | offset = (GET_MODE_SIZE (is_mode) |
d7cd794f | 6391 | - GET_MODE_SIZE (wanted_inner_mode) - offset); |
c6b3f1f2 | 6392 | |
d7cd794f | 6393 | if (offset != 0 || inner_mode != wanted_inner_mode) |
f1ec5147 | 6394 | inner = adjust_address_nv (inner, wanted_inner_mode, offset); |
230d793d RS |
6395 | } |
6396 | ||
9e74dc41 RK |
6397 | /* If INNER is not memory, we can always get it into the proper mode. If we |
6398 | are changing its mode, POS must be a constant and smaller than the size | |
6399 | of the new mode. */ | |
3c0cb5de | 6400 | else if (!MEM_P (inner)) |
9e74dc41 RK |
6401 | { |
6402 | if (GET_MODE (inner) != wanted_inner_mode | |
6403 | && (pos_rtx != 0 | |
6404 | || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode))) | |
6405 | return 0; | |
6406 | ||
6407 | inner = force_to_mode (inner, wanted_inner_mode, | |
6408 | pos_rtx | |
6409 | || len + orig_pos >= HOST_BITS_PER_WIDE_INT | |
0345195a | 6410 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 RK |
6411 | : ((((unsigned HOST_WIDE_INT) 1 << len) - 1) |
6412 | << orig_pos), | |
9e74dc41 RK |
6413 | NULL_RTX, 0); |
6414 | } | |
230d793d RS |
6415 | |
6416 | /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
6417 | have to zero extend. Otherwise, we can just use a SUBREG. */ | |
8999a12e | 6418 | if (pos_rtx != 0 |
230d793d | 6419 | && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) |
0f808b6f | 6420 | { |
f1c6ba8b | 6421 | rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx); |
0f808b6f JH |
6422 | |
6423 | /* If we know that no extraneous bits are set, and that the high | |
eaec9b3d | 6424 | bit is not set, convert extraction to cheaper one - either |
0f808b6f JH |
6425 | SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these |
6426 | cases. */ | |
6427 | if (flag_expensive_optimizations | |
6428 | && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT | |
6429 | && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx)) | |
663522cb KH |
6430 | & ~(((unsigned HOST_WIDE_INT) |
6431 | GET_MODE_MASK (GET_MODE (pos_rtx))) | |
6432 | >> 1)) | |
0f808b6f JH |
6433 | == 0))) |
6434 | { | |
6435 | rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx); | |
6436 | ||
25ffb1f6 | 6437 | /* Prefer ZERO_EXTENSION, since it gives more information to |
0f808b6f JH |
6438 | backends. */ |
6439 | if (rtx_cost (temp1, SET) < rtx_cost (temp, SET)) | |
6440 | temp = temp1; | |
6441 | } | |
6442 | pos_rtx = temp; | |
6443 | } | |
8999a12e | 6444 | else if (pos_rtx != 0 |
230d793d | 6445 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) |
4de249d9 | 6446 | pos_rtx = gen_lowpart (pos_mode, pos_rtx); |
230d793d | 6447 | |
8999a12e RK |
6448 | /* Make POS_RTX unless we already have it and it is correct. If we don't |
6449 | have a POS_RTX but we do have an ORIG_POS_RTX, the latter must | |
0f41302f | 6450 | be a CONST_INT. */ |
8999a12e RK |
6451 | if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos) |
6452 | pos_rtx = orig_pos_rtx; | |
6453 | ||
6454 | else if (pos_rtx == 0) | |
5f4f0e22 | 6455 | pos_rtx = GEN_INT (pos); |
230d793d RS |
6456 | |
6457 | /* Make the required operation. See if we can use existing rtx. */ | |
f1c6ba8b | 6458 | new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, |
5f4f0e22 | 6459 | extraction_mode, inner, GEN_INT (len), pos_rtx); |
230d793d | 6460 | if (! in_dest) |
4de249d9 | 6461 | new = gen_lowpart (mode, new); |
230d793d RS |
6462 | |
6463 | return new; | |
6464 | } | |
6465 | \f | |
71923da7 RK |
6466 | /* See if X contains an ASHIFT of COUNT or more bits that can be commuted |
6467 | with any other operations in X. Return X without that shift if so. */ | |
6468 | ||
6469 | static rtx | |
79a490a9 | 6470 | extract_left_shift (rtx x, int count) |
71923da7 RK |
6471 | { |
6472 | enum rtx_code code = GET_CODE (x); | |
6473 | enum machine_mode mode = GET_MODE (x); | |
6474 | rtx tem; | |
6475 | ||
6476 | switch (code) | |
6477 | { | |
6478 | case ASHIFT: | |
6479 | /* This is the shift itself. If it is wide enough, we will return | |
6480 | either the value being shifted if the shift count is equal to | |
6481 | COUNT or a shift for the difference. */ | |
6482 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6483 | && INTVAL (XEXP (x, 1)) >= count) | |
6484 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), | |
6485 | INTVAL (XEXP (x, 1)) - count); | |
6486 | break; | |
6487 | ||
6488 | case NEG: case NOT: | |
6489 | if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0) | |
f1c6ba8b | 6490 | return simplify_gen_unary (code, mode, tem, mode); |
71923da7 RK |
6491 | |
6492 | break; | |
6493 | ||
6494 | case PLUS: case IOR: case XOR: case AND: | |
6495 | /* If we can safely shift this constant and we find the inner shift, | |
6496 | make a new operation. */ | |
e869aa39 | 6497 | if (GET_CODE (XEXP (x, 1)) == CONST_INT |
b729186a | 6498 | && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0 |
71923da7 | 6499 | && (tem = extract_left_shift (XEXP (x, 0), count)) != 0) |
bcb34aa3 PB |
6500 | return simplify_gen_binary (code, mode, tem, |
6501 | GEN_INT (INTVAL (XEXP (x, 1)) >> count)); | |
71923da7 RK |
6502 | |
6503 | break; | |
663522cb | 6504 | |
e9a25f70 JL |
6505 | default: |
6506 | break; | |
71923da7 RK |
6507 | } |
6508 | ||
6509 | return 0; | |
6510 | } | |
6511 | \f | |
230d793d RS |
6512 | /* Look at the expression rooted at X. Look for expressions |
6513 | equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
6514 | Form these expressions. | |
6515 | ||
6516 | Return the new rtx, usually just X. | |
6517 | ||
8aeea6e6 | 6518 | Also, for machines like the VAX that don't have logical shift insns, |
230d793d RS |
6519 | try to convert logical to arithmetic shift operations in cases where |
6520 | they are equivalent. This undoes the canonicalizations to logical | |
6521 | shifts done elsewhere. | |
6522 | ||
6523 | We try, as much as possible, to re-use rtl expressions to save memory. | |
6524 | ||
6525 | IN_CODE says what kind of expression we are processing. Normally, it is | |
42495ca0 RK |
6526 | SET. In a memory address (inside a MEM, PLUS or minus, the latter two |
6527 | being kludges), it is MEM. When processing the arguments of a comparison | |
230d793d RS |
6528 | or a COMPARE against zero, it is COMPARE. */ |
6529 | ||
6530 | static rtx | |
79a490a9 | 6531 | make_compound_operation (rtx x, enum rtx_code in_code) |
230d793d RS |
6532 | { |
6533 | enum rtx_code code = GET_CODE (x); | |
6534 | enum machine_mode mode = GET_MODE (x); | |
6535 | int mode_width = GET_MODE_BITSIZE (mode); | |
71923da7 | 6536 | rtx rhs, lhs; |
230d793d | 6537 | enum rtx_code next_code; |
f24ad0e4 | 6538 | int i; |
230d793d | 6539 | rtx new = 0; |
280f58ba | 6540 | rtx tem; |
6f7d635c | 6541 | const char *fmt; |
230d793d RS |
6542 | |
6543 | /* Select the code to be used in recursive calls. Once we are inside an | |
6544 | address, we stay there. If we have a comparison, set to COMPARE, | |
6545 | but once inside, go back to our default of SET. */ | |
6546 | ||
42495ca0 | 6547 | next_code = (code == MEM || code == PLUS || code == MINUS ? MEM |
ec8e098d | 6548 | : ((code == COMPARE || COMPARISON_P (x)) |
230d793d RS |
6549 | && XEXP (x, 1) == const0_rtx) ? COMPARE |
6550 | : in_code == COMPARE ? SET : in_code); | |
6551 | ||
6552 | /* Process depending on the code of this operation. If NEW is set | |
da7d8304 | 6553 | nonzero, it will be returned. */ |
230d793d RS |
6554 | |
6555 | switch (code) | |
6556 | { | |
6557 | case ASHIFT: | |
230d793d RS |
6558 | /* Convert shifts by constants into multiplications if inside |
6559 | an address. */ | |
6560 | if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT | |
5f4f0e22 | 6561 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
230d793d | 6562 | && INTVAL (XEXP (x, 1)) >= 0) |
280f58ba RK |
6563 | { |
6564 | new = make_compound_operation (XEXP (x, 0), next_code); | |
f1c6ba8b RK |
6565 | new = gen_rtx_MULT (mode, new, |
6566 | GEN_INT ((HOST_WIDE_INT) 1 | |
6567 | << INTVAL (XEXP (x, 1)))); | |
280f58ba | 6568 | } |
230d793d RS |
6569 | break; |
6570 | ||
6571 | case AND: | |
6572 | /* If the second operand is not a constant, we can't do anything | |
6573 | with it. */ | |
6574 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
6575 | break; | |
6576 | ||
6577 | /* If the constant is a power of two minus one and the first operand | |
6578 | is a logical right shift, make an extraction. */ | |
6579 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
6580 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6581 | { |
6582 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6583 | new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1, | |
6584 | 0, in_code == COMPARE); | |
6585 | } | |
dfbe1b2f | 6586 | |
230d793d RS |
6587 | /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ |
6588 | else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
6589 | && subreg_lowpart_p (XEXP (x, 0)) | |
6590 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
6591 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6592 | { |
6593 | new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0), | |
6594 | next_code); | |
2f99f437 | 6595 | new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0, |
280f58ba RK |
6596 | XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, |
6597 | 0, in_code == COMPARE); | |
6598 | } | |
45620ed4 | 6599 | /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */ |
c2f9f64e JW |
6600 | else if ((GET_CODE (XEXP (x, 0)) == XOR |
6601 | || GET_CODE (XEXP (x, 0)) == IOR) | |
6602 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT | |
6603 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT | |
6604 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
6605 | { | |
6606 | /* Apply the distributive law, and then try to make extractions. */ | |
f1c6ba8b RK |
6607 | new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode, |
6608 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0), | |
6609 | XEXP (x, 1)), | |
6610 | gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1), | |
6611 | XEXP (x, 1))); | |
c2f9f64e JW |
6612 | new = make_compound_operation (new, in_code); |
6613 | } | |
a7c99304 RK |
6614 | |
6615 | /* If we are have (and (rotate X C) M) and C is larger than the number | |
6616 | of bits in M, this is an extraction. */ | |
6617 | ||
6618 | else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
6619 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
6620 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 | |
6621 | && i <= INTVAL (XEXP (XEXP (x, 0), 1))) | |
280f58ba RK |
6622 | { |
6623 | new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code); | |
6624 | new = make_extraction (mode, new, | |
6625 | (GET_MODE_BITSIZE (mode) | |
6626 | - INTVAL (XEXP (XEXP (x, 0), 1))), | |
6627 | NULL_RTX, i, 1, 0, in_code == COMPARE); | |
6628 | } | |
a7c99304 RK |
6629 | |
6630 | /* On machines without logical shifts, if the operand of the AND is | |
230d793d RS |
6631 | a logical shift and our mask turns off all the propagated sign |
6632 | bits, we can replace the logical shift with an arithmetic shift. */ | |
ef89d648 ZW |
6633 | else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT |
6634 | && !have_insn_for (LSHIFTRT, mode) | |
6635 | && have_insn_for (ASHIFTRT, mode) | |
230d793d RS |
6636 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT |
6637 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
5f4f0e22 CH |
6638 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT |
6639 | && mode_width <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 6640 | { |
5f4f0e22 | 6641 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
6642 | |
6643 | mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
6644 | if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
6645 | SUBST (XEXP (x, 0), | |
f1c6ba8b RK |
6646 | gen_rtx_ASHIFTRT (mode, |
6647 | make_compound_operation | |
6648 | (XEXP (XEXP (x, 0), 0), next_code), | |
6649 | XEXP (XEXP (x, 0), 1))); | |
230d793d RS |
6650 | } |
6651 | ||
6652 | /* If the constant is one less than a power of two, this might be | |
6653 | representable by an extraction even if no shift is present. | |
6654 | If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
6655 | we are in a COMPARE. */ | |
6656 | else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
280f58ba RK |
6657 | new = make_extraction (mode, |
6658 | make_compound_operation (XEXP (x, 0), | |
6659 | next_code), | |
6660 | 0, NULL_RTX, i, 1, 0, in_code == COMPARE); | |
230d793d RS |
6661 | |
6662 | /* If we are in a comparison and this is an AND with a power of two, | |
6663 | convert this into the appropriate bit extract. */ | |
6664 | else if (in_code == COMPARE | |
6665 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
280f58ba RK |
6666 | new = make_extraction (mode, |
6667 | make_compound_operation (XEXP (x, 0), | |
6668 | next_code), | |
6669 | i, NULL_RTX, 1, 1, 0, 1); | |
230d793d RS |
6670 | |
6671 | break; | |
6672 | ||
6673 | case LSHIFTRT: | |
6674 | /* If the sign bit is known to be zero, replace this with an | |
6675 | arithmetic shift. */ | |
ef89d648 ZW |
6676 | if (have_insn_for (ASHIFTRT, mode) |
6677 | && ! have_insn_for (LSHIFTRT, mode) | |
5f4f0e22 | 6678 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 6679 | && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0) |
230d793d | 6680 | { |
f1c6ba8b RK |
6681 | new = gen_rtx_ASHIFTRT (mode, |
6682 | make_compound_operation (XEXP (x, 0), | |
6683 | next_code), | |
6684 | XEXP (x, 1)); | |
230d793d RS |
6685 | break; |
6686 | } | |
6687 | ||
0f41302f | 6688 | /* ... fall through ... */ |
230d793d RS |
6689 | |
6690 | case ASHIFTRT: | |
71923da7 RK |
6691 | lhs = XEXP (x, 0); |
6692 | rhs = XEXP (x, 1); | |
6693 | ||
230d793d RS |
6694 | /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, |
6695 | this is a SIGN_EXTRACT. */ | |
71923da7 RK |
6696 | if (GET_CODE (rhs) == CONST_INT |
6697 | && GET_CODE (lhs) == ASHIFT | |
6698 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
6699 | && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))) | |
280f58ba | 6700 | { |
71923da7 | 6701 | new = make_compound_operation (XEXP (lhs, 0), next_code); |
280f58ba | 6702 | new = make_extraction (mode, new, |
71923da7 RK |
6703 | INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), |
6704 | NULL_RTX, mode_width - INTVAL (rhs), | |
d0ab8cd3 | 6705 | code == LSHIFTRT, 0, in_code == COMPARE); |
8231ad94 | 6706 | break; |
d0ab8cd3 RK |
6707 | } |
6708 | ||
71923da7 RK |
6709 | /* See if we have operations between an ASHIFTRT and an ASHIFT. |
6710 | If so, try to merge the shifts into a SIGN_EXTEND. We could | |
6711 | also do this for some cases of SIGN_EXTRACT, but it doesn't | |
6712 | seem worth the effort; the case checked for occurs on Alpha. */ | |
663522cb | 6713 | |
ec8e098d | 6714 | if (!OBJECT_P (lhs) |
71923da7 | 6715 | && ! (GET_CODE (lhs) == SUBREG |
ec8e098d | 6716 | && (OBJECT_P (SUBREG_REG (lhs)))) |
71923da7 RK |
6717 | && GET_CODE (rhs) == CONST_INT |
6718 | && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT | |
6719 | && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0) | |
6720 | new = make_extraction (mode, make_compound_operation (new, next_code), | |
6721 | 0, NULL_RTX, mode_width - INTVAL (rhs), | |
6722 | code == LSHIFTRT, 0, in_code == COMPARE); | |
663522cb | 6723 | |
230d793d | 6724 | break; |
280f58ba RK |
6725 | |
6726 | case SUBREG: | |
6727 | /* Call ourselves recursively on the inner expression. If we are | |
6728 | narrowing the object and it has a different RTL code from | |
6729 | what it originally did, do this SUBREG as a force_to_mode. */ | |
6730 | ||
0a5cbff6 | 6731 | tem = make_compound_operation (SUBREG_REG (x), in_code); |
280f58ba RK |
6732 | if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x)) |
6733 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem)) | |
6734 | && subreg_lowpart_p (x)) | |
0a5cbff6 | 6735 | { |
e8dc6d50 JH |
6736 | rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, |
6737 | NULL_RTX, 0); | |
0a5cbff6 RK |
6738 | |
6739 | /* If we have something other than a SUBREG, we might have | |
eaec9b3d | 6740 | done an expansion, so rerun ourselves. */ |
0a5cbff6 RK |
6741 | if (GET_CODE (newer) != SUBREG) |
6742 | newer = make_compound_operation (newer, in_code); | |
6743 | ||
6744 | return newer; | |
6745 | } | |
6f28d3e9 RH |
6746 | |
6747 | /* If this is a paradoxical subreg, and the new code is a sign or | |
6748 | zero extension, omit the subreg and widen the extension. If it | |
6749 | is a regular subreg, we can still get rid of the subreg by not | |
6750 | widening so much, or in fact removing the extension entirely. */ | |
6751 | if ((GET_CODE (tem) == SIGN_EXTEND | |
6752 | || GET_CODE (tem) == ZERO_EXTEND) | |
6753 | && subreg_lowpart_p (x)) | |
6754 | { | |
6755 | if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem)) | |
6756 | || (GET_MODE_SIZE (mode) > | |
6757 | GET_MODE_SIZE (GET_MODE (XEXP (tem, 0))))) | |
b10f2187 | 6758 | { |
ab5ecb01 | 6759 | if (! SCALAR_INT_MODE_P (mode)) |
b10f2187 R |
6760 | break; |
6761 | tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0)); | |
6762 | } | |
6f28d3e9 | 6763 | else |
4de249d9 | 6764 | tem = gen_lowpart (mode, XEXP (tem, 0)); |
6f28d3e9 RH |
6765 | return tem; |
6766 | } | |
e9a25f70 | 6767 | break; |
663522cb | 6768 | |
e9a25f70 JL |
6769 | default: |
6770 | break; | |
230d793d RS |
6771 | } |
6772 | ||
6773 | if (new) | |
6774 | { | |
4de249d9 | 6775 | x = gen_lowpart (mode, new); |
230d793d RS |
6776 | code = GET_CODE (x); |
6777 | } | |
6778 | ||
6779 | /* Now recursively process each operand of this operation. */ | |
6780 | fmt = GET_RTX_FORMAT (code); | |
6781 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6782 | if (fmt[i] == 'e') | |
6783 | { | |
6784 | new = make_compound_operation (XEXP (x, i), next_code); | |
6785 | SUBST (XEXP (x, i), new); | |
6786 | } | |
6787 | ||
6788 | return x; | |
6789 | } | |
6790 | \f | |
6791 | /* Given M see if it is a value that would select a field of bits | |
663522cb KH |
6792 | within an item, but not the entire word. Return -1 if not. |
6793 | Otherwise, return the starting position of the field, where 0 is the | |
6794 | low-order bit. | |
230d793d RS |
6795 | |
6796 | *PLEN is set to the length of the field. */ | |
6797 | ||
6798 | static int | |
79a490a9 | 6799 | get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen) |
230d793d RS |
6800 | { |
6801 | /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
663522cb | 6802 | int pos = exact_log2 (m & -m); |
6de9cd9a | 6803 | int len = 0; |
230d793d | 6804 | |
6de9cd9a DN |
6805 | if (pos >= 0) |
6806 | /* Now shift off the low-order zero bits and see if we have a | |
6807 | power of two minus 1. */ | |
6808 | len = exact_log2 ((m >> pos) + 1); | |
230d793d | 6809 | |
d3bc8938 | 6810 | if (len <= 0) |
6de9cd9a | 6811 | pos = -1; |
230d793d | 6812 | |
d3bc8938 | 6813 | *plen = len; |
230d793d RS |
6814 | return pos; |
6815 | } | |
6816 | \f | |
6139ff20 RK |
6817 | /* See if X can be simplified knowing that we will only refer to it in |
6818 | MODE and will only refer to those bits that are nonzero in MASK. | |
6819 | If other bits are being computed or if masking operations are done | |
6820 | that select a superset of the bits in MASK, they can sometimes be | |
6821 | ignored. | |
6822 | ||
6823 | Return a possibly simplified expression, but always convert X to | |
6824 | MODE. If X is a CONST_INT, AND the CONST_INT with MASK. | |
dfbe1b2f | 6825 | |
da7d8304 | 6826 | Also, if REG is nonzero and X is a register equal in value to REG, |
e3d616e3 RK |
6827 | replace X with REG. |
6828 | ||
6829 | If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK | |
6830 | are all off in X. This is used when X will be complemented, by either | |
180b8e4b | 6831 | NOT, NEG, or XOR. */ |
dfbe1b2f RK |
6832 | |
6833 | static rtx | |
79a490a9 AJ |
6834 | force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask, |
6835 | rtx reg, int just_select) | |
dfbe1b2f RK |
6836 | { |
6837 | enum rtx_code code = GET_CODE (x); | |
180b8e4b | 6838 | int next_select = just_select || code == XOR || code == NOT || code == NEG; |
ef026f91 RS |
6839 | enum machine_mode op_mode; |
6840 | unsigned HOST_WIDE_INT fuller_mask, nonzero; | |
6139ff20 RK |
6841 | rtx op0, op1, temp; |
6842 | ||
132d2040 RK |
6843 | /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the |
6844 | code below will do the wrong thing since the mode of such an | |
663522cb | 6845 | expression is VOIDmode. |
be3d27d6 CI |
6846 | |
6847 | Also do nothing if X is a CLOBBER; this can happen if X was | |
4de249d9 | 6848 | the return value from a call to gen_lowpart. */ |
be3d27d6 | 6849 | if (code == CALL || code == ASM_OPERANDS || code == CLOBBER) |
246e00f2 RK |
6850 | return x; |
6851 | ||
6139ff20 RK |
6852 | /* We want to perform the operation is its present mode unless we know |
6853 | that the operation is valid in MODE, in which case we do the operation | |
6854 | in MODE. */ | |
1c75dfa4 | 6855 | op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x)) |
ef89d648 | 6856 | && have_insn_for (code, mode)) |
ef026f91 | 6857 | ? mode : GET_MODE (x)); |
e3d616e3 | 6858 | |
aa988991 RS |
6859 | /* It is not valid to do a right-shift in a narrower mode |
6860 | than the one it came in with. */ | |
6861 | if ((code == LSHIFTRT || code == ASHIFTRT) | |
6862 | && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x))) | |
6863 | op_mode = GET_MODE (x); | |
ef026f91 RS |
6864 | |
6865 | /* Truncate MASK to fit OP_MODE. */ | |
6866 | if (op_mode) | |
6867 | mask &= GET_MODE_MASK (op_mode); | |
6139ff20 RK |
6868 | |
6869 | /* When we have an arithmetic operation, or a shift whose count we | |
50b29dbb | 6870 | do not know, we need to assume that all bits up to the highest-order |
6139ff20 | 6871 | bit in MASK will be needed. This is how we form such a mask. */ |
50b29dbb ILT |
6872 | if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1))) |
6873 | fuller_mask = ~(unsigned HOST_WIDE_INT) 0; | |
ef026f91 | 6874 | else |
50b29dbb ILT |
6875 | fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) |
6876 | - 1); | |
ef026f91 RS |
6877 | |
6878 | /* Determine what bits of X are guaranteed to be (non)zero. */ | |
6879 | nonzero = nonzero_bits (x, mode); | |
6139ff20 RK |
6880 | |
6881 | /* If none of the bits in X are needed, return a zero. */ | |
e3d616e3 | 6882 | if (! just_select && (nonzero & mask) == 0) |
ccf7aef4 | 6883 | x = const0_rtx; |
dfbe1b2f | 6884 | |
6139ff20 RK |
6885 | /* If X is a CONST_INT, return a new one. Do this here since the |
6886 | test below will fail. */ | |
6887 | if (GET_CODE (x) == CONST_INT) | |
ccf7aef4 RH |
6888 | { |
6889 | if (SCALAR_INT_MODE_P (mode)) | |
6890 | return gen_int_mode (INTVAL (x) & mask, mode); | |
6891 | else | |
6892 | { | |
6893 | x = GEN_INT (INTVAL (x) & mask); | |
6894 | return gen_lowpart_common (mode, x); | |
6895 | } | |
6896 | } | |
dfbe1b2f | 6897 | |
180b8e4b RK |
6898 | /* If X is narrower than MODE and we want all the bits in X's mode, just |
6899 | get X in the proper mode. */ | |
6900 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
663522cb | 6901 | && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0) |
4de249d9 | 6902 | return gen_lowpart (mode, x); |
dfbe1b2f RK |
6903 | |
6904 | switch (code) | |
6905 | { | |
6139ff20 RK |
6906 | case CLOBBER: |
6907 | /* If X is a (clobber (const_int)), return it since we know we are | |
0f41302f | 6908 | generating something that won't match. */ |
6139ff20 RK |
6909 | return x; |
6910 | ||
6139ff20 RK |
6911 | case USE: |
6912 | /* X is a (use (mem ..)) that was made from a bit-field extraction that | |
6913 | spanned the boundary of the MEM. If we are now masking so it is | |
6914 | within that boundary, we don't need the USE any more. */ | |
f76b9db2 | 6915 | if (! BITS_BIG_ENDIAN |
663522cb | 6916 | && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0) |
e3d616e3 | 6917 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
f76b9db2 | 6918 | break; |
6139ff20 | 6919 | |
dfbe1b2f RK |
6920 | case SIGN_EXTEND: |
6921 | case ZERO_EXTEND: | |
6922 | case ZERO_EXTRACT: | |
6923 | case SIGN_EXTRACT: | |
6924 | x = expand_compound_operation (x); | |
6925 | if (GET_CODE (x) != code) | |
e3d616e3 | 6926 | return force_to_mode (x, mode, mask, reg, next_select); |
dfbe1b2f RK |
6927 | break; |
6928 | ||
6929 | case REG: | |
6930 | if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) | |
6931 | || rtx_equal_p (reg, get_last_value (x)))) | |
6932 | x = reg; | |
6933 | break; | |
6934 | ||
dfbe1b2f | 6935 | case SUBREG: |
6139ff20 | 6936 | if (subreg_lowpart_p (x) |
180b8e4b RK |
6937 | /* We can ignore the effect of this SUBREG if it narrows the mode or |
6938 | if the constant masks to zero all the bits the mode doesn't | |
6939 | have. */ | |
6139ff20 RK |
6940 | && ((GET_MODE_SIZE (GET_MODE (x)) |
6941 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
6139ff20 RK |
6942 | || (0 == (mask |
6943 | & GET_MODE_MASK (GET_MODE (x)) | |
663522cb | 6944 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))))))) |
e3d616e3 | 6945 | return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select); |
dfbe1b2f RK |
6946 | break; |
6947 | ||
6948 | case AND: | |
6139ff20 RK |
6949 | /* If this is an AND with a constant, convert it into an AND |
6950 | whose constant is the AND of that constant with MASK. If it | |
6951 | remains an AND of MASK, delete it since it is redundant. */ | |
dfbe1b2f | 6952 | |
2ca9ae17 | 6953 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) |
dfbe1b2f | 6954 | { |
6139ff20 RK |
6955 | x = simplify_and_const_int (x, op_mode, XEXP (x, 0), |
6956 | mask & INTVAL (XEXP (x, 1))); | |
dfbe1b2f RK |
6957 | |
6958 | /* If X is still an AND, see if it is an AND with a mask that | |
71923da7 RK |
6959 | is just some low-order bits. If so, and it is MASK, we don't |
6960 | need it. */ | |
dfbe1b2f RK |
6961 | |
6962 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0c9db30 | 6963 | && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x))) |
3129af4c | 6964 | == mask)) |
dfbe1b2f | 6965 | x = XEXP (x, 0); |
d0ab8cd3 | 6966 | |
71923da7 RK |
6967 | /* If it remains an AND, try making another AND with the bits |
6968 | in the mode mask that aren't in MASK turned on. If the | |
6969 | constant in the AND is wide enough, this might make a | |
6970 | cheaper constant. */ | |
6971 | ||
6972 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2ca9ae17 JW |
6973 | && GET_MODE_MASK (GET_MODE (x)) != mask |
6974 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT) | |
71923da7 RK |
6975 | { |
6976 | HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1)) | |
663522cb | 6977 | | (GET_MODE_MASK (GET_MODE (x)) & ~mask)); |
71923da7 RK |
6978 | int width = GET_MODE_BITSIZE (GET_MODE (x)); |
6979 | rtx y; | |
6980 | ||
71cc389b | 6981 | /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative |
71923da7 RK |
6982 | number, sign extend it. */ |
6983 | if (width > 0 && width < HOST_BITS_PER_WIDE_INT | |
6984 | && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
6985 | cval |= (HOST_WIDE_INT) -1 << width; | |
6986 | ||
bcb34aa3 PB |
6987 | y = simplify_gen_binary (AND, GET_MODE (x), |
6988 | XEXP (x, 0), GEN_INT (cval)); | |
71923da7 RK |
6989 | if (rtx_cost (y, SET) < rtx_cost (x, SET)) |
6990 | x = y; | |
6991 | } | |
6992 | ||
d0ab8cd3 | 6993 | break; |
dfbe1b2f RK |
6994 | } |
6995 | ||
6139ff20 | 6996 | goto binop; |
dfbe1b2f RK |
6997 | |
6998 | case PLUS: | |
6139ff20 RK |
6999 | /* In (and (plus FOO C1) M), if M is a mask that just turns off |
7000 | low-order bits (as in an alignment operation) and FOO is already | |
7001 | aligned to that boundary, mask C1 to that boundary as well. | |
7002 | This may eliminate that PLUS and, later, the AND. */ | |
9fa6d012 TG |
7003 | |
7004 | { | |
770ae6cc | 7005 | unsigned int width = GET_MODE_BITSIZE (mode); |
9fa6d012 TG |
7006 | unsigned HOST_WIDE_INT smask = mask; |
7007 | ||
7008 | /* If MODE is narrower than HOST_WIDE_INT and mask is a negative | |
7009 | number, sign extend it. */ | |
7010 | ||
7011 | if (width < HOST_BITS_PER_WIDE_INT | |
7012 | && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) | |
7013 | smask |= (HOST_WIDE_INT) -1 << width; | |
7014 | ||
7015 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
563c12b0 RH |
7016 | && exact_log2 (- smask) >= 0 |
7017 | && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0 | |
7018 | && (INTVAL (XEXP (x, 1)) & ~smask) != 0) | |
7019 | return force_to_mode (plus_constant (XEXP (x, 0), | |
7020 | (INTVAL (XEXP (x, 1)) & smask)), | |
7021 | mode, smask, reg, next_select); | |
9fa6d012 | 7022 | } |
6139ff20 | 7023 | |
0f41302f | 7024 | /* ... fall through ... */ |
6139ff20 | 7025 | |
dfbe1b2f | 7026 | case MULT: |
6139ff20 RK |
7027 | /* For PLUS, MINUS and MULT, we need any bits less significant than the |
7028 | most significant bit in MASK since carries from those bits will | |
7029 | affect the bits we are interested in. */ | |
7030 | mask = fuller_mask; | |
7031 | goto binop; | |
7032 | ||
d41638e4 RH |
7033 | case MINUS: |
7034 | /* If X is (minus C Y) where C's least set bit is larger than any bit | |
7035 | in the mask, then we may replace with (neg Y). */ | |
7036 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
0345195a RK |
7037 | && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0)) |
7038 | & -INTVAL (XEXP (x, 0)))) | |
7039 | > mask)) | |
d41638e4 | 7040 | { |
f1c6ba8b RK |
7041 | x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1), |
7042 | GET_MODE (x)); | |
d41638e4 RH |
7043 | return force_to_mode (x, mode, mask, reg, next_select); |
7044 | } | |
7045 | ||
bc02f8d3 | 7046 | /* Similarly, if C contains every bit in the fuller_mask, then we may |
d41638e4 RH |
7047 | replace with (not Y). */ |
7048 | if (GET_CODE (XEXP (x, 0)) == CONST_INT | |
bc02f8d3 | 7049 | && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask) |
0345195a | 7050 | == INTVAL (XEXP (x, 0)))) |
d41638e4 | 7051 | { |
f1c6ba8b RK |
7052 | x = simplify_gen_unary (NOT, GET_MODE (x), |
7053 | XEXP (x, 1), GET_MODE (x)); | |
d41638e4 RH |
7054 | return force_to_mode (x, mode, mask, reg, next_select); |
7055 | } | |
7056 | ||
7057 | mask = fuller_mask; | |
7058 | goto binop; | |
7059 | ||
dfbe1b2f RK |
7060 | case IOR: |
7061 | case XOR: | |
6139ff20 RK |
7062 | /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and |
7063 | LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
7064 | operation which may be a bitfield extraction. Ensure that the | |
7065 | constant we form is not wider than the mode of X. */ | |
7066 | ||
7067 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7068 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7069 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7070 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT | |
7071 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
7072 | && ((INTVAL (XEXP (XEXP (x, 0), 1)) | |
7073 | + floor_log2 (INTVAL (XEXP (x, 1)))) | |
7074 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7075 | && (INTVAL (XEXP (x, 1)) | |
663522cb | 7076 | & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0) |
6139ff20 RK |
7077 | { |
7078 | temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask) | |
663522cb | 7079 | << INTVAL (XEXP (XEXP (x, 0), 1))); |
bcb34aa3 PB |
7080 | temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x), |
7081 | XEXP (XEXP (x, 0), 0), temp); | |
7082 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp, | |
7083 | XEXP (XEXP (x, 0), 1)); | |
e3d616e3 | 7084 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7085 | } |
7086 | ||
7087 | binop: | |
dfbe1b2f | 7088 | /* For most binary operations, just propagate into the operation and |
6d2f8887 | 7089 | change the mode if we have an operation of that mode. */ |
6139ff20 | 7090 | |
4de249d9 PB |
7091 | op0 = gen_lowpart (op_mode, |
7092 | force_to_mode (XEXP (x, 0), mode, mask, | |
7093 | reg, next_select)); | |
7094 | op1 = gen_lowpart (op_mode, | |
7095 | force_to_mode (XEXP (x, 1), mode, mask, | |
7096 | reg, next_select)); | |
6139ff20 RK |
7097 | |
7098 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
bcb34aa3 | 7099 | x = simplify_gen_binary (code, op_mode, op0, op1); |
d0ab8cd3 | 7100 | break; |
dfbe1b2f RK |
7101 | |
7102 | case ASHIFT: | |
dfbe1b2f | 7103 | /* For left shifts, do the same, but just for the first operand. |
f6785026 RK |
7104 | However, we cannot do anything with shifts where we cannot |
7105 | guarantee that the counts are smaller than the size of the mode | |
7106 | because such a count will have a different meaning in a | |
6139ff20 | 7107 | wider mode. */ |
f6785026 RK |
7108 | |
7109 | if (! (GET_CODE (XEXP (x, 1)) == CONST_INT | |
6139ff20 | 7110 | && INTVAL (XEXP (x, 1)) >= 0 |
f6785026 RK |
7111 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode)) |
7112 | && ! (GET_MODE (XEXP (x, 1)) != VOIDmode | |
7113 | && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1))) | |
adb7a1cb | 7114 | < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode)))) |
f6785026 | 7115 | break; |
663522cb | 7116 | |
6139ff20 RK |
7117 | /* If the shift count is a constant and we can do arithmetic in |
7118 | the mode of the shift, refine which bits we need. Otherwise, use the | |
7119 | conservative form of the mask. */ | |
7120 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7121 | && INTVAL (XEXP (x, 1)) >= 0 | |
7122 | && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode) | |
7123 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) | |
7124 | mask >>= INTVAL (XEXP (x, 1)); | |
7125 | else | |
7126 | mask = fuller_mask; | |
7127 | ||
4de249d9 PB |
7128 | op0 = gen_lowpart (op_mode, |
7129 | force_to_mode (XEXP (x, 0), op_mode, | |
7130 | mask, reg, next_select)); | |
6139ff20 RK |
7131 | |
7132 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) | |
bcb34aa3 | 7133 | x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1)); |
d0ab8cd3 | 7134 | break; |
dfbe1b2f RK |
7135 | |
7136 | case LSHIFTRT: | |
1347292b JW |
7137 | /* Here we can only do something if the shift count is a constant, |
7138 | this shift constant is valid for the host, and we can do arithmetic | |
7139 | in OP_MODE. */ | |
dfbe1b2f RK |
7140 | |
7141 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
1347292b | 7142 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT |
6139ff20 | 7143 | && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT) |
d0ab8cd3 | 7144 | { |
6139ff20 | 7145 | rtx inner = XEXP (x, 0); |
402b6c2a | 7146 | unsigned HOST_WIDE_INT inner_mask; |
6139ff20 RK |
7147 | |
7148 | /* Select the mask of the bits we need for the shift operand. */ | |
402b6c2a | 7149 | inner_mask = mask << INTVAL (XEXP (x, 1)); |
d0ab8cd3 | 7150 | |
6139ff20 | 7151 | /* We can only change the mode of the shift if we can do arithmetic |
402b6c2a | 7152 | in the mode of the shift and INNER_MASK is no wider than the |
f3b2657c JJ |
7153 | width of X's mode. */ |
7154 | if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0) | |
d0ab8cd3 RK |
7155 | op_mode = GET_MODE (x); |
7156 | ||
402b6c2a | 7157 | inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select); |
6139ff20 RK |
7158 | |
7159 | if (GET_MODE (x) != op_mode || inner != XEXP (x, 0)) | |
bcb34aa3 | 7160 | x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1)); |
d0ab8cd3 | 7161 | } |
6139ff20 RK |
7162 | |
7163 | /* If we have (and (lshiftrt FOO C1) C2) where the combination of the | |
7164 | shift and AND produces only copies of the sign bit (C2 is one less | |
7165 | than a power of two), we can do this with just a shift. */ | |
7166 | ||
7167 | if (GET_CODE (x) == LSHIFTRT | |
7168 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
cfff35c1 JW |
7169 | /* The shift puts one of the sign bit copies in the least significant |
7170 | bit. */ | |
6139ff20 RK |
7171 | && ((INTVAL (XEXP (x, 1)) |
7172 | + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))) | |
7173 | >= GET_MODE_BITSIZE (GET_MODE (x))) | |
7174 | && exact_log2 (mask + 1) >= 0 | |
cfff35c1 JW |
7175 | /* Number of bits left after the shift must be more than the mask |
7176 | needs. */ | |
7177 | && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1)) | |
7178 | <= GET_MODE_BITSIZE (GET_MODE (x))) | |
7179 | /* Must be more sign bit copies than the mask needs. */ | |
770ae6cc | 7180 | && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))) |
6139ff20 | 7181 | >= exact_log2 (mask + 1))) |
bcb34aa3 PB |
7182 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), |
7183 | GEN_INT (GET_MODE_BITSIZE (GET_MODE (x)) | |
7184 | - exact_log2 (mask + 1))); | |
fae2db47 JW |
7185 | |
7186 | goto shiftrt; | |
d0ab8cd3 RK |
7187 | |
7188 | case ASHIFTRT: | |
6139ff20 RK |
7189 | /* If we are just looking for the sign bit, we don't need this shift at |
7190 | all, even if it has a variable count. */ | |
9bf22b75 | 7191 | if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT |
e51712db | 7192 | && (mask == ((unsigned HOST_WIDE_INT) 1 |
9bf22b75 | 7193 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) |
e3d616e3 | 7194 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 RK |
7195 | |
7196 | /* If this is a shift by a constant, get a mask that contains those bits | |
7197 | that are not copies of the sign bit. We then have two cases: If | |
7198 | MASK only includes those bits, this can be a logical shift, which may | |
7199 | allow simplifications. If MASK is a single-bit field not within | |
7200 | those bits, we are requesting a copy of the sign bit and hence can | |
7201 | shift the sign bit to the appropriate location. */ | |
7202 | ||
7203 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0 | |
7204 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) | |
7205 | { | |
7206 | int i = -1; | |
7207 | ||
3e92902c | 7208 | /* If the considered data is wider than HOST_WIDE_INT, we can't |
b69960ac RK |
7209 | represent a mask for all its bits in a single scalar. |
7210 | But we only care about the lower bits, so calculate these. */ | |
7211 | ||
6a11342f | 7212 | if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT) |
b69960ac | 7213 | { |
663522cb | 7214 | nonzero = ~(HOST_WIDE_INT) 0; |
b69960ac RK |
7215 | |
7216 | /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7217 | is the number of bits a full-width mask would have set. | |
7218 | We need only shift if these are fewer than nonzero can | |
7219 | hold. If not, we must keep all bits set in nonzero. */ | |
7220 | ||
7221 | if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1)) | |
7222 | < HOST_BITS_PER_WIDE_INT) | |
7223 | nonzero >>= INTVAL (XEXP (x, 1)) | |
7224 | + HOST_BITS_PER_WIDE_INT | |
7225 | - GET_MODE_BITSIZE (GET_MODE (x)) ; | |
7226 | } | |
7227 | else | |
7228 | { | |
7229 | nonzero = GET_MODE_MASK (GET_MODE (x)); | |
7230 | nonzero >>= INTVAL (XEXP (x, 1)); | |
7231 | } | |
6139ff20 | 7232 | |
663522cb | 7233 | if ((mask & ~nonzero) == 0 |
6139ff20 RK |
7234 | || (i = exact_log2 (mask)) >= 0) |
7235 | { | |
7236 | x = simplify_shift_const | |
7237 | (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0), | |
7238 | i < 0 ? INTVAL (XEXP (x, 1)) | |
7239 | : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i); | |
7240 | ||
7241 | if (GET_CODE (x) != ASHIFTRT) | |
e3d616e3 | 7242 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7243 | } |
7244 | } | |
7245 | ||
e0a2f705 | 7246 | /* If MASK is 1, convert this to an LSHIFTRT. This can be done |
6139ff20 RK |
7247 | even if the shift count isn't a constant. */ |
7248 | if (mask == 1) | |
bcb34aa3 PB |
7249 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), |
7250 | XEXP (x, 0), XEXP (x, 1)); | |
6139ff20 | 7251 | |
fae2db47 JW |
7252 | shiftrt: |
7253 | ||
7254 | /* If this is a zero- or sign-extension operation that just affects bits | |
4c002f29 RK |
7255 | we don't care about, remove it. Be sure the call above returned |
7256 | something that is still a shift. */ | |
d0ab8cd3 | 7257 | |
4c002f29 RK |
7258 | if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT) |
7259 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
d0ab8cd3 | 7260 | && INTVAL (XEXP (x, 1)) >= 0 |
6139ff20 RK |
7261 | && (INTVAL (XEXP (x, 1)) |
7262 | <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1)) | |
d0ab8cd3 | 7263 | && GET_CODE (XEXP (x, 0)) == ASHIFT |
fa9ea255 | 7264 | && XEXP (XEXP (x, 0), 1) == XEXP (x, 1)) |
e3d616e3 RK |
7265 | return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, |
7266 | reg, next_select); | |
6139ff20 | 7267 | |
dfbe1b2f RK |
7268 | break; |
7269 | ||
6139ff20 RK |
7270 | case ROTATE: |
7271 | case ROTATERT: | |
7272 | /* If the shift count is constant and we can do computations | |
7273 | in the mode of X, compute where the bits we care about are. | |
7274 | Otherwise, we can't do anything. Don't change the mode of | |
7275 | the shift or propagate MODE into the shift, though. */ | |
7276 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
7277 | && INTVAL (XEXP (x, 1)) >= 0) | |
7278 | { | |
7279 | temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE, | |
7280 | GET_MODE (x), GEN_INT (mask), | |
7281 | XEXP (x, 1)); | |
e869aa39 | 7282 | if (temp && GET_CODE (temp) == CONST_INT) |
6139ff20 RK |
7283 | SUBST (XEXP (x, 0), |
7284 | force_to_mode (XEXP (x, 0), GET_MODE (x), | |
e3d616e3 | 7285 | INTVAL (temp), reg, next_select)); |
6139ff20 RK |
7286 | } |
7287 | break; | |
663522cb | 7288 | |
dfbe1b2f | 7289 | case NEG: |
180b8e4b | 7290 | /* If we just want the low-order bit, the NEG isn't needed since it |
3ef42a0c | 7291 | won't change the low-order bit. */ |
180b8e4b RK |
7292 | if (mask == 1) |
7293 | return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select); | |
7294 | ||
6139ff20 RK |
7295 | /* We need any bits less significant than the most significant bit in |
7296 | MASK since carries from those bits will affect the bits we are | |
7297 | interested in. */ | |
7298 | mask = fuller_mask; | |
7299 | goto unop; | |
7300 | ||
dfbe1b2f | 7301 | case NOT: |
6139ff20 RK |
7302 | /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the |
7303 | same as the XOR case above. Ensure that the constant we form is not | |
7304 | wider than the mode of X. */ | |
7305 | ||
7306 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
7307 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7308 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
7309 | && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask) | |
7310 | < GET_MODE_BITSIZE (GET_MODE (x))) | |
7311 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT) | |
7312 | { | |
6a04f4e0 AM |
7313 | temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), |
7314 | GET_MODE (x)); | |
bcb34aa3 PB |
7315 | temp = simplify_gen_binary (XOR, GET_MODE (x), |
7316 | XEXP (XEXP (x, 0), 0), temp); | |
7317 | x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), | |
7318 | temp, XEXP (XEXP (x, 0), 1)); | |
6139ff20 | 7319 | |
e3d616e3 | 7320 | return force_to_mode (x, mode, mask, reg, next_select); |
6139ff20 RK |
7321 | } |
7322 | ||
f82da7d2 JW |
7323 | /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must |
7324 | use the full mask inside the NOT. */ | |
7325 | mask = fuller_mask; | |
7326 | ||
6139ff20 | 7327 | unop: |
4de249d9 PB |
7328 | op0 = gen_lowpart (op_mode, |
7329 | force_to_mode (XEXP (x, 0), mode, mask, | |
7330 | reg, next_select)); | |
6139ff20 | 7331 | if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0)) |
f1c6ba8b | 7332 | x = simplify_gen_unary (code, op_mode, op0, op_mode); |
6139ff20 RK |
7333 | break; |
7334 | ||
7335 | case NE: | |
7336 | /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included | |
3aceff0d | 7337 | in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero, |
1a6ec070 | 7338 | which is equal to STORE_FLAG_VALUE. */ |
663522cb | 7339 | if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx |
7d103eb5 | 7340 | && GET_MODE (XEXP (x, 0)) == mode |
3aceff0d | 7341 | && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0 |
43196589 AS |
7342 | && (nonzero_bits (XEXP (x, 0), mode) |
7343 | == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE)) | |
e3d616e3 | 7344 | return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select); |
6139ff20 | 7345 | |
d0ab8cd3 RK |
7346 | break; |
7347 | ||
7348 | case IF_THEN_ELSE: | |
7349 | /* We have no way of knowing if the IF_THEN_ELSE can itself be | |
7350 | written in a narrower mode. We play it safe and do not do so. */ | |
7351 | ||
7352 | SUBST (XEXP (x, 1), | |
4de249d9 | 7353 | gen_lowpart (GET_MODE (x), |
d0ab8cd3 | 7354 | force_to_mode (XEXP (x, 1), mode, |
e3d616e3 | 7355 | mask, reg, next_select))); |
d0ab8cd3 | 7356 | SUBST (XEXP (x, 2), |
4de249d9 | 7357 | gen_lowpart (GET_MODE (x), |
d0ab8cd3 | 7358 | force_to_mode (XEXP (x, 2), mode, |
e869aa39 | 7359 | mask, reg, next_select))); |
d0ab8cd3 | 7360 | break; |
663522cb | 7361 | |
e9a25f70 JL |
7362 | default: |
7363 | break; | |
dfbe1b2f RK |
7364 | } |
7365 | ||
d0ab8cd3 | 7366 | /* Ensure we return a value of the proper mode. */ |
4de249d9 | 7367 | return gen_lowpart (mode, x); |
dfbe1b2f RK |
7368 | } |
7369 | \f | |
abe6e52f RK |
7370 | /* Return nonzero if X is an expression that has one of two values depending on |
7371 | whether some other value is zero or nonzero. In that case, we return the | |
7372 | value that is being tested, *PTRUE is set to the value if the rtx being | |
7373 | returned has a nonzero value, and *PFALSE is set to the other alternative. | |
7374 | ||
7375 | If we return zero, we set *PTRUE and *PFALSE to X. */ | |
7376 | ||
7377 | static rtx | |
79a490a9 | 7378 | if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse) |
abe6e52f RK |
7379 | { |
7380 | enum machine_mode mode = GET_MODE (x); | |
7381 | enum rtx_code code = GET_CODE (x); | |
abe6e52f RK |
7382 | rtx cond0, cond1, true0, true1, false0, false1; |
7383 | unsigned HOST_WIDE_INT nz; | |
7384 | ||
14a774a9 RK |
7385 | /* If we are comparing a value against zero, we are done. */ |
7386 | if ((code == NE || code == EQ) | |
87d9741e | 7387 | && XEXP (x, 1) == const0_rtx) |
14a774a9 | 7388 | { |
e8758a3a JL |
7389 | *ptrue = (code == NE) ? const_true_rtx : const0_rtx; |
7390 | *pfalse = (code == NE) ? const0_rtx : const_true_rtx; | |
14a774a9 RK |
7391 | return XEXP (x, 0); |
7392 | } | |
7393 | ||
abe6e52f RK |
7394 | /* If this is a unary operation whose operand has one of two values, apply |
7395 | our opcode to compute those values. */ | |
ec8e098d | 7396 | else if (UNARY_P (x) |
14a774a9 | 7397 | && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0) |
abe6e52f | 7398 | { |
f1c6ba8b RK |
7399 | *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0))); |
7400 | *pfalse = simplify_gen_unary (code, mode, false0, | |
7401 | GET_MODE (XEXP (x, 0))); | |
abe6e52f RK |
7402 | return cond0; |
7403 | } | |
7404 | ||
3a19aabc | 7405 | /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would |
ddd5a7c1 | 7406 | make can't possibly match and would suppress other optimizations. */ |
3a19aabc RK |
7407 | else if (code == COMPARE) |
7408 | ; | |
7409 | ||
abe6e52f RK |
7410 | /* If this is a binary operation, see if either side has only one of two |
7411 | values. If either one does or if both do and they are conditional on | |
7412 | the same value, compute the new true and false values. */ | |
ec8e098d | 7413 | else if (BINARY_P (x)) |
abe6e52f RK |
7414 | { |
7415 | cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0); | |
7416 | cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1); | |
7417 | ||
7418 | if ((cond0 != 0 || cond1 != 0) | |
7419 | && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1))) | |
7420 | { | |
987e845a JW |
7421 | /* If if_then_else_cond returned zero, then true/false are the |
7422 | same rtl. We must copy one of them to prevent invalid rtl | |
7423 | sharing. */ | |
7424 | if (cond0 == 0) | |
7425 | true0 = copy_rtx (true0); | |
7426 | else if (cond1 == 0) | |
7427 | true1 = copy_rtx (true1); | |
7428 | ||
bcb34aa3 PB |
7429 | if (COMPARISON_P (x)) |
7430 | { | |
7431 | *ptrue = simplify_gen_relational (code, mode, VOIDmode, | |
7432 | true0, true1); | |
7433 | *pfalse = simplify_gen_relational (code, mode, VOIDmode, | |
7434 | false0, false1); | |
7435 | } | |
7436 | else | |
7437 | { | |
7438 | *ptrue = simplify_gen_binary (code, mode, true0, true1); | |
7439 | *pfalse = simplify_gen_binary (code, mode, false0, false1); | |
7440 | } | |
7441 | ||
abe6e52f RK |
7442 | return cond0 ? cond0 : cond1; |
7443 | } | |
9210df58 | 7444 | |
9210df58 | 7445 | /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the |
da7d8304 | 7446 | operands is zero when the other is nonzero, and vice-versa, |
0802d516 | 7447 | and STORE_FLAG_VALUE is 1 or -1. */ |
9210df58 | 7448 | |
0802d516 RK |
7449 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7450 | && (code == PLUS || code == IOR || code == XOR || code == MINUS | |
663522cb | 7451 | || code == UMAX) |
9210df58 RK |
7452 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7453 | { | |
7454 | rtx op0 = XEXP (XEXP (x, 0), 1); | |
7455 | rtx op1 = XEXP (XEXP (x, 1), 1); | |
7456 | ||
7457 | cond0 = XEXP (XEXP (x, 0), 0); | |
7458 | cond1 = XEXP (XEXP (x, 1), 0); | |
7459 | ||
ec8e098d PB |
7460 | if (COMPARISON_P (cond0) |
7461 | && COMPARISON_P (cond1) | |
14f02e73 | 7462 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
9210df58 RK |
7463 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7464 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7465 | || ((swap_condition (GET_CODE (cond0)) | |
14f02e73 | 7466 | == reversed_comparison_code (cond1, NULL)) |
9210df58 RK |
7467 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7468 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7469 | && ! side_effects_p (x)) | |
7470 | { | |
bcb34aa3 PB |
7471 | *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx); |
7472 | *pfalse = simplify_gen_binary (MULT, mode, | |
7473 | (code == MINUS | |
7474 | ? simplify_gen_unary (NEG, mode, | |
7475 | op1, mode) | |
7476 | : op1), | |
7477 | const_true_rtx); | |
9210df58 RK |
7478 | return cond0; |
7479 | } | |
7480 | } | |
7481 | ||
eaec9b3d | 7482 | /* Similarly for MULT, AND and UMIN, except that for these the result |
9210df58 | 7483 | is always zero. */ |
0802d516 RK |
7484 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
7485 | && (code == MULT || code == AND || code == UMIN) | |
9210df58 RK |
7486 | && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT) |
7487 | { | |
7488 | cond0 = XEXP (XEXP (x, 0), 0); | |
7489 | cond1 = XEXP (XEXP (x, 1), 0); | |
7490 | ||
ec8e098d PB |
7491 | if (COMPARISON_P (cond0) |
7492 | && COMPARISON_P (cond1) | |
14f02e73 | 7493 | && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL) |
9210df58 RK |
7494 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0)) |
7495 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1))) | |
7496 | || ((swap_condition (GET_CODE (cond0)) | |
14f02e73 | 7497 | == reversed_comparison_code (cond1, NULL)) |
9210df58 RK |
7498 | && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1)) |
7499 | && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0)))) | |
7500 | && ! side_effects_p (x)) | |
7501 | { | |
7502 | *ptrue = *pfalse = const0_rtx; | |
7503 | return cond0; | |
7504 | } | |
7505 | } | |
abe6e52f RK |
7506 | } |
7507 | ||
7508 | else if (code == IF_THEN_ELSE) | |
7509 | { | |
7510 | /* If we have IF_THEN_ELSE already, extract the condition and | |
7511 | canonicalize it if it is NE or EQ. */ | |
7512 | cond0 = XEXP (x, 0); | |
7513 | *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2); | |
7514 | if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx) | |
7515 | return XEXP (cond0, 0); | |
7516 | else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx) | |
7517 | { | |
7518 | *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1); | |
7519 | return XEXP (cond0, 0); | |
7520 | } | |
7521 | else | |
7522 | return cond0; | |
7523 | } | |
7524 | ||
0631e0bf JH |
7525 | /* If X is a SUBREG, we can narrow both the true and false values |
7526 | if the inner expression, if there is a condition. */ | |
7527 | else if (code == SUBREG | |
abe6e52f RK |
7528 | && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x), |
7529 | &true0, &false0))) | |
7530 | { | |
bbe708a3 UW |
7531 | true0 = simplify_gen_subreg (mode, true0, |
7532 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); | |
7533 | false0 = simplify_gen_subreg (mode, false0, | |
0631e0bf | 7534 | GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x)); |
bbe708a3 UW |
7535 | if (true0 && false0) |
7536 | { | |
7537 | *ptrue = true0; | |
7538 | *pfalse = false0; | |
7539 | return cond0; | |
7540 | } | |
abe6e52f RK |
7541 | } |
7542 | ||
7543 | /* If X is a constant, this isn't special and will cause confusions | |
7544 | if we treat it as such. Likewise if it is equivalent to a constant. */ | |
7545 | else if (CONSTANT_P (x) | |
7546 | || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0))) | |
7547 | ; | |
7548 | ||
1f3f36d1 RH |
7549 | /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that |
7550 | will be least confusing to the rest of the compiler. */ | |
7551 | else if (mode == BImode) | |
7552 | { | |
7553 | *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx; | |
7554 | return x; | |
7555 | } | |
7556 | ||
663522cb | 7557 | /* If X is known to be either 0 or -1, those are the true and |
abe6e52f | 7558 | false values when testing X. */ |
49219895 JH |
7559 | else if (x == constm1_rtx || x == const0_rtx |
7560 | || (mode != VOIDmode | |
7561 | && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode))) | |
abe6e52f RK |
7562 | { |
7563 | *ptrue = constm1_rtx, *pfalse = const0_rtx; | |
7564 | return x; | |
7565 | } | |
7566 | ||
7567 | /* Likewise for 0 or a single bit. */ | |
9eb54558 | 7568 | else if (SCALAR_INT_MODE_P (mode) |
49219895 JH |
7569 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
7570 | && exact_log2 (nz = nonzero_bits (x, mode)) >= 0) | |
abe6e52f | 7571 | { |
578fc63d | 7572 | *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx; |
abe6e52f RK |
7573 | return x; |
7574 | } | |
7575 | ||
7576 | /* Otherwise fail; show no condition with true and false values the same. */ | |
7577 | *ptrue = *pfalse = x; | |
7578 | return 0; | |
7579 | } | |
7580 | \f | |
1a26b032 RK |
7581 | /* Return the value of expression X given the fact that condition COND |
7582 | is known to be true when applied to REG as its first operand and VAL | |
7583 | as its second. X is known to not be shared and so can be modified in | |
7584 | place. | |
7585 | ||
7586 | We only handle the simplest cases, and specifically those cases that | |
7587 | arise with IF_THEN_ELSE expressions. */ | |
7588 | ||
7589 | static rtx | |
79a490a9 | 7590 | known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val) |
1a26b032 RK |
7591 | { |
7592 | enum rtx_code code = GET_CODE (x); | |
f24ad0e4 | 7593 | rtx temp; |
6f7d635c | 7594 | const char *fmt; |
1a26b032 RK |
7595 | int i, j; |
7596 | ||
7597 | if (side_effects_p (x)) | |
7598 | return x; | |
7599 | ||
805f1694 JL |
7600 | /* If either operand of the condition is a floating point value, |
7601 | then we have to avoid collapsing an EQ comparison. */ | |
7602 | if (cond == EQ | |
7603 | && rtx_equal_p (x, reg) | |
7604 | && ! FLOAT_MODE_P (GET_MODE (x)) | |
7605 | && ! FLOAT_MODE_P (GET_MODE (val))) | |
69bc0a1f | 7606 | return val; |
805f1694 | 7607 | |
69bc0a1f | 7608 | if (cond == UNEQ && rtx_equal_p (x, reg)) |
1a26b032 RK |
7609 | return val; |
7610 | ||
7611 | /* If X is (abs REG) and we know something about REG's relationship | |
7612 | with zero, we may be able to simplify this. */ | |
7613 | ||
7614 | if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx) | |
7615 | switch (cond) | |
7616 | { | |
7617 | case GE: case GT: case EQ: | |
7618 | return XEXP (x, 0); | |
7619 | case LT: case LE: | |
f1c6ba8b RK |
7620 | return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)), |
7621 | XEXP (x, 0), | |
7622 | GET_MODE (XEXP (x, 0))); | |
e9a25f70 JL |
7623 | default: |
7624 | break; | |
1a26b032 RK |
7625 | } |
7626 | ||
7627 | /* The only other cases we handle are MIN, MAX, and comparisons if the | |
7628 | operands are the same as REG and VAL. */ | |
7629 | ||
ec8e098d | 7630 | else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x)) |
1a26b032 RK |
7631 | { |
7632 | if (rtx_equal_p (XEXP (x, 0), val)) | |
7633 | cond = swap_condition (cond), temp = val, val = reg, reg = temp; | |
7634 | ||
7635 | if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val)) | |
7636 | { | |
ec8e098d | 7637 | if (COMPARISON_P (x)) |
1eb8759b RH |
7638 | { |
7639 | if (comparison_dominates_p (cond, code)) | |
7640 | return const_true_rtx; | |
1a26b032 | 7641 | |
14f02e73 | 7642 | code = reversed_comparison_code (x, NULL); |
1eb8759b RH |
7643 | if (code != UNKNOWN |
7644 | && comparison_dominates_p (cond, code)) | |
7645 | return const0_rtx; | |
7646 | else | |
7647 | return x; | |
7648 | } | |
1a26b032 RK |
7649 | else if (code == SMAX || code == SMIN |
7650 | || code == UMIN || code == UMAX) | |
7651 | { | |
7652 | int unsignedp = (code == UMIN || code == UMAX); | |
7653 | ||
ac4cdf40 JE |
7654 | /* Do not reverse the condition when it is NE or EQ. |
7655 | This is because we cannot conclude anything about | |
7656 | the value of 'SMAX (x, y)' when x is not equal to y, | |
23190837 | 7657 | but we can when x equals y. */ |
ac4cdf40 JE |
7658 | if ((code == SMAX || code == UMAX) |
7659 | && ! (cond == EQ || cond == NE)) | |
1a26b032 RK |
7660 | cond = reverse_condition (cond); |
7661 | ||
7662 | switch (cond) | |
7663 | { | |
7664 | case GE: case GT: | |
7665 | return unsignedp ? x : XEXP (x, 1); | |
7666 | case LE: case LT: | |
7667 | return unsignedp ? x : XEXP (x, 0); | |
7668 | case GEU: case GTU: | |
7669 | return unsignedp ? XEXP (x, 1) : x; | |
7670 | case LEU: case LTU: | |
7671 | return unsignedp ? XEXP (x, 0) : x; | |
e9a25f70 JL |
7672 | default: |
7673 | break; | |
1a26b032 RK |
7674 | } |
7675 | } | |
7676 | } | |
7677 | } | |
9a360704 AO |
7678 | else if (code == SUBREG) |
7679 | { | |
7680 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x)); | |
7681 | rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val); | |
7682 | ||
7683 | if (SUBREG_REG (x) != r) | |
7684 | { | |
7685 | /* We must simplify subreg here, before we lose track of the | |
7686 | original inner_mode. */ | |
7687 | new = simplify_subreg (GET_MODE (x), r, | |
7688 | inner_mode, SUBREG_BYTE (x)); | |
7689 | if (new) | |
7690 | return new; | |
7691 | else | |
7692 | SUBST (SUBREG_REG (x), r); | |
7693 | } | |
7694 | ||
7695 | return x; | |
7696 | } | |
4161da12 AO |
7697 | /* We don't have to handle SIGN_EXTEND here, because even in the |
7698 | case of replacing something with a modeless CONST_INT, a | |
7699 | CONST_INT is already (supposed to be) a valid sign extension for | |
7700 | its narrower mode, which implies it's already properly | |
7701 | sign-extended for the wider mode. Now, for ZERO_EXTEND, the | |
7702 | story is different. */ | |
7703 | else if (code == ZERO_EXTEND) | |
7704 | { | |
7705 | enum machine_mode inner_mode = GET_MODE (XEXP (x, 0)); | |
7706 | rtx new, r = known_cond (XEXP (x, 0), cond, reg, val); | |
7707 | ||
7708 | if (XEXP (x, 0) != r) | |
7709 | { | |
7710 | /* We must simplify the zero_extend here, before we lose | |
7711 | track of the original inner_mode. */ | |
7712 | new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), | |
7713 | r, inner_mode); | |
7714 | if (new) | |
7715 | return new; | |
7716 | else | |
7717 | SUBST (XEXP (x, 0), r); | |
7718 | } | |
7719 | ||
7720 | return x; | |
7721 | } | |
1a26b032 RK |
7722 | |
7723 | fmt = GET_RTX_FORMAT (code); | |
7724 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7725 | { | |
7726 | if (fmt[i] == 'e') | |
7727 | SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val)); | |
7728 | else if (fmt[i] == 'E') | |
7729 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7730 | SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j), | |
7731 | cond, reg, val)); | |
7732 | } | |
7733 | ||
7734 | return x; | |
7735 | } | |
7736 | \f | |
e11fa86f RK |
7737 | /* See if X and Y are equal for the purposes of seeing if we can rewrite an |
7738 | assignment as a field assignment. */ | |
7739 | ||
7740 | static int | |
79a490a9 | 7741 | rtx_equal_for_field_assignment_p (rtx x, rtx y) |
e11fa86f | 7742 | { |
e11fa86f RK |
7743 | if (x == y || rtx_equal_p (x, y)) |
7744 | return 1; | |
7745 | ||
7746 | if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y)) | |
7747 | return 0; | |
7748 | ||
7749 | /* Check for a paradoxical SUBREG of a MEM compared with the MEM. | |
7750 | Note that all SUBREGs of MEM are paradoxical; otherwise they | |
7751 | would have been rewritten. */ | |
3c0cb5de JQ |
7752 | if (MEM_P (x) && GET_CODE (y) == SUBREG |
7753 | && MEM_P (SUBREG_REG (y)) | |
e11fa86f | 7754 | && rtx_equal_p (SUBREG_REG (y), |
4de249d9 | 7755 | gen_lowpart (GET_MODE (SUBREG_REG (y)), x))) |
e11fa86f RK |
7756 | return 1; |
7757 | ||
3c0cb5de JQ |
7758 | if (MEM_P (y) && GET_CODE (x) == SUBREG |
7759 | && MEM_P (SUBREG_REG (x)) | |
e11fa86f | 7760 | && rtx_equal_p (SUBREG_REG (x), |
4de249d9 | 7761 | gen_lowpart (GET_MODE (SUBREG_REG (x)), y))) |
e11fa86f RK |
7762 | return 1; |
7763 | ||
9ec36da5 JL |
7764 | /* We used to see if get_last_value of X and Y were the same but that's |
7765 | not correct. In one direction, we'll cause the assignment to have | |
7766 | the wrong destination and in the case, we'll import a register into this | |
7767 | insn that might have already have been dead. So fail if none of the | |
7768 | above cases are true. */ | |
7769 | return 0; | |
e11fa86f RK |
7770 | } |
7771 | \f | |
230d793d RS |
7772 | /* See if X, a SET operation, can be rewritten as a bit-field assignment. |
7773 | Return that assignment if so. | |
7774 | ||
7775 | We only handle the most common cases. */ | |
7776 | ||
7777 | static rtx | |
79a490a9 | 7778 | make_field_assignment (rtx x) |
230d793d RS |
7779 | { |
7780 | rtx dest = SET_DEST (x); | |
7781 | rtx src = SET_SRC (x); | |
dfbe1b2f | 7782 | rtx assign; |
e11fa86f | 7783 | rtx rhs, lhs; |
5f4f0e22 | 7784 | HOST_WIDE_INT c1; |
770ae6cc RK |
7785 | HOST_WIDE_INT pos; |
7786 | unsigned HOST_WIDE_INT len; | |
dfbe1b2f RK |
7787 | rtx other; |
7788 | enum machine_mode mode; | |
230d793d RS |
7789 | |
7790 | /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
7791 | a clear of a one-bit field. We will have changed it to | |
7792 | (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
7793 | for a SUBREG. */ | |
7794 | ||
7795 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
7796 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT | |
7797 | && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 | |
e11fa86f | 7798 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) |
230d793d | 7799 | { |
8999a12e | 7800 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7801 | 1, 1, 1, 0); |
76184def | 7802 | if (assign != 0) |
38a448ca | 7803 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7804 | return x; |
230d793d RS |
7805 | } |
7806 | ||
55e79aef RH |
7807 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG |
7808 | && subreg_lowpart_p (XEXP (src, 0)) | |
7809 | && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) | |
7810 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) | |
7811 | && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
7812 | && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT | |
7813 | && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 | |
7814 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
230d793d | 7815 | { |
8999a12e | 7816 | assign = make_extraction (VOIDmode, dest, 0, |
230d793d RS |
7817 | XEXP (SUBREG_REG (XEXP (src, 0)), 1), |
7818 | 1, 1, 1, 0); | |
76184def | 7819 | if (assign != 0) |
38a448ca | 7820 | return gen_rtx_SET (VOIDmode, assign, const0_rtx); |
76184def | 7821 | return x; |
230d793d RS |
7822 | } |
7823 | ||
9dd11dcb | 7824 | /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a |
230d793d | 7825 | one-bit field. */ |
55e79aef RH |
7826 | if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT |
7827 | && XEXP (XEXP (src, 0), 0) == const1_rtx | |
7828 | && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1))) | |
230d793d | 7829 | { |
8999a12e | 7830 | assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1), |
230d793d | 7831 | 1, 1, 1, 0); |
76184def | 7832 | if (assign != 0) |
38a448ca | 7833 | return gen_rtx_SET (VOIDmode, assign, const1_rtx); |
76184def | 7834 | return x; |
230d793d RS |
7835 | } |
7836 | ||
55e79aef RH |
7837 | /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the |
7838 | SRC is an AND with all bits of that field set, then we can discard | |
7839 | the AND. */ | |
7840 | if (GET_CODE (dest) == ZERO_EXTRACT | |
7841 | && GET_CODE (XEXP (dest, 1)) == CONST_INT | |
7842 | && GET_CODE (src) == AND | |
7843 | && GET_CODE (XEXP (src, 1)) == CONST_INT) | |
7844 | { | |
7845 | HOST_WIDE_INT width = INTVAL (XEXP (dest, 1)); | |
7846 | unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1)); | |
7847 | unsigned HOST_WIDE_INT ze_mask; | |
7848 | ||
7849 | if (width >= HOST_BITS_PER_WIDE_INT) | |
7850 | ze_mask = -1; | |
7851 | else | |
7852 | ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1; | |
7853 | ||
7854 | /* Complete overlap. We can remove the source AND. */ | |
7855 | if ((and_mask & ze_mask) == ze_mask) | |
7856 | return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0)); | |
7857 | ||
7858 | /* Partial overlap. We can reduce the source AND. */ | |
7859 | if ((and_mask & ze_mask) != and_mask) | |
7860 | { | |
7861 | mode = GET_MODE (src); | |
7862 | src = gen_rtx_AND (mode, XEXP (src, 0), | |
eb2ab511 | 7863 | gen_int_mode (and_mask & ze_mask, mode)); |
55e79aef RH |
7864 | return gen_rtx_SET (VOIDmode, dest, src); |
7865 | } | |
7866 | } | |
7867 | ||
dfbe1b2f | 7868 | /* The other case we handle is assignments into a constant-position |
9dd11dcb | 7869 | field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents |
dfbe1b2f RK |
7870 | a mask that has all one bits except for a group of zero bits and |
7871 | OTHER is known to have zeros where C1 has ones, this is such an | |
7872 | assignment. Compute the position and length from C1. Shift OTHER | |
7873 | to the appropriate position, force it to the required mode, and | |
7874 | make the extraction. Check for the AND in both operands. */ | |
7875 | ||
9dd11dcb | 7876 | if (GET_CODE (src) != IOR && GET_CODE (src) != XOR) |
e11fa86f RK |
7877 | return x; |
7878 | ||
7879 | rhs = expand_compound_operation (XEXP (src, 0)); | |
7880 | lhs = expand_compound_operation (XEXP (src, 1)); | |
7881 | ||
7882 | if (GET_CODE (rhs) == AND | |
7883 | && GET_CODE (XEXP (rhs, 1)) == CONST_INT | |
7884 | && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest)) | |
7885 | c1 = INTVAL (XEXP (rhs, 1)), other = lhs; | |
7886 | else if (GET_CODE (lhs) == AND | |
7887 | && GET_CODE (XEXP (lhs, 1)) == CONST_INT | |
7888 | && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest)) | |
7889 | c1 = INTVAL (XEXP (lhs, 1)), other = rhs; | |
dfbe1b2f RK |
7890 | else |
7891 | return x; | |
230d793d | 7892 | |
663522cb | 7893 | pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len); |
dfbe1b2f | 7894 | if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) |
e5e809f4 JL |
7895 | || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT |
7896 | || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0) | |
dfbe1b2f | 7897 | return x; |
230d793d | 7898 | |
5f4f0e22 | 7899 | assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0); |
76184def DE |
7900 | if (assign == 0) |
7901 | return x; | |
230d793d | 7902 | |
dfbe1b2f RK |
7903 | /* The mode to use for the source is the mode of the assignment, or of |
7904 | what is inside a possible STRICT_LOW_PART. */ | |
663522cb | 7905 | mode = (GET_CODE (assign) == STRICT_LOW_PART |
dfbe1b2f | 7906 | ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); |
230d793d | 7907 | |
dfbe1b2f RK |
7908 | /* Shift OTHER right POS places and make it the source, restricting it |
7909 | to the proper length and mode. */ | |
230d793d | 7910 | |
5f4f0e22 CH |
7911 | src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT, |
7912 | GET_MODE (src), other, pos), | |
6139ff20 RK |
7913 | mode, |
7914 | GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT | |
0345195a | 7915 | ? ~(unsigned HOST_WIDE_INT) 0 |
729a2125 | 7916 | : ((unsigned HOST_WIDE_INT) 1 << len) - 1, |
e3d616e3 | 7917 | dest, 0); |
230d793d | 7918 | |
6e814b8d KH |
7919 | /* If SRC is masked by an AND that does not make a difference in |
7920 | the value being stored, strip it. */ | |
7921 | if (GET_CODE (assign) == ZERO_EXTRACT | |
7922 | && GET_CODE (XEXP (assign, 1)) == CONST_INT | |
7923 | && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT | |
7924 | && GET_CODE (src) == AND | |
7925 | && GET_CODE (XEXP (src, 1)) == CONST_INT | |
c5c15353 | 7926 | && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1)) |
6e814b8d KH |
7927 | == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)) |
7928 | src = XEXP (src, 0); | |
7929 | ||
f1c6ba8b | 7930 | return gen_rtx_SET (VOIDmode, assign, src); |
230d793d RS |
7931 | } |
7932 | \f | |
7933 | /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
7934 | if so. */ | |
7935 | ||
7936 | static rtx | |
79a490a9 | 7937 | apply_distributive_law (rtx x) |
230d793d RS |
7938 | { |
7939 | enum rtx_code code = GET_CODE (x); | |
2981fafe | 7940 | enum rtx_code inner_code; |
230d793d RS |
7941 | rtx lhs, rhs, other; |
7942 | rtx tem; | |
230d793d | 7943 | |
2981fafe RS |
7944 | /* Distributivity is not true for floating point as it can change the |
7945 | value. So we don't do it unless -funsafe-math-optimizations. */ | |
7946 | if (FLOAT_MODE_P (GET_MODE (x)) | |
7947 | && ! flag_unsafe_math_optimizations) | |
d8a8a4da RS |
7948 | return x; |
7949 | ||
230d793d RS |
7950 | /* The outer operation can only be one of the following: */ |
7951 | if (code != IOR && code != AND && code != XOR | |
7952 | && code != PLUS && code != MINUS) | |
7953 | return x; | |
7954 | ||
2981fafe RS |
7955 | lhs = XEXP (x, 0); |
7956 | rhs = XEXP (x, 1); | |
230d793d | 7957 | |
0f41302f MS |
7958 | /* If either operand is a primitive we can't do anything, so get out |
7959 | fast. */ | |
ec8e098d | 7960 | if (OBJECT_P (lhs) || OBJECT_P (rhs)) |
230d793d RS |
7961 | return x; |
7962 | ||
7963 | lhs = expand_compound_operation (lhs); | |
7964 | rhs = expand_compound_operation (rhs); | |
7965 | inner_code = GET_CODE (lhs); | |
7966 | if (inner_code != GET_CODE (rhs)) | |
7967 | return x; | |
7968 | ||
7969 | /* See if the inner and outer operations distribute. */ | |
7970 | switch (inner_code) | |
7971 | { | |
7972 | case LSHIFTRT: | |
7973 | case ASHIFTRT: | |
7974 | case AND: | |
7975 | case IOR: | |
7976 | /* These all distribute except over PLUS. */ | |
7977 | if (code == PLUS || code == MINUS) | |
7978 | return x; | |
7979 | break; | |
7980 | ||
7981 | case MULT: | |
7982 | if (code != PLUS && code != MINUS) | |
7983 | return x; | |
7984 | break; | |
7985 | ||
7986 | case ASHIFT: | |
45620ed4 | 7987 | /* This is also a multiply, so it distributes over everything. */ |
230d793d RS |
7988 | break; |
7989 | ||
7990 | case SUBREG: | |
dfbe1b2f | 7991 | /* Non-paradoxical SUBREGs distributes over all operations, provided |
ddef6bc7 | 7992 | the inner modes and byte offsets are the same, this is an extraction |
2b4bd1bc JW |
7993 | of a low-order part, we don't convert an fp operation to int or |
7994 | vice versa, and we would not be converting a single-word | |
dfbe1b2f | 7995 | operation into a multi-word operation. The latter test is not |
2b4bd1bc | 7996 | required, but it prevents generating unneeded multi-word operations. |
dfbe1b2f RK |
7997 | Some of the previous tests are redundant given the latter test, but |
7998 | are retained because they are required for correctness. | |
7999 | ||
8000 | We produce the result slightly differently in this case. */ | |
8001 | ||
8002 | if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) | |
ddef6bc7 | 8003 | || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs) |
dfbe1b2f | 8004 | || ! subreg_lowpart_p (lhs) |
2b4bd1bc JW |
8005 | || (GET_MODE_CLASS (GET_MODE (lhs)) |
8006 | != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) | |
dfbe1b2f | 8007 | || (GET_MODE_SIZE (GET_MODE (lhs)) |
8af24e26 | 8008 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) |
dfbe1b2f | 8009 | || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) |
230d793d RS |
8010 | return x; |
8011 | ||
bcb34aa3 PB |
8012 | tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)), |
8013 | SUBREG_REG (lhs), SUBREG_REG (rhs)); | |
4de249d9 | 8014 | return gen_lowpart (GET_MODE (x), tem); |
230d793d RS |
8015 | |
8016 | default: | |
8017 | return x; | |
8018 | } | |
8019 | ||
8020 | /* Set LHS and RHS to the inner operands (A and B in the example | |
8021 | above) and set OTHER to the common operand (C in the example). | |
ec8e098d | 8022 | There is only one way to do this unless the inner operation is |
230d793d | 8023 | commutative. */ |
ec8e098d | 8024 | if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8025 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) |
8026 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
ec8e098d | 8027 | else if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8028 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) |
8029 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
ec8e098d | 8030 | else if (COMMUTATIVE_ARITH_P (lhs) |
230d793d RS |
8031 | && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) |
8032 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
8033 | else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
8034 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
8035 | else | |
8036 | return x; | |
8037 | ||
8038 | /* Form the new inner operation, seeing if it simplifies first. */ | |
bcb34aa3 | 8039 | tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs); |
230d793d RS |
8040 | |
8041 | /* There is one exception to the general way of distributing: | |
a0209ac2 | 8042 | (a | c) ^ (b | c) -> (a ^ b) & ~c */ |
230d793d RS |
8043 | if (code == XOR && inner_code == IOR) |
8044 | { | |
8045 | inner_code = AND; | |
f1c6ba8b | 8046 | other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x)); |
230d793d RS |
8047 | } |
8048 | ||
8049 | /* We may be able to continuing distributing the result, so call | |
8050 | ourselves recursively on the inner operation before forming the | |
8051 | outer operation, which we return. */ | |
bcb34aa3 PB |
8052 | return simplify_gen_binary (inner_code, GET_MODE (x), |
8053 | apply_distributive_law (tem), other); | |
8054 | } | |
8055 | ||
8056 | /* See if X is of the form (* (+ A B) C), and if so convert to | |
8057 | (+ (* A C) (* B C)) and try to simplify. | |
8058 | ||
8059 | Most of the time, this results in no change. However, if some of | |
8060 | the operands are the same or inverses of each other, simplifications | |
8061 | will result. | |
8062 | ||
8063 | For example, (and (ior A B) (not B)) can occur as the result of | |
8064 | expanding a bit field assignment. When we apply the distributive | |
8065 | law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
8066 | which then simplifies to (and (A (not B))). | |
8067 | ||
8068 | Note that no checks happen on the validity of applying the inverse | |
8069 | distributive law. This is pointless since we can do it in the | |
8070 | few places where this routine is called. | |
8071 | ||
8072 | N is the index of the term that is decomposed (the arithmetic operation, | |
8073 | i.e. (+ A B) in the first example above). !N is the index of the term that | |
8074 | is distributed, i.e. of C in the first example above. */ | |
8075 | static rtx | |
8076 | distribute_and_simplify_rtx (rtx x, int n) | |
8077 | { | |
8078 | enum machine_mode mode; | |
8079 | enum rtx_code outer_code, inner_code; | |
8080 | rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp; | |
8081 | ||
8082 | decomposed = XEXP (x, n); | |
8083 | if (!ARITHMETIC_P (decomposed)) | |
8084 | return NULL_RTX; | |
8085 | ||
8086 | mode = GET_MODE (x); | |
8087 | outer_code = GET_CODE (x); | |
8088 | distributed = XEXP (x, !n); | |
8089 | ||
8090 | inner_code = GET_CODE (decomposed); | |
8091 | inner_op0 = XEXP (decomposed, 0); | |
8092 | inner_op1 = XEXP (decomposed, 1); | |
8093 | ||
8094 | /* Special case (and (xor B C) (not A)), which is equivalent to | |
8095 | (xor (ior A B) (ior A C)) */ | |
8096 | if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT) | |
8097 | { | |
8098 | distributed = XEXP (distributed, 0); | |
8099 | outer_code = IOR; | |
8100 | } | |
8101 | ||
8102 | if (n == 0) | |
8103 | { | |
8104 | /* Distribute the second term. */ | |
8105 | new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed); | |
8106 | new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed); | |
8107 | } | |
8108 | else | |
8109 | { | |
8110 | /* Distribute the first term. */ | |
8111 | new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0); | |
8112 | new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1); | |
8113 | } | |
8114 | ||
8115 | tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode, | |
8116 | new_op0, new_op1)); | |
8117 | if (GET_CODE (tmp) != outer_code | |
8118 | && rtx_cost (tmp, SET) < rtx_cost (x, SET)) | |
8119 | return tmp; | |
8120 | ||
8121 | return NULL_RTX; | |
230d793d RS |
8122 | } |
8123 | \f | |
8124 | /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
8125 | in MODE. | |
8126 | ||
8127 | Return an equivalent form, if different from X. Otherwise, return X. If | |
8128 | X is zero, we are to always construct the equivalent form. */ | |
8129 | ||
8130 | static rtx | |
79a490a9 AJ |
8131 | simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop, |
8132 | unsigned HOST_WIDE_INT constop) | |
230d793d | 8133 | { |
951553af | 8134 | unsigned HOST_WIDE_INT nonzero; |
42301240 | 8135 | int i; |
230d793d | 8136 | |
6139ff20 | 8137 | /* Simplify VAROP knowing that we will be only looking at some of the |
8bc52806 JL |
8138 | bits in it. |
8139 | ||
8140 | Note by passing in CONSTOP, we guarantee that the bits not set in | |
8141 | CONSTOP are not significant and will never be examined. We must | |
8142 | ensure that is the case by explicitly masking out those bits | |
8143 | before returning. */ | |
e3d616e3 | 8144 | varop = force_to_mode (varop, mode, constop, NULL_RTX, 0); |
230d793d | 8145 | |
8bc52806 JL |
8146 | /* If VAROP is a CLOBBER, we will fail so return it. */ |
8147 | if (GET_CODE (varop) == CLOBBER) | |
6139ff20 | 8148 | return varop; |
230d793d | 8149 | |
8bc52806 JL |
8150 | /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP |
8151 | to VAROP and return the new constant. */ | |
8152 | if (GET_CODE (varop) == CONST_INT) | |
bb80db7b | 8153 | return gen_int_mode (INTVAL (varop) & constop, mode); |
8bc52806 | 8154 | |
fc06d7aa RK |
8155 | /* See what bits may be nonzero in VAROP. Unlike the general case of |
8156 | a call to nonzero_bits, here we don't care about bits outside | |
8157 | MODE. */ | |
8158 | ||
8159 | nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode); | |
9fa6d012 | 8160 | |
230d793d | 8161 | /* Turn off all bits in the constant that are known to already be zero. |
951553af | 8162 | Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS |
230d793d RS |
8163 | which is tested below. */ |
8164 | ||
951553af | 8165 | constop &= nonzero; |
230d793d RS |
8166 | |
8167 | /* If we don't have any bits left, return zero. */ | |
8168 | if (constop == 0) | |
8169 | return const0_rtx; | |
8170 | ||
42301240 | 8171 | /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is |
e0a2f705 | 8172 | a power of two, we can replace this with an ASHIFT. */ |
42301240 RK |
8173 | if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1 |
8174 | && (i = exact_log2 (constop)) >= 0) | |
8175 | return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i); | |
663522cb | 8176 | |
6139ff20 RK |
8177 | /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR |
8178 | or XOR, then try to apply the distributive law. This may eliminate | |
8179 | operations if either branch can be simplified because of the AND. | |
8180 | It may also make some cases more complex, but those cases probably | |
8181 | won't match a pattern either with or without this. */ | |
8182 | ||
8183 | if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR) | |
8184 | return | |
4de249d9 | 8185 | gen_lowpart |
6139ff20 RK |
8186 | (mode, |
8187 | apply_distributive_law | |
bcb34aa3 PB |
8188 | (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop), |
8189 | simplify_and_const_int (NULL_RTX, | |
8190 | GET_MODE (varop), | |
8191 | XEXP (varop, 0), | |
8192 | constop), | |
8193 | simplify_and_const_int (NULL_RTX, | |
8194 | GET_MODE (varop), | |
8195 | XEXP (varop, 1), | |
8196 | constop)))); | |
6139ff20 | 8197 | |
8deb7514 RH |
8198 | /* If VAROP is PLUS, and the constant is a mask of low bite, distribute |
8199 | the AND and see if one of the operands simplifies to zero. If so, we | |
8200 | may eliminate it. */ | |
8201 | ||
8202 | if (GET_CODE (varop) == PLUS | |
8203 | && exact_log2 (constop + 1) >= 0) | |
8204 | { | |
8205 | rtx o0, o1; | |
8206 | ||
8207 | o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop); | |
8208 | o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop); | |
8209 | if (o0 == const0_rtx) | |
8210 | return o1; | |
8211 | if (o1 == const0_rtx) | |
8212 | return o0; | |
8213 | } | |
8214 | ||
230d793d RS |
8215 | /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG |
8216 | if we already had one (just check for the simplest cases). */ | |
8217 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
8218 | && GET_MODE (XEXP (x, 0)) == mode | |
8219 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
8220 | varop = XEXP (x, 0); | |
8221 | else | |
4de249d9 | 8222 | varop = gen_lowpart (mode, varop); |
230d793d | 8223 | |
0f41302f | 8224 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
8225 | if (GET_CODE (varop) == CLOBBER) |
8226 | return x ? x : varop; | |
8227 | ||
8228 | /* If we are only masking insignificant bits, return VAROP. */ | |
951553af | 8229 | if (constop == nonzero) |
230d793d | 8230 | x = varop; |
230d793d RS |
8231 | else |
8232 | { | |
d0c9db30 | 8233 | /* Otherwise, return an AND. */ |
3b5708e7 | 8234 | constop = trunc_int_for_mode (constop, mode); |
d0c9db30 AM |
8235 | /* See how much, if any, of X we can use. */ |
8236 | if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) | |
bcb34aa3 | 8237 | x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop)); |
230d793d | 8238 | |
d0c9db30 AM |
8239 | else |
8240 | { | |
8241 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
8242 | || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop) | |
8243 | SUBST (XEXP (x, 1), GEN_INT (constop)); | |
8244 | ||
8245 | SUBST (XEXP (x, 0), varop); | |
8246 | } | |
230d793d RS |
8247 | } |
8248 | ||
8249 | return x; | |
8250 | } | |
8251 | \f | |
2f93eea8 | 8252 | /* Given a REG, X, compute which bits in X can be nonzero. |
230d793d RS |
8253 | We don't care about bits outside of those defined in MODE. |
8254 | ||
8255 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
8256 | a shift, AND, or zero_extract, we can do better. */ | |
8257 | ||
2f93eea8 PB |
8258 | static rtx |
8259 | reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode, | |
8260 | rtx known_x ATTRIBUTE_UNUSED, | |
8261 | enum machine_mode known_mode ATTRIBUTE_UNUSED, | |
8262 | unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED, | |
8263 | unsigned HOST_WIDE_INT *nonzero) | |
230d793d | 8264 | { |
230d793d RS |
8265 | rtx tem; |
8266 | ||
2f93eea8 PB |
8267 | /* If X is a register whose nonzero bits value is current, use it. |
8268 | Otherwise, if X is a register whose value we can find, use that | |
8269 | value. Otherwise, use the previously-computed global nonzero bits | |
8270 | for this register. */ | |
8271 | ||
8272 | if (reg_stat[REGNO (x)].last_set_value != 0 | |
8273 | && (reg_stat[REGNO (x)].last_set_mode == mode | |
8274 | || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT | |
8275 | && GET_MODE_CLASS (mode) == MODE_INT)) | |
8276 | && (reg_stat[REGNO (x)].last_set_label == label_tick | |
8277 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8278 | && REG_N_SETS (REGNO (x)) == 1 | |
8279 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, | |
8280 | REGNO (x)))) | |
8281 | && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) | |
230d793d | 8282 | { |
2f93eea8 PB |
8283 | *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits; |
8284 | return NULL; | |
230d793d RS |
8285 | } |
8286 | ||
2f93eea8 | 8287 | tem = get_last_value (x); |
230d793d | 8288 | |
2f93eea8 | 8289 | if (tem) |
0840fd91 | 8290 | { |
9afa3d54 | 8291 | #ifdef SHORT_IMMEDIATES_SIGN_EXTEND |
2f93eea8 PB |
8292 | /* If X is narrower than MODE and TEM is a non-negative |
8293 | constant that would appear negative in the mode of X, | |
8294 | sign-extend it for use in reg_nonzero_bits because some | |
8295 | machines (maybe most) will actually do the sign-extension | |
8296 | and this is the conservative approach. | |
8297 | ||
8298 | ??? For 2.5, try to tighten up the MD files in this regard | |
8299 | instead of this kludge. */ | |
8300 | ||
8301 | if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode) | |
8302 | && GET_CODE (tem) == CONST_INT | |
8303 | && INTVAL (tem) > 0 | |
8304 | && 0 != (INTVAL (tem) | |
8305 | & ((HOST_WIDE_INT) 1 | |
8306 | << (GET_MODE_BITSIZE (GET_MODE (x)) - 1)))) | |
8307 | tem = GEN_INT (INTVAL (tem) | |
8308 | | ((HOST_WIDE_INT) (-1) | |
8309 | << GET_MODE_BITSIZE (GET_MODE (x)))); | |
230d793d | 8310 | #endif |
2f93eea8 | 8311 | return tem; |
230d793d | 8312 | } |
2f93eea8 | 8313 | else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits) |
8fd73754 | 8314 | { |
2f93eea8 | 8315 | unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits; |
8fd73754 | 8316 | |
2f93eea8 PB |
8317 | if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)) |
8318 | /* We don't know anything about the upper bits. */ | |
8319 | mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x)); | |
8320 | *nonzero &= mask; | |
8fd73754 AN |
8321 | } |
8322 | ||
2f93eea8 | 8323 | return NULL; |
8fd73754 AN |
8324 | } |
8325 | ||
d0ab8cd3 | 8326 | /* Return the number of bits at the high-order end of X that are known to |
5109d49f RK |
8327 | be equal to the sign bit. X will be used in mode MODE; if MODE is |
8328 | VOIDmode, X will be used in its own mode. The returned value will always | |
8329 | be between 1 and the number of bits in MODE. */ | |
d0ab8cd3 | 8330 | |
2f93eea8 PB |
8331 | static rtx |
8332 | reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode, | |
8333 | rtx known_x ATTRIBUTE_UNUSED, | |
8334 | enum machine_mode known_mode | |
8335 | ATTRIBUTE_UNUSED, | |
8336 | unsigned int known_ret ATTRIBUTE_UNUSED, | |
8337 | unsigned int *result) | |
d0ab8cd3 | 8338 | { |
d0ab8cd3 RK |
8339 | rtx tem; |
8340 | ||
2f93eea8 PB |
8341 | if (reg_stat[REGNO (x)].last_set_value != 0 |
8342 | && reg_stat[REGNO (x)].last_set_mode == mode | |
8343 | && (reg_stat[REGNO (x)].last_set_label == label_tick | |
8344 | || (REGNO (x) >= FIRST_PSEUDO_REGISTER | |
8345 | && REG_N_SETS (REGNO (x)) == 1 | |
8346 | && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, | |
8347 | REGNO (x)))) | |
8348 | && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid) | |
770ae6cc | 8349 | { |
2f93eea8 PB |
8350 | *result = reg_stat[REGNO (x)].last_set_sign_bit_copies; |
8351 | return NULL; | |
d0ab8cd3 RK |
8352 | } |
8353 | ||
2f93eea8 PB |
8354 | tem = get_last_value (x); |
8355 | if (tem != 0) | |
8356 | return tem; | |
d0ab8cd3 | 8357 | |
2f93eea8 PB |
8358 | if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0 |
8359 | && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode)) | |
8360 | *result = reg_stat[REGNO (x)].sign_bit_copies; | |
8361 | ||
8362 | return NULL; | |
d0ab8cd3 RK |
8363 | } |
8364 | \f | |
1a26b032 RK |
8365 | /* Return the number of "extended" bits there are in X, when interpreted |
8366 | as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For | |
8367 | unsigned quantities, this is the number of high-order zero bits. | |
8368 | For signed quantities, this is the number of copies of the sign bit | |
8369 | minus 1. In both case, this function returns the number of "spare" | |
8370 | bits. For example, if two quantities for which this function returns | |
8371 | at least 1 are added, the addition is known not to overflow. | |
8372 | ||
8373 | This function will always return 0 unless called during combine, which | |
8374 | implies that it must be called from a define_split. */ | |
8375 | ||
770ae6cc | 8376 | unsigned int |
79a490a9 | 8377 | extended_count (rtx x, enum machine_mode mode, int unsignedp) |
1a26b032 | 8378 | { |
951553af | 8379 | if (nonzero_sign_valid == 0) |
1a26b032 RK |
8380 | return 0; |
8381 | ||
8382 | return (unsignedp | |
ac49a949 | 8383 | ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
26c34780 RS |
8384 | ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1 |
8385 | - floor_log2 (nonzero_bits (x, mode))) | |
770ae6cc | 8386 | : 0) |
1a26b032 RK |
8387 | : num_sign_bit_copies (x, mode) - 1); |
8388 | } | |
8389 | \f | |
230d793d RS |
8390 | /* This function is called from `simplify_shift_const' to merge two |
8391 | outer operations. Specifically, we have already found that we need | |
8392 | to perform operation *POP0 with constant *PCONST0 at the outermost | |
8393 | position. We would now like to also perform OP1 with constant CONST1 | |
8394 | (with *POP0 being done last). | |
8395 | ||
8396 | Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
663522cb | 8397 | the resulting operation. *PCOMP_P is set to 1 if we would need to |
230d793d RS |
8398 | complement the innermost operand, otherwise it is unchanged. |
8399 | ||
8400 | MODE is the mode in which the operation will be done. No bits outside | |
8401 | the width of this mode matter. It is assumed that the width of this mode | |
5f4f0e22 | 8402 | is smaller than or equal to HOST_BITS_PER_WIDE_INT. |
230d793d | 8403 | |
f822d252 | 8404 | If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS, |
230d793d RS |
8405 | IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper |
8406 | result is simply *PCONST0. | |
8407 | ||
8408 | If the resulting operation cannot be expressed as one operation, we | |
8409 | return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
8410 | ||
8411 | static int | |
79a490a9 | 8412 | merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p) |
230d793d RS |
8413 | { |
8414 | enum rtx_code op0 = *pop0; | |
5f4f0e22 | 8415 | HOST_WIDE_INT const0 = *pconst0; |
230d793d RS |
8416 | |
8417 | const0 &= GET_MODE_MASK (mode); | |
8418 | const1 &= GET_MODE_MASK (mode); | |
8419 | ||
8420 | /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
8421 | if (op0 == AND) | |
8422 | const1 &= const0; | |
8423 | ||
f822d252 | 8424 | /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or |
230d793d RS |
8425 | if OP0 is SET. */ |
8426 | ||
f822d252 | 8427 | if (op1 == UNKNOWN || op0 == SET) |
230d793d RS |
8428 | return 1; |
8429 | ||
f822d252 | 8430 | else if (op0 == UNKNOWN) |
230d793d RS |
8431 | op0 = op1, const0 = const1; |
8432 | ||
8433 | else if (op0 == op1) | |
8434 | { | |
8435 | switch (op0) | |
8436 | { | |
8437 | case AND: | |
8438 | const0 &= const1; | |
8439 | break; | |
8440 | case IOR: | |
8441 | const0 |= const1; | |
8442 | break; | |
8443 | case XOR: | |
8444 | const0 ^= const1; | |
8445 | break; | |
8446 | case PLUS: | |
8447 | const0 += const1; | |
8448 | break; | |
8449 | case NEG: | |
f822d252 | 8450 | op0 = UNKNOWN; |
230d793d | 8451 | break; |
e9a25f70 JL |
8452 | default: |
8453 | break; | |
230d793d RS |
8454 | } |
8455 | } | |
8456 | ||
8457 | /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
8458 | else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
8459 | return 0; | |
8460 | ||
8461 | /* If the two constants aren't the same, we can't do anything. The | |
8462 | remaining six cases can all be done. */ | |
8463 | else if (const0 != const1) | |
8464 | return 0; | |
8465 | ||
8466 | else | |
8467 | switch (op0) | |
8468 | { | |
8469 | case IOR: | |
8470 | if (op1 == AND) | |
8471 | /* (a & b) | b == b */ | |
8472 | op0 = SET; | |
8473 | else /* op1 == XOR */ | |
8474 | /* (a ^ b) | b == a | b */ | |
b729186a | 8475 | {;} |
230d793d RS |
8476 | break; |
8477 | ||
8478 | case XOR: | |
8479 | if (op1 == AND) | |
8480 | /* (a & b) ^ b == (~a) & b */ | |
8481 | op0 = AND, *pcomp_p = 1; | |
8482 | else /* op1 == IOR */ | |
8483 | /* (a | b) ^ b == a & ~b */ | |
7d4444ea | 8484 | op0 = AND, const0 = ~const0; |
230d793d RS |
8485 | break; |
8486 | ||
8487 | case AND: | |
8488 | if (op1 == IOR) | |
8489 | /* (a | b) & b == b */ | |
8490 | op0 = SET; | |
8491 | else /* op1 == XOR */ | |
8492 | /* (a ^ b) & b) == (~a) & b */ | |
8493 | *pcomp_p = 1; | |
8494 | break; | |
e9a25f70 JL |
8495 | default: |
8496 | break; | |
230d793d RS |
8497 | } |
8498 | ||
8499 | /* Check for NO-OP cases. */ | |
8500 | const0 &= GET_MODE_MASK (mode); | |
8501 | if (const0 == 0 | |
8502 | && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
f822d252 | 8503 | op0 = UNKNOWN; |
230d793d RS |
8504 | else if (const0 == 0 && op0 == AND) |
8505 | op0 = SET; | |
e51712db KG |
8506 | else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode) |
8507 | && op0 == AND) | |
f822d252 | 8508 | op0 = UNKNOWN; |
230d793d | 8509 | |
7e4ce834 RH |
8510 | /* ??? Slightly redundant with the above mask, but not entirely. |
8511 | Moving this above means we'd have to sign-extend the mode mask | |
8512 | for the final test. */ | |
8513 | const0 = trunc_int_for_mode (const0, mode); | |
9fa6d012 | 8514 | |
230d793d RS |
8515 | *pop0 = op0; |
8516 | *pconst0 = const0; | |
8517 | ||
8518 | return 1; | |
8519 | } | |
8520 | \f | |
8521 | /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
da7d8304 | 8522 | The result of the shift is RESULT_MODE. X, if nonzero, is an expression |
230d793d RS |
8523 | that we started with. |
8524 | ||
8525 | The shift is normally computed in the widest mode we find in VAROP, as | |
8526 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
8527 | are ASHIFTRT and ROTATE, which are always done in their original mode, */ | |
8528 | ||
8529 | static rtx | |
79a490a9 AJ |
8530 | simplify_shift_const (rtx x, enum rtx_code code, |
8531 | enum machine_mode result_mode, rtx varop, | |
8532 | int orig_count) | |
230d793d RS |
8533 | { |
8534 | enum rtx_code orig_code = code; | |
770ae6cc RK |
8535 | unsigned int count; |
8536 | int signed_count; | |
230d793d RS |
8537 | enum machine_mode mode = result_mode; |
8538 | enum machine_mode shift_mode, tmode; | |
770ae6cc | 8539 | unsigned int mode_words |
230d793d RS |
8540 | = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; |
8541 | /* We form (outer_op (code varop count) (outer_const)). */ | |
f822d252 | 8542 | enum rtx_code outer_op = UNKNOWN; |
c4e861e8 | 8543 | HOST_WIDE_INT outer_const = 0; |
230d793d RS |
8544 | rtx const_rtx; |
8545 | int complement_p = 0; | |
8546 | rtx new; | |
8547 | ||
0051b6ca RH |
8548 | /* Make sure and truncate the "natural" shift on the way in. We don't |
8549 | want to do this inside the loop as it makes it more difficult to | |
8550 | combine shifts. */ | |
0051b6ca RH |
8551 | if (SHIFT_COUNT_TRUNCATED) |
8552 | orig_count &= GET_MODE_BITSIZE (mode) - 1; | |
0051b6ca | 8553 | |
230d793d RS |
8554 | /* If we were given an invalid count, don't do anything except exactly |
8555 | what was requested. */ | |
8556 | ||
0051b6ca | 8557 | if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode)) |
230d793d RS |
8558 | { |
8559 | if (x) | |
8560 | return x; | |
8561 | ||
0051b6ca | 8562 | return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count)); |
230d793d RS |
8563 | } |
8564 | ||
0051b6ca | 8565 | count = orig_count; |
853d8828 | 8566 | |
230d793d RS |
8567 | /* Unless one of the branches of the `if' in this loop does a `continue', |
8568 | we will `break' the loop after the `if'. */ | |
8569 | ||
8570 | while (count != 0) | |
8571 | { | |
8572 | /* If we have an operand of (clobber (const_int 0)), just return that | |
8573 | value. */ | |
8574 | if (GET_CODE (varop) == CLOBBER) | |
8575 | return varop; | |
8576 | ||
8577 | /* If we discovered we had to complement VAROP, leave. Making a NOT | |
8578 | here would cause an infinite loop. */ | |
8579 | if (complement_p) | |
8580 | break; | |
8581 | ||
abc95ed3 | 8582 | /* Convert ROTATERT to ROTATE. */ |
230d793d | 8583 | if (code == ROTATERT) |
ad9df12f IS |
8584 | { |
8585 | unsigned int bitsize = GET_MODE_BITSIZE (result_mode);; | |
8586 | code = ROTATE; | |
8587 | if (VECTOR_MODE_P (result_mode)) | |
8588 | count = bitsize / GET_MODE_NUNITS (result_mode) - count; | |
8589 | else | |
8590 | count = bitsize - count; | |
8591 | } | |
230d793d | 8592 | |
230d793d | 8593 | /* We need to determine what mode we will do the shift in. If the |
f6789c77 RK |
8594 | shift is a right shift or a ROTATE, we must always do it in the mode |
8595 | it was originally done in. Otherwise, we can do it in MODE, the | |
0f41302f | 8596 | widest mode encountered. */ |
f6789c77 RK |
8597 | shift_mode |
8598 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
8599 | ? result_mode : mode); | |
230d793d RS |
8600 | |
8601 | /* Handle cases where the count is greater than the size of the mode | |
853d8828 RH |
8602 | minus 1. For ASHIFT, use the size minus one as the count (this can |
8603 | occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
8604 | take the count modulo the size. For other shifts, the result is | |
8605 | zero. | |
230d793d RS |
8606 | |
8607 | Since these shifts are being produced by the compiler by combining | |
8608 | multiple operations, each of which are defined, we know what the | |
8609 | result is supposed to be. */ | |
663522cb | 8610 | |
26c34780 | 8611 | if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1)) |
230d793d RS |
8612 | { |
8613 | if (code == ASHIFTRT) | |
8614 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
8615 | else if (code == ROTATE || code == ROTATERT) | |
8616 | count %= GET_MODE_BITSIZE (shift_mode); | |
8617 | else | |
8618 | { | |
8619 | /* We can't simply return zero because there may be an | |
8620 | outer op. */ | |
8621 | varop = const0_rtx; | |
8622 | count = 0; | |
8623 | break; | |
8624 | } | |
8625 | } | |
8626 | ||
312def2e RK |
8627 | /* An arithmetic right shift of a quantity known to be -1 or 0 |
8628 | is a no-op. */ | |
8629 | if (code == ASHIFTRT | |
8630 | && (num_sign_bit_copies (varop, shift_mode) | |
8631 | == GET_MODE_BITSIZE (shift_mode))) | |
d0ab8cd3 | 8632 | { |
312def2e RK |
8633 | count = 0; |
8634 | break; | |
8635 | } | |
d0ab8cd3 | 8636 | |
312def2e RK |
8637 | /* If we are doing an arithmetic right shift and discarding all but |
8638 | the sign bit copies, this is equivalent to doing a shift by the | |
8639 | bitsize minus one. Convert it into that shift because it will often | |
8640 | allow other simplifications. */ | |
500c518b | 8641 | |
312def2e RK |
8642 | if (code == ASHIFTRT |
8643 | && (count + num_sign_bit_copies (varop, shift_mode) | |
8644 | >= GET_MODE_BITSIZE (shift_mode))) | |
8645 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
500c518b | 8646 | |
230d793d RS |
8647 | /* We simplify the tests below and elsewhere by converting |
8648 | ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
e0a2f705 KH |
8649 | `make_compound_operation' will convert it to an ASHIFTRT for |
8650 | those machines (such as VAX) that don't have an LSHIFTRT. */ | |
5f4f0e22 | 8651 | if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 8652 | && code == ASHIFTRT |
951553af | 8653 | && ((nonzero_bits (varop, shift_mode) |
5f4f0e22 CH |
8654 | & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1))) |
8655 | == 0)) | |
230d793d RS |
8656 | code = LSHIFTRT; |
8657 | ||
b9422b69 JH |
8658 | if (code == LSHIFTRT |
8659 | && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
8660 | && !(nonzero_bits (varop, shift_mode) >> count)) | |
2d21f7d6 | 8661 | varop = const0_rtx; |
b9422b69 JH |
8662 | if (code == ASHIFT |
8663 | && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT | |
8664 | && !((nonzero_bits (varop, shift_mode) << count) | |
8665 | & GET_MODE_MASK (shift_mode))) | |
2d21f7d6 | 8666 | varop = const0_rtx; |
b9422b69 | 8667 | |
230d793d RS |
8668 | switch (GET_CODE (varop)) |
8669 | { | |
8670 | case SIGN_EXTEND: | |
8671 | case ZERO_EXTEND: | |
8672 | case SIGN_EXTRACT: | |
8673 | case ZERO_EXTRACT: | |
8674 | new = expand_compound_operation (varop); | |
8675 | if (new != varop) | |
8676 | { | |
8677 | varop = new; | |
8678 | continue; | |
8679 | } | |
8680 | break; | |
8681 | ||
8682 | case MEM: | |
8683 | /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
8684 | minus the width of a smaller mode, we can do this with a | |
8685 | SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
8686 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
8687 | && ! mode_dependent_address_p (XEXP (varop, 0)) | |
8688 | && ! MEM_VOLATILE_P (varop) | |
8689 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
8690 | MODE_INT, 1)) != BLKmode) | |
8691 | { | |
f1ec5147 RK |
8692 | new = adjust_address_nv (varop, tmode, |
8693 | BYTES_BIG_ENDIAN ? 0 | |
8694 | : count / BITS_PER_UNIT); | |
bf49b139 | 8695 | |
f1c6ba8b RK |
8696 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
8697 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
8698 | count = 0; |
8699 | continue; | |
8700 | } | |
8701 | break; | |
8702 | ||
8703 | case USE: | |
8704 | /* Similar to the case above, except that we can only do this if | |
8705 | the resulting mode is the same as that of the underlying | |
8706 | MEM and adjust the address depending on the *bits* endianness | |
8707 | because of the way that bit-field extract insns are defined. */ | |
8708 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
8709 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
8710 | MODE_INT, 1)) != BLKmode | |
8711 | && tmode == GET_MODE (XEXP (varop, 0))) | |
8712 | { | |
f76b9db2 ILT |
8713 | if (BITS_BIG_ENDIAN) |
8714 | new = XEXP (varop, 0); | |
8715 | else | |
8716 | { | |
8717 | new = copy_rtx (XEXP (varop, 0)); | |
663522cb | 8718 | SUBST (XEXP (new, 0), |
f76b9db2 ILT |
8719 | plus_constant (XEXP (new, 0), |
8720 | count / BITS_PER_UNIT)); | |
8721 | } | |
230d793d | 8722 | |
f1c6ba8b RK |
8723 | varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND |
8724 | : ZERO_EXTEND, mode, new); | |
230d793d RS |
8725 | count = 0; |
8726 | continue; | |
8727 | } | |
8728 | break; | |
8729 | ||
8730 | case SUBREG: | |
8731 | /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
8732 | the same number of words as what we've seen so far. Then store | |
8733 | the widest mode in MODE. */ | |
f9e67232 RS |
8734 | if (subreg_lowpart_p (varop) |
8735 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
8736 | > GET_MODE_SIZE (GET_MODE (varop))) | |
26c34780 RS |
8737 | && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) |
8738 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
8739 | == mode_words) | |
230d793d RS |
8740 | { |
8741 | varop = SUBREG_REG (varop); | |
8742 | if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
8743 | mode = GET_MODE (varop); | |
8744 | continue; | |
8745 | } | |
8746 | break; | |
8747 | ||
8748 | case MULT: | |
8749 | /* Some machines use MULT instead of ASHIFT because MULT | |
8750 | is cheaper. But it is still better on those machines to | |
8751 | merge two shifts into one. */ | |
8752 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8753 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
8754 | { | |
770ae6cc | 8755 | varop |
bcb34aa3 PB |
8756 | = simplify_gen_binary (ASHIFT, GET_MODE (varop), |
8757 | XEXP (varop, 0), | |
8758 | GEN_INT (exact_log2 ( | |
8759 | INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
8760 | continue; |
8761 | } | |
8762 | break; | |
8763 | ||
8764 | case UDIV: | |
8765 | /* Similar, for when divides are cheaper. */ | |
8766 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8767 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
8768 | { | |
770ae6cc | 8769 | varop |
bcb34aa3 PB |
8770 | = simplify_gen_binary (LSHIFTRT, GET_MODE (varop), |
8771 | XEXP (varop, 0), | |
8772 | GEN_INT (exact_log2 ( | |
8773 | INTVAL (XEXP (varop, 1))))); | |
230d793d RS |
8774 | continue; |
8775 | } | |
8776 | break; | |
8777 | ||
8778 | case ASHIFTRT: | |
8f8d8d6e AO |
8779 | /* If we are extracting just the sign bit of an arithmetic |
8780 | right shift, that shift is not needed. However, the sign | |
8781 | bit of a wider mode may be different from what would be | |
8782 | interpreted as the sign bit in a narrower mode, so, if | |
8783 | the result is narrower, don't discard the shift. */ | |
26c34780 RS |
8784 | if (code == LSHIFTRT |
8785 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
8f8d8d6e AO |
8786 | && (GET_MODE_BITSIZE (result_mode) |
8787 | >= GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
8788 | { |
8789 | varop = XEXP (varop, 0); | |
8790 | continue; | |
8791 | } | |
8792 | ||
0f41302f | 8793 | /* ... fall through ... */ |
230d793d RS |
8794 | |
8795 | case LSHIFTRT: | |
8796 | case ASHIFT: | |
230d793d RS |
8797 | case ROTATE: |
8798 | /* Here we have two nested shifts. The result is usually the | |
8799 | AND of a new shift with a mask. We compute the result below. */ | |
8800 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
8801 | && INTVAL (XEXP (varop, 1)) >= 0 | |
8802 | && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) | |
5f4f0e22 CH |
8803 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
8804 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d RS |
8805 | { |
8806 | enum rtx_code first_code = GET_CODE (varop); | |
770ae6cc | 8807 | unsigned int first_count = INTVAL (XEXP (varop, 1)); |
5f4f0e22 | 8808 | unsigned HOST_WIDE_INT mask; |
230d793d | 8809 | rtx mask_rtx; |
230d793d | 8810 | |
230d793d RS |
8811 | /* We have one common special case. We can't do any merging if |
8812 | the inner code is an ASHIFTRT of a smaller mode. However, if | |
8813 | we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
8814 | with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
8815 | we can convert it to | |
8816 | (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). | |
8817 | This simplifies certain SIGN_EXTEND operations. */ | |
8818 | if (code == ASHIFT && first_code == ASHIFTRT | |
26c34780 RS |
8819 | && count == (unsigned int) |
8820 | (GET_MODE_BITSIZE (result_mode) | |
8821 | - GET_MODE_BITSIZE (GET_MODE (varop)))) | |
230d793d RS |
8822 | { |
8823 | /* C3 has the low-order C1 bits zero. */ | |
663522cb | 8824 | |
5f4f0e22 | 8825 | mask = (GET_MODE_MASK (mode) |
663522cb | 8826 | & ~(((HOST_WIDE_INT) 1 << first_count) - 1)); |
230d793d | 8827 | |
5f4f0e22 | 8828 | varop = simplify_and_const_int (NULL_RTX, result_mode, |
230d793d | 8829 | XEXP (varop, 0), mask); |
5f4f0e22 | 8830 | varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode, |
230d793d RS |
8831 | varop, count); |
8832 | count = first_count; | |
8833 | code = ASHIFTRT; | |
8834 | continue; | |
8835 | } | |
663522cb | 8836 | |
d0ab8cd3 RK |
8837 | /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more |
8838 | than C1 high-order bits equal to the sign bit, we can convert | |
e0a2f705 | 8839 | this to either an ASHIFT or an ASHIFTRT depending on the |
663522cb | 8840 | two counts. |
230d793d RS |
8841 | |
8842 | We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
8843 | ||
8844 | if (code == ASHIFTRT && first_code == ASHIFT | |
8845 | && GET_MODE (varop) == shift_mode | |
d0ab8cd3 RK |
8846 | && (num_sign_bit_copies (XEXP (varop, 0), shift_mode) |
8847 | > first_count)) | |
230d793d | 8848 | { |
d0ab8cd3 | 8849 | varop = XEXP (varop, 0); |
770ae6cc RK |
8850 | |
8851 | signed_count = count - first_count; | |
8852 | if (signed_count < 0) | |
663522cb | 8853 | count = -signed_count, code = ASHIFT; |
770ae6cc RK |
8854 | else |
8855 | count = signed_count; | |
8856 | ||
d0ab8cd3 | 8857 | continue; |
230d793d RS |
8858 | } |
8859 | ||
8860 | /* There are some cases we can't do. If CODE is ASHIFTRT, | |
8861 | we can only do this if FIRST_CODE is also ASHIFTRT. | |
8862 | ||
8863 | We can't do the case when CODE is ROTATE and FIRST_CODE is | |
8864 | ASHIFTRT. | |
8865 | ||
8866 | If the mode of this shift is not the mode of the outer shift, | |
bdaae9a0 | 8867 | we can't do this if either shift is a right shift or ROTATE. |
230d793d RS |
8868 | |
8869 | Finally, we can't do any of these if the mode is too wide | |
8870 | unless the codes are the same. | |
8871 | ||
8872 | Handle the case where the shift codes are the same | |
8873 | first. */ | |
8874 | ||
8875 | if (code == first_code) | |
8876 | { | |
8877 | if (GET_MODE (varop) != result_mode | |
bdaae9a0 RK |
8878 | && (code == ASHIFTRT || code == LSHIFTRT |
8879 | || code == ROTATE)) | |
230d793d RS |
8880 | break; |
8881 | ||
8882 | count += first_count; | |
8883 | varop = XEXP (varop, 0); | |
8884 | continue; | |
8885 | } | |
8886 | ||
8887 | if (code == ASHIFTRT | |
8888 | || (code == ROTATE && first_code == ASHIFTRT) | |
5f4f0e22 | 8889 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT |
230d793d | 8890 | || (GET_MODE (varop) != result_mode |
bdaae9a0 RK |
8891 | && (first_code == ASHIFTRT || first_code == LSHIFTRT |
8892 | || first_code == ROTATE | |
230d793d RS |
8893 | || code == ROTATE))) |
8894 | break; | |
8895 | ||
8896 | /* To compute the mask to apply after the shift, shift the | |
663522cb | 8897 | nonzero bits of the inner shift the same way the |
230d793d RS |
8898 | outer shift will. */ |
8899 | ||
951553af | 8900 | mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop))); |
230d793d RS |
8901 | |
8902 | mask_rtx | |
8903 | = simplify_binary_operation (code, result_mode, mask_rtx, | |
5f4f0e22 | 8904 | GEN_INT (count)); |
663522cb | 8905 | |
230d793d RS |
8906 | /* Give up if we can't compute an outer operation to use. */ |
8907 | if (mask_rtx == 0 | |
8908 | || GET_CODE (mask_rtx) != CONST_INT | |
8909 | || ! merge_outer_ops (&outer_op, &outer_const, AND, | |
8910 | INTVAL (mask_rtx), | |
8911 | result_mode, &complement_p)) | |
8912 | break; | |
8913 | ||
8914 | /* If the shifts are in the same direction, we add the | |
8915 | counts. Otherwise, we subtract them. */ | |
770ae6cc | 8916 | signed_count = count; |
230d793d RS |
8917 | if ((code == ASHIFTRT || code == LSHIFTRT) |
8918 | == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
770ae6cc | 8919 | signed_count += first_count; |
230d793d | 8920 | else |
770ae6cc | 8921 | signed_count -= first_count; |
230d793d | 8922 | |
663522cb | 8923 | /* If COUNT is positive, the new shift is usually CODE, |
230d793d RS |
8924 | except for the two exceptions below, in which case it is |
8925 | FIRST_CODE. If the count is negative, FIRST_CODE should | |
8926 | always be used */ | |
770ae6cc | 8927 | if (signed_count > 0 |
230d793d RS |
8928 | && ((first_code == ROTATE && code == ASHIFT) |
8929 | || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
770ae6cc RK |
8930 | code = first_code, count = signed_count; |
8931 | else if (signed_count < 0) | |
663522cb | 8932 | code = first_code, count = -signed_count; |
770ae6cc RK |
8933 | else |
8934 | count = signed_count; | |
230d793d RS |
8935 | |
8936 | varop = XEXP (varop, 0); | |
8937 | continue; | |
8938 | } | |
8939 | ||
8940 | /* If we have (A << B << C) for any shift, we can convert this to | |
8941 | (A << C << B). This wins if A is a constant. Only try this if | |
8942 | B is not a constant. */ | |
8943 | ||
8944 | else if (GET_CODE (varop) == code | |
8945 | && GET_CODE (XEXP (varop, 1)) != CONST_INT | |
8946 | && 0 != (new | |
8947 | = simplify_binary_operation (code, mode, | |
8948 | XEXP (varop, 0), | |
5f4f0e22 | 8949 | GEN_INT (count)))) |
230d793d | 8950 | { |
f1c6ba8b | 8951 | varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1)); |
230d793d RS |
8952 | count = 0; |
8953 | continue; | |
8954 | } | |
8955 | break; | |
8956 | ||
8957 | case NOT: | |
8958 | /* Make this fit the case below. */ | |
f1c6ba8b RK |
8959 | varop = gen_rtx_XOR (mode, XEXP (varop, 0), |
8960 | GEN_INT (GET_MODE_MASK (mode))); | |
230d793d RS |
8961 | continue; |
8962 | ||
8963 | case IOR: | |
8964 | case AND: | |
8965 | case XOR: | |
8966 | /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
8967 | with C the size of VAROP - 1 and the shift is logical if | |
8968 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
8969 | we have an (le X 0) operation. If we have an arithmetic shift | |
8970 | and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
8971 | STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
8972 | ||
8973 | if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
8974 | && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
8975 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
8976 | && (code == LSHIFTRT || code == ASHIFTRT) | |
26c34780 RS |
8977 | && count == (unsigned int) |
8978 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
8979 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
8980 | { | |
8981 | count = 0; | |
f1c6ba8b RK |
8982 | varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1), |
8983 | const0_rtx); | |
230d793d RS |
8984 | |
8985 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 8986 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
8987 | |
8988 | continue; | |
8989 | } | |
8990 | ||
8991 | /* If we have (shift (logical)), move the logical to the outside | |
8992 | to allow it to possibly combine with another logical and the | |
8993 | shift to combine with another shift. This also canonicalizes to | |
8994 | what a ZERO_EXTRACT looks like. Also, some machines have | |
8995 | (and (shift)) insns. */ | |
8996 | ||
8997 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
39a44a4e RK |
8998 | /* We can't do this if we have (ashiftrt (xor)) and the |
8999 | constant has its sign bit set in shift_mode. */ | |
9000 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9001 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9002 | shift_mode)) | |
230d793d RS |
9003 | && (new = simplify_binary_operation (code, result_mode, |
9004 | XEXP (varop, 1), | |
5f4f0e22 | 9005 | GEN_INT (count))) != 0 |
663522cb | 9006 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9007 | && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), |
9008 | INTVAL (new), result_mode, &complement_p)) | |
9009 | { | |
9010 | varop = XEXP (varop, 0); | |
9011 | continue; | |
9012 | } | |
9013 | ||
9014 | /* If we can't do that, try to simplify the shift in each arm of the | |
9015 | logical expression, make a new logical expression, and apply | |
39a44a4e RK |
9016 | the inverse distributive law. This also can't be done |
9017 | for some (ashiftrt (xor)). */ | |
446f52f4 GS |
9018 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT |
9019 | && !(code == ASHIFTRT && GET_CODE (varop) == XOR | |
9020 | && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)), | |
9021 | shift_mode))) | |
39a44a4e RK |
9022 | { |
9023 | rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9024 | XEXP (varop, 0), count); | |
9025 | rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode, | |
9026 | XEXP (varop, 1), count); | |
230d793d | 9027 | |
bcb34aa3 PB |
9028 | varop = simplify_gen_binary (GET_CODE (varop), shift_mode, |
9029 | lhs, rhs); | |
39a44a4e | 9030 | varop = apply_distributive_law (varop); |
230d793d | 9031 | |
39a44a4e | 9032 | count = 0; |
446f52f4 | 9033 | continue; |
39a44a4e | 9034 | } |
230d793d RS |
9035 | break; |
9036 | ||
9037 | case EQ: | |
beb235f8 | 9038 | /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE |
230d793d | 9039 | says that the sign bit can be tested, FOO has mode MODE, C is |
45620ed4 RK |
9040 | GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit |
9041 | that may be nonzero. */ | |
9042 | if (code == LSHIFTRT | |
230d793d RS |
9043 | && XEXP (varop, 1) == const0_rtx |
9044 | && GET_MODE (XEXP (varop, 0)) == result_mode | |
26c34780 | 9045 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) |
5f4f0e22 | 9046 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
230d793d | 9047 | && ((STORE_FLAG_VALUE |
663522cb | 9048 | & ((HOST_WIDE_INT) 1 |
770ae6cc | 9049 | < (GET_MODE_BITSIZE (result_mode) - 1)))) |
951553af | 9050 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9051 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9052 | (HOST_WIDE_INT) 1, result_mode, | |
9053 | &complement_p)) | |
230d793d RS |
9054 | { |
9055 | varop = XEXP (varop, 0); | |
9056 | count = 0; | |
9057 | continue; | |
9058 | } | |
9059 | break; | |
9060 | ||
9061 | case NEG: | |
d0ab8cd3 RK |
9062 | /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less |
9063 | than the number of bits in the mode is equivalent to A. */ | |
26c34780 RS |
9064 | if (code == LSHIFTRT |
9065 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
951553af | 9066 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1) |
230d793d | 9067 | { |
d0ab8cd3 | 9068 | varop = XEXP (varop, 0); |
230d793d RS |
9069 | count = 0; |
9070 | continue; | |
9071 | } | |
9072 | ||
9073 | /* NEG commutes with ASHIFT since it is multiplication. Move the | |
9074 | NEG outside to allow shifts to combine. */ | |
9075 | if (code == ASHIFT | |
5f4f0e22 CH |
9076 | && merge_outer_ops (&outer_op, &outer_const, NEG, |
9077 | (HOST_WIDE_INT) 0, result_mode, | |
9078 | &complement_p)) | |
230d793d RS |
9079 | { |
9080 | varop = XEXP (varop, 0); | |
9081 | continue; | |
9082 | } | |
9083 | break; | |
9084 | ||
9085 | case PLUS: | |
d0ab8cd3 RK |
9086 | /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C |
9087 | is one less than the number of bits in the mode is | |
9088 | equivalent to (xor A 1). */ | |
26c34780 RS |
9089 | if (code == LSHIFTRT |
9090 | && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1) | |
230d793d | 9091 | && XEXP (varop, 1) == constm1_rtx |
951553af | 9092 | && nonzero_bits (XEXP (varop, 0), result_mode) == 1 |
5f4f0e22 CH |
9093 | && merge_outer_ops (&outer_op, &outer_const, XOR, |
9094 | (HOST_WIDE_INT) 1, result_mode, | |
9095 | &complement_p)) | |
230d793d RS |
9096 | { |
9097 | count = 0; | |
9098 | varop = XEXP (varop, 0); | |
9099 | continue; | |
9100 | } | |
9101 | ||
3f508eca | 9102 | /* If we have (xshiftrt (plus FOO BAR) C), and the only bits |
951553af | 9103 | that might be nonzero in BAR are those being shifted out and those |
3f508eca RK |
9104 | bits are known zero in FOO, we can replace the PLUS with FOO. |
9105 | Similarly in the other operand order. This code occurs when | |
9106 | we are computing the size of a variable-size array. */ | |
9107 | ||
9108 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9109 | && count < HOST_BITS_PER_WIDE_INT |
951553af RK |
9110 | && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0 |
9111 | && (nonzero_bits (XEXP (varop, 1), result_mode) | |
9112 | & nonzero_bits (XEXP (varop, 0), result_mode)) == 0) | |
3f508eca RK |
9113 | { |
9114 | varop = XEXP (varop, 0); | |
9115 | continue; | |
9116 | } | |
9117 | else if ((code == ASHIFTRT || code == LSHIFTRT) | |
5f4f0e22 | 9118 | && count < HOST_BITS_PER_WIDE_INT |
ac49a949 | 9119 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT |
951553af | 9120 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
3f508eca | 9121 | >> count) |
951553af RK |
9122 | && 0 == (nonzero_bits (XEXP (varop, 0), result_mode) |
9123 | & nonzero_bits (XEXP (varop, 1), | |
3f508eca RK |
9124 | result_mode))) |
9125 | { | |
9126 | varop = XEXP (varop, 1); | |
9127 | continue; | |
9128 | } | |
9129 | ||
230d793d RS |
9130 | /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ |
9131 | if (code == ASHIFT | |
9132 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9133 | && (new = simplify_binary_operation (ASHIFT, result_mode, | |
9134 | XEXP (varop, 1), | |
5f4f0e22 | 9135 | GEN_INT (count))) != 0 |
770ae6cc | 9136 | && GET_CODE (new) == CONST_INT |
230d793d RS |
9137 | && merge_outer_ops (&outer_op, &outer_const, PLUS, |
9138 | INTVAL (new), result_mode, &complement_p)) | |
9139 | { | |
9140 | varop = XEXP (varop, 0); | |
9141 | continue; | |
9142 | } | |
b757b9f8 PH |
9143 | |
9144 | /* Check for 'PLUS signbit', which is the canonical form of 'XOR | |
9145 | signbit', and attempt to change the PLUS to an XOR and move it to | |
9146 | the outer operation as is done above in the AND/IOR/XOR case | |
9147 | leg for shift(logical). See details in logical handling above | |
471854f8 | 9148 | for reasoning in doing so. */ |
b757b9f8 PH |
9149 | if (code == LSHIFTRT |
9150 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
9151 | && mode_signbit_p (result_mode, XEXP (varop, 1)) | |
9152 | && (new = simplify_binary_operation (code, result_mode, | |
9153 | XEXP (varop, 1), | |
9154 | GEN_INT (count))) != 0 | |
9155 | && GET_CODE (new) == CONST_INT | |
9156 | && merge_outer_ops (&outer_op, &outer_const, XOR, | |
9157 | INTVAL (new), result_mode, &complement_p)) | |
9158 | { | |
9159 | varop = XEXP (varop, 0); | |
9160 | continue; | |
9161 | } | |
9162 | ||
230d793d RS |
9163 | break; |
9164 | ||
9165 | case MINUS: | |
9166 | /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
9167 | with C the size of VAROP - 1 and the shift is logical if | |
9168 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
9169 | we have a (gt X 0) operation. If the shift is arithmetic with | |
9170 | STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
9171 | we have a (neg (gt X 0)) operation. */ | |
9172 | ||
0802d516 RK |
9173 | if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) |
9174 | && GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
26c34780 RS |
9175 | && count == (unsigned int) |
9176 | (GET_MODE_BITSIZE (GET_MODE (varop)) - 1) | |
230d793d RS |
9177 | && (code == LSHIFTRT || code == ASHIFTRT) |
9178 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
26c34780 RS |
9179 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1)) |
9180 | == count | |
230d793d RS |
9181 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) |
9182 | { | |
9183 | count = 0; | |
f1c6ba8b RK |
9184 | varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1), |
9185 | const0_rtx); | |
230d793d RS |
9186 | |
9187 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
f1c6ba8b | 9188 | varop = gen_rtx_NEG (GET_MODE (varop), varop); |
230d793d RS |
9189 | |
9190 | continue; | |
9191 | } | |
9192 | break; | |
6e0ef100 JC |
9193 | |
9194 | case TRUNCATE: | |
9195 | /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt)) | |
9196 | if the truncate does not affect the value. */ | |
9197 | if (code == LSHIFTRT | |
9198 | && GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
9199 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
9200 | && (INTVAL (XEXP (XEXP (varop, 0), 1)) | |
b577a8ff JL |
9201 | >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0))) |
9202 | - GET_MODE_BITSIZE (GET_MODE (varop))))) | |
6e0ef100 JC |
9203 | { |
9204 | rtx varop_inner = XEXP (varop, 0); | |
9205 | ||
770ae6cc | 9206 | varop_inner |
f1c6ba8b RK |
9207 | = gen_rtx_LSHIFTRT (GET_MODE (varop_inner), |
9208 | XEXP (varop_inner, 0), | |
9209 | GEN_INT | |
9210 | (count + INTVAL (XEXP (varop_inner, 1)))); | |
9211 | varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner); | |
6e0ef100 JC |
9212 | count = 0; |
9213 | continue; | |
9214 | } | |
9215 | break; | |
663522cb | 9216 | |
e9a25f70 JL |
9217 | default: |
9218 | break; | |
230d793d RS |
9219 | } |
9220 | ||
9221 | break; | |
9222 | } | |
9223 | ||
9224 | /* We need to determine what mode to do the shift in. If the shift is | |
f6789c77 RK |
9225 | a right shift or ROTATE, we must always do it in the mode it was |
9226 | originally done in. Otherwise, we can do it in MODE, the widest mode | |
9227 | encountered. The code we care about is that of the shift that will | |
9228 | actually be done, not the shift that was originally requested. */ | |
9229 | shift_mode | |
9230 | = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE | |
9231 | ? result_mode : mode); | |
230d793d RS |
9232 | |
9233 | /* We have now finished analyzing the shift. The result should be | |
9234 | a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
f822d252 | 9235 | OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied |
230d793d RS |
9236 | to the result of the shift. OUTER_CONST is the relevant constant, |
9237 | but we must turn off all bits turned off in the shift. | |
9238 | ||
9239 | If we were passed a value for X, see if we can use any pieces of | |
9240 | it. If not, make new rtx. */ | |
9241 | ||
ec8e098d | 9242 | if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH |
230d793d | 9243 | && GET_CODE (XEXP (x, 1)) == CONST_INT |
26c34780 | 9244 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count) |
230d793d RS |
9245 | const_rtx = XEXP (x, 1); |
9246 | else | |
5f4f0e22 | 9247 | const_rtx = GEN_INT (count); |
230d793d RS |
9248 | |
9249 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
9250 | && GET_MODE (XEXP (x, 0)) == shift_mode | |
9251 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
9252 | varop = XEXP (x, 0); | |
9253 | else if (GET_MODE (varop) != shift_mode) | |
4de249d9 | 9254 | varop = gen_lowpart (shift_mode, varop); |
230d793d | 9255 | |
0f41302f | 9256 | /* If we can't make the SUBREG, try to return what we were given. */ |
230d793d RS |
9257 | if (GET_CODE (varop) == CLOBBER) |
9258 | return x ? x : varop; | |
9259 | ||
9260 | new = simplify_binary_operation (code, shift_mode, varop, const_rtx); | |
9261 | if (new != 0) | |
9262 | x = new; | |
9263 | else | |
6c2d03d0 | 9264 | x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx); |
230d793d | 9265 | |
224eeff2 RK |
9266 | /* If we have an outer operation and we just made a shift, it is |
9267 | possible that we could have simplified the shift were it not | |
9268 | for the outer operation. So try to do the simplification | |
9269 | recursively. */ | |
9270 | ||
f822d252 | 9271 | if (outer_op != UNKNOWN && GET_CODE (x) == code |
224eeff2 RK |
9272 | && GET_CODE (XEXP (x, 1)) == CONST_INT) |
9273 | x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0), | |
9274 | INTVAL (XEXP (x, 1))); | |
9275 | ||
e0a2f705 | 9276 | /* If we were doing an LSHIFTRT in a wider mode than it was originally, |
230d793d RS |
9277 | turn off all the bits that the shift would have turned off. */ |
9278 | if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
5f4f0e22 | 9279 | x = simplify_and_const_int (NULL_RTX, shift_mode, x, |
230d793d | 9280 | GET_MODE_MASK (result_mode) >> orig_count); |
663522cb | 9281 | |
230d793d | 9282 | /* Do the remainder of the processing in RESULT_MODE. */ |
4de249d9 | 9283 | x = gen_lowpart (result_mode, x); |
230d793d RS |
9284 | |
9285 | /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
9286 | operation. */ | |
9287 | if (complement_p) | |
e869aa39 | 9288 | x = simplify_gen_unary (NOT, result_mode, x, result_mode); |
230d793d | 9289 | |
f822d252 | 9290 | if (outer_op != UNKNOWN) |
230d793d | 9291 | { |
5f4f0e22 | 9292 | if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT) |
7e4ce834 | 9293 | outer_const = trunc_int_for_mode (outer_const, result_mode); |
230d793d RS |
9294 | |
9295 | if (outer_op == AND) | |
5f4f0e22 | 9296 | x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const); |
230d793d RS |
9297 | else if (outer_op == SET) |
9298 | /* This means that we have determined that the result is | |
9299 | equivalent to a constant. This should be rare. */ | |
5f4f0e22 | 9300 | x = GEN_INT (outer_const); |
ec8e098d | 9301 | else if (GET_RTX_CLASS (outer_op) == RTX_UNARY) |
f1c6ba8b | 9302 | x = simplify_gen_unary (outer_op, result_mode, x, result_mode); |
230d793d | 9303 | else |
bcb34aa3 PB |
9304 | x = simplify_gen_binary (outer_op, result_mode, x, |
9305 | GEN_INT (outer_const)); | |
230d793d RS |
9306 | } |
9307 | ||
9308 | return x; | |
663522cb | 9309 | } |
230d793d RS |
9310 | \f |
9311 | /* Like recog, but we receive the address of a pointer to a new pattern. | |
9312 | We try to match the rtx that the pointer points to. | |
9313 | If that fails, we may try to modify or replace the pattern, | |
9314 | storing the replacement into the same pointer object. | |
9315 | ||
9316 | Modifications include deletion or addition of CLOBBERs. | |
9317 | ||
9318 | PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
9319 | the CLOBBERs are placed. | |
9320 | ||
9321 | The value is the final insn code from the pattern ultimately matched, | |
9322 | or -1. */ | |
9323 | ||
9324 | static int | |
79a490a9 | 9325 | recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes) |
230d793d | 9326 | { |
b3694847 | 9327 | rtx pat = *pnewpat; |
230d793d RS |
9328 | int insn_code_number; |
9329 | int num_clobbers_to_add = 0; | |
9330 | int i; | |
9331 | rtx notes = 0; | |
e6d83128 | 9332 | rtx old_notes, old_pat; |
230d793d | 9333 | |
974f4146 RK |
9334 | /* If PAT is a PARALLEL, check to see if it contains the CLOBBER |
9335 | we use to indicate that something didn't match. If we find such a | |
9336 | thing, force rejection. */ | |
d96023cf | 9337 | if (GET_CODE (pat) == PARALLEL) |
974f4146 | 9338 | for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) |
d96023cf RK |
9339 | if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER |
9340 | && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) | |
974f4146 RK |
9341 | return -1; |
9342 | ||
e6d83128 JH |
9343 | old_pat = PATTERN (insn); |
9344 | old_notes = REG_NOTES (insn); | |
9345 | PATTERN (insn) = pat; | |
9346 | REG_NOTES (insn) = 0; | |
c1194d74 | 9347 | |
e6d83128 | 9348 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); |
230d793d RS |
9349 | |
9350 | /* If it isn't, there is the possibility that we previously had an insn | |
9351 | that clobbered some register as a side effect, but the combined | |
9352 | insn doesn't need to do that. So try once more without the clobbers | |
9353 | unless this represents an ASM insn. */ | |
9354 | ||
9355 | if (insn_code_number < 0 && ! check_asm_operands (pat) | |
9356 | && GET_CODE (pat) == PARALLEL) | |
9357 | { | |
9358 | int pos; | |
9359 | ||
9360 | for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
9361 | if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
9362 | { | |
9363 | if (i != pos) | |
9364 | SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
9365 | pos++; | |
9366 | } | |
9367 | ||
9368 | SUBST_INT (XVECLEN (pat, 0), pos); | |
9369 | ||
9370 | if (pos == 1) | |
9371 | pat = XVECEXP (pat, 0, 0); | |
9372 | ||
e6d83128 JH |
9373 | PATTERN (insn) = pat; |
9374 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
230d793d | 9375 | } |
e6d83128 JH |
9376 | PATTERN (insn) = old_pat; |
9377 | REG_NOTES (insn) = old_notes; | |
230d793d | 9378 | |
b5832b43 JH |
9379 | /* Recognize all noop sets, these will be killed by followup pass. */ |
9380 | if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat)) | |
9381 | insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0; | |
9382 | ||
230d793d RS |
9383 | /* If we had any clobbers to add, make a new pattern than contains |
9384 | them. Then check to make sure that all of them are dead. */ | |
9385 | if (num_clobbers_to_add) | |
9386 | { | |
38a448ca | 9387 | rtx newpat = gen_rtx_PARALLEL (VOIDmode, |
bf103ec2 R |
9388 | rtvec_alloc (GET_CODE (pat) == PARALLEL |
9389 | ? (XVECLEN (pat, 0) | |
9390 | + num_clobbers_to_add) | |
9391 | : num_clobbers_to_add + 1)); | |
230d793d RS |
9392 | |
9393 | if (GET_CODE (pat) == PARALLEL) | |
9394 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
9395 | XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
9396 | else | |
9397 | XVECEXP (newpat, 0, 0) = pat; | |
9398 | ||
9399 | add_clobbers (newpat, insn_code_number); | |
9400 | ||
9401 | for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
9402 | i < XVECLEN (newpat, 0); i++) | |
9403 | { | |
f8cfc6aa | 9404 | if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)) |
230d793d RS |
9405 | && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) |
9406 | return -1; | |
38a448ca RH |
9407 | notes = gen_rtx_EXPR_LIST (REG_UNUSED, |
9408 | XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
230d793d RS |
9409 | } |
9410 | pat = newpat; | |
9411 | } | |
9412 | ||
9413 | *pnewpat = pat; | |
9414 | *pnotes = notes; | |
9415 | ||
9416 | return insn_code_number; | |
9417 | } | |
9418 | \f | |
4de249d9 PB |
9419 | /* Like gen_lowpart_general but for use by combine. In combine it |
9420 | is not possible to create any new pseudoregs. However, it is | |
9421 | safe to create invalid memory addresses, because combine will | |
9422 | try to recognize them and all they will do is make the combine | |
9423 | attempt fail. | |
230d793d RS |
9424 | |
9425 | If for some reason this cannot do its job, an rtx | |
9426 | (clobber (const_int 0)) is returned. | |
9427 | An insn containing that will not be recognized. */ | |
9428 | ||
230d793d | 9429 | static rtx |
7a32a925 | 9430 | gen_lowpart_for_combine (enum machine_mode omode, rtx x) |
230d793d | 9431 | { |
7a32a925 RH |
9432 | enum machine_mode imode = GET_MODE (x); |
9433 | unsigned int osize = GET_MODE_SIZE (omode); | |
9434 | unsigned int isize = GET_MODE_SIZE (imode); | |
230d793d RS |
9435 | rtx result; |
9436 | ||
7a32a925 | 9437 | if (omode == imode) |
230d793d RS |
9438 | return x; |
9439 | ||
7a32a925 RH |
9440 | /* Return identity if this is a CONST or symbolic reference. */ |
9441 | if (omode == Pmode | |
cafe096b EC |
9442 | && (GET_CODE (x) == CONST |
9443 | || GET_CODE (x) == SYMBOL_REF | |
9444 | || GET_CODE (x) == LABEL_REF)) | |
9445 | return x; | |
9446 | ||
eae957a8 RK |
9447 | /* We can only support MODE being wider than a word if X is a |
9448 | constant integer or has a mode the same size. */ | |
7a32a925 RH |
9449 | if (GET_MODE_SIZE (omode) > UNITS_PER_WORD |
9450 | && ! ((imode == VOIDmode | |
eae957a8 RK |
9451 | && (GET_CODE (x) == CONST_INT |
9452 | || GET_CODE (x) == CONST_DOUBLE)) | |
7a32a925 RH |
9453 | || isize == osize)) |
9454 | goto fail; | |
230d793d RS |
9455 | |
9456 | /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
9457 | won't know what to do. So we will strip off the SUBREG here and | |
9458 | process normally. */ | |
3c0cb5de | 9459 | if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x))) |
230d793d RS |
9460 | { |
9461 | x = SUBREG_REG (x); | |
32f2ce02 HPN |
9462 | |
9463 | /* For use in case we fall down into the address adjustments | |
9464 | further below, we need to adjust the known mode and size of | |
9465 | x; imode and isize, since we just adjusted x. */ | |
9466 | imode = GET_MODE (x); | |
9467 | ||
9468 | if (imode == omode) | |
230d793d | 9469 | return x; |
32f2ce02 HPN |
9470 | |
9471 | isize = GET_MODE_SIZE (imode); | |
230d793d RS |
9472 | } |
9473 | ||
7a32a925 RH |
9474 | result = gen_lowpart_common (omode, x); |
9475 | ||
cff9f8d5 | 9476 | #ifdef CANNOT_CHANGE_MODE_CLASS |
41bf2a8b RH |
9477 | if (result != 0 && GET_CODE (result) == SUBREG) |
9478 | record_subregs_of_mode (result); | |
02188693 | 9479 | #endif |
64bf47a2 | 9480 | |
230d793d RS |
9481 | if (result) |
9482 | return result; | |
9483 | ||
3c0cb5de | 9484 | if (MEM_P (x)) |
230d793d | 9485 | { |
b3694847 | 9486 | int offset = 0; |
230d793d RS |
9487 | |
9488 | /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
9489 | address. */ | |
9490 | if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) | |
7a32a925 | 9491 | goto fail; |
230d793d RS |
9492 | |
9493 | /* If we want to refer to something bigger than the original memref, | |
9a5a17f3 | 9494 | generate a paradoxical subreg instead. That will force a reload |
230d793d | 9495 | of the original memref X. */ |
7a32a925 RH |
9496 | if (isize < osize) |
9497 | return gen_rtx_SUBREG (omode, x, 0); | |
230d793d | 9498 | |
f76b9db2 | 9499 | if (WORDS_BIG_ENDIAN) |
7a32a925 | 9500 | offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD); |
c5c76735 | 9501 | |
6c6cfbfd KH |
9502 | /* Adjust the address so that the address-after-the-data is |
9503 | unchanged. */ | |
f76b9db2 | 9504 | if (BYTES_BIG_ENDIAN) |
7a32a925 | 9505 | offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize); |
f1ec5147 | 9506 | |
7a32a925 | 9507 | return adjust_address_nv (x, omode, offset); |
230d793d RS |
9508 | } |
9509 | ||
9510 | /* If X is a comparison operator, rewrite it in a new mode. This | |
9511 | probably won't match, but may allow further simplifications. */ | |
ec8e098d | 9512 | else if (COMPARISON_P (x)) |
7a32a925 | 9513 | return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1)); |
230d793d RS |
9514 | |
9515 | /* If we couldn't simplify X any other way, just enclose it in a | |
9516 | SUBREG. Normally, this SUBREG won't match, but some patterns may | |
a7c99304 | 9517 | include an explicit SUBREG or we may simplify it further in combine. */ |
230d793d | 9518 | else |
dfbe1b2f | 9519 | { |
ddef6bc7 | 9520 | int offset = 0; |
e0e08ac2 | 9521 | rtx res; |
dfbe1b2f | 9522 | |
7a32a925 RH |
9523 | offset = subreg_lowpart_offset (omode, imode); |
9524 | if (imode == VOIDmode) | |
80ba02b1 | 9525 | { |
7a32a925 RH |
9526 | imode = int_mode_for_mode (omode); |
9527 | x = gen_lowpart_common (imode, x); | |
9528 | if (x == NULL) | |
9529 | goto fail; | |
80ba02b1 | 9530 | } |
7a32a925 | 9531 | res = simplify_gen_subreg (omode, x, imode, offset); |
e0e08ac2 JH |
9532 | if (res) |
9533 | return res; | |
dfbe1b2f | 9534 | } |
7a32a925 RH |
9535 | |
9536 | fail: | |
9537 | return gen_rtx_CLOBBER (imode, const0_rtx); | |
230d793d RS |
9538 | } |
9539 | \f | |
230d793d RS |
9540 | /* Simplify a comparison between *POP0 and *POP1 where CODE is the |
9541 | comparison code that will be tested. | |
9542 | ||
9543 | The result is a possibly different comparison code to use. *POP0 and | |
9544 | *POP1 may be updated. | |
9545 | ||
9546 | It is possible that we might detect that a comparison is either always | |
9547 | true or always false. However, we do not perform general constant | |
5089e22e | 9548 | folding in combine, so this knowledge isn't useful. Such tautologies |
230d793d RS |
9549 | should have been detected earlier. Hence we ignore all such cases. */ |
9550 | ||
9551 | static enum rtx_code | |
79a490a9 | 9552 | simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) |
230d793d RS |
9553 | { |
9554 | rtx op0 = *pop0; | |
9555 | rtx op1 = *pop1; | |
9556 | rtx tem, tem1; | |
9557 | int i; | |
9558 | enum machine_mode mode, tmode; | |
9559 | ||
9560 | /* Try a few ways of applying the same transformation to both operands. */ | |
9561 | while (1) | |
9562 | { | |
3a19aabc RK |
9563 | #ifndef WORD_REGISTER_OPERATIONS |
9564 | /* The test below this one won't handle SIGN_EXTENDs on these machines, | |
9565 | so check specially. */ | |
9566 | if (code != GTU && code != GEU && code != LTU && code != LEU | |
9567 | && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT | |
9568 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
9569 | && GET_CODE (XEXP (op1, 0)) == ASHIFT | |
9570 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG | |
9571 | && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG | |
9572 | && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))) | |
ad25ba17 | 9573 | == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))) |
3a19aabc | 9574 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
fa9ea255 KH |
9575 | && XEXP (op0, 1) == XEXP (op1, 1) |
9576 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
9577 | && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1) | |
3a19aabc RK |
9578 | && (INTVAL (XEXP (op0, 1)) |
9579 | == (GET_MODE_BITSIZE (GET_MODE (op0)) | |
9580 | - (GET_MODE_BITSIZE | |
9581 | (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))))))) | |
9582 | { | |
9583 | op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0)); | |
9584 | op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0)); | |
9585 | } | |
9586 | #endif | |
9587 | ||
230d793d RS |
9588 | /* If both operands are the same constant shift, see if we can ignore the |
9589 | shift. We can if the shift is a rotate or if the bits shifted out of | |
951553af | 9590 | this shift are known to be zero for both inputs and if the type of |
230d793d | 9591 | comparison is compatible with the shift. */ |
67232b23 RK |
9592 | if (GET_CODE (op0) == GET_CODE (op1) |
9593 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT | |
9594 | && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) | |
45620ed4 | 9595 | || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT) |
67232b23 RK |
9596 | && (code != GT && code != LT && code != GE && code != LE)) |
9597 | || (GET_CODE (op0) == ASHIFTRT | |
9598 | && (code != GTU && code != LTU | |
99dc5306 | 9599 | && code != GEU && code != LEU))) |
67232b23 RK |
9600 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
9601 | && INTVAL (XEXP (op0, 1)) >= 0 | |
9602 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT | |
9603 | && XEXP (op0, 1) == XEXP (op1, 1)) | |
230d793d RS |
9604 | { |
9605 | enum machine_mode mode = GET_MODE (op0); | |
5f4f0e22 | 9606 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
9607 | int shift_count = INTVAL (XEXP (op0, 1)); |
9608 | ||
9609 | if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
9610 | mask &= (mask >> shift_count) << shift_count; | |
45620ed4 | 9611 | else if (GET_CODE (op0) == ASHIFT) |
230d793d RS |
9612 | mask = (mask & (mask << shift_count)) >> shift_count; |
9613 | ||
663522cb KH |
9614 | if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0 |
9615 | && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0) | |
230d793d RS |
9616 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); |
9617 | else | |
9618 | break; | |
9619 | } | |
9620 | ||
9621 | /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
9622 | SUBREGs are of the same mode, and, in both cases, the AND would | |
9623 | be redundant if the comparison was done in the narrower mode, | |
9624 | do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
951553af RK |
9625 | and the operand's possibly nonzero bits are 0xffffff01; in that case |
9626 | if we only care about QImode, we don't need the AND). This case | |
9627 | occurs if the output mode of an scc insn is not SImode and | |
7e4dc511 RK |
9628 | STORE_FLAG_VALUE == 1 (e.g., the 386). |
9629 | ||
9630 | Similarly, check for a case where the AND's are ZERO_EXTEND | |
9631 | operations from some narrower mode even though a SUBREG is not | |
9632 | present. */ | |
230d793d | 9633 | |
663522cb KH |
9634 | else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND |
9635 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
9636 | && GET_CODE (XEXP (op1, 1)) == CONST_INT) | |
230d793d | 9637 | { |
7e4dc511 RK |
9638 | rtx inner_op0 = XEXP (op0, 0); |
9639 | rtx inner_op1 = XEXP (op1, 0); | |
9640 | HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1)); | |
9641 | HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1)); | |
9642 | int changed = 0; | |
663522cb | 9643 | |
7e4dc511 RK |
9644 | if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG |
9645 | && (GET_MODE_SIZE (GET_MODE (inner_op0)) | |
9646 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0)))) | |
9647 | && (GET_MODE (SUBREG_REG (inner_op0)) | |
9648 | == GET_MODE (SUBREG_REG (inner_op1))) | |
729a2bc6 | 9649 | && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0))) |
7e4dc511 | 9650 | <= HOST_BITS_PER_WIDE_INT) |
01c82bbb | 9651 | && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0), |
729a2bc6 | 9652 | GET_MODE (SUBREG_REG (inner_op0))))) |
01c82bbb RK |
9653 | && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1), |
9654 | GET_MODE (SUBREG_REG (inner_op1)))))) | |
7e4dc511 RK |
9655 | { |
9656 | op0 = SUBREG_REG (inner_op0); | |
9657 | op1 = SUBREG_REG (inner_op1); | |
9658 | ||
9659 | /* The resulting comparison is always unsigned since we masked | |
0f41302f | 9660 | off the original sign bit. */ |
7e4dc511 RK |
9661 | code = unsigned_condition (code); |
9662 | ||
9663 | changed = 1; | |
9664 | } | |
230d793d | 9665 | |
7e4dc511 RK |
9666 | else if (c0 == c1) |
9667 | for (tmode = GET_CLASS_NARROWEST_MODE | |
9668 | (GET_MODE_CLASS (GET_MODE (op0))); | |
9669 | tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode)) | |
e51712db | 9670 | if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode)) |
7e4dc511 | 9671 | { |
4de249d9 PB |
9672 | op0 = gen_lowpart (tmode, inner_op0); |
9673 | op1 = gen_lowpart (tmode, inner_op1); | |
66415c8b | 9674 | code = unsigned_condition (code); |
7e4dc511 RK |
9675 | changed = 1; |
9676 | break; | |
9677 | } | |
9678 | ||
9679 | if (! changed) | |
9680 | break; | |
230d793d | 9681 | } |
3a19aabc | 9682 | |
ad25ba17 RK |
9683 | /* If both operands are NOT, we can strip off the outer operation |
9684 | and adjust the comparison code for swapped operands; similarly for | |
9685 | NEG, except that this must be an equality comparison. */ | |
9686 | else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT) | |
9687 | || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG | |
9688 | && (code == EQ || code == NE))) | |
9689 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code); | |
3a19aabc | 9690 | |
230d793d RS |
9691 | else |
9692 | break; | |
9693 | } | |
663522cb | 9694 | |
230d793d | 9695 | /* If the first operand is a constant, swap the operands and adjust the |
3aceff0d RK |
9696 | comparison code appropriately, but don't do this if the second operand |
9697 | is already a constant integer. */ | |
8c9864f3 | 9698 | if (swap_commutative_operands_p (op0, op1)) |
230d793d RS |
9699 | { |
9700 | tem = op0, op0 = op1, op1 = tem; | |
9701 | code = swap_condition (code); | |
9702 | } | |
9703 | ||
9704 | /* We now enter a loop during which we will try to simplify the comparison. | |
9705 | For the most part, we only are concerned with comparisons with zero, | |
9706 | but some things may really be comparisons with zero but not start | |
9707 | out looking that way. */ | |
9708 | ||
9709 | while (GET_CODE (op1) == CONST_INT) | |
9710 | { | |
9711 | enum machine_mode mode = GET_MODE (op0); | |
770ae6cc | 9712 | unsigned int mode_width = GET_MODE_BITSIZE (mode); |
5f4f0e22 | 9713 | unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode); |
230d793d RS |
9714 | int equality_comparison_p; |
9715 | int sign_bit_comparison_p; | |
9716 | int unsigned_comparison_p; | |
5f4f0e22 | 9717 | HOST_WIDE_INT const_op; |
230d793d RS |
9718 | |
9719 | /* We only want to handle integral modes. This catches VOIDmode, | |
9720 | CCmode, and the floating-point modes. An exception is that we | |
9721 | can handle VOIDmode if OP0 is a COMPARE or a comparison | |
9722 | operation. */ | |
9723 | ||
9724 | if (GET_MODE_CLASS (mode) != MODE_INT | |
9725 | && ! (mode == VOIDmode | |
ec8e098d | 9726 | && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0)))) |
230d793d RS |
9727 | break; |
9728 | ||
9729 | /* Get the constant we are comparing against and turn off all bits | |
9730 | not on in our mode. */ | |
71012d97 GK |
9731 | const_op = INTVAL (op1); |
9732 | if (mode != VOIDmode) | |
9733 | const_op = trunc_int_for_mode (const_op, mode); | |
b4fbaca7 | 9734 | op1 = GEN_INT (const_op); |
230d793d RS |
9735 | |
9736 | /* If we are comparing against a constant power of two and the value | |
951553af | 9737 | being compared can only have that single bit nonzero (e.g., it was |
230d793d RS |
9738 | `and'ed with that bit), we can replace this with a comparison |
9739 | with zero. */ | |
9740 | if (const_op | |
9741 | && (code == EQ || code == NE || code == GE || code == GEU | |
9742 | || code == LT || code == LTU) | |
5f4f0e22 | 9743 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 9744 | && exact_log2 (const_op) >= 0 |
e51712db | 9745 | && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op) |
230d793d RS |
9746 | { |
9747 | code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
9748 | op1 = const0_rtx, const_op = 0; | |
9749 | } | |
9750 | ||
d0ab8cd3 RK |
9751 | /* Similarly, if we are comparing a value known to be either -1 or |
9752 | 0 with -1, change it to the opposite comparison against zero. */ | |
9753 | ||
9754 | if (const_op == -1 | |
9755 | && (code == EQ || code == NE || code == GT || code == LE | |
9756 | || code == GEU || code == LTU) | |
9757 | && num_sign_bit_copies (op0, mode) == mode_width) | |
9758 | { | |
9759 | code = (code == EQ || code == LE || code == GEU ? NE : EQ); | |
9760 | op1 = const0_rtx, const_op = 0; | |
9761 | } | |
9762 | ||
230d793d | 9763 | /* Do some canonicalizations based on the comparison code. We prefer |
663522cb | 9764 | comparisons against zero and then prefer equality comparisons. |
4803a34a | 9765 | If we can reduce the size of a constant, we will do that too. */ |
230d793d RS |
9766 | |
9767 | switch (code) | |
9768 | { | |
9769 | case LT: | |
4803a34a RK |
9770 | /* < C is equivalent to <= (C - 1) */ |
9771 | if (const_op > 0) | |
230d793d | 9772 | { |
4803a34a | 9773 | const_op -= 1; |
5f4f0e22 | 9774 | op1 = GEN_INT (const_op); |
230d793d RS |
9775 | code = LE; |
9776 | /* ... fall through to LE case below. */ | |
9777 | } | |
9778 | else | |
9779 | break; | |
9780 | ||
9781 | case LE: | |
4803a34a RK |
9782 | /* <= C is equivalent to < (C + 1); we do this for C < 0 */ |
9783 | if (const_op < 0) | |
9784 | { | |
9785 | const_op += 1; | |
5f4f0e22 | 9786 | op1 = GEN_INT (const_op); |
4803a34a RK |
9787 | code = LT; |
9788 | } | |
230d793d RS |
9789 | |
9790 | /* If we are doing a <= 0 comparison on a value known to have | |
9791 | a zero sign bit, we can replace this with == 0. */ | |
9792 | else if (const_op == 0 | |
5f4f0e22 | 9793 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 9794 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 9795 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
9796 | code = EQ; |
9797 | break; | |
9798 | ||
9799 | case GE: | |
0f41302f | 9800 | /* >= C is equivalent to > (C - 1). */ |
4803a34a | 9801 | if (const_op > 0) |
230d793d | 9802 | { |
4803a34a | 9803 | const_op -= 1; |
5f4f0e22 | 9804 | op1 = GEN_INT (const_op); |
230d793d RS |
9805 | code = GT; |
9806 | /* ... fall through to GT below. */ | |
9807 | } | |
9808 | else | |
9809 | break; | |
9810 | ||
9811 | case GT: | |
663522cb | 9812 | /* > C is equivalent to >= (C + 1); we do this for C < 0. */ |
4803a34a RK |
9813 | if (const_op < 0) |
9814 | { | |
9815 | const_op += 1; | |
5f4f0e22 | 9816 | op1 = GEN_INT (const_op); |
4803a34a RK |
9817 | code = GE; |
9818 | } | |
230d793d RS |
9819 | |
9820 | /* If we are doing a > 0 comparison on a value known to have | |
9821 | a zero sign bit, we can replace this with != 0. */ | |
9822 | else if (const_op == 0 | |
5f4f0e22 | 9823 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 9824 | && (nonzero_bits (op0, mode) |
5f4f0e22 | 9825 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0) |
230d793d RS |
9826 | code = NE; |
9827 | break; | |
9828 | ||
230d793d | 9829 | case LTU: |
4803a34a RK |
9830 | /* < C is equivalent to <= (C - 1). */ |
9831 | if (const_op > 0) | |
9832 | { | |
9833 | const_op -= 1; | |
5f4f0e22 | 9834 | op1 = GEN_INT (const_op); |
4803a34a | 9835 | code = LEU; |
0f41302f | 9836 | /* ... fall through ... */ |
4803a34a | 9837 | } |
d0ab8cd3 RK |
9838 | |
9839 | /* (unsigned) < 0x80000000 is equivalent to >= 0. */ | |
f77aada2 JW |
9840 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
9841 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
9842 | { |
9843 | const_op = 0, op1 = const0_rtx; | |
9844 | code = GE; | |
9845 | break; | |
9846 | } | |
4803a34a RK |
9847 | else |
9848 | break; | |
230d793d RS |
9849 | |
9850 | case LEU: | |
9851 | /* unsigned <= 0 is equivalent to == 0 */ | |
9852 | if (const_op == 0) | |
9853 | code = EQ; | |
d0ab8cd3 | 9854 | |
0f41302f | 9855 | /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */ |
f77aada2 JW |
9856 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
9857 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) | |
d0ab8cd3 RK |
9858 | { |
9859 | const_op = 0, op1 = const0_rtx; | |
9860 | code = GE; | |
9861 | } | |
230d793d RS |
9862 | break; |
9863 | ||
4803a34a | 9864 | case GEU: |
b8ff6ca0 | 9865 | /* >= C is equivalent to > (C - 1). */ |
4803a34a RK |
9866 | if (const_op > 1) |
9867 | { | |
9868 | const_op -= 1; | |
5f4f0e22 | 9869 | op1 = GEN_INT (const_op); |
4803a34a | 9870 | code = GTU; |
0f41302f | 9871 | /* ... fall through ... */ |
4803a34a | 9872 | } |
d0ab8cd3 RK |
9873 | |
9874 | /* (unsigned) >= 0x80000000 is equivalent to < 0. */ | |
f77aada2 JW |
9875 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
9876 | && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))) | |
d0ab8cd3 RK |
9877 | { |
9878 | const_op = 0, op1 = const0_rtx; | |
9879 | code = LT; | |
8b2e69e1 | 9880 | break; |
d0ab8cd3 | 9881 | } |
4803a34a RK |
9882 | else |
9883 | break; | |
9884 | ||
230d793d RS |
9885 | case GTU: |
9886 | /* unsigned > 0 is equivalent to != 0 */ | |
9887 | if (const_op == 0) | |
9888 | code = NE; | |
d0ab8cd3 RK |
9889 | |
9890 | /* (unsigned) > 0x7fffffff is equivalent to < 0. */ | |
f77aada2 | 9891 | else if ((mode_width <= HOST_BITS_PER_WIDE_INT) |
e869aa39 | 9892 | && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)) |
d0ab8cd3 RK |
9893 | { |
9894 | const_op = 0, op1 = const0_rtx; | |
9895 | code = LT; | |
9896 | } | |
230d793d | 9897 | break; |
e9a25f70 JL |
9898 | |
9899 | default: | |
9900 | break; | |
230d793d RS |
9901 | } |
9902 | ||
9903 | /* Compute some predicates to simplify code below. */ | |
9904 | ||
9905 | equality_comparison_p = (code == EQ || code == NE); | |
9906 | sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
9907 | unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
d5010e66 | 9908 | || code == GEU); |
230d793d | 9909 | |
6139ff20 RK |
9910 | /* If this is a sign bit comparison and we can do arithmetic in |
9911 | MODE, say that we will only be needing the sign bit of OP0. */ | |
9912 | if (sign_bit_comparison_p | |
9913 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
9914 | op0 = force_to_mode (op0, mode, | |
9915 | ((HOST_WIDE_INT) 1 | |
9916 | << (GET_MODE_BITSIZE (mode) - 1)), | |
e3d616e3 | 9917 | NULL_RTX, 0); |
6139ff20 | 9918 | |
230d793d RS |
9919 | /* Now try cases based on the opcode of OP0. If none of the cases |
9920 | does a "continue", we exit this loop immediately after the | |
9921 | switch. */ | |
9922 | ||
9923 | switch (GET_CODE (op0)) | |
9924 | { | |
9925 | case ZERO_EXTRACT: | |
9926 | /* If we are extracting a single bit from a variable position in | |
9927 | a constant that has only a single bit set and are comparing it | |
663522cb | 9928 | with zero, we can convert this into an equality comparison |
d7cd794f | 9929 | between the position and the location of the single bit. */ |
a475bff7 RH |
9930 | /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might |
9931 | have already reduced the shift count modulo the word size. */ | |
9932 | if (!SHIFT_COUNT_TRUNCATED | |
9933 | && GET_CODE (XEXP (op0, 0)) == CONST_INT | |
230d793d RS |
9934 | && XEXP (op0, 1) == const1_rtx |
9935 | && equality_comparison_p && const_op == 0 | |
d7cd794f | 9936 | && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) |
230d793d | 9937 | { |
f76b9db2 | 9938 | if (BITS_BIG_ENDIAN) |
0d8e55d8 | 9939 | { |
da920570 ZW |
9940 | enum machine_mode new_mode |
9941 | = mode_for_extraction (EP_extzv, 1); | |
9942 | if (new_mode == MAX_MACHINE_MODE) | |
9943 | i = BITS_PER_WORD - 1 - i; | |
9944 | else | |
9945 | { | |
9946 | mode = new_mode; | |
9947 | i = (GET_MODE_BITSIZE (mode) - 1 - i); | |
9948 | } | |
0d8e55d8 | 9949 | } |
230d793d RS |
9950 | |
9951 | op0 = XEXP (op0, 2); | |
5f4f0e22 | 9952 | op1 = GEN_INT (i); |
230d793d RS |
9953 | const_op = i; |
9954 | ||
9955 | /* Result is nonzero iff shift count is equal to I. */ | |
9956 | code = reverse_condition (code); | |
9957 | continue; | |
9958 | } | |
230d793d | 9959 | |
0f41302f | 9960 | /* ... fall through ... */ |
230d793d RS |
9961 | |
9962 | case SIGN_EXTRACT: | |
9963 | tem = expand_compound_operation (op0); | |
9964 | if (tem != op0) | |
9965 | { | |
9966 | op0 = tem; | |
9967 | continue; | |
9968 | } | |
9969 | break; | |
9970 | ||
9971 | case NOT: | |
9972 | /* If testing for equality, we can take the NOT of the constant. */ | |
9973 | if (equality_comparison_p | |
9974 | && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
9975 | { | |
9976 | op0 = XEXP (op0, 0); | |
9977 | op1 = tem; | |
9978 | continue; | |
9979 | } | |
9980 | ||
9981 | /* If just looking at the sign bit, reverse the sense of the | |
9982 | comparison. */ | |
9983 | if (sign_bit_comparison_p) | |
9984 | { | |
9985 | op0 = XEXP (op0, 0); | |
9986 | code = (code == GE ? LT : GE); | |
9987 | continue; | |
9988 | } | |
9989 | break; | |
9990 | ||
9991 | case NEG: | |
9992 | /* If testing for equality, we can take the NEG of the constant. */ | |
9993 | if (equality_comparison_p | |
9994 | && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
9995 | { | |
9996 | op0 = XEXP (op0, 0); | |
9997 | op1 = tem; | |
9998 | continue; | |
9999 | } | |
10000 | ||
10001 | /* The remaining cases only apply to comparisons with zero. */ | |
10002 | if (const_op != 0) | |
10003 | break; | |
10004 | ||
10005 | /* When X is ABS or is known positive, | |
10006 | (neg X) is < 0 if and only if X != 0. */ | |
10007 | ||
10008 | if (sign_bit_comparison_p | |
10009 | && (GET_CODE (XEXP (op0, 0)) == ABS | |
5f4f0e22 | 10010 | || (mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10011 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 10012 | & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0))) |
230d793d RS |
10013 | { |
10014 | op0 = XEXP (op0, 0); | |
10015 | code = (code == LT ? NE : EQ); | |
10016 | continue; | |
10017 | } | |
10018 | ||
3bed8141 | 10019 | /* If we have NEG of something whose two high-order bits are the |
0f41302f | 10020 | same, we know that "(-a) < 0" is equivalent to "a > 0". */ |
3bed8141 | 10021 | if (num_sign_bit_copies (op0, mode) >= 2) |
230d793d RS |
10022 | { |
10023 | op0 = XEXP (op0, 0); | |
10024 | code = swap_condition (code); | |
10025 | continue; | |
10026 | } | |
10027 | break; | |
10028 | ||
10029 | case ROTATE: | |
10030 | /* If we are testing equality and our count is a constant, we | |
10031 | can perform the inverse operation on our RHS. */ | |
10032 | if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10033 | && (tem = simplify_binary_operation (ROTATERT, mode, | |
10034 | op1, XEXP (op0, 1))) != 0) | |
10035 | { | |
10036 | op0 = XEXP (op0, 0); | |
10037 | op1 = tem; | |
10038 | continue; | |
10039 | } | |
10040 | ||
10041 | /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
10042 | a particular bit. Convert it to an AND of a constant of that | |
10043 | bit. This will be converted into a ZERO_EXTRACT. */ | |
10044 | if (const_op == 0 && sign_bit_comparison_p | |
10045 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10046 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10047 | { |
5f4f0e22 CH |
10048 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10049 | ((HOST_WIDE_INT) 1 | |
10050 | << (mode_width - 1 | |
10051 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10052 | code = (code == LT ? NE : EQ); |
10053 | continue; | |
10054 | } | |
10055 | ||
663522cb | 10056 | /* Fall through. */ |
230d793d RS |
10057 | |
10058 | case ABS: | |
10059 | /* ABS is ignorable inside an equality comparison with zero. */ | |
10060 | if (const_op == 0 && equality_comparison_p) | |
10061 | { | |
10062 | op0 = XEXP (op0, 0); | |
10063 | continue; | |
10064 | } | |
10065 | break; | |
230d793d RS |
10066 | |
10067 | case SIGN_EXTEND: | |
aa2d0bc3 AO |
10068 | /* Can simplify (compare (zero/sign_extend FOO) CONST) to |
10069 | (compare FOO CONST) if CONST fits in FOO's mode and we | |
10070 | are either testing inequality or have an unsigned | |
10071 | comparison with ZERO_EXTEND or a signed comparison with | |
10072 | SIGN_EXTEND. But don't do it if we don't have a compare | |
10073 | insn of the given mode, since we'd have to revert it | |
10074 | later on, and then we wouldn't know whether to sign- or | |
10075 | zero-extend. */ | |
10076 | mode = GET_MODE (XEXP (op0, 0)); | |
10077 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10078 | && ! unsigned_comparison_p | |
10079 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
5f4f0e22 | 10080 | && ((unsigned HOST_WIDE_INT) const_op |
aa2d0bc3 AO |
10081 | < (((unsigned HOST_WIDE_INT) 1 |
10082 | << (GET_MODE_BITSIZE (mode) - 1)))) | |
10083 | && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
230d793d RS |
10084 | { |
10085 | op0 = XEXP (op0, 0); | |
10086 | continue; | |
10087 | } | |
10088 | break; | |
10089 | ||
10090 | case SUBREG: | |
f917ae96 EB |
10091 | /* Check for the case where we are comparing A - C1 with C2, that is |
10092 | ||
10093 | (subreg:MODE (plus (A) (-C1))) op (C2) | |
10094 | ||
10095 | with C1 a constant, and try to lift the SUBREG, i.e. to do the | |
10096 | comparison in the wider mode. One of the following two conditions | |
10097 | must be true in order for this to be valid: | |
10098 | ||
10099 | 1. The mode extension results in the same bit pattern being added | |
10100 | on both sides and the comparison is equality or unsigned. As | |
10101 | C2 has been truncated to fit in MODE, the pattern can only be | |
10102 | all 0s or all 1s. | |
10103 | ||
10104 | 2. The mode extension results in the sign bit being copied on | |
10105 | each side. | |
10106 | ||
10107 | The difficulty here is that we have predicates for A but not for | |
10108 | (A - C1) so we need to check that C1 is within proper bounds so | |
10109 | as to perturbate A as little as possible. */ | |
a687e897 RK |
10110 | |
10111 | if (mode_width <= HOST_BITS_PER_WIDE_INT | |
10112 | && subreg_lowpart_p (op0) | |
f917ae96 | 10113 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width |
a687e897 | 10114 | && GET_CODE (SUBREG_REG (op0)) == PLUS |
f917ae96 | 10115 | && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT) |
a687e897 | 10116 | { |
f917ae96 EB |
10117 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
10118 | rtx a = XEXP (SUBREG_REG (op0), 0); | |
10119 | HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1)); | |
10120 | ||
10121 | if ((c1 > 0 | |
10122 | && (unsigned HOST_WIDE_INT) c1 | |
10123 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1) | |
10124 | && (equality_comparison_p || unsigned_comparison_p) | |
10125 | /* (A - C1) zero-extends if it is positive and sign-extends | |
10126 | if it is negative, C2 both zero- and sign-extends. */ | |
10127 | && ((0 == (nonzero_bits (a, inner_mode) | |
10128 | & ~GET_MODE_MASK (mode)) | |
10129 | && const_op >= 0) | |
10130 | /* (A - C1) sign-extends if it is positive and 1-extends | |
10131 | if it is negative, C2 both sign- and 1-extends. */ | |
10132 | || (num_sign_bit_copies (a, inner_mode) | |
10133 | > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
10134 | - mode_width) | |
10135 | && const_op < 0))) | |
10136 | || ((unsigned HOST_WIDE_INT) c1 | |
10137 | < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2) | |
10138 | /* (A - C1) always sign-extends, like C2. */ | |
10139 | && num_sign_bit_copies (a, inner_mode) | |
10140 | > (unsigned int) (GET_MODE_BITSIZE (inner_mode) | |
10141 | - mode_width - 1))) | |
10142 | { | |
10143 | op0 = SUBREG_REG (op0); | |
10144 | continue; | |
10145 | } | |
a687e897 RK |
10146 | } |
10147 | ||
fe0cf571 RK |
10148 | /* If the inner mode is narrower and we are extracting the low part, |
10149 | we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
10150 | if (subreg_lowpart_p (op0) | |
89f1c7f2 RS |
10151 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width) |
10152 | /* Fall through */ ; | |
10153 | else | |
230d793d RS |
10154 | break; |
10155 | ||
0f41302f | 10156 | /* ... fall through ... */ |
230d793d RS |
10157 | |
10158 | case ZERO_EXTEND: | |
aa2d0bc3 AO |
10159 | mode = GET_MODE (XEXP (op0, 0)); |
10160 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10161 | && (unsigned_comparison_p || equality_comparison_p) | |
10162 | && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10163 | && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode)) | |
10164 | && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing) | |
230d793d RS |
10165 | { |
10166 | op0 = XEXP (op0, 0); | |
10167 | continue; | |
10168 | } | |
10169 | break; | |
10170 | ||
10171 | case PLUS: | |
20fdd649 | 10172 | /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do |
5089e22e | 10173 | this for equality comparisons due to pathological cases involving |
230d793d | 10174 | overflows. */ |
20fdd649 RK |
10175 | if (equality_comparison_p |
10176 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10177 | op1, XEXP (op0, 1)))) | |
230d793d RS |
10178 | { |
10179 | op0 = XEXP (op0, 0); | |
10180 | op1 = tem; | |
10181 | continue; | |
10182 | } | |
10183 | ||
10184 | /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
10185 | if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
10186 | && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
10187 | { | |
10188 | op0 = XEXP (XEXP (op0, 0), 0); | |
10189 | code = (code == LT ? EQ : NE); | |
10190 | continue; | |
10191 | } | |
10192 | break; | |
10193 | ||
10194 | case MINUS: | |
65945ec1 HPN |
10195 | /* We used to optimize signed comparisons against zero, but that |
10196 | was incorrect. Unsigned comparisons against zero (GTU, LEU) | |
10197 | arrive here as equality comparisons, or (GEU, LTU) are | |
10198 | optimized away. No need to special-case them. */ | |
0bd4b461 | 10199 | |
20fdd649 RK |
10200 | /* (eq (minus A B) C) -> (eq A (plus B C)) or |
10201 | (eq B (minus A C)), whichever simplifies. We can only do | |
10202 | this for equality comparisons due to pathological cases involving | |
10203 | overflows. */ | |
10204 | if (equality_comparison_p | |
10205 | && 0 != (tem = simplify_binary_operation (PLUS, mode, | |
10206 | XEXP (op0, 1), op1))) | |
10207 | { | |
10208 | op0 = XEXP (op0, 0); | |
10209 | op1 = tem; | |
10210 | continue; | |
10211 | } | |
10212 | ||
10213 | if (equality_comparison_p | |
10214 | && 0 != (tem = simplify_binary_operation (MINUS, mode, | |
10215 | XEXP (op0, 0), op1))) | |
10216 | { | |
10217 | op0 = XEXP (op0, 1); | |
10218 | op1 = tem; | |
10219 | continue; | |
10220 | } | |
10221 | ||
230d793d RS |
10222 | /* The sign bit of (minus (ashiftrt X C) X), where C is the number |
10223 | of bits in X minus 1, is one iff X > 0. */ | |
10224 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
10225 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
26c34780 RS |
10226 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1)) |
10227 | == mode_width - 1 | |
230d793d RS |
10228 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) |
10229 | { | |
10230 | op0 = XEXP (op0, 1); | |
10231 | code = (code == GE ? LE : GT); | |
10232 | continue; | |
10233 | } | |
10234 | break; | |
10235 | ||
10236 | case XOR: | |
10237 | /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
10238 | if C is zero or B is a constant. */ | |
10239 | if (equality_comparison_p | |
10240 | && 0 != (tem = simplify_binary_operation (XOR, mode, | |
10241 | XEXP (op0, 1), op1))) | |
10242 | { | |
10243 | op0 = XEXP (op0, 0); | |
10244 | op1 = tem; | |
10245 | continue; | |
10246 | } | |
10247 | break; | |
10248 | ||
10249 | case EQ: case NE: | |
69bc0a1f JH |
10250 | case UNEQ: case LTGT: |
10251 | case LT: case LTU: case UNLT: case LE: case LEU: case UNLE: | |
10252 | case GT: case GTU: case UNGT: case GE: case GEU: case UNGE: | |
10253 | case UNORDERED: case ORDERED: | |
230d793d RS |
10254 | /* We can't do anything if OP0 is a condition code value, rather |
10255 | than an actual data value. */ | |
10256 | if (const_op != 0 | |
8beccec8 | 10257 | || CC0_P (XEXP (op0, 0)) |
230d793d RS |
10258 | || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) |
10259 | break; | |
10260 | ||
10261 | /* Get the two operands being compared. */ | |
10262 | if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
10263 | tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
10264 | else | |
10265 | tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
10266 | ||
10267 | /* Check for the cases where we simply want the result of the | |
10268 | earlier test or the opposite of that result. */ | |
9a915772 | 10269 | if (code == NE || code == EQ |
5f4f0e22 | 10270 | || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT |
3f508eca | 10271 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT |
230d793d | 10272 | && (STORE_FLAG_VALUE |
5f4f0e22 CH |
10273 | & (((HOST_WIDE_INT) 1 |
10274 | << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))) | |
aa6683f7 | 10275 | && (code == LT || code == GE))) |
230d793d | 10276 | { |
aa6683f7 GK |
10277 | enum rtx_code new_code; |
10278 | if (code == LT || code == NE) | |
10279 | new_code = GET_CODE (op0); | |
10280 | else | |
14f02e73 | 10281 | new_code = reversed_comparison_code (op0, NULL); |
23190837 | 10282 | |
aa6683f7 | 10283 | if (new_code != UNKNOWN) |
9a915772 | 10284 | { |
aa6683f7 GK |
10285 | code = new_code; |
10286 | op0 = tem; | |
10287 | op1 = tem1; | |
9a915772 JH |
10288 | continue; |
10289 | } | |
230d793d RS |
10290 | } |
10291 | break; | |
10292 | ||
10293 | case IOR: | |
da7d8304 | 10294 | /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero |
230d793d RS |
10295 | iff X <= 0. */ |
10296 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
10297 | && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
10298 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
10299 | { | |
10300 | op0 = XEXP (op0, 1); | |
10301 | code = (code == GE ? GT : LE); | |
10302 | continue; | |
10303 | } | |
10304 | break; | |
10305 | ||
10306 | case AND: | |
10307 | /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
10308 | will be converted to a ZERO_EXTRACT later. */ | |
10309 | if (const_op == 0 && equality_comparison_p | |
45620ed4 | 10310 | && GET_CODE (XEXP (op0, 0)) == ASHIFT |
230d793d RS |
10311 | && XEXP (XEXP (op0, 0), 0) == const1_rtx) |
10312 | { | |
10313 | op0 = simplify_and_const_int | |
f1c6ba8b RK |
10314 | (op0, mode, gen_rtx_LSHIFTRT (mode, |
10315 | XEXP (op0, 1), | |
10316 | XEXP (XEXP (op0, 0), 1)), | |
5f4f0e22 | 10317 | (HOST_WIDE_INT) 1); |
230d793d RS |
10318 | continue; |
10319 | } | |
10320 | ||
10321 | /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
10322 | zero and X is a comparison and C1 and C2 describe only bits set | |
10323 | in STORE_FLAG_VALUE, we can compare with X. */ | |
10324 | if (const_op == 0 && equality_comparison_p | |
5f4f0e22 | 10325 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d RS |
10326 | && GET_CODE (XEXP (op0, 1)) == CONST_INT |
10327 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
10328 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10329 | && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 | |
5f4f0e22 | 10330 | && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT) |
230d793d RS |
10331 | { |
10332 | mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
10333 | << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
663522cb | 10334 | if ((~STORE_FLAG_VALUE & mask) == 0 |
ec8e098d | 10335 | && (COMPARISON_P (XEXP (XEXP (op0, 0), 0)) |
230d793d | 10336 | || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 |
ec8e098d | 10337 | && COMPARISON_P (tem)))) |
230d793d RS |
10338 | { |
10339 | op0 = XEXP (XEXP (op0, 0), 0); | |
10340 | continue; | |
10341 | } | |
10342 | } | |
10343 | ||
10344 | /* If we are doing an equality comparison of an AND of a bit equal | |
10345 | to the sign bit, replace this with a LT or GE comparison of | |
10346 | the underlying value. */ | |
10347 | if (equality_comparison_p | |
10348 | && const_op == 0 | |
10349 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
5f4f0e22 | 10350 | && mode_width <= HOST_BITS_PER_WIDE_INT |
230d793d | 10351 | && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) |
e51712db | 10352 | == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) |
230d793d RS |
10353 | { |
10354 | op0 = XEXP (op0, 0); | |
10355 | code = (code == EQ ? GE : LT); | |
10356 | continue; | |
10357 | } | |
10358 | ||
10359 | /* If this AND operation is really a ZERO_EXTEND from a narrower | |
10360 | mode, the constant fits within that mode, and this is either an | |
10361 | equality or unsigned comparison, try to do this comparison in | |
10362 | the narrower mode. */ | |
10363 | if ((equality_comparison_p || unsigned_comparison_p) | |
10364 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10365 | && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) | |
10366 | & GET_MODE_MASK (mode)) | |
10367 | + 1)) >= 0 | |
10368 | && const_op >> i == 0 | |
10369 | && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) | |
10370 | { | |
4de249d9 | 10371 | op0 = gen_lowpart (tmode, XEXP (op0, 0)); |
230d793d RS |
10372 | continue; |
10373 | } | |
e5e809f4 | 10374 | |
70e1b8fc AM |
10375 | /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 |
10376 | fits in both M1 and M2 and the SUBREG is either paradoxical | |
10377 | or represents the low part, permute the SUBREG and the AND | |
10378 | and try again. */ | |
10379 | if (GET_CODE (XEXP (op0, 0)) == SUBREG) | |
10380 | { | |
10381 | unsigned HOST_WIDE_INT c1; | |
10382 | tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0))); | |
678e68fc JW |
10383 | /* Require an integral mode, to avoid creating something like |
10384 | (AND:SF ...). */ | |
70e1b8fc AM |
10385 | if (SCALAR_INT_MODE_P (tmode) |
10386 | /* It is unsafe to commute the AND into the SUBREG if the | |
10387 | SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is | |
10388 | not defined. As originally written the upper bits | |
10389 | have a defined value due to the AND operation. | |
10390 | However, if we commute the AND inside the SUBREG then | |
10391 | they no longer have defined values and the meaning of | |
10392 | the code has been changed. */ | |
10393 | && (0 | |
9ec36da5 | 10394 | #ifdef WORD_REGISTER_OPERATIONS |
70e1b8fc AM |
10395 | || (mode_width > GET_MODE_BITSIZE (tmode) |
10396 | && mode_width <= BITS_PER_WORD) | |
9ec36da5 | 10397 | #endif |
70e1b8fc AM |
10398 | || (mode_width <= GET_MODE_BITSIZE (tmode) |
10399 | && subreg_lowpart_p (XEXP (op0, 0)))) | |
10400 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10401 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
10402 | && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT | |
10403 | && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0 | |
10404 | && (c1 & ~GET_MODE_MASK (tmode)) == 0 | |
10405 | && c1 != mask | |
10406 | && c1 != GET_MODE_MASK (tmode)) | |
10407 | { | |
bcb34aa3 PB |
10408 | op0 = simplify_gen_binary (AND, tmode, |
10409 | SUBREG_REG (XEXP (op0, 0)), | |
10410 | gen_int_mode (c1, tmode)); | |
4de249d9 | 10411 | op0 = gen_lowpart (mode, op0); |
70e1b8fc AM |
10412 | continue; |
10413 | } | |
e5e809f4 JL |
10414 | } |
10415 | ||
34ed3bb0 KH |
10416 | /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */ |
10417 | if (const_op == 0 && equality_comparison_p | |
10418 | && XEXP (op0, 1) == const1_rtx | |
10419 | && GET_CODE (XEXP (op0, 0)) == NOT) | |
10420 | { | |
10421 | op0 = simplify_and_const_int | |
e5686da7 | 10422 | (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1); |
34ed3bb0 KH |
10423 | code = (code == NE ? EQ : NE); |
10424 | continue; | |
10425 | } | |
10426 | ||
9f8e169e | 10427 | /* Convert (ne (and (lshiftrt (not X)) 1) 0) to |
5565e874 KH |
10428 | (eq (and (lshiftrt X) 1) 0). |
10429 | Also handle the case where (not X) is expressed using xor. */ | |
9f8e169e RH |
10430 | if (const_op == 0 && equality_comparison_p |
10431 | && XEXP (op0, 1) == const1_rtx | |
5565e874 | 10432 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT) |
9f8e169e | 10433 | { |
5565e874 KH |
10434 | rtx shift_op = XEXP (XEXP (op0, 0), 0); |
10435 | rtx shift_count = XEXP (XEXP (op0, 0), 1); | |
10436 | ||
10437 | if (GET_CODE (shift_op) == NOT | |
10438 | || (GET_CODE (shift_op) == XOR | |
10439 | && GET_CODE (XEXP (shift_op, 1)) == CONST_INT | |
10440 | && GET_CODE (shift_count) == CONST_INT | |
10441 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT | |
10442 | && (INTVAL (XEXP (shift_op, 1)) | |
10443 | == (HOST_WIDE_INT) 1 << INTVAL (shift_count)))) | |
10444 | { | |
10445 | op0 = simplify_and_const_int | |
10446 | (NULL_RTX, mode, | |
10447 | gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count), | |
10448 | (HOST_WIDE_INT) 1); | |
10449 | code = (code == NE ? EQ : NE); | |
10450 | continue; | |
10451 | } | |
9f8e169e | 10452 | } |
230d793d RS |
10453 | break; |
10454 | ||
10455 | case ASHIFT: | |
45620ed4 | 10456 | /* If we have (compare (ashift FOO N) (const_int C)) and |
230d793d | 10457 | the high order N bits of FOO (N+1 if an inequality comparison) |
951553af | 10458 | are known to be zero, we can do this by comparing FOO with C |
230d793d RS |
10459 | shifted right N bits so long as the low-order N bits of C are |
10460 | zero. */ | |
10461 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10462 | && INTVAL (XEXP (op0, 1)) >= 0 | |
10463 | && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
5f4f0e22 CH |
10464 | < HOST_BITS_PER_WIDE_INT) |
10465 | && ((const_op | |
34785d05 | 10466 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0) |
5f4f0e22 | 10467 | && mode_width <= HOST_BITS_PER_WIDE_INT |
951553af | 10468 | && (nonzero_bits (XEXP (op0, 0), mode) |
663522cb KH |
10469 | & ~(mask >> (INTVAL (XEXP (op0, 1)) |
10470 | + ! equality_comparison_p))) == 0) | |
230d793d | 10471 | { |
7ce787fe NC |
10472 | /* We must perform a logical shift, not an arithmetic one, |
10473 | as we want the top N bits of C to be zero. */ | |
aaaec114 | 10474 | unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode); |
663522cb | 10475 | |
7ce787fe | 10476 | temp >>= INTVAL (XEXP (op0, 1)); |
2496c7bd | 10477 | op1 = gen_int_mode (temp, mode); |
230d793d RS |
10478 | op0 = XEXP (op0, 0); |
10479 | continue; | |
10480 | } | |
10481 | ||
dfbe1b2f | 10482 | /* If we are doing a sign bit comparison, it means we are testing |
230d793d | 10483 | a particular bit. Convert it to the appropriate AND. */ |
dfbe1b2f | 10484 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT |
5f4f0e22 | 10485 | && mode_width <= HOST_BITS_PER_WIDE_INT) |
230d793d | 10486 | { |
5f4f0e22 CH |
10487 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10488 | ((HOST_WIDE_INT) 1 | |
10489 | << (mode_width - 1 | |
10490 | - INTVAL (XEXP (op0, 1))))); | |
230d793d RS |
10491 | code = (code == LT ? NE : EQ); |
10492 | continue; | |
10493 | } | |
dfbe1b2f RK |
10494 | |
10495 | /* If this an equality comparison with zero and we are shifting | |
10496 | the low bit to the sign bit, we can convert this to an AND of the | |
10497 | low-order bit. */ | |
10498 | if (const_op == 0 && equality_comparison_p | |
10499 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
10500 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
10501 | == mode_width - 1) | |
dfbe1b2f | 10502 | { |
5f4f0e22 CH |
10503 | op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), |
10504 | (HOST_WIDE_INT) 1); | |
dfbe1b2f RK |
10505 | continue; |
10506 | } | |
230d793d RS |
10507 | break; |
10508 | ||
10509 | case ASHIFTRT: | |
d0ab8cd3 RK |
10510 | /* If this is an equality comparison with zero, we can do this |
10511 | as a logical shift, which might be much simpler. */ | |
10512 | if (equality_comparison_p && const_op == 0 | |
10513 | && GET_CODE (XEXP (op0, 1)) == CONST_INT) | |
10514 | { | |
10515 | op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, | |
10516 | XEXP (op0, 0), | |
10517 | INTVAL (XEXP (op0, 1))); | |
10518 | continue; | |
10519 | } | |
10520 | ||
230d793d RS |
10521 | /* If OP0 is a sign extension and CODE is not an unsigned comparison, |
10522 | do the comparison in a narrower mode. */ | |
10523 | if (! unsigned_comparison_p | |
10524 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10525 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
10526 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
10527 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
22331794 | 10528 | MODE_INT, 1)) != BLKmode |
67e469d7 AM |
10529 | && (((unsigned HOST_WIDE_INT) const_op |
10530 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
10531 | <= GET_MODE_MASK (tmode))) | |
230d793d | 10532 | { |
4de249d9 | 10533 | op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0)); |
230d793d RS |
10534 | continue; |
10535 | } | |
10536 | ||
14a774a9 RK |
10537 | /* Likewise if OP0 is a PLUS of a sign extension with a |
10538 | constant, which is usually represented with the PLUS | |
10539 | between the shifts. */ | |
10540 | if (! unsigned_comparison_p | |
10541 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10542 | && GET_CODE (XEXP (op0, 0)) == PLUS | |
10543 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
10544 | && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT | |
10545 | && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1) | |
10546 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
10547 | MODE_INT, 1)) != BLKmode | |
67e469d7 AM |
10548 | && (((unsigned HOST_WIDE_INT) const_op |
10549 | + (GET_MODE_MASK (tmode) >> 1) + 1) | |
10550 | <= GET_MODE_MASK (tmode))) | |
14a774a9 RK |
10551 | { |
10552 | rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0); | |
10553 | rtx add_const = XEXP (XEXP (op0, 0), 1); | |
bcb34aa3 PB |
10554 | rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0), |
10555 | add_const, XEXP (op0, 1)); | |
14a774a9 | 10556 | |
bcb34aa3 PB |
10557 | op0 = simplify_gen_binary (PLUS, tmode, |
10558 | gen_lowpart (tmode, inner), | |
10559 | new_const); | |
14a774a9 RK |
10560 | continue; |
10561 | } | |
10562 | ||
0f41302f | 10563 | /* ... fall through ... */ |
230d793d RS |
10564 | case LSHIFTRT: |
10565 | /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
951553af | 10566 | the low order N bits of FOO are known to be zero, we can do this |
230d793d RS |
10567 | by comparing FOO with C shifted left N bits so long as no |
10568 | overflow occurs. */ | |
10569 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
10570 | && INTVAL (XEXP (op0, 1)) >= 0 | |
5f4f0e22 CH |
10571 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT |
10572 | && mode_width <= HOST_BITS_PER_WIDE_INT | |
951553af | 10573 | && (nonzero_bits (XEXP (op0, 0), mode) |
5f4f0e22 | 10574 | & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 |
67e469d7 AM |
10575 | && (((unsigned HOST_WIDE_INT) const_op |
10576 | + (GET_CODE (op0) != LSHIFTRT | |
10577 | ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1) | |
10578 | + 1) | |
10579 | : 0)) | |
10580 | <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)))) | |
230d793d | 10581 | { |
145d3bf2 RE |
10582 | /* If the shift was logical, then we must make the condition |
10583 | unsigned. */ | |
10584 | if (GET_CODE (op0) == LSHIFTRT) | |
10585 | code = unsigned_condition (code); | |
10586 | ||
230d793d | 10587 | const_op <<= INTVAL (XEXP (op0, 1)); |
5f4f0e22 | 10588 | op1 = GEN_INT (const_op); |
230d793d RS |
10589 | op0 = XEXP (op0, 0); |
10590 | continue; | |
10591 | } | |
10592 | ||
10593 | /* If we are using this shift to extract just the sign bit, we | |
10594 | can replace this with an LT or GE comparison. */ | |
10595 | if (const_op == 0 | |
10596 | && (equality_comparison_p || sign_bit_comparison_p) | |
10597 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
26c34780 RS |
10598 | && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) |
10599 | == mode_width - 1) | |
230d793d RS |
10600 | { |
10601 | op0 = XEXP (op0, 0); | |
10602 | code = (code == NE || code == GT ? LT : GE); | |
10603 | continue; | |
10604 | } | |
10605 | break; | |
663522cb | 10606 | |
e9a25f70 JL |
10607 | default: |
10608 | break; | |
230d793d RS |
10609 | } |
10610 | ||
10611 | break; | |
10612 | } | |
10613 | ||
10614 | /* Now make any compound operations involved in this comparison. Then, | |
76d31c63 | 10615 | check for an outmost SUBREG on OP0 that is not doing anything or is |
5add6d1a JL |
10616 | paradoxical. The latter transformation must only be performed when |
10617 | it is known that the "extra" bits will be the same in op0 and op1 or | |
10618 | that they don't matter. There are three cases to consider: | |
10619 | ||
10620 | 1. SUBREG_REG (op0) is a register. In this case the bits are don't | |
10621 | care bits and we can assume they have any convenient value. So | |
10622 | making the transformation is safe. | |
10623 | ||
10624 | 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined. | |
10625 | In this case the upper bits of op0 are undefined. We should not make | |
10626 | the simplification in that case as we do not know the contents of | |
10627 | those bits. | |
10628 | ||
10629 | 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not | |
f822d252 | 10630 | UNKNOWN. In that case we know those bits are zeros or ones. We must |
5add6d1a JL |
10631 | also be sure that they are the same as the upper bits of op1. |
10632 | ||
10633 | We can never remove a SUBREG for a non-equality comparison because | |
10634 | the sign bit is in a different place in the underlying object. */ | |
230d793d RS |
10635 | |
10636 | op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
10637 | op1 = make_compound_operation (op1, SET); | |
10638 | ||
10639 | if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
10640 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
fa4e13e0 | 10641 | && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT |
5add6d1a | 10642 | && (code == NE || code == EQ)) |
230d793d | 10643 | { |
5add6d1a JL |
10644 | if (GET_MODE_SIZE (GET_MODE (op0)) |
10645 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))) | |
10646 | { | |
dc5c3188 UW |
10647 | /* For paradoxical subregs, allow case 1 as above. Case 3 isn't |
10648 | implemented. */ | |
f8cfc6aa | 10649 | if (REG_P (SUBREG_REG (op0))) |
dc5c3188 UW |
10650 | { |
10651 | op0 = SUBREG_REG (op0); | |
4de249d9 | 10652 | op1 = gen_lowpart (GET_MODE (op0), op1); |
dc5c3188 | 10653 | } |
5add6d1a JL |
10654 | } |
10655 | else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) | |
10656 | <= HOST_BITS_PER_WIDE_INT) | |
10657 | && (nonzero_bits (SUBREG_REG (op0), | |
10658 | GET_MODE (SUBREG_REG (op0))) | |
10659 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
10660 | { | |
4de249d9 | 10661 | tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1); |
230d793d | 10662 | |
5add6d1a JL |
10663 | if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0))) |
10664 | & ~GET_MODE_MASK (GET_MODE (op0))) == 0) | |
10665 | op0 = SUBREG_REG (op0), op1 = tem; | |
10666 | } | |
10667 | } | |
230d793d RS |
10668 | |
10669 | /* We now do the opposite procedure: Some machines don't have compare | |
10670 | insns in all modes. If OP0's mode is an integer mode smaller than a | |
10671 | word and we can't do a compare in that mode, see if there is a larger | |
a687e897 RK |
10672 | mode for which we can do the compare. There are a number of cases in |
10673 | which we can use the wider mode. */ | |
230d793d RS |
10674 | |
10675 | mode = GET_MODE (op0); | |
10676 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
10677 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
ef89d648 | 10678 | && ! have_insn_for (COMPARE, mode)) |
230d793d | 10679 | for (tmode = GET_MODE_WIDER_MODE (mode); |
5f4f0e22 CH |
10680 | (tmode != VOIDmode |
10681 | && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT); | |
230d793d | 10682 | tmode = GET_MODE_WIDER_MODE (tmode)) |
ef89d648 | 10683 | if (have_insn_for (COMPARE, tmode)) |
230d793d | 10684 | { |
d4c5ac1f AM |
10685 | int zero_extended; |
10686 | ||
951553af | 10687 | /* If the only nonzero bits in OP0 and OP1 are those in the |
a687e897 RK |
10688 | narrower mode and this is an equality or unsigned comparison, |
10689 | we can use the wider mode. Similarly for sign-extended | |
7e4dc511 | 10690 | values, in which case it is true for all comparisons. */ |
d4c5ac1f AM |
10691 | zero_extended = ((code == EQ || code == NE |
10692 | || code == GEU || code == GTU | |
10693 | || code == LEU || code == LTU) | |
10694 | && (nonzero_bits (op0, tmode) | |
10695 | & ~GET_MODE_MASK (mode)) == 0 | |
10696 | && ((GET_CODE (op1) == CONST_INT | |
10697 | || (nonzero_bits (op1, tmode) | |
10698 | & ~GET_MODE_MASK (mode)) == 0))); | |
10699 | ||
10700 | if (zero_extended | |
7e4dc511 | 10701 | || ((num_sign_bit_copies (op0, tmode) |
26c34780 RS |
10702 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
10703 | - GET_MODE_BITSIZE (mode))) | |
a687e897 | 10704 | && (num_sign_bit_copies (op1, tmode) |
26c34780 RS |
10705 | > (unsigned int) (GET_MODE_BITSIZE (tmode) |
10706 | - GET_MODE_BITSIZE (mode))))) | |
a687e897 | 10707 | { |
14a774a9 RK |
10708 | /* If OP0 is an AND and we don't have an AND in MODE either, |
10709 | make a new AND in the proper mode. */ | |
10710 | if (GET_CODE (op0) == AND | |
ef89d648 | 10711 | && !have_insn_for (AND, mode)) |
bcb34aa3 PB |
10712 | op0 = simplify_gen_binary (AND, tmode, |
10713 | gen_lowpart (tmode, | |
10714 | XEXP (op0, 0)), | |
10715 | gen_lowpart (tmode, | |
10716 | XEXP (op0, 1))); | |
14a774a9 | 10717 | |
4de249d9 | 10718 | op0 = gen_lowpart (tmode, op0); |
d4c5ac1f AM |
10719 | if (zero_extended && GET_CODE (op1) == CONST_INT) |
10720 | op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode)); | |
4de249d9 | 10721 | op1 = gen_lowpart (tmode, op1); |
a687e897 RK |
10722 | break; |
10723 | } | |
230d793d | 10724 | |
a687e897 RK |
10725 | /* If this is a test for negative, we can make an explicit |
10726 | test of the sign bit. */ | |
10727 | ||
10728 | if (op1 == const0_rtx && (code == LT || code == GE) | |
10729 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
230d793d | 10730 | { |
bcb34aa3 PB |
10731 | op0 = simplify_gen_binary (AND, tmode, |
10732 | gen_lowpart (tmode, op0), | |
10733 | GEN_INT ((HOST_WIDE_INT) 1 | |
10734 | << (GET_MODE_BITSIZE (mode) | |
10735 | - 1))); | |
230d793d | 10736 | code = (code == LT) ? NE : EQ; |
a687e897 | 10737 | break; |
230d793d | 10738 | } |
230d793d RS |
10739 | } |
10740 | ||
b7a775b2 RK |
10741 | #ifdef CANONICALIZE_COMPARISON |
10742 | /* If this machine only supports a subset of valid comparisons, see if we | |
10743 | can convert an unsupported one into a supported one. */ | |
10744 | CANONICALIZE_COMPARISON (code, op0, op1); | |
10745 | #endif | |
10746 | ||
230d793d RS |
10747 | *pop0 = op0; |
10748 | *pop1 = op1; | |
10749 | ||
10750 | return code; | |
10751 | } | |
10752 | \f | |
49c3b9a8 JJ |
10753 | /* Utility function for record_value_for_reg. Count number of |
10754 | rtxs in X. */ | |
10755 | static int | |
10756 | count_rtxs (rtx x) | |
10757 | { | |
10758 | enum rtx_code code = GET_CODE (x); | |
10759 | const char *fmt; | |
10760 | int i, ret = 1; | |
10761 | ||
10762 | if (GET_RTX_CLASS (code) == '2' | |
10763 | || GET_RTX_CLASS (code) == 'c') | |
10764 | { | |
10765 | rtx x0 = XEXP (x, 0); | |
10766 | rtx x1 = XEXP (x, 1); | |
10767 | ||
10768 | if (x0 == x1) | |
10769 | return 1 + 2 * count_rtxs (x0); | |
10770 | ||
10771 | if ((GET_RTX_CLASS (GET_CODE (x1)) == '2' | |
10772 | || GET_RTX_CLASS (GET_CODE (x1)) == 'c') | |
10773 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) | |
10774 | return 2 + 2 * count_rtxs (x0) | |
10775 | + count_rtxs (x == XEXP (x1, 0) | |
10776 | ? XEXP (x1, 1) : XEXP (x1, 0)); | |
10777 | ||
10778 | if ((GET_RTX_CLASS (GET_CODE (x0)) == '2' | |
10779 | || GET_RTX_CLASS (GET_CODE (x0)) == 'c') | |
10780 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) | |
10781 | return 2 + 2 * count_rtxs (x1) | |
10782 | + count_rtxs (x == XEXP (x0, 0) | |
10783 | ? XEXP (x0, 1) : XEXP (x0, 0)); | |
10784 | } | |
10785 | ||
10786 | fmt = GET_RTX_FORMAT (code); | |
10787 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
10788 | if (fmt[i] == 'e') | |
10789 | ret += count_rtxs (XEXP (x, i)); | |
10790 | ||
10791 | return ret; | |
10792 | } | |
10793 | \f | |
230d793d | 10794 | /* Utility function for following routine. Called when X is part of a value |
5eaad481 | 10795 | being stored into last_set_value. Sets last_set_table_tick |
230d793d RS |
10796 | for each register mentioned. Similar to mention_regs in cse.c */ |
10797 | ||
10798 | static void | |
79a490a9 | 10799 | update_table_tick (rtx x) |
230d793d | 10800 | { |
b3694847 SS |
10801 | enum rtx_code code = GET_CODE (x); |
10802 | const char *fmt = GET_RTX_FORMAT (code); | |
10803 | int i; | |
230d793d RS |
10804 | |
10805 | if (code == REG) | |
10806 | { | |
770ae6cc RK |
10807 | unsigned int regno = REGNO (x); |
10808 | unsigned int endregno | |
10809 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 10810 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
770ae6cc | 10811 | unsigned int r; |
230d793d | 10812 | |
770ae6cc | 10813 | for (r = regno; r < endregno; r++) |
5eaad481 | 10814 | reg_stat[r].last_set_table_tick = label_tick; |
230d793d RS |
10815 | |
10816 | return; | |
10817 | } | |
663522cb | 10818 | |
230d793d RS |
10819 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) |
10820 | /* Note that we can't have an "E" in values stored; see | |
10821 | get_last_value_validate. */ | |
10822 | if (fmt[i] == 'e') | |
8fd73754 AN |
10823 | { |
10824 | /* Check for identical subexpressions. If x contains | |
10825 | identical subexpression we only have to traverse one of | |
10826 | them. */ | |
ec8e098d | 10827 | if (i == 0 && ARITHMETIC_P (x)) |
8fd73754 AN |
10828 | { |
10829 | /* Note that at this point x1 has already been | |
10830 | processed. */ | |
10831 | rtx x0 = XEXP (x, 0); | |
10832 | rtx x1 = XEXP (x, 1); | |
10833 | ||
10834 | /* If x0 and x1 are identical then there is no need to | |
10835 | process x0. */ | |
10836 | if (x0 == x1) | |
10837 | break; | |
10838 | ||
10839 | /* If x0 is identical to a subexpression of x1 then while | |
10840 | processing x1, x0 has already been processed. Thus we | |
10841 | are done with x. */ | |
ec8e098d | 10842 | if (ARITHMETIC_P (x1) |
8fd73754 AN |
10843 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
10844 | break; | |
10845 | ||
10846 | /* If x1 is identical to a subexpression of x0 then we | |
10847 | still have to process the rest of x0. */ | |
ec8e098d | 10848 | if (ARITHMETIC_P (x0) |
8fd73754 AN |
10849 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
10850 | { | |
10851 | update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0)); | |
10852 | break; | |
10853 | } | |
10854 | } | |
73a39fc4 | 10855 | |
8fd73754 AN |
10856 | update_table_tick (XEXP (x, i)); |
10857 | } | |
230d793d RS |
10858 | } |
10859 | ||
10860 | /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
10861 | are saying that the register is clobbered and we no longer know its | |
5eaad481 PB |
10862 | value. If INSN is zero, don't update reg_stat[].last_set; this is |
10863 | only permitted with VALUE also zero and is used to invalidate the | |
10864 | register. */ | |
230d793d RS |
10865 | |
10866 | static void | |
79a490a9 | 10867 | record_value_for_reg (rtx reg, rtx insn, rtx value) |
230d793d | 10868 | { |
770ae6cc RK |
10869 | unsigned int regno = REGNO (reg); |
10870 | unsigned int endregno | |
10871 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 10872 | ? hard_regno_nregs[regno][GET_MODE (reg)] : 1); |
770ae6cc | 10873 | unsigned int i; |
230d793d RS |
10874 | |
10875 | /* If VALUE contains REG and we have a previous value for REG, substitute | |
10876 | the previous value. */ | |
10877 | if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
10878 | { | |
10879 | rtx tem; | |
10880 | ||
10881 | /* Set things up so get_last_value is allowed to see anything set up to | |
10882 | our insn. */ | |
10883 | subst_low_cuid = INSN_CUID (insn); | |
663522cb | 10884 | tem = get_last_value (reg); |
230d793d | 10885 | |
14a774a9 RK |
10886 | /* If TEM is simply a binary operation with two CLOBBERs as operands, |
10887 | it isn't going to be useful and will take a lot of time to process, | |
10888 | so just use the CLOBBER. */ | |
10889 | ||
230d793d | 10890 | if (tem) |
14a774a9 | 10891 | { |
ec8e098d | 10892 | if (ARITHMETIC_P (tem) |
14a774a9 RK |
10893 | && GET_CODE (XEXP (tem, 0)) == CLOBBER |
10894 | && GET_CODE (XEXP (tem, 1)) == CLOBBER) | |
10895 | tem = XEXP (tem, 0); | |
49c3b9a8 JJ |
10896 | else if (count_occurrences (value, reg, 1) >= 2) |
10897 | { | |
10898 | /* If there are two or more occurrences of REG in VALUE, | |
10899 | prevent the value from growing too much. */ | |
10900 | if (count_rtxs (tem) > MAX_LAST_VALUE_RTL) | |
10901 | tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx); | |
10902 | } | |
14a774a9 RK |
10903 | |
10904 | value = replace_rtx (copy_rtx (value), reg, tem); | |
10905 | } | |
230d793d RS |
10906 | } |
10907 | ||
10908 | /* For each register modified, show we don't know its value, that | |
ef026f91 RS |
10909 | we don't know about its bitwise content, that its value has been |
10910 | updated, and that we don't know the location of the death of the | |
10911 | register. */ | |
770ae6cc | 10912 | for (i = regno; i < endregno; i++) |
230d793d RS |
10913 | { |
10914 | if (insn) | |
5eaad481 | 10915 | reg_stat[i].last_set = insn; |
770ae6cc | 10916 | |
5eaad481 PB |
10917 | reg_stat[i].last_set_value = 0; |
10918 | reg_stat[i].last_set_mode = 0; | |
10919 | reg_stat[i].last_set_nonzero_bits = 0; | |
10920 | reg_stat[i].last_set_sign_bit_copies = 0; | |
10921 | reg_stat[i].last_death = 0; | |
230d793d RS |
10922 | } |
10923 | ||
10924 | /* Mark registers that are being referenced in this value. */ | |
10925 | if (value) | |
10926 | update_table_tick (value); | |
10927 | ||
10928 | /* Now update the status of each register being set. | |
10929 | If someone is using this register in this block, set this register | |
10930 | to invalid since we will get confused between the two lives in this | |
10931 | basic block. This makes using this register always invalid. In cse, we | |
10932 | scan the table to invalidate all entries using this register, but this | |
10933 | is too much work for us. */ | |
10934 | ||
10935 | for (i = regno; i < endregno; i++) | |
10936 | { | |
5eaad481 PB |
10937 | reg_stat[i].last_set_label = label_tick; |
10938 | if (value && reg_stat[i].last_set_table_tick == label_tick) | |
10939 | reg_stat[i].last_set_invalid = 1; | |
230d793d | 10940 | else |
5eaad481 | 10941 | reg_stat[i].last_set_invalid = 0; |
230d793d RS |
10942 | } |
10943 | ||
10944 | /* The value being assigned might refer to X (like in "x++;"). In that | |
10945 | case, we must replace it with (clobber (const_int 0)) to prevent | |
10946 | infinite loops. */ | |
9a893315 | 10947 | if (value && ! get_last_value_validate (&value, insn, |
5eaad481 | 10948 | reg_stat[regno].last_set_label, 0)) |
230d793d RS |
10949 | { |
10950 | value = copy_rtx (value); | |
9a893315 | 10951 | if (! get_last_value_validate (&value, insn, |
5eaad481 | 10952 | reg_stat[regno].last_set_label, 1)) |
230d793d RS |
10953 | value = 0; |
10954 | } | |
10955 | ||
55310dad RK |
10956 | /* For the main register being modified, update the value, the mode, the |
10957 | nonzero bits, and the number of sign bit copies. */ | |
10958 | ||
5eaad481 | 10959 | reg_stat[regno].last_set_value = value; |
230d793d | 10960 | |
55310dad RK |
10961 | if (value) |
10962 | { | |
0a0440c9 | 10963 | enum machine_mode mode = GET_MODE (reg); |
2afabb48 | 10964 | subst_low_cuid = INSN_CUID (insn); |
5eaad481 | 10965 | reg_stat[regno].last_set_mode = mode; |
0a0440c9 JJ |
10966 | if (GET_MODE_CLASS (mode) == MODE_INT |
10967 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
10968 | mode = nonzero_bits_mode; | |
5eaad481 PB |
10969 | reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode); |
10970 | reg_stat[regno].last_set_sign_bit_copies | |
55310dad RK |
10971 | = num_sign_bit_copies (value, GET_MODE (reg)); |
10972 | } | |
230d793d RS |
10973 | } |
10974 | ||
230d793d | 10975 | /* Called via note_stores from record_dead_and_set_regs to handle one |
84832317 MM |
10976 | SET or CLOBBER in an insn. DATA is the instruction in which the |
10977 | set is occurring. */ | |
230d793d RS |
10978 | |
10979 | static void | |
79a490a9 | 10980 | record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data) |
230d793d | 10981 | { |
84832317 MM |
10982 | rtx record_dead_insn = (rtx) data; |
10983 | ||
ca89d290 RK |
10984 | if (GET_CODE (dest) == SUBREG) |
10985 | dest = SUBREG_REG (dest); | |
10986 | ||
f8cfc6aa | 10987 | if (REG_P (dest)) |
230d793d RS |
10988 | { |
10989 | /* If we are setting the whole register, we know its value. Otherwise | |
10990 | show that we don't know the value. We can handle SUBREG in | |
10991 | some cases. */ | |
10992 | if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
10993 | record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
10994 | else if (GET_CODE (setter) == SET | |
10995 | && GET_CODE (SET_DEST (setter)) == SUBREG | |
10996 | && SUBREG_REG (SET_DEST (setter)) == dest | |
90bf8081 | 10997 | && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD |
230d793d | 10998 | && subreg_lowpart_p (SET_DEST (setter))) |
d0ab8cd3 | 10999 | record_value_for_reg (dest, record_dead_insn, |
4de249d9 | 11000 | gen_lowpart (GET_MODE (dest), |
d0ab8cd3 | 11001 | SET_SRC (setter))); |
230d793d | 11002 | else |
5f4f0e22 | 11003 | record_value_for_reg (dest, record_dead_insn, NULL_RTX); |
230d793d | 11004 | } |
3c0cb5de | 11005 | else if (MEM_P (dest) |
230d793d RS |
11006 | /* Ignore pushes, they clobber nothing. */ |
11007 | && ! push_operand (dest, GET_MODE (dest))) | |
11008 | mem_last_set = INSN_CUID (record_dead_insn); | |
11009 | } | |
11010 | ||
11011 | /* Update the records of when each REG was most recently set or killed | |
11012 | for the things done by INSN. This is the last thing done in processing | |
11013 | INSN in the combiner loop. | |
11014 | ||
5eaad481 PB |
11015 | We update reg_stat[], in particular fields last_set, last_set_value, |
11016 | last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies, | |
11017 | last_death, and also the similar information mem_last_set (which insn | |
11018 | most recently modified memory) and last_call_cuid (which insn was the | |
11019 | most recent subroutine call). */ | |
230d793d RS |
11020 | |
11021 | static void | |
79a490a9 | 11022 | record_dead_and_set_regs (rtx insn) |
230d793d | 11023 | { |
b3694847 | 11024 | rtx link; |
770ae6cc | 11025 | unsigned int i; |
55310dad | 11026 | |
230d793d RS |
11027 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) |
11028 | { | |
dbc131f3 | 11029 | if (REG_NOTE_KIND (link) == REG_DEAD |
f8cfc6aa | 11030 | && REG_P (XEXP (link, 0))) |
dbc131f3 | 11031 | { |
770ae6cc RK |
11032 | unsigned int regno = REGNO (XEXP (link, 0)); |
11033 | unsigned int endregno | |
dbc131f3 | 11034 | = regno + (regno < FIRST_PSEUDO_REGISTER |
66fd46b6 | 11035 | ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))] |
dbc131f3 | 11036 | : 1); |
dbc131f3 RK |
11037 | |
11038 | for (i = regno; i < endregno; i++) | |
5eaad481 | 11039 | reg_stat[i].last_death = insn; |
dbc131f3 | 11040 | } |
230d793d | 11041 | else if (REG_NOTE_KIND (link) == REG_INC) |
5f4f0e22 | 11042 | record_value_for_reg (XEXP (link, 0), insn, NULL_RTX); |
230d793d RS |
11043 | } |
11044 | ||
4b4bf941 | 11045 | if (CALL_P (insn)) |
55310dad RK |
11046 | { |
11047 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
29655d3d | 11048 | if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i)) |
55310dad | 11049 | { |
5eaad481 PB |
11050 | reg_stat[i].last_set_value = 0; |
11051 | reg_stat[i].last_set_mode = 0; | |
11052 | reg_stat[i].last_set_nonzero_bits = 0; | |
11053 | reg_stat[i].last_set_sign_bit_copies = 0; | |
11054 | reg_stat[i].last_death = 0; | |
55310dad RK |
11055 | } |
11056 | ||
11057 | last_call_cuid = mem_last_set = INSN_CUID (insn); | |
29655d3d ZW |
11058 | |
11059 | /* Don't bother recording what this insn does. It might set the | |
11060 | return value register, but we can't combine into a call | |
11061 | pattern anyway, so there's no point trying (and it may cause | |
11062 | a crash, if e.g. we wind up asking for last_set_value of a | |
11063 | SUBREG of the return value register). */ | |
11064 | return; | |
55310dad | 11065 | } |
230d793d | 11066 | |
84832317 | 11067 | note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn); |
230d793d | 11068 | } |
732f2ac9 | 11069 | |
732f2ac9 JJ |
11070 | /* If a SUBREG has the promoted bit set, it is in fact a property of the |
11071 | register present in the SUBREG, so for each such SUBREG go back and | |
11072 | adjust nonzero and sign bit information of the registers that are | |
11073 | known to have some zero/sign bits set. | |
11074 | ||
11075 | This is needed because when combine blows the SUBREGs away, the | |
11076 | information on zero/sign bits is lost and further combines can be | |
11077 | missed because of that. */ | |
11078 | ||
11079 | static void | |
79a490a9 | 11080 | record_promoted_value (rtx insn, rtx subreg) |
732f2ac9 | 11081 | { |
4a71b24f | 11082 | rtx links, set; |
770ae6cc | 11083 | unsigned int regno = REGNO (SUBREG_REG (subreg)); |
732f2ac9 JJ |
11084 | enum machine_mode mode = GET_MODE (subreg); |
11085 | ||
25af74a0 | 11086 | if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT) |
732f2ac9 JJ |
11087 | return; |
11088 | ||
663522cb | 11089 | for (links = LOG_LINKS (insn); links;) |
732f2ac9 JJ |
11090 | { |
11091 | insn = XEXP (links, 0); | |
11092 | set = single_set (insn); | |
11093 | ||
f8cfc6aa | 11094 | if (! set || !REG_P (SET_DEST (set)) |
732f2ac9 JJ |
11095 | || REGNO (SET_DEST (set)) != regno |
11096 | || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg))) | |
11097 | { | |
11098 | links = XEXP (links, 1); | |
11099 | continue; | |
11100 | } | |
11101 | ||
5eaad481 | 11102 | if (reg_stat[regno].last_set == insn) |
663522cb | 11103 | { |
7879b81e | 11104 | if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0) |
5eaad481 | 11105 | reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode); |
663522cb | 11106 | } |
732f2ac9 | 11107 | |
f8cfc6aa | 11108 | if (REG_P (SET_SRC (set))) |
732f2ac9 JJ |
11109 | { |
11110 | regno = REGNO (SET_SRC (set)); | |
11111 | links = LOG_LINKS (insn); | |
11112 | } | |
11113 | else | |
11114 | break; | |
11115 | } | |
11116 | } | |
11117 | ||
11118 | /* Scan X for promoted SUBREGs. For each one found, | |
11119 | note what it implies to the registers used in it. */ | |
11120 | ||
11121 | static void | |
79a490a9 | 11122 | check_promoted_subreg (rtx insn, rtx x) |
732f2ac9 JJ |
11123 | { |
11124 | if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x) | |
f8cfc6aa | 11125 | && REG_P (SUBREG_REG (x))) |
732f2ac9 JJ |
11126 | record_promoted_value (insn, x); |
11127 | else | |
11128 | { | |
11129 | const char *format = GET_RTX_FORMAT (GET_CODE (x)); | |
11130 | int i, j; | |
11131 | ||
11132 | for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++) | |
663522cb | 11133 | switch (format[i]) |
732f2ac9 JJ |
11134 | { |
11135 | case 'e': | |
11136 | check_promoted_subreg (insn, XEXP (x, i)); | |
11137 | break; | |
11138 | case 'V': | |
11139 | case 'E': | |
11140 | if (XVEC (x, i) != 0) | |
11141 | for (j = 0; j < XVECLEN (x, i); j++) | |
11142 | check_promoted_subreg (insn, XVECEXP (x, i, j)); | |
11143 | break; | |
11144 | } | |
11145 | } | |
11146 | } | |
230d793d RS |
11147 | \f |
11148 | /* Utility routine for the following function. Verify that all the registers | |
11149 | mentioned in *LOC are valid when *LOC was part of a value set when | |
11150 | label_tick == TICK. Return 0 if some are not. | |
11151 | ||
da7d8304 | 11152 | If REPLACE is nonzero, replace the invalid reference with |
230d793d RS |
11153 | (clobber (const_int 0)) and return 1. This replacement is useful because |
11154 | we often can get useful information about the form of a value (e.g., if | |
11155 | it was produced by a shift that always produces -1 or 0) even though | |
11156 | we don't know exactly what registers it was produced from. */ | |
11157 | ||
11158 | static int | |
79a490a9 | 11159 | get_last_value_validate (rtx *loc, rtx insn, int tick, int replace) |
230d793d RS |
11160 | { |
11161 | rtx x = *loc; | |
6f7d635c | 11162 | const char *fmt = GET_RTX_FORMAT (GET_CODE (x)); |
230d793d RS |
11163 | int len = GET_RTX_LENGTH (GET_CODE (x)); |
11164 | int i; | |
11165 | ||
f8cfc6aa | 11166 | if (REG_P (x)) |
230d793d | 11167 | { |
770ae6cc RK |
11168 | unsigned int regno = REGNO (x); |
11169 | unsigned int endregno | |
11170 | = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11171 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
770ae6cc | 11172 | unsigned int j; |
230d793d RS |
11173 | |
11174 | for (j = regno; j < endregno; j++) | |
5eaad481 | 11175 | if (reg_stat[j].last_set_invalid |
57cf50a4 GRK |
11176 | /* If this is a pseudo-register that was only set once and not |
11177 | live at the beginning of the function, it is always valid. */ | |
663522cb | 11178 | || (! (regno >= FIRST_PSEUDO_REGISTER |
57cf50a4 | 11179 | && REG_N_SETS (regno) == 1 |
770ae6cc | 11180 | && (! REGNO_REG_SET_P |
f6366fc7 | 11181 | (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno))) |
5eaad481 | 11182 | && reg_stat[j].last_set_label > tick)) |
230d793d RS |
11183 | { |
11184 | if (replace) | |
38a448ca | 11185 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
230d793d RS |
11186 | return replace; |
11187 | } | |
11188 | ||
11189 | return 1; | |
11190 | } | |
9a893315 JW |
11191 | /* If this is a memory reference, make sure that there were |
11192 | no stores after it that might have clobbered the value. We don't | |
11193 | have alias info, so we assume any store invalidates it. */ | |
389fdba0 | 11194 | else if (MEM_P (x) && !MEM_READONLY_P (x) |
9a893315 JW |
11195 | && INSN_CUID (insn) <= mem_last_set) |
11196 | { | |
11197 | if (replace) | |
38a448ca | 11198 | *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); |
9a893315 JW |
11199 | return replace; |
11200 | } | |
230d793d RS |
11201 | |
11202 | for (i = 0; i < len; i++) | |
8fd73754 AN |
11203 | { |
11204 | if (fmt[i] == 'e') | |
11205 | { | |
11206 | /* Check for identical subexpressions. If x contains | |
11207 | identical subexpression we only have to traverse one of | |
11208 | them. */ | |
ec8e098d | 11209 | if (i == 1 && ARITHMETIC_P (x)) |
8fd73754 AN |
11210 | { |
11211 | /* Note that at this point x0 has already been checked | |
11212 | and found valid. */ | |
11213 | rtx x0 = XEXP (x, 0); | |
11214 | rtx x1 = XEXP (x, 1); | |
11215 | ||
11216 | /* If x0 and x1 are identical then x is also valid. */ | |
11217 | if (x0 == x1) | |
11218 | return 1; | |
11219 | ||
11220 | /* If x1 is identical to a subexpression of x0 then | |
11221 | while checking x0, x1 has already been checked. Thus | |
11222 | it is valid and so as x. */ | |
ec8e098d | 11223 | if (ARITHMETIC_P (x0) |
8fd73754 AN |
11224 | && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) |
11225 | return 1; | |
11226 | ||
11227 | /* If x0 is identical to a subexpression of x1 then x is | |
11228 | valid iff the rest of x1 is valid. */ | |
ec8e098d | 11229 | if (ARITHMETIC_P (x1) |
8fd73754 AN |
11230 | && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) |
11231 | return | |
11232 | get_last_value_validate (&XEXP (x1, | |
11233 | x0 == XEXP (x1, 0) ? 1 : 0), | |
11234 | insn, tick, replace); | |
11235 | } | |
11236 | ||
11237 | if (get_last_value_validate (&XEXP (x, i), insn, tick, | |
11238 | replace) == 0) | |
11239 | return 0; | |
11240 | } | |
11241 | /* Don't bother with these. They shouldn't occur anyway. */ | |
11242 | else if (fmt[i] == 'E') | |
11243 | return 0; | |
11244 | } | |
230d793d RS |
11245 | |
11246 | /* If we haven't found a reason for it to be invalid, it is valid. */ | |
11247 | return 1; | |
11248 | } | |
11249 | ||
11250 | /* Get the last value assigned to X, if known. Some registers | |
11251 | in the value may be replaced with (clobber (const_int 0)) if their value | |
11252 | is known longer known reliably. */ | |
11253 | ||
11254 | static rtx | |
79a490a9 | 11255 | get_last_value (rtx x) |
230d793d | 11256 | { |
770ae6cc | 11257 | unsigned int regno; |
230d793d RS |
11258 | rtx value; |
11259 | ||
11260 | /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
11261 | then convert it to the desired mode. If this is a paradoxical SUBREG, | |
0f41302f | 11262 | we cannot predict what values the "extra" bits might have. */ |
230d793d RS |
11263 | if (GET_CODE (x) == SUBREG |
11264 | && subreg_lowpart_p (x) | |
11265 | && (GET_MODE_SIZE (GET_MODE (x)) | |
11266 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
11267 | && (value = get_last_value (SUBREG_REG (x))) != 0) | |
4de249d9 | 11268 | return gen_lowpart (GET_MODE (x), value); |
230d793d | 11269 | |
f8cfc6aa | 11270 | if (!REG_P (x)) |
230d793d RS |
11271 | return 0; |
11272 | ||
11273 | regno = REGNO (x); | |
5eaad481 | 11274 | value = reg_stat[regno].last_set_value; |
230d793d | 11275 | |
57cf50a4 GRK |
11276 | /* If we don't have a value, or if it isn't for this basic block and |
11277 | it's either a hard register, set more than once, or it's a live | |
663522cb | 11278 | at the beginning of the function, return 0. |
57cf50a4 | 11279 | |
eaec9b3d | 11280 | Because if it's not live at the beginning of the function then the reg |
57cf50a4 GRK |
11281 | is always set before being used (is never used without being set). |
11282 | And, if it's set only once, and it's always set before use, then all | |
11283 | uses must have the same last value, even if it's not from this basic | |
11284 | block. */ | |
230d793d RS |
11285 | |
11286 | if (value == 0 | |
5eaad481 | 11287 | || (reg_stat[regno].last_set_label != label_tick |
57cf50a4 GRK |
11288 | && (regno < FIRST_PSEUDO_REGISTER |
11289 | || REG_N_SETS (regno) != 1 | |
770ae6cc | 11290 | || (REGNO_REG_SET_P |
f6366fc7 | 11291 | (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno))))) |
230d793d RS |
11292 | return 0; |
11293 | ||
4255220d | 11294 | /* If the value was set in a later insn than the ones we are processing, |
ca4cd906 | 11295 | we can't use it even if the register was only set once. */ |
5eaad481 | 11296 | if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid) |
ca4cd906 | 11297 | return 0; |
d0ab8cd3 RK |
11298 | |
11299 | /* If the value has all its registers valid, return it. */ | |
5eaad481 PB |
11300 | if (get_last_value_validate (&value, reg_stat[regno].last_set, |
11301 | reg_stat[regno].last_set_label, 0)) | |
230d793d RS |
11302 | return value; |
11303 | ||
11304 | /* Otherwise, make a copy and replace any invalid register with | |
11305 | (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
11306 | ||
11307 | value = copy_rtx (value); | |
5eaad481 PB |
11308 | if (get_last_value_validate (&value, reg_stat[regno].last_set, |
11309 | reg_stat[regno].last_set_label, 1)) | |
230d793d RS |
11310 | return value; |
11311 | ||
11312 | return 0; | |
11313 | } | |
11314 | \f | |
11315 | /* Return nonzero if expression X refers to a REG or to memory | |
11316 | that is set in an instruction more recent than FROM_CUID. */ | |
11317 | ||
11318 | static int | |
79a490a9 | 11319 | use_crosses_set_p (rtx x, int from_cuid) |
230d793d | 11320 | { |
b3694847 SS |
11321 | const char *fmt; |
11322 | int i; | |
11323 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
11324 | |
11325 | if (code == REG) | |
11326 | { | |
770ae6cc RK |
11327 | unsigned int regno = REGNO (x); |
11328 | unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11329 | ? hard_regno_nregs[regno][GET_MODE (x)] : 1); |
663522cb | 11330 | |
230d793d RS |
11331 | #ifdef PUSH_ROUNDING |
11332 | /* Don't allow uses of the stack pointer to be moved, | |
11333 | because we don't know whether the move crosses a push insn. */ | |
f73ad30e | 11334 | if (regno == STACK_POINTER_REGNUM && PUSH_ARGS) |
230d793d RS |
11335 | return 1; |
11336 | #endif | |
770ae6cc | 11337 | for (; regno < endreg; regno++) |
5eaad481 PB |
11338 | if (reg_stat[regno].last_set |
11339 | && INSN_CUID (reg_stat[regno].last_set) > from_cuid) | |
e28f5732 RK |
11340 | return 1; |
11341 | return 0; | |
230d793d RS |
11342 | } |
11343 | ||
11344 | if (code == MEM && mem_last_set > from_cuid) | |
11345 | return 1; | |
11346 | ||
11347 | fmt = GET_RTX_FORMAT (code); | |
11348 | ||
11349 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11350 | { | |
11351 | if (fmt[i] == 'E') | |
11352 | { | |
b3694847 | 11353 | int j; |
230d793d RS |
11354 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
11355 | if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) | |
11356 | return 1; | |
11357 | } | |
11358 | else if (fmt[i] == 'e' | |
11359 | && use_crosses_set_p (XEXP (x, i), from_cuid)) | |
11360 | return 1; | |
11361 | } | |
11362 | return 0; | |
11363 | } | |
11364 | \f | |
11365 | /* Define three variables used for communication between the following | |
11366 | routines. */ | |
11367 | ||
770ae6cc | 11368 | static unsigned int reg_dead_regno, reg_dead_endregno; |
230d793d RS |
11369 | static int reg_dead_flag; |
11370 | ||
11371 | /* Function called via note_stores from reg_dead_at_p. | |
11372 | ||
663522cb | 11373 | If DEST is within [reg_dead_regno, reg_dead_endregno), set |
230d793d RS |
11374 | reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ |
11375 | ||
11376 | static void | |
79a490a9 | 11377 | reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED) |
230d793d | 11378 | { |
770ae6cc | 11379 | unsigned int regno, endregno; |
230d793d | 11380 | |
f8cfc6aa | 11381 | if (!REG_P (dest)) |
230d793d RS |
11382 | return; |
11383 | ||
11384 | regno = REGNO (dest); | |
663522cb | 11385 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER |
66fd46b6 | 11386 | ? hard_regno_nregs[regno][GET_MODE (dest)] : 1); |
230d793d RS |
11387 | |
11388 | if (reg_dead_endregno > regno && reg_dead_regno < endregno) | |
11389 | reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
11390 | } | |
11391 | ||
da7d8304 | 11392 | /* Return nonzero if REG is known to be dead at INSN. |
230d793d RS |
11393 | |
11394 | We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
11395 | referencing REG, it is dead. If we hit a SET referencing REG, it is | |
11396 | live. Otherwise, see if it is live or dead at the start of the basic | |
6e25d159 RK |
11397 | block we are in. Hard regs marked as being live in NEWPAT_USED_REGS |
11398 | must be assumed to be always live. */ | |
230d793d RS |
11399 | |
11400 | static int | |
79a490a9 | 11401 | reg_dead_at_p (rtx reg, rtx insn) |
230d793d | 11402 | { |
e0082a72 | 11403 | basic_block block; |
770ae6cc | 11404 | unsigned int i; |
230d793d RS |
11405 | |
11406 | /* Set variables for reg_dead_at_p_1. */ | |
11407 | reg_dead_regno = REGNO (reg); | |
11408 | reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 JH |
11409 | ? hard_regno_nregs[reg_dead_regno] |
11410 | [GET_MODE (reg)] | |
230d793d RS |
11411 | : 1); |
11412 | ||
11413 | reg_dead_flag = 0; | |
11414 | ||
45da19e3 UW |
11415 | /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers |
11416 | we allow the machine description to decide whether use-and-clobber | |
11417 | patterns are OK. */ | |
6e25d159 RK |
11418 | if (reg_dead_regno < FIRST_PSEUDO_REGISTER) |
11419 | { | |
11420 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
45da19e3 | 11421 | if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i)) |
6e25d159 RK |
11422 | return 0; |
11423 | } | |
11424 | ||
230d793d RS |
11425 | /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or |
11426 | beginning of function. */ | |
4b4bf941 | 11427 | for (; insn && !LABEL_P (insn) && !BARRIER_P (insn); |
230d793d RS |
11428 | insn = prev_nonnote_insn (insn)) |
11429 | { | |
84832317 | 11430 | note_stores (PATTERN (insn), reg_dead_at_p_1, NULL); |
230d793d RS |
11431 | if (reg_dead_flag) |
11432 | return reg_dead_flag == 1 ? 1 : 0; | |
11433 | ||
11434 | if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) | |
11435 | return 1; | |
11436 | } | |
11437 | ||
e0082a72 | 11438 | /* Get the basic block that we were in. */ |
230d793d | 11439 | if (insn == 0) |
e0082a72 | 11440 | block = ENTRY_BLOCK_PTR->next_bb; |
230d793d RS |
11441 | else |
11442 | { | |
e0082a72 | 11443 | FOR_EACH_BB (block) |
a813c111 | 11444 | if (insn == BB_HEAD (block)) |
230d793d RS |
11445 | break; |
11446 | ||
e0082a72 | 11447 | if (block == EXIT_BLOCK_PTR) |
230d793d RS |
11448 | return 0; |
11449 | } | |
11450 | ||
11451 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
e0082a72 | 11452 | if (REGNO_REG_SET_P (block->global_live_at_start, i)) |
230d793d RS |
11453 | return 0; |
11454 | ||
11455 | return 1; | |
11456 | } | |
6e25d159 RK |
11457 | \f |
11458 | /* Note hard registers in X that are used. This code is similar to | |
11459 | that in flow.c, but much simpler since we don't care about pseudos. */ | |
11460 | ||
11461 | static void | |
79a490a9 | 11462 | mark_used_regs_combine (rtx x) |
6e25d159 | 11463 | { |
770ae6cc RK |
11464 | RTX_CODE code = GET_CODE (x); |
11465 | unsigned int regno; | |
6e25d159 RK |
11466 | int i; |
11467 | ||
11468 | switch (code) | |
11469 | { | |
11470 | case LABEL_REF: | |
11471 | case SYMBOL_REF: | |
11472 | case CONST_INT: | |
11473 | case CONST: | |
11474 | case CONST_DOUBLE: | |
69ef87e2 | 11475 | case CONST_VECTOR: |
6e25d159 RK |
11476 | case PC: |
11477 | case ADDR_VEC: | |
11478 | case ADDR_DIFF_VEC: | |
11479 | case ASM_INPUT: | |
11480 | #ifdef HAVE_cc0 | |
11481 | /* CC0 must die in the insn after it is set, so we don't need to take | |
11482 | special note of it here. */ | |
11483 | case CC0: | |
11484 | #endif | |
11485 | return; | |
11486 | ||
11487 | case CLOBBER: | |
11488 | /* If we are clobbering a MEM, mark any hard registers inside the | |
11489 | address as used. */ | |
3c0cb5de | 11490 | if (MEM_P (XEXP (x, 0))) |
6e25d159 RK |
11491 | mark_used_regs_combine (XEXP (XEXP (x, 0), 0)); |
11492 | return; | |
11493 | ||
11494 | case REG: | |
11495 | regno = REGNO (x); | |
11496 | /* A hard reg in a wide mode may really be multiple registers. | |
11497 | If so, mark all of them just like the first. */ | |
11498 | if (regno < FIRST_PSEUDO_REGISTER) | |
11499 | { | |
770ae6cc RK |
11500 | unsigned int endregno, r; |
11501 | ||
3eae4643 | 11502 | /* None of this applies to the stack, frame or arg pointers. */ |
6e25d159 RK |
11503 | if (regno == STACK_POINTER_REGNUM |
11504 | #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM | |
11505 | || regno == HARD_FRAME_POINTER_REGNUM | |
11506 | #endif | |
11507 | #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM | |
11508 | || (regno == ARG_POINTER_REGNUM && fixed_regs[regno]) | |
11509 | #endif | |
11510 | || regno == FRAME_POINTER_REGNUM) | |
11511 | return; | |
11512 | ||
66fd46b6 | 11513 | endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc RK |
11514 | for (r = regno; r < endregno; r++) |
11515 | SET_HARD_REG_BIT (newpat_used_regs, r); | |
6e25d159 RK |
11516 | } |
11517 | return; | |
11518 | ||
11519 | case SET: | |
11520 | { | |
11521 | /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in | |
11522 | the address. */ | |
b3694847 | 11523 | rtx testreg = SET_DEST (x); |
6e25d159 | 11524 | |
e048778f RK |
11525 | while (GET_CODE (testreg) == SUBREG |
11526 | || GET_CODE (testreg) == ZERO_EXTRACT | |
e048778f | 11527 | || GET_CODE (testreg) == STRICT_LOW_PART) |
6e25d159 RK |
11528 | testreg = XEXP (testreg, 0); |
11529 | ||
3c0cb5de | 11530 | if (MEM_P (testreg)) |
6e25d159 RK |
11531 | mark_used_regs_combine (XEXP (testreg, 0)); |
11532 | ||
11533 | mark_used_regs_combine (SET_SRC (x)); | |
6e25d159 | 11534 | } |
e9a25f70 JL |
11535 | return; |
11536 | ||
11537 | default: | |
11538 | break; | |
6e25d159 RK |
11539 | } |
11540 | ||
11541 | /* Recursively scan the operands of this expression. */ | |
11542 | ||
11543 | { | |
b3694847 | 11544 | const char *fmt = GET_RTX_FORMAT (code); |
6e25d159 RK |
11545 | |
11546 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
11547 | { | |
663522cb | 11548 | if (fmt[i] == 'e') |
6e25d159 | 11549 | mark_used_regs_combine (XEXP (x, i)); |
663522cb KH |
11550 | else if (fmt[i] == 'E') |
11551 | { | |
b3694847 | 11552 | int j; |
6e25d159 | 11553 | |
663522cb KH |
11554 | for (j = 0; j < XVECLEN (x, i); j++) |
11555 | mark_used_regs_combine (XVECEXP (x, i, j)); | |
11556 | } | |
6e25d159 RK |
11557 | } |
11558 | } | |
11559 | } | |
230d793d RS |
11560 | \f |
11561 | /* Remove register number REGNO from the dead registers list of INSN. | |
11562 | ||
11563 | Return the note used to record the death, if there was one. */ | |
11564 | ||
11565 | rtx | |
79a490a9 | 11566 | remove_death (unsigned int regno, rtx insn) |
230d793d | 11567 | { |
b3694847 | 11568 | rtx note = find_regno_note (insn, REG_DEAD, regno); |
230d793d RS |
11569 | |
11570 | if (note) | |
1a26b032 | 11571 | { |
b1f21e0a | 11572 | REG_N_DEATHS (regno)--; |
1a26b032 RK |
11573 | remove_note (insn, note); |
11574 | } | |
230d793d RS |
11575 | |
11576 | return note; | |
11577 | } | |
11578 | ||
11579 | /* For each register (hardware or pseudo) used within expression X, if its | |
11580 | death is in an instruction with cuid between FROM_CUID (inclusive) and | |
11581 | TO_INSN (exclusive), put a REG_DEAD note for that register in the | |
663522cb | 11582 | list headed by PNOTES. |
230d793d | 11583 | |
6eb12cef RK |
11584 | That said, don't move registers killed by maybe_kill_insn. |
11585 | ||
230d793d RS |
11586 | This is done when X is being merged by combination into TO_INSN. These |
11587 | notes will then be distributed as needed. */ | |
11588 | ||
11589 | static void | |
79a490a9 AJ |
11590 | move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn, |
11591 | rtx *pnotes) | |
230d793d | 11592 | { |
b3694847 SS |
11593 | const char *fmt; |
11594 | int len, i; | |
11595 | enum rtx_code code = GET_CODE (x); | |
230d793d RS |
11596 | |
11597 | if (code == REG) | |
11598 | { | |
770ae6cc | 11599 | unsigned int regno = REGNO (x); |
5eaad481 | 11600 | rtx where_dead = reg_stat[regno].last_death; |
b3694847 | 11601 | rtx before_dead, after_dead; |
e340018d | 11602 | |
3eae4643 | 11603 | /* Don't move the register if it gets killed in between from and to. */ |
6eb12cef | 11604 | if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn) |
770ae6cc | 11605 | && ! reg_referenced_p (x, maybe_kill_insn)) |
6eb12cef RK |
11606 | return; |
11607 | ||
e340018d JW |
11608 | /* WHERE_DEAD could be a USE insn made by combine, so first we |
11609 | make sure that we have insns with valid INSN_CUID values. */ | |
11610 | before_dead = where_dead; | |
11611 | while (before_dead && INSN_UID (before_dead) > max_uid_cuid) | |
11612 | before_dead = PREV_INSN (before_dead); | |
770ae6cc | 11613 | |
e340018d JW |
11614 | after_dead = where_dead; |
11615 | while (after_dead && INSN_UID (after_dead) > max_uid_cuid) | |
11616 | after_dead = NEXT_INSN (after_dead); | |
11617 | ||
11618 | if (before_dead && after_dead | |
11619 | && INSN_CUID (before_dead) >= from_cuid | |
11620 | && (INSN_CUID (after_dead) < INSN_CUID (to_insn) | |
11621 | || (where_dead != after_dead | |
11622 | && INSN_CUID (after_dead) == INSN_CUID (to_insn)))) | |
230d793d | 11623 | { |
dbc131f3 | 11624 | rtx note = remove_death (regno, where_dead); |
230d793d RS |
11625 | |
11626 | /* It is possible for the call above to return 0. This can occur | |
5eaad481 | 11627 | when last_death points to I2 or I1 that we combined with. |
dbc131f3 RK |
11628 | In that case make a new note. |
11629 | ||
11630 | We must also check for the case where X is a hard register | |
11631 | and NOTE is a death note for a range of hard registers | |
11632 | including X. In that case, we must put REG_DEAD notes for | |
11633 | the remaining registers in place of NOTE. */ | |
11634 | ||
11635 | if (note != 0 && regno < FIRST_PSEUDO_REGISTER | |
11636 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
24e46fc4 | 11637 | > GET_MODE_SIZE (GET_MODE (x)))) |
dbc131f3 | 11638 | { |
770ae6cc RK |
11639 | unsigned int deadregno = REGNO (XEXP (note, 0)); |
11640 | unsigned int deadend | |
66fd46b6 JH |
11641 | = (deadregno + hard_regno_nregs[deadregno] |
11642 | [GET_MODE (XEXP (note, 0))]); | |
770ae6cc | 11643 | unsigned int ourend |
66fd46b6 | 11644 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 11645 | unsigned int i; |
dbc131f3 RK |
11646 | |
11647 | for (i = deadregno; i < deadend; i++) | |
11648 | if (i < regno || i >= ourend) | |
11649 | REG_NOTES (where_dead) | |
38a448ca | 11650 | = gen_rtx_EXPR_LIST (REG_DEAD, |
e50126e8 | 11651 | regno_reg_rtx[i], |
38a448ca | 11652 | REG_NOTES (where_dead)); |
dbc131f3 | 11653 | } |
770ae6cc | 11654 | |
24e46fc4 JW |
11655 | /* If we didn't find any note, or if we found a REG_DEAD note that |
11656 | covers only part of the given reg, and we have a multi-reg hard | |
fabd69e8 RK |
11657 | register, then to be safe we must check for REG_DEAD notes |
11658 | for each register other than the first. They could have | |
11659 | their own REG_DEAD notes lying around. */ | |
24e46fc4 JW |
11660 | else if ((note == 0 |
11661 | || (note != 0 | |
11662 | && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0))) | |
11663 | < GET_MODE_SIZE (GET_MODE (x))))) | |
11664 | && regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 11665 | && hard_regno_nregs[regno][GET_MODE (x)] > 1) |
fabd69e8 | 11666 | { |
770ae6cc | 11667 | unsigned int ourend |
66fd46b6 | 11668 | = regno + hard_regno_nregs[regno][GET_MODE (x)]; |
770ae6cc | 11669 | unsigned int i, offset; |
fabd69e8 RK |
11670 | rtx oldnotes = 0; |
11671 | ||
24e46fc4 | 11672 | if (note) |
66fd46b6 | 11673 | offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))]; |
24e46fc4 JW |
11674 | else |
11675 | offset = 1; | |
11676 | ||
11677 | for (i = regno + offset; i < ourend; i++) | |
e50126e8 | 11678 | move_deaths (regno_reg_rtx[i], |
6eb12cef | 11679 | maybe_kill_insn, from_cuid, to_insn, &oldnotes); |
fabd69e8 | 11680 | } |
230d793d | 11681 | |
dbc131f3 | 11682 | if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x)) |
230d793d RS |
11683 | { |
11684 | XEXP (note, 1) = *pnotes; | |
11685 | *pnotes = note; | |
11686 | } | |
11687 | else | |
38a448ca | 11688 | *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes); |
1a26b032 | 11689 | |
b1f21e0a | 11690 | REG_N_DEATHS (regno)++; |
230d793d RS |
11691 | } |
11692 | ||
11693 | return; | |
11694 | } | |
11695 | ||
11696 | else if (GET_CODE (x) == SET) | |
11697 | { | |
11698 | rtx dest = SET_DEST (x); | |
11699 | ||
6eb12cef | 11700 | move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d | 11701 | |
a7c99304 RK |
11702 | /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG |
11703 | that accesses one word of a multi-word item, some | |
11704 | piece of everything register in the expression is used by | |
11705 | this insn, so remove any old death. */ | |
ddef6bc7 | 11706 | /* ??? So why do we test for equality of the sizes? */ |
a7c99304 RK |
11707 | |
11708 | if (GET_CODE (dest) == ZERO_EXTRACT | |
11709 | || GET_CODE (dest) == STRICT_LOW_PART | |
11710 | || (GET_CODE (dest) == SUBREG | |
11711 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
11712 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
11713 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
11714 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
230d793d | 11715 | { |
6eb12cef | 11716 | move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes); |
a7c99304 | 11717 | return; |
230d793d RS |
11718 | } |
11719 | ||
a7c99304 RK |
11720 | /* If this is some other SUBREG, we know it replaces the entire |
11721 | value, so use that as the destination. */ | |
11722 | if (GET_CODE (dest) == SUBREG) | |
11723 | dest = SUBREG_REG (dest); | |
11724 | ||
11725 | /* If this is a MEM, adjust deaths of anything used in the address. | |
11726 | For a REG (the only other possibility), the entire value is | |
11727 | being replaced so the old value is not used in this insn. */ | |
230d793d | 11728 | |
3c0cb5de | 11729 | if (MEM_P (dest)) |
6eb12cef RK |
11730 | move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid, |
11731 | to_insn, pnotes); | |
230d793d RS |
11732 | return; |
11733 | } | |
11734 | ||
11735 | else if (GET_CODE (x) == CLOBBER) | |
11736 | return; | |
11737 | ||
11738 | len = GET_RTX_LENGTH (code); | |
11739 | fmt = GET_RTX_FORMAT (code); | |
11740 | ||
11741 | for (i = 0; i < len; i++) | |
11742 | { | |
11743 | if (fmt[i] == 'E') | |
11744 | { | |
b3694847 | 11745 | int j; |
230d793d | 11746 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) |
6eb12cef RK |
11747 | move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid, |
11748 | to_insn, pnotes); | |
230d793d RS |
11749 | } |
11750 | else if (fmt[i] == 'e') | |
6eb12cef | 11751 | move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes); |
230d793d RS |
11752 | } |
11753 | } | |
11754 | \f | |
a7c99304 RK |
11755 | /* Return 1 if X is the target of a bit-field assignment in BODY, the |
11756 | pattern of an insn. X must be a REG. */ | |
230d793d RS |
11757 | |
11758 | static int | |
79a490a9 | 11759 | reg_bitfield_target_p (rtx x, rtx body) |
230d793d RS |
11760 | { |
11761 | int i; | |
11762 | ||
11763 | if (GET_CODE (body) == SET) | |
a7c99304 RK |
11764 | { |
11765 | rtx dest = SET_DEST (body); | |
11766 | rtx target; | |
770ae6cc | 11767 | unsigned int regno, tregno, endregno, endtregno; |
a7c99304 RK |
11768 | |
11769 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
11770 | target = XEXP (dest, 0); | |
11771 | else if (GET_CODE (dest) == STRICT_LOW_PART) | |
11772 | target = SUBREG_REG (XEXP (dest, 0)); | |
11773 | else | |
11774 | return 0; | |
11775 | ||
11776 | if (GET_CODE (target) == SUBREG) | |
11777 | target = SUBREG_REG (target); | |
11778 | ||
f8cfc6aa | 11779 | if (!REG_P (target)) |
a7c99304 RK |
11780 | return 0; |
11781 | ||
11782 | tregno = REGNO (target), regno = REGNO (x); | |
11783 | if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
11784 | return target == x; | |
11785 | ||
66fd46b6 JH |
11786 | endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)]; |
11787 | endregno = regno + hard_regno_nregs[regno][GET_MODE (x)]; | |
a7c99304 RK |
11788 | |
11789 | return endregno > tregno && regno < endtregno; | |
11790 | } | |
230d793d RS |
11791 | |
11792 | else if (GET_CODE (body) == PARALLEL) | |
11793 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
a7c99304 | 11794 | if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) |
230d793d RS |
11795 | return 1; |
11796 | ||
11797 | return 0; | |
663522cb | 11798 | } |
230d793d RS |
11799 | \f |
11800 | /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
11801 | as appropriate. I3 and I2 are the insns resulting from the combination | |
11802 | insns including FROM (I2 may be zero). | |
11803 | ||
230d793d RS |
11804 | Each note in the list is either ignored or placed on some insns, depending |
11805 | on the type of note. */ | |
11806 | ||
11807 | static void | |
79a490a9 | 11808 | distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2) |
230d793d RS |
11809 | { |
11810 | rtx note, next_note; | |
11811 | rtx tem; | |
11812 | ||
11813 | for (note = notes; note; note = next_note) | |
11814 | { | |
11815 | rtx place = 0, place2 = 0; | |
11816 | ||
11817 | /* If this NOTE references a pseudo register, ensure it references | |
11818 | the latest copy of that register. */ | |
f8cfc6aa | 11819 | if (XEXP (note, 0) && REG_P (XEXP (note, 0)) |
230d793d RS |
11820 | && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) |
11821 | XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; | |
11822 | ||
11823 | next_note = XEXP (note, 1); | |
11824 | switch (REG_NOTE_KIND (note)) | |
11825 | { | |
c9903b44 | 11826 | case REG_BR_PROB: |
4db384c9 | 11827 | case REG_BR_PRED: |
c9903b44 DE |
11828 | /* Doesn't matter much where we put this, as long as it's somewhere. |
11829 | It is preferable to keep these notes on branches, which is most | |
11830 | likely to be i3. */ | |
4a8d0c9c RH |
11831 | place = i3; |
11832 | break; | |
11833 | ||
6e885ee3 ZD |
11834 | case REG_VALUE_PROFILE: |
11835 | /* Just get rid of this note, as it is unused later anyway. */ | |
11836 | break; | |
11837 | ||
f7cfa78d | 11838 | case REG_NON_LOCAL_GOTO: |
4b4bf941 | 11839 | if (JUMP_P (i3)) |
f7cfa78d | 11840 | place = i3; |
f7cfa78d | 11841 | else |
341c100f NS |
11842 | { |
11843 | gcc_assert (i2 && JUMP_P (i2)); | |
11844 | place = i2; | |
11845 | } | |
f7cfa78d GS |
11846 | break; |
11847 | ||
4b7c585f | 11848 | case REG_EH_REGION: |
662795a8 | 11849 | /* These notes must remain with the call or trapping instruction. */ |
4b4bf941 | 11850 | if (CALL_P (i3)) |
662795a8 | 11851 | place = i3; |
4b4bf941 | 11852 | else if (i2 && CALL_P (i2)) |
662795a8 | 11853 | place = i2; |
341c100f | 11854 | else |
662795a8 | 11855 | { |
341c100f | 11856 | gcc_assert (flag_non_call_exceptions); |
662795a8 RH |
11857 | if (may_trap_p (i3)) |
11858 | place = i3; | |
11859 | else if (i2 && may_trap_p (i2)) | |
11860 | place = i2; | |
11861 | /* ??? Otherwise assume we've combined things such that we | |
11862 | can now prove that the instructions can't trap. Drop the | |
11863 | note in this case. */ | |
11864 | } | |
662795a8 RH |
11865 | break; |
11866 | ||
ca3920ad | 11867 | case REG_NORETURN: |
ab61c93f | 11868 | case REG_SETJMP: |
0e403ec3 AS |
11869 | /* These notes must remain with the call. It should not be |
11870 | possible for both I2 and I3 to be a call. */ | |
4b4bf941 | 11871 | if (CALL_P (i3)) |
4b7c585f | 11872 | place = i3; |
4b7c585f | 11873 | else |
341c100f NS |
11874 | { |
11875 | gcc_assert (i2 && CALL_P (i2)); | |
11876 | place = i2; | |
11877 | } | |
4b7c585f JL |
11878 | break; |
11879 | ||
230d793d | 11880 | case REG_UNUSED: |
07d0cbdd | 11881 | /* Any clobbers for i3 may still exist, and so we must process |
176c9e6b JW |
11882 | REG_UNUSED notes from that insn. |
11883 | ||
11884 | Any clobbers from i2 or i1 can only exist if they were added by | |
11885 | recog_for_combine. In that case, recog_for_combine created the | |
11886 | necessary REG_UNUSED notes. Trying to keep any original | |
11887 | REG_UNUSED notes from these insns can cause incorrect output | |
11888 | if it is for the same register as the original i3 dest. | |
11889 | In that case, we will notice that the register is set in i3, | |
11890 | and then add a REG_UNUSED note for the destination of i3, which | |
07d0cbdd JW |
11891 | is wrong. However, it is possible to have REG_UNUSED notes from |
11892 | i2 or i1 for register which were both used and clobbered, so | |
11893 | we keep notes from i2 or i1 if they will turn into REG_DEAD | |
11894 | notes. */ | |
176c9e6b | 11895 | |
230d793d RS |
11896 | /* If this register is set or clobbered in I3, put the note there |
11897 | unless there is one already. */ | |
07d0cbdd | 11898 | if (reg_set_p (XEXP (note, 0), PATTERN (i3))) |
230d793d | 11899 | { |
07d0cbdd JW |
11900 | if (from_insn != i3) |
11901 | break; | |
11902 | ||
f8cfc6aa | 11903 | if (! (REG_P (XEXP (note, 0)) |
230d793d RS |
11904 | ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) |
11905 | : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
11906 | place = i3; | |
11907 | } | |
11908 | /* Otherwise, if this register is used by I3, then this register | |
11909 | now dies here, so we must put a REG_DEAD note here unless there | |
11910 | is one already. */ | |
11911 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
f8cfc6aa | 11912 | && ! (REG_P (XEXP (note, 0)) |
770ae6cc RK |
11913 | ? find_regno_note (i3, REG_DEAD, |
11914 | REGNO (XEXP (note, 0))) | |
230d793d RS |
11915 | : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) |
11916 | { | |
11917 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
11918 | place = i3; | |
11919 | } | |
11920 | break; | |
11921 | ||
11922 | case REG_EQUAL: | |
11923 | case REG_EQUIV: | |
9ae8ffe7 | 11924 | case REG_NOALIAS: |
230d793d RS |
11925 | /* These notes say something about results of an insn. We can |
11926 | only support them if they used to be on I3 in which case they | |
a687e897 RK |
11927 | remain on I3. Otherwise they are ignored. |
11928 | ||
11929 | If the note refers to an expression that is not a constant, we | |
11930 | must also ignore the note since we cannot tell whether the | |
11931 | equivalence is still true. It might be possible to do | |
11932 | slightly better than this (we only have a problem if I2DEST | |
11933 | or I1DEST is present in the expression), but it doesn't | |
11934 | seem worth the trouble. */ | |
11935 | ||
11936 | if (from_insn == i3 | |
11937 | && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0)))) | |
230d793d RS |
11938 | place = i3; |
11939 | break; | |
11940 | ||
11941 | case REG_INC: | |
11942 | case REG_NO_CONFLICT: | |
230d793d RS |
11943 | /* These notes say something about how a register is used. They must |
11944 | be present on any use of the register in I2 or I3. */ | |
11945 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
11946 | place = i3; | |
11947 | ||
11948 | if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
11949 | { | |
11950 | if (place) | |
11951 | place2 = i2; | |
11952 | else | |
11953 | place = i2; | |
11954 | } | |
11955 | break; | |
11956 | ||
e55b4486 RH |
11957 | case REG_LABEL: |
11958 | /* This can show up in several ways -- either directly in the | |
11959 | pattern, or hidden off in the constant pool with (or without?) | |
11960 | a REG_EQUAL note. */ | |
11961 | /* ??? Ignore the without-reg_equal-note problem for now. */ | |
11962 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)) | |
11963 | || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX)) | |
11964 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF | |
11965 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))) | |
11966 | place = i3; | |
11967 | ||
11968 | if (i2 | |
11969 | && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2)) | |
663522cb | 11970 | || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX)) |
e55b4486 RH |
11971 | && GET_CODE (XEXP (tem, 0)) == LABEL_REF |
11972 | && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))) | |
11973 | { | |
11974 | if (place) | |
11975 | place2 = i2; | |
11976 | else | |
11977 | place = i2; | |
11978 | } | |
2a3b43b6 | 11979 | |
b54567e2 RZ |
11980 | /* Don't attach REG_LABEL note to a JUMP_INSN. Add |
11981 | a JUMP_LABEL instead or decrement LABEL_NUSES. */ | |
11982 | if (place && JUMP_P (place)) | |
2a3b43b6 | 11983 | { |
341c100f NS |
11984 | rtx label = JUMP_LABEL (place); |
11985 | ||
11986 | if (!label) | |
b54567e2 | 11987 | JUMP_LABEL (place) = XEXP (note, 0); |
341c100f NS |
11988 | else |
11989 | { | |
11990 | gcc_assert (label == XEXP (note, 0)); | |
11991 | if (LABEL_P (label)) | |
11992 | LABEL_NUSES (label)--; | |
11993 | } | |
2a3b43b6 JJ |
11994 | place = 0; |
11995 | } | |
b54567e2 | 11996 | if (place2 && JUMP_P (place2)) |
2a3b43b6 | 11997 | { |
341c100f NS |
11998 | rtx label = JUMP_LABEL (place2); |
11999 | ||
12000 | if (!label) | |
b54567e2 | 12001 | JUMP_LABEL (place2) = XEXP (note, 0); |
341c100f NS |
12002 | else |
12003 | { | |
12004 | gcc_assert (label == XEXP (note, 0)); | |
12005 | if (LABEL_P (label)) | |
12006 | LABEL_NUSES (label)--; | |
12007 | } | |
2a3b43b6 JJ |
12008 | place2 = 0; |
12009 | } | |
e55b4486 RH |
12010 | break; |
12011 | ||
c1194d74 | 12012 | case REG_NONNEG: |
6001794d | 12013 | /* This note says something about the value of a register prior |
c1194d74 JW |
12014 | to the execution of an insn. It is too much trouble to see |
12015 | if the note is still correct in all situations. It is better | |
12016 | to simply delete it. */ | |
230d793d RS |
12017 | break; |
12018 | ||
12019 | case REG_RETVAL: | |
12020 | /* If the insn previously containing this note still exists, | |
12021 | put it back where it was. Otherwise move it to the previous | |
12022 | insn. Adjust the corresponding REG_LIBCALL note. */ | |
4b4bf941 | 12023 | if (!NOTE_P (from_insn)) |
230d793d RS |
12024 | place = from_insn; |
12025 | else | |
12026 | { | |
5f4f0e22 | 12027 | tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX); |
230d793d RS |
12028 | place = prev_real_insn (from_insn); |
12029 | if (tem && place) | |
12030 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12031 | /* If we're deleting the last remaining instruction of a |
12032 | libcall sequence, don't add the notes. */ | |
12033 | else if (XEXP (note, 0) == from_insn) | |
12034 | tem = place = 0; | |
e51f9159 KK |
12035 | /* Don't add the dangling REG_RETVAL note. */ |
12036 | else if (! tem) | |
12037 | place = 0; | |
230d793d RS |
12038 | } |
12039 | break; | |
12040 | ||
12041 | case REG_LIBCALL: | |
12042 | /* This is handled similarly to REG_RETVAL. */ | |
4b4bf941 | 12043 | if (!NOTE_P (from_insn)) |
230d793d RS |
12044 | place = from_insn; |
12045 | else | |
12046 | { | |
5f4f0e22 | 12047 | tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX); |
230d793d RS |
12048 | place = next_real_insn (from_insn); |
12049 | if (tem && place) | |
12050 | XEXP (tem, 0) = place; | |
c71e1201 AO |
12051 | /* If we're deleting the last remaining instruction of a |
12052 | libcall sequence, don't add the notes. */ | |
12053 | else if (XEXP (note, 0) == from_insn) | |
12054 | tem = place = 0; | |
e51f9159 KK |
12055 | /* Don't add the dangling REG_LIBCALL note. */ |
12056 | else if (! tem) | |
12057 | place = 0; | |
230d793d RS |
12058 | } |
12059 | break; | |
12060 | ||
12061 | case REG_DEAD: | |
12062 | /* If the register is used as an input in I3, it dies there. | |
da7d8304 | 12063 | Similarly for I2, if it is nonzero and adjacent to I3. |
230d793d RS |
12064 | |
12065 | If the register is not used as an input in either I3 or I2 | |
12066 | and it is not one of the registers we were supposed to eliminate, | |
12067 | there are two possibilities. We might have a non-adjacent I2 | |
12068 | or we might have somehow eliminated an additional register | |
12069 | from a computation. For example, we might have had A & B where | |
12070 | we discover that B will always be zero. In this case we will | |
12071 | eliminate the reference to A. | |
12072 | ||
12073 | In both cases, we must search to see if we can find a previous | |
12074 | use of A and put the death note there. */ | |
12075 | ||
6e2d1486 | 12076 | if (from_insn |
4b4bf941 | 12077 | && CALL_P (from_insn) |
663522cb | 12078 | && find_reg_fusage (from_insn, USE, XEXP (note, 0))) |
6e2d1486 RK |
12079 | place = from_insn; |
12080 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
230d793d RS |
12081 | place = i3; |
12082 | else if (i2 != 0 && next_nonnote_insn (i2) == i3 | |
12083 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
12084 | place = i2; | |
12085 | ||
230d793d | 12086 | if (place == 0) |
38d8473f | 12087 | { |
f6366fc7 | 12088 | basic_block bb = this_basic_block; |
d3a923ee RH |
12089 | |
12090 | for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem)) | |
38d8473f | 12091 | { |
2c3c49de | 12092 | if (! INSN_P (tem)) |
d3a923ee | 12093 | { |
a813c111 | 12094 | if (tem == BB_HEAD (bb)) |
d3a923ee RH |
12095 | break; |
12096 | continue; | |
12097 | } | |
12098 | ||
38d8473f RK |
12099 | /* If the register is being set at TEM, see if that is all |
12100 | TEM is doing. If so, delete TEM. Otherwise, make this | |
de7c79cc EC |
12101 | into a REG_UNUSED note instead. Don't delete sets to |
12102 | global register vars. */ | |
2cd54c2a ZW |
12103 | if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER |
12104 | || !global_regs[REGNO (XEXP (note, 0))]) | |
12105 | && reg_set_p (XEXP (note, 0), PATTERN (tem))) | |
38d8473f RK |
12106 | { |
12107 | rtx set = single_set (tem); | |
e5e809f4 | 12108 | rtx inner_dest = 0; |
e51712db | 12109 | #ifdef HAVE_cc0 |
f5c97640 | 12110 | rtx cc0_setter = NULL_RTX; |
e51712db | 12111 | #endif |
e5e809f4 JL |
12112 | |
12113 | if (set != 0) | |
12114 | for (inner_dest = SET_DEST (set); | |
663522cb KH |
12115 | (GET_CODE (inner_dest) == STRICT_LOW_PART |
12116 | || GET_CODE (inner_dest) == SUBREG | |
12117 | || GET_CODE (inner_dest) == ZERO_EXTRACT); | |
e5e809f4 JL |
12118 | inner_dest = XEXP (inner_dest, 0)) |
12119 | ; | |
38d8473f RK |
12120 | |
12121 | /* Verify that it was the set, and not a clobber that | |
663522cb | 12122 | modified the register. |
f5c97640 RH |
12123 | |
12124 | CC0 targets must be careful to maintain setter/user | |
12125 | pairs. If we cannot delete the setter due to side | |
12126 | effects, mark the user with an UNUSED note instead | |
12127 | of deleting it. */ | |
38d8473f RK |
12128 | |
12129 | if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
f5c97640 RH |
12130 | && rtx_equal_p (XEXP (note, 0), inner_dest) |
12131 | #ifdef HAVE_cc0 | |
12132 | && (! reg_mentioned_p (cc0_rtx, SET_SRC (set)) | |
12133 | || ((cc0_setter = prev_cc0_setter (tem)) != NULL | |
12134 | && sets_cc0_p (PATTERN (cc0_setter)) > 0)) | |
12135 | #endif | |
12136 | ) | |
38d8473f RK |
12137 | { |
12138 | /* Move the notes and links of TEM elsewhere. | |
663522cb | 12139 | This might delete other dead insns recursively. |
38d8473f RK |
12140 | First set the pattern to something that won't use |
12141 | any register. */ | |
f9af39d0 | 12142 | rtx old_notes = REG_NOTES (tem); |
38d8473f RK |
12143 | |
12144 | PATTERN (tem) = pc_rtx; | |
f9af39d0 | 12145 | REG_NOTES (tem) = NULL; |
38d8473f | 12146 | |
f9af39d0 | 12147 | distribute_notes (old_notes, tem, tem, NULL_RTX); |
38d8473f RK |
12148 | distribute_links (LOG_LINKS (tem)); |
12149 | ||
6773e15f | 12150 | SET_INSN_DELETED (tem); |
f5c97640 RH |
12151 | |
12152 | #ifdef HAVE_cc0 | |
12153 | /* Delete the setter too. */ | |
12154 | if (cc0_setter) | |
12155 | { | |
12156 | PATTERN (cc0_setter) = pc_rtx; | |
f9af39d0 RE |
12157 | old_notes = REG_NOTES (cc0_setter); |
12158 | REG_NOTES (cc0_setter) = NULL; | |
f5c97640 | 12159 | |
f9af39d0 RE |
12160 | distribute_notes (old_notes, cc0_setter, |
12161 | cc0_setter, NULL_RTX); | |
f5c97640 RH |
12162 | distribute_links (LOG_LINKS (cc0_setter)); |
12163 | ||
6773e15f | 12164 | SET_INSN_DELETED (cc0_setter); |
f5c97640 RH |
12165 | } |
12166 | #endif | |
38d8473f RK |
12167 | } |
12168 | else | |
12169 | { | |
12170 | PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
663522cb | 12171 | |
38d8473f | 12172 | /* If there isn't already a REG_UNUSED note, put one |
b30e1617 DJ |
12173 | here. Do not place a REG_DEAD note, even if |
12174 | the register is also used here; that would not | |
12175 | match the algorithm used in lifetime analysis | |
12176 | and can cause the consistency check in the | |
12177 | scheduler to fail. */ | |
38d8473f RK |
12178 | if (! find_regno_note (tem, REG_UNUSED, |
12179 | REGNO (XEXP (note, 0)))) | |
12180 | place = tem; | |
12181 | break; | |
d3a923ee RH |
12182 | } |
12183 | } | |
12184 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)) | |
4b4bf941 | 12185 | || (CALL_P (tem) |
d3a923ee RH |
12186 | && find_reg_fusage (tem, USE, XEXP (note, 0)))) |
12187 | { | |
12188 | place = tem; | |
12189 | ||
12190 | /* If we are doing a 3->2 combination, and we have a | |
12191 | register which formerly died in i3 and was not used | |
12192 | by i2, which now no longer dies in i3 and is used in | |
12193 | i2 but does not die in i2, and place is between i2 | |
12194 | and i3, then we may need to move a link from place to | |
12195 | i2. */ | |
12196 | if (i2 && INSN_UID (place) <= max_uid_cuid | |
12197 | && INSN_CUID (place) > INSN_CUID (i2) | |
663522cb KH |
12198 | && from_insn |
12199 | && INSN_CUID (from_insn) > INSN_CUID (i2) | |
d3a923ee RH |
12200 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) |
12201 | { | |
12202 | rtx links = LOG_LINKS (place); | |
12203 | LOG_LINKS (place) = 0; | |
12204 | distribute_links (links); | |
12205 | } | |
12206 | break; | |
12207 | } | |
12208 | ||
a813c111 | 12209 | if (tem == BB_HEAD (bb)) |
230d793d | 12210 | break; |
38d8473f | 12211 | } |
663522cb | 12212 | |
d3a923ee RH |
12213 | /* We haven't found an insn for the death note and it |
12214 | is still a REG_DEAD note, but we have hit the beginning | |
12215 | of the block. If the existing life info says the reg | |
715e7fbc | 12216 | was dead, there's nothing left to do. Otherwise, we'll |
e7139885 RH |
12217 | need to do a global life update after combine. */ |
12218 | if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 | |
12219 | && REGNO_REG_SET_P (bb->global_live_at_start, | |
12220 | REGNO (XEXP (note, 0)))) | |
4977bab6 | 12221 | SET_BIT (refresh_blocks, this_basic_block->index); |
38d8473f | 12222 | } |
230d793d RS |
12223 | |
12224 | /* If the register is set or already dead at PLACE, we needn't do | |
e5e809f4 | 12225 | anything with this note if it is still a REG_DEAD note. |
e8679703 | 12226 | We check here if it is set at all, not if is it totally replaced, |
e5e809f4 JL |
12227 | which is what `dead_or_set_p' checks, so also check for it being |
12228 | set partially. */ | |
12229 | ||
230d793d RS |
12230 | if (place && REG_NOTE_KIND (note) == REG_DEAD) |
12231 | { | |
770ae6cc | 12232 | unsigned int regno = REGNO (XEXP (note, 0)); |
230d793d | 12233 | |
e7139885 RH |
12234 | /* Similarly, if the instruction on which we want to place |
12235 | the note is a noop, we'll need do a global live update | |
12236 | after we remove them in delete_noop_moves. */ | |
12237 | if (noop_move_p (place)) | |
4977bab6 | 12238 | SET_BIT (refresh_blocks, this_basic_block->index); |
e7139885 | 12239 | |
230d793d RS |
12240 | if (dead_or_set_p (place, XEXP (note, 0)) |
12241 | || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
12242 | { | |
12243 | /* Unless the register previously died in PLACE, clear | |
5eaad481 | 12244 | last_death. [I no longer understand why this is |
230d793d | 12245 | being done.] */ |
5eaad481 PB |
12246 | if (reg_stat[regno].last_death != place) |
12247 | reg_stat[regno].last_death = 0; | |
230d793d RS |
12248 | place = 0; |
12249 | } | |
12250 | else | |
5eaad481 | 12251 | reg_stat[regno].last_death = place; |
230d793d RS |
12252 | |
12253 | /* If this is a death note for a hard reg that is occupying | |
12254 | multiple registers, ensure that we are still using all | |
12255 | parts of the object. If we find a piece of the object | |
03afaf36 R |
12256 | that is unused, we must arrange for an appropriate REG_DEAD |
12257 | note to be added for it. However, we can't just emit a USE | |
12258 | and tag the note to it, since the register might actually | |
12259 | be dead; so we recourse, and the recursive call then finds | |
12260 | the previous insn that used this register. */ | |
230d793d RS |
12261 | |
12262 | if (place && regno < FIRST_PSEUDO_REGISTER | |
66fd46b6 | 12263 | && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1) |
230d793d | 12264 | { |
770ae6cc | 12265 | unsigned int endregno |
66fd46b6 JH |
12266 | = regno + hard_regno_nregs[regno] |
12267 | [GET_MODE (XEXP (note, 0))]; | |
230d793d | 12268 | int all_used = 1; |
770ae6cc | 12269 | unsigned int i; |
230d793d RS |
12270 | |
12271 | for (i = regno; i < endregno; i++) | |
03afaf36 R |
12272 | if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0) |
12273 | && ! find_regno_fusage (place, USE, i)) | |
12274 | || dead_or_set_regno_p (place, i)) | |
12275 | all_used = 0; | |
a394b17b | 12276 | |
230d793d RS |
12277 | if (! all_used) |
12278 | { | |
12279 | /* Put only REG_DEAD notes for pieces that are | |
03afaf36 | 12280 | not already dead or set. */ |
230d793d | 12281 | |
03afaf36 | 12282 | for (i = regno; i < endregno; |
66fd46b6 | 12283 | i += hard_regno_nregs[i][reg_raw_mode[i]]) |
230d793d | 12284 | { |
e50126e8 | 12285 | rtx piece = regno_reg_rtx[i]; |
f6366fc7 | 12286 | basic_block bb = this_basic_block; |
230d793d | 12287 | |
03afaf36 | 12288 | if (! dead_or_set_p (place, piece) |
230d793d RS |
12289 | && ! reg_bitfield_target_p (piece, |
12290 | PATTERN (place))) | |
03afaf36 R |
12291 | { |
12292 | rtx new_note | |
12293 | = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX); | |
12294 | ||
12295 | distribute_notes (new_note, place, place, | |
72531479 | 12296 | NULL_RTX); |
03afaf36 | 12297 | } |
c762163e R |
12298 | else if (! refers_to_regno_p (i, i + 1, |
12299 | PATTERN (place), 0) | |
12300 | && ! find_regno_fusage (place, USE, i)) | |
12301 | for (tem = PREV_INSN (place); ; | |
12302 | tem = PREV_INSN (tem)) | |
12303 | { | |
12304 | if (! INSN_P (tem)) | |
12305 | { | |
a813c111 | 12306 | if (tem == BB_HEAD (bb)) |
c762163e R |
12307 | { |
12308 | SET_BIT (refresh_blocks, | |
f6366fc7 | 12309 | this_basic_block->index); |
c762163e R |
12310 | break; |
12311 | } | |
12312 | continue; | |
12313 | } | |
12314 | if (dead_or_set_p (tem, piece) | |
12315 | || reg_bitfield_target_p (piece, | |
12316 | PATTERN (tem))) | |
12317 | { | |
12318 | REG_NOTES (tem) | |
71fd5a51 | 12319 | = gen_rtx_EXPR_LIST (REG_UNUSED, piece, |
c762163e R |
12320 | REG_NOTES (tem)); |
12321 | break; | |
12322 | } | |
12323 | } | |
12324 | ||
230d793d RS |
12325 | } |
12326 | ||
12327 | place = 0; | |
12328 | } | |
12329 | } | |
12330 | } | |
12331 | break; | |
12332 | ||
12333 | default: | |
12334 | /* Any other notes should not be present at this point in the | |
12335 | compilation. */ | |
341c100f | 12336 | gcc_unreachable (); |
230d793d RS |
12337 | } |
12338 | ||
12339 | if (place) | |
12340 | { | |
12341 | XEXP (note, 1) = REG_NOTES (place); | |
12342 | REG_NOTES (place) = note; | |
12343 | } | |
1a26b032 RK |
12344 | else if ((REG_NOTE_KIND (note) == REG_DEAD |
12345 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
f8cfc6aa | 12346 | && REG_P (XEXP (note, 0))) |
b1f21e0a | 12347 | REG_N_DEATHS (REGNO (XEXP (note, 0)))--; |
230d793d RS |
12348 | |
12349 | if (place2) | |
1a26b032 RK |
12350 | { |
12351 | if ((REG_NOTE_KIND (note) == REG_DEAD | |
12352 | || REG_NOTE_KIND (note) == REG_UNUSED) | |
f8cfc6aa | 12353 | && REG_P (XEXP (note, 0))) |
b1f21e0a | 12354 | REG_N_DEATHS (REGNO (XEXP (note, 0)))++; |
1a26b032 | 12355 | |
38a448ca RH |
12356 | REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note), |
12357 | REG_NOTE_KIND (note), | |
12358 | XEXP (note, 0), | |
12359 | REG_NOTES (place2)); | |
1a26b032 | 12360 | } |
230d793d RS |
12361 | } |
12362 | } | |
12363 | \f | |
12364 | /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
8c03ca00 EB |
12365 | I3, I2, and I1 to new locations. This is also called to add a link |
12366 | pointing at I3 when I3's destination is changed. */ | |
230d793d RS |
12367 | |
12368 | static void | |
79a490a9 | 12369 | distribute_links (rtx links) |
230d793d RS |
12370 | { |
12371 | rtx link, next_link; | |
12372 | ||
12373 | for (link = links; link; link = next_link) | |
12374 | { | |
12375 | rtx place = 0; | |
12376 | rtx insn; | |
12377 | rtx set, reg; | |
12378 | ||
12379 | next_link = XEXP (link, 1); | |
12380 | ||
12381 | /* If the insn that this link points to is a NOTE or isn't a single | |
12382 | set, ignore it. In the latter case, it isn't clear what we | |
663522cb | 12383 | can do other than ignore the link, since we can't tell which |
230d793d RS |
12384 | register it was for. Such links wouldn't be used by combine |
12385 | anyway. | |
12386 | ||
12387 | It is not possible for the destination of the target of the link to | |
12388 | have been changed by combine. The only potential of this is if we | |
12389 | replace I3, I2, and I1 by I3 and I2. But in that case the | |
12390 | destination of I2 also remains unchanged. */ | |
12391 | ||
4b4bf941 | 12392 | if (NOTE_P (XEXP (link, 0)) |
230d793d RS |
12393 | || (set = single_set (XEXP (link, 0))) == 0) |
12394 | continue; | |
12395 | ||
12396 | reg = SET_DEST (set); | |
12397 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
230d793d RS |
12398 | || GET_CODE (reg) == STRICT_LOW_PART) |
12399 | reg = XEXP (reg, 0); | |
12400 | ||
12401 | /* A LOG_LINK is defined as being placed on the first insn that uses | |
12402 | a register and points to the insn that sets the register. Start | |
12403 | searching at the next insn after the target of the link and stop | |
12404 | when we reach a set of the register or the end of the basic block. | |
12405 | ||
12406 | Note that this correctly handles the link that used to point from | |
5089e22e | 12407 | I3 to I2. Also note that not much searching is typically done here |
230d793d RS |
12408 | since most links don't point very far away. */ |
12409 | ||
12410 | for (insn = NEXT_INSN (XEXP (link, 0)); | |
f6366fc7 | 12411 | (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR |
a813c111 | 12412 | || BB_HEAD (this_basic_block->next_bb) != insn)); |
230d793d | 12413 | insn = NEXT_INSN (insn)) |
2c3c49de | 12414 | if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn))) |
230d793d RS |
12415 | { |
12416 | if (reg_referenced_p (reg, PATTERN (insn))) | |
12417 | place = insn; | |
12418 | break; | |
12419 | } | |
4b4bf941 | 12420 | else if (CALL_P (insn) |
663522cb | 12421 | && find_reg_fusage (insn, USE, reg)) |
6e2d1486 RK |
12422 | { |
12423 | place = insn; | |
12424 | break; | |
12425 | } | |
892c9f1f RK |
12426 | else if (INSN_P (insn) && reg_set_p (reg, insn)) |
12427 | break; | |
230d793d RS |
12428 | |
12429 | /* If we found a place to put the link, place it there unless there | |
12430 | is already a link to the same insn as LINK at that point. */ | |
12431 | ||
12432 | if (place) | |
12433 | { | |
12434 | rtx link2; | |
12435 | ||
12436 | for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) | |
12437 | if (XEXP (link2, 0) == XEXP (link, 0)) | |
12438 | break; | |
12439 | ||
12440 | if (link2 == 0) | |
12441 | { | |
12442 | XEXP (link, 1) = LOG_LINKS (place); | |
12443 | LOG_LINKS (place) = link; | |
abe6e52f RK |
12444 | |
12445 | /* Set added_links_insn to the earliest insn we added a | |
12446 | link to. */ | |
663522cb | 12447 | if (added_links_insn == 0 |
abe6e52f RK |
12448 | || INSN_CUID (added_links_insn) > INSN_CUID (place)) |
12449 | added_links_insn = place; | |
230d793d RS |
12450 | } |
12451 | } | |
12452 | } | |
12453 | } | |
12454 | \f | |
67962db5 RS |
12455 | /* Subroutine of unmentioned_reg_p and callback from for_each_rtx. |
12456 | Check whether the expression pointer to by LOC is a register or | |
12457 | memory, and if so return 1 if it isn't mentioned in the rtx EXPR. | |
12458 | Otherwise return zero. */ | |
12459 | ||
12460 | static int | |
12461 | unmentioned_reg_p_1 (rtx *loc, void *expr) | |
12462 | { | |
12463 | rtx x = *loc; | |
12464 | ||
12465 | if (x != NULL_RTX | |
3c0cb5de | 12466 | && (REG_P (x) || MEM_P (x)) |
67962db5 RS |
12467 | && ! reg_mentioned_p (x, (rtx) expr)) |
12468 | return 1; | |
12469 | return 0; | |
12470 | } | |
12471 | ||
12472 | /* Check for any register or memory mentioned in EQUIV that is not | |
12473 | mentioned in EXPR. This is used to restrict EQUIV to "specializations" | |
12474 | of EXPR where some registers may have been replaced by constants. */ | |
12475 | ||
12476 | static bool | |
12477 | unmentioned_reg_p (rtx equiv, rtx expr) | |
12478 | { | |
12479 | return for_each_rtx (&equiv, unmentioned_reg_p_1, expr); | |
12480 | } | |
12481 | \f | |
1427d6d2 RK |
12482 | /* Compute INSN_CUID for INSN, which is an insn made by combine. */ |
12483 | ||
12484 | static int | |
79a490a9 | 12485 | insn_cuid (rtx insn) |
1427d6d2 RK |
12486 | { |
12487 | while (insn != 0 && INSN_UID (insn) > max_uid_cuid | |
4b4bf941 | 12488 | && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE) |
1427d6d2 RK |
12489 | insn = NEXT_INSN (insn); |
12490 | ||
341c100f | 12491 | gcc_assert (INSN_UID (insn) <= max_uid_cuid); |
1427d6d2 RK |
12492 | |
12493 | return INSN_CUID (insn); | |
12494 | } | |
12495 | \f | |
230d793d | 12496 | void |
79a490a9 | 12497 | dump_combine_stats (FILE *file) |
230d793d | 12498 | { |
ab87f8c8 | 12499 | fnotice |
230d793d RS |
12500 | (file, |
12501 | ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
12502 | combine_attempts, combine_merges, combine_extras, combine_successes); | |
12503 | } | |
12504 | ||
12505 | void | |
79a490a9 | 12506 | dump_combine_total_stats (FILE *file) |
230d793d | 12507 | { |
ab87f8c8 | 12508 | fnotice |
230d793d RS |
12509 | (file, |
12510 | "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
12511 | total_attempts, total_merges, total_extras, total_successes); | |
12512 | } |