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230d793d 1/* Optimize by combining instructions for GNU compiler.
1bf27b5b 2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
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3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
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18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
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20
21
22/* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
230d793d 77#include "config.h"
670ee920 78#include "system.h"
789f983a 79#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
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80#include "flags.h"
81#include "regs.h"
55310dad 82#include "hard-reg-set.h"
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83#include "basic-block.h"
84#include "insn-config.h"
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85/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
86#include "expr.h"
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87#include "insn-flags.h"
88#include "insn-codes.h"
89#include "insn-attr.h"
90#include "recog.h"
91#include "real.h"
2e107e9e 92#include "toplev.h"
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93
94/* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96#define gen_lowpart dont_use_gen_lowpart_you_dummy
97
98/* Number of attempts to combine instructions in this function. */
99
100static int combine_attempts;
101
102/* Number of attempts that got as far as substitution in this function. */
103
104static int combine_merges;
105
106/* Number of instructions combined with added SETs in this function. */
107
108static int combine_extras;
109
110/* Number of instructions combined in this function. */
111
112static int combine_successes;
113
114/* Totals over entire compilation. */
115
116static int total_attempts, total_merges, total_extras, total_successes;
9210df58 117
ddd5a7c1 118/* Define a default value for REVERSIBLE_CC_MODE.
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119 We can never assume that a condition code mode is safe to reverse unless
120 the md tells us so. */
121#ifndef REVERSIBLE_CC_MODE
122#define REVERSIBLE_CC_MODE(MODE) 0
123#endif
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124\f
125/* Vector mapping INSN_UIDs to cuids.
5089e22e 126 The cuids are like uids but increase monotonically always.
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127 Combine always uses cuids so that it can compare them.
128 But actually renumbering the uids, which we used to do,
129 proves to be a bad idea because it makes it hard to compare
130 the dumps produced by earlier passes with those from later passes. */
131
132static int *uid_cuid;
4255220d 133static int max_uid_cuid;
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134
135/* Get the cuid of an insn. */
136
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137#define INSN_CUID(INSN) \
138(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
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139
140/* Maximum register number, which is the size of the tables below. */
141
142static int combine_max_regno;
143
144/* Record last point of death of (hard or pseudo) register n. */
145
146static rtx *reg_last_death;
147
148/* Record last point of modification of (hard or pseudo) register n. */
149
150static rtx *reg_last_set;
151
152/* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
154
155static int mem_last_set;
156
157/* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
159
160static int last_call_cuid;
161
162/* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
167
168static rtx subst_insn;
169
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170/* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
172
173static rtx subst_prev_insn;
174
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175/* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
181
182static int subst_low_cuid;
183
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184/* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
186
187static HARD_REG_SET newpat_used_regs;
188
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189/* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
191 that location. */
192
193static rtx added_links_insn;
194
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195/* Basic block number of the block in which we are performing combines. */
196static int this_basic_block;
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197\f
198/* The next group of arrays allows the recording of the last value assigned
199 to (hard or pseudo) register n. We use this information to see if a
5089e22e 200 operation being processed is redundant given a prior operation performed
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201 on the register. For example, an `and' with a constant is redundant if
202 all the zero bits are already known to be turned off.
203
204 We use an approach similar to that used by cse, but change it in the
205 following ways:
206
207 (1) We do not want to reinitialize at each label.
208 (2) It is useful, but not critical, to know the actual value assigned
209 to a register. Often just its form is helpful.
210
211 Therefore, we maintain the following arrays:
212
213 reg_last_set_value the last value assigned
214 reg_last_set_label records the value of label_tick when the
215 register was assigned
216 reg_last_set_table_tick records the value of label_tick when a
217 value using the register is assigned
218 reg_last_set_invalid set to non-zero when it is not valid
219 to use the value of this register in some
220 register's value
221
222 To understand the usage of these tables, it is important to understand
223 the distinction between the value in reg_last_set_value being valid
224 and the register being validly contained in some other expression in the
225 table.
226
227 Entry I in reg_last_set_value is valid if it is non-zero, and either
228 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
229
230 Register I may validly appear in any expression returned for the value
231 of another register if reg_n_sets[i] is 1. It may also appear in the
232 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
233 reg_last_set_invalid[j] is zero.
234
235 If an expression is found in the table containing a register which may
236 not validly appear in an expression, the register is replaced by
237 something that won't match, (clobber (const_int 0)).
238
239 reg_last_set_invalid[i] is set non-zero when register I is being assigned
240 to and reg_last_set_table_tick[i] == label_tick. */
241
0f41302f 242/* Record last value assigned to (hard or pseudo) register n. */
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243
244static rtx *reg_last_set_value;
245
246/* Record the value of label_tick when the value for register n is placed in
247 reg_last_set_value[n]. */
248
568356af 249static int *reg_last_set_label;
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250
251/* Record the value of label_tick when an expression involving register n
0f41302f 252 is placed in reg_last_set_value. */
230d793d 253
568356af 254static int *reg_last_set_table_tick;
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255
256/* Set non-zero if references to register n in expressions should not be
257 used. */
258
259static char *reg_last_set_invalid;
260
0f41302f 261/* Incremented for each label. */
230d793d 262
568356af 263static int label_tick;
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264
265/* Some registers that are set more than once and used in more than one
266 basic block are nevertheless always set in similar ways. For example,
267 a QImode register may be loaded from memory in two places on a machine
268 where byte loads zero extend.
269
951553af 270 We record in the following array what we know about the nonzero
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271 bits of a register, specifically which bits are known to be zero.
272
273 If an entry is zero, it means that we don't know anything special. */
274
55310dad 275static unsigned HOST_WIDE_INT *reg_nonzero_bits;
230d793d 276
951553af 277/* Mode used to compute significance in reg_nonzero_bits. It is the largest
5f4f0e22 278 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
230d793d 279
951553af 280static enum machine_mode nonzero_bits_mode;
230d793d 281
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282/* Nonzero if we know that a register has some leading bits that are always
283 equal to the sign bit. */
284
285static char *reg_sign_bit_copies;
286
951553af 287/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
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288 It is zero while computing them and after combine has completed. This
289 former test prevents propagating values based on previously set values,
290 which can be incorrect if a variable is modified in a loop. */
230d793d 291
951553af 292static int nonzero_sign_valid;
55310dad
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293
294/* These arrays are maintained in parallel with reg_last_set_value
295 and are used to store the mode in which the register was last set,
296 the bits that were known to be zero when it was last set, and the
297 number of sign bits copies it was known to have when it was last set. */
298
299static enum machine_mode *reg_last_set_mode;
300static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
301static char *reg_last_set_sign_bit_copies;
230d793d
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302\f
303/* Record one modification to rtl structure
304 to be undone by storing old_contents into *where.
305 is_int is 1 if the contents are an int. */
306
307struct undo
308{
241cea85 309 struct undo *next;
230d793d 310 int is_int;
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311 union {rtx r; int i;} old_contents;
312 union {rtx *r; int *i;} where;
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313};
314
315/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
316 num_undo says how many are currently recorded.
317
318 storage is nonzero if we must undo the allocation of new storage.
319 The value of storage is what to pass to obfree.
320
321 other_insn is nonzero if we have modified some other insn in the process
241cea85 322 of working on subst_insn. It must be verified too.
230d793d 323
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324 previous_undos is the value of undobuf.undos when we started processing
325 this substitution. This will prevent gen_rtx_combine from re-used a piece
326 from the previous expression. Doing so can produce circular rtl
327 structures. */
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328
329struct undobuf
330{
230d793d 331 char *storage;
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332 struct undo *undos;
333 struct undo *frees;
334 struct undo *previous_undos;
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335 rtx other_insn;
336};
337
338static struct undobuf undobuf;
339
cc876596 340/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
230d793d 341 insn. The substitution can be undone by undo_all. If INTO is already
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342 set to NEWVAL, do not record this change. Because computing NEWVAL might
343 also call SUBST, we have to compute it before we put anything into
344 the undo table. */
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345
346#define SUBST(INTO, NEWVAL) \
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347 do { rtx _new = (NEWVAL); \
348 struct undo *_buf; \
349 \
350 if (undobuf.frees) \
351 _buf = undobuf.frees, undobuf.frees = _buf->next; \
352 else \
353 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
354 \
355 _buf->is_int = 0; \
356 _buf->where.r = &INTO; \
357 _buf->old_contents.r = INTO; \
358 INTO = _new; \
359 if (_buf->old_contents.r == INTO) \
360 _buf->next = undobuf.frees, undobuf.frees = _buf; \
361 else \
362 _buf->next = undobuf.undos, undobuf.undos = _buf; \
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363 } while (0)
364
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365/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
366 for the value of a HOST_WIDE_INT value (including CONST_INT) is
367 not safe. */
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368
369#define SUBST_INT(INTO, NEWVAL) \
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370 do { struct undo *_buf; \
371 \
372 if (undobuf.frees) \
373 _buf = undobuf.frees, undobuf.frees = _buf->next; \
374 else \
375 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
376 \
377 _buf->is_int = 1; \
378 _buf->where.i = (int *) &INTO; \
379 _buf->old_contents.i = INTO; \
380 INTO = NEWVAL; \
381 if (_buf->old_contents.i == INTO) \
382 _buf->next = undobuf.frees, undobuf.frees = _buf; \
383 else \
384 _buf->next = undobuf.undos, undobuf.undos = _buf; \
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385 } while (0)
386
387/* Number of times the pseudo being substituted for
388 was found and replaced. */
389
390static int n_occurrences;
391
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392static void init_reg_last_arrays PROTO((void));
393static void setup_incoming_promotions PROTO((void));
fe2db4fb
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394static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
395static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
e009aaf3 396static int sets_function_arg_p PROTO((rtx));
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397static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
398static rtx try_combine PROTO((rtx, rtx, rtx));
399static void undo_all PROTO((void));
400static rtx *find_split_point PROTO((rtx *, rtx));
401static rtx subst PROTO((rtx, rtx, rtx, int, int));
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402static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
403static rtx simplify_if_then_else PROTO((rtx));
404static rtx simplify_set PROTO((rtx));
405static rtx simplify_logical PROTO((rtx, int));
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406static rtx expand_compound_operation PROTO((rtx));
407static rtx expand_field_assignment PROTO((rtx));
408static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
409 int, int, int));
71923da7 410static rtx extract_left_shift PROTO((rtx, int));
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411static rtx make_compound_operation PROTO((rtx, enum rtx_code));
412static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
6139ff20 413static rtx force_to_mode PROTO((rtx, enum machine_mode,
e3d616e3 414 unsigned HOST_WIDE_INT, rtx, int));
abe6e52f 415static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
fe2db4fb 416static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
e11fa86f 417static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
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418static rtx make_field_assignment PROTO((rtx));
419static rtx apply_distributive_law PROTO((rtx));
420static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
421 unsigned HOST_WIDE_INT));
422static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
423static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
424static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
425 enum rtx_code, HOST_WIDE_INT,
426 enum machine_mode, int *));
427static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
428 rtx, int));
8e2f6e35 429static int recog_for_combine PROTO((rtx *, rtx, rtx *));
fe2db4fb 430static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
d18225c4 431static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
4f90e4a0 432 ...));
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433static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
434 rtx, rtx));
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435static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
436 enum machine_mode, rtx));
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437static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
438static int reversible_comparison_p PROTO((rtx));
439static void update_table_tick PROTO((rtx));
440static void record_value_for_reg PROTO((rtx, rtx, rtx));
441static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
442static void record_dead_and_set_regs PROTO((rtx));
9a893315 443static int get_last_value_validate PROTO((rtx *, rtx, int, int));
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444static rtx get_last_value PROTO((rtx));
445static int use_crosses_set_p PROTO((rtx, int));
446static void reg_dead_at_p_1 PROTO((rtx, rtx));
447static int reg_dead_at_p PROTO((rtx, rtx));
6eb12cef 448static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
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449static int reg_bitfield_target_p PROTO((rtx, rtx));
450static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
451static void distribute_links PROTO((rtx));
6e25d159 452static void mark_used_regs_combine PROTO((rtx));
1427d6d2 453static int insn_cuid PROTO((rtx));
230d793d
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454\f
455/* Main entry point for combiner. F is the first insn of the function.
456 NREGS is the first unused pseudo-reg number. */
457
458void
459combine_instructions (f, nregs)
460 rtx f;
461 int nregs;
462{
b729186a
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463 register rtx insn, next;
464#ifdef HAVE_cc0
465 register rtx prev;
466#endif
230d793d
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467 register int i;
468 register rtx links, nextlinks;
469
470 combine_attempts = 0;
471 combine_merges = 0;
472 combine_extras = 0;
473 combine_successes = 0;
241cea85 474 undobuf.undos = undobuf.previous_undos = 0;
230d793d
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475
476 combine_max_regno = nregs;
477
ef026f91
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478 reg_nonzero_bits
479 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
480 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
481
4c9a05bc 482 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS
483 bzero (reg_sign_bit_copies, nregs * sizeof (char));
484
230d793d
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485 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
486 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
487 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
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488 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
489 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
5f4f0e22 490 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
55310dad
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491 reg_last_set_mode
492 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
493 reg_last_set_nonzero_bits
494 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
495 reg_last_set_sign_bit_copies
496 = (char *) alloca (nregs * sizeof (char));
497
ef026f91 498 init_reg_last_arrays ();
230d793d
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499
500 init_recog_no_volatile ();
501
502 /* Compute maximum uid value so uid_cuid can be allocated. */
503
504 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
505 if (INSN_UID (insn) > i)
506 i = INSN_UID (insn);
507
508 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
4255220d 509 max_uid_cuid = i;
230d793d 510
951553af 511 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
230d793d 512
951553af 513 /* Don't use reg_nonzero_bits when computing it. This can cause problems
230d793d
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514 when, for example, we have j <<= 1 in a loop. */
515
951553af 516 nonzero_sign_valid = 0;
230d793d
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517
518 /* Compute the mapping from uids to cuids.
519 Cuids are numbers assigned to insns, like uids,
520 except that cuids increase monotonically through the code.
521
522 Scan all SETs and see if we can deduce anything about what
951553af 523 bits are known to be zero for some registers and how many copies
d79f08e0
RK
524 of the sign bit are known to exist for those registers.
525
526 Also set any known values so that we can use it while searching
527 for what bits are known to be set. */
528
529 label_tick = 1;
230d793d 530
bcd49eb7
JW
531 /* We need to initialize it here, because record_dead_and_set_regs may call
532 get_last_value. */
533 subst_prev_insn = NULL_RTX;
534
7988fd36
RK
535 setup_incoming_promotions ();
536
230d793d
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537 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
538 {
4255220d 539 uid_cuid[INSN_UID (insn)] = ++i;
d79f08e0
RK
540 subst_low_cuid = i;
541 subst_insn = insn;
542
230d793d 543 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
d79f08e0
RK
544 {
545 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
546 record_dead_and_set_regs (insn);
2dab894a
RK
547
548#ifdef AUTO_INC_DEC
549 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
550 if (REG_NOTE_KIND (links) == REG_INC)
551 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
552#endif
d79f08e0
RK
553 }
554
555 if (GET_CODE (insn) == CODE_LABEL)
556 label_tick++;
230d793d
RS
557 }
558
951553af 559 nonzero_sign_valid = 1;
230d793d
RS
560
561 /* Now scan all the insns in forward order. */
562
0d4d42c3 563 this_basic_block = -1;
230d793d
RS
564 label_tick = 1;
565 last_call_cuid = 0;
566 mem_last_set = 0;
ef026f91 567 init_reg_last_arrays ();
7988fd36
RK
568 setup_incoming_promotions ();
569
230d793d
RS
570 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
571 {
572 next = 0;
573
0d4d42c3 574 /* If INSN starts a new basic block, update our basic block number. */
f085c9cd 575 if (this_basic_block + 1 < n_basic_blocks
3b413743 576 && BLOCK_HEAD (this_basic_block + 1) == insn)
0d4d42c3
RK
577 this_basic_block++;
578
230d793d
RS
579 if (GET_CODE (insn) == CODE_LABEL)
580 label_tick++;
581
0d4d42c3 582 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
230d793d
RS
583 {
584 /* Try this insn with each insn it links back to. */
585
586 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
5f4f0e22 587 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
230d793d
RS
588 goto retry;
589
590 /* Try each sequence of three linked insns ending with this one. */
591
592 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
593 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
594 nextlinks = XEXP (nextlinks, 1))
595 if ((next = try_combine (insn, XEXP (links, 0),
596 XEXP (nextlinks, 0))) != 0)
597 goto retry;
598
599#ifdef HAVE_cc0
600 /* Try to combine a jump insn that uses CC0
601 with a preceding insn that sets CC0, and maybe with its
602 logical predecessor as well.
603 This is how we make decrement-and-branch insns.
604 We need this special code because data flow connections
605 via CC0 do not get entered in LOG_LINKS. */
606
607 if (GET_CODE (insn) == JUMP_INSN
608 && (prev = prev_nonnote_insn (insn)) != 0
609 && GET_CODE (prev) == INSN
610 && sets_cc0_p (PATTERN (prev)))
611 {
5f4f0e22 612 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS
613 goto retry;
614
615 for (nextlinks = LOG_LINKS (prev); nextlinks;
616 nextlinks = XEXP (nextlinks, 1))
617 if ((next = try_combine (insn, prev,
618 XEXP (nextlinks, 0))) != 0)
619 goto retry;
620 }
621
622 /* Do the same for an insn that explicitly references CC0. */
623 if (GET_CODE (insn) == INSN
624 && (prev = prev_nonnote_insn (insn)) != 0
625 && GET_CODE (prev) == INSN
626 && sets_cc0_p (PATTERN (prev))
627 && GET_CODE (PATTERN (insn)) == SET
628 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
629 {
5f4f0e22 630 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS
631 goto retry;
632
633 for (nextlinks = LOG_LINKS (prev); nextlinks;
634 nextlinks = XEXP (nextlinks, 1))
635 if ((next = try_combine (insn, prev,
636 XEXP (nextlinks, 0))) != 0)
637 goto retry;
638 }
639
640 /* Finally, see if any of the insns that this insn links to
641 explicitly references CC0. If so, try this insn, that insn,
5089e22e 642 and its predecessor if it sets CC0. */
230d793d
RS
643 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
644 if (GET_CODE (XEXP (links, 0)) == INSN
645 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
646 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
647 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev))
650 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
651 goto retry;
652#endif
653
654 /* Try combining an insn with two different insns whose results it
655 uses. */
656 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
657 for (nextlinks = XEXP (links, 1); nextlinks;
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, XEXP (links, 0),
660 XEXP (nextlinks, 0))) != 0)
661 goto retry;
662
663 if (GET_CODE (insn) != NOTE)
664 record_dead_and_set_regs (insn);
665
666 retry:
667 ;
668 }
669 }
670
671 total_attempts += combine_attempts;
672 total_merges += combine_merges;
673 total_extras += combine_extras;
674 total_successes += combine_successes;
1a26b032 675
951553af 676 nonzero_sign_valid = 0;
972b320c
R
677
678 /* Make recognizer allow volatile MEMs again. */
679 init_recog ();
230d793d 680}
ef026f91
RS
681
682/* Wipe the reg_last_xxx arrays in preparation for another pass. */
683
684static void
685init_reg_last_arrays ()
686{
687 int nregs = combine_max_regno;
688
4c9a05bc
RK
689 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
692 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
693 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
ef026f91 694 bzero (reg_last_set_invalid, nregs * sizeof (char));
4c9a05bc
RK
695 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
696 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS
697 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
698}
230d793d 699\f
7988fd36
RK
700/* Set up any promoted values for incoming argument registers. */
701
ee791cc3 702static void
7988fd36
RK
703setup_incoming_promotions ()
704{
705#ifdef PROMOTE_FUNCTION_ARGS
706 int regno;
707 rtx reg;
708 enum machine_mode mode;
709 int unsignedp;
710 rtx first = get_insns ();
711
712 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
713 if (FUNCTION_ARG_REGNO_P (regno)
714 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
38a448ca
RH
715 {
716 record_value_for_reg
717 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
718 : SIGN_EXTEND),
719 GET_MODE (reg),
720 gen_rtx_CLOBBER (mode, const0_rtx)));
721 }
7988fd36
RK
722#endif
723}
724\f
91102d5a
RK
725/* Called via note_stores. If X is a pseudo that is narrower than
726 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
230d793d
RS
727
728 If we are setting only a portion of X and we can't figure out what
729 portion, assume all bits will be used since we don't know what will
d0ab8cd3
RK
730 be happening.
731
732 Similarly, set how many bits of X are known to be copies of the sign bit
733 at all locations in the function. This is the smallest number implied
734 by any set of X. */
230d793d
RS
735
736static void
951553af 737set_nonzero_bits_and_sign_copies (x, set)
230d793d
RS
738 rtx x;
739 rtx set;
740{
d0ab8cd3
RK
741 int num;
742
230d793d
RS
743 if (GET_CODE (x) == REG
744 && REGNO (x) >= FIRST_PSEUDO_REGISTER
e8095e80
RK
745 /* If this register is undefined at the start of the file, we can't
746 say what its contents were. */
8e08106d 747 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
5f4f0e22 748 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
230d793d 749 {
2dab894a 750 if (set == 0 || GET_CODE (set) == CLOBBER)
e8095e80
RK
751 {
752 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 753 reg_sign_bit_copies[REGNO (x)] = 1;
e8095e80
RK
754 return;
755 }
230d793d
RS
756
757 /* If this is a complex assignment, see if we can convert it into a
5089e22e 758 simple assignment. */
230d793d 759 set = expand_field_assignment (set);
d79f08e0
RK
760
761 /* If this is a simple assignment, or we have a paradoxical SUBREG,
762 set what we know about X. */
763
764 if (SET_DEST (set) == x
765 || (GET_CODE (SET_DEST (set)) == SUBREG
705c7b3b
JW
766 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
d79f08e0 768 && SUBREG_REG (SET_DEST (set)) == x))
d0ab8cd3 769 {
9afa3d54
RK
770 rtx src = SET_SRC (set);
771
772#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
773 /* If X is narrower than a word and SRC is a non-negative
774 constant that would appear negative in the mode of X,
775 sign-extend it for use in reg_nonzero_bits because some
776 machines (maybe most) will actually do the sign-extension
777 and this is the conservative approach.
778
779 ??? For 2.5, try to tighten up the MD files in this regard
780 instead of this kludge. */
781
782 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
783 && GET_CODE (src) == CONST_INT
784 && INTVAL (src) > 0
785 && 0 != (INTVAL (src)
786 & ((HOST_WIDE_INT) 1
9e69be8c 787 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK
788 src = GEN_INT (INTVAL (src)
789 | ((HOST_WIDE_INT) (-1)
790 << GET_MODE_BITSIZE (GET_MODE (x))));
791#endif
792
951553af 793 reg_nonzero_bits[REGNO (x)]
9afa3d54 794 |= nonzero_bits (src, nonzero_bits_mode);
d0ab8cd3
RK
795 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
796 if (reg_sign_bit_copies[REGNO (x)] == 0
797 || reg_sign_bit_copies[REGNO (x)] > num)
798 reg_sign_bit_copies[REGNO (x)] = num;
799 }
230d793d 800 else
d0ab8cd3 801 {
951553af 802 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 803 reg_sign_bit_copies[REGNO (x)] = 1;
d0ab8cd3 804 }
230d793d
RS
805 }
806}
807\f
808/* See if INSN can be combined into I3. PRED and SUCC are optionally
809 insns that were previously combined into I3 or that will be combined
810 into the merger of INSN and I3.
811
812 Return 0 if the combination is not allowed for any reason.
813
814 If the combination is allowed, *PDEST will be set to the single
815 destination of INSN and *PSRC to the single source, and this function
816 will return 1. */
817
818static int
819can_combine_p (insn, i3, pred, succ, pdest, psrc)
820 rtx insn;
821 rtx i3;
e51712db
KG
822 rtx pred ATTRIBUTE_UNUSED;
823 rtx succ;
230d793d
RS
824 rtx *pdest, *psrc;
825{
826 int i;
827 rtx set = 0, src, dest;
b729186a
JL
828 rtx p;
829#ifdef AUTO_INC_DEC
76d31c63 830 rtx link;
b729186a 831#endif
230d793d
RS
832 int all_adjacent = (succ ? (next_active_insn (insn) == succ
833 && next_active_insn (succ) == i3)
834 : next_active_insn (insn) == i3);
835
836 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
837 or a PARALLEL consisting of such a SET and CLOBBERs.
838
839 If INSN has CLOBBER parallel parts, ignore them for our processing.
840 By definition, these happen during the execution of the insn. When it
841 is merged with another insn, all bets are off. If they are, in fact,
842 needed and aren't also supplied in I3, they may be added by
843 recog_for_combine. Otherwise, it won't match.
844
845 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
846 note.
847
848 Get the source and destination of INSN. If more than one, can't
849 combine. */
850
851 if (GET_CODE (PATTERN (insn)) == SET)
852 set = PATTERN (insn);
853 else if (GET_CODE (PATTERN (insn)) == PARALLEL
854 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
855 {
856 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
857 {
858 rtx elt = XVECEXP (PATTERN (insn), 0, i);
859
860 switch (GET_CODE (elt))
861 {
e3258cef
R
862 /* This is important to combine floating point insns
863 for the SH4 port. */
864 case USE:
865 /* Combining an isolated USE doesn't make sense.
866 We depend here on combinable_i3_pat to reject them. */
867 /* The code below this loop only verifies that the inputs of
868 the SET in INSN do not change. We call reg_set_between_p
869 to verify that the REG in the USE does not change betweeen
870 I3 and INSN.
871 If the USE in INSN was for a pseudo register, the matching
872 insn pattern will likely match any register; combining this
873 with any other USE would only be safe if we knew that the
874 used registers have identical values, or if there was
875 something to tell them apart, e.g. different modes. For
876 now, we forgo such compilcated tests and simply disallow
877 combining of USES of pseudo registers with any other USE. */
878 if (GET_CODE (XEXP (elt, 0)) == REG
879 && GET_CODE (PATTERN (i3)) == PARALLEL)
880 {
881 rtx i3pat = PATTERN (i3);
882 int i = XVECLEN (i3pat, 0) - 1;
883 int regno = REGNO (XEXP (elt, 0));
884 do
885 {
886 rtx i3elt = XVECEXP (i3pat, 0, i);
887 if (GET_CODE (i3elt) == USE
888 && GET_CODE (XEXP (i3elt, 0)) == REG
889 && (REGNO (XEXP (i3elt, 0)) == regno
890 ? reg_set_between_p (XEXP (elt, 0),
891 PREV_INSN (insn), i3)
892 : regno >= FIRST_PSEUDO_REGISTER))
893 return 0;
894 }
895 while (--i >= 0);
896 }
897 break;
898
230d793d
RS
899 /* We can ignore CLOBBERs. */
900 case CLOBBER:
901 break;
902
903 case SET:
904 /* Ignore SETs whose result isn't used but not those that
905 have side-effects. */
906 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
907 && ! side_effects_p (elt))
908 break;
909
910 /* If we have already found a SET, this is a second one and
911 so we cannot combine with this insn. */
912 if (set)
913 return 0;
914
915 set = elt;
916 break;
917
918 default:
919 /* Anything else means we can't combine. */
920 return 0;
921 }
922 }
923
924 if (set == 0
925 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
926 so don't do anything with it. */
927 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
928 return 0;
929 }
930 else
931 return 0;
932
933 if (set == 0)
934 return 0;
935
936 set = expand_field_assignment (set);
937 src = SET_SRC (set), dest = SET_DEST (set);
938
939 /* Don't eliminate a store in the stack pointer. */
940 if (dest == stack_pointer_rtx
230d793d
RS
941 /* If we couldn't eliminate a field assignment, we can't combine. */
942 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
943 /* Don't combine with an insn that sets a register to itself if it has
944 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
5f4f0e22 945 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
230d793d
RS
946 /* Can't merge a function call. */
947 || GET_CODE (src) == CALL
cd5e8f1f 948 /* Don't eliminate a function call argument. */
4dca5ec5
RK
949 || (GET_CODE (i3) == CALL_INSN
950 && (find_reg_fusage (i3, USE, dest)
951 || (GET_CODE (dest) == REG
952 && REGNO (dest) < FIRST_PSEUDO_REGISTER
953 && global_regs[REGNO (dest)])))
230d793d
RS
954 /* Don't substitute into an incremented register. */
955 || FIND_REG_INC_NOTE (i3, dest)
956 || (succ && FIND_REG_INC_NOTE (succ, dest))
ec35104c 957#if 0
230d793d 958 /* Don't combine the end of a libcall into anything. */
ec35104c
JL
959 /* ??? This gives worse code, and appears to be unnecessary, since no
960 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
961 use REG_RETVAL notes for noconflict blocks, but other code here
962 makes sure that those insns don't disappear. */
5f4f0e22 963 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
ec35104c 964#endif
230d793d
RS
965 /* Make sure that DEST is not used after SUCC but before I3. */
966 || (succ && ! all_adjacent
967 && reg_used_between_p (dest, succ, i3))
968 /* Make sure that the value that is to be substituted for the register
969 does not use any registers whose values alter in between. However,
970 If the insns are adjacent, a use can't cross a set even though we
971 think it might (this can happen for a sequence of insns each setting
972 the same destination; reg_last_set of that register might point to
d81481d3
RK
973 a NOTE). If INSN has a REG_EQUIV note, the register is always
974 equivalent to the memory so the substitution is valid even if there
975 are intervening stores. Also, don't move a volatile asm or
976 UNSPEC_VOLATILE across any other insns. */
230d793d 977 || (! all_adjacent
d81481d3
RK
978 && (((GET_CODE (src) != MEM
979 || ! find_reg_note (insn, REG_EQUIV, src))
980 && use_crosses_set_p (src, INSN_CUID (insn)))
a66a10c7
RS
981 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
982 || GET_CODE (src) == UNSPEC_VOLATILE))
230d793d
RS
983 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
984 better register allocation by not doing the combine. */
985 || find_reg_note (i3, REG_NO_CONFLICT, dest)
986 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
987 /* Don't combine across a CALL_INSN, because that would possibly
988 change whether the life span of some REGs crosses calls or not,
989 and it is a pain to update that information.
990 Exception: if source is a constant, moving it later can't hurt.
991 Accept that special case, because it helps -fforce-addr a lot. */
992 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
993 return 0;
994
995 /* DEST must either be a REG or CC0. */
996 if (GET_CODE (dest) == REG)
997 {
998 /* If register alignment is being enforced for multi-word items in all
999 cases except for parameters, it is possible to have a register copy
1000 insn referencing a hard register that is not allowed to contain the
1001 mode being copied and which would not be valid as an operand of most
1002 insns. Eliminate this problem by not combining with such an insn.
1003
1004 Also, on some machines we don't want to extend the life of a hard
4d2c432d
RK
1005 register.
1006
1007 This is the same test done in can_combine except that we don't test
1008 if SRC is a CALL operation to permit a hard register with
1009 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1010 into account. */
230d793d
RS
1011
1012 if (GET_CODE (src) == REG
1013 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1014 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
c448a43e
RK
1015 /* Don't extend the life of a hard register unless it is
1016 user variable (if we have few registers) or it can't
1017 fit into the desired register (meaning something special
ecd40809
RK
1018 is going on).
1019 Also avoid substituting a return register into I3, because
1020 reload can't handle a conflict with constraints of other
1021 inputs. */
230d793d 1022 || (REGNO (src) < FIRST_PSEUDO_REGISTER
c448a43e 1023 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
f95182a4
ILT
1024 || (SMALL_REGISTER_CLASSES
1025 && ((! all_adjacent && ! REG_USERVAR_P (src))
1026 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
e9a25f70 1027 && ! REG_USERVAR_P (src))))))))
230d793d
RS
1028 return 0;
1029 }
1030 else if (GET_CODE (dest) != CC0)
1031 return 0;
1032
5f96750d
RS
1033 /* Don't substitute for a register intended as a clobberable operand.
1034 Similarly, don't substitute an expression containing a register that
1035 will be clobbered in I3. */
230d793d
RS
1036 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1037 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1038 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
5f96750d
RS
1039 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1040 src)
1041 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
230d793d
RS
1042 return 0;
1043
1044 /* If INSN contains anything volatile, or is an `asm' (whether volatile
d276f2bb 1045 or not), reject, unless nothing volatile comes between it and I3 */
230d793d
RS
1046
1047 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
d276f2bb
CM
1048 {
1049 /* Make sure succ doesn't contain a volatile reference. */
1050 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1051 return 0;
1052
1053 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1054 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1055 && p != succ && volatile_refs_p (PATTERN (p)))
1056 return 0;
1057 }
230d793d 1058
b79ee7eb
RH
1059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1060 to be an explicit register variable, and was chosen for a reason. */
1061
1062 if (GET_CODE (src) == ASM_OPERANDS
1063 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1064 return 0;
1065
4b2cb4a2
RS
1066 /* If there are any volatile insns between INSN and I3, reject, because
1067 they might affect machine state. */
1068
1069 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1070 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1071 && p != succ && volatile_insn_p (PATTERN (p)))
1072 return 0;
1073
230d793d
RS
1074 /* If INSN or I2 contains an autoincrement or autodecrement,
1075 make sure that register is not used between there and I3,
1076 and not already used in I3 either.
1077 Also insist that I3 not be a jump; if it were one
1078 and the incremented register were spilled, we would lose. */
1079
1080#ifdef AUTO_INC_DEC
1081 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1082 if (REG_NOTE_KIND (link) == REG_INC
1083 && (GET_CODE (i3) == JUMP_INSN
1084 || reg_used_between_p (XEXP (link, 0), insn, i3)
1085 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1086 return 0;
1087#endif
1088
1089#ifdef HAVE_cc0
1090 /* Don't combine an insn that follows a CC0-setting insn.
1091 An insn that uses CC0 must not be separated from the one that sets it.
1092 We do, however, allow I2 to follow a CC0-setting insn if that insn
1093 is passed as I1; in that case it will be deleted also.
1094 We also allow combining in this case if all the insns are adjacent
1095 because that would leave the two CC0 insns adjacent as well.
1096 It would be more logical to test whether CC0 occurs inside I1 or I2,
1097 but that would be much slower, and this ought to be equivalent. */
1098
1099 p = prev_nonnote_insn (insn);
1100 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1101 && ! all_adjacent)
1102 return 0;
1103#endif
1104
1105 /* If we get here, we have passed all the tests and the combination is
1106 to be allowed. */
1107
1108 *pdest = dest;
1109 *psrc = src;
1110
1111 return 1;
1112}
1113\f
956d6950
JL
1114/* Check if PAT is an insn - or a part of it - used to set up an
1115 argument for a function in a hard register. */
1116
1117static int
1118sets_function_arg_p (pat)
1119 rtx pat;
1120{
1121 int i;
1122 rtx inner_dest;
1123
1124 switch (GET_CODE (pat))
1125 {
1126 case INSN:
1127 return sets_function_arg_p (PATTERN (pat));
1128
1129 case PARALLEL:
1130 for (i = XVECLEN (pat, 0); --i >= 0;)
1131 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1132 return 1;
1133
1134 break;
1135
1136 case SET:
1137 inner_dest = SET_DEST (pat);
1138 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1139 || GET_CODE (inner_dest) == SUBREG
1140 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1141 inner_dest = XEXP (inner_dest, 0);
1142
1143 return (GET_CODE (inner_dest) == REG
1144 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1145 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1d300e19
KG
1146
1147 default:
1148 break;
956d6950
JL
1149 }
1150
1151 return 0;
1152}
1153
230d793d
RS
1154/* LOC is the location within I3 that contains its pattern or the component
1155 of a PARALLEL of the pattern. We validate that it is valid for combining.
1156
1157 One problem is if I3 modifies its output, as opposed to replacing it
1158 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1159 so would produce an insn that is not equivalent to the original insns.
1160
1161 Consider:
1162
1163 (set (reg:DI 101) (reg:DI 100))
1164 (set (subreg:SI (reg:DI 101) 0) <foo>)
1165
1166 This is NOT equivalent to:
1167
1168 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1169 (set (reg:DI 101) (reg:DI 100))])
1170
1171 Not only does this modify 100 (in which case it might still be valid
1172 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1173
1174 We can also run into a problem if I2 sets a register that I1
1175 uses and I1 gets directly substituted into I3 (not via I2). In that
1176 case, we would be getting the wrong value of I2DEST into I3, so we
1177 must reject the combination. This case occurs when I2 and I1 both
1178 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1179 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1180 of a SET must prevent combination from occurring.
1181
e9a25f70 1182 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
c448a43e
RK
1183 if the destination of a SET is a hard register that isn't a user
1184 variable.
230d793d
RS
1185
1186 Before doing the above check, we first try to expand a field assignment
1187 into a set of logical operations.
1188
1189 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1190 we place a register that is both set and used within I3. If more than one
1191 such register is detected, we fail.
1192
1193 Return 1 if the combination is valid, zero otherwise. */
1194
1195static int
1196combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1197 rtx i3;
1198 rtx *loc;
1199 rtx i2dest;
1200 rtx i1dest;
1201 int i1_not_in_src;
1202 rtx *pi3dest_killed;
1203{
1204 rtx x = *loc;
1205
1206 if (GET_CODE (x) == SET)
1207 {
1208 rtx set = expand_field_assignment (x);
1209 rtx dest = SET_DEST (set);
1210 rtx src = SET_SRC (set);
29a82058
JL
1211 rtx inner_dest = dest;
1212
1213#if 0
1214 rtx inner_src = src;
1215#endif
230d793d
RS
1216
1217 SUBST (*loc, set);
1218
1219 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest) == SUBREG
1221 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1222 inner_dest = XEXP (inner_dest, 0);
1223
1224 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1225 was added. */
1226#if 0
1227 while (GET_CODE (inner_src) == STRICT_LOW_PART
1228 || GET_CODE (inner_src) == SUBREG
1229 || GET_CODE (inner_src) == ZERO_EXTRACT)
1230 inner_src = XEXP (inner_src, 0);
1231
1232 /* If it is better that two different modes keep two different pseudos,
1233 avoid combining them. This avoids producing the following pattern
1234 on a 386:
1235 (set (subreg:SI (reg/v:QI 21) 0)
1236 (lshiftrt:SI (reg/v:SI 20)
1237 (const_int 24)))
1238 If that were made, reload could not handle the pair of
1239 reg 20/21, since it would try to get any GENERAL_REGS
1240 but some of them don't handle QImode. */
1241
1242 if (rtx_equal_p (inner_src, i2dest)
1243 && GET_CODE (inner_dest) == REG
1244 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1245 return 0;
1246#endif
1247
1248 /* Check for the case where I3 modifies its output, as
1249 discussed above. */
1250 if ((inner_dest != dest
1251 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1252 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
956d6950 1253
3f508eca
RK
1254 /* This is the same test done in can_combine_p except that we
1255 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
956d6950
JL
1256 CALL operation. Moreover, we can't test all_adjacent; we don't
1257 have to, since this instruction will stay in place, thus we are
1258 not considering increasing the lifetime of INNER_DEST.
1259
1260 Also, if this insn sets a function argument, combining it with
1261 something that might need a spill could clobber a previous
1262 function argument; the all_adjacent test in can_combine_p also
1263 checks this; here, we do a more specific test for this case. */
1264
230d793d 1265 || (GET_CODE (inner_dest) == REG
dfbe1b2f 1266 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
c448a43e
RK
1267 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1268 GET_MODE (inner_dest))
e9a25f70
JL
1269 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1270 && ! REG_USERVAR_P (inner_dest)
956d6950
JL
1271 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1272 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1273 && i3 != 0
1274 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
230d793d
RS
1275 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1276 return 0;
1277
1278 /* If DEST is used in I3, it is being killed in this insn,
36a9c2e9
JL
1279 so record that for later.
1280 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1281 STACK_POINTER_REGNUM, since these are always considered to be
1282 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
230d793d 1283 if (pi3dest_killed && GET_CODE (dest) == REG
36a9c2e9
JL
1284 && reg_referenced_p (dest, PATTERN (i3))
1285 && REGNO (dest) != FRAME_POINTER_REGNUM
6d7096b0
DE
1286#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1287 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1288#endif
36a9c2e9
JL
1289#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1290 && (REGNO (dest) != ARG_POINTER_REGNUM
1291 || ! fixed_regs [REGNO (dest)])
1292#endif
1293 && REGNO (dest) != STACK_POINTER_REGNUM)
230d793d
RS
1294 {
1295 if (*pi3dest_killed)
1296 return 0;
1297
1298 *pi3dest_killed = dest;
1299 }
1300 }
1301
1302 else if (GET_CODE (x) == PARALLEL)
1303 {
1304 int i;
1305
1306 for (i = 0; i < XVECLEN (x, 0); i++)
1307 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1308 i1_not_in_src, pi3dest_killed))
1309 return 0;
1310 }
1311
1312 return 1;
1313}
1314\f
1315/* Try to combine the insns I1 and I2 into I3.
1316 Here I1 and I2 appear earlier than I3.
1317 I1 can be zero; then we combine just I2 into I3.
1318
1319 It we are combining three insns and the resulting insn is not recognized,
1320 try splitting it into two insns. If that happens, I2 and I3 are retained
1321 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1322 are pseudo-deleted.
1323
abe6e52f
RK
1324 Return 0 if the combination does not work. Then nothing is changed.
1325 If we did the combination, return the insn at which combine should
1326 resume scanning. */
230d793d
RS
1327
1328static rtx
1329try_combine (i3, i2, i1)
1330 register rtx i3, i2, i1;
1331{
1332 /* New patterns for I3 and I3, respectively. */
1333 rtx newpat, newi2pat = 0;
1334 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1335 int added_sets_1, added_sets_2;
1336 /* Total number of SETs to put into I3. */
1337 int total_sets;
1338 /* Nonzero is I2's body now appears in I3. */
1339 int i2_is_used;
1340 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1341 int insn_code_number, i2_code_number, other_code_number;
1342 /* Contains I3 if the destination of I3 is used in its source, which means
1343 that the old life of I3 is being killed. If that usage is placed into
1344 I2 and not in I3, a REG_DEAD note must be made. */
1345 rtx i3dest_killed = 0;
1346 /* SET_DEST and SET_SRC of I2 and I1. */
1347 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1348 /* PATTERN (I2), or a copy of it in certain cases. */
1349 rtx i2pat;
1350 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
c4e861e8 1351 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
230d793d
RS
1352 int i1_feeds_i3 = 0;
1353 /* Notes that must be added to REG_NOTES in I3 and I2. */
1354 rtx new_i3_notes, new_i2_notes;
176c9e6b
JW
1355 /* Notes that we substituted I3 into I2 instead of the normal case. */
1356 int i3_subst_into_i2 = 0;
df7d75de
RK
1357 /* Notes that I1, I2 or I3 is a MULT operation. */
1358 int have_mult = 0;
230d793d
RS
1359
1360 int maxreg;
1361 rtx temp;
1362 register rtx link;
1363 int i;
1364
1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1366 This can occur when flow deletes an insn that it has merged into an
1367 auto-increment address. We also can't do anything if I3 has a
1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1369 libcall. */
1370
1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
ec35104c
JL
1374#if 0
1375 /* ??? This gives worse code, and appears to be unnecessary, since no
1376 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1377 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1378#endif
1379)
230d793d
RS
1380 return 0;
1381
1382 combine_attempts++;
1383
241cea85 1384 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS
1385 undobuf.other_insn = 0;
1386
1387 /* Save the current high-water-mark so we can free storage if we didn't
1388 accept this combination. */
1389 undobuf.storage = (char *) oballoc (0);
1390
6e25d159
RK
1391 /* Reset the hard register usage information. */
1392 CLEAR_HARD_REG_SET (newpat_used_regs);
1393
230d793d
RS
1394 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1395 code below, set I1 to be the earlier of the two insns. */
1396 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1397 temp = i1, i1 = i2, i2 = temp;
1398
abe6e52f 1399 added_links_insn = 0;
137e889e 1400
230d793d
RS
1401 /* First check for one important special-case that the code below will
1402 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1403 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1404 we may be able to replace that destination with the destination of I3.
1405 This occurs in the common code where we compute both a quotient and
1406 remainder into a structure, in which case we want to do the computation
1407 directly into the structure to avoid register-register copies.
1408
1409 We make very conservative checks below and only try to handle the
1410 most common cases of this. For example, we only handle the case
1411 where I2 and I3 are adjacent to avoid making difficult register
1412 usage tests. */
1413
1414 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1415 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1416 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
f95182a4 1417 && (! SMALL_REGISTER_CLASSES
e9a25f70
JL
1418 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1419 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1420 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
230d793d
RS
1421 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1422 && GET_CODE (PATTERN (i2)) == PARALLEL
1423 && ! side_effects_p (SET_DEST (PATTERN (i3)))
5089e22e
RS
1424 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1425 below would need to check what is inside (and reg_overlap_mentioned_p
1426 doesn't support those codes anyway). Don't allow those destinations;
1427 the resulting insn isn't likely to be recognized anyway. */
1428 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1429 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
230d793d
RS
1430 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1431 SET_DEST (PATTERN (i3)))
1432 && next_real_insn (i2) == i3)
5089e22e
RS
1433 {
1434 rtx p2 = PATTERN (i2);
1435
1436 /* Make sure that the destination of I3,
1437 which we are going to substitute into one output of I2,
1438 is not used within another output of I2. We must avoid making this:
1439 (parallel [(set (mem (reg 69)) ...)
1440 (set (reg 69) ...)])
1441 which is not well-defined as to order of actions.
1442 (Besides, reload can't handle output reloads for this.)
1443
1444 The problem can also happen if the dest of I3 is a memory ref,
1445 if another dest in I2 is an indirect memory ref. */
1446 for (i = 0; i < XVECLEN (p2, 0); i++)
7ca919b7
RK
1447 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1448 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
5089e22e
RS
1449 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1450 SET_DEST (XVECEXP (p2, 0, i))))
1451 break;
230d793d 1452
5089e22e
RS
1453 if (i == XVECLEN (p2, 0))
1454 for (i = 0; i < XVECLEN (p2, 0); i++)
1455 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1456 {
1457 combine_merges++;
230d793d 1458
5089e22e
RS
1459 subst_insn = i3;
1460 subst_low_cuid = INSN_CUID (i2);
230d793d 1461
c4e861e8 1462 added_sets_2 = added_sets_1 = 0;
5089e22e 1463 i2dest = SET_SRC (PATTERN (i3));
230d793d 1464
5089e22e
RS
1465 /* Replace the dest in I2 with our dest and make the resulting
1466 insn the new pattern for I3. Then skip to where we
1467 validate the pattern. Everything was set up above. */
1468 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1469 SET_DEST (PATTERN (i3)));
1470
1471 newpat = p2;
176c9e6b 1472 i3_subst_into_i2 = 1;
5089e22e
RS
1473 goto validate_replacement;
1474 }
1475 }
230d793d
RS
1476
1477#ifndef HAVE_cc0
1478 /* If we have no I1 and I2 looks like:
1479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1480 (set Y OP)])
1481 make up a dummy I1 that is
1482 (set Y OP)
1483 and change I2 to be
1484 (set (reg:CC X) (compare:CC Y (const_int 0)))
1485
1486 (We can ignore any trailing CLOBBERs.)
1487
1488 This undoes a previous combination and allows us to match a branch-and-
1489 decrement insn. */
1490
1491 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1492 && XVECLEN (PATTERN (i2), 0) >= 2
1493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1495 == MODE_CC)
1496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1498 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1499 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1501 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1502 {
1503 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1504 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1505 break;
1506
1507 if (i == 1)
1508 {
1509 /* We make I1 with the same INSN_UID as I2. This gives it
1510 the same INSN_CUID for value tracking. Our fake I1 will
1511 never appear in the insn stream so giving it the same INSN_UID
1512 as I2 will not cause a problem. */
1513
0d9641d1 1514 subst_prev_insn = i1
38a448ca
RH
1515 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1516 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1517 NULL_RTX);
230d793d
RS
1518
1519 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1520 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1521 SET_DEST (PATTERN (i1)));
1522 }
1523 }
1524#endif
1525
1526 /* Verify that I2 and I1 are valid for combining. */
5f4f0e22
CH
1527 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1528 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
230d793d
RS
1529 {
1530 undo_all ();
1531 return 0;
1532 }
1533
1534 /* Record whether I2DEST is used in I2SRC and similarly for the other
1535 cases. Knowing this will help in register status updating below. */
1536 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1537 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1538 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1539
916f14f1 1540 /* See if I1 directly feeds into I3. It does if I1DEST is not used
230d793d
RS
1541 in I2SRC. */
1542 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1543
1544 /* Ensure that I3's pattern can be the destination of combines. */
1545 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1546 i1 && i2dest_in_i1src && i1_feeds_i3,
1547 &i3dest_killed))
1548 {
1549 undo_all ();
1550 return 0;
1551 }
1552
df7d75de
RK
1553 /* See if any of the insns is a MULT operation. Unless one is, we will
1554 reject a combination that is, since it must be slower. Be conservative
1555 here. */
1556 if (GET_CODE (i2src) == MULT
1557 || (i1 != 0 && GET_CODE (i1src) == MULT)
1558 || (GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1560 have_mult = 1;
1561
230d793d
RS
1562 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1563 We used to do this EXCEPT in one case: I3 has a post-inc in an
1564 output operand. However, that exception can give rise to insns like
1565 mov r3,(r3)+
1566 which is a famous insn on the PDP-11 where the value of r3 used as the
5089e22e 1567 source was model-dependent. Avoid this sort of thing. */
230d793d
RS
1568
1569#if 0
1570 if (!(GET_CODE (PATTERN (i3)) == SET
1571 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1572 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1573 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1574 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1575 /* It's not the exception. */
1576#endif
1577#ifdef AUTO_INC_DEC
1578 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1579 if (REG_NOTE_KIND (link) == REG_INC
1580 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1581 || (i1 != 0
1582 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1583 {
1584 undo_all ();
1585 return 0;
1586 }
1587#endif
1588
1589 /* See if the SETs in I1 or I2 need to be kept around in the merged
1590 instruction: whenever the value set there is still needed past I3.
1591 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1592
1593 For the SET in I1, we have two cases: If I1 and I2 independently
1594 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1595 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1596 in I1 needs to be kept around unless I1DEST dies or is set in either
1597 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1598 I1DEST. If so, we know I1 feeds into I2. */
1599
1600 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1601
1602 added_sets_1
1603 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1604 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1605
1606 /* If the set in I2 needs to be kept around, we must make a copy of
1607 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
5089e22e 1608 PATTERN (I2), we are only substituting for the original I1DEST, not into
230d793d
RS
1609 an already-substituted copy. This also prevents making self-referential
1610 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1611 I2DEST. */
1612
1613 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
38a448ca 1614 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
230d793d
RS
1615 : PATTERN (i2));
1616
1617 if (added_sets_2)
1618 i2pat = copy_rtx (i2pat);
1619
1620 combine_merges++;
1621
1622 /* Substitute in the latest insn for the regs set by the earlier ones. */
1623
1624 maxreg = max_reg_num ();
1625
1626 subst_insn = i3;
230d793d
RS
1627
1628 /* It is possible that the source of I2 or I1 may be performing an
1629 unneeded operation, such as a ZERO_EXTEND of something that is known
1630 to have the high part zero. Handle that case by letting subst look at
1631 the innermost one of them.
1632
1633 Another way to do this would be to have a function that tries to
1634 simplify a single insn instead of merging two or more insns. We don't
1635 do this because of the potential of infinite loops and because
1636 of the potential extra memory required. However, doing it the way
1637 we are is a bit of a kludge and doesn't catch all cases.
1638
1639 But only do this if -fexpensive-optimizations since it slows things down
1640 and doesn't usually win. */
1641
1642 if (flag_expensive_optimizations)
1643 {
1644 /* Pass pc_rtx so no substitutions are done, just simplifications.
1645 The cases that we are interested in here do not involve the few
1646 cases were is_replaced is checked. */
1647 if (i1)
d0ab8cd3
RK
1648 {
1649 subst_low_cuid = INSN_CUID (i1);
1650 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1651 }
230d793d 1652 else
d0ab8cd3
RK
1653 {
1654 subst_low_cuid = INSN_CUID (i2);
1655 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1656 }
230d793d 1657
241cea85 1658 undobuf.previous_undos = undobuf.undos;
230d793d
RS
1659 }
1660
1661#ifndef HAVE_cc0
1662 /* Many machines that don't use CC0 have insns that can both perform an
1663 arithmetic operation and set the condition code. These operations will
1664 be represented as a PARALLEL with the first element of the vector
1665 being a COMPARE of an arithmetic operation with the constant zero.
1666 The second element of the vector will set some pseudo to the result
1667 of the same arithmetic operation. If we simplify the COMPARE, we won't
1668 match such a pattern and so will generate an extra insn. Here we test
1669 for this case, where both the comparison and the operation result are
1670 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1671 I2SRC. Later we will make the PARALLEL that contains I2. */
1672
1673 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1674 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1675 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1676 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1677 {
081f5e7e 1678#ifdef EXTRA_CC_MODES
230d793d
RS
1679 rtx *cc_use;
1680 enum machine_mode compare_mode;
081f5e7e 1681#endif
230d793d
RS
1682
1683 newpat = PATTERN (i3);
1684 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1685
1686 i2_is_used = 1;
1687
1688#ifdef EXTRA_CC_MODES
1689 /* See if a COMPARE with the operand we substituted in should be done
1690 with the mode that is currently being used. If not, do the same
1691 processing we do in `subst' for a SET; namely, if the destination
1692 is used only once, try to replace it with a register of the proper
1693 mode and also replace the COMPARE. */
1694 if (undobuf.other_insn == 0
1695 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1696 &undobuf.other_insn))
77fa0940
RK
1697 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1698 i2src, const0_rtx))
230d793d
RS
1699 != GET_MODE (SET_DEST (newpat))))
1700 {
1701 int regno = REGNO (SET_DEST (newpat));
38a448ca 1702 rtx new_dest = gen_rtx_REG (compare_mode, regno);
230d793d
RS
1703
1704 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 1705 || (REG_N_SETS (regno) == 1 && ! added_sets_2
230d793d
RS
1706 && ! REG_USERVAR_P (SET_DEST (newpat))))
1707 {
1708 if (regno >= FIRST_PSEUDO_REGISTER)
1709 SUBST (regno_reg_rtx[regno], new_dest);
1710
1711 SUBST (SET_DEST (newpat), new_dest);
1712 SUBST (XEXP (*cc_use, 0), new_dest);
1713 SUBST (SET_SRC (newpat),
1714 gen_rtx_combine (COMPARE, compare_mode,
1715 i2src, const0_rtx));
1716 }
1717 else
1718 undobuf.other_insn = 0;
1719 }
1720#endif
1721 }
1722 else
1723#endif
1724 {
1725 n_occurrences = 0; /* `subst' counts here */
1726
1727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1728 need to make a unique copy of I2SRC each time we substitute it
1729 to avoid self-referential rtl. */
1730
d0ab8cd3 1731 subst_low_cuid = INSN_CUID (i2);
230d793d
RS
1732 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1733 ! i1_feeds_i3 && i1dest_in_i1src);
241cea85 1734 undobuf.previous_undos = undobuf.undos;
230d793d
RS
1735
1736 /* Record whether i2's body now appears within i3's body. */
1737 i2_is_used = n_occurrences;
1738 }
1739
1740 /* If we already got a failure, don't try to do more. Otherwise,
1741 try to substitute in I1 if we have it. */
1742
1743 if (i1 && GET_CODE (newpat) != CLOBBER)
1744 {
1745 /* Before we can do this substitution, we must redo the test done
1746 above (see detailed comments there) that ensures that I1DEST
0f41302f 1747 isn't mentioned in any SETs in NEWPAT that are field assignments. */
230d793d 1748
5f4f0e22
CH
1749 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1750 0, NULL_PTR))
230d793d
RS
1751 {
1752 undo_all ();
1753 return 0;
1754 }
1755
1756 n_occurrences = 0;
d0ab8cd3 1757 subst_low_cuid = INSN_CUID (i1);
230d793d 1758 newpat = subst (newpat, i1dest, i1src, 0, 0);
241cea85 1759 undobuf.previous_undos = undobuf.undos;
230d793d
RS
1760 }
1761
916f14f1
RK
1762 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1763 to count all the ways that I2SRC and I1SRC can be used. */
5f4f0e22 1764 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
916f14f1 1765 && i2_is_used + added_sets_2 > 1)
5f4f0e22 1766 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
916f14f1
RK
1767 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1768 > 1))
230d793d
RS
1769 /* Fail if we tried to make a new register (we used to abort, but there's
1770 really no reason to). */
1771 || max_reg_num () != maxreg
1772 /* Fail if we couldn't do something and have a CLOBBER. */
df7d75de
RK
1773 || GET_CODE (newpat) == CLOBBER
1774 /* Fail if this new pattern is a MULT and we didn't have one before
1775 at the outer level. */
1776 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1777 && ! have_mult))
230d793d
RS
1778 {
1779 undo_all ();
1780 return 0;
1781 }
1782
1783 /* If the actions of the earlier insns must be kept
1784 in addition to substituting them into the latest one,
1785 we must make a new PARALLEL for the latest insn
1786 to hold additional the SETs. */
1787
1788 if (added_sets_1 || added_sets_2)
1789 {
1790 combine_extras++;
1791
1792 if (GET_CODE (newpat) == PARALLEL)
1793 {
1794 rtvec old = XVEC (newpat, 0);
1795 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
38a448ca 1796 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
59888de2 1797 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
230d793d
RS
1798 sizeof (old->elem[0]) * old->num_elem);
1799 }
1800 else
1801 {
1802 rtx old = newpat;
1803 total_sets = 1 + added_sets_1 + added_sets_2;
38a448ca 1804 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
230d793d
RS
1805 XVECEXP (newpat, 0, 0) = old;
1806 }
1807
1808 if (added_sets_1)
1809 XVECEXP (newpat, 0, --total_sets)
1810 = (GET_CODE (PATTERN (i1)) == PARALLEL
38a448ca 1811 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
230d793d
RS
1812
1813 if (added_sets_2)
1814 {
1815 /* If there is no I1, use I2's body as is. We used to also not do
1816 the subst call below if I2 was substituted into I3,
1817 but that could lose a simplification. */
1818 if (i1 == 0)
1819 XVECEXP (newpat, 0, --total_sets) = i2pat;
1820 else
1821 /* See comment where i2pat is assigned. */
1822 XVECEXP (newpat, 0, --total_sets)
1823 = subst (i2pat, i1dest, i1src, 0, 0);
1824 }
1825 }
1826
1827 /* We come here when we are replacing a destination in I2 with the
1828 destination of I3. */
1829 validate_replacement:
1830
6e25d159
RK
1831 /* Note which hard regs this insn has as inputs. */
1832 mark_used_regs_combine (newpat);
1833
230d793d 1834 /* Is the result of combination a valid instruction? */
8e2f6e35 1835 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS
1836
1837 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1838 the second SET's destination is a register that is unused. In that case,
1839 we just need the first SET. This can occur when simplifying a divmod
1840 insn. We *must* test for this case here because the code below that
1841 splits two independent SETs doesn't handle this case correctly when it
1842 updates the register status. Also check the case where the first
1843 SET's destination is unused. That would not cause incorrect code, but
1844 does cause an unneeded insn to remain. */
1845
1846 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1847 && XVECLEN (newpat, 0) == 2
1848 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1849 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1850 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1851 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1852 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1853 && asm_noperands (newpat) < 0)
1854 {
1855 newpat = XVECEXP (newpat, 0, 0);
8e2f6e35 1856 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS
1857 }
1858
1859 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1860 && XVECLEN (newpat, 0) == 2
1861 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1862 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1863 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1864 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1865 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1866 && asm_noperands (newpat) < 0)
1867 {
1868 newpat = XVECEXP (newpat, 0, 1);
8e2f6e35 1869 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS
1870 }
1871
1872 /* If we were combining three insns and the result is a simple SET
1873 with no ASM_OPERANDS that wasn't recognized, try to split it into two
916f14f1
RK
1874 insns. There are two ways to do this. It can be split using a
1875 machine-specific method (like when you have an addition of a large
1876 constant) or by combine in the function find_split_point. */
1877
230d793d
RS
1878 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1879 && asm_noperands (newpat) < 0)
1880 {
916f14f1 1881 rtx m_split, *split;
42495ca0 1882 rtx ni2dest = i2dest;
916f14f1
RK
1883
1884 /* See if the MD file can split NEWPAT. If it can't, see if letting it
42495ca0
RK
1885 use I2DEST as a scratch register will help. In the latter case,
1886 convert I2DEST to the mode of the source of NEWPAT if we can. */
916f14f1
RK
1887
1888 m_split = split_insns (newpat, i3);
a70c61d9
JW
1889
1890 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1891 inputs of NEWPAT. */
1892
1893 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1894 possible to try that as a scratch reg. This would require adding
1895 more code to make it work though. */
1896
1897 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
42495ca0
RK
1898 {
1899 /* If I2DEST is a hard register or the only use of a pseudo,
1900 we can change its mode. */
1901 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
02f4ada4 1902 && GET_MODE (SET_DEST (newpat)) != VOIDmode
60654f77 1903 && GET_CODE (i2dest) == REG
42495ca0 1904 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1905 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
42495ca0 1906 && ! REG_USERVAR_P (i2dest))))
38a448ca 1907 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
42495ca0
RK
1908 REGNO (i2dest));
1909
38a448ca
RH
1910 m_split = split_insns
1911 (gen_rtx_PARALLEL (VOIDmode,
1912 gen_rtvec (2, newpat,
1913 gen_rtx_CLOBBER (VOIDmode,
1914 ni2dest))),
1915 i3);
42495ca0 1916 }
916f14f1
RK
1917
1918 if (m_split && GET_CODE (m_split) == SEQUENCE
3f508eca
RK
1919 && XVECLEN (m_split, 0) == 2
1920 && (next_real_insn (i2) == i3
1921 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1922 INSN_CUID (i2))))
916f14f1 1923 {
1a26b032 1924 rtx i2set, i3set;
d0ab8cd3 1925 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
916f14f1 1926 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
916f14f1 1927
e4ba89be
RK
1928 i3set = single_set (XVECEXP (m_split, 0, 1));
1929 i2set = single_set (XVECEXP (m_split, 0, 0));
1a26b032 1930
42495ca0
RK
1931 /* In case we changed the mode of I2DEST, replace it in the
1932 pseudo-register table here. We can't do it above in case this
1933 code doesn't get executed and we do a split the other way. */
1934
1935 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1936 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1937
8e2f6e35 1938 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1a26b032
RK
1939
1940 /* If I2 or I3 has multiple SETs, we won't know how to track
9cc96794
RK
1941 register status, so don't use these insns. If I2's destination
1942 is used between I2 and I3, we also can't use these insns. */
1a26b032 1943
9cc96794
RK
1944 if (i2_code_number >= 0 && i2set && i3set
1945 && (next_real_insn (i2) == i3
1946 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
8e2f6e35
BS
1947 insn_code_number = recog_for_combine (&newi3pat, i3,
1948 &new_i3_notes);
d0ab8cd3
RK
1949 if (insn_code_number >= 0)
1950 newpat = newi3pat;
1951
c767f54b 1952 /* It is possible that both insns now set the destination of I3.
22609cbf 1953 If so, we must show an extra use of it. */
c767f54b 1954
393de53f
RK
1955 if (insn_code_number >= 0)
1956 {
1957 rtx new_i3_dest = SET_DEST (i3set);
1958 rtx new_i2_dest = SET_DEST (i2set);
1959
1960 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1961 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1962 || GET_CODE (new_i3_dest) == SUBREG)
1963 new_i3_dest = XEXP (new_i3_dest, 0);
1964
d4096689
RK
1965 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1966 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1967 || GET_CODE (new_i2_dest) == SUBREG)
1968 new_i2_dest = XEXP (new_i2_dest, 0);
1969
393de53f
RK
1970 if (GET_CODE (new_i3_dest) == REG
1971 && GET_CODE (new_i2_dest) == REG
1972 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
b1f21e0a 1973 REG_N_SETS (REGNO (new_i2_dest))++;
393de53f 1974 }
916f14f1 1975 }
230d793d
RS
1976
1977 /* If we can split it and use I2DEST, go ahead and see if that
1978 helps things be recognized. Verify that none of the registers
1979 are set between I2 and I3. */
d0ab8cd3 1980 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
230d793d
RS
1981#ifdef HAVE_cc0
1982 && GET_CODE (i2dest) == REG
1983#endif
1984 /* We need I2DEST in the proper mode. If it is a hard register
1985 or the only use of a pseudo, we can change its mode. */
1986 && (GET_MODE (*split) == GET_MODE (i2dest)
1987 || GET_MODE (*split) == VOIDmode
1988 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1989 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
230d793d
RS
1990 && ! REG_USERVAR_P (i2dest)))
1991 && (next_real_insn (i2) == i3
1992 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1993 /* We can't overwrite I2DEST if its value is still used by
1994 NEWPAT. */
1995 && ! reg_referenced_p (i2dest, newpat))
1996 {
1997 rtx newdest = i2dest;
df7d75de
RK
1998 enum rtx_code split_code = GET_CODE (*split);
1999 enum machine_mode split_mode = GET_MODE (*split);
230d793d
RS
2000
2001 /* Get NEWDEST as a register in the proper mode. We have already
2002 validated that we can do this. */
df7d75de 2003 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
230d793d 2004 {
38a448ca 2005 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
230d793d
RS
2006
2007 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2008 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2009 }
2010
2011 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2012 an ASHIFT. This can occur if it was inside a PLUS and hence
2013 appeared to be a memory address. This is a kludge. */
df7d75de 2014 if (split_code == MULT
230d793d
RS
2015 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2016 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1dc8a823
JW
2017 {
2018 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2019 XEXP (*split, 0), GEN_INT (i)));
2020 /* Update split_code because we may not have a multiply
2021 anymore. */
2022 split_code = GET_CODE (*split);
2023 }
230d793d
RS
2024
2025#ifdef INSN_SCHEDULING
2026 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2027 be written as a ZERO_EXTEND. */
df7d75de
RK
2028 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2029 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
230d793d
RS
2030 XEXP (*split, 0)));
2031#endif
2032
2033 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2034 SUBST (*split, newdest);
8e2f6e35 2035 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
df7d75de
RK
2036
2037 /* If the split point was a MULT and we didn't have one before,
2038 don't use one now. */
2039 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
8e2f6e35 2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS
2041 }
2042 }
2043
2044 /* Check for a case where we loaded from memory in a narrow mode and
2045 then sign extended it, but we need both registers. In that case,
2046 we have a PARALLEL with both loads from the same memory location.
2047 We can split this into a load from memory followed by a register-register
2048 copy. This saves at least one insn, more if register allocation can
f0343c74
RK
2049 eliminate the copy.
2050
2051 We cannot do this if the destination of the second assignment is
2052 a register that we have already assumed is zero-extended. Similarly
2053 for a SUBREG of such a register. */
230d793d
RS
2054
2055 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2056 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2060 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2061 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2062 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2063 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2064 INSN_CUID (i2))
2065 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
f0343c74
RK
2067 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2068 (GET_CODE (temp) == REG
2069 && reg_nonzero_bits[REGNO (temp)] != 0
2070 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2072 && (reg_nonzero_bits[REGNO (temp)]
2073 != GET_MODE_MASK (word_mode))))
2074 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2075 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2076 (GET_CODE (temp) == REG
2077 && reg_nonzero_bits[REGNO (temp)] != 0
2078 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2080 && (reg_nonzero_bits[REGNO (temp)]
2081 != GET_MODE_MASK (word_mode)))))
230d793d
RS
2082 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2083 SET_SRC (XVECEXP (newpat, 0, 1)))
2084 && ! find_reg_note (i3, REG_UNUSED,
2085 SET_DEST (XVECEXP (newpat, 0, 0))))
2086 {
472fbdd1
RK
2087 rtx ni2dest;
2088
230d793d 2089 newi2pat = XVECEXP (newpat, 0, 0);
472fbdd1 2090 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
230d793d
RS
2091 newpat = XVECEXP (newpat, 0, 1);
2092 SUBST (SET_SRC (newpat),
472fbdd1 2093 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
8e2f6e35 2094 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2095
230d793d 2096 if (i2_code_number >= 0)
8e2f6e35 2097 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
5089e22e
RS
2098
2099 if (insn_code_number >= 0)
2100 {
2101 rtx insn;
2102 rtx link;
2103
2104 /* If we will be able to accept this, we have made a change to the
2105 destination of I3. This can invalidate a LOG_LINKS pointing
2106 to I3. No other part of combine.c makes such a transformation.
2107
2108 The new I3 will have a destination that was previously the
2109 destination of I1 or I2 and which was used in i2 or I3. Call
2110 distribute_links to make a LOG_LINK from the next use of
2111 that destination. */
2112
2113 PATTERN (i3) = newpat;
38a448ca 2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
5089e22e
RS
2115
2116 /* I3 now uses what used to be its destination and which is
2117 now I2's destination. That means we need a LOG_LINK from
2118 I3 to I2. But we used to have one, so we still will.
2119
2120 However, some later insn might be using I2's dest and have
2121 a LOG_LINK pointing at I3. We must remove this link.
2122 The simplest way to remove the link is to point it at I1,
2123 which we know will be a NOTE. */
2124
2125 for (insn = NEXT_INSN (i3);
0d4d42c3 2126 insn && (this_basic_block == n_basic_blocks - 1
3b413743 2127 || insn != BLOCK_HEAD (this_basic_block + 1));
5089e22e
RS
2128 insn = NEXT_INSN (insn))
2129 {
2130 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
472fbdd1 2131 && reg_referenced_p (ni2dest, PATTERN (insn)))
5089e22e
RS
2132 {
2133 for (link = LOG_LINKS (insn); link;
2134 link = XEXP (link, 1))
2135 if (XEXP (link, 0) == i3)
2136 XEXP (link, 0) = i1;
2137
2138 break;
2139 }
2140 }
2141 }
230d793d
RS
2142 }
2143
2144 /* Similarly, check for a case where we have a PARALLEL of two independent
2145 SETs but we started with three insns. In this case, we can do the sets
2146 as two separate insns. This case occurs when some SET allows two
2147 other insns to combine, but the destination of that SET is still live. */
2148
2149 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2150 && GET_CODE (newpat) == PARALLEL
2151 && XVECLEN (newpat, 0) == 2
2152 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2153 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2154 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2155 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2156 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2158 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2159 INSN_CUID (i2))
2160 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2161 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2162 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2163 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2164 XVECEXP (newpat, 0, 0))
2165 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2166 XVECEXP (newpat, 0, 1)))
2167 {
e9a25f70
JL
2168 /* Normally, it doesn't matter which of the two is done first,
2169 but it does if one references cc0. In that case, it has to
2170 be first. */
2171#ifdef HAVE_cc0
2172 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2173 {
2174 newi2pat = XVECEXP (newpat, 0, 0);
2175 newpat = XVECEXP (newpat, 0, 1);
2176 }
2177 else
2178#endif
2179 {
2180 newi2pat = XVECEXP (newpat, 0, 1);
2181 newpat = XVECEXP (newpat, 0, 0);
2182 }
230d793d 2183
8e2f6e35 2184 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2185
230d793d 2186 if (i2_code_number >= 0)
8e2f6e35 2187 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS
2188 }
2189
2190 /* If it still isn't recognized, fail and change things back the way they
2191 were. */
2192 if ((insn_code_number < 0
2193 /* Is the result a reasonable ASM_OPERANDS? */
2194 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2195 {
2196 undo_all ();
2197 return 0;
2198 }
2199
2200 /* If we had to change another insn, make sure it is valid also. */
2201 if (undobuf.other_insn)
2202 {
230d793d
RS
2203 rtx other_pat = PATTERN (undobuf.other_insn);
2204 rtx new_other_notes;
2205 rtx note, next;
2206
6e25d159
RK
2207 CLEAR_HARD_REG_SET (newpat_used_regs);
2208
8e2f6e35
BS
2209 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2210 &new_other_notes);
230d793d
RS
2211
2212 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2213 {
2214 undo_all ();
2215 return 0;
2216 }
2217
2218 PATTERN (undobuf.other_insn) = other_pat;
2219
2220 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2221 are still valid. Then add any non-duplicate notes added by
2222 recog_for_combine. */
2223 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2224 {
2225 next = XEXP (note, 1);
2226
2227 if (REG_NOTE_KIND (note) == REG_UNUSED
2228 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1a26b032
RK
2229 {
2230 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2231 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
1a26b032
RK
2232
2233 remove_note (undobuf.other_insn, note);
2234 }
230d793d
RS
2235 }
2236
1a26b032
RK
2237 for (note = new_other_notes; note; note = XEXP (note, 1))
2238 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2239 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 2240
230d793d 2241 distribute_notes (new_other_notes, undobuf.other_insn,
5f4f0e22 2242 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
230d793d
RS
2243 }
2244
2245 /* We now know that we can do this combination. Merge the insns and
2246 update the status of registers and LOG_LINKS. */
2247
2248 {
2249 rtx i3notes, i2notes, i1notes = 0;
2250 rtx i3links, i2links, i1links = 0;
2251 rtx midnotes = 0;
230d793d 2252 register int regno;
ff3467a9
JW
2253 /* Compute which registers we expect to eliminate. newi2pat may be setting
2254 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2255 same as i3dest, in which case newi2pat may be setting i1dest. */
2256 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2257 || i2dest_in_i2src || i2dest_in_i1src
230d793d 2258 ? 0 : i2dest);
ff3467a9
JW
2259 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2260 || (newi2pat && reg_set_p (i1dest, newi2pat))
2261 ? 0 : i1dest);
230d793d
RS
2262
2263 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2264 clear them. */
2265 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2266 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2267 if (i1)
2268 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2269
2270 /* Ensure that we do not have something that should not be shared but
2271 occurs multiple times in the new insns. Check this by first
5089e22e 2272 resetting all the `used' flags and then copying anything is shared. */
230d793d
RS
2273
2274 reset_used_flags (i3notes);
2275 reset_used_flags (i2notes);
2276 reset_used_flags (i1notes);
2277 reset_used_flags (newpat);
2278 reset_used_flags (newi2pat);
2279 if (undobuf.other_insn)
2280 reset_used_flags (PATTERN (undobuf.other_insn));
2281
2282 i3notes = copy_rtx_if_shared (i3notes);
2283 i2notes = copy_rtx_if_shared (i2notes);
2284 i1notes = copy_rtx_if_shared (i1notes);
2285 newpat = copy_rtx_if_shared (newpat);
2286 newi2pat = copy_rtx_if_shared (newi2pat);
2287 if (undobuf.other_insn)
2288 reset_used_flags (PATTERN (undobuf.other_insn));
2289
2290 INSN_CODE (i3) = insn_code_number;
2291 PATTERN (i3) = newpat;
2292 if (undobuf.other_insn)
2293 INSN_CODE (undobuf.other_insn) = other_code_number;
2294
2295 /* We had one special case above where I2 had more than one set and
2296 we replaced a destination of one of those sets with the destination
2297 of I3. In that case, we have to update LOG_LINKS of insns later
176c9e6b
JW
2298 in this basic block. Note that this (expensive) case is rare.
2299
2300 Also, in this case, we must pretend that all REG_NOTEs for I2
2301 actually came from I3, so that REG_UNUSED notes from I2 will be
2302 properly handled. */
2303
2304 if (i3_subst_into_i2)
2305 {
2306 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2307 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2308 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2309 && ! find_reg_note (i2, REG_UNUSED,
2310 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2311 for (temp = NEXT_INSN (i2);
2312 temp && (this_basic_block == n_basic_blocks - 1
3b413743 2313 || BLOCK_HEAD (this_basic_block) != temp);
176c9e6b
JW
2314 temp = NEXT_INSN (temp))
2315 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2316 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2317 if (XEXP (link, 0) == i2)
2318 XEXP (link, 0) = i3;
2319
2320 if (i3notes)
2321 {
2322 rtx link = i3notes;
2323 while (XEXP (link, 1))
2324 link = XEXP (link, 1);
2325 XEXP (link, 1) = i2notes;
2326 }
2327 else
2328 i3notes = i2notes;
2329 i2notes = 0;
2330 }
230d793d
RS
2331
2332 LOG_LINKS (i3) = 0;
2333 REG_NOTES (i3) = 0;
2334 LOG_LINKS (i2) = 0;
2335 REG_NOTES (i2) = 0;
2336
2337 if (newi2pat)
2338 {
2339 INSN_CODE (i2) = i2_code_number;
2340 PATTERN (i2) = newi2pat;
2341 }
2342 else
2343 {
2344 PUT_CODE (i2, NOTE);
2345 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2346 NOTE_SOURCE_FILE (i2) = 0;
2347 }
2348
2349 if (i1)
2350 {
2351 LOG_LINKS (i1) = 0;
2352 REG_NOTES (i1) = 0;
2353 PUT_CODE (i1, NOTE);
2354 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2355 NOTE_SOURCE_FILE (i1) = 0;
2356 }
2357
2358 /* Get death notes for everything that is now used in either I3 or
6eb12cef
RK
2359 I2 and used to die in a previous insn. If we built two new
2360 patterns, move from I1 to I2 then I2 to I3 so that we get the
2361 proper movement on registers that I2 modifies. */
230d793d 2362
230d793d 2363 if (newi2pat)
6eb12cef
RK
2364 {
2365 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2366 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2367 }
2368 else
2369 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2370 i3, &midnotes);
230d793d
RS
2371
2372 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2373 if (i3notes)
5f4f0e22
CH
2374 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2375 elim_i2, elim_i1);
230d793d 2376 if (i2notes)
5f4f0e22
CH
2377 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2378 elim_i2, elim_i1);
230d793d 2379 if (i1notes)
5f4f0e22
CH
2380 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2381 elim_i2, elim_i1);
230d793d 2382 if (midnotes)
5f4f0e22
CH
2383 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2384 elim_i2, elim_i1);
230d793d
RS
2385
2386 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2387 know these are REG_UNUSED and want them to go to the desired insn,
1a26b032
RK
2388 so we always pass it as i3. We have not counted the notes in
2389 reg_n_deaths yet, so we need to do so now. */
2390
230d793d 2391 if (newi2pat && new_i2_notes)
1a26b032
RK
2392 {
2393 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2394 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2395 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK
2396
2397 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2398 }
2399
230d793d 2400 if (new_i3_notes)
1a26b032
RK
2401 {
2402 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2403 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2404 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK
2405
2406 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2407 }
230d793d
RS
2408
2409 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
e9a25f70
JL
2410 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2411 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2412 in that case, it might delete I2. Similarly for I2 and I1.
1a26b032
RK
2413 Show an additional death due to the REG_DEAD note we make here. If
2414 we discard it in distribute_notes, we will decrement it again. */
d0ab8cd3 2415
230d793d 2416 if (i3dest_killed)
1a26b032
RK
2417 {
2418 if (GET_CODE (i3dest_killed) == REG)
b1f21e0a 2419 REG_N_DEATHS (REGNO (i3dest_killed))++;
1a26b032 2420
e9a25f70 2421 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
38a448ca
RH
2422 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2423 NULL_RTX),
ff3467a9 2424 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
e9a25f70 2425 else
38a448ca
RH
2426 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2427 NULL_RTX),
e9a25f70 2428 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
ff3467a9 2429 elim_i2, elim_i1);
1a26b032 2430 }
58c8c593 2431
230d793d 2432 if (i2dest_in_i2src)
58c8c593 2433 {
1a26b032 2434 if (GET_CODE (i2dest) == REG)
b1f21e0a 2435 REG_N_DEATHS (REGNO (i2dest))++;
1a26b032 2436
58c8c593 2437 if (newi2pat && reg_set_p (i2dest, newi2pat))
38a448ca 2438 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK
2439 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2440 else
38a448ca 2441 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK
2442 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2443 NULL_RTX, NULL_RTX);
2444 }
2445
230d793d 2446 if (i1dest_in_i1src)
58c8c593 2447 {
1a26b032 2448 if (GET_CODE (i1dest) == REG)
b1f21e0a 2449 REG_N_DEATHS (REGNO (i1dest))++;
1a26b032 2450
58c8c593 2451 if (newi2pat && reg_set_p (i1dest, newi2pat))
38a448ca 2452 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK
2453 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2454 else
38a448ca 2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK
2456 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2457 NULL_RTX, NULL_RTX);
2458 }
230d793d
RS
2459
2460 distribute_links (i3links);
2461 distribute_links (i2links);
2462 distribute_links (i1links);
2463
2464 if (GET_CODE (i2dest) == REG)
2465 {
d0ab8cd3
RK
2466 rtx link;
2467 rtx i2_insn = 0, i2_val = 0, set;
2468
2469 /* The insn that used to set this register doesn't exist, and
2470 this life of the register may not exist either. See if one of
2471 I3's links points to an insn that sets I2DEST. If it does,
2472 that is now the last known value for I2DEST. If we don't update
2473 this and I2 set the register to a value that depended on its old
230d793d
RS
2474 contents, we will get confused. If this insn is used, thing
2475 will be set correctly in combine_instructions. */
d0ab8cd3
RK
2476
2477 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2478 if ((set = single_set (XEXP (link, 0))) != 0
2479 && rtx_equal_p (i2dest, SET_DEST (set)))
2480 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2481
2482 record_value_for_reg (i2dest, i2_insn, i2_val);
230d793d
RS
2483
2484 /* If the reg formerly set in I2 died only once and that was in I3,
2485 zero its use count so it won't make `reload' do any work. */
538fe8cd
ILT
2486 if (! added_sets_2
2487 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2488 && ! i2dest_in_i2src)
230d793d
RS
2489 {
2490 regno = REGNO (i2dest);
b1f21e0a
MM
2491 REG_N_SETS (regno)--;
2492 if (REG_N_SETS (regno) == 0
8e08106d 2493 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2494 REG_N_REFS (regno) = 0;
230d793d
RS
2495 }
2496 }
2497
2498 if (i1 && GET_CODE (i1dest) == REG)
2499 {
d0ab8cd3
RK
2500 rtx link;
2501 rtx i1_insn = 0, i1_val = 0, set;
2502
2503 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2504 if ((set = single_set (XEXP (link, 0))) != 0
2505 && rtx_equal_p (i1dest, SET_DEST (set)))
2506 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2507
2508 record_value_for_reg (i1dest, i1_insn, i1_val);
2509
230d793d 2510 regno = REGNO (i1dest);
5af91171 2511 if (! added_sets_1 && ! i1dest_in_i1src)
230d793d 2512 {
b1f21e0a
MM
2513 REG_N_SETS (regno)--;
2514 if (REG_N_SETS (regno) == 0
8e08106d 2515 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2516 REG_N_REFS (regno) = 0;
230d793d
RS
2517 }
2518 }
2519
951553af 2520 /* Update reg_nonzero_bits et al for any changes that may have been made
22609cbf
RK
2521 to this insn. */
2522
951553af 2523 note_stores (newpat, set_nonzero_bits_and_sign_copies);
22609cbf 2524 if (newi2pat)
951553af 2525 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
22609cbf 2526
230d793d
RS
2527 /* If I3 is now an unconditional jump, ensure that it has a
2528 BARRIER following it since it may have initially been a
381ee8af 2529 conditional jump. It may also be the last nonnote insn. */
230d793d
RS
2530
2531 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
381ee8af
TW
2532 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2533 || GET_CODE (temp) != BARRIER))
230d793d
RS
2534 emit_barrier_after (i3);
2535 }
2536
2537 combine_successes++;
2538
bcd49eb7
JW
2539 /* Clear this here, so that subsequent get_last_value calls are not
2540 affected. */
2541 subst_prev_insn = NULL_RTX;
2542
abe6e52f
RK
2543 if (added_links_insn
2544 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2545 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2546 return added_links_insn;
2547 else
2548 return newi2pat ? i2 : i3;
230d793d
RS
2549}
2550\f
2551/* Undo all the modifications recorded in undobuf. */
2552
2553static void
2554undo_all ()
2555{
241cea85
RK
2556 struct undo *undo, *next;
2557
2558 for (undo = undobuf.undos; undo; undo = next)
7c046e4e 2559 {
241cea85
RK
2560 next = undo->next;
2561 if (undo->is_int)
2562 *undo->where.i = undo->old_contents.i;
7c046e4e 2563 else
241cea85
RK
2564 *undo->where.r = undo->old_contents.r;
2565
2566 undo->next = undobuf.frees;
2567 undobuf.frees = undo;
7c046e4e 2568 }
230d793d
RS
2569
2570 obfree (undobuf.storage);
845fc875 2571 undobuf.undos = undobuf.previous_undos = 0;
bcd49eb7
JW
2572
2573 /* Clear this here, so that subsequent get_last_value calls are not
2574 affected. */
2575 subst_prev_insn = NULL_RTX;
230d793d
RS
2576}
2577\f
2578/* Find the innermost point within the rtx at LOC, possibly LOC itself,
d0ab8cd3
RK
2579 where we have an arithmetic expression and return that point. LOC will
2580 be inside INSN.
230d793d
RS
2581
2582 try_combine will call this function to see if an insn can be split into
2583 two insns. */
2584
2585static rtx *
d0ab8cd3 2586find_split_point (loc, insn)
230d793d 2587 rtx *loc;
d0ab8cd3 2588 rtx insn;
230d793d
RS
2589{
2590 rtx x = *loc;
2591 enum rtx_code code = GET_CODE (x);
2592 rtx *split;
2593 int len = 0, pos, unsignedp;
2594 rtx inner;
2595
2596 /* First special-case some codes. */
2597 switch (code)
2598 {
2599 case SUBREG:
2600#ifdef INSN_SCHEDULING
2601 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2602 point. */
2603 if (GET_CODE (SUBREG_REG (x)) == MEM)
2604 return loc;
2605#endif
d0ab8cd3 2606 return find_split_point (&SUBREG_REG (x), insn);
230d793d 2607
230d793d 2608 case MEM:
916f14f1 2609#ifdef HAVE_lo_sum
230d793d
RS
2610 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2611 using LO_SUM and HIGH. */
2612 if (GET_CODE (XEXP (x, 0)) == CONST
2613 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2614 {
2615 SUBST (XEXP (x, 0),
2616 gen_rtx_combine (LO_SUM, Pmode,
2617 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2618 XEXP (x, 0)));
2619 return &XEXP (XEXP (x, 0), 0);
2620 }
230d793d
RS
2621#endif
2622
916f14f1
RK
2623 /* If we have a PLUS whose second operand is a constant and the
2624 address is not valid, perhaps will can split it up using
2625 the machine-specific way to split large constants. We use
ddd5a7c1 2626 the first pseudo-reg (one of the virtual regs) as a placeholder;
916f14f1
RK
2627 it will not remain in the result. */
2628 if (GET_CODE (XEXP (x, 0)) == PLUS
2629 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2630 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2631 {
2632 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
38a448ca 2633 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
916f14f1
RK
2634 subst_insn);
2635
2636 /* This should have produced two insns, each of which sets our
2637 placeholder. If the source of the second is a valid address,
2638 we can make put both sources together and make a split point
2639 in the middle. */
2640
2641 if (seq && XVECLEN (seq, 0) == 2
2642 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2643 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2644 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2645 && ! reg_mentioned_p (reg,
2646 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2647 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2648 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2649 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2650 && memory_address_p (GET_MODE (x),
2651 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2652 {
2653 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2654 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2655
2656 /* Replace the placeholder in SRC2 with SRC1. If we can
2657 find where in SRC2 it was placed, that can become our
2658 split point and we can replace this address with SRC2.
2659 Just try two obvious places. */
2660
2661 src2 = replace_rtx (src2, reg, src1);
2662 split = 0;
2663 if (XEXP (src2, 0) == src1)
2664 split = &XEXP (src2, 0);
2665 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2666 && XEXP (XEXP (src2, 0), 0) == src1)
2667 split = &XEXP (XEXP (src2, 0), 0);
2668
2669 if (split)
2670 {
2671 SUBST (XEXP (x, 0), src2);
2672 return split;
2673 }
2674 }
1a26b032
RK
2675
2676 /* If that didn't work, perhaps the first operand is complex and
2677 needs to be computed separately, so make a split point there.
2678 This will occur on machines that just support REG + CONST
2679 and have a constant moved through some previous computation. */
2680
2681 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2682 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2683 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2684 == 'o')))
2685 return &XEXP (XEXP (x, 0), 0);
916f14f1
RK
2686 }
2687 break;
2688
230d793d
RS
2689 case SET:
2690#ifdef HAVE_cc0
2691 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2692 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2693 we need to put the operand into a register. So split at that
2694 point. */
2695
2696 if (SET_DEST (x) == cc0_rtx
2697 && GET_CODE (SET_SRC (x)) != COMPARE
2698 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2699 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2700 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2701 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2702 return &SET_SRC (x);
2703#endif
2704
2705 /* See if we can split SET_SRC as it stands. */
d0ab8cd3 2706 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS
2707 if (split && split != &SET_SRC (x))
2708 return split;
2709
041d7180
JL
2710 /* See if we can split SET_DEST as it stands. */
2711 split = find_split_point (&SET_DEST (x), insn);
2712 if (split && split != &SET_DEST (x))
2713 return split;
2714
230d793d
RS
2715 /* See if this is a bitfield assignment with everything constant. If
2716 so, this is an IOR of an AND, so split it into that. */
2717 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
5f4f0e22 2719 <= HOST_BITS_PER_WIDE_INT)
230d793d
RS
2720 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2721 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2722 && GET_CODE (SET_SRC (x)) == CONST_INT
2723 && ((INTVAL (XEXP (SET_DEST (x), 1))
2724 + INTVAL (XEXP (SET_DEST (x), 2)))
2725 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2726 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2727 {
2728 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2729 int len = INTVAL (XEXP (SET_DEST (x), 1));
2730 int src = INTVAL (SET_SRC (x));
2731 rtx dest = XEXP (SET_DEST (x), 0);
2732 enum machine_mode mode = GET_MODE (dest);
5f4f0e22 2733 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
230d793d 2734
f76b9db2
ILT
2735 if (BITS_BIG_ENDIAN)
2736 pos = GET_MODE_BITSIZE (mode) - len - pos;
230d793d 2737
e51712db 2738 if ((unsigned HOST_WIDE_INT) src == mask)
230d793d 2739 SUBST (SET_SRC (x),
5f4f0e22 2740 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
230d793d
RS
2741 else
2742 SUBST (SET_SRC (x),
2743 gen_binary (IOR, mode,
2744 gen_binary (AND, mode, dest,
5f4f0e22
CH
2745 GEN_INT (~ (mask << pos)
2746 & GET_MODE_MASK (mode))),
2747 GEN_INT (src << pos)));
230d793d
RS
2748
2749 SUBST (SET_DEST (x), dest);
2750
d0ab8cd3 2751 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS
2752 if (split && split != &SET_SRC (x))
2753 return split;
2754 }
2755
2756 /* Otherwise, see if this is an operation that we can split into two.
2757 If so, try to split that. */
2758 code = GET_CODE (SET_SRC (x));
2759
2760 switch (code)
2761 {
d0ab8cd3
RK
2762 case AND:
2763 /* If we are AND'ing with a large constant that is only a single
2764 bit and the result is only being used in a context where we
2765 need to know if it is zero or non-zero, replace it with a bit
2766 extraction. This will avoid the large constant, which might
2767 have taken more than one insn to make. If the constant were
2768 not a valid argument to the AND but took only one insn to make,
2769 this is no worse, but if it took more than one insn, it will
2770 be better. */
2771
2772 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2773 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2774 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2775 && GET_CODE (SET_DEST (x)) == REG
2776 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2777 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2778 && XEXP (*split, 0) == SET_DEST (x)
2779 && XEXP (*split, 1) == const0_rtx)
2780 {
76184def
DE
2781 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2782 XEXP (SET_SRC (x), 0),
2783 pos, NULL_RTX, 1, 1, 0, 0);
2784 if (extraction != 0)
2785 {
2786 SUBST (SET_SRC (x), extraction);
2787 return find_split_point (loc, insn);
2788 }
d0ab8cd3
RK
2789 }
2790 break;
2791
1a6ec070
RK
2792 case NE:
2793 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2794 is known to be on, this can be converted into a NEG of a shift. */
2795 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2796 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4eb2cb10 2797 && 1 <= (pos = exact_log2
1a6ec070
RK
2798 (nonzero_bits (XEXP (SET_SRC (x), 0),
2799 GET_MODE (XEXP (SET_SRC (x), 0))))))
2800 {
2801 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2802
2803 SUBST (SET_SRC (x),
2804 gen_rtx_combine (NEG, mode,
2805 gen_rtx_combine (LSHIFTRT, mode,
2806 XEXP (SET_SRC (x), 0),
4eb2cb10 2807 GEN_INT (pos))));
1a6ec070
RK
2808
2809 split = find_split_point (&SET_SRC (x), insn);
2810 if (split && split != &SET_SRC (x))
2811 return split;
2812 }
2813 break;
2814
230d793d
RS
2815 case SIGN_EXTEND:
2816 inner = XEXP (SET_SRC (x), 0);
101c1a3d
JL
2817
2818 /* We can't optimize if either mode is a partial integer
2819 mode as we don't know how many bits are significant
2820 in those modes. */
2821 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2822 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2823 break;
2824
230d793d
RS
2825 pos = 0;
2826 len = GET_MODE_BITSIZE (GET_MODE (inner));
2827 unsignedp = 0;
2828 break;
2829
2830 case SIGN_EXTRACT:
2831 case ZERO_EXTRACT:
2832 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2833 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2834 {
2835 inner = XEXP (SET_SRC (x), 0);
2836 len = INTVAL (XEXP (SET_SRC (x), 1));
2837 pos = INTVAL (XEXP (SET_SRC (x), 2));
2838
f76b9db2
ILT
2839 if (BITS_BIG_ENDIAN)
2840 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
230d793d
RS
2841 unsignedp = (code == ZERO_EXTRACT);
2842 }
2843 break;
e9a25f70
JL
2844
2845 default:
2846 break;
230d793d
RS
2847 }
2848
2849 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2850 {
2851 enum machine_mode mode = GET_MODE (SET_SRC (x));
2852
d0ab8cd3
RK
2853 /* For unsigned, we have a choice of a shift followed by an
2854 AND or two shifts. Use two shifts for field sizes where the
2855 constant might be too large. We assume here that we can
2856 always at least get 8-bit constants in an AND insn, which is
2857 true for every current RISC. */
2858
2859 if (unsignedp && len <= 8)
230d793d
RS
2860 {
2861 SUBST (SET_SRC (x),
2862 gen_rtx_combine
2863 (AND, mode,
2864 gen_rtx_combine (LSHIFTRT, mode,
2865 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH
2866 GEN_INT (pos)),
2867 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
230d793d 2868
d0ab8cd3 2869 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS
2870 if (split && split != &SET_SRC (x))
2871 return split;
2872 }
2873 else
2874 {
2875 SUBST (SET_SRC (x),
2876 gen_rtx_combine
d0ab8cd3 2877 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
230d793d
RS
2878 gen_rtx_combine (ASHIFT, mode,
2879 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH
2880 GEN_INT (GET_MODE_BITSIZE (mode)
2881 - len - pos)),
2882 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
230d793d 2883
d0ab8cd3 2884 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS
2885 if (split && split != &SET_SRC (x))
2886 return split;
2887 }
2888 }
2889
2890 /* See if this is a simple operation with a constant as the second
2891 operand. It might be that this constant is out of range and hence
2892 could be used as a split point. */
2893 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2894 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2895 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2896 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2897 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2898 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2899 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2900 == 'o'))))
2901 return &XEXP (SET_SRC (x), 1);
2902
2903 /* Finally, see if this is a simple operation with its first operand
2904 not in a register. The operation might require this operand in a
2905 register, so return it as a split point. We can always do this
2906 because if the first operand were another operation, we would have
2907 already found it as a split point. */
2908 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2909 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2910 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2911 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2912 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2913 return &XEXP (SET_SRC (x), 0);
2914
2915 return 0;
2916
2917 case AND:
2918 case IOR:
2919 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2920 it is better to write this as (not (ior A B)) so we can split it.
2921 Similarly for IOR. */
2922 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2923 {
2924 SUBST (*loc,
2925 gen_rtx_combine (NOT, GET_MODE (x),
2926 gen_rtx_combine (code == IOR ? AND : IOR,
2927 GET_MODE (x),
2928 XEXP (XEXP (x, 0), 0),
2929 XEXP (XEXP (x, 1), 0))));
d0ab8cd3 2930 return find_split_point (loc, insn);
230d793d
RS
2931 }
2932
2933 /* Many RISC machines have a large set of logical insns. If the
2934 second operand is a NOT, put it first so we will try to split the
2935 other operand first. */
2936 if (GET_CODE (XEXP (x, 1)) == NOT)
2937 {
2938 rtx tem = XEXP (x, 0);
2939 SUBST (XEXP (x, 0), XEXP (x, 1));
2940 SUBST (XEXP (x, 1), tem);
2941 }
2942 break;
e9a25f70
JL
2943
2944 default:
2945 break;
230d793d
RS
2946 }
2947
2948 /* Otherwise, select our actions depending on our rtx class. */
2949 switch (GET_RTX_CLASS (code))
2950 {
2951 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2952 case '3':
d0ab8cd3 2953 split = find_split_point (&XEXP (x, 2), insn);
230d793d
RS
2954 if (split)
2955 return split;
0f41302f 2956 /* ... fall through ... */
230d793d
RS
2957 case '2':
2958 case 'c':
2959 case '<':
d0ab8cd3 2960 split = find_split_point (&XEXP (x, 1), insn);
230d793d
RS
2961 if (split)
2962 return split;
0f41302f 2963 /* ... fall through ... */
230d793d
RS
2964 case '1':
2965 /* Some machines have (and (shift ...) ...) insns. If X is not
2966 an AND, but XEXP (X, 0) is, use it as our split point. */
2967 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2968 return &XEXP (x, 0);
2969
d0ab8cd3 2970 split = find_split_point (&XEXP (x, 0), insn);
230d793d
RS
2971 if (split)
2972 return split;
2973 return loc;
2974 }
2975
2976 /* Otherwise, we don't have a split point. */
2977 return 0;
2978}
2979\f
2980/* Throughout X, replace FROM with TO, and return the result.
2981 The result is TO if X is FROM;
2982 otherwise the result is X, but its contents may have been modified.
2983 If they were modified, a record was made in undobuf so that
2984 undo_all will (among other things) return X to its original state.
2985
2986 If the number of changes necessary is too much to record to undo,
2987 the excess changes are not made, so the result is invalid.
2988 The changes already made can still be undone.
2989 undobuf.num_undo is incremented for such changes, so by testing that
2990 the caller can tell whether the result is valid.
2991
2992 `n_occurrences' is incremented each time FROM is replaced.
2993
2994 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2995
5089e22e 2996 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
230d793d
RS
2997 by copying if `n_occurrences' is non-zero. */
2998
2999static rtx
3000subst (x, from, to, in_dest, unique_copy)
3001 register rtx x, from, to;
3002 int in_dest;
3003 int unique_copy;
3004{
f24ad0e4 3005 register enum rtx_code code = GET_CODE (x);
230d793d 3006 enum machine_mode op0_mode = VOIDmode;
8079805d
RK
3007 register char *fmt;
3008 register int len, i;
3009 rtx new;
230d793d
RS
3010
3011/* Two expressions are equal if they are identical copies of a shared
3012 RTX or if they are both registers with the same register number
3013 and mode. */
3014
3015#define COMBINE_RTX_EQUAL_P(X,Y) \
3016 ((X) == (Y) \
3017 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3018 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3019
3020 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3021 {
3022 n_occurrences++;
3023 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3024 }
3025
3026 /* If X and FROM are the same register but different modes, they will
3027 not have been seen as equal above. However, flow.c will make a
3028 LOG_LINKS entry for that case. If we do nothing, we will try to
3029 rerecognize our original insn and, when it succeeds, we will
3030 delete the feeding insn, which is incorrect.
3031
3032 So force this insn not to match in this (rare) case. */
3033 if (! in_dest && code == REG && GET_CODE (from) == REG
3034 && REGNO (x) == REGNO (from))
38a448ca 3035 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS
3036
3037 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3038 of which may contain things that can be combined. */
3039 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3040 return x;
3041
3042 /* It is possible to have a subexpression appear twice in the insn.
3043 Suppose that FROM is a register that appears within TO.
3044 Then, after that subexpression has been scanned once by `subst',
3045 the second time it is scanned, TO may be found. If we were
3046 to scan TO here, we would find FROM within it and create a
3047 self-referent rtl structure which is completely wrong. */
3048 if (COMBINE_RTX_EQUAL_P (x, to))
3049 return to;
3050
4f4b3679
RH
3051 /* Parallel asm_operands need special attention because all of the
3052 inputs are shared across the arms. Furthermore, unsharing the
3053 rtl results in recognition failures. Failure to handle this case
3054 specially can result in circular rtl.
3055
3056 Solve this by doing a normal pass across the first entry of the
3057 parallel, and only processing the SET_DESTs of the subsequent
3058 entries. Ug. */
3059
3060 if (code == PARALLEL
3061 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3062 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
230d793d 3063 {
4f4b3679
RH
3064 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3065
3066 /* If this substitution failed, this whole thing fails. */
3067 if (GET_CODE (new) == CLOBBER
3068 && XEXP (new, 0) == const0_rtx)
3069 return new;
3070
3071 SUBST (XVECEXP (x, 0, 0), new);
3072
3073 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
230d793d 3074 {
4f4b3679
RH
3075 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3076
3077 if (GET_CODE (dest) != REG
3078 && GET_CODE (dest) != CC0
3079 && GET_CODE (dest) != PC)
230d793d 3080 {
4f4b3679 3081 new = subst (dest, from, to, 0, unique_copy);
230d793d 3082
4f4b3679
RH
3083 /* If this substitution failed, this whole thing fails. */
3084 if (GET_CODE (new) == CLOBBER
3085 && XEXP (new, 0) == const0_rtx)
3086 return new;
230d793d 3087
4f4b3679 3088 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
230d793d
RS
3089 }
3090 }
4f4b3679
RH
3091 }
3092 else
3093 {
3094 len = GET_RTX_LENGTH (code);
3095 fmt = GET_RTX_FORMAT (code);
3096
3097 /* We don't need to process a SET_DEST that is a register, CC0,
3098 or PC, so set up to skip this common case. All other cases
3099 where we want to suppress replacing something inside a
3100 SET_SRC are handled via the IN_DEST operand. */
3101 if (code == SET
3102 && (GET_CODE (SET_DEST (x)) == REG
3103 || GET_CODE (SET_DEST (x)) == CC0
3104 || GET_CODE (SET_DEST (x)) == PC))
3105 fmt = "ie";
3106
3107 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3108 constant. */
3109 if (fmt[0] == 'e')
3110 op0_mode = GET_MODE (XEXP (x, 0));
3111
3112 for (i = 0; i < len; i++)
230d793d 3113 {
4f4b3679 3114 if (fmt[i] == 'E')
230d793d 3115 {
4f4b3679
RH
3116 register int j;
3117 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3118 {
3119 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3120 {
3121 new = (unique_copy && n_occurrences
3122 ? copy_rtx (to) : to);
3123 n_occurrences++;
3124 }
3125 else
3126 {
3127 new = subst (XVECEXP (x, i, j), from, to, 0,
3128 unique_copy);
3129
3130 /* If this substitution failed, this whole thing
3131 fails. */
3132 if (GET_CODE (new) == CLOBBER
3133 && XEXP (new, 0) == const0_rtx)
3134 return new;
3135 }
3136
3137 SUBST (XVECEXP (x, i, j), new);
3138 }
3139 }
3140 else if (fmt[i] == 'e')
3141 {
3142 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3143 {
3144 /* In general, don't install a subreg involving two
3145 modes not tieable. It can worsen register
3146 allocation, and can even make invalid reload
3147 insns, since the reg inside may need to be copied
3148 from in the outside mode, and that may be invalid
3149 if it is an fp reg copied in integer mode.
3150
3151 We allow two exceptions to this: It is valid if
3152 it is inside another SUBREG and the mode of that
3153 SUBREG and the mode of the inside of TO is
3154 tieable and it is valid if X is a SET that copies
3155 FROM to CC0. */
3156
3157 if (GET_CODE (to) == SUBREG
3158 && ! MODES_TIEABLE_P (GET_MODE (to),
3159 GET_MODE (SUBREG_REG (to)))
3160 && ! (code == SUBREG
3161 && MODES_TIEABLE_P (GET_MODE (x),
3162 GET_MODE (SUBREG_REG (to))))
42301240 3163#ifdef HAVE_cc0
4f4b3679 3164 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
42301240 3165#endif
4f4b3679
RH
3166 )
3167 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
42301240 3168
4f4b3679
RH
3169 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3170 n_occurrences++;
3171 }
3172 else
3173 /* If we are in a SET_DEST, suppress most cases unless we
3174 have gone inside a MEM, in which case we want to
3175 simplify the address. We assume here that things that
3176 are actually part of the destination have their inner
3177 parts in the first expression. This is true for SUBREG,
3178 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3179 things aside from REG and MEM that should appear in a
3180 SET_DEST. */
3181 new = subst (XEXP (x, i), from, to,
3182 (((in_dest
3183 && (code == SUBREG || code == STRICT_LOW_PART
3184 || code == ZERO_EXTRACT))
3185 || code == SET)
3186 && i == 0), unique_copy);
3187
3188 /* If we found that we will have to reject this combination,
3189 indicate that by returning the CLOBBER ourselves, rather than
3190 an expression containing it. This will speed things up as
3191 well as prevent accidents where two CLOBBERs are considered
3192 to be equal, thus producing an incorrect simplification. */
3193
3194 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3195 return new;
3196
3197 SUBST (XEXP (x, i), new);
230d793d 3198 }
230d793d
RS
3199 }
3200 }
3201
8079805d
RK
3202 /* Try to simplify X. If the simplification changed the code, it is likely
3203 that further simplification will help, so loop, but limit the number
3204 of repetitions that will be performed. */
3205
3206 for (i = 0; i < 4; i++)
3207 {
3208 /* If X is sufficiently simple, don't bother trying to do anything
3209 with it. */
3210 if (code != CONST_INT && code != REG && code != CLOBBER)
3211 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
d0ab8cd3 3212
8079805d
RK
3213 if (GET_CODE (x) == code)
3214 break;
d0ab8cd3 3215
8079805d 3216 code = GET_CODE (x);
eeb43d32 3217
8079805d
RK
3218 /* We no longer know the original mode of operand 0 since we
3219 have changed the form of X) */
3220 op0_mode = VOIDmode;
3221 }
eeb43d32 3222
8079805d
RK
3223 return x;
3224}
3225\f
3226/* Simplify X, a piece of RTL. We just operate on the expression at the
3227 outer level; call `subst' to simplify recursively. Return the new
3228 expression.
3229
3230 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3231 will be the iteration even if an expression with a code different from
3232 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
eeb43d32 3233
8079805d
RK
3234static rtx
3235simplify_rtx (x, op0_mode, last, in_dest)
3236 rtx x;
3237 enum machine_mode op0_mode;
3238 int last;
3239 int in_dest;
3240{
3241 enum rtx_code code = GET_CODE (x);
3242 enum machine_mode mode = GET_MODE (x);
3243 rtx temp;
3244 int i;
d0ab8cd3 3245
230d793d
RS
3246 /* If this is a commutative operation, put a constant last and a complex
3247 expression first. We don't need to do this for comparisons here. */
3248 if (GET_RTX_CLASS (code) == 'c'
3249 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3250 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3251 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3252 || (GET_CODE (XEXP (x, 0)) == SUBREG
3253 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3254 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3255 {
3256 temp = XEXP (x, 0);
3257 SUBST (XEXP (x, 0), XEXP (x, 1));
3258 SUBST (XEXP (x, 1), temp);
3259 }
3260
22609cbf
RK
3261 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3262 sign extension of a PLUS with a constant, reverse the order of the sign
3263 extension and the addition. Note that this not the same as the original
3264 code, but overflow is undefined for signed values. Also note that the
3265 PLUS will have been partially moved "inside" the sign-extension, so that
3266 the first operand of X will really look like:
3267 (ashiftrt (plus (ashift A C4) C5) C4).
3268 We convert this to
3269 (plus (ashiftrt (ashift A C4) C2) C4)
3270 and replace the first operand of X with that expression. Later parts
3271 of this function may simplify the expression further.
3272
3273 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3274 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3275 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3276
3277 We do this to simplify address expressions. */
3278
3279 if ((code == PLUS || code == MINUS || code == MULT)
3280 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3281 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3282 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3283 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3284 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3285 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3286 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3287 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3288 XEXP (XEXP (XEXP (x, 0), 0), 1),
3289 XEXP (XEXP (x, 0), 1))) != 0)
3290 {
3291 rtx new
3292 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3293 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3294 INTVAL (XEXP (XEXP (x, 0), 1)));
3295
3296 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3297 INTVAL (XEXP (XEXP (x, 0), 1)));
3298
3299 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3300 }
3301
d0ab8cd3
RK
3302 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3303 applying it to the arms of the IF_THEN_ELSE. This often simplifies
abe6e52f
RK
3304 things. Check for cases where both arms are testing the same
3305 condition.
3306
3307 Don't do anything if all operands are very simple. */
3308
3309 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3310 || GET_RTX_CLASS (code) == '<')
3311 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3312 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3313 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3314 == 'o')))
3315 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3316 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3317 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3318 == 'o')))))
3319 || (GET_RTX_CLASS (code) == '1'
3320 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3321 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3322 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3323 == 'o'))))))
d0ab8cd3 3324 {
abe6e52f
RK
3325 rtx cond, true, false;
3326
3327 cond = if_then_else_cond (x, &true, &false);
0802d516
RK
3328 if (cond != 0
3329 /* If everything is a comparison, what we have is highly unlikely
3330 to be simpler, so don't use it. */
3331 && ! (GET_RTX_CLASS (code) == '<'
3332 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3333 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
abe6e52f
RK
3334 {
3335 rtx cop1 = const0_rtx;
3336 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3337
15448afc
RK
3338 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3339 return x;
3340
9210df58
RK
3341 /* Simplify the alternative arms; this may collapse the true and
3342 false arms to store-flag values. */
3343 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3344 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3345
3346 /* Restarting if we generate a store-flag expression will cause
3347 us to loop. Just drop through in this case. */
3348
abe6e52f
RK
3349 /* If the result values are STORE_FLAG_VALUE and zero, we can
3350 just make the comparison operation. */
3351 if (true == const_true_rtx && false == const0_rtx)
3352 x = gen_binary (cond_code, mode, cond, cop1);
3353 else if (true == const0_rtx && false == const_true_rtx)
3354 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3355
3356 /* Likewise, we can make the negate of a comparison operation
3357 if the result values are - STORE_FLAG_VALUE and zero. */
3358 else if (GET_CODE (true) == CONST_INT
3359 && INTVAL (true) == - STORE_FLAG_VALUE
3360 && false == const0_rtx)
0c1c8ea6 3361 x = gen_unary (NEG, mode, mode,
abe6e52f
RK
3362 gen_binary (cond_code, mode, cond, cop1));
3363 else if (GET_CODE (false) == CONST_INT
3364 && INTVAL (false) == - STORE_FLAG_VALUE
3365 && true == const0_rtx)
0c1c8ea6 3366 x = gen_unary (NEG, mode, mode,
abe6e52f
RK
3367 gen_binary (reverse_condition (cond_code),
3368 mode, cond, cop1));
3369 else
38a448ca
RH
3370 return gen_rtx_IF_THEN_ELSE (mode,
3371 gen_binary (cond_code, VOIDmode,
3372 cond, cop1),
3373 true, false);
5109d49f 3374
9210df58
RK
3375 code = GET_CODE (x);
3376 op0_mode = VOIDmode;
abe6e52f 3377 }
d0ab8cd3
RK
3378 }
3379
230d793d
RS
3380 /* Try to fold this expression in case we have constants that weren't
3381 present before. */
3382 temp = 0;
3383 switch (GET_RTX_CLASS (code))
3384 {
3385 case '1':
3386 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3387 break;
3388 case '<':
3389 temp = simplify_relational_operation (code, op0_mode,
3390 XEXP (x, 0), XEXP (x, 1));
77fa0940
RK
3391#ifdef FLOAT_STORE_FLAG_VALUE
3392 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3393 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3394 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3395#endif
230d793d
RS
3396 break;
3397 case 'c':
3398 case '2':
3399 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3400 break;
3401 case 'b':
3402 case '3':
3403 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3404 XEXP (x, 1), XEXP (x, 2));
3405 break;
3406 }
3407
3408 if (temp)
d0ab8cd3 3409 x = temp, code = GET_CODE (temp);
230d793d 3410
230d793d 3411 /* First see if we can apply the inverse distributive law. */
224eeff2
RK
3412 if (code == PLUS || code == MINUS
3413 || code == AND || code == IOR || code == XOR)
230d793d
RS
3414 {
3415 x = apply_distributive_law (x);
3416 code = GET_CODE (x);
3417 }
3418
3419 /* If CODE is an associative operation not otherwise handled, see if we
3420 can associate some operands. This can win if they are constants or
3421 if they are logically related (i.e. (a & b) & a. */
3422 if ((code == PLUS || code == MINUS
3423 || code == MULT || code == AND || code == IOR || code == XOR
3424 || code == DIV || code == UDIV
3425 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3ad2180a 3426 && INTEGRAL_MODE_P (mode))
230d793d
RS
3427 {
3428 if (GET_CODE (XEXP (x, 0)) == code)
3429 {
3430 rtx other = XEXP (XEXP (x, 0), 0);
3431 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3432 rtx inner_op1 = XEXP (x, 1);
3433 rtx inner;
3434
3435 /* Make sure we pass the constant operand if any as the second
3436 one if this is a commutative operation. */
3437 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3438 {
3439 rtx tem = inner_op0;
3440 inner_op0 = inner_op1;
3441 inner_op1 = tem;
3442 }
3443 inner = simplify_binary_operation (code == MINUS ? PLUS
3444 : code == DIV ? MULT
3445 : code == UDIV ? MULT
3446 : code,
3447 mode, inner_op0, inner_op1);
3448
3449 /* For commutative operations, try the other pair if that one
3450 didn't simplify. */
3451 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3452 {
3453 other = XEXP (XEXP (x, 0), 1);
3454 inner = simplify_binary_operation (code, mode,
3455 XEXP (XEXP (x, 0), 0),
3456 XEXP (x, 1));
3457 }
3458
3459 if (inner)
8079805d 3460 return gen_binary (code, mode, other, inner);
230d793d
RS
3461 }
3462 }
3463
3464 /* A little bit of algebraic simplification here. */
3465 switch (code)
3466 {
3467 case MEM:
3468 /* Ensure that our address has any ASHIFTs converted to MULT in case
3469 address-recognizing predicates are called later. */
3470 temp = make_compound_operation (XEXP (x, 0), MEM);
3471 SUBST (XEXP (x, 0), temp);
3472 break;
3473
3474 case SUBREG:
3475 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3476 is paradoxical. If we can't do that safely, then it becomes
3477 something nonsensical so that this combination won't take place. */
3478
3479 if (GET_CODE (SUBREG_REG (x)) == MEM
3480 && (GET_MODE_SIZE (mode)
3481 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3482 {
3483 rtx inner = SUBREG_REG (x);
3484 int endian_offset = 0;
3485 /* Don't change the mode of the MEM
3486 if that would change the meaning of the address. */
3487 if (MEM_VOLATILE_P (SUBREG_REG (x))
3488 || mode_dependent_address_p (XEXP (inner, 0)))
38a448ca 3489 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d 3490
f76b9db2
ILT
3491 if (BYTES_BIG_ENDIAN)
3492 {
3493 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3494 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3495 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3496 endian_offset -= (UNITS_PER_WORD
3497 - GET_MODE_SIZE (GET_MODE (inner)));
3498 }
230d793d
RS
3499 /* Note if the plus_constant doesn't make a valid address
3500 then this combination won't be accepted. */
38a448ca
RH
3501 x = gen_rtx_MEM (mode,
3502 plus_constant (XEXP (inner, 0),
3503 (SUBREG_WORD (x) * UNITS_PER_WORD
3504 + endian_offset)));
230d793d 3505 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
c6df88cb 3506 MEM_COPY_ATTRIBUTES (x, inner);
230d793d
RS
3507 return x;
3508 }
3509
3510 /* If we are in a SET_DEST, these other cases can't apply. */
3511 if (in_dest)
3512 return x;
3513
3514 /* Changing mode twice with SUBREG => just change it once,
3515 or not at all if changing back to starting mode. */
3516 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3517 {
3518 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3519 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3520 return SUBREG_REG (SUBREG_REG (x));
3521
3522 SUBST_INT (SUBREG_WORD (x),
3523 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3524 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3525 }
3526
3527 /* SUBREG of a hard register => just change the register number
3528 and/or mode. If the hard register is not valid in that mode,
26ecfc76
RK
3529 suppress this combination. If the hard register is the stack,
3530 frame, or argument pointer, leave this as a SUBREG. */
230d793d
RS
3531
3532 if (GET_CODE (SUBREG_REG (x)) == REG
26ecfc76
RK
3533 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3534 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
6d7096b0
DE
3535#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3536 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3537#endif
26ecfc76
RK
3538#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3539 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3540#endif
3541 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
230d793d
RS
3542 {
3543 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3544 mode))
38a448ca
RH
3545 return gen_rtx_REG (mode,
3546 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
230d793d 3547 else
38a448ca 3548 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d
RS
3549 }
3550
3551 /* For a constant, try to pick up the part we want. Handle a full
a4bde0b1
RK
3552 word and low-order part. Only do this if we are narrowing
3553 the constant; if it is being widened, we have no idea what
3554 the extra bits will have been set to. */
230d793d
RS
3555
3556 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3557 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3c99d5ff 3558 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
230d793d
RS
3559 && GET_MODE_CLASS (mode) == MODE_INT)
3560 {
3561 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
5f4f0e22 3562 0, op0_mode);
230d793d
RS
3563 if (temp)
3564 return temp;
3565 }
3566
19808e22
RS
3567 /* If we want a subreg of a constant, at offset 0,
3568 take the low bits. On a little-endian machine, that's
3569 always valid. On a big-endian machine, it's valid
3c99d5ff 3570 only if the constant's mode fits in one word. Note that we
61b1bece 3571 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3c99d5ff
RK
3572 if (CONSTANT_P (SUBREG_REG (x))
3573 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3574 || ! WORDS_BIG_ENDIAN)
3575 ? SUBREG_WORD (x) == 0
3576 : (SUBREG_WORD (x)
3577 == ((GET_MODE_SIZE (op0_mode)
3578 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3579 / UNITS_PER_WORD)))
f82da7d2 3580 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
f76b9db2
ILT
3581 && (! WORDS_BIG_ENDIAN
3582 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
230d793d
RS
3583 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3584
b65c1b5b
RK
3585 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3586 since we are saying that the high bits don't matter. */
3587 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3588 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3589 return SUBREG_REG (x);
3590
87e3e0c1
RK
3591 /* Note that we cannot do any narrowing for non-constants since
3592 we might have been counting on using the fact that some bits were
3593 zero. We now do this in the SET. */
3594
230d793d
RS
3595 break;
3596
3597 case NOT:
3598 /* (not (plus X -1)) can become (neg X). */
3599 if (GET_CODE (XEXP (x, 0)) == PLUS
3600 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
8079805d 3601 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS
3602
3603 /* Similarly, (not (neg X)) is (plus X -1). */
3604 if (GET_CODE (XEXP (x, 0)) == NEG)
8079805d
RK
3605 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3606 constm1_rtx);
230d793d 3607
d0ab8cd3
RK
3608 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3609 if (GET_CODE (XEXP (x, 0)) == XOR
3610 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3611 && (temp = simplify_unary_operation (NOT, mode,
3612 XEXP (XEXP (x, 0), 1),
3613 mode)) != 0)
787745f5 3614 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
d0ab8cd3 3615
230d793d
RS
3616 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3617 other than 1, but that is not valid. We could do a similar
3618 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3619 but this doesn't seem common enough to bother with. */
3620 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3621 && XEXP (XEXP (x, 0), 0) == const1_rtx)
38a448ca
RH
3622 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3623 XEXP (XEXP (x, 0), 1));
230d793d
RS
3624
3625 if (GET_CODE (XEXP (x, 0)) == SUBREG
3626 && subreg_lowpart_p (XEXP (x, 0))
3627 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3628 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3629 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3630 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3631 {
3632 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3633
38a448ca
RH
3634 x = gen_rtx_ROTATE (inner_mode,
3635 gen_unary (NOT, inner_mode, inner_mode,
3636 const1_rtx),
3637 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
8079805d 3638 return gen_lowpart_for_combine (mode, x);
230d793d
RS
3639 }
3640
0802d516
RK
3641 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3642 reversing the comparison code if valid. */
3643 if (STORE_FLAG_VALUE == -1
3644 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
230d793d
RS
3645 && reversible_comparison_p (XEXP (x, 0)))
3646 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3647 mode, XEXP (XEXP (x, 0), 0),
3648 XEXP (XEXP (x, 0), 1));
500c518b
RK
3649
3650 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
0802d516
RK
3651 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3652 perform the above simplification. */
500c518b 3653
0802d516
RK
3654 if (STORE_FLAG_VALUE == -1
3655 && XEXP (x, 1) == const1_rtx
500c518b
RK
3656 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3657 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3658 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3659 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
230d793d
RS
3660
3661 /* Apply De Morgan's laws to reduce number of patterns for machines
3662 with negating logical insns (and-not, nand, etc.). If result has
3663 only one NOT, put it first, since that is how the patterns are
3664 coded. */
3665
3666 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3667 {
3668 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3669
3670 if (GET_CODE (in1) == NOT)
3671 in1 = XEXP (in1, 0);
3672 else
3673 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3674
3675 if (GET_CODE (in2) == NOT)
3676 in2 = XEXP (in2, 0);
3677 else if (GET_CODE (in2) == CONST_INT
5f4f0e22
CH
3678 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3679 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
230d793d
RS
3680 else
3681 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3682
3683 if (GET_CODE (in2) == NOT)
3684 {
3685 rtx tem = in2;
3686 in2 = in1; in1 = tem;
3687 }
3688
8079805d
RK
3689 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3690 mode, in1, in2);
230d793d
RS
3691 }
3692 break;
3693
3694 case NEG:
3695 /* (neg (plus X 1)) can become (not X). */
3696 if (GET_CODE (XEXP (x, 0)) == PLUS
3697 && XEXP (XEXP (x, 0), 1) == const1_rtx)
8079805d 3698 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS
3699
3700 /* Similarly, (neg (not X)) is (plus X 1). */
3701 if (GET_CODE (XEXP (x, 0)) == NOT)
8079805d 3702 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
230d793d 3703
230d793d
RS
3704 /* (neg (minus X Y)) can become (minus Y X). */
3705 if (GET_CODE (XEXP (x, 0)) == MINUS
3ad2180a 3706 && (! FLOAT_MODE_P (mode)
0f41302f 3707 /* x-y != -(y-x) with IEEE floating point. */
7e2a0d8e
RK
3708 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3709 || flag_fast_math))
8079805d
RK
3710 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3711 XEXP (XEXP (x, 0), 0));
230d793d 3712
0f41302f 3713 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
d0ab8cd3 3714 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
951553af 3715 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
8079805d 3716 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
d0ab8cd3 3717
230d793d
RS
3718 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3719 if we can then eliminate the NEG (e.g.,
3720 if the operand is a constant). */
3721
3722 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3723 {
3724 temp = simplify_unary_operation (NEG, mode,
3725 XEXP (XEXP (x, 0), 0), mode);
3726 if (temp)
3727 {
3728 SUBST (XEXP (XEXP (x, 0), 0), temp);
3729 return XEXP (x, 0);
3730 }
3731 }
3732
3733 temp = expand_compound_operation (XEXP (x, 0));
3734
3735 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3736 replaced by (lshiftrt X C). This will convert
3737 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3738
3739 if (GET_CODE (temp) == ASHIFTRT
3740 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3741 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
8079805d
RK
3742 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3743 INTVAL (XEXP (temp, 1)));
230d793d 3744
951553af 3745 /* If X has only a single bit that might be nonzero, say, bit I, convert
230d793d
RS
3746 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3747 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3748 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3749 or a SUBREG of one since we'd be making the expression more
3750 complex if it was just a register. */
3751
3752 if (GET_CODE (temp) != REG
3753 && ! (GET_CODE (temp) == SUBREG
3754 && GET_CODE (SUBREG_REG (temp)) == REG)
951553af 3755 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
230d793d
RS
3756 {
3757 rtx temp1 = simplify_shift_const
5f4f0e22
CH
3758 (NULL_RTX, ASHIFTRT, mode,
3759 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
230d793d
RS
3760 GET_MODE_BITSIZE (mode) - 1 - i),
3761 GET_MODE_BITSIZE (mode) - 1 - i);
3762
3763 /* If all we did was surround TEMP with the two shifts, we
3764 haven't improved anything, so don't use it. Otherwise,
3765 we are better off with TEMP1. */
3766 if (GET_CODE (temp1) != ASHIFTRT
3767 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3768 || XEXP (XEXP (temp1, 0), 0) != temp)
8079805d 3769 return temp1;
230d793d
RS
3770 }
3771 break;
3772
2ca9ae17 3773 case TRUNCATE:
e30fb98f
JL
3774 /* We can't handle truncation to a partial integer mode here
3775 because we don't know the real bitsize of the partial
3776 integer mode. */
3777 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3778 break;
3779
80608e27
JL
3780 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3781 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3782 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
2ca9ae17
JW
3783 SUBST (XEXP (x, 0),
3784 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3785 GET_MODE_MASK (mode), NULL_RTX, 0));
0f13a422
ILT
3786
3787 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3788 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3789 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3790 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3791 return XEXP (XEXP (x, 0), 0);
3792
3793 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3794 (OP:SI foo:SI) if OP is NEG or ABS. */
3795 if ((GET_CODE (XEXP (x, 0)) == ABS
3796 || GET_CODE (XEXP (x, 0)) == NEG)
3797 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3798 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3799 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3800 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3801 XEXP (XEXP (XEXP (x, 0), 0), 0));
3802
3803 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3804 (truncate:SI x). */
3805 if (GET_CODE (XEXP (x, 0)) == SUBREG
3806 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3807 && subreg_lowpart_p (XEXP (x, 0)))
3808 return SUBREG_REG (XEXP (x, 0));
3809
3810 /* If we know that the value is already truncated, we can
6a992214
JL
3811 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3812 nonzero for the corresponding modes. */
3813 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3814 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3815 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3816 >= GET_MODE_BITSIZE (mode) + 1)
0f13a422
ILT
3817 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3818
3819 /* A truncate of a comparison can be replaced with a subreg if
3820 STORE_FLAG_VALUE permits. This is like the previous test,
3821 but it works even if the comparison is done in a mode larger
3822 than HOST_BITS_PER_WIDE_INT. */
3823 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3824 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3825 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3826 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3827
3828 /* Similarly, a truncate of a register whose value is a
3829 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3830 permits. */
3831 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3832 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3833 && (temp = get_last_value (XEXP (x, 0)))
3834 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3835 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3836
2ca9ae17
JW
3837 break;
3838
230d793d
RS
3839 case FLOAT_TRUNCATE:
3840 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3841 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3842 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3843 return XEXP (XEXP (x, 0), 0);
4635f748
RK
3844
3845 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3846 (OP:SF foo:SF) if OP is NEG or ABS. */
3847 if ((GET_CODE (XEXP (x, 0)) == ABS
3848 || GET_CODE (XEXP (x, 0)) == NEG)
3849 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3850 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
0c1c8ea6
RK
3851 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3852 XEXP (XEXP (XEXP (x, 0), 0), 0));
1d12df72
RK
3853
3854 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3855 is (float_truncate:SF x). */
3856 if (GET_CODE (XEXP (x, 0)) == SUBREG
3857 && subreg_lowpart_p (XEXP (x, 0))
3858 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3859 return SUBREG_REG (XEXP (x, 0));
230d793d
RS
3860 break;
3861
3862#ifdef HAVE_cc0
3863 case COMPARE:
3864 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3865 using cc0, in which case we want to leave it as a COMPARE
3866 so we can distinguish it from a register-register-copy. */
3867 if (XEXP (x, 1) == const0_rtx)
3868 return XEXP (x, 0);
3869
3870 /* In IEEE floating point, x-0 is not the same as x. */
3871 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e
RK
3872 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3873 || flag_fast_math)
230d793d
RS
3874 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3875 return XEXP (x, 0);
3876 break;
3877#endif
3878
3879 case CONST:
3880 /* (const (const X)) can become (const X). Do it this way rather than
3881 returning the inner CONST since CONST can be shared with a
3882 REG_EQUAL note. */
3883 if (GET_CODE (XEXP (x, 0)) == CONST)
3884 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3885 break;
3886
3887#ifdef HAVE_lo_sum
3888 case LO_SUM:
3889 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3890 can add in an offset. find_split_point will split this address up
3891 again if it doesn't match. */
3892 if (GET_CODE (XEXP (x, 0)) == HIGH
3893 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3894 return XEXP (x, 1);
3895 break;
3896#endif
3897
3898 case PLUS:
3899 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3900 outermost. That's because that's the way indexed addresses are
3901 supposed to appear. This code used to check many more cases, but
3902 they are now checked elsewhere. */
3903 if (GET_CODE (XEXP (x, 0)) == PLUS
3904 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3905 return gen_binary (PLUS, mode,
3906 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3907 XEXP (x, 1)),
3908 XEXP (XEXP (x, 0), 1));
3909
3910 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3911 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3912 bit-field and can be replaced by either a sign_extend or a
3913 sign_extract. The `and' may be a zero_extend. */
3914 if (GET_CODE (XEXP (x, 0)) == XOR
3915 && GET_CODE (XEXP (x, 1)) == CONST_INT
3916 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3917 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3918 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5f4f0e22 3919 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
230d793d
RS
3920 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3921 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3922 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5f4f0e22 3923 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
230d793d
RS
3924 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3925 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3926 == i + 1))))
8079805d
RK
3927 return simplify_shift_const
3928 (NULL_RTX, ASHIFTRT, mode,
3929 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3930 XEXP (XEXP (XEXP (x, 0), 0), 0),
3931 GET_MODE_BITSIZE (mode) - (i + 1)),
3932 GET_MODE_BITSIZE (mode) - (i + 1));
230d793d 3933
bc0776c6
RK
3934 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3935 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3936 is 1. This produces better code than the alternative immediately
3937 below. */
3938 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3939 && reversible_comparison_p (XEXP (x, 0))
3940 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3941 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
8079805d 3942 return
0c1c8ea6 3943 gen_unary (NEG, mode, mode,
8079805d
RK
3944 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3945 mode, XEXP (XEXP (x, 0), 0),
3946 XEXP (XEXP (x, 0), 1)));
bc0776c6
RK
3947
3948 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
230d793d
RS
3949 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3950 the bitsize of the mode - 1. This allows simplification of
3951 "a = (b & 8) == 0;" */
3952 if (XEXP (x, 1) == constm1_rtx
3953 && GET_CODE (XEXP (x, 0)) != REG
3954 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3955 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
951553af 3956 && nonzero_bits (XEXP (x, 0), mode) == 1)
8079805d
RK
3957 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3958 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3959 gen_rtx_combine (XOR, mode,
3960 XEXP (x, 0), const1_rtx),
3961 GET_MODE_BITSIZE (mode) - 1),
3962 GET_MODE_BITSIZE (mode) - 1);
02f4ada4
RK
3963
3964 /* If we are adding two things that have no bits in common, convert
3965 the addition into an IOR. This will often be further simplified,
3966 for example in cases like ((a & 1) + (a & 2)), which can
3967 become a & 3. */
3968
ac49a949 3969 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
951553af
RK
3970 && (nonzero_bits (XEXP (x, 0), mode)
3971 & nonzero_bits (XEXP (x, 1), mode)) == 0)
8079805d 3972 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
230d793d
RS
3973 break;
3974
3975 case MINUS:
0802d516
RK
3976 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3977 by reversing the comparison code if valid. */
3978 if (STORE_FLAG_VALUE == 1
3979 && XEXP (x, 0) == const1_rtx
5109d49f
RK
3980 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3981 && reversible_comparison_p (XEXP (x, 1)))
3982 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3983 mode, XEXP (XEXP (x, 1), 0),
3984 XEXP (XEXP (x, 1), 1));
5109d49f 3985
230d793d
RS
3986 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3987 (and <foo> (const_int pow2-1)) */
3988 if (GET_CODE (XEXP (x, 1)) == AND
3989 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3990 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3991 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8079805d
RK
3992 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3993 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
7bef8680
RK
3994
3995 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3996 integers. */
3997 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
8079805d
RK
3998 return gen_binary (MINUS, mode,
3999 gen_binary (MINUS, mode, XEXP (x, 0),
4000 XEXP (XEXP (x, 1), 0)),
4001 XEXP (XEXP (x, 1), 1));
230d793d
RS
4002 break;
4003
4004 case MULT:
4005 /* If we have (mult (plus A B) C), apply the distributive law and then
4006 the inverse distributive law to see if things simplify. This
4007 occurs mostly in addresses, often when unrolling loops. */
4008
4009 if (GET_CODE (XEXP (x, 0)) == PLUS)
4010 {
4011 x = apply_distributive_law
4012 (gen_binary (PLUS, mode,
4013 gen_binary (MULT, mode,
4014 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4015 gen_binary (MULT, mode,
4016 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4017
4018 if (GET_CODE (x) != MULT)
8079805d 4019 return x;
230d793d 4020 }
230d793d
RS
4021 break;
4022
4023 case UDIV:
4024 /* If this is a divide by a power of two, treat it as a shift if
4025 its first operand is a shift. */
4026 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4027 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4028 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4029 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4030 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4031 || GET_CODE (XEXP (x, 0)) == ROTATE
4032 || GET_CODE (XEXP (x, 0)) == ROTATERT))
8079805d 4033 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
230d793d
RS
4034 break;
4035
4036 case EQ: case NE:
4037 case GT: case GTU: case GE: case GEU:
4038 case LT: case LTU: case LE: case LEU:
4039 /* If the first operand is a condition code, we can't do anything
4040 with it. */
4041 if (GET_CODE (XEXP (x, 0)) == COMPARE
4042 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4043#ifdef HAVE_cc0
4044 && XEXP (x, 0) != cc0_rtx
4045#endif
4046 ))
4047 {
4048 rtx op0 = XEXP (x, 0);
4049 rtx op1 = XEXP (x, 1);
4050 enum rtx_code new_code;
4051
4052 if (GET_CODE (op0) == COMPARE)
4053 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4054
4055 /* Simplify our comparison, if possible. */
4056 new_code = simplify_comparison (code, &op0, &op1);
4057
230d793d 4058 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
951553af 4059 if only the low-order bit is possibly nonzero in X (such as when
5109d49f
RK
4060 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4061 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4062 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4063 (plus X 1).
4064
4065 Remove any ZERO_EXTRACT we made when thinking this was a
4066 comparison. It may now be simpler to use, e.g., an AND. If a
4067 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4068 the call to make_compound_operation in the SET case. */
4069
0802d516
RK
4070 if (STORE_FLAG_VALUE == 1
4071 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4072 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
818b11b9
RK
4073 return gen_lowpart_for_combine (mode,
4074 expand_compound_operation (op0));
5109d49f 4075
0802d516
RK
4076 else if (STORE_FLAG_VALUE == 1
4077 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK
4078 && op1 == const0_rtx
4079 && (num_sign_bit_copies (op0, mode)
4080 == GET_MODE_BITSIZE (mode)))
4081 {
4082 op0 = expand_compound_operation (op0);
0c1c8ea6 4083 return gen_unary (NEG, mode, mode,
8079805d 4084 gen_lowpart_for_combine (mode, op0));
5109d49f
RK
4085 }
4086
0802d516
RK
4087 else if (STORE_FLAG_VALUE == 1
4088 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4089 && op1 == const0_rtx
5109d49f 4090 && nonzero_bits (op0, mode) == 1)
818b11b9
RK
4091 {
4092 op0 = expand_compound_operation (op0);
8079805d
RK
4093 return gen_binary (XOR, mode,
4094 gen_lowpart_for_combine (mode, op0),
4095 const1_rtx);
5109d49f 4096 }
818b11b9 4097
0802d516
RK
4098 else if (STORE_FLAG_VALUE == 1
4099 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK
4100 && op1 == const0_rtx
4101 && (num_sign_bit_copies (op0, mode)
4102 == GET_MODE_BITSIZE (mode)))
4103 {
4104 op0 = expand_compound_operation (op0);
8079805d 4105 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
818b11b9 4106 }
230d793d 4107
5109d49f
RK
4108 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4109 those above. */
0802d516
RK
4110 if (STORE_FLAG_VALUE == -1
4111 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4112 && op1 == const0_rtx
5109d49f
RK
4113 && (num_sign_bit_copies (op0, mode)
4114 == GET_MODE_BITSIZE (mode)))
4115 return gen_lowpart_for_combine (mode,
4116 expand_compound_operation (op0));
4117
0802d516
RK
4118 else if (STORE_FLAG_VALUE == -1
4119 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK
4120 && op1 == const0_rtx
4121 && nonzero_bits (op0, mode) == 1)
4122 {
4123 op0 = expand_compound_operation (op0);
0c1c8ea6 4124 return gen_unary (NEG, mode, mode,
8079805d 4125 gen_lowpart_for_combine (mode, op0));
5109d49f
RK
4126 }
4127
0802d516
RK
4128 else if (STORE_FLAG_VALUE == -1
4129 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK
4130 && op1 == const0_rtx
4131 && (num_sign_bit_copies (op0, mode)
4132 == GET_MODE_BITSIZE (mode)))
230d793d 4133 {
818b11b9 4134 op0 = expand_compound_operation (op0);
0c1c8ea6 4135 return gen_unary (NOT, mode, mode,
8079805d 4136 gen_lowpart_for_combine (mode, op0));
5109d49f
RK
4137 }
4138
4139 /* If X is 0/1, (eq X 0) is X-1. */
0802d516
RK
4140 else if (STORE_FLAG_VALUE == -1
4141 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK
4142 && op1 == const0_rtx
4143 && nonzero_bits (op0, mode) == 1)
4144 {
4145 op0 = expand_compound_operation (op0);
8079805d 4146 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
230d793d 4147 }
230d793d
RS
4148
4149 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
951553af
RK
4150 one bit that might be nonzero, we can convert (ne x 0) to
4151 (ashift x c) where C puts the bit in the sign bit. Remove any
4152 AND with STORE_FLAG_VALUE when we are done, since we are only
4153 going to test the sign bit. */
3f508eca 4154 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5f4f0e22 4155 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 4156 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 4157 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
230d793d
RS
4158 && op1 == const0_rtx
4159 && mode == GET_MODE (op0)
5109d49f 4160 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
230d793d 4161 {
818b11b9
RK
4162 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4163 expand_compound_operation (op0),
230d793d
RS
4164 GET_MODE_BITSIZE (mode) - 1 - i);
4165 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4166 return XEXP (x, 0);
4167 else
4168 return x;
4169 }
4170
4171 /* If the code changed, return a whole new comparison. */
4172 if (new_code != code)
4173 return gen_rtx_combine (new_code, mode, op0, op1);
4174
4175 /* Otherwise, keep this operation, but maybe change its operands.
4176 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4177 SUBST (XEXP (x, 0), op0);
4178 SUBST (XEXP (x, 1), op1);
4179 }
4180 break;
4181
4182 case IF_THEN_ELSE:
8079805d 4183 return simplify_if_then_else (x);
9210df58 4184
8079805d
RK
4185 case ZERO_EXTRACT:
4186 case SIGN_EXTRACT:
4187 case ZERO_EXTEND:
4188 case SIGN_EXTEND:
0f41302f 4189 /* If we are processing SET_DEST, we are done. */
8079805d
RK
4190 if (in_dest)
4191 return x;
d0ab8cd3 4192
8079805d 4193 return expand_compound_operation (x);
d0ab8cd3 4194
8079805d
RK
4195 case SET:
4196 return simplify_set (x);
1a26b032 4197
8079805d
RK
4198 case AND:
4199 case IOR:
4200 case XOR:
4201 return simplify_logical (x, last);
d0ab8cd3 4202
b472527b 4203 case ABS:
8079805d
RK
4204 /* (abs (neg <foo>)) -> (abs <foo>) */
4205 if (GET_CODE (XEXP (x, 0)) == NEG)
4206 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
1a26b032 4207
b472527b
JL
4208 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4209 do nothing. */
4210 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4211 break;
f40421ce 4212
8079805d
RK
4213 /* If operand is something known to be positive, ignore the ABS. */
4214 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4215 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4216 <= HOST_BITS_PER_WIDE_INT)
4217 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4218 & ((HOST_WIDE_INT) 1
4219 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4220 == 0)))
4221 return XEXP (x, 0);
1a26b032 4222
1a26b032 4223
8079805d
RK
4224 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4225 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4226 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
1a26b032 4227
8079805d 4228 break;
1a26b032 4229
8079805d
RK
4230 case FFS:
4231 /* (ffs (*_extend <X>)) = (ffs <X>) */
4232 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4233 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4234 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4235 break;
1a26b032 4236
8079805d
RK
4237 case FLOAT:
4238 /* (float (sign_extend <X>)) = (float <X>). */
4239 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4240 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4241 break;
1a26b032 4242
8079805d
RK
4243 case ASHIFT:
4244 case LSHIFTRT:
4245 case ASHIFTRT:
4246 case ROTATE:
4247 case ROTATERT:
4248 /* If this is a shift by a constant amount, simplify it. */
4249 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4250 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4251 INTVAL (XEXP (x, 1)));
4252
4253#ifdef SHIFT_COUNT_TRUNCATED
4254 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4255 SUBST (XEXP (x, 1),
4256 force_to_mode (XEXP (x, 1), GET_MODE (x),
4257 ((HOST_WIDE_INT) 1
4258 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4259 - 1,
4260 NULL_RTX, 0));
4261#endif
4262
4263 break;
e9a25f70
JL
4264
4265 default:
4266 break;
8079805d
RK
4267 }
4268
4269 return x;
4270}
4271\f
4272/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5109d49f 4273
8079805d
RK
4274static rtx
4275simplify_if_then_else (x)
4276 rtx x;
4277{
4278 enum machine_mode mode = GET_MODE (x);
4279 rtx cond = XEXP (x, 0);
4280 rtx true = XEXP (x, 1);
4281 rtx false = XEXP (x, 2);
4282 enum rtx_code true_code = GET_CODE (cond);
4283 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4284 rtx temp;
4285 int i;
4286
0f41302f 4287 /* Simplify storing of the truth value. */
8079805d
RK
4288 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4289 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4290
0f41302f 4291 /* Also when the truth value has to be reversed. */
8079805d
RK
4292 if (comparison_p && reversible_comparison_p (cond)
4293 && true == const0_rtx && false == const_true_rtx)
4294 return gen_binary (reverse_condition (true_code),
4295 mode, XEXP (cond, 0), XEXP (cond, 1));
4296
4297 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4298 in it is being compared against certain values. Get the true and false
4299 comparisons and see if that says anything about the value of each arm. */
4300
4301 if (comparison_p && reversible_comparison_p (cond)
4302 && GET_CODE (XEXP (cond, 0)) == REG)
4303 {
4304 HOST_WIDE_INT nzb;
4305 rtx from = XEXP (cond, 0);
4306 enum rtx_code false_code = reverse_condition (true_code);
4307 rtx true_val = XEXP (cond, 1);
4308 rtx false_val = true_val;
4309 int swapped = 0;
9210df58 4310
8079805d 4311 /* If FALSE_CODE is EQ, swap the codes and arms. */
5109d49f 4312
8079805d 4313 if (false_code == EQ)
1a26b032 4314 {
8079805d
RK
4315 swapped = 1, true_code = EQ, false_code = NE;
4316 temp = true, true = false, false = temp;
4317 }
5109d49f 4318
8079805d
RK
4319 /* If we are comparing against zero and the expression being tested has
4320 only a single bit that might be nonzero, that is its value when it is
4321 not equal to zero. Similarly if it is known to be -1 or 0. */
4322
4323 if (true_code == EQ && true_val == const0_rtx
4324 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4325 false_code = EQ, false_val = GEN_INT (nzb);
4326 else if (true_code == EQ && true_val == const0_rtx
4327 && (num_sign_bit_copies (from, GET_MODE (from))
4328 == GET_MODE_BITSIZE (GET_MODE (from))))
4329 false_code = EQ, false_val = constm1_rtx;
4330
4331 /* Now simplify an arm if we know the value of the register in the
4332 branch and it is used in the arm. Be careful due to the potential
4333 of locally-shared RTL. */
4334
4335 if (reg_mentioned_p (from, true))
4336 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4337 pc_rtx, pc_rtx, 0, 0);
4338 if (reg_mentioned_p (from, false))
4339 false = subst (known_cond (copy_rtx (false), false_code,
4340 from, false_val),
4341 pc_rtx, pc_rtx, 0, 0);
4342
4343 SUBST (XEXP (x, 1), swapped ? false : true);
4344 SUBST (XEXP (x, 2), swapped ? true : false);
4345
4346 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4347 }
5109d49f 4348
8079805d
RK
4349 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4350 reversed, do so to avoid needing two sets of patterns for
4351 subtract-and-branch insns. Similarly if we have a constant in the true
4352 arm, the false arm is the same as the first operand of the comparison, or
4353 the false arm is more complicated than the true arm. */
4354
4355 if (comparison_p && reversible_comparison_p (cond)
4356 && (true == pc_rtx
4357 || (CONSTANT_P (true)
4358 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4359 || true == const0_rtx
4360 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4361 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4362 || (GET_CODE (true) == SUBREG
4363 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4364 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4365 || reg_mentioned_p (true, false)
4366 || rtx_equal_p (false, XEXP (cond, 0))))
4367 {
4368 true_code = reverse_condition (true_code);
4369 SUBST (XEXP (x, 0),
4370 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4371 XEXP (cond, 1)));
5109d49f 4372
8079805d
RK
4373 SUBST (XEXP (x, 1), false);
4374 SUBST (XEXP (x, 2), true);
1a26b032 4375
8079805d 4376 temp = true, true = false, false = temp, cond = XEXP (x, 0);
bb821298 4377
0f41302f 4378 /* It is possible that the conditional has been simplified out. */
bb821298
RK
4379 true_code = GET_CODE (cond);
4380 comparison_p = GET_RTX_CLASS (true_code) == '<';
8079805d 4381 }
abe6e52f 4382
8079805d 4383 /* If the two arms are identical, we don't need the comparison. */
1a26b032 4384
8079805d
RK
4385 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4386 return true;
1a26b032 4387
5be669c7
RK
4388 /* Convert a == b ? b : a to "a". */
4389 if (true_code == EQ && ! side_effects_p (cond)
4390 && rtx_equal_p (XEXP (cond, 0), false)
4391 && rtx_equal_p (XEXP (cond, 1), true))
4392 return false;
4393 else if (true_code == NE && ! side_effects_p (cond)
4394 && rtx_equal_p (XEXP (cond, 0), true)
4395 && rtx_equal_p (XEXP (cond, 1), false))
4396 return true;
4397
8079805d
RK
4398 /* Look for cases where we have (abs x) or (neg (abs X)). */
4399
4400 if (GET_MODE_CLASS (mode) == MODE_INT
4401 && GET_CODE (false) == NEG
4402 && rtx_equal_p (true, XEXP (false, 0))
4403 && comparison_p
4404 && rtx_equal_p (true, XEXP (cond, 0))
4405 && ! side_effects_p (true))
4406 switch (true_code)
4407 {
4408 case GT:
4409 case GE:
0c1c8ea6 4410 return gen_unary (ABS, mode, mode, true);
8079805d
RK
4411 case LT:
4412 case LE:
0c1c8ea6 4413 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
e9a25f70
JL
4414 default:
4415 break;
8079805d
RK
4416 }
4417
4418 /* Look for MIN or MAX. */
4419
34c8be72 4420 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
8079805d
RK
4421 && comparison_p
4422 && rtx_equal_p (XEXP (cond, 0), true)
4423 && rtx_equal_p (XEXP (cond, 1), false)
4424 && ! side_effects_p (cond))
4425 switch (true_code)
4426 {
4427 case GE:
4428 case GT:
4429 return gen_binary (SMAX, mode, true, false);
4430 case LE:
4431 case LT:
4432 return gen_binary (SMIN, mode, true, false);
4433 case GEU:
4434 case GTU:
4435 return gen_binary (UMAX, mode, true, false);
4436 case LEU:
4437 case LTU:
4438 return gen_binary (UMIN, mode, true, false);
e9a25f70
JL
4439 default:
4440 break;
8079805d
RK
4441 }
4442
8079805d
RK
4443 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4444 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4445 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4446 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4447 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
0802d516 4448 neither 1 or -1, but it isn't worth checking for. */
8079805d 4449
0802d516
RK
4450 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4451 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
8079805d
RK
4452 {
4453 rtx t = make_compound_operation (true, SET);
4454 rtx f = make_compound_operation (false, SET);
4455 rtx cond_op0 = XEXP (cond, 0);
4456 rtx cond_op1 = XEXP (cond, 1);
4457 enum rtx_code op, extend_op = NIL;
4458 enum machine_mode m = mode;
f24ad0e4 4459 rtx z = 0, c1;
8079805d 4460
8079805d
RK
4461 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4462 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4463 || GET_CODE (t) == ASHIFT
4464 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4465 && rtx_equal_p (XEXP (t, 0), f))
4466 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4467
4468 /* If an identity-zero op is commutative, check whether there
0f41302f 4469 would be a match if we swapped the operands. */
8079805d
RK
4470 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4471 || GET_CODE (t) == XOR)
4472 && rtx_equal_p (XEXP (t, 1), f))
4473 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4474 else if (GET_CODE (t) == SIGN_EXTEND
4475 && (GET_CODE (XEXP (t, 0)) == PLUS
4476 || GET_CODE (XEXP (t, 0)) == MINUS
4477 || GET_CODE (XEXP (t, 0)) == IOR
4478 || GET_CODE (XEXP (t, 0)) == XOR
4479 || GET_CODE (XEXP (t, 0)) == ASHIFT
4480 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4481 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4482 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4483 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4484 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4485 && (num_sign_bit_copies (f, GET_MODE (f))
4486 > (GET_MODE_BITSIZE (mode)
4487 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4488 {
4489 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4490 extend_op = SIGN_EXTEND;
4491 m = GET_MODE (XEXP (t, 0));
1a26b032 4492 }
8079805d
RK
4493 else if (GET_CODE (t) == SIGN_EXTEND
4494 && (GET_CODE (XEXP (t, 0)) == PLUS
4495 || GET_CODE (XEXP (t, 0)) == IOR
4496 || GET_CODE (XEXP (t, 0)) == XOR)
4497 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4498 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4499 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4500 && (num_sign_bit_copies (f, GET_MODE (f))
4501 > (GET_MODE_BITSIZE (mode)
4502 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4503 {
4504 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4505 extend_op = SIGN_EXTEND;
4506 m = GET_MODE (XEXP (t, 0));
4507 }
4508 else if (GET_CODE (t) == ZERO_EXTEND
4509 && (GET_CODE (XEXP (t, 0)) == PLUS
4510 || GET_CODE (XEXP (t, 0)) == MINUS
4511 || GET_CODE (XEXP (t, 0)) == IOR
4512 || GET_CODE (XEXP (t, 0)) == XOR
4513 || GET_CODE (XEXP (t, 0)) == ASHIFT
4514 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4515 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4516 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4517 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4518 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4519 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4520 && ((nonzero_bits (f, GET_MODE (f))
4521 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4522 == 0))
4523 {
4524 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4525 extend_op = ZERO_EXTEND;
4526 m = GET_MODE (XEXP (t, 0));
4527 }
4528 else if (GET_CODE (t) == ZERO_EXTEND
4529 && (GET_CODE (XEXP (t, 0)) == PLUS
4530 || GET_CODE (XEXP (t, 0)) == IOR
4531 || GET_CODE (XEXP (t, 0)) == XOR)
4532 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4533 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4534 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4535 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4536 && ((nonzero_bits (f, GET_MODE (f))
4537 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4538 == 0))
4539 {
4540 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4541 extend_op = ZERO_EXTEND;
4542 m = GET_MODE (XEXP (t, 0));
4543 }
4544
4545 if (z)
4546 {
4547 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4548 pc_rtx, pc_rtx, 0, 0);
4549 temp = gen_binary (MULT, m, temp,
4550 gen_binary (MULT, m, c1, const_true_rtx));
4551 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4552 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4553
4554 if (extend_op != NIL)
0c1c8ea6 4555 temp = gen_unary (extend_op, mode, m, temp);
8079805d
RK
4556
4557 return temp;
4558 }
4559 }
224eeff2 4560
8079805d
RK
4561 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4562 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4563 negation of a single bit, we can convert this operation to a shift. We
4564 can actually do this more generally, but it doesn't seem worth it. */
4565
4566 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4567 && false == const0_rtx && GET_CODE (true) == CONST_INT
4568 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4569 && (i = exact_log2 (INTVAL (true))) >= 0)
4570 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4571 == GET_MODE_BITSIZE (mode))
4572 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4573 return
4574 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4575 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
230d793d 4576
8079805d
RK
4577 return x;
4578}
4579\f
4580/* Simplify X, a SET expression. Return the new expression. */
230d793d 4581
8079805d
RK
4582static rtx
4583simplify_set (x)
4584 rtx x;
4585{
4586 rtx src = SET_SRC (x);
4587 rtx dest = SET_DEST (x);
4588 enum machine_mode mode
4589 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4590 rtx other_insn;
4591 rtx *cc_use;
4592
4593 /* (set (pc) (return)) gets written as (return). */
4594 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4595 return src;
230d793d 4596
87e3e0c1
RK
4597 /* Now that we know for sure which bits of SRC we are using, see if we can
4598 simplify the expression for the object knowing that we only need the
4599 low-order bits. */
4600
4601 if (GET_MODE_CLASS (mode) == MODE_INT)
4602 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4603
8079805d
RK
4604 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4605 the comparison result and try to simplify it unless we already have used
4606 undobuf.other_insn. */
4607 if ((GET_CODE (src) == COMPARE
230d793d 4608#ifdef HAVE_cc0
8079805d 4609 || dest == cc0_rtx
230d793d 4610#endif
8079805d
RK
4611 )
4612 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4613 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4614 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
c0d3ac4d 4615 && rtx_equal_p (XEXP (*cc_use, 0), dest))
8079805d
RK
4616 {
4617 enum rtx_code old_code = GET_CODE (*cc_use);
4618 enum rtx_code new_code;
4619 rtx op0, op1;
4620 int other_changed = 0;
4621 enum machine_mode compare_mode = GET_MODE (dest);
4622
4623 if (GET_CODE (src) == COMPARE)
4624 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4625 else
4626 op0 = src, op1 = const0_rtx;
230d793d 4627
8079805d
RK
4628 /* Simplify our comparison, if possible. */
4629 new_code = simplify_comparison (old_code, &op0, &op1);
230d793d 4630
c141a106 4631#ifdef EXTRA_CC_MODES
8079805d
RK
4632 /* If this machine has CC modes other than CCmode, check to see if we
4633 need to use a different CC mode here. */
4634 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
c141a106 4635#endif /* EXTRA_CC_MODES */
230d793d 4636
c141a106 4637#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
8079805d
RK
4638 /* If the mode changed, we have to change SET_DEST, the mode in the
4639 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4640 a hard register, just build new versions with the proper mode. If it
4641 is a pseudo, we lose unless it is only time we set the pseudo, in
4642 which case we can safely change its mode. */
4643 if (compare_mode != GET_MODE (dest))
4644 {
4645 int regno = REGNO (dest);
38a448ca 4646 rtx new_dest = gen_rtx_REG (compare_mode, regno);
8079805d
RK
4647
4648 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 4649 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
230d793d 4650 {
8079805d
RK
4651 if (regno >= FIRST_PSEUDO_REGISTER)
4652 SUBST (regno_reg_rtx[regno], new_dest);
230d793d 4653
8079805d
RK
4654 SUBST (SET_DEST (x), new_dest);
4655 SUBST (XEXP (*cc_use, 0), new_dest);
4656 other_changed = 1;
230d793d 4657
8079805d 4658 dest = new_dest;
230d793d 4659 }
8079805d 4660 }
230d793d
RS
4661#endif
4662
8079805d
RK
4663 /* If the code changed, we have to build a new comparison in
4664 undobuf.other_insn. */
4665 if (new_code != old_code)
4666 {
4667 unsigned HOST_WIDE_INT mask;
4668
4669 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4670 dest, const0_rtx));
4671
4672 /* If the only change we made was to change an EQ into an NE or
4673 vice versa, OP0 has only one bit that might be nonzero, and OP1
4674 is zero, check if changing the user of the condition code will
4675 produce a valid insn. If it won't, we can keep the original code
4676 in that insn by surrounding our operation with an XOR. */
4677
4678 if (((old_code == NE && new_code == EQ)
4679 || (old_code == EQ && new_code == NE))
4680 && ! other_changed && op1 == const0_rtx
4681 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4682 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
230d793d 4683 {
8079805d 4684 rtx pat = PATTERN (other_insn), note = 0;
230d793d 4685
8e2f6e35 4686 if ((recog_for_combine (&pat, other_insn, &note) < 0
8079805d
RK
4687 && ! check_asm_operands (pat)))
4688 {
4689 PUT_CODE (*cc_use, old_code);
4690 other_insn = 0;
230d793d 4691
8079805d 4692 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
230d793d 4693 }
230d793d
RS
4694 }
4695
8079805d
RK
4696 other_changed = 1;
4697 }
4698
4699 if (other_changed)
4700 undobuf.other_insn = other_insn;
230d793d
RS
4701
4702#ifdef HAVE_cc0
8079805d
RK
4703 /* If we are now comparing against zero, change our source if
4704 needed. If we do not use cc0, we always have a COMPARE. */
4705 if (op1 == const0_rtx && dest == cc0_rtx)
4706 {
4707 SUBST (SET_SRC (x), op0);
4708 src = op0;
4709 }
4710 else
230d793d
RS
4711#endif
4712
8079805d
RK
4713 /* Otherwise, if we didn't previously have a COMPARE in the
4714 correct mode, we need one. */
4715 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4716 {
4717 SUBST (SET_SRC (x),
4718 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4719 src = SET_SRC (x);
230d793d
RS
4720 }
4721 else
4722 {
8079805d
RK
4723 /* Otherwise, update the COMPARE if needed. */
4724 SUBST (XEXP (src, 0), op0);
4725 SUBST (XEXP (src, 1), op1);
230d793d 4726 }
8079805d
RK
4727 }
4728 else
4729 {
4730 /* Get SET_SRC in a form where we have placed back any
4731 compound expressions. Then do the checks below. */
4732 src = make_compound_operation (src, SET);
4733 SUBST (SET_SRC (x), src);
4734 }
230d793d 4735
8079805d
RK
4736 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4737 and X being a REG or (subreg (reg)), we may be able to convert this to
4738 (set (subreg:m2 x) (op)).
df62f951 4739
8079805d
RK
4740 We can always do this if M1 is narrower than M2 because that means that
4741 we only care about the low bits of the result.
df62f951 4742
8079805d 4743 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
9ec36da5 4744 perform a narrower operation than requested since the high-order bits will
8079805d
RK
4745 be undefined. On machine where it is defined, this transformation is safe
4746 as long as M1 and M2 have the same number of words. */
df62f951 4747
8079805d
RK
4748 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4749 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4750 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4751 / UNITS_PER_WORD)
4752 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4753 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
8baf60bb 4754#ifndef WORD_REGISTER_OPERATIONS
8079805d
RK
4755 && (GET_MODE_SIZE (GET_MODE (src))
4756 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
df62f951 4757#endif
f507a070
RK
4758#ifdef CLASS_CANNOT_CHANGE_SIZE
4759 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4760 && (TEST_HARD_REG_BIT
4761 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4762 REGNO (dest)))
4763 && (GET_MODE_SIZE (GET_MODE (src))
4764 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4765#endif
8079805d
RK
4766 && (GET_CODE (dest) == REG
4767 || (GET_CODE (dest) == SUBREG
4768 && GET_CODE (SUBREG_REG (dest)) == REG)))
4769 {
4770 SUBST (SET_DEST (x),
4771 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4772 dest));
4773 SUBST (SET_SRC (x), SUBREG_REG (src));
4774
4775 src = SET_SRC (x), dest = SET_DEST (x);
4776 }
df62f951 4777
8baf60bb 4778#ifdef LOAD_EXTEND_OP
8079805d
RK
4779 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4780 would require a paradoxical subreg. Replace the subreg with a
0f41302f 4781 zero_extend to avoid the reload that would otherwise be required. */
8079805d
RK
4782
4783 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4784 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4785 && SUBREG_WORD (src) == 0
4786 && (GET_MODE_SIZE (GET_MODE (src))
4787 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4788 && GET_CODE (SUBREG_REG (src)) == MEM)
4789 {
4790 SUBST (SET_SRC (x),
4791 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4792 GET_MODE (src), XEXP (src, 0)));
4793
4794 src = SET_SRC (x);
4795 }
230d793d
RS
4796#endif
4797
8079805d
RK
4798 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4799 are comparing an item known to be 0 or -1 against 0, use a logical
4800 operation instead. Check for one of the arms being an IOR of the other
4801 arm with some value. We compute three terms to be IOR'ed together. In
4802 practice, at most two will be nonzero. Then we do the IOR's. */
4803
4804 if (GET_CODE (dest) != PC
4805 && GET_CODE (src) == IF_THEN_ELSE
36b8d792 4806 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
8079805d
RK
4807 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4808 && XEXP (XEXP (src, 0), 1) == const0_rtx
6dd49058 4809 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
ea414472
DE
4810#ifdef HAVE_conditional_move
4811 && ! can_conditionally_move_p (GET_MODE (src))
4812#endif
8079805d
RK
4813 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4814 GET_MODE (XEXP (XEXP (src, 0), 0)))
4815 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4816 && ! side_effects_p (src))
4817 {
4818 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4819 ? XEXP (src, 1) : XEXP (src, 2));
4820 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4821 ? XEXP (src, 2) : XEXP (src, 1));
4822 rtx term1 = const0_rtx, term2, term3;
4823
4824 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4825 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4826 else if (GET_CODE (true) == IOR
4827 && rtx_equal_p (XEXP (true, 1), false))
4828 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4829 else if (GET_CODE (false) == IOR
4830 && rtx_equal_p (XEXP (false, 0), true))
4831 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4832 else if (GET_CODE (false) == IOR
4833 && rtx_equal_p (XEXP (false, 1), true))
4834 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4835
4836 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4837 term3 = gen_binary (AND, GET_MODE (src),
0c1c8ea6 4838 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
8079805d
RK
4839 XEXP (XEXP (src, 0), 0)),
4840 false);
4841
4842 SUBST (SET_SRC (x),
4843 gen_binary (IOR, GET_MODE (src),
4844 gen_binary (IOR, GET_MODE (src), term1, term2),
4845 term3));
4846
4847 src = SET_SRC (x);
4848 }
230d793d 4849
246e00f2
RK
4850 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4851 whole thing fail. */
4852 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4853 return src;
4854 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4855 return dest;
4856 else
4857 /* Convert this into a field assignment operation, if possible. */
4858 return make_field_assignment (x);
8079805d
RK
4859}
4860\f
4861/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4862 result. LAST is nonzero if this is the last retry. */
4863
4864static rtx
4865simplify_logical (x, last)
4866 rtx x;
4867 int last;
4868{
4869 enum machine_mode mode = GET_MODE (x);
4870 rtx op0 = XEXP (x, 0);
4871 rtx op1 = XEXP (x, 1);
4872
4873 switch (GET_CODE (x))
4874 {
230d793d 4875 case AND:
8079805d
RK
4876 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4877 insn (and may simplify more). */
4878 if (GET_CODE (op0) == XOR
4879 && rtx_equal_p (XEXP (op0, 0), op1)
4880 && ! side_effects_p (op1))
0c1c8ea6
RK
4881 x = gen_binary (AND, mode,
4882 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
8079805d
RK
4883
4884 if (GET_CODE (op0) == XOR
4885 && rtx_equal_p (XEXP (op0, 1), op1)
4886 && ! side_effects_p (op1))
0c1c8ea6
RK
4887 x = gen_binary (AND, mode,
4888 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
8079805d
RK
4889
4890 /* Similarly for (~ (A ^ B)) & A. */
4891 if (GET_CODE (op0) == NOT
4892 && GET_CODE (XEXP (op0, 0)) == XOR
4893 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4894 && ! side_effects_p (op1))
4895 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4896
4897 if (GET_CODE (op0) == NOT
4898 && GET_CODE (XEXP (op0, 0)) == XOR
4899 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4900 && ! side_effects_p (op1))
4901 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4902
4903 if (GET_CODE (op1) == CONST_INT)
230d793d 4904 {
8079805d 4905 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
230d793d
RS
4906
4907 /* If we have (ior (and (X C1) C2)) and the next restart would be
4908 the last, simplify this by making C1 as small as possible
0f41302f 4909 and then exit. */
8079805d
RK
4910 if (last
4911 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4912 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4913 && GET_CODE (op1) == CONST_INT)
4914 return gen_binary (IOR, mode,
4915 gen_binary (AND, mode, XEXP (op0, 0),
4916 GEN_INT (INTVAL (XEXP (op0, 1))
4917 & ~ INTVAL (op1))), op1);
230d793d
RS
4918
4919 if (GET_CODE (x) != AND)
8079805d 4920 return x;
0e32506c
RK
4921
4922 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4923 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4924 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
230d793d
RS
4925 }
4926
4927 /* Convert (A | B) & A to A. */
8079805d
RK
4928 if (GET_CODE (op0) == IOR
4929 && (rtx_equal_p (XEXP (op0, 0), op1)
4930 || rtx_equal_p (XEXP (op0, 1), op1))
4931 && ! side_effects_p (XEXP (op0, 0))
4932 && ! side_effects_p (XEXP (op0, 1)))
4933 return op1;
230d793d 4934
d0ab8cd3 4935 /* In the following group of tests (and those in case IOR below),
230d793d
RS
4936 we start with some combination of logical operations and apply
4937 the distributive law followed by the inverse distributive law.
4938 Most of the time, this results in no change. However, if some of
4939 the operands are the same or inverses of each other, simplifications
4940 will result.
4941
4942 For example, (and (ior A B) (not B)) can occur as the result of
4943 expanding a bit field assignment. When we apply the distributive
4944 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8079805d 4945 which then simplifies to (and (A (not B))).
230d793d 4946
8079805d 4947 If we have (and (ior A B) C), apply the distributive law and then
230d793d
RS
4948 the inverse distributive law to see if things simplify. */
4949
8079805d 4950 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
230d793d
RS
4951 {
4952 x = apply_distributive_law
8079805d
RK
4953 (gen_binary (GET_CODE (op0), mode,
4954 gen_binary (AND, mode, XEXP (op0, 0), op1),
4955 gen_binary (AND, mode, XEXP (op0, 1), op1)));
230d793d 4956 if (GET_CODE (x) != AND)
8079805d 4957 return x;
230d793d
RS
4958 }
4959
8079805d
RK
4960 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4961 return apply_distributive_law
4962 (gen_binary (GET_CODE (op1), mode,
4963 gen_binary (AND, mode, XEXP (op1, 0), op0),
4964 gen_binary (AND, mode, XEXP (op1, 1), op0)));
230d793d
RS
4965
4966 /* Similarly, taking advantage of the fact that
4967 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4968
8079805d
RK
4969 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4970 return apply_distributive_law
4971 (gen_binary (XOR, mode,
4972 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4973 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
230d793d 4974
8079805d
RK
4975 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4976 return apply_distributive_law
4977 (gen_binary (XOR, mode,
4978 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4979 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
230d793d
RS
4980 break;
4981
4982 case IOR:
951553af 4983 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
8079805d 4984 if (GET_CODE (op1) == CONST_INT
ac49a949 4985 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8079805d
RK
4986 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4987 return op1;
d0ab8cd3 4988
230d793d 4989 /* Convert (A & B) | A to A. */
8079805d
RK
4990 if (GET_CODE (op0) == AND
4991 && (rtx_equal_p (XEXP (op0, 0), op1)
4992 || rtx_equal_p (XEXP (op0, 1), op1))
4993 && ! side_effects_p (XEXP (op0, 0))
4994 && ! side_effects_p (XEXP (op0, 1)))
4995 return op1;
230d793d
RS
4996
4997 /* If we have (ior (and A B) C), apply the distributive law and then
4998 the inverse distributive law to see if things simplify. */
4999
8079805d 5000 if (GET_CODE (op0) == AND)
230d793d
RS
5001 {
5002 x = apply_distributive_law
5003 (gen_binary (AND, mode,
8079805d
RK
5004 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5005 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
230d793d
RS
5006
5007 if (GET_CODE (x) != IOR)
8079805d 5008 return x;
230d793d
RS
5009 }
5010
8079805d 5011 if (GET_CODE (op1) == AND)
230d793d
RS
5012 {
5013 x = apply_distributive_law
5014 (gen_binary (AND, mode,
8079805d
RK
5015 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5016 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
230d793d
RS
5017
5018 if (GET_CODE (x) != IOR)
8079805d 5019 return x;
230d793d
RS
5020 }
5021
5022 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5023 mode size to (rotate A CX). */
5024
8079805d
RK
5025 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5026 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5027 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5028 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5029 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5030 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
230d793d 5031 == GET_MODE_BITSIZE (mode)))
38a448ca
RH
5032 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5033 (GET_CODE (op0) == ASHIFT
5034 ? XEXP (op0, 1) : XEXP (op1, 1)));
230d793d 5035
71923da7
RK
5036 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5037 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5038 does not affect any of the bits in OP1, it can really be done
5039 as a PLUS and we can associate. We do this by seeing if OP1
5040 can be safely shifted left C bits. */
5041 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5042 && GET_CODE (XEXP (op0, 0)) == PLUS
5043 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5044 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5045 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5046 {
5047 int count = INTVAL (XEXP (op0, 1));
5048 HOST_WIDE_INT mask = INTVAL (op1) << count;
5049
5050 if (mask >> count == INTVAL (op1)
5051 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5052 {
5053 SUBST (XEXP (XEXP (op0, 0), 1),
5054 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5055 return op0;
5056 }
5057 }
230d793d
RS
5058 break;
5059
5060 case XOR:
5061 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5062 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5063 (NOT y). */
5064 {
5065 int num_negated = 0;
230d793d 5066
8079805d
RK
5067 if (GET_CODE (op0) == NOT)
5068 num_negated++, op0 = XEXP (op0, 0);
5069 if (GET_CODE (op1) == NOT)
5070 num_negated++, op1 = XEXP (op1, 0);
230d793d
RS
5071
5072 if (num_negated == 2)
5073 {
8079805d
RK
5074 SUBST (XEXP (x, 0), op0);
5075 SUBST (XEXP (x, 1), op1);
230d793d
RS
5076 }
5077 else if (num_negated == 1)
0c1c8ea6 5078 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
230d793d
RS
5079 }
5080
5081 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5082 correspond to a machine insn or result in further simplifications
5083 if B is a constant. */
5084
8079805d
RK
5085 if (GET_CODE (op0) == AND
5086 && rtx_equal_p (XEXP (op0, 1), op1)
5087 && ! side_effects_p (op1))
0c1c8ea6
RK
5088 return gen_binary (AND, mode,
5089 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
8079805d 5090 op1);
230d793d 5091
8079805d
RK
5092 else if (GET_CODE (op0) == AND
5093 && rtx_equal_p (XEXP (op0, 0), op1)
5094 && ! side_effects_p (op1))
0c1c8ea6
RK
5095 return gen_binary (AND, mode,
5096 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
8079805d 5097 op1);
230d793d 5098
230d793d 5099 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
0802d516
RK
5100 comparison if STORE_FLAG_VALUE is 1. */
5101 if (STORE_FLAG_VALUE == 1
5102 && op1 == const1_rtx
8079805d
RK
5103 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5104 && reversible_comparison_p (op0))
5105 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5106 mode, XEXP (op0, 0), XEXP (op0, 1));
500c518b
RK
5107
5108 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5109 is (lt foo (const_int 0)), so we can perform the above
0802d516 5110 simplification if STORE_FLAG_VALUE is 1. */
500c518b 5111
0802d516
RK
5112 if (STORE_FLAG_VALUE == 1
5113 && op1 == const1_rtx
8079805d
RK
5114 && GET_CODE (op0) == LSHIFTRT
5115 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5116 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5117 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
230d793d
RS
5118
5119 /* (xor (comparison foo bar) (const_int sign-bit))
5120 when STORE_FLAG_VALUE is the sign bit. */
5f4f0e22 5121 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 5122 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 5123 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
8079805d
RK
5124 && op1 == const_true_rtx
5125 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5126 && reversible_comparison_p (op0))
5127 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5128 mode, XEXP (op0, 0), XEXP (op0, 1));
230d793d 5129 break;
e9a25f70
JL
5130
5131 default:
5132 abort ();
230d793d
RS
5133 }
5134
5135 return x;
5136}
5137\f
5138/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5139 operations" because they can be replaced with two more basic operations.
5140 ZERO_EXTEND is also considered "compound" because it can be replaced with
5141 an AND operation, which is simpler, though only one operation.
5142
5143 The function expand_compound_operation is called with an rtx expression
5144 and will convert it to the appropriate shifts and AND operations,
5145 simplifying at each stage.
5146
5147 The function make_compound_operation is called to convert an expression
5148 consisting of shifts and ANDs into the equivalent compound expression.
5149 It is the inverse of this function, loosely speaking. */
5150
5151static rtx
5152expand_compound_operation (x)
5153 rtx x;
5154{
5155 int pos = 0, len;
5156 int unsignedp = 0;
5157 int modewidth;
5158 rtx tem;
5159
5160 switch (GET_CODE (x))
5161 {
5162 case ZERO_EXTEND:
5163 unsignedp = 1;
5164 case SIGN_EXTEND:
75473182
RS
5165 /* We can't necessarily use a const_int for a multiword mode;
5166 it depends on implicitly extending the value.
5167 Since we don't know the right way to extend it,
5168 we can't tell whether the implicit way is right.
5169
5170 Even for a mode that is no wider than a const_int,
5171 we can't win, because we need to sign extend one of its bits through
5172 the rest of it, and we don't know which bit. */
230d793d 5173 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
75473182 5174 return x;
230d793d 5175
8079805d
RK
5176 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5177 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5178 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5179 reloaded. If not for that, MEM's would very rarely be safe.
5180
5181 Reject MODEs bigger than a word, because we might not be able
5182 to reference a two-register group starting with an arbitrary register
5183 (and currently gen_lowpart might crash for a SUBREG). */
5184
5185 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
230d793d
RS
5186 return x;
5187
5188 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5189 /* If the inner object has VOIDmode (the only way this can happen
5190 is if it is a ASM_OPERANDS), we can't do anything since we don't
5191 know how much masking to do. */
5192 if (len == 0)
5193 return x;
5194
5195 break;
5196
5197 case ZERO_EXTRACT:
5198 unsignedp = 1;
5199 case SIGN_EXTRACT:
5200 /* If the operand is a CLOBBER, just return it. */
5201 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5202 return XEXP (x, 0);
5203
5204 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5205 || GET_CODE (XEXP (x, 2)) != CONST_INT
5206 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5207 return x;
5208
5209 len = INTVAL (XEXP (x, 1));
5210 pos = INTVAL (XEXP (x, 2));
5211
5212 /* If this goes outside the object being extracted, replace the object
5213 with a (use (mem ...)) construct that only combine understands
5214 and is used only for this purpose. */
5215 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
38a448ca 5216 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
230d793d 5217
f76b9db2
ILT
5218 if (BITS_BIG_ENDIAN)
5219 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5220
230d793d
RS
5221 break;
5222
5223 default:
5224 return x;
5225 }
5226
0f13a422
ILT
5227 /* We can optimize some special cases of ZERO_EXTEND. */
5228 if (GET_CODE (x) == ZERO_EXTEND)
5229 {
5230 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5231 know that the last value didn't have any inappropriate bits
5232 set. */
5233 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5234 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5235 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5236 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5237 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5238 return XEXP (XEXP (x, 0), 0);
5239
5240 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5241 if (GET_CODE (XEXP (x, 0)) == SUBREG
5242 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5243 && subreg_lowpart_p (XEXP (x, 0))
5244 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5245 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
fcc60894 5246 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
0f13a422
ILT
5247 return SUBREG_REG (XEXP (x, 0));
5248
5249 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5250 is a comparison and STORE_FLAG_VALUE permits. This is like
5251 the first case, but it works even when GET_MODE (x) is larger
5252 than HOST_WIDE_INT. */
5253 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5254 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5255 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5256 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5257 <= HOST_BITS_PER_WIDE_INT)
5258 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5259 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5260 return XEXP (XEXP (x, 0), 0);
5261
5262 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5263 if (GET_CODE (XEXP (x, 0)) == SUBREG
5264 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5265 && subreg_lowpart_p (XEXP (x, 0))
5266 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5267 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5268 <= HOST_BITS_PER_WIDE_INT)
5269 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5270 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5271 return SUBREG_REG (XEXP (x, 0));
5272
5273 /* If sign extension is cheaper than zero extension, then use it
5274 if we know that no extraneous bits are set, and that the high
5275 bit is not set. */
5276 if (flag_expensive_optimizations
5277 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5278 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5279 & ~ (((unsigned HOST_WIDE_INT)
5280 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5281 >> 1))
5282 == 0))
5283 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5284 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5285 <= HOST_BITS_PER_WIDE_INT)
5286 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5287 & ~ (((unsigned HOST_WIDE_INT)
5288 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5289 >> 1))
5290 == 0))))
5291 {
38a448ca 5292 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
0f13a422
ILT
5293
5294 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5295 return expand_compound_operation (temp);
5296 }
5297 }
5298
230d793d
RS
5299 /* If we reach here, we want to return a pair of shifts. The inner
5300 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5301 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5302 logical depending on the value of UNSIGNEDP.
5303
5304 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5305 converted into an AND of a shift.
5306
5307 We must check for the case where the left shift would have a negative
5308 count. This can happen in a case like (x >> 31) & 255 on machines
5309 that can't shift by a constant. On those machines, we would first
5310 combine the shift with the AND to produce a variable-position
5311 extraction. Then the constant of 31 would be substituted in to produce
5312 a such a position. */
5313
5314 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5315 if (modewidth >= pos - len)
5f4f0e22 5316 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
230d793d 5317 GET_MODE (x),
5f4f0e22
CH
5318 simplify_shift_const (NULL_RTX, ASHIFT,
5319 GET_MODE (x),
230d793d
RS
5320 XEXP (x, 0),
5321 modewidth - pos - len),
5322 modewidth - len);
5323
5f4f0e22
CH
5324 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5325 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5326 simplify_shift_const (NULL_RTX, LSHIFTRT,
230d793d
RS
5327 GET_MODE (x),
5328 XEXP (x, 0), pos),
5f4f0e22 5329 ((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS
5330 else
5331 /* Any other cases we can't handle. */
5332 return x;
5333
5334
5335 /* If we couldn't do this for some reason, return the original
5336 expression. */
5337 if (GET_CODE (tem) == CLOBBER)
5338 return x;
5339
5340 return tem;
5341}
5342\f
5343/* X is a SET which contains an assignment of one object into
5344 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5345 or certain SUBREGS). If possible, convert it into a series of
5346 logical operations.
5347
5348 We half-heartedly support variable positions, but do not at all
5349 support variable lengths. */
5350
5351static rtx
5352expand_field_assignment (x)
5353 rtx x;
5354{
5355 rtx inner;
0f41302f 5356 rtx pos; /* Always counts from low bit. */
230d793d
RS
5357 int len;
5358 rtx mask;
5359 enum machine_mode compute_mode;
5360
5361 /* Loop until we find something we can't simplify. */
5362 while (1)
5363 {
5364 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5365 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5366 {
5367 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5368 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4d9cfc7b 5369 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
230d793d
RS
5370 }
5371 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5372 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5373 {
5374 inner = XEXP (SET_DEST (x), 0);
5375 len = INTVAL (XEXP (SET_DEST (x), 1));
5376 pos = XEXP (SET_DEST (x), 2);
5377
5378 /* If the position is constant and spans the width of INNER,
5379 surround INNER with a USE to indicate this. */
5380 if (GET_CODE (pos) == CONST_INT
5381 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
38a448ca 5382 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
230d793d 5383
f76b9db2
ILT
5384 if (BITS_BIG_ENDIAN)
5385 {
5386 if (GET_CODE (pos) == CONST_INT)
5387 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5388 - INTVAL (pos));
5389 else if (GET_CODE (pos) == MINUS
5390 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5391 && (INTVAL (XEXP (pos, 1))
5392 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5393 /* If position is ADJUST - X, new position is X. */
5394 pos = XEXP (pos, 0);
5395 else
5396 pos = gen_binary (MINUS, GET_MODE (pos),
5397 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5398 - len),
5399 pos);
5400 }
230d793d
RS
5401 }
5402
5403 /* A SUBREG between two modes that occupy the same numbers of words
5404 can be done by moving the SUBREG to the source. */
5405 else if (GET_CODE (SET_DEST (x)) == SUBREG
5406 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5407 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5408 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5409 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5410 {
38a448ca
RH
5411 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5412 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5413 SET_SRC (x)));
230d793d
RS
5414 continue;
5415 }
5416 else
5417 break;
5418
5419 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5420 inner = SUBREG_REG (inner);
5421
5422 compute_mode = GET_MODE (inner);
5423
861556b4
RH
5424 /* Don't attempt bitwise arithmetic on non-integral modes. */
5425 if (! INTEGRAL_MODE_P (compute_mode))
5426 {
5427 enum machine_mode imode;
5428
5429 /* Something is probably seriously wrong if this matches. */
5430 if (! FLOAT_MODE_P (compute_mode))
5431 break;
5432
5433 /* Try to find an integral mode to pun with. */
5434 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5435 if (imode == BLKmode)
5436 break;
5437
5438 compute_mode = imode;
5439 inner = gen_lowpart_for_combine (imode, inner);
5440 }
5441
230d793d 5442 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5f4f0e22
CH
5443 if (len < HOST_BITS_PER_WIDE_INT)
5444 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS
5445 else
5446 break;
5447
5448 /* Now compute the equivalent expression. Make a copy of INNER
5449 for the SET_DEST in case it is a MEM into which we will substitute;
5450 we don't want shared RTL in that case. */
38a448ca
RH
5451 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5452 gen_binary (IOR, compute_mode,
5453 gen_binary (AND, compute_mode,
5454 gen_unary (NOT, compute_mode,
5455 compute_mode,
5456 gen_binary (ASHIFT,
5457 compute_mode,
5458 mask, pos)),
5459 inner),
5460 gen_binary (ASHIFT, compute_mode,
5461 gen_binary (AND, compute_mode,
5462 gen_lowpart_for_combine
5463 (compute_mode,
5464 SET_SRC (x)),
5465 mask),
5466 pos)));
230d793d
RS
5467 }
5468
5469 return x;
5470}
5471\f
8999a12e
RK
5472/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5473 it is an RTX that represents a variable starting position; otherwise,
5474 POS is the (constant) starting bit position (counted from the LSB).
230d793d
RS
5475
5476 INNER may be a USE. This will occur when we started with a bitfield
5477 that went outside the boundary of the object in memory, which is
5478 allowed on most machines. To isolate this case, we produce a USE
5479 whose mode is wide enough and surround the MEM with it. The only
5480 code that understands the USE is this routine. If it is not removed,
5481 it will cause the resulting insn not to match.
5482
5483 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5484 signed reference.
5485
5486 IN_DEST is non-zero if this is a reference in the destination of a
5487 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5488 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5489 be used.
5490
5491 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5492 ZERO_EXTRACT should be built even for bits starting at bit 0.
5493
76184def
DE
5494 MODE is the desired mode of the result (if IN_DEST == 0).
5495
5496 The result is an RTX for the extraction or NULL_RTX if the target
5497 can't handle it. */
230d793d
RS
5498
5499static rtx
5500make_extraction (mode, inner, pos, pos_rtx, len,
5501 unsignedp, in_dest, in_compare)
5502 enum machine_mode mode;
5503 rtx inner;
5504 int pos;
5505 rtx pos_rtx;
5506 int len;
5507 int unsignedp;
5508 int in_dest, in_compare;
5509{
94b4b17a
RS
5510 /* This mode describes the size of the storage area
5511 to fetch the overall value from. Within that, we
5512 ignore the POS lowest bits, etc. */
230d793d
RS
5513 enum machine_mode is_mode = GET_MODE (inner);
5514 enum machine_mode inner_mode;
d7cd794f
RK
5515 enum machine_mode wanted_inner_mode = byte_mode;
5516 enum machine_mode wanted_inner_reg_mode = word_mode;
230d793d
RS
5517 enum machine_mode pos_mode = word_mode;
5518 enum machine_mode extraction_mode = word_mode;
5519 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5520 int spans_byte = 0;
5521 rtx new = 0;
8999a12e 5522 rtx orig_pos_rtx = pos_rtx;
6139ff20 5523 int orig_pos;
230d793d
RS
5524
5525 /* Get some information about INNER and get the innermost object. */
5526 if (GET_CODE (inner) == USE)
94b4b17a 5527 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
230d793d
RS
5528 /* We don't need to adjust the position because we set up the USE
5529 to pretend that it was a full-word object. */
5530 spans_byte = 1, inner = XEXP (inner, 0);
5531 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
94b4b17a
RS
5532 {
5533 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5534 consider just the QI as the memory to extract from.
5535 The subreg adds or removes high bits; its mode is
5536 irrelevant to the meaning of this extraction,
5537 since POS and LEN count from the lsb. */
5538 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5539 is_mode = GET_MODE (SUBREG_REG (inner));
5540 inner = SUBREG_REG (inner);
5541 }
230d793d
RS
5542
5543 inner_mode = GET_MODE (inner);
5544
5545 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
8999a12e 5546 pos = INTVAL (pos_rtx), pos_rtx = 0;
230d793d
RS
5547
5548 /* See if this can be done without an extraction. We never can if the
5549 width of the field is not the same as that of some integer mode. For
5550 registers, we can only avoid the extraction if the position is at the
5551 low-order bit and this is either not in the destination or we have the
5552 appropriate STRICT_LOW_PART operation available.
5553
5554 For MEM, we can avoid an extract if the field starts on an appropriate
5555 boundary and we can change the mode of the memory reference. However,
5556 we cannot directly access the MEM if we have a USE and the underlying
5557 MEM is not TMODE. This combination means that MEM was being used in a
5558 context where bits outside its mode were being referenced; that is only
5559 valid in bit-field insns. */
5560
5561 if (tmode != BLKmode
5562 && ! (spans_byte && inner_mode != tmode)
4d9cfc7b
RK
5563 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5564 && GET_CODE (inner) != MEM
230d793d 5565 && (! in_dest
df62f951
RK
5566 || (GET_CODE (inner) == REG
5567 && (movstrict_optab->handlers[(int) tmode].insn_code
5568 != CODE_FOR_nothing))))
8999a12e 5569 || (GET_CODE (inner) == MEM && pos_rtx == 0
dfbe1b2f
RK
5570 && (pos
5571 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5572 : BITS_PER_UNIT)) == 0
230d793d
RS
5573 /* We can't do this if we are widening INNER_MODE (it
5574 may not be aligned, for one thing). */
5575 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5576 && (inner_mode == tmode
5577 || (! mode_dependent_address_p (XEXP (inner, 0))
5578 && ! MEM_VOLATILE_P (inner))))))
5579 {
230d793d
RS
5580 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5581 field. If the original and current mode are the same, we need not
5582 adjust the offset. Otherwise, we do if bytes big endian.
5583
4d9cfc7b
RK
5584 If INNER is not a MEM, get a piece consisting of just the field
5585 of interest (in this case POS % BITS_PER_WORD must be 0). */
230d793d
RS
5586
5587 if (GET_CODE (inner) == MEM)
5588 {
94b4b17a
RS
5589 int offset;
5590 /* POS counts from lsb, but make OFFSET count in memory order. */
5591 if (BYTES_BIG_ENDIAN)
5592 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5593 else
5594 offset = pos / BITS_PER_UNIT;
230d793d 5595
38a448ca 5596 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
230d793d 5597 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
c6df88cb 5598 MEM_COPY_ATTRIBUTES (new, inner);
230d793d 5599 }
df62f951 5600 else if (GET_CODE (inner) == REG)
c0d3ac4d
RK
5601 {
5602 /* We can't call gen_lowpart_for_combine here since we always want
5603 a SUBREG and it would sometimes return a new hard register. */
5604 if (tmode != inner_mode)
38a448ca
RH
5605 new = gen_rtx_SUBREG (tmode, inner,
5606 (WORDS_BIG_ENDIAN
5607 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5608 ? (((GET_MODE_SIZE (inner_mode)
5609 - GET_MODE_SIZE (tmode))
5610 / UNITS_PER_WORD)
5611 - pos / BITS_PER_WORD)
5612 : pos / BITS_PER_WORD));
c0d3ac4d
RK
5613 else
5614 new = inner;
5615 }
230d793d 5616 else
6139ff20
RK
5617 new = force_to_mode (inner, tmode,
5618 len >= HOST_BITS_PER_WIDE_INT
5619 ? GET_MODE_MASK (tmode)
5620 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 5621 NULL_RTX, 0);
230d793d
RS
5622
5623 /* If this extraction is going into the destination of a SET,
5624 make a STRICT_LOW_PART unless we made a MEM. */
5625
5626 if (in_dest)
5627 return (GET_CODE (new) == MEM ? new
77fa0940 5628 : (GET_CODE (new) != SUBREG
38a448ca 5629 ? gen_rtx_CLOBBER (tmode, const0_rtx)
77fa0940 5630 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
230d793d
RS
5631
5632 /* Otherwise, sign- or zero-extend unless we already are in the
5633 proper mode. */
5634
5635 return (mode == tmode ? new
5636 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5637 mode, new));
5638 }
5639
cc471082
RS
5640 /* Unless this is a COMPARE or we have a funny memory reference,
5641 don't do anything with zero-extending field extracts starting at
5642 the low-order bit since they are simple AND operations. */
8999a12e
RK
5643 if (pos_rtx == 0 && pos == 0 && ! in_dest
5644 && ! in_compare && ! spans_byte && unsignedp)
230d793d
RS
5645 return 0;
5646
e7373556
RK
5647 /* Unless we are allowed to span bytes, reject this if we would be
5648 spanning bytes or if the position is not a constant and the length
5649 is not 1. In all other cases, we would only be going outside
5650 out object in cases when an original shift would have been
5651 undefined. */
5652 if (! spans_byte
5653 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5654 || (pos_rtx != 0 && len != 1)))
5655 return 0;
5656
d7cd794f 5657 /* Get the mode to use should INNER not be a MEM, the mode for the position,
230d793d
RS
5658 and the mode for the result. */
5659#ifdef HAVE_insv
5660 if (in_dest)
5661 {
0d8e55d8
JL
5662 wanted_inner_reg_mode
5663 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode
5664 ? word_mode
5665 : insn_operand_mode[(int) CODE_FOR_insv][0]);
5666 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode
5667 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]);
5668 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode
5669 ? word_mode
5670 : insn_operand_mode[(int) CODE_FOR_insv][3]);
230d793d
RS
5671 }
5672#endif
5673
5674#ifdef HAVE_extzv
5675 if (! in_dest && unsignedp)
5676 {
0d8e55d8
JL
5677 wanted_inner_reg_mode
5678 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode
5679 ? word_mode
5680 : insn_operand_mode[(int) CODE_FOR_extzv][1]);
5681 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode
5682 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]);
5683 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode
5684 ? word_mode
5685 : insn_operand_mode[(int) CODE_FOR_extzv][0]);
230d793d
RS
5686 }
5687#endif
5688
5689#ifdef HAVE_extv
5690 if (! in_dest && ! unsignedp)
5691 {
0d8e55d8
JL
5692 wanted_inner_reg_mode
5693 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode
5694 ? word_mode
5695 : insn_operand_mode[(int) CODE_FOR_extv][1]);
5696 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode
5697 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]);
5698 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode
5699 ? word_mode
5700 : insn_operand_mode[(int) CODE_FOR_extv][0]);
230d793d
RS
5701 }
5702#endif
5703
5704 /* Never narrow an object, since that might not be safe. */
5705
5706 if (mode != VOIDmode
5707 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5708 extraction_mode = mode;
5709
5710 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5711 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5712 pos_mode = GET_MODE (pos_rtx);
5713
d7cd794f
RK
5714 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5715 if we have to change the mode of memory and cannot, the desired mode is
5716 EXTRACTION_MODE. */
5717 if (GET_CODE (inner) != MEM)
5718 wanted_inner_mode = wanted_inner_reg_mode;
5719 else if (inner_mode != wanted_inner_mode
5720 && (mode_dependent_address_p (XEXP (inner, 0))
5721 || MEM_VOLATILE_P (inner)))
5722 wanted_inner_mode = extraction_mode;
230d793d 5723
6139ff20
RK
5724 orig_pos = pos;
5725
f76b9db2
ILT
5726 if (BITS_BIG_ENDIAN)
5727 {
cf54c2cd
DE
5728 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5729 BITS_BIG_ENDIAN style. If position is constant, compute new
5730 position. Otherwise, build subtraction.
5731 Note that POS is relative to the mode of the original argument.
5732 If it's a MEM we need to recompute POS relative to that.
5733 However, if we're extracting from (or inserting into) a register,
5734 we want to recompute POS relative to wanted_inner_mode. */
5735 int width = (GET_CODE (inner) == MEM
5736 ? GET_MODE_BITSIZE (is_mode)
5737 : GET_MODE_BITSIZE (wanted_inner_mode));
5738
f76b9db2 5739 if (pos_rtx == 0)
cf54c2cd 5740 pos = width - len - pos;
f76b9db2
ILT
5741 else
5742 pos_rtx
5743 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
cf54c2cd
DE
5744 GEN_INT (width - len), pos_rtx);
5745 /* POS may be less than 0 now, but we check for that below.
5746 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
f76b9db2 5747 }
230d793d
RS
5748
5749 /* If INNER has a wider mode, make it smaller. If this is a constant
5750 extract, try to adjust the byte to point to the byte containing
5751 the value. */
d7cd794f
RK
5752 if (wanted_inner_mode != VOIDmode
5753 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
230d793d 5754 && ((GET_CODE (inner) == MEM
d7cd794f 5755 && (inner_mode == wanted_inner_mode
230d793d
RS
5756 || (! mode_dependent_address_p (XEXP (inner, 0))
5757 && ! MEM_VOLATILE_P (inner))))))
5758 {
5759 int offset = 0;
5760
5761 /* The computations below will be correct if the machine is big
5762 endian in both bits and bytes or little endian in bits and bytes.
5763 If it is mixed, we must adjust. */
5764
230d793d 5765 /* If bytes are big endian and we had a paradoxical SUBREG, we must
0f41302f 5766 adjust OFFSET to compensate. */
f76b9db2
ILT
5767 if (BYTES_BIG_ENDIAN
5768 && ! spans_byte
230d793d
RS
5769 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5770 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
230d793d
RS
5771
5772 /* If this is a constant position, we can move to the desired byte. */
8999a12e 5773 if (pos_rtx == 0)
230d793d
RS
5774 {
5775 offset += pos / BITS_PER_UNIT;
d7cd794f 5776 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
230d793d
RS
5777 }
5778
f76b9db2
ILT
5779 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5780 && ! spans_byte
d7cd794f 5781 && is_mode != wanted_inner_mode)
c6b3f1f2 5782 offset = (GET_MODE_SIZE (is_mode)
d7cd794f 5783 - GET_MODE_SIZE (wanted_inner_mode) - offset);
c6b3f1f2 5784
d7cd794f 5785 if (offset != 0 || inner_mode != wanted_inner_mode)
230d793d 5786 {
38a448ca
RH
5787 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5788 plus_constant (XEXP (inner, 0), offset));
230d793d 5789 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
c6df88cb 5790 MEM_COPY_ATTRIBUTES (newmem, inner);
230d793d
RS
5791 inner = newmem;
5792 }
5793 }
5794
9e74dc41
RK
5795 /* If INNER is not memory, we can always get it into the proper mode. If we
5796 are changing its mode, POS must be a constant and smaller than the size
5797 of the new mode. */
230d793d 5798 else if (GET_CODE (inner) != MEM)
9e74dc41
RK
5799 {
5800 if (GET_MODE (inner) != wanted_inner_mode
5801 && (pos_rtx != 0
5802 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5803 return 0;
5804
5805 inner = force_to_mode (inner, wanted_inner_mode,
5806 pos_rtx
5807 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5808 ? GET_MODE_MASK (wanted_inner_mode)
5809 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5810 NULL_RTX, 0);
5811 }
230d793d
RS
5812
5813 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5814 have to zero extend. Otherwise, we can just use a SUBREG. */
8999a12e 5815 if (pos_rtx != 0
230d793d
RS
5816 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5817 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
8999a12e 5818 else if (pos_rtx != 0
230d793d
RS
5819 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5820 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5821
8999a12e
RK
5822 /* Make POS_RTX unless we already have it and it is correct. If we don't
5823 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
0f41302f 5824 be a CONST_INT. */
8999a12e
RK
5825 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5826 pos_rtx = orig_pos_rtx;
5827
5828 else if (pos_rtx == 0)
5f4f0e22 5829 pos_rtx = GEN_INT (pos);
230d793d
RS
5830
5831 /* Make the required operation. See if we can use existing rtx. */
5832 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5f4f0e22 5833 extraction_mode, inner, GEN_INT (len), pos_rtx);
230d793d
RS
5834 if (! in_dest)
5835 new = gen_lowpart_for_combine (mode, new);
5836
5837 return new;
5838}
5839\f
71923da7
RK
5840/* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5841 with any other operations in X. Return X without that shift if so. */
5842
5843static rtx
5844extract_left_shift (x, count)
5845 rtx x;
5846 int count;
5847{
5848 enum rtx_code code = GET_CODE (x);
5849 enum machine_mode mode = GET_MODE (x);
5850 rtx tem;
5851
5852 switch (code)
5853 {
5854 case ASHIFT:
5855 /* This is the shift itself. If it is wide enough, we will return
5856 either the value being shifted if the shift count is equal to
5857 COUNT or a shift for the difference. */
5858 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5859 && INTVAL (XEXP (x, 1)) >= count)
5860 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5861 INTVAL (XEXP (x, 1)) - count);
5862 break;
5863
5864 case NEG: case NOT:
5865 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
0c1c8ea6 5866 return gen_unary (code, mode, mode, tem);
71923da7
RK
5867
5868 break;
5869
5870 case PLUS: case IOR: case XOR: case AND:
5871 /* If we can safely shift this constant and we find the inner shift,
5872 make a new operation. */
5873 if (GET_CODE (XEXP (x,1)) == CONST_INT
b729186a 5874 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
71923da7
RK
5875 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5876 return gen_binary (code, mode, tem,
5877 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5878
5879 break;
e9a25f70
JL
5880
5881 default:
5882 break;
71923da7
RK
5883 }
5884
5885 return 0;
5886}
5887\f
230d793d
RS
5888/* Look at the expression rooted at X. Look for expressions
5889 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5890 Form these expressions.
5891
5892 Return the new rtx, usually just X.
5893
5894 Also, for machines like the Vax that don't have logical shift insns,
5895 try to convert logical to arithmetic shift operations in cases where
5896 they are equivalent. This undoes the canonicalizations to logical
5897 shifts done elsewhere.
5898
5899 We try, as much as possible, to re-use rtl expressions to save memory.
5900
5901 IN_CODE says what kind of expression we are processing. Normally, it is
42495ca0
RK
5902 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5903 being kludges), it is MEM. When processing the arguments of a comparison
230d793d
RS
5904 or a COMPARE against zero, it is COMPARE. */
5905
5906static rtx
5907make_compound_operation (x, in_code)
5908 rtx x;
5909 enum rtx_code in_code;
5910{
5911 enum rtx_code code = GET_CODE (x);
5912 enum machine_mode mode = GET_MODE (x);
5913 int mode_width = GET_MODE_BITSIZE (mode);
71923da7 5914 rtx rhs, lhs;
230d793d 5915 enum rtx_code next_code;
f24ad0e4 5916 int i;
230d793d 5917 rtx new = 0;
280f58ba 5918 rtx tem;
230d793d
RS
5919 char *fmt;
5920
5921 /* Select the code to be used in recursive calls. Once we are inside an
5922 address, we stay there. If we have a comparison, set to COMPARE,
5923 but once inside, go back to our default of SET. */
5924
42495ca0 5925 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
230d793d
RS
5926 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5927 && XEXP (x, 1) == const0_rtx) ? COMPARE
5928 : in_code == COMPARE ? SET : in_code);
5929
5930 /* Process depending on the code of this operation. If NEW is set
5931 non-zero, it will be returned. */
5932
5933 switch (code)
5934 {
5935 case ASHIFT:
230d793d
RS
5936 /* Convert shifts by constants into multiplications if inside
5937 an address. */
5938 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 5939 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
230d793d 5940 && INTVAL (XEXP (x, 1)) >= 0)
280f58ba
RK
5941 {
5942 new = make_compound_operation (XEXP (x, 0), next_code);
5943 new = gen_rtx_combine (MULT, mode, new,
5944 GEN_INT ((HOST_WIDE_INT) 1
5945 << INTVAL (XEXP (x, 1))));
5946 }
230d793d
RS
5947 break;
5948
5949 case AND:
5950 /* If the second operand is not a constant, we can't do anything
5951 with it. */
5952 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5953 break;
5954
5955 /* If the constant is a power of two minus one and the first operand
5956 is a logical right shift, make an extraction. */
5957 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5958 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK
5959 {
5960 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5961 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5962 0, in_code == COMPARE);
5963 }
dfbe1b2f 5964
230d793d
RS
5965 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5966 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5967 && subreg_lowpart_p (XEXP (x, 0))
5968 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5969 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK
5970 {
5971 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5972 next_code);
2f99f437 5973 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
280f58ba
RK
5974 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5975 0, in_code == COMPARE);
5976 }
45620ed4 5977 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
c2f9f64e
JW
5978 else if ((GET_CODE (XEXP (x, 0)) == XOR
5979 || GET_CODE (XEXP (x, 0)) == IOR)
5980 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5981 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5982 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5983 {
5984 /* Apply the distributive law, and then try to make extractions. */
5985 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
38a448ca
RH
5986 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5987 XEXP (x, 1)),
5988 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5989 XEXP (x, 1)));
c2f9f64e
JW
5990 new = make_compound_operation (new, in_code);
5991 }
a7c99304
RK
5992
5993 /* If we are have (and (rotate X C) M) and C is larger than the number
5994 of bits in M, this is an extraction. */
5995
5996 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5997 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5998 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5999 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
280f58ba
RK
6000 {
6001 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6002 new = make_extraction (mode, new,
6003 (GET_MODE_BITSIZE (mode)
6004 - INTVAL (XEXP (XEXP (x, 0), 1))),
6005 NULL_RTX, i, 1, 0, in_code == COMPARE);
6006 }
a7c99304
RK
6007
6008 /* On machines without logical shifts, if the operand of the AND is
230d793d
RS
6009 a logical shift and our mask turns off all the propagated sign
6010 bits, we can replace the logical shift with an arithmetic shift. */
d0ab8cd3
RK
6011 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6012 && (lshr_optab->handlers[(int) mode].insn_code
6013 == CODE_FOR_nothing)
230d793d
RS
6014 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6015 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6016 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5f4f0e22
CH
6017 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6018 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 6019 {
5f4f0e22 6020 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS
6021
6022 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6023 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6024 SUBST (XEXP (x, 0),
280f58ba
RK
6025 gen_rtx_combine (ASHIFTRT, mode,
6026 make_compound_operation (XEXP (XEXP (x, 0), 0),
6027 next_code),
230d793d
RS
6028 XEXP (XEXP (x, 0), 1)));
6029 }
6030
6031 /* If the constant is one less than a power of two, this might be
6032 representable by an extraction even if no shift is present.
6033 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6034 we are in a COMPARE. */
6035 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK
6036 new = make_extraction (mode,
6037 make_compound_operation (XEXP (x, 0),
6038 next_code),
6039 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
230d793d
RS
6040
6041 /* If we are in a comparison and this is an AND with a power of two,
6042 convert this into the appropriate bit extract. */
6043 else if (in_code == COMPARE
6044 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
280f58ba
RK
6045 new = make_extraction (mode,
6046 make_compound_operation (XEXP (x, 0),
6047 next_code),
6048 i, NULL_RTX, 1, 1, 0, 1);
230d793d
RS
6049
6050 break;
6051
6052 case LSHIFTRT:
6053 /* If the sign bit is known to be zero, replace this with an
6054 arithmetic shift. */
d0ab8cd3
RK
6055 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6056 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5f4f0e22 6057 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 6058 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
230d793d 6059 {
280f58ba
RK
6060 new = gen_rtx_combine (ASHIFTRT, mode,
6061 make_compound_operation (XEXP (x, 0),
6062 next_code),
6063 XEXP (x, 1));
230d793d
RS
6064 break;
6065 }
6066
0f41302f 6067 /* ... fall through ... */
230d793d
RS
6068
6069 case ASHIFTRT:
71923da7
RK
6070 lhs = XEXP (x, 0);
6071 rhs = XEXP (x, 1);
6072
230d793d
RS
6073 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6074 this is a SIGN_EXTRACT. */
71923da7
RK
6075 if (GET_CODE (rhs) == CONST_INT
6076 && GET_CODE (lhs) == ASHIFT
6077 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6078 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
280f58ba 6079 {
71923da7 6080 new = make_compound_operation (XEXP (lhs, 0), next_code);
280f58ba 6081 new = make_extraction (mode, new,
71923da7
RK
6082 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6083 NULL_RTX, mode_width - INTVAL (rhs),
d0ab8cd3
RK
6084 code == LSHIFTRT, 0, in_code == COMPARE);
6085 }
6086
71923da7
RK
6087 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6088 If so, try to merge the shifts into a SIGN_EXTEND. We could
6089 also do this for some cases of SIGN_EXTRACT, but it doesn't
6090 seem worth the effort; the case checked for occurs on Alpha. */
6091
6092 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6093 && ! (GET_CODE (lhs) == SUBREG
6094 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6095 && GET_CODE (rhs) == CONST_INT
6096 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6097 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6098 new = make_extraction (mode, make_compound_operation (new, next_code),
6099 0, NULL_RTX, mode_width - INTVAL (rhs),
6100 code == LSHIFTRT, 0, in_code == COMPARE);
6101
230d793d 6102 break;
280f58ba
RK
6103
6104 case SUBREG:
6105 /* Call ourselves recursively on the inner expression. If we are
6106 narrowing the object and it has a different RTL code from
6107 what it originally did, do this SUBREG as a force_to_mode. */
6108
0a5cbff6 6109 tem = make_compound_operation (SUBREG_REG (x), in_code);
280f58ba
RK
6110 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6111 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6112 && subreg_lowpart_p (x))
0a5cbff6
RK
6113 {
6114 rtx newer = force_to_mode (tem, mode,
e3d616e3 6115 GET_MODE_MASK (mode), NULL_RTX, 0);
0a5cbff6
RK
6116
6117 /* If we have something other than a SUBREG, we might have
6118 done an expansion, so rerun outselves. */
6119 if (GET_CODE (newer) != SUBREG)
6120 newer = make_compound_operation (newer, in_code);
6121
6122 return newer;
6123 }
6f28d3e9
RH
6124
6125 /* If this is a paradoxical subreg, and the new code is a sign or
6126 zero extension, omit the subreg and widen the extension. If it
6127 is a regular subreg, we can still get rid of the subreg by not
6128 widening so much, or in fact removing the extension entirely. */
6129 if ((GET_CODE (tem) == SIGN_EXTEND
6130 || GET_CODE (tem) == ZERO_EXTEND)
6131 && subreg_lowpart_p (x))
6132 {
6133 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6134 || (GET_MODE_SIZE (mode) >
6135 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6136 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6137 else
6138 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6139 return tem;
6140 }
e9a25f70
JL
6141 break;
6142
6143 default:
6144 break;
230d793d
RS
6145 }
6146
6147 if (new)
6148 {
df62f951 6149 x = gen_lowpart_for_combine (mode, new);
230d793d
RS
6150 code = GET_CODE (x);
6151 }
6152
6153 /* Now recursively process each operand of this operation. */
6154 fmt = GET_RTX_FORMAT (code);
6155 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6156 if (fmt[i] == 'e')
6157 {
6158 new = make_compound_operation (XEXP (x, i), next_code);
6159 SUBST (XEXP (x, i), new);
6160 }
6161
6162 return x;
6163}
6164\f
6165/* Given M see if it is a value that would select a field of bits
6166 within an item, but not the entire word. Return -1 if not.
6167 Otherwise, return the starting position of the field, where 0 is the
6168 low-order bit.
6169
6170 *PLEN is set to the length of the field. */
6171
6172static int
6173get_pos_from_mask (m, plen)
5f4f0e22 6174 unsigned HOST_WIDE_INT m;
230d793d
RS
6175 int *plen;
6176{
6177 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6178 int pos = exact_log2 (m & - m);
6179
6180 if (pos < 0)
6181 return -1;
6182
6183 /* Now shift off the low-order zero bits and see if we have a power of
6184 two minus 1. */
6185 *plen = exact_log2 ((m >> pos) + 1);
6186
6187 if (*plen <= 0)
6188 return -1;
6189
6190 return pos;
6191}
6192\f
6139ff20
RK
6193/* See if X can be simplified knowing that we will only refer to it in
6194 MODE and will only refer to those bits that are nonzero in MASK.
6195 If other bits are being computed or if masking operations are done
6196 that select a superset of the bits in MASK, they can sometimes be
6197 ignored.
6198
6199 Return a possibly simplified expression, but always convert X to
6200 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
dfbe1b2f
RK
6201
6202 Also, if REG is non-zero and X is a register equal in value to REG,
e3d616e3
RK
6203 replace X with REG.
6204
6205 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6206 are all off in X. This is used when X will be complemented, by either
180b8e4b 6207 NOT, NEG, or XOR. */
dfbe1b2f
RK
6208
6209static rtx
e3d616e3 6210force_to_mode (x, mode, mask, reg, just_select)
dfbe1b2f
RK
6211 rtx x;
6212 enum machine_mode mode;
6139ff20 6213 unsigned HOST_WIDE_INT mask;
dfbe1b2f 6214 rtx reg;
e3d616e3 6215 int just_select;
dfbe1b2f
RK
6216{
6217 enum rtx_code code = GET_CODE (x);
180b8e4b 6218 int next_select = just_select || code == XOR || code == NOT || code == NEG;
ef026f91
RS
6219 enum machine_mode op_mode;
6220 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6139ff20
RK
6221 rtx op0, op1, temp;
6222
132d2040
RK
6223 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6224 code below will do the wrong thing since the mode of such an
be3d27d6
CI
6225 expression is VOIDmode.
6226
6227 Also do nothing if X is a CLOBBER; this can happen if X was
6228 the return value from a call to gen_lowpart_for_combine. */
6229 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
246e00f2
RK
6230 return x;
6231
6139ff20
RK
6232 /* We want to perform the operation is its present mode unless we know
6233 that the operation is valid in MODE, in which case we do the operation
6234 in MODE. */
1c75dfa4
RK
6235 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6236 && code_to_optab[(int) code] != 0
ef026f91
RS
6237 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6238 != CODE_FOR_nothing))
6239 ? mode : GET_MODE (x));
e3d616e3 6240
aa988991
RS
6241 /* It is not valid to do a right-shift in a narrower mode
6242 than the one it came in with. */
6243 if ((code == LSHIFTRT || code == ASHIFTRT)
6244 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6245 op_mode = GET_MODE (x);
ef026f91
RS
6246
6247 /* Truncate MASK to fit OP_MODE. */
6248 if (op_mode)
6249 mask &= GET_MODE_MASK (op_mode);
6139ff20
RK
6250
6251 /* When we have an arithmetic operation, or a shift whose count we
6252 do not know, we need to assume that all bit the up to the highest-order
6253 bit in MASK will be needed. This is how we form such a mask. */
ef026f91
RS
6254 if (op_mode)
6255 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6256 ? GET_MODE_MASK (op_mode)
6257 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6258 else
6259 fuller_mask = ~ (HOST_WIDE_INT) 0;
6260
6261 /* Determine what bits of X are guaranteed to be (non)zero. */
6262 nonzero = nonzero_bits (x, mode);
6139ff20
RK
6263
6264 /* If none of the bits in X are needed, return a zero. */
e3d616e3 6265 if (! just_select && (nonzero & mask) == 0)
6139ff20 6266 return const0_rtx;
dfbe1b2f 6267
6139ff20
RK
6268 /* If X is a CONST_INT, return a new one. Do this here since the
6269 test below will fail. */
6270 if (GET_CODE (x) == CONST_INT)
ceb7983c
RK
6271 {
6272 HOST_WIDE_INT cval = INTVAL (x) & mask;
6273 int width = GET_MODE_BITSIZE (mode);
6274
6275 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6276 number, sign extend it. */
6277 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6278 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6279 cval |= (HOST_WIDE_INT) -1 << width;
6280
6281 return GEN_INT (cval);
6282 }
dfbe1b2f 6283
180b8e4b
RK
6284 /* If X is narrower than MODE and we want all the bits in X's mode, just
6285 get X in the proper mode. */
6286 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6287 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
dfbe1b2f
RK
6288 return gen_lowpart_for_combine (mode, x);
6289
71923da7
RK
6290 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6291 MASK are already known to be zero in X, we need not do anything. */
6292 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6139ff20
RK
6293 return x;
6294
dfbe1b2f
RK
6295 switch (code)
6296 {
6139ff20
RK
6297 case CLOBBER:
6298 /* If X is a (clobber (const_int)), return it since we know we are
0f41302f 6299 generating something that won't match. */
6139ff20
RK
6300 return x;
6301
6139ff20
RK
6302 case USE:
6303 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6304 spanned the boundary of the MEM. If we are now masking so it is
6305 within that boundary, we don't need the USE any more. */
f76b9db2
ILT
6306 if (! BITS_BIG_ENDIAN
6307 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
e3d616e3 6308 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
f76b9db2 6309 break;
6139ff20 6310
dfbe1b2f
RK
6311 case SIGN_EXTEND:
6312 case ZERO_EXTEND:
6313 case ZERO_EXTRACT:
6314 case SIGN_EXTRACT:
6315 x = expand_compound_operation (x);
6316 if (GET_CODE (x) != code)
e3d616e3 6317 return force_to_mode (x, mode, mask, reg, next_select);
dfbe1b2f
RK
6318 break;
6319
6320 case REG:
6321 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6322 || rtx_equal_p (reg, get_last_value (x))))
6323 x = reg;
6324 break;
6325
dfbe1b2f 6326 case SUBREG:
6139ff20 6327 if (subreg_lowpart_p (x)
180b8e4b
RK
6328 /* We can ignore the effect of this SUBREG if it narrows the mode or
6329 if the constant masks to zero all the bits the mode doesn't
6330 have. */
6139ff20
RK
6331 && ((GET_MODE_SIZE (GET_MODE (x))
6332 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6139ff20
RK
6333 || (0 == (mask
6334 & GET_MODE_MASK (GET_MODE (x))
180b8e4b 6335 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
e3d616e3 6336 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
dfbe1b2f
RK
6337 break;
6338
6339 case AND:
6139ff20
RK
6340 /* If this is an AND with a constant, convert it into an AND
6341 whose constant is the AND of that constant with MASK. If it
6342 remains an AND of MASK, delete it since it is redundant. */
dfbe1b2f 6343
2ca9ae17 6344 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
dfbe1b2f 6345 {
6139ff20
RK
6346 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6347 mask & INTVAL (XEXP (x, 1)));
dfbe1b2f
RK
6348
6349 /* If X is still an AND, see if it is an AND with a mask that
71923da7
RK
6350 is just some low-order bits. If so, and it is MASK, we don't
6351 need it. */
dfbe1b2f
RK
6352
6353 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
e51712db 6354 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
dfbe1b2f 6355 x = XEXP (x, 0);
d0ab8cd3 6356
71923da7
RK
6357 /* If it remains an AND, try making another AND with the bits
6358 in the mode mask that aren't in MASK turned on. If the
6359 constant in the AND is wide enough, this might make a
6360 cheaper constant. */
6361
6362 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
2ca9ae17
JW
6363 && GET_MODE_MASK (GET_MODE (x)) != mask
6364 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
71923da7
RK
6365 {
6366 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6367 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6368 int width = GET_MODE_BITSIZE (GET_MODE (x));
6369 rtx y;
6370
6371 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6372 number, sign extend it. */
6373 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6374 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6375 cval |= (HOST_WIDE_INT) -1 << width;
6376
6377 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6378 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6379 x = y;
6380 }
6381
d0ab8cd3 6382 break;
dfbe1b2f
RK
6383 }
6384
6139ff20 6385 goto binop;
dfbe1b2f
RK
6386
6387 case PLUS:
6139ff20
RK
6388 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6389 low-order bits (as in an alignment operation) and FOO is already
6390 aligned to that boundary, mask C1 to that boundary as well.
6391 This may eliminate that PLUS and, later, the AND. */
9fa6d012
TG
6392
6393 {
6394 int width = GET_MODE_BITSIZE (mode);
6395 unsigned HOST_WIDE_INT smask = mask;
6396
6397 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6398 number, sign extend it. */
6399
6400 if (width < HOST_BITS_PER_WIDE_INT
6401 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6402 smask |= (HOST_WIDE_INT) -1 << width;
6403
6404 if (GET_CODE (XEXP (x, 1)) == CONST_INT
0e9ff885
DM
6405 && exact_log2 (- smask) >= 0)
6406 {
6407#ifdef STACK_BIAS
6408 if (STACK_BIAS
6409 && (XEXP (x, 0) == stack_pointer_rtx
6410 || XEXP (x, 0) == frame_pointer_rtx))
6411 {
6412 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6413 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6414
6415 sp_mask &= ~ (sp_alignment - 1);
6416 if ((sp_mask & ~ mask) == 0
6417 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6418 return force_to_mode (plus_constant (XEXP (x, 0),
6419 ((INTVAL (XEXP (x, 1)) -
6420 STACK_BIAS) & mask)
6421 + STACK_BIAS),
6422 mode, mask, reg, next_select);
6423 }
6424#endif
6425 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6426 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6427 return force_to_mode (plus_constant (XEXP (x, 0),
6428 INTVAL (XEXP (x, 1)) & mask),
6429 mode, mask, reg, next_select);
6430 }
9fa6d012 6431 }
6139ff20 6432
0f41302f 6433 /* ... fall through ... */
6139ff20 6434
dfbe1b2f
RK
6435 case MINUS:
6436 case MULT:
6139ff20
RK
6437 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6438 most significant bit in MASK since carries from those bits will
6439 affect the bits we are interested in. */
6440 mask = fuller_mask;
6441 goto binop;
6442
dfbe1b2f
RK
6443 case IOR:
6444 case XOR:
6139ff20
RK
6445 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6446 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6447 operation which may be a bitfield extraction. Ensure that the
6448 constant we form is not wider than the mode of X. */
6449
6450 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6451 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6452 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6453 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6454 && GET_CODE (XEXP (x, 1)) == CONST_INT
6455 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6456 + floor_log2 (INTVAL (XEXP (x, 1))))
6457 < GET_MODE_BITSIZE (GET_MODE (x)))
6458 && (INTVAL (XEXP (x, 1))
01c82bbb 6459 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6139ff20
RK
6460 {
6461 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6462 << INTVAL (XEXP (XEXP (x, 0), 1)));
6463 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6464 XEXP (XEXP (x, 0), 0), temp);
d4d2b13f
RK
6465 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6466 XEXP (XEXP (x, 0), 1));
e3d616e3 6467 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK
6468 }
6469
6470 binop:
dfbe1b2f 6471 /* For most binary operations, just propagate into the operation and
6139ff20
RK
6472 change the mode if we have an operation of that mode. */
6473
e3d616e3
RK
6474 op0 = gen_lowpart_for_combine (op_mode,
6475 force_to_mode (XEXP (x, 0), mode, mask,
6476 reg, next_select));
6477 op1 = gen_lowpart_for_combine (op_mode,
6478 force_to_mode (XEXP (x, 1), mode, mask,
6479 reg, next_select));
6139ff20 6480
2dd484ed
RK
6481 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6482 MASK since OP1 might have been sign-extended but we never want
6483 to turn on extra bits, since combine might have previously relied
6484 on them being off. */
6485 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6486 && (INTVAL (op1) & mask) != 0)
6487 op1 = GEN_INT (INTVAL (op1) & mask);
6488
6139ff20
RK
6489 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6490 x = gen_binary (code, op_mode, op0, op1);
d0ab8cd3 6491 break;
dfbe1b2f
RK
6492
6493 case ASHIFT:
dfbe1b2f 6494 /* For left shifts, do the same, but just for the first operand.
f6785026
RK
6495 However, we cannot do anything with shifts where we cannot
6496 guarantee that the counts are smaller than the size of the mode
6497 because such a count will have a different meaning in a
6139ff20 6498 wider mode. */
f6785026
RK
6499
6500 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6501 && INTVAL (XEXP (x, 1)) >= 0
f6785026
RK
6502 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6503 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6504 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
adb7a1cb 6505 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
f6785026
RK
6506 break;
6507
6139ff20
RK
6508 /* If the shift count is a constant and we can do arithmetic in
6509 the mode of the shift, refine which bits we need. Otherwise, use the
6510 conservative form of the mask. */
6511 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6512 && INTVAL (XEXP (x, 1)) >= 0
6513 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6514 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6515 mask >>= INTVAL (XEXP (x, 1));
6516 else
6517 mask = fuller_mask;
6518
6519 op0 = gen_lowpart_for_combine (op_mode,
6520 force_to_mode (XEXP (x, 0), op_mode,
e3d616e3 6521 mask, reg, next_select));
6139ff20
RK
6522
6523 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6524 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
d0ab8cd3 6525 break;
dfbe1b2f
RK
6526
6527 case LSHIFTRT:
1347292b
JW
6528 /* Here we can only do something if the shift count is a constant,
6529 this shift constant is valid for the host, and we can do arithmetic
6530 in OP_MODE. */
dfbe1b2f
RK
6531
6532 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1347292b 6533 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6139ff20 6534 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 6535 {
6139ff20
RK
6536 rtx inner = XEXP (x, 0);
6537
6538 /* Select the mask of the bits we need for the shift operand. */
6539 mask <<= INTVAL (XEXP (x, 1));
d0ab8cd3 6540
6139ff20
RK
6541 /* We can only change the mode of the shift if we can do arithmetic
6542 in the mode of the shift and MASK is no wider than the width of
6543 OP_MODE. */
6544 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6545 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
d0ab8cd3
RK
6546 op_mode = GET_MODE (x);
6547
e3d616e3 6548 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6139ff20
RK
6549
6550 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6551 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
d0ab8cd3 6552 }
6139ff20
RK
6553
6554 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6555 shift and AND produces only copies of the sign bit (C2 is one less
6556 than a power of two), we can do this with just a shift. */
6557
6558 if (GET_CODE (x) == LSHIFTRT
6559 && GET_CODE (XEXP (x, 1)) == CONST_INT
6560 && ((INTVAL (XEXP (x, 1))
6561 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6562 >= GET_MODE_BITSIZE (GET_MODE (x)))
6563 && exact_log2 (mask + 1) >= 0
6564 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6565 >= exact_log2 (mask + 1)))
6566 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6567 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6568 - exact_log2 (mask + 1)));
d0ab8cd3
RK
6569 break;
6570
6571 case ASHIFTRT:
6139ff20
RK
6572 /* If we are just looking for the sign bit, we don't need this shift at
6573 all, even if it has a variable count. */
9bf22b75 6574 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
e51712db 6575 && (mask == ((unsigned HOST_WIDE_INT) 1
9bf22b75 6576 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
e3d616e3 6577 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20
RK
6578
6579 /* If this is a shift by a constant, get a mask that contains those bits
6580 that are not copies of the sign bit. We then have two cases: If
6581 MASK only includes those bits, this can be a logical shift, which may
6582 allow simplifications. If MASK is a single-bit field not within
6583 those bits, we are requesting a copy of the sign bit and hence can
6584 shift the sign bit to the appropriate location. */
6585
6586 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6587 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6588 {
6589 int i = -1;
6590
b69960ac
RK
6591 /* If the considered data is wider then HOST_WIDE_INT, we can't
6592 represent a mask for all its bits in a single scalar.
6593 But we only care about the lower bits, so calculate these. */
6594
6a11342f 6595 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
b69960ac 6596 {
0f41302f 6597 nonzero = ~ (HOST_WIDE_INT) 0;
b69960ac
RK
6598
6599 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6600 is the number of bits a full-width mask would have set.
6601 We need only shift if these are fewer than nonzero can
6602 hold. If not, we must keep all bits set in nonzero. */
6603
6604 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6605 < HOST_BITS_PER_WIDE_INT)
6606 nonzero >>= INTVAL (XEXP (x, 1))
6607 + HOST_BITS_PER_WIDE_INT
6608 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6609 }
6610 else
6611 {
6612 nonzero = GET_MODE_MASK (GET_MODE (x));
6613 nonzero >>= INTVAL (XEXP (x, 1));
6614 }
6139ff20
RK
6615
6616 if ((mask & ~ nonzero) == 0
6617 || (i = exact_log2 (mask)) >= 0)
6618 {
6619 x = simplify_shift_const
6620 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6621 i < 0 ? INTVAL (XEXP (x, 1))
6622 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6623
6624 if (GET_CODE (x) != ASHIFTRT)
e3d616e3 6625 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK
6626 }
6627 }
6628
6629 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6630 even if the shift count isn't a constant. */
6631 if (mask == 1)
6632 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6633
d0ab8cd3 6634 /* If this is a sign-extension operation that just affects bits
4c002f29
RK
6635 we don't care about, remove it. Be sure the call above returned
6636 something that is still a shift. */
d0ab8cd3 6637
4c002f29
RK
6638 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6639 && GET_CODE (XEXP (x, 1)) == CONST_INT
d0ab8cd3 6640 && INTVAL (XEXP (x, 1)) >= 0
6139ff20
RK
6641 && (INTVAL (XEXP (x, 1))
6642 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
d0ab8cd3
RK
6643 && GET_CODE (XEXP (x, 0)) == ASHIFT
6644 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6645 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
e3d616e3
RK
6646 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6647 reg, next_select);
6139ff20 6648
dfbe1b2f
RK
6649 break;
6650
6139ff20
RK
6651 case ROTATE:
6652 case ROTATERT:
6653 /* If the shift count is constant and we can do computations
6654 in the mode of X, compute where the bits we care about are.
6655 Otherwise, we can't do anything. Don't change the mode of
6656 the shift or propagate MODE into the shift, though. */
6657 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6658 && INTVAL (XEXP (x, 1)) >= 0)
6659 {
6660 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6661 GET_MODE (x), GEN_INT (mask),
6662 XEXP (x, 1));
7d171a1e 6663 if (temp && GET_CODE(temp) == CONST_INT)
6139ff20
RK
6664 SUBST (XEXP (x, 0),
6665 force_to_mode (XEXP (x, 0), GET_MODE (x),
e3d616e3 6666 INTVAL (temp), reg, next_select));
6139ff20
RK
6667 }
6668 break;
6669
dfbe1b2f 6670 case NEG:
180b8e4b
RK
6671 /* If we just want the low-order bit, the NEG isn't needed since it
6672 won't change the low-order bit. */
6673 if (mask == 1)
6674 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6675
6139ff20
RK
6676 /* We need any bits less significant than the most significant bit in
6677 MASK since carries from those bits will affect the bits we are
6678 interested in. */
6679 mask = fuller_mask;
6680 goto unop;
6681
dfbe1b2f 6682 case NOT:
6139ff20
RK
6683 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6684 same as the XOR case above. Ensure that the constant we form is not
6685 wider than the mode of X. */
6686
6687 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6688 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6689 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6690 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6691 < GET_MODE_BITSIZE (GET_MODE (x)))
6692 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6693 {
6694 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6695 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6696 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6697
e3d616e3 6698 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK
6699 }
6700
f82da7d2
JW
6701 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6702 use the full mask inside the NOT. */
6703 mask = fuller_mask;
6704
6139ff20 6705 unop:
e3d616e3
RK
6706 op0 = gen_lowpart_for_combine (op_mode,
6707 force_to_mode (XEXP (x, 0), mode, mask,
6708 reg, next_select));
6139ff20 6709 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
0c1c8ea6 6710 x = gen_unary (code, op_mode, op_mode, op0);
6139ff20
RK
6711 break;
6712
6713 case NE:
6714 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
3aceff0d 6715 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
1a6ec070 6716 which is equal to STORE_FLAG_VALUE. */
3aceff0d
RK
6717 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6718 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
1a6ec070 6719 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
e3d616e3 6720 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20 6721
d0ab8cd3
RK
6722 break;
6723
6724 case IF_THEN_ELSE:
6725 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6726 written in a narrower mode. We play it safe and do not do so. */
6727
6728 SUBST (XEXP (x, 1),
6729 gen_lowpart_for_combine (GET_MODE (x),
6730 force_to_mode (XEXP (x, 1), mode,
e3d616e3 6731 mask, reg, next_select)));
d0ab8cd3
RK
6732 SUBST (XEXP (x, 2),
6733 gen_lowpart_for_combine (GET_MODE (x),
6734 force_to_mode (XEXP (x, 2), mode,
e3d616e3 6735 mask, reg,next_select)));
d0ab8cd3 6736 break;
e9a25f70
JL
6737
6738 default:
6739 break;
dfbe1b2f
RK
6740 }
6741
d0ab8cd3 6742 /* Ensure we return a value of the proper mode. */
dfbe1b2f
RK
6743 return gen_lowpart_for_combine (mode, x);
6744}
6745\f
abe6e52f
RK
6746/* Return nonzero if X is an expression that has one of two values depending on
6747 whether some other value is zero or nonzero. In that case, we return the
6748 value that is being tested, *PTRUE is set to the value if the rtx being
6749 returned has a nonzero value, and *PFALSE is set to the other alternative.
6750
6751 If we return zero, we set *PTRUE and *PFALSE to X. */
6752
6753static rtx
6754if_then_else_cond (x, ptrue, pfalse)
6755 rtx x;
6756 rtx *ptrue, *pfalse;
6757{
6758 enum machine_mode mode = GET_MODE (x);
6759 enum rtx_code code = GET_CODE (x);
6760 int size = GET_MODE_BITSIZE (mode);
6761 rtx cond0, cond1, true0, true1, false0, false1;
6762 unsigned HOST_WIDE_INT nz;
6763
6764 /* If this is a unary operation whose operand has one of two values, apply
6765 our opcode to compute those values. */
6766 if (GET_RTX_CLASS (code) == '1'
6767 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6768 {
0c1c8ea6
RK
6769 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6770 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
abe6e52f
RK
6771 return cond0;
6772 }
6773
3a19aabc 6774 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
ddd5a7c1 6775 make can't possibly match and would suppress other optimizations. */
3a19aabc
RK
6776 else if (code == COMPARE)
6777 ;
6778
abe6e52f
RK
6779 /* If this is a binary operation, see if either side has only one of two
6780 values. If either one does or if both do and they are conditional on
6781 the same value, compute the new true and false values. */
6782 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6783 || GET_RTX_CLASS (code) == '<')
6784 {
6785 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6786 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6787
6788 if ((cond0 != 0 || cond1 != 0)
6789 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6790 {
987e845a
JW
6791 /* If if_then_else_cond returned zero, then true/false are the
6792 same rtl. We must copy one of them to prevent invalid rtl
6793 sharing. */
6794 if (cond0 == 0)
6795 true0 = copy_rtx (true0);
6796 else if (cond1 == 0)
6797 true1 = copy_rtx (true1);
6798
abe6e52f
RK
6799 *ptrue = gen_binary (code, mode, true0, true1);
6800 *pfalse = gen_binary (code, mode, false0, false1);
6801 return cond0 ? cond0 : cond1;
6802 }
9210df58 6803
9210df58 6804 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
0802d516
RK
6805 operands is zero when the other is non-zero, and vice-versa,
6806 and STORE_FLAG_VALUE is 1 or -1. */
9210df58 6807
0802d516
RK
6808 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6809 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9210df58
RK
6810 || code == UMAX)
6811 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6812 {
6813 rtx op0 = XEXP (XEXP (x, 0), 1);
6814 rtx op1 = XEXP (XEXP (x, 1), 1);
6815
6816 cond0 = XEXP (XEXP (x, 0), 0);
6817 cond1 = XEXP (XEXP (x, 1), 0);
6818
6819 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6820 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6821 && reversible_comparison_p (cond1)
6822 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6823 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6824 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6825 || ((swap_condition (GET_CODE (cond0))
6826 == reverse_condition (GET_CODE (cond1)))
6827 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6828 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6829 && ! side_effects_p (x))
6830 {
6831 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6832 *pfalse = gen_binary (MULT, mode,
6833 (code == MINUS
0c1c8ea6 6834 ? gen_unary (NEG, mode, mode, op1) : op1),
9210df58
RK
6835 const_true_rtx);
6836 return cond0;
6837 }
6838 }
6839
6840 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6841 is always zero. */
0802d516
RK
6842 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6843 && (code == MULT || code == AND || code == UMIN)
9210df58
RK
6844 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6845 {
6846 cond0 = XEXP (XEXP (x, 0), 0);
6847 cond1 = XEXP (XEXP (x, 1), 0);
6848
6849 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6850 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6851 && reversible_comparison_p (cond1)
6852 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6853 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6854 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6855 || ((swap_condition (GET_CODE (cond0))
6856 == reverse_condition (GET_CODE (cond1)))
6857 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6858 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6859 && ! side_effects_p (x))
6860 {
6861 *ptrue = *pfalse = const0_rtx;
6862 return cond0;
6863 }
6864 }
abe6e52f
RK
6865 }
6866
6867 else if (code == IF_THEN_ELSE)
6868 {
6869 /* If we have IF_THEN_ELSE already, extract the condition and
6870 canonicalize it if it is NE or EQ. */
6871 cond0 = XEXP (x, 0);
6872 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6873 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6874 return XEXP (cond0, 0);
6875 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6876 {
6877 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6878 return XEXP (cond0, 0);
6879 }
6880 else
6881 return cond0;
6882 }
6883
6884 /* If X is a normal SUBREG with both inner and outer modes integral,
6885 we can narrow both the true and false values of the inner expression,
6886 if there is a condition. */
6887 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6888 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6889 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6890 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6891 &true0, &false0)))
6892 {
00244e6b
RK
6893 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6894 *pfalse
6895 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
abe6e52f 6896
abe6e52f
RK
6897 return cond0;
6898 }
6899
6900 /* If X is a constant, this isn't special and will cause confusions
6901 if we treat it as such. Likewise if it is equivalent to a constant. */
6902 else if (CONSTANT_P (x)
6903 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6904 ;
6905
6906 /* If X is known to be either 0 or -1, those are the true and
6907 false values when testing X. */
6908 else if (num_sign_bit_copies (x, mode) == size)
6909 {
6910 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6911 return x;
6912 }
6913
6914 /* Likewise for 0 or a single bit. */
6915 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6916 {
6917 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6918 return x;
6919 }
6920
6921 /* Otherwise fail; show no condition with true and false values the same. */
6922 *ptrue = *pfalse = x;
6923 return 0;
6924}
6925\f
1a26b032
RK
6926/* Return the value of expression X given the fact that condition COND
6927 is known to be true when applied to REG as its first operand and VAL
6928 as its second. X is known to not be shared and so can be modified in
6929 place.
6930
6931 We only handle the simplest cases, and specifically those cases that
6932 arise with IF_THEN_ELSE expressions. */
6933
6934static rtx
6935known_cond (x, cond, reg, val)
6936 rtx x;
6937 enum rtx_code cond;
6938 rtx reg, val;
6939{
6940 enum rtx_code code = GET_CODE (x);
f24ad0e4 6941 rtx temp;
1a26b032
RK
6942 char *fmt;
6943 int i, j;
6944
6945 if (side_effects_p (x))
6946 return x;
6947
6948 if (cond == EQ && rtx_equal_p (x, reg))
6949 return val;
6950
6951 /* If X is (abs REG) and we know something about REG's relationship
6952 with zero, we may be able to simplify this. */
6953
6954 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6955 switch (cond)
6956 {
6957 case GE: case GT: case EQ:
6958 return XEXP (x, 0);
6959 case LT: case LE:
0c1c8ea6
RK
6960 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6961 XEXP (x, 0));
e9a25f70
JL
6962 default:
6963 break;
1a26b032
RK
6964 }
6965
6966 /* The only other cases we handle are MIN, MAX, and comparisons if the
6967 operands are the same as REG and VAL. */
6968
6969 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6970 {
6971 if (rtx_equal_p (XEXP (x, 0), val))
6972 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6973
6974 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6975 {
6976 if (GET_RTX_CLASS (code) == '<')
6977 return (comparison_dominates_p (cond, code) ? const_true_rtx
6978 : (comparison_dominates_p (cond,
6979 reverse_condition (code))
6980 ? const0_rtx : x));
6981
6982 else if (code == SMAX || code == SMIN
6983 || code == UMIN || code == UMAX)
6984 {
6985 int unsignedp = (code == UMIN || code == UMAX);
6986
6987 if (code == SMAX || code == UMAX)
6988 cond = reverse_condition (cond);
6989
6990 switch (cond)
6991 {
6992 case GE: case GT:
6993 return unsignedp ? x : XEXP (x, 1);
6994 case LE: case LT:
6995 return unsignedp ? x : XEXP (x, 0);
6996 case GEU: case GTU:
6997 return unsignedp ? XEXP (x, 1) : x;
6998 case LEU: case LTU:
6999 return unsignedp ? XEXP (x, 0) : x;
e9a25f70
JL
7000 default:
7001 break;
1a26b032
RK
7002 }
7003 }
7004 }
7005 }
7006
7007 fmt = GET_RTX_FORMAT (code);
7008 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7009 {
7010 if (fmt[i] == 'e')
7011 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7012 else if (fmt[i] == 'E')
7013 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7014 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7015 cond, reg, val));
7016 }
7017
7018 return x;
7019}
7020\f
e11fa86f
RK
7021/* See if X and Y are equal for the purposes of seeing if we can rewrite an
7022 assignment as a field assignment. */
7023
7024static int
7025rtx_equal_for_field_assignment_p (x, y)
7026 rtx x;
7027 rtx y;
7028{
e11fa86f
RK
7029 if (x == y || rtx_equal_p (x, y))
7030 return 1;
7031
7032 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7033 return 0;
7034
7035 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7036 Note that all SUBREGs of MEM are paradoxical; otherwise they
7037 would have been rewritten. */
7038 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7039 && GET_CODE (SUBREG_REG (y)) == MEM
7040 && rtx_equal_p (SUBREG_REG (y),
7041 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7042 return 1;
7043
7044 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7045 && GET_CODE (SUBREG_REG (x)) == MEM
7046 && rtx_equal_p (SUBREG_REG (x),
7047 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7048 return 1;
7049
9ec36da5
JL
7050 /* We used to see if get_last_value of X and Y were the same but that's
7051 not correct. In one direction, we'll cause the assignment to have
7052 the wrong destination and in the case, we'll import a register into this
7053 insn that might have already have been dead. So fail if none of the
7054 above cases are true. */
7055 return 0;
e11fa86f
RK
7056}
7057\f
230d793d
RS
7058/* See if X, a SET operation, can be rewritten as a bit-field assignment.
7059 Return that assignment if so.
7060
7061 We only handle the most common cases. */
7062
7063static rtx
7064make_field_assignment (x)
7065 rtx x;
7066{
7067 rtx dest = SET_DEST (x);
7068 rtx src = SET_SRC (x);
dfbe1b2f 7069 rtx assign;
e11fa86f 7070 rtx rhs, lhs;
5f4f0e22
CH
7071 HOST_WIDE_INT c1;
7072 int pos, len;
dfbe1b2f
RK
7073 rtx other;
7074 enum machine_mode mode;
230d793d
RS
7075
7076 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7077 a clear of a one-bit field. We will have changed it to
7078 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7079 for a SUBREG. */
7080
7081 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7082 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7083 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
e11fa86f 7084 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7085 {
8999a12e 7086 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7087 1, 1, 1, 0);
76184def 7088 if (assign != 0)
38a448ca 7089 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7090 return x;
230d793d
RS
7091 }
7092
7093 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7094 && subreg_lowpart_p (XEXP (src, 0))
7095 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7096 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7097 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7098 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
e11fa86f 7099 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7100 {
8999a12e 7101 assign = make_extraction (VOIDmode, dest, 0,
230d793d
RS
7102 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7103 1, 1, 1, 0);
76184def 7104 if (assign != 0)
38a448ca 7105 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7106 return x;
230d793d
RS
7107 }
7108
9dd11dcb 7109 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
230d793d
RS
7110 one-bit field. */
7111 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7112 && XEXP (XEXP (src, 0), 0) == const1_rtx
e11fa86f 7113 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7114 {
8999a12e 7115 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7116 1, 1, 1, 0);
76184def 7117 if (assign != 0)
38a448ca 7118 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
76184def 7119 return x;
230d793d
RS
7120 }
7121
dfbe1b2f 7122 /* The other case we handle is assignments into a constant-position
9dd11dcb 7123 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
dfbe1b2f
RK
7124 a mask that has all one bits except for a group of zero bits and
7125 OTHER is known to have zeros where C1 has ones, this is such an
7126 assignment. Compute the position and length from C1. Shift OTHER
7127 to the appropriate position, force it to the required mode, and
7128 make the extraction. Check for the AND in both operands. */
7129
9dd11dcb 7130 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
e11fa86f
RK
7131 return x;
7132
7133 rhs = expand_compound_operation (XEXP (src, 0));
7134 lhs = expand_compound_operation (XEXP (src, 1));
7135
7136 if (GET_CODE (rhs) == AND
7137 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7138 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7139 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7140 else if (GET_CODE (lhs) == AND
7141 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7142 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7143 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
dfbe1b2f
RK
7144 else
7145 return x;
230d793d 7146
e11fa86f 7147 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
dfbe1b2f 7148 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
e5e809f4
JL
7149 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7150 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
dfbe1b2f 7151 return x;
230d793d 7152
5f4f0e22 7153 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
76184def
DE
7154 if (assign == 0)
7155 return x;
230d793d 7156
dfbe1b2f
RK
7157 /* The mode to use for the source is the mode of the assignment, or of
7158 what is inside a possible STRICT_LOW_PART. */
7159 mode = (GET_CODE (assign) == STRICT_LOW_PART
7160 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
230d793d 7161
dfbe1b2f
RK
7162 /* Shift OTHER right POS places and make it the source, restricting it
7163 to the proper length and mode. */
230d793d 7164
5f4f0e22
CH
7165 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7166 GET_MODE (src), other, pos),
6139ff20
RK
7167 mode,
7168 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7169 ? GET_MODE_MASK (mode)
7170 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 7171 dest, 0);
230d793d 7172
dfbe1b2f 7173 return gen_rtx_combine (SET, VOIDmode, assign, src);
230d793d
RS
7174}
7175\f
7176/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7177 if so. */
7178
7179static rtx
7180apply_distributive_law (x)
7181 rtx x;
7182{
7183 enum rtx_code code = GET_CODE (x);
7184 rtx lhs, rhs, other;
7185 rtx tem;
7186 enum rtx_code inner_code;
7187
d8a8a4da
RS
7188 /* Distributivity is not true for floating point.
7189 It can change the value. So don't do it.
7190 -- rms and moshier@world.std.com. */
3ad2180a 7191 if (FLOAT_MODE_P (GET_MODE (x)))
d8a8a4da
RS
7192 return x;
7193
230d793d
RS
7194 /* The outer operation can only be one of the following: */
7195 if (code != IOR && code != AND && code != XOR
7196 && code != PLUS && code != MINUS)
7197 return x;
7198
7199 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7200
0f41302f
MS
7201 /* If either operand is a primitive we can't do anything, so get out
7202 fast. */
230d793d 7203 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
dfbe1b2f 7204 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
230d793d
RS
7205 return x;
7206
7207 lhs = expand_compound_operation (lhs);
7208 rhs = expand_compound_operation (rhs);
7209 inner_code = GET_CODE (lhs);
7210 if (inner_code != GET_CODE (rhs))
7211 return x;
7212
7213 /* See if the inner and outer operations distribute. */
7214 switch (inner_code)
7215 {
7216 case LSHIFTRT:
7217 case ASHIFTRT:
7218 case AND:
7219 case IOR:
7220 /* These all distribute except over PLUS. */
7221 if (code == PLUS || code == MINUS)
7222 return x;
7223 break;
7224
7225 case MULT:
7226 if (code != PLUS && code != MINUS)
7227 return x;
7228 break;
7229
7230 case ASHIFT:
45620ed4 7231 /* This is also a multiply, so it distributes over everything. */
230d793d
RS
7232 break;
7233
7234 case SUBREG:
dfbe1b2f
RK
7235 /* Non-paradoxical SUBREGs distributes over all operations, provided
7236 the inner modes and word numbers are the same, this is an extraction
2b4bd1bc
JW
7237 of a low-order part, we don't convert an fp operation to int or
7238 vice versa, and we would not be converting a single-word
dfbe1b2f 7239 operation into a multi-word operation. The latter test is not
2b4bd1bc 7240 required, but it prevents generating unneeded multi-word operations.
dfbe1b2f
RK
7241 Some of the previous tests are redundant given the latter test, but
7242 are retained because they are required for correctness.
7243
7244 We produce the result slightly differently in this case. */
7245
7246 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7247 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7248 || ! subreg_lowpart_p (lhs)
2b4bd1bc
JW
7249 || (GET_MODE_CLASS (GET_MODE (lhs))
7250 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7251 || (GET_MODE_SIZE (GET_MODE (lhs))
8af24e26 7252 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7253 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
230d793d
RS
7254 return x;
7255
7256 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7257 SUBREG_REG (lhs), SUBREG_REG (rhs));
7258 return gen_lowpart_for_combine (GET_MODE (x), tem);
7259
7260 default:
7261 return x;
7262 }
7263
7264 /* Set LHS and RHS to the inner operands (A and B in the example
7265 above) and set OTHER to the common operand (C in the example).
7266 These is only one way to do this unless the inner operation is
7267 commutative. */
7268 if (GET_RTX_CLASS (inner_code) == 'c'
7269 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7270 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7271 else if (GET_RTX_CLASS (inner_code) == 'c'
7272 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7273 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7274 else if (GET_RTX_CLASS (inner_code) == 'c'
7275 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7276 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7277 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7278 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7279 else
7280 return x;
7281
7282 /* Form the new inner operation, seeing if it simplifies first. */
7283 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7284
7285 /* There is one exception to the general way of distributing:
7286 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7287 if (code == XOR && inner_code == IOR)
7288 {
7289 inner_code = AND;
0c1c8ea6 7290 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
230d793d
RS
7291 }
7292
7293 /* We may be able to continuing distributing the result, so call
7294 ourselves recursively on the inner operation before forming the
7295 outer operation, which we return. */
7296 return gen_binary (inner_code, GET_MODE (x),
7297 apply_distributive_law (tem), other);
7298}
7299\f
7300/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7301 in MODE.
7302
7303 Return an equivalent form, if different from X. Otherwise, return X. If
7304 X is zero, we are to always construct the equivalent form. */
7305
7306static rtx
7307simplify_and_const_int (x, mode, varop, constop)
7308 rtx x;
7309 enum machine_mode mode;
7310 rtx varop;
5f4f0e22 7311 unsigned HOST_WIDE_INT constop;
230d793d 7312{
951553af 7313 unsigned HOST_WIDE_INT nonzero;
9fa6d012 7314 int width = GET_MODE_BITSIZE (mode);
42301240 7315 int i;
230d793d 7316
6139ff20
RK
7317 /* Simplify VAROP knowing that we will be only looking at some of the
7318 bits in it. */
e3d616e3 7319 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
230d793d 7320
6139ff20
RK
7321 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7322 CONST_INT, we are done. */
7323 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7324 return varop;
230d793d 7325
fc06d7aa
RK
7326 /* See what bits may be nonzero in VAROP. Unlike the general case of
7327 a call to nonzero_bits, here we don't care about bits outside
7328 MODE. */
7329
7330 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
230d793d 7331
9fa6d012
TG
7332 /* If this would be an entire word for the target, but is not for
7333 the host, then sign-extend on the host so that the number will look
7334 the same way on the host that it would on the target.
7335
7336 For example, when building a 64 bit alpha hosted 32 bit sparc
7337 targeted compiler, then we want the 32 bit unsigned value -1 to be
7338 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7339 The later confuses the sparc backend. */
7340
7341 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7342 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7343 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7344
230d793d 7345 /* Turn off all bits in the constant that are known to already be zero.
951553af 7346 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
230d793d
RS
7347 which is tested below. */
7348
951553af 7349 constop &= nonzero;
230d793d
RS
7350
7351 /* If we don't have any bits left, return zero. */
7352 if (constop == 0)
7353 return const0_rtx;
7354
42301240
RK
7355 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7356 a power of two, we can replace this with a ASHIFT. */
7357 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7358 && (i = exact_log2 (constop)) >= 0)
7359 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7360
6139ff20
RK
7361 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7362 or XOR, then try to apply the distributive law. This may eliminate
7363 operations if either branch can be simplified because of the AND.
7364 It may also make some cases more complex, but those cases probably
7365 won't match a pattern either with or without this. */
7366
7367 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7368 return
7369 gen_lowpart_for_combine
7370 (mode,
7371 apply_distributive_law
7372 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7373 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7374 XEXP (varop, 0), constop),
7375 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7376 XEXP (varop, 1), constop))));
7377
230d793d
RS
7378 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7379 if we already had one (just check for the simplest cases). */
7380 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7381 && GET_MODE (XEXP (x, 0)) == mode
7382 && SUBREG_REG (XEXP (x, 0)) == varop)
7383 varop = XEXP (x, 0);
7384 else
7385 varop = gen_lowpart_for_combine (mode, varop);
7386
0f41302f 7387 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS
7388 if (GET_CODE (varop) == CLOBBER)
7389 return x ? x : varop;
7390
7391 /* If we are only masking insignificant bits, return VAROP. */
951553af 7392 if (constop == nonzero)
230d793d
RS
7393 x = varop;
7394
7395 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7396 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6139ff20 7397 x = gen_binary (AND, mode, varop, GEN_INT (constop));
230d793d
RS
7398
7399 else
7400 {
7401 if (GET_CODE (XEXP (x, 1)) != CONST_INT
e51712db 7402 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
5f4f0e22 7403 SUBST (XEXP (x, 1), GEN_INT (constop));
230d793d
RS
7404
7405 SUBST (XEXP (x, 0), varop);
7406 }
7407
7408 return x;
7409}
7410\f
b3728b0e
JW
7411/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7412 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7413 is less useful. We can't allow both, because that results in exponential
956d6950 7414 run time recursion. There is a nullstone testcase that triggered
b3728b0e
JW
7415 this. This macro avoids accidental uses of num_sign_bit_copies. */
7416#define num_sign_bit_copies()
7417
230d793d
RS
7418/* Given an expression, X, compute which bits in X can be non-zero.
7419 We don't care about bits outside of those defined in MODE.
7420
7421 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7422 a shift, AND, or zero_extract, we can do better. */
7423
5f4f0e22 7424static unsigned HOST_WIDE_INT
951553af 7425nonzero_bits (x, mode)
230d793d
RS
7426 rtx x;
7427 enum machine_mode mode;
7428{
951553af
RK
7429 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7430 unsigned HOST_WIDE_INT inner_nz;
230d793d
RS
7431 enum rtx_code code;
7432 int mode_width = GET_MODE_BITSIZE (mode);
7433 rtx tem;
7434
1c75dfa4
RK
7435 /* For floating-point values, assume all bits are needed. */
7436 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7437 return nonzero;
7438
230d793d
RS
7439 /* If X is wider than MODE, use its mode instead. */
7440 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7441 {
7442 mode = GET_MODE (x);
951553af 7443 nonzero = GET_MODE_MASK (mode);
230d793d
RS
7444 mode_width = GET_MODE_BITSIZE (mode);
7445 }
7446
5f4f0e22 7447 if (mode_width > HOST_BITS_PER_WIDE_INT)
230d793d
RS
7448 /* Our only callers in this case look for single bit values. So
7449 just return the mode mask. Those tests will then be false. */
951553af 7450 return nonzero;
230d793d 7451
8baf60bb 7452#ifndef WORD_REGISTER_OPERATIONS
c6965c0f 7453 /* If MODE is wider than X, but both are a single word for both the host
0840fd91
RK
7454 and target machines, we can compute this from which bits of the
7455 object might be nonzero in its own mode, taking into account the fact
7456 that on many CISC machines, accessing an object in a wider mode
7457 causes the high-order bits to become undefined. So they are
7458 not known to be zero. */
7459
7460 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7461 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7462 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
c6965c0f 7463 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
0840fd91
RK
7464 {
7465 nonzero &= nonzero_bits (x, GET_MODE (x));
7466 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7467 return nonzero;
7468 }
7469#endif
7470
230d793d
RS
7471 code = GET_CODE (x);
7472 switch (code)
7473 {
7474 case REG:
320dd7a7
RK
7475#ifdef POINTERS_EXTEND_UNSIGNED
7476 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7477 all the bits above ptr_mode are known to be zero. */
7478 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7479 && REGNO_POINTER_FLAG (REGNO (x)))
7480 nonzero &= GET_MODE_MASK (ptr_mode);
7481#endif
7482
b0d71df9
RK
7483#ifdef STACK_BOUNDARY
7484 /* If this is the stack pointer, we may know something about its
7485 alignment. If PUSH_ROUNDING is defined, it is possible for the
230d793d
RS
7486 stack to be momentarily aligned only to that amount, so we pick
7487 the least alignment. */
7488
ee49a9c7
JW
7489 /* We can't check for arg_pointer_rtx here, because it is not
7490 guaranteed to have as much alignment as the stack pointer.
7491 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7492 alignment but the argument pointer has only 64 bit alignment. */
7493
0e9ff885
DM
7494 if ((x == frame_pointer_rtx
7495 || x == stack_pointer_rtx
7496 || x == hard_frame_pointer_rtx
7497 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7498 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7499#ifdef STACK_BIAS
7500 && !STACK_BIAS
7501#endif
7502 )
230d793d 7503 {
b0d71df9 7504 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
230d793d
RS
7505
7506#ifdef PUSH_ROUNDING
91102d5a 7507 if (REGNO (x) == STACK_POINTER_REGNUM)
b0d71df9 7508 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
230d793d
RS
7509#endif
7510
320dd7a7
RK
7511 /* We must return here, otherwise we may get a worse result from
7512 one of the choices below. There is nothing useful below as
7513 far as the stack pointer is concerned. */
b0d71df9 7514 return nonzero &= ~ (sp_alignment - 1);
230d793d 7515 }
b0d71df9 7516#endif
230d793d 7517
55310dad
RK
7518 /* If X is a register whose nonzero bits value is current, use it.
7519 Otherwise, if X is a register whose value we can find, use that
7520 value. Otherwise, use the previously-computed global nonzero bits
7521 for this register. */
7522
7523 if (reg_last_set_value[REGNO (x)] != 0
7524 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7525 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK
7526 || reg_last_set_label[REGNO (x)] == label_tick)
7527 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7528 return reg_last_set_nonzero_bits[REGNO (x)];
230d793d
RS
7529
7530 tem = get_last_value (x);
9afa3d54 7531
230d793d 7532 if (tem)
9afa3d54
RK
7533 {
7534#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7535 /* If X is narrower than MODE and TEM is a non-negative
7536 constant that would appear negative in the mode of X,
7537 sign-extend it for use in reg_nonzero_bits because some
7538 machines (maybe most) will actually do the sign-extension
7539 and this is the conservative approach.
7540
7541 ??? For 2.5, try to tighten up the MD files in this regard
7542 instead of this kludge. */
7543
7544 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7545 && GET_CODE (tem) == CONST_INT
7546 && INTVAL (tem) > 0
7547 && 0 != (INTVAL (tem)
7548 & ((HOST_WIDE_INT) 1
9e69be8c 7549 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK
7550 tem = GEN_INT (INTVAL (tem)
7551 | ((HOST_WIDE_INT) (-1)
7552 << GET_MODE_BITSIZE (GET_MODE (x))));
7553#endif
7554 return nonzero_bits (tem, mode);
7555 }
951553af
RK
7556 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7557 return reg_nonzero_bits[REGNO (x)] & nonzero;
230d793d 7558 else
951553af 7559 return nonzero;
230d793d
RS
7560
7561 case CONST_INT:
9afa3d54
RK
7562#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7563 /* If X is negative in MODE, sign-extend the value. */
9e69be8c
RK
7564 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7565 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7566 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
9afa3d54
RK
7567#endif
7568
230d793d
RS
7569 return INTVAL (x);
7570
230d793d 7571 case MEM:
8baf60bb 7572#ifdef LOAD_EXTEND_OP
230d793d
RS
7573 /* In many, if not most, RISC machines, reading a byte from memory
7574 zeros the rest of the register. Noticing that fact saves a lot
7575 of extra zero-extends. */
8baf60bb
RK
7576 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7577 nonzero &= GET_MODE_MASK (GET_MODE (x));
230d793d 7578#endif
8baf60bb 7579 break;
230d793d 7580
230d793d
RS
7581 case EQ: case NE:
7582 case GT: case GTU:
7583 case LT: case LTU:
7584 case GE: case GEU:
7585 case LE: case LEU:
3f508eca 7586
c6965c0f
RK
7587 /* If this produces an integer result, we know which bits are set.
7588 Code here used to clear bits outside the mode of X, but that is
7589 now done above. */
230d793d 7590
c6965c0f
RK
7591 if (GET_MODE_CLASS (mode) == MODE_INT
7592 && mode_width <= HOST_BITS_PER_WIDE_INT)
7593 nonzero = STORE_FLAG_VALUE;
230d793d 7594 break;
230d793d 7595
230d793d 7596 case NEG:
b3728b0e
JW
7597#if 0
7598 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7599 and num_sign_bit_copies. */
d0ab8cd3
RK
7600 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7601 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7602 nonzero = 1;
b3728b0e 7603#endif
230d793d
RS
7604
7605 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
951553af 7606 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
230d793d 7607 break;
d0ab8cd3
RK
7608
7609 case ABS:
b3728b0e
JW
7610#if 0
7611 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7612 and num_sign_bit_copies. */
d0ab8cd3
RK
7613 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7614 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7615 nonzero = 1;
b3728b0e 7616#endif
d0ab8cd3 7617 break;
230d793d
RS
7618
7619 case TRUNCATE:
951553af 7620 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
230d793d
RS
7621 break;
7622
7623 case ZERO_EXTEND:
951553af 7624 nonzero &= nonzero_bits (XEXP (x, 0), mode);
230d793d 7625 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
951553af 7626 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
230d793d
RS
7627 break;
7628
7629 case SIGN_EXTEND:
7630 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7631 Otherwise, show all the bits in the outer mode but not the inner
7632 may be non-zero. */
951553af 7633 inner_nz = nonzero_bits (XEXP (x, 0), mode);
230d793d
RS
7634 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7635 {
951553af 7636 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
e3da301d
MS
7637 if (inner_nz
7638 & (((HOST_WIDE_INT) 1
7639 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
951553af 7640 inner_nz |= (GET_MODE_MASK (mode)
230d793d
RS
7641 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7642 }
7643
951553af 7644 nonzero &= inner_nz;
230d793d
RS
7645 break;
7646
7647 case AND:
951553af
RK
7648 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7649 & nonzero_bits (XEXP (x, 1), mode));
230d793d
RS
7650 break;
7651
d0ab8cd3
RK
7652 case XOR: case IOR:
7653 case UMIN: case UMAX: case SMIN: case SMAX:
951553af
RK
7654 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7655 | nonzero_bits (XEXP (x, 1), mode));
230d793d
RS
7656 break;
7657
7658 case PLUS: case MINUS:
7659 case MULT:
7660 case DIV: case UDIV:
7661 case MOD: case UMOD:
7662 /* We can apply the rules of arithmetic to compute the number of
7663 high- and low-order zero bits of these operations. We start by
7664 computing the width (position of the highest-order non-zero bit)
7665 and the number of low-order zero bits for each value. */
7666 {
951553af
RK
7667 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7668 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7669 int width0 = floor_log2 (nz0) + 1;
7670 int width1 = floor_log2 (nz1) + 1;
7671 int low0 = floor_log2 (nz0 & -nz0);
7672 int low1 = floor_log2 (nz1 & -nz1);
318b149c
RK
7673 HOST_WIDE_INT op0_maybe_minusp
7674 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7675 HOST_WIDE_INT op1_maybe_minusp
7676 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
230d793d
RS
7677 int result_width = mode_width;
7678 int result_low = 0;
7679
7680 switch (code)
7681 {
7682 case PLUS:
0e9ff885
DM
7683#ifdef STACK_BIAS
7684 if (STACK_BIAS
7685 && (XEXP (x, 0) == stack_pointer_rtx
7686 || XEXP (x, 0) == frame_pointer_rtx)
7687 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7688 {
7689 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7690
7691 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7692 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7693 width0 = floor_log2 (nz0) + 1;
7694 width1 = floor_log2 (nz1) + 1;
7695 low0 = floor_log2 (nz0 & -nz0);
7696 low1 = floor_log2 (nz1 & -nz1);
7697 }
7698#endif
230d793d
RS
7699 result_width = MAX (width0, width1) + 1;
7700 result_low = MIN (low0, low1);
7701 break;
7702 case MINUS:
7703 result_low = MIN (low0, low1);
7704 break;
7705 case MULT:
7706 result_width = width0 + width1;
7707 result_low = low0 + low1;
7708 break;
7709 case DIV:
7710 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7711 result_width = width0;
7712 break;
7713 case UDIV:
7714 result_width = width0;
7715 break;
7716 case MOD:
7717 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7718 result_width = MIN (width0, width1);
7719 result_low = MIN (low0, low1);
7720 break;
7721 case UMOD:
7722 result_width = MIN (width0, width1);
7723 result_low = MIN (low0, low1);
7724 break;
e9a25f70
JL
7725 default:
7726 abort ();
230d793d
RS
7727 }
7728
7729 if (result_width < mode_width)
951553af 7730 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
230d793d
RS
7731
7732 if (result_low > 0)
951553af 7733 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
230d793d
RS
7734 }
7735 break;
7736
7737 case ZERO_EXTRACT:
7738 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 7739 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
951553af 7740 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
230d793d
RS
7741 break;
7742
7743 case SUBREG:
c3c2cb37
RK
7744 /* If this is a SUBREG formed for a promoted variable that has
7745 been zero-extended, we know that at least the high-order bits
7746 are zero, though others might be too. */
7747
7748 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
951553af
RK
7749 nonzero = (GET_MODE_MASK (GET_MODE (x))
7750 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
c3c2cb37 7751
230d793d
RS
7752 /* If the inner mode is a single word for both the host and target
7753 machines, we can compute this from which bits of the inner
951553af 7754 object might be nonzero. */
230d793d 7755 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5f4f0e22
CH
7756 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7757 <= HOST_BITS_PER_WIDE_INT))
230d793d 7758 {
951553af 7759 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8baf60bb 7760
b52ce03d
R
7761#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7762 /* If this is a typical RISC machine, we only have to worry
7763 about the way loads are extended. */
7764 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7765 ? (nonzero
7766 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7767 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
230d793d 7768#endif
b52ce03d
R
7769 {
7770 /* On many CISC machines, accessing an object in a wider mode
7771 causes the high-order bits to become undefined. So they are
7772 not known to be zero. */
7773 if (GET_MODE_SIZE (GET_MODE (x))
7774 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7775 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7776 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7777 }
230d793d
RS
7778 }
7779 break;
7780
7781 case ASHIFTRT:
7782 case LSHIFTRT:
7783 case ASHIFT:
230d793d 7784 case ROTATE:
951553af 7785 /* The nonzero bits are in two classes: any bits within MODE
230d793d 7786 that aren't in GET_MODE (x) are always significant. The rest of the
951553af 7787 nonzero bits are those that are significant in the operand of
230d793d
RS
7788 the shift when shifted the appropriate number of bits. This
7789 shows that high-order bits are cleared by the right shift and
7790 low-order bits by left shifts. */
7791 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7792 && INTVAL (XEXP (x, 1)) >= 0
5f4f0e22 7793 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS
7794 {
7795 enum machine_mode inner_mode = GET_MODE (x);
7796 int width = GET_MODE_BITSIZE (inner_mode);
7797 int count = INTVAL (XEXP (x, 1));
5f4f0e22 7798 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
951553af
RK
7799 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7800 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5f4f0e22 7801 unsigned HOST_WIDE_INT outer = 0;
230d793d
RS
7802
7803 if (mode_width > width)
951553af 7804 outer = (op_nonzero & nonzero & ~ mode_mask);
230d793d
RS
7805
7806 if (code == LSHIFTRT)
7807 inner >>= count;
7808 else if (code == ASHIFTRT)
7809 {
7810 inner >>= count;
7811
951553af 7812 /* If the sign bit may have been nonzero before the shift, we
230d793d 7813 need to mark all the places it could have been copied to
951553af 7814 by the shift as possibly nonzero. */
5f4f0e22
CH
7815 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7816 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
230d793d 7817 }
45620ed4 7818 else if (code == ASHIFT)
230d793d
RS
7819 inner <<= count;
7820 else
7821 inner = ((inner << (count % width)
7822 | (inner >> (width - (count % width)))) & mode_mask);
7823
951553af 7824 nonzero &= (outer | inner);
230d793d
RS
7825 }
7826 break;
7827
7828 case FFS:
7829 /* This is at most the number of bits in the mode. */
951553af 7830 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
230d793d 7831 break;
d0ab8cd3
RK
7832
7833 case IF_THEN_ELSE:
951553af
RK
7834 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7835 | nonzero_bits (XEXP (x, 2), mode));
d0ab8cd3 7836 break;
e9a25f70
JL
7837
7838 default:
7839 break;
230d793d
RS
7840 }
7841
951553af 7842 return nonzero;
230d793d 7843}
b3728b0e
JW
7844
7845/* See the macro definition above. */
7846#undef num_sign_bit_copies
230d793d 7847\f
d0ab8cd3 7848/* Return the number of bits at the high-order end of X that are known to
5109d49f
RK
7849 be equal to the sign bit. X will be used in mode MODE; if MODE is
7850 VOIDmode, X will be used in its own mode. The returned value will always
7851 be between 1 and the number of bits in MODE. */
d0ab8cd3
RK
7852
7853static int
7854num_sign_bit_copies (x, mode)
7855 rtx x;
7856 enum machine_mode mode;
7857{
7858 enum rtx_code code = GET_CODE (x);
7859 int bitwidth;
7860 int num0, num1, result;
951553af 7861 unsigned HOST_WIDE_INT nonzero;
d0ab8cd3
RK
7862 rtx tem;
7863
7864 /* If we weren't given a mode, use the mode of X. If the mode is still
1c75dfa4
RK
7865 VOIDmode, we don't know anything. Likewise if one of the modes is
7866 floating-point. */
d0ab8cd3
RK
7867
7868 if (mode == VOIDmode)
7869 mode = GET_MODE (x);
7870
1c75dfa4 7871 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
6752e8d2 7872 return 1;
d0ab8cd3
RK
7873
7874 bitwidth = GET_MODE_BITSIZE (mode);
7875
0f41302f 7876 /* For a smaller object, just ignore the high bits. */
312def2e
RK
7877 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7878 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7879 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7880
e9a25f70
JL
7881 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7882 {
0c314d1a
RK
7883#ifndef WORD_REGISTER_OPERATIONS
7884 /* If this machine does not do all register operations on the entire
7885 register and MODE is wider than the mode of X, we can say nothing
7886 at all about the high-order bits. */
e9a25f70
JL
7887 return 1;
7888#else
7889 /* Likewise on machines that do, if the mode of the object is smaller
7890 than a word and loads of that size don't sign extend, we can say
7891 nothing about the high order bits. */
7892 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7893#ifdef LOAD_EXTEND_OP
7894 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7895#endif
7896 )
7897 return 1;
0c314d1a 7898#endif
e9a25f70 7899 }
0c314d1a 7900
d0ab8cd3
RK
7901 switch (code)
7902 {
7903 case REG:
55310dad 7904
ff0dbdd1
RK
7905#ifdef POINTERS_EXTEND_UNSIGNED
7906 /* If pointers extend signed and this is a pointer in Pmode, say that
7907 all the bits above ptr_mode are known to be sign bit copies. */
7908 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7909 && REGNO_POINTER_FLAG (REGNO (x)))
7910 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7911#endif
7912
55310dad
RK
7913 if (reg_last_set_value[REGNO (x)] != 0
7914 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7915 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK
7916 || reg_last_set_label[REGNO (x)] == label_tick)
7917 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7918 return reg_last_set_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK
7919
7920 tem = get_last_value (x);
7921 if (tem != 0)
7922 return num_sign_bit_copies (tem, mode);
55310dad
RK
7923
7924 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7925 return reg_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK
7926 break;
7927
457816e2 7928 case MEM:
8baf60bb 7929#ifdef LOAD_EXTEND_OP
457816e2 7930 /* Some RISC machines sign-extend all loads of smaller than a word. */
8baf60bb
RK
7931 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7932 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
457816e2 7933#endif
8baf60bb 7934 break;
457816e2 7935
d0ab8cd3
RK
7936 case CONST_INT:
7937 /* If the constant is negative, take its 1's complement and remask.
7938 Then see how many zero bits we have. */
951553af 7939 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
ac49a949 7940 if (bitwidth <= HOST_BITS_PER_WIDE_INT
951553af
RK
7941 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7942 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
d0ab8cd3 7943
951553af 7944 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK
7945
7946 case SUBREG:
c3c2cb37
RK
7947 /* If this is a SUBREG for a promoted object that is sign-extended
7948 and we are looking at it in a wider mode, we know that at least the
7949 high-order bits are known to be sign bit copies. */
7950
7951 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
dc3e17ad
RK
7952 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7953 num_sign_bit_copies (SUBREG_REG (x), mode));
c3c2cb37 7954
0f41302f 7955 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK
7956 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7957 {
7958 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7959 return MAX (1, (num0
7960 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7961 - bitwidth)));
7962 }
457816e2 7963
8baf60bb 7964#ifdef WORD_REGISTER_OPERATIONS
2aec5b7a 7965#ifdef LOAD_EXTEND_OP
8baf60bb
RK
7966 /* For paradoxical SUBREGs on machines where all register operations
7967 affect the entire register, just look inside. Note that we are
7968 passing MODE to the recursive call, so the number of sign bit copies
7969 will remain relative to that mode, not the inner mode. */
457816e2 7970
2aec5b7a
JW
7971 /* This works only if loads sign extend. Otherwise, if we get a
7972 reload for the inner part, it may be loaded from the stack, and
7973 then we lose all sign bit copies that existed before the store
7974 to the stack. */
7975
7976 if ((GET_MODE_SIZE (GET_MODE (x))
7977 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7978 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
457816e2 7979 return num_sign_bit_copies (SUBREG_REG (x), mode);
2aec5b7a 7980#endif
457816e2 7981#endif
d0ab8cd3
RK
7982 break;
7983
7984 case SIGN_EXTRACT:
7985 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7986 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7987 break;
7988
7989 case SIGN_EXTEND:
7990 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7991 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7992
7993 case TRUNCATE:
0f41302f 7994 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK
7995 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7996 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7997 - bitwidth)));
7998
7999 case NOT:
8000 return num_sign_bit_copies (XEXP (x, 0), mode);
8001
8002 case ROTATE: case ROTATERT:
8003 /* If we are rotating left by a number of bits less than the number
8004 of sign bit copies, we can just subtract that amount from the
8005 number. */
8006 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8007 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8008 {
8009 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8010 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8011 : bitwidth - INTVAL (XEXP (x, 1))));
8012 }
8013 break;
8014
8015 case NEG:
8016 /* In general, this subtracts one sign bit copy. But if the value
8017 is known to be positive, the number of sign bit copies is the
951553af
RK
8018 same as that of the input. Finally, if the input has just one bit
8019 that might be nonzero, all the bits are copies of the sign bit. */
70186b34
BS
8020 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8021 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8022 return num0 > 1 ? num0 - 1 : 1;
8023
951553af
RK
8024 nonzero = nonzero_bits (XEXP (x, 0), mode);
8025 if (nonzero == 1)
d0ab8cd3
RK
8026 return bitwidth;
8027
d0ab8cd3 8028 if (num0 > 1
951553af 8029 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
d0ab8cd3
RK
8030 num0--;
8031
8032 return num0;
8033
8034 case IOR: case AND: case XOR:
8035 case SMIN: case SMAX: case UMIN: case UMAX:
8036 /* Logical operations will preserve the number of sign-bit copies.
8037 MIN and MAX operations always return one of the operands. */
8038 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8039 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8040 return MIN (num0, num1);
8041
8042 case PLUS: case MINUS:
8043 /* For addition and subtraction, we can have a 1-bit carry. However,
8044 if we are subtracting 1 from a positive number, there will not
8045 be such a carry. Furthermore, if the positive number is known to
8046 be 0 or 1, we know the result is either -1 or 0. */
8047
3e3ea975 8048 if (code == PLUS && XEXP (x, 1) == constm1_rtx
9295e6af 8049 && bitwidth <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 8050 {
951553af
RK
8051 nonzero = nonzero_bits (XEXP (x, 0), mode);
8052 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8053 return (nonzero == 1 || nonzero == 0 ? bitwidth
8054 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK
8055 }
8056
8057 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8058 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8059 return MAX (1, MIN (num0, num1) - 1);
8060
8061 case MULT:
8062 /* The number of bits of the product is the sum of the number of
8063 bits of both terms. However, unless one of the terms if known
8064 to be positive, we must allow for an additional bit since negating
8065 a negative number can remove one sign bit copy. */
8066
8067 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8068 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8069
8070 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8071 if (result > 0
70186b34
BS
8072 && (bitwidth > HOST_BITS_PER_WIDE_INT
8073 || (((nonzero_bits (XEXP (x, 0), mode)
8074 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8075 && ((nonzero_bits (XEXP (x, 1), mode)
8076 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
d0ab8cd3
RK
8077 result--;
8078
8079 return MAX (1, result);
8080
8081 case UDIV:
70186b34
BS
8082 /* The result must be <= the first operand. If the first operand
8083 has the high bit set, we know nothing about the number of sign
8084 bit copies. */
8085 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8086 return 1;
8087 else if ((nonzero_bits (XEXP (x, 0), mode)
8088 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8089 return 1;
8090 else
8091 return num_sign_bit_copies (XEXP (x, 0), mode);
8092
d0ab8cd3
RK
8093 case UMOD:
8094 /* The result must be <= the scond operand. */
8095 return num_sign_bit_copies (XEXP (x, 1), mode);
8096
8097 case DIV:
8098 /* Similar to unsigned division, except that we have to worry about
8099 the case where the divisor is negative, in which case we have
8100 to add 1. */
8101 result = num_sign_bit_copies (XEXP (x, 0), mode);
8102 if (result > 1
70186b34
BS
8103 && (bitwidth > HOST_BITS_PER_WIDE_INT
8104 || (nonzero_bits (XEXP (x, 1), mode)
8105 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8106 result--;
d0ab8cd3
RK
8107
8108 return result;
8109
8110 case MOD:
8111 result = num_sign_bit_copies (XEXP (x, 1), mode);
8112 if (result > 1
70186b34
BS
8113 && (bitwidth > HOST_BITS_PER_WIDE_INT
8114 || (nonzero_bits (XEXP (x, 1), mode)
8115 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8116 result--;
d0ab8cd3
RK
8117
8118 return result;
8119
8120 case ASHIFTRT:
8121 /* Shifts by a constant add to the number of bits equal to the
8122 sign bit. */
8123 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8124 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8125 && INTVAL (XEXP (x, 1)) > 0)
8126 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8127
8128 return num0;
8129
8130 case ASHIFT:
d0ab8cd3
RK
8131 /* Left shifts destroy copies. */
8132 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8133 || INTVAL (XEXP (x, 1)) < 0
8134 || INTVAL (XEXP (x, 1)) >= bitwidth)
8135 return 1;
8136
8137 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8138 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8139
8140 case IF_THEN_ELSE:
8141 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8142 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8143 return MIN (num0, num1);
8144
d0ab8cd3
RK
8145 case EQ: case NE: case GE: case GT: case LE: case LT:
8146 case GEU: case GTU: case LEU: case LTU:
0802d516
RK
8147 if (STORE_FLAG_VALUE == -1)
8148 return bitwidth;
e9a25f70
JL
8149 break;
8150
8151 default:
8152 break;
d0ab8cd3
RK
8153 }
8154
8155 /* If we haven't been able to figure it out by one of the above rules,
8156 see if some of the high-order bits are known to be zero. If so,
ac49a949
RS
8157 count those bits and return one less than that amount. If we can't
8158 safely compute the mask for this mode, always return BITWIDTH. */
8159
8160 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6752e8d2 8161 return 1;
d0ab8cd3 8162
951553af 8163 nonzero = nonzero_bits (x, mode);
df6f4086 8164 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
951553af 8165 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK
8166}
8167\f
1a26b032
RK
8168/* Return the number of "extended" bits there are in X, when interpreted
8169 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8170 unsigned quantities, this is the number of high-order zero bits.
8171 For signed quantities, this is the number of copies of the sign bit
8172 minus 1. In both case, this function returns the number of "spare"
8173 bits. For example, if two quantities for which this function returns
8174 at least 1 are added, the addition is known not to overflow.
8175
8176 This function will always return 0 unless called during combine, which
8177 implies that it must be called from a define_split. */
8178
8179int
8180extended_count (x, mode, unsignedp)
8181 rtx x;
8182 enum machine_mode mode;
8183 int unsignedp;
8184{
951553af 8185 if (nonzero_sign_valid == 0)
1a26b032
RK
8186 return 0;
8187
8188 return (unsignedp
ac49a949
RS
8189 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8190 && (GET_MODE_BITSIZE (mode) - 1
951553af 8191 - floor_log2 (nonzero_bits (x, mode))))
1a26b032
RK
8192 : num_sign_bit_copies (x, mode) - 1);
8193}
8194\f
230d793d
RS
8195/* This function is called from `simplify_shift_const' to merge two
8196 outer operations. Specifically, we have already found that we need
8197 to perform operation *POP0 with constant *PCONST0 at the outermost
8198 position. We would now like to also perform OP1 with constant CONST1
8199 (with *POP0 being done last).
8200
8201 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8202 the resulting operation. *PCOMP_P is set to 1 if we would need to
8203 complement the innermost operand, otherwise it is unchanged.
8204
8205 MODE is the mode in which the operation will be done. No bits outside
8206 the width of this mode matter. It is assumed that the width of this mode
5f4f0e22 8207 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
230d793d
RS
8208
8209 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8210 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8211 result is simply *PCONST0.
8212
8213 If the resulting operation cannot be expressed as one operation, we
8214 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8215
8216static int
8217merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8218 enum rtx_code *pop0;
5f4f0e22 8219 HOST_WIDE_INT *pconst0;
230d793d 8220 enum rtx_code op1;
5f4f0e22 8221 HOST_WIDE_INT const1;
230d793d
RS
8222 enum machine_mode mode;
8223 int *pcomp_p;
8224{
8225 enum rtx_code op0 = *pop0;
5f4f0e22 8226 HOST_WIDE_INT const0 = *pconst0;
9fa6d012 8227 int width = GET_MODE_BITSIZE (mode);
230d793d
RS
8228
8229 const0 &= GET_MODE_MASK (mode);
8230 const1 &= GET_MODE_MASK (mode);
8231
8232 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8233 if (op0 == AND)
8234 const1 &= const0;
8235
8236 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8237 if OP0 is SET. */
8238
8239 if (op1 == NIL || op0 == SET)
8240 return 1;
8241
8242 else if (op0 == NIL)
8243 op0 = op1, const0 = const1;
8244
8245 else if (op0 == op1)
8246 {
8247 switch (op0)
8248 {
8249 case AND:
8250 const0 &= const1;
8251 break;
8252 case IOR:
8253 const0 |= const1;
8254 break;
8255 case XOR:
8256 const0 ^= const1;
8257 break;
8258 case PLUS:
8259 const0 += const1;
8260 break;
8261 case NEG:
8262 op0 = NIL;
8263 break;
e9a25f70
JL
8264 default:
8265 break;
230d793d
RS
8266 }
8267 }
8268
8269 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8270 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8271 return 0;
8272
8273 /* If the two constants aren't the same, we can't do anything. The
8274 remaining six cases can all be done. */
8275 else if (const0 != const1)
8276 return 0;
8277
8278 else
8279 switch (op0)
8280 {
8281 case IOR:
8282 if (op1 == AND)
8283 /* (a & b) | b == b */
8284 op0 = SET;
8285 else /* op1 == XOR */
8286 /* (a ^ b) | b == a | b */
b729186a 8287 {;}
230d793d
RS
8288 break;
8289
8290 case XOR:
8291 if (op1 == AND)
8292 /* (a & b) ^ b == (~a) & b */
8293 op0 = AND, *pcomp_p = 1;
8294 else /* op1 == IOR */
8295 /* (a | b) ^ b == a & ~b */
8296 op0 = AND, *pconst0 = ~ const0;
8297 break;
8298
8299 case AND:
8300 if (op1 == IOR)
8301 /* (a | b) & b == b */
8302 op0 = SET;
8303 else /* op1 == XOR */
8304 /* (a ^ b) & b) == (~a) & b */
8305 *pcomp_p = 1;
8306 break;
e9a25f70
JL
8307 default:
8308 break;
230d793d
RS
8309 }
8310
8311 /* Check for NO-OP cases. */
8312 const0 &= GET_MODE_MASK (mode);
8313 if (const0 == 0
8314 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8315 op0 = NIL;
8316 else if (const0 == 0 && op0 == AND)
8317 op0 = SET;
e51712db
KG
8318 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8319 && op0 == AND)
230d793d
RS
8320 op0 = NIL;
8321
9fa6d012
TG
8322 /* If this would be an entire word for the target, but is not for
8323 the host, then sign-extend on the host so that the number will look
8324 the same way on the host that it would on the target.
8325
8326 For example, when building a 64 bit alpha hosted 32 bit sparc
8327 targeted compiler, then we want the 32 bit unsigned value -1 to be
8328 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8329 The later confuses the sparc backend. */
8330
8331 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8332 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8333 const0 |= ((HOST_WIDE_INT) (-1) << width);
8334
230d793d
RS
8335 *pop0 = op0;
8336 *pconst0 = const0;
8337
8338 return 1;
8339}
8340\f
8341/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8342 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8343 that we started with.
8344
8345 The shift is normally computed in the widest mode we find in VAROP, as
8346 long as it isn't a different number of words than RESULT_MODE. Exceptions
8347 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8348
8349static rtx
8350simplify_shift_const (x, code, result_mode, varop, count)
8351 rtx x;
8352 enum rtx_code code;
8353 enum machine_mode result_mode;
8354 rtx varop;
8355 int count;
8356{
8357 enum rtx_code orig_code = code;
8358 int orig_count = count;
8359 enum machine_mode mode = result_mode;
8360 enum machine_mode shift_mode, tmode;
8361 int mode_words
8362 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8363 /* We form (outer_op (code varop count) (outer_const)). */
8364 enum rtx_code outer_op = NIL;
c4e861e8 8365 HOST_WIDE_INT outer_const = 0;
230d793d
RS
8366 rtx const_rtx;
8367 int complement_p = 0;
8368 rtx new;
8369
8370 /* If we were given an invalid count, don't do anything except exactly
8371 what was requested. */
8372
8373 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8374 {
8375 if (x)
8376 return x;
8377
38a448ca 8378 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
230d793d
RS
8379 }
8380
8381 /* Unless one of the branches of the `if' in this loop does a `continue',
8382 we will `break' the loop after the `if'. */
8383
8384 while (count != 0)
8385 {
8386 /* If we have an operand of (clobber (const_int 0)), just return that
8387 value. */
8388 if (GET_CODE (varop) == CLOBBER)
8389 return varop;
8390
8391 /* If we discovered we had to complement VAROP, leave. Making a NOT
8392 here would cause an infinite loop. */
8393 if (complement_p)
8394 break;
8395
abc95ed3 8396 /* Convert ROTATERT to ROTATE. */
230d793d
RS
8397 if (code == ROTATERT)
8398 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8399
230d793d 8400 /* We need to determine what mode we will do the shift in. If the
f6789c77
RK
8401 shift is a right shift or a ROTATE, we must always do it in the mode
8402 it was originally done in. Otherwise, we can do it in MODE, the
0f41302f 8403 widest mode encountered. */
f6789c77
RK
8404 shift_mode
8405 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8406 ? result_mode : mode);
230d793d
RS
8407
8408 /* Handle cases where the count is greater than the size of the mode
8409 minus 1. For ASHIFT, use the size minus one as the count (this can
8410 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8411 take the count modulo the size. For other shifts, the result is
8412 zero.
8413
8414 Since these shifts are being produced by the compiler by combining
8415 multiple operations, each of which are defined, we know what the
8416 result is supposed to be. */
8417
8418 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8419 {
8420 if (code == ASHIFTRT)
8421 count = GET_MODE_BITSIZE (shift_mode) - 1;
8422 else if (code == ROTATE || code == ROTATERT)
8423 count %= GET_MODE_BITSIZE (shift_mode);
8424 else
8425 {
8426 /* We can't simply return zero because there may be an
8427 outer op. */
8428 varop = const0_rtx;
8429 count = 0;
8430 break;
8431 }
8432 }
8433
8434 /* Negative counts are invalid and should not have been made (a
8435 programmer-specified negative count should have been handled
0f41302f 8436 above). */
230d793d
RS
8437 else if (count < 0)
8438 abort ();
8439
312def2e
RK
8440 /* An arithmetic right shift of a quantity known to be -1 or 0
8441 is a no-op. */
8442 if (code == ASHIFTRT
8443 && (num_sign_bit_copies (varop, shift_mode)
8444 == GET_MODE_BITSIZE (shift_mode)))
d0ab8cd3 8445 {
312def2e
RK
8446 count = 0;
8447 break;
8448 }
d0ab8cd3 8449
312def2e
RK
8450 /* If we are doing an arithmetic right shift and discarding all but
8451 the sign bit copies, this is equivalent to doing a shift by the
8452 bitsize minus one. Convert it into that shift because it will often
8453 allow other simplifications. */
500c518b 8454
312def2e
RK
8455 if (code == ASHIFTRT
8456 && (count + num_sign_bit_copies (varop, shift_mode)
8457 >= GET_MODE_BITSIZE (shift_mode)))
8458 count = GET_MODE_BITSIZE (shift_mode) - 1;
500c518b 8459
230d793d
RS
8460 /* We simplify the tests below and elsewhere by converting
8461 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8462 `make_compound_operation' will convert it to a ASHIFTRT for
8463 those machines (such as Vax) that don't have a LSHIFTRT. */
5f4f0e22 8464 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8465 && code == ASHIFTRT
951553af 8466 && ((nonzero_bits (varop, shift_mode)
5f4f0e22
CH
8467 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8468 == 0))
230d793d
RS
8469 code = LSHIFTRT;
8470
8471 switch (GET_CODE (varop))
8472 {
8473 case SIGN_EXTEND:
8474 case ZERO_EXTEND:
8475 case SIGN_EXTRACT:
8476 case ZERO_EXTRACT:
8477 new = expand_compound_operation (varop);
8478 if (new != varop)
8479 {
8480 varop = new;
8481 continue;
8482 }
8483 break;
8484
8485 case MEM:
8486 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8487 minus the width of a smaller mode, we can do this with a
8488 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8489 if ((code == ASHIFTRT || code == LSHIFTRT)
8490 && ! mode_dependent_address_p (XEXP (varop, 0))
8491 && ! MEM_VOLATILE_P (varop)
8492 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8493 MODE_INT, 1)) != BLKmode)
8494 {
f76b9db2 8495 if (BYTES_BIG_ENDIAN)
38a448ca 8496 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
f76b9db2 8497 else
38a448ca
RH
8498 new = gen_rtx_MEM (tmode,
8499 plus_constant (XEXP (varop, 0),
8500 count / BITS_PER_UNIT));
e24b00c8 8501 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
c6df88cb 8502 MEM_COPY_ATTRIBUTES (new, varop);
230d793d
RS
8503 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8504 : ZERO_EXTEND, mode, new);
8505 count = 0;
8506 continue;
8507 }
8508 break;
8509
8510 case USE:
8511 /* Similar to the case above, except that we can only do this if
8512 the resulting mode is the same as that of the underlying
8513 MEM and adjust the address depending on the *bits* endianness
8514 because of the way that bit-field extract insns are defined. */
8515 if ((code == ASHIFTRT || code == LSHIFTRT)
8516 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8517 MODE_INT, 1)) != BLKmode
8518 && tmode == GET_MODE (XEXP (varop, 0)))
8519 {
f76b9db2
ILT
8520 if (BITS_BIG_ENDIAN)
8521 new = XEXP (varop, 0);
8522 else
8523 {
8524 new = copy_rtx (XEXP (varop, 0));
8525 SUBST (XEXP (new, 0),
8526 plus_constant (XEXP (new, 0),
8527 count / BITS_PER_UNIT));
8528 }
230d793d
RS
8529
8530 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8531 : ZERO_EXTEND, mode, new);
8532 count = 0;
8533 continue;
8534 }
8535 break;
8536
8537 case SUBREG:
8538 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8539 the same number of words as what we've seen so far. Then store
8540 the widest mode in MODE. */
f9e67232
RS
8541 if (subreg_lowpart_p (varop)
8542 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8543 > GET_MODE_SIZE (GET_MODE (varop)))
230d793d
RS
8544 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8545 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8546 == mode_words))
8547 {
8548 varop = SUBREG_REG (varop);
8549 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8550 mode = GET_MODE (varop);
8551 continue;
8552 }
8553 break;
8554
8555 case MULT:
8556 /* Some machines use MULT instead of ASHIFT because MULT
8557 is cheaper. But it is still better on those machines to
8558 merge two shifts into one. */
8559 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8560 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8561 {
8562 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8563 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
230d793d
RS
8564 continue;
8565 }
8566 break;
8567
8568 case UDIV:
8569 /* Similar, for when divides are cheaper. */
8570 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8571 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8572 {
8573 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8574 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS
8575 continue;
8576 }
8577 break;
8578
8579 case ASHIFTRT:
8580 /* If we are extracting just the sign bit of an arithmetic right
8581 shift, that shift is not needed. */
8582 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8583 {
8584 varop = XEXP (varop, 0);
8585 continue;
8586 }
8587
0f41302f 8588 /* ... fall through ... */
230d793d
RS
8589
8590 case LSHIFTRT:
8591 case ASHIFT:
230d793d
RS
8592 case ROTATE:
8593 /* Here we have two nested shifts. The result is usually the
8594 AND of a new shift with a mask. We compute the result below. */
8595 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8596 && INTVAL (XEXP (varop, 1)) >= 0
8597 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5f4f0e22
CH
8598 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8599 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d
RS
8600 {
8601 enum rtx_code first_code = GET_CODE (varop);
8602 int first_count = INTVAL (XEXP (varop, 1));
5f4f0e22 8603 unsigned HOST_WIDE_INT mask;
230d793d 8604 rtx mask_rtx;
230d793d 8605
230d793d
RS
8606 /* We have one common special case. We can't do any merging if
8607 the inner code is an ASHIFTRT of a smaller mode. However, if
8608 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8609 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8610 we can convert it to
8611 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8612 This simplifies certain SIGN_EXTEND operations. */
8613 if (code == ASHIFT && first_code == ASHIFTRT
8614 && (GET_MODE_BITSIZE (result_mode)
8615 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8616 {
8617 /* C3 has the low-order C1 bits zero. */
8618
5f4f0e22
CH
8619 mask = (GET_MODE_MASK (mode)
8620 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
230d793d 8621
5f4f0e22 8622 varop = simplify_and_const_int (NULL_RTX, result_mode,
230d793d 8623 XEXP (varop, 0), mask);
5f4f0e22 8624 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
230d793d
RS
8625 varop, count);
8626 count = first_count;
8627 code = ASHIFTRT;
8628 continue;
8629 }
8630
d0ab8cd3
RK
8631 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8632 than C1 high-order bits equal to the sign bit, we can convert
8633 this to either an ASHIFT or a ASHIFTRT depending on the
8634 two counts.
230d793d
RS
8635
8636 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8637
8638 if (code == ASHIFTRT && first_code == ASHIFT
8639 && GET_MODE (varop) == shift_mode
d0ab8cd3
RK
8640 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8641 > first_count))
230d793d 8642 {
d0ab8cd3
RK
8643 count -= first_count;
8644 if (count < 0)
8645 count = - count, code = ASHIFT;
8646 varop = XEXP (varop, 0);
8647 continue;
230d793d
RS
8648 }
8649
8650 /* There are some cases we can't do. If CODE is ASHIFTRT,
8651 we can only do this if FIRST_CODE is also ASHIFTRT.
8652
8653 We can't do the case when CODE is ROTATE and FIRST_CODE is
8654 ASHIFTRT.
8655
8656 If the mode of this shift is not the mode of the outer shift,
bdaae9a0 8657 we can't do this if either shift is a right shift or ROTATE.
230d793d
RS
8658
8659 Finally, we can't do any of these if the mode is too wide
8660 unless the codes are the same.
8661
8662 Handle the case where the shift codes are the same
8663 first. */
8664
8665 if (code == first_code)
8666 {
8667 if (GET_MODE (varop) != result_mode
bdaae9a0
RK
8668 && (code == ASHIFTRT || code == LSHIFTRT
8669 || code == ROTATE))
230d793d
RS
8670 break;
8671
8672 count += first_count;
8673 varop = XEXP (varop, 0);
8674 continue;
8675 }
8676
8677 if (code == ASHIFTRT
8678 || (code == ROTATE && first_code == ASHIFTRT)
5f4f0e22 8679 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
230d793d 8680 || (GET_MODE (varop) != result_mode
bdaae9a0
RK
8681 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8682 || first_code == ROTATE
230d793d
RS
8683 || code == ROTATE)))
8684 break;
8685
8686 /* To compute the mask to apply after the shift, shift the
951553af 8687 nonzero bits of the inner shift the same way the
230d793d
RS
8688 outer shift will. */
8689
951553af 8690 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
230d793d
RS
8691
8692 mask_rtx
8693 = simplify_binary_operation (code, result_mode, mask_rtx,
5f4f0e22 8694 GEN_INT (count));
230d793d
RS
8695
8696 /* Give up if we can't compute an outer operation to use. */
8697 if (mask_rtx == 0
8698 || GET_CODE (mask_rtx) != CONST_INT
8699 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8700 INTVAL (mask_rtx),
8701 result_mode, &complement_p))
8702 break;
8703
8704 /* If the shifts are in the same direction, we add the
8705 counts. Otherwise, we subtract them. */
8706 if ((code == ASHIFTRT || code == LSHIFTRT)
8707 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8708 count += first_count;
8709 else
8710 count -= first_count;
8711
8712 /* If COUNT is positive, the new shift is usually CODE,
8713 except for the two exceptions below, in which case it is
8714 FIRST_CODE. If the count is negative, FIRST_CODE should
8715 always be used */
8716 if (count > 0
8717 && ((first_code == ROTATE && code == ASHIFT)
8718 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8719 code = first_code;
8720 else if (count < 0)
8721 code = first_code, count = - count;
8722
8723 varop = XEXP (varop, 0);
8724 continue;
8725 }
8726
8727 /* If we have (A << B << C) for any shift, we can convert this to
8728 (A << C << B). This wins if A is a constant. Only try this if
8729 B is not a constant. */
8730
8731 else if (GET_CODE (varop) == code
8732 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8733 && 0 != (new
8734 = simplify_binary_operation (code, mode,
8735 XEXP (varop, 0),
5f4f0e22 8736 GEN_INT (count))))
230d793d
RS
8737 {
8738 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8739 count = 0;
8740 continue;
8741 }
8742 break;
8743
8744 case NOT:
8745 /* Make this fit the case below. */
8746 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5f4f0e22 8747 GEN_INT (GET_MODE_MASK (mode)));
230d793d
RS
8748 continue;
8749
8750 case IOR:
8751 case AND:
8752 case XOR:
8753 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8754 with C the size of VAROP - 1 and the shift is logical if
8755 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8756 we have an (le X 0) operation. If we have an arithmetic shift
8757 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8758 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8759
8760 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8761 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8762 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8763 && (code == LSHIFTRT || code == ASHIFTRT)
8764 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8765 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8766 {
8767 count = 0;
8768 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8769 const0_rtx);
8770
8771 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8772 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8773
8774 continue;
8775 }
8776
8777 /* If we have (shift (logical)), move the logical to the outside
8778 to allow it to possibly combine with another logical and the
8779 shift to combine with another shift. This also canonicalizes to
8780 what a ZERO_EXTRACT looks like. Also, some machines have
8781 (and (shift)) insns. */
8782
8783 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8784 && (new = simplify_binary_operation (code, result_mode,
8785 XEXP (varop, 1),
5f4f0e22 8786 GEN_INT (count))) != 0
7d171a1e 8787 && GET_CODE(new) == CONST_INT
230d793d
RS
8788 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8789 INTVAL (new), result_mode, &complement_p))
8790 {
8791 varop = XEXP (varop, 0);
8792 continue;
8793 }
8794
8795 /* If we can't do that, try to simplify the shift in each arm of the
8796 logical expression, make a new logical expression, and apply
8797 the inverse distributive law. */
8798 {
00d4ca1c 8799 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d 8800 XEXP (varop, 0), count);
00d4ca1c 8801 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d
RS
8802 XEXP (varop, 1), count);
8803
21a64bf1 8804 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
230d793d
RS
8805 varop = apply_distributive_law (varop);
8806
8807 count = 0;
8808 }
8809 break;
8810
8811 case EQ:
45620ed4 8812 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
230d793d 8813 says that the sign bit can be tested, FOO has mode MODE, C is
45620ed4
RK
8814 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8815 that may be nonzero. */
8816 if (code == LSHIFTRT
230d793d
RS
8817 && XEXP (varop, 1) == const0_rtx
8818 && GET_MODE (XEXP (varop, 0)) == result_mode
8819 && count == GET_MODE_BITSIZE (result_mode) - 1
5f4f0e22 8820 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8821 && ((STORE_FLAG_VALUE
5f4f0e22 8822 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
951553af 8823 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH
8824 && merge_outer_ops (&outer_op, &outer_const, XOR,
8825 (HOST_WIDE_INT) 1, result_mode,
8826 &complement_p))
230d793d
RS
8827 {
8828 varop = XEXP (varop, 0);
8829 count = 0;
8830 continue;
8831 }
8832 break;
8833
8834 case NEG:
d0ab8cd3
RK
8835 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8836 than the number of bits in the mode is equivalent to A. */
8837 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
951553af 8838 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
230d793d 8839 {
d0ab8cd3 8840 varop = XEXP (varop, 0);
230d793d
RS
8841 count = 0;
8842 continue;
8843 }
8844
8845 /* NEG commutes with ASHIFT since it is multiplication. Move the
8846 NEG outside to allow shifts to combine. */
8847 if (code == ASHIFT
5f4f0e22
CH
8848 && merge_outer_ops (&outer_op, &outer_const, NEG,
8849 (HOST_WIDE_INT) 0, result_mode,
8850 &complement_p))
230d793d
RS
8851 {
8852 varop = XEXP (varop, 0);
8853 continue;
8854 }
8855 break;
8856
8857 case PLUS:
d0ab8cd3
RK
8858 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8859 is one less than the number of bits in the mode is
8860 equivalent to (xor A 1). */
230d793d
RS
8861 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8862 && XEXP (varop, 1) == constm1_rtx
951553af 8863 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH
8864 && merge_outer_ops (&outer_op, &outer_const, XOR,
8865 (HOST_WIDE_INT) 1, result_mode,
8866 &complement_p))
230d793d
RS
8867 {
8868 count = 0;
8869 varop = XEXP (varop, 0);
8870 continue;
8871 }
8872
3f508eca 8873 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
951553af 8874 that might be nonzero in BAR are those being shifted out and those
3f508eca
RK
8875 bits are known zero in FOO, we can replace the PLUS with FOO.
8876 Similarly in the other operand order. This code occurs when
8877 we are computing the size of a variable-size array. */
8878
8879 if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8880 && count < HOST_BITS_PER_WIDE_INT
951553af
RK
8881 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8882 && (nonzero_bits (XEXP (varop, 1), result_mode)
8883 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
3f508eca
RK
8884 {
8885 varop = XEXP (varop, 0);
8886 continue;
8887 }
8888 else if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8889 && count < HOST_BITS_PER_WIDE_INT
ac49a949 8890 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
951553af 8891 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
3f508eca 8892 >> count)
951553af
RK
8893 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8894 & nonzero_bits (XEXP (varop, 1),
3f508eca
RK
8895 result_mode)))
8896 {
8897 varop = XEXP (varop, 1);
8898 continue;
8899 }
8900
230d793d
RS
8901 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8902 if (code == ASHIFT
8903 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8904 && (new = simplify_binary_operation (ASHIFT, result_mode,
8905 XEXP (varop, 1),
5f4f0e22 8906 GEN_INT (count))) != 0
7d171a1e 8907 && GET_CODE(new) == CONST_INT
230d793d
RS
8908 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8909 INTVAL (new), result_mode, &complement_p))
8910 {
8911 varop = XEXP (varop, 0);
8912 continue;
8913 }
8914 break;
8915
8916 case MINUS:
8917 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8918 with C the size of VAROP - 1 and the shift is logical if
8919 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8920 we have a (gt X 0) operation. If the shift is arithmetic with
8921 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8922 we have a (neg (gt X 0)) operation. */
8923
0802d516
RK
8924 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8925 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
230d793d 8926 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
230d793d
RS
8927 && (code == LSHIFTRT || code == ASHIFTRT)
8928 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8929 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8930 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8931 {
8932 count = 0;
8933 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8934 const0_rtx);
8935
8936 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8937 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8938
8939 continue;
8940 }
8941 break;
6e0ef100
JC
8942
8943 case TRUNCATE:
8944 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8945 if the truncate does not affect the value. */
8946 if (code == LSHIFTRT
8947 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8948 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8949 && (INTVAL (XEXP (XEXP (varop, 0), 1))
b577a8ff
JL
8950 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8951 - GET_MODE_BITSIZE (GET_MODE (varop)))))
6e0ef100
JC
8952 {
8953 rtx varop_inner = XEXP (varop, 0);
8954
8955 varop_inner = gen_rtx_combine (LSHIFTRT,
8956 GET_MODE (varop_inner),
8957 XEXP (varop_inner, 0),
8958 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8959 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8960 varop_inner);
8961 count = 0;
8962 continue;
8963 }
8964 break;
e9a25f70
JL
8965
8966 default:
8967 break;
230d793d
RS
8968 }
8969
8970 break;
8971 }
8972
8973 /* We need to determine what mode to do the shift in. If the shift is
f6789c77
RK
8974 a right shift or ROTATE, we must always do it in the mode it was
8975 originally done in. Otherwise, we can do it in MODE, the widest mode
8976 encountered. The code we care about is that of the shift that will
8977 actually be done, not the shift that was originally requested. */
8978 shift_mode
8979 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8980 ? result_mode : mode);
230d793d
RS
8981
8982 /* We have now finished analyzing the shift. The result should be
8983 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8984 OUTER_OP is non-NIL, it is an operation that needs to be applied
8985 to the result of the shift. OUTER_CONST is the relevant constant,
8986 but we must turn off all bits turned off in the shift.
8987
8988 If we were passed a value for X, see if we can use any pieces of
8989 it. If not, make new rtx. */
8990
8991 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8992 && GET_CODE (XEXP (x, 1)) == CONST_INT
8993 && INTVAL (XEXP (x, 1)) == count)
8994 const_rtx = XEXP (x, 1);
8995 else
5f4f0e22 8996 const_rtx = GEN_INT (count);
230d793d
RS
8997
8998 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8999 && GET_MODE (XEXP (x, 0)) == shift_mode
9000 && SUBREG_REG (XEXP (x, 0)) == varop)
9001 varop = XEXP (x, 0);
9002 else if (GET_MODE (varop) != shift_mode)
9003 varop = gen_lowpart_for_combine (shift_mode, varop);
9004
0f41302f 9005 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS
9006 if (GET_CODE (varop) == CLOBBER)
9007 return x ? x : varop;
9008
9009 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9010 if (new != 0)
9011 x = new;
9012 else
9013 {
9014 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9015 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9016
9017 SUBST (XEXP (x, 0), varop);
9018 SUBST (XEXP (x, 1), const_rtx);
9019 }
9020
224eeff2
RK
9021 /* If we have an outer operation and we just made a shift, it is
9022 possible that we could have simplified the shift were it not
9023 for the outer operation. So try to do the simplification
9024 recursively. */
9025
9026 if (outer_op != NIL && GET_CODE (x) == code
9027 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9028 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9029 INTVAL (XEXP (x, 1)));
9030
230d793d
RS
9031 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9032 turn off all the bits that the shift would have turned off. */
9033 if (orig_code == LSHIFTRT && result_mode != shift_mode)
5f4f0e22 9034 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
230d793d
RS
9035 GET_MODE_MASK (result_mode) >> orig_count);
9036
9037 /* Do the remainder of the processing in RESULT_MODE. */
9038 x = gen_lowpart_for_combine (result_mode, x);
9039
9040 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9041 operation. */
9042 if (complement_p)
0c1c8ea6 9043 x = gen_unary (NOT, result_mode, result_mode, x);
230d793d
RS
9044
9045 if (outer_op != NIL)
9046 {
5f4f0e22 9047 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9fa6d012
TG
9048 {
9049 int width = GET_MODE_BITSIZE (result_mode);
9050
9051 outer_const &= GET_MODE_MASK (result_mode);
9052
9053 /* If this would be an entire word for the target, but is not for
9054 the host, then sign-extend on the host so that the number will
9055 look the same way on the host that it would on the target.
9056
9057 For example, when building a 64 bit alpha hosted 32 bit sparc
9058 targeted compiler, then we want the 32 bit unsigned value -1 to be
9059 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
9060 The later confuses the sparc backend. */
9061
9062 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
9063 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
9064 outer_const |= ((HOST_WIDE_INT) (-1) << width);
9065 }
230d793d
RS
9066
9067 if (outer_op == AND)
5f4f0e22 9068 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
230d793d
RS
9069 else if (outer_op == SET)
9070 /* This means that we have determined that the result is
9071 equivalent to a constant. This should be rare. */
5f4f0e22 9072 x = GEN_INT (outer_const);
230d793d 9073 else if (GET_RTX_CLASS (outer_op) == '1')
0c1c8ea6 9074 x = gen_unary (outer_op, result_mode, result_mode, x);
230d793d 9075 else
5f4f0e22 9076 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
230d793d
RS
9077 }
9078
9079 return x;
9080}
9081\f
9082/* Like recog, but we receive the address of a pointer to a new pattern.
9083 We try to match the rtx that the pointer points to.
9084 If that fails, we may try to modify or replace the pattern,
9085 storing the replacement into the same pointer object.
9086
9087 Modifications include deletion or addition of CLOBBERs.
9088
9089 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9090 the CLOBBERs are placed.
9091
9092 The value is the final insn code from the pattern ultimately matched,
9093 or -1. */
9094
9095static int
8e2f6e35 9096recog_for_combine (pnewpat, insn, pnotes)
230d793d
RS
9097 rtx *pnewpat;
9098 rtx insn;
9099 rtx *pnotes;
9100{
9101 register rtx pat = *pnewpat;
9102 int insn_code_number;
9103 int num_clobbers_to_add = 0;
9104 int i;
9105 rtx notes = 0;
9106
974f4146
RK
9107 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9108 we use to indicate that something didn't match. If we find such a
9109 thing, force rejection. */
d96023cf 9110 if (GET_CODE (pat) == PARALLEL)
974f4146 9111 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
d96023cf
RK
9112 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9113 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
974f4146
RK
9114 return -1;
9115
230d793d
RS
9116 /* Is the result of combination a valid instruction? */
9117 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9118
9119 /* If it isn't, there is the possibility that we previously had an insn
9120 that clobbered some register as a side effect, but the combined
9121 insn doesn't need to do that. So try once more without the clobbers
9122 unless this represents an ASM insn. */
9123
9124 if (insn_code_number < 0 && ! check_asm_operands (pat)
9125 && GET_CODE (pat) == PARALLEL)
9126 {
9127 int pos;
9128
9129 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9130 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9131 {
9132 if (i != pos)
9133 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9134 pos++;
9135 }
9136
9137 SUBST_INT (XVECLEN (pat, 0), pos);
9138
9139 if (pos == 1)
9140 pat = XVECEXP (pat, 0, 0);
9141
9142 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9143 }
9144
9145 /* If we had any clobbers to add, make a new pattern than contains
9146 them. Then check to make sure that all of them are dead. */
9147 if (num_clobbers_to_add)
9148 {
38a448ca
RH
9149 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9150 gen_rtvec (GET_CODE (pat) == PARALLEL
9151 ? XVECLEN (pat, 0) + num_clobbers_to_add
9152 : num_clobbers_to_add + 1));
230d793d
RS
9153
9154 if (GET_CODE (pat) == PARALLEL)
9155 for (i = 0; i < XVECLEN (pat, 0); i++)
9156 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9157 else
9158 XVECEXP (newpat, 0, 0) = pat;
9159
9160 add_clobbers (newpat, insn_code_number);
9161
9162 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9163 i < XVECLEN (newpat, 0); i++)
9164 {
9165 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9166 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9167 return -1;
38a448ca
RH
9168 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9169 XEXP (XVECEXP (newpat, 0, i), 0), notes);
230d793d
RS
9170 }
9171 pat = newpat;
9172 }
9173
9174 *pnewpat = pat;
9175 *pnotes = notes;
9176
9177 return insn_code_number;
9178}
9179\f
9180/* Like gen_lowpart but for use by combine. In combine it is not possible
9181 to create any new pseudoregs. However, it is safe to create
9182 invalid memory addresses, because combine will try to recognize
9183 them and all they will do is make the combine attempt fail.
9184
9185 If for some reason this cannot do its job, an rtx
9186 (clobber (const_int 0)) is returned.
9187 An insn containing that will not be recognized. */
9188
9189#undef gen_lowpart
9190
9191static rtx
9192gen_lowpart_for_combine (mode, x)
9193 enum machine_mode mode;
9194 register rtx x;
9195{
9196 rtx result;
9197
9198 if (GET_MODE (x) == mode)
9199 return x;
9200
eae957a8
RK
9201 /* We can only support MODE being wider than a word if X is a
9202 constant integer or has a mode the same size. */
9203
9204 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9205 && ! ((GET_MODE (x) == VOIDmode
9206 && (GET_CODE (x) == CONST_INT
9207 || GET_CODE (x) == CONST_DOUBLE))
9208 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
38a448ca 9209 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS
9210
9211 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9212 won't know what to do. So we will strip off the SUBREG here and
9213 process normally. */
9214 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9215 {
9216 x = SUBREG_REG (x);
9217 if (GET_MODE (x) == mode)
9218 return x;
9219 }
9220
9221 result = gen_lowpart_common (mode, x);
64bf47a2
RK
9222 if (result != 0
9223 && GET_CODE (result) == SUBREG
9224 && GET_CODE (SUBREG_REG (result)) == REG
9225 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9226 && (GET_MODE_SIZE (GET_MODE (result))
9227 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
b1f21e0a 9228 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
64bf47a2 9229
230d793d
RS
9230 if (result)
9231 return result;
9232
9233 if (GET_CODE (x) == MEM)
9234 {
9235 register int offset = 0;
9236 rtx new;
9237
9238 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9239 address. */
9240 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
38a448ca 9241 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS
9242
9243 /* If we want to refer to something bigger than the original memref,
9244 generate a perverse subreg instead. That will force a reload
9245 of the original memref X. */
9246 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
38a448ca 9247 return gen_rtx_SUBREG (mode, x, 0);
230d793d 9248
f76b9db2
ILT
9249 if (WORDS_BIG_ENDIAN)
9250 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9251 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9252 if (BYTES_BIG_ENDIAN)
9253 {
9254 /* Adjust the address so that the address-after-the-data is
9255 unchanged. */
9256 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9257 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9258 }
38a448ca 9259 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
230d793d 9260 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
c6df88cb 9261 MEM_COPY_ATTRIBUTES (new, x);
230d793d
RS
9262 return new;
9263 }
9264
9265 /* If X is a comparison operator, rewrite it in a new mode. This
9266 probably won't match, but may allow further simplifications. */
9267 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9268 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9269
9270 /* If we couldn't simplify X any other way, just enclose it in a
9271 SUBREG. Normally, this SUBREG won't match, but some patterns may
a7c99304 9272 include an explicit SUBREG or we may simplify it further in combine. */
230d793d 9273 else
dfbe1b2f
RK
9274 {
9275 int word = 0;
9276
9277 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9278 word = ((GET_MODE_SIZE (GET_MODE (x))
9279 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9280 / UNITS_PER_WORD);
38a448ca 9281 return gen_rtx_SUBREG (mode, x, word);
dfbe1b2f 9282 }
230d793d
RS
9283}
9284\f
9285/* Make an rtx expression. This is a subset of gen_rtx and only supports
9286 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9287
9288 If the identical expression was previously in the insn (in the undobuf),
9289 it will be returned. Only if it is not found will a new expression
9290 be made. */
9291
9292/*VARARGS2*/
9293static rtx
4f90e4a0 9294gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
230d793d 9295{
5148a72b 9296#ifndef ANSI_PROTOTYPES
230d793d
RS
9297 enum rtx_code code;
9298 enum machine_mode mode;
4f90e4a0
RK
9299#endif
9300 va_list p;
230d793d
RS
9301 int n_args;
9302 rtx args[3];
b729186a 9303 int j;
230d793d
RS
9304 char *fmt;
9305 rtx rt;
241cea85 9306 struct undo *undo;
230d793d 9307
4f90e4a0
RK
9308 VA_START (p, mode);
9309
5148a72b 9310#ifndef ANSI_PROTOTYPES
230d793d
RS
9311 code = va_arg (p, enum rtx_code);
9312 mode = va_arg (p, enum machine_mode);
4f90e4a0
RK
9313#endif
9314
230d793d
RS
9315 n_args = GET_RTX_LENGTH (code);
9316 fmt = GET_RTX_FORMAT (code);
9317
9318 if (n_args == 0 || n_args > 3)
9319 abort ();
9320
9321 /* Get each arg and verify that it is supposed to be an expression. */
9322 for (j = 0; j < n_args; j++)
9323 {
9324 if (*fmt++ != 'e')
9325 abort ();
9326
9327 args[j] = va_arg (p, rtx);
9328 }
9329
9330 /* See if this is in undobuf. Be sure we don't use objects that came
9331 from another insn; this could produce circular rtl structures. */
9332
241cea85
RK
9333 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9334 if (!undo->is_int
9335 && GET_CODE (undo->old_contents.r) == code
9336 && GET_MODE (undo->old_contents.r) == mode)
230d793d
RS
9337 {
9338 for (j = 0; j < n_args; j++)
241cea85 9339 if (XEXP (undo->old_contents.r, j) != args[j])
230d793d
RS
9340 break;
9341
9342 if (j == n_args)
241cea85 9343 return undo->old_contents.r;
230d793d
RS
9344 }
9345
9346 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9347 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9348 rt = rtx_alloc (code);
9349 PUT_MODE (rt, mode);
9350 XEXP (rt, 0) = args[0];
9351 if (n_args > 1)
9352 {
9353 XEXP (rt, 1) = args[1];
9354 if (n_args > 2)
9355 XEXP (rt, 2) = args[2];
9356 }
9357 return rt;
9358}
9359
9360/* These routines make binary and unary operations by first seeing if they
9361 fold; if not, a new expression is allocated. */
9362
9363static rtx
9364gen_binary (code, mode, op0, op1)
9365 enum rtx_code code;
9366 enum machine_mode mode;
9367 rtx op0, op1;
9368{
9369 rtx result;
1a26b032
RK
9370 rtx tem;
9371
9372 if (GET_RTX_CLASS (code) == 'c'
9373 && (GET_CODE (op0) == CONST_INT
9374 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9375 tem = op0, op0 = op1, op1 = tem;
230d793d
RS
9376
9377 if (GET_RTX_CLASS (code) == '<')
9378 {
9379 enum machine_mode op_mode = GET_MODE (op0);
9210df58
RK
9380
9381 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
0f41302f 9382 just (REL_OP X Y). */
9210df58
RK
9383 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9384 {
9385 op1 = XEXP (op0, 1);
9386 op0 = XEXP (op0, 0);
9387 op_mode = GET_MODE (op0);
9388 }
9389
230d793d
RS
9390 if (op_mode == VOIDmode)
9391 op_mode = GET_MODE (op1);
9392 result = simplify_relational_operation (code, op_mode, op0, op1);
9393 }
9394 else
9395 result = simplify_binary_operation (code, mode, op0, op1);
9396
9397 if (result)
9398 return result;
9399
9400 /* Put complex operands first and constants second. */
9401 if (GET_RTX_CLASS (code) == 'c'
9402 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9403 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9404 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9405 || (GET_CODE (op0) == SUBREG
9406 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9407 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9408 return gen_rtx_combine (code, mode, op1, op0);
9409
e5e809f4
JL
9410 /* If we are turning off bits already known off in OP0, we need not do
9411 an AND. */
9412 else if (code == AND && GET_CODE (op1) == CONST_INT
9413 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9414 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9415 return op0;
9416
230d793d
RS
9417 return gen_rtx_combine (code, mode, op0, op1);
9418}
9419
9420static rtx
0c1c8ea6 9421gen_unary (code, mode, op0_mode, op0)
230d793d 9422 enum rtx_code code;
0c1c8ea6 9423 enum machine_mode mode, op0_mode;
230d793d
RS
9424 rtx op0;
9425{
0c1c8ea6 9426 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
230d793d
RS
9427
9428 if (result)
9429 return result;
9430
9431 return gen_rtx_combine (code, mode, op0);
9432}
9433\f
9434/* Simplify a comparison between *POP0 and *POP1 where CODE is the
9435 comparison code that will be tested.
9436
9437 The result is a possibly different comparison code to use. *POP0 and
9438 *POP1 may be updated.
9439
9440 It is possible that we might detect that a comparison is either always
9441 true or always false. However, we do not perform general constant
5089e22e 9442 folding in combine, so this knowledge isn't useful. Such tautologies
230d793d
RS
9443 should have been detected earlier. Hence we ignore all such cases. */
9444
9445static enum rtx_code
9446simplify_comparison (code, pop0, pop1)
9447 enum rtx_code code;
9448 rtx *pop0;
9449 rtx *pop1;
9450{
9451 rtx op0 = *pop0;
9452 rtx op1 = *pop1;
9453 rtx tem, tem1;
9454 int i;
9455 enum machine_mode mode, tmode;
9456
9457 /* Try a few ways of applying the same transformation to both operands. */
9458 while (1)
9459 {
3a19aabc
RK
9460#ifndef WORD_REGISTER_OPERATIONS
9461 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9462 so check specially. */
9463 if (code != GTU && code != GEU && code != LTU && code != LEU
9464 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9465 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9466 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9467 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9468 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9469 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
ad25ba17 9470 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
3a19aabc
RK
9471 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9472 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9473 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9474 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9475 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9476 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9477 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9478 && (INTVAL (XEXP (op0, 1))
9479 == (GET_MODE_BITSIZE (GET_MODE (op0))
9480 - (GET_MODE_BITSIZE
9481 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9482 {
9483 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9484 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9485 }
9486#endif
9487
230d793d
RS
9488 /* If both operands are the same constant shift, see if we can ignore the
9489 shift. We can if the shift is a rotate or if the bits shifted out of
951553af 9490 this shift are known to be zero for both inputs and if the type of
230d793d 9491 comparison is compatible with the shift. */
67232b23
RK
9492 if (GET_CODE (op0) == GET_CODE (op1)
9493 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9494 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
45620ed4 9495 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
67232b23
RK
9496 && (code != GT && code != LT && code != GE && code != LE))
9497 || (GET_CODE (op0) == ASHIFTRT
9498 && (code != GTU && code != LTU
9499 && code != GEU && code != GEU)))
9500 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9501 && INTVAL (XEXP (op0, 1)) >= 0
9502 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9503 && XEXP (op0, 1) == XEXP (op1, 1))
230d793d
RS
9504 {
9505 enum machine_mode mode = GET_MODE (op0);
5f4f0e22 9506 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS
9507 int shift_count = INTVAL (XEXP (op0, 1));
9508
9509 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9510 mask &= (mask >> shift_count) << shift_count;
45620ed4 9511 else if (GET_CODE (op0) == ASHIFT)
230d793d
RS
9512 mask = (mask & (mask << shift_count)) >> shift_count;
9513
951553af
RK
9514 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9515 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
230d793d
RS
9516 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9517 else
9518 break;
9519 }
9520
9521 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9522 SUBREGs are of the same mode, and, in both cases, the AND would
9523 be redundant if the comparison was done in the narrower mode,
9524 do the comparison in the narrower mode (e.g., we are AND'ing with 1
951553af
RK
9525 and the operand's possibly nonzero bits are 0xffffff01; in that case
9526 if we only care about QImode, we don't need the AND). This case
9527 occurs if the output mode of an scc insn is not SImode and
7e4dc511
RK
9528 STORE_FLAG_VALUE == 1 (e.g., the 386).
9529
9530 Similarly, check for a case where the AND's are ZERO_EXTEND
9531 operations from some narrower mode even though a SUBREG is not
9532 present. */
230d793d
RS
9533
9534 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9535 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7e4dc511 9536 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
230d793d 9537 {
7e4dc511
RK
9538 rtx inner_op0 = XEXP (op0, 0);
9539 rtx inner_op1 = XEXP (op1, 0);
9540 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9541 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9542 int changed = 0;
9543
9544 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9545 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9546 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9547 && (GET_MODE (SUBREG_REG (inner_op0))
9548 == GET_MODE (SUBREG_REG (inner_op1)))
729a2bc6 9549 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
7e4dc511 9550 <= HOST_BITS_PER_WIDE_INT)
01c82bbb 9551 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
729a2bc6 9552 GET_MODE (SUBREG_REG (inner_op0)))))
01c82bbb
RK
9553 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9554 GET_MODE (SUBREG_REG (inner_op1))))))
7e4dc511
RK
9555 {
9556 op0 = SUBREG_REG (inner_op0);
9557 op1 = SUBREG_REG (inner_op1);
9558
9559 /* The resulting comparison is always unsigned since we masked
0f41302f 9560 off the original sign bit. */
7e4dc511
RK
9561 code = unsigned_condition (code);
9562
9563 changed = 1;
9564 }
230d793d 9565
7e4dc511
RK
9566 else if (c0 == c1)
9567 for (tmode = GET_CLASS_NARROWEST_MODE
9568 (GET_MODE_CLASS (GET_MODE (op0)));
9569 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
e51712db 9570 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
7e4dc511
RK
9571 {
9572 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9573 op1 = gen_lowpart_for_combine (tmode, inner_op1);
66415c8b 9574 code = unsigned_condition (code);
7e4dc511
RK
9575 changed = 1;
9576 break;
9577 }
9578
9579 if (! changed)
9580 break;
230d793d 9581 }
3a19aabc 9582
ad25ba17
RK
9583 /* If both operands are NOT, we can strip off the outer operation
9584 and adjust the comparison code for swapped operands; similarly for
9585 NEG, except that this must be an equality comparison. */
9586 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9587 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9588 && (code == EQ || code == NE)))
9589 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
3a19aabc 9590
230d793d
RS
9591 else
9592 break;
9593 }
9594
9595 /* If the first operand is a constant, swap the operands and adjust the
3aceff0d
RK
9596 comparison code appropriately, but don't do this if the second operand
9597 is already a constant integer. */
9598 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
230d793d
RS
9599 {
9600 tem = op0, op0 = op1, op1 = tem;
9601 code = swap_condition (code);
9602 }
9603
9604 /* We now enter a loop during which we will try to simplify the comparison.
9605 For the most part, we only are concerned with comparisons with zero,
9606 but some things may really be comparisons with zero but not start
9607 out looking that way. */
9608
9609 while (GET_CODE (op1) == CONST_INT)
9610 {
9611 enum machine_mode mode = GET_MODE (op0);
9612 int mode_width = GET_MODE_BITSIZE (mode);
5f4f0e22 9613 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS
9614 int equality_comparison_p;
9615 int sign_bit_comparison_p;
9616 int unsigned_comparison_p;
5f4f0e22 9617 HOST_WIDE_INT const_op;
230d793d
RS
9618
9619 /* We only want to handle integral modes. This catches VOIDmode,
9620 CCmode, and the floating-point modes. An exception is that we
9621 can handle VOIDmode if OP0 is a COMPARE or a comparison
9622 operation. */
9623
9624 if (GET_MODE_CLASS (mode) != MODE_INT
9625 && ! (mode == VOIDmode
9626 && (GET_CODE (op0) == COMPARE
9627 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9628 break;
9629
9630 /* Get the constant we are comparing against and turn off all bits
9631 not on in our mode. */
9632 const_op = INTVAL (op1);
5f4f0e22 9633 if (mode_width <= HOST_BITS_PER_WIDE_INT)
4803a34a 9634 const_op &= mask;
230d793d
RS
9635
9636 /* If we are comparing against a constant power of two and the value
951553af 9637 being compared can only have that single bit nonzero (e.g., it was
230d793d
RS
9638 `and'ed with that bit), we can replace this with a comparison
9639 with zero. */
9640 if (const_op
9641 && (code == EQ || code == NE || code == GE || code == GEU
9642 || code == LT || code == LTU)
5f4f0e22 9643 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 9644 && exact_log2 (const_op) >= 0
e51712db 9645 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
230d793d
RS
9646 {
9647 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9648 op1 = const0_rtx, const_op = 0;
9649 }
9650
d0ab8cd3
RK
9651 /* Similarly, if we are comparing a value known to be either -1 or
9652 0 with -1, change it to the opposite comparison against zero. */
9653
9654 if (const_op == -1
9655 && (code == EQ || code == NE || code == GT || code == LE
9656 || code == GEU || code == LTU)
9657 && num_sign_bit_copies (op0, mode) == mode_width)
9658 {
9659 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9660 op1 = const0_rtx, const_op = 0;
9661 }
9662
230d793d 9663 /* Do some canonicalizations based on the comparison code. We prefer
4803a34a
RK
9664 comparisons against zero and then prefer equality comparisons.
9665 If we can reduce the size of a constant, we will do that too. */
230d793d
RS
9666
9667 switch (code)
9668 {
9669 case LT:
4803a34a
RK
9670 /* < C is equivalent to <= (C - 1) */
9671 if (const_op > 0)
230d793d 9672 {
4803a34a 9673 const_op -= 1;
5f4f0e22 9674 op1 = GEN_INT (const_op);
230d793d
RS
9675 code = LE;
9676 /* ... fall through to LE case below. */
9677 }
9678 else
9679 break;
9680
9681 case LE:
4803a34a
RK
9682 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9683 if (const_op < 0)
9684 {
9685 const_op += 1;
5f4f0e22 9686 op1 = GEN_INT (const_op);
4803a34a
RK
9687 code = LT;
9688 }
230d793d
RS
9689
9690 /* If we are doing a <= 0 comparison on a value known to have
9691 a zero sign bit, we can replace this with == 0. */
9692 else if (const_op == 0
5f4f0e22 9693 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9694 && (nonzero_bits (op0, mode)
5f4f0e22 9695 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS
9696 code = EQ;
9697 break;
9698
9699 case GE:
0f41302f 9700 /* >= C is equivalent to > (C - 1). */
4803a34a 9701 if (const_op > 0)
230d793d 9702 {
4803a34a 9703 const_op -= 1;
5f4f0e22 9704 op1 = GEN_INT (const_op);
230d793d
RS
9705 code = GT;
9706 /* ... fall through to GT below. */
9707 }
9708 else
9709 break;
9710
9711 case GT:
4803a34a
RK
9712 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9713 if (const_op < 0)
9714 {
9715 const_op += 1;
5f4f0e22 9716 op1 = GEN_INT (const_op);
4803a34a
RK
9717 code = GE;
9718 }
230d793d
RS
9719
9720 /* If we are doing a > 0 comparison on a value known to have
9721 a zero sign bit, we can replace this with != 0. */
9722 else if (const_op == 0
5f4f0e22 9723 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9724 && (nonzero_bits (op0, mode)
5f4f0e22 9725 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS
9726 code = NE;
9727 break;
9728
230d793d 9729 case LTU:
4803a34a
RK
9730 /* < C is equivalent to <= (C - 1). */
9731 if (const_op > 0)
9732 {
9733 const_op -= 1;
5f4f0e22 9734 op1 = GEN_INT (const_op);
4803a34a 9735 code = LEU;
0f41302f 9736 /* ... fall through ... */
4803a34a 9737 }
d0ab8cd3
RK
9738
9739 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
f77aada2
JW
9740 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9741 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK
9742 {
9743 const_op = 0, op1 = const0_rtx;
9744 code = GE;
9745 break;
9746 }
4803a34a
RK
9747 else
9748 break;
230d793d
RS
9749
9750 case LEU:
9751 /* unsigned <= 0 is equivalent to == 0 */
9752 if (const_op == 0)
9753 code = EQ;
d0ab8cd3 9754
0f41302f 9755 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
f77aada2
JW
9756 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9757 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK
9758 {
9759 const_op = 0, op1 = const0_rtx;
9760 code = GE;
9761 }
230d793d
RS
9762 break;
9763
4803a34a
RK
9764 case GEU:
9765 /* >= C is equivalent to < (C - 1). */
9766 if (const_op > 1)
9767 {
9768 const_op -= 1;
5f4f0e22 9769 op1 = GEN_INT (const_op);
4803a34a 9770 code = GTU;
0f41302f 9771 /* ... fall through ... */
4803a34a 9772 }
d0ab8cd3
RK
9773
9774 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
f77aada2
JW
9775 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9776 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK
9777 {
9778 const_op = 0, op1 = const0_rtx;
9779 code = LT;
8b2e69e1 9780 break;
d0ab8cd3 9781 }
4803a34a
RK
9782 else
9783 break;
9784
230d793d
RS
9785 case GTU:
9786 /* unsigned > 0 is equivalent to != 0 */
9787 if (const_op == 0)
9788 code = NE;
d0ab8cd3
RK
9789
9790 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
f77aada2
JW
9791 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9792 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK
9793 {
9794 const_op = 0, op1 = const0_rtx;
9795 code = LT;
9796 }
230d793d 9797 break;
e9a25f70
JL
9798
9799 default:
9800 break;
230d793d
RS
9801 }
9802
9803 /* Compute some predicates to simplify code below. */
9804
9805 equality_comparison_p = (code == EQ || code == NE);
9806 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9807 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9808 || code == LEU);
9809
6139ff20
RK
9810 /* If this is a sign bit comparison and we can do arithmetic in
9811 MODE, say that we will only be needing the sign bit of OP0. */
9812 if (sign_bit_comparison_p
9813 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9814 op0 = force_to_mode (op0, mode,
9815 ((HOST_WIDE_INT) 1
9816 << (GET_MODE_BITSIZE (mode) - 1)),
e3d616e3 9817 NULL_RTX, 0);
6139ff20 9818
230d793d
RS
9819 /* Now try cases based on the opcode of OP0. If none of the cases
9820 does a "continue", we exit this loop immediately after the
9821 switch. */
9822
9823 switch (GET_CODE (op0))
9824 {
9825 case ZERO_EXTRACT:
9826 /* If we are extracting a single bit from a variable position in
9827 a constant that has only a single bit set and are comparing it
9828 with zero, we can convert this into an equality comparison
d7cd794f 9829 between the position and the location of the single bit. */
230d793d 9830
230d793d
RS
9831 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9832 && XEXP (op0, 1) == const1_rtx
9833 && equality_comparison_p && const_op == 0
d7cd794f 9834 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
230d793d 9835 {
f76b9db2 9836 if (BITS_BIG_ENDIAN)
0d8e55d8 9837 {
d7cd794f 9838#ifdef HAVE_extzv
0d8e55d8
JL
9839 mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
9840 if (mode == VOIDmode)
9841 mode = word_mode;
9842 i = (GET_MODE_BITSIZE (mode) - 1 - i);
d7cd794f 9843#else
0d8e55d8 9844 i = BITS_PER_WORD - 1 - i;
230d793d 9845#endif
0d8e55d8 9846 }
230d793d
RS
9847
9848 op0 = XEXP (op0, 2);
5f4f0e22 9849 op1 = GEN_INT (i);
230d793d
RS
9850 const_op = i;
9851
9852 /* Result is nonzero iff shift count is equal to I. */
9853 code = reverse_condition (code);
9854 continue;
9855 }
230d793d 9856
0f41302f 9857 /* ... fall through ... */
230d793d
RS
9858
9859 case SIGN_EXTRACT:
9860 tem = expand_compound_operation (op0);
9861 if (tem != op0)
9862 {
9863 op0 = tem;
9864 continue;
9865 }
9866 break;
9867
9868 case NOT:
9869 /* If testing for equality, we can take the NOT of the constant. */
9870 if (equality_comparison_p
9871 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9872 {
9873 op0 = XEXP (op0, 0);
9874 op1 = tem;
9875 continue;
9876 }
9877
9878 /* If just looking at the sign bit, reverse the sense of the
9879 comparison. */
9880 if (sign_bit_comparison_p)
9881 {
9882 op0 = XEXP (op0, 0);
9883 code = (code == GE ? LT : GE);
9884 continue;
9885 }
9886 break;
9887
9888 case NEG:
9889 /* If testing for equality, we can take the NEG of the constant. */
9890 if (equality_comparison_p
9891 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9892 {
9893 op0 = XEXP (op0, 0);
9894 op1 = tem;
9895 continue;
9896 }
9897
9898 /* The remaining cases only apply to comparisons with zero. */
9899 if (const_op != 0)
9900 break;
9901
9902 /* When X is ABS or is known positive,
9903 (neg X) is < 0 if and only if X != 0. */
9904
9905 if (sign_bit_comparison_p
9906 && (GET_CODE (XEXP (op0, 0)) == ABS
5f4f0e22 9907 || (mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9908 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 9909 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
230d793d
RS
9910 {
9911 op0 = XEXP (op0, 0);
9912 code = (code == LT ? NE : EQ);
9913 continue;
9914 }
9915
3bed8141 9916 /* If we have NEG of something whose two high-order bits are the
0f41302f 9917 same, we know that "(-a) < 0" is equivalent to "a > 0". */
3bed8141 9918 if (num_sign_bit_copies (op0, mode) >= 2)
230d793d
RS
9919 {
9920 op0 = XEXP (op0, 0);
9921 code = swap_condition (code);
9922 continue;
9923 }
9924 break;
9925
9926 case ROTATE:
9927 /* If we are testing equality and our count is a constant, we
9928 can perform the inverse operation on our RHS. */
9929 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9930 && (tem = simplify_binary_operation (ROTATERT, mode,
9931 op1, XEXP (op0, 1))) != 0)
9932 {
9933 op0 = XEXP (op0, 0);
9934 op1 = tem;
9935 continue;
9936 }
9937
9938 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9939 a particular bit. Convert it to an AND of a constant of that
9940 bit. This will be converted into a ZERO_EXTRACT. */
9941 if (const_op == 0 && sign_bit_comparison_p
9942 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 9943 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 9944 {
5f4f0e22
CH
9945 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9946 ((HOST_WIDE_INT) 1
9947 << (mode_width - 1
9948 - INTVAL (XEXP (op0, 1)))));
230d793d
RS
9949 code = (code == LT ? NE : EQ);
9950 continue;
9951 }
9952
0f41302f 9953 /* ... fall through ... */
230d793d
RS
9954
9955 case ABS:
9956 /* ABS is ignorable inside an equality comparison with zero. */
9957 if (const_op == 0 && equality_comparison_p)
9958 {
9959 op0 = XEXP (op0, 0);
9960 continue;
9961 }
9962 break;
9963
9964
9965 case SIGN_EXTEND:
9966 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9967 to (compare FOO CONST) if CONST fits in FOO's mode and we
9968 are either testing inequality or have an unsigned comparison
9969 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9970 if (! unsigned_comparison_p
9971 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH
9972 <= HOST_BITS_PER_WIDE_INT)
9973 && ((unsigned HOST_WIDE_INT) const_op
e51712db 9974 < (((unsigned HOST_WIDE_INT) 1
5f4f0e22 9975 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
230d793d
RS
9976 {
9977 op0 = XEXP (op0, 0);
9978 continue;
9979 }
9980 break;
9981
9982 case SUBREG:
a687e897 9983 /* Check for the case where we are comparing A - C1 with C2,
abc95ed3 9984 both constants are smaller than 1/2 the maximum positive
a687e897
RK
9985 value in MODE, and the comparison is equality or unsigned.
9986 In that case, if A is either zero-extended to MODE or has
9987 sufficient sign bits so that the high-order bit in MODE
9988 is a copy of the sign in the inner mode, we can prove that it is
9989 safe to do the operation in the wider mode. This simplifies
9990 many range checks. */
9991
9992 if (mode_width <= HOST_BITS_PER_WIDE_INT
9993 && subreg_lowpart_p (op0)
9994 && GET_CODE (SUBREG_REG (op0)) == PLUS
9995 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9996 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9997 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
e51712db 9998 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
adb7a1cb 9999 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
951553af
RK
10000 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10001 GET_MODE (SUBREG_REG (op0)))
a687e897
RK
10002 & ~ GET_MODE_MASK (mode))
10003 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10004 GET_MODE (SUBREG_REG (op0)))
10005 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10006 - GET_MODE_BITSIZE (mode)))))
10007 {
10008 op0 = SUBREG_REG (op0);
10009 continue;
10010 }
10011
fe0cf571
RK
10012 /* If the inner mode is narrower and we are extracting the low part,
10013 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10014 if (subreg_lowpart_p (op0)
89f1c7f2
RS
10015 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10016 /* Fall through */ ;
10017 else
230d793d
RS
10018 break;
10019
0f41302f 10020 /* ... fall through ... */
230d793d
RS
10021
10022 case ZERO_EXTEND:
10023 if ((unsigned_comparison_p || equality_comparison_p)
10024 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH
10025 <= HOST_BITS_PER_WIDE_INT)
10026 && ((unsigned HOST_WIDE_INT) const_op
230d793d
RS
10027 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10028 {
10029 op0 = XEXP (op0, 0);
10030 continue;
10031 }
10032 break;
10033
10034 case PLUS:
20fdd649 10035 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
5089e22e 10036 this for equality comparisons due to pathological cases involving
230d793d 10037 overflows. */
20fdd649
RK
10038 if (equality_comparison_p
10039 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10040 op1, XEXP (op0, 1))))
230d793d
RS
10041 {
10042 op0 = XEXP (op0, 0);
10043 op1 = tem;
10044 continue;
10045 }
10046
10047 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10048 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10049 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10050 {
10051 op0 = XEXP (XEXP (op0, 0), 0);
10052 code = (code == LT ? EQ : NE);
10053 continue;
10054 }
10055 break;
10056
10057 case MINUS:
20fdd649
RK
10058 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10059 (eq B (minus A C)), whichever simplifies. We can only do
10060 this for equality comparisons due to pathological cases involving
10061 overflows. */
10062 if (equality_comparison_p
10063 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10064 XEXP (op0, 1), op1)))
10065 {
10066 op0 = XEXP (op0, 0);
10067 op1 = tem;
10068 continue;
10069 }
10070
10071 if (equality_comparison_p
10072 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10073 XEXP (op0, 0), op1)))
10074 {
10075 op0 = XEXP (op0, 1);
10076 op1 = tem;
10077 continue;
10078 }
10079
230d793d
RS
10080 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10081 of bits in X minus 1, is one iff X > 0. */
10082 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10083 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10084 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10085 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10086 {
10087 op0 = XEXP (op0, 1);
10088 code = (code == GE ? LE : GT);
10089 continue;
10090 }
10091 break;
10092
10093 case XOR:
10094 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10095 if C is zero or B is a constant. */
10096 if (equality_comparison_p
10097 && 0 != (tem = simplify_binary_operation (XOR, mode,
10098 XEXP (op0, 1), op1)))
10099 {
10100 op0 = XEXP (op0, 0);
10101 op1 = tem;
10102 continue;
10103 }
10104 break;
10105
10106 case EQ: case NE:
10107 case LT: case LTU: case LE: case LEU:
10108 case GT: case GTU: case GE: case GEU:
10109 /* We can't do anything if OP0 is a condition code value, rather
10110 than an actual data value. */
10111 if (const_op != 0
10112#ifdef HAVE_cc0
10113 || XEXP (op0, 0) == cc0_rtx
10114#endif
10115 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10116 break;
10117
10118 /* Get the two operands being compared. */
10119 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10120 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10121 else
10122 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10123
10124 /* Check for the cases where we simply want the result of the
10125 earlier test or the opposite of that result. */
10126 if (code == NE
10127 || (code == EQ && reversible_comparison_p (op0))
5f4f0e22 10128 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
3f508eca 10129 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
230d793d 10130 && (STORE_FLAG_VALUE
5f4f0e22
CH
10131 & (((HOST_WIDE_INT) 1
10132 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
230d793d
RS
10133 && (code == LT
10134 || (code == GE && reversible_comparison_p (op0)))))
10135 {
10136 code = (code == LT || code == NE
10137 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10138 op0 = tem, op1 = tem1;
10139 continue;
10140 }
10141 break;
10142
10143 case IOR:
10144 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10145 iff X <= 0. */
10146 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10147 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10148 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10149 {
10150 op0 = XEXP (op0, 1);
10151 code = (code == GE ? GT : LE);
10152 continue;
10153 }
10154 break;
10155
10156 case AND:
10157 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10158 will be converted to a ZERO_EXTRACT later. */
10159 if (const_op == 0 && equality_comparison_p
45620ed4 10160 && GET_CODE (XEXP (op0, 0)) == ASHIFT
230d793d
RS
10161 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10162 {
10163 op0 = simplify_and_const_int
10164 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10165 XEXP (op0, 1),
10166 XEXP (XEXP (op0, 0), 1)),
5f4f0e22 10167 (HOST_WIDE_INT) 1);
230d793d
RS
10168 continue;
10169 }
10170
10171 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10172 zero and X is a comparison and C1 and C2 describe only bits set
10173 in STORE_FLAG_VALUE, we can compare with X. */
10174 if (const_op == 0 && equality_comparison_p
5f4f0e22 10175 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d
RS
10176 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10177 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10178 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10179 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
5f4f0e22 10180 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS
10181 {
10182 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10183 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10184 if ((~ STORE_FLAG_VALUE & mask) == 0
10185 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10186 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10187 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10188 {
10189 op0 = XEXP (XEXP (op0, 0), 0);
10190 continue;
10191 }
10192 }
10193
10194 /* If we are doing an equality comparison of an AND of a bit equal
10195 to the sign bit, replace this with a LT or GE comparison of
10196 the underlying value. */
10197 if (equality_comparison_p
10198 && const_op == 0
10199 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10200 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 10201 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
e51712db 10202 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
230d793d
RS
10203 {
10204 op0 = XEXP (op0, 0);
10205 code = (code == EQ ? GE : LT);
10206 continue;
10207 }
10208
10209 /* If this AND operation is really a ZERO_EXTEND from a narrower
10210 mode, the constant fits within that mode, and this is either an
10211 equality or unsigned comparison, try to do this comparison in
10212 the narrower mode. */
10213 if ((equality_comparison_p || unsigned_comparison_p)
10214 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10215 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10216 & GET_MODE_MASK (mode))
10217 + 1)) >= 0
10218 && const_op >> i == 0
10219 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10220 {
10221 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10222 continue;
10223 }
e5e809f4
JL
10224
10225 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10226 in both M1 and M2 and the SUBREG is either paradoxical or
10227 represents the low part, permute the SUBREG and the AND and
10228 try again. */
10229 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10230 && ((mode_width
10231 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
9ec36da5
JL
10232#ifdef WORD_REGISTER_OPERATIONS
10233 || subreg_lowpart_p (XEXP (op0, 0))
10234#endif
10235 )
adc05e6c
JL
10236#ifndef WORD_REGISTER_OPERATIONS
10237 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10238 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10239 As originally written the upper bits have a defined value
10240 due to the AND operation. However, if we commute the AND
10241 inside the SUBREG then they no longer have defined values
10242 and the meaning of the code has been changed. */
10243 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10244 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10245#endif
e5e809f4
JL
10246 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10247 && mode_width <= HOST_BITS_PER_WIDE_INT
10248 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10249 <= HOST_BITS_PER_WIDE_INT)
10250 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10251 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
9ec36da5 10252 & INTVAL (XEXP (op0, 1)))
e51712db
KG
10253 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10254 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
9ec36da5 10255 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
e5e809f4
JL
10256
10257 {
10258 op0
10259 = gen_lowpart_for_combine
10260 (mode,
10261 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10262 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10263 continue;
10264 }
10265
230d793d
RS
10266 break;
10267
10268 case ASHIFT:
45620ed4 10269 /* If we have (compare (ashift FOO N) (const_int C)) and
230d793d 10270 the high order N bits of FOO (N+1 if an inequality comparison)
951553af 10271 are known to be zero, we can do this by comparing FOO with C
230d793d
RS
10272 shifted right N bits so long as the low-order N bits of C are
10273 zero. */
10274 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10275 && INTVAL (XEXP (op0, 1)) >= 0
10276 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
5f4f0e22
CH
10277 < HOST_BITS_PER_WIDE_INT)
10278 && ((const_op
34785d05 10279 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
5f4f0e22 10280 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10281 && (nonzero_bits (XEXP (op0, 0), mode)
230d793d
RS
10282 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10283 + ! equality_comparison_p))) == 0)
10284 {
10285 const_op >>= INTVAL (XEXP (op0, 1));
5f4f0e22 10286 op1 = GEN_INT (const_op);
230d793d
RS
10287 op0 = XEXP (op0, 0);
10288 continue;
10289 }
10290
dfbe1b2f 10291 /* If we are doing a sign bit comparison, it means we are testing
230d793d 10292 a particular bit. Convert it to the appropriate AND. */
dfbe1b2f 10293 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10294 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 10295 {
5f4f0e22
CH
10296 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10297 ((HOST_WIDE_INT) 1
10298 << (mode_width - 1
10299 - INTVAL (XEXP (op0, 1)))));
230d793d
RS
10300 code = (code == LT ? NE : EQ);
10301 continue;
10302 }
dfbe1b2f
RK
10303
10304 /* If this an equality comparison with zero and we are shifting
10305 the low bit to the sign bit, we can convert this to an AND of the
10306 low-order bit. */
10307 if (const_op == 0 && equality_comparison_p
10308 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10309 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10310 {
5f4f0e22
CH
10311 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10312 (HOST_WIDE_INT) 1);
dfbe1b2f
RK
10313 continue;
10314 }
230d793d
RS
10315 break;
10316
10317 case ASHIFTRT:
d0ab8cd3
RK
10318 /* If this is an equality comparison with zero, we can do this
10319 as a logical shift, which might be much simpler. */
10320 if (equality_comparison_p && const_op == 0
10321 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10322 {
10323 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10324 XEXP (op0, 0),
10325 INTVAL (XEXP (op0, 1)));
10326 continue;
10327 }
10328
230d793d
RS
10329 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10330 do the comparison in a narrower mode. */
10331 if (! unsigned_comparison_p
10332 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10333 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10334 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10335 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
22331794 10336 MODE_INT, 1)) != BLKmode
5f4f0e22
CH
10337 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10338 || ((unsigned HOST_WIDE_INT) - const_op
10339 <= GET_MODE_MASK (tmode))))
230d793d
RS
10340 {
10341 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10342 continue;
10343 }
10344
0f41302f 10345 /* ... fall through ... */
230d793d
RS
10346 case LSHIFTRT:
10347 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
951553af 10348 the low order N bits of FOO are known to be zero, we can do this
230d793d
RS
10349 by comparing FOO with C shifted left N bits so long as no
10350 overflow occurs. */
10351 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10352 && INTVAL (XEXP (op0, 1)) >= 0
5f4f0e22
CH
10353 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10354 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10355 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 10356 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
230d793d
RS
10357 && (const_op == 0
10358 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10359 < mode_width)))
10360 {
10361 const_op <<= INTVAL (XEXP (op0, 1));
5f4f0e22 10362 op1 = GEN_INT (const_op);
230d793d
RS
10363 op0 = XEXP (op0, 0);
10364 continue;
10365 }
10366
10367 /* If we are using this shift to extract just the sign bit, we
10368 can replace this with an LT or GE comparison. */
10369 if (const_op == 0
10370 && (equality_comparison_p || sign_bit_comparison_p)
10371 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10372 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10373 {
10374 op0 = XEXP (op0, 0);
10375 code = (code == NE || code == GT ? LT : GE);
10376 continue;
10377 }
10378 break;
e9a25f70
JL
10379
10380 default:
10381 break;
230d793d
RS
10382 }
10383
10384 break;
10385 }
10386
10387 /* Now make any compound operations involved in this comparison. Then,
76d31c63 10388 check for an outmost SUBREG on OP0 that is not doing anything or is
230d793d
RS
10389 paradoxical. The latter case can only occur when it is known that the
10390 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10391 We can never remove a SUBREG for a non-equality comparison because the
10392 sign bit is in a different place in the underlying object. */
10393
10394 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10395 op1 = make_compound_operation (op1, SET);
10396
10397 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10398 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10399 && (code == NE || code == EQ)
10400 && ((GET_MODE_SIZE (GET_MODE (op0))
10401 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10402 {
10403 op0 = SUBREG_REG (op0);
10404 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10405 }
10406
10407 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10408 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10409 && (code == NE || code == EQ)
ac49a949
RS
10410 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10411 <= HOST_BITS_PER_WIDE_INT)
951553af 10412 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
230d793d
RS
10413 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10414 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10415 op1),
951553af 10416 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
230d793d
RS
10417 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10418 op0 = SUBREG_REG (op0), op1 = tem;
10419
10420 /* We now do the opposite procedure: Some machines don't have compare
10421 insns in all modes. If OP0's mode is an integer mode smaller than a
10422 word and we can't do a compare in that mode, see if there is a larger
a687e897
RK
10423 mode for which we can do the compare. There are a number of cases in
10424 which we can use the wider mode. */
230d793d
RS
10425
10426 mode = GET_MODE (op0);
10427 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10428 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10429 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10430 for (tmode = GET_MODE_WIDER_MODE (mode);
5f4f0e22
CH
10431 (tmode != VOIDmode
10432 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
230d793d 10433 tmode = GET_MODE_WIDER_MODE (tmode))
a687e897 10434 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
230d793d 10435 {
951553af 10436 /* If the only nonzero bits in OP0 and OP1 are those in the
a687e897
RK
10437 narrower mode and this is an equality or unsigned comparison,
10438 we can use the wider mode. Similarly for sign-extended
7e4dc511 10439 values, in which case it is true for all comparisons. */
a687e897
RK
10440 if (((code == EQ || code == NE
10441 || code == GEU || code == GTU || code == LEU || code == LTU)
951553af
RK
10442 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10443 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
7e4dc511
RK
10444 || ((num_sign_bit_copies (op0, tmode)
10445 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
a687e897 10446 && (num_sign_bit_copies (op1, tmode)
58744483 10447 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
a687e897
RK
10448 {
10449 op0 = gen_lowpart_for_combine (tmode, op0);
10450 op1 = gen_lowpart_for_combine (tmode, op1);
10451 break;
10452 }
230d793d 10453
a687e897
RK
10454 /* If this is a test for negative, we can make an explicit
10455 test of the sign bit. */
10456
10457 if (op1 == const0_rtx && (code == LT || code == GE)
10458 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d 10459 {
a687e897
RK
10460 op0 = gen_binary (AND, tmode,
10461 gen_lowpart_for_combine (tmode, op0),
5f4f0e22
CH
10462 GEN_INT ((HOST_WIDE_INT) 1
10463 << (GET_MODE_BITSIZE (mode) - 1)));
230d793d 10464 code = (code == LT) ? NE : EQ;
a687e897 10465 break;
230d793d 10466 }
230d793d
RS
10467 }
10468
b7a775b2
RK
10469#ifdef CANONICALIZE_COMPARISON
10470 /* If this machine only supports a subset of valid comparisons, see if we
10471 can convert an unsupported one into a supported one. */
10472 CANONICALIZE_COMPARISON (code, op0, op1);
10473#endif
10474
230d793d
RS
10475 *pop0 = op0;
10476 *pop1 = op1;
10477
10478 return code;
10479}
10480\f
10481/* Return 1 if we know that X, a comparison operation, is not operating
10482 on a floating-point value or is EQ or NE, meaning that we can safely
10483 reverse it. */
10484
10485static int
10486reversible_comparison_p (x)
10487 rtx x;
10488{
10489 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e 10490 || flag_fast_math
230d793d
RS
10491 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10492 return 1;
10493
10494 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10495 {
10496 case MODE_INT:
3ad2180a
RK
10497 case MODE_PARTIAL_INT:
10498 case MODE_COMPLEX_INT:
230d793d
RS
10499 return 1;
10500
10501 case MODE_CC:
9210df58
RK
10502 /* If the mode of the condition codes tells us that this is safe,
10503 we need look no further. */
10504 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10505 return 1;
10506
10507 /* Otherwise try and find where the condition codes were last set and
10508 use that. */
230d793d
RS
10509 x = get_last_value (XEXP (x, 0));
10510 return (x && GET_CODE (x) == COMPARE
3ad2180a 10511 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
e9a25f70
JL
10512
10513 default:
10514 return 0;
230d793d 10515 }
230d793d
RS
10516}
10517\f
10518/* Utility function for following routine. Called when X is part of a value
10519 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10520 for each register mentioned. Similar to mention_regs in cse.c */
10521
10522static void
10523update_table_tick (x)
10524 rtx x;
10525{
10526 register enum rtx_code code = GET_CODE (x);
10527 register char *fmt = GET_RTX_FORMAT (code);
10528 register int i;
10529
10530 if (code == REG)
10531 {
10532 int regno = REGNO (x);
10533 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10534 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10535
10536 for (i = regno; i < endregno; i++)
10537 reg_last_set_table_tick[i] = label_tick;
10538
10539 return;
10540 }
10541
10542 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10543 /* Note that we can't have an "E" in values stored; see
10544 get_last_value_validate. */
10545 if (fmt[i] == 'e')
10546 update_table_tick (XEXP (x, i));
10547}
10548
10549/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10550 are saying that the register is clobbered and we no longer know its
7988fd36
RK
10551 value. If INSN is zero, don't update reg_last_set; this is only permitted
10552 with VALUE also zero and is used to invalidate the register. */
230d793d
RS
10553
10554static void
10555record_value_for_reg (reg, insn, value)
10556 rtx reg;
10557 rtx insn;
10558 rtx value;
10559{
10560 int regno = REGNO (reg);
10561 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10562 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10563 int i;
10564
10565 /* If VALUE contains REG and we have a previous value for REG, substitute
10566 the previous value. */
10567 if (value && insn && reg_overlap_mentioned_p (reg, value))
10568 {
10569 rtx tem;
10570
10571 /* Set things up so get_last_value is allowed to see anything set up to
10572 our insn. */
10573 subst_low_cuid = INSN_CUID (insn);
10574 tem = get_last_value (reg);
10575
10576 if (tem)
10577 value = replace_rtx (copy_rtx (value), reg, tem);
10578 }
10579
10580 /* For each register modified, show we don't know its value, that
ef026f91
RS
10581 we don't know about its bitwise content, that its value has been
10582 updated, and that we don't know the location of the death of the
10583 register. */
230d793d
RS
10584 for (i = regno; i < endregno; i ++)
10585 {
10586 if (insn)
10587 reg_last_set[i] = insn;
10588 reg_last_set_value[i] = 0;
ef026f91
RS
10589 reg_last_set_mode[i] = 0;
10590 reg_last_set_nonzero_bits[i] = 0;
10591 reg_last_set_sign_bit_copies[i] = 0;
230d793d
RS
10592 reg_last_death[i] = 0;
10593 }
10594
10595 /* Mark registers that are being referenced in this value. */
10596 if (value)
10597 update_table_tick (value);
10598
10599 /* Now update the status of each register being set.
10600 If someone is using this register in this block, set this register
10601 to invalid since we will get confused between the two lives in this
10602 basic block. This makes using this register always invalid. In cse, we
10603 scan the table to invalidate all entries using this register, but this
10604 is too much work for us. */
10605
10606 for (i = regno; i < endregno; i++)
10607 {
10608 reg_last_set_label[i] = label_tick;
10609 if (value && reg_last_set_table_tick[i] == label_tick)
10610 reg_last_set_invalid[i] = 1;
10611 else
10612 reg_last_set_invalid[i] = 0;
10613 }
10614
10615 /* The value being assigned might refer to X (like in "x++;"). In that
10616 case, we must replace it with (clobber (const_int 0)) to prevent
10617 infinite loops. */
9a893315 10618 if (value && ! get_last_value_validate (&value, insn,
230d793d
RS
10619 reg_last_set_label[regno], 0))
10620 {
10621 value = copy_rtx (value);
9a893315
JW
10622 if (! get_last_value_validate (&value, insn,
10623 reg_last_set_label[regno], 1))
230d793d
RS
10624 value = 0;
10625 }
10626
55310dad
RK
10627 /* For the main register being modified, update the value, the mode, the
10628 nonzero bits, and the number of sign bit copies. */
10629
230d793d
RS
10630 reg_last_set_value[regno] = value;
10631
55310dad
RK
10632 if (value)
10633 {
2afabb48 10634 subst_low_cuid = INSN_CUID (insn);
55310dad
RK
10635 reg_last_set_mode[regno] = GET_MODE (reg);
10636 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10637 reg_last_set_sign_bit_copies[regno]
10638 = num_sign_bit_copies (value, GET_MODE (reg));
10639 }
230d793d
RS
10640}
10641
10642/* Used for communication between the following two routines. */
10643static rtx record_dead_insn;
10644
10645/* Called via note_stores from record_dead_and_set_regs to handle one
10646 SET or CLOBBER in an insn. */
10647
10648static void
10649record_dead_and_set_regs_1 (dest, setter)
10650 rtx dest, setter;
10651{
ca89d290
RK
10652 if (GET_CODE (dest) == SUBREG)
10653 dest = SUBREG_REG (dest);
10654
230d793d
RS
10655 if (GET_CODE (dest) == REG)
10656 {
10657 /* If we are setting the whole register, we know its value. Otherwise
10658 show that we don't know the value. We can handle SUBREG in
10659 some cases. */
10660 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10661 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10662 else if (GET_CODE (setter) == SET
10663 && GET_CODE (SET_DEST (setter)) == SUBREG
10664 && SUBREG_REG (SET_DEST (setter)) == dest
90bf8081 10665 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
230d793d 10666 && subreg_lowpart_p (SET_DEST (setter)))
d0ab8cd3
RK
10667 record_value_for_reg (dest, record_dead_insn,
10668 gen_lowpart_for_combine (GET_MODE (dest),
10669 SET_SRC (setter)));
230d793d 10670 else
5f4f0e22 10671 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
230d793d
RS
10672 }
10673 else if (GET_CODE (dest) == MEM
10674 /* Ignore pushes, they clobber nothing. */
10675 && ! push_operand (dest, GET_MODE (dest)))
10676 mem_last_set = INSN_CUID (record_dead_insn);
10677}
10678
10679/* Update the records of when each REG was most recently set or killed
10680 for the things done by INSN. This is the last thing done in processing
10681 INSN in the combiner loop.
10682
ef026f91
RS
10683 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10684 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10685 and also the similar information mem_last_set (which insn most recently
10686 modified memory) and last_call_cuid (which insn was the most recent
10687 subroutine call). */
230d793d
RS
10688
10689static void
10690record_dead_and_set_regs (insn)
10691 rtx insn;
10692{
10693 register rtx link;
55310dad
RK
10694 int i;
10695
230d793d
RS
10696 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10697 {
dbc131f3
RK
10698 if (REG_NOTE_KIND (link) == REG_DEAD
10699 && GET_CODE (XEXP (link, 0)) == REG)
10700 {
10701 int regno = REGNO (XEXP (link, 0));
10702 int endregno
10703 = regno + (regno < FIRST_PSEUDO_REGISTER
10704 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10705 : 1);
dbc131f3
RK
10706
10707 for (i = regno; i < endregno; i++)
10708 reg_last_death[i] = insn;
10709 }
230d793d 10710 else if (REG_NOTE_KIND (link) == REG_INC)
5f4f0e22 10711 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
230d793d
RS
10712 }
10713
10714 if (GET_CODE (insn) == CALL_INSN)
55310dad
RK
10715 {
10716 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10717 if (call_used_regs[i])
10718 {
10719 reg_last_set_value[i] = 0;
ef026f91
RS
10720 reg_last_set_mode[i] = 0;
10721 reg_last_set_nonzero_bits[i] = 0;
10722 reg_last_set_sign_bit_copies[i] = 0;
55310dad
RK
10723 reg_last_death[i] = 0;
10724 }
10725
10726 last_call_cuid = mem_last_set = INSN_CUID (insn);
10727 }
230d793d
RS
10728
10729 record_dead_insn = insn;
10730 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10731}
10732\f
10733/* Utility routine for the following function. Verify that all the registers
10734 mentioned in *LOC are valid when *LOC was part of a value set when
10735 label_tick == TICK. Return 0 if some are not.
10736
10737 If REPLACE is non-zero, replace the invalid reference with
10738 (clobber (const_int 0)) and return 1. This replacement is useful because
10739 we often can get useful information about the form of a value (e.g., if
10740 it was produced by a shift that always produces -1 or 0) even though
10741 we don't know exactly what registers it was produced from. */
10742
10743static int
9a893315 10744get_last_value_validate (loc, insn, tick, replace)
230d793d 10745 rtx *loc;
9a893315 10746 rtx insn;
230d793d
RS
10747 int tick;
10748 int replace;
10749{
10750 rtx x = *loc;
10751 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10752 int len = GET_RTX_LENGTH (GET_CODE (x));
10753 int i;
10754
10755 if (GET_CODE (x) == REG)
10756 {
10757 int regno = REGNO (x);
10758 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10759 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10760 int j;
10761
10762 for (j = regno; j < endregno; j++)
10763 if (reg_last_set_invalid[j]
10764 /* If this is a pseudo-register that was only set once, it is
10765 always valid. */
b1f21e0a 10766 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
230d793d
RS
10767 && reg_last_set_label[j] > tick))
10768 {
10769 if (replace)
38a448ca 10770 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS
10771 return replace;
10772 }
10773
10774 return 1;
10775 }
9a893315
JW
10776 /* If this is a memory reference, make sure that there were
10777 no stores after it that might have clobbered the value. We don't
10778 have alias info, so we assume any store invalidates it. */
10779 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10780 && INSN_CUID (insn) <= mem_last_set)
10781 {
10782 if (replace)
38a448ca 10783 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9a893315
JW
10784 return replace;
10785 }
230d793d
RS
10786
10787 for (i = 0; i < len; i++)
10788 if ((fmt[i] == 'e'
9a893315 10789 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
230d793d
RS
10790 /* Don't bother with these. They shouldn't occur anyway. */
10791 || fmt[i] == 'E')
10792 return 0;
10793
10794 /* If we haven't found a reason for it to be invalid, it is valid. */
10795 return 1;
10796}
10797
10798/* Get the last value assigned to X, if known. Some registers
10799 in the value may be replaced with (clobber (const_int 0)) if their value
10800 is known longer known reliably. */
10801
10802static rtx
10803get_last_value (x)
10804 rtx x;
10805{
10806 int regno;
10807 rtx value;
10808
10809 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10810 then convert it to the desired mode. If this is a paradoxical SUBREG,
0f41302f 10811 we cannot predict what values the "extra" bits might have. */
230d793d
RS
10812 if (GET_CODE (x) == SUBREG
10813 && subreg_lowpart_p (x)
10814 && (GET_MODE_SIZE (GET_MODE (x))
10815 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10816 && (value = get_last_value (SUBREG_REG (x))) != 0)
10817 return gen_lowpart_for_combine (GET_MODE (x), value);
10818
10819 if (GET_CODE (x) != REG)
10820 return 0;
10821
10822 regno = REGNO (x);
10823 value = reg_last_set_value[regno];
10824
0f41302f
MS
10825 /* If we don't have a value or if it isn't for this basic block,
10826 return 0. */
230d793d
RS
10827
10828 if (value == 0
b1f21e0a 10829 || (REG_N_SETS (regno) != 1
55310dad 10830 && reg_last_set_label[regno] != label_tick))
230d793d
RS
10831 return 0;
10832
4255220d 10833 /* If the value was set in a later insn than the ones we are processing,
4090a6b3
RK
10834 we can't use it even if the register was only set once, but make a quick
10835 check to see if the previous insn set it to something. This is commonly
0d9641d1
JW
10836 the case when the same pseudo is used by repeated insns.
10837
10838 This does not work if there exists an instruction which is temporarily
10839 not on the insn chain. */
d0ab8cd3 10840
bcd49eb7 10841 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
d0ab8cd3
RK
10842 {
10843 rtx insn, set;
10844
bcd49eb7
JW
10845 /* We can not do anything useful in this case, because there is
10846 an instruction which is not on the insn chain. */
10847 if (subst_prev_insn)
10848 return 0;
10849
4255220d
JW
10850 /* Skip over USE insns. They are not useful here, and they may have
10851 been made by combine, in which case they do not have a INSN_CUID
d6c80562 10852 value. We can't use prev_real_insn, because that would incorrectly
e340018d
JW
10853 take us backwards across labels. Skip over BARRIERs also, since
10854 they could have been made by combine. If we see one, we must be
10855 optimizing dead code, so it doesn't matter what we do. */
d6c80562
JW
10856 for (insn = prev_nonnote_insn (subst_insn);
10857 insn && ((GET_CODE (insn) == INSN
10858 && GET_CODE (PATTERN (insn)) == USE)
e340018d 10859 || GET_CODE (insn) == BARRIER
4255220d 10860 || INSN_CUID (insn) >= subst_low_cuid);
d6c80562 10861 insn = prev_nonnote_insn (insn))
3adde2a5 10862 ;
d0ab8cd3
RK
10863
10864 if (insn
10865 && (set = single_set (insn)) != 0
10866 && rtx_equal_p (SET_DEST (set), x))
10867 {
10868 value = SET_SRC (set);
10869
10870 /* Make sure that VALUE doesn't reference X. Replace any
ddd5a7c1 10871 explicit references with a CLOBBER. If there are any remaining
d0ab8cd3
RK
10872 references (rare), don't use the value. */
10873
10874 if (reg_mentioned_p (x, value))
10875 value = replace_rtx (copy_rtx (value), x,
38a448ca 10876 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
d0ab8cd3
RK
10877
10878 if (reg_overlap_mentioned_p (x, value))
10879 return 0;
10880 }
10881 else
10882 return 0;
10883 }
10884
10885 /* If the value has all its registers valid, return it. */
9a893315
JW
10886 if (get_last_value_validate (&value, reg_last_set[regno],
10887 reg_last_set_label[regno], 0))
230d793d
RS
10888 return value;
10889
10890 /* Otherwise, make a copy and replace any invalid register with
10891 (clobber (const_int 0)). If that fails for some reason, return 0. */
10892
10893 value = copy_rtx (value);
9a893315
JW
10894 if (get_last_value_validate (&value, reg_last_set[regno],
10895 reg_last_set_label[regno], 1))
230d793d
RS
10896 return value;
10897
10898 return 0;
10899}
10900\f
10901/* Return nonzero if expression X refers to a REG or to memory
10902 that is set in an instruction more recent than FROM_CUID. */
10903
10904static int
10905use_crosses_set_p (x, from_cuid)
10906 register rtx x;
10907 int from_cuid;
10908{
10909 register char *fmt;
10910 register int i;
10911 register enum rtx_code code = GET_CODE (x);
10912
10913 if (code == REG)
10914 {
10915 register int regno = REGNO (x);
e28f5732
RK
10916 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10917 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10918
230d793d
RS
10919#ifdef PUSH_ROUNDING
10920 /* Don't allow uses of the stack pointer to be moved,
10921 because we don't know whether the move crosses a push insn. */
10922 if (regno == STACK_POINTER_REGNUM)
10923 return 1;
10924#endif
e28f5732
RK
10925 for (;regno < endreg; regno++)
10926 if (reg_last_set[regno]
10927 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10928 return 1;
10929 return 0;
230d793d
RS
10930 }
10931
10932 if (code == MEM && mem_last_set > from_cuid)
10933 return 1;
10934
10935 fmt = GET_RTX_FORMAT (code);
10936
10937 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10938 {
10939 if (fmt[i] == 'E')
10940 {
10941 register int j;
10942 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10943 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10944 return 1;
10945 }
10946 else if (fmt[i] == 'e'
10947 && use_crosses_set_p (XEXP (x, i), from_cuid))
10948 return 1;
10949 }
10950 return 0;
10951}
10952\f
10953/* Define three variables used for communication between the following
10954 routines. */
10955
10956static int reg_dead_regno, reg_dead_endregno;
10957static int reg_dead_flag;
10958
10959/* Function called via note_stores from reg_dead_at_p.
10960
ddd5a7c1 10961 If DEST is within [reg_dead_regno, reg_dead_endregno), set
230d793d
RS
10962 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10963
10964static void
10965reg_dead_at_p_1 (dest, x)
10966 rtx dest;
10967 rtx x;
10968{
10969 int regno, endregno;
10970
10971 if (GET_CODE (dest) != REG)
10972 return;
10973
10974 regno = REGNO (dest);
10975 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10976 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10977
10978 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10979 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10980}
10981
10982/* Return non-zero if REG is known to be dead at INSN.
10983
10984 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10985 referencing REG, it is dead. If we hit a SET referencing REG, it is
10986 live. Otherwise, see if it is live or dead at the start of the basic
6e25d159
RK
10987 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10988 must be assumed to be always live. */
230d793d
RS
10989
10990static int
10991reg_dead_at_p (reg, insn)
10992 rtx reg;
10993 rtx insn;
10994{
10995 int block, i;
10996
10997 /* Set variables for reg_dead_at_p_1. */
10998 reg_dead_regno = REGNO (reg);
10999 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11000 ? HARD_REGNO_NREGS (reg_dead_regno,
11001 GET_MODE (reg))
11002 : 1);
11003
11004 reg_dead_flag = 0;
11005
6e25d159
RK
11006 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11007 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11008 {
11009 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11010 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11011 return 0;
11012 }
11013
230d793d
RS
11014 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11015 beginning of function. */
60715d0b 11016 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
230d793d
RS
11017 insn = prev_nonnote_insn (insn))
11018 {
11019 note_stores (PATTERN (insn), reg_dead_at_p_1);
11020 if (reg_dead_flag)
11021 return reg_dead_flag == 1 ? 1 : 0;
11022
11023 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11024 return 1;
11025 }
11026
11027 /* Get the basic block number that we were in. */
11028 if (insn == 0)
11029 block = 0;
11030 else
11031 {
11032 for (block = 0; block < n_basic_blocks; block++)
3b413743 11033 if (insn == BLOCK_HEAD (block))
230d793d
RS
11034 break;
11035
11036 if (block == n_basic_blocks)
11037 return 0;
11038 }
11039
11040 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8e08106d 11041 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
230d793d
RS
11042 return 0;
11043
11044 return 1;
11045}
6e25d159
RK
11046\f
11047/* Note hard registers in X that are used. This code is similar to
11048 that in flow.c, but much simpler since we don't care about pseudos. */
11049
11050static void
11051mark_used_regs_combine (x)
11052 rtx x;
11053{
11054 register RTX_CODE code = GET_CODE (x);
11055 register int regno;
11056 int i;
11057
11058 switch (code)
11059 {
11060 case LABEL_REF:
11061 case SYMBOL_REF:
11062 case CONST_INT:
11063 case CONST:
11064 case CONST_DOUBLE:
11065 case PC:
11066 case ADDR_VEC:
11067 case ADDR_DIFF_VEC:
11068 case ASM_INPUT:
11069#ifdef HAVE_cc0
11070 /* CC0 must die in the insn after it is set, so we don't need to take
11071 special note of it here. */
11072 case CC0:
11073#endif
11074 return;
11075
11076 case CLOBBER:
11077 /* If we are clobbering a MEM, mark any hard registers inside the
11078 address as used. */
11079 if (GET_CODE (XEXP (x, 0)) == MEM)
11080 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11081 return;
11082
11083 case REG:
11084 regno = REGNO (x);
11085 /* A hard reg in a wide mode may really be multiple registers.
11086 If so, mark all of them just like the first. */
11087 if (regno < FIRST_PSEUDO_REGISTER)
11088 {
11089 /* None of this applies to the stack, frame or arg pointers */
11090 if (regno == STACK_POINTER_REGNUM
11091#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11092 || regno == HARD_FRAME_POINTER_REGNUM
11093#endif
11094#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11095 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11096#endif
11097 || regno == FRAME_POINTER_REGNUM)
11098 return;
11099
11100 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11101 while (i-- > 0)
11102 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11103 }
11104 return;
11105
11106 case SET:
11107 {
11108 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11109 the address. */
11110 register rtx testreg = SET_DEST (x);
11111
e048778f
RK
11112 while (GET_CODE (testreg) == SUBREG
11113 || GET_CODE (testreg) == ZERO_EXTRACT
11114 || GET_CODE (testreg) == SIGN_EXTRACT
11115 || GET_CODE (testreg) == STRICT_LOW_PART)
6e25d159
RK
11116 testreg = XEXP (testreg, 0);
11117
11118 if (GET_CODE (testreg) == MEM)
11119 mark_used_regs_combine (XEXP (testreg, 0));
11120
11121 mark_used_regs_combine (SET_SRC (x));
6e25d159 11122 }
e9a25f70
JL
11123 return;
11124
11125 default:
11126 break;
6e25d159
RK
11127 }
11128
11129 /* Recursively scan the operands of this expression. */
11130
11131 {
11132 register char *fmt = GET_RTX_FORMAT (code);
11133
11134 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11135 {
11136 if (fmt[i] == 'e')
11137 mark_used_regs_combine (XEXP (x, i));
11138 else if (fmt[i] == 'E')
11139 {
11140 register int j;
11141
11142 for (j = 0; j < XVECLEN (x, i); j++)
11143 mark_used_regs_combine (XVECEXP (x, i, j));
11144 }
11145 }
11146 }
11147}
11148
230d793d
RS
11149\f
11150/* Remove register number REGNO from the dead registers list of INSN.
11151
11152 Return the note used to record the death, if there was one. */
11153
11154rtx
11155remove_death (regno, insn)
11156 int regno;
11157 rtx insn;
11158{
11159 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11160
11161 if (note)
1a26b032 11162 {
b1f21e0a 11163 REG_N_DEATHS (regno)--;
1a26b032
RK
11164 remove_note (insn, note);
11165 }
230d793d
RS
11166
11167 return note;
11168}
11169
11170/* For each register (hardware or pseudo) used within expression X, if its
11171 death is in an instruction with cuid between FROM_CUID (inclusive) and
11172 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11173 list headed by PNOTES.
11174
6eb12cef
RK
11175 That said, don't move registers killed by maybe_kill_insn.
11176
230d793d
RS
11177 This is done when X is being merged by combination into TO_INSN. These
11178 notes will then be distributed as needed. */
11179
11180static void
6eb12cef 11181move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
230d793d 11182 rtx x;
6eb12cef 11183 rtx maybe_kill_insn;
230d793d
RS
11184 int from_cuid;
11185 rtx to_insn;
11186 rtx *pnotes;
11187{
11188 register char *fmt;
11189 register int len, i;
11190 register enum rtx_code code = GET_CODE (x);
11191
11192 if (code == REG)
11193 {
11194 register int regno = REGNO (x);
11195 register rtx where_dead = reg_last_death[regno];
e340018d
JW
11196 register rtx before_dead, after_dead;
11197
6eb12cef
RK
11198 /* Don't move the register if it gets killed in between from and to */
11199 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11200 && !reg_referenced_p (x, maybe_kill_insn))
11201 return;
11202
e340018d
JW
11203 /* WHERE_DEAD could be a USE insn made by combine, so first we
11204 make sure that we have insns with valid INSN_CUID values. */
11205 before_dead = where_dead;
11206 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11207 before_dead = PREV_INSN (before_dead);
11208 after_dead = where_dead;
11209 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11210 after_dead = NEXT_INSN (after_dead);
11211
11212 if (before_dead && after_dead
11213 && INSN_CUID (before_dead) >= from_cuid
11214 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11215 || (where_dead != after_dead
11216 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
230d793d 11217 {
dbc131f3 11218 rtx note = remove_death (regno, where_dead);
230d793d
RS
11219
11220 /* It is possible for the call above to return 0. This can occur
11221 when reg_last_death points to I2 or I1 that we combined with.
dbc131f3
RK
11222 In that case make a new note.
11223
11224 We must also check for the case where X is a hard register
11225 and NOTE is a death note for a range of hard registers
11226 including X. In that case, we must put REG_DEAD notes for
11227 the remaining registers in place of NOTE. */
11228
11229 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11230 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
24e46fc4 11231 > GET_MODE_SIZE (GET_MODE (x))))
dbc131f3
RK
11232 {
11233 int deadregno = REGNO (XEXP (note, 0));
11234 int deadend
11235 = (deadregno + HARD_REGNO_NREGS (deadregno,
11236 GET_MODE (XEXP (note, 0))));
11237 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11238 int i;
11239
11240 for (i = deadregno; i < deadend; i++)
11241 if (i < regno || i >= ourend)
11242 REG_NOTES (where_dead)
38a448ca
RH
11243 = gen_rtx_EXPR_LIST (REG_DEAD,
11244 gen_rtx_REG (reg_raw_mode[i], i),
11245 REG_NOTES (where_dead));
dbc131f3 11246 }
24e46fc4
JW
11247 /* If we didn't find any note, or if we found a REG_DEAD note that
11248 covers only part of the given reg, and we have a multi-reg hard
fabd69e8
RK
11249 register, then to be safe we must check for REG_DEAD notes
11250 for each register other than the first. They could have
11251 their own REG_DEAD notes lying around. */
24e46fc4
JW
11252 else if ((note == 0
11253 || (note != 0
11254 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11255 < GET_MODE_SIZE (GET_MODE (x)))))
11256 && regno < FIRST_PSEUDO_REGISTER
fabd69e8
RK
11257 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11258 {
11259 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
24e46fc4 11260 int i, offset;
fabd69e8
RK
11261 rtx oldnotes = 0;
11262
24e46fc4
JW
11263 if (note)
11264 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11265 else
11266 offset = 1;
11267
11268 for (i = regno + offset; i < ourend; i++)
38a448ca 11269 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
6eb12cef 11270 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
fabd69e8 11271 }
230d793d 11272
dbc131f3 11273 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
230d793d
RS
11274 {
11275 XEXP (note, 1) = *pnotes;
11276 *pnotes = note;
11277 }
11278 else
38a448ca 11279 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
1a26b032 11280
b1f21e0a 11281 REG_N_DEATHS (regno)++;
230d793d
RS
11282 }
11283
11284 return;
11285 }
11286
11287 else if (GET_CODE (x) == SET)
11288 {
11289 rtx dest = SET_DEST (x);
11290
6eb12cef 11291 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d 11292
a7c99304
RK
11293 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11294 that accesses one word of a multi-word item, some
11295 piece of everything register in the expression is used by
11296 this insn, so remove any old death. */
11297
11298 if (GET_CODE (dest) == ZERO_EXTRACT
11299 || GET_CODE (dest) == STRICT_LOW_PART
11300 || (GET_CODE (dest) == SUBREG
11301 && (((GET_MODE_SIZE (GET_MODE (dest))
11302 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11303 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11304 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
230d793d 11305 {
6eb12cef 11306 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
a7c99304 11307 return;
230d793d
RS
11308 }
11309
a7c99304
RK
11310 /* If this is some other SUBREG, we know it replaces the entire
11311 value, so use that as the destination. */
11312 if (GET_CODE (dest) == SUBREG)
11313 dest = SUBREG_REG (dest);
11314
11315 /* If this is a MEM, adjust deaths of anything used in the address.
11316 For a REG (the only other possibility), the entire value is
11317 being replaced so the old value is not used in this insn. */
230d793d
RS
11318
11319 if (GET_CODE (dest) == MEM)
6eb12cef
RK
11320 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11321 to_insn, pnotes);
230d793d
RS
11322 return;
11323 }
11324
11325 else if (GET_CODE (x) == CLOBBER)
11326 return;
11327
11328 len = GET_RTX_LENGTH (code);
11329 fmt = GET_RTX_FORMAT (code);
11330
11331 for (i = 0; i < len; i++)
11332 {
11333 if (fmt[i] == 'E')
11334 {
11335 register int j;
11336 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6eb12cef
RK
11337 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11338 to_insn, pnotes);
230d793d
RS
11339 }
11340 else if (fmt[i] == 'e')
6eb12cef 11341 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d
RS
11342 }
11343}
11344\f
a7c99304
RK
11345/* Return 1 if X is the target of a bit-field assignment in BODY, the
11346 pattern of an insn. X must be a REG. */
230d793d
RS
11347
11348static int
a7c99304
RK
11349reg_bitfield_target_p (x, body)
11350 rtx x;
230d793d
RS
11351 rtx body;
11352{
11353 int i;
11354
11355 if (GET_CODE (body) == SET)
a7c99304
RK
11356 {
11357 rtx dest = SET_DEST (body);
11358 rtx target;
11359 int regno, tregno, endregno, endtregno;
11360
11361 if (GET_CODE (dest) == ZERO_EXTRACT)
11362 target = XEXP (dest, 0);
11363 else if (GET_CODE (dest) == STRICT_LOW_PART)
11364 target = SUBREG_REG (XEXP (dest, 0));
11365 else
11366 return 0;
11367
11368 if (GET_CODE (target) == SUBREG)
11369 target = SUBREG_REG (target);
11370
11371 if (GET_CODE (target) != REG)
11372 return 0;
11373
11374 tregno = REGNO (target), regno = REGNO (x);
11375 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11376 return target == x;
11377
11378 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11379 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11380
11381 return endregno > tregno && regno < endtregno;
11382 }
230d793d
RS
11383
11384 else if (GET_CODE (body) == PARALLEL)
11385 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
a7c99304 11386 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
230d793d
RS
11387 return 1;
11388
11389 return 0;
11390}
11391\f
11392/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11393 as appropriate. I3 and I2 are the insns resulting from the combination
11394 insns including FROM (I2 may be zero).
11395
11396 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11397 not need REG_DEAD notes because they are being substituted for. This
11398 saves searching in the most common cases.
11399
11400 Each note in the list is either ignored or placed on some insns, depending
11401 on the type of note. */
11402
11403static void
11404distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11405 rtx notes;
11406 rtx from_insn;
11407 rtx i3, i2;
11408 rtx elim_i2, elim_i1;
11409{
11410 rtx note, next_note;
11411 rtx tem;
11412
11413 for (note = notes; note; note = next_note)
11414 {
11415 rtx place = 0, place2 = 0;
11416
11417 /* If this NOTE references a pseudo register, ensure it references
11418 the latest copy of that register. */
11419 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11420 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11421 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11422
11423 next_note = XEXP (note, 1);
11424 switch (REG_NOTE_KIND (note))
11425 {
c9903b44
DE
11426 case REG_BR_PROB:
11427 case REG_EXEC_COUNT:
11428 /* Doesn't matter much where we put this, as long as it's somewhere.
11429 It is preferable to keep these notes on branches, which is most
11430 likely to be i3. */
11431 place = i3;
11432 break;
11433
230d793d 11434 case REG_UNUSED:
07d0cbdd 11435 /* Any clobbers for i3 may still exist, and so we must process
176c9e6b
JW
11436 REG_UNUSED notes from that insn.
11437
11438 Any clobbers from i2 or i1 can only exist if they were added by
11439 recog_for_combine. In that case, recog_for_combine created the
11440 necessary REG_UNUSED notes. Trying to keep any original
11441 REG_UNUSED notes from these insns can cause incorrect output
11442 if it is for the same register as the original i3 dest.
11443 In that case, we will notice that the register is set in i3,
11444 and then add a REG_UNUSED note for the destination of i3, which
07d0cbdd
JW
11445 is wrong. However, it is possible to have REG_UNUSED notes from
11446 i2 or i1 for register which were both used and clobbered, so
11447 we keep notes from i2 or i1 if they will turn into REG_DEAD
11448 notes. */
176c9e6b 11449
230d793d
RS
11450 /* If this register is set or clobbered in I3, put the note there
11451 unless there is one already. */
07d0cbdd 11452 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
230d793d 11453 {
07d0cbdd
JW
11454 if (from_insn != i3)
11455 break;
11456
230d793d
RS
11457 if (! (GET_CODE (XEXP (note, 0)) == REG
11458 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11459 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11460 place = i3;
11461 }
11462 /* Otherwise, if this register is used by I3, then this register
11463 now dies here, so we must put a REG_DEAD note here unless there
11464 is one already. */
11465 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11466 && ! (GET_CODE (XEXP (note, 0)) == REG
11467 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11468 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11469 {
11470 PUT_REG_NOTE_KIND (note, REG_DEAD);
11471 place = i3;
11472 }
11473 break;
11474
11475 case REG_EQUAL:
11476 case REG_EQUIV:
11477 case REG_NONNEG:
9ae8ffe7 11478 case REG_NOALIAS:
230d793d
RS
11479 /* These notes say something about results of an insn. We can
11480 only support them if they used to be on I3 in which case they
a687e897
RK
11481 remain on I3. Otherwise they are ignored.
11482
11483 If the note refers to an expression that is not a constant, we
11484 must also ignore the note since we cannot tell whether the
11485 equivalence is still true. It might be possible to do
11486 slightly better than this (we only have a problem if I2DEST
11487 or I1DEST is present in the expression), but it doesn't
11488 seem worth the trouble. */
11489
11490 if (from_insn == i3
11491 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
230d793d
RS
11492 place = i3;
11493 break;
11494
11495 case REG_INC:
11496 case REG_NO_CONFLICT:
11497 case REG_LABEL:
11498 /* These notes say something about how a register is used. They must
11499 be present on any use of the register in I2 or I3. */
11500 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11501 place = i3;
11502
11503 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11504 {
11505 if (place)
11506 place2 = i2;
11507 else
11508 place = i2;
11509 }
11510 break;
11511
11512 case REG_WAS_0:
11513 /* It is too much trouble to try to see if this note is still
11514 correct in all situations. It is better to simply delete it. */
11515 break;
11516
11517 case REG_RETVAL:
11518 /* If the insn previously containing this note still exists,
11519 put it back where it was. Otherwise move it to the previous
11520 insn. Adjust the corresponding REG_LIBCALL note. */
11521 if (GET_CODE (from_insn) != NOTE)
11522 place = from_insn;
11523 else
11524 {
5f4f0e22 11525 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
230d793d
RS
11526 place = prev_real_insn (from_insn);
11527 if (tem && place)
11528 XEXP (tem, 0) = place;
11529 }
11530 break;
11531
11532 case REG_LIBCALL:
11533 /* This is handled similarly to REG_RETVAL. */
11534 if (GET_CODE (from_insn) != NOTE)
11535 place = from_insn;
11536 else
11537 {
5f4f0e22 11538 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
230d793d
RS
11539 place = next_real_insn (from_insn);
11540 if (tem && place)
11541 XEXP (tem, 0) = place;
11542 }
11543 break;
11544
11545 case REG_DEAD:
11546 /* If the register is used as an input in I3, it dies there.
11547 Similarly for I2, if it is non-zero and adjacent to I3.
11548
11549 If the register is not used as an input in either I3 or I2
11550 and it is not one of the registers we were supposed to eliminate,
11551 there are two possibilities. We might have a non-adjacent I2
11552 or we might have somehow eliminated an additional register
11553 from a computation. For example, we might have had A & B where
11554 we discover that B will always be zero. In this case we will
11555 eliminate the reference to A.
11556
11557 In both cases, we must search to see if we can find a previous
11558 use of A and put the death note there. */
11559
6e2d1486
RK
11560 if (from_insn
11561 && GET_CODE (from_insn) == CALL_INSN
11562 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11563 place = from_insn;
11564 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
230d793d
RS
11565 place = i3;
11566 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11567 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11568 place = i2;
11569
11570 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11571 break;
11572
510dd77e
RK
11573 /* If the register is used in both I2 and I3 and it dies in I3,
11574 we might have added another reference to it. If reg_n_refs
11575 was 2, bump it to 3. This has to be correct since the
11576 register must have been set somewhere. The reason this is
11577 done is because local-alloc.c treats 2 references as a
11578 special case. */
11579
11580 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
b1f21e0a 11581 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
510dd77e 11582 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
b1f21e0a 11583 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
510dd77e 11584
230d793d 11585 if (place == 0)
38d8473f
RK
11586 {
11587 for (tem = prev_nonnote_insn (i3);
11588 place == 0 && tem
11589 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11590 tem = prev_nonnote_insn (tem))
11591 {
11592 /* If the register is being set at TEM, see if that is all
11593 TEM is doing. If so, delete TEM. Otherwise, make this
11594 into a REG_UNUSED note instead. */
11595 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11596 {
11597 rtx set = single_set (tem);
e5e809f4 11598 rtx inner_dest = 0;
e51712db 11599#ifdef HAVE_cc0
f5c97640 11600 rtx cc0_setter = NULL_RTX;
e51712db 11601#endif
e5e809f4
JL
11602
11603 if (set != 0)
11604 for (inner_dest = SET_DEST (set);
11605 GET_CODE (inner_dest) == STRICT_LOW_PART
11606 || GET_CODE (inner_dest) == SUBREG
11607 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11608 inner_dest = XEXP (inner_dest, 0))
11609 ;
38d8473f
RK
11610
11611 /* Verify that it was the set, and not a clobber that
f5c97640
RH
11612 modified the register.
11613
11614 CC0 targets must be careful to maintain setter/user
11615 pairs. If we cannot delete the setter due to side
11616 effects, mark the user with an UNUSED note instead
11617 of deleting it. */
38d8473f
RK
11618
11619 if (set != 0 && ! side_effects_p (SET_SRC (set))
f5c97640
RH
11620 && rtx_equal_p (XEXP (note, 0), inner_dest)
11621#ifdef HAVE_cc0
11622 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11623 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11624 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11625#endif
11626 )
38d8473f
RK
11627 {
11628 /* Move the notes and links of TEM elsewhere.
11629 This might delete other dead insns recursively.
11630 First set the pattern to something that won't use
11631 any register. */
11632
11633 PATTERN (tem) = pc_rtx;
11634
11635 distribute_notes (REG_NOTES (tem), tem, tem,
11636 NULL_RTX, NULL_RTX, NULL_RTX);
11637 distribute_links (LOG_LINKS (tem));
11638
11639 PUT_CODE (tem, NOTE);
11640 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11641 NOTE_SOURCE_FILE (tem) = 0;
f5c97640
RH
11642
11643#ifdef HAVE_cc0
11644 /* Delete the setter too. */
11645 if (cc0_setter)
11646 {
11647 PATTERN (cc0_setter) = pc_rtx;
11648
11649 distribute_notes (REG_NOTES (cc0_setter),
11650 cc0_setter, cc0_setter,
11651 NULL_RTX, NULL_RTX, NULL_RTX);
11652 distribute_links (LOG_LINKS (cc0_setter));
11653
11654 PUT_CODE (cc0_setter, NOTE);
11655 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED;
11656 NOTE_SOURCE_FILE (cc0_setter) = 0;
11657 }
11658#endif
38d8473f 11659 }
e5e809f4
JL
11660 /* If the register is both set and used here, put the
11661 REG_DEAD note here, but place a REG_UNUSED note
11662 here too unless there already is one. */
11663 else if (reg_referenced_p (XEXP (note, 0),
11664 PATTERN (tem)))
11665 {
11666 place = tem;
11667
11668 if (! find_regno_note (tem, REG_UNUSED,
11669 REGNO (XEXP (note, 0))))
11670 REG_NOTES (tem)
9e6a5703
JC
11671 = gen_rtx_EXPR_LIST (REG_UNUSED,
11672 XEXP (note, 0),
11673 REG_NOTES (tem));
e5e809f4 11674 }
38d8473f
RK
11675 else
11676 {
11677 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11678
11679 /* If there isn't already a REG_UNUSED note, put one
11680 here. */
11681 if (! find_regno_note (tem, REG_UNUSED,
11682 REGNO (XEXP (note, 0))))
11683 place = tem;
11684 break;
230d793d
RS
11685 }
11686 }
13018fad
RE
11687 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11688 || (GET_CODE (tem) == CALL_INSN
11689 && find_reg_fusage (tem, USE, XEXP (note, 0))))
230d793d
RS
11690 {
11691 place = tem;
932d1119
RK
11692
11693 /* If we are doing a 3->2 combination, and we have a
11694 register which formerly died in i3 and was not used
11695 by i2, which now no longer dies in i3 and is used in
11696 i2 but does not die in i2, and place is between i2
11697 and i3, then we may need to move a link from place to
11698 i2. */
a8908849
RK
11699 if (i2 && INSN_UID (place) <= max_uid_cuid
11700 && INSN_CUID (place) > INSN_CUID (i2)
932d1119
RK
11701 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11702 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11703 {
11704 rtx links = LOG_LINKS (place);
11705 LOG_LINKS (place) = 0;
11706 distribute_links (links);
11707 }
230d793d
RS
11708 break;
11709 }
38d8473f
RK
11710 }
11711
11712 /* If we haven't found an insn for the death note and it
11713 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11714 insert a USE insn for the register at that label and
11715 put the death node there. This prevents problems with
11716 call-state tracking in caller-save.c. */
11717 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
e2cce0cf
RK
11718 {
11719 place
38a448ca 11720 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
e2cce0cf
RK
11721 tem);
11722
11723 /* If this insn was emitted between blocks, then update
3b413743
RH
11724 BLOCK_HEAD of the current block to include it. */
11725 if (BLOCK_END (this_basic_block - 1) == tem)
11726 BLOCK_HEAD (this_basic_block) = place;
e2cce0cf 11727 }
38d8473f 11728 }
230d793d
RS
11729
11730 /* If the register is set or already dead at PLACE, we needn't do
e5e809f4
JL
11731 anything with this note if it is still a REG_DEAD note.
11732 We can here if it is set at all, not if is it totally replace,
11733 which is what `dead_or_set_p' checks, so also check for it being
11734 set partially. */
11735
230d793d 11736
230d793d
RS
11737 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11738 {
11739 int regno = REGNO (XEXP (note, 0));
11740
11741 if (dead_or_set_p (place, XEXP (note, 0))
11742 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11743 {
11744 /* Unless the register previously died in PLACE, clear
11745 reg_last_death. [I no longer understand why this is
11746 being done.] */
11747 if (reg_last_death[regno] != place)
11748 reg_last_death[regno] = 0;
11749 place = 0;
11750 }
11751 else
11752 reg_last_death[regno] = place;
11753
11754 /* If this is a death note for a hard reg that is occupying
11755 multiple registers, ensure that we are still using all
11756 parts of the object. If we find a piece of the object
11757 that is unused, we must add a USE for that piece before
11758 PLACE and put the appropriate REG_DEAD note on it.
11759
11760 An alternative would be to put a REG_UNUSED for the pieces
11761 on the insn that set the register, but that can't be done if
11762 it is not in the same block. It is simpler, though less
11763 efficient, to add the USE insns. */
11764
11765 if (place && regno < FIRST_PSEUDO_REGISTER
11766 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11767 {
11768 int endregno
11769 = regno + HARD_REGNO_NREGS (regno,
11770 GET_MODE (XEXP (note, 0)));
11771 int all_used = 1;
11772 int i;
11773
11774 for (i = regno; i < endregno; i++)
9fd5bb62
JW
11775 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11776 && ! find_regno_fusage (place, USE, i))
230d793d 11777 {
38a448ca 11778 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
28f6d3af
RK
11779 rtx p;
11780
11781 /* See if we already placed a USE note for this
11782 register in front of PLACE. */
11783 for (p = place;
11784 GET_CODE (PREV_INSN (p)) == INSN
11785 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11786 p = PREV_INSN (p))
11787 if (rtx_equal_p (piece,
11788 XEXP (PATTERN (PREV_INSN (p)), 0)))
11789 {
11790 p = 0;
11791 break;
11792 }
11793
11794 if (p)
11795 {
11796 rtx use_insn
38a448ca
RH
11797 = emit_insn_before (gen_rtx_USE (VOIDmode,
11798 piece),
28f6d3af
RK
11799 p);
11800 REG_NOTES (use_insn)
38a448ca
RH
11801 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11802 REG_NOTES (use_insn));
28f6d3af 11803 }
230d793d 11804
5089e22e 11805 all_used = 0;
230d793d
RS
11806 }
11807
a394b17b
JW
11808 /* Check for the case where the register dying partially
11809 overlaps the register set by this insn. */
11810 if (all_used)
11811 for (i = regno; i < endregno; i++)
11812 if (dead_or_set_regno_p (place, i))
11813 {
11814 all_used = 0;
11815 break;
11816 }
11817
230d793d
RS
11818 if (! all_used)
11819 {
11820 /* Put only REG_DEAD notes for pieces that are
11821 still used and that are not already dead or set. */
11822
11823 for (i = regno; i < endregno; i++)
11824 {
38a448ca 11825 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
230d793d 11826
17cbf358
JW
11827 if ((reg_referenced_p (piece, PATTERN (place))
11828 || (GET_CODE (place) == CALL_INSN
11829 && find_reg_fusage (place, USE, piece)))
230d793d
RS
11830 && ! dead_or_set_p (place, piece)
11831 && ! reg_bitfield_target_p (piece,
11832 PATTERN (place)))
38a448ca
RH
11833 REG_NOTES (place)
11834 = gen_rtx_EXPR_LIST (REG_DEAD,
11835 piece, REG_NOTES (place));
230d793d
RS
11836 }
11837
11838 place = 0;
11839 }
11840 }
11841 }
11842 break;
11843
11844 default:
11845 /* Any other notes should not be present at this point in the
11846 compilation. */
11847 abort ();
11848 }
11849
11850 if (place)
11851 {
11852 XEXP (note, 1) = REG_NOTES (place);
11853 REG_NOTES (place) = note;
11854 }
1a26b032
RK
11855 else if ((REG_NOTE_KIND (note) == REG_DEAD
11856 || REG_NOTE_KIND (note) == REG_UNUSED)
11857 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11858 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
230d793d
RS
11859
11860 if (place2)
1a26b032
RK
11861 {
11862 if ((REG_NOTE_KIND (note) == REG_DEAD
11863 || REG_NOTE_KIND (note) == REG_UNUSED)
11864 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11865 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 11866
38a448ca
RH
11867 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11868 REG_NOTE_KIND (note),
11869 XEXP (note, 0),
11870 REG_NOTES (place2));
1a26b032 11871 }
230d793d
RS
11872 }
11873}
11874\f
11875/* Similarly to above, distribute the LOG_LINKS that used to be present on
5089e22e
RS
11876 I3, I2, and I1 to new locations. This is also called in one case to
11877 add a link pointing at I3 when I3's destination is changed. */
230d793d
RS
11878
11879static void
11880distribute_links (links)
11881 rtx links;
11882{
11883 rtx link, next_link;
11884
11885 for (link = links; link; link = next_link)
11886 {
11887 rtx place = 0;
11888 rtx insn;
11889 rtx set, reg;
11890
11891 next_link = XEXP (link, 1);
11892
11893 /* If the insn that this link points to is a NOTE or isn't a single
11894 set, ignore it. In the latter case, it isn't clear what we
11895 can do other than ignore the link, since we can't tell which
11896 register it was for. Such links wouldn't be used by combine
11897 anyway.
11898
11899 It is not possible for the destination of the target of the link to
11900 have been changed by combine. The only potential of this is if we
11901 replace I3, I2, and I1 by I3 and I2. But in that case the
11902 destination of I2 also remains unchanged. */
11903
11904 if (GET_CODE (XEXP (link, 0)) == NOTE
11905 || (set = single_set (XEXP (link, 0))) == 0)
11906 continue;
11907
11908 reg = SET_DEST (set);
11909 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11910 || GET_CODE (reg) == SIGN_EXTRACT
11911 || GET_CODE (reg) == STRICT_LOW_PART)
11912 reg = XEXP (reg, 0);
11913
11914 /* A LOG_LINK is defined as being placed on the first insn that uses
11915 a register and points to the insn that sets the register. Start
11916 searching at the next insn after the target of the link and stop
11917 when we reach a set of the register or the end of the basic block.
11918
11919 Note that this correctly handles the link that used to point from
5089e22e 11920 I3 to I2. Also note that not much searching is typically done here
230d793d
RS
11921 since most links don't point very far away. */
11922
11923 for (insn = NEXT_INSN (XEXP (link, 0));
0d4d42c3 11924 (insn && (this_basic_block == n_basic_blocks - 1
3b413743 11925 || BLOCK_HEAD (this_basic_block + 1) != insn));
230d793d
RS
11926 insn = NEXT_INSN (insn))
11927 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11928 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11929 {
11930 if (reg_referenced_p (reg, PATTERN (insn)))
11931 place = insn;
11932 break;
11933 }
6e2d1486
RK
11934 else if (GET_CODE (insn) == CALL_INSN
11935 && find_reg_fusage (insn, USE, reg))
11936 {
11937 place = insn;
11938 break;
11939 }
230d793d
RS
11940
11941 /* If we found a place to put the link, place it there unless there
11942 is already a link to the same insn as LINK at that point. */
11943
11944 if (place)
11945 {
11946 rtx link2;
11947
11948 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11949 if (XEXP (link2, 0) == XEXP (link, 0))
11950 break;
11951
11952 if (link2 == 0)
11953 {
11954 XEXP (link, 1) = LOG_LINKS (place);
11955 LOG_LINKS (place) = link;
abe6e52f
RK
11956
11957 /* Set added_links_insn to the earliest insn we added a
11958 link to. */
11959 if (added_links_insn == 0
11960 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11961 added_links_insn = place;
230d793d
RS
11962 }
11963 }
11964 }
11965}
11966\f
1427d6d2
RK
11967/* Compute INSN_CUID for INSN, which is an insn made by combine. */
11968
11969static int
11970insn_cuid (insn)
11971 rtx insn;
11972{
11973 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11974 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11975 insn = NEXT_INSN (insn);
11976
11977 if (INSN_UID (insn) > max_uid_cuid)
11978 abort ();
11979
11980 return INSN_CUID (insn);
11981}
11982\f
230d793d
RS
11983void
11984dump_combine_stats (file)
11985 FILE *file;
11986{
11987 fprintf
11988 (file,
11989 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11990 combine_attempts, combine_merges, combine_extras, combine_successes);
11991}
11992
11993void
11994dump_combine_total_stats (file)
11995 FILE *file;
11996{
11997 fprintf
11998 (file,
11999 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12000 total_attempts, total_merges, total_extras, total_successes);
12001}
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