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230d793d RS |
1 | /* Optimize by combining instructions for GNU compiler. |
2 | Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* This module is essentially the "combiner" phase of the U. of Arizona | |
22 | Portable Optimizer, but redone to work on our list-structured | |
23 | representation for RTL instead of their string representation. | |
24 | ||
25 | The LOG_LINKS of each insn identify the most recent assignment | |
26 | to each REG used in the insn. It is a list of previous insns, | |
27 | each of which contains a SET for a REG that is used in this insn | |
28 | and not used or set in between. LOG_LINKs never cross basic blocks. | |
29 | They were set up by the preceding pass (lifetime analysis). | |
30 | ||
31 | We try to combine each pair of insns joined by a logical link. | |
32 | We also try to combine triples of insns A, B and C when | |
33 | C has a link back to B and B has a link back to A. | |
34 | ||
35 | LOG_LINKS does not have links for use of the CC0. They don't | |
36 | need to, because the insn that sets the CC0 is always immediately | |
37 | before the insn that tests it. So we always regard a branch | |
38 | insn as having a logical link to the preceding insn. The same is true | |
39 | for an insn explicitly using CC0. | |
40 | ||
41 | We check (with use_crosses_set_p) to avoid combining in such a way | |
42 | as to move a computation to a place where its value would be different. | |
43 | ||
44 | Combination is done by mathematically substituting the previous | |
45 | insn(s) values for the regs they set into the expressions in | |
46 | the later insns that refer to these regs. If the result is a valid insn | |
47 | for our target machine, according to the machine description, | |
48 | we install it, delete the earlier insns, and update the data flow | |
49 | information (LOG_LINKS and REG_NOTES) for what we did. | |
50 | ||
51 | There are a few exceptions where the dataflow information created by | |
52 | flow.c aren't completely updated: | |
53 | ||
54 | - reg_live_length is not updated | |
55 | - reg_n_refs is not adjusted in the rare case when a register is | |
56 | no longer required in a computation | |
57 | - there are extremely rare cases (see distribute_regnotes) when a | |
58 | REG_DEAD note is lost | |
59 | - a LOG_LINKS entry that refers to an insn with multiple SETs may be | |
60 | removed because there is no way to know which register it was | |
61 | linking | |
62 | ||
63 | To simplify substitution, we combine only when the earlier insn(s) | |
64 | consist of only a single assignment. To simplify updating afterward, | |
65 | we never combine when a subroutine call appears in the middle. | |
66 | ||
67 | Since we do not represent assignments to CC0 explicitly except when that | |
68 | is all an insn does, there is no LOG_LINKS entry in an insn that uses | |
69 | the condition code for the insn that set the condition code. | |
70 | Fortunately, these two insns must be consecutive. | |
71 | Therefore, every JUMP_INSN is taken to have an implicit logical link | |
72 | to the preceding insn. This is not quite right, since non-jumps can | |
73 | also use the condition code; but in practice such insns would not | |
74 | combine anyway. */ | |
75 | ||
76 | #include <stdio.h> | |
77 | ||
78 | #include "config.h" | |
79 | #include "gvarargs.h" | |
80 | #include "rtl.h" | |
81 | #include "flags.h" | |
82 | #include "regs.h" | |
83 | #include "expr.h" | |
84 | #include "basic-block.h" | |
85 | #include "insn-config.h" | |
86 | #include "insn-flags.h" | |
87 | #include "insn-codes.h" | |
88 | #include "insn-attr.h" | |
89 | #include "recog.h" | |
90 | #include "real.h" | |
91 | ||
92 | /* It is not safe to use ordinary gen_lowpart in combine. | |
93 | Use gen_lowpart_for_combine instead. See comments there. */ | |
94 | #define gen_lowpart dont_use_gen_lowpart_you_dummy | |
95 | ||
96 | /* Number of attempts to combine instructions in this function. */ | |
97 | ||
98 | static int combine_attempts; | |
99 | ||
100 | /* Number of attempts that got as far as substitution in this function. */ | |
101 | ||
102 | static int combine_merges; | |
103 | ||
104 | /* Number of instructions combined with added SETs in this function. */ | |
105 | ||
106 | static int combine_extras; | |
107 | ||
108 | /* Number of instructions combined in this function. */ | |
109 | ||
110 | static int combine_successes; | |
111 | ||
112 | /* Totals over entire compilation. */ | |
113 | ||
114 | static int total_attempts, total_merges, total_extras, total_successes; | |
115 | \f | |
116 | /* Vector mapping INSN_UIDs to cuids. | |
5089e22e | 117 | The cuids are like uids but increase monotonically always. |
230d793d RS |
118 | Combine always uses cuids so that it can compare them. |
119 | But actually renumbering the uids, which we used to do, | |
120 | proves to be a bad idea because it makes it hard to compare | |
121 | the dumps produced by earlier passes with those from later passes. */ | |
122 | ||
123 | static int *uid_cuid; | |
124 | ||
125 | /* Get the cuid of an insn. */ | |
126 | ||
127 | #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)]) | |
128 | ||
129 | /* Maximum register number, which is the size of the tables below. */ | |
130 | ||
131 | static int combine_max_regno; | |
132 | ||
133 | /* Record last point of death of (hard or pseudo) register n. */ | |
134 | ||
135 | static rtx *reg_last_death; | |
136 | ||
137 | /* Record last point of modification of (hard or pseudo) register n. */ | |
138 | ||
139 | static rtx *reg_last_set; | |
140 | ||
141 | /* Record the cuid of the last insn that invalidated memory | |
142 | (anything that writes memory, and subroutine calls, but not pushes). */ | |
143 | ||
144 | static int mem_last_set; | |
145 | ||
146 | /* Record the cuid of the last CALL_INSN | |
147 | so we can tell whether a potential combination crosses any calls. */ | |
148 | ||
149 | static int last_call_cuid; | |
150 | ||
151 | /* When `subst' is called, this is the insn that is being modified | |
152 | (by combining in a previous insn). The PATTERN of this insn | |
153 | is still the old pattern partially modified and it should not be | |
154 | looked at, but this may be used to examine the successors of the insn | |
155 | to judge whether a simplification is valid. */ | |
156 | ||
157 | static rtx subst_insn; | |
158 | ||
159 | /* This is the lowest CUID that `subst' is currently dealing with. | |
160 | get_last_value will not return a value if the register was set at or | |
161 | after this CUID. If not for this mechanism, we could get confused if | |
162 | I2 or I1 in try_combine were an insn that used the old value of a register | |
163 | to obtain a new value. In that case, we might erroneously get the | |
164 | new value of the register when we wanted the old one. */ | |
165 | ||
166 | static int subst_low_cuid; | |
167 | ||
168 | /* This is the value of undobuf.num_undo when we started processing this | |
169 | substitution. This will prevent gen_rtx_combine from re-used a piece | |
170 | from the previous expression. Doing so can produce circular rtl | |
171 | structures. */ | |
172 | ||
173 | static int previous_num_undos; | |
174 | \f | |
175 | /* The next group of arrays allows the recording of the last value assigned | |
176 | to (hard or pseudo) register n. We use this information to see if a | |
5089e22e | 177 | operation being processed is redundant given a prior operation performed |
230d793d RS |
178 | on the register. For example, an `and' with a constant is redundant if |
179 | all the zero bits are already known to be turned off. | |
180 | ||
181 | We use an approach similar to that used by cse, but change it in the | |
182 | following ways: | |
183 | ||
184 | (1) We do not want to reinitialize at each label. | |
185 | (2) It is useful, but not critical, to know the actual value assigned | |
186 | to a register. Often just its form is helpful. | |
187 | ||
188 | Therefore, we maintain the following arrays: | |
189 | ||
190 | reg_last_set_value the last value assigned | |
191 | reg_last_set_label records the value of label_tick when the | |
192 | register was assigned | |
193 | reg_last_set_table_tick records the value of label_tick when a | |
194 | value using the register is assigned | |
195 | reg_last_set_invalid set to non-zero when it is not valid | |
196 | to use the value of this register in some | |
197 | register's value | |
198 | ||
199 | To understand the usage of these tables, it is important to understand | |
200 | the distinction between the value in reg_last_set_value being valid | |
201 | and the register being validly contained in some other expression in the | |
202 | table. | |
203 | ||
204 | Entry I in reg_last_set_value is valid if it is non-zero, and either | |
205 | reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick. | |
206 | ||
207 | Register I may validly appear in any expression returned for the value | |
208 | of another register if reg_n_sets[i] is 1. It may also appear in the | |
209 | value for register J if reg_last_set_label[i] < reg_last_set_label[j] or | |
210 | reg_last_set_invalid[j] is zero. | |
211 | ||
212 | If an expression is found in the table containing a register which may | |
213 | not validly appear in an expression, the register is replaced by | |
214 | something that won't match, (clobber (const_int 0)). | |
215 | ||
216 | reg_last_set_invalid[i] is set non-zero when register I is being assigned | |
217 | to and reg_last_set_table_tick[i] == label_tick. */ | |
218 | ||
219 | /* Record last value assigned to (hard or pseudo) register n. */ | |
220 | ||
221 | static rtx *reg_last_set_value; | |
222 | ||
223 | /* Record the value of label_tick when the value for register n is placed in | |
224 | reg_last_set_value[n]. */ | |
225 | ||
226 | static short *reg_last_set_label; | |
227 | ||
228 | /* Record the value of label_tick when an expression involving register n | |
229 | is placed in reg_last_set_value. */ | |
230 | ||
231 | static short *reg_last_set_table_tick; | |
232 | ||
233 | /* Set non-zero if references to register n in expressions should not be | |
234 | used. */ | |
235 | ||
236 | static char *reg_last_set_invalid; | |
237 | ||
238 | /* Incremented for each label. */ | |
239 | ||
240 | static short label_tick; | |
241 | ||
242 | /* Some registers that are set more than once and used in more than one | |
243 | basic block are nevertheless always set in similar ways. For example, | |
244 | a QImode register may be loaded from memory in two places on a machine | |
245 | where byte loads zero extend. | |
246 | ||
247 | We record in the following array what we know about the significant | |
248 | bits of a register, specifically which bits are known to be zero. | |
249 | ||
250 | If an entry is zero, it means that we don't know anything special. */ | |
251 | ||
252 | static int *reg_significant; | |
253 | ||
254 | /* Mode used to compute significance in reg_significant. It is the largest | |
255 | integer mode that can fit in HOST_BITS_PER_INT. */ | |
256 | ||
257 | static enum machine_mode significant_mode; | |
258 | ||
259 | /* Nonzero when reg_significant can be safely used. It is zero while | |
260 | computing reg_significant. This prevents propagating values based | |
261 | on previously set values, which can be incorrect if a variable | |
262 | is modified in a loop. */ | |
263 | ||
264 | static int significant_valid; | |
265 | \f | |
266 | /* Record one modification to rtl structure | |
267 | to be undone by storing old_contents into *where. | |
268 | is_int is 1 if the contents are an int. */ | |
269 | ||
270 | struct undo | |
271 | { | |
272 | rtx *where; | |
273 | rtx old_contents; | |
274 | int is_int; | |
275 | }; | |
276 | ||
277 | struct undo_int | |
278 | { | |
279 | int *where; | |
280 | int old_contents; | |
281 | int is_int; | |
282 | }; | |
283 | ||
284 | /* Record a bunch of changes to be undone, up to MAX_UNDO of them. | |
285 | num_undo says how many are currently recorded. | |
286 | ||
287 | storage is nonzero if we must undo the allocation of new storage. | |
288 | The value of storage is what to pass to obfree. | |
289 | ||
290 | other_insn is nonzero if we have modified some other insn in the process | |
291 | of working on subst_insn. It must be verified too. */ | |
292 | ||
293 | #define MAX_UNDO 50 | |
294 | ||
295 | struct undobuf | |
296 | { | |
297 | int num_undo; | |
298 | char *storage; | |
299 | struct undo undo[MAX_UNDO]; | |
300 | rtx other_insn; | |
301 | }; | |
302 | ||
303 | static struct undobuf undobuf; | |
304 | ||
305 | /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some | |
306 | insn. The substitution can be undone by undo_all. If INTO is already | |
307 | set to NEWVAL, do not record this change. */ | |
308 | ||
309 | #define SUBST(INTO, NEWVAL) \ | |
310 | do { if (undobuf.num_undo < MAX_UNDO) \ | |
311 | { \ | |
312 | undobuf.undo[undobuf.num_undo].where = &INTO; \ | |
313 | undobuf.undo[undobuf.num_undo].old_contents = INTO; \ | |
314 | undobuf.undo[undobuf.num_undo].is_int = 0; \ | |
315 | INTO = NEWVAL; \ | |
316 | if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \ | |
317 | undobuf.num_undo++; \ | |
318 | } \ | |
319 | } while (0) | |
320 | ||
321 | /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT | |
322 | expression. | |
323 | Note that substitution for the value of a CONST_INT is not safe. */ | |
324 | ||
325 | #define SUBST_INT(INTO, NEWVAL) \ | |
326 | do { if (undobuf.num_undo < MAX_UNDO) \ | |
327 | { \ | |
328 | struct undo_int *u \ | |
329 | = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \ | |
330 | u->where = (int *) &INTO; \ | |
331 | u->old_contents = INTO; \ | |
332 | u->is_int = 1; \ | |
333 | INTO = NEWVAL; \ | |
334 | if (u->old_contents != INTO) \ | |
335 | undobuf.num_undo++; \ | |
336 | } \ | |
337 | } while (0) | |
338 | ||
339 | /* Number of times the pseudo being substituted for | |
340 | was found and replaced. */ | |
341 | ||
342 | static int n_occurrences; | |
343 | ||
344 | static void set_significant (); | |
345 | static void move_deaths (); | |
346 | rtx remove_death (); | |
347 | static void record_value_for_reg (); | |
348 | static void record_dead_and_set_regs (); | |
349 | static int use_crosses_set_p (); | |
350 | static rtx try_combine (); | |
351 | static rtx *find_split_point (); | |
352 | static rtx subst (); | |
353 | static void undo_all (); | |
354 | static int reg_dead_at_p (); | |
355 | static rtx expand_compound_operation (); | |
356 | static rtx expand_field_assignment (); | |
357 | static rtx make_extraction (); | |
358 | static int get_pos_from_mask (); | |
359 | static rtx make_field_assignment (); | |
360 | static rtx make_compound_operation (); | |
361 | static rtx apply_distributive_law (); | |
362 | static rtx simplify_and_const_int (); | |
363 | static unsigned significant_bits (); | |
364 | static int merge_outer_ops (); | |
365 | static rtx simplify_shift_const (); | |
366 | static int recog_for_combine (); | |
367 | static rtx gen_lowpart_for_combine (); | |
368 | static rtx gen_rtx_combine (); | |
369 | static rtx gen_binary (); | |
370 | static rtx gen_unary (); | |
371 | static enum rtx_code simplify_comparison (); | |
372 | static int reversible_comparison_p (); | |
373 | static int get_last_value_validate (); | |
374 | static rtx get_last_value (); | |
375 | static void distribute_notes (); | |
376 | static void distribute_links (); | |
377 | \f | |
378 | /* Main entry point for combiner. F is the first insn of the function. | |
379 | NREGS is the first unused pseudo-reg number. */ | |
380 | ||
381 | void | |
382 | combine_instructions (f, nregs) | |
383 | rtx f; | |
384 | int nregs; | |
385 | { | |
386 | register rtx insn, next, prev; | |
387 | register int i; | |
388 | register rtx links, nextlinks; | |
389 | ||
390 | combine_attempts = 0; | |
391 | combine_merges = 0; | |
392 | combine_extras = 0; | |
393 | combine_successes = 0; | |
394 | ||
395 | combine_max_regno = nregs; | |
396 | ||
397 | reg_last_death = (rtx *) alloca (nregs * sizeof (rtx)); | |
398 | reg_last_set = (rtx *) alloca (nregs * sizeof (rtx)); | |
399 | reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx)); | |
400 | reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short)); | |
401 | reg_last_set_label = (short *) alloca (nregs * sizeof (short)); | |
402 | reg_last_set_invalid = (char *) alloca (nregs * sizeof (short)); | |
403 | reg_significant = (int *) alloca (nregs * sizeof (int)); | |
404 | ||
405 | bzero (reg_last_death, nregs * sizeof (rtx)); | |
406 | bzero (reg_last_set, nregs * sizeof (rtx)); | |
407 | bzero (reg_last_set_value, nregs * sizeof (rtx)); | |
408 | bzero (reg_last_set_table_tick, nregs * sizeof (short)); | |
409 | bzero (reg_last_set_invalid, nregs * sizeof (char)); | |
410 | bzero (reg_significant, nregs * sizeof (int)); | |
411 | ||
412 | init_recog_no_volatile (); | |
413 | ||
414 | /* Compute maximum uid value so uid_cuid can be allocated. */ | |
415 | ||
416 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) | |
417 | if (INSN_UID (insn) > i) | |
418 | i = INSN_UID (insn); | |
419 | ||
420 | uid_cuid = (int *) alloca ((i + 1) * sizeof (int)); | |
421 | ||
422 | significant_mode = mode_for_size (HOST_BITS_PER_INT, MODE_INT, 0); | |
423 | ||
424 | /* Don't use reg_significant when computing it. This can cause problems | |
425 | when, for example, we have j <<= 1 in a loop. */ | |
426 | ||
427 | significant_valid = 0; | |
428 | ||
429 | /* Compute the mapping from uids to cuids. | |
430 | Cuids are numbers assigned to insns, like uids, | |
431 | except that cuids increase monotonically through the code. | |
432 | ||
433 | Scan all SETs and see if we can deduce anything about what | |
434 | bits are significant for some registers. */ | |
435 | ||
436 | for (insn = f, i = 0; insn; insn = NEXT_INSN (insn)) | |
437 | { | |
438 | INSN_CUID (insn) = ++i; | |
439 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
440 | note_stores (PATTERN (insn), set_significant); | |
441 | } | |
442 | ||
443 | significant_valid = 1; | |
444 | ||
445 | /* Now scan all the insns in forward order. */ | |
446 | ||
447 | label_tick = 1; | |
448 | last_call_cuid = 0; | |
449 | mem_last_set = 0; | |
450 | ||
451 | for (insn = f; insn; insn = next ? next : NEXT_INSN (insn)) | |
452 | { | |
453 | next = 0; | |
454 | ||
455 | if (GET_CODE (insn) == CODE_LABEL) | |
456 | label_tick++; | |
457 | ||
458 | else if (GET_CODE (insn) == INSN | |
459 | || GET_CODE (insn) == CALL_INSN | |
460 | || GET_CODE (insn) == JUMP_INSN) | |
461 | { | |
462 | /* Try this insn with each insn it links back to. */ | |
463 | ||
464 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
465 | if ((next = try_combine (insn, XEXP (links, 0), 0)) != 0) | |
466 | goto retry; | |
467 | ||
468 | /* Try each sequence of three linked insns ending with this one. */ | |
469 | ||
470 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
471 | for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks; | |
472 | nextlinks = XEXP (nextlinks, 1)) | |
473 | if ((next = try_combine (insn, XEXP (links, 0), | |
474 | XEXP (nextlinks, 0))) != 0) | |
475 | goto retry; | |
476 | ||
477 | #ifdef HAVE_cc0 | |
478 | /* Try to combine a jump insn that uses CC0 | |
479 | with a preceding insn that sets CC0, and maybe with its | |
480 | logical predecessor as well. | |
481 | This is how we make decrement-and-branch insns. | |
482 | We need this special code because data flow connections | |
483 | via CC0 do not get entered in LOG_LINKS. */ | |
484 | ||
485 | if (GET_CODE (insn) == JUMP_INSN | |
486 | && (prev = prev_nonnote_insn (insn)) != 0 | |
487 | && GET_CODE (prev) == INSN | |
488 | && sets_cc0_p (PATTERN (prev))) | |
489 | { | |
490 | if ((next = try_combine (insn, prev, 0)) != 0) | |
491 | goto retry; | |
492 | ||
493 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
494 | nextlinks = XEXP (nextlinks, 1)) | |
495 | if ((next = try_combine (insn, prev, | |
496 | XEXP (nextlinks, 0))) != 0) | |
497 | goto retry; | |
498 | } | |
499 | ||
500 | /* Do the same for an insn that explicitly references CC0. */ | |
501 | if (GET_CODE (insn) == INSN | |
502 | && (prev = prev_nonnote_insn (insn)) != 0 | |
503 | && GET_CODE (prev) == INSN | |
504 | && sets_cc0_p (PATTERN (prev)) | |
505 | && GET_CODE (PATTERN (insn)) == SET | |
506 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn)))) | |
507 | { | |
508 | if ((next = try_combine (insn, prev, 0)) != 0) | |
509 | goto retry; | |
510 | ||
511 | for (nextlinks = LOG_LINKS (prev); nextlinks; | |
512 | nextlinks = XEXP (nextlinks, 1)) | |
513 | if ((next = try_combine (insn, prev, | |
514 | XEXP (nextlinks, 0))) != 0) | |
515 | goto retry; | |
516 | } | |
517 | ||
518 | /* Finally, see if any of the insns that this insn links to | |
519 | explicitly references CC0. If so, try this insn, that insn, | |
5089e22e | 520 | and its predecessor if it sets CC0. */ |
230d793d RS |
521 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) |
522 | if (GET_CODE (XEXP (links, 0)) == INSN | |
523 | && GET_CODE (PATTERN (XEXP (links, 0))) == SET | |
524 | && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0)))) | |
525 | && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0 | |
526 | && GET_CODE (prev) == INSN | |
527 | && sets_cc0_p (PATTERN (prev)) | |
528 | && (next = try_combine (insn, XEXP (links, 0), prev)) != 0) | |
529 | goto retry; | |
530 | #endif | |
531 | ||
532 | /* Try combining an insn with two different insns whose results it | |
533 | uses. */ | |
534 | for (links = LOG_LINKS (insn); links; links = XEXP (links, 1)) | |
535 | for (nextlinks = XEXP (links, 1); nextlinks; | |
536 | nextlinks = XEXP (nextlinks, 1)) | |
537 | if ((next = try_combine (insn, XEXP (links, 0), | |
538 | XEXP (nextlinks, 0))) != 0) | |
539 | goto retry; | |
540 | ||
541 | if (GET_CODE (insn) != NOTE) | |
542 | record_dead_and_set_regs (insn); | |
543 | ||
544 | retry: | |
545 | ; | |
546 | } | |
547 | } | |
548 | ||
549 | total_attempts += combine_attempts; | |
550 | total_merges += combine_merges; | |
551 | total_extras += combine_extras; | |
552 | total_successes += combine_successes; | |
553 | } | |
554 | \f | |
555 | /* Called via note_stores. If X is a pseudo that is used in more than | |
556 | one basic block, is narrower that HOST_BITS_PER_INT, and is being | |
557 | set, record what bits are significant. If we are clobbering X, | |
558 | ignore this "set" because the clobbered value won't be used. | |
559 | ||
560 | If we are setting only a portion of X and we can't figure out what | |
561 | portion, assume all bits will be used since we don't know what will | |
562 | be happening. */ | |
563 | ||
564 | static void | |
565 | set_significant (x, set) | |
566 | rtx x; | |
567 | rtx set; | |
568 | { | |
569 | if (GET_CODE (x) == REG | |
570 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
571 | && reg_n_sets[REGNO (x)] > 1 | |
572 | && reg_basic_block[REGNO (x)] < 0 | |
573 | && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_INT) | |
574 | { | |
575 | if (GET_CODE (set) == CLOBBER) | |
576 | return; | |
577 | ||
578 | /* If this is a complex assignment, see if we can convert it into a | |
5089e22e | 579 | simple assignment. */ |
230d793d RS |
580 | set = expand_field_assignment (set); |
581 | if (SET_DEST (set) == x) | |
582 | reg_significant[REGNO (x)] | |
583 | |= significant_bits (SET_SRC (set), significant_mode); | |
584 | else | |
585 | reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x)); | |
586 | } | |
587 | } | |
588 | \f | |
589 | /* See if INSN can be combined into I3. PRED and SUCC are optionally | |
590 | insns that were previously combined into I3 or that will be combined | |
591 | into the merger of INSN and I3. | |
592 | ||
593 | Return 0 if the combination is not allowed for any reason. | |
594 | ||
595 | If the combination is allowed, *PDEST will be set to the single | |
596 | destination of INSN and *PSRC to the single source, and this function | |
597 | will return 1. */ | |
598 | ||
599 | static int | |
600 | can_combine_p (insn, i3, pred, succ, pdest, psrc) | |
601 | rtx insn; | |
602 | rtx i3; | |
603 | rtx pred, succ; | |
604 | rtx *pdest, *psrc; | |
605 | { | |
606 | int i; | |
607 | rtx set = 0, src, dest; | |
608 | rtx p, link; | |
609 | int all_adjacent = (succ ? (next_active_insn (insn) == succ | |
610 | && next_active_insn (succ) == i3) | |
611 | : next_active_insn (insn) == i3); | |
612 | ||
613 | /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0. | |
614 | or a PARALLEL consisting of such a SET and CLOBBERs. | |
615 | ||
616 | If INSN has CLOBBER parallel parts, ignore them for our processing. | |
617 | By definition, these happen during the execution of the insn. When it | |
618 | is merged with another insn, all bets are off. If they are, in fact, | |
619 | needed and aren't also supplied in I3, they may be added by | |
620 | recog_for_combine. Otherwise, it won't match. | |
621 | ||
622 | We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED | |
623 | note. | |
624 | ||
625 | Get the source and destination of INSN. If more than one, can't | |
626 | combine. */ | |
627 | ||
628 | if (GET_CODE (PATTERN (insn)) == SET) | |
629 | set = PATTERN (insn); | |
630 | else if (GET_CODE (PATTERN (insn)) == PARALLEL | |
631 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) | |
632 | { | |
633 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
634 | { | |
635 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
636 | ||
637 | switch (GET_CODE (elt)) | |
638 | { | |
639 | /* We can ignore CLOBBERs. */ | |
640 | case CLOBBER: | |
641 | break; | |
642 | ||
643 | case SET: | |
644 | /* Ignore SETs whose result isn't used but not those that | |
645 | have side-effects. */ | |
646 | if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt)) | |
647 | && ! side_effects_p (elt)) | |
648 | break; | |
649 | ||
650 | /* If we have already found a SET, this is a second one and | |
651 | so we cannot combine with this insn. */ | |
652 | if (set) | |
653 | return 0; | |
654 | ||
655 | set = elt; | |
656 | break; | |
657 | ||
658 | default: | |
659 | /* Anything else means we can't combine. */ | |
660 | return 0; | |
661 | } | |
662 | } | |
663 | ||
664 | if (set == 0 | |
665 | /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs, | |
666 | so don't do anything with it. */ | |
667 | || GET_CODE (SET_SRC (set)) == ASM_OPERANDS) | |
668 | return 0; | |
669 | } | |
670 | else | |
671 | return 0; | |
672 | ||
673 | if (set == 0) | |
674 | return 0; | |
675 | ||
676 | set = expand_field_assignment (set); | |
677 | src = SET_SRC (set), dest = SET_DEST (set); | |
678 | ||
679 | /* Don't eliminate a store in the stack pointer. */ | |
680 | if (dest == stack_pointer_rtx | |
681 | /* Don't install a subreg involving two modes not tieable. | |
682 | It can worsen register allocation, and can even make invalid reload | |
683 | insns, since the reg inside may need to be copied from in the | |
684 | outside mode, and that may be invalid if it is an fp reg copied in | |
5089e22e RS |
685 | integer mode. As a special exception, we can allow this if |
686 | I3 is simply copying DEST, a REG, to CC0. */ | |
230d793d | 687 | || (GET_CODE (src) == SUBREG |
5089e22e RS |
688 | && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src))) |
689 | #ifdef HAVE_cc0 | |
690 | && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET | |
691 | && SET_DEST (PATTERN (i3)) == cc0_rtx | |
692 | && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3))) | |
693 | #endif | |
694 | ) | |
230d793d RS |
695 | /* If we couldn't eliminate a field assignment, we can't combine. */ |
696 | || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART | |
697 | /* Don't combine with an insn that sets a register to itself if it has | |
698 | a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */ | |
699 | || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, 0)) | |
700 | /* Can't merge a function call. */ | |
701 | || GET_CODE (src) == CALL | |
702 | /* Don't substitute into an incremented register. */ | |
703 | || FIND_REG_INC_NOTE (i3, dest) | |
704 | || (succ && FIND_REG_INC_NOTE (succ, dest)) | |
705 | /* Don't combine the end of a libcall into anything. */ | |
706 | || find_reg_note (insn, REG_RETVAL, 0) | |
707 | /* Make sure that DEST is not used after SUCC but before I3. */ | |
708 | || (succ && ! all_adjacent | |
709 | && reg_used_between_p (dest, succ, i3)) | |
710 | /* Make sure that the value that is to be substituted for the register | |
711 | does not use any registers whose values alter in between. However, | |
712 | If the insns are adjacent, a use can't cross a set even though we | |
713 | think it might (this can happen for a sequence of insns each setting | |
714 | the same destination; reg_last_set of that register might point to | |
715 | a NOTE). Also, don't move a volatile asm across any other insns. */ | |
716 | || (! all_adjacent | |
717 | && (use_crosses_set_p (src, INSN_CUID (insn)) | |
718 | || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src)))) | |
719 | /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get | |
720 | better register allocation by not doing the combine. */ | |
721 | || find_reg_note (i3, REG_NO_CONFLICT, dest) | |
722 | || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest)) | |
723 | /* Don't combine across a CALL_INSN, because that would possibly | |
724 | change whether the life span of some REGs crosses calls or not, | |
725 | and it is a pain to update that information. | |
726 | Exception: if source is a constant, moving it later can't hurt. | |
727 | Accept that special case, because it helps -fforce-addr a lot. */ | |
728 | || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src))) | |
729 | return 0; | |
730 | ||
731 | /* DEST must either be a REG or CC0. */ | |
732 | if (GET_CODE (dest) == REG) | |
733 | { | |
734 | /* If register alignment is being enforced for multi-word items in all | |
735 | cases except for parameters, it is possible to have a register copy | |
736 | insn referencing a hard register that is not allowed to contain the | |
737 | mode being copied and which would not be valid as an operand of most | |
738 | insns. Eliminate this problem by not combining with such an insn. | |
739 | ||
740 | Also, on some machines we don't want to extend the life of a hard | |
741 | register. */ | |
742 | ||
743 | if (GET_CODE (src) == REG | |
744 | && ((REGNO (dest) < FIRST_PSEUDO_REGISTER | |
745 | && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest))) | |
746 | #ifdef SMALL_REGISTER_CLASSES | |
747 | /* Don't extend the life of a hard register. */ | |
748 | || REGNO (src) < FIRST_PSEUDO_REGISTER | |
749 | #else | |
750 | || (REGNO (src) < FIRST_PSEUDO_REGISTER | |
751 | && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))) | |
752 | #endif | |
753 | )) | |
754 | return 0; | |
755 | } | |
756 | else if (GET_CODE (dest) != CC0) | |
757 | return 0; | |
758 | ||
759 | /* Don't substitute for a register intended as a clobberable operand. */ | |
760 | if (GET_CODE (PATTERN (i3)) == PARALLEL) | |
761 | for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--) | |
762 | if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER | |
763 | && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)) | |
764 | return 0; | |
765 | ||
766 | /* If INSN contains anything volatile, or is an `asm' (whether volatile | |
767 | or not), reject, unless nothing volatile comes between it and I3, | |
768 | with the exception of SUCC. */ | |
769 | ||
770 | if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src)) | |
771 | for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p)) | |
772 | if (GET_RTX_CLASS (GET_CODE (p)) == 'i' | |
773 | && p != succ && volatile_refs_p (PATTERN (p))) | |
774 | return 0; | |
775 | ||
776 | /* If INSN or I2 contains an autoincrement or autodecrement, | |
777 | make sure that register is not used between there and I3, | |
778 | and not already used in I3 either. | |
779 | Also insist that I3 not be a jump; if it were one | |
780 | and the incremented register were spilled, we would lose. */ | |
781 | ||
782 | #ifdef AUTO_INC_DEC | |
783 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
784 | if (REG_NOTE_KIND (link) == REG_INC | |
785 | && (GET_CODE (i3) == JUMP_INSN | |
786 | || reg_used_between_p (XEXP (link, 0), insn, i3) | |
787 | || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3)))) | |
788 | return 0; | |
789 | #endif | |
790 | ||
791 | #ifdef HAVE_cc0 | |
792 | /* Don't combine an insn that follows a CC0-setting insn. | |
793 | An insn that uses CC0 must not be separated from the one that sets it. | |
794 | We do, however, allow I2 to follow a CC0-setting insn if that insn | |
795 | is passed as I1; in that case it will be deleted also. | |
796 | We also allow combining in this case if all the insns are adjacent | |
797 | because that would leave the two CC0 insns adjacent as well. | |
798 | It would be more logical to test whether CC0 occurs inside I1 or I2, | |
799 | but that would be much slower, and this ought to be equivalent. */ | |
800 | ||
801 | p = prev_nonnote_insn (insn); | |
802 | if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p)) | |
803 | && ! all_adjacent) | |
804 | return 0; | |
805 | #endif | |
806 | ||
807 | /* If we get here, we have passed all the tests and the combination is | |
808 | to be allowed. */ | |
809 | ||
810 | *pdest = dest; | |
811 | *psrc = src; | |
812 | ||
813 | return 1; | |
814 | } | |
815 | \f | |
816 | /* LOC is the location within I3 that contains its pattern or the component | |
817 | of a PARALLEL of the pattern. We validate that it is valid for combining. | |
818 | ||
819 | One problem is if I3 modifies its output, as opposed to replacing it | |
820 | entirely, we can't allow the output to contain I2DEST or I1DEST as doing | |
821 | so would produce an insn that is not equivalent to the original insns. | |
822 | ||
823 | Consider: | |
824 | ||
825 | (set (reg:DI 101) (reg:DI 100)) | |
826 | (set (subreg:SI (reg:DI 101) 0) <foo>) | |
827 | ||
828 | This is NOT equivalent to: | |
829 | ||
830 | (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>) | |
831 | (set (reg:DI 101) (reg:DI 100))]) | |
832 | ||
833 | Not only does this modify 100 (in which case it might still be valid | |
834 | if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100. | |
835 | ||
836 | We can also run into a problem if I2 sets a register that I1 | |
837 | uses and I1 gets directly substituted into I3 (not via I2). In that | |
838 | case, we would be getting the wrong value of I2DEST into I3, so we | |
839 | must reject the combination. This case occurs when I2 and I1 both | |
840 | feed into I3, rather than when I1 feeds into I2, which feeds into I3. | |
841 | If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source | |
842 | of a SET must prevent combination from occurring. | |
843 | ||
844 | On machines where SMALL_REGISTER_CLASSES is defined, we don't combine | |
845 | if the destination of a SET is a hard register. | |
846 | ||
847 | Before doing the above check, we first try to expand a field assignment | |
848 | into a set of logical operations. | |
849 | ||
850 | If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which | |
851 | we place a register that is both set and used within I3. If more than one | |
852 | such register is detected, we fail. | |
853 | ||
854 | Return 1 if the combination is valid, zero otherwise. */ | |
855 | ||
856 | static int | |
857 | combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed) | |
858 | rtx i3; | |
859 | rtx *loc; | |
860 | rtx i2dest; | |
861 | rtx i1dest; | |
862 | int i1_not_in_src; | |
863 | rtx *pi3dest_killed; | |
864 | { | |
865 | rtx x = *loc; | |
866 | ||
867 | if (GET_CODE (x) == SET) | |
868 | { | |
869 | rtx set = expand_field_assignment (x); | |
870 | rtx dest = SET_DEST (set); | |
871 | rtx src = SET_SRC (set); | |
872 | rtx inner_dest = dest, inner_src = src; | |
873 | ||
874 | SUBST (*loc, set); | |
875 | ||
876 | while (GET_CODE (inner_dest) == STRICT_LOW_PART | |
877 | || GET_CODE (inner_dest) == SUBREG | |
878 | || GET_CODE (inner_dest) == ZERO_EXTRACT) | |
879 | inner_dest = XEXP (inner_dest, 0); | |
880 | ||
881 | /* We probably don't need this any more now that LIMIT_RELOAD_CLASS | |
882 | was added. */ | |
883 | #if 0 | |
884 | while (GET_CODE (inner_src) == STRICT_LOW_PART | |
885 | || GET_CODE (inner_src) == SUBREG | |
886 | || GET_CODE (inner_src) == ZERO_EXTRACT) | |
887 | inner_src = XEXP (inner_src, 0); | |
888 | ||
889 | /* If it is better that two different modes keep two different pseudos, | |
890 | avoid combining them. This avoids producing the following pattern | |
891 | on a 386: | |
892 | (set (subreg:SI (reg/v:QI 21) 0) | |
893 | (lshiftrt:SI (reg/v:SI 20) | |
894 | (const_int 24))) | |
895 | If that were made, reload could not handle the pair of | |
896 | reg 20/21, since it would try to get any GENERAL_REGS | |
897 | but some of them don't handle QImode. */ | |
898 | ||
899 | if (rtx_equal_p (inner_src, i2dest) | |
900 | && GET_CODE (inner_dest) == REG | |
901 | && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest))) | |
902 | return 0; | |
903 | #endif | |
904 | ||
905 | /* Check for the case where I3 modifies its output, as | |
906 | discussed above. */ | |
907 | if ((inner_dest != dest | |
908 | && (reg_overlap_mentioned_p (i2dest, inner_dest) | |
909 | || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest)))) | |
3f508eca RK |
910 | /* This is the same test done in can_combine_p except that we |
911 | allow a hard register with SMALL_REGISTER_CLASSES if SRC is a | |
912 | CALL operation. */ | |
230d793d | 913 | || (GET_CODE (inner_dest) == REG |
dfbe1b2f | 914 | && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER |
3f508eca RK |
915 | #ifdef SMALL_REGISTER_CLASSES |
916 | && GET_CODE (src) != CALL | |
917 | #else | |
dfbe1b2f RK |
918 | && ! HARD_REGNO_MODE_OK (REGNO (inner_dest), |
919 | GET_MODE (inner_dest)) | |
230d793d | 920 | #endif |
dfbe1b2f RK |
921 | ) |
922 | ||
230d793d RS |
923 | || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))) |
924 | return 0; | |
925 | ||
926 | /* If DEST is used in I3, it is being killed in this insn, | |
927 | so record that for later. */ | |
928 | if (pi3dest_killed && GET_CODE (dest) == REG | |
929 | && reg_referenced_p (dest, PATTERN (i3))) | |
930 | { | |
931 | if (*pi3dest_killed) | |
932 | return 0; | |
933 | ||
934 | *pi3dest_killed = dest; | |
935 | } | |
936 | } | |
937 | ||
938 | else if (GET_CODE (x) == PARALLEL) | |
939 | { | |
940 | int i; | |
941 | ||
942 | for (i = 0; i < XVECLEN (x, 0); i++) | |
943 | if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, | |
944 | i1_not_in_src, pi3dest_killed)) | |
945 | return 0; | |
946 | } | |
947 | ||
948 | return 1; | |
949 | } | |
950 | \f | |
951 | /* Try to combine the insns I1 and I2 into I3. | |
952 | Here I1 and I2 appear earlier than I3. | |
953 | I1 can be zero; then we combine just I2 into I3. | |
954 | ||
955 | It we are combining three insns and the resulting insn is not recognized, | |
956 | try splitting it into two insns. If that happens, I2 and I3 are retained | |
957 | and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2 | |
958 | are pseudo-deleted. | |
959 | ||
960 | If we created two insns, return I2; otherwise return I3. | |
961 | Return 0 if the combination does not work. Then nothing is changed. */ | |
962 | ||
963 | static rtx | |
964 | try_combine (i3, i2, i1) | |
965 | register rtx i3, i2, i1; | |
966 | { | |
967 | /* New patterns for I3 and I3, respectively. */ | |
968 | rtx newpat, newi2pat = 0; | |
969 | /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */ | |
970 | int added_sets_1, added_sets_2; | |
971 | /* Total number of SETs to put into I3. */ | |
972 | int total_sets; | |
973 | /* Nonzero is I2's body now appears in I3. */ | |
974 | int i2_is_used; | |
975 | /* INSN_CODEs for new I3, new I2, and user of condition code. */ | |
976 | int insn_code_number, i2_code_number, other_code_number; | |
977 | /* Contains I3 if the destination of I3 is used in its source, which means | |
978 | that the old life of I3 is being killed. If that usage is placed into | |
979 | I2 and not in I3, a REG_DEAD note must be made. */ | |
980 | rtx i3dest_killed = 0; | |
981 | /* SET_DEST and SET_SRC of I2 and I1. */ | |
982 | rtx i2dest, i2src, i1dest = 0, i1src = 0; | |
983 | /* PATTERN (I2), or a copy of it in certain cases. */ | |
984 | rtx i2pat; | |
985 | /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */ | |
986 | int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0; | |
987 | int i1_feeds_i3 = 0; | |
988 | /* Notes that must be added to REG_NOTES in I3 and I2. */ | |
989 | rtx new_i3_notes, new_i2_notes; | |
990 | ||
991 | int maxreg; | |
992 | rtx temp; | |
993 | register rtx link; | |
994 | int i; | |
995 | ||
996 | /* If any of I1, I2, and I3 isn't really an insn, we can't do anything. | |
997 | This can occur when flow deletes an insn that it has merged into an | |
998 | auto-increment address. We also can't do anything if I3 has a | |
999 | REG_LIBCALL note since we don't want to disrupt the contiguity of a | |
1000 | libcall. */ | |
1001 | ||
1002 | if (GET_RTX_CLASS (GET_CODE (i3)) != 'i' | |
1003 | || GET_RTX_CLASS (GET_CODE (i2)) != 'i' | |
1004 | || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i') | |
1005 | || find_reg_note (i3, REG_LIBCALL, 0)) | |
1006 | return 0; | |
1007 | ||
1008 | combine_attempts++; | |
1009 | ||
1010 | undobuf.num_undo = previous_num_undos = 0; | |
1011 | undobuf.other_insn = 0; | |
1012 | ||
1013 | /* Save the current high-water-mark so we can free storage if we didn't | |
1014 | accept this combination. */ | |
1015 | undobuf.storage = (char *) oballoc (0); | |
1016 | ||
1017 | /* If I1 and I2 both feed I3, they can be in any order. To simplify the | |
1018 | code below, set I1 to be the earlier of the two insns. */ | |
1019 | if (i1 && INSN_CUID (i1) > INSN_CUID (i2)) | |
1020 | temp = i1, i1 = i2, i2 = temp; | |
1021 | ||
1022 | /* First check for one important special-case that the code below will | |
1023 | not handle. Namely, the case where I1 is zero, I2 has multiple sets, | |
1024 | and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case, | |
1025 | we may be able to replace that destination with the destination of I3. | |
1026 | This occurs in the common code where we compute both a quotient and | |
1027 | remainder into a structure, in which case we want to do the computation | |
1028 | directly into the structure to avoid register-register copies. | |
1029 | ||
1030 | We make very conservative checks below and only try to handle the | |
1031 | most common cases of this. For example, we only handle the case | |
1032 | where I2 and I3 are adjacent to avoid making difficult register | |
1033 | usage tests. */ | |
1034 | ||
1035 | if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET | |
1036 | && GET_CODE (SET_SRC (PATTERN (i3))) == REG | |
1037 | && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER | |
1038 | #ifdef SMALL_REGISTER_CLASSES | |
1039 | && (GET_CODE (SET_DEST (PATTERN (i3))) != REG | |
1040 | || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER) | |
1041 | #endif | |
1042 | && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3))) | |
1043 | && GET_CODE (PATTERN (i2)) == PARALLEL | |
1044 | && ! side_effects_p (SET_DEST (PATTERN (i3))) | |
5089e22e RS |
1045 | /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code |
1046 | below would need to check what is inside (and reg_overlap_mentioned_p | |
1047 | doesn't support those codes anyway). Don't allow those destinations; | |
1048 | the resulting insn isn't likely to be recognized anyway. */ | |
1049 | && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT | |
1050 | && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART | |
230d793d RS |
1051 | && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)), |
1052 | SET_DEST (PATTERN (i3))) | |
1053 | && next_real_insn (i2) == i3) | |
5089e22e RS |
1054 | { |
1055 | rtx p2 = PATTERN (i2); | |
1056 | ||
1057 | /* Make sure that the destination of I3, | |
1058 | which we are going to substitute into one output of I2, | |
1059 | is not used within another output of I2. We must avoid making this: | |
1060 | (parallel [(set (mem (reg 69)) ...) | |
1061 | (set (reg 69) ...)]) | |
1062 | which is not well-defined as to order of actions. | |
1063 | (Besides, reload can't handle output reloads for this.) | |
1064 | ||
1065 | The problem can also happen if the dest of I3 is a memory ref, | |
1066 | if another dest in I2 is an indirect memory ref. */ | |
1067 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
1068 | if (GET_CODE (XVECEXP (p2, 0, i)) == SET | |
1069 | && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), | |
1070 | SET_DEST (XVECEXP (p2, 0, i)))) | |
1071 | break; | |
230d793d | 1072 | |
5089e22e RS |
1073 | if (i == XVECLEN (p2, 0)) |
1074 | for (i = 0; i < XVECLEN (p2, 0); i++) | |
1075 | if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3))) | |
1076 | { | |
1077 | combine_merges++; | |
230d793d | 1078 | |
5089e22e RS |
1079 | subst_insn = i3; |
1080 | subst_low_cuid = INSN_CUID (i2); | |
230d793d | 1081 | |
5089e22e RS |
1082 | added_sets_2 = 0; |
1083 | i2dest = SET_SRC (PATTERN (i3)); | |
230d793d | 1084 | |
5089e22e RS |
1085 | /* Replace the dest in I2 with our dest and make the resulting |
1086 | insn the new pattern for I3. Then skip to where we | |
1087 | validate the pattern. Everything was set up above. */ | |
1088 | SUBST (SET_DEST (XVECEXP (p2, 0, i)), | |
1089 | SET_DEST (PATTERN (i3))); | |
1090 | ||
1091 | newpat = p2; | |
1092 | goto validate_replacement; | |
1093 | } | |
1094 | } | |
230d793d RS |
1095 | |
1096 | #ifndef HAVE_cc0 | |
1097 | /* If we have no I1 and I2 looks like: | |
1098 | (parallel [(set (reg:CC X) (compare:CC OP (const_int 0))) | |
1099 | (set Y OP)]) | |
1100 | make up a dummy I1 that is | |
1101 | (set Y OP) | |
1102 | and change I2 to be | |
1103 | (set (reg:CC X) (compare:CC Y (const_int 0))) | |
1104 | ||
1105 | (We can ignore any trailing CLOBBERs.) | |
1106 | ||
1107 | This undoes a previous combination and allows us to match a branch-and- | |
1108 | decrement insn. */ | |
1109 | ||
1110 | if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL | |
1111 | && XVECLEN (PATTERN (i2), 0) >= 2 | |
1112 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET | |
1113 | && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)))) | |
1114 | == MODE_CC) | |
1115 | && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE | |
1116 | && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx | |
1117 | && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET | |
1118 | && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG | |
1119 | && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0), | |
1120 | SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))) | |
1121 | { | |
1122 | for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--) | |
1123 | if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER) | |
1124 | break; | |
1125 | ||
1126 | if (i == 1) | |
1127 | { | |
1128 | /* We make I1 with the same INSN_UID as I2. This gives it | |
1129 | the same INSN_CUID for value tracking. Our fake I1 will | |
1130 | never appear in the insn stream so giving it the same INSN_UID | |
1131 | as I2 will not cause a problem. */ | |
1132 | ||
1133 | i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2, | |
1134 | XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0); | |
1135 | ||
1136 | SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0)); | |
1137 | SUBST (XEXP (SET_SRC (PATTERN (i2)), 0), | |
1138 | SET_DEST (PATTERN (i1))); | |
1139 | } | |
1140 | } | |
1141 | #endif | |
1142 | ||
1143 | /* Verify that I2 and I1 are valid for combining. */ | |
1144 | if (! can_combine_p (i2, i3, i1, 0, &i2dest, &i2src) | |
1145 | || (i1 && ! can_combine_p (i1, i3, 0, i2, &i1dest, &i1src))) | |
1146 | { | |
1147 | undo_all (); | |
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | /* Record whether I2DEST is used in I2SRC and similarly for the other | |
1152 | cases. Knowing this will help in register status updating below. */ | |
1153 | i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src); | |
1154 | i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src); | |
1155 | i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src); | |
1156 | ||
916f14f1 | 1157 | /* See if I1 directly feeds into I3. It does if I1DEST is not used |
230d793d RS |
1158 | in I2SRC. */ |
1159 | i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src); | |
1160 | ||
1161 | /* Ensure that I3's pattern can be the destination of combines. */ | |
1162 | if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, | |
1163 | i1 && i2dest_in_i1src && i1_feeds_i3, | |
1164 | &i3dest_killed)) | |
1165 | { | |
1166 | undo_all (); | |
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd. | |
1171 | We used to do this EXCEPT in one case: I3 has a post-inc in an | |
1172 | output operand. However, that exception can give rise to insns like | |
1173 | mov r3,(r3)+ | |
1174 | which is a famous insn on the PDP-11 where the value of r3 used as the | |
5089e22e | 1175 | source was model-dependent. Avoid this sort of thing. */ |
230d793d RS |
1176 | |
1177 | #if 0 | |
1178 | if (!(GET_CODE (PATTERN (i3)) == SET | |
1179 | && GET_CODE (SET_SRC (PATTERN (i3))) == REG | |
1180 | && GET_CODE (SET_DEST (PATTERN (i3))) == MEM | |
1181 | && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC | |
1182 | || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC))) | |
1183 | /* It's not the exception. */ | |
1184 | #endif | |
1185 | #ifdef AUTO_INC_DEC | |
1186 | for (link = REG_NOTES (i3); link; link = XEXP (link, 1)) | |
1187 | if (REG_NOTE_KIND (link) == REG_INC | |
1188 | && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2)) | |
1189 | || (i1 != 0 | |
1190 | && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1))))) | |
1191 | { | |
1192 | undo_all (); | |
1193 | return 0; | |
1194 | } | |
1195 | #endif | |
1196 | ||
1197 | /* See if the SETs in I1 or I2 need to be kept around in the merged | |
1198 | instruction: whenever the value set there is still needed past I3. | |
1199 | For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3. | |
1200 | ||
1201 | For the SET in I1, we have two cases: If I1 and I2 independently | |
1202 | feed into I3, the set in I1 needs to be kept around if I1DEST dies | |
1203 | or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set | |
1204 | in I1 needs to be kept around unless I1DEST dies or is set in either | |
1205 | I2 or I3. We can distinguish these cases by seeing if I2SRC mentions | |
1206 | I1DEST. If so, we know I1 feeds into I2. */ | |
1207 | ||
1208 | added_sets_2 = ! dead_or_set_p (i3, i2dest); | |
1209 | ||
1210 | added_sets_1 | |
1211 | = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest) | |
1212 | : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest))); | |
1213 | ||
1214 | /* If the set in I2 needs to be kept around, we must make a copy of | |
1215 | PATTERN (I2), so that when we substitute I1SRC for I1DEST in | |
5089e22e | 1216 | PATTERN (I2), we are only substituting for the original I1DEST, not into |
230d793d RS |
1217 | an already-substituted copy. This also prevents making self-referential |
1218 | rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to | |
1219 | I2DEST. */ | |
1220 | ||
1221 | i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL | |
1222 | ? gen_rtx (SET, VOIDmode, i2dest, i2src) | |
1223 | : PATTERN (i2)); | |
1224 | ||
1225 | if (added_sets_2) | |
1226 | i2pat = copy_rtx (i2pat); | |
1227 | ||
1228 | combine_merges++; | |
1229 | ||
1230 | /* Substitute in the latest insn for the regs set by the earlier ones. */ | |
1231 | ||
1232 | maxreg = max_reg_num (); | |
1233 | ||
1234 | subst_insn = i3; | |
1235 | subst_low_cuid = i1 ? INSN_CUID (i1) : INSN_CUID (i2); | |
1236 | ||
1237 | /* It is possible that the source of I2 or I1 may be performing an | |
1238 | unneeded operation, such as a ZERO_EXTEND of something that is known | |
1239 | to have the high part zero. Handle that case by letting subst look at | |
1240 | the innermost one of them. | |
1241 | ||
1242 | Another way to do this would be to have a function that tries to | |
1243 | simplify a single insn instead of merging two or more insns. We don't | |
1244 | do this because of the potential of infinite loops and because | |
1245 | of the potential extra memory required. However, doing it the way | |
1246 | we are is a bit of a kludge and doesn't catch all cases. | |
1247 | ||
1248 | But only do this if -fexpensive-optimizations since it slows things down | |
1249 | and doesn't usually win. */ | |
1250 | ||
1251 | if (flag_expensive_optimizations) | |
1252 | { | |
1253 | /* Pass pc_rtx so no substitutions are done, just simplifications. | |
1254 | The cases that we are interested in here do not involve the few | |
1255 | cases were is_replaced is checked. */ | |
1256 | if (i1) | |
1257 | i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0); | |
1258 | else | |
1259 | i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0); | |
1260 | ||
1261 | previous_num_undos = undobuf.num_undo; | |
1262 | } | |
1263 | ||
1264 | #ifndef HAVE_cc0 | |
1265 | /* Many machines that don't use CC0 have insns that can both perform an | |
1266 | arithmetic operation and set the condition code. These operations will | |
1267 | be represented as a PARALLEL with the first element of the vector | |
1268 | being a COMPARE of an arithmetic operation with the constant zero. | |
1269 | The second element of the vector will set some pseudo to the result | |
1270 | of the same arithmetic operation. If we simplify the COMPARE, we won't | |
1271 | match such a pattern and so will generate an extra insn. Here we test | |
1272 | for this case, where both the comparison and the operation result are | |
1273 | needed, and make the PARALLEL by just replacing I2DEST in I3SRC with | |
1274 | I2SRC. Later we will make the PARALLEL that contains I2. */ | |
1275 | ||
1276 | if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET | |
1277 | && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE | |
1278 | && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx | |
1279 | && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest)) | |
1280 | { | |
1281 | rtx *cc_use; | |
1282 | enum machine_mode compare_mode; | |
1283 | ||
1284 | newpat = PATTERN (i3); | |
1285 | SUBST (XEXP (SET_SRC (newpat), 0), i2src); | |
1286 | ||
1287 | i2_is_used = 1; | |
1288 | ||
1289 | #ifdef EXTRA_CC_MODES | |
1290 | /* See if a COMPARE with the operand we substituted in should be done | |
1291 | with the mode that is currently being used. If not, do the same | |
1292 | processing we do in `subst' for a SET; namely, if the destination | |
1293 | is used only once, try to replace it with a register of the proper | |
1294 | mode and also replace the COMPARE. */ | |
1295 | if (undobuf.other_insn == 0 | |
1296 | && (cc_use = find_single_use (SET_DEST (newpat), i3, | |
1297 | &undobuf.other_insn)) | |
1298 | && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), i2src)) | |
1299 | != GET_MODE (SET_DEST (newpat)))) | |
1300 | { | |
1301 | int regno = REGNO (SET_DEST (newpat)); | |
1302 | rtx new_dest = gen_rtx (REG, compare_mode, regno); | |
1303 | ||
1304 | if (regno < FIRST_PSEUDO_REGISTER | |
1305 | || (reg_n_sets[regno] == 1 && ! added_sets_2 | |
1306 | && ! REG_USERVAR_P (SET_DEST (newpat)))) | |
1307 | { | |
1308 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1309 | SUBST (regno_reg_rtx[regno], new_dest); | |
1310 | ||
1311 | SUBST (SET_DEST (newpat), new_dest); | |
1312 | SUBST (XEXP (*cc_use, 0), new_dest); | |
1313 | SUBST (SET_SRC (newpat), | |
1314 | gen_rtx_combine (COMPARE, compare_mode, | |
1315 | i2src, const0_rtx)); | |
1316 | } | |
1317 | else | |
1318 | undobuf.other_insn = 0; | |
1319 | } | |
1320 | #endif | |
1321 | } | |
1322 | else | |
1323 | #endif | |
1324 | { | |
1325 | n_occurrences = 0; /* `subst' counts here */ | |
1326 | ||
1327 | /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we | |
1328 | need to make a unique copy of I2SRC each time we substitute it | |
1329 | to avoid self-referential rtl. */ | |
1330 | ||
1331 | newpat = subst (PATTERN (i3), i2dest, i2src, 0, | |
1332 | ! i1_feeds_i3 && i1dest_in_i1src); | |
1333 | previous_num_undos = undobuf.num_undo; | |
1334 | ||
1335 | /* Record whether i2's body now appears within i3's body. */ | |
1336 | i2_is_used = n_occurrences; | |
1337 | } | |
1338 | ||
1339 | /* If we already got a failure, don't try to do more. Otherwise, | |
1340 | try to substitute in I1 if we have it. */ | |
1341 | ||
1342 | if (i1 && GET_CODE (newpat) != CLOBBER) | |
1343 | { | |
1344 | /* Before we can do this substitution, we must redo the test done | |
1345 | above (see detailed comments there) that ensures that I1DEST | |
1346 | isn't mentioned in any SETs in NEWPAT that are field assignments. */ | |
1347 | ||
1348 | if (! combinable_i3pat (0, &newpat, i1dest, 0, 0, 0)) | |
1349 | { | |
1350 | undo_all (); | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | n_occurrences = 0; | |
1355 | newpat = subst (newpat, i1dest, i1src, 0, 0); | |
1356 | previous_num_undos = undobuf.num_undo; | |
1357 | } | |
1358 | ||
916f14f1 RK |
1359 | /* Fail if an autoincrement side-effect has been duplicated. Be careful |
1360 | to count all the ways that I2SRC and I1SRC can be used. */ | |
1361 | if ((FIND_REG_INC_NOTE (i2, 0) != 0 | |
1362 | && i2_is_used + added_sets_2 > 1) | |
1363 | || (i1 != 0 && FIND_REG_INC_NOTE (i1, 0) != 0 | |
1364 | && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3) | |
1365 | > 1)) | |
230d793d RS |
1366 | /* Fail if we tried to make a new register (we used to abort, but there's |
1367 | really no reason to). */ | |
1368 | || max_reg_num () != maxreg | |
1369 | /* Fail if we couldn't do something and have a CLOBBER. */ | |
1370 | || GET_CODE (newpat) == CLOBBER) | |
1371 | { | |
1372 | undo_all (); | |
1373 | return 0; | |
1374 | } | |
1375 | ||
1376 | /* If the actions of the earlier insns must be kept | |
1377 | in addition to substituting them into the latest one, | |
1378 | we must make a new PARALLEL for the latest insn | |
1379 | to hold additional the SETs. */ | |
1380 | ||
1381 | if (added_sets_1 || added_sets_2) | |
1382 | { | |
1383 | combine_extras++; | |
1384 | ||
1385 | if (GET_CODE (newpat) == PARALLEL) | |
1386 | { | |
1387 | rtvec old = XVEC (newpat, 0); | |
1388 | total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2; | |
1389 | newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); | |
1390 | bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0), | |
1391 | sizeof (old->elem[0]) * old->num_elem); | |
1392 | } | |
1393 | else | |
1394 | { | |
1395 | rtx old = newpat; | |
1396 | total_sets = 1 + added_sets_1 + added_sets_2; | |
1397 | newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets)); | |
1398 | XVECEXP (newpat, 0, 0) = old; | |
1399 | } | |
1400 | ||
1401 | if (added_sets_1) | |
1402 | XVECEXP (newpat, 0, --total_sets) | |
1403 | = (GET_CODE (PATTERN (i1)) == PARALLEL | |
1404 | ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1)); | |
1405 | ||
1406 | if (added_sets_2) | |
1407 | { | |
1408 | /* If there is no I1, use I2's body as is. We used to also not do | |
1409 | the subst call below if I2 was substituted into I3, | |
1410 | but that could lose a simplification. */ | |
1411 | if (i1 == 0) | |
1412 | XVECEXP (newpat, 0, --total_sets) = i2pat; | |
1413 | else | |
1414 | /* See comment where i2pat is assigned. */ | |
1415 | XVECEXP (newpat, 0, --total_sets) | |
1416 | = subst (i2pat, i1dest, i1src, 0, 0); | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /* We come here when we are replacing a destination in I2 with the | |
1421 | destination of I3. */ | |
1422 | validate_replacement: | |
1423 | ||
1424 | /* Is the result of combination a valid instruction? */ | |
1425 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1426 | ||
1427 | /* If the result isn't valid, see if it is a PARALLEL of two SETs where | |
1428 | the second SET's destination is a register that is unused. In that case, | |
1429 | we just need the first SET. This can occur when simplifying a divmod | |
1430 | insn. We *must* test for this case here because the code below that | |
1431 | splits two independent SETs doesn't handle this case correctly when it | |
1432 | updates the register status. Also check the case where the first | |
1433 | SET's destination is unused. That would not cause incorrect code, but | |
1434 | does cause an unneeded insn to remain. */ | |
1435 | ||
1436 | if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL | |
1437 | && XVECLEN (newpat, 0) == 2 | |
1438 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
1439 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
1440 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG | |
1441 | && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1))) | |
1442 | && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1))) | |
1443 | && asm_noperands (newpat) < 0) | |
1444 | { | |
1445 | newpat = XVECEXP (newpat, 0, 0); | |
1446 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1447 | } | |
1448 | ||
1449 | else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL | |
1450 | && XVECLEN (newpat, 0) == 2 | |
1451 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
1452 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
1453 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG | |
1454 | && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0))) | |
1455 | && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0))) | |
1456 | && asm_noperands (newpat) < 0) | |
1457 | { | |
1458 | newpat = XVECEXP (newpat, 0, 1); | |
1459 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1460 | } | |
1461 | ||
1462 | /* If we were combining three insns and the result is a simple SET | |
1463 | with no ASM_OPERANDS that wasn't recognized, try to split it into two | |
916f14f1 RK |
1464 | insns. There are two ways to do this. It can be split using a |
1465 | machine-specific method (like when you have an addition of a large | |
1466 | constant) or by combine in the function find_split_point. */ | |
1467 | ||
230d793d RS |
1468 | if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET |
1469 | && asm_noperands (newpat) < 0) | |
1470 | { | |
916f14f1 RK |
1471 | rtx m_split, *split; |
1472 | ||
1473 | /* See if the MD file can split NEWPAT. If it can't, see if letting it | |
1474 | use I2DEST as a scratch register will help. */ | |
1475 | ||
1476 | m_split = split_insns (newpat, i3); | |
1477 | if (m_split == 0) | |
1478 | m_split = split_insns (gen_rtx (PARALLEL, VOIDmode, | |
1479 | gen_rtvec (2, newpat, | |
1480 | gen_rtx (CLOBBER, VOIDmode, | |
1481 | i2dest))), | |
1482 | i3); | |
1483 | ||
1484 | if (m_split && GET_CODE (m_split) == SEQUENCE | |
3f508eca RK |
1485 | && XVECLEN (m_split, 0) == 2 |
1486 | && (next_real_insn (i2) == i3 | |
1487 | || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)), | |
1488 | INSN_CUID (i2)))) | |
916f14f1 RK |
1489 | { |
1490 | newi2pat = PATTERN (XVECEXP (m_split, 0, 0)); | |
1491 | newpat = PATTERN (XVECEXP (m_split, 0, 1)); | |
1492 | ||
1493 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
1494 | if (i2_code_number >= 0) | |
1495 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1496 | } | |
230d793d RS |
1497 | |
1498 | /* If we can split it and use I2DEST, go ahead and see if that | |
1499 | helps things be recognized. Verify that none of the registers | |
1500 | are set between I2 and I3. */ | |
916f14f1 | 1501 | else if ((split = find_split_point (&newpat)) != 0 |
230d793d RS |
1502 | #ifdef HAVE_cc0 |
1503 | && GET_CODE (i2dest) == REG | |
1504 | #endif | |
1505 | /* We need I2DEST in the proper mode. If it is a hard register | |
1506 | or the only use of a pseudo, we can change its mode. */ | |
1507 | && (GET_MODE (*split) == GET_MODE (i2dest) | |
1508 | || GET_MODE (*split) == VOIDmode | |
1509 | || REGNO (i2dest) < FIRST_PSEUDO_REGISTER | |
1510 | || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2 | |
1511 | && ! REG_USERVAR_P (i2dest))) | |
1512 | && (next_real_insn (i2) == i3 | |
1513 | || ! use_crosses_set_p (*split, INSN_CUID (i2))) | |
1514 | /* We can't overwrite I2DEST if its value is still used by | |
1515 | NEWPAT. */ | |
1516 | && ! reg_referenced_p (i2dest, newpat)) | |
1517 | { | |
1518 | rtx newdest = i2dest; | |
1519 | ||
1520 | /* Get NEWDEST as a register in the proper mode. We have already | |
1521 | validated that we can do this. */ | |
1522 | if (GET_MODE (i2dest) != GET_MODE (*split) | |
1523 | && GET_MODE (*split) != VOIDmode) | |
1524 | { | |
1525 | newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest)); | |
1526 | ||
1527 | if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER) | |
1528 | SUBST (regno_reg_rtx[REGNO (i2dest)], newdest); | |
1529 | } | |
1530 | ||
1531 | /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to | |
1532 | an ASHIFT. This can occur if it was inside a PLUS and hence | |
1533 | appeared to be a memory address. This is a kludge. */ | |
1534 | if (GET_CODE (*split) == MULT | |
1535 | && GET_CODE (XEXP (*split, 1)) == CONST_INT | |
1536 | && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0) | |
1537 | SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split), | |
1538 | XEXP (*split, 0), | |
1539 | gen_rtx (CONST_INT, VOIDmode, i))); | |
1540 | ||
1541 | #ifdef INSN_SCHEDULING | |
1542 | /* If *SPLIT is a paradoxical SUBREG, when we split it, it should | |
1543 | be written as a ZERO_EXTEND. */ | |
1544 | if (GET_CODE (*split) == SUBREG | |
1545 | && GET_CODE (SUBREG_REG (*split)) == MEM) | |
1546 | SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split), | |
1547 | XEXP (*split, 0))); | |
1548 | #endif | |
1549 | ||
1550 | newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split); | |
1551 | SUBST (*split, newdest); | |
1552 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
1553 | if (i2_code_number >= 0) | |
1554 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | /* Check for a case where we loaded from memory in a narrow mode and | |
1559 | then sign extended it, but we need both registers. In that case, | |
1560 | we have a PARALLEL with both loads from the same memory location. | |
1561 | We can split this into a load from memory followed by a register-register | |
1562 | copy. This saves at least one insn, more if register allocation can | |
1563 | eliminate the copy. */ | |
1564 | ||
1565 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
1566 | && GET_CODE (newpat) == PARALLEL | |
1567 | && XVECLEN (newpat, 0) == 2 | |
1568 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
1569 | && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND | |
1570 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
1571 | && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
1572 | XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0)) | |
1573 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
1574 | INSN_CUID (i2)) | |
1575 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
1576 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
1577 | && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
1578 | SET_SRC (XVECEXP (newpat, 0, 1))) | |
1579 | && ! find_reg_note (i3, REG_UNUSED, | |
1580 | SET_DEST (XVECEXP (newpat, 0, 0)))) | |
1581 | { | |
1582 | newi2pat = XVECEXP (newpat, 0, 0); | |
1583 | newpat = XVECEXP (newpat, 0, 1); | |
1584 | SUBST (SET_SRC (newpat), | |
1585 | gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), | |
1586 | SET_DEST (newi2pat))); | |
1587 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
1588 | if (i2_code_number >= 0) | |
1589 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
5089e22e RS |
1590 | |
1591 | if (insn_code_number >= 0) | |
1592 | { | |
1593 | rtx insn; | |
1594 | rtx link; | |
1595 | ||
1596 | /* If we will be able to accept this, we have made a change to the | |
1597 | destination of I3. This can invalidate a LOG_LINKS pointing | |
1598 | to I3. No other part of combine.c makes such a transformation. | |
1599 | ||
1600 | The new I3 will have a destination that was previously the | |
1601 | destination of I1 or I2 and which was used in i2 or I3. Call | |
1602 | distribute_links to make a LOG_LINK from the next use of | |
1603 | that destination. */ | |
1604 | ||
1605 | PATTERN (i3) = newpat; | |
1606 | distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, 0)); | |
1607 | ||
1608 | /* I3 now uses what used to be its destination and which is | |
1609 | now I2's destination. That means we need a LOG_LINK from | |
1610 | I3 to I2. But we used to have one, so we still will. | |
1611 | ||
1612 | However, some later insn might be using I2's dest and have | |
1613 | a LOG_LINK pointing at I3. We must remove this link. | |
1614 | The simplest way to remove the link is to point it at I1, | |
1615 | which we know will be a NOTE. */ | |
1616 | ||
1617 | for (insn = NEXT_INSN (i3); | |
1618 | insn && GET_CODE (insn) != CODE_LABEL | |
1619 | && GET_CODE (PREV_INSN (insn)) != JUMP_INSN; | |
1620 | insn = NEXT_INSN (insn)) | |
1621 | { | |
1622 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
1623 | && reg_referenced_p (SET_DEST (newi2pat), PATTERN (insn))) | |
1624 | { | |
1625 | for (link = LOG_LINKS (insn); link; | |
1626 | link = XEXP (link, 1)) | |
1627 | if (XEXP (link, 0) == i3) | |
1628 | XEXP (link, 0) = i1; | |
1629 | ||
1630 | break; | |
1631 | } | |
1632 | } | |
1633 | } | |
230d793d RS |
1634 | } |
1635 | ||
1636 | /* Similarly, check for a case where we have a PARALLEL of two independent | |
1637 | SETs but we started with three insns. In this case, we can do the sets | |
1638 | as two separate insns. This case occurs when some SET allows two | |
1639 | other insns to combine, but the destination of that SET is still live. */ | |
1640 | ||
1641 | else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0 | |
1642 | && GET_CODE (newpat) == PARALLEL | |
1643 | && XVECLEN (newpat, 0) == 2 | |
1644 | && GET_CODE (XVECEXP (newpat, 0, 0)) == SET | |
1645 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT | |
1646 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART | |
1647 | && GET_CODE (XVECEXP (newpat, 0, 1)) == SET | |
1648 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT | |
1649 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART | |
1650 | && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)), | |
1651 | INSN_CUID (i2)) | |
1652 | /* Don't pass sets with (USE (MEM ...)) dests to the following. */ | |
1653 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE | |
1654 | && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE | |
1655 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)), | |
1656 | XVECEXP (newpat, 0, 0)) | |
1657 | && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)), | |
1658 | XVECEXP (newpat, 0, 1))) | |
1659 | { | |
1660 | newi2pat = XVECEXP (newpat, 0, 1); | |
1661 | newpat = XVECEXP (newpat, 0, 0); | |
1662 | ||
1663 | i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes); | |
1664 | if (i2_code_number >= 0) | |
1665 | insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes); | |
1666 | } | |
1667 | ||
1668 | /* If it still isn't recognized, fail and change things back the way they | |
1669 | were. */ | |
1670 | if ((insn_code_number < 0 | |
1671 | /* Is the result a reasonable ASM_OPERANDS? */ | |
1672 | && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2))) | |
1673 | { | |
1674 | undo_all (); | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | /* If we had to change another insn, make sure it is valid also. */ | |
1679 | if (undobuf.other_insn) | |
1680 | { | |
1681 | rtx other_notes = REG_NOTES (undobuf.other_insn); | |
1682 | rtx other_pat = PATTERN (undobuf.other_insn); | |
1683 | rtx new_other_notes; | |
1684 | rtx note, next; | |
1685 | ||
1686 | other_code_number = recog_for_combine (&other_pat, undobuf.other_insn, | |
1687 | &new_other_notes); | |
1688 | ||
1689 | if (other_code_number < 0 && ! check_asm_operands (other_pat)) | |
1690 | { | |
1691 | undo_all (); | |
1692 | return 0; | |
1693 | } | |
1694 | ||
1695 | PATTERN (undobuf.other_insn) = other_pat; | |
1696 | ||
1697 | /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they | |
1698 | are still valid. Then add any non-duplicate notes added by | |
1699 | recog_for_combine. */ | |
1700 | for (note = REG_NOTES (undobuf.other_insn); note; note = next) | |
1701 | { | |
1702 | next = XEXP (note, 1); | |
1703 | ||
1704 | if (REG_NOTE_KIND (note) == REG_UNUSED | |
1705 | && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn))) | |
1706 | remove_note (undobuf.other_insn, note); | |
1707 | } | |
1708 | ||
1709 | distribute_notes (new_other_notes, undobuf.other_insn, | |
1710 | undobuf.other_insn, 0, 0, 0); | |
1711 | } | |
1712 | ||
1713 | /* We now know that we can do this combination. Merge the insns and | |
1714 | update the status of registers and LOG_LINKS. */ | |
1715 | ||
1716 | { | |
1717 | rtx i3notes, i2notes, i1notes = 0; | |
1718 | rtx i3links, i2links, i1links = 0; | |
1719 | rtx midnotes = 0; | |
1720 | int all_adjacent = (next_real_insn (i2) == i3 | |
1721 | && (i1 == 0 || next_real_insn (i1) == i2)); | |
1722 | register int regno; | |
1723 | /* Compute which registers we expect to eliminate. */ | |
1724 | rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src | |
1725 | ? 0 : i2dest); | |
1726 | rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest; | |
1727 | ||
1728 | /* Get the old REG_NOTES and LOG_LINKS from all our insns and | |
1729 | clear them. */ | |
1730 | i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3); | |
1731 | i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2); | |
1732 | if (i1) | |
1733 | i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1); | |
1734 | ||
1735 | /* Ensure that we do not have something that should not be shared but | |
1736 | occurs multiple times in the new insns. Check this by first | |
5089e22e | 1737 | resetting all the `used' flags and then copying anything is shared. */ |
230d793d RS |
1738 | |
1739 | reset_used_flags (i3notes); | |
1740 | reset_used_flags (i2notes); | |
1741 | reset_used_flags (i1notes); | |
1742 | reset_used_flags (newpat); | |
1743 | reset_used_flags (newi2pat); | |
1744 | if (undobuf.other_insn) | |
1745 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
1746 | ||
1747 | i3notes = copy_rtx_if_shared (i3notes); | |
1748 | i2notes = copy_rtx_if_shared (i2notes); | |
1749 | i1notes = copy_rtx_if_shared (i1notes); | |
1750 | newpat = copy_rtx_if_shared (newpat); | |
1751 | newi2pat = copy_rtx_if_shared (newi2pat); | |
1752 | if (undobuf.other_insn) | |
1753 | reset_used_flags (PATTERN (undobuf.other_insn)); | |
1754 | ||
1755 | INSN_CODE (i3) = insn_code_number; | |
1756 | PATTERN (i3) = newpat; | |
1757 | if (undobuf.other_insn) | |
1758 | INSN_CODE (undobuf.other_insn) = other_code_number; | |
1759 | ||
1760 | /* We had one special case above where I2 had more than one set and | |
1761 | we replaced a destination of one of those sets with the destination | |
1762 | of I3. In that case, we have to update LOG_LINKS of insns later | |
1763 | in this basic block. Note that this (expensive) case is rare. */ | |
1764 | ||
1765 | if (GET_CODE (PATTERN (i2)) == PARALLEL) | |
1766 | for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++) | |
1767 | if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG | |
1768 | && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest | |
1769 | && ! find_reg_note (i2, REG_UNUSED, | |
1770 | SET_DEST (XVECEXP (PATTERN (i2), 0, i)))) | |
1771 | { | |
1772 | register rtx insn; | |
1773 | ||
1774 | for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn)) | |
1775 | { | |
1776 | if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i') | |
1777 | for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) | |
1778 | if (XEXP (link, 0) == i2) | |
1779 | XEXP (link, 0) = i3; | |
1780 | ||
1781 | if (GET_CODE (insn) == CODE_LABEL | |
1782 | || GET_CODE (insn) == JUMP_INSN) | |
1783 | break; | |
1784 | } | |
1785 | } | |
1786 | ||
1787 | LOG_LINKS (i3) = 0; | |
1788 | REG_NOTES (i3) = 0; | |
1789 | LOG_LINKS (i2) = 0; | |
1790 | REG_NOTES (i2) = 0; | |
1791 | ||
1792 | if (newi2pat) | |
1793 | { | |
1794 | INSN_CODE (i2) = i2_code_number; | |
1795 | PATTERN (i2) = newi2pat; | |
1796 | } | |
1797 | else | |
1798 | { | |
1799 | PUT_CODE (i2, NOTE); | |
1800 | NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; | |
1801 | NOTE_SOURCE_FILE (i2) = 0; | |
1802 | } | |
1803 | ||
1804 | if (i1) | |
1805 | { | |
1806 | LOG_LINKS (i1) = 0; | |
1807 | REG_NOTES (i1) = 0; | |
1808 | PUT_CODE (i1, NOTE); | |
1809 | NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED; | |
1810 | NOTE_SOURCE_FILE (i1) = 0; | |
1811 | } | |
1812 | ||
1813 | /* Get death notes for everything that is now used in either I3 or | |
1814 | I2 and used to die in a previous insn. */ | |
1815 | ||
1816 | move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes); | |
1817 | if (newi2pat) | |
1818 | move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes); | |
1819 | ||
1820 | /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */ | |
1821 | if (i3notes) | |
1822 | distribute_notes (i3notes, i3, i3, newi2pat ? i2 : 0, elim_i2, elim_i1); | |
1823 | if (i2notes) | |
1824 | distribute_notes (i2notes, i2, i3, newi2pat ? i2 : 0, elim_i2, elim_i1); | |
1825 | if (i1notes) | |
1826 | distribute_notes (i1notes, i1, i3, newi2pat ? i2 : 0, elim_i2, elim_i1); | |
1827 | if (midnotes) | |
1828 | distribute_notes (midnotes, 0, i3, newi2pat ? i2 : 0, elim_i2, elim_i1); | |
1829 | ||
1830 | /* Distribute any notes added to I2 or I3 by recog_for_combine. We | |
1831 | know these are REG_UNUSED and want them to go to the desired insn, | |
1832 | so we always pass it as i3. */ | |
1833 | if (newi2pat && new_i2_notes) | |
1834 | distribute_notes (new_i2_notes, i2, i2, 0, 0, 0); | |
1835 | if (new_i3_notes) | |
1836 | distribute_notes (new_i3_notes, i3, i3, 0, 0, 0); | |
1837 | ||
1838 | /* If I3DEST was used in I3SRC, it really died in I3. We may need to | |
1839 | put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */ | |
1840 | if (i3dest_killed) | |
1841 | distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 0), | |
1842 | 0, i3, newi2pat ? i2 : 0, 0, 0); | |
1843 | if (i2dest_in_i2src) | |
1844 | distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, 0), | |
1845 | 0, i3, newi2pat ? i2 : 0, 0, 0); | |
1846 | if (i1dest_in_i1src) | |
1847 | distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, 0), | |
1848 | 0, i3, newi2pat ? i2 : 0, 0, 0); | |
1849 | ||
1850 | distribute_links (i3links); | |
1851 | distribute_links (i2links); | |
1852 | distribute_links (i1links); | |
1853 | ||
1854 | if (GET_CODE (i2dest) == REG) | |
1855 | { | |
1856 | /* The insn that previously set this register doesn't exist, and | |
1857 | this life of the register may not exist either. Show that | |
1858 | we don't know its value any more. If we don't do this and | |
1859 | I2 set the register to a value that depended on its old | |
1860 | contents, we will get confused. If this insn is used, thing | |
1861 | will be set correctly in combine_instructions. */ | |
1862 | record_value_for_reg (i2dest, 0, 0); | |
1863 | ||
1864 | /* If the reg formerly set in I2 died only once and that was in I3, | |
1865 | zero its use count so it won't make `reload' do any work. */ | |
1866 | if (! added_sets_2 && newi2pat == 0) | |
1867 | { | |
1868 | regno = REGNO (i2dest); | |
1869 | reg_n_sets[regno]--; | |
1870 | if (reg_n_sets[regno] == 0 | |
1871 | && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT] | |
1872 | & (1 << (regno % HOST_BITS_PER_INT)))) | |
1873 | reg_n_refs[regno] = 0; | |
1874 | } | |
1875 | } | |
1876 | ||
1877 | if (i1 && GET_CODE (i1dest) == REG) | |
1878 | { | |
1879 | record_value_for_reg (i1dest, 0, 0); | |
1880 | regno = REGNO (i1dest); | |
1881 | if (! added_sets_1) | |
1882 | { | |
1883 | reg_n_sets[regno]--; | |
1884 | if (reg_n_sets[regno] == 0 | |
1885 | && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT] | |
1886 | & (1 << (regno % HOST_BITS_PER_INT)))) | |
1887 | reg_n_refs[regno] = 0; | |
1888 | } | |
1889 | } | |
1890 | ||
1891 | /* If I3 is now an unconditional jump, ensure that it has a | |
1892 | BARRIER following it since it may have initially been a | |
1893 | conditional jump. */ | |
1894 | ||
1895 | if ((GET_CODE (newpat) == RETURN || simplejump_p (i3)) | |
1896 | && GET_CODE (next_nonnote_insn (i3)) != BARRIER) | |
1897 | emit_barrier_after (i3); | |
1898 | } | |
1899 | ||
1900 | combine_successes++; | |
1901 | ||
1902 | return newi2pat ? i2 : i3; | |
1903 | } | |
1904 | \f | |
1905 | /* Undo all the modifications recorded in undobuf. */ | |
1906 | ||
1907 | static void | |
1908 | undo_all () | |
1909 | { | |
1910 | register int i; | |
1911 | if (undobuf.num_undo > MAX_UNDO) | |
1912 | undobuf.num_undo = MAX_UNDO; | |
1913 | for (i = undobuf.num_undo - 1; i >= 0; i--) | |
1914 | *undobuf.undo[i].where = undobuf.undo[i].old_contents; | |
1915 | ||
1916 | obfree (undobuf.storage); | |
1917 | undobuf.num_undo = 0; | |
1918 | } | |
1919 | \f | |
1920 | /* Find the innermost point within the rtx at LOC, possibly LOC itself, | |
1921 | where we have an arithmetic expression and return that point. | |
1922 | ||
1923 | try_combine will call this function to see if an insn can be split into | |
1924 | two insns. */ | |
1925 | ||
1926 | static rtx * | |
1927 | find_split_point (loc) | |
1928 | rtx *loc; | |
1929 | { | |
1930 | rtx x = *loc; | |
1931 | enum rtx_code code = GET_CODE (x); | |
1932 | rtx *split; | |
1933 | int len = 0, pos, unsignedp; | |
1934 | rtx inner; | |
1935 | ||
1936 | /* First special-case some codes. */ | |
1937 | switch (code) | |
1938 | { | |
1939 | case SUBREG: | |
1940 | #ifdef INSN_SCHEDULING | |
1941 | /* If we are making a paradoxical SUBREG invalid, it becomes a split | |
1942 | point. */ | |
1943 | if (GET_CODE (SUBREG_REG (x)) == MEM) | |
1944 | return loc; | |
1945 | #endif | |
1946 | return find_split_point (&SUBREG_REG (x)); | |
1947 | ||
230d793d | 1948 | case MEM: |
916f14f1 | 1949 | #ifdef HAVE_lo_sum |
230d793d RS |
1950 | /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it |
1951 | using LO_SUM and HIGH. */ | |
1952 | if (GET_CODE (XEXP (x, 0)) == CONST | |
1953 | || GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1954 | { | |
1955 | SUBST (XEXP (x, 0), | |
1956 | gen_rtx_combine (LO_SUM, Pmode, | |
1957 | gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)), | |
1958 | XEXP (x, 0))); | |
1959 | return &XEXP (XEXP (x, 0), 0); | |
1960 | } | |
230d793d RS |
1961 | #endif |
1962 | ||
916f14f1 RK |
1963 | /* If we have a PLUS whose second operand is a constant and the |
1964 | address is not valid, perhaps will can split it up using | |
1965 | the machine-specific way to split large constants. We use | |
1966 | the first psuedo-reg (one of the virtual regs) as a placeholder; | |
1967 | it will not remain in the result. */ | |
1968 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
1969 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1970 | && ! memory_address_p (GET_MODE (x), XEXP (x, 0))) | |
1971 | { | |
1972 | rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER]; | |
1973 | rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)), | |
1974 | subst_insn); | |
1975 | ||
1976 | /* This should have produced two insns, each of which sets our | |
1977 | placeholder. If the source of the second is a valid address, | |
1978 | we can make put both sources together and make a split point | |
1979 | in the middle. */ | |
1980 | ||
1981 | if (seq && XVECLEN (seq, 0) == 2 | |
1982 | && GET_CODE (XVECEXP (seq, 0, 0)) == INSN | |
1983 | && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET | |
1984 | && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg | |
1985 | && ! reg_mentioned_p (reg, | |
1986 | SET_SRC (PATTERN (XVECEXP (seq, 0, 0)))) | |
1987 | && GET_CODE (XVECEXP (seq, 0, 1)) == INSN | |
1988 | && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET | |
1989 | && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg | |
1990 | && memory_address_p (GET_MODE (x), | |
1991 | SET_SRC (PATTERN (XVECEXP (seq, 0, 1))))) | |
1992 | { | |
1993 | rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0))); | |
1994 | rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1))); | |
1995 | ||
1996 | /* Replace the placeholder in SRC2 with SRC1. If we can | |
1997 | find where in SRC2 it was placed, that can become our | |
1998 | split point and we can replace this address with SRC2. | |
1999 | Just try two obvious places. */ | |
2000 | ||
2001 | src2 = replace_rtx (src2, reg, src1); | |
2002 | split = 0; | |
2003 | if (XEXP (src2, 0) == src1) | |
2004 | split = &XEXP (src2, 0); | |
2005 | else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e' | |
2006 | && XEXP (XEXP (src2, 0), 0) == src1) | |
2007 | split = &XEXP (XEXP (src2, 0), 0); | |
2008 | ||
2009 | if (split) | |
2010 | { | |
2011 | SUBST (XEXP (x, 0), src2); | |
2012 | return split; | |
2013 | } | |
2014 | } | |
2015 | } | |
2016 | break; | |
2017 | ||
230d793d RS |
2018 | case SET: |
2019 | #ifdef HAVE_cc0 | |
2020 | /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a | |
2021 | ZERO_EXTRACT, the most likely reason why this doesn't match is that | |
2022 | we need to put the operand into a register. So split at that | |
2023 | point. */ | |
2024 | ||
2025 | if (SET_DEST (x) == cc0_rtx | |
2026 | && GET_CODE (SET_SRC (x)) != COMPARE | |
2027 | && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT | |
2028 | && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o' | |
2029 | && ! (GET_CODE (SET_SRC (x)) == SUBREG | |
2030 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o')) | |
2031 | return &SET_SRC (x); | |
2032 | #endif | |
2033 | ||
2034 | /* See if we can split SET_SRC as it stands. */ | |
2035 | split = find_split_point (&SET_SRC (x)); | |
2036 | if (split && split != &SET_SRC (x)) | |
2037 | return split; | |
2038 | ||
2039 | /* See if this is a bitfield assignment with everything constant. If | |
2040 | so, this is an IOR of an AND, so split it into that. */ | |
2041 | if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
2042 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))) | |
2043 | <= HOST_BITS_PER_INT) | |
2044 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT | |
2045 | && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT | |
2046 | && GET_CODE (SET_SRC (x)) == CONST_INT | |
2047 | && ((INTVAL (XEXP (SET_DEST (x), 1)) | |
2048 | + INTVAL (XEXP (SET_DEST (x), 2))) | |
2049 | <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))) | |
2050 | && ! side_effects_p (XEXP (SET_DEST (x), 0))) | |
2051 | { | |
2052 | int pos = INTVAL (XEXP (SET_DEST (x), 2)); | |
2053 | int len = INTVAL (XEXP (SET_DEST (x), 1)); | |
2054 | int src = INTVAL (SET_SRC (x)); | |
2055 | rtx dest = XEXP (SET_DEST (x), 0); | |
2056 | enum machine_mode mode = GET_MODE (dest); | |
2057 | unsigned int mask = (1 << len) - 1; | |
2058 | ||
2059 | #if BITS_BIG_ENDIAN | |
2060 | pos = GET_MODE_BITSIZE (mode) - len - pos; | |
2061 | #endif | |
2062 | ||
2063 | if (src == mask) | |
2064 | SUBST (SET_SRC (x), | |
2065 | gen_binary (IOR, mode, dest, | |
2066 | gen_rtx (CONST_INT, VOIDmode, src << pos))); | |
2067 | else | |
2068 | SUBST (SET_SRC (x), | |
2069 | gen_binary (IOR, mode, | |
2070 | gen_binary (AND, mode, dest, | |
2071 | gen_rtx (CONST_INT, VOIDmode, | |
2072 | (~ (mask << pos) | |
2073 | & GET_MODE_MASK (mode)))), | |
2074 | gen_rtx (CONST_INT, VOIDmode, src << pos))); | |
2075 | ||
2076 | SUBST (SET_DEST (x), dest); | |
2077 | ||
2078 | split = find_split_point (&SET_SRC (x)); | |
2079 | if (split && split != &SET_SRC (x)) | |
2080 | return split; | |
2081 | } | |
2082 | ||
2083 | /* Otherwise, see if this is an operation that we can split into two. | |
2084 | If so, try to split that. */ | |
2085 | code = GET_CODE (SET_SRC (x)); | |
2086 | ||
2087 | switch (code) | |
2088 | { | |
2089 | case SIGN_EXTEND: | |
2090 | inner = XEXP (SET_SRC (x), 0); | |
2091 | pos = 0; | |
2092 | len = GET_MODE_BITSIZE (GET_MODE (inner)); | |
2093 | unsignedp = 0; | |
2094 | break; | |
2095 | ||
2096 | case SIGN_EXTRACT: | |
2097 | case ZERO_EXTRACT: | |
2098 | if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT | |
2099 | && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT) | |
2100 | { | |
2101 | inner = XEXP (SET_SRC (x), 0); | |
2102 | len = INTVAL (XEXP (SET_SRC (x), 1)); | |
2103 | pos = INTVAL (XEXP (SET_SRC (x), 2)); | |
2104 | ||
2105 | #if BITS_BIG_ENDIAN | |
2106 | pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos; | |
2107 | #endif | |
2108 | unsignedp = (code == ZERO_EXTRACT); | |
2109 | } | |
2110 | break; | |
2111 | } | |
2112 | ||
2113 | if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner))) | |
2114 | { | |
2115 | enum machine_mode mode = GET_MODE (SET_SRC (x)); | |
2116 | ||
2117 | if (unsignedp && len < HOST_BITS_PER_INT) | |
2118 | { | |
2119 | SUBST (SET_SRC (x), | |
2120 | gen_rtx_combine | |
2121 | (AND, mode, | |
2122 | gen_rtx_combine (LSHIFTRT, mode, | |
2123 | gen_lowpart_for_combine (mode, inner), | |
2124 | gen_rtx (CONST_INT, VOIDmode, pos)), | |
2125 | gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1))); | |
2126 | ||
2127 | split = find_split_point (&SET_SRC (x)); | |
2128 | if (split && split != &SET_SRC (x)) | |
2129 | return split; | |
2130 | } | |
2131 | else | |
2132 | { | |
2133 | SUBST (SET_SRC (x), | |
2134 | gen_rtx_combine | |
2135 | (ASHIFTRT, mode, | |
2136 | gen_rtx_combine (ASHIFT, mode, | |
2137 | gen_lowpart_for_combine (mode, inner), | |
2138 | gen_rtx (CONST_INT, VOIDmode, | |
2139 | (GET_MODE_BITSIZE (mode) | |
2140 | - len - pos))), | |
2141 | gen_rtx (CONST_INT, VOIDmode, | |
2142 | GET_MODE_BITSIZE (mode) - len))); | |
2143 | ||
2144 | split = find_split_point (&SET_SRC (x)); | |
2145 | if (split && split != &SET_SRC (x)) | |
2146 | return split; | |
2147 | } | |
2148 | } | |
2149 | ||
2150 | /* See if this is a simple operation with a constant as the second | |
2151 | operand. It might be that this constant is out of range and hence | |
2152 | could be used as a split point. */ | |
2153 | if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' | |
2154 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' | |
2155 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<') | |
2156 | && CONSTANT_P (XEXP (SET_SRC (x), 1)) | |
2157 | && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o' | |
2158 | || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG | |
2159 | && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0)))) | |
2160 | == 'o')))) | |
2161 | return &XEXP (SET_SRC (x), 1); | |
2162 | ||
2163 | /* Finally, see if this is a simple operation with its first operand | |
2164 | not in a register. The operation might require this operand in a | |
2165 | register, so return it as a split point. We can always do this | |
2166 | because if the first operand were another operation, we would have | |
2167 | already found it as a split point. */ | |
2168 | if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2' | |
2169 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c' | |
2170 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<' | |
2171 | || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1') | |
2172 | && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode)) | |
2173 | return &XEXP (SET_SRC (x), 0); | |
2174 | ||
2175 | return 0; | |
2176 | ||
2177 | case AND: | |
2178 | case IOR: | |
2179 | /* We write NOR as (and (not A) (not B)), but if we don't have a NOR, | |
2180 | it is better to write this as (not (ior A B)) so we can split it. | |
2181 | Similarly for IOR. */ | |
2182 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT) | |
2183 | { | |
2184 | SUBST (*loc, | |
2185 | gen_rtx_combine (NOT, GET_MODE (x), | |
2186 | gen_rtx_combine (code == IOR ? AND : IOR, | |
2187 | GET_MODE (x), | |
2188 | XEXP (XEXP (x, 0), 0), | |
2189 | XEXP (XEXP (x, 1), 0)))); | |
2190 | return find_split_point (loc); | |
2191 | } | |
2192 | ||
2193 | /* Many RISC machines have a large set of logical insns. If the | |
2194 | second operand is a NOT, put it first so we will try to split the | |
2195 | other operand first. */ | |
2196 | if (GET_CODE (XEXP (x, 1)) == NOT) | |
2197 | { | |
2198 | rtx tem = XEXP (x, 0); | |
2199 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
2200 | SUBST (XEXP (x, 1), tem); | |
2201 | } | |
2202 | break; | |
2203 | } | |
2204 | ||
2205 | /* Otherwise, select our actions depending on our rtx class. */ | |
2206 | switch (GET_RTX_CLASS (code)) | |
2207 | { | |
2208 | case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */ | |
2209 | case '3': | |
2210 | split = find_split_point (&XEXP (x, 2)); | |
2211 | if (split) | |
2212 | return split; | |
2213 | /* ... fall through ... */ | |
2214 | case '2': | |
2215 | case 'c': | |
2216 | case '<': | |
2217 | split = find_split_point (&XEXP (x, 1)); | |
2218 | if (split) | |
2219 | return split; | |
2220 | /* ... fall through ... */ | |
2221 | case '1': | |
2222 | /* Some machines have (and (shift ...) ...) insns. If X is not | |
2223 | an AND, but XEXP (X, 0) is, use it as our split point. */ | |
2224 | if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND) | |
2225 | return &XEXP (x, 0); | |
2226 | ||
2227 | split = find_split_point (&XEXP (x, 0)); | |
2228 | if (split) | |
2229 | return split; | |
2230 | return loc; | |
2231 | } | |
2232 | ||
2233 | /* Otherwise, we don't have a split point. */ | |
2234 | return 0; | |
2235 | } | |
2236 | \f | |
2237 | /* Throughout X, replace FROM with TO, and return the result. | |
2238 | The result is TO if X is FROM; | |
2239 | otherwise the result is X, but its contents may have been modified. | |
2240 | If they were modified, a record was made in undobuf so that | |
2241 | undo_all will (among other things) return X to its original state. | |
2242 | ||
2243 | If the number of changes necessary is too much to record to undo, | |
2244 | the excess changes are not made, so the result is invalid. | |
2245 | The changes already made can still be undone. | |
2246 | undobuf.num_undo is incremented for such changes, so by testing that | |
2247 | the caller can tell whether the result is valid. | |
2248 | ||
2249 | `n_occurrences' is incremented each time FROM is replaced. | |
2250 | ||
2251 | IN_DEST is non-zero if we are processing the SET_DEST of a SET. | |
2252 | ||
5089e22e | 2253 | UNIQUE_COPY is non-zero if each substitution must be unique. We do this |
230d793d RS |
2254 | by copying if `n_occurrences' is non-zero. */ |
2255 | ||
2256 | static rtx | |
2257 | subst (x, from, to, in_dest, unique_copy) | |
2258 | register rtx x, from, to; | |
2259 | int in_dest; | |
2260 | int unique_copy; | |
2261 | { | |
2262 | register char *fmt; | |
2263 | register int len, i; | |
2264 | register enum rtx_code code = GET_CODE (x), orig_code = code; | |
2265 | rtx temp; | |
2266 | enum machine_mode mode = GET_MODE (x); | |
2267 | enum machine_mode op0_mode = VOIDmode; | |
2268 | rtx other_insn; | |
2269 | rtx *cc_use; | |
2270 | int n_restarts = 0; | |
2271 | ||
2272 | /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe | |
2273 | replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM). | |
2274 | If it is 0, that cannot be done. We can now do this for any MEM | |
2275 | because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded. | |
2276 | If not for that, MEM's would very rarely be safe. */ | |
2277 | ||
2278 | /* Reject MODEs bigger than a word, because we might not be able | |
2279 | to reference a two-register group starting with an arbitrary register | |
2280 | (and currently gen_lowpart might crash for a SUBREG). */ | |
2281 | ||
2282 | #define FAKE_EXTEND_SAFE_P(MODE, FROM) \ | |
2283 | (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) | |
2284 | ||
2285 | /* Two expressions are equal if they are identical copies of a shared | |
2286 | RTX or if they are both registers with the same register number | |
2287 | and mode. */ | |
2288 | ||
2289 | #define COMBINE_RTX_EQUAL_P(X,Y) \ | |
2290 | ((X) == (Y) \ | |
2291 | || (GET_CODE (X) == REG && GET_CODE (Y) == REG \ | |
2292 | && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y))) | |
2293 | ||
2294 | if (! in_dest && COMBINE_RTX_EQUAL_P (x, from)) | |
2295 | { | |
2296 | n_occurrences++; | |
2297 | return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to); | |
2298 | } | |
2299 | ||
2300 | /* If X and FROM are the same register but different modes, they will | |
2301 | not have been seen as equal above. However, flow.c will make a | |
2302 | LOG_LINKS entry for that case. If we do nothing, we will try to | |
2303 | rerecognize our original insn and, when it succeeds, we will | |
2304 | delete the feeding insn, which is incorrect. | |
2305 | ||
2306 | So force this insn not to match in this (rare) case. */ | |
2307 | if (! in_dest && code == REG && GET_CODE (from) == REG | |
2308 | && REGNO (x) == REGNO (from)) | |
2309 | return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); | |
2310 | ||
2311 | /* If this is an object, we are done unless it is a MEM or LO_SUM, both | |
2312 | of which may contain things that can be combined. */ | |
2313 | if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o') | |
2314 | return x; | |
2315 | ||
2316 | /* It is possible to have a subexpression appear twice in the insn. | |
2317 | Suppose that FROM is a register that appears within TO. | |
2318 | Then, after that subexpression has been scanned once by `subst', | |
2319 | the second time it is scanned, TO may be found. If we were | |
2320 | to scan TO here, we would find FROM within it and create a | |
2321 | self-referent rtl structure which is completely wrong. */ | |
2322 | if (COMBINE_RTX_EQUAL_P (x, to)) | |
2323 | return to; | |
2324 | ||
2325 | len = GET_RTX_LENGTH (code); | |
2326 | fmt = GET_RTX_FORMAT (code); | |
2327 | ||
2328 | /* We don't need to process a SET_DEST that is a register, CC0, or PC, so | |
2329 | set up to skip this common case. All other cases where we want to | |
2330 | suppress replacing something inside a SET_SRC are handled via the | |
2331 | IN_DEST operand. */ | |
2332 | if (code == SET | |
2333 | && (GET_CODE (SET_DEST (x)) == REG | |
2334 | || GET_CODE (SET_DEST (x)) == CC0 | |
2335 | || GET_CODE (SET_DEST (x)) == PC)) | |
2336 | fmt = "ie"; | |
2337 | ||
2338 | /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */ | |
2339 | if (fmt[0] == 'e') | |
2340 | op0_mode = GET_MODE (XEXP (x, 0)); | |
2341 | ||
2342 | for (i = 0; i < len; i++) | |
2343 | { | |
2344 | if (fmt[i] == 'E') | |
2345 | { | |
2346 | register int j; | |
2347 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2348 | { | |
2349 | register rtx new; | |
2350 | if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from)) | |
2351 | { | |
2352 | new = (unique_copy && n_occurrences ? copy_rtx (to) : to); | |
2353 | n_occurrences++; | |
2354 | } | |
2355 | else | |
2356 | { | |
2357 | new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy); | |
2358 | ||
2359 | /* If this substitution failed, this whole thing fails. */ | |
2360 | if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) | |
2361 | return new; | |
2362 | } | |
2363 | ||
2364 | SUBST (XVECEXP (x, i, j), new); | |
2365 | } | |
2366 | } | |
2367 | else if (fmt[i] == 'e') | |
2368 | { | |
2369 | register rtx new; | |
2370 | ||
2371 | if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from)) | |
2372 | { | |
2373 | new = (unique_copy && n_occurrences ? copy_rtx (to) : to); | |
2374 | n_occurrences++; | |
2375 | } | |
2376 | else | |
2377 | /* If we are in a SET_DEST, suppress most cases unless we | |
2378 | have gone inside a MEM, in which case we want to | |
2379 | simplify the address. We assume here that things that | |
2380 | are actually part of the destination have their inner | |
2381 | parts in the first expression. This is true for SUBREG, | |
2382 | STRICT_LOW_PART, and ZERO_EXTRACT, which are the only | |
2383 | things aside from REG and MEM that should appear in a | |
2384 | SET_DEST. */ | |
2385 | new = subst (XEXP (x, i), from, to, | |
2386 | (((in_dest | |
2387 | && (code == SUBREG || code == STRICT_LOW_PART | |
2388 | || code == ZERO_EXTRACT)) | |
2389 | || code == SET) | |
2390 | && i == 0), unique_copy); | |
2391 | ||
2392 | /* If we found that we will have to reject this combination, | |
2393 | indicate that by returning the CLOBBER ourselves, rather than | |
2394 | an expression containing it. This will speed things up as | |
2395 | well as prevent accidents where two CLOBBERs are considered | |
2396 | to be equal, thus producing an incorrect simplification. */ | |
2397 | ||
2398 | if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx) | |
2399 | return new; | |
2400 | ||
2401 | SUBST (XEXP (x, i), new); | |
2402 | } | |
2403 | } | |
2404 | ||
2405 | /* If this is a commutative operation, put a constant last and a complex | |
2406 | expression first. We don't need to do this for comparisons here. */ | |
2407 | if (GET_RTX_CLASS (code) == 'c' | |
2408 | && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT) | |
2409 | || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o' | |
2410 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o') | |
2411 | || (GET_CODE (XEXP (x, 0)) == SUBREG | |
2412 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o' | |
2413 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'))) | |
2414 | { | |
2415 | temp = XEXP (x, 0); | |
2416 | SUBST (XEXP (x, 0), XEXP (x, 1)); | |
2417 | SUBST (XEXP (x, 1), temp); | |
2418 | } | |
2419 | ||
2420 | /* Try to fold this expression in case we have constants that weren't | |
2421 | present before. */ | |
2422 | temp = 0; | |
2423 | switch (GET_RTX_CLASS (code)) | |
2424 | { | |
2425 | case '1': | |
2426 | temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode); | |
2427 | break; | |
2428 | case '<': | |
2429 | temp = simplify_relational_operation (code, op0_mode, | |
2430 | XEXP (x, 0), XEXP (x, 1)); | |
2431 | break; | |
2432 | case 'c': | |
2433 | case '2': | |
2434 | temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1)); | |
2435 | break; | |
2436 | case 'b': | |
2437 | case '3': | |
2438 | temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0), | |
2439 | XEXP (x, 1), XEXP (x, 2)); | |
2440 | break; | |
2441 | } | |
2442 | ||
2443 | if (temp) | |
2444 | x = temp; | |
2445 | ||
2446 | /* We come back to here if we have replaced the expression with one of | |
2447 | a different code and it is likely that further simplification will be | |
2448 | possible. */ | |
2449 | ||
2450 | restart: | |
2451 | ||
2452 | /* If we have restarted more than 4 times, we are probably looping, so | |
2453 | give up. */ | |
2454 | if (++n_restarts > 4) | |
2455 | return x; | |
2456 | ||
2457 | code = GET_CODE (x); | |
2458 | ||
2459 | /* First see if we can apply the inverse distributive law. */ | |
2460 | if (code == PLUS || code == MINUS || code == IOR || code == XOR) | |
2461 | { | |
2462 | x = apply_distributive_law (x); | |
2463 | code = GET_CODE (x); | |
2464 | } | |
2465 | ||
2466 | /* If CODE is an associative operation not otherwise handled, see if we | |
2467 | can associate some operands. This can win if they are constants or | |
2468 | if they are logically related (i.e. (a & b) & a. */ | |
2469 | if ((code == PLUS || code == MINUS | |
2470 | || code == MULT || code == AND || code == IOR || code == XOR | |
2471 | || code == DIV || code == UDIV | |
2472 | || code == SMAX || code == SMIN || code == UMAX || code == UMIN) | |
2473 | && GET_MODE_CLASS (mode) == MODE_INT) | |
2474 | { | |
2475 | if (GET_CODE (XEXP (x, 0)) == code) | |
2476 | { | |
2477 | rtx other = XEXP (XEXP (x, 0), 0); | |
2478 | rtx inner_op0 = XEXP (XEXP (x, 0), 1); | |
2479 | rtx inner_op1 = XEXP (x, 1); | |
2480 | rtx inner; | |
2481 | ||
2482 | /* Make sure we pass the constant operand if any as the second | |
2483 | one if this is a commutative operation. */ | |
2484 | if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c') | |
2485 | { | |
2486 | rtx tem = inner_op0; | |
2487 | inner_op0 = inner_op1; | |
2488 | inner_op1 = tem; | |
2489 | } | |
2490 | inner = simplify_binary_operation (code == MINUS ? PLUS | |
2491 | : code == DIV ? MULT | |
2492 | : code == UDIV ? MULT | |
2493 | : code, | |
2494 | mode, inner_op0, inner_op1); | |
2495 | ||
2496 | /* For commutative operations, try the other pair if that one | |
2497 | didn't simplify. */ | |
2498 | if (inner == 0 && GET_RTX_CLASS (code) == 'c') | |
2499 | { | |
2500 | other = XEXP (XEXP (x, 0), 1); | |
2501 | inner = simplify_binary_operation (code, mode, | |
2502 | XEXP (XEXP (x, 0), 0), | |
2503 | XEXP (x, 1)); | |
2504 | } | |
2505 | ||
2506 | if (inner) | |
2507 | { | |
2508 | x = gen_binary (code, mode, other, inner); | |
2509 | goto restart; | |
2510 | ||
2511 | } | |
2512 | } | |
2513 | } | |
2514 | ||
2515 | /* A little bit of algebraic simplification here. */ | |
2516 | switch (code) | |
2517 | { | |
2518 | case MEM: | |
2519 | /* Ensure that our address has any ASHIFTs converted to MULT in case | |
2520 | address-recognizing predicates are called later. */ | |
2521 | temp = make_compound_operation (XEXP (x, 0), MEM); | |
2522 | SUBST (XEXP (x, 0), temp); | |
2523 | break; | |
2524 | ||
2525 | case SUBREG: | |
2526 | /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG | |
2527 | is paradoxical. If we can't do that safely, then it becomes | |
2528 | something nonsensical so that this combination won't take place. */ | |
2529 | ||
2530 | if (GET_CODE (SUBREG_REG (x)) == MEM | |
2531 | && (GET_MODE_SIZE (mode) | |
2532 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))) | |
2533 | { | |
2534 | rtx inner = SUBREG_REG (x); | |
2535 | int endian_offset = 0; | |
2536 | /* Don't change the mode of the MEM | |
2537 | if that would change the meaning of the address. */ | |
2538 | if (MEM_VOLATILE_P (SUBREG_REG (x)) | |
2539 | || mode_dependent_address_p (XEXP (inner, 0))) | |
2540 | return gen_rtx (CLOBBER, mode, const0_rtx); | |
2541 | ||
2542 | #if BYTES_BIG_ENDIAN | |
2543 | if (GET_MODE_SIZE (mode) < UNITS_PER_WORD) | |
2544 | endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode); | |
2545 | if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD) | |
2546 | endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner)); | |
2547 | #endif | |
2548 | /* Note if the plus_constant doesn't make a valid address | |
2549 | then this combination won't be accepted. */ | |
2550 | x = gen_rtx (MEM, mode, | |
2551 | plus_constant (XEXP (inner, 0), | |
2552 | (SUBREG_WORD (x) * UNITS_PER_WORD | |
2553 | + endian_offset))); | |
2554 | MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner); | |
2555 | RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner); | |
2556 | MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner); | |
2557 | return x; | |
2558 | } | |
2559 | ||
2560 | /* If we are in a SET_DEST, these other cases can't apply. */ | |
2561 | if (in_dest) | |
2562 | return x; | |
2563 | ||
2564 | /* Changing mode twice with SUBREG => just change it once, | |
2565 | or not at all if changing back to starting mode. */ | |
2566 | if (GET_CODE (SUBREG_REG (x)) == SUBREG) | |
2567 | { | |
2568 | if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x))) | |
2569 | && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0) | |
2570 | return SUBREG_REG (SUBREG_REG (x)); | |
2571 | ||
2572 | SUBST_INT (SUBREG_WORD (x), | |
2573 | SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x))); | |
2574 | SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x))); | |
2575 | } | |
2576 | ||
2577 | /* SUBREG of a hard register => just change the register number | |
2578 | and/or mode. If the hard register is not valid in that mode, | |
2579 | suppress this combination. */ | |
2580 | ||
2581 | if (GET_CODE (SUBREG_REG (x)) == REG | |
2582 | && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) | |
2583 | { | |
2584 | if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x), | |
2585 | mode)) | |
2586 | return gen_rtx (REG, mode, | |
2587 | REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)); | |
2588 | else | |
2589 | return gen_rtx (CLOBBER, mode, const0_rtx); | |
2590 | } | |
2591 | ||
2592 | /* For a constant, try to pick up the part we want. Handle a full | |
a4bde0b1 RK |
2593 | word and low-order part. Only do this if we are narrowing |
2594 | the constant; if it is being widened, we have no idea what | |
2595 | the extra bits will have been set to. */ | |
230d793d RS |
2596 | |
2597 | if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode | |
2598 | && GET_MODE_SIZE (mode) == UNITS_PER_WORD | |
a4bde0b1 | 2599 | && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD |
230d793d RS |
2600 | && GET_MODE_CLASS (mode) == MODE_INT) |
2601 | { | |
2602 | temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x), | |
2603 | 0, op0_mode); | |
2604 | if (temp) | |
2605 | return temp; | |
2606 | } | |
2607 | ||
a4bde0b1 RK |
2608 | if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x) |
2609 | && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode)) | |
230d793d RS |
2610 | return gen_lowpart_for_combine (mode, SUBREG_REG (x)); |
2611 | ||
2612 | /* If we are narrowing the object, we need to see if we can simplify | |
2613 | the expression for the object knowing that we only need the | |
2614 | low-order bits. We do this by computing an AND of the object | |
2615 | with only the bits we care about. That will produce any needed | |
2616 | simplifications. If the resulting computation is just the | |
2617 | AND with the significant bits, our operand is the first operand | |
2618 | of the AND. Otherwise, it is the resulting expression. */ | |
2619 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) | |
2620 | && subreg_lowpart_p (x) | |
2621 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT) | |
2622 | { | |
2623 | temp = simplify_and_const_int (0, GET_MODE (SUBREG_REG (x)), | |
2624 | SUBREG_REG (x), GET_MODE_MASK (mode)); | |
2625 | if (GET_CODE (temp) == AND && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
2626 | && INTVAL (XEXP (temp, 1)) == GET_MODE_MASK (mode)) | |
2627 | temp = XEXP (temp, 0); | |
2628 | return gen_lowpart_for_combine (mode, temp); | |
2629 | } | |
2630 | ||
2631 | break; | |
2632 | ||
2633 | case NOT: | |
2634 | /* (not (plus X -1)) can become (neg X). */ | |
2635 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2636 | && XEXP (XEXP (x, 0), 1) == constm1_rtx) | |
2637 | { | |
2638 | x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0)); | |
2639 | goto restart; | |
2640 | } | |
2641 | ||
2642 | /* Similarly, (not (neg X)) is (plus X -1). */ | |
2643 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
2644 | { | |
2645 | x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx); | |
2646 | goto restart; | |
2647 | } | |
2648 | ||
2649 | /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands | |
2650 | other than 1, but that is not valid. We could do a similar | |
2651 | simplification for (not (lshiftrt C X)) where C is just the sign bit, | |
2652 | but this doesn't seem common enough to bother with. */ | |
2653 | if (GET_CODE (XEXP (x, 0)) == ASHIFT | |
2654 | && XEXP (XEXP (x, 0), 0) == const1_rtx) | |
2655 | { | |
2656 | x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx), | |
2657 | XEXP (XEXP (x, 0), 1)); | |
2658 | goto restart; | |
2659 | } | |
2660 | ||
2661 | if (GET_CODE (XEXP (x, 0)) == SUBREG | |
2662 | && subreg_lowpart_p (XEXP (x, 0)) | |
2663 | && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) | |
2664 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0))))) | |
2665 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT | |
2666 | && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx) | |
2667 | { | |
2668 | enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0))); | |
2669 | ||
2670 | x = gen_rtx (ROTATE, inner_mode, | |
2671 | gen_unary (NOT, inner_mode, const1_rtx), | |
2672 | XEXP (SUBREG_REG (XEXP (x, 0)), 1)); | |
2673 | x = gen_lowpart_for_combine (mode, x); | |
2674 | goto restart; | |
2675 | } | |
2676 | ||
2677 | #if STORE_FLAG_VALUE == -1 | |
2678 | /* (not (comparison foo bar)) can be done by reversing the comparison | |
2679 | code if valid. */ | |
2680 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
2681 | && reversible_comparison_p (XEXP (x, 0))) | |
2682 | return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), | |
2683 | mode, XEXP (XEXP (x, 0), 0), | |
2684 | XEXP (XEXP (x, 0), 1)); | |
2685 | #endif | |
2686 | ||
2687 | /* Apply De Morgan's laws to reduce number of patterns for machines | |
2688 | with negating logical insns (and-not, nand, etc.). If result has | |
2689 | only one NOT, put it first, since that is how the patterns are | |
2690 | coded. */ | |
2691 | ||
2692 | if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND) | |
2693 | { | |
2694 | rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1); | |
2695 | ||
2696 | if (GET_CODE (in1) == NOT) | |
2697 | in1 = XEXP (in1, 0); | |
2698 | else | |
2699 | in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1); | |
2700 | ||
2701 | if (GET_CODE (in2) == NOT) | |
2702 | in2 = XEXP (in2, 0); | |
2703 | else if (GET_CODE (in2) == CONST_INT | |
2704 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT) | |
2705 | in2 = gen_rtx (CONST_INT, VOIDmode, | |
2706 | GET_MODE_MASK (mode) & ~ INTVAL (in2)); | |
2707 | else | |
2708 | in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2); | |
2709 | ||
2710 | if (GET_CODE (in2) == NOT) | |
2711 | { | |
2712 | rtx tem = in2; | |
2713 | in2 = in1; in1 = tem; | |
2714 | } | |
2715 | ||
2716 | x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR, | |
2717 | mode, in1, in2); | |
2718 | goto restart; | |
2719 | } | |
2720 | break; | |
2721 | ||
2722 | case NEG: | |
2723 | /* (neg (plus X 1)) can become (not X). */ | |
2724 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2725 | && XEXP (XEXP (x, 0), 1) == const1_rtx) | |
2726 | { | |
2727 | x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0)); | |
2728 | goto restart; | |
2729 | } | |
2730 | ||
2731 | /* Similarly, (neg (not X)) is (plus X 1). */ | |
2732 | if (GET_CODE (XEXP (x, 0)) == NOT) | |
2733 | { | |
2734 | x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx); | |
2735 | goto restart; | |
2736 | } | |
2737 | ||
2738 | /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */ | |
2739 | if (GET_CODE (XEXP (x, 0)) == ABS | |
2740 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTRACT | |
2741 | && XEXP (XEXP (XEXP (x, 0), 0), 1) == const1_rtx) | |
2742 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFTRT | |
2743 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
2744 | && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
2745 | == GET_MODE_BITSIZE (mode) - 1)) | |
2746 | || ((temp = get_last_value (XEXP (XEXP (x, 0), 0))) != 0 | |
2747 | && ((GET_CODE (temp) == SIGN_EXTRACT | |
2748 | && XEXP (temp, 1) == const1_rtx) | |
2749 | || (GET_CODE (temp) == ASHIFTRT | |
2750 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
2751 | && (INTVAL (XEXP (temp, 1)) | |
2752 | == GET_MODE_BITSIZE (mode) - 1)))))) | |
2753 | return XEXP (XEXP (x, 0), 0); | |
2754 | ||
2755 | /* (neg (minus X Y)) can become (minus Y X). */ | |
2756 | if (GET_CODE (XEXP (x, 0)) == MINUS | |
2757 | && (GET_MODE_CLASS (mode) != MODE_FLOAT | |
2758 | /* x-y != -(y-x) with IEEE floating point. */ | |
2759 | || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT)) | |
2760 | { | |
2761 | x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1), | |
2762 | XEXP (XEXP (x, 0), 0)); | |
2763 | goto restart; | |
2764 | } | |
2765 | ||
2766 | /* NEG commutes with ASHIFT since it is multiplication. Only do this | |
2767 | if we can then eliminate the NEG (e.g., | |
2768 | if the operand is a constant). */ | |
2769 | ||
2770 | if (GET_CODE (XEXP (x, 0)) == ASHIFT) | |
2771 | { | |
2772 | temp = simplify_unary_operation (NEG, mode, | |
2773 | XEXP (XEXP (x, 0), 0), mode); | |
2774 | if (temp) | |
2775 | { | |
2776 | SUBST (XEXP (XEXP (x, 0), 0), temp); | |
2777 | return XEXP (x, 0); | |
2778 | } | |
2779 | } | |
2780 | ||
2781 | temp = expand_compound_operation (XEXP (x, 0)); | |
2782 | ||
2783 | /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be | |
2784 | replaced by (lshiftrt X C). This will convert | |
2785 | (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */ | |
2786 | ||
2787 | if (GET_CODE (temp) == ASHIFTRT | |
2788 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
2789 | && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1) | |
2790 | { | |
2791 | x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0), | |
2792 | INTVAL (XEXP (temp, 1))); | |
2793 | goto restart; | |
2794 | } | |
2795 | ||
2796 | /* If X has only a single bit significant, say, bit I, convert | |
2797 | (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of | |
2798 | MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to | |
2799 | (sign_extract X 1 Y). But only do this if TEMP isn't a register | |
2800 | or a SUBREG of one since we'd be making the expression more | |
2801 | complex if it was just a register. */ | |
2802 | ||
2803 | if (GET_CODE (temp) != REG | |
2804 | && ! (GET_CODE (temp) == SUBREG | |
2805 | && GET_CODE (SUBREG_REG (temp)) == REG) | |
2806 | && (i = exact_log2 (significant_bits (temp, mode))) >= 0) | |
2807 | { | |
2808 | rtx temp1 = simplify_shift_const | |
2809 | (0, ASHIFTRT, mode, | |
2810 | simplify_shift_const (0, ASHIFT, mode, temp, | |
2811 | GET_MODE_BITSIZE (mode) - 1 - i), | |
2812 | GET_MODE_BITSIZE (mode) - 1 - i); | |
2813 | ||
2814 | /* If all we did was surround TEMP with the two shifts, we | |
2815 | haven't improved anything, so don't use it. Otherwise, | |
2816 | we are better off with TEMP1. */ | |
2817 | if (GET_CODE (temp1) != ASHIFTRT | |
2818 | || GET_CODE (XEXP (temp1, 0)) != ASHIFT | |
2819 | || XEXP (XEXP (temp1, 0), 0) != temp) | |
2820 | { | |
2821 | x = temp1; | |
2822 | goto restart; | |
2823 | } | |
2824 | } | |
2825 | break; | |
2826 | ||
2827 | case FLOAT_TRUNCATE: | |
2828 | /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */ | |
2829 | if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND | |
2830 | && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode) | |
2831 | return XEXP (XEXP (x, 0), 0); | |
2832 | break; | |
2833 | ||
2834 | #ifdef HAVE_cc0 | |
2835 | case COMPARE: | |
2836 | /* Convert (compare FOO (const_int 0)) to FOO unless we aren't | |
2837 | using cc0, in which case we want to leave it as a COMPARE | |
2838 | so we can distinguish it from a register-register-copy. */ | |
2839 | if (XEXP (x, 1) == const0_rtx) | |
2840 | return XEXP (x, 0); | |
2841 | ||
2842 | /* In IEEE floating point, x-0 is not the same as x. */ | |
2843 | if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT | |
2844 | || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT) | |
2845 | && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0)))) | |
2846 | return XEXP (x, 0); | |
2847 | break; | |
2848 | #endif | |
2849 | ||
2850 | case CONST: | |
2851 | /* (const (const X)) can become (const X). Do it this way rather than | |
2852 | returning the inner CONST since CONST can be shared with a | |
2853 | REG_EQUAL note. */ | |
2854 | if (GET_CODE (XEXP (x, 0)) == CONST) | |
2855 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
2856 | break; | |
2857 | ||
2858 | #ifdef HAVE_lo_sum | |
2859 | case LO_SUM: | |
2860 | /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we | |
2861 | can add in an offset. find_split_point will split this address up | |
2862 | again if it doesn't match. */ | |
2863 | if (GET_CODE (XEXP (x, 0)) == HIGH | |
2864 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))) | |
2865 | return XEXP (x, 1); | |
2866 | break; | |
2867 | #endif | |
2868 | ||
2869 | case PLUS: | |
2870 | /* If we have (plus (plus (A const) B)), associate it so that CONST is | |
2871 | outermost. That's because that's the way indexed addresses are | |
2872 | supposed to appear. This code used to check many more cases, but | |
2873 | they are now checked elsewhere. */ | |
2874 | if (GET_CODE (XEXP (x, 0)) == PLUS | |
2875 | && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1))) | |
2876 | return gen_binary (PLUS, mode, | |
2877 | gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), | |
2878 | XEXP (x, 1)), | |
2879 | XEXP (XEXP (x, 0), 1)); | |
2880 | ||
2881 | /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>) | |
2882 | when c is (const_int (pow2 + 1) / 2) is a sign extension of a | |
2883 | bit-field and can be replaced by either a sign_extend or a | |
2884 | sign_extract. The `and' may be a zero_extend. */ | |
2885 | if (GET_CODE (XEXP (x, 0)) == XOR | |
2886 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2887 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
2888 | && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1)) | |
2889 | && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0 | |
2890 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT | |
2891 | && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND | |
2892 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
2893 | && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) | |
2894 | == (1 << (i + 1)) - 1)) | |
2895 | || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND | |
2896 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0))) | |
2897 | == i + 1)))) | |
2898 | { | |
2899 | x = simplify_shift_const | |
2900 | (0, ASHIFTRT, mode, | |
2901 | simplify_shift_const (0, ASHIFT, mode, | |
2902 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
2903 | GET_MODE_BITSIZE (mode) - (i + 1)), | |
2904 | GET_MODE_BITSIZE (mode) - (i + 1)); | |
2905 | goto restart; | |
2906 | } | |
2907 | ||
2908 | /* If only the low-order bit of X is significant, (plus x -1) | |
2909 | can become (ashiftrt (ashift (xor x 1) C) C) where C is | |
2910 | the bitsize of the mode - 1. This allows simplification of | |
2911 | "a = (b & 8) == 0;" */ | |
2912 | if (XEXP (x, 1) == constm1_rtx | |
2913 | && GET_CODE (XEXP (x, 0)) != REG | |
2914 | && ! (GET_CODE (XEXP (x,0)) == SUBREG | |
2915 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG) | |
2916 | && significant_bits (XEXP (x, 0), mode) == 1) | |
2917 | { | |
2918 | x = simplify_shift_const | |
2919 | (0, ASHIFTRT, mode, | |
2920 | simplify_shift_const (0, ASHIFT, mode, | |
2921 | gen_rtx_combine (XOR, mode, | |
2922 | XEXP (x, 0), const1_rtx), | |
2923 | GET_MODE_BITSIZE (mode) - 1), | |
2924 | GET_MODE_BITSIZE (mode) - 1); | |
2925 | goto restart; | |
2926 | } | |
2927 | break; | |
2928 | ||
2929 | case MINUS: | |
2930 | /* (minus <foo> (and <foo> (const_int -pow2))) becomes | |
2931 | (and <foo> (const_int pow2-1)) */ | |
2932 | if (GET_CODE (XEXP (x, 1)) == AND | |
2933 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
2934 | && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0 | |
2935 | && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) | |
2936 | { | |
2937 | x = simplify_and_const_int (0, mode, XEXP (x, 0), | |
2938 | - INTVAL (XEXP (XEXP (x, 1), 1)) - 1); | |
2939 | goto restart; | |
2940 | } | |
2941 | break; | |
2942 | ||
2943 | case MULT: | |
2944 | /* If we have (mult (plus A B) C), apply the distributive law and then | |
2945 | the inverse distributive law to see if things simplify. This | |
2946 | occurs mostly in addresses, often when unrolling loops. */ | |
2947 | ||
2948 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
2949 | { | |
2950 | x = apply_distributive_law | |
2951 | (gen_binary (PLUS, mode, | |
2952 | gen_binary (MULT, mode, | |
2953 | XEXP (XEXP (x, 0), 0), XEXP (x, 1)), | |
2954 | gen_binary (MULT, mode, | |
2955 | XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); | |
2956 | ||
2957 | if (GET_CODE (x) != MULT) | |
2958 | goto restart; | |
2959 | } | |
2960 | ||
2961 | /* If this is multiplication by a power of two and its first operand is | |
2962 | a shift, treat the multiply as a shift to allow the shifts to | |
2963 | possibly combine. */ | |
2964 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2965 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
2966 | && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
2967 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
2968 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
2969 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
2970 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
2971 | { | |
2972 | x = simplify_shift_const (0, ASHIFT, mode, XEXP (x, 0), i); | |
2973 | goto restart; | |
2974 | } | |
2975 | ||
2976 | /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */ | |
2977 | if (GET_CODE (XEXP (x, 0)) == ASHIFT | |
2978 | && XEXP (XEXP (x, 0), 0) == const1_rtx) | |
2979 | return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1), | |
2980 | XEXP (XEXP (x, 0), 1)); | |
2981 | break; | |
2982 | ||
2983 | case UDIV: | |
2984 | /* If this is a divide by a power of two, treat it as a shift if | |
2985 | its first operand is a shift. */ | |
2986 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
2987 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0 | |
2988 | && (GET_CODE (XEXP (x, 0)) == ASHIFT | |
2989 | || GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
2990 | || GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
2991 | || GET_CODE (XEXP (x, 0)) == ROTATE | |
2992 | || GET_CODE (XEXP (x, 0)) == ROTATERT)) | |
2993 | { | |
2994 | x = simplify_shift_const (0, LSHIFTRT, mode, XEXP (x, 0), i); | |
2995 | goto restart; | |
2996 | } | |
2997 | break; | |
2998 | ||
2999 | case EQ: case NE: | |
3000 | case GT: case GTU: case GE: case GEU: | |
3001 | case LT: case LTU: case LE: case LEU: | |
3002 | /* If the first operand is a condition code, we can't do anything | |
3003 | with it. */ | |
3004 | if (GET_CODE (XEXP (x, 0)) == COMPARE | |
3005 | || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC | |
3006 | #ifdef HAVE_cc0 | |
3007 | && XEXP (x, 0) != cc0_rtx | |
3008 | #endif | |
3009 | )) | |
3010 | { | |
3011 | rtx op0 = XEXP (x, 0); | |
3012 | rtx op1 = XEXP (x, 1); | |
3013 | enum rtx_code new_code; | |
3014 | ||
3015 | if (GET_CODE (op0) == COMPARE) | |
3016 | op1 = XEXP (op0, 1), op0 = XEXP (op0, 0); | |
3017 | ||
3018 | /* Simplify our comparison, if possible. */ | |
3019 | new_code = simplify_comparison (code, &op0, &op1); | |
3020 | ||
3021 | #if STORE_FLAG_VALUE == 1 | |
3022 | /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X | |
3023 | if only the low-order bit is significant in X (such as when | |
3024 | X is a ZERO_EXTRACT of one bit. Similarly, we can convert | |
3025 | EQ to (xor X 1). */ | |
3f508eca | 3026 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
230d793d RS |
3027 | && op1 == const0_rtx |
3028 | && significant_bits (op0, GET_MODE (op0)) == 1) | |
3029 | return gen_lowpart_for_combine (mode, op0); | |
3f508eca | 3030 | else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT |
230d793d RS |
3031 | && op1 == const0_rtx |
3032 | && significant_bits (op0, GET_MODE (op0)) == 1) | |
3033 | return gen_rtx_combine (XOR, mode, | |
3034 | gen_lowpart_for_combine (mode, op0), | |
3035 | const1_rtx); | |
3036 | #endif | |
3037 | ||
3038 | #if STORE_FLAG_VALUE == -1 | |
3039 | /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0) | |
3040 | to (neg x) if only the low-order bit of X is significant. | |
3041 | This converts (ne (zero_extract X 1 Y) 0) to | |
3042 | (sign_extract X 1 Y). */ | |
3f508eca | 3043 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
230d793d RS |
3044 | && op1 == const0_rtx |
3045 | && significant_bits (op0, GET_MODE (op0)) == 1) | |
3046 | { | |
3047 | x = gen_rtx_combine (NEG, mode, | |
3048 | gen_lowpart_for_combine (mode, op0)); | |
3049 | goto restart; | |
3050 | } | |
3051 | #endif | |
3052 | ||
3053 | /* If STORE_FLAG_VALUE says to just test the sign bit and X has just | |
3054 | one significant bit, we can convert (ne x 0) to (ashift x c) | |
3055 | where C puts the bit in the sign bit. Remove any AND with | |
3056 | STORE_FLAG_VALUE when we are done, since we are only going to | |
3057 | test the sign bit. */ | |
3f508eca | 3058 | if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT |
230d793d RS |
3059 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT |
3060 | && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1) | |
3061 | && op1 == const0_rtx | |
3062 | && mode == GET_MODE (op0) | |
3063 | && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0) | |
3064 | { | |
3065 | x = simplify_shift_const (0, ASHIFT, mode, op0, | |
3066 | GET_MODE_BITSIZE (mode) - 1 - i); | |
3067 | if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx) | |
3068 | return XEXP (x, 0); | |
3069 | else | |
3070 | return x; | |
3071 | } | |
3072 | ||
3073 | /* If the code changed, return a whole new comparison. */ | |
3074 | if (new_code != code) | |
3075 | return gen_rtx_combine (new_code, mode, op0, op1); | |
3076 | ||
3077 | /* Otherwise, keep this operation, but maybe change its operands. | |
3078 | This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */ | |
3079 | SUBST (XEXP (x, 0), op0); | |
3080 | SUBST (XEXP (x, 1), op1); | |
3081 | } | |
3082 | break; | |
3083 | ||
3084 | case IF_THEN_ELSE: | |
3085 | /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be | |
3086 | reversed, do so to avoid needing two sets of patterns for | |
3087 | subtract-and-branch insns. */ | |
9797b9e8 RS |
3088 | if (XEXP (x, 1) == pc_rtx |
3089 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
3090 | && reversible_comparison_p (XEXP (x, 0))) | |
230d793d RS |
3091 | { |
3092 | SUBST (XEXP (x, 0), | |
3093 | gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), | |
3094 | GET_MODE (XEXP (x, 0)), | |
3095 | XEXP (XEXP (x, 0), 0), | |
3096 | XEXP (XEXP (x, 0), 1))); | |
3097 | SUBST (XEXP (x, 1), XEXP (x, 2)); | |
3098 | SUBST (XEXP (x, 2), pc_rtx); | |
3099 | } | |
3100 | break; | |
3101 | ||
3102 | case ZERO_EXTRACT: | |
3103 | case SIGN_EXTRACT: | |
3104 | case ZERO_EXTEND: | |
3105 | case SIGN_EXTEND: | |
3106 | /* If we are processing SET_DEST, we are done. */ | |
3107 | if (in_dest) | |
3108 | return x; | |
3109 | ||
3110 | x = expand_compound_operation (x); | |
3111 | if (GET_CODE (x) != code) | |
3112 | goto restart; | |
3113 | break; | |
3114 | ||
3115 | case SET: | |
3116 | /* (set (pc) (return)) gets written as (return). */ | |
3117 | if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN) | |
3118 | return SET_SRC (x); | |
3119 | ||
3120 | /* Convert this into a field assignment operation, if possible. */ | |
3121 | x = make_field_assignment (x); | |
3122 | ||
3123 | /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some | |
3124 | operation, and X being a REG or (subreg (reg)), we may be able to | |
3125 | convert this to (set (subreg:m2 x) (op)). | |
3126 | ||
3127 | We can always do this if M1 is narrower than M2 because that | |
3128 | means that we only care about the low bits of the result. | |
3129 | ||
3130 | However, on most machines (those with BYTE_LOADS_ZERO_EXTEND | |
3131 | not defined), we cannot perform a narrower operation that | |
3132 | requested since the high-order bits will be undefined. On | |
3133 | machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this | |
3134 | transformation is safe as long as M1 and M2 have the same number | |
3135 | of words. */ | |
3136 | ||
3137 | if (GET_CODE (SET_SRC (x)) == SUBREG | |
3138 | && subreg_lowpart_p (SET_SRC (x)) | |
3139 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o' | |
3140 | && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1)) | |
3141 | / UNITS_PER_WORD) | |
3142 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))) | |
3143 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)) | |
3144 | #ifndef BYTE_LOADS_ZERO_EXTEND | |
3145 | && (GET_MODE_SIZE (GET_MODE (SET_SRC (x))) | |
3146 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))) | |
3147 | #endif | |
3148 | && (GET_CODE (SET_DEST (x)) == REG | |
3149 | || (GET_CODE (SET_DEST (x)) == SUBREG | |
3150 | && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG))) | |
3151 | { | |
3152 | /* Get the object that will be the SUBREG_REG of the | |
3153 | SUBREG we are making. Note that SUBREG_WORD will always | |
3154 | be zero because this will either be a paradoxical SUBREG | |
3155 | or a SUBREG with the same number of words on the outside and | |
3156 | inside. */ | |
3157 | rtx object = (GET_CODE (SET_DEST (x)) == REG ? SET_DEST (x) | |
3158 | : SUBREG_REG (SET_DEST (x))); | |
3159 | ||
3160 | SUBST (SET_DEST (x), | |
3161 | gen_rtx (SUBREG, GET_MODE (SUBREG_REG (SET_SRC (x))), | |
3162 | object, 0)); | |
3163 | SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x))); | |
3164 | } | |
3165 | ||
3166 | /* If we are setting CC0 or if the source is a COMPARE, look for the | |
3167 | use of the comparison result and try to simplify it unless we already | |
3168 | have used undobuf.other_insn. */ | |
3169 | if ((GET_CODE (SET_SRC (x)) == COMPARE | |
3170 | #ifdef HAVE_cc0 | |
3171 | || SET_DEST (x) == cc0_rtx | |
3172 | #endif | |
3173 | ) | |
3174 | && (cc_use = find_single_use (SET_DEST (x), subst_insn, | |
3175 | &other_insn)) != 0 | |
3176 | && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn) | |
3177 | && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<' | |
3178 | && XEXP (*cc_use, 0) == SET_DEST (x)) | |
3179 | { | |
3180 | enum rtx_code old_code = GET_CODE (*cc_use); | |
3181 | enum rtx_code new_code; | |
3182 | rtx op0, op1; | |
3183 | int other_changed = 0; | |
3184 | enum machine_mode compare_mode = GET_MODE (SET_DEST (x)); | |
3185 | ||
3186 | if (GET_CODE (SET_SRC (x)) == COMPARE) | |
3187 | op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1); | |
3188 | else | |
3189 | op0 = SET_SRC (x), op1 = const0_rtx; | |
3190 | ||
3191 | /* Simplify our comparison, if possible. */ | |
3192 | new_code = simplify_comparison (old_code, &op0, &op1); | |
3193 | ||
3194 | #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES) | |
3195 | /* If this machine has CC modes other than CCmode, check to see | |
3196 | if we need to use a different CC mode here. */ | |
3197 | compare_mode = SELECT_CC_MODE (new_code, op0); | |
3198 | ||
3199 | /* If the mode changed, we have to change SET_DEST, the mode | |
3200 | in the compare, and the mode in the place SET_DEST is used. | |
3201 | If SET_DEST is a hard register, just build new versions with | |
3202 | the proper mode. If it is a pseudo, we lose unless it is only | |
3203 | time we set the pseudo, in which case we can safely change | |
3204 | its mode. */ | |
3205 | if (compare_mode != GET_MODE (SET_DEST (x))) | |
3206 | { | |
3207 | int regno = REGNO (SET_DEST (x)); | |
3208 | rtx new_dest = gen_rtx (REG, compare_mode, regno); | |
3209 | ||
3210 | if (regno < FIRST_PSEUDO_REGISTER | |
3211 | || (reg_n_sets[regno] == 1 | |
3212 | && ! REG_USERVAR_P (SET_DEST (x)))) | |
3213 | { | |
3214 | if (regno >= FIRST_PSEUDO_REGISTER) | |
3215 | SUBST (regno_reg_rtx[regno], new_dest); | |
3216 | ||
3217 | SUBST (SET_DEST (x), new_dest); | |
3218 | SUBST (XEXP (*cc_use, 0), new_dest); | |
3219 | other_changed = 1; | |
3220 | } | |
3221 | } | |
3222 | #endif | |
3223 | ||
3224 | /* If the code changed, we have to build a new comparison | |
3225 | in undobuf.other_insn. */ | |
3226 | if (new_code != old_code) | |
3227 | { | |
3228 | unsigned mask; | |
3229 | ||
3230 | SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use), | |
3231 | SET_DEST (x), const0_rtx)); | |
3232 | ||
3233 | /* If the only change we made was to change an EQ into an | |
3234 | NE or vice versa, OP0 has only one significant bit, | |
3235 | and OP1 is zero, check if changing the user of the condition | |
3236 | code will produce a valid insn. If it won't, we can keep | |
3237 | the original code in that insn by surrounding our operation | |
3238 | with an XOR. */ | |
3239 | ||
3240 | if (((old_code == NE && new_code == EQ) | |
3241 | || (old_code == EQ && new_code == NE)) | |
3242 | && ! other_changed && op1 == const0_rtx | |
3243 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT | |
3244 | && (exact_log2 (mask = significant_bits (op0, | |
3245 | GET_MODE (op0))) | |
3246 | >= 0)) | |
3247 | { | |
3248 | rtx pat = PATTERN (other_insn), note = 0; | |
3249 | ||
3250 | if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0 | |
3251 | && ! check_asm_operands (pat))) | |
3252 | { | |
3253 | PUT_CODE (*cc_use, old_code); | |
3254 | other_insn = 0; | |
3255 | ||
3256 | op0 = gen_binary (XOR, GET_MODE (op0), op0, | |
3257 | gen_rtx (CONST_INT, VOIDmode, mask)); | |
3258 | } | |
3259 | } | |
3260 | ||
3261 | other_changed = 1; | |
3262 | } | |
3263 | ||
3264 | if (other_changed) | |
3265 | undobuf.other_insn = other_insn; | |
3266 | ||
3267 | #ifdef HAVE_cc0 | |
3268 | /* If we are now comparing against zero, change our source if | |
3269 | needed. If we do not use cc0, we always have a COMPARE. */ | |
3270 | if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx) | |
3271 | SUBST (SET_SRC (x), op0); | |
3272 | else | |
3273 | #endif | |
3274 | ||
3275 | /* Otherwise, if we didn't previously have a COMPARE in the | |
3276 | correct mode, we need one. */ | |
3277 | if (GET_CODE (SET_SRC (x)) != COMPARE | |
3278 | || GET_MODE (SET_SRC (x)) != compare_mode) | |
3279 | SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode, | |
3280 | op0, op1)); | |
3281 | else | |
3282 | { | |
3283 | /* Otherwise, update the COMPARE if needed. */ | |
3284 | SUBST (XEXP (SET_SRC (x), 0), op0); | |
3285 | SUBST (XEXP (SET_SRC (x), 1), op1); | |
3286 | } | |
3287 | } | |
3288 | else | |
3289 | { | |
3290 | /* Get SET_SRC in a form where we have placed back any | |
3291 | compound expressions. Then do the checks below. */ | |
3292 | temp = make_compound_operation (SET_SRC (x), SET); | |
3293 | SUBST (SET_SRC (x), temp); | |
3294 | } | |
3295 | ||
3296 | #ifdef BYTE_LOADS_ZERO_EXTEND | |
3297 | /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with | |
3298 | M wider than N, this would require a paradoxical subreg. | |
3299 | Replace the subreg with a zero_extend to avoid the reload that | |
3300 | would otherwise be required. */ | |
3301 | if (GET_CODE (SET_SRC (x)) == SUBREG | |
3302 | && subreg_lowpart_p (SET_SRC (x)) | |
3303 | && SUBREG_WORD (SET_SRC (x)) == 0 | |
3304 | && (GET_MODE_SIZE (GET_MODE (SET_SRC (x))) | |
3305 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))) | |
3306 | && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM) | |
3307 | SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND, | |
3308 | GET_MODE (SET_SRC (x)), | |
3309 | XEXP (SET_SRC (x), 0))); | |
3310 | #endif | |
3311 | ||
3312 | break; | |
3313 | ||
3314 | case AND: | |
3315 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3316 | { | |
3317 | x = simplify_and_const_int (x, mode, XEXP (x, 0), | |
3318 | INTVAL (XEXP (x, 1))); | |
3319 | ||
3320 | /* If we have (ior (and (X C1) C2)) and the next restart would be | |
3321 | the last, simplify this by making C1 as small as possible | |
3322 | and then exit. */ | |
3323 | if (n_restarts >= 3 && GET_CODE (x) == IOR | |
3324 | && GET_CODE (XEXP (x, 0)) == AND | |
3325 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3326 | && GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3327 | { | |
3328 | temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0), | |
3329 | gen_rtx (CONST_INT, VOIDmode, | |
3330 | (INTVAL (XEXP (XEXP (x, 0), 1)) | |
3331 | & ~ INTVAL (XEXP (x, 1))))); | |
3332 | return gen_binary (IOR, mode, temp, XEXP (x, 1)); | |
3333 | } | |
3334 | ||
3335 | if (GET_CODE (x) != AND) | |
3336 | goto restart; | |
3337 | } | |
3338 | ||
3339 | /* Convert (A | B) & A to A. */ | |
3340 | if (GET_CODE (XEXP (x, 0)) == IOR | |
3341 | && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) | |
3342 | || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))) | |
3343 | && ! side_effects_p (XEXP (XEXP (x, 0), 0)) | |
3344 | && ! side_effects_p (XEXP (XEXP (x, 0), 1))) | |
3345 | return XEXP (x, 1); | |
3346 | ||
3347 | /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single | |
3348 | insn (and may simplify more). */ | |
3349 | else if (GET_CODE (XEXP (x, 0)) == XOR | |
3350 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) | |
3351 | && ! side_effects_p (XEXP (x, 1))) | |
3352 | { | |
3353 | x = gen_binary (AND, mode, | |
3354 | gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)), | |
3355 | XEXP (x, 1)); | |
3356 | goto restart; | |
3357 | } | |
3358 | else if (GET_CODE (XEXP (x, 0)) == XOR | |
3359 | && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)) | |
3360 | && ! side_effects_p (XEXP (x, 1))) | |
3361 | { | |
3362 | x = gen_binary (AND, mode, | |
3363 | gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)), | |
3364 | XEXP (x, 1)); | |
3365 | goto restart; | |
3366 | } | |
3367 | ||
3368 | /* Similarly for (~ (A ^ B)) & A. */ | |
3369 | else if (GET_CODE (XEXP (x, 0)) == NOT | |
3370 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR | |
3371 | && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1)) | |
3372 | && ! side_effects_p (XEXP (x, 1))) | |
3373 | { | |
3374 | x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1), | |
3375 | XEXP (x, 1)); | |
3376 | goto restart; | |
3377 | } | |
3378 | else if (GET_CODE (XEXP (x, 0)) == NOT | |
3379 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR | |
3380 | && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1)) | |
3381 | && ! side_effects_p (XEXP (x, 1))) | |
3382 | { | |
3383 | x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0), | |
3384 | XEXP (x, 1)); | |
3385 | goto restart; | |
3386 | } | |
3387 | ||
3388 | /* In the follow group of tests (and those in case IOR below), | |
3389 | we start with some combination of logical operations and apply | |
3390 | the distributive law followed by the inverse distributive law. | |
3391 | Most of the time, this results in no change. However, if some of | |
3392 | the operands are the same or inverses of each other, simplifications | |
3393 | will result. | |
3394 | ||
3395 | For example, (and (ior A B) (not B)) can occur as the result of | |
3396 | expanding a bit field assignment. When we apply the distributive | |
3397 | law to this, we get (ior (and (A (not B))) (and (B (not B)))), | |
3398 | which then simplifies to (and (A (not B))). */ | |
3399 | ||
3400 | /* If we have (and (ior A B) C), apply the distributive law and then | |
3401 | the inverse distributive law to see if things simplify. */ | |
3402 | ||
3403 | if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR) | |
3404 | { | |
3405 | x = apply_distributive_law | |
3406 | (gen_binary (GET_CODE (XEXP (x, 0)), mode, | |
3407 | gen_binary (AND, mode, | |
3408 | XEXP (XEXP (x, 0), 0), XEXP (x, 1)), | |
3409 | gen_binary (AND, mode, | |
3410 | XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); | |
3411 | if (GET_CODE (x) != AND) | |
3412 | goto restart; | |
3413 | } | |
3414 | ||
3415 | if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR) | |
3416 | { | |
3417 | x = apply_distributive_law | |
3418 | (gen_binary (GET_CODE (XEXP (x, 1)), mode, | |
3419 | gen_binary (AND, mode, | |
3420 | XEXP (XEXP (x, 1), 0), XEXP (x, 0)), | |
3421 | gen_binary (AND, mode, | |
3422 | XEXP (XEXP (x, 1), 1), XEXP (x, 0)))); | |
3423 | if (GET_CODE (x) != AND) | |
3424 | goto restart; | |
3425 | } | |
3426 | ||
3427 | /* Similarly, taking advantage of the fact that | |
3428 | (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */ | |
3429 | ||
3430 | if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR) | |
3431 | { | |
3432 | x = apply_distributive_law | |
3433 | (gen_binary (XOR, mode, | |
3434 | gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0), | |
3435 | XEXP (XEXP (x, 1), 0)), | |
3436 | gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0), | |
3437 | XEXP (XEXP (x, 1), 1)))); | |
3438 | if (GET_CODE (x) != AND) | |
3439 | goto restart; | |
3440 | } | |
3441 | ||
3442 | else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR) | |
3443 | { | |
3444 | x = apply_distributive_law | |
3445 | (gen_binary (XOR, mode, | |
3446 | gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0), | |
3447 | XEXP (XEXP (x, 0), 0)), | |
3448 | gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0), | |
3449 | XEXP (XEXP (x, 0), 1)))); | |
3450 | if (GET_CODE (x) != AND) | |
3451 | goto restart; | |
3452 | } | |
3453 | break; | |
3454 | ||
3455 | case IOR: | |
3456 | /* Convert (A & B) | A to A. */ | |
3457 | if (GET_CODE (XEXP (x, 0)) == AND | |
3458 | && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) | |
3459 | || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))) | |
3460 | && ! side_effects_p (XEXP (XEXP (x, 0), 0)) | |
3461 | && ! side_effects_p (XEXP (XEXP (x, 0), 1))) | |
3462 | return XEXP (x, 1); | |
3463 | ||
3464 | /* If we have (ior (and A B) C), apply the distributive law and then | |
3465 | the inverse distributive law to see if things simplify. */ | |
3466 | ||
3467 | if (GET_CODE (XEXP (x, 0)) == AND) | |
3468 | { | |
3469 | x = apply_distributive_law | |
3470 | (gen_binary (AND, mode, | |
3471 | gen_binary (IOR, mode, | |
3472 | XEXP (XEXP (x, 0), 0), XEXP (x, 1)), | |
3473 | gen_binary (IOR, mode, | |
3474 | XEXP (XEXP (x, 0), 1), XEXP (x, 1)))); | |
3475 | ||
3476 | if (GET_CODE (x) != IOR) | |
3477 | goto restart; | |
3478 | } | |
3479 | ||
3480 | if (GET_CODE (XEXP (x, 1)) == AND) | |
3481 | { | |
3482 | x = apply_distributive_law | |
3483 | (gen_binary (AND, mode, | |
3484 | gen_binary (IOR, mode, | |
3485 | XEXP (XEXP (x, 1), 0), XEXP (x, 0)), | |
3486 | gen_binary (IOR, mode, | |
3487 | XEXP (XEXP (x, 1), 1), XEXP (x, 0)))); | |
3488 | ||
3489 | if (GET_CODE (x) != IOR) | |
3490 | goto restart; | |
3491 | } | |
3492 | ||
3493 | /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the | |
3494 | mode size to (rotate A CX). */ | |
3495 | ||
3496 | if (((GET_CODE (XEXP (x, 0)) == ASHIFT | |
3497 | && GET_CODE (XEXP (x, 1)) == LSHIFTRT) | |
3498 | || (GET_CODE (XEXP (x, 1)) == ASHIFT | |
3499 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT)) | |
3500 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0)) | |
3501 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3502 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
3503 | && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1)) | |
3504 | == GET_MODE_BITSIZE (mode))) | |
3505 | { | |
3506 | rtx shift_count; | |
3507 | ||
3508 | if (GET_CODE (XEXP (x, 0)) == ASHIFT) | |
3509 | shift_count = XEXP (XEXP (x, 0), 1); | |
3510 | else | |
3511 | shift_count = XEXP (XEXP (x, 1), 1); | |
3512 | x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count); | |
3513 | goto restart; | |
3514 | } | |
3515 | break; | |
3516 | ||
3517 | case XOR: | |
3518 | /* Convert (XOR (NOT x) (NOT y)) to (XOR x y). | |
3519 | Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for | |
3520 | (NOT y). */ | |
3521 | { | |
3522 | int num_negated = 0; | |
3523 | rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1); | |
3524 | ||
3525 | if (GET_CODE (in1) == NOT) | |
3526 | num_negated++, in1 = XEXP (in1, 0); | |
3527 | if (GET_CODE (in2) == NOT) | |
3528 | num_negated++, in2 = XEXP (in2, 0); | |
3529 | ||
3530 | if (num_negated == 2) | |
3531 | { | |
3532 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
3533 | SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0)); | |
3534 | } | |
3535 | else if (num_negated == 1) | |
3536 | return gen_rtx_combine (NOT, mode, | |
3537 | gen_rtx_combine (XOR, mode, in1, in2)); | |
3538 | } | |
3539 | ||
3540 | /* Convert (xor (and A B) B) to (and (not A) B). The latter may | |
3541 | correspond to a machine insn or result in further simplifications | |
3542 | if B is a constant. */ | |
3543 | ||
3544 | if (GET_CODE (XEXP (x, 0)) == AND | |
3545 | && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)) | |
3546 | && ! side_effects_p (XEXP (x, 1))) | |
3547 | { | |
3548 | x = gen_binary (AND, mode, | |
3549 | gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)), | |
3550 | XEXP (x, 1)); | |
3551 | goto restart; | |
3552 | } | |
3553 | else if (GET_CODE (XEXP (x, 0)) == AND | |
3554 | && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)) | |
3555 | && ! side_effects_p (XEXP (x, 1))) | |
3556 | { | |
3557 | x = gen_binary (AND, mode, | |
3558 | gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)), | |
3559 | XEXP (x, 1)); | |
3560 | goto restart; | |
3561 | } | |
3562 | ||
3563 | ||
3564 | #if STORE_FLAG_VALUE == 1 | |
3565 | /* (xor (comparison foo bar) (const_int 1)) can become the reversed | |
3566 | comparison. */ | |
3567 | if (XEXP (x, 1) == const1_rtx | |
3568 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
3569 | && reversible_comparison_p (XEXP (x, 0))) | |
3570 | return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), | |
3571 | mode, XEXP (XEXP (x, 0), 0), | |
3572 | XEXP (XEXP (x, 0), 1)); | |
3573 | #endif | |
3574 | ||
3575 | /* (xor (comparison foo bar) (const_int sign-bit)) | |
3576 | when STORE_FLAG_VALUE is the sign bit. */ | |
3577 | if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT | |
3578 | && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1) | |
3579 | && XEXP (x, 1) == const_true_rtx | |
3580 | && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
3581 | && reversible_comparison_p (XEXP (x, 0))) | |
3582 | return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))), | |
3583 | mode, XEXP (XEXP (x, 0), 0), | |
3584 | XEXP (XEXP (x, 0), 1)); | |
3585 | break; | |
3586 | ||
3587 | case ABS: | |
3588 | /* (abs (neg <foo>)) -> (abs <foo>) */ | |
3589 | if (GET_CODE (XEXP (x, 0)) == NEG) | |
3590 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
3591 | ||
3592 | /* If operand is something known to be positive, ignore the ABS. */ | |
3593 | if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS | |
3594 | || (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_INT | |
3595 | && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0))) | |
3596 | & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) | |
3597 | == 0))) | |
3598 | return XEXP (x, 0); | |
3599 | ||
3600 | ||
3601 | /* If operand is known to be only -1 or 0, convert ABS to NEG. */ | |
3602 | if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT | |
3603 | && XEXP (XEXP (x, 0), 1) == const1_rtx) | |
3604 | || (GET_CODE (XEXP (x, 0)) == ASHIFTRT | |
3605 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3606 | && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1) | |
3607 | || ((temp = get_last_value (XEXP (x, 0))) != 0 | |
3608 | && ((GET_CODE (temp) == SIGN_EXTRACT | |
3609 | && XEXP (temp, 1) == const1_rtx) | |
3610 | || (GET_CODE (temp) == ASHIFTRT | |
3611 | && GET_CODE (XEXP (temp, 1)) == CONST_INT | |
3612 | && (INTVAL (XEXP (temp, 1)) | |
3613 | == GET_MODE_BITSIZE (mode) - 1))))) | |
3614 | { | |
3615 | x = gen_rtx_combine (NEG, mode, XEXP (x, 0)); | |
3616 | goto restart; | |
3617 | } | |
3618 | break; | |
3619 | ||
a7c99304 RK |
3620 | case FFS: |
3621 | /* (ffs (*_extend <X>)) = (ffs <X>) */ | |
3622 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND | |
3623 | || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND) | |
3624 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
3625 | break; | |
3626 | ||
230d793d RS |
3627 | case FLOAT: |
3628 | /* (float (sign_extend <X>)) = (float <X>). */ | |
3629 | if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) | |
3630 | SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0)); | |
3631 | break; | |
3632 | ||
3633 | case LSHIFT: | |
3634 | case ASHIFT: | |
3635 | case LSHIFTRT: | |
3636 | case ASHIFTRT: | |
3637 | case ROTATE: | |
3638 | case ROTATERT: | |
3639 | #ifdef SHIFT_COUNT_TRUNCATED | |
3640 | /* (*shift <X> (sign_extend <Y>)) = (*shift <X> <Y>) (most machines). | |
3641 | True for all kinds of shifts and also for zero_extend. */ | |
3642 | if ((GET_CODE (XEXP (x, 1)) == SIGN_EXTEND | |
3643 | || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND) | |
3644 | && FAKE_EXTEND_SAFE_P (mode, XEXP (XEXP (x, 1), 0))) | |
3645 | SUBST (XEXP (x, 1), | |
3646 | /* This is a perverse SUBREG, wider than its base. */ | |
3647 | gen_lowpart_for_combine (mode, XEXP (XEXP (x, 1), 0))); | |
3648 | ||
3649 | /* tege: Change (bitshifts ... (and ... mask), c) | |
3650 | to (bitshifts ... c) if mask just masks the bits the bitshift | |
3651 | insns do automatically on this machine. */ | |
3652 | if (GET_CODE (XEXP (x, 1)) == AND | |
3653 | && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT | |
3654 | && (~ INTVAL (XEXP (XEXP (x, 1), 1)) & GET_MODE_MASK (mode)) == 0) | |
3655 | SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0)); | |
3656 | #endif | |
3657 | ||
3658 | /* If this is a shift by a constant amount, simplify it. */ | |
3659 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
3660 | { | |
3661 | x = simplify_shift_const (x, code, mode, XEXP (x, 0), | |
3662 | INTVAL (XEXP (x, 1))); | |
3663 | if (GET_CODE (x) != code) | |
3664 | goto restart; | |
3665 | } | |
3666 | break; | |
3667 | } | |
3668 | ||
3669 | return x; | |
3670 | } | |
3671 | \f | |
3672 | /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound | |
3673 | operations" because they can be replaced with two more basic operations. | |
3674 | ZERO_EXTEND is also considered "compound" because it can be replaced with | |
3675 | an AND operation, which is simpler, though only one operation. | |
3676 | ||
3677 | The function expand_compound_operation is called with an rtx expression | |
3678 | and will convert it to the appropriate shifts and AND operations, | |
3679 | simplifying at each stage. | |
3680 | ||
3681 | The function make_compound_operation is called to convert an expression | |
3682 | consisting of shifts and ANDs into the equivalent compound expression. | |
3683 | It is the inverse of this function, loosely speaking. */ | |
3684 | ||
3685 | static rtx | |
3686 | expand_compound_operation (x) | |
3687 | rtx x; | |
3688 | { | |
3689 | int pos = 0, len; | |
3690 | int unsignedp = 0; | |
3691 | int modewidth; | |
3692 | rtx tem; | |
3693 | ||
3694 | switch (GET_CODE (x)) | |
3695 | { | |
3696 | case ZERO_EXTEND: | |
3697 | unsignedp = 1; | |
3698 | case SIGN_EXTEND: | |
75473182 RS |
3699 | /* We can't necessarily use a const_int for a multiword mode; |
3700 | it depends on implicitly extending the value. | |
3701 | Since we don't know the right way to extend it, | |
3702 | we can't tell whether the implicit way is right. | |
3703 | ||
3704 | Even for a mode that is no wider than a const_int, | |
3705 | we can't win, because we need to sign extend one of its bits through | |
3706 | the rest of it, and we don't know which bit. */ | |
230d793d | 3707 | if (GET_CODE (XEXP (x, 0)) == CONST_INT) |
75473182 | 3708 | return x; |
230d793d RS |
3709 | |
3710 | if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0))) | |
3711 | return x; | |
3712 | ||
3713 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))); | |
3714 | /* If the inner object has VOIDmode (the only way this can happen | |
3715 | is if it is a ASM_OPERANDS), we can't do anything since we don't | |
3716 | know how much masking to do. */ | |
3717 | if (len == 0) | |
3718 | return x; | |
3719 | ||
3720 | break; | |
3721 | ||
3722 | case ZERO_EXTRACT: | |
3723 | unsignedp = 1; | |
3724 | case SIGN_EXTRACT: | |
3725 | /* If the operand is a CLOBBER, just return it. */ | |
3726 | if (GET_CODE (XEXP (x, 0)) == CLOBBER) | |
3727 | return XEXP (x, 0); | |
3728 | ||
3729 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
3730 | || GET_CODE (XEXP (x, 2)) != CONST_INT | |
3731 | || GET_MODE (XEXP (x, 0)) == VOIDmode) | |
3732 | return x; | |
3733 | ||
3734 | len = INTVAL (XEXP (x, 1)); | |
3735 | pos = INTVAL (XEXP (x, 2)); | |
3736 | ||
3737 | /* If this goes outside the object being extracted, replace the object | |
3738 | with a (use (mem ...)) construct that only combine understands | |
3739 | and is used only for this purpose. */ | |
3740 | if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) | |
3741 | SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0))); | |
3742 | ||
3743 | #if BITS_BIG_ENDIAN | |
3744 | pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos; | |
3745 | #endif | |
3746 | break; | |
3747 | ||
3748 | default: | |
3749 | return x; | |
3750 | } | |
3751 | ||
3752 | /* If we reach here, we want to return a pair of shifts. The inner | |
3753 | shift is a left shift of BITSIZE - POS - LEN bits. The outer | |
3754 | shift is a right shift of BITSIZE - LEN bits. It is arithmetic or | |
3755 | logical depending on the value of UNSIGNEDP. | |
3756 | ||
3757 | If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be | |
3758 | converted into an AND of a shift. | |
3759 | ||
3760 | We must check for the case where the left shift would have a negative | |
3761 | count. This can happen in a case like (x >> 31) & 255 on machines | |
3762 | that can't shift by a constant. On those machines, we would first | |
3763 | combine the shift with the AND to produce a variable-position | |
3764 | extraction. Then the constant of 31 would be substituted in to produce | |
3765 | a such a position. */ | |
3766 | ||
3767 | modewidth = GET_MODE_BITSIZE (GET_MODE (x)); | |
3768 | if (modewidth >= pos - len) | |
3769 | tem = simplify_shift_const (0, unsignedp ? LSHIFTRT : ASHIFTRT, | |
3770 | GET_MODE (x), | |
3771 | simplify_shift_const (0, ASHIFT, GET_MODE (x), | |
3772 | XEXP (x, 0), | |
3773 | modewidth - pos - len), | |
3774 | modewidth - len); | |
3775 | ||
3776 | else if (unsignedp && len < HOST_BITS_PER_INT) | |
3777 | tem = simplify_and_const_int (0, GET_MODE (x), | |
3778 | simplify_shift_const (0, LSHIFTRT, | |
3779 | GET_MODE (x), | |
3780 | XEXP (x, 0), pos), | |
3781 | (1 << len) - 1); | |
3782 | else | |
3783 | /* Any other cases we can't handle. */ | |
3784 | return x; | |
3785 | ||
3786 | ||
3787 | /* If we couldn't do this for some reason, return the original | |
3788 | expression. */ | |
3789 | if (GET_CODE (tem) == CLOBBER) | |
3790 | return x; | |
3791 | ||
3792 | return tem; | |
3793 | } | |
3794 | \f | |
3795 | /* X is a SET which contains an assignment of one object into | |
3796 | a part of another (such as a bit-field assignment, STRICT_LOW_PART, | |
3797 | or certain SUBREGS). If possible, convert it into a series of | |
3798 | logical operations. | |
3799 | ||
3800 | We half-heartedly support variable positions, but do not at all | |
3801 | support variable lengths. */ | |
3802 | ||
3803 | static rtx | |
3804 | expand_field_assignment (x) | |
3805 | rtx x; | |
3806 | { | |
3807 | rtx inner; | |
3808 | rtx pos; /* Always counts from low bit. */ | |
3809 | int len; | |
3810 | rtx mask; | |
3811 | enum machine_mode compute_mode; | |
3812 | ||
3813 | /* Loop until we find something we can't simplify. */ | |
3814 | while (1) | |
3815 | { | |
3816 | if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART | |
3817 | && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG) | |
3818 | { | |
3819 | inner = SUBREG_REG (XEXP (SET_DEST (x), 0)); | |
3820 | len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))); | |
3821 | pos = const0_rtx; | |
3822 | } | |
3823 | else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT | |
3824 | && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT) | |
3825 | { | |
3826 | inner = XEXP (SET_DEST (x), 0); | |
3827 | len = INTVAL (XEXP (SET_DEST (x), 1)); | |
3828 | pos = XEXP (SET_DEST (x), 2); | |
3829 | ||
3830 | /* If the position is constant and spans the width of INNER, | |
3831 | surround INNER with a USE to indicate this. */ | |
3832 | if (GET_CODE (pos) == CONST_INT | |
3833 | && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner))) | |
3834 | inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner); | |
3835 | ||
3836 | #if BITS_BIG_ENDIAN | |
3837 | if (GET_CODE (pos) == CONST_INT) | |
3838 | pos = gen_rtx (CONST_INT, VOIDmode, | |
3839 | (GET_MODE_BITSIZE (GET_MODE (inner)) - len | |
3840 | - INTVAL (pos))); | |
3841 | else if (GET_CODE (pos) == MINUS | |
3842 | && GET_CODE (XEXP (pos, 1)) == CONST_INT | |
3843 | && (INTVAL (XEXP (pos, 1)) | |
3844 | == GET_MODE_BITSIZE (GET_MODE (inner)) - len)) | |
3845 | /* If position is ADJUST - X, new position is X. */ | |
3846 | pos = XEXP (pos, 0); | |
3847 | else | |
3848 | pos = gen_binary (MINUS, GET_MODE (pos), | |
3849 | gen_rtx (CONST_INT, VOIDmode, | |
3850 | (GET_MODE_BITSIZE (GET_MODE (inner)) | |
3851 | - len)), pos); | |
3852 | #endif | |
3853 | } | |
3854 | ||
3855 | /* A SUBREG between two modes that occupy the same numbers of words | |
3856 | can be done by moving the SUBREG to the source. */ | |
3857 | else if (GET_CODE (SET_DEST (x)) == SUBREG | |
3858 | && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x))) | |
3859 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
3860 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x)))) | |
3861 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) | |
3862 | { | |
3863 | x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)), | |
3864 | gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))), | |
3865 | SET_SRC (x))); | |
3866 | continue; | |
3867 | } | |
3868 | else | |
3869 | break; | |
3870 | ||
3871 | while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
3872 | inner = SUBREG_REG (inner); | |
3873 | ||
3874 | compute_mode = GET_MODE (inner); | |
3875 | ||
3876 | /* Compute a mask of LEN bits, if we can do this on the host machine. */ | |
3877 | if (len < HOST_BITS_PER_INT) | |
3878 | mask = gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1); | |
3879 | else | |
3880 | break; | |
3881 | ||
3882 | /* Now compute the equivalent expression. Make a copy of INNER | |
3883 | for the SET_DEST in case it is a MEM into which we will substitute; | |
3884 | we don't want shared RTL in that case. */ | |
3885 | x = gen_rtx (SET, VOIDmode, copy_rtx (inner), | |
3886 | gen_binary (IOR, compute_mode, | |
3887 | gen_binary (AND, compute_mode, | |
3888 | gen_unary (NOT, compute_mode, | |
3889 | gen_binary (ASHIFT, | |
3890 | compute_mode, | |
3891 | mask, pos)), | |
3892 | inner), | |
3893 | gen_binary (ASHIFT, compute_mode, | |
3894 | gen_binary (AND, compute_mode, | |
3895 | gen_lowpart_for_combine | |
3896 | (compute_mode, | |
3897 | SET_SRC (x)), | |
3898 | mask), | |
3899 | pos))); | |
3900 | } | |
3901 | ||
3902 | return x; | |
3903 | } | |
3904 | \f | |
3905 | /* Return an RTX for a reference to LEN bits of INNER. POS is the starting | |
3906 | bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents | |
3907 | the starting bit position. | |
3908 | ||
3909 | INNER may be a USE. This will occur when we started with a bitfield | |
3910 | that went outside the boundary of the object in memory, which is | |
3911 | allowed on most machines. To isolate this case, we produce a USE | |
3912 | whose mode is wide enough and surround the MEM with it. The only | |
3913 | code that understands the USE is this routine. If it is not removed, | |
3914 | it will cause the resulting insn not to match. | |
3915 | ||
3916 | UNSIGNEDP is non-zero for an unsigned reference and zero for a | |
3917 | signed reference. | |
3918 | ||
3919 | IN_DEST is non-zero if this is a reference in the destination of a | |
3920 | SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero, | |
3921 | a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will | |
3922 | be used. | |
3923 | ||
3924 | IN_COMPARE is non-zero if we are in a COMPARE. This means that a | |
3925 | ZERO_EXTRACT should be built even for bits starting at bit 0. | |
3926 | ||
3927 | MODE is the desired mode of the result (if IN_DEST == 0). */ | |
3928 | ||
3929 | static rtx | |
3930 | make_extraction (mode, inner, pos, pos_rtx, len, | |
3931 | unsignedp, in_dest, in_compare) | |
3932 | enum machine_mode mode; | |
3933 | rtx inner; | |
3934 | int pos; | |
3935 | rtx pos_rtx; | |
3936 | int len; | |
3937 | int unsignedp; | |
3938 | int in_dest, in_compare; | |
3939 | { | |
3940 | enum machine_mode is_mode = GET_MODE (inner); | |
3941 | enum machine_mode inner_mode; | |
3942 | enum machine_mode wanted_mem_mode = byte_mode; | |
3943 | enum machine_mode pos_mode = word_mode; | |
3944 | enum machine_mode extraction_mode = word_mode; | |
3945 | enum machine_mode tmode = mode_for_size (len, MODE_INT, 1); | |
3946 | int spans_byte = 0; | |
3947 | rtx new = 0; | |
3948 | ||
3949 | /* Get some information about INNER and get the innermost object. */ | |
3950 | if (GET_CODE (inner) == USE) | |
3951 | /* We don't need to adjust the position because we set up the USE | |
3952 | to pretend that it was a full-word object. */ | |
3953 | spans_byte = 1, inner = XEXP (inner, 0); | |
3954 | else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner)) | |
3955 | inner = SUBREG_REG (inner); | |
3956 | ||
3957 | inner_mode = GET_MODE (inner); | |
3958 | ||
3959 | if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT) | |
3960 | pos = INTVAL (pos_rtx); | |
3961 | ||
3962 | /* See if this can be done without an extraction. We never can if the | |
3963 | width of the field is not the same as that of some integer mode. For | |
3964 | registers, we can only avoid the extraction if the position is at the | |
3965 | low-order bit and this is either not in the destination or we have the | |
3966 | appropriate STRICT_LOW_PART operation available. | |
3967 | ||
3968 | For MEM, we can avoid an extract if the field starts on an appropriate | |
3969 | boundary and we can change the mode of the memory reference. However, | |
3970 | we cannot directly access the MEM if we have a USE and the underlying | |
3971 | MEM is not TMODE. This combination means that MEM was being used in a | |
3972 | context where bits outside its mode were being referenced; that is only | |
3973 | valid in bit-field insns. */ | |
3974 | ||
3975 | if (tmode != BLKmode | |
3976 | && ! (spans_byte && inner_mode != tmode) | |
3977 | && ((pos == 0 && GET_CODE (inner) == REG | |
3978 | && (! in_dest | |
3979 | || (movstrict_optab->handlers[(int) tmode].insn_code | |
3980 | != CODE_FOR_nothing))) | |
3981 | || (GET_CODE (inner) == MEM && pos >= 0 | |
dfbe1b2f RK |
3982 | && (pos |
3983 | % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode) | |
3984 | : BITS_PER_UNIT)) == 0 | |
230d793d RS |
3985 | /* We can't do this if we are widening INNER_MODE (it |
3986 | may not be aligned, for one thing). */ | |
3987 | && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode) | |
3988 | && (inner_mode == tmode | |
3989 | || (! mode_dependent_address_p (XEXP (inner, 0)) | |
3990 | && ! MEM_VOLATILE_P (inner)))))) | |
3991 | { | |
3992 | int offset = pos / BITS_PER_UNIT; | |
3993 | ||
3994 | /* If INNER is a MEM, make a new MEM that encompasses just the desired | |
3995 | field. If the original and current mode are the same, we need not | |
3996 | adjust the offset. Otherwise, we do if bytes big endian. | |
3997 | ||
3998 | If INNER is not a MEM, get a piece consisting of the just the field | |
3999 | of interest (in this case INNER must be a REG and POS must be 0). */ | |
4000 | ||
4001 | if (GET_CODE (inner) == MEM) | |
4002 | { | |
4003 | #if BYTES_BIG_ENDIAN | |
4004 | if (inner_mode != tmode) | |
4005 | offset = (GET_MODE_SIZE (inner_mode) | |
4006 | - GET_MODE_SIZE (tmode) - offset); | |
4007 | #endif | |
4008 | ||
4009 | new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset)); | |
4010 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner); | |
4011 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner); | |
4012 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner); | |
4013 | } | |
4014 | else | |
4015 | new = gen_lowpart_for_combine (tmode, inner); | |
4016 | ||
4017 | /* If this extraction is going into the destination of a SET, | |
4018 | make a STRICT_LOW_PART unless we made a MEM. */ | |
4019 | ||
4020 | if (in_dest) | |
4021 | return (GET_CODE (new) == MEM ? new | |
4022 | : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)); | |
4023 | ||
4024 | /* Otherwise, sign- or zero-extend unless we already are in the | |
4025 | proper mode. */ | |
4026 | ||
4027 | return (mode == tmode ? new | |
4028 | : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND, | |
4029 | mode, new)); | |
4030 | } | |
4031 | ||
4032 | /* Unless this is in a COMPARE or we have a funny memory reference, | |
4033 | don't do anything with field extracts starting at the low-order | |
4034 | bit since they are simple AND operations. */ | |
4035 | if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte) | |
4036 | return 0; | |
4037 | ||
4038 | /* Get the mode to use should INNER be a MEM, the mode for the position, | |
4039 | and the mode for the result. */ | |
4040 | #ifdef HAVE_insv | |
4041 | if (in_dest) | |
4042 | { | |
4043 | wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0]; | |
4044 | pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2]; | |
4045 | extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3]; | |
4046 | } | |
4047 | #endif | |
4048 | ||
4049 | #ifdef HAVE_extzv | |
4050 | if (! in_dest && unsignedp) | |
4051 | { | |
4052 | wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1]; | |
4053 | pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3]; | |
4054 | extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0]; | |
4055 | } | |
4056 | #endif | |
4057 | ||
4058 | #ifdef HAVE_extv | |
4059 | if (! in_dest && ! unsignedp) | |
4060 | { | |
4061 | wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1]; | |
4062 | pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3]; | |
4063 | extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0]; | |
4064 | } | |
4065 | #endif | |
4066 | ||
4067 | /* Never narrow an object, since that might not be safe. */ | |
4068 | ||
4069 | if (mode != VOIDmode | |
4070 | && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode)) | |
4071 | extraction_mode = mode; | |
4072 | ||
4073 | if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode | |
4074 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
4075 | pos_mode = GET_MODE (pos_rtx); | |
4076 | ||
4077 | /* If this is not from memory or we have to change the mode of memory and | |
4078 | cannot, the desired mode is EXTRACTION_MODE. */ | |
4079 | if (GET_CODE (inner) != MEM | |
4080 | || (inner_mode != wanted_mem_mode | |
4081 | && (mode_dependent_address_p (XEXP (inner, 0)) | |
4082 | || MEM_VOLATILE_P (inner)))) | |
4083 | wanted_mem_mode = extraction_mode; | |
4084 | ||
4085 | #if BITS_BIG_ENDIAN | |
4086 | /* If position is constant, compute new position. Otherwise, build | |
4087 | subtraction. */ | |
4088 | if (pos >= 0) | |
4089 | pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode)) | |
4090 | - len - pos); | |
4091 | else | |
4092 | pos_rtx | |
4093 | = gen_rtx_combine (MINUS, GET_MODE (pos_rtx), | |
4094 | gen_rtx (CONST_INT, VOIDmode, | |
4095 | (MAX (GET_MODE_BITSIZE (is_mode), | |
4096 | GET_MODE_BITSIZE (wanted_mem_mode)) | |
4097 | - len)), pos_rtx); | |
4098 | #endif | |
4099 | ||
4100 | /* If INNER has a wider mode, make it smaller. If this is a constant | |
4101 | extract, try to adjust the byte to point to the byte containing | |
4102 | the value. */ | |
4103 | if (wanted_mem_mode != VOIDmode | |
4104 | && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode) | |
4105 | && ((GET_CODE (inner) == MEM | |
4106 | && (inner_mode == wanted_mem_mode | |
4107 | || (! mode_dependent_address_p (XEXP (inner, 0)) | |
4108 | && ! MEM_VOLATILE_P (inner)))))) | |
4109 | { | |
4110 | int offset = 0; | |
4111 | ||
4112 | /* The computations below will be correct if the machine is big | |
4113 | endian in both bits and bytes or little endian in bits and bytes. | |
4114 | If it is mixed, we must adjust. */ | |
4115 | ||
4116 | #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN | |
4117 | if (! spans_byte && is_mode != wanted_mem_mode) | |
4118 | offset = (GET_MODE_SIZE (is_mode) | |
4119 | - GET_MODE_SIZE (wanted_mem_mode) - offset); | |
4120 | #endif | |
4121 | ||
4122 | /* If bytes are big endian and we had a paradoxical SUBREG, we must | |
4123 | adjust OFFSET to compensate. */ | |
4124 | #if BYTES_BIG_ENDIAN | |
4125 | if (! spans_byte | |
4126 | && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode)) | |
4127 | offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode); | |
4128 | #endif | |
4129 | ||
4130 | /* If this is a constant position, we can move to the desired byte. */ | |
4131 | if (pos >= 0) | |
4132 | { | |
4133 | offset += pos / BITS_PER_UNIT; | |
4134 | pos %= GET_MODE_BITSIZE (wanted_mem_mode); | |
4135 | } | |
4136 | ||
4137 | if (offset != 0 || inner_mode != wanted_mem_mode) | |
4138 | { | |
4139 | rtx newmem = gen_rtx (MEM, wanted_mem_mode, | |
4140 | plus_constant (XEXP (inner, 0), offset)); | |
4141 | RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner); | |
4142 | MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner); | |
4143 | MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner); | |
4144 | inner = newmem; | |
4145 | } | |
4146 | } | |
4147 | ||
4148 | /* If INNER is not memory, we can always get it into the proper mode. */ | |
4149 | else if (GET_CODE (inner) != MEM) | |
4150 | inner = gen_lowpart_for_combine (extraction_mode, inner); | |
4151 | ||
4152 | /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we | |
4153 | have to zero extend. Otherwise, we can just use a SUBREG. */ | |
4154 | if (pos < 0 | |
4155 | && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
4156 | pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx); | |
4157 | else if (pos < 0 | |
4158 | && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx))) | |
4159 | pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx); | |
4160 | ||
4161 | /* Make POS_RTX unless we already have it and it is correct. */ | |
4162 | if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos)) | |
4163 | pos_rtx = gen_rtx (CONST_INT, VOIDmode, pos); | |
4164 | ||
4165 | /* Make the required operation. See if we can use existing rtx. */ | |
4166 | new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT, | |
4167 | extraction_mode, inner, | |
4168 | gen_rtx (CONST_INT, VOIDmode, len), pos_rtx); | |
4169 | if (! in_dest) | |
4170 | new = gen_lowpart_for_combine (mode, new); | |
4171 | ||
4172 | return new; | |
4173 | } | |
4174 | \f | |
4175 | /* Look at the expression rooted at X. Look for expressions | |
4176 | equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND. | |
4177 | Form these expressions. | |
4178 | ||
4179 | Return the new rtx, usually just X. | |
4180 | ||
4181 | Also, for machines like the Vax that don't have logical shift insns, | |
4182 | try to convert logical to arithmetic shift operations in cases where | |
4183 | they are equivalent. This undoes the canonicalizations to logical | |
4184 | shifts done elsewhere. | |
4185 | ||
4186 | We try, as much as possible, to re-use rtl expressions to save memory. | |
4187 | ||
4188 | IN_CODE says what kind of expression we are processing. Normally, it is | |
4189 | SET. In a memory address (inside a MEM or PLUS, the latter being a | |
4190 | kludge), it is MEM. When processing the arguments of a comparison | |
4191 | or a COMPARE against zero, it is COMPARE. */ | |
4192 | ||
4193 | static rtx | |
4194 | make_compound_operation (x, in_code) | |
4195 | rtx x; | |
4196 | enum rtx_code in_code; | |
4197 | { | |
4198 | enum rtx_code code = GET_CODE (x); | |
4199 | enum machine_mode mode = GET_MODE (x); | |
4200 | int mode_width = GET_MODE_BITSIZE (mode); | |
4201 | enum rtx_code next_code; | |
4202 | int i; | |
4203 | rtx new = 0; | |
4204 | char *fmt; | |
4205 | ||
4206 | /* Select the code to be used in recursive calls. Once we are inside an | |
4207 | address, we stay there. If we have a comparison, set to COMPARE, | |
4208 | but once inside, go back to our default of SET. */ | |
4209 | ||
4210 | next_code = (code == MEM || code == PLUS ? MEM | |
4211 | : ((code == COMPARE || GET_RTX_CLASS (code) == '<') | |
4212 | && XEXP (x, 1) == const0_rtx) ? COMPARE | |
4213 | : in_code == COMPARE ? SET : in_code); | |
4214 | ||
4215 | /* Process depending on the code of this operation. If NEW is set | |
4216 | non-zero, it will be returned. */ | |
4217 | ||
4218 | switch (code) | |
4219 | { | |
4220 | case ASHIFT: | |
4221 | case LSHIFT: | |
4222 | /* Convert shifts by constants into multiplications if inside | |
4223 | an address. */ | |
4224 | if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4225 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT | |
4226 | && INTVAL (XEXP (x, 1)) >= 0) | |
4227 | new = gen_rtx_combine (MULT, mode, XEXP (x, 0), | |
4228 | gen_rtx (CONST_INT, VOIDmode, | |
4229 | 1 << INTVAL (XEXP (x, 1)))); | |
4230 | break; | |
4231 | ||
4232 | case AND: | |
4233 | /* If the second operand is not a constant, we can't do anything | |
4234 | with it. */ | |
4235 | if (GET_CODE (XEXP (x, 1)) != CONST_INT) | |
4236 | break; | |
4237 | ||
4238 | /* If the constant is a power of two minus one and the first operand | |
4239 | is a logical right shift, make an extraction. */ | |
4240 | if (GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
4241 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
4242 | new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1, | |
4243 | XEXP (XEXP (x, 0), 1), i, 1, | |
4244 | 0, in_code == COMPARE); | |
dfbe1b2f | 4245 | |
230d793d RS |
4246 | /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */ |
4247 | else if (GET_CODE (XEXP (x, 0)) == SUBREG | |
4248 | && subreg_lowpart_p (XEXP (x, 0)) | |
4249 | && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT | |
4250 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
4251 | new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), | |
4252 | XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1, | |
4253 | XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1, | |
4254 | 0, in_code == COMPARE); | |
230d793d | 4255 | |
a7c99304 RK |
4256 | |
4257 | /* If we are have (and (rotate X C) M) and C is larger than the number | |
4258 | of bits in M, this is an extraction. */ | |
4259 | ||
4260 | else if (GET_CODE (XEXP (x, 0)) == ROTATE | |
4261 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4262 | && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0 | |
4263 | && i <= INTVAL (XEXP (XEXP (x, 0), 1))) | |
4264 | new = make_extraction (mode, XEXP (XEXP (x, 0), 0), | |
4265 | (GET_MODE_BITSIZE (mode) | |
4266 | - INTVAL (XEXP (XEXP (x, 0), 1))), | |
4267 | 0, i, 1, 0, in_code == COMPARE); | |
4268 | ||
4269 | /* On machines without logical shifts, if the operand of the AND is | |
230d793d RS |
4270 | a logical shift and our mask turns off all the propagated sign |
4271 | bits, we can replace the logical shift with an arithmetic shift. */ | |
4272 | else if ( | |
4273 | #ifdef HAVE_ashrsi3 | |
4274 | HAVE_ashrsi3 | |
4275 | #else | |
4276 | 0 | |
4277 | #endif | |
4278 | #ifdef HAVE_lshrsi3 | |
4279 | && ! HAVE_lshrsi3 | |
4280 | #else | |
4281 | && 1 | |
4282 | #endif | |
4283 | && GET_CODE (XEXP (x, 0)) == LSHIFTRT | |
4284 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4285 | && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0 | |
4286 | && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_INT | |
4287 | && mode_width <= HOST_BITS_PER_INT) | |
4288 | { | |
4289 | unsigned mask = GET_MODE_MASK (mode); | |
4290 | ||
4291 | mask >>= INTVAL (XEXP (XEXP (x, 0), 1)); | |
4292 | if ((INTVAL (XEXP (x, 1)) & ~mask) == 0) | |
4293 | SUBST (XEXP (x, 0), | |
4294 | gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0), | |
4295 | XEXP (XEXP (x, 0), 1))); | |
4296 | } | |
4297 | ||
4298 | /* If the constant is one less than a power of two, this might be | |
4299 | representable by an extraction even if no shift is present. | |
4300 | If it doesn't end up being a ZERO_EXTEND, we will ignore it unless | |
4301 | we are in a COMPARE. */ | |
4302 | else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0) | |
4303 | new = make_extraction (mode, XEXP (x, 0), 0, 0, i, 1, | |
4304 | 0, in_code == COMPARE); | |
4305 | ||
4306 | /* If we are in a comparison and this is an AND with a power of two, | |
4307 | convert this into the appropriate bit extract. */ | |
4308 | else if (in_code == COMPARE | |
4309 | && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0) | |
4310 | new = make_extraction (mode, XEXP (x, 0), i, 0, 1, 1, 0, 1); | |
4311 | ||
4312 | break; | |
4313 | ||
4314 | case LSHIFTRT: | |
4315 | /* If the sign bit is known to be zero, replace this with an | |
4316 | arithmetic shift. */ | |
4317 | if ( | |
4318 | #ifdef HAVE_ashrsi3 | |
4319 | HAVE_ashrsi3 | |
4320 | #else | |
4321 | 0 | |
4322 | #endif | |
4323 | #ifdef HAVE_lshrsi3 | |
4324 | && ! HAVE_lshrsi3 | |
4325 | #else | |
4326 | && 1 | |
4327 | #endif | |
4328 | && mode_width <= HOST_BITS_PER_INT | |
4329 | && (significant_bits (XEXP (x, 0), mode) | |
4330 | & (1 << (mode_width - 1))) == 0) | |
4331 | { | |
4332 | new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1)); | |
4333 | break; | |
4334 | } | |
4335 | ||
4336 | /* ... fall through ... */ | |
4337 | ||
4338 | case ASHIFTRT: | |
4339 | /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1, | |
4340 | this is a SIGN_EXTRACT. */ | |
4341 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
4342 | && GET_CODE (XEXP (x, 0)) == ASHIFT | |
4343 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4344 | && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1))) | |
4345 | new = make_extraction (mode, XEXP (XEXP (x, 0), 0), | |
4346 | (INTVAL (XEXP (x, 1)) | |
4347 | - INTVAL (XEXP (XEXP (x, 0), 1))), | |
4348 | 0, mode_width - INTVAL (XEXP (x, 1)), | |
4349 | code == LSHIFTRT, 0, in_code == COMPARE); | |
4350 | break; | |
4351 | } | |
4352 | ||
4353 | if (new) | |
4354 | { | |
4355 | x = new; | |
4356 | code = GET_CODE (x); | |
4357 | } | |
4358 | ||
4359 | /* Now recursively process each operand of this operation. */ | |
4360 | fmt = GET_RTX_FORMAT (code); | |
4361 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
4362 | if (fmt[i] == 'e') | |
4363 | { | |
4364 | new = make_compound_operation (XEXP (x, i), next_code); | |
4365 | SUBST (XEXP (x, i), new); | |
4366 | } | |
4367 | ||
4368 | return x; | |
4369 | } | |
4370 | \f | |
4371 | /* Given M see if it is a value that would select a field of bits | |
4372 | within an item, but not the entire word. Return -1 if not. | |
4373 | Otherwise, return the starting position of the field, where 0 is the | |
4374 | low-order bit. | |
4375 | ||
4376 | *PLEN is set to the length of the field. */ | |
4377 | ||
4378 | static int | |
4379 | get_pos_from_mask (m, plen) | |
4380 | unsigned int m; | |
4381 | int *plen; | |
4382 | { | |
4383 | /* Get the bit number of the first 1 bit from the right, -1 if none. */ | |
4384 | int pos = exact_log2 (m & - m); | |
4385 | ||
4386 | if (pos < 0) | |
4387 | return -1; | |
4388 | ||
4389 | /* Now shift off the low-order zero bits and see if we have a power of | |
4390 | two minus 1. */ | |
4391 | *plen = exact_log2 ((m >> pos) + 1); | |
4392 | ||
4393 | if (*plen <= 0) | |
4394 | return -1; | |
4395 | ||
4396 | return pos; | |
4397 | } | |
4398 | \f | |
dfbe1b2f RK |
4399 | /* Rewrite X so that it is an expression in MODE. We only care about the |
4400 | low-order BITS bits so we can ignore AND operations that just clear | |
4401 | higher-order bits. | |
4402 | ||
4403 | Also, if REG is non-zero and X is a register equal in value to REG, | |
4404 | replace X with REG. */ | |
4405 | ||
4406 | static rtx | |
4407 | force_to_mode (x, mode, bits, reg) | |
4408 | rtx x; | |
4409 | enum machine_mode mode; | |
4410 | int bits; | |
4411 | rtx reg; | |
4412 | { | |
4413 | enum rtx_code code = GET_CODE (x); | |
4414 | ||
4415 | /* If X is narrower than MODE or if BITS is larger than the size of MODE, | |
4416 | just get X in the proper mode. */ | |
4417 | ||
4418 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode) | |
4419 | || bits > GET_MODE_BITSIZE (mode)) | |
4420 | return gen_lowpart_for_combine (mode, x); | |
4421 | ||
4422 | switch (code) | |
4423 | { | |
4424 | case SIGN_EXTEND: | |
4425 | case ZERO_EXTEND: | |
4426 | case ZERO_EXTRACT: | |
4427 | case SIGN_EXTRACT: | |
4428 | x = expand_compound_operation (x); | |
4429 | if (GET_CODE (x) != code) | |
4430 | return force_to_mode (x, mode, bits, reg); | |
4431 | break; | |
4432 | ||
4433 | case REG: | |
4434 | if (reg != 0 && (rtx_equal_p (get_last_value (reg), x) | |
4435 | || rtx_equal_p (reg, get_last_value (x)))) | |
4436 | x = reg; | |
4437 | break; | |
4438 | ||
4439 | case CONST_INT: | |
4440 | if (bits < HOST_BITS_PER_INT) | |
bec2e359 | 4441 | x = gen_rtx (CONST_INT, VOIDmode, INTVAL (x) & ((1 << bits) - 1)); |
dfbe1b2f RK |
4442 | return x; |
4443 | ||
4444 | case SUBREG: | |
4445 | /* Ignore low-order SUBREGs. */ | |
4446 | if (subreg_lowpart_p (x)) | |
4447 | return force_to_mode (SUBREG_REG (x), mode, bits, reg); | |
4448 | break; | |
4449 | ||
4450 | case AND: | |
4451 | /* If this is an AND with a constant. Otherwise, we fall through to | |
4452 | do the general binary case. */ | |
4453 | ||
4454 | if (GET_CODE (XEXP (x, 1)) == CONST_INT) | |
4455 | { | |
4456 | int mask = INTVAL (XEXP (x, 1)); | |
4457 | int len = exact_log2 (mask + 1); | |
4458 | rtx op = XEXP (x, 0); | |
4459 | ||
4460 | /* If this is masking some low-order bits, we may be able to | |
4461 | impose a stricter constraint on what bits of the operand are | |
4462 | required. */ | |
4463 | ||
4464 | op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits, | |
4465 | reg); | |
4466 | ||
4467 | if (bits < HOST_BITS_PER_INT) | |
bec2e359 | 4468 | mask &= (1 << bits) - 1; |
dfbe1b2f RK |
4469 | |
4470 | x = simplify_and_const_int (x, mode, op, mask); | |
4471 | ||
4472 | /* If X is still an AND, see if it is an AND with a mask that | |
4473 | is just some low-order bits. If so, and it is BITS wide (it | |
4474 | can't be wider), we don't need it. */ | |
4475 | ||
4476 | if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT | |
4477 | && bits < HOST_BITS_PER_INT | |
bec2e359 | 4478 | && INTVAL (XEXP (x, 1)) == (1 << bits) - 1) |
dfbe1b2f RK |
4479 | x = XEXP (x, 0); |
4480 | return x; | |
4481 | } | |
4482 | ||
4483 | /* ... fall through ... */ | |
4484 | ||
4485 | case PLUS: | |
4486 | case MINUS: | |
4487 | case MULT: | |
4488 | case IOR: | |
4489 | case XOR: | |
4490 | /* For most binary operations, just propagate into the operation and | |
4491 | change the mode. */ | |
4492 | ||
4493 | return gen_binary (code, mode, | |
4494 | force_to_mode (XEXP (x, 0), mode, bits, reg), | |
4495 | force_to_mode (XEXP (x, 1), mode, bits, reg)); | |
4496 | ||
4497 | case ASHIFT: | |
4498 | case LSHIFT: | |
4499 | /* For left shifts, do the same, but just for the first operand. | |
4500 | If the shift count is a constant, we need even fewer bits of the | |
4501 | first operand. */ | |
4502 | ||
4503 | if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits) | |
4504 | bits -= INTVAL (XEXP (x, 1)); | |
4505 | ||
4506 | return gen_binary (code, mode, | |
4507 | force_to_mode (XEXP (x, 0), mode, bits, reg), | |
4508 | XEXP (x, 1)); | |
4509 | ||
4510 | case LSHIFTRT: | |
4511 | /* Here we can only do something if the shift count is a constant and | |
4512 | the count plus BITS is no larger than the width of MODE, we can do | |
4513 | the shift in MODE. */ | |
4514 | ||
4515 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
4516 | && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode)) | |
4517 | return gen_binary (LSHIFTRT, mode, | |
4518 | force_to_mode (XEXP (x, 0), mode, | |
4519 | bits + INTVAL (XEXP (x, 1)), reg), | |
4520 | XEXP (x, 1)); | |
4521 | break; | |
4522 | ||
4523 | case NEG: | |
4524 | case NOT: | |
4525 | /* Handle these similarly to the way we handle most binary operations. */ | |
4526 | return gen_unary (code, mode, | |
4527 | force_to_mode (XEXP (x, 0), mode, bits, reg)); | |
4528 | } | |
4529 | ||
4530 | /* Otherwise, just do the operation canonically. */ | |
4531 | return gen_lowpart_for_combine (mode, x); | |
4532 | } | |
4533 | \f | |
230d793d RS |
4534 | /* See if X, a SET operation, can be rewritten as a bit-field assignment. |
4535 | Return that assignment if so. | |
4536 | ||
4537 | We only handle the most common cases. */ | |
4538 | ||
4539 | static rtx | |
4540 | make_field_assignment (x) | |
4541 | rtx x; | |
4542 | { | |
4543 | rtx dest = SET_DEST (x); | |
4544 | rtx src = SET_SRC (x); | |
dfbe1b2f RK |
4545 | rtx ourdest; |
4546 | rtx assign; | |
4547 | int c1, pos, len; | |
4548 | rtx other; | |
4549 | enum machine_mode mode; | |
230d793d RS |
4550 | |
4551 | /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is | |
4552 | a clear of a one-bit field. We will have changed it to | |
4553 | (and (rotate (const_int -2) POS) DEST), so check for that. Also check | |
4554 | for a SUBREG. */ | |
4555 | ||
4556 | if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE | |
4557 | && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT | |
4558 | && INTVAL (XEXP (XEXP (src, 0), 0)) == -2 | |
dfbe1b2f RK |
4559 | && (rtx_equal_p (dest, XEXP (src, 1)) |
4560 | || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) | |
4561 | || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) | |
230d793d RS |
4562 | { |
4563 | assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1), | |
4564 | 1, 1, 1, 0); | |
dfbe1b2f | 4565 | return gen_rtx (SET, VOIDmode, assign, const0_rtx); |
230d793d RS |
4566 | } |
4567 | ||
4568 | else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG | |
4569 | && subreg_lowpart_p (XEXP (src, 0)) | |
4570 | && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0))) | |
4571 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0))))) | |
4572 | && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE | |
4573 | && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2 | |
dfbe1b2f RK |
4574 | && (rtx_equal_p (dest, XEXP (src, 1)) |
4575 | || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) | |
4576 | || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) | |
230d793d RS |
4577 | { |
4578 | assign = make_extraction (VOIDmode, dest, -1, | |
4579 | XEXP (SUBREG_REG (XEXP (src, 0)), 1), | |
4580 | 1, 1, 1, 0); | |
dfbe1b2f | 4581 | return gen_rtx (SET, VOIDmode, assign, const0_rtx); |
230d793d RS |
4582 | } |
4583 | ||
4584 | /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a | |
4585 | one-bit field. */ | |
4586 | else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT | |
4587 | && XEXP (XEXP (src, 0), 0) == const1_rtx | |
dfbe1b2f RK |
4588 | && (rtx_equal_p (dest, XEXP (src, 1)) |
4589 | || rtx_equal_p (dest, get_last_value (XEXP (src, 1))) | |
4590 | || rtx_equal_p (get_last_value (dest), XEXP (src, 1)))) | |
230d793d RS |
4591 | { |
4592 | assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1), | |
4593 | 1, 1, 1, 0); | |
dfbe1b2f | 4594 | return gen_rtx (SET, VOIDmode, assign, const1_rtx); |
230d793d RS |
4595 | } |
4596 | ||
dfbe1b2f RK |
4597 | /* The other case we handle is assignments into a constant-position |
4598 | field. They look like (ior (and DEST C1) OTHER). If C1 represents | |
4599 | a mask that has all one bits except for a group of zero bits and | |
4600 | OTHER is known to have zeros where C1 has ones, this is such an | |
4601 | assignment. Compute the position and length from C1. Shift OTHER | |
4602 | to the appropriate position, force it to the required mode, and | |
4603 | make the extraction. Check for the AND in both operands. */ | |
4604 | ||
4605 | if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND | |
4606 | && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT | |
4607 | && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest) | |
4608 | || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest)) | |
4609 | || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest))) | |
4610 | c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1); | |
4611 | else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND | |
4612 | && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT | |
4613 | && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest) | |
4614 | || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest)) | |
4615 | || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)), | |
4616 | dest))) | |
4617 | c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0); | |
4618 | else | |
4619 | return x; | |
230d793d | 4620 | |
dfbe1b2f RK |
4621 | pos = get_pos_from_mask (~c1, &len); |
4622 | if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest)) | |
4623 | || (c1 & significant_bits (other, GET_MODE (other))) != 0) | |
4624 | return x; | |
230d793d | 4625 | |
dfbe1b2f | 4626 | assign = make_extraction (VOIDmode, dest, pos, 0, len, 1, 1, 0); |
230d793d | 4627 | |
dfbe1b2f RK |
4628 | /* The mode to use for the source is the mode of the assignment, or of |
4629 | what is inside a possible STRICT_LOW_PART. */ | |
4630 | mode = (GET_CODE (assign) == STRICT_LOW_PART | |
4631 | ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign)); | |
230d793d | 4632 | |
dfbe1b2f RK |
4633 | /* Shift OTHER right POS places and make it the source, restricting it |
4634 | to the proper length and mode. */ | |
230d793d | 4635 | |
5089e22e RS |
4636 | src = force_to_mode (simplify_shift_const (0, LSHIFTRT, GET_MODE (src), |
4637 | other, pos), | |
dfbe1b2f | 4638 | mode, len, dest); |
230d793d | 4639 | |
dfbe1b2f | 4640 | return gen_rtx_combine (SET, VOIDmode, assign, src); |
230d793d RS |
4641 | } |
4642 | \f | |
4643 | /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c) | |
4644 | if so. */ | |
4645 | ||
4646 | static rtx | |
4647 | apply_distributive_law (x) | |
4648 | rtx x; | |
4649 | { | |
4650 | enum rtx_code code = GET_CODE (x); | |
4651 | rtx lhs, rhs, other; | |
4652 | rtx tem; | |
4653 | enum rtx_code inner_code; | |
4654 | ||
4655 | /* The outer operation can only be one of the following: */ | |
4656 | if (code != IOR && code != AND && code != XOR | |
4657 | && code != PLUS && code != MINUS) | |
4658 | return x; | |
4659 | ||
4660 | lhs = XEXP (x, 0), rhs = XEXP (x, 1); | |
4661 | ||
dfbe1b2f | 4662 | /* If either operand is a primitive we can't do anything, so get out fast. */ |
230d793d | 4663 | if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o' |
dfbe1b2f | 4664 | || GET_RTX_CLASS (GET_CODE (rhs)) == 'o') |
230d793d RS |
4665 | return x; |
4666 | ||
4667 | lhs = expand_compound_operation (lhs); | |
4668 | rhs = expand_compound_operation (rhs); | |
4669 | inner_code = GET_CODE (lhs); | |
4670 | if (inner_code != GET_CODE (rhs)) | |
4671 | return x; | |
4672 | ||
4673 | /* See if the inner and outer operations distribute. */ | |
4674 | switch (inner_code) | |
4675 | { | |
4676 | case LSHIFTRT: | |
4677 | case ASHIFTRT: | |
4678 | case AND: | |
4679 | case IOR: | |
4680 | /* These all distribute except over PLUS. */ | |
4681 | if (code == PLUS || code == MINUS) | |
4682 | return x; | |
4683 | break; | |
4684 | ||
4685 | case MULT: | |
4686 | if (code != PLUS && code != MINUS) | |
4687 | return x; | |
4688 | break; | |
4689 | ||
4690 | case ASHIFT: | |
4691 | case LSHIFT: | |
4692 | /* These are also multiplies, so they distribute over everything. */ | |
4693 | break; | |
4694 | ||
4695 | case SUBREG: | |
dfbe1b2f RK |
4696 | /* Non-paradoxical SUBREGs distributes over all operations, provided |
4697 | the inner modes and word numbers are the same, this is an extraction | |
2b4bd1bc JW |
4698 | of a low-order part, we don't convert an fp operation to int or |
4699 | vice versa, and we would not be converting a single-word | |
dfbe1b2f | 4700 | operation into a multi-word operation. The latter test is not |
2b4bd1bc | 4701 | required, but it prevents generating unneeded multi-word operations. |
dfbe1b2f RK |
4702 | Some of the previous tests are redundant given the latter test, but |
4703 | are retained because they are required for correctness. | |
4704 | ||
4705 | We produce the result slightly differently in this case. */ | |
4706 | ||
4707 | if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs)) | |
4708 | || SUBREG_WORD (lhs) != SUBREG_WORD (rhs) | |
4709 | || ! subreg_lowpart_p (lhs) | |
2b4bd1bc JW |
4710 | || (GET_MODE_CLASS (GET_MODE (lhs)) |
4711 | != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs)))) | |
dfbe1b2f RK |
4712 | || (GET_MODE_SIZE (GET_MODE (lhs)) |
4713 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs)))) | |
4714 | || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD) | |
230d793d RS |
4715 | return x; |
4716 | ||
4717 | tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)), | |
4718 | SUBREG_REG (lhs), SUBREG_REG (rhs)); | |
4719 | return gen_lowpart_for_combine (GET_MODE (x), tem); | |
4720 | ||
4721 | default: | |
4722 | return x; | |
4723 | } | |
4724 | ||
4725 | /* Set LHS and RHS to the inner operands (A and B in the example | |
4726 | above) and set OTHER to the common operand (C in the example). | |
4727 | These is only one way to do this unless the inner operation is | |
4728 | commutative. */ | |
4729 | if (GET_RTX_CLASS (inner_code) == 'c' | |
4730 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0))) | |
4731 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1); | |
4732 | else if (GET_RTX_CLASS (inner_code) == 'c' | |
4733 | && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1))) | |
4734 | other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0); | |
4735 | else if (GET_RTX_CLASS (inner_code) == 'c' | |
4736 | && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0))) | |
4737 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1); | |
4738 | else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1))) | |
4739 | other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0); | |
4740 | else | |
4741 | return x; | |
4742 | ||
4743 | /* Form the new inner operation, seeing if it simplifies first. */ | |
4744 | tem = gen_binary (code, GET_MODE (x), lhs, rhs); | |
4745 | ||
4746 | /* There is one exception to the general way of distributing: | |
4747 | (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */ | |
4748 | if (code == XOR && inner_code == IOR) | |
4749 | { | |
4750 | inner_code = AND; | |
4751 | other = gen_unary (NOT, GET_MODE (x), other); | |
4752 | } | |
4753 | ||
4754 | /* We may be able to continuing distributing the result, so call | |
4755 | ourselves recursively on the inner operation before forming the | |
4756 | outer operation, which we return. */ | |
4757 | return gen_binary (inner_code, GET_MODE (x), | |
4758 | apply_distributive_law (tem), other); | |
4759 | } | |
4760 | \f | |
4761 | /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done | |
4762 | in MODE. | |
4763 | ||
4764 | Return an equivalent form, if different from X. Otherwise, return X. If | |
4765 | X is zero, we are to always construct the equivalent form. */ | |
4766 | ||
4767 | static rtx | |
4768 | simplify_and_const_int (x, mode, varop, constop) | |
4769 | rtx x; | |
4770 | enum machine_mode mode; | |
4771 | rtx varop; | |
4772 | unsigned constop; | |
4773 | { | |
4774 | register enum machine_mode tmode; | |
4775 | register rtx temp; | |
4776 | unsigned significant; | |
4777 | ||
4778 | /* There is a large class of optimizations based on the principle that | |
4779 | some operations produce results where certain bits are known to be zero, | |
4780 | and hence are not significant to the AND. For example, if we have just | |
4781 | done a left shift of one bit, the low-order bit is known to be zero and | |
4782 | hence an AND with a mask of ~1 would not do anything. | |
4783 | ||
4784 | At the end of the following loop, we set: | |
4785 | ||
4786 | VAROP to be the item to be AND'ed with; | |
4787 | CONSTOP to the constant value to AND it with. */ | |
4788 | ||
4789 | while (1) | |
4790 | { | |
4791 | /* If we ever encounter a mode wider than the host machine's word | |
4792 | size, we can't compute the masks accurately, so give up. */ | |
4793 | if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_INT) | |
4794 | break; | |
4795 | ||
4796 | /* Unless one of the cases below does a `continue', | |
4797 | a `break' will be executed to exit the loop. */ | |
4798 | ||
4799 | switch (GET_CODE (varop)) | |
4800 | { | |
4801 | case CLOBBER: | |
4802 | /* If VAROP is a (clobber (const_int)), return it since we know | |
4803 | we are generating something that won't match. */ | |
4804 | return varop; | |
4805 | ||
4806 | #if ! BITS_BIG_ENDIAN | |
4807 | case USE: | |
4808 | /* VAROP is a (use (mem ..)) that was made from a bit-field | |
4809 | extraction that spanned the boundary of the MEM. If we are | |
4810 | now masking so it is within that boundary, we don't need the | |
4811 | USE any more. */ | |
4812 | if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0) | |
4813 | { | |
4814 | varop = XEXP (varop, 0); | |
4815 | continue; | |
4816 | } | |
4817 | break; | |
4818 | #endif | |
4819 | ||
4820 | case SUBREG: | |
4821 | if (subreg_lowpart_p (varop) | |
4822 | /* We can ignore the effect this SUBREG if it narrows the mode | |
4823 | or, on machines where byte operations zero extend, if the | |
4824 | constant masks to zero all the bits the mode doesn't have. */ | |
4825 | && ((GET_MODE_SIZE (GET_MODE (varop)) | |
4826 | < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))) | |
4827 | #ifdef BYTE_LOADS_ZERO_EXTEND | |
4828 | || (0 == (constop | |
4829 | & GET_MODE_MASK (GET_MODE (varop)) | |
4830 | & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop))))) | |
4831 | #endif | |
4832 | )) | |
4833 | { | |
4834 | varop = SUBREG_REG (varop); | |
4835 | continue; | |
4836 | } | |
4837 | break; | |
4838 | ||
4839 | case ZERO_EXTRACT: | |
4840 | case SIGN_EXTRACT: | |
4841 | case ZERO_EXTEND: | |
4842 | case SIGN_EXTEND: | |
4843 | /* Try to expand these into a series of shifts and then work | |
4844 | with that result. If we can't, for example, if the extract | |
4845 | isn't at a fixed position, give up. */ | |
4846 | temp = expand_compound_operation (varop); | |
4847 | if (temp != varop) | |
4848 | { | |
4849 | varop = temp; | |
4850 | continue; | |
4851 | } | |
4852 | break; | |
4853 | ||
4854 | case AND: | |
4855 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT) | |
4856 | { | |
4857 | constop &= INTVAL (XEXP (varop, 1)); | |
4858 | varop = XEXP (varop, 0); | |
4859 | continue; | |
4860 | } | |
4861 | break; | |
4862 | ||
4863 | case IOR: | |
4864 | case XOR: | |
4865 | /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and | |
4866 | LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...) | |
4867 | operation which may be a bitfield extraction. */ | |
4868 | ||
4869 | if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
4870 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
4871 | && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0 | |
4872 | && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT | |
4873 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
4874 | && (INTVAL (XEXP (varop, 1)) | |
4875 | & ~ significant_bits (XEXP (varop, 0), | |
4876 | GET_MODE (varop)) == 0)) | |
4877 | { | |
4878 | temp = gen_rtx (CONST_INT, VOIDmode, | |
4879 | ((INTVAL (XEXP (varop, 1)) & constop) | |
4880 | << INTVAL (XEXP (XEXP (varop, 0), 1)))); | |
4881 | temp = gen_binary (GET_CODE (varop), GET_MODE (varop), | |
4882 | XEXP (XEXP (varop, 0), 0), temp); | |
4883 | varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), | |
4884 | temp, XEXP (varop, 1)); | |
4885 | continue; | |
4886 | } | |
4887 | ||
4888 | /* Apply the AND to both branches of the IOR or XOR, then try to | |
4889 | apply the distributive law. This may eliminate operations | |
4890 | if either branch can be simplified because of the AND. | |
4891 | It may also make some cases more complex, but those cases | |
4892 | probably won't match a pattern either with or without this. */ | |
4893 | return | |
4894 | gen_lowpart_for_combine | |
4895 | (mode, apply_distributive_law | |
4896 | (gen_rtx_combine | |
4897 | (GET_CODE (varop), GET_MODE (varop), | |
4898 | simplify_and_const_int (0, GET_MODE (varop), | |
4899 | XEXP (varop, 0), constop), | |
4900 | simplify_and_const_int (0, GET_MODE (varop), | |
4901 | XEXP (varop, 1), constop)))); | |
4902 | ||
4903 | case NOT: | |
4904 | /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an | |
4905 | LSHIFTRT we can do the same as above. */ | |
4906 | ||
4907 | if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT | |
4908 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
4909 | && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0 | |
4910 | && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT) | |
4911 | { | |
4912 | temp = gen_rtx (CONST_INT, VOIDmode, | |
4913 | constop << INTVAL (XEXP (XEXP (varop, 0), 1))); | |
4914 | temp = gen_binary (XOR, GET_MODE (varop), | |
4915 | XEXP (XEXP (varop, 0), 0), temp); | |
4916 | varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), | |
4917 | temp, XEXP (XEXP (varop, 0), 1)); | |
4918 | continue; | |
4919 | } | |
4920 | break; | |
4921 | ||
4922 | case ASHIFTRT: | |
4923 | /* If we are just looking for the sign bit, we don't need this | |
4924 | shift at all, even if it has a variable count. */ | |
4925 | if (constop == 1 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)) | |
4926 | { | |
4927 | varop = XEXP (varop, 0); | |
4928 | continue; | |
4929 | } | |
4930 | ||
4931 | /* If this is a shift by a constant, get a mask that contains | |
4932 | those bits that are not copies of the sign bit. We then have | |
4933 | two cases: If CONSTOP only includes those bits, this can be | |
4934 | a logical shift, which may allow simplifications. If CONSTOP | |
4935 | is a single-bit field not within those bits, we are requesting | |
4936 | a copy of the sign bit and hence can shift the sign bit to | |
4937 | the appropriate location. */ | |
4938 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
4939 | && INTVAL (XEXP (varop, 1)) >= 0 | |
4940 | && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_INT) | |
4941 | { | |
4942 | int i = -1; | |
4943 | ||
4944 | significant = GET_MODE_MASK (GET_MODE (varop)); | |
4945 | significant >>= INTVAL (XEXP (varop, 1)); | |
4946 | ||
4947 | if ((constop & ~significant) == 0 | |
4948 | || (i = exact_log2 (constop)) >= 0) | |
4949 | { | |
4950 | varop = simplify_shift_const | |
4951 | (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), | |
4952 | i < 0 ? INTVAL (XEXP (varop, 1)) | |
4953 | : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i); | |
4954 | if (GET_CODE (varop) != ASHIFTRT) | |
4955 | continue; | |
4956 | } | |
4957 | } | |
4958 | ||
4959 | /* If our mask is 1, convert this to a LSHIFTRT. This can be done | |
4960 | even if the shift count isn't a constant. */ | |
4961 | if (constop == 1) | |
4962 | varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), | |
4963 | XEXP (varop, 0), XEXP (varop, 1)); | |
4964 | break; | |
4965 | ||
4966 | case NE: | |
4967 | /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is | |
4968 | included in STORE_FLAG_VALUE and FOO has no significant bits | |
4969 | not in CONST. */ | |
4970 | if ((constop & ~ STORE_FLAG_VALUE) == 0 | |
4971 | && XEXP (varop, 0) == const0_rtx | |
4972 | && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0) | |
4973 | { | |
4974 | varop = XEXP (varop, 0); | |
4975 | continue; | |
4976 | } | |
4977 | break; | |
4978 | ||
4979 | case PLUS: | |
4980 | /* In (and (plus FOO C1) M), if M is a mask that just turns off | |
4981 | low-order bits (as in an alignment operation) and FOO is already | |
4982 | aligned to that boundary, we can convert remove this AND | |
4983 | and possibly the PLUS if it is now adding zero. */ | |
4984 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
4985 | && exact_log2 (-constop) >= 0 | |
4986 | && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0) | |
4987 | { | |
4988 | varop = plus_constant (XEXP (varop, 0), | |
4989 | INTVAL (XEXP (varop, 1)) & constop); | |
4990 | constop = ~0; | |
4991 | break; | |
4992 | } | |
4993 | ||
4994 | /* ... fall through ... */ | |
4995 | ||
4996 | case MINUS: | |
4997 | /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one | |
4998 | less than powers of two and M2 is narrower than M1, we can | |
4999 | eliminate the inner AND. This occurs when incrementing | |
5000 | bit fields. */ | |
5001 | ||
5002 | if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT | |
5003 | || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND) | |
5004 | SUBST (XEXP (varop, 0), | |
5005 | expand_compound_operation (XEXP (varop, 0))); | |
5006 | ||
5007 | if (GET_CODE (XEXP (varop, 0)) == AND | |
5008 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
5009 | && exact_log2 (constop + 1) >= 0 | |
5010 | && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0 | |
5011 | && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0) | |
5012 | SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0)); | |
5013 | break; | |
5014 | } | |
5015 | ||
5016 | break; | |
5017 | } | |
5018 | ||
5019 | /* If we have reached a constant, this whole thing is constant. */ | |
5020 | if (GET_CODE (varop) == CONST_INT) | |
5021 | return gen_rtx (CONST_INT, VOIDmode, constop & INTVAL (varop)); | |
5022 | ||
5023 | /* See what bits are significant in VAROP. */ | |
5024 | significant = significant_bits (varop, mode); | |
5025 | ||
5026 | /* Turn off all bits in the constant that are known to already be zero. | |
5027 | Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT | |
5028 | which is tested below. */ | |
5029 | ||
5030 | constop &= significant; | |
5031 | ||
5032 | /* If we don't have any bits left, return zero. */ | |
5033 | if (constop == 0) | |
5034 | return const0_rtx; | |
5035 | ||
5036 | /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG | |
5037 | if we already had one (just check for the simplest cases). */ | |
5038 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
5039 | && GET_MODE (XEXP (x, 0)) == mode | |
5040 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
5041 | varop = XEXP (x, 0); | |
5042 | else | |
5043 | varop = gen_lowpart_for_combine (mode, varop); | |
5044 | ||
5045 | /* If we can't make the SUBREG, try to return what we were given. */ | |
5046 | if (GET_CODE (varop) == CLOBBER) | |
5047 | return x ? x : varop; | |
5048 | ||
5049 | /* If we are only masking insignificant bits, return VAROP. */ | |
5050 | if (constop == significant) | |
5051 | x = varop; | |
5052 | ||
5053 | /* Otherwise, return an AND. See how much, if any, of X we can use. */ | |
5054 | else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode) | |
5055 | x = gen_rtx_combine (AND, mode, varop, | |
5056 | gen_rtx (CONST_INT, VOIDmode, constop)); | |
5057 | ||
5058 | else | |
5059 | { | |
5060 | if (GET_CODE (XEXP (x, 1)) != CONST_INT | |
5061 | || INTVAL (XEXP (x, 1)) != constop) | |
5062 | SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, constop)); | |
5063 | ||
5064 | SUBST (XEXP (x, 0), varop); | |
5065 | } | |
5066 | ||
5067 | return x; | |
5068 | } | |
5069 | \f | |
5070 | /* Given an expression, X, compute which bits in X can be non-zero. | |
5071 | We don't care about bits outside of those defined in MODE. | |
5072 | ||
5073 | For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is | |
5074 | a shift, AND, or zero_extract, we can do better. */ | |
5075 | ||
5076 | static unsigned | |
5077 | significant_bits (x, mode) | |
5078 | rtx x; | |
5079 | enum machine_mode mode; | |
5080 | { | |
5081 | unsigned significant = GET_MODE_MASK (mode); | |
5082 | unsigned inner_sig; | |
5083 | enum rtx_code code; | |
5084 | int mode_width = GET_MODE_BITSIZE (mode); | |
5085 | rtx tem; | |
5086 | ||
5087 | /* If X is wider than MODE, use its mode instead. */ | |
5088 | if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width) | |
5089 | { | |
5090 | mode = GET_MODE (x); | |
5091 | significant = GET_MODE_MASK (mode); | |
5092 | mode_width = GET_MODE_BITSIZE (mode); | |
5093 | } | |
5094 | ||
5095 | if (mode_width > HOST_BITS_PER_INT) | |
5096 | /* Our only callers in this case look for single bit values. So | |
5097 | just return the mode mask. Those tests will then be false. */ | |
5098 | return significant; | |
5099 | ||
5100 | code = GET_CODE (x); | |
5101 | switch (code) | |
5102 | { | |
5103 | case REG: | |
5104 | #ifdef STACK_BOUNDARY | |
5105 | /* If this is the stack pointer, we may know something about its | |
5106 | alignment. If PUSH_ROUNDING is defined, it is possible for the | |
5107 | stack to be momentarily aligned only to that amount, so we pick | |
5108 | the least alignment. */ | |
5109 | ||
5110 | if (x == stack_pointer_rtx) | |
5111 | { | |
5112 | int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT; | |
5113 | ||
5114 | #ifdef PUSH_ROUNDING | |
5115 | sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment); | |
5116 | #endif | |
5117 | ||
5118 | return significant & ~ (sp_alignment - 1); | |
5119 | } | |
5120 | #endif | |
5121 | ||
5122 | /* If X is a register whose value we can find, use that value. | |
5123 | Otherwise, use the previously-computed significant bits for this | |
5124 | register. */ | |
5125 | ||
5126 | tem = get_last_value (x); | |
5127 | if (tem) | |
5128 | return significant_bits (tem, mode); | |
5129 | else if (significant_valid && reg_significant[REGNO (x)]) | |
5130 | return reg_significant[REGNO (x)] & significant; | |
5131 | else | |
5132 | return significant; | |
5133 | ||
5134 | case CONST_INT: | |
5135 | return INTVAL (x); | |
5136 | ||
5137 | #ifdef BYTE_LOADS_ZERO_EXTEND | |
5138 | case MEM: | |
5139 | /* In many, if not most, RISC machines, reading a byte from memory | |
5140 | zeros the rest of the register. Noticing that fact saves a lot | |
5141 | of extra zero-extends. */ | |
5142 | significant &= GET_MODE_MASK (GET_MODE (x)); | |
5143 | break; | |
5144 | #endif | |
5145 | ||
5146 | #if STORE_FLAG_VALUE == 1 | |
5147 | case EQ: case NE: | |
5148 | case GT: case GTU: | |
5149 | case LT: case LTU: | |
5150 | case GE: case GEU: | |
5151 | case LE: case LEU: | |
3f508eca RK |
5152 | |
5153 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5154 | significant = 1; | |
230d793d RS |
5155 | |
5156 | /* A comparison operation only sets the bits given by its mode. The | |
5157 | rest are set undefined. */ | |
5158 | if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) | |
5159 | significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); | |
5160 | break; | |
5161 | #endif | |
5162 | ||
5163 | #if STORE_FLAG_VALUE == -1 | |
5164 | case NEG: | |
5165 | if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' | |
5166 | || ((tem = get_last_value (XEXP (x, 0))) != 0 | |
5167 | && GET_RTX_CLASS (GET_CODE (tem)) == '<')) | |
5168 | significant = 1; | |
5169 | ||
5170 | if (GET_MODE_SIZE (GET_MODE (x)) < mode_width) | |
5171 | significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x))); | |
5172 | break; | |
5173 | #endif | |
5174 | ||
5175 | case TRUNCATE: | |
5176 | significant &= (significant_bits (XEXP (x, 0), mode) | |
5177 | & GET_MODE_MASK (mode)); | |
5178 | break; | |
5179 | ||
5180 | case ZERO_EXTEND: | |
5181 | significant &= significant_bits (XEXP (x, 0), mode); | |
5182 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) | |
5183 | significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); | |
5184 | break; | |
5185 | ||
5186 | case SIGN_EXTEND: | |
5187 | /* If the sign bit is known clear, this is the same as ZERO_EXTEND. | |
5188 | Otherwise, show all the bits in the outer mode but not the inner | |
5189 | may be non-zero. */ | |
5190 | inner_sig = significant_bits (XEXP (x, 0), mode); | |
5191 | if (GET_MODE (XEXP (x, 0)) != VOIDmode) | |
5192 | { | |
5193 | inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); | |
5194 | if (inner_sig & | |
5195 | (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))) | |
5196 | inner_sig |= (GET_MODE_MASK (mode) | |
5197 | & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); | |
5198 | } | |
5199 | ||
5200 | significant &= inner_sig; | |
5201 | break; | |
5202 | ||
5203 | case AND: | |
5204 | significant &= (significant_bits (XEXP (x, 0), mode) | |
5205 | & significant_bits (XEXP (x, 1), mode)); | |
5206 | break; | |
5207 | ||
5208 | case XOR: | |
5209 | case IOR: | |
5210 | significant &= (significant_bits (XEXP (x, 0), mode) | |
5211 | | significant_bits (XEXP (x, 1), mode)); | |
5212 | break; | |
5213 | ||
5214 | case PLUS: case MINUS: | |
5215 | case MULT: | |
5216 | case DIV: case UDIV: | |
5217 | case MOD: case UMOD: | |
5218 | /* We can apply the rules of arithmetic to compute the number of | |
5219 | high- and low-order zero bits of these operations. We start by | |
5220 | computing the width (position of the highest-order non-zero bit) | |
5221 | and the number of low-order zero bits for each value. */ | |
5222 | { | |
5223 | unsigned sig0 = significant_bits (XEXP (x, 0), mode); | |
5224 | unsigned sig1 = significant_bits (XEXP (x, 1), mode); | |
5225 | int width0 = floor_log2 (sig0) + 1; | |
5226 | int width1 = floor_log2 (sig1) + 1; | |
5227 | int low0 = floor_log2 (sig0 & -sig0); | |
5228 | int low1 = floor_log2 (sig1 & -sig1); | |
5229 | int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1))); | |
5230 | int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1))); | |
5231 | int result_width = mode_width; | |
5232 | int result_low = 0; | |
5233 | ||
5234 | switch (code) | |
5235 | { | |
5236 | case PLUS: | |
5237 | result_width = MAX (width0, width1) + 1; | |
5238 | result_low = MIN (low0, low1); | |
5239 | break; | |
5240 | case MINUS: | |
5241 | result_low = MIN (low0, low1); | |
5242 | break; | |
5243 | case MULT: | |
5244 | result_width = width0 + width1; | |
5245 | result_low = low0 + low1; | |
5246 | break; | |
5247 | case DIV: | |
5248 | if (! op0_maybe_minusp && ! op1_maybe_minusp) | |
5249 | result_width = width0; | |
5250 | break; | |
5251 | case UDIV: | |
5252 | result_width = width0; | |
5253 | break; | |
5254 | case MOD: | |
5255 | if (! op0_maybe_minusp && ! op1_maybe_minusp) | |
5256 | result_width = MIN (width0, width1); | |
5257 | result_low = MIN (low0, low1); | |
5258 | break; | |
5259 | case UMOD: | |
5260 | result_width = MIN (width0, width1); | |
5261 | result_low = MIN (low0, low1); | |
5262 | break; | |
5263 | } | |
5264 | ||
5265 | if (result_width < mode_width) | |
5266 | significant &= (1 << result_width) - 1; | |
5267 | ||
5268 | if (result_low > 0) | |
5269 | significant &= ~ ((1 << result_low) - 1); | |
5270 | } | |
5271 | break; | |
5272 | ||
5273 | case ZERO_EXTRACT: | |
5274 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5275 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT) | |
5276 | significant &= (1 << INTVAL (XEXP (x, 1))) - 1; | |
5277 | break; | |
5278 | ||
5279 | case SUBREG: | |
5280 | /* If the inner mode is a single word for both the host and target | |
5281 | machines, we can compute this from which bits of the inner | |
5282 | object are known significant. */ | |
5283 | if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD | |
5284 | && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT) | |
5285 | { | |
5286 | significant &= significant_bits (SUBREG_REG (x), mode); | |
5287 | #ifndef BYTE_LOADS_ZERO_EXTEND | |
5288 | /* On many CISC machines, accessing an object in a wider mode | |
5289 | causes the high-order bits to become undefined. So they are | |
5290 | not known to be zero. */ | |
5291 | if (GET_MODE_SIZE (GET_MODE (x)) | |
5292 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
5293 | significant |= (GET_MODE_MASK (GET_MODE (x)) | |
5294 | & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))); | |
5295 | #endif | |
5296 | } | |
5297 | break; | |
5298 | ||
5299 | case ASHIFTRT: | |
5300 | case LSHIFTRT: | |
5301 | case ASHIFT: | |
5302 | case LSHIFT: | |
5303 | case ROTATE: | |
5304 | /* The significant bits are in two classes: any bits within MODE | |
5305 | that aren't in GET_MODE (x) are always significant. The rest of the | |
5306 | significant bits are those that are significant in the operand of | |
5307 | the shift when shifted the appropriate number of bits. This | |
5308 | shows that high-order bits are cleared by the right shift and | |
5309 | low-order bits by left shifts. */ | |
5310 | if (GET_CODE (XEXP (x, 1)) == CONST_INT | |
5311 | && INTVAL (XEXP (x, 1)) >= 0 | |
5312 | && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT) | |
5313 | { | |
5314 | enum machine_mode inner_mode = GET_MODE (x); | |
5315 | int width = GET_MODE_BITSIZE (inner_mode); | |
5316 | int count = INTVAL (XEXP (x, 1)); | |
5317 | unsigned mode_mask = GET_MODE_MASK (inner_mode); | |
5318 | unsigned op_significant = significant_bits (XEXP (x, 0), mode); | |
5319 | unsigned inner = op_significant & mode_mask; | |
5320 | unsigned outer = 0; | |
5321 | ||
5322 | if (mode_width > width) | |
5323 | outer = (op_significant & significant & ~ mode_mask); | |
5324 | ||
5325 | if (code == LSHIFTRT) | |
5326 | inner >>= count; | |
5327 | else if (code == ASHIFTRT) | |
5328 | { | |
5329 | inner >>= count; | |
5330 | ||
5331 | /* If the sign bit was significant at before the shift, we | |
5332 | need to mark all the places it could have been copied to | |
5333 | by the shift significant. */ | |
5334 | if (inner & (1 << (width - 1 - count))) | |
5335 | inner |= ((1 << count) - 1) << (width - count); | |
5336 | } | |
5337 | else if (code == LSHIFT || code == ASHIFT) | |
5338 | inner <<= count; | |
5339 | else | |
5340 | inner = ((inner << (count % width) | |
5341 | | (inner >> (width - (count % width)))) & mode_mask); | |
5342 | ||
5343 | significant &= (outer | inner); | |
5344 | } | |
5345 | break; | |
5346 | ||
5347 | case FFS: | |
5348 | /* This is at most the number of bits in the mode. */ | |
5349 | significant = (1 << (floor_log2 (mode_width) + 1)) - 1; | |
5350 | break; | |
5351 | } | |
5352 | ||
5353 | return significant; | |
5354 | } | |
5355 | \f | |
5356 | /* This function is called from `simplify_shift_const' to merge two | |
5357 | outer operations. Specifically, we have already found that we need | |
5358 | to perform operation *POP0 with constant *PCONST0 at the outermost | |
5359 | position. We would now like to also perform OP1 with constant CONST1 | |
5360 | (with *POP0 being done last). | |
5361 | ||
5362 | Return 1 if we can do the operation and update *POP0 and *PCONST0 with | |
5363 | the resulting operation. *PCOMP_P is set to 1 if we would need to | |
5364 | complement the innermost operand, otherwise it is unchanged. | |
5365 | ||
5366 | MODE is the mode in which the operation will be done. No bits outside | |
5367 | the width of this mode matter. It is assumed that the width of this mode | |
5368 | is smaller than or equal to HOST_BITS_PER_INT. | |
5369 | ||
5370 | If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS, | |
5371 | IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper | |
5372 | result is simply *PCONST0. | |
5373 | ||
5374 | If the resulting operation cannot be expressed as one operation, we | |
5375 | return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */ | |
5376 | ||
5377 | static int | |
5378 | merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p) | |
5379 | enum rtx_code *pop0; | |
5380 | int *pconst0; | |
5381 | enum rtx_code op1; | |
5382 | int const1; | |
5383 | enum machine_mode mode; | |
5384 | int *pcomp_p; | |
5385 | { | |
5386 | enum rtx_code op0 = *pop0; | |
5387 | int const0 = *pconst0; | |
5388 | ||
5389 | const0 &= GET_MODE_MASK (mode); | |
5390 | const1 &= GET_MODE_MASK (mode); | |
5391 | ||
5392 | /* If OP0 is an AND, clear unimportant bits in CONST1. */ | |
5393 | if (op0 == AND) | |
5394 | const1 &= const0; | |
5395 | ||
5396 | /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or | |
5397 | if OP0 is SET. */ | |
5398 | ||
5399 | if (op1 == NIL || op0 == SET) | |
5400 | return 1; | |
5401 | ||
5402 | else if (op0 == NIL) | |
5403 | op0 = op1, const0 = const1; | |
5404 | ||
5405 | else if (op0 == op1) | |
5406 | { | |
5407 | switch (op0) | |
5408 | { | |
5409 | case AND: | |
5410 | const0 &= const1; | |
5411 | break; | |
5412 | case IOR: | |
5413 | const0 |= const1; | |
5414 | break; | |
5415 | case XOR: | |
5416 | const0 ^= const1; | |
5417 | break; | |
5418 | case PLUS: | |
5419 | const0 += const1; | |
5420 | break; | |
5421 | case NEG: | |
5422 | op0 = NIL; | |
5423 | break; | |
5424 | } | |
5425 | } | |
5426 | ||
5427 | /* Otherwise, if either is a PLUS or NEG, we can't do anything. */ | |
5428 | else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG) | |
5429 | return 0; | |
5430 | ||
5431 | /* If the two constants aren't the same, we can't do anything. The | |
5432 | remaining six cases can all be done. */ | |
5433 | else if (const0 != const1) | |
5434 | return 0; | |
5435 | ||
5436 | else | |
5437 | switch (op0) | |
5438 | { | |
5439 | case IOR: | |
5440 | if (op1 == AND) | |
5441 | /* (a & b) | b == b */ | |
5442 | op0 = SET; | |
5443 | else /* op1 == XOR */ | |
5444 | /* (a ^ b) | b == a | b */ | |
5445 | ; | |
5446 | break; | |
5447 | ||
5448 | case XOR: | |
5449 | if (op1 == AND) | |
5450 | /* (a & b) ^ b == (~a) & b */ | |
5451 | op0 = AND, *pcomp_p = 1; | |
5452 | else /* op1 == IOR */ | |
5453 | /* (a | b) ^ b == a & ~b */ | |
5454 | op0 = AND, *pconst0 = ~ const0; | |
5455 | break; | |
5456 | ||
5457 | case AND: | |
5458 | if (op1 == IOR) | |
5459 | /* (a | b) & b == b */ | |
5460 | op0 = SET; | |
5461 | else /* op1 == XOR */ | |
5462 | /* (a ^ b) & b) == (~a) & b */ | |
5463 | *pcomp_p = 1; | |
5464 | break; | |
5465 | } | |
5466 | ||
5467 | /* Check for NO-OP cases. */ | |
5468 | const0 &= GET_MODE_MASK (mode); | |
5469 | if (const0 == 0 | |
5470 | && (op0 == IOR || op0 == XOR || op0 == PLUS)) | |
5471 | op0 = NIL; | |
5472 | else if (const0 == 0 && op0 == AND) | |
5473 | op0 = SET; | |
5474 | else if (const0 == GET_MODE_MASK (mode) && op0 == AND) | |
5475 | op0 = NIL; | |
5476 | ||
5477 | *pop0 = op0; | |
5478 | *pconst0 = const0; | |
5479 | ||
5480 | return 1; | |
5481 | } | |
5482 | \f | |
5483 | /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift. | |
5484 | The result of the shift is RESULT_MODE. X, if non-zero, is an expression | |
5485 | that we started with. | |
5486 | ||
5487 | The shift is normally computed in the widest mode we find in VAROP, as | |
5488 | long as it isn't a different number of words than RESULT_MODE. Exceptions | |
5489 | are ASHIFTRT and ROTATE, which are always done in their original mode, */ | |
5490 | ||
5491 | static rtx | |
5492 | simplify_shift_const (x, code, result_mode, varop, count) | |
5493 | rtx x; | |
5494 | enum rtx_code code; | |
5495 | enum machine_mode result_mode; | |
5496 | rtx varop; | |
5497 | int count; | |
5498 | { | |
5499 | enum rtx_code orig_code = code; | |
5500 | int orig_count = count; | |
5501 | enum machine_mode mode = result_mode; | |
5502 | enum machine_mode shift_mode, tmode; | |
5503 | int mode_words | |
5504 | = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD; | |
5505 | /* We form (outer_op (code varop count) (outer_const)). */ | |
5506 | enum rtx_code outer_op = NIL; | |
5507 | int outer_const; | |
5508 | rtx const_rtx; | |
5509 | int complement_p = 0; | |
5510 | rtx new; | |
5511 | ||
5512 | /* If we were given an invalid count, don't do anything except exactly | |
5513 | what was requested. */ | |
5514 | ||
5515 | if (count < 0 || count > GET_MODE_BITSIZE (mode)) | |
5516 | { | |
5517 | if (x) | |
5518 | return x; | |
5519 | ||
5520 | return gen_rtx (code, mode, varop, gen_rtx (CONST_INT, VOIDmode, count)); | |
5521 | } | |
5522 | ||
5523 | /* Unless one of the branches of the `if' in this loop does a `continue', | |
5524 | we will `break' the loop after the `if'. */ | |
5525 | ||
5526 | while (count != 0) | |
5527 | { | |
5528 | /* If we have an operand of (clobber (const_int 0)), just return that | |
5529 | value. */ | |
5530 | if (GET_CODE (varop) == CLOBBER) | |
5531 | return varop; | |
5532 | ||
5533 | /* If we discovered we had to complement VAROP, leave. Making a NOT | |
5534 | here would cause an infinite loop. */ | |
5535 | if (complement_p) | |
5536 | break; | |
5537 | ||
5538 | /* Convert ROTATETRT to ROTATE. */ | |
5539 | if (code == ROTATERT) | |
5540 | code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count; | |
5541 | ||
5542 | /* Canonicalize LSHIFT to ASHIFT. */ | |
5543 | if (code == LSHIFT) | |
5544 | code = ASHIFT; | |
5545 | ||
5546 | /* We need to determine what mode we will do the shift in. If the | |
5547 | shift is a ASHIFTRT or ROTATE, we must always do it in the mode it | |
5548 | was originally done in. Otherwise, we can do it in MODE, the widest | |
5549 | mode encountered. */ | |
5550 | shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); | |
5551 | ||
5552 | /* Handle cases where the count is greater than the size of the mode | |
5553 | minus 1. For ASHIFT, use the size minus one as the count (this can | |
5554 | occur when simplifying (lshiftrt (ashiftrt ..))). For rotates, | |
5555 | take the count modulo the size. For other shifts, the result is | |
5556 | zero. | |
5557 | ||
5558 | Since these shifts are being produced by the compiler by combining | |
5559 | multiple operations, each of which are defined, we know what the | |
5560 | result is supposed to be. */ | |
5561 | ||
5562 | if (count > GET_MODE_BITSIZE (shift_mode) - 1) | |
5563 | { | |
5564 | if (code == ASHIFTRT) | |
5565 | count = GET_MODE_BITSIZE (shift_mode) - 1; | |
5566 | else if (code == ROTATE || code == ROTATERT) | |
5567 | count %= GET_MODE_BITSIZE (shift_mode); | |
5568 | else | |
5569 | { | |
5570 | /* We can't simply return zero because there may be an | |
5571 | outer op. */ | |
5572 | varop = const0_rtx; | |
5573 | count = 0; | |
5574 | break; | |
5575 | } | |
5576 | } | |
5577 | ||
5578 | /* Negative counts are invalid and should not have been made (a | |
5579 | programmer-specified negative count should have been handled | |
5580 | above). */ | |
5581 | else if (count < 0) | |
5582 | abort (); | |
5583 | ||
5584 | /* We simplify the tests below and elsewhere by converting | |
5585 | ASHIFTRT to LSHIFTRT if we know the sign bit is clear. | |
5586 | `make_compound_operation' will convert it to a ASHIFTRT for | |
5587 | those machines (such as Vax) that don't have a LSHIFTRT. */ | |
5588 | if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_INT | |
5589 | && code == ASHIFTRT | |
5590 | && (significant_bits (varop, shift_mode) | |
5591 | & (1 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0) | |
5592 | code = LSHIFTRT; | |
5593 | ||
5594 | switch (GET_CODE (varop)) | |
5595 | { | |
5596 | case SIGN_EXTEND: | |
5597 | case ZERO_EXTEND: | |
5598 | case SIGN_EXTRACT: | |
5599 | case ZERO_EXTRACT: | |
5600 | new = expand_compound_operation (varop); | |
5601 | if (new != varop) | |
5602 | { | |
5603 | varop = new; | |
5604 | continue; | |
5605 | } | |
5606 | break; | |
5607 | ||
5608 | case MEM: | |
5609 | /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH | |
5610 | minus the width of a smaller mode, we can do this with a | |
5611 | SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */ | |
5612 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5613 | && ! mode_dependent_address_p (XEXP (varop, 0)) | |
5614 | && ! MEM_VOLATILE_P (varop) | |
5615 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
5616 | MODE_INT, 1)) != BLKmode) | |
5617 | { | |
5618 | #if BYTES_BIG_ENDIAN | |
5619 | new = gen_rtx (MEM, tmode, XEXP (varop, 0)); | |
5620 | #else | |
5621 | new = gen_rtx (MEM, tmode, | |
5622 | plus_constant (XEXP (varop, 0), | |
5623 | count / BITS_PER_UNIT)); | |
5624 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop); | |
5625 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop); | |
5626 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop); | |
5627 | #endif | |
5628 | varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND | |
5629 | : ZERO_EXTEND, mode, new); | |
5630 | count = 0; | |
5631 | continue; | |
5632 | } | |
5633 | break; | |
5634 | ||
5635 | case USE: | |
5636 | /* Similar to the case above, except that we can only do this if | |
5637 | the resulting mode is the same as that of the underlying | |
5638 | MEM and adjust the address depending on the *bits* endianness | |
5639 | because of the way that bit-field extract insns are defined. */ | |
5640 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5641 | && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count, | |
5642 | MODE_INT, 1)) != BLKmode | |
5643 | && tmode == GET_MODE (XEXP (varop, 0))) | |
5644 | { | |
5645 | #if BITS_BIG_ENDIAN | |
5646 | new = XEXP (varop, 0); | |
5647 | #else | |
5648 | new = copy_rtx (XEXP (varop, 0)); | |
5649 | SUBST (XEXP (new, 0), | |
5650 | plus_constant (XEXP (new, 0), | |
5651 | count / BITS_PER_UNIT)); | |
5652 | #endif | |
5653 | ||
5654 | varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND | |
5655 | : ZERO_EXTEND, mode, new); | |
5656 | count = 0; | |
5657 | continue; | |
5658 | } | |
5659 | break; | |
5660 | ||
5661 | case SUBREG: | |
5662 | /* If VAROP is a SUBREG, strip it as long as the inner operand has | |
5663 | the same number of words as what we've seen so far. Then store | |
5664 | the widest mode in MODE. */ | |
5665 | if (SUBREG_WORD (varop) == 0 | |
5666 | && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))) | |
5667 | + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) | |
5668 | == mode_words)) | |
5669 | { | |
5670 | varop = SUBREG_REG (varop); | |
5671 | if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode)) | |
5672 | mode = GET_MODE (varop); | |
5673 | continue; | |
5674 | } | |
5675 | break; | |
5676 | ||
5677 | case MULT: | |
5678 | /* Some machines use MULT instead of ASHIFT because MULT | |
5679 | is cheaper. But it is still better on those machines to | |
5680 | merge two shifts into one. */ | |
5681 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
5682 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
5683 | { | |
5684 | varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0), | |
5685 | gen_rtx (CONST_INT, VOIDmode, | |
5686 | exact_log2 (INTVAL (XEXP (varop, 1))))); | |
5687 | continue; | |
5688 | } | |
5689 | break; | |
5690 | ||
5691 | case UDIV: | |
5692 | /* Similar, for when divides are cheaper. */ | |
5693 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
5694 | && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0) | |
5695 | { | |
5696 | varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0), | |
5697 | gen_rtx (CONST_INT, VOIDmode, | |
5698 | exact_log2 (INTVAL (XEXP (varop, 1))))); | |
5699 | continue; | |
5700 | } | |
5701 | break; | |
5702 | ||
5703 | case ASHIFTRT: | |
5704 | /* If we are extracting just the sign bit of an arithmetic right | |
5705 | shift, that shift is not needed. */ | |
5706 | if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1) | |
5707 | { | |
5708 | varop = XEXP (varop, 0); | |
5709 | continue; | |
5710 | } | |
5711 | ||
5712 | /* ... fall through ... */ | |
5713 | ||
5714 | case LSHIFTRT: | |
5715 | case ASHIFT: | |
5716 | case LSHIFT: | |
5717 | case ROTATE: | |
5718 | /* Here we have two nested shifts. The result is usually the | |
5719 | AND of a new shift with a mask. We compute the result below. */ | |
5720 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
5721 | && INTVAL (XEXP (varop, 1)) >= 0 | |
5722 | && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop)) | |
5723 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT | |
5724 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT) | |
5725 | { | |
5726 | enum rtx_code first_code = GET_CODE (varop); | |
5727 | int first_count = INTVAL (XEXP (varop, 1)); | |
5728 | unsigned int mask; | |
5729 | rtx mask_rtx; | |
5730 | rtx inner; | |
5731 | ||
5732 | if (first_code == LSHIFT) | |
5733 | first_code = ASHIFT; | |
5734 | ||
5735 | /* We have one common special case. We can't do any merging if | |
5736 | the inner code is an ASHIFTRT of a smaller mode. However, if | |
5737 | we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2) | |
5738 | with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2), | |
5739 | we can convert it to | |
5740 | (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1). | |
5741 | This simplifies certain SIGN_EXTEND operations. */ | |
5742 | if (code == ASHIFT && first_code == ASHIFTRT | |
5743 | && (GET_MODE_BITSIZE (result_mode) | |
5744 | - GET_MODE_BITSIZE (GET_MODE (varop))) == count) | |
5745 | { | |
5746 | /* C3 has the low-order C1 bits zero. */ | |
5747 | ||
5748 | mask = GET_MODE_MASK (mode) & ~ ((1 << first_count) - 1); | |
5749 | ||
5750 | varop = simplify_and_const_int (0, result_mode, | |
5751 | XEXP (varop, 0), mask); | |
5752 | varop = simplify_shift_const (0, ASHIFT, result_mode, | |
5753 | varop, count); | |
5754 | count = first_count; | |
5755 | code = ASHIFTRT; | |
5756 | continue; | |
5757 | } | |
5758 | ||
5759 | /* If this was (ashiftrt (ashift foo C1) C2) and we know | |
5760 | something about FOO's previous value, we may be able to | |
5761 | optimize this even though the code below can't handle this | |
5762 | case. | |
5763 | ||
5764 | If FOO has J high-order bits equal to the sign bit with | |
5765 | J > C1, then we can convert this to either an ASHIFT or | |
5766 | a ASHIFTRT depending on the two counts. | |
5767 | ||
5768 | We cannot do this if VAROP's mode is not SHIFT_MODE. */ | |
5769 | ||
5770 | if (code == ASHIFTRT && first_code == ASHIFT | |
5771 | && GET_MODE (varop) == shift_mode | |
5772 | && (inner = get_last_value (XEXP (varop, 0))) != 0) | |
5773 | { | |
5774 | if ((GET_CODE (inner) == CONST_INT | |
5775 | && (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == 0 | |
5776 | || (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == -1))) | |
5777 | || (GET_CODE (inner) == SIGN_EXTEND | |
5778 | && ((GET_MODE_BITSIZE (GET_MODE (inner)) | |
5779 | - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner)))) | |
5780 | >= first_count)) | |
5781 | || (GET_CODE (inner) == ASHIFTRT | |
5782 | && GET_CODE (XEXP (inner, 1)) == CONST_INT | |
5783 | && INTVAL (XEXP (inner, 1)) >= first_count)) | |
5784 | { | |
5785 | count -= first_count; | |
5786 | if (count < 0) | |
5787 | count = - count, code = ASHIFT; | |
5788 | varop = XEXP (varop, 0); | |
5789 | continue; | |
5790 | } | |
5791 | } | |
5792 | ||
5793 | /* There are some cases we can't do. If CODE is ASHIFTRT, | |
5794 | we can only do this if FIRST_CODE is also ASHIFTRT. | |
5795 | ||
5796 | We can't do the case when CODE is ROTATE and FIRST_CODE is | |
5797 | ASHIFTRT. | |
5798 | ||
5799 | If the mode of this shift is not the mode of the outer shift, | |
5800 | we can't do this if either shift is ASHIFTRT or ROTATE. | |
5801 | ||
5802 | Finally, we can't do any of these if the mode is too wide | |
5803 | unless the codes are the same. | |
5804 | ||
5805 | Handle the case where the shift codes are the same | |
5806 | first. */ | |
5807 | ||
5808 | if (code == first_code) | |
5809 | { | |
5810 | if (GET_MODE (varop) != result_mode | |
5811 | && (code == ASHIFTRT || code == ROTATE)) | |
5812 | break; | |
5813 | ||
5814 | count += first_count; | |
5815 | varop = XEXP (varop, 0); | |
5816 | continue; | |
5817 | } | |
5818 | ||
5819 | if (code == ASHIFTRT | |
5820 | || (code == ROTATE && first_code == ASHIFTRT) | |
5821 | || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_INT | |
5822 | || (GET_MODE (varop) != result_mode | |
5823 | && (first_code == ASHIFTRT || first_code == ROTATE | |
5824 | || code == ROTATE))) | |
5825 | break; | |
5826 | ||
5827 | /* To compute the mask to apply after the shift, shift the | |
5828 | significant bits of the inner shift the same way the | |
5829 | outer shift will. */ | |
5830 | ||
5831 | mask_rtx = gen_rtx (CONST_INT, VOIDmode, | |
5832 | significant_bits (varop, GET_MODE (varop))); | |
5833 | ||
5834 | mask_rtx | |
5835 | = simplify_binary_operation (code, result_mode, mask_rtx, | |
5836 | gen_rtx (CONST_INT, VOIDmode, | |
5837 | count)); | |
5838 | ||
5839 | /* Give up if we can't compute an outer operation to use. */ | |
5840 | if (mask_rtx == 0 | |
5841 | || GET_CODE (mask_rtx) != CONST_INT | |
5842 | || ! merge_outer_ops (&outer_op, &outer_const, AND, | |
5843 | INTVAL (mask_rtx), | |
5844 | result_mode, &complement_p)) | |
5845 | break; | |
5846 | ||
5847 | /* If the shifts are in the same direction, we add the | |
5848 | counts. Otherwise, we subtract them. */ | |
5849 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
5850 | == (first_code == ASHIFTRT || first_code == LSHIFTRT)) | |
5851 | count += first_count; | |
5852 | else | |
5853 | count -= first_count; | |
5854 | ||
5855 | /* If COUNT is positive, the new shift is usually CODE, | |
5856 | except for the two exceptions below, in which case it is | |
5857 | FIRST_CODE. If the count is negative, FIRST_CODE should | |
5858 | always be used */ | |
5859 | if (count > 0 | |
5860 | && ((first_code == ROTATE && code == ASHIFT) | |
5861 | || (first_code == ASHIFTRT && code == LSHIFTRT))) | |
5862 | code = first_code; | |
5863 | else if (count < 0) | |
5864 | code = first_code, count = - count; | |
5865 | ||
5866 | varop = XEXP (varop, 0); | |
5867 | continue; | |
5868 | } | |
5869 | ||
5870 | /* If we have (A << B << C) for any shift, we can convert this to | |
5871 | (A << C << B). This wins if A is a constant. Only try this if | |
5872 | B is not a constant. */ | |
5873 | ||
5874 | else if (GET_CODE (varop) == code | |
5875 | && GET_CODE (XEXP (varop, 1)) != CONST_INT | |
5876 | && 0 != (new | |
5877 | = simplify_binary_operation (code, mode, | |
5878 | XEXP (varop, 0), | |
5879 | gen_rtx (CONST_INT, | |
5880 | VOIDmode, | |
5881 | count)))) | |
5882 | { | |
5883 | varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1)); | |
5884 | count = 0; | |
5885 | continue; | |
5886 | } | |
5887 | break; | |
5888 | ||
5889 | case NOT: | |
5890 | /* Make this fit the case below. */ | |
5891 | varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0), | |
5892 | gen_rtx (CONST_INT, VOIDmode, | |
5893 | GET_MODE_MASK (mode))); | |
5894 | continue; | |
5895 | ||
5896 | case IOR: | |
5897 | case AND: | |
5898 | case XOR: | |
5899 | /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C) | |
5900 | with C the size of VAROP - 1 and the shift is logical if | |
5901 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
5902 | we have an (le X 0) operation. If we have an arithmetic shift | |
5903 | and STORE_FLAG_VALUE is 1 or we have a logical shift with | |
5904 | STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */ | |
5905 | ||
5906 | if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS | |
5907 | && XEXP (XEXP (varop, 0), 1) == constm1_rtx | |
5908 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
5909 | && (code == LSHIFTRT || code == ASHIFTRT) | |
5910 | && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 | |
5911 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) | |
5912 | { | |
5913 | count = 0; | |
5914 | varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1), | |
5915 | const0_rtx); | |
5916 | ||
5917 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
5918 | varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); | |
5919 | ||
5920 | continue; | |
5921 | } | |
5922 | ||
5923 | /* If we have (shift (logical)), move the logical to the outside | |
5924 | to allow it to possibly combine with another logical and the | |
5925 | shift to combine with another shift. This also canonicalizes to | |
5926 | what a ZERO_EXTRACT looks like. Also, some machines have | |
5927 | (and (shift)) insns. */ | |
5928 | ||
5929 | if (GET_CODE (XEXP (varop, 1)) == CONST_INT | |
5930 | && (new = simplify_binary_operation (code, result_mode, | |
5931 | XEXP (varop, 1), | |
5932 | gen_rtx (CONST_INT, | |
5933 | VOIDmode, | |
5934 | count))) != 0 | |
5935 | && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop), | |
5936 | INTVAL (new), result_mode, &complement_p)) | |
5937 | { | |
5938 | varop = XEXP (varop, 0); | |
5939 | continue; | |
5940 | } | |
5941 | ||
5942 | /* If we can't do that, try to simplify the shift in each arm of the | |
5943 | logical expression, make a new logical expression, and apply | |
5944 | the inverse distributive law. */ | |
5945 | { | |
5946 | rtx lhs = simplify_shift_const (0, code, result_mode, | |
5947 | XEXP (varop, 0), count); | |
5948 | rtx rhs = simplify_shift_const (0, code, result_mode, | |
5949 | XEXP (varop, 1), count); | |
5950 | ||
5951 | varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs); | |
5952 | varop = apply_distributive_law (varop); | |
5953 | ||
5954 | count = 0; | |
5955 | } | |
5956 | break; | |
5957 | ||
5958 | case EQ: | |
5959 | /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE | |
5960 | says that the sign bit can be tested, FOO has mode MODE, C is | |
5961 | GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit | |
5962 | significant. */ | |
5963 | if (code == LSHIFT | |
5964 | && XEXP (varop, 1) == const0_rtx | |
5965 | && GET_MODE (XEXP (varop, 0)) == result_mode | |
5966 | && count == GET_MODE_BITSIZE (result_mode) - 1 | |
5967 | && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT | |
5968 | && ((STORE_FLAG_VALUE | |
5969 | & (1 << (GET_MODE_BITSIZE (result_mode) - 1)))) | |
5970 | && significant_bits (XEXP (varop, 0), result_mode) == 1 | |
5971 | && merge_outer_ops (&outer_op, &outer_const, XOR, 1, | |
5972 | result_mode, &complement_p)) | |
5973 | { | |
5974 | varop = XEXP (varop, 0); | |
5975 | count = 0; | |
5976 | continue; | |
5977 | } | |
5978 | break; | |
5979 | ||
5980 | case NEG: | |
5981 | /* If we are doing an arithmetic right shift of something known | |
5982 | to be -1 or 0, we don't need the shift. */ | |
5983 | if (code == ASHIFTRT | |
5984 | && significant_bits (XEXP (varop, 0), result_mode) == 1) | |
5985 | { | |
5986 | count = 0; | |
5987 | continue; | |
5988 | } | |
5989 | ||
5990 | /* NEG commutes with ASHIFT since it is multiplication. Move the | |
5991 | NEG outside to allow shifts to combine. */ | |
5992 | if (code == ASHIFT | |
5993 | && merge_outer_ops (&outer_op, &outer_const, NEG, 0, | |
5994 | result_mode, &complement_p)) | |
5995 | { | |
5996 | varop = XEXP (varop, 0); | |
5997 | continue; | |
5998 | } | |
5999 | break; | |
6000 | ||
6001 | case PLUS: | |
6002 | /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */ | |
6003 | if (XEXP (varop, 1) == constm1_rtx && code == ASHIFTRT | |
6004 | && significant_bits (XEXP (varop, 0), result_mode) == 1) | |
6005 | { | |
6006 | count = 0; | |
6007 | continue; | |
6008 | } | |
6009 | ||
6010 | /* If we have the same operands as above but we are shifting the | |
6011 | sign bit into the low-order bit, we are exclusive-or'ing | |
6012 | the operand of the PLUS with a one. */ | |
6013 | if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1 | |
6014 | && XEXP (varop, 1) == constm1_rtx | |
6015 | && significant_bits (XEXP (varop, 0), result_mode) == 1 | |
6016 | && merge_outer_ops (&outer_op, &outer_const, XOR, 1, | |
6017 | result_mode, &complement_p)) | |
6018 | { | |
6019 | count = 0; | |
6020 | varop = XEXP (varop, 0); | |
6021 | continue; | |
6022 | } | |
6023 | ||
3f508eca RK |
6024 | /* If we have (xshiftrt (plus FOO BAR) C), and the only bits |
6025 | significant in BAR are those being shifted out and those | |
6026 | bits are known zero in FOO, we can replace the PLUS with FOO. | |
6027 | Similarly in the other operand order. This code occurs when | |
6028 | we are computing the size of a variable-size array. */ | |
6029 | ||
6030 | if ((code == ASHIFTRT || code == LSHIFTRT) | |
6031 | && count < HOST_BITS_PER_INT | |
6032 | && significant_bits (XEXP (varop, 1), result_mode) >> count == 0 | |
6033 | && (significant_bits (XEXP (varop, 1), result_mode) | |
6034 | & significant_bits (XEXP (varop, 0), result_mode)) == 0) | |
6035 | { | |
6036 | varop = XEXP (varop, 0); | |
6037 | continue; | |
6038 | } | |
6039 | else if ((code == ASHIFTRT || code == LSHIFTRT) | |
6040 | && count < HOST_BITS_PER_INT | |
6041 | && 0 == (significant_bits (XEXP (varop, 0), result_mode) | |
6042 | >> count) | |
6043 | && 0 == (significant_bits (XEXP (varop, 0), result_mode) | |
6044 | & significant_bits (XEXP (varop, 1), | |
6045 | result_mode))) | |
6046 | { | |
6047 | varop = XEXP (varop, 1); | |
6048 | continue; | |
6049 | } | |
6050 | ||
230d793d RS |
6051 | /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */ |
6052 | if (code == ASHIFT | |
6053 | && GET_CODE (XEXP (varop, 1)) == CONST_INT | |
6054 | && (new = simplify_binary_operation (ASHIFT, result_mode, | |
6055 | XEXP (varop, 1), | |
6056 | gen_rtx (CONST_INT, | |
6057 | VOIDmode, | |
6058 | count))) != 0 | |
6059 | && merge_outer_ops (&outer_op, &outer_const, PLUS, | |
6060 | INTVAL (new), result_mode, &complement_p)) | |
6061 | { | |
6062 | varop = XEXP (varop, 0); | |
6063 | continue; | |
6064 | } | |
6065 | break; | |
6066 | ||
6067 | case MINUS: | |
6068 | /* If we have (xshiftrt (minus (ashiftrt X C)) X) C) | |
6069 | with C the size of VAROP - 1 and the shift is logical if | |
6070 | STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1, | |
6071 | we have a (gt X 0) operation. If the shift is arithmetic with | |
6072 | STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1, | |
6073 | we have a (neg (gt X 0)) operation. */ | |
6074 | ||
6075 | if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT | |
6076 | && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1 | |
6077 | && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1) | |
6078 | && (code == LSHIFTRT || code == ASHIFTRT) | |
6079 | && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT | |
6080 | && INTVAL (XEXP (XEXP (varop, 0), 1)) == count | |
6081 | && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1))) | |
6082 | { | |
6083 | count = 0; | |
6084 | varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1), | |
6085 | const0_rtx); | |
6086 | ||
6087 | if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT) | |
6088 | varop = gen_rtx_combine (NEG, GET_MODE (varop), varop); | |
6089 | ||
6090 | continue; | |
6091 | } | |
6092 | break; | |
6093 | } | |
6094 | ||
6095 | break; | |
6096 | } | |
6097 | ||
6098 | /* We need to determine what mode to do the shift in. If the shift is | |
6099 | a ASHIFTRT or ROTATE, we must always do it in the mode it was originally | |
6100 | done in. Otherwise, we can do it in MODE, the widest mode encountered. | |
6101 | The code we care about is that of the shift that will actually be done, | |
6102 | not the shift that was originally requested. */ | |
6103 | shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode); | |
6104 | ||
6105 | /* We have now finished analyzing the shift. The result should be | |
6106 | a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If | |
6107 | OUTER_OP is non-NIL, it is an operation that needs to be applied | |
6108 | to the result of the shift. OUTER_CONST is the relevant constant, | |
6109 | but we must turn off all bits turned off in the shift. | |
6110 | ||
6111 | If we were passed a value for X, see if we can use any pieces of | |
6112 | it. If not, make new rtx. */ | |
6113 | ||
6114 | if (x && GET_RTX_CLASS (GET_CODE (x)) == '2' | |
6115 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
6116 | && INTVAL (XEXP (x, 1)) == count) | |
6117 | const_rtx = XEXP (x, 1); | |
6118 | else | |
6119 | const_rtx = gen_rtx (CONST_INT, VOIDmode, count); | |
6120 | ||
6121 | if (x && GET_CODE (XEXP (x, 0)) == SUBREG | |
6122 | && GET_MODE (XEXP (x, 0)) == shift_mode | |
6123 | && SUBREG_REG (XEXP (x, 0)) == varop) | |
6124 | varop = XEXP (x, 0); | |
6125 | else if (GET_MODE (varop) != shift_mode) | |
6126 | varop = gen_lowpart_for_combine (shift_mode, varop); | |
6127 | ||
6128 | /* If we can't make the SUBREG, try to return what we were given. */ | |
6129 | if (GET_CODE (varop) == CLOBBER) | |
6130 | return x ? x : varop; | |
6131 | ||
6132 | new = simplify_binary_operation (code, shift_mode, varop, const_rtx); | |
6133 | if (new != 0) | |
6134 | x = new; | |
6135 | else | |
6136 | { | |
6137 | if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode) | |
6138 | x = gen_rtx_combine (code, shift_mode, varop, const_rtx); | |
6139 | ||
6140 | SUBST (XEXP (x, 0), varop); | |
6141 | SUBST (XEXP (x, 1), const_rtx); | |
6142 | } | |
6143 | ||
6144 | /* If we were doing a LSHIFTRT in a wider mode than it was originally, | |
6145 | turn off all the bits that the shift would have turned off. */ | |
6146 | if (orig_code == LSHIFTRT && result_mode != shift_mode) | |
6147 | x = simplify_and_const_int (0, shift_mode, x, | |
6148 | GET_MODE_MASK (result_mode) >> orig_count); | |
6149 | ||
6150 | /* Do the remainder of the processing in RESULT_MODE. */ | |
6151 | x = gen_lowpart_for_combine (result_mode, x); | |
6152 | ||
6153 | /* If COMPLEMENT_P is set, we have to complement X before doing the outer | |
6154 | operation. */ | |
6155 | if (complement_p) | |
6156 | x = gen_unary (NOT, result_mode, x); | |
6157 | ||
6158 | if (outer_op != NIL) | |
6159 | { | |
6160 | if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_INT) | |
6161 | outer_const &= GET_MODE_MASK (result_mode); | |
6162 | ||
6163 | if (outer_op == AND) | |
6164 | x = simplify_and_const_int (0, result_mode, x, outer_const); | |
6165 | else if (outer_op == SET) | |
6166 | /* This means that we have determined that the result is | |
6167 | equivalent to a constant. This should be rare. */ | |
6168 | x = gen_rtx (CONST_INT, VOIDmode, outer_const); | |
6169 | else if (GET_RTX_CLASS (outer_op) == '1') | |
6170 | x = gen_unary (outer_op, result_mode, x); | |
6171 | else | |
6172 | x = gen_binary (outer_op, result_mode, x, | |
6173 | gen_rtx (CONST_INT, VOIDmode, outer_const)); | |
6174 | } | |
6175 | ||
6176 | return x; | |
6177 | } | |
6178 | \f | |
6179 | /* Like recog, but we receive the address of a pointer to a new pattern. | |
6180 | We try to match the rtx that the pointer points to. | |
6181 | If that fails, we may try to modify or replace the pattern, | |
6182 | storing the replacement into the same pointer object. | |
6183 | ||
6184 | Modifications include deletion or addition of CLOBBERs. | |
6185 | ||
6186 | PNOTES is a pointer to a location where any REG_UNUSED notes added for | |
6187 | the CLOBBERs are placed. | |
6188 | ||
6189 | The value is the final insn code from the pattern ultimately matched, | |
6190 | or -1. */ | |
6191 | ||
6192 | static int | |
6193 | recog_for_combine (pnewpat, insn, pnotes) | |
6194 | rtx *pnewpat; | |
6195 | rtx insn; | |
6196 | rtx *pnotes; | |
6197 | { | |
6198 | register rtx pat = *pnewpat; | |
6199 | int insn_code_number; | |
6200 | int num_clobbers_to_add = 0; | |
6201 | int i; | |
6202 | rtx notes = 0; | |
6203 | ||
6204 | /* Is the result of combination a valid instruction? */ | |
6205 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
6206 | ||
6207 | /* If it isn't, there is the possibility that we previously had an insn | |
6208 | that clobbered some register as a side effect, but the combined | |
6209 | insn doesn't need to do that. So try once more without the clobbers | |
6210 | unless this represents an ASM insn. */ | |
6211 | ||
6212 | if (insn_code_number < 0 && ! check_asm_operands (pat) | |
6213 | && GET_CODE (pat) == PARALLEL) | |
6214 | { | |
6215 | int pos; | |
6216 | ||
6217 | for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++) | |
6218 | if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER) | |
6219 | { | |
6220 | if (i != pos) | |
6221 | SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i)); | |
6222 | pos++; | |
6223 | } | |
6224 | ||
6225 | SUBST_INT (XVECLEN (pat, 0), pos); | |
6226 | ||
6227 | if (pos == 1) | |
6228 | pat = XVECEXP (pat, 0, 0); | |
6229 | ||
6230 | insn_code_number = recog (pat, insn, &num_clobbers_to_add); | |
6231 | } | |
6232 | ||
6233 | /* If we had any clobbers to add, make a new pattern than contains | |
6234 | them. Then check to make sure that all of them are dead. */ | |
6235 | if (num_clobbers_to_add) | |
6236 | { | |
6237 | rtx newpat = gen_rtx (PARALLEL, VOIDmode, | |
6238 | gen_rtvec (GET_CODE (pat) == PARALLEL | |
6239 | ? XVECLEN (pat, 0) + num_clobbers_to_add | |
6240 | : num_clobbers_to_add + 1)); | |
6241 | ||
6242 | if (GET_CODE (pat) == PARALLEL) | |
6243 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
6244 | XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i); | |
6245 | else | |
6246 | XVECEXP (newpat, 0, 0) = pat; | |
6247 | ||
6248 | add_clobbers (newpat, insn_code_number); | |
6249 | ||
6250 | for (i = XVECLEN (newpat, 0) - num_clobbers_to_add; | |
6251 | i < XVECLEN (newpat, 0); i++) | |
6252 | { | |
6253 | if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG | |
6254 | && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn)) | |
6255 | return -1; | |
6256 | notes = gen_rtx (EXPR_LIST, REG_UNUSED, | |
6257 | XEXP (XVECEXP (newpat, 0, i), 0), notes); | |
6258 | } | |
6259 | pat = newpat; | |
6260 | } | |
6261 | ||
6262 | *pnewpat = pat; | |
6263 | *pnotes = notes; | |
6264 | ||
6265 | return insn_code_number; | |
6266 | } | |
6267 | \f | |
6268 | /* Like gen_lowpart but for use by combine. In combine it is not possible | |
6269 | to create any new pseudoregs. However, it is safe to create | |
6270 | invalid memory addresses, because combine will try to recognize | |
6271 | them and all they will do is make the combine attempt fail. | |
6272 | ||
6273 | If for some reason this cannot do its job, an rtx | |
6274 | (clobber (const_int 0)) is returned. | |
6275 | An insn containing that will not be recognized. */ | |
6276 | ||
6277 | #undef gen_lowpart | |
6278 | ||
6279 | static rtx | |
6280 | gen_lowpart_for_combine (mode, x) | |
6281 | enum machine_mode mode; | |
6282 | register rtx x; | |
6283 | { | |
6284 | rtx result; | |
6285 | ||
6286 | if (GET_MODE (x) == mode) | |
6287 | return x; | |
6288 | ||
6289 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) | |
6290 | return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); | |
6291 | ||
6292 | /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart | |
6293 | won't know what to do. So we will strip off the SUBREG here and | |
6294 | process normally. */ | |
6295 | if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM) | |
6296 | { | |
6297 | x = SUBREG_REG (x); | |
6298 | if (GET_MODE (x) == mode) | |
6299 | return x; | |
6300 | } | |
6301 | ||
6302 | result = gen_lowpart_common (mode, x); | |
6303 | if (result) | |
6304 | return result; | |
6305 | ||
6306 | if (GET_CODE (x) == MEM) | |
6307 | { | |
6308 | register int offset = 0; | |
6309 | rtx new; | |
6310 | ||
6311 | /* Refuse to work on a volatile memory ref or one with a mode-dependent | |
6312 | address. */ | |
6313 | if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0))) | |
6314 | return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); | |
6315 | ||
6316 | /* If we want to refer to something bigger than the original memref, | |
6317 | generate a perverse subreg instead. That will force a reload | |
6318 | of the original memref X. */ | |
6319 | if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)) | |
6320 | return gen_rtx (SUBREG, mode, x, 0); | |
6321 | ||
6322 | #if WORDS_BIG_ENDIAN | |
6323 | offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD) | |
6324 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)); | |
6325 | #endif | |
6326 | #if BYTES_BIG_ENDIAN | |
6327 | /* Adjust the address so that the address-after-the-data | |
6328 | is unchanged. */ | |
6329 | offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)) | |
6330 | - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x)))); | |
6331 | #endif | |
6332 | new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset)); | |
6333 | RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x); | |
6334 | MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x); | |
6335 | MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x); | |
6336 | return new; | |
6337 | } | |
6338 | ||
6339 | /* If X is a comparison operator, rewrite it in a new mode. This | |
6340 | probably won't match, but may allow further simplifications. */ | |
6341 | else if (GET_RTX_CLASS (GET_CODE (x)) == '<') | |
6342 | return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1)); | |
6343 | ||
6344 | /* If we couldn't simplify X any other way, just enclose it in a | |
6345 | SUBREG. Normally, this SUBREG won't match, but some patterns may | |
a7c99304 | 6346 | include an explicit SUBREG or we may simplify it further in combine. */ |
230d793d | 6347 | else |
dfbe1b2f RK |
6348 | { |
6349 | int word = 0; | |
6350 | ||
6351 | if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) | |
6352 | word = ((GET_MODE_SIZE (GET_MODE (x)) | |
6353 | - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD)) | |
6354 | / UNITS_PER_WORD); | |
6355 | return gen_rtx (SUBREG, mode, x, word); | |
6356 | } | |
230d793d RS |
6357 | } |
6358 | \f | |
6359 | /* Make an rtx expression. This is a subset of gen_rtx and only supports | |
6360 | expressions of 1, 2, or 3 operands, each of which are rtx expressions. | |
6361 | ||
6362 | If the identical expression was previously in the insn (in the undobuf), | |
6363 | it will be returned. Only if it is not found will a new expression | |
6364 | be made. */ | |
6365 | ||
6366 | /*VARARGS2*/ | |
6367 | static rtx | |
6368 | gen_rtx_combine (va_alist) | |
6369 | va_dcl | |
6370 | { | |
6371 | va_list p; | |
6372 | enum rtx_code code; | |
6373 | enum machine_mode mode; | |
6374 | int n_args; | |
6375 | rtx args[3]; | |
6376 | int i, j; | |
6377 | char *fmt; | |
6378 | rtx rt; | |
6379 | ||
6380 | va_start (p); | |
6381 | code = va_arg (p, enum rtx_code); | |
6382 | mode = va_arg (p, enum machine_mode); | |
6383 | n_args = GET_RTX_LENGTH (code); | |
6384 | fmt = GET_RTX_FORMAT (code); | |
6385 | ||
6386 | if (n_args == 0 || n_args > 3) | |
6387 | abort (); | |
6388 | ||
6389 | /* Get each arg and verify that it is supposed to be an expression. */ | |
6390 | for (j = 0; j < n_args; j++) | |
6391 | { | |
6392 | if (*fmt++ != 'e') | |
6393 | abort (); | |
6394 | ||
6395 | args[j] = va_arg (p, rtx); | |
6396 | } | |
6397 | ||
6398 | /* See if this is in undobuf. Be sure we don't use objects that came | |
6399 | from another insn; this could produce circular rtl structures. */ | |
6400 | ||
6401 | for (i = previous_num_undos; i < undobuf.num_undo; i++) | |
6402 | if (!undobuf.undo[i].is_int | |
6403 | && GET_CODE (undobuf.undo[i].old_contents) == code | |
6404 | && GET_MODE (undobuf.undo[i].old_contents) == mode) | |
6405 | { | |
6406 | for (j = 0; j < n_args; j++) | |
6407 | if (XEXP (undobuf.undo[i].old_contents, j) != args[j]) | |
6408 | break; | |
6409 | ||
6410 | if (j == n_args) | |
6411 | return undobuf.undo[i].old_contents; | |
6412 | } | |
6413 | ||
6414 | /* Otherwise make a new rtx. We know we have 1, 2, or 3 args. | |
6415 | Use rtx_alloc instead of gen_rtx because it's faster on RISC. */ | |
6416 | rt = rtx_alloc (code); | |
6417 | PUT_MODE (rt, mode); | |
6418 | XEXP (rt, 0) = args[0]; | |
6419 | if (n_args > 1) | |
6420 | { | |
6421 | XEXP (rt, 1) = args[1]; | |
6422 | if (n_args > 2) | |
6423 | XEXP (rt, 2) = args[2]; | |
6424 | } | |
6425 | return rt; | |
6426 | } | |
6427 | ||
6428 | /* These routines make binary and unary operations by first seeing if they | |
6429 | fold; if not, a new expression is allocated. */ | |
6430 | ||
6431 | static rtx | |
6432 | gen_binary (code, mode, op0, op1) | |
6433 | enum rtx_code code; | |
6434 | enum machine_mode mode; | |
6435 | rtx op0, op1; | |
6436 | { | |
6437 | rtx result; | |
6438 | ||
6439 | if (GET_RTX_CLASS (code) == '<') | |
6440 | { | |
6441 | enum machine_mode op_mode = GET_MODE (op0); | |
6442 | if (op_mode == VOIDmode) | |
6443 | op_mode = GET_MODE (op1); | |
6444 | result = simplify_relational_operation (code, op_mode, op0, op1); | |
6445 | } | |
6446 | else | |
6447 | result = simplify_binary_operation (code, mode, op0, op1); | |
6448 | ||
6449 | if (result) | |
6450 | return result; | |
6451 | ||
6452 | /* Put complex operands first and constants second. */ | |
6453 | if (GET_RTX_CLASS (code) == 'c' | |
6454 | && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT) | |
6455 | || (GET_RTX_CLASS (GET_CODE (op0)) == 'o' | |
6456 | && GET_RTX_CLASS (GET_CODE (op1)) != 'o') | |
6457 | || (GET_CODE (op0) == SUBREG | |
6458 | && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o' | |
6459 | && GET_RTX_CLASS (GET_CODE (op1)) != 'o'))) | |
6460 | return gen_rtx_combine (code, mode, op1, op0); | |
6461 | ||
6462 | return gen_rtx_combine (code, mode, op0, op1); | |
6463 | } | |
6464 | ||
6465 | static rtx | |
6466 | gen_unary (code, mode, op0) | |
6467 | enum rtx_code code; | |
6468 | enum machine_mode mode; | |
6469 | rtx op0; | |
6470 | { | |
6471 | rtx result = simplify_unary_operation (code, mode, op0, mode); | |
6472 | ||
6473 | if (result) | |
6474 | return result; | |
6475 | ||
6476 | return gen_rtx_combine (code, mode, op0); | |
6477 | } | |
6478 | \f | |
6479 | /* Simplify a comparison between *POP0 and *POP1 where CODE is the | |
6480 | comparison code that will be tested. | |
6481 | ||
6482 | The result is a possibly different comparison code to use. *POP0 and | |
6483 | *POP1 may be updated. | |
6484 | ||
6485 | It is possible that we might detect that a comparison is either always | |
6486 | true or always false. However, we do not perform general constant | |
5089e22e | 6487 | folding in combine, so this knowledge isn't useful. Such tautologies |
230d793d RS |
6488 | should have been detected earlier. Hence we ignore all such cases. */ |
6489 | ||
6490 | static enum rtx_code | |
6491 | simplify_comparison (code, pop0, pop1) | |
6492 | enum rtx_code code; | |
6493 | rtx *pop0; | |
6494 | rtx *pop1; | |
6495 | { | |
6496 | rtx op0 = *pop0; | |
6497 | rtx op1 = *pop1; | |
6498 | rtx tem, tem1; | |
6499 | int i; | |
6500 | enum machine_mode mode, tmode; | |
6501 | ||
6502 | /* Try a few ways of applying the same transformation to both operands. */ | |
6503 | while (1) | |
6504 | { | |
6505 | /* If both operands are the same constant shift, see if we can ignore the | |
6506 | shift. We can if the shift is a rotate or if the bits shifted out of | |
6507 | this shift are not significant for either input and if the type of | |
6508 | comparison is compatible with the shift. */ | |
6509 | if (GET_CODE (op0) == GET_CODE (op1) | |
6510 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT | |
6511 | && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ)) | |
6512 | || ((GET_CODE (op0) == LSHIFTRT | |
6513 | || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT) | |
6514 | && (code != GT && code != LT && code != GE && code != LE)) | |
6515 | || (GET_CODE (op0) == ASHIFTRT | |
6516 | && (code != GTU && code != LTU | |
6517 | && code != GEU && code != GEU))) | |
6518 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
6519 | && INTVAL (XEXP (op0, 1)) >= 0 | |
6520 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT | |
6521 | && XEXP (op0, 1) == XEXP (op1, 1)) | |
6522 | { | |
6523 | enum machine_mode mode = GET_MODE (op0); | |
6524 | unsigned mask = GET_MODE_MASK (mode); | |
6525 | int shift_count = INTVAL (XEXP (op0, 1)); | |
6526 | ||
6527 | if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT) | |
6528 | mask &= (mask >> shift_count) << shift_count; | |
6529 | else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT) | |
6530 | mask = (mask & (mask << shift_count)) >> shift_count; | |
6531 | ||
6532 | if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0 | |
6533 | && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0) | |
6534 | op0 = XEXP (op0, 0), op1 = XEXP (op1, 0); | |
6535 | else | |
6536 | break; | |
6537 | } | |
6538 | ||
6539 | /* If both operands are AND's of a paradoxical SUBREG by constant, the | |
6540 | SUBREGs are of the same mode, and, in both cases, the AND would | |
6541 | be redundant if the comparison was done in the narrower mode, | |
6542 | do the comparison in the narrower mode (e.g., we are AND'ing with 1 | |
6543 | and the operand's significant bits are 0xffffff01; in that case if | |
6544 | we only care about QImode, we don't need the AND). This case occurs | |
6545 | if the output mode of an scc insn is not SImode and | |
6546 | STORE_FLAG_VALUE == 1 (e.g., the 386). */ | |
6547 | ||
6548 | else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND | |
6549 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
6550 | && GET_CODE (XEXP (op1, 1)) == CONST_INT | |
6551 | && GET_CODE (XEXP (op0, 0)) == SUBREG | |
6552 | && GET_CODE (XEXP (op1, 0)) == SUBREG | |
6553 | && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) | |
6554 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))) | |
6555 | && (GET_MODE (SUBREG_REG (XEXP (op0, 0))) | |
6556 | == GET_MODE (SUBREG_REG (XEXP (op1, 0)))) | |
6557 | && (significant_bits (SUBREG_REG (XEXP (op0, 0)), | |
6558 | GET_MODE (SUBREG_REG (XEXP (op0, 0)))) | |
6559 | & ~ INTVAL (XEXP (op0, 1))) == 0 | |
6560 | && (significant_bits (SUBREG_REG (XEXP (op1, 0)), | |
6561 | GET_MODE (SUBREG_REG (XEXP (op1, 0)))) | |
6562 | & ~ INTVAL (XEXP (op1, 1))) == 0) | |
6563 | { | |
6564 | op0 = SUBREG_REG (XEXP (op0, 0)); | |
6565 | op1 = SUBREG_REG (XEXP (op1, 0)); | |
6566 | ||
6567 | /* the resulting comparison is always unsigned since we masked off | |
6568 | the original sign bit. */ | |
6569 | code = unsigned_condition (code); | |
6570 | } | |
6571 | else | |
6572 | break; | |
6573 | } | |
6574 | ||
6575 | /* If the first operand is a constant, swap the operands and adjust the | |
6576 | comparison code appropriately. */ | |
6577 | if (CONSTANT_P (op0)) | |
6578 | { | |
6579 | tem = op0, op0 = op1, op1 = tem; | |
6580 | code = swap_condition (code); | |
6581 | } | |
6582 | ||
6583 | /* We now enter a loop during which we will try to simplify the comparison. | |
6584 | For the most part, we only are concerned with comparisons with zero, | |
6585 | but some things may really be comparisons with zero but not start | |
6586 | out looking that way. */ | |
6587 | ||
6588 | while (GET_CODE (op1) == CONST_INT) | |
6589 | { | |
6590 | enum machine_mode mode = GET_MODE (op0); | |
6591 | int mode_width = GET_MODE_BITSIZE (mode); | |
6592 | unsigned mask = GET_MODE_MASK (mode); | |
6593 | int equality_comparison_p; | |
6594 | int sign_bit_comparison_p; | |
6595 | int unsigned_comparison_p; | |
6596 | int const_op; | |
6597 | ||
6598 | /* We only want to handle integral modes. This catches VOIDmode, | |
6599 | CCmode, and the floating-point modes. An exception is that we | |
6600 | can handle VOIDmode if OP0 is a COMPARE or a comparison | |
6601 | operation. */ | |
6602 | ||
6603 | if (GET_MODE_CLASS (mode) != MODE_INT | |
6604 | && ! (mode == VOIDmode | |
6605 | && (GET_CODE (op0) == COMPARE | |
6606 | || GET_RTX_CLASS (GET_CODE (op0)) == '<'))) | |
6607 | break; | |
6608 | ||
6609 | /* Get the constant we are comparing against and turn off all bits | |
6610 | not on in our mode. */ | |
6611 | const_op = INTVAL (op1); | |
6612 | if (mode_width <= HOST_BITS_PER_INT) | |
4803a34a | 6613 | const_op &= mask; |
230d793d RS |
6614 | |
6615 | /* If we are comparing against a constant power of two and the value | |
6616 | being compared has only that single significant bit (e.g., it was | |
6617 | `and'ed with that bit), we can replace this with a comparison | |
6618 | with zero. */ | |
6619 | if (const_op | |
6620 | && (code == EQ || code == NE || code == GE || code == GEU | |
6621 | || code == LT || code == LTU) | |
6622 | && mode_width <= HOST_BITS_PER_INT | |
6623 | && exact_log2 (const_op) >= 0 | |
6624 | && significant_bits (op0, mode) == const_op) | |
6625 | { | |
6626 | code = (code == EQ || code == GE || code == GEU ? NE : EQ); | |
6627 | op1 = const0_rtx, const_op = 0; | |
6628 | } | |
6629 | ||
6630 | /* Do some canonicalizations based on the comparison code. We prefer | |
4803a34a RK |
6631 | comparisons against zero and then prefer equality comparisons. |
6632 | If we can reduce the size of a constant, we will do that too. */ | |
230d793d RS |
6633 | |
6634 | switch (code) | |
6635 | { | |
6636 | case LT: | |
4803a34a RK |
6637 | /* < C is equivalent to <= (C - 1) */ |
6638 | if (const_op > 0) | |
230d793d | 6639 | { |
4803a34a RK |
6640 | const_op -= 1; |
6641 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
230d793d RS |
6642 | code = LE; |
6643 | /* ... fall through to LE case below. */ | |
6644 | } | |
6645 | else | |
6646 | break; | |
6647 | ||
6648 | case LE: | |
4803a34a RK |
6649 | /* <= C is equivalent to < (C + 1); we do this for C < 0 */ |
6650 | if (const_op < 0) | |
6651 | { | |
6652 | const_op += 1; | |
6653 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
6654 | code = LT; | |
6655 | } | |
230d793d RS |
6656 | |
6657 | /* If we are doing a <= 0 comparison on a value known to have | |
6658 | a zero sign bit, we can replace this with == 0. */ | |
6659 | else if (const_op == 0 | |
6660 | && mode_width <= HOST_BITS_PER_INT | |
6661 | && (significant_bits (op0, mode) | |
6662 | & (1 << (mode_width - 1))) == 0) | |
6663 | code = EQ; | |
6664 | break; | |
6665 | ||
6666 | case GE: | |
4803a34a RK |
6667 | /* >= C is equivalent to > (C - 1). */ |
6668 | if (const_op > 0) | |
230d793d | 6669 | { |
4803a34a RK |
6670 | const_op -= 1; |
6671 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
230d793d RS |
6672 | code = GT; |
6673 | /* ... fall through to GT below. */ | |
6674 | } | |
6675 | else | |
6676 | break; | |
6677 | ||
6678 | case GT: | |
4803a34a RK |
6679 | /* > C is equivalent to >= (C + 1); we do this for C < 0*/ |
6680 | if (const_op < 0) | |
6681 | { | |
6682 | const_op += 1; | |
6683 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
6684 | code = GE; | |
6685 | } | |
230d793d RS |
6686 | |
6687 | /* If we are doing a > 0 comparison on a value known to have | |
6688 | a zero sign bit, we can replace this with != 0. */ | |
6689 | else if (const_op == 0 | |
6690 | && mode_width <= HOST_BITS_PER_INT | |
6691 | && (significant_bits (op0, mode) | |
6692 | & (1 << (mode_width - 1))) == 0) | |
6693 | code = NE; | |
6694 | break; | |
6695 | ||
230d793d | 6696 | case LTU: |
4803a34a RK |
6697 | /* < C is equivalent to <= (C - 1). */ |
6698 | if (const_op > 0) | |
6699 | { | |
6700 | const_op -= 1; | |
6701 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
6702 | code = LEU; | |
6703 | /* ... fall through ... */ | |
6704 | } | |
6705 | else | |
6706 | break; | |
230d793d RS |
6707 | |
6708 | case LEU: | |
6709 | /* unsigned <= 0 is equivalent to == 0 */ | |
6710 | if (const_op == 0) | |
6711 | code = EQ; | |
6712 | break; | |
6713 | ||
4803a34a RK |
6714 | case GEU: |
6715 | /* >= C is equivalent to < (C - 1). */ | |
6716 | if (const_op > 1) | |
6717 | { | |
6718 | const_op -= 1; | |
6719 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
6720 | code = GTU; | |
6721 | /* ... fall through ... */ | |
6722 | } | |
6723 | else | |
6724 | break; | |
6725 | ||
230d793d RS |
6726 | case GTU: |
6727 | /* unsigned > 0 is equivalent to != 0 */ | |
6728 | if (const_op == 0) | |
6729 | code = NE; | |
6730 | break; | |
6731 | } | |
6732 | ||
6733 | /* Compute some predicates to simplify code below. */ | |
6734 | ||
6735 | equality_comparison_p = (code == EQ || code == NE); | |
6736 | sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0); | |
6737 | unsigned_comparison_p = (code == LTU || code == LEU || code == GTU | |
6738 | || code == LEU); | |
6739 | ||
6740 | /* Now try cases based on the opcode of OP0. If none of the cases | |
6741 | does a "continue", we exit this loop immediately after the | |
6742 | switch. */ | |
6743 | ||
6744 | switch (GET_CODE (op0)) | |
6745 | { | |
6746 | case ZERO_EXTRACT: | |
6747 | /* If we are extracting a single bit from a variable position in | |
6748 | a constant that has only a single bit set and are comparing it | |
6749 | with zero, we can convert this into an equality comparison | |
6750 | between the position and the location of the single bit. We can't | |
6751 | do this if bit endian and we don't have an extzv since we then | |
6752 | can't know what mode to use for the endianness adjustment. */ | |
6753 | ||
6754 | #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv) | |
6755 | if (GET_CODE (XEXP (op0, 0)) == CONST_INT | |
6756 | && XEXP (op0, 1) == const1_rtx | |
6757 | && equality_comparison_p && const_op == 0 | |
6758 | && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0) | |
6759 | { | |
6760 | #if BITS_BIG_ENDIAN | |
6761 | i = (GET_MODE_BITSIZE | |
6762 | (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i); | |
6763 | #endif | |
6764 | ||
6765 | op0 = XEXP (op0, 2); | |
6766 | op1 = gen_rtx (CONST_INT, VOIDmode, i); | |
6767 | const_op = i; | |
6768 | ||
6769 | /* Result is nonzero iff shift count is equal to I. */ | |
6770 | code = reverse_condition (code); | |
6771 | continue; | |
6772 | } | |
6773 | #endif | |
6774 | ||
6775 | /* ... fall through ... */ | |
6776 | ||
6777 | case SIGN_EXTRACT: | |
6778 | tem = expand_compound_operation (op0); | |
6779 | if (tem != op0) | |
6780 | { | |
6781 | op0 = tem; | |
6782 | continue; | |
6783 | } | |
6784 | break; | |
6785 | ||
6786 | case NOT: | |
6787 | /* If testing for equality, we can take the NOT of the constant. */ | |
6788 | if (equality_comparison_p | |
6789 | && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0) | |
6790 | { | |
6791 | op0 = XEXP (op0, 0); | |
6792 | op1 = tem; | |
6793 | continue; | |
6794 | } | |
6795 | ||
6796 | /* If just looking at the sign bit, reverse the sense of the | |
6797 | comparison. */ | |
6798 | if (sign_bit_comparison_p) | |
6799 | { | |
6800 | op0 = XEXP (op0, 0); | |
6801 | code = (code == GE ? LT : GE); | |
6802 | continue; | |
6803 | } | |
6804 | break; | |
6805 | ||
6806 | case NEG: | |
6807 | /* If testing for equality, we can take the NEG of the constant. */ | |
6808 | if (equality_comparison_p | |
6809 | && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0) | |
6810 | { | |
6811 | op0 = XEXP (op0, 0); | |
6812 | op1 = tem; | |
6813 | continue; | |
6814 | } | |
6815 | ||
6816 | /* The remaining cases only apply to comparisons with zero. */ | |
6817 | if (const_op != 0) | |
6818 | break; | |
6819 | ||
6820 | /* When X is ABS or is known positive, | |
6821 | (neg X) is < 0 if and only if X != 0. */ | |
6822 | ||
6823 | if (sign_bit_comparison_p | |
6824 | && (GET_CODE (XEXP (op0, 0)) == ABS | |
6825 | || (mode_width <= HOST_BITS_PER_INT | |
6826 | && (significant_bits (XEXP (op0, 0), mode) | |
6827 | & (1 << (mode_width - 1))) == 0))) | |
6828 | { | |
6829 | op0 = XEXP (op0, 0); | |
6830 | code = (code == LT ? NE : EQ); | |
6831 | continue; | |
6832 | } | |
6833 | ||
6834 | /* If we have NEG of something that is the result of a | |
6835 | SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the | |
6836 | two high-order bits must be the same and hence that | |
6837 | "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't | |
6838 | do this. */ | |
6839 | if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND | |
6840 | || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT | |
6841 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
6842 | && (INTVAL (XEXP (XEXP (op0, 0), 1)) | |
6843 | < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0))))) | |
6844 | || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
6845 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
6846 | && XEXP (XEXP (op0, 0), 1) != const0_rtx) | |
6847 | || ((tem = get_last_value (XEXP (op0, 0))) != 0 | |
6848 | && (GET_CODE (tem) == SIGN_EXTEND | |
6849 | || (GET_CODE (tem) == SIGN_EXTRACT | |
6850 | && GET_CODE (XEXP (tem, 1)) == CONST_INT | |
6851 | && (INTVAL (XEXP (tem, 1)) | |
6852 | < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0))))) | |
6853 | || (GET_CODE (tem) == ASHIFTRT | |
6854 | && GET_CODE (XEXP (tem, 1)) == CONST_INT | |
6855 | && XEXP (tem, 1) != const0_rtx)))) | |
6856 | { | |
6857 | op0 = XEXP (op0, 0); | |
6858 | code = swap_condition (code); | |
6859 | continue; | |
6860 | } | |
6861 | break; | |
6862 | ||
6863 | case ROTATE: | |
6864 | /* If we are testing equality and our count is a constant, we | |
6865 | can perform the inverse operation on our RHS. */ | |
6866 | if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
6867 | && (tem = simplify_binary_operation (ROTATERT, mode, | |
6868 | op1, XEXP (op0, 1))) != 0) | |
6869 | { | |
6870 | op0 = XEXP (op0, 0); | |
6871 | op1 = tem; | |
6872 | continue; | |
6873 | } | |
6874 | ||
6875 | /* If we are doing a < 0 or >= 0 comparison, it means we are testing | |
6876 | a particular bit. Convert it to an AND of a constant of that | |
6877 | bit. This will be converted into a ZERO_EXTRACT. */ | |
6878 | if (const_op == 0 && sign_bit_comparison_p | |
6879 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
6880 | && mode_width <= HOST_BITS_PER_INT) | |
6881 | { | |
6882 | op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), | |
6883 | 1 << (mode_width - 1 | |
6884 | - INTVAL (XEXP (op0, 1)))); | |
6885 | code = (code == LT ? NE : EQ); | |
6886 | continue; | |
6887 | } | |
6888 | ||
6889 | /* ... fall through ... */ | |
6890 | ||
6891 | case ABS: | |
6892 | /* ABS is ignorable inside an equality comparison with zero. */ | |
6893 | if (const_op == 0 && equality_comparison_p) | |
6894 | { | |
6895 | op0 = XEXP (op0, 0); | |
6896 | continue; | |
6897 | } | |
6898 | break; | |
6899 | ||
6900 | ||
6901 | case SIGN_EXTEND: | |
6902 | /* Can simplify (compare (zero/sign_extend FOO) CONST) | |
6903 | to (compare FOO CONST) if CONST fits in FOO's mode and we | |
6904 | are either testing inequality or have an unsigned comparison | |
6905 | with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */ | |
6906 | if (! unsigned_comparison_p | |
6907 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) | |
6908 | <= HOST_BITS_PER_INT) | |
6909 | && ((unsigned) const_op | |
6910 | < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))) | |
6911 | { | |
6912 | op0 = XEXP (op0, 0); | |
6913 | continue; | |
6914 | } | |
6915 | break; | |
6916 | ||
6917 | case SUBREG: | |
6918 | /* If the inner mode is smaller and we are extracting the low | |
6919 | part, we can treat the SUBREG as if it were a ZERO_EXTEND. */ | |
6920 | if (! subreg_lowpart_p (op0) | |
6921 | || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) >= mode_width) | |
6922 | break; | |
6923 | ||
6924 | /* ... fall through ... */ | |
6925 | ||
6926 | case ZERO_EXTEND: | |
6927 | if ((unsigned_comparison_p || equality_comparison_p) | |
6928 | && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) | |
6929 | <= HOST_BITS_PER_INT) | |
6930 | && ((unsigned) const_op | |
6931 | < GET_MODE_MASK (GET_MODE (XEXP (op0, 0))))) | |
6932 | { | |
6933 | op0 = XEXP (op0, 0); | |
6934 | continue; | |
6935 | } | |
6936 | break; | |
6937 | ||
6938 | case PLUS: | |
6939 | /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do | |
5089e22e | 6940 | this for equality comparisons due to pathological cases involving |
230d793d RS |
6941 | overflows. */ |
6942 | if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
6943 | && (tem = simplify_binary_operation (MINUS, mode, op1, | |
6944 | XEXP (op0, 1))) != 0) | |
6945 | { | |
6946 | op0 = XEXP (op0, 0); | |
6947 | op1 = tem; | |
6948 | continue; | |
6949 | } | |
6950 | ||
6951 | /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */ | |
6952 | if (const_op == 0 && XEXP (op0, 1) == constm1_rtx | |
6953 | && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p) | |
6954 | { | |
6955 | op0 = XEXP (XEXP (op0, 0), 0); | |
6956 | code = (code == LT ? EQ : NE); | |
6957 | continue; | |
6958 | } | |
6959 | break; | |
6960 | ||
6961 | case MINUS: | |
6962 | /* The sign bit of (minus (ashiftrt X C) X), where C is the number | |
6963 | of bits in X minus 1, is one iff X > 0. */ | |
6964 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT | |
6965 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
6966 | && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1 | |
6967 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
6968 | { | |
6969 | op0 = XEXP (op0, 1); | |
6970 | code = (code == GE ? LE : GT); | |
6971 | continue; | |
6972 | } | |
6973 | break; | |
6974 | ||
6975 | case XOR: | |
6976 | /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification | |
6977 | if C is zero or B is a constant. */ | |
6978 | if (equality_comparison_p | |
6979 | && 0 != (tem = simplify_binary_operation (XOR, mode, | |
6980 | XEXP (op0, 1), op1))) | |
6981 | { | |
6982 | op0 = XEXP (op0, 0); | |
6983 | op1 = tem; | |
6984 | continue; | |
6985 | } | |
6986 | break; | |
6987 | ||
6988 | case EQ: case NE: | |
6989 | case LT: case LTU: case LE: case LEU: | |
6990 | case GT: case GTU: case GE: case GEU: | |
6991 | /* We can't do anything if OP0 is a condition code value, rather | |
6992 | than an actual data value. */ | |
6993 | if (const_op != 0 | |
6994 | #ifdef HAVE_cc0 | |
6995 | || XEXP (op0, 0) == cc0_rtx | |
6996 | #endif | |
6997 | || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC) | |
6998 | break; | |
6999 | ||
7000 | /* Get the two operands being compared. */ | |
7001 | if (GET_CODE (XEXP (op0, 0)) == COMPARE) | |
7002 | tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1); | |
7003 | else | |
7004 | tem = XEXP (op0, 0), tem1 = XEXP (op0, 1); | |
7005 | ||
7006 | /* Check for the cases where we simply want the result of the | |
7007 | earlier test or the opposite of that result. */ | |
7008 | if (code == NE | |
7009 | || (code == EQ && reversible_comparison_p (op0)) | |
7010 | || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT | |
3f508eca | 7011 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT |
230d793d RS |
7012 | && (STORE_FLAG_VALUE |
7013 | & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))) | |
7014 | && (code == LT | |
7015 | || (code == GE && reversible_comparison_p (op0))))) | |
7016 | { | |
7017 | code = (code == LT || code == NE | |
7018 | ? GET_CODE (op0) : reverse_condition (GET_CODE (op0))); | |
7019 | op0 = tem, op1 = tem1; | |
7020 | continue; | |
7021 | } | |
7022 | break; | |
7023 | ||
7024 | case IOR: | |
7025 | /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero | |
7026 | iff X <= 0. */ | |
7027 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS | |
7028 | && XEXP (XEXP (op0, 0), 1) == constm1_rtx | |
7029 | && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1))) | |
7030 | { | |
7031 | op0 = XEXP (op0, 1); | |
7032 | code = (code == GE ? GT : LE); | |
7033 | continue; | |
7034 | } | |
7035 | break; | |
7036 | ||
7037 | case AND: | |
7038 | /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This | |
7039 | will be converted to a ZERO_EXTRACT later. */ | |
7040 | if (const_op == 0 && equality_comparison_p | |
7041 | && (GET_CODE (XEXP (op0, 0)) == ASHIFT | |
7042 | || GET_CODE (XEXP (op0, 0)) == LSHIFT) | |
7043 | && XEXP (XEXP (op0, 0), 0) == const1_rtx) | |
7044 | { | |
7045 | op0 = simplify_and_const_int | |
7046 | (op0, mode, gen_rtx_combine (LSHIFTRT, mode, | |
7047 | XEXP (op0, 1), | |
7048 | XEXP (XEXP (op0, 0), 1)), | |
7049 | 1); | |
7050 | continue; | |
7051 | } | |
7052 | ||
7053 | /* If we are comparing (and (lshiftrt X C1) C2) for equality with | |
7054 | zero and X is a comparison and C1 and C2 describe only bits set | |
7055 | in STORE_FLAG_VALUE, we can compare with X. */ | |
7056 | if (const_op == 0 && equality_comparison_p | |
7057 | && mode_width <= HOST_BITS_PER_INT | |
7058 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7059 | && GET_CODE (XEXP (op0, 0)) == LSHIFTRT | |
7060 | && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT | |
7061 | && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0 | |
7062 | && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_INT) | |
7063 | { | |
7064 | mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
7065 | << INTVAL (XEXP (XEXP (op0, 0), 1))); | |
7066 | if ((~ STORE_FLAG_VALUE & mask) == 0 | |
7067 | && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<' | |
7068 | || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0 | |
7069 | && GET_RTX_CLASS (GET_CODE (tem)) == '<'))) | |
7070 | { | |
7071 | op0 = XEXP (XEXP (op0, 0), 0); | |
7072 | continue; | |
7073 | } | |
7074 | } | |
7075 | ||
7076 | /* If we are doing an equality comparison of an AND of a bit equal | |
7077 | to the sign bit, replace this with a LT or GE comparison of | |
7078 | the underlying value. */ | |
7079 | if (equality_comparison_p | |
7080 | && const_op == 0 | |
7081 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7082 | && mode_width <= HOST_BITS_PER_INT | |
7083 | && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode)) | |
7084 | == 1 << (mode_width - 1))) | |
7085 | { | |
7086 | op0 = XEXP (op0, 0); | |
7087 | code = (code == EQ ? GE : LT); | |
7088 | continue; | |
7089 | } | |
7090 | ||
7091 | /* If this AND operation is really a ZERO_EXTEND from a narrower | |
7092 | mode, the constant fits within that mode, and this is either an | |
7093 | equality or unsigned comparison, try to do this comparison in | |
7094 | the narrower mode. */ | |
7095 | if ((equality_comparison_p || unsigned_comparison_p) | |
7096 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7097 | && (i = exact_log2 ((INTVAL (XEXP (op0, 1)) | |
7098 | & GET_MODE_MASK (mode)) | |
7099 | + 1)) >= 0 | |
7100 | && const_op >> i == 0 | |
7101 | && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode) | |
7102 | { | |
7103 | op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0)); | |
7104 | continue; | |
7105 | } | |
7106 | break; | |
7107 | ||
7108 | case ASHIFT: | |
7109 | case LSHIFT: | |
7110 | /* If we have (compare (xshift FOO N) (const_int C)) and | |
7111 | the high order N bits of FOO (N+1 if an inequality comparison) | |
7112 | are not significant, we can do this by comparing FOO with C | |
7113 | shifted right N bits so long as the low-order N bits of C are | |
7114 | zero. */ | |
7115 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7116 | && INTVAL (XEXP (op0, 1)) >= 0 | |
7117 | && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p) | |
7118 | < HOST_BITS_PER_INT) | |
7119 | && (const_op & ~ ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 | |
7120 | && mode_width <= HOST_BITS_PER_INT | |
7121 | && (significant_bits (XEXP (op0, 0), mode) | |
7122 | & ~ (mask >> (INTVAL (XEXP (op0, 1)) | |
7123 | + ! equality_comparison_p))) == 0) | |
7124 | { | |
7125 | const_op >>= INTVAL (XEXP (op0, 1)); | |
7126 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
7127 | op0 = XEXP (op0, 0); | |
7128 | continue; | |
7129 | } | |
7130 | ||
dfbe1b2f | 7131 | /* If we are doing a sign bit comparison, it means we are testing |
230d793d | 7132 | a particular bit. Convert it to the appropriate AND. */ |
dfbe1b2f | 7133 | if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT |
230d793d RS |
7134 | && mode_width <= HOST_BITS_PER_INT) |
7135 | { | |
7136 | op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), | |
7137 | 1 << ( mode_width - 1 | |
7138 | - INTVAL (XEXP (op0, 1)))); | |
7139 | code = (code == LT ? NE : EQ); | |
7140 | continue; | |
7141 | } | |
dfbe1b2f RK |
7142 | |
7143 | /* If this an equality comparison with zero and we are shifting | |
7144 | the low bit to the sign bit, we can convert this to an AND of the | |
7145 | low-order bit. */ | |
7146 | if (const_op == 0 && equality_comparison_p | |
7147 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7148 | && INTVAL (XEXP (op0, 1)) == mode_width - 1) | |
7149 | { | |
7150 | op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), 1); | |
7151 | continue; | |
7152 | } | |
230d793d RS |
7153 | break; |
7154 | ||
7155 | case ASHIFTRT: | |
7156 | /* If OP0 is a sign extension and CODE is not an unsigned comparison, | |
7157 | do the comparison in a narrower mode. */ | |
7158 | if (! unsigned_comparison_p | |
7159 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7160 | && GET_CODE (XEXP (op0, 0)) == ASHIFT | |
7161 | && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1) | |
7162 | && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), | |
7163 | MODE_INT, 1)) != VOIDmode | |
7164 | && ((unsigned) const_op <= GET_MODE_MASK (tmode) | |
7165 | || (unsigned) - const_op <= GET_MODE_MASK (tmode))) | |
7166 | { | |
7167 | op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0)); | |
7168 | continue; | |
7169 | } | |
7170 | ||
7171 | /* ... fall through ... */ | |
7172 | case LSHIFTRT: | |
7173 | /* If we have (compare (xshiftrt FOO N) (const_int C)) and | |
7174 | the low order N bits of FOO are not significant, we can do this | |
7175 | by comparing FOO with C shifted left N bits so long as no | |
7176 | overflow occurs. */ | |
7177 | if (GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7178 | && INTVAL (XEXP (op0, 1)) >= 0 | |
7179 | && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT | |
7180 | && mode_width <= HOST_BITS_PER_INT | |
7181 | && (significant_bits (XEXP (op0, 0), mode) | |
7182 | & ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0 | |
7183 | && (const_op == 0 | |
7184 | || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1)) | |
7185 | < mode_width))) | |
7186 | { | |
7187 | const_op <<= INTVAL (XEXP (op0, 1)); | |
7188 | op1 = gen_rtx (CONST_INT, VOIDmode, const_op); | |
7189 | op0 = XEXP (op0, 0); | |
7190 | continue; | |
7191 | } | |
7192 | ||
7193 | /* If we are using this shift to extract just the sign bit, we | |
7194 | can replace this with an LT or GE comparison. */ | |
7195 | if (const_op == 0 | |
7196 | && (equality_comparison_p || sign_bit_comparison_p) | |
7197 | && GET_CODE (XEXP (op0, 1)) == CONST_INT | |
7198 | && INTVAL (XEXP (op0, 1)) == mode_width - 1) | |
7199 | { | |
7200 | op0 = XEXP (op0, 0); | |
7201 | code = (code == NE || code == GT ? LT : GE); | |
7202 | continue; | |
7203 | } | |
7204 | break; | |
7205 | } | |
7206 | ||
7207 | break; | |
7208 | } | |
7209 | ||
7210 | /* Now make any compound operations involved in this comparison. Then, | |
7211 | check for an outmost SUBREG on OP0 that isn't doing anything or is | |
7212 | paradoxical. The latter case can only occur when it is known that the | |
7213 | "extra" bits will be zero. Therefore, it is safe to remove the SUBREG. | |
7214 | We can never remove a SUBREG for a non-equality comparison because the | |
7215 | sign bit is in a different place in the underlying object. */ | |
7216 | ||
7217 | op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET); | |
7218 | op1 = make_compound_operation (op1, SET); | |
7219 | ||
7220 | if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
7221 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
7222 | && (code == NE || code == EQ) | |
7223 | && ((GET_MODE_SIZE (GET_MODE (op0)) | |
7224 | > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))) | |
7225 | { | |
7226 | op0 = SUBREG_REG (op0); | |
7227 | op1 = gen_lowpart_for_combine (GET_MODE (op0), op1); | |
7228 | } | |
7229 | ||
7230 | else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) | |
7231 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT | |
7232 | && (code == NE || code == EQ) | |
7233 | && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT | |
7234 | && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0))) | |
7235 | & ~ GET_MODE_MASK (GET_MODE (op0))) == 0 | |
7236 | && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), | |
7237 | op1), | |
7238 | (significant_bits (tem, GET_MODE (SUBREG_REG (op0))) | |
7239 | & ~ GET_MODE_MASK (GET_MODE (op0))) == 0)) | |
7240 | op0 = SUBREG_REG (op0), op1 = tem; | |
7241 | ||
7242 | /* We now do the opposite procedure: Some machines don't have compare | |
7243 | insns in all modes. If OP0's mode is an integer mode smaller than a | |
7244 | word and we can't do a compare in that mode, see if there is a larger | |
7245 | mode for which we can do the compare and where the only significant | |
7246 | bits in OP0 and OP1 are those in the narrower mode. We can do | |
7247 | this if this is an equality comparison, in which case we can | |
7248 | merely widen the operation, or if we are testing the sign bit, in | |
7249 | which case we can explicitly put in the test. */ | |
7250 | ||
7251 | mode = GET_MODE (op0); | |
7252 | if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT | |
7253 | && GET_MODE_SIZE (mode) < UNITS_PER_WORD | |
7254 | && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing) | |
7255 | for (tmode = GET_MODE_WIDER_MODE (mode); | |
7256 | tmode != VOIDmode && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_INT; | |
7257 | tmode = GET_MODE_WIDER_MODE (tmode)) | |
7258 | if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing | |
7259 | && (significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0 | |
7260 | && (significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0 | |
7261 | && (code == EQ || code == NE | |
7262 | || (op1 == const0_rtx && (code == LT || code == GE) | |
7263 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT))) | |
7264 | { | |
7265 | op0 = gen_lowpart_for_combine (tmode, op0); | |
7266 | op1 = gen_lowpart_for_combine (tmode, op1); | |
7267 | ||
7268 | if (code == LT || code == GE) | |
7269 | { | |
7270 | op0 = gen_binary (AND, tmode, op0, | |
7271 | gen_rtx (CONST_INT, VOIDmode, | |
7272 | 1 << (GET_MODE_BITSIZE (mode) - 1))); | |
7273 | code = (code == LT) ? NE : EQ; | |
7274 | } | |
7275 | ||
7276 | break; | |
7277 | } | |
7278 | ||
7279 | *pop0 = op0; | |
7280 | *pop1 = op1; | |
7281 | ||
7282 | return code; | |
7283 | } | |
7284 | \f | |
7285 | /* Return 1 if we know that X, a comparison operation, is not operating | |
7286 | on a floating-point value or is EQ or NE, meaning that we can safely | |
7287 | reverse it. */ | |
7288 | ||
7289 | static int | |
7290 | reversible_comparison_p (x) | |
7291 | rtx x; | |
7292 | { | |
7293 | if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT | |
7294 | || GET_CODE (x) == NE || GET_CODE (x) == EQ) | |
7295 | return 1; | |
7296 | ||
7297 | switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0)))) | |
7298 | { | |
7299 | case MODE_INT: | |
7300 | return 1; | |
7301 | ||
7302 | case MODE_CC: | |
7303 | x = get_last_value (XEXP (x, 0)); | |
7304 | return (x && GET_CODE (x) == COMPARE | |
7305 | && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT); | |
7306 | } | |
7307 | ||
7308 | return 0; | |
7309 | } | |
7310 | \f | |
7311 | /* Utility function for following routine. Called when X is part of a value | |
7312 | being stored into reg_last_set_value. Sets reg_last_set_table_tick | |
7313 | for each register mentioned. Similar to mention_regs in cse.c */ | |
7314 | ||
7315 | static void | |
7316 | update_table_tick (x) | |
7317 | rtx x; | |
7318 | { | |
7319 | register enum rtx_code code = GET_CODE (x); | |
7320 | register char *fmt = GET_RTX_FORMAT (code); | |
7321 | register int i; | |
7322 | ||
7323 | if (code == REG) | |
7324 | { | |
7325 | int regno = REGNO (x); | |
7326 | int endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
7327 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
7328 | ||
7329 | for (i = regno; i < endregno; i++) | |
7330 | reg_last_set_table_tick[i] = label_tick; | |
7331 | ||
7332 | return; | |
7333 | } | |
7334 | ||
7335 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7336 | /* Note that we can't have an "E" in values stored; see | |
7337 | get_last_value_validate. */ | |
7338 | if (fmt[i] == 'e') | |
7339 | update_table_tick (XEXP (x, i)); | |
7340 | } | |
7341 | ||
7342 | /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we | |
7343 | are saying that the register is clobbered and we no longer know its | |
7344 | value. If INSN is zero, don't update reg_last_set; this call is normally | |
7345 | done with VALUE also zero to invalidate the register. */ | |
7346 | ||
7347 | static void | |
7348 | record_value_for_reg (reg, insn, value) | |
7349 | rtx reg; | |
7350 | rtx insn; | |
7351 | rtx value; | |
7352 | { | |
7353 | int regno = REGNO (reg); | |
7354 | int endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
7355 | ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1); | |
7356 | int i; | |
7357 | ||
7358 | /* If VALUE contains REG and we have a previous value for REG, substitute | |
7359 | the previous value. */ | |
7360 | if (value && insn && reg_overlap_mentioned_p (reg, value)) | |
7361 | { | |
7362 | rtx tem; | |
7363 | ||
7364 | /* Set things up so get_last_value is allowed to see anything set up to | |
7365 | our insn. */ | |
7366 | subst_low_cuid = INSN_CUID (insn); | |
7367 | tem = get_last_value (reg); | |
7368 | ||
7369 | if (tem) | |
7370 | value = replace_rtx (copy_rtx (value), reg, tem); | |
7371 | } | |
7372 | ||
7373 | /* For each register modified, show we don't know its value, that | |
7374 | its value has been updated, and that we don't know the location of | |
7375 | the death of the register. */ | |
7376 | for (i = regno; i < endregno; i ++) | |
7377 | { | |
7378 | if (insn) | |
7379 | reg_last_set[i] = insn; | |
7380 | reg_last_set_value[i] = 0; | |
7381 | reg_last_death[i] = 0; | |
7382 | } | |
7383 | ||
7384 | /* Mark registers that are being referenced in this value. */ | |
7385 | if (value) | |
7386 | update_table_tick (value); | |
7387 | ||
7388 | /* Now update the status of each register being set. | |
7389 | If someone is using this register in this block, set this register | |
7390 | to invalid since we will get confused between the two lives in this | |
7391 | basic block. This makes using this register always invalid. In cse, we | |
7392 | scan the table to invalidate all entries using this register, but this | |
7393 | is too much work for us. */ | |
7394 | ||
7395 | for (i = regno; i < endregno; i++) | |
7396 | { | |
7397 | reg_last_set_label[i] = label_tick; | |
7398 | if (value && reg_last_set_table_tick[i] == label_tick) | |
7399 | reg_last_set_invalid[i] = 1; | |
7400 | else | |
7401 | reg_last_set_invalid[i] = 0; | |
7402 | } | |
7403 | ||
7404 | /* The value being assigned might refer to X (like in "x++;"). In that | |
7405 | case, we must replace it with (clobber (const_int 0)) to prevent | |
7406 | infinite loops. */ | |
7407 | if (value && ! get_last_value_validate (&value, | |
7408 | reg_last_set_label[regno], 0)) | |
7409 | { | |
7410 | value = copy_rtx (value); | |
7411 | if (! get_last_value_validate (&value, reg_last_set_label[regno], 1)) | |
7412 | value = 0; | |
7413 | } | |
7414 | ||
7415 | /* For the main register being modified, update the value. */ | |
7416 | reg_last_set_value[regno] = value; | |
7417 | ||
7418 | } | |
7419 | ||
7420 | /* Used for communication between the following two routines. */ | |
7421 | static rtx record_dead_insn; | |
7422 | ||
7423 | /* Called via note_stores from record_dead_and_set_regs to handle one | |
7424 | SET or CLOBBER in an insn. */ | |
7425 | ||
7426 | static void | |
7427 | record_dead_and_set_regs_1 (dest, setter) | |
7428 | rtx dest, setter; | |
7429 | { | |
7430 | if (GET_CODE (dest) == REG) | |
7431 | { | |
7432 | /* If we are setting the whole register, we know its value. Otherwise | |
7433 | show that we don't know the value. We can handle SUBREG in | |
7434 | some cases. */ | |
7435 | if (GET_CODE (setter) == SET && dest == SET_DEST (setter)) | |
7436 | record_value_for_reg (dest, record_dead_insn, SET_SRC (setter)); | |
7437 | else if (GET_CODE (setter) == SET | |
7438 | && GET_CODE (SET_DEST (setter)) == SUBREG | |
7439 | && SUBREG_REG (SET_DEST (setter)) == dest | |
7440 | && subreg_lowpart_p (SET_DEST (setter))) | |
7441 | record_value_for_reg | |
7442 | (dest, record_dead_insn, | |
7443 | gen_lowpart_for_combine (GET_MODE (SET_DEST (setter)), | |
7444 | SET_SRC (setter))); | |
7445 | else | |
7446 | record_value_for_reg (dest, record_dead_insn, 0); | |
7447 | } | |
7448 | else if (GET_CODE (dest) == MEM | |
7449 | /* Ignore pushes, they clobber nothing. */ | |
7450 | && ! push_operand (dest, GET_MODE (dest))) | |
7451 | mem_last_set = INSN_CUID (record_dead_insn); | |
7452 | } | |
7453 | ||
7454 | /* Update the records of when each REG was most recently set or killed | |
7455 | for the things done by INSN. This is the last thing done in processing | |
7456 | INSN in the combiner loop. | |
7457 | ||
7458 | We update reg_last_set, reg_last_set_value, reg_last_death, and also the | |
7459 | similar information mem_last_set (which insn most recently modified memory) | |
7460 | and last_call_cuid (which insn was the most recent subroutine call). */ | |
7461 | ||
7462 | static void | |
7463 | record_dead_and_set_regs (insn) | |
7464 | rtx insn; | |
7465 | { | |
7466 | register rtx link; | |
7467 | for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) | |
7468 | { | |
7469 | if (REG_NOTE_KIND (link) == REG_DEAD) | |
7470 | reg_last_death[REGNO (XEXP (link, 0))] = insn; | |
7471 | else if (REG_NOTE_KIND (link) == REG_INC) | |
7472 | record_value_for_reg (XEXP (link, 0), insn, 0); | |
7473 | } | |
7474 | ||
7475 | if (GET_CODE (insn) == CALL_INSN) | |
7476 | last_call_cuid = mem_last_set = INSN_CUID (insn); | |
7477 | ||
7478 | record_dead_insn = insn; | |
7479 | note_stores (PATTERN (insn), record_dead_and_set_regs_1); | |
7480 | } | |
7481 | \f | |
7482 | /* Utility routine for the following function. Verify that all the registers | |
7483 | mentioned in *LOC are valid when *LOC was part of a value set when | |
7484 | label_tick == TICK. Return 0 if some are not. | |
7485 | ||
7486 | If REPLACE is non-zero, replace the invalid reference with | |
7487 | (clobber (const_int 0)) and return 1. This replacement is useful because | |
7488 | we often can get useful information about the form of a value (e.g., if | |
7489 | it was produced by a shift that always produces -1 or 0) even though | |
7490 | we don't know exactly what registers it was produced from. */ | |
7491 | ||
7492 | static int | |
7493 | get_last_value_validate (loc, tick, replace) | |
7494 | rtx *loc; | |
7495 | int tick; | |
7496 | int replace; | |
7497 | { | |
7498 | rtx x = *loc; | |
7499 | char *fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
7500 | int len = GET_RTX_LENGTH (GET_CODE (x)); | |
7501 | int i; | |
7502 | ||
7503 | if (GET_CODE (x) == REG) | |
7504 | { | |
7505 | int regno = REGNO (x); | |
7506 | int endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
7507 | ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1); | |
7508 | int j; | |
7509 | ||
7510 | for (j = regno; j < endregno; j++) | |
7511 | if (reg_last_set_invalid[j] | |
7512 | /* If this is a pseudo-register that was only set once, it is | |
7513 | always valid. */ | |
7514 | || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1) | |
7515 | && reg_last_set_label[j] > tick)) | |
7516 | { | |
7517 | if (replace) | |
7518 | *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx); | |
7519 | return replace; | |
7520 | } | |
7521 | ||
7522 | return 1; | |
7523 | } | |
7524 | ||
7525 | for (i = 0; i < len; i++) | |
7526 | if ((fmt[i] == 'e' | |
7527 | && get_last_value_validate (&XEXP (x, i), tick, replace) == 0) | |
7528 | /* Don't bother with these. They shouldn't occur anyway. */ | |
7529 | || fmt[i] == 'E') | |
7530 | return 0; | |
7531 | ||
7532 | /* If we haven't found a reason for it to be invalid, it is valid. */ | |
7533 | return 1; | |
7534 | } | |
7535 | ||
7536 | /* Get the last value assigned to X, if known. Some registers | |
7537 | in the value may be replaced with (clobber (const_int 0)) if their value | |
7538 | is known longer known reliably. */ | |
7539 | ||
7540 | static rtx | |
7541 | get_last_value (x) | |
7542 | rtx x; | |
7543 | { | |
7544 | int regno; | |
7545 | rtx value; | |
7546 | ||
7547 | /* If this is a non-paradoxical SUBREG, get the value of its operand and | |
7548 | then convert it to the desired mode. If this is a paradoxical SUBREG, | |
7549 | we cannot predict what values the "extra" bits might have. */ | |
7550 | if (GET_CODE (x) == SUBREG | |
7551 | && subreg_lowpart_p (x) | |
7552 | && (GET_MODE_SIZE (GET_MODE (x)) | |
7553 | <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) | |
7554 | && (value = get_last_value (SUBREG_REG (x))) != 0) | |
7555 | return gen_lowpart_for_combine (GET_MODE (x), value); | |
7556 | ||
7557 | if (GET_CODE (x) != REG) | |
7558 | return 0; | |
7559 | ||
7560 | regno = REGNO (x); | |
7561 | value = reg_last_set_value[regno]; | |
7562 | ||
7563 | /* If we don't have a value, it isn't for this basic block, or if it was | |
7564 | set in a later insn that the ones we are processing, return 0. */ | |
7565 | ||
7566 | if (value == 0 | |
7567 | || (reg_n_sets[regno] != 1 | |
7568 | && (reg_last_set_label[regno] != label_tick | |
7569 | || INSN_CUID (reg_last_set[regno]) >= subst_low_cuid))) | |
7570 | return 0; | |
7571 | ||
7572 | /* If the value has all its register valid, return it. */ | |
7573 | if (get_last_value_validate (&value, reg_last_set_label[regno], 0)) | |
7574 | return value; | |
7575 | ||
7576 | /* Otherwise, make a copy and replace any invalid register with | |
7577 | (clobber (const_int 0)). If that fails for some reason, return 0. */ | |
7578 | ||
7579 | value = copy_rtx (value); | |
7580 | if (get_last_value_validate (&value, reg_last_set_label[regno], 1)) | |
7581 | return value; | |
7582 | ||
7583 | return 0; | |
7584 | } | |
7585 | \f | |
7586 | /* Return nonzero if expression X refers to a REG or to memory | |
7587 | that is set in an instruction more recent than FROM_CUID. */ | |
7588 | ||
7589 | static int | |
7590 | use_crosses_set_p (x, from_cuid) | |
7591 | register rtx x; | |
7592 | int from_cuid; | |
7593 | { | |
7594 | register char *fmt; | |
7595 | register int i; | |
7596 | register enum rtx_code code = GET_CODE (x); | |
7597 | ||
7598 | if (code == REG) | |
7599 | { | |
7600 | register int regno = REGNO (x); | |
7601 | #ifdef PUSH_ROUNDING | |
7602 | /* Don't allow uses of the stack pointer to be moved, | |
7603 | because we don't know whether the move crosses a push insn. */ | |
7604 | if (regno == STACK_POINTER_REGNUM) | |
7605 | return 1; | |
7606 | #endif | |
7607 | return (reg_last_set[regno] | |
7608 | && INSN_CUID (reg_last_set[regno]) > from_cuid); | |
7609 | } | |
7610 | ||
7611 | if (code == MEM && mem_last_set > from_cuid) | |
7612 | return 1; | |
7613 | ||
7614 | fmt = GET_RTX_FORMAT (code); | |
7615 | ||
7616 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7617 | { | |
7618 | if (fmt[i] == 'E') | |
7619 | { | |
7620 | register int j; | |
7621 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7622 | if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid)) | |
7623 | return 1; | |
7624 | } | |
7625 | else if (fmt[i] == 'e' | |
7626 | && use_crosses_set_p (XEXP (x, i), from_cuid)) | |
7627 | return 1; | |
7628 | } | |
7629 | return 0; | |
7630 | } | |
7631 | \f | |
7632 | /* Define three variables used for communication between the following | |
7633 | routines. */ | |
7634 | ||
7635 | static int reg_dead_regno, reg_dead_endregno; | |
7636 | static int reg_dead_flag; | |
7637 | ||
7638 | /* Function called via note_stores from reg_dead_at_p. | |
7639 | ||
7640 | If DEST is within [reg_dead_rengno, reg_dead_endregno), set | |
7641 | reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */ | |
7642 | ||
7643 | static void | |
7644 | reg_dead_at_p_1 (dest, x) | |
7645 | rtx dest; | |
7646 | rtx x; | |
7647 | { | |
7648 | int regno, endregno; | |
7649 | ||
7650 | if (GET_CODE (dest) != REG) | |
7651 | return; | |
7652 | ||
7653 | regno = REGNO (dest); | |
7654 | endregno = regno + (regno < FIRST_PSEUDO_REGISTER | |
7655 | ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1); | |
7656 | ||
7657 | if (reg_dead_endregno > regno && reg_dead_regno < endregno) | |
7658 | reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1; | |
7659 | } | |
7660 | ||
7661 | /* Return non-zero if REG is known to be dead at INSN. | |
7662 | ||
7663 | We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER | |
7664 | referencing REG, it is dead. If we hit a SET referencing REG, it is | |
7665 | live. Otherwise, see if it is live or dead at the start of the basic | |
7666 | block we are in. */ | |
7667 | ||
7668 | static int | |
7669 | reg_dead_at_p (reg, insn) | |
7670 | rtx reg; | |
7671 | rtx insn; | |
7672 | { | |
7673 | int block, i; | |
7674 | ||
7675 | /* Set variables for reg_dead_at_p_1. */ | |
7676 | reg_dead_regno = REGNO (reg); | |
7677 | reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER | |
7678 | ? HARD_REGNO_NREGS (reg_dead_regno, | |
7679 | GET_MODE (reg)) | |
7680 | : 1); | |
7681 | ||
7682 | reg_dead_flag = 0; | |
7683 | ||
7684 | /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or | |
7685 | beginning of function. */ | |
7686 | for (; insn && GET_CODE (insn) != CODE_LABEL; | |
7687 | insn = prev_nonnote_insn (insn)) | |
7688 | { | |
7689 | note_stores (PATTERN (insn), reg_dead_at_p_1); | |
7690 | if (reg_dead_flag) | |
7691 | return reg_dead_flag == 1 ? 1 : 0; | |
7692 | ||
7693 | if (find_regno_note (insn, REG_DEAD, reg_dead_regno)) | |
7694 | return 1; | |
7695 | } | |
7696 | ||
7697 | /* Get the basic block number that we were in. */ | |
7698 | if (insn == 0) | |
7699 | block = 0; | |
7700 | else | |
7701 | { | |
7702 | for (block = 0; block < n_basic_blocks; block++) | |
7703 | if (insn == basic_block_head[block]) | |
7704 | break; | |
7705 | ||
7706 | if (block == n_basic_blocks) | |
7707 | return 0; | |
7708 | } | |
7709 | ||
7710 | for (i = reg_dead_regno; i < reg_dead_endregno; i++) | |
7711 | if (basic_block_live_at_start[block][i / HOST_BITS_PER_INT] | |
7712 | & (1 << (i % HOST_BITS_PER_INT))) | |
7713 | return 0; | |
7714 | ||
7715 | return 1; | |
7716 | } | |
7717 | \f | |
7718 | /* Remove register number REGNO from the dead registers list of INSN. | |
7719 | ||
7720 | Return the note used to record the death, if there was one. */ | |
7721 | ||
7722 | rtx | |
7723 | remove_death (regno, insn) | |
7724 | int regno; | |
7725 | rtx insn; | |
7726 | { | |
7727 | register rtx note = find_regno_note (insn, REG_DEAD, regno); | |
7728 | ||
7729 | if (note) | |
7730 | remove_note (insn, note); | |
7731 | ||
7732 | return note; | |
7733 | } | |
7734 | ||
7735 | /* For each register (hardware or pseudo) used within expression X, if its | |
7736 | death is in an instruction with cuid between FROM_CUID (inclusive) and | |
7737 | TO_INSN (exclusive), put a REG_DEAD note for that register in the | |
7738 | list headed by PNOTES. | |
7739 | ||
7740 | This is done when X is being merged by combination into TO_INSN. These | |
7741 | notes will then be distributed as needed. */ | |
7742 | ||
7743 | static void | |
7744 | move_deaths (x, from_cuid, to_insn, pnotes) | |
7745 | rtx x; | |
7746 | int from_cuid; | |
7747 | rtx to_insn; | |
7748 | rtx *pnotes; | |
7749 | { | |
7750 | register char *fmt; | |
7751 | register int len, i; | |
7752 | register enum rtx_code code = GET_CODE (x); | |
7753 | ||
7754 | if (code == REG) | |
7755 | { | |
7756 | register int regno = REGNO (x); | |
7757 | register rtx where_dead = reg_last_death[regno]; | |
7758 | ||
7759 | if (where_dead && INSN_CUID (where_dead) >= from_cuid | |
7760 | && INSN_CUID (where_dead) < INSN_CUID (to_insn)) | |
7761 | { | |
7762 | rtx note = remove_death (regno, reg_last_death[regno]); | |
7763 | ||
7764 | /* It is possible for the call above to return 0. This can occur | |
7765 | when reg_last_death points to I2 or I1 that we combined with. | |
7766 | In that case make a new note. */ | |
7767 | ||
7768 | if (note) | |
7769 | { | |
7770 | XEXP (note, 1) = *pnotes; | |
7771 | *pnotes = note; | |
7772 | } | |
7773 | else | |
7774 | *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes); | |
7775 | } | |
7776 | ||
7777 | return; | |
7778 | } | |
7779 | ||
7780 | else if (GET_CODE (x) == SET) | |
7781 | { | |
7782 | rtx dest = SET_DEST (x); | |
7783 | ||
7784 | move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes); | |
7785 | ||
a7c99304 RK |
7786 | /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG |
7787 | that accesses one word of a multi-word item, some | |
7788 | piece of everything register in the expression is used by | |
7789 | this insn, so remove any old death. */ | |
7790 | ||
7791 | if (GET_CODE (dest) == ZERO_EXTRACT | |
7792 | || GET_CODE (dest) == STRICT_LOW_PART | |
7793 | || (GET_CODE (dest) == SUBREG | |
7794 | && (((GET_MODE_SIZE (GET_MODE (dest)) | |
7795 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
7796 | == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) | |
7797 | + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))) | |
230d793d | 7798 | { |
a7c99304 RK |
7799 | move_deaths (dest, from_cuid, to_insn, pnotes); |
7800 | return; | |
230d793d RS |
7801 | } |
7802 | ||
a7c99304 RK |
7803 | /* If this is some other SUBREG, we know it replaces the entire |
7804 | value, so use that as the destination. */ | |
7805 | if (GET_CODE (dest) == SUBREG) | |
7806 | dest = SUBREG_REG (dest); | |
7807 | ||
7808 | /* If this is a MEM, adjust deaths of anything used in the address. | |
7809 | For a REG (the only other possibility), the entire value is | |
7810 | being replaced so the old value is not used in this insn. */ | |
230d793d RS |
7811 | |
7812 | if (GET_CODE (dest) == MEM) | |
7813 | move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes); | |
7814 | return; | |
7815 | } | |
7816 | ||
7817 | else if (GET_CODE (x) == CLOBBER) | |
7818 | return; | |
7819 | ||
7820 | len = GET_RTX_LENGTH (code); | |
7821 | fmt = GET_RTX_FORMAT (code); | |
7822 | ||
7823 | for (i = 0; i < len; i++) | |
7824 | { | |
7825 | if (fmt[i] == 'E') | |
7826 | { | |
7827 | register int j; | |
7828 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
7829 | move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes); | |
7830 | } | |
7831 | else if (fmt[i] == 'e') | |
7832 | move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes); | |
7833 | } | |
7834 | } | |
7835 | \f | |
a7c99304 RK |
7836 | /* Return 1 if X is the target of a bit-field assignment in BODY, the |
7837 | pattern of an insn. X must be a REG. */ | |
230d793d RS |
7838 | |
7839 | static int | |
a7c99304 RK |
7840 | reg_bitfield_target_p (x, body) |
7841 | rtx x; | |
230d793d RS |
7842 | rtx body; |
7843 | { | |
7844 | int i; | |
7845 | ||
7846 | if (GET_CODE (body) == SET) | |
a7c99304 RK |
7847 | { |
7848 | rtx dest = SET_DEST (body); | |
7849 | rtx target; | |
7850 | int regno, tregno, endregno, endtregno; | |
7851 | ||
7852 | if (GET_CODE (dest) == ZERO_EXTRACT) | |
7853 | target = XEXP (dest, 0); | |
7854 | else if (GET_CODE (dest) == STRICT_LOW_PART) | |
7855 | target = SUBREG_REG (XEXP (dest, 0)); | |
7856 | else | |
7857 | return 0; | |
7858 | ||
7859 | if (GET_CODE (target) == SUBREG) | |
7860 | target = SUBREG_REG (target); | |
7861 | ||
7862 | if (GET_CODE (target) != REG) | |
7863 | return 0; | |
7864 | ||
7865 | tregno = REGNO (target), regno = REGNO (x); | |
7866 | if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER) | |
7867 | return target == x; | |
7868 | ||
7869 | endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target)); | |
7870 | endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x)); | |
7871 | ||
7872 | return endregno > tregno && regno < endtregno; | |
7873 | } | |
230d793d RS |
7874 | |
7875 | else if (GET_CODE (body) == PARALLEL) | |
7876 | for (i = XVECLEN (body, 0) - 1; i >= 0; i--) | |
a7c99304 | 7877 | if (reg_bitfield_target_p (x, XVECEXP (body, 0, i))) |
230d793d RS |
7878 | return 1; |
7879 | ||
7880 | return 0; | |
7881 | } | |
7882 | \f | |
7883 | /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them | |
7884 | as appropriate. I3 and I2 are the insns resulting from the combination | |
7885 | insns including FROM (I2 may be zero). | |
7886 | ||
7887 | ELIM_I2 and ELIM_I1 are either zero or registers that we know will | |
7888 | not need REG_DEAD notes because they are being substituted for. This | |
7889 | saves searching in the most common cases. | |
7890 | ||
7891 | Each note in the list is either ignored or placed on some insns, depending | |
7892 | on the type of note. */ | |
7893 | ||
7894 | static void | |
7895 | distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1) | |
7896 | rtx notes; | |
7897 | rtx from_insn; | |
7898 | rtx i3, i2; | |
7899 | rtx elim_i2, elim_i1; | |
7900 | { | |
7901 | rtx note, next_note; | |
7902 | rtx tem; | |
7903 | ||
7904 | for (note = notes; note; note = next_note) | |
7905 | { | |
7906 | rtx place = 0, place2 = 0; | |
7907 | ||
7908 | /* If this NOTE references a pseudo register, ensure it references | |
7909 | the latest copy of that register. */ | |
7910 | if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG | |
7911 | && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER) | |
7912 | XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))]; | |
7913 | ||
7914 | next_note = XEXP (note, 1); | |
7915 | switch (REG_NOTE_KIND (note)) | |
7916 | { | |
7917 | case REG_UNUSED: | |
7918 | /* If this register is set or clobbered in I3, put the note there | |
7919 | unless there is one already. */ | |
7920 | if (reg_set_p (XEXP (note, 0), PATTERN (i3))) | |
7921 | { | |
7922 | if (! (GET_CODE (XEXP (note, 0)) == REG | |
7923 | ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0))) | |
7924 | : find_reg_note (i3, REG_UNUSED, XEXP (note, 0)))) | |
7925 | place = i3; | |
7926 | } | |
7927 | /* Otherwise, if this register is used by I3, then this register | |
7928 | now dies here, so we must put a REG_DEAD note here unless there | |
7929 | is one already. */ | |
7930 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)) | |
7931 | && ! (GET_CODE (XEXP (note, 0)) == REG | |
7932 | ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0))) | |
7933 | : find_reg_note (i3, REG_DEAD, XEXP (note, 0)))) | |
7934 | { | |
7935 | PUT_REG_NOTE_KIND (note, REG_DEAD); | |
7936 | place = i3; | |
7937 | } | |
7938 | break; | |
7939 | ||
7940 | case REG_EQUAL: | |
7941 | case REG_EQUIV: | |
7942 | case REG_NONNEG: | |
7943 | /* These notes say something about results of an insn. We can | |
7944 | only support them if they used to be on I3 in which case they | |
7945 | remain on I3. Otherwise they are ignored. */ | |
7946 | if (from_insn == i3) | |
7947 | place = i3; | |
7948 | break; | |
7949 | ||
7950 | case REG_INC: | |
7951 | case REG_NO_CONFLICT: | |
7952 | case REG_LABEL: | |
7953 | /* These notes say something about how a register is used. They must | |
7954 | be present on any use of the register in I2 or I3. */ | |
7955 | if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))) | |
7956 | place = i3; | |
7957 | ||
7958 | if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2))) | |
7959 | { | |
7960 | if (place) | |
7961 | place2 = i2; | |
7962 | else | |
7963 | place = i2; | |
7964 | } | |
7965 | break; | |
7966 | ||
7967 | case REG_WAS_0: | |
7968 | /* It is too much trouble to try to see if this note is still | |
7969 | correct in all situations. It is better to simply delete it. */ | |
7970 | break; | |
7971 | ||
7972 | case REG_RETVAL: | |
7973 | /* If the insn previously containing this note still exists, | |
7974 | put it back where it was. Otherwise move it to the previous | |
7975 | insn. Adjust the corresponding REG_LIBCALL note. */ | |
7976 | if (GET_CODE (from_insn) != NOTE) | |
7977 | place = from_insn; | |
7978 | else | |
7979 | { | |
7980 | tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, 0); | |
7981 | place = prev_real_insn (from_insn); | |
7982 | if (tem && place) | |
7983 | XEXP (tem, 0) = place; | |
7984 | } | |
7985 | break; | |
7986 | ||
7987 | case REG_LIBCALL: | |
7988 | /* This is handled similarly to REG_RETVAL. */ | |
7989 | if (GET_CODE (from_insn) != NOTE) | |
7990 | place = from_insn; | |
7991 | else | |
7992 | { | |
7993 | tem = find_reg_note (XEXP (note, 0), REG_RETVAL, 0); | |
7994 | place = next_real_insn (from_insn); | |
7995 | if (tem && place) | |
7996 | XEXP (tem, 0) = place; | |
7997 | } | |
7998 | break; | |
7999 | ||
8000 | case REG_DEAD: | |
8001 | /* If the register is used as an input in I3, it dies there. | |
8002 | Similarly for I2, if it is non-zero and adjacent to I3. | |
8003 | ||
8004 | If the register is not used as an input in either I3 or I2 | |
8005 | and it is not one of the registers we were supposed to eliminate, | |
8006 | there are two possibilities. We might have a non-adjacent I2 | |
8007 | or we might have somehow eliminated an additional register | |
8008 | from a computation. For example, we might have had A & B where | |
8009 | we discover that B will always be zero. In this case we will | |
8010 | eliminate the reference to A. | |
8011 | ||
8012 | In both cases, we must search to see if we can find a previous | |
8013 | use of A and put the death note there. */ | |
8014 | ||
8015 | if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))) | |
8016 | place = i3; | |
8017 | else if (i2 != 0 && next_nonnote_insn (i2) == i3 | |
8018 | && reg_referenced_p (XEXP (note, 0), PATTERN (i2))) | |
8019 | place = i2; | |
8020 | ||
8021 | if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1) | |
8022 | break; | |
8023 | ||
8024 | if (place == 0) | |
8025 | for (tem = prev_nonnote_insn (i3); | |
8026 | tem && (GET_CODE (tem) == INSN | |
8027 | || GET_CODE (tem) == CALL_INSN); | |
8028 | tem = prev_nonnote_insn (tem)) | |
8029 | { | |
8030 | /* If the register is being set at TEM, see if that is all | |
8031 | TEM is doing. If so, delete TEM. Otherwise, make this | |
8032 | into a REG_UNUSED note instead. */ | |
8033 | if (reg_set_p (XEXP (note, 0), PATTERN (tem))) | |
8034 | { | |
8035 | rtx set = single_set (tem); | |
8036 | ||
5089e22e RS |
8037 | /* Verify that it was the set, and not a clobber that |
8038 | modified the register. */ | |
8039 | ||
8040 | if (set != 0 && ! side_effects_p (SET_SRC (set)) | |
8041 | && rtx_equal_p (XEXP (note, 0), SET_DEST (set))) | |
230d793d RS |
8042 | { |
8043 | /* Move the notes and links of TEM elsewhere. | |
8044 | This might delete other dead insns recursively. | |
8045 | First set the pattern to something that won't use | |
8046 | any register. */ | |
8047 | ||
8048 | PATTERN (tem) = pc_rtx; | |
8049 | ||
8050 | distribute_notes (REG_NOTES (tem), tem, tem, 0, 0, 0); | |
8051 | distribute_links (LOG_LINKS (tem)); | |
8052 | ||
8053 | PUT_CODE (tem, NOTE); | |
8054 | NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED; | |
8055 | NOTE_SOURCE_FILE (tem) = 0; | |
8056 | } | |
8057 | else | |
8058 | { | |
8059 | PUT_REG_NOTE_KIND (note, REG_UNUSED); | |
8060 | ||
8061 | /* If there isn't already a REG_UNUSED note, put one | |
8062 | here. */ | |
8063 | if (! find_regno_note (tem, REG_UNUSED, | |
8064 | REGNO (XEXP (note, 0)))) | |
8065 | place = tem; | |
8066 | break; | |
8067 | } | |
8068 | } | |
8069 | else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))) | |
8070 | { | |
8071 | place = tem; | |
8072 | break; | |
8073 | } | |
8074 | } | |
8075 | ||
8076 | /* If the register is set or already dead at PLACE, we needn't do | |
8077 | anything with this note if it is still a REG_DEAD note. | |
8078 | ||
8079 | Note that we cannot use just `dead_or_set_p' here since we can | |
8080 | convert an assignment to a register into a bit-field assignment. | |
8081 | Therefore, we must also omit the note if the register is the | |
8082 | target of a bitfield assignment. */ | |
8083 | ||
8084 | if (place && REG_NOTE_KIND (note) == REG_DEAD) | |
8085 | { | |
8086 | int regno = REGNO (XEXP (note, 0)); | |
8087 | ||
8088 | if (dead_or_set_p (place, XEXP (note, 0)) | |
8089 | || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place))) | |
8090 | { | |
8091 | /* Unless the register previously died in PLACE, clear | |
8092 | reg_last_death. [I no longer understand why this is | |
8093 | being done.] */ | |
8094 | if (reg_last_death[regno] != place) | |
8095 | reg_last_death[regno] = 0; | |
8096 | place = 0; | |
8097 | } | |
8098 | else | |
8099 | reg_last_death[regno] = place; | |
8100 | ||
8101 | /* If this is a death note for a hard reg that is occupying | |
8102 | multiple registers, ensure that we are still using all | |
8103 | parts of the object. If we find a piece of the object | |
8104 | that is unused, we must add a USE for that piece before | |
8105 | PLACE and put the appropriate REG_DEAD note on it. | |
8106 | ||
8107 | An alternative would be to put a REG_UNUSED for the pieces | |
8108 | on the insn that set the register, but that can't be done if | |
8109 | it is not in the same block. It is simpler, though less | |
8110 | efficient, to add the USE insns. */ | |
8111 | ||
8112 | if (place && regno < FIRST_PSEUDO_REGISTER | |
8113 | && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1) | |
8114 | { | |
8115 | int endregno | |
8116 | = regno + HARD_REGNO_NREGS (regno, | |
8117 | GET_MODE (XEXP (note, 0))); | |
8118 | int all_used = 1; | |
8119 | int i; | |
8120 | ||
8121 | for (i = regno; i < endregno; i++) | |
8122 | if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)) | |
8123 | { | |
8124 | rtx piece = gen_rtx (REG, word_mode, i); | |
28f6d3af RK |
8125 | rtx p; |
8126 | ||
8127 | /* See if we already placed a USE note for this | |
8128 | register in front of PLACE. */ | |
8129 | for (p = place; | |
8130 | GET_CODE (PREV_INSN (p)) == INSN | |
8131 | && GET_CODE (PATTERN (PREV_INSN (p))) == USE; | |
8132 | p = PREV_INSN (p)) | |
8133 | if (rtx_equal_p (piece, | |
8134 | XEXP (PATTERN (PREV_INSN (p)), 0))) | |
8135 | { | |
8136 | p = 0; | |
8137 | break; | |
8138 | } | |
8139 | ||
8140 | if (p) | |
8141 | { | |
8142 | rtx use_insn | |
8143 | = emit_insn_before (gen_rtx (USE, VOIDmode, | |
8144 | piece), | |
8145 | p); | |
8146 | REG_NOTES (use_insn) | |
8147 | = gen_rtx (EXPR_LIST, REG_DEAD, piece, | |
8148 | REG_NOTES (use_insn)); | |
8149 | } | |
230d793d | 8150 | |
5089e22e | 8151 | all_used = 0; |
230d793d RS |
8152 | } |
8153 | ||
8154 | if (! all_used) | |
8155 | { | |
8156 | /* Put only REG_DEAD notes for pieces that are | |
8157 | still used and that are not already dead or set. */ | |
8158 | ||
8159 | for (i = regno; i < endregno; i++) | |
8160 | { | |
8161 | rtx piece = gen_rtx (REG, word_mode, i); | |
8162 | ||
8163 | if (reg_referenced_p (piece, PATTERN (place)) | |
8164 | && ! dead_or_set_p (place, piece) | |
8165 | && ! reg_bitfield_target_p (piece, | |
8166 | PATTERN (place))) | |
8167 | REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD, | |
8168 | piece, | |
8169 | REG_NOTES (place)); | |
8170 | } | |
8171 | ||
8172 | place = 0; | |
8173 | } | |
8174 | } | |
8175 | } | |
8176 | break; | |
8177 | ||
8178 | default: | |
8179 | /* Any other notes should not be present at this point in the | |
8180 | compilation. */ | |
8181 | abort (); | |
8182 | } | |
8183 | ||
8184 | if (place) | |
8185 | { | |
8186 | XEXP (note, 1) = REG_NOTES (place); | |
8187 | REG_NOTES (place) = note; | |
8188 | } | |
8189 | ||
8190 | if (place2) | |
8191 | REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note), | |
8192 | XEXP (note, 0), REG_NOTES (place2)); | |
8193 | } | |
8194 | } | |
8195 | \f | |
8196 | /* Similarly to above, distribute the LOG_LINKS that used to be present on | |
5089e22e RS |
8197 | I3, I2, and I1 to new locations. This is also called in one case to |
8198 | add a link pointing at I3 when I3's destination is changed. */ | |
230d793d RS |
8199 | |
8200 | static void | |
8201 | distribute_links (links) | |
8202 | rtx links; | |
8203 | { | |
8204 | rtx link, next_link; | |
8205 | ||
8206 | for (link = links; link; link = next_link) | |
8207 | { | |
8208 | rtx place = 0; | |
8209 | rtx insn; | |
8210 | rtx set, reg; | |
8211 | ||
8212 | next_link = XEXP (link, 1); | |
8213 | ||
8214 | /* If the insn that this link points to is a NOTE or isn't a single | |
8215 | set, ignore it. In the latter case, it isn't clear what we | |
8216 | can do other than ignore the link, since we can't tell which | |
8217 | register it was for. Such links wouldn't be used by combine | |
8218 | anyway. | |
8219 | ||
8220 | It is not possible for the destination of the target of the link to | |
8221 | have been changed by combine. The only potential of this is if we | |
8222 | replace I3, I2, and I1 by I3 and I2. But in that case the | |
8223 | destination of I2 also remains unchanged. */ | |
8224 | ||
8225 | if (GET_CODE (XEXP (link, 0)) == NOTE | |
8226 | || (set = single_set (XEXP (link, 0))) == 0) | |
8227 | continue; | |
8228 | ||
8229 | reg = SET_DEST (set); | |
8230 | while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT | |
8231 | || GET_CODE (reg) == SIGN_EXTRACT | |
8232 | || GET_CODE (reg) == STRICT_LOW_PART) | |
8233 | reg = XEXP (reg, 0); | |
8234 | ||
8235 | /* A LOG_LINK is defined as being placed on the first insn that uses | |
8236 | a register and points to the insn that sets the register. Start | |
8237 | searching at the next insn after the target of the link and stop | |
8238 | when we reach a set of the register or the end of the basic block. | |
8239 | ||
8240 | Note that this correctly handles the link that used to point from | |
5089e22e | 8241 | I3 to I2. Also note that not much searching is typically done here |
230d793d RS |
8242 | since most links don't point very far away. */ |
8243 | ||
8244 | for (insn = NEXT_INSN (XEXP (link, 0)); | |
8245 | (insn && GET_CODE (insn) != CODE_LABEL | |
8246 | && GET_CODE (PREV_INSN (insn)) != JUMP_INSN); | |
8247 | insn = NEXT_INSN (insn)) | |
8248 | if (GET_RTX_CLASS (GET_CODE (insn)) == 'i' | |
8249 | && reg_overlap_mentioned_p (reg, PATTERN (insn))) | |
8250 | { | |
8251 | if (reg_referenced_p (reg, PATTERN (insn))) | |
8252 | place = insn; | |
8253 | break; | |
8254 | } | |
8255 | ||
8256 | /* If we found a place to put the link, place it there unless there | |
8257 | is already a link to the same insn as LINK at that point. */ | |
8258 | ||
8259 | if (place) | |
8260 | { | |
8261 | rtx link2; | |
8262 | ||
8263 | for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1)) | |
8264 | if (XEXP (link2, 0) == XEXP (link, 0)) | |
8265 | break; | |
8266 | ||
8267 | if (link2 == 0) | |
8268 | { | |
8269 | XEXP (link, 1) = LOG_LINKS (place); | |
8270 | LOG_LINKS (place) = link; | |
8271 | } | |
8272 | } | |
8273 | } | |
8274 | } | |
8275 | \f | |
8276 | void | |
8277 | dump_combine_stats (file) | |
8278 | FILE *file; | |
8279 | { | |
8280 | fprintf | |
8281 | (file, | |
8282 | ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n", | |
8283 | combine_attempts, combine_merges, combine_extras, combine_successes); | |
8284 | } | |
8285 | ||
8286 | void | |
8287 | dump_combine_total_stats (file) | |
8288 | FILE *file; | |
8289 | { | |
8290 | fprintf | |
8291 | (file, | |
8292 | "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n", | |
8293 | total_attempts, total_merges, total_extras, total_successes); | |
8294 | } |