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230d793d 1/* Optimize by combining instructions for GNU compiler.
c85f7c16 2 Copyright (C) 1987, 88, 92-97, 1998 Free Software Foundation, Inc.
230d793d
RS		 3
4This file is part of GNU CC.
5
6GNU CC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2, or (at your option)
9any later version.
10
11GNU CC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with GNU CC; see the file COPYING. If not, write to
940d9d63
RK		 18the Free Software Foundation, 59 Temple Place - Suite 330,
19Boston, MA 02111-1307, USA. */
230d793d
RS		 20
21
22/* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
25
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
31
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
35
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
41
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
44
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
51
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
54
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
59 REG_DEAD note is lost
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
62 linking
63
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
67
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
75 combine anyway. */
76
230d793d 77#include "config.h"
670ee920 78#include "system.h"
789f983a 79#include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
230d793d
RS		 80#include "flags.h"
81#include "regs.h"
55310dad 82#include "hard-reg-set.h"
230d793d
RS		 83#include "basic-block.h"
84#include "insn-config.h"
d6f4ec51
KG		 85/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
86#include "expr.h"
230d793d
RS		 87#include "insn-flags.h"
88#include "insn-codes.h"
89#include "insn-attr.h"
90#include "recog.h"
91#include "real.h"
2e107e9e 92#include "toplev.h"
230d793d
RS		 93
94/* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96#define gen_lowpart dont_use_gen_lowpart_you_dummy
97
98/* Number of attempts to combine instructions in this function. */
99
100static int combine_attempts;
101
102/* Number of attempts that got as far as substitution in this function. */
103
104static int combine_merges;
105
106/* Number of instructions combined with added SETs in this function. */
107
108static int combine_extras;
109
110/* Number of instructions combined in this function. */
111
112static int combine_successes;
113
114/* Totals over entire compilation. */
115
116static int total_attempts, total_merges, total_extras, total_successes;
9210df58 117
ddd5a7c1 118/* Define a default value for REVERSIBLE_CC_MODE.
9210df58
RK		 119 We can never assume that a condition code mode is safe to reverse unless
120 the md tells us so. */
121#ifndef REVERSIBLE_CC_MODE
122#define REVERSIBLE_CC_MODE(MODE) 0
123#endif
230d793d
RS		 124\f
125/* Vector mapping INSN_UIDs to cuids.
5089e22e 126 The cuids are like uids but increase monotonically always.
230d793d
RS		 127 Combine always uses cuids so that it can compare them.
128 But actually renumbering the uids, which we used to do,
129 proves to be a bad idea because it makes it hard to compare
130 the dumps produced by earlier passes with those from later passes. */
131
132static int *uid_cuid;
4255220d 133static int max_uid_cuid;
230d793d
RS		 134
135/* Get the cuid of an insn. */
136
1427d6d2
RK		 137#define INSN_CUID(INSN) \
138(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
230d793d
RS		 139
140/* Maximum register number, which is the size of the tables below. */
141
142static int combine_max_regno;
143
144/* Record last point of death of (hard or pseudo) register n. */
145
146static rtx *reg_last_death;
147
148/* Record last point of modification of (hard or pseudo) register n. */
149
150static rtx *reg_last_set;
151
152/* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
154
155static int mem_last_set;
156
157/* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
159
160static int last_call_cuid;
161
162/* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
167
168static rtx subst_insn;
169
0d9641d1
JW		 170/* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
172
173static rtx subst_prev_insn;
174
230d793d
RS		 175/* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
181
182static int subst_low_cuid;
183
6e25d159
RK		 184/* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
186
187static HARD_REG_SET newpat_used_regs;
188
abe6e52f
RK		 189/* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
191 that location. */
192
193static rtx added_links_insn;
194
0d4d42c3
RK		 195/* Basic block number of the block in which we are performing combines. */
196static int this_basic_block;
230d793d
RS		 197\f
198/* The next group of arrays allows the recording of the last value assigned
199 to (hard or pseudo) register n. We use this information to see if a
5089e22e 200 operation being processed is redundant given a prior operation performed
230d793d
RS		 201 on the register. For example, an `and' with a constant is redundant if
202 all the zero bits are already known to be turned off.
203
204 We use an approach similar to that used by cse, but change it in the
205 following ways:
206
207 (1) We do not want to reinitialize at each label.
208 (2) It is useful, but not critical, to know the actual value assigned
209 to a register. Often just its form is helpful.
210
211 Therefore, we maintain the following arrays:
212
213 reg_last_set_value the last value assigned
214 reg_last_set_label records the value of label_tick when the
215 register was assigned
216 reg_last_set_table_tick records the value of label_tick when a
217 value using the register is assigned
218 reg_last_set_invalid set to non-zero when it is not valid
219 to use the value of this register in some
220 register's value
221
222 To understand the usage of these tables, it is important to understand
223 the distinction between the value in reg_last_set_value being valid
224 and the register being validly contained in some other expression in the
225 table.
226
227 Entry I in reg_last_set_value is valid if it is non-zero, and either
228 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
229
230 Register I may validly appear in any expression returned for the value
231 of another register if reg_n_sets[i] is 1. It may also appear in the
232 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
233 reg_last_set_invalid[j] is zero.
234
235 If an expression is found in the table containing a register which may
236 not validly appear in an expression, the register is replaced by
237 something that won't match, (clobber (const_int 0)).
238
239 reg_last_set_invalid[i] is set non-zero when register I is being assigned
240 to and reg_last_set_table_tick[i] == label_tick. */
241
0f41302f 242/* Record last value assigned to (hard or pseudo) register n. */
230d793d
RS		 243
244static rtx *reg_last_set_value;
245
246/* Record the value of label_tick when the value for register n is placed in
247 reg_last_set_value[n]. */
248
568356af 249static int *reg_last_set_label;
230d793d
RS		 250
251/* Record the value of label_tick when an expression involving register n
0f41302f 252 is placed in reg_last_set_value. */
230d793d 253
568356af 254static int *reg_last_set_table_tick;
230d793d
RS		 255
256/* Set non-zero if references to register n in expressions should not be
257 used. */
258
259static char *reg_last_set_invalid;
260
0f41302f 261/* Incremented for each label. */
230d793d 262
568356af 263static int label_tick;
230d793d
RS		 264
265/* Some registers that are set more than once and used in more than one
266 basic block are nevertheless always set in similar ways. For example,
267 a QImode register may be loaded from memory in two places on a machine
268 where byte loads zero extend.
269
951553af 270 We record in the following array what we know about the nonzero
230d793d
RS		 271 bits of a register, specifically which bits are known to be zero.
272
273 If an entry is zero, it means that we don't know anything special. */
274
55310dad 275static unsigned HOST_WIDE_INT *reg_nonzero_bits;
230d793d 276
951553af 277/* Mode used to compute significance in reg_nonzero_bits. It is the largest
5f4f0e22 278 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
230d793d 279
951553af 280static enum machine_mode nonzero_bits_mode;
230d793d 281
d0ab8cd3
RK		 282/* Nonzero if we know that a register has some leading bits that are always
283 equal to the sign bit. */
284
285static char *reg_sign_bit_copies;
286
951553af 287/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
1a26b032
RK		 288 It is zero while computing them and after combine has completed. This
289 former test prevents propagating values based on previously set values,
290 which can be incorrect if a variable is modified in a loop. */
230d793d 291
951553af 292static int nonzero_sign_valid;
55310dad
RK		 293
294/* These arrays are maintained in parallel with reg_last_set_value
295 and are used to store the mode in which the register was last set,
296 the bits that were known to be zero when it was last set, and the
297 number of sign bits copies it was known to have when it was last set. */
298
299static enum machine_mode *reg_last_set_mode;
300static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
301static char *reg_last_set_sign_bit_copies;
230d793d
RS		 302\f
303/* Record one modification to rtl structure
304 to be undone by storing old_contents into *where.
305 is_int is 1 if the contents are an int. */
306
307struct undo
308{
241cea85 309 struct undo *next;
230d793d 310 int is_int;
f5393ab9
RS		 311 union {rtx r; int i;} old_contents;
312 union {rtx *r; int *i;} where;
230d793d
RS		 313};
314
315/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
316 num_undo says how many are currently recorded.
317
318 storage is nonzero if we must undo the allocation of new storage.
319 The value of storage is what to pass to obfree.
320
321 other_insn is nonzero if we have modified some other insn in the process
241cea85 322 of working on subst_insn. It must be verified too.
230d793d 323
241cea85
RK		 324 previous_undos is the value of undobuf.undos when we started processing
325 this substitution. This will prevent gen_rtx_combine from re-used a piece
326 from the previous expression. Doing so can produce circular rtl
327 structures. */
230d793d
RS		 328
329struct undobuf
330{
230d793d 331 char *storage;
241cea85
RK		 332 struct undo *undos;
333 struct undo *frees;
334 struct undo *previous_undos;
230d793d
RS		 335 rtx other_insn;
336};
337
338static struct undobuf undobuf;
339
cc876596 340/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
230d793d 341 insn. The substitution can be undone by undo_all. If INTO is already
cc876596
RK		 342 set to NEWVAL, do not record this change. Because computing NEWVAL might
343 also call SUBST, we have to compute it before we put anything into
344 the undo table. */
230d793d
RS		 345
346#define SUBST(INTO, NEWVAL) \
241cea85
RK		 347 do { rtx _new = (NEWVAL); \
348 struct undo *_buf; \
349 \
350 if (undobuf.frees) \
351 _buf = undobuf.frees, undobuf.frees = _buf->next; \
352 else \
353 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
354 \
355 _buf->is_int = 0; \
356 _buf->where.r = &INTO; \
357 _buf->old_contents.r = INTO; \
358 INTO = _new; \
359 if (_buf->old_contents.r == INTO) \
360 _buf->next = undobuf.frees, undobuf.frees = _buf; \
361 else \
362 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 363 } while (0)
364
241cea85
RK		 365/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
366 for the value of a HOST_WIDE_INT value (including CONST_INT) is
367 not safe. */
230d793d
RS		 368
369#define SUBST_INT(INTO, NEWVAL) \
241cea85
RK		 370 do { struct undo *_buf; \
371 \
372 if (undobuf.frees) \
373 _buf = undobuf.frees, undobuf.frees = _buf->next; \
374 else \
375 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
376 \
377 _buf->is_int = 1; \
378 _buf->where.i = (int *) &INTO; \
379 _buf->old_contents.i = INTO; \
380 INTO = NEWVAL; \
381 if (_buf->old_contents.i == INTO) \
382 _buf->next = undobuf.frees, undobuf.frees = _buf; \
383 else \
384 _buf->next = undobuf.undos, undobuf.undos = _buf; \
230d793d
RS		 385 } while (0)
386
387/* Number of times the pseudo being substituted for
388 was found and replaced. */
389
390static int n_occurrences;
391
c5ad722c
RK		 392static void init_reg_last_arrays PROTO((void));
393static void setup_incoming_promotions PROTO((void));
fe2db4fb
RK		 394static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
395static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
e009aaf3 396static int sets_function_arg_p PROTO((rtx));
fe2db4fb
RK		 397static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
398static rtx try_combine PROTO((rtx, rtx, rtx));
399static void undo_all PROTO((void));
400static rtx *find_split_point PROTO((rtx *, rtx));
401static rtx subst PROTO((rtx, rtx, rtx, int, int));
8079805d
RK		 402static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
403static rtx simplify_if_then_else PROTO((rtx));
404static rtx simplify_set PROTO((rtx));
405static rtx simplify_logical PROTO((rtx, int));
fe2db4fb
RK		 406static rtx expand_compound_operation PROTO((rtx));
407static rtx expand_field_assignment PROTO((rtx));
408static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
409 int, int, int));
71923da7 410static rtx extract_left_shift PROTO((rtx, int));
fe2db4fb
RK		 411static rtx make_compound_operation PROTO((rtx, enum rtx_code));
412static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
6139ff20 413static rtx force_to_mode PROTO((rtx, enum machine_mode,
e3d616e3 414 unsigned HOST_WIDE_INT, rtx, int));
abe6e52f 415static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
fe2db4fb 416static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
e11fa86f 417static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
fe2db4fb
RK		 418static rtx make_field_assignment PROTO((rtx));
419static rtx apply_distributive_law PROTO((rtx));
420static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
421 unsigned HOST_WIDE_INT));
422static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
423static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
424static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
425 enum rtx_code, HOST_WIDE_INT,
426 enum machine_mode, int *));
427static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
428 rtx, int));
8e2f6e35 429static int recog_for_combine PROTO((rtx *, rtx, rtx *));
fe2db4fb 430static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
d18225c4 431static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
4f90e4a0 432 ...));
fe2db4fb
RK		 433static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
434 rtx, rtx));
0c1c8ea6
RK		 435static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
436 enum machine_mode, rtx));
fe2db4fb
RK		 437static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
438static int reversible_comparison_p PROTO((rtx));
439static void update_table_tick PROTO((rtx));
440static void record_value_for_reg PROTO((rtx, rtx, rtx));
441static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
442static void record_dead_and_set_regs PROTO((rtx));
9a893315 443static int get_last_value_validate PROTO((rtx *, rtx, int, int));
fe2db4fb
RK		 444static rtx get_last_value PROTO((rtx));
445static int use_crosses_set_p PROTO((rtx, int));
446static void reg_dead_at_p_1 PROTO((rtx, rtx));
447static int reg_dead_at_p PROTO((rtx, rtx));
6eb12cef 448static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
fe2db4fb
RK		 449static int reg_bitfield_target_p PROTO((rtx, rtx));
450static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
451static void distribute_links PROTO((rtx));
6e25d159 452static void mark_used_regs_combine PROTO((rtx));
1427d6d2 453static int insn_cuid PROTO((rtx));
230d793d
RS		 454\f
455/* Main entry point for combiner. F is the first insn of the function.
456 NREGS is the first unused pseudo-reg number. */
457
458void
459combine_instructions (f, nregs)
460 rtx f;
461 int nregs;
462{
b729186a
JL		 463 register rtx insn, next;
464#ifdef HAVE_cc0
465 register rtx prev;
466#endif
230d793d
RS		 467 register int i;
468 register rtx links, nextlinks;
469
470 combine_attempts = 0;
471 combine_merges = 0;
472 combine_extras = 0;
473 combine_successes = 0;
241cea85 474 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 475
476 combine_max_regno = nregs;
477
ef026f91
RS		 478 reg_nonzero_bits
479 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
480 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
481
4c9a05bc 482 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 483 bzero (reg_sign_bit_copies, nregs * sizeof (char));
484
230d793d
RS		 485 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
486 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
487 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
568356af
RK		 488 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
489 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
5f4f0e22 490 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
55310dad
RK		 491 reg_last_set_mode
492 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
493 reg_last_set_nonzero_bits
494 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
495 reg_last_set_sign_bit_copies
496 = (char *) alloca (nregs * sizeof (char));
497
ef026f91 498 init_reg_last_arrays ();
230d793d
RS		 499
500 init_recog_no_volatile ();
501
502 /* Compute maximum uid value so uid_cuid can be allocated. */
503
504 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
505 if (INSN_UID (insn) > i)
506 i = INSN_UID (insn);
507
508 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
4255220d 509 max_uid_cuid = i;
230d793d 510
951553af 511 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
230d793d 512
951553af 513 /* Don't use reg_nonzero_bits when computing it. This can cause problems
230d793d
RS		 514 when, for example, we have j <<= 1 in a loop. */
515
951553af 516 nonzero_sign_valid = 0;
230d793d
RS		 517
518 /* Compute the mapping from uids to cuids.
519 Cuids are numbers assigned to insns, like uids,
520 except that cuids increase monotonically through the code.
521
522 Scan all SETs and see if we can deduce anything about what
951553af 523 bits are known to be zero for some registers and how many copies
d79f08e0
RK		 524 of the sign bit are known to exist for those registers.
525
526 Also set any known values so that we can use it while searching
527 for what bits are known to be set. */
528
529 label_tick = 1;
230d793d 530
bcd49eb7
JW		 531 /* We need to initialize it here, because record_dead_and_set_regs may call
532 get_last_value. */
533 subst_prev_insn = NULL_RTX;
534
7988fd36
RK		 535 setup_incoming_promotions ();
536
230d793d
RS		 537 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
538 {
4255220d 539 uid_cuid[INSN_UID (insn)] = ++i;
d79f08e0
RK		 540 subst_low_cuid = i;
541 subst_insn = insn;
542
230d793d 543 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
d79f08e0
RK		 544 {
545 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
546 record_dead_and_set_regs (insn);
2dab894a
RK		 547
548#ifdef AUTO_INC_DEC
549 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
550 if (REG_NOTE_KIND (links) == REG_INC)
551 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
552#endif
d79f08e0
RK		 553 }
554
555 if (GET_CODE (insn) == CODE_LABEL)
556 label_tick++;
230d793d
RS		 557 }
558
951553af 559 nonzero_sign_valid = 1;
230d793d
RS		 560
561 /* Now scan all the insns in forward order. */
562
0d4d42c3 563 this_basic_block = -1;
230d793d
RS		 564 label_tick = 1;
565 last_call_cuid = 0;
566 mem_last_set = 0;
ef026f91 567 init_reg_last_arrays ();
7988fd36
RK		 568 setup_incoming_promotions ();
569
230d793d
RS		 570 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
571 {
572 next = 0;
573
0d4d42c3 574 /* If INSN starts a new basic block, update our basic block number. */
f085c9cd 575 if (this_basic_block + 1 < n_basic_blocks
0d4d42c3
RK		 576 && basic_block_head[this_basic_block + 1] == insn)
577 this_basic_block++;
578
230d793d
RS		 579 if (GET_CODE (insn) == CODE_LABEL)
580 label_tick++;
581
0d4d42c3 582 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
230d793d
RS		 583 {
584 /* Try this insn with each insn it links back to. */
585
586 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
5f4f0e22 587 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
230d793d
RS		 588 goto retry;
589
590 /* Try each sequence of three linked insns ending with this one. */
591
592 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
593 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
594 nextlinks = XEXP (nextlinks, 1))
595 if ((next = try_combine (insn, XEXP (links, 0),
596 XEXP (nextlinks, 0))) != 0)
597 goto retry;
598
599#ifdef HAVE_cc0
600 /* Try to combine a jump insn that uses CC0
601 with a preceding insn that sets CC0, and maybe with its
602 logical predecessor as well.
603 This is how we make decrement-and-branch insns.
604 We need this special code because data flow connections
605 via CC0 do not get entered in LOG_LINKS. */
606
607 if (GET_CODE (insn) == JUMP_INSN
608 && (prev = prev_nonnote_insn (insn)) != 0
609 && GET_CODE (prev) == INSN
610 && sets_cc0_p (PATTERN (prev)))
611 {
5f4f0e22 612 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 613 goto retry;
614
615 for (nextlinks = LOG_LINKS (prev); nextlinks;
616 nextlinks = XEXP (nextlinks, 1))
617 if ((next = try_combine (insn, prev,
618 XEXP (nextlinks, 0))) != 0)
619 goto retry;
620 }
621
622 /* Do the same for an insn that explicitly references CC0. */
623 if (GET_CODE (insn) == INSN
624 && (prev = prev_nonnote_insn (insn)) != 0
625 && GET_CODE (prev) == INSN
626 && sets_cc0_p (PATTERN (prev))
627 && GET_CODE (PATTERN (insn)) == SET
628 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
629 {
5f4f0e22 630 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
230d793d
RS		 631 goto retry;
632
633 for (nextlinks = LOG_LINKS (prev); nextlinks;
634 nextlinks = XEXP (nextlinks, 1))
635 if ((next = try_combine (insn, prev,
636 XEXP (nextlinks, 0))) != 0)
637 goto retry;
638 }
639
640 /* Finally, see if any of the insns that this insn links to
641 explicitly references CC0. If so, try this insn, that insn,
5089e22e 642 and its predecessor if it sets CC0. */
230d793d
RS		 643 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
644 if (GET_CODE (XEXP (links, 0)) == INSN
645 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
646 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
647 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev))
650 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
651 goto retry;
652#endif
653
654 /* Try combining an insn with two different insns whose results it
655 uses. */
656 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
657 for (nextlinks = XEXP (links, 1); nextlinks;
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, XEXP (links, 0),
660 XEXP (nextlinks, 0))) != 0)
661 goto retry;
662
663 if (GET_CODE (insn) != NOTE)
664 record_dead_and_set_regs (insn);
665
666 retry:
667 ;
668 }
669 }
670
671 total_attempts += combine_attempts;
672 total_merges += combine_merges;
673 total_extras += combine_extras;
674 total_successes += combine_successes;
1a26b032 675
951553af 676 nonzero_sign_valid = 0;
972b320c
R		 677
678 /* Make recognizer allow volatile MEMs again. */
679 init_recog ();
230d793d 680}
ef026f91
RS		 681
682/* Wipe the reg_last_xxx arrays in preparation for another pass. */
683
684static void
685init_reg_last_arrays ()
686{
687 int nregs = combine_max_regno;
688
4c9a05bc
RK		 689 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
692 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
693 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
ef026f91 694 bzero (reg_last_set_invalid, nregs * sizeof (char));
4c9a05bc
RK		 695 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
696 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
ef026f91
RS		 697 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
698}
230d793d 699\f
7988fd36
RK		 700/* Set up any promoted values for incoming argument registers. */
701
ee791cc3 702static void
7988fd36
RK		 703setup_incoming_promotions ()
704{
705#ifdef PROMOTE_FUNCTION_ARGS
706 int regno;
707 rtx reg;
708 enum machine_mode mode;
709 int unsignedp;
710 rtx first = get_insns ();
711
712 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
713 if (FUNCTION_ARG_REGNO_P (regno)
714 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
38a448ca
RH		 715 {
716 record_value_for_reg
717 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
718 : SIGN_EXTEND),
719 GET_MODE (reg),
720 gen_rtx_CLOBBER (mode, const0_rtx)));
721 }
7988fd36
RK		 722#endif
723}
724\f
91102d5a
RK		 725/* Called via note_stores. If X is a pseudo that is narrower than
726 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
230d793d
RS		 727
728 If we are setting only a portion of X and we can't figure out what
729 portion, assume all bits will be used since we don't know what will
d0ab8cd3
RK		 730 be happening.
731
732 Similarly, set how many bits of X are known to be copies of the sign bit
733 at all locations in the function. This is the smallest number implied
734 by any set of X. */
230d793d
RS		 735
736static void
951553af 737set_nonzero_bits_and_sign_copies (x, set)
230d793d
RS		 738 rtx x;
739 rtx set;
740{
d0ab8cd3
RK		 741 int num;
742
230d793d
RS		 743 if (GET_CODE (x) == REG
744 && REGNO (x) >= FIRST_PSEUDO_REGISTER
e8095e80
RK		 745 /* If this register is undefined at the start of the file, we can't
746 say what its contents were. */
8e08106d 747 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
5f4f0e22 748 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
230d793d 749 {
2dab894a 750 if (set == 0 || GET_CODE (set) == CLOBBER)
e8095e80
RK		 751 {
752 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 753 reg_sign_bit_copies[REGNO (x)] = 1;
e8095e80
RK		 754 return;
755 }
230d793d
RS		 756
757 /* If this is a complex assignment, see if we can convert it into a
5089e22e 758 simple assignment. */
230d793d 759 set = expand_field_assignment (set);
d79f08e0
RK		 760
761 /* If this is a simple assignment, or we have a paradoxical SUBREG,
762 set what we know about X. */
763
764 if (SET_DEST (set) == x
765 || (GET_CODE (SET_DEST (set)) == SUBREG
705c7b3b
JW		 766 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
d79f08e0 768 && SUBREG_REG (SET_DEST (set)) == x))
d0ab8cd3 769 {
9afa3d54
RK		 770 rtx src = SET_SRC (set);
771
772#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
773 /* If X is narrower than a word and SRC is a non-negative
774 constant that would appear negative in the mode of X,
775 sign-extend it for use in reg_nonzero_bits because some
776 machines (maybe most) will actually do the sign-extension
777 and this is the conservative approach.
778
779 ??? For 2.5, try to tighten up the MD files in this regard
780 instead of this kludge. */
781
782 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
783 && GET_CODE (src) == CONST_INT
784 && INTVAL (src) > 0
785 && 0 != (INTVAL (src)
786 & ((HOST_WIDE_INT) 1
9e69be8c 787 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 788 src = GEN_INT (INTVAL (src)
789 | ((HOST_WIDE_INT) (-1)
790 << GET_MODE_BITSIZE (GET_MODE (x))));
791#endif
792
951553af 793 reg_nonzero_bits[REGNO (x)]
9afa3d54 794 |= nonzero_bits (src, nonzero_bits_mode);
d0ab8cd3
RK		 795 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
796 if (reg_sign_bit_copies[REGNO (x)] == 0
797 || reg_sign_bit_copies[REGNO (x)] > num)
798 reg_sign_bit_copies[REGNO (x)] = num;
799 }
230d793d 800 else
d0ab8cd3 801 {
951553af 802 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
88306d12 803 reg_sign_bit_copies[REGNO (x)] = 1;
d0ab8cd3 804 }
230d793d
RS		 805 }
806}
807\f
808/* See if INSN can be combined into I3. PRED and SUCC are optionally
809 insns that were previously combined into I3 or that will be combined
810 into the merger of INSN and I3.
811
812 Return 0 if the combination is not allowed for any reason.
813
814 If the combination is allowed, *PDEST will be set to the single
815 destination of INSN and *PSRC to the single source, and this function
816 will return 1. */
817
818static int
819can_combine_p (insn, i3, pred, succ, pdest, psrc)
820 rtx insn;
821 rtx i3;
e51712db
KG		 822 rtx pred ATTRIBUTE_UNUSED;
823 rtx succ;
230d793d
RS		 824 rtx *pdest, *psrc;
825{
826 int i;
827 rtx set = 0, src, dest;
b729186a
JL		 828 rtx p;
829#ifdef AUTO_INC_DEC
76d31c63 830 rtx link;
b729186a 831#endif
230d793d
RS		 832 int all_adjacent = (succ ? (next_active_insn (insn) == succ
833 && next_active_insn (succ) == i3)
834 : next_active_insn (insn) == i3);
835
836 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
837 or a PARALLEL consisting of such a SET and CLOBBERs.
838
839 If INSN has CLOBBER parallel parts, ignore them for our processing.
840 By definition, these happen during the execution of the insn. When it
841 is merged with another insn, all bets are off. If they are, in fact,
842 needed and aren't also supplied in I3, they may be added by
843 recog_for_combine. Otherwise, it won't match.
844
845 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
846 note.
847
848 Get the source and destination of INSN. If more than one, can't
849 combine. */
850
851 if (GET_CODE (PATTERN (insn)) == SET)
852 set = PATTERN (insn);
853 else if (GET_CODE (PATTERN (insn)) == PARALLEL
854 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
855 {
856 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
857 {
858 rtx elt = XVECEXP (PATTERN (insn), 0, i);
859
860 switch (GET_CODE (elt))
861 {
e3258cef
R		 862 /* This is important to combine floating point insns
863 for the SH4 port. */
864 case USE:
865 /* Combining an isolated USE doesn't make sense.
866 We depend here on combinable_i3_pat to reject them. */
867 /* The code below this loop only verifies that the inputs of
868 the SET in INSN do not change. We call reg_set_between_p
869 to verify that the REG in the USE does not change betweeen
870 I3 and INSN.
871 If the USE in INSN was for a pseudo register, the matching
872 insn pattern will likely match any register; combining this
873 with any other USE would only be safe if we knew that the
874 used registers have identical values, or if there was
875 something to tell them apart, e.g. different modes. For
876 now, we forgo such compilcated tests and simply disallow
877 combining of USES of pseudo registers with any other USE. */
878 if (GET_CODE (XEXP (elt, 0)) == REG
879 && GET_CODE (PATTERN (i3)) == PARALLEL)
880 {
881 rtx i3pat = PATTERN (i3);
882 int i = XVECLEN (i3pat, 0) - 1;
883 int regno = REGNO (XEXP (elt, 0));
884 do
885 {
886 rtx i3elt = XVECEXP (i3pat, 0, i);
887 if (GET_CODE (i3elt) == USE
888 && GET_CODE (XEXP (i3elt, 0)) == REG
889 && (REGNO (XEXP (i3elt, 0)) == regno
890 ? reg_set_between_p (XEXP (elt, 0),
891 PREV_INSN (insn), i3)
892 : regno >= FIRST_PSEUDO_REGISTER))
893 return 0;
894 }
895 while (--i >= 0);
896 }
897 break;
898
230d793d
RS		 899 /* We can ignore CLOBBERs. */
900 case CLOBBER:
901 break;
902
903 case SET:
904 /* Ignore SETs whose result isn't used but not those that
905 have side-effects. */
906 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
907 && ! side_effects_p (elt))
908 break;
909
910 /* If we have already found a SET, this is a second one and
911 so we cannot combine with this insn. */
912 if (set)
913 return 0;
914
915 set = elt;
916 break;
917
918 default:
919 /* Anything else means we can't combine. */
920 return 0;
921 }
922 }
923
924 if (set == 0
925 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
926 so don't do anything with it. */
927 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
928 return 0;
929 }
930 else
931 return 0;
932
933 if (set == 0)
934 return 0;
935
936 set = expand_field_assignment (set);
937 src = SET_SRC (set), dest = SET_DEST (set);
938
939 /* Don't eliminate a store in the stack pointer. */
940 if (dest == stack_pointer_rtx
230d793d
RS		 941 /* If we couldn't eliminate a field assignment, we can't combine. */
942 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
943 /* Don't combine with an insn that sets a register to itself if it has
944 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
5f4f0e22 945 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
230d793d
RS		 946 /* Can't merge a function call. */
947 || GET_CODE (src) == CALL
cd5e8f1f 948 /* Don't eliminate a function call argument. */
4dca5ec5
RK		 949 || (GET_CODE (i3) == CALL_INSN
950 && (find_reg_fusage (i3, USE, dest)
951 || (GET_CODE (dest) == REG
952 && REGNO (dest) < FIRST_PSEUDO_REGISTER
953 && global_regs[REGNO (dest)])))
230d793d
RS		 954 /* Don't substitute into an incremented register. */
955 || FIND_REG_INC_NOTE (i3, dest)
956 || (succ && FIND_REG_INC_NOTE (succ, dest))
ec35104c 957#if 0
230d793d 958 /* Don't combine the end of a libcall into anything. */
ec35104c
JL		 959 /* ??? This gives worse code, and appears to be unnecessary, since no
960 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
961 use REG_RETVAL notes for noconflict blocks, but other code here
962 makes sure that those insns don't disappear. */
5f4f0e22 963 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
ec35104c 964#endif
230d793d
RS		 965 /* Make sure that DEST is not used after SUCC but before I3. */
966 || (succ && ! all_adjacent
967 && reg_used_between_p (dest, succ, i3))
968 /* Make sure that the value that is to be substituted for the register
969 does not use any registers whose values alter in between. However,
970 If the insns are adjacent, a use can't cross a set even though we
971 think it might (this can happen for a sequence of insns each setting
972 the same destination; reg_last_set of that register might point to
d81481d3
RK		 973 a NOTE). If INSN has a REG_EQUIV note, the register is always
974 equivalent to the memory so the substitution is valid even if there
975 are intervening stores. Also, don't move a volatile asm or
976 UNSPEC_VOLATILE across any other insns. */
230d793d 977 || (! all_adjacent
d81481d3
RK		 978 && (((GET_CODE (src) != MEM
979 || ! find_reg_note (insn, REG_EQUIV, src))
980 && use_crosses_set_p (src, INSN_CUID (insn)))
a66a10c7
RS		 981 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
982 || GET_CODE (src) == UNSPEC_VOLATILE))
230d793d
RS		 983 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
984 better register allocation by not doing the combine. */
985 || find_reg_note (i3, REG_NO_CONFLICT, dest)
986 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
987 /* Don't combine across a CALL_INSN, because that would possibly
988 change whether the life span of some REGs crosses calls or not,
989 and it is a pain to update that information.
990 Exception: if source is a constant, moving it later can't hurt.
991 Accept that special case, because it helps -fforce-addr a lot. */
992 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
993 return 0;
994
995 /* DEST must either be a REG or CC0. */
996 if (GET_CODE (dest) == REG)
997 {
998 /* If register alignment is being enforced for multi-word items in all
999 cases except for parameters, it is possible to have a register copy
1000 insn referencing a hard register that is not allowed to contain the
1001 mode being copied and which would not be valid as an operand of most
1002 insns. Eliminate this problem by not combining with such an insn.
1003
1004 Also, on some machines we don't want to extend the life of a hard
4d2c432d
RK		 1005 register.
1006
1007 This is the same test done in can_combine except that we don't test
1008 if SRC is a CALL operation to permit a hard register with
1009 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1010 into account. */
230d793d
RS		 1011
1012 if (GET_CODE (src) == REG
1013 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1014 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
c448a43e
RK		 1015 /* Don't extend the life of a hard register unless it is
1016 user variable (if we have few registers) or it can't
1017 fit into the desired register (meaning something special
ecd40809
RK		 1018 is going on).
1019 Also avoid substituting a return register into I3, because
1020 reload can't handle a conflict with constraints of other
1021 inputs. */
230d793d 1022 || (REGNO (src) < FIRST_PSEUDO_REGISTER
c448a43e 1023 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
f95182a4
ILT		 1024 || (SMALL_REGISTER_CLASSES
1025 && ((! all_adjacent && ! REG_USERVAR_P (src))
1026 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
e9a25f70 1027 && ! REG_USERVAR_P (src))))))))
230d793d
RS		 1028 return 0;
1029 }
1030 else if (GET_CODE (dest) != CC0)
1031 return 0;
1032
5f96750d
RS		 1033 /* Don't substitute for a register intended as a clobberable operand.
1034 Similarly, don't substitute an expression containing a register that
1035 will be clobbered in I3. */
230d793d
RS		 1036 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1037 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1038 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
5f96750d
RS		 1039 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1040 src)
1041 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
230d793d
RS		 1042 return 0;
1043
1044 /* If INSN contains anything volatile, or is an `asm' (whether volatile
d276f2bb 1045 or not), reject, unless nothing volatile comes between it and I3 */
230d793d
RS		 1046
1047 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
d276f2bb
CM		 1048 {
1049 /* Make sure succ doesn't contain a volatile reference. */
1050 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1051 return 0;
1052
1053 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1054 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1055 && p != succ && volatile_refs_p (PATTERN (p)))
1056 return 0;
1057 }
230d793d 1058
b79ee7eb
RH		 1059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1060 to be an explicit register variable, and was chosen for a reason. */
1061
1062 if (GET_CODE (src) == ASM_OPERANDS
1063 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1064 return 0;
1065
4b2cb4a2
RS		 1066 /* If there are any volatile insns between INSN and I3, reject, because
1067 they might affect machine state. */
1068
1069 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1070 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1071 && p != succ && volatile_insn_p (PATTERN (p)))
1072 return 0;
1073
230d793d
RS		 1074 /* If INSN or I2 contains an autoincrement or autodecrement,
1075 make sure that register is not used between there and I3,
1076 and not already used in I3 either.
1077 Also insist that I3 not be a jump; if it were one
1078 and the incremented register were spilled, we would lose. */
1079
1080#ifdef AUTO_INC_DEC
1081 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1082 if (REG_NOTE_KIND (link) == REG_INC
1083 && (GET_CODE (i3) == JUMP_INSN
1084 || reg_used_between_p (XEXP (link, 0), insn, i3)
1085 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1086 return 0;
1087#endif
1088
1089#ifdef HAVE_cc0
1090 /* Don't combine an insn that follows a CC0-setting insn.
1091 An insn that uses CC0 must not be separated from the one that sets it.
1092 We do, however, allow I2 to follow a CC0-setting insn if that insn
1093 is passed as I1; in that case it will be deleted also.
1094 We also allow combining in this case if all the insns are adjacent
1095 because that would leave the two CC0 insns adjacent as well.
1096 It would be more logical to test whether CC0 occurs inside I1 or I2,
1097 but that would be much slower, and this ought to be equivalent. */
1098
1099 p = prev_nonnote_insn (insn);
1100 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1101 && ! all_adjacent)
1102 return 0;
1103#endif
1104
1105 /* If we get here, we have passed all the tests and the combination is
1106 to be allowed. */
1107
1108 *pdest = dest;
1109 *psrc = src;
1110
1111 return 1;
1112}
1113\f
956d6950
JL		 1114/* Check if PAT is an insn - or a part of it - used to set up an
1115 argument for a function in a hard register. */
1116
1117static int
1118sets_function_arg_p (pat)
1119 rtx pat;
1120{
1121 int i;
1122 rtx inner_dest;
1123
1124 switch (GET_CODE (pat))
1125 {
1126 case INSN:
1127 return sets_function_arg_p (PATTERN (pat));
1128
1129 case PARALLEL:
1130 for (i = XVECLEN (pat, 0); --i >= 0;)
1131 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1132 return 1;
1133
1134 break;
1135
1136 case SET:
1137 inner_dest = SET_DEST (pat);
1138 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1139 || GET_CODE (inner_dest) == SUBREG
1140 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1141 inner_dest = XEXP (inner_dest, 0);
1142
1143 return (GET_CODE (inner_dest) == REG
1144 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1145 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1d300e19
KG		 1146
1147 default:
1148 break;
956d6950
JL		 1149 }
1150
1151 return 0;
1152}
1153
230d793d
RS		 1154/* LOC is the location within I3 that contains its pattern or the component
1155 of a PARALLEL of the pattern. We validate that it is valid for combining.
1156
1157 One problem is if I3 modifies its output, as opposed to replacing it
1158 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1159 so would produce an insn that is not equivalent to the original insns.
1160
1161 Consider:
1162
1163 (set (reg:DI 101) (reg:DI 100))
1164 (set (subreg:SI (reg:DI 101) 0) <foo>)
1165
1166 This is NOT equivalent to:
1167
1168 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1169 (set (reg:DI 101) (reg:DI 100))])
1170
1171 Not only does this modify 100 (in which case it might still be valid
1172 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1173
1174 We can also run into a problem if I2 sets a register that I1
1175 uses and I1 gets directly substituted into I3 (not via I2). In that
1176 case, we would be getting the wrong value of I2DEST into I3, so we
1177 must reject the combination. This case occurs when I2 and I1 both
1178 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1179 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1180 of a SET must prevent combination from occurring.
1181
e9a25f70 1182 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
c448a43e
RK		 1183 if the destination of a SET is a hard register that isn't a user
1184 variable.
230d793d
RS		 1185
1186 Before doing the above check, we first try to expand a field assignment
1187 into a set of logical operations.
1188
1189 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1190 we place a register that is both set and used within I3. If more than one
1191 such register is detected, we fail.
1192
1193 Return 1 if the combination is valid, zero otherwise. */
1194
1195static int
1196combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1197 rtx i3;
1198 rtx *loc;
1199 rtx i2dest;
1200 rtx i1dest;
1201 int i1_not_in_src;
1202 rtx *pi3dest_killed;
1203{
1204 rtx x = *loc;
1205
1206 if (GET_CODE (x) == SET)
1207 {
1208 rtx set = expand_field_assignment (x);
1209 rtx dest = SET_DEST (set);
1210 rtx src = SET_SRC (set);
29a82058
JL		 1211 rtx inner_dest = dest;
1212
1213#if 0
1214 rtx inner_src = src;
1215#endif
230d793d
RS		 1216
1217 SUBST (*loc, set);
1218
1219 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest) == SUBREG
1221 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1222 inner_dest = XEXP (inner_dest, 0);
1223
1224 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1225 was added. */
1226#if 0
1227 while (GET_CODE (inner_src) == STRICT_LOW_PART
1228 || GET_CODE (inner_src) == SUBREG
1229 || GET_CODE (inner_src) == ZERO_EXTRACT)
1230 inner_src = XEXP (inner_src, 0);
1231
1232 /* If it is better that two different modes keep two different pseudos,
1233 avoid combining them. This avoids producing the following pattern
1234 on a 386:
1235 (set (subreg:SI (reg/v:QI 21) 0)
1236 (lshiftrt:SI (reg/v:SI 20)
1237 (const_int 24)))
1238 If that were made, reload could not handle the pair of
1239 reg 20/21, since it would try to get any GENERAL_REGS
1240 but some of them don't handle QImode. */
1241
1242 if (rtx_equal_p (inner_src, i2dest)
1243 && GET_CODE (inner_dest) == REG
1244 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1245 return 0;
1246#endif
1247
1248 /* Check for the case where I3 modifies its output, as
1249 discussed above. */
1250 if ((inner_dest != dest
1251 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1252 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
956d6950 1253
3f508eca
RK		 1254 /* This is the same test done in can_combine_p except that we
1255 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
956d6950
JL		 1256 CALL operation. Moreover, we can't test all_adjacent; we don't
1257 have to, since this instruction will stay in place, thus we are
1258 not considering increasing the lifetime of INNER_DEST.
1259
1260 Also, if this insn sets a function argument, combining it with
1261 something that might need a spill could clobber a previous
1262 function argument; the all_adjacent test in can_combine_p also
1263 checks this; here, we do a more specific test for this case. */
1264
230d793d 1265 || (GET_CODE (inner_dest) == REG
dfbe1b2f 1266 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
c448a43e
RK		 1267 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1268 GET_MODE (inner_dest))
e9a25f70
JL		 1269 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1270 && ! REG_USERVAR_P (inner_dest)
956d6950
JL		 1271 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1272 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1273 && i3 != 0
1274 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
230d793d
RS		 1275 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1276 return 0;
1277
1278 /* If DEST is used in I3, it is being killed in this insn,
36a9c2e9
JL		 1279 so record that for later.
1280 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1281 STACK_POINTER_REGNUM, since these are always considered to be
1282 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
230d793d 1283 if (pi3dest_killed && GET_CODE (dest) == REG
36a9c2e9
JL		 1284 && reg_referenced_p (dest, PATTERN (i3))
1285 && REGNO (dest) != FRAME_POINTER_REGNUM
6d7096b0
DE		 1286#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1287 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1288#endif
36a9c2e9
JL		 1289#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1290 && (REGNO (dest) != ARG_POINTER_REGNUM
1291 || ! fixed_regs [REGNO (dest)])
1292#endif
1293 && REGNO (dest) != STACK_POINTER_REGNUM)
230d793d
RS		 1294 {
1295 if (*pi3dest_killed)
1296 return 0;
1297
1298 *pi3dest_killed = dest;
1299 }
1300 }
1301
1302 else if (GET_CODE (x) == PARALLEL)
1303 {
1304 int i;
1305
1306 for (i = 0; i < XVECLEN (x, 0); i++)
1307 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1308 i1_not_in_src, pi3dest_killed))
1309 return 0;
1310 }
1311
1312 return 1;
1313}
1314\f
1315/* Try to combine the insns I1 and I2 into I3.
1316 Here I1 and I2 appear earlier than I3.
1317 I1 can be zero; then we combine just I2 into I3.
1318
1319 It we are combining three insns and the resulting insn is not recognized,
1320 try splitting it into two insns. If that happens, I2 and I3 are retained
1321 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1322 are pseudo-deleted.
1323
abe6e52f
RK		 1324 Return 0 if the combination does not work. Then nothing is changed.
1325 If we did the combination, return the insn at which combine should
1326 resume scanning. */
230d793d
RS		 1327
1328static rtx
1329try_combine (i3, i2, i1)
1330 register rtx i3, i2, i1;
1331{
1332 /* New patterns for I3 and I3, respectively. */
1333 rtx newpat, newi2pat = 0;
1334 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1335 int added_sets_1, added_sets_2;
1336 /* Total number of SETs to put into I3. */
1337 int total_sets;
1338 /* Nonzero is I2's body now appears in I3. */
1339 int i2_is_used;
1340 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1341 int insn_code_number, i2_code_number, other_code_number;
1342 /* Contains I3 if the destination of I3 is used in its source, which means
1343 that the old life of I3 is being killed. If that usage is placed into
1344 I2 and not in I3, a REG_DEAD note must be made. */
1345 rtx i3dest_killed = 0;
1346 /* SET_DEST and SET_SRC of I2 and I1. */
1347 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1348 /* PATTERN (I2), or a copy of it in certain cases. */
1349 rtx i2pat;
1350 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
c4e861e8 1351 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
230d793d
RS		 1352 int i1_feeds_i3 = 0;
1353 /* Notes that must be added to REG_NOTES in I3 and I2. */
1354 rtx new_i3_notes, new_i2_notes;
176c9e6b
JW		 1355 /* Notes that we substituted I3 into I2 instead of the normal case. */
1356 int i3_subst_into_i2 = 0;
df7d75de
RK		 1357 /* Notes that I1, I2 or I3 is a MULT operation. */
1358 int have_mult = 0;
230d793d
RS		 1359
1360 int maxreg;
1361 rtx temp;
1362 register rtx link;
1363 int i;
1364
1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1366 This can occur when flow deletes an insn that it has merged into an
1367 auto-increment address. We also can't do anything if I3 has a
1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1369 libcall. */
1370
1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
ec35104c
JL		 1374#if 0
1375 /* ??? This gives worse code, and appears to be unnecessary, since no
1376 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1377 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1378#endif
1379)
230d793d
RS		 1380 return 0;
1381
1382 combine_attempts++;
1383
241cea85 1384 undobuf.undos = undobuf.previous_undos = 0;
230d793d
RS		 1385 undobuf.other_insn = 0;
1386
1387 /* Save the current high-water-mark so we can free storage if we didn't
1388 accept this combination. */
1389 undobuf.storage = (char *) oballoc (0);
1390
6e25d159
RK		 1391 /* Reset the hard register usage information. */
1392 CLEAR_HARD_REG_SET (newpat_used_regs);
1393
230d793d
RS		 1394 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1395 code below, set I1 to be the earlier of the two insns. */
1396 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1397 temp = i1, i1 = i2, i2 = temp;
1398
abe6e52f 1399 added_links_insn = 0;
137e889e 1400
230d793d
RS		 1401 /* First check for one important special-case that the code below will
1402 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1403 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1404 we may be able to replace that destination with the destination of I3.
1405 This occurs in the common code where we compute both a quotient and
1406 remainder into a structure, in which case we want to do the computation
1407 directly into the structure to avoid register-register copies.
1408
1409 We make very conservative checks below and only try to handle the
1410 most common cases of this. For example, we only handle the case
1411 where I2 and I3 are adjacent to avoid making difficult register
1412 usage tests. */
1413
1414 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1415 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1416 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
f95182a4 1417 && (! SMALL_REGISTER_CLASSES
e9a25f70
JL		 1418 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1419 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1420 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
230d793d
RS		 1421 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1422 && GET_CODE (PATTERN (i2)) == PARALLEL
1423 && ! side_effects_p (SET_DEST (PATTERN (i3)))
5089e22e
RS		 1424 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1425 below would need to check what is inside (and reg_overlap_mentioned_p
1426 doesn't support those codes anyway). Don't allow those destinations;
1427 the resulting insn isn't likely to be recognized anyway. */
1428 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1429 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
230d793d
RS		 1430 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1431 SET_DEST (PATTERN (i3)))
1432 && next_real_insn (i2) == i3)
5089e22e
RS		 1433 {
1434 rtx p2 = PATTERN (i2);
1435
1436 /* Make sure that the destination of I3,
1437 which we are going to substitute into one output of I2,
1438 is not used within another output of I2. We must avoid making this:
1439 (parallel [(set (mem (reg 69)) ...)
1440 (set (reg 69) ...)])
1441 which is not well-defined as to order of actions.
1442 (Besides, reload can't handle output reloads for this.)
1443
1444 The problem can also happen if the dest of I3 is a memory ref,
1445 if another dest in I2 is an indirect memory ref. */
1446 for (i = 0; i < XVECLEN (p2, 0); i++)
7ca919b7
RK		 1447 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1448 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
5089e22e
RS		 1449 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1450 SET_DEST (XVECEXP (p2, 0, i))))
1451 break;
230d793d 1452
5089e22e
RS		 1453 if (i == XVECLEN (p2, 0))
1454 for (i = 0; i < XVECLEN (p2, 0); i++)
1455 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1456 {
1457 combine_merges++;
230d793d 1458
5089e22e
RS		 1459 subst_insn = i3;
1460 subst_low_cuid = INSN_CUID (i2);
230d793d 1461
c4e861e8 1462 added_sets_2 = added_sets_1 = 0;
5089e22e 1463 i2dest = SET_SRC (PATTERN (i3));
230d793d 1464
5089e22e
RS		 1465 /* Replace the dest in I2 with our dest and make the resulting
1466 insn the new pattern for I3. Then skip to where we
1467 validate the pattern. Everything was set up above. */
1468 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1469 SET_DEST (PATTERN (i3)));
1470
1471 newpat = p2;
176c9e6b 1472 i3_subst_into_i2 = 1;
5089e22e
RS		 1473 goto validate_replacement;
1474 }
1475 }
230d793d
RS		 1476
1477#ifndef HAVE_cc0
1478 /* If we have no I1 and I2 looks like:
1479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1480 (set Y OP)])
1481 make up a dummy I1 that is
1482 (set Y OP)
1483 and change I2 to be
1484 (set (reg:CC X) (compare:CC Y (const_int 0)))
1485
1486 (We can ignore any trailing CLOBBERs.)
1487
1488 This undoes a previous combination and allows us to match a branch-and-
1489 decrement insn. */
1490
1491 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1492 && XVECLEN (PATTERN (i2), 0) >= 2
1493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1495 == MODE_CC)
1496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1498 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1499 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1501 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1502 {
1503 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1504 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1505 break;
1506
1507 if (i == 1)
1508 {
1509 /* We make I1 with the same INSN_UID as I2. This gives it
1510 the same INSN_CUID for value tracking. Our fake I1 will
1511 never appear in the insn stream so giving it the same INSN_UID
1512 as I2 will not cause a problem. */
1513
0d9641d1 1514 subst_prev_insn = i1
38a448ca
RH		 1515 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1516 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1517 NULL_RTX);
230d793d
RS		 1518
1519 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1520 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1521 SET_DEST (PATTERN (i1)));
1522 }
1523 }
1524#endif
1525
1526 /* Verify that I2 and I1 are valid for combining. */
5f4f0e22
CH		 1527 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1528 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
230d793d
RS		 1529 {
1530 undo_all ();
1531 return 0;
1532 }
1533
1534 /* Record whether I2DEST is used in I2SRC and similarly for the other
1535 cases. Knowing this will help in register status updating below. */
1536 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1537 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1538 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1539
916f14f1 1540 /* See if I1 directly feeds into I3. It does if I1DEST is not used
230d793d
RS		 1541 in I2SRC. */
1542 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1543
1544 /* Ensure that I3's pattern can be the destination of combines. */
1545 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1546 i1 && i2dest_in_i1src && i1_feeds_i3,
1547 &i3dest_killed))
1548 {
1549 undo_all ();
1550 return 0;
1551 }
1552
df7d75de
RK		 1553 /* See if any of the insns is a MULT operation. Unless one is, we will
1554 reject a combination that is, since it must be slower. Be conservative
1555 here. */
1556 if (GET_CODE (i2src) == MULT
1557 || (i1 != 0 && GET_CODE (i1src) == MULT)
1558 || (GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1560 have_mult = 1;
1561
230d793d
RS		 1562 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1563 We used to do this EXCEPT in one case: I3 has a post-inc in an
1564 output operand. However, that exception can give rise to insns like
1565 mov r3,(r3)+
1566 which is a famous insn on the PDP-11 where the value of r3 used as the
5089e22e 1567 source was model-dependent. Avoid this sort of thing. */
230d793d
RS		 1568
1569#if 0
1570 if (!(GET_CODE (PATTERN (i3)) == SET
1571 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1572 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1573 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1574 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1575 /* It's not the exception. */
1576#endif
1577#ifdef AUTO_INC_DEC
1578 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1579 if (REG_NOTE_KIND (link) == REG_INC
1580 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1581 || (i1 != 0
1582 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1583 {
1584 undo_all ();
1585 return 0;
1586 }
1587#endif
1588
1589 /* See if the SETs in I1 or I2 need to be kept around in the merged
1590 instruction: whenever the value set there is still needed past I3.
1591 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1592
1593 For the SET in I1, we have two cases: If I1 and I2 independently
1594 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1595 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1596 in I1 needs to be kept around unless I1DEST dies or is set in either
1597 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1598 I1DEST. If so, we know I1 feeds into I2. */
1599
1600 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1601
1602 added_sets_1
1603 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1604 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1605
1606 /* If the set in I2 needs to be kept around, we must make a copy of
1607 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
5089e22e 1608 PATTERN (I2), we are only substituting for the original I1DEST, not into
230d793d
RS		 1609 an already-substituted copy. This also prevents making self-referential
1610 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1611 I2DEST. */
1612
1613 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
38a448ca 1614 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
230d793d
RS		 1615 : PATTERN (i2));
1616
1617 if (added_sets_2)
1618 i2pat = copy_rtx (i2pat);
1619
1620 combine_merges++;
1621
1622 /* Substitute in the latest insn for the regs set by the earlier ones. */
1623
1624 maxreg = max_reg_num ();
1625
1626 subst_insn = i3;
230d793d
RS		 1627
1628 /* It is possible that the source of I2 or I1 may be performing an
1629 unneeded operation, such as a ZERO_EXTEND of something that is known
1630 to have the high part zero. Handle that case by letting subst look at
1631 the innermost one of them.
1632
1633 Another way to do this would be to have a function that tries to
1634 simplify a single insn instead of merging two or more insns. We don't
1635 do this because of the potential of infinite loops and because
1636 of the potential extra memory required. However, doing it the way
1637 we are is a bit of a kludge and doesn't catch all cases.
1638
1639 But only do this if -fexpensive-optimizations since it slows things down
1640 and doesn't usually win. */
1641
1642 if (flag_expensive_optimizations)
1643 {
1644 /* Pass pc_rtx so no substitutions are done, just simplifications.
1645 The cases that we are interested in here do not involve the few
1646 cases were is_replaced is checked. */
1647 if (i1)
d0ab8cd3
RK		 1648 {
1649 subst_low_cuid = INSN_CUID (i1);
1650 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1651 }
230d793d 1652 else
d0ab8cd3
RK		 1653 {
1654 subst_low_cuid = INSN_CUID (i2);
1655 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1656 }
230d793d 1657
241cea85 1658 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1659 }
1660
1661#ifndef HAVE_cc0
1662 /* Many machines that don't use CC0 have insns that can both perform an
1663 arithmetic operation and set the condition code. These operations will
1664 be represented as a PARALLEL with the first element of the vector
1665 being a COMPARE of an arithmetic operation with the constant zero.
1666 The second element of the vector will set some pseudo to the result
1667 of the same arithmetic operation. If we simplify the COMPARE, we won't
1668 match such a pattern and so will generate an extra insn. Here we test
1669 for this case, where both the comparison and the operation result are
1670 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1671 I2SRC. Later we will make the PARALLEL that contains I2. */
1672
1673 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1674 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1675 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1676 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1677 {
081f5e7e 1678#ifdef EXTRA_CC_MODES
230d793d
RS		 1679 rtx *cc_use;
1680 enum machine_mode compare_mode;
081f5e7e 1681#endif
230d793d
RS		 1682
1683 newpat = PATTERN (i3);
1684 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1685
1686 i2_is_used = 1;
1687
1688#ifdef EXTRA_CC_MODES
1689 /* See if a COMPARE with the operand we substituted in should be done
1690 with the mode that is currently being used. If not, do the same
1691 processing we do in `subst' for a SET; namely, if the destination
1692 is used only once, try to replace it with a register of the proper
1693 mode and also replace the COMPARE. */
1694 if (undobuf.other_insn == 0
1695 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1696 &undobuf.other_insn))
77fa0940
RK		 1697 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1698 i2src, const0_rtx))
230d793d
RS		 1699 != GET_MODE (SET_DEST (newpat))))
1700 {
1701 int regno = REGNO (SET_DEST (newpat));
38a448ca 1702 rtx new_dest = gen_rtx_REG (compare_mode, regno);
230d793d
RS		 1703
1704 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 1705 || (REG_N_SETS (regno) == 1 && ! added_sets_2
230d793d
RS		 1706 && ! REG_USERVAR_P (SET_DEST (newpat))))
1707 {
1708 if (regno >= FIRST_PSEUDO_REGISTER)
1709 SUBST (regno_reg_rtx[regno], new_dest);
1710
1711 SUBST (SET_DEST (newpat), new_dest);
1712 SUBST (XEXP (*cc_use, 0), new_dest);
1713 SUBST (SET_SRC (newpat),
1714 gen_rtx_combine (COMPARE, compare_mode,
1715 i2src, const0_rtx));
1716 }
1717 else
1718 undobuf.other_insn = 0;
1719 }
1720#endif
1721 }
1722 else
1723#endif
1724 {
1725 n_occurrences = 0; /* `subst' counts here */
1726
1727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1728 need to make a unique copy of I2SRC each time we substitute it
1729 to avoid self-referential rtl. */
1730
d0ab8cd3 1731 subst_low_cuid = INSN_CUID (i2);
230d793d
RS		 1732 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1733 ! i1_feeds_i3 && i1dest_in_i1src);
241cea85 1734 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1735
1736 /* Record whether i2's body now appears within i3's body. */
1737 i2_is_used = n_occurrences;
1738 }
1739
1740 /* If we already got a failure, don't try to do more. Otherwise,
1741 try to substitute in I1 if we have it. */
1742
1743 if (i1 && GET_CODE (newpat) != CLOBBER)
1744 {
1745 /* Before we can do this substitution, we must redo the test done
1746 above (see detailed comments there) that ensures that I1DEST
0f41302f 1747 isn't mentioned in any SETs in NEWPAT that are field assignments. */
230d793d 1748
5f4f0e22
CH		 1749 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1750 0, NULL_PTR))
230d793d
RS		 1751 {
1752 undo_all ();
1753 return 0;
1754 }
1755
1756 n_occurrences = 0;
d0ab8cd3 1757 subst_low_cuid = INSN_CUID (i1);
230d793d 1758 newpat = subst (newpat, i1dest, i1src, 0, 0);
241cea85 1759 undobuf.previous_undos = undobuf.undos;
230d793d
RS		 1760 }
1761
916f14f1
RK		 1762 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1763 to count all the ways that I2SRC and I1SRC can be used. */
5f4f0e22 1764 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
916f14f1 1765 && i2_is_used + added_sets_2 > 1)
5f4f0e22 1766 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
916f14f1
RK		 1767 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1768 > 1))
230d793d
RS		 1769 /* Fail if we tried to make a new register (we used to abort, but there's
1770 really no reason to). */
1771 || max_reg_num () != maxreg
1772 /* Fail if we couldn't do something and have a CLOBBER. */
df7d75de
RK		 1773 || GET_CODE (newpat) == CLOBBER
1774 /* Fail if this new pattern is a MULT and we didn't have one before
1775 at the outer level. */
1776 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1777 && ! have_mult))
230d793d
RS		 1778 {
1779 undo_all ();
1780 return 0;
1781 }
1782
1783 /* If the actions of the earlier insns must be kept
1784 in addition to substituting them into the latest one,
1785 we must make a new PARALLEL for the latest insn
1786 to hold additional the SETs. */
1787
1788 if (added_sets_1 || added_sets_2)
1789 {
1790 combine_extras++;
1791
1792 if (GET_CODE (newpat) == PARALLEL)
1793 {
1794 rtvec old = XVEC (newpat, 0);
1795 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
38a448ca 1796 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
59888de2 1797 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
230d793d
RS		 1798 sizeof (old->elem[0]) * old->num_elem);
1799 }
1800 else
1801 {
1802 rtx old = newpat;
1803 total_sets = 1 + added_sets_1 + added_sets_2;
38a448ca 1804 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
230d793d
RS		 1805 XVECEXP (newpat, 0, 0) = old;
1806 }
1807
1808 if (added_sets_1)
1809 XVECEXP (newpat, 0, --total_sets)
1810 = (GET_CODE (PATTERN (i1)) == PARALLEL
38a448ca 1811 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
230d793d
RS		 1812
1813 if (added_sets_2)
1814 {
1815 /* If there is no I1, use I2's body as is. We used to also not do
1816 the subst call below if I2 was substituted into I3,
1817 but that could lose a simplification. */
1818 if (i1 == 0)
1819 XVECEXP (newpat, 0, --total_sets) = i2pat;
1820 else
1821 /* See comment where i2pat is assigned. */
1822 XVECEXP (newpat, 0, --total_sets)
1823 = subst (i2pat, i1dest, i1src, 0, 0);
1824 }
1825 }
1826
1827 /* We come here when we are replacing a destination in I2 with the
1828 destination of I3. */
1829 validate_replacement:
1830
6e25d159
RK		 1831 /* Note which hard regs this insn has as inputs. */
1832 mark_used_regs_combine (newpat);
1833
230d793d 1834 /* Is the result of combination a valid instruction? */
8e2f6e35 1835 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1836
1837 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1838 the second SET's destination is a register that is unused. In that case,
1839 we just need the first SET. This can occur when simplifying a divmod
1840 insn. We *must* test for this case here because the code below that
1841 splits two independent SETs doesn't handle this case correctly when it
1842 updates the register status. Also check the case where the first
1843 SET's destination is unused. That would not cause incorrect code, but
1844 does cause an unneeded insn to remain. */
1845
1846 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1847 && XVECLEN (newpat, 0) == 2
1848 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1849 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1850 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1851 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1852 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1853 && asm_noperands (newpat) < 0)
1854 {
1855 newpat = XVECEXP (newpat, 0, 0);
8e2f6e35 1856 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1857 }
1858
1859 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1860 && XVECLEN (newpat, 0) == 2
1861 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1862 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1863 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1864 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1865 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1866 && asm_noperands (newpat) < 0)
1867 {
1868 newpat = XVECEXP (newpat, 0, 1);
8e2f6e35 1869 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 1870 }
1871
1872 /* If we were combining three insns and the result is a simple SET
1873 with no ASM_OPERANDS that wasn't recognized, try to split it into two
916f14f1
RK		 1874 insns. There are two ways to do this. It can be split using a
1875 machine-specific method (like when you have an addition of a large
1876 constant) or by combine in the function find_split_point. */
1877
230d793d
RS		 1878 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1879 && asm_noperands (newpat) < 0)
1880 {
916f14f1 1881 rtx m_split, *split;
42495ca0 1882 rtx ni2dest = i2dest;
916f14f1
RK		 1883
1884 /* See if the MD file can split NEWPAT. If it can't, see if letting it
42495ca0
RK		 1885 use I2DEST as a scratch register will help. In the latter case,
1886 convert I2DEST to the mode of the source of NEWPAT if we can. */
916f14f1
RK		 1887
1888 m_split = split_insns (newpat, i3);
a70c61d9
JW		 1889
1890 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1891 inputs of NEWPAT. */
1892
1893 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1894 possible to try that as a scratch reg. This would require adding
1895 more code to make it work though. */
1896
1897 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
42495ca0
RK		 1898 {
1899 /* If I2DEST is a hard register or the only use of a pseudo,
1900 we can change its mode. */
1901 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
02f4ada4 1902 && GET_MODE (SET_DEST (newpat)) != VOIDmode
60654f77 1903 && GET_CODE (i2dest) == REG
42495ca0 1904 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1905 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
42495ca0 1906 && ! REG_USERVAR_P (i2dest))))
38a448ca 1907 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
42495ca0
RK		 1908 REGNO (i2dest));
1909
38a448ca
RH		 1910 m_split = split_insns
1911 (gen_rtx_PARALLEL (VOIDmode,
1912 gen_rtvec (2, newpat,
1913 gen_rtx_CLOBBER (VOIDmode,
1914 ni2dest))),
1915 i3);
42495ca0 1916 }
916f14f1
RK		 1917
1918 if (m_split && GET_CODE (m_split) == SEQUENCE
3f508eca
RK		 1919 && XVECLEN (m_split, 0) == 2
1920 && (next_real_insn (i2) == i3
1921 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1922 INSN_CUID (i2))))
916f14f1 1923 {
1a26b032 1924 rtx i2set, i3set;
d0ab8cd3 1925 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
916f14f1 1926 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
916f14f1 1927
e4ba89be
RK		 1928 i3set = single_set (XVECEXP (m_split, 0, 1));
1929 i2set = single_set (XVECEXP (m_split, 0, 0));
1a26b032 1930
42495ca0
RK		 1931 /* In case we changed the mode of I2DEST, replace it in the
1932 pseudo-register table here. We can't do it above in case this
1933 code doesn't get executed and we do a split the other way. */
1934
1935 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1936 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1937
8e2f6e35 1938 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1a26b032
RK		 1939
1940 /* If I2 or I3 has multiple SETs, we won't know how to track
9cc96794
RK		 1941 register status, so don't use these insns. If I2's destination
1942 is used between I2 and I3, we also can't use these insns. */
1a26b032 1943
9cc96794
RK		 1944 if (i2_code_number >= 0 && i2set && i3set
1945 && (next_real_insn (i2) == i3
1946 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
8e2f6e35
BS		 1947 insn_code_number = recog_for_combine (&newi3pat, i3,
1948 &new_i3_notes);
d0ab8cd3
RK		 1949 if (insn_code_number >= 0)
1950 newpat = newi3pat;
1951
c767f54b 1952 /* It is possible that both insns now set the destination of I3.
22609cbf 1953 If so, we must show an extra use of it. */
c767f54b 1954
393de53f
RK		 1955 if (insn_code_number >= 0)
1956 {
1957 rtx new_i3_dest = SET_DEST (i3set);
1958 rtx new_i2_dest = SET_DEST (i2set);
1959
1960 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1961 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1962 || GET_CODE (new_i3_dest) == SUBREG)
1963 new_i3_dest = XEXP (new_i3_dest, 0);
1964
d4096689
RK		 1965 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1966 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1967 || GET_CODE (new_i2_dest) == SUBREG)
1968 new_i2_dest = XEXP (new_i2_dest, 0);
1969
393de53f
RK		 1970 if (GET_CODE (new_i3_dest) == REG
1971 && GET_CODE (new_i2_dest) == REG
1972 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
b1f21e0a 1973 REG_N_SETS (REGNO (new_i2_dest))++;
393de53f 1974 }
916f14f1 1975 }
230d793d
RS		 1976
1977 /* If we can split it and use I2DEST, go ahead and see if that
1978 helps things be recognized. Verify that none of the registers
1979 are set between I2 and I3. */
d0ab8cd3 1980 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
230d793d
RS		 1981#ifdef HAVE_cc0
1982 && GET_CODE (i2dest) == REG
1983#endif
1984 /* We need I2DEST in the proper mode. If it is a hard register
1985 or the only use of a pseudo, we can change its mode. */
1986 && (GET_MODE (*split) == GET_MODE (i2dest)
1987 || GET_MODE (*split) == VOIDmode
1988 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
b1f21e0a 1989 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
230d793d
RS		 1990 && ! REG_USERVAR_P (i2dest)))
1991 && (next_real_insn (i2) == i3
1992 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1993 /* We can't overwrite I2DEST if its value is still used by
1994 NEWPAT. */
1995 && ! reg_referenced_p (i2dest, newpat))
1996 {
1997 rtx newdest = i2dest;
df7d75de
RK		 1998 enum rtx_code split_code = GET_CODE (*split);
1999 enum machine_mode split_mode = GET_MODE (*split);
230d793d
RS		 2000
2001 /* Get NEWDEST as a register in the proper mode. We have already
2002 validated that we can do this. */
df7d75de 2003 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
230d793d 2004 {
38a448ca 2005 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
230d793d
RS		 2006
2007 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2008 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2009 }
2010
2011 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2012 an ASHIFT. This can occur if it was inside a PLUS and hence
2013 appeared to be a memory address. This is a kludge. */
df7d75de 2014 if (split_code == MULT
230d793d
RS		 2015 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2016 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1dc8a823
JW		 2017 {
2018 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2019 XEXP (*split, 0), GEN_INT (i)));
2020 /* Update split_code because we may not have a multiply
2021 anymore. */
2022 split_code = GET_CODE (*split);
2023 }
230d793d
RS		 2024
2025#ifdef INSN_SCHEDULING
2026 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2027 be written as a ZERO_EXTEND. */
df7d75de
RK		 2028 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2029 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
230d793d
RS		 2030 XEXP (*split, 0)));
2031#endif
2032
2033 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2034 SUBST (*split, newdest);
8e2f6e35 2035 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
df7d75de
RK		 2036
2037 /* If the split point was a MULT and we didn't have one before,
2038 don't use one now. */
2039 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
8e2f6e35 2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 2041 }
2042 }
2043
2044 /* Check for a case where we loaded from memory in a narrow mode and
2045 then sign extended it, but we need both registers. In that case,
2046 we have a PARALLEL with both loads from the same memory location.
2047 We can split this into a load from memory followed by a register-register
2048 copy. This saves at least one insn, more if register allocation can
f0343c74
RK		 2049 eliminate the copy.
2050
2051 We cannot do this if the destination of the second assignment is
2052 a register that we have already assumed is zero-extended. Similarly
2053 for a SUBREG of such a register. */
230d793d
RS		 2054
2055 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2056 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2060 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2061 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2062 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2063 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2064 INSN_CUID (i2))
2065 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
f0343c74
RK		 2067 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2068 (GET_CODE (temp) == REG
2069 && reg_nonzero_bits[REGNO (temp)] != 0
2070 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2072 && (reg_nonzero_bits[REGNO (temp)]
2073 != GET_MODE_MASK (word_mode))))
2074 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2075 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2076 (GET_CODE (temp) == REG
2077 && reg_nonzero_bits[REGNO (temp)] != 0
2078 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2080 && (reg_nonzero_bits[REGNO (temp)]
2081 != GET_MODE_MASK (word_mode)))))
230d793d
RS		 2082 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2083 SET_SRC (XVECEXP (newpat, 0, 1)))
2084 && ! find_reg_note (i3, REG_UNUSED,
2085 SET_DEST (XVECEXP (newpat, 0, 0))))
2086 {
472fbdd1
RK		 2087 rtx ni2dest;
2088
230d793d 2089 newi2pat = XVECEXP (newpat, 0, 0);
472fbdd1 2090 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
230d793d
RS		 2091 newpat = XVECEXP (newpat, 0, 1);
2092 SUBST (SET_SRC (newpat),
472fbdd1 2093 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
8e2f6e35 2094 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2095
230d793d 2096 if (i2_code_number >= 0)
8e2f6e35 2097 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
5089e22e
RS		 2098
2099 if (insn_code_number >= 0)
2100 {
2101 rtx insn;
2102 rtx link;
2103
2104 /* If we will be able to accept this, we have made a change to the
2105 destination of I3. This can invalidate a LOG_LINKS pointing
2106 to I3. No other part of combine.c makes such a transformation.
2107
2108 The new I3 will have a destination that was previously the
2109 destination of I1 or I2 and which was used in i2 or I3. Call
2110 distribute_links to make a LOG_LINK from the next use of
2111 that destination. */
2112
2113 PATTERN (i3) = newpat;
38a448ca 2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
5089e22e
RS		 2115
2116 /* I3 now uses what used to be its destination and which is
2117 now I2's destination. That means we need a LOG_LINK from
2118 I3 to I2. But we used to have one, so we still will.
2119
2120 However, some later insn might be using I2's dest and have
2121 a LOG_LINK pointing at I3. We must remove this link.
2122 The simplest way to remove the link is to point it at I1,
2123 which we know will be a NOTE. */
2124
2125 for (insn = NEXT_INSN (i3);
0d4d42c3
RK		 2126 insn && (this_basic_block == n_basic_blocks - 1
2127 || insn != basic_block_head[this_basic_block + 1]);
5089e22e
RS		 2128 insn = NEXT_INSN (insn))
2129 {
2130 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
472fbdd1 2131 && reg_referenced_p (ni2dest, PATTERN (insn)))
5089e22e
RS		 2132 {
2133 for (link = LOG_LINKS (insn); link;
2134 link = XEXP (link, 1))
2135 if (XEXP (link, 0) == i3)
2136 XEXP (link, 0) = i1;
2137
2138 break;
2139 }
2140 }
2141 }
230d793d
RS		 2142 }
2143
2144 /* Similarly, check for a case where we have a PARALLEL of two independent
2145 SETs but we started with three insns. In this case, we can do the sets
2146 as two separate insns. This case occurs when some SET allows two
2147 other insns to combine, but the destination of that SET is still live. */
2148
2149 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2150 && GET_CODE (newpat) == PARALLEL
2151 && XVECLEN (newpat, 0) == 2
2152 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2153 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2154 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2155 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2156 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2158 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2159 INSN_CUID (i2))
2160 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2161 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2162 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2163 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2164 XVECEXP (newpat, 0, 0))
2165 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2166 XVECEXP (newpat, 0, 1)))
2167 {
e9a25f70
JL		 2168 /* Normally, it doesn't matter which of the two is done first,
2169 but it does if one references cc0. In that case, it has to
2170 be first. */
2171#ifdef HAVE_cc0
2172 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2173 {
2174 newi2pat = XVECEXP (newpat, 0, 0);
2175 newpat = XVECEXP (newpat, 0, 1);
2176 }
2177 else
2178#endif
2179 {
2180 newi2pat = XVECEXP (newpat, 0, 1);
2181 newpat = XVECEXP (newpat, 0, 0);
2182 }
230d793d 2183
8e2f6e35 2184 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
a29ca9db 2185
230d793d 2186 if (i2_code_number >= 0)
8e2f6e35 2187 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
230d793d
RS		 2188 }
2189
2190 /* If it still isn't recognized, fail and change things back the way they
2191 were. */
2192 if ((insn_code_number < 0
2193 /* Is the result a reasonable ASM_OPERANDS? */
2194 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2195 {
2196 undo_all ();
2197 return 0;
2198 }
2199
2200 /* If we had to change another insn, make sure it is valid also. */
2201 if (undobuf.other_insn)
2202 {
230d793d
RS		 2203 rtx other_pat = PATTERN (undobuf.other_insn);
2204 rtx new_other_notes;
2205 rtx note, next;
2206
6e25d159
RK		 2207 CLEAR_HARD_REG_SET (newpat_used_regs);
2208
8e2f6e35
BS		 2209 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2210 &new_other_notes);
230d793d
RS		 2211
2212 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2213 {
2214 undo_all ();
2215 return 0;
2216 }
2217
2218 PATTERN (undobuf.other_insn) = other_pat;
2219
2220 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2221 are still valid. Then add any non-duplicate notes added by
2222 recog_for_combine. */
2223 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2224 {
2225 next = XEXP (note, 1);
2226
2227 if (REG_NOTE_KIND (note) == REG_UNUSED
2228 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1a26b032
RK		 2229 {
2230 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2231 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
1a26b032
RK		 2232
2233 remove_note (undobuf.other_insn, note);
2234 }
230d793d
RS		 2235 }
2236
1a26b032
RK		 2237 for (note = new_other_notes; note; note = XEXP (note, 1))
2238 if (GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 2239 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 2240
230d793d 2241 distribute_notes (new_other_notes, undobuf.other_insn,
5f4f0e22 2242 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
230d793d
RS		 2243 }
2244
2245 /* We now know that we can do this combination. Merge the insns and
2246 update the status of registers and LOG_LINKS. */
2247
2248 {
2249 rtx i3notes, i2notes, i1notes = 0;
2250 rtx i3links, i2links, i1links = 0;
2251 rtx midnotes = 0;
230d793d 2252 register int regno;
ff3467a9
JW		 2253 /* Compute which registers we expect to eliminate. newi2pat may be setting
2254 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2255 same as i3dest, in which case newi2pat may be setting i1dest. */
2256 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2257 || i2dest_in_i2src || i2dest_in_i1src
230d793d 2258 ? 0 : i2dest);
ff3467a9
JW		 2259 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2260 || (newi2pat && reg_set_p (i1dest, newi2pat))
2261 ? 0 : i1dest);
230d793d
RS		 2262
2263 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2264 clear them. */
2265 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2266 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2267 if (i1)
2268 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2269
2270 /* Ensure that we do not have something that should not be shared but
2271 occurs multiple times in the new insns. Check this by first
5089e22e 2272 resetting all the `used' flags and then copying anything is shared. */
230d793d
RS		 2273
2274 reset_used_flags (i3notes);
2275 reset_used_flags (i2notes);
2276 reset_used_flags (i1notes);
2277 reset_used_flags (newpat);
2278 reset_used_flags (newi2pat);
2279 if (undobuf.other_insn)
2280 reset_used_flags (PATTERN (undobuf.other_insn));
2281
2282 i3notes = copy_rtx_if_shared (i3notes);
2283 i2notes = copy_rtx_if_shared (i2notes);
2284 i1notes = copy_rtx_if_shared (i1notes);
2285 newpat = copy_rtx_if_shared (newpat);
2286 newi2pat = copy_rtx_if_shared (newi2pat);
2287 if (undobuf.other_insn)
2288 reset_used_flags (PATTERN (undobuf.other_insn));
2289
2290 INSN_CODE (i3) = insn_code_number;
2291 PATTERN (i3) = newpat;
2292 if (undobuf.other_insn)
2293 INSN_CODE (undobuf.other_insn) = other_code_number;
2294
2295 /* We had one special case above where I2 had more than one set and
2296 we replaced a destination of one of those sets with the destination
2297 of I3. In that case, we have to update LOG_LINKS of insns later
176c9e6b
JW		 2298 in this basic block. Note that this (expensive) case is rare.
2299
2300 Also, in this case, we must pretend that all REG_NOTEs for I2
2301 actually came from I3, so that REG_UNUSED notes from I2 will be
2302 properly handled. */
2303
2304 if (i3_subst_into_i2)
2305 {
2306 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2307 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2308 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2309 && ! find_reg_note (i2, REG_UNUSED,
2310 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2311 for (temp = NEXT_INSN (i2);
2312 temp && (this_basic_block == n_basic_blocks - 1
2313 || basic_block_head[this_basic_block] != temp);
2314 temp = NEXT_INSN (temp))
2315 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2316 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2317 if (XEXP (link, 0) == i2)
2318 XEXP (link, 0) = i3;
2319
2320 if (i3notes)
2321 {
2322 rtx link = i3notes;
2323 while (XEXP (link, 1))
2324 link = XEXP (link, 1);
2325 XEXP (link, 1) = i2notes;
2326 }
2327 else
2328 i3notes = i2notes;
2329 i2notes = 0;
2330 }
230d793d
RS		 2331
2332 LOG_LINKS (i3) = 0;
2333 REG_NOTES (i3) = 0;
2334 LOG_LINKS (i2) = 0;
2335 REG_NOTES (i2) = 0;
2336
2337 if (newi2pat)
2338 {
2339 INSN_CODE (i2) = i2_code_number;
2340 PATTERN (i2) = newi2pat;
2341 }
2342 else
2343 {
2344 PUT_CODE (i2, NOTE);
2345 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2346 NOTE_SOURCE_FILE (i2) = 0;
2347 }
2348
2349 if (i1)
2350 {
2351 LOG_LINKS (i1) = 0;
2352 REG_NOTES (i1) = 0;
2353 PUT_CODE (i1, NOTE);
2354 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2355 NOTE_SOURCE_FILE (i1) = 0;
2356 }
2357
2358 /* Get death notes for everything that is now used in either I3 or
6eb12cef
RK		 2359 I2 and used to die in a previous insn. If we built two new
2360 patterns, move from I1 to I2 then I2 to I3 so that we get the
2361 proper movement on registers that I2 modifies. */
230d793d 2362
230d793d 2363 if (newi2pat)
6eb12cef
RK		 2364 {
2365 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2366 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2367 }
2368 else
2369 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2370 i3, &midnotes);
230d793d
RS		 2371
2372 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2373 if (i3notes)
5f4f0e22
CH		 2374 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2375 elim_i2, elim_i1);
230d793d 2376 if (i2notes)
5f4f0e22
CH		 2377 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2378 elim_i2, elim_i1);
230d793d 2379 if (i1notes)
5f4f0e22
CH		 2380 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2381 elim_i2, elim_i1);
230d793d 2382 if (midnotes)
5f4f0e22
CH		 2383 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2384 elim_i2, elim_i1);
230d793d
RS		 2385
2386 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2387 know these are REG_UNUSED and want them to go to the desired insn,
1a26b032
RK		 2388 so we always pass it as i3. We have not counted the notes in
2389 reg_n_deaths yet, so we need to do so now. */
2390
230d793d 2391 if (newi2pat && new_i2_notes)
1a26b032
RK		 2392 {
2393 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2394 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2395 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2396
2397 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2398 }
2399
230d793d 2400 if (new_i3_notes)
1a26b032
RK		 2401 {
2402 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2403 if (GET_CODE (XEXP (temp, 0)) == REG)
b1f21e0a 2404 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
1a26b032
RK		 2405
2406 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2407 }
230d793d
RS		 2408
2409 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
e9a25f70
JL		 2410 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2411 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2412 in that case, it might delete I2. Similarly for I2 and I1.
1a26b032
RK		 2413 Show an additional death due to the REG_DEAD note we make here. If
2414 we discard it in distribute_notes, we will decrement it again. */
d0ab8cd3 2415
230d793d 2416 if (i3dest_killed)
1a26b032
RK		 2417 {
2418 if (GET_CODE (i3dest_killed) == REG)
b1f21e0a 2419 REG_N_DEATHS (REGNO (i3dest_killed))++;
1a26b032 2420
e9a25f70 2421 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
38a448ca
RH		 2422 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2423 NULL_RTX),
ff3467a9 2424 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
e9a25f70 2425 else
38a448ca
RH		 2426 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2427 NULL_RTX),
e9a25f70 2428 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
ff3467a9 2429 elim_i2, elim_i1);
1a26b032 2430 }
58c8c593 2431
230d793d 2432 if (i2dest_in_i2src)
58c8c593 2433 {
1a26b032 2434 if (GET_CODE (i2dest) == REG)
b1f21e0a 2435 REG_N_DEATHS (REGNO (i2dest))++;
1a26b032 2436
58c8c593 2437 if (newi2pat && reg_set_p (i2dest, newi2pat))
38a448ca 2438 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2439 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2440 else
38a448ca 2441 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
58c8c593
RK		 2442 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2443 NULL_RTX, NULL_RTX);
2444 }
2445
230d793d 2446 if (i1dest_in_i1src)
58c8c593 2447 {
1a26b032 2448 if (GET_CODE (i1dest) == REG)
b1f21e0a 2449 REG_N_DEATHS (REGNO (i1dest))++;
1a26b032 2450
58c8c593 2451 if (newi2pat && reg_set_p (i1dest, newi2pat))
38a448ca 2452 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2453 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2454 else
38a448ca 2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
58c8c593
RK		 2456 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2457 NULL_RTX, NULL_RTX);
2458 }
230d793d
RS		 2459
2460 distribute_links (i3links);
2461 distribute_links (i2links);
2462 distribute_links (i1links);
2463
2464 if (GET_CODE (i2dest) == REG)
2465 {
d0ab8cd3
RK		 2466 rtx link;
2467 rtx i2_insn = 0, i2_val = 0, set;
2468
2469 /* The insn that used to set this register doesn't exist, and
2470 this life of the register may not exist either. See if one of
2471 I3's links points to an insn that sets I2DEST. If it does,
2472 that is now the last known value for I2DEST. If we don't update
2473 this and I2 set the register to a value that depended on its old
230d793d
RS		 2474 contents, we will get confused. If this insn is used, thing
2475 will be set correctly in combine_instructions. */
d0ab8cd3
RK		 2476
2477 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2478 if ((set = single_set (XEXP (link, 0))) != 0
2479 && rtx_equal_p (i2dest, SET_DEST (set)))
2480 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2481
2482 record_value_for_reg (i2dest, i2_insn, i2_val);
230d793d
RS		 2483
2484 /* If the reg formerly set in I2 died only once and that was in I3,
2485 zero its use count so it won't make `reload' do any work. */
538fe8cd
ILT		 2486 if (! added_sets_2
2487 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2488 && ! i2dest_in_i2src)
230d793d
RS		 2489 {
2490 regno = REGNO (i2dest);
b1f21e0a
MM		 2491 REG_N_SETS (regno)--;
2492 if (REG_N_SETS (regno) == 0
8e08106d 2493 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2494 REG_N_REFS (regno) = 0;
230d793d
RS		 2495 }
2496 }
2497
2498 if (i1 && GET_CODE (i1dest) == REG)
2499 {
d0ab8cd3
RK		 2500 rtx link;
2501 rtx i1_insn = 0, i1_val = 0, set;
2502
2503 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2504 if ((set = single_set (XEXP (link, 0))) != 0
2505 && rtx_equal_p (i1dest, SET_DEST (set)))
2506 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2507
2508 record_value_for_reg (i1dest, i1_insn, i1_val);
2509
230d793d 2510 regno = REGNO (i1dest);
5af91171 2511 if (! added_sets_1 && ! i1dest_in_i1src)
230d793d 2512 {
b1f21e0a
MM		 2513 REG_N_SETS (regno)--;
2514 if (REG_N_SETS (regno) == 0
8e08106d 2515 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
b1f21e0a 2516 REG_N_REFS (regno) = 0;
230d793d
RS		 2517 }
2518 }
2519
951553af 2520 /* Update reg_nonzero_bits et al for any changes that may have been made
22609cbf
RK		 2521 to this insn. */
2522
951553af 2523 note_stores (newpat, set_nonzero_bits_and_sign_copies);
22609cbf 2524 if (newi2pat)
951553af 2525 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
22609cbf 2526
230d793d
RS		 2527 /* If I3 is now an unconditional jump, ensure that it has a
2528 BARRIER following it since it may have initially been a
381ee8af 2529 conditional jump. It may also be the last nonnote insn. */
230d793d
RS		 2530
2531 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
381ee8af
TW		 2532 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2533 || GET_CODE (temp) != BARRIER))
230d793d
RS		 2534 emit_barrier_after (i3);
2535 }
2536
2537 combine_successes++;
2538
bcd49eb7
JW		 2539 /* Clear this here, so that subsequent get_last_value calls are not
2540 affected. */
2541 subst_prev_insn = NULL_RTX;
2542
abe6e52f
RK		 2543 if (added_links_insn
2544 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2545 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2546 return added_links_insn;
2547 else
2548 return newi2pat ? i2 : i3;
230d793d
RS		 2549}
2550\f
2551/* Undo all the modifications recorded in undobuf. */
2552
2553static void
2554undo_all ()
2555{
241cea85
RK		 2556 struct undo *undo, *next;
2557
2558 for (undo = undobuf.undos; undo; undo = next)
7c046e4e 2559 {
241cea85
RK		 2560 next = undo->next;
2561 if (undo->is_int)
2562 *undo->where.i = undo->old_contents.i;
7c046e4e 2563 else
241cea85
RK		 2564 *undo->where.r = undo->old_contents.r;
2565
2566 undo->next = undobuf.frees;
2567 undobuf.frees = undo;
7c046e4e 2568 }
230d793d
RS		 2569
2570 obfree (undobuf.storage);
845fc875 2571 undobuf.undos = undobuf.previous_undos = 0;
bcd49eb7
JW		 2572
2573 /* Clear this here, so that subsequent get_last_value calls are not
2574 affected. */
2575 subst_prev_insn = NULL_RTX;
230d793d
RS		 2576}
2577\f
2578/* Find the innermost point within the rtx at LOC, possibly LOC itself,
d0ab8cd3
RK		 2579 where we have an arithmetic expression and return that point. LOC will
2580 be inside INSN.
230d793d
RS		 2581
2582 try_combine will call this function to see if an insn can be split into
2583 two insns. */
2584
2585static rtx *
d0ab8cd3 2586find_split_point (loc, insn)
230d793d 2587 rtx *loc;
d0ab8cd3 2588 rtx insn;
230d793d
RS		 2589{
2590 rtx x = *loc;
2591 enum rtx_code code = GET_CODE (x);
2592 rtx *split;
2593 int len = 0, pos, unsignedp;
2594 rtx inner;
2595
2596 /* First special-case some codes. */
2597 switch (code)
2598 {
2599 case SUBREG:
2600#ifdef INSN_SCHEDULING
2601 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2602 point. */
2603 if (GET_CODE (SUBREG_REG (x)) == MEM)
2604 return loc;
2605#endif
d0ab8cd3 2606 return find_split_point (&SUBREG_REG (x), insn);
230d793d 2607
230d793d 2608 case MEM:
916f14f1 2609#ifdef HAVE_lo_sum
230d793d
RS		 2610 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2611 using LO_SUM and HIGH. */
2612 if (GET_CODE (XEXP (x, 0)) == CONST
2613 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2614 {
2615 SUBST (XEXP (x, 0),
2616 gen_rtx_combine (LO_SUM, Pmode,
2617 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2618 XEXP (x, 0)));
2619 return &XEXP (XEXP (x, 0), 0);
2620 }
230d793d
RS		 2621#endif
2622
916f14f1
RK		 2623 /* If we have a PLUS whose second operand is a constant and the
2624 address is not valid, perhaps will can split it up using
2625 the machine-specific way to split large constants. We use
ddd5a7c1 2626 the first pseudo-reg (one of the virtual regs) as a placeholder;
916f14f1
RK		 2627 it will not remain in the result. */
2628 if (GET_CODE (XEXP (x, 0)) == PLUS
2629 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2630 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2631 {
2632 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
38a448ca 2633 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
916f14f1
RK		 2634 subst_insn);
2635
2636 /* This should have produced two insns, each of which sets our
2637 placeholder. If the source of the second is a valid address,
2638 we can make put both sources together and make a split point
2639 in the middle. */
2640
2641 if (seq && XVECLEN (seq, 0) == 2
2642 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2643 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2644 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2645 && ! reg_mentioned_p (reg,
2646 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2647 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2648 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2649 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2650 && memory_address_p (GET_MODE (x),
2651 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2652 {
2653 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2654 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2655
2656 /* Replace the placeholder in SRC2 with SRC1. If we can
2657 find where in SRC2 it was placed, that can become our
2658 split point and we can replace this address with SRC2.
2659 Just try two obvious places. */
2660
2661 src2 = replace_rtx (src2, reg, src1);
2662 split = 0;
2663 if (XEXP (src2, 0) == src1)
2664 split = &XEXP (src2, 0);
2665 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2666 && XEXP (XEXP (src2, 0), 0) == src1)
2667 split = &XEXP (XEXP (src2, 0), 0);
2668
2669 if (split)
2670 {
2671 SUBST (XEXP (x, 0), src2);
2672 return split;
2673 }
2674 }
1a26b032
RK		 2675
2676 /* If that didn't work, perhaps the first operand is complex and
2677 needs to be computed separately, so make a split point there.
2678 This will occur on machines that just support REG + CONST
2679 and have a constant moved through some previous computation. */
2680
2681 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2682 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2683 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2684 == 'o')))
2685 return &XEXP (XEXP (x, 0), 0);
916f14f1
RK		 2686 }
2687 break;
2688
230d793d
RS		 2689 case SET:
2690#ifdef HAVE_cc0
2691 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2692 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2693 we need to put the operand into a register. So split at that
2694 point. */
2695
2696 if (SET_DEST (x) == cc0_rtx
2697 && GET_CODE (SET_SRC (x)) != COMPARE
2698 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2699 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2700 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2701 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2702 return &SET_SRC (x);
2703#endif
2704
2705 /* See if we can split SET_SRC as it stands. */
d0ab8cd3 2706 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2707 if (split && split != &SET_SRC (x))
2708 return split;
2709
041d7180
JL		 2710 /* See if we can split SET_DEST as it stands. */
2711 split = find_split_point (&SET_DEST (x), insn);
2712 if (split && split != &SET_DEST (x))
2713 return split;
2714
230d793d
RS		 2715 /* See if this is a bitfield assignment with everything constant. If
2716 so, this is an IOR of an AND, so split it into that. */
2717 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2718 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
5f4f0e22 2719 <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 2720 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2721 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2722 && GET_CODE (SET_SRC (x)) == CONST_INT
2723 && ((INTVAL (XEXP (SET_DEST (x), 1))
2724 + INTVAL (XEXP (SET_DEST (x), 2)))
2725 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2726 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2727 {
2728 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2729 int len = INTVAL (XEXP (SET_DEST (x), 1));
2730 int src = INTVAL (SET_SRC (x));
2731 rtx dest = XEXP (SET_DEST (x), 0);
2732 enum machine_mode mode = GET_MODE (dest);
5f4f0e22 2733 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
230d793d 2734
f76b9db2
ILT		 2735 if (BITS_BIG_ENDIAN)
2736 pos = GET_MODE_BITSIZE (mode) - len - pos;
230d793d 2737
e51712db 2738 if ((unsigned HOST_WIDE_INT) src == mask)
230d793d 2739 SUBST (SET_SRC (x),
5f4f0e22 2740 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
230d793d
RS		 2741 else
2742 SUBST (SET_SRC (x),
2743 gen_binary (IOR, mode,
2744 gen_binary (AND, mode, dest,
5f4f0e22
CH		 2745 GEN_INT (~ (mask << pos)
2746 & GET_MODE_MASK (mode))),
2747 GEN_INT (src << pos)));
230d793d
RS		 2748
2749 SUBST (SET_DEST (x), dest);
2750
d0ab8cd3 2751 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2752 if (split && split != &SET_SRC (x))
2753 return split;
2754 }
2755
2756 /* Otherwise, see if this is an operation that we can split into two.
2757 If so, try to split that. */
2758 code = GET_CODE (SET_SRC (x));
2759
2760 switch (code)
2761 {
d0ab8cd3
RK		 2762 case AND:
2763 /* If we are AND'ing with a large constant that is only a single
2764 bit and the result is only being used in a context where we
2765 need to know if it is zero or non-zero, replace it with a bit
2766 extraction. This will avoid the large constant, which might
2767 have taken more than one insn to make. If the constant were
2768 not a valid argument to the AND but took only one insn to make,
2769 this is no worse, but if it took more than one insn, it will
2770 be better. */
2771
2772 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2773 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2774 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2775 && GET_CODE (SET_DEST (x)) == REG
2776 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2777 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2778 && XEXP (*split, 0) == SET_DEST (x)
2779 && XEXP (*split, 1) == const0_rtx)
2780 {
76184def
DE		 2781 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2782 XEXP (SET_SRC (x), 0),
2783 pos, NULL_RTX, 1, 1, 0, 0);
2784 if (extraction != 0)
2785 {
2786 SUBST (SET_SRC (x), extraction);
2787 return find_split_point (loc, insn);
2788 }
d0ab8cd3
RK		 2789 }
2790 break;
2791
1a6ec070
RK		 2792 case NE:
2793 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2794 is known to be on, this can be converted into a NEG of a shift. */
2795 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2796 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4eb2cb10 2797 && 1 <= (pos = exact_log2
1a6ec070
RK		 2798 (nonzero_bits (XEXP (SET_SRC (x), 0),
2799 GET_MODE (XEXP (SET_SRC (x), 0))))))
2800 {
2801 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2802
2803 SUBST (SET_SRC (x),
2804 gen_rtx_combine (NEG, mode,
2805 gen_rtx_combine (LSHIFTRT, mode,
2806 XEXP (SET_SRC (x), 0),
4eb2cb10 2807 GEN_INT (pos))));
1a6ec070
RK		 2808
2809 split = find_split_point (&SET_SRC (x), insn);
2810 if (split && split != &SET_SRC (x))
2811 return split;
2812 }
2813 break;
2814
230d793d
RS		 2815 case SIGN_EXTEND:
2816 inner = XEXP (SET_SRC (x), 0);
101c1a3d
JL		 2817
2818 /* We can't optimize if either mode is a partial integer
2819 mode as we don't know how many bits are significant
2820 in those modes. */
2821 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2822 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2823 break;
2824
230d793d
RS		 2825 pos = 0;
2826 len = GET_MODE_BITSIZE (GET_MODE (inner));
2827 unsignedp = 0;
2828 break;
2829
2830 case SIGN_EXTRACT:
2831 case ZERO_EXTRACT:
2832 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2833 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2834 {
2835 inner = XEXP (SET_SRC (x), 0);
2836 len = INTVAL (XEXP (SET_SRC (x), 1));
2837 pos = INTVAL (XEXP (SET_SRC (x), 2));
2838
f76b9db2
ILT		 2839 if (BITS_BIG_ENDIAN)
2840 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
230d793d
RS		 2841 unsignedp = (code == ZERO_EXTRACT);
2842 }
2843 break;
e9a25f70
JL		 2844
2845 default:
2846 break;
230d793d
RS		 2847 }
2848
2849 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2850 {
2851 enum machine_mode mode = GET_MODE (SET_SRC (x));
2852
d0ab8cd3
RK		 2853 /* For unsigned, we have a choice of a shift followed by an
2854 AND or two shifts. Use two shifts for field sizes where the
2855 constant might be too large. We assume here that we can
2856 always at least get 8-bit constants in an AND insn, which is
2857 true for every current RISC. */
2858
2859 if (unsignedp && len <= 8)
230d793d
RS		 2860 {
2861 SUBST (SET_SRC (x),
2862 gen_rtx_combine
2863 (AND, mode,
2864 gen_rtx_combine (LSHIFTRT, mode,
2865 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2866 GEN_INT (pos)),
2867 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
230d793d 2868
d0ab8cd3 2869 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2870 if (split && split != &SET_SRC (x))
2871 return split;
2872 }
2873 else
2874 {
2875 SUBST (SET_SRC (x),
2876 gen_rtx_combine
d0ab8cd3 2877 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
230d793d
RS		 2878 gen_rtx_combine (ASHIFT, mode,
2879 gen_lowpart_for_combine (mode, inner),
5f4f0e22
CH		 2880 GEN_INT (GET_MODE_BITSIZE (mode)
2881 - len - pos)),
2882 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
230d793d 2883
d0ab8cd3 2884 split = find_split_point (&SET_SRC (x), insn);
230d793d
RS		 2885 if (split && split != &SET_SRC (x))
2886 return split;
2887 }
2888 }
2889
2890 /* See if this is a simple operation with a constant as the second
2891 operand. It might be that this constant is out of range and hence
2892 could be used as a split point. */
2893 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2894 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2895 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2896 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2897 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2898 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2899 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2900 == 'o'))))
2901 return &XEXP (SET_SRC (x), 1);
2902
2903 /* Finally, see if this is a simple operation with its first operand
2904 not in a register. The operation might require this operand in a
2905 register, so return it as a split point. We can always do this
2906 because if the first operand were another operation, we would have
2907 already found it as a split point. */
2908 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2909 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2910 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2911 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2912 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2913 return &XEXP (SET_SRC (x), 0);
2914
2915 return 0;
2916
2917 case AND:
2918 case IOR:
2919 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2920 it is better to write this as (not (ior A B)) so we can split it.
2921 Similarly for IOR. */
2922 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2923 {
2924 SUBST (*loc,
2925 gen_rtx_combine (NOT, GET_MODE (x),
2926 gen_rtx_combine (code == IOR ? AND : IOR,
2927 GET_MODE (x),
2928 XEXP (XEXP (x, 0), 0),
2929 XEXP (XEXP (x, 1), 0))));
d0ab8cd3 2930 return find_split_point (loc, insn);
230d793d
RS		 2931 }
2932
2933 /* Many RISC machines have a large set of logical insns. If the
2934 second operand is a NOT, put it first so we will try to split the
2935 other operand first. */
2936 if (GET_CODE (XEXP (x, 1)) == NOT)
2937 {
2938 rtx tem = XEXP (x, 0);
2939 SUBST (XEXP (x, 0), XEXP (x, 1));
2940 SUBST (XEXP (x, 1), tem);
2941 }
2942 break;
e9a25f70
JL		 2943
2944 default:
2945 break;
230d793d
RS		 2946 }
2947
2948 /* Otherwise, select our actions depending on our rtx class. */
2949 switch (GET_RTX_CLASS (code))
2950 {
2951 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2952 case '3':
d0ab8cd3 2953 split = find_split_point (&XEXP (x, 2), insn);
230d793d
RS		 2954 if (split)
2955 return split;
0f41302f 2956 /* ... fall through ... */
230d793d
RS		 2957 case '2':
2958 case 'c':
2959 case '<':
d0ab8cd3 2960 split = find_split_point (&XEXP (x, 1), insn);
230d793d
RS		 2961 if (split)
2962 return split;
0f41302f 2963 /* ... fall through ... */
230d793d
RS		 2964 case '1':
2965 /* Some machines have (and (shift ...) ...) insns. If X is not
2966 an AND, but XEXP (X, 0) is, use it as our split point. */
2967 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2968 return &XEXP (x, 0);
2969
d0ab8cd3 2970 split = find_split_point (&XEXP (x, 0), insn);
230d793d
RS		 2971 if (split)
2972 return split;
2973 return loc;
2974 }
2975
2976 /* Otherwise, we don't have a split point. */
2977 return 0;
2978}
2979\f
2980/* Throughout X, replace FROM with TO, and return the result.
2981 The result is TO if X is FROM;
2982 otherwise the result is X, but its contents may have been modified.
2983 If they were modified, a record was made in undobuf so that
2984 undo_all will (among other things) return X to its original state.
2985
2986 If the number of changes necessary is too much to record to undo,
2987 the excess changes are not made, so the result is invalid.
2988 The changes already made can still be undone.
2989 undobuf.num_undo is incremented for such changes, so by testing that
2990 the caller can tell whether the result is valid.
2991
2992 `n_occurrences' is incremented each time FROM is replaced.
2993
2994 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2995
5089e22e 2996 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
230d793d
RS		 2997 by copying if `n_occurrences' is non-zero. */
2998
2999static rtx
3000subst (x, from, to, in_dest, unique_copy)
3001 register rtx x, from, to;
3002 int in_dest;
3003 int unique_copy;
3004{
f24ad0e4 3005 register enum rtx_code code = GET_CODE (x);
230d793d 3006 enum machine_mode op0_mode = VOIDmode;
8079805d
RK		 3007 register char *fmt;
3008 register int len, i;
3009 rtx new;
230d793d
RS		 3010
3011/* Two expressions are equal if they are identical copies of a shared
3012 RTX or if they are both registers with the same register number
3013 and mode. */
3014
3015#define COMBINE_RTX_EQUAL_P(X,Y) \
3016 ((X) == (Y) \
3017 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3018 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3019
3020 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3021 {
3022 n_occurrences++;
3023 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3024 }
3025
3026 /* If X and FROM are the same register but different modes, they will
3027 not have been seen as equal above. However, flow.c will make a
3028 LOG_LINKS entry for that case. If we do nothing, we will try to
3029 rerecognize our original insn and, when it succeeds, we will
3030 delete the feeding insn, which is incorrect.
3031
3032 So force this insn not to match in this (rare) case. */
3033 if (! in_dest && code == REG && GET_CODE (from) == REG
3034 && REGNO (x) == REGNO (from))
38a448ca 3035 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 3036
3037 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3038 of which may contain things that can be combined. */
3039 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3040 return x;
3041
3042 /* It is possible to have a subexpression appear twice in the insn.
3043 Suppose that FROM is a register that appears within TO.
3044 Then, after that subexpression has been scanned once by `subst',
3045 the second time it is scanned, TO may be found. If we were
3046 to scan TO here, we would find FROM within it and create a
3047 self-referent rtl structure which is completely wrong. */
3048 if (COMBINE_RTX_EQUAL_P (x, to))
3049 return to;
3050
4f4b3679
RH		 3051 /* Parallel asm_operands need special attention because all of the
3052 inputs are shared across the arms. Furthermore, unsharing the
3053 rtl results in recognition failures. Failure to handle this case
3054 specially can result in circular rtl.
3055
3056 Solve this by doing a normal pass across the first entry of the
3057 parallel, and only processing the SET_DESTs of the subsequent
3058 entries. Ug. */
3059
3060 if (code == PARALLEL
3061 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3062 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
230d793d 3063 {
4f4b3679
RH		 3064 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3065
3066 /* If this substitution failed, this whole thing fails. */
3067 if (GET_CODE (new) == CLOBBER
3068 && XEXP (new, 0) == const0_rtx)
3069 return new;
3070
3071 SUBST (XVECEXP (x, 0, 0), new);
3072
3073 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
230d793d 3074 {
4f4b3679
RH		 3075 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3076
3077 if (GET_CODE (dest) != REG
3078 && GET_CODE (dest) != CC0
3079 && GET_CODE (dest) != PC)
230d793d 3080 {
4f4b3679 3081 new = subst (dest, from, to, 0, unique_copy);
230d793d 3082
4f4b3679
RH		 3083 /* If this substitution failed, this whole thing fails. */
3084 if (GET_CODE (new) == CLOBBER
3085 && XEXP (new, 0) == const0_rtx)
3086 return new;
230d793d 3087
4f4b3679 3088 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
230d793d
RS		 3089 }
3090 }
4f4b3679
RH		 3091 }
3092 else
3093 {
3094 len = GET_RTX_LENGTH (code);
3095 fmt = GET_RTX_FORMAT (code);
3096
3097 /* We don't need to process a SET_DEST that is a register, CC0,
3098 or PC, so set up to skip this common case. All other cases
3099 where we want to suppress replacing something inside a
3100 SET_SRC are handled via the IN_DEST operand. */
3101 if (code == SET
3102 && (GET_CODE (SET_DEST (x)) == REG
3103 || GET_CODE (SET_DEST (x)) == CC0
3104 || GET_CODE (SET_DEST (x)) == PC))
3105 fmt = "ie";
3106
3107 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3108 constant. */
3109 if (fmt[0] == 'e')
3110 op0_mode = GET_MODE (XEXP (x, 0));
3111
3112 for (i = 0; i < len; i++)
230d793d 3113 {
4f4b3679 3114 if (fmt[i] == 'E')
230d793d 3115 {
4f4b3679
RH		 3116 register int j;
3117 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3118 {
3119 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3120 {
3121 new = (unique_copy && n_occurrences
3122 ? copy_rtx (to) : to);
3123 n_occurrences++;
3124 }
3125 else
3126 {
3127 new = subst (XVECEXP (x, i, j), from, to, 0,
3128 unique_copy);
3129
3130 /* If this substitution failed, this whole thing
3131 fails. */
3132 if (GET_CODE (new) == CLOBBER
3133 && XEXP (new, 0) == const0_rtx)
3134 return new;
3135 }
3136
3137 SUBST (XVECEXP (x, i, j), new);
3138 }
3139 }
3140 else if (fmt[i] == 'e')
3141 {
3142 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3143 {
3144 /* In general, don't install a subreg involving two
3145 modes not tieable. It can worsen register
3146 allocation, and can even make invalid reload
3147 insns, since the reg inside may need to be copied
3148 from in the outside mode, and that may be invalid
3149 if it is an fp reg copied in integer mode.
3150
3151 We allow two exceptions to this: It is valid if
3152 it is inside another SUBREG and the mode of that
3153 SUBREG and the mode of the inside of TO is
3154 tieable and it is valid if X is a SET that copies
3155 FROM to CC0. */
3156
3157 if (GET_CODE (to) == SUBREG
3158 && ! MODES_TIEABLE_P (GET_MODE (to),
3159 GET_MODE (SUBREG_REG (to)))
3160 && ! (code == SUBREG
3161 && MODES_TIEABLE_P (GET_MODE (x),
3162 GET_MODE (SUBREG_REG (to))))
42301240 3163#ifdef HAVE_cc0
4f4b3679 3164 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
42301240 3165#endif
4f4b3679
RH		 3166 )
3167 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
42301240 3168
4f4b3679
RH		 3169 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3170 n_occurrences++;
3171 }
3172 else
3173 /* If we are in a SET_DEST, suppress most cases unless we
3174 have gone inside a MEM, in which case we want to
3175 simplify the address. We assume here that things that
3176 are actually part of the destination have their inner
3177 parts in the first expression. This is true for SUBREG,
3178 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3179 things aside from REG and MEM that should appear in a
3180 SET_DEST. */
3181 new = subst (XEXP (x, i), from, to,
3182 (((in_dest
3183 && (code == SUBREG || code == STRICT_LOW_PART
3184 || code == ZERO_EXTRACT))
3185 || code == SET)
3186 && i == 0), unique_copy);
3187
3188 /* If we found that we will have to reject this combination,
3189 indicate that by returning the CLOBBER ourselves, rather than
3190 an expression containing it. This will speed things up as
3191 well as prevent accidents where two CLOBBERs are considered
3192 to be equal, thus producing an incorrect simplification. */
3193
3194 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3195 return new;
3196
3197 SUBST (XEXP (x, i), new);
230d793d 3198 }
230d793d
RS		 3199 }
3200 }
3201
8079805d
RK		 3202 /* Try to simplify X. If the simplification changed the code, it is likely
3203 that further simplification will help, so loop, but limit the number
3204 of repetitions that will be performed. */
3205
3206 for (i = 0; i < 4; i++)
3207 {
3208 /* If X is sufficiently simple, don't bother trying to do anything
3209 with it. */
3210 if (code != CONST_INT && code != REG && code != CLOBBER)
3211 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
d0ab8cd3 3212
8079805d
RK		 3213 if (GET_CODE (x) == code)
3214 break;
d0ab8cd3 3215
8079805d 3216 code = GET_CODE (x);
eeb43d32 3217
8079805d
RK		 3218 /* We no longer know the original mode of operand 0 since we
3219 have changed the form of X) */
3220 op0_mode = VOIDmode;
3221 }
eeb43d32 3222
8079805d
RK		 3223 return x;
3224}
3225\f
3226/* Simplify X, a piece of RTL. We just operate on the expression at the
3227 outer level; call `subst' to simplify recursively. Return the new
3228 expression.
3229
3230 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3231 will be the iteration even if an expression with a code different from
3232 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
eeb43d32 3233
8079805d
RK		 3234static rtx
3235simplify_rtx (x, op0_mode, last, in_dest)
3236 rtx x;
3237 enum machine_mode op0_mode;
3238 int last;
3239 int in_dest;
3240{
3241 enum rtx_code code = GET_CODE (x);
3242 enum machine_mode mode = GET_MODE (x);
3243 rtx temp;
3244 int i;
d0ab8cd3 3245
230d793d
RS		 3246 /* If this is a commutative operation, put a constant last and a complex
3247 expression first. We don't need to do this for comparisons here. */
3248 if (GET_RTX_CLASS (code) == 'c'
3249 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3250 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3251 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3252 || (GET_CODE (XEXP (x, 0)) == SUBREG
3253 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3254 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3255 {
3256 temp = XEXP (x, 0);
3257 SUBST (XEXP (x, 0), XEXP (x, 1));
3258 SUBST (XEXP (x, 1), temp);
3259 }
3260
22609cbf
RK		 3261 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3262 sign extension of a PLUS with a constant, reverse the order of the sign
3263 extension and the addition. Note that this not the same as the original
3264 code, but overflow is undefined for signed values. Also note that the
3265 PLUS will have been partially moved "inside" the sign-extension, so that
3266 the first operand of X will really look like:
3267 (ashiftrt (plus (ashift A C4) C5) C4).
3268 We convert this to
3269 (plus (ashiftrt (ashift A C4) C2) C4)
3270 and replace the first operand of X with that expression. Later parts
3271 of this function may simplify the expression further.
3272
3273 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3274 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3275 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3276
3277 We do this to simplify address expressions. */
3278
3279 if ((code == PLUS || code == MINUS || code == MULT)
3280 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3281 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3282 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3283 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3284 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3285 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3286 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3287 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3288 XEXP (XEXP (XEXP (x, 0), 0), 1),
3289 XEXP (XEXP (x, 0), 1))) != 0)
3290 {
3291 rtx new
3292 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3293 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3294 INTVAL (XEXP (XEXP (x, 0), 1)));
3295
3296 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3297 INTVAL (XEXP (XEXP (x, 0), 1)));
3298
3299 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3300 }
3301
d0ab8cd3
RK		 3302 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3303 applying it to the arms of the IF_THEN_ELSE. This often simplifies
abe6e52f
RK		 3304 things. Check for cases where both arms are testing the same
3305 condition.
3306
3307 Don't do anything if all operands are very simple. */
3308
3309 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3310 || GET_RTX_CLASS (code) == '<')
3311 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3312 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3313 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3314 == 'o')))
3315 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3316 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3317 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3318 == 'o')))))
3319 || (GET_RTX_CLASS (code) == '1'
3320 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3321 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3322 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3323 == 'o'))))))
d0ab8cd3 3324 {
abe6e52f
RK		 3325 rtx cond, true, false;
3326
3327 cond = if_then_else_cond (x, &true, &false);
0802d516
RK		 3328 if (cond != 0
3329 /* If everything is a comparison, what we have is highly unlikely
3330 to be simpler, so don't use it. */
3331 && ! (GET_RTX_CLASS (code) == '<'
3332 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3333 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
abe6e52f
RK		 3334 {
3335 rtx cop1 = const0_rtx;
3336 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3337
15448afc
RK		 3338 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3339 return x;
3340
9210df58
RK		 3341 /* Simplify the alternative arms; this may collapse the true and
3342 false arms to store-flag values. */
3343 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3344 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3345
3346 /* Restarting if we generate a store-flag expression will cause
3347 us to loop. Just drop through in this case. */
3348
abe6e52f
RK		 3349 /* If the result values are STORE_FLAG_VALUE and zero, we can
3350 just make the comparison operation. */
3351 if (true == const_true_rtx && false == const0_rtx)
3352 x = gen_binary (cond_code, mode, cond, cop1);
3353 else if (true == const0_rtx && false == const_true_rtx)
3354 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3355
3356 /* Likewise, we can make the negate of a comparison operation
3357 if the result values are - STORE_FLAG_VALUE and zero. */
3358 else if (GET_CODE (true) == CONST_INT
3359 && INTVAL (true) == - STORE_FLAG_VALUE
3360 && false == const0_rtx)
0c1c8ea6 3361 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3362 gen_binary (cond_code, mode, cond, cop1));
3363 else if (GET_CODE (false) == CONST_INT
3364 && INTVAL (false) == - STORE_FLAG_VALUE
3365 && true == const0_rtx)
0c1c8ea6 3366 x = gen_unary (NEG, mode, mode,
abe6e52f
RK		 3367 gen_binary (reverse_condition (cond_code),
3368 mode, cond, cop1));
3369 else
38a448ca
RH		 3370 return gen_rtx_IF_THEN_ELSE (mode,
3371 gen_binary (cond_code, VOIDmode,
3372 cond, cop1),
3373 true, false);
5109d49f 3374
9210df58
RK		 3375 code = GET_CODE (x);
3376 op0_mode = VOIDmode;
abe6e52f 3377 }
d0ab8cd3
RK		 3378 }
3379
230d793d
RS		 3380 /* Try to fold this expression in case we have constants that weren't
3381 present before. */
3382 temp = 0;
3383 switch (GET_RTX_CLASS (code))
3384 {
3385 case '1':
3386 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3387 break;
3388 case '<':
3389 temp = simplify_relational_operation (code, op0_mode,
3390 XEXP (x, 0), XEXP (x, 1));
77fa0940
RK		 3391#ifdef FLOAT_STORE_FLAG_VALUE
3392 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3393 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3394 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3395#endif
230d793d
RS		 3396 break;
3397 case 'c':
3398 case '2':
3399 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3400 break;
3401 case 'b':
3402 case '3':
3403 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3404 XEXP (x, 1), XEXP (x, 2));
3405 break;
3406 }
3407
3408 if (temp)
d0ab8cd3 3409 x = temp, code = GET_CODE (temp);
230d793d 3410
230d793d 3411 /* First see if we can apply the inverse distributive law. */
224eeff2
RK		 3412 if (code == PLUS || code == MINUS
3413 || code == AND || code == IOR || code == XOR)
230d793d
RS		 3414 {
3415 x = apply_distributive_law (x);
3416 code = GET_CODE (x);
3417 }
3418
3419 /* If CODE is an associative operation not otherwise handled, see if we
3420 can associate some operands. This can win if they are constants or
3421 if they are logically related (i.e. (a & b) & a. */
3422 if ((code == PLUS || code == MINUS
3423 || code == MULT || code == AND || code == IOR || code == XOR
3424 || code == DIV || code == UDIV
3425 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3ad2180a 3426 && INTEGRAL_MODE_P (mode))
230d793d
RS		 3427 {
3428 if (GET_CODE (XEXP (x, 0)) == code)
3429 {
3430 rtx other = XEXP (XEXP (x, 0), 0);
3431 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3432 rtx inner_op1 = XEXP (x, 1);
3433 rtx inner;
3434
3435 /* Make sure we pass the constant operand if any as the second
3436 one if this is a commutative operation. */
3437 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3438 {
3439 rtx tem = inner_op0;
3440 inner_op0 = inner_op1;
3441 inner_op1 = tem;
3442 }
3443 inner = simplify_binary_operation (code == MINUS ? PLUS
3444 : code == DIV ? MULT
3445 : code == UDIV ? MULT
3446 : code,
3447 mode, inner_op0, inner_op1);
3448
3449 /* For commutative operations, try the other pair if that one
3450 didn't simplify. */
3451 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3452 {
3453 other = XEXP (XEXP (x, 0), 1);
3454 inner = simplify_binary_operation (code, mode,
3455 XEXP (XEXP (x, 0), 0),
3456 XEXP (x, 1));
3457 }
3458
3459 if (inner)
8079805d 3460 return gen_binary (code, mode, other, inner);
230d793d
RS		 3461 }
3462 }
3463
3464 /* A little bit of algebraic simplification here. */
3465 switch (code)
3466 {
3467 case MEM:
3468 /* Ensure that our address has any ASHIFTs converted to MULT in case
3469 address-recognizing predicates are called later. */
3470 temp = make_compound_operation (XEXP (x, 0), MEM);
3471 SUBST (XEXP (x, 0), temp);
3472 break;
3473
3474 case SUBREG:
3475 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3476 is paradoxical. If we can't do that safely, then it becomes
3477 something nonsensical so that this combination won't take place. */
3478
3479 if (GET_CODE (SUBREG_REG (x)) == MEM
3480 && (GET_MODE_SIZE (mode)
3481 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3482 {
3483 rtx inner = SUBREG_REG (x);
3484 int endian_offset = 0;
3485 /* Don't change the mode of the MEM
3486 if that would change the meaning of the address. */
3487 if (MEM_VOLATILE_P (SUBREG_REG (x))
3488 || mode_dependent_address_p (XEXP (inner, 0)))
38a448ca 3489 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d 3490
f76b9db2
ILT		 3491 if (BYTES_BIG_ENDIAN)
3492 {
3493 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3494 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3495 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3496 endian_offset -= (UNITS_PER_WORD
3497 - GET_MODE_SIZE (GET_MODE (inner)));
3498 }
230d793d
RS		 3499 /* Note if the plus_constant doesn't make a valid address
3500 then this combination won't be accepted. */
38a448ca
RH		 3501 x = gen_rtx_MEM (mode,
3502 plus_constant (XEXP (inner, 0),
3503 (SUBREG_WORD (x) * UNITS_PER_WORD
3504 + endian_offset)));
230d793d
RS		 3505 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3506 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3507 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3508 return x;
3509 }
3510
3511 /* If we are in a SET_DEST, these other cases can't apply. */
3512 if (in_dest)
3513 return x;
3514
3515 /* Changing mode twice with SUBREG => just change it once,
3516 or not at all if changing back to starting mode. */
3517 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3518 {
3519 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3520 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3521 return SUBREG_REG (SUBREG_REG (x));
3522
3523 SUBST_INT (SUBREG_WORD (x),
3524 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3525 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3526 }
3527
3528 /* SUBREG of a hard register => just change the register number
3529 and/or mode. If the hard register is not valid in that mode,
26ecfc76
RK		 3530 suppress this combination. If the hard register is the stack,
3531 frame, or argument pointer, leave this as a SUBREG. */
230d793d
RS		 3532
3533 if (GET_CODE (SUBREG_REG (x)) == REG
26ecfc76
RK		 3534 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3535 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
6d7096b0
DE		 3536#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3537 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3538#endif
26ecfc76
RK		 3539#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3540 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3541#endif
3542 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
230d793d
RS		 3543 {
3544 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3545 mode))
38a448ca
RH		 3546 return gen_rtx_REG (mode,
3547 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
230d793d 3548 else
38a448ca 3549 return gen_rtx_CLOBBER (mode, const0_rtx);
230d793d
RS		 3550 }
3551
3552 /* For a constant, try to pick up the part we want. Handle a full
a4bde0b1
RK		 3553 word and low-order part. Only do this if we are narrowing
3554 the constant; if it is being widened, we have no idea what
3555 the extra bits will have been set to. */
230d793d
RS		 3556
3557 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3558 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3c99d5ff 3559 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
230d793d
RS		 3560 && GET_MODE_CLASS (mode) == MODE_INT)
3561 {
3562 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
5f4f0e22 3563 0, op0_mode);
230d793d
RS		 3564 if (temp)
3565 return temp;
3566 }
3567
19808e22
RS		 3568 /* If we want a subreg of a constant, at offset 0,
3569 take the low bits. On a little-endian machine, that's
3570 always valid. On a big-endian machine, it's valid
3c99d5ff 3571 only if the constant's mode fits in one word. Note that we
61b1bece 3572 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3c99d5ff
RK		 3573 if (CONSTANT_P (SUBREG_REG (x))
3574 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3575 || ! WORDS_BIG_ENDIAN)
3576 ? SUBREG_WORD (x) == 0
3577 : (SUBREG_WORD (x)
3578 == ((GET_MODE_SIZE (op0_mode)
3579 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3580 / UNITS_PER_WORD)))
f82da7d2 3581 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
f76b9db2
ILT		 3582 && (! WORDS_BIG_ENDIAN
3583 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
230d793d
RS		 3584 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3585
b65c1b5b
RK		 3586 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3587 since we are saying that the high bits don't matter. */
3588 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3589 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3590 return SUBREG_REG (x);
3591
87e3e0c1
RK		 3592 /* Note that we cannot do any narrowing for non-constants since
3593 we might have been counting on using the fact that some bits were
3594 zero. We now do this in the SET. */
3595
230d793d
RS		 3596 break;
3597
3598 case NOT:
3599 /* (not (plus X -1)) can become (neg X). */
3600 if (GET_CODE (XEXP (x, 0)) == PLUS
3601 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
8079805d 3602 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3603
3604 /* Similarly, (not (neg X)) is (plus X -1). */
3605 if (GET_CODE (XEXP (x, 0)) == NEG)
8079805d
RK		 3606 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3607 constm1_rtx);
230d793d 3608
d0ab8cd3
RK		 3609 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3610 if (GET_CODE (XEXP (x, 0)) == XOR
3611 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3612 && (temp = simplify_unary_operation (NOT, mode,
3613 XEXP (XEXP (x, 0), 1),
3614 mode)) != 0)
787745f5 3615 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
d0ab8cd3 3616
230d793d
RS		 3617 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3618 other than 1, but that is not valid. We could do a similar
3619 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3620 but this doesn't seem common enough to bother with. */
3621 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3622 && XEXP (XEXP (x, 0), 0) == const1_rtx)
38a448ca
RH		 3623 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3624 XEXP (XEXP (x, 0), 1));
230d793d
RS		 3625
3626 if (GET_CODE (XEXP (x, 0)) == SUBREG
3627 && subreg_lowpart_p (XEXP (x, 0))
3628 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3629 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3630 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3631 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3632 {
3633 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3634
38a448ca
RH		 3635 x = gen_rtx_ROTATE (inner_mode,
3636 gen_unary (NOT, inner_mode, inner_mode,
3637 const1_rtx),
3638 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
8079805d 3639 return gen_lowpart_for_combine (mode, x);
230d793d
RS		 3640 }
3641
0802d516
RK		 3642 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3643 reversing the comparison code if valid. */
3644 if (STORE_FLAG_VALUE == -1
3645 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
230d793d
RS		 3646 && reversible_comparison_p (XEXP (x, 0)))
3647 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3648 mode, XEXP (XEXP (x, 0), 0),
3649 XEXP (XEXP (x, 0), 1));
500c518b
RK		 3650
3651 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
0802d516
RK		 3652 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3653 perform the above simplification. */
500c518b 3654
0802d516
RK		 3655 if (STORE_FLAG_VALUE == -1
3656 && XEXP (x, 1) == const1_rtx
500c518b
RK		 3657 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3658 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3659 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3660 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
230d793d
RS		 3661
3662 /* Apply De Morgan's laws to reduce number of patterns for machines
3663 with negating logical insns (and-not, nand, etc.). If result has
3664 only one NOT, put it first, since that is how the patterns are
3665 coded. */
3666
3667 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3668 {
3669 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3670
3671 if (GET_CODE (in1) == NOT)
3672 in1 = XEXP (in1, 0);
3673 else
3674 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3675
3676 if (GET_CODE (in2) == NOT)
3677 in2 = XEXP (in2, 0);
3678 else if (GET_CODE (in2) == CONST_INT
5f4f0e22
CH		 3679 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3680 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
230d793d
RS		 3681 else
3682 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3683
3684 if (GET_CODE (in2) == NOT)
3685 {
3686 rtx tem = in2;
3687 in2 = in1; in1 = tem;
3688 }
3689
8079805d
RK		 3690 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3691 mode, in1, in2);
230d793d
RS		 3692 }
3693 break;
3694
3695 case NEG:
3696 /* (neg (plus X 1)) can become (not X). */
3697 if (GET_CODE (XEXP (x, 0)) == PLUS
3698 && XEXP (XEXP (x, 0), 1) == const1_rtx)
8079805d 3699 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
230d793d
RS		 3700
3701 /* Similarly, (neg (not X)) is (plus X 1). */
3702 if (GET_CODE (XEXP (x, 0)) == NOT)
8079805d 3703 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
230d793d 3704
230d793d
RS		 3705 /* (neg (minus X Y)) can become (minus Y X). */
3706 if (GET_CODE (XEXP (x, 0)) == MINUS
3ad2180a 3707 && (! FLOAT_MODE_P (mode)
0f41302f 3708 /* x-y != -(y-x) with IEEE floating point. */
7e2a0d8e
RK		 3709 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3710 || flag_fast_math))
8079805d
RK		 3711 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3712 XEXP (XEXP (x, 0), 0));
230d793d 3713
0f41302f 3714 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
d0ab8cd3 3715 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
951553af 3716 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
8079805d 3717 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
d0ab8cd3 3718
230d793d
RS		 3719 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3720 if we can then eliminate the NEG (e.g.,
3721 if the operand is a constant). */
3722
3723 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3724 {
3725 temp = simplify_unary_operation (NEG, mode,
3726 XEXP (XEXP (x, 0), 0), mode);
3727 if (temp)
3728 {
3729 SUBST (XEXP (XEXP (x, 0), 0), temp);
3730 return XEXP (x, 0);
3731 }
3732 }
3733
3734 temp = expand_compound_operation (XEXP (x, 0));
3735
3736 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3737 replaced by (lshiftrt X C). This will convert
3738 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3739
3740 if (GET_CODE (temp) == ASHIFTRT
3741 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3742 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
8079805d
RK		 3743 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3744 INTVAL (XEXP (temp, 1)));
230d793d 3745
951553af 3746 /* If X has only a single bit that might be nonzero, say, bit I, convert
230d793d
RS		 3747 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3748 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3749 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3750 or a SUBREG of one since we'd be making the expression more
3751 complex if it was just a register. */
3752
3753 if (GET_CODE (temp) != REG
3754 && ! (GET_CODE (temp) == SUBREG
3755 && GET_CODE (SUBREG_REG (temp)) == REG)
951553af 3756 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
230d793d
RS		 3757 {
3758 rtx temp1 = simplify_shift_const
5f4f0e22
CH		 3759 (NULL_RTX, ASHIFTRT, mode,
3760 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
230d793d
RS		 3761 GET_MODE_BITSIZE (mode) - 1 - i),
3762 GET_MODE_BITSIZE (mode) - 1 - i);
3763
3764 /* If all we did was surround TEMP with the two shifts, we
3765 haven't improved anything, so don't use it. Otherwise,
3766 we are better off with TEMP1. */
3767 if (GET_CODE (temp1) != ASHIFTRT
3768 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3769 || XEXP (XEXP (temp1, 0), 0) != temp)
8079805d 3770 return temp1;
230d793d
RS		 3771 }
3772 break;
3773
2ca9ae17 3774 case TRUNCATE:
e30fb98f
JL		 3775 /* We can't handle truncation to a partial integer mode here
3776 because we don't know the real bitsize of the partial
3777 integer mode. */
3778 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3779 break;
3780
80608e27
JL		 3781 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3782 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3783 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
2ca9ae17
JW		 3784 SUBST (XEXP (x, 0),
3785 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3786 GET_MODE_MASK (mode), NULL_RTX, 0));
0f13a422
ILT		 3787
3788 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3789 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3790 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3791 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3792 return XEXP (XEXP (x, 0), 0);
3793
3794 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3795 (OP:SI foo:SI) if OP is NEG or ABS. */
3796 if ((GET_CODE (XEXP (x, 0)) == ABS
3797 || GET_CODE (XEXP (x, 0)) == NEG)
3798 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3799 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3800 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3801 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3802 XEXP (XEXP (XEXP (x, 0), 0), 0));
3803
3804 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3805 (truncate:SI x). */
3806 if (GET_CODE (XEXP (x, 0)) == SUBREG
3807 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3808 && subreg_lowpart_p (XEXP (x, 0)))
3809 return SUBREG_REG (XEXP (x, 0));
3810
3811 /* If we know that the value is already truncated, we can
6a992214
JL		 3812 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3813 nonzero for the corresponding modes. */
3814 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3815 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3816 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3817 >= GET_MODE_BITSIZE (mode) + 1)
0f13a422
ILT		 3818 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3819
3820 /* A truncate of a comparison can be replaced with a subreg if
3821 STORE_FLAG_VALUE permits. This is like the previous test,
3822 but it works even if the comparison is done in a mode larger
3823 than HOST_BITS_PER_WIDE_INT. */
3824 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3825 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3826 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3827 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3828
3829 /* Similarly, a truncate of a register whose value is a
3830 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3831 permits. */
3832 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3833 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3834 && (temp = get_last_value (XEXP (x, 0)))
3835 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3836 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3837
2ca9ae17
JW		 3838 break;
3839
230d793d
RS		 3840 case FLOAT_TRUNCATE:
3841 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3842 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3843 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3844 return XEXP (XEXP (x, 0), 0);
4635f748
RK		 3845
3846 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3847 (OP:SF foo:SF) if OP is NEG or ABS. */
3848 if ((GET_CODE (XEXP (x, 0)) == ABS
3849 || GET_CODE (XEXP (x, 0)) == NEG)
3850 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3851 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
0c1c8ea6
RK		 3852 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3853 XEXP (XEXP (XEXP (x, 0), 0), 0));
1d12df72
RK		 3854
3855 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3856 is (float_truncate:SF x). */
3857 if (GET_CODE (XEXP (x, 0)) == SUBREG
3858 && subreg_lowpart_p (XEXP (x, 0))
3859 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3860 return SUBREG_REG (XEXP (x, 0));
230d793d
RS		 3861 break;
3862
3863#ifdef HAVE_cc0
3864 case COMPARE:
3865 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3866 using cc0, in which case we want to leave it as a COMPARE
3867 so we can distinguish it from a register-register-copy. */
3868 if (XEXP (x, 1) == const0_rtx)
3869 return XEXP (x, 0);
3870
3871 /* In IEEE floating point, x-0 is not the same as x. */
3872 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e
RK		 3873 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3874 || flag_fast_math)
230d793d
RS		 3875 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3876 return XEXP (x, 0);
3877 break;
3878#endif
3879
3880 case CONST:
3881 /* (const (const X)) can become (const X). Do it this way rather than
3882 returning the inner CONST since CONST can be shared with a
3883 REG_EQUAL note. */
3884 if (GET_CODE (XEXP (x, 0)) == CONST)
3885 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3886 break;
3887
3888#ifdef HAVE_lo_sum
3889 case LO_SUM:
3890 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3891 can add in an offset. find_split_point will split this address up
3892 again if it doesn't match. */
3893 if (GET_CODE (XEXP (x, 0)) == HIGH
3894 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3895 return XEXP (x, 1);
3896 break;
3897#endif
3898
3899 case PLUS:
3900 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3901 outermost. That's because that's the way indexed addresses are
3902 supposed to appear. This code used to check many more cases, but
3903 they are now checked elsewhere. */
3904 if (GET_CODE (XEXP (x, 0)) == PLUS
3905 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3906 return gen_binary (PLUS, mode,
3907 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3908 XEXP (x, 1)),
3909 XEXP (XEXP (x, 0), 1));
3910
3911 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3912 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3913 bit-field and can be replaced by either a sign_extend or a
3914 sign_extract. The `and' may be a zero_extend. */
3915 if (GET_CODE (XEXP (x, 0)) == XOR
3916 && GET_CODE (XEXP (x, 1)) == CONST_INT
3917 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3918 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3919 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5f4f0e22 3920 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 3921 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3922 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3923 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5f4f0e22 3924 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
230d793d
RS		 3925 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3926 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3927 == i + 1))))
8079805d
RK		 3928 return simplify_shift_const
3929 (NULL_RTX, ASHIFTRT, mode,
3930 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3931 XEXP (XEXP (XEXP (x, 0), 0), 0),
3932 GET_MODE_BITSIZE (mode) - (i + 1)),
3933 GET_MODE_BITSIZE (mode) - (i + 1));
230d793d 3934
bc0776c6
RK		 3935 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3936 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3937 is 1. This produces better code than the alternative immediately
3938 below. */
3939 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3940 && reversible_comparison_p (XEXP (x, 0))
3941 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3942 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
8079805d 3943 return
0c1c8ea6 3944 gen_unary (NEG, mode, mode,
8079805d
RK		 3945 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3946 mode, XEXP (XEXP (x, 0), 0),
3947 XEXP (XEXP (x, 0), 1)));
bc0776c6
RK		 3948
3949 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
230d793d
RS		 3950 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3951 the bitsize of the mode - 1. This allows simplification of
3952 "a = (b & 8) == 0;" */
3953 if (XEXP (x, 1) == constm1_rtx
3954 && GET_CODE (XEXP (x, 0)) != REG
3955 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3956 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
951553af 3957 && nonzero_bits (XEXP (x, 0), mode) == 1)
8079805d
RK		 3958 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3959 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3960 gen_rtx_combine (XOR, mode,
3961 XEXP (x, 0), const1_rtx),
3962 GET_MODE_BITSIZE (mode) - 1),
3963 GET_MODE_BITSIZE (mode) - 1);
02f4ada4
RK		 3964
3965 /* If we are adding two things that have no bits in common, convert
3966 the addition into an IOR. This will often be further simplified,
3967 for example in cases like ((a & 1) + (a & 2)), which can
3968 become a & 3. */
3969
ac49a949 3970 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
951553af
RK		 3971 && (nonzero_bits (XEXP (x, 0), mode)
3972 & nonzero_bits (XEXP (x, 1), mode)) == 0)
8079805d 3973 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
230d793d
RS		 3974 break;
3975
3976 case MINUS:
0802d516
RK		 3977 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3978 by reversing the comparison code if valid. */
3979 if (STORE_FLAG_VALUE == 1
3980 && XEXP (x, 0) == const1_rtx
5109d49f
RK		 3981 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3982 && reversible_comparison_p (XEXP (x, 1)))
3983 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3984 mode, XEXP (XEXP (x, 1), 0),
3985 XEXP (XEXP (x, 1), 1));
5109d49f 3986
230d793d
RS		 3987 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3988 (and <foo> (const_int pow2-1)) */
3989 if (GET_CODE (XEXP (x, 1)) == AND
3990 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3991 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3992 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8079805d
RK		 3993 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3994 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
7bef8680
RK		 3995
3996 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3997 integers. */
3998 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
8079805d
RK		 3999 return gen_binary (MINUS, mode,
4000 gen_binary (MINUS, mode, XEXP (x, 0),
4001 XEXP (XEXP (x, 1), 0)),
4002 XEXP (XEXP (x, 1), 1));
230d793d
RS		 4003 break;
4004
4005 case MULT:
4006 /* If we have (mult (plus A B) C), apply the distributive law and then
4007 the inverse distributive law to see if things simplify. This
4008 occurs mostly in addresses, often when unrolling loops. */
4009
4010 if (GET_CODE (XEXP (x, 0)) == PLUS)
4011 {
4012 x = apply_distributive_law
4013 (gen_binary (PLUS, mode,
4014 gen_binary (MULT, mode,
4015 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4016 gen_binary (MULT, mode,
4017 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4018
4019 if (GET_CODE (x) != MULT)
8079805d 4020 return x;
230d793d 4021 }
230d793d
RS		 4022 break;
4023
4024 case UDIV:
4025 /* If this is a divide by a power of two, treat it as a shift if
4026 its first operand is a shift. */
4027 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4028 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4029 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4030 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4031 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4032 || GET_CODE (XEXP (x, 0)) == ROTATE
4033 || GET_CODE (XEXP (x, 0)) == ROTATERT))
8079805d 4034 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
230d793d
RS		 4035 break;
4036
4037 case EQ: case NE:
4038 case GT: case GTU: case GE: case GEU:
4039 case LT: case LTU: case LE: case LEU:
4040 /* If the first operand is a condition code, we can't do anything
4041 with it. */
4042 if (GET_CODE (XEXP (x, 0)) == COMPARE
4043 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4044#ifdef HAVE_cc0
4045 && XEXP (x, 0) != cc0_rtx
4046#endif
4047 ))
4048 {
4049 rtx op0 = XEXP (x, 0);
4050 rtx op1 = XEXP (x, 1);
4051 enum rtx_code new_code;
4052
4053 if (GET_CODE (op0) == COMPARE)
4054 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4055
4056 /* Simplify our comparison, if possible. */
4057 new_code = simplify_comparison (code, &op0, &op1);
4058
230d793d 4059 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
951553af 4060 if only the low-order bit is possibly nonzero in X (such as when
5109d49f
RK		 4061 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4062 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4063 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4064 (plus X 1).
4065
4066 Remove any ZERO_EXTRACT we made when thinking this was a
4067 comparison. It may now be simpler to use, e.g., an AND. If a
4068 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4069 the call to make_compound_operation in the SET case. */
4070
0802d516
RK		 4071 if (STORE_FLAG_VALUE == 1
4072 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4073 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4074 return gen_lowpart_for_combine (mode,
4075 expand_compound_operation (op0));
5109d49f 4076
0802d516
RK		 4077 else if (STORE_FLAG_VALUE == 1
4078 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4079 && op1 == const0_rtx
4080 && (num_sign_bit_copies (op0, mode)
4081 == GET_MODE_BITSIZE (mode)))
4082 {
4083 op0 = expand_compound_operation (op0);
0c1c8ea6 4084 return gen_unary (NEG, mode, mode,
8079805d 4085 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4086 }
4087
0802d516
RK		 4088 else if (STORE_FLAG_VALUE == 1
4089 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4090 && op1 == const0_rtx
5109d49f 4091 && nonzero_bits (op0, mode) == 1)
818b11b9
RK		 4092 {
4093 op0 = expand_compound_operation (op0);
8079805d
RK		 4094 return gen_binary (XOR, mode,
4095 gen_lowpart_for_combine (mode, op0),
4096 const1_rtx);
5109d49f 4097 }
818b11b9 4098
0802d516
RK		 4099 else if (STORE_FLAG_VALUE == 1
4100 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4101 && op1 == const0_rtx
4102 && (num_sign_bit_copies (op0, mode)
4103 == GET_MODE_BITSIZE (mode)))
4104 {
4105 op0 = expand_compound_operation (op0);
8079805d 4106 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
818b11b9 4107 }
230d793d 4108
5109d49f
RK		 4109 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4110 those above. */
0802d516
RK		 4111 if (STORE_FLAG_VALUE == -1
4112 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
230d793d 4113 && op1 == const0_rtx
5109d49f
RK		 4114 && (num_sign_bit_copies (op0, mode)
4115 == GET_MODE_BITSIZE (mode)))
4116 return gen_lowpart_for_combine (mode,
4117 expand_compound_operation (op0));
4118
0802d516
RK		 4119 else if (STORE_FLAG_VALUE == -1
4120 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4121 && op1 == const0_rtx
4122 && nonzero_bits (op0, mode) == 1)
4123 {
4124 op0 = expand_compound_operation (op0);
0c1c8ea6 4125 return gen_unary (NEG, mode, mode,
8079805d 4126 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4127 }
4128
0802d516
RK		 4129 else if (STORE_FLAG_VALUE == -1
4130 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4131 && op1 == const0_rtx
4132 && (num_sign_bit_copies (op0, mode)
4133 == GET_MODE_BITSIZE (mode)))
230d793d 4134 {
818b11b9 4135 op0 = expand_compound_operation (op0);
0c1c8ea6 4136 return gen_unary (NOT, mode, mode,
8079805d 4137 gen_lowpart_for_combine (mode, op0));
5109d49f
RK		 4138 }
4139
4140 /* If X is 0/1, (eq X 0) is X-1. */
0802d516
RK		 4141 else if (STORE_FLAG_VALUE == -1
4142 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109d49f
RK		 4143 && op1 == const0_rtx
4144 && nonzero_bits (op0, mode) == 1)
4145 {
4146 op0 = expand_compound_operation (op0);
8079805d 4147 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
230d793d 4148 }
230d793d
RS		 4149
4150 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
951553af
RK		 4151 one bit that might be nonzero, we can convert (ne x 0) to
4152 (ashift x c) where C puts the bit in the sign bit. Remove any
4153 AND with STORE_FLAG_VALUE when we are done, since we are only
4154 going to test the sign bit. */
3f508eca 4155 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5f4f0e22 4156 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 4157 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 4158 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
230d793d
RS		 4159 && op1 == const0_rtx
4160 && mode == GET_MODE (op0)
5109d49f 4161 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
230d793d 4162 {
818b11b9
RK		 4163 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4164 expand_compound_operation (op0),
230d793d
RS		 4165 GET_MODE_BITSIZE (mode) - 1 - i);
4166 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4167 return XEXP (x, 0);
4168 else
4169 return x;
4170 }
4171
4172 /* If the code changed, return a whole new comparison. */
4173 if (new_code != code)
4174 return gen_rtx_combine (new_code, mode, op0, op1);
4175
4176 /* Otherwise, keep this operation, but maybe change its operands.
4177 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4178 SUBST (XEXP (x, 0), op0);
4179 SUBST (XEXP (x, 1), op1);
4180 }
4181 break;
4182
4183 case IF_THEN_ELSE:
8079805d 4184 return simplify_if_then_else (x);
9210df58 4185
8079805d
RK		 4186 case ZERO_EXTRACT:
4187 case SIGN_EXTRACT:
4188 case ZERO_EXTEND:
4189 case SIGN_EXTEND:
0f41302f 4190 /* If we are processing SET_DEST, we are done. */
8079805d
RK		 4191 if (in_dest)
4192 return x;
d0ab8cd3 4193
8079805d 4194 return expand_compound_operation (x);
d0ab8cd3 4195
8079805d
RK		 4196 case SET:
4197 return simplify_set (x);
1a26b032 4198
8079805d
RK		 4199 case AND:
4200 case IOR:
4201 case XOR:
4202 return simplify_logical (x, last);
d0ab8cd3 4203
b472527b 4204 case ABS:
8079805d
RK		 4205 /* (abs (neg <foo>)) -> (abs <foo>) */
4206 if (GET_CODE (XEXP (x, 0)) == NEG)
4207 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
1a26b032 4208
b472527b
JL		 4209 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4210 do nothing. */
4211 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4212 break;
f40421ce 4213
8079805d
RK		 4214 /* If operand is something known to be positive, ignore the ABS. */
4215 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4216 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4217 <= HOST_BITS_PER_WIDE_INT)
4218 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4219 & ((HOST_WIDE_INT) 1
4220 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4221 == 0)))
4222 return XEXP (x, 0);
1a26b032 4223
1a26b032 4224
8079805d
RK		 4225 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4226 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4227 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
1a26b032 4228
8079805d 4229 break;
1a26b032 4230
8079805d
RK		 4231 case FFS:
4232 /* (ffs (*_extend <X>)) = (ffs <X>) */
4233 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4234 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4235 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4236 break;
1a26b032 4237
8079805d
RK		 4238 case FLOAT:
4239 /* (float (sign_extend <X>)) = (float <X>). */
4240 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4241 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4242 break;
1a26b032 4243
8079805d
RK		 4244 case ASHIFT:
4245 case LSHIFTRT:
4246 case ASHIFTRT:
4247 case ROTATE:
4248 case ROTATERT:
4249 /* If this is a shift by a constant amount, simplify it. */
4250 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4251 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4252 INTVAL (XEXP (x, 1)));
4253
4254#ifdef SHIFT_COUNT_TRUNCATED
4255 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4256 SUBST (XEXP (x, 1),
4257 force_to_mode (XEXP (x, 1), GET_MODE (x),
4258 ((HOST_WIDE_INT) 1
4259 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4260 - 1,
4261 NULL_RTX, 0));
4262#endif
4263
4264 break;
e9a25f70
JL		 4265
4266 default:
4267 break;
8079805d
RK		 4268 }
4269
4270 return x;
4271}
4272\f
4273/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5109d49f 4274
8079805d
RK		 4275static rtx
4276simplify_if_then_else (x)
4277 rtx x;
4278{
4279 enum machine_mode mode = GET_MODE (x);
4280 rtx cond = XEXP (x, 0);
4281 rtx true = XEXP (x, 1);
4282 rtx false = XEXP (x, 2);
4283 enum rtx_code true_code = GET_CODE (cond);
4284 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4285 rtx temp;
4286 int i;
4287
0f41302f 4288 /* Simplify storing of the truth value. */
8079805d
RK		 4289 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4290 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4291
0f41302f 4292 /* Also when the truth value has to be reversed. */
8079805d
RK		 4293 if (comparison_p && reversible_comparison_p (cond)
4294 && true == const0_rtx && false == const_true_rtx)
4295 return gen_binary (reverse_condition (true_code),
4296 mode, XEXP (cond, 0), XEXP (cond, 1));
4297
4298 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4299 in it is being compared against certain values. Get the true and false
4300 comparisons and see if that says anything about the value of each arm. */
4301
4302 if (comparison_p && reversible_comparison_p (cond)
4303 && GET_CODE (XEXP (cond, 0)) == REG)
4304 {
4305 HOST_WIDE_INT nzb;
4306 rtx from = XEXP (cond, 0);
4307 enum rtx_code false_code = reverse_condition (true_code);
4308 rtx true_val = XEXP (cond, 1);
4309 rtx false_val = true_val;
4310 int swapped = 0;
9210df58 4311
8079805d 4312 /* If FALSE_CODE is EQ, swap the codes and arms. */
5109d49f 4313
8079805d 4314 if (false_code == EQ)
1a26b032 4315 {
8079805d
RK		 4316 swapped = 1, true_code = EQ, false_code = NE;
4317 temp = true, true = false, false = temp;
4318 }
5109d49f 4319
8079805d
RK		 4320 /* If we are comparing against zero and the expression being tested has
4321 only a single bit that might be nonzero, that is its value when it is
4322 not equal to zero. Similarly if it is known to be -1 or 0. */
4323
4324 if (true_code == EQ && true_val == const0_rtx
4325 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4326 false_code = EQ, false_val = GEN_INT (nzb);
4327 else if (true_code == EQ && true_val == const0_rtx
4328 && (num_sign_bit_copies (from, GET_MODE (from))
4329 == GET_MODE_BITSIZE (GET_MODE (from))))
4330 false_code = EQ, false_val = constm1_rtx;
4331
4332 /* Now simplify an arm if we know the value of the register in the
4333 branch and it is used in the arm. Be careful due to the potential
4334 of locally-shared RTL. */
4335
4336 if (reg_mentioned_p (from, true))
4337 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4338 pc_rtx, pc_rtx, 0, 0);
4339 if (reg_mentioned_p (from, false))
4340 false = subst (known_cond (copy_rtx (false), false_code,
4341 from, false_val),
4342 pc_rtx, pc_rtx, 0, 0);
4343
4344 SUBST (XEXP (x, 1), swapped ? false : true);
4345 SUBST (XEXP (x, 2), swapped ? true : false);
4346
4347 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4348 }
5109d49f 4349
8079805d
RK		 4350 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4351 reversed, do so to avoid needing two sets of patterns for
4352 subtract-and-branch insns. Similarly if we have a constant in the true
4353 arm, the false arm is the same as the first operand of the comparison, or
4354 the false arm is more complicated than the true arm. */
4355
4356 if (comparison_p && reversible_comparison_p (cond)
4357 && (true == pc_rtx
4358 || (CONSTANT_P (true)
4359 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4360 || true == const0_rtx
4361 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4362 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4363 || (GET_CODE (true) == SUBREG
4364 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4365 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4366 || reg_mentioned_p (true, false)
4367 || rtx_equal_p (false, XEXP (cond, 0))))
4368 {
4369 true_code = reverse_condition (true_code);
4370 SUBST (XEXP (x, 0),
4371 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4372 XEXP (cond, 1)));
5109d49f 4373
8079805d
RK		 4374 SUBST (XEXP (x, 1), false);
4375 SUBST (XEXP (x, 2), true);
1a26b032 4376
8079805d 4377 temp = true, true = false, false = temp, cond = XEXP (x, 0);
bb821298 4378
0f41302f 4379 /* It is possible that the conditional has been simplified out. */
bb821298
RK		 4380 true_code = GET_CODE (cond);
4381 comparison_p = GET_RTX_CLASS (true_code) == '<';
8079805d 4382 }
abe6e52f 4383
8079805d 4384 /* If the two arms are identical, we don't need the comparison. */
1a26b032 4385
8079805d
RK		 4386 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4387 return true;
1a26b032 4388
5be669c7
RK		 4389 /* Convert a == b ? b : a to "a". */
4390 if (true_code == EQ && ! side_effects_p (cond)
4391 && rtx_equal_p (XEXP (cond, 0), false)
4392 && rtx_equal_p (XEXP (cond, 1), true))
4393 return false;
4394 else if (true_code == NE && ! side_effects_p (cond)
4395 && rtx_equal_p (XEXP (cond, 0), true)
4396 && rtx_equal_p (XEXP (cond, 1), false))
4397 return true;
4398
8079805d
RK		 4399 /* Look for cases where we have (abs x) or (neg (abs X)). */
4400
4401 if (GET_MODE_CLASS (mode) == MODE_INT
4402 && GET_CODE (false) == NEG
4403 && rtx_equal_p (true, XEXP (false, 0))
4404 && comparison_p
4405 && rtx_equal_p (true, XEXP (cond, 0))
4406 && ! side_effects_p (true))
4407 switch (true_code)
4408 {
4409 case GT:
4410 case GE:
0c1c8ea6 4411 return gen_unary (ABS, mode, mode, true);
8079805d
RK		 4412 case LT:
4413 case LE:
0c1c8ea6 4414 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
e9a25f70
JL		 4415 default:
4416 break;
8079805d
RK		 4417 }
4418
4419 /* Look for MIN or MAX. */
4420
34c8be72 4421 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
8079805d
RK		 4422 && comparison_p
4423 && rtx_equal_p (XEXP (cond, 0), true)
4424 && rtx_equal_p (XEXP (cond, 1), false)
4425 && ! side_effects_p (cond))
4426 switch (true_code)
4427 {
4428 case GE:
4429 case GT:
4430 return gen_binary (SMAX, mode, true, false);
4431 case LE:
4432 case LT:
4433 return gen_binary (SMIN, mode, true, false);
4434 case GEU:
4435 case GTU:
4436 return gen_binary (UMAX, mode, true, false);
4437 case LEU:
4438 case LTU:
4439 return gen_binary (UMIN, mode, true, false);
e9a25f70
JL		 4440 default:
4441 break;
8079805d
RK		 4442 }
4443
8079805d
RK		 4444 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4445 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4446 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4447 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4448 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
0802d516 4449 neither 1 or -1, but it isn't worth checking for. */
8079805d 4450
0802d516
RK		 4451 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4452 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
8079805d
RK		 4453 {
4454 rtx t = make_compound_operation (true, SET);
4455 rtx f = make_compound_operation (false, SET);
4456 rtx cond_op0 = XEXP (cond, 0);
4457 rtx cond_op1 = XEXP (cond, 1);
4458 enum rtx_code op, extend_op = NIL;
4459 enum machine_mode m = mode;
f24ad0e4 4460 rtx z = 0, c1;
8079805d 4461
8079805d
RK		 4462 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4463 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4464 || GET_CODE (t) == ASHIFT
4465 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4466 && rtx_equal_p (XEXP (t, 0), f))
4467 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4468
4469 /* If an identity-zero op is commutative, check whether there
0f41302f 4470 would be a match if we swapped the operands. */
8079805d
RK		 4471 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4472 || GET_CODE (t) == XOR)
4473 && rtx_equal_p (XEXP (t, 1), f))
4474 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4475 else if (GET_CODE (t) == SIGN_EXTEND
4476 && (GET_CODE (XEXP (t, 0)) == PLUS
4477 || GET_CODE (XEXP (t, 0)) == MINUS
4478 || GET_CODE (XEXP (t, 0)) == IOR
4479 || GET_CODE (XEXP (t, 0)) == XOR
4480 || GET_CODE (XEXP (t, 0)) == ASHIFT
4481 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4482 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4483 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4484 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4485 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4486 && (num_sign_bit_copies (f, GET_MODE (f))
4487 > (GET_MODE_BITSIZE (mode)
4488 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4489 {
4490 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4491 extend_op = SIGN_EXTEND;
4492 m = GET_MODE (XEXP (t, 0));
1a26b032 4493 }
8079805d
RK		 4494 else if (GET_CODE (t) == SIGN_EXTEND
4495 && (GET_CODE (XEXP (t, 0)) == PLUS
4496 || GET_CODE (XEXP (t, 0)) == IOR
4497 || GET_CODE (XEXP (t, 0)) == XOR)
4498 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4499 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4500 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4501 && (num_sign_bit_copies (f, GET_MODE (f))
4502 > (GET_MODE_BITSIZE (mode)
4503 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4504 {
4505 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4506 extend_op = SIGN_EXTEND;
4507 m = GET_MODE (XEXP (t, 0));
4508 }
4509 else if (GET_CODE (t) == ZERO_EXTEND
4510 && (GET_CODE (XEXP (t, 0)) == PLUS
4511 || GET_CODE (XEXP (t, 0)) == MINUS
4512 || GET_CODE (XEXP (t, 0)) == IOR
4513 || GET_CODE (XEXP (t, 0)) == XOR
4514 || GET_CODE (XEXP (t, 0)) == ASHIFT
4515 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4516 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4517 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4518 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4519 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4520 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4521 && ((nonzero_bits (f, GET_MODE (f))
4522 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4523 == 0))
4524 {
4525 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4526 extend_op = ZERO_EXTEND;
4527 m = GET_MODE (XEXP (t, 0));
4528 }
4529 else if (GET_CODE (t) == ZERO_EXTEND
4530 && (GET_CODE (XEXP (t, 0)) == PLUS
4531 || GET_CODE (XEXP (t, 0)) == IOR
4532 || GET_CODE (XEXP (t, 0)) == XOR)
4533 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4534 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4535 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4536 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4537 && ((nonzero_bits (f, GET_MODE (f))
4538 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4539 == 0))
4540 {
4541 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4542 extend_op = ZERO_EXTEND;
4543 m = GET_MODE (XEXP (t, 0));
4544 }
4545
4546 if (z)
4547 {
4548 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4549 pc_rtx, pc_rtx, 0, 0);
4550 temp = gen_binary (MULT, m, temp,
4551 gen_binary (MULT, m, c1, const_true_rtx));
4552 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4553 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4554
4555 if (extend_op != NIL)
0c1c8ea6 4556 temp = gen_unary (extend_op, mode, m, temp);
8079805d
RK		 4557
4558 return temp;
4559 }
4560 }
224eeff2 4561
8079805d
RK		 4562 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4563 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4564 negation of a single bit, we can convert this operation to a shift. We
4565 can actually do this more generally, but it doesn't seem worth it. */
4566
4567 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4568 && false == const0_rtx && GET_CODE (true) == CONST_INT
4569 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4570 && (i = exact_log2 (INTVAL (true))) >= 0)
4571 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4572 == GET_MODE_BITSIZE (mode))
4573 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4574 return
4575 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4576 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
230d793d 4577
8079805d
RK		 4578 return x;
4579}
4580\f
4581/* Simplify X, a SET expression. Return the new expression. */
230d793d 4582
8079805d
RK		 4583static rtx
4584simplify_set (x)
4585 rtx x;
4586{
4587 rtx src = SET_SRC (x);
4588 rtx dest = SET_DEST (x);
4589 enum machine_mode mode
4590 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4591 rtx other_insn;
4592 rtx *cc_use;
4593
4594 /* (set (pc) (return)) gets written as (return). */
4595 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4596 return src;
230d793d 4597
87e3e0c1
RK		 4598 /* Now that we know for sure which bits of SRC we are using, see if we can
4599 simplify the expression for the object knowing that we only need the
4600 low-order bits. */
4601
4602 if (GET_MODE_CLASS (mode) == MODE_INT)
4603 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4604
8079805d
RK		 4605 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4606 the comparison result and try to simplify it unless we already have used
4607 undobuf.other_insn. */
4608 if ((GET_CODE (src) == COMPARE
230d793d 4609#ifdef HAVE_cc0
8079805d 4610 || dest == cc0_rtx
230d793d 4611#endif
8079805d
RK		 4612 )
4613 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4614 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4615 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
c0d3ac4d 4616 && rtx_equal_p (XEXP (*cc_use, 0), dest))
8079805d
RK		 4617 {
4618 enum rtx_code old_code = GET_CODE (*cc_use);
4619 enum rtx_code new_code;
4620 rtx op0, op1;
4621 int other_changed = 0;
4622 enum machine_mode compare_mode = GET_MODE (dest);
4623
4624 if (GET_CODE (src) == COMPARE)
4625 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4626 else
4627 op0 = src, op1 = const0_rtx;
230d793d 4628
8079805d
RK		 4629 /* Simplify our comparison, if possible. */
4630 new_code = simplify_comparison (old_code, &op0, &op1);
230d793d 4631
c141a106 4632#ifdef EXTRA_CC_MODES
8079805d
RK		 4633 /* If this machine has CC modes other than CCmode, check to see if we
4634 need to use a different CC mode here. */
4635 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
c141a106 4636#endif /* EXTRA_CC_MODES */
230d793d 4637
c141a106 4638#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
8079805d
RK		 4639 /* If the mode changed, we have to change SET_DEST, the mode in the
4640 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4641 a hard register, just build new versions with the proper mode. If it
4642 is a pseudo, we lose unless it is only time we set the pseudo, in
4643 which case we can safely change its mode. */
4644 if (compare_mode != GET_MODE (dest))
4645 {
4646 int regno = REGNO (dest);
38a448ca 4647 rtx new_dest = gen_rtx_REG (compare_mode, regno);
8079805d
RK		 4648
4649 if (regno < FIRST_PSEUDO_REGISTER
b1f21e0a 4650 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
230d793d 4651 {
8079805d
RK		 4652 if (regno >= FIRST_PSEUDO_REGISTER)
4653 SUBST (regno_reg_rtx[regno], new_dest);
230d793d 4654
8079805d
RK		 4655 SUBST (SET_DEST (x), new_dest);
4656 SUBST (XEXP (*cc_use, 0), new_dest);
4657 other_changed = 1;
230d793d 4658
8079805d 4659 dest = new_dest;
230d793d 4660 }
8079805d 4661 }
230d793d
RS		 4662#endif
4663
8079805d
RK		 4664 /* If the code changed, we have to build a new comparison in
4665 undobuf.other_insn. */
4666 if (new_code != old_code)
4667 {
4668 unsigned HOST_WIDE_INT mask;
4669
4670 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4671 dest, const0_rtx));
4672
4673 /* If the only change we made was to change an EQ into an NE or
4674 vice versa, OP0 has only one bit that might be nonzero, and OP1
4675 is zero, check if changing the user of the condition code will
4676 produce a valid insn. If it won't, we can keep the original code
4677 in that insn by surrounding our operation with an XOR. */
4678
4679 if (((old_code == NE && new_code == EQ)
4680 || (old_code == EQ && new_code == NE))
4681 && ! other_changed && op1 == const0_rtx
4682 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4683 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
230d793d 4684 {
8079805d 4685 rtx pat = PATTERN (other_insn), note = 0;
230d793d 4686
8e2f6e35 4687 if ((recog_for_combine (&pat, other_insn, &note) < 0
8079805d
RK		 4688 && ! check_asm_operands (pat)))
4689 {
4690 PUT_CODE (*cc_use, old_code);
4691 other_insn = 0;
230d793d 4692
8079805d 4693 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
230d793d 4694 }
230d793d
RS		 4695 }
4696
8079805d
RK		 4697 other_changed = 1;
4698 }
4699
4700 if (other_changed)
4701 undobuf.other_insn = other_insn;
230d793d
RS		 4702
4703#ifdef HAVE_cc0
8079805d
RK		 4704 /* If we are now comparing against zero, change our source if
4705 needed. If we do not use cc0, we always have a COMPARE. */
4706 if (op1 == const0_rtx && dest == cc0_rtx)
4707 {
4708 SUBST (SET_SRC (x), op0);
4709 src = op0;
4710 }
4711 else
230d793d
RS		 4712#endif
4713
8079805d
RK		 4714 /* Otherwise, if we didn't previously have a COMPARE in the
4715 correct mode, we need one. */
4716 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4717 {
4718 SUBST (SET_SRC (x),
4719 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4720 src = SET_SRC (x);
230d793d
RS		 4721 }
4722 else
4723 {
8079805d
RK		 4724 /* Otherwise, update the COMPARE if needed. */
4725 SUBST (XEXP (src, 0), op0);
4726 SUBST (XEXP (src, 1), op1);
230d793d 4727 }
8079805d
RK		 4728 }
4729 else
4730 {
4731 /* Get SET_SRC in a form where we have placed back any
4732 compound expressions. Then do the checks below. */
4733 src = make_compound_operation (src, SET);
4734 SUBST (SET_SRC (x), src);
4735 }
230d793d 4736
8079805d
RK		 4737 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4738 and X being a REG or (subreg (reg)), we may be able to convert this to
4739 (set (subreg:m2 x) (op)).
df62f951 4740
8079805d
RK		 4741 We can always do this if M1 is narrower than M2 because that means that
4742 we only care about the low bits of the result.
df62f951 4743
8079805d 4744 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
9ec36da5 4745 perform a narrower operation than requested since the high-order bits will
8079805d
RK		 4746 be undefined. On machine where it is defined, this transformation is safe
4747 as long as M1 and M2 have the same number of words. */
df62f951 4748
8079805d
RK		 4749 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4750 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4751 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4752 / UNITS_PER_WORD)
4753 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4754 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
8baf60bb 4755#ifndef WORD_REGISTER_OPERATIONS
8079805d
RK		 4756 && (GET_MODE_SIZE (GET_MODE (src))
4757 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
df62f951 4758#endif
f507a070
RK		 4759#ifdef CLASS_CANNOT_CHANGE_SIZE
4760 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4761 && (TEST_HARD_REG_BIT
4762 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4763 REGNO (dest)))
4764 && (GET_MODE_SIZE (GET_MODE (src))
4765 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4766#endif
8079805d
RK		 4767 && (GET_CODE (dest) == REG
4768 || (GET_CODE (dest) == SUBREG
4769 && GET_CODE (SUBREG_REG (dest)) == REG)))
4770 {
4771 SUBST (SET_DEST (x),
4772 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4773 dest));
4774 SUBST (SET_SRC (x), SUBREG_REG (src));
4775
4776 src = SET_SRC (x), dest = SET_DEST (x);
4777 }
df62f951 4778
8baf60bb 4779#ifdef LOAD_EXTEND_OP
8079805d
RK		 4780 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4781 would require a paradoxical subreg. Replace the subreg with a
0f41302f 4782 zero_extend to avoid the reload that would otherwise be required. */
8079805d
RK		 4783
4784 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4785 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4786 && SUBREG_WORD (src) == 0
4787 && (GET_MODE_SIZE (GET_MODE (src))
4788 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4789 && GET_CODE (SUBREG_REG (src)) == MEM)
4790 {
4791 SUBST (SET_SRC (x),
4792 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4793 GET_MODE (src), XEXP (src, 0)));
4794
4795 src = SET_SRC (x);
4796 }
230d793d
RS		 4797#endif
4798
8079805d
RK		 4799 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4800 are comparing an item known to be 0 or -1 against 0, use a logical
4801 operation instead. Check for one of the arms being an IOR of the other
4802 arm with some value. We compute three terms to be IOR'ed together. In
4803 practice, at most two will be nonzero. Then we do the IOR's. */
4804
4805 if (GET_CODE (dest) != PC
4806 && GET_CODE (src) == IF_THEN_ELSE
36b8d792 4807 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
8079805d
RK		 4808 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4809 && XEXP (XEXP (src, 0), 1) == const0_rtx
6dd49058 4810 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
ea414472
DE		 4811#ifdef HAVE_conditional_move
4812 && ! can_conditionally_move_p (GET_MODE (src))
4813#endif
8079805d
RK		 4814 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4815 GET_MODE (XEXP (XEXP (src, 0), 0)))
4816 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4817 && ! side_effects_p (src))
4818 {
4819 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4820 ? XEXP (src, 1) : XEXP (src, 2));
4821 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4822 ? XEXP (src, 2) : XEXP (src, 1));
4823 rtx term1 = const0_rtx, term2, term3;
4824
4825 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4826 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4827 else if (GET_CODE (true) == IOR
4828 && rtx_equal_p (XEXP (true, 1), false))
4829 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4830 else if (GET_CODE (false) == IOR
4831 && rtx_equal_p (XEXP (false, 0), true))
4832 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4833 else if (GET_CODE (false) == IOR
4834 && rtx_equal_p (XEXP (false, 1), true))
4835 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4836
4837 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4838 term3 = gen_binary (AND, GET_MODE (src),
0c1c8ea6 4839 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
8079805d
RK		 4840 XEXP (XEXP (src, 0), 0)),
4841 false);
4842
4843 SUBST (SET_SRC (x),
4844 gen_binary (IOR, GET_MODE (src),
4845 gen_binary (IOR, GET_MODE (src), term1, term2),
4846 term3));
4847
4848 src = SET_SRC (x);
4849 }
230d793d 4850
246e00f2
RK		 4851 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4852 whole thing fail. */
4853 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4854 return src;
4855 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4856 return dest;
4857 else
4858 /* Convert this into a field assignment operation, if possible. */
4859 return make_field_assignment (x);
8079805d
RK		 4860}
4861\f
4862/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4863 result. LAST is nonzero if this is the last retry. */
4864
4865static rtx
4866simplify_logical (x, last)
4867 rtx x;
4868 int last;
4869{
4870 enum machine_mode mode = GET_MODE (x);
4871 rtx op0 = XEXP (x, 0);
4872 rtx op1 = XEXP (x, 1);
4873
4874 switch (GET_CODE (x))
4875 {
230d793d 4876 case AND:
8079805d
RK		 4877 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4878 insn (and may simplify more). */
4879 if (GET_CODE (op0) == XOR
4880 && rtx_equal_p (XEXP (op0, 0), op1)
4881 && ! side_effects_p (op1))
0c1c8ea6
RK		 4882 x = gen_binary (AND, mode,
4883 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
8079805d
RK		 4884
4885 if (GET_CODE (op0) == XOR
4886 && rtx_equal_p (XEXP (op0, 1), op1)
4887 && ! side_effects_p (op1))
0c1c8ea6
RK		 4888 x = gen_binary (AND, mode,
4889 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
8079805d
RK		 4890
4891 /* Similarly for (~ (A ^ B)) & A. */
4892 if (GET_CODE (op0) == NOT
4893 && GET_CODE (XEXP (op0, 0)) == XOR
4894 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4895 && ! side_effects_p (op1))
4896 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4897
4898 if (GET_CODE (op0) == NOT
4899 && GET_CODE (XEXP (op0, 0)) == XOR
4900 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4901 && ! side_effects_p (op1))
4902 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4903
4904 if (GET_CODE (op1) == CONST_INT)
230d793d 4905 {
8079805d 4906 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
230d793d
RS		 4907
4908 /* If we have (ior (and (X C1) C2)) and the next restart would be
4909 the last, simplify this by making C1 as small as possible
0f41302f 4910 and then exit. */
8079805d
RK		 4911 if (last
4912 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4913 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4914 && GET_CODE (op1) == CONST_INT)
4915 return gen_binary (IOR, mode,
4916 gen_binary (AND, mode, XEXP (op0, 0),
4917 GEN_INT (INTVAL (XEXP (op0, 1))
4918 & ~ INTVAL (op1))), op1);
230d793d
RS		 4919
4920 if (GET_CODE (x) != AND)
8079805d 4921 return x;
0e32506c
RK		 4922
4923 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4924 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4925 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
230d793d
RS		 4926 }
4927
4928 /* Convert (A | B) & A to A. */
8079805d
RK		 4929 if (GET_CODE (op0) == IOR
4930 && (rtx_equal_p (XEXP (op0, 0), op1)
4931 || rtx_equal_p (XEXP (op0, 1), op1))
4932 && ! side_effects_p (XEXP (op0, 0))
4933 && ! side_effects_p (XEXP (op0, 1)))
4934 return op1;
230d793d 4935
d0ab8cd3 4936 /* In the following group of tests (and those in case IOR below),
230d793d
RS		 4937 we start with some combination of logical operations and apply
4938 the distributive law followed by the inverse distributive law.
4939 Most of the time, this results in no change. However, if some of
4940 the operands are the same or inverses of each other, simplifications
4941 will result.
4942
4943 For example, (and (ior A B) (not B)) can occur as the result of
4944 expanding a bit field assignment. When we apply the distributive
4945 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8079805d 4946 which then simplifies to (and (A (not B))).
230d793d 4947
8079805d 4948 If we have (and (ior A B) C), apply the distributive law and then
230d793d
RS		 4949 the inverse distributive law to see if things simplify. */
4950
8079805d 4951 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
230d793d
RS		 4952 {
4953 x = apply_distributive_law
8079805d
RK		 4954 (gen_binary (GET_CODE (op0), mode,
4955 gen_binary (AND, mode, XEXP (op0, 0), op1),
4956 gen_binary (AND, mode, XEXP (op0, 1), op1)));
230d793d 4957 if (GET_CODE (x) != AND)
8079805d 4958 return x;
230d793d
RS		 4959 }
4960
8079805d
RK		 4961 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4962 return apply_distributive_law
4963 (gen_binary (GET_CODE (op1), mode,
4964 gen_binary (AND, mode, XEXP (op1, 0), op0),
4965 gen_binary (AND, mode, XEXP (op1, 1), op0)));
230d793d
RS		 4966
4967 /* Similarly, taking advantage of the fact that
4968 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4969
8079805d
RK		 4970 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4971 return apply_distributive_law
4972 (gen_binary (XOR, mode,
4973 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4974 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
230d793d 4975
8079805d
RK		 4976 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4977 return apply_distributive_law
4978 (gen_binary (XOR, mode,
4979 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4980 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
230d793d
RS		 4981 break;
4982
4983 case IOR:
951553af 4984 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
8079805d 4985 if (GET_CODE (op1) == CONST_INT
ac49a949 4986 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8079805d
RK		 4987 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4988 return op1;
d0ab8cd3 4989
230d793d 4990 /* Convert (A & B) | A to A. */
8079805d
RK		 4991 if (GET_CODE (op0) == AND
4992 && (rtx_equal_p (XEXP (op0, 0), op1)
4993 || rtx_equal_p (XEXP (op0, 1), op1))
4994 && ! side_effects_p (XEXP (op0, 0))
4995 && ! side_effects_p (XEXP (op0, 1)))
4996 return op1;
230d793d
RS		 4997
4998 /* If we have (ior (and A B) C), apply the distributive law and then
4999 the inverse distributive law to see if things simplify. */
5000
8079805d 5001 if (GET_CODE (op0) == AND)
230d793d
RS		 5002 {
5003 x = apply_distributive_law
5004 (gen_binary (AND, mode,
8079805d
RK		 5005 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5006 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
230d793d
RS		 5007
5008 if (GET_CODE (x) != IOR)
8079805d 5009 return x;
230d793d
RS		 5010 }
5011
8079805d 5012 if (GET_CODE (op1) == AND)
230d793d
RS		 5013 {
5014 x = apply_distributive_law
5015 (gen_binary (AND, mode,
8079805d
RK		 5016 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5017 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
230d793d
RS		 5018
5019 if (GET_CODE (x) != IOR)
8079805d 5020 return x;
230d793d
RS		 5021 }
5022
5023 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5024 mode size to (rotate A CX). */
5025
8079805d
RK		 5026 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5027 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5028 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5029 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5030 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5031 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
230d793d 5032 == GET_MODE_BITSIZE (mode)))
38a448ca
RH		 5033 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5034 (GET_CODE (op0) == ASHIFT
5035 ? XEXP (op0, 1) : XEXP (op1, 1)));
230d793d 5036
71923da7
RK		 5037 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5038 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5039 does not affect any of the bits in OP1, it can really be done
5040 as a PLUS and we can associate. We do this by seeing if OP1
5041 can be safely shifted left C bits. */
5042 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5043 && GET_CODE (XEXP (op0, 0)) == PLUS
5044 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5045 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5046 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5047 {
5048 int count = INTVAL (XEXP (op0, 1));
5049 HOST_WIDE_INT mask = INTVAL (op1) << count;
5050
5051 if (mask >> count == INTVAL (op1)
5052 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5053 {
5054 SUBST (XEXP (XEXP (op0, 0), 1),
5055 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5056 return op0;
5057 }
5058 }
230d793d
RS		 5059 break;
5060
5061 case XOR:
5062 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5063 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5064 (NOT y). */
5065 {
5066 int num_negated = 0;
230d793d 5067
8079805d
RK		 5068 if (GET_CODE (op0) == NOT)
5069 num_negated++, op0 = XEXP (op0, 0);
5070 if (GET_CODE (op1) == NOT)
5071 num_negated++, op1 = XEXP (op1, 0);
230d793d
RS		 5072
5073 if (num_negated == 2)
5074 {
8079805d
RK		 5075 SUBST (XEXP (x, 0), op0);
5076 SUBST (XEXP (x, 1), op1);
230d793d
RS		 5077 }
5078 else if (num_negated == 1)
0c1c8ea6 5079 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
230d793d
RS		 5080 }
5081
5082 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5083 correspond to a machine insn or result in further simplifications
5084 if B is a constant. */
5085
8079805d
RK		 5086 if (GET_CODE (op0) == AND
5087 && rtx_equal_p (XEXP (op0, 1), op1)
5088 && ! side_effects_p (op1))
0c1c8ea6
RK		 5089 return gen_binary (AND, mode,
5090 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
8079805d 5091 op1);
230d793d 5092
8079805d
RK		 5093 else if (GET_CODE (op0) == AND
5094 && rtx_equal_p (XEXP (op0, 0), op1)
5095 && ! side_effects_p (op1))
0c1c8ea6
RK		 5096 return gen_binary (AND, mode,
5097 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
8079805d 5098 op1);
230d793d 5099
230d793d 5100 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
0802d516
RK		 5101 comparison if STORE_FLAG_VALUE is 1. */
5102 if (STORE_FLAG_VALUE == 1
5103 && op1 == const1_rtx
8079805d
RK		 5104 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5105 && reversible_comparison_p (op0))
5106 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5107 mode, XEXP (op0, 0), XEXP (op0, 1));
500c518b
RK		 5108
5109 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5110 is (lt foo (const_int 0)), so we can perform the above
0802d516 5111 simplification if STORE_FLAG_VALUE is 1. */
500c518b 5112
0802d516
RK		 5113 if (STORE_FLAG_VALUE == 1
5114 && op1 == const1_rtx
8079805d
RK		 5115 && GET_CODE (op0) == LSHIFTRT
5116 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5117 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5118 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
230d793d
RS		 5119
5120 /* (xor (comparison foo bar) (const_int sign-bit))
5121 when STORE_FLAG_VALUE is the sign bit. */
5f4f0e22 5122 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
0802d516 5123 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
e51712db 5124 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
8079805d
RK		 5125 && op1 == const_true_rtx
5126 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5127 && reversible_comparison_p (op0))
5128 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5129 mode, XEXP (op0, 0), XEXP (op0, 1));
230d793d 5130 break;
e9a25f70
JL		 5131
5132 default:
5133 abort ();
230d793d
RS		 5134 }
5135
5136 return x;
5137}
5138\f
5139/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5140 operations" because they can be replaced with two more basic operations.
5141 ZERO_EXTEND is also considered "compound" because it can be replaced with
5142 an AND operation, which is simpler, though only one operation.
5143
5144 The function expand_compound_operation is called with an rtx expression
5145 and will convert it to the appropriate shifts and AND operations,
5146 simplifying at each stage.
5147
5148 The function make_compound_operation is called to convert an expression
5149 consisting of shifts and ANDs into the equivalent compound expression.
5150 It is the inverse of this function, loosely speaking. */
5151
5152static rtx
5153expand_compound_operation (x)
5154 rtx x;
5155{
5156 int pos = 0, len;
5157 int unsignedp = 0;
5158 int modewidth;
5159 rtx tem;
5160
5161 switch (GET_CODE (x))
5162 {
5163 case ZERO_EXTEND:
5164 unsignedp = 1;
5165 case SIGN_EXTEND:
75473182
RS		 5166 /* We can't necessarily use a const_int for a multiword mode;
5167 it depends on implicitly extending the value.
5168 Since we don't know the right way to extend it,
5169 we can't tell whether the implicit way is right.
5170
5171 Even for a mode that is no wider than a const_int,
5172 we can't win, because we need to sign extend one of its bits through
5173 the rest of it, and we don't know which bit. */
230d793d 5174 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
75473182 5175 return x;
230d793d 5176
8079805d
RK		 5177 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5178 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5179 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5180 reloaded. If not for that, MEM's would very rarely be safe.
5181
5182 Reject MODEs bigger than a word, because we might not be able
5183 to reference a two-register group starting with an arbitrary register
5184 (and currently gen_lowpart might crash for a SUBREG). */
5185
5186 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
230d793d
RS		 5187 return x;
5188
5189 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5190 /* If the inner object has VOIDmode (the only way this can happen
5191 is if it is a ASM_OPERANDS), we can't do anything since we don't
5192 know how much masking to do. */
5193 if (len == 0)
5194 return x;
5195
5196 break;
5197
5198 case ZERO_EXTRACT:
5199 unsignedp = 1;
5200 case SIGN_EXTRACT:
5201 /* If the operand is a CLOBBER, just return it. */
5202 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5203 return XEXP (x, 0);
5204
5205 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5206 || GET_CODE (XEXP (x, 2)) != CONST_INT
5207 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5208 return x;
5209
5210 len = INTVAL (XEXP (x, 1));
5211 pos = INTVAL (XEXP (x, 2));
5212
5213 /* If this goes outside the object being extracted, replace the object
5214 with a (use (mem ...)) construct that only combine understands
5215 and is used only for this purpose. */
5216 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
38a448ca 5217 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
230d793d 5218
f76b9db2
ILT		 5219 if (BITS_BIG_ENDIAN)
5220 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5221
230d793d
RS		 5222 break;
5223
5224 default:
5225 return x;
5226 }
5227
0f13a422
ILT		 5228 /* We can optimize some special cases of ZERO_EXTEND. */
5229 if (GET_CODE (x) == ZERO_EXTEND)
5230 {
5231 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5232 know that the last value didn't have any inappropriate bits
5233 set. */
5234 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5235 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5236 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5237 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5238 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5239 return XEXP (XEXP (x, 0), 0);
5240
5241 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5242 if (GET_CODE (XEXP (x, 0)) == SUBREG
5243 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5244 && subreg_lowpart_p (XEXP (x, 0))
5245 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5246 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
fcc60894 5247 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
0f13a422
ILT		 5248 return SUBREG_REG (XEXP (x, 0));
5249
5250 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5251 is a comparison and STORE_FLAG_VALUE permits. This is like
5252 the first case, but it works even when GET_MODE (x) is larger
5253 than HOST_WIDE_INT. */
5254 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5255 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5256 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5257 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5258 <= HOST_BITS_PER_WIDE_INT)
5259 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5260 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5261 return XEXP (XEXP (x, 0), 0);
5262
5263 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5264 if (GET_CODE (XEXP (x, 0)) == SUBREG
5265 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5266 && subreg_lowpart_p (XEXP (x, 0))
5267 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5268 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5269 <= HOST_BITS_PER_WIDE_INT)
5270 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5271 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5272 return SUBREG_REG (XEXP (x, 0));
5273
5274 /* If sign extension is cheaper than zero extension, then use it
5275 if we know that no extraneous bits are set, and that the high
5276 bit is not set. */
5277 if (flag_expensive_optimizations
5278 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5279 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5280 & ~ (((unsigned HOST_WIDE_INT)
5281 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5282 >> 1))
5283 == 0))
5284 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5285 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5286 <= HOST_BITS_PER_WIDE_INT)
5287 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5288 & ~ (((unsigned HOST_WIDE_INT)
5289 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5290 >> 1))
5291 == 0))))
5292 {
38a448ca 5293 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
0f13a422
ILT		 5294
5295 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5296 return expand_compound_operation (temp);
5297 }
5298 }
5299
230d793d
RS		 5300 /* If we reach here, we want to return a pair of shifts. The inner
5301 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5302 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5303 logical depending on the value of UNSIGNEDP.
5304
5305 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5306 converted into an AND of a shift.
5307
5308 We must check for the case where the left shift would have a negative
5309 count. This can happen in a case like (x >> 31) & 255 on machines
5310 that can't shift by a constant. On those machines, we would first
5311 combine the shift with the AND to produce a variable-position
5312 extraction. Then the constant of 31 would be substituted in to produce
5313 a such a position. */
5314
5315 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5316 if (modewidth >= pos - len)
5f4f0e22 5317 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
230d793d 5318 GET_MODE (x),
5f4f0e22
CH		 5319 simplify_shift_const (NULL_RTX, ASHIFT,
5320 GET_MODE (x),
230d793d
RS		 5321 XEXP (x, 0),
5322 modewidth - pos - len),
5323 modewidth - len);
5324
5f4f0e22
CH		 5325 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5326 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5327 simplify_shift_const (NULL_RTX, LSHIFTRT,
230d793d
RS		 5328 GET_MODE (x),
5329 XEXP (x, 0), pos),
5f4f0e22 5330 ((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5331 else
5332 /* Any other cases we can't handle. */
5333 return x;
5334
5335
5336 /* If we couldn't do this for some reason, return the original
5337 expression. */
5338 if (GET_CODE (tem) == CLOBBER)
5339 return x;
5340
5341 return tem;
5342}
5343\f
5344/* X is a SET which contains an assignment of one object into
5345 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5346 or certain SUBREGS). If possible, convert it into a series of
5347 logical operations.
5348
5349 We half-heartedly support variable positions, but do not at all
5350 support variable lengths. */
5351
5352static rtx
5353expand_field_assignment (x)
5354 rtx x;
5355{
5356 rtx inner;
0f41302f 5357 rtx pos; /* Always counts from low bit. */
230d793d
RS		 5358 int len;
5359 rtx mask;
5360 enum machine_mode compute_mode;
5361
5362 /* Loop until we find something we can't simplify. */
5363 while (1)
5364 {
5365 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5366 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5367 {
5368 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5369 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4d9cfc7b 5370 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
230d793d
RS		 5371 }
5372 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5373 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5374 {
5375 inner = XEXP (SET_DEST (x), 0);
5376 len = INTVAL (XEXP (SET_DEST (x), 1));
5377 pos = XEXP (SET_DEST (x), 2);
5378
5379 /* If the position is constant and spans the width of INNER,
5380 surround INNER with a USE to indicate this. */
5381 if (GET_CODE (pos) == CONST_INT
5382 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
38a448ca 5383 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
230d793d 5384
f76b9db2
ILT		 5385 if (BITS_BIG_ENDIAN)
5386 {
5387 if (GET_CODE (pos) == CONST_INT)
5388 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5389 - INTVAL (pos));
5390 else if (GET_CODE (pos) == MINUS
5391 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5392 && (INTVAL (XEXP (pos, 1))
5393 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5394 /* If position is ADJUST - X, new position is X. */
5395 pos = XEXP (pos, 0);
5396 else
5397 pos = gen_binary (MINUS, GET_MODE (pos),
5398 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5399 - len),
5400 pos);
5401 }
230d793d
RS		 5402 }
5403
5404 /* A SUBREG between two modes that occupy the same numbers of words
5405 can be done by moving the SUBREG to the source. */
5406 else if (GET_CODE (SET_DEST (x)) == SUBREG
5407 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5408 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5409 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5410 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5411 {
38a448ca
RH		 5412 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5413 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5414 SET_SRC (x)));
230d793d
RS		 5415 continue;
5416 }
5417 else
5418 break;
5419
5420 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5421 inner = SUBREG_REG (inner);
5422
5423 compute_mode = GET_MODE (inner);
5424
861556b4
RH		 5425 /* Don't attempt bitwise arithmetic on non-integral modes. */
5426 if (! INTEGRAL_MODE_P (compute_mode))
5427 {
5428 enum machine_mode imode;
5429
5430 /* Something is probably seriously wrong if this matches. */
5431 if (! FLOAT_MODE_P (compute_mode))
5432 break;
5433
5434 /* Try to find an integral mode to pun with. */
5435 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5436 if (imode == BLKmode)
5437 break;
5438
5439 compute_mode = imode;
5440 inner = gen_lowpart_for_combine (imode, inner);
5441 }
5442
230d793d 5443 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5f4f0e22
CH		 5444 if (len < HOST_BITS_PER_WIDE_INT)
5445 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
230d793d
RS		 5446 else
5447 break;
5448
5449 /* Now compute the equivalent expression. Make a copy of INNER
5450 for the SET_DEST in case it is a MEM into which we will substitute;
5451 we don't want shared RTL in that case. */
38a448ca
RH		 5452 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5453 gen_binary (IOR, compute_mode,
5454 gen_binary (AND, compute_mode,
5455 gen_unary (NOT, compute_mode,
5456 compute_mode,
5457 gen_binary (ASHIFT,
5458 compute_mode,
5459 mask, pos)),
5460 inner),
5461 gen_binary (ASHIFT, compute_mode,
5462 gen_binary (AND, compute_mode,
5463 gen_lowpart_for_combine
5464 (compute_mode,
5465 SET_SRC (x)),
5466 mask),
5467 pos)));
230d793d
RS		 5468 }
5469
5470 return x;
5471}
5472\f
8999a12e
RK		 5473/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5474 it is an RTX that represents a variable starting position; otherwise,
5475 POS is the (constant) starting bit position (counted from the LSB).
230d793d
RS		 5476
5477 INNER may be a USE. This will occur when we started with a bitfield
5478 that went outside the boundary of the object in memory, which is
5479 allowed on most machines. To isolate this case, we produce a USE
5480 whose mode is wide enough and surround the MEM with it. The only
5481 code that understands the USE is this routine. If it is not removed,
5482 it will cause the resulting insn not to match.
5483
5484 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5485 signed reference.
5486
5487 IN_DEST is non-zero if this is a reference in the destination of a
5488 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5489 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5490 be used.
5491
5492 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5493 ZERO_EXTRACT should be built even for bits starting at bit 0.
5494
76184def
DE		 5495 MODE is the desired mode of the result (if IN_DEST == 0).
5496
5497 The result is an RTX for the extraction or NULL_RTX if the target
5498 can't handle it. */
230d793d
RS		 5499
5500static rtx
5501make_extraction (mode, inner, pos, pos_rtx, len,
5502 unsignedp, in_dest, in_compare)
5503 enum machine_mode mode;
5504 rtx inner;
5505 int pos;
5506 rtx pos_rtx;
5507 int len;
5508 int unsignedp;
5509 int in_dest, in_compare;
5510{
94b4b17a
RS		 5511 /* This mode describes the size of the storage area
5512 to fetch the overall value from. Within that, we
5513 ignore the POS lowest bits, etc. */
230d793d
RS		 5514 enum machine_mode is_mode = GET_MODE (inner);
5515 enum machine_mode inner_mode;
d7cd794f
RK		 5516 enum machine_mode wanted_inner_mode = byte_mode;
5517 enum machine_mode wanted_inner_reg_mode = word_mode;
230d793d
RS		 5518 enum machine_mode pos_mode = word_mode;
5519 enum machine_mode extraction_mode = word_mode;
5520 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5521 int spans_byte = 0;
5522 rtx new = 0;
8999a12e 5523 rtx orig_pos_rtx = pos_rtx;
6139ff20 5524 int orig_pos;
230d793d
RS		 5525
5526 /* Get some information about INNER and get the innermost object. */
5527 if (GET_CODE (inner) == USE)
94b4b17a 5528 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
230d793d
RS		 5529 /* We don't need to adjust the position because we set up the USE
5530 to pretend that it was a full-word object. */
5531 spans_byte = 1, inner = XEXP (inner, 0);
5532 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
94b4b17a
RS		 5533 {
5534 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5535 consider just the QI as the memory to extract from.
5536 The subreg adds or removes high bits; its mode is
5537 irrelevant to the meaning of this extraction,
5538 since POS and LEN count from the lsb. */
5539 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5540 is_mode = GET_MODE (SUBREG_REG (inner));
5541 inner = SUBREG_REG (inner);
5542 }
230d793d
RS		 5543
5544 inner_mode = GET_MODE (inner);
5545
5546 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
8999a12e 5547 pos = INTVAL (pos_rtx), pos_rtx = 0;
230d793d
RS		 5548
5549 /* See if this can be done without an extraction. We never can if the
5550 width of the field is not the same as that of some integer mode. For
5551 registers, we can only avoid the extraction if the position is at the
5552 low-order bit and this is either not in the destination or we have the
5553 appropriate STRICT_LOW_PART operation available.
5554
5555 For MEM, we can avoid an extract if the field starts on an appropriate
5556 boundary and we can change the mode of the memory reference. However,
5557 we cannot directly access the MEM if we have a USE and the underlying
5558 MEM is not TMODE. This combination means that MEM was being used in a
5559 context where bits outside its mode were being referenced; that is only
5560 valid in bit-field insns. */
5561
5562 if (tmode != BLKmode
5563 && ! (spans_byte && inner_mode != tmode)
4d9cfc7b
RK		 5564 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5565 && GET_CODE (inner) != MEM
230d793d 5566 && (! in_dest
df62f951
RK		 5567 || (GET_CODE (inner) == REG
5568 && (movstrict_optab->handlers[(int) tmode].insn_code
5569 != CODE_FOR_nothing))))
8999a12e 5570 || (GET_CODE (inner) == MEM && pos_rtx == 0
dfbe1b2f
RK		 5571 && (pos
5572 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5573 : BITS_PER_UNIT)) == 0
230d793d
RS		 5574 /* We can't do this if we are widening INNER_MODE (it
5575 may not be aligned, for one thing). */
5576 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5577 && (inner_mode == tmode
5578 || (! mode_dependent_address_p (XEXP (inner, 0))
5579 && ! MEM_VOLATILE_P (inner))))))
5580 {
230d793d
RS		 5581 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5582 field. If the original and current mode are the same, we need not
5583 adjust the offset. Otherwise, we do if bytes big endian.
5584
4d9cfc7b
RK		 5585 If INNER is not a MEM, get a piece consisting of just the field
5586 of interest (in this case POS % BITS_PER_WORD must be 0). */
230d793d
RS		 5587
5588 if (GET_CODE (inner) == MEM)
5589 {
94b4b17a
RS		 5590 int offset;
5591 /* POS counts from lsb, but make OFFSET count in memory order. */
5592 if (BYTES_BIG_ENDIAN)
5593 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5594 else
5595 offset = pos / BITS_PER_UNIT;
230d793d 5596
38a448ca 5597 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5598 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5599 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5600 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5601 }
df62f951 5602 else if (GET_CODE (inner) == REG)
c0d3ac4d
RK		 5603 {
5604 /* We can't call gen_lowpart_for_combine here since we always want
5605 a SUBREG and it would sometimes return a new hard register. */
5606 if (tmode != inner_mode)
38a448ca
RH		 5607 new = gen_rtx_SUBREG (tmode, inner,
5608 (WORDS_BIG_ENDIAN
5609 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5610 ? (((GET_MODE_SIZE (inner_mode)
5611 - GET_MODE_SIZE (tmode))
5612 / UNITS_PER_WORD)
5613 - pos / BITS_PER_WORD)
5614 : pos / BITS_PER_WORD));
c0d3ac4d
RK		 5615 else
5616 new = inner;
5617 }
230d793d 5618 else
6139ff20
RK		 5619 new = force_to_mode (inner, tmode,
5620 len >= HOST_BITS_PER_WIDE_INT
5621 ? GET_MODE_MASK (tmode)
5622 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 5623 NULL_RTX, 0);
230d793d
RS		 5624
5625 /* If this extraction is going into the destination of a SET,
5626 make a STRICT_LOW_PART unless we made a MEM. */
5627
5628 if (in_dest)
5629 return (GET_CODE (new) == MEM ? new
77fa0940 5630 : (GET_CODE (new) != SUBREG
38a448ca 5631 ? gen_rtx_CLOBBER (tmode, const0_rtx)
77fa0940 5632 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
230d793d
RS		 5633
5634 /* Otherwise, sign- or zero-extend unless we already are in the
5635 proper mode. */
5636
5637 return (mode == tmode ? new
5638 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5639 mode, new));
5640 }
5641
cc471082
RS		 5642 /* Unless this is a COMPARE or we have a funny memory reference,
5643 don't do anything with zero-extending field extracts starting at
5644 the low-order bit since they are simple AND operations. */
8999a12e
RK		 5645 if (pos_rtx == 0 && pos == 0 && ! in_dest
5646 && ! in_compare && ! spans_byte && unsignedp)
230d793d
RS		 5647 return 0;
5648
e7373556
RK		 5649 /* Unless we are allowed to span bytes, reject this if we would be
5650 spanning bytes or if the position is not a constant and the length
5651 is not 1. In all other cases, we would only be going outside
5652 out object in cases when an original shift would have been
5653 undefined. */
5654 if (! spans_byte
5655 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5656 || (pos_rtx != 0 && len != 1)))
5657 return 0;
5658
d7cd794f 5659 /* Get the mode to use should INNER not be a MEM, the mode for the position,
230d793d
RS		 5660 and the mode for the result. */
5661#ifdef HAVE_insv
5662 if (in_dest)
5663 {
0d8e55d8
JL		 5664 wanted_inner_reg_mode
5665 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode
5666 ? word_mode
5667 : insn_operand_mode[(int) CODE_FOR_insv][0]);
5668 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode
5669 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]);
5670 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode
5671 ? word_mode
5672 : insn_operand_mode[(int) CODE_FOR_insv][3]);
230d793d
RS		 5673 }
5674#endif
5675
5676#ifdef HAVE_extzv
5677 if (! in_dest && unsignedp)
5678 {
0d8e55d8
JL		 5679 wanted_inner_reg_mode
5680 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode
5681 ? word_mode
5682 : insn_operand_mode[(int) CODE_FOR_extzv][1]);
5683 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode
5684 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]);
5685 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode
5686 ? word_mode
5687 : insn_operand_mode[(int) CODE_FOR_extzv][0]);
230d793d
RS		 5688 }
5689#endif
5690
5691#ifdef HAVE_extv
5692 if (! in_dest && ! unsignedp)
5693 {
0d8e55d8
JL		 5694 wanted_inner_reg_mode
5695 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode
5696 ? word_mode
5697 : insn_operand_mode[(int) CODE_FOR_extv][1]);
5698 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode
5699 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]);
5700 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode
5701 ? word_mode
5702 : insn_operand_mode[(int) CODE_FOR_extv][0]);
230d793d
RS		 5703 }
5704#endif
5705
5706 /* Never narrow an object, since that might not be safe. */
5707
5708 if (mode != VOIDmode
5709 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5710 extraction_mode = mode;
5711
5712 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5713 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5714 pos_mode = GET_MODE (pos_rtx);
5715
d7cd794f
RK		 5716 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5717 if we have to change the mode of memory and cannot, the desired mode is
5718 EXTRACTION_MODE. */
5719 if (GET_CODE (inner) != MEM)
5720 wanted_inner_mode = wanted_inner_reg_mode;
5721 else if (inner_mode != wanted_inner_mode
5722 && (mode_dependent_address_p (XEXP (inner, 0))
5723 || MEM_VOLATILE_P (inner)))
5724 wanted_inner_mode = extraction_mode;
230d793d 5725
6139ff20
RK		 5726 orig_pos = pos;
5727
f76b9db2
ILT		 5728 if (BITS_BIG_ENDIAN)
5729 {
cf54c2cd
DE		 5730 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5731 BITS_BIG_ENDIAN style. If position is constant, compute new
5732 position. Otherwise, build subtraction.
5733 Note that POS is relative to the mode of the original argument.
5734 If it's a MEM we need to recompute POS relative to that.
5735 However, if we're extracting from (or inserting into) a register,
5736 we want to recompute POS relative to wanted_inner_mode. */
5737 int width = (GET_CODE (inner) == MEM
5738 ? GET_MODE_BITSIZE (is_mode)
5739 : GET_MODE_BITSIZE (wanted_inner_mode));
5740
f76b9db2 5741 if (pos_rtx == 0)
cf54c2cd 5742 pos = width - len - pos;
f76b9db2
ILT		 5743 else
5744 pos_rtx
5745 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
cf54c2cd
DE		 5746 GEN_INT (width - len), pos_rtx);
5747 /* POS may be less than 0 now, but we check for that below.
5748 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
f76b9db2 5749 }
230d793d
RS		 5750
5751 /* If INNER has a wider mode, make it smaller. If this is a constant
5752 extract, try to adjust the byte to point to the byte containing
5753 the value. */
d7cd794f
RK		 5754 if (wanted_inner_mode != VOIDmode
5755 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
230d793d 5756 && ((GET_CODE (inner) == MEM
d7cd794f 5757 && (inner_mode == wanted_inner_mode
230d793d
RS		 5758 || (! mode_dependent_address_p (XEXP (inner, 0))
5759 && ! MEM_VOLATILE_P (inner))))))
5760 {
5761 int offset = 0;
5762
5763 /* The computations below will be correct if the machine is big
5764 endian in both bits and bytes or little endian in bits and bytes.
5765 If it is mixed, we must adjust. */
5766
230d793d 5767 /* If bytes are big endian and we had a paradoxical SUBREG, we must
0f41302f 5768 adjust OFFSET to compensate. */
f76b9db2
ILT		 5769 if (BYTES_BIG_ENDIAN
5770 && ! spans_byte
230d793d
RS		 5771 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5772 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
230d793d
RS		 5773
5774 /* If this is a constant position, we can move to the desired byte. */
8999a12e 5775 if (pos_rtx == 0)
230d793d
RS		 5776 {
5777 offset += pos / BITS_PER_UNIT;
d7cd794f 5778 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
230d793d
RS		 5779 }
5780
f76b9db2
ILT		 5781 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5782 && ! spans_byte
d7cd794f 5783 && is_mode != wanted_inner_mode)
c6b3f1f2 5784 offset = (GET_MODE_SIZE (is_mode)
d7cd794f 5785 - GET_MODE_SIZE (wanted_inner_mode) - offset);
c6b3f1f2 5786
d7cd794f 5787 if (offset != 0 || inner_mode != wanted_inner_mode)
230d793d 5788 {
38a448ca
RH		 5789 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5790 plus_constant (XEXP (inner, 0), offset));
230d793d
RS		 5791 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5792 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5793 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5794 inner = newmem;
5795 }
5796 }
5797
9e74dc41
RK		 5798 /* If INNER is not memory, we can always get it into the proper mode. If we
5799 are changing its mode, POS must be a constant and smaller than the size
5800 of the new mode. */
230d793d 5801 else if (GET_CODE (inner) != MEM)
9e74dc41
RK		 5802 {
5803 if (GET_MODE (inner) != wanted_inner_mode
5804 && (pos_rtx != 0
5805 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5806 return 0;
5807
5808 inner = force_to_mode (inner, wanted_inner_mode,
5809 pos_rtx
5810 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5811 ? GET_MODE_MASK (wanted_inner_mode)
5812 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5813 NULL_RTX, 0);
5814 }
230d793d
RS		 5815
5816 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5817 have to zero extend. Otherwise, we can just use a SUBREG. */
8999a12e 5818 if (pos_rtx != 0
230d793d
RS		 5819 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5820 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
8999a12e 5821 else if (pos_rtx != 0
230d793d
RS		 5822 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5823 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5824
8999a12e
RK		 5825 /* Make POS_RTX unless we already have it and it is correct. If we don't
5826 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
0f41302f 5827 be a CONST_INT. */
8999a12e
RK		 5828 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5829 pos_rtx = orig_pos_rtx;
5830
5831 else if (pos_rtx == 0)
5f4f0e22 5832 pos_rtx = GEN_INT (pos);
230d793d
RS		 5833
5834 /* Make the required operation. See if we can use existing rtx. */
5835 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5f4f0e22 5836 extraction_mode, inner, GEN_INT (len), pos_rtx);
230d793d
RS		 5837 if (! in_dest)
5838 new = gen_lowpart_for_combine (mode, new);
5839
5840 return new;
5841}
5842\f
71923da7
RK		 5843/* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5844 with any other operations in X. Return X without that shift if so. */
5845
5846static rtx
5847extract_left_shift (x, count)
5848 rtx x;
5849 int count;
5850{
5851 enum rtx_code code = GET_CODE (x);
5852 enum machine_mode mode = GET_MODE (x);
5853 rtx tem;
5854
5855 switch (code)
5856 {
5857 case ASHIFT:
5858 /* This is the shift itself. If it is wide enough, we will return
5859 either the value being shifted if the shift count is equal to
5860 COUNT or a shift for the difference. */
5861 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5862 && INTVAL (XEXP (x, 1)) >= count)
5863 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5864 INTVAL (XEXP (x, 1)) - count);
5865 break;
5866
5867 case NEG: case NOT:
5868 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
0c1c8ea6 5869 return gen_unary (code, mode, mode, tem);
71923da7
RK		 5870
5871 break;
5872
5873 case PLUS: case IOR: case XOR: case AND:
5874 /* If we can safely shift this constant and we find the inner shift,
5875 make a new operation. */
5876 if (GET_CODE (XEXP (x,1)) == CONST_INT
b729186a 5877 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
71923da7
RK		 5878 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5879 return gen_binary (code, mode, tem,
5880 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5881
5882 break;
e9a25f70
JL		 5883
5884 default:
5885 break;
71923da7
RK		 5886 }
5887
5888 return 0;
5889}
5890\f
230d793d
RS		 5891/* Look at the expression rooted at X. Look for expressions
5892 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5893 Form these expressions.
5894
5895 Return the new rtx, usually just X.
5896
5897 Also, for machines like the Vax that don't have logical shift insns,
5898 try to convert logical to arithmetic shift operations in cases where
5899 they are equivalent. This undoes the canonicalizations to logical
5900 shifts done elsewhere.
5901
5902 We try, as much as possible, to re-use rtl expressions to save memory.
5903
5904 IN_CODE says what kind of expression we are processing. Normally, it is
42495ca0
RK		 5905 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5906 being kludges), it is MEM. When processing the arguments of a comparison
230d793d
RS		 5907 or a COMPARE against zero, it is COMPARE. */
5908
5909static rtx
5910make_compound_operation (x, in_code)
5911 rtx x;
5912 enum rtx_code in_code;
5913{
5914 enum rtx_code code = GET_CODE (x);
5915 enum machine_mode mode = GET_MODE (x);
5916 int mode_width = GET_MODE_BITSIZE (mode);
71923da7 5917 rtx rhs, lhs;
230d793d 5918 enum rtx_code next_code;
f24ad0e4 5919 int i;
230d793d 5920 rtx new = 0;
280f58ba 5921 rtx tem;
230d793d
RS		 5922 char *fmt;
5923
5924 /* Select the code to be used in recursive calls. Once we are inside an
5925 address, we stay there. If we have a comparison, set to COMPARE,
5926 but once inside, go back to our default of SET. */
5927
42495ca0 5928 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
230d793d
RS		 5929 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5930 && XEXP (x, 1) == const0_rtx) ? COMPARE
5931 : in_code == COMPARE ? SET : in_code);
5932
5933 /* Process depending on the code of this operation. If NEW is set
5934 non-zero, it will be returned. */
5935
5936 switch (code)
5937 {
5938 case ASHIFT:
230d793d
RS		 5939 /* Convert shifts by constants into multiplications if inside
5940 an address. */
5941 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 5942 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
230d793d 5943 && INTVAL (XEXP (x, 1)) >= 0)
280f58ba
RK		 5944 {
5945 new = make_compound_operation (XEXP (x, 0), next_code);
5946 new = gen_rtx_combine (MULT, mode, new,
5947 GEN_INT ((HOST_WIDE_INT) 1
5948 << INTVAL (XEXP (x, 1))));
5949 }
230d793d
RS		 5950 break;
5951
5952 case AND:
5953 /* If the second operand is not a constant, we can't do anything
5954 with it. */
5955 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5956 break;
5957
5958 /* If the constant is a power of two minus one and the first operand
5959 is a logical right shift, make an extraction. */
5960 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5961 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5962 {
5963 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5964 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5965 0, in_code == COMPARE);
5966 }
dfbe1b2f 5967
230d793d
RS		 5968 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5969 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5970 && subreg_lowpart_p (XEXP (x, 0))
5971 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5972 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 5973 {
5974 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5975 next_code);
2f99f437 5976 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
280f58ba
RK		 5977 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5978 0, in_code == COMPARE);
5979 }
45620ed4 5980 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
c2f9f64e
JW		 5981 else if ((GET_CODE (XEXP (x, 0)) == XOR
5982 || GET_CODE (XEXP (x, 0)) == IOR)
5983 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5984 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5985 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5986 {
5987 /* Apply the distributive law, and then try to make extractions. */
5988 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
38a448ca
RH		 5989 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5990 XEXP (x, 1)),
5991 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5992 XEXP (x, 1)));
c2f9f64e
JW		 5993 new = make_compound_operation (new, in_code);
5994 }
a7c99304
RK		 5995
5996 /* If we are have (and (rotate X C) M) and C is larger than the number
5997 of bits in M, this is an extraction. */
5998
5999 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6000 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6001 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6002 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
280f58ba
RK		 6003 {
6004 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6005 new = make_extraction (mode, new,
6006 (GET_MODE_BITSIZE (mode)
6007 - INTVAL (XEXP (XEXP (x, 0), 1))),
6008 NULL_RTX, i, 1, 0, in_code == COMPARE);
6009 }
a7c99304
RK		 6010
6011 /* On machines without logical shifts, if the operand of the AND is
230d793d
RS		 6012 a logical shift and our mask turns off all the propagated sign
6013 bits, we can replace the logical shift with an arithmetic shift. */
d0ab8cd3
RK		 6014 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6015 && (lshr_optab->handlers[(int) mode].insn_code
6016 == CODE_FOR_nothing)
230d793d
RS		 6017 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6018 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6019 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5f4f0e22
CH		 6020 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6021 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 6022 {
5f4f0e22 6023 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 6024
6025 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6026 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6027 SUBST (XEXP (x, 0),
280f58ba
RK		 6028 gen_rtx_combine (ASHIFTRT, mode,
6029 make_compound_operation (XEXP (XEXP (x, 0), 0),
6030 next_code),
230d793d
RS		 6031 XEXP (XEXP (x, 0), 1)));
6032 }
6033
6034 /* If the constant is one less than a power of two, this might be
6035 representable by an extraction even if no shift is present.
6036 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6037 we are in a COMPARE. */
6038 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
280f58ba
RK		 6039 new = make_extraction (mode,
6040 make_compound_operation (XEXP (x, 0),
6041 next_code),
6042 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
230d793d
RS		 6043
6044 /* If we are in a comparison and this is an AND with a power of two,
6045 convert this into the appropriate bit extract. */
6046 else if (in_code == COMPARE
6047 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
280f58ba
RK		 6048 new = make_extraction (mode,
6049 make_compound_operation (XEXP (x, 0),
6050 next_code),
6051 i, NULL_RTX, 1, 1, 0, 1);
230d793d
RS		 6052
6053 break;
6054
6055 case LSHIFTRT:
6056 /* If the sign bit is known to be zero, replace this with an
6057 arithmetic shift. */
d0ab8cd3
RK		 6058 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6059 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5f4f0e22 6060 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 6061 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
230d793d 6062 {
280f58ba
RK		 6063 new = gen_rtx_combine (ASHIFTRT, mode,
6064 make_compound_operation (XEXP (x, 0),
6065 next_code),
6066 XEXP (x, 1));
230d793d
RS		 6067 break;
6068 }
6069
0f41302f 6070 /* ... fall through ... */
230d793d
RS		 6071
6072 case ASHIFTRT:
71923da7
RK		 6073 lhs = XEXP (x, 0);
6074 rhs = XEXP (x, 1);
6075
230d793d
RS		 6076 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6077 this is a SIGN_EXTRACT. */
71923da7
RK		 6078 if (GET_CODE (rhs) == CONST_INT
6079 && GET_CODE (lhs) == ASHIFT
6080 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6081 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
280f58ba 6082 {
71923da7 6083 new = make_compound_operation (XEXP (lhs, 0), next_code);
280f58ba 6084 new = make_extraction (mode, new,
71923da7
RK		 6085 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6086 NULL_RTX, mode_width - INTVAL (rhs),
d0ab8cd3
RK		 6087 code == LSHIFTRT, 0, in_code == COMPARE);
6088 }
6089
71923da7
RK		 6090 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6091 If so, try to merge the shifts into a SIGN_EXTEND. We could
6092 also do this for some cases of SIGN_EXTRACT, but it doesn't
6093 seem worth the effort; the case checked for occurs on Alpha. */
6094
6095 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6096 && ! (GET_CODE (lhs) == SUBREG
6097 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6098 && GET_CODE (rhs) == CONST_INT
6099 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6100 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6101 new = make_extraction (mode, make_compound_operation (new, next_code),
6102 0, NULL_RTX, mode_width - INTVAL (rhs),
6103 code == LSHIFTRT, 0, in_code == COMPARE);
6104
230d793d 6105 break;
280f58ba
RK		 6106
6107 case SUBREG:
6108 /* Call ourselves recursively on the inner expression. If we are
6109 narrowing the object and it has a different RTL code from
6110 what it originally did, do this SUBREG as a force_to_mode. */
6111
0a5cbff6 6112 tem = make_compound_operation (SUBREG_REG (x), in_code);
280f58ba
RK		 6113 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6114 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6115 && subreg_lowpart_p (x))
0a5cbff6
RK		 6116 {
6117 rtx newer = force_to_mode (tem, mode,
e3d616e3 6118 GET_MODE_MASK (mode), NULL_RTX, 0);
0a5cbff6
RK		 6119
6120 /* If we have something other than a SUBREG, we might have
6121 done an expansion, so rerun outselves. */
6122 if (GET_CODE (newer) != SUBREG)
6123 newer = make_compound_operation (newer, in_code);
6124
6125 return newer;
6126 }
6f28d3e9
RH		 6127
6128 /* If this is a paradoxical subreg, and the new code is a sign or
6129 zero extension, omit the subreg and widen the extension. If it
6130 is a regular subreg, we can still get rid of the subreg by not
6131 widening so much, or in fact removing the extension entirely. */
6132 if ((GET_CODE (tem) == SIGN_EXTEND
6133 || GET_CODE (tem) == ZERO_EXTEND)
6134 && subreg_lowpart_p (x))
6135 {
6136 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6137 || (GET_MODE_SIZE (mode) >
6138 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6139 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6140 else
6141 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6142 return tem;
6143 }
e9a25f70
JL		 6144 break;
6145
6146 default:
6147 break;
230d793d
RS		 6148 }
6149
6150 if (new)
6151 {
df62f951 6152 x = gen_lowpart_for_combine (mode, new);
230d793d
RS		 6153 code = GET_CODE (x);
6154 }
6155
6156 /* Now recursively process each operand of this operation. */
6157 fmt = GET_RTX_FORMAT (code);
6158 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6159 if (fmt[i] == 'e')
6160 {
6161 new = make_compound_operation (XEXP (x, i), next_code);
6162 SUBST (XEXP (x, i), new);
6163 }
6164
6165 return x;
6166}
6167\f
6168/* Given M see if it is a value that would select a field of bits
6169 within an item, but not the entire word. Return -1 if not.
6170 Otherwise, return the starting position of the field, where 0 is the
6171 low-order bit.
6172
6173 *PLEN is set to the length of the field. */
6174
6175static int
6176get_pos_from_mask (m, plen)
5f4f0e22 6177 unsigned HOST_WIDE_INT m;
230d793d
RS		 6178 int *plen;
6179{
6180 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6181 int pos = exact_log2 (m & - m);
6182
6183 if (pos < 0)
6184 return -1;
6185
6186 /* Now shift off the low-order zero bits and see if we have a power of
6187 two minus 1. */
6188 *plen = exact_log2 ((m >> pos) + 1);
6189
6190 if (*plen <= 0)
6191 return -1;
6192
6193 return pos;
6194}
6195\f
6139ff20
RK		 6196/* See if X can be simplified knowing that we will only refer to it in
6197 MODE and will only refer to those bits that are nonzero in MASK.
6198 If other bits are being computed or if masking operations are done
6199 that select a superset of the bits in MASK, they can sometimes be
6200 ignored.
6201
6202 Return a possibly simplified expression, but always convert X to
6203 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
dfbe1b2f
RK		 6204
6205 Also, if REG is non-zero and X is a register equal in value to REG,
e3d616e3
RK		 6206 replace X with REG.
6207
6208 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6209 are all off in X. This is used when X will be complemented, by either
180b8e4b 6210 NOT, NEG, or XOR. */
dfbe1b2f
RK		 6211
6212static rtx
e3d616e3 6213force_to_mode (x, mode, mask, reg, just_select)
dfbe1b2f
RK		 6214 rtx x;
6215 enum machine_mode mode;
6139ff20 6216 unsigned HOST_WIDE_INT mask;
dfbe1b2f 6217 rtx reg;
e3d616e3 6218 int just_select;
dfbe1b2f
RK		 6219{
6220 enum rtx_code code = GET_CODE (x);
180b8e4b 6221 int next_select = just_select || code == XOR || code == NOT || code == NEG;
ef026f91
RS		 6222 enum machine_mode op_mode;
6223 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6139ff20
RK		 6224 rtx op0, op1, temp;
6225
132d2040
RK		 6226 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6227 code below will do the wrong thing since the mode of such an
be3d27d6
CI		 6228 expression is VOIDmode.
6229
6230 Also do nothing if X is a CLOBBER; this can happen if X was
6231 the return value from a call to gen_lowpart_for_combine. */
6232 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
246e00f2
RK		 6233 return x;
6234
6139ff20
RK		 6235 /* We want to perform the operation is its present mode unless we know
6236 that the operation is valid in MODE, in which case we do the operation
6237 in MODE. */
1c75dfa4
RK		 6238 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6239 && code_to_optab[(int) code] != 0
ef026f91
RS		 6240 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6241 != CODE_FOR_nothing))
6242 ? mode : GET_MODE (x));
e3d616e3 6243
aa988991
RS		 6244 /* It is not valid to do a right-shift in a narrower mode
6245 than the one it came in with. */
6246 if ((code == LSHIFTRT || code == ASHIFTRT)
6247 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6248 op_mode = GET_MODE (x);
ef026f91
RS		 6249
6250 /* Truncate MASK to fit OP_MODE. */
6251 if (op_mode)
6252 mask &= GET_MODE_MASK (op_mode);
6139ff20
RK		 6253
6254 /* When we have an arithmetic operation, or a shift whose count we
6255 do not know, we need to assume that all bit the up to the highest-order
6256 bit in MASK will be needed. This is how we form such a mask. */
ef026f91
RS		 6257 if (op_mode)
6258 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6259 ? GET_MODE_MASK (op_mode)
6260 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6261 else
6262 fuller_mask = ~ (HOST_WIDE_INT) 0;
6263
6264 /* Determine what bits of X are guaranteed to be (non)zero. */
6265 nonzero = nonzero_bits (x, mode);
6139ff20
RK		 6266
6267 /* If none of the bits in X are needed, return a zero. */
e3d616e3 6268 if (! just_select && (nonzero & mask) == 0)
6139ff20 6269 return const0_rtx;
dfbe1b2f 6270
6139ff20
RK		 6271 /* If X is a CONST_INT, return a new one. Do this here since the
6272 test below will fail. */
6273 if (GET_CODE (x) == CONST_INT)
ceb7983c
RK		 6274 {
6275 HOST_WIDE_INT cval = INTVAL (x) & mask;
6276 int width = GET_MODE_BITSIZE (mode);
6277
6278 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6279 number, sign extend it. */
6280 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6281 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6282 cval |= (HOST_WIDE_INT) -1 << width;
6283
6284 return GEN_INT (cval);
6285 }
dfbe1b2f 6286
180b8e4b
RK		 6287 /* If X is narrower than MODE and we want all the bits in X's mode, just
6288 get X in the proper mode. */
6289 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6290 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
dfbe1b2f
RK		 6291 return gen_lowpart_for_combine (mode, x);
6292
71923da7
RK		 6293 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6294 MASK are already known to be zero in X, we need not do anything. */
6295 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6139ff20
RK		 6296 return x;
6297
dfbe1b2f
RK		 6298 switch (code)
6299 {
6139ff20
RK		 6300 case CLOBBER:
6301 /* If X is a (clobber (const_int)), return it since we know we are
0f41302f 6302 generating something that won't match. */
6139ff20
RK		 6303 return x;
6304
6139ff20
RK		 6305 case USE:
6306 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6307 spanned the boundary of the MEM. If we are now masking so it is
6308 within that boundary, we don't need the USE any more. */
f76b9db2
ILT		 6309 if (! BITS_BIG_ENDIAN
6310 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
e3d616e3 6311 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
f76b9db2 6312 break;
6139ff20 6313
dfbe1b2f
RK		 6314 case SIGN_EXTEND:
6315 case ZERO_EXTEND:
6316 case ZERO_EXTRACT:
6317 case SIGN_EXTRACT:
6318 x = expand_compound_operation (x);
6319 if (GET_CODE (x) != code)
e3d616e3 6320 return force_to_mode (x, mode, mask, reg, next_select);
dfbe1b2f
RK		 6321 break;
6322
6323 case REG:
6324 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6325 || rtx_equal_p (reg, get_last_value (x))))
6326 x = reg;
6327 break;
6328
dfbe1b2f 6329 case SUBREG:
6139ff20 6330 if (subreg_lowpart_p (x)
180b8e4b
RK		 6331 /* We can ignore the effect of this SUBREG if it narrows the mode or
6332 if the constant masks to zero all the bits the mode doesn't
6333 have. */
6139ff20
RK		 6334 && ((GET_MODE_SIZE (GET_MODE (x))
6335 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6139ff20
RK		 6336 || (0 == (mask
6337 & GET_MODE_MASK (GET_MODE (x))
180b8e4b 6338 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
e3d616e3 6339 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
dfbe1b2f
RK		 6340 break;
6341
6342 case AND:
6139ff20
RK		 6343 /* If this is an AND with a constant, convert it into an AND
6344 whose constant is the AND of that constant with MASK. If it
6345 remains an AND of MASK, delete it since it is redundant. */
dfbe1b2f 6346
2ca9ae17 6347 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
dfbe1b2f 6348 {
6139ff20
RK		 6349 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6350 mask & INTVAL (XEXP (x, 1)));
dfbe1b2f
RK		 6351
6352 /* If X is still an AND, see if it is an AND with a mask that
71923da7
RK		 6353 is just some low-order bits. If so, and it is MASK, we don't
6354 need it. */
dfbe1b2f
RK		 6355
6356 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
e51712db 6357 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
dfbe1b2f 6358 x = XEXP (x, 0);
d0ab8cd3 6359
71923da7
RK		 6360 /* If it remains an AND, try making another AND with the bits
6361 in the mode mask that aren't in MASK turned on. If the
6362 constant in the AND is wide enough, this might make a
6363 cheaper constant. */
6364
6365 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
2ca9ae17
JW		 6366 && GET_MODE_MASK (GET_MODE (x)) != mask
6367 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
71923da7
RK		 6368 {
6369 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6370 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6371 int width = GET_MODE_BITSIZE (GET_MODE (x));
6372 rtx y;
6373
6374 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6375 number, sign extend it. */
6376 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6377 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6378 cval |= (HOST_WIDE_INT) -1 << width;
6379
6380 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6381 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6382 x = y;
6383 }
6384
d0ab8cd3 6385 break;
dfbe1b2f
RK		 6386 }
6387
6139ff20 6388 goto binop;
dfbe1b2f
RK		 6389
6390 case PLUS:
6139ff20
RK		 6391 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6392 low-order bits (as in an alignment operation) and FOO is already
6393 aligned to that boundary, mask C1 to that boundary as well.
6394 This may eliminate that PLUS and, later, the AND. */
9fa6d012
TG		 6395
6396 {
6397 int width = GET_MODE_BITSIZE (mode);
6398 unsigned HOST_WIDE_INT smask = mask;
6399
6400 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6401 number, sign extend it. */
6402
6403 if (width < HOST_BITS_PER_WIDE_INT
6404 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6405 smask |= (HOST_WIDE_INT) -1 << width;
6406
6407 if (GET_CODE (XEXP (x, 1)) == CONST_INT
0e9ff885
DM		 6408 && exact_log2 (- smask) >= 0)
6409 {
6410#ifdef STACK_BIAS
6411 if (STACK_BIAS
6412 && (XEXP (x, 0) == stack_pointer_rtx
6413 || XEXP (x, 0) == frame_pointer_rtx))
6414 {
6415 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6416 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6417
6418 sp_mask &= ~ (sp_alignment - 1);
6419 if ((sp_mask & ~ mask) == 0
6420 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ mask) != 0)
6421 return force_to_mode (plus_constant (XEXP (x, 0),
6422 ((INTVAL (XEXP (x, 1)) -
6423 STACK_BIAS) & mask)
6424 + STACK_BIAS),
6425 mode, mask, reg, next_select);
6426 }
6427#endif
6428 if ((nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6429 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6430 return force_to_mode (plus_constant (XEXP (x, 0),
6431 INTVAL (XEXP (x, 1)) & mask),
6432 mode, mask, reg, next_select);
6433 }
9fa6d012 6434 }
6139ff20 6435
0f41302f 6436 /* ... fall through ... */
6139ff20 6437
dfbe1b2f
RK		 6438 case MINUS:
6439 case MULT:
6139ff20
RK		 6440 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6441 most significant bit in MASK since carries from those bits will
6442 affect the bits we are interested in. */
6443 mask = fuller_mask;
6444 goto binop;
6445
dfbe1b2f
RK		 6446 case IOR:
6447 case XOR:
6139ff20
RK		 6448 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6449 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6450 operation which may be a bitfield extraction. Ensure that the
6451 constant we form is not wider than the mode of X. */
6452
6453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6454 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6455 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6456 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6457 && GET_CODE (XEXP (x, 1)) == CONST_INT
6458 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6459 + floor_log2 (INTVAL (XEXP (x, 1))))
6460 < GET_MODE_BITSIZE (GET_MODE (x)))
6461 && (INTVAL (XEXP (x, 1))
01c82bbb 6462 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6139ff20
RK		 6463 {
6464 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6465 << INTVAL (XEXP (XEXP (x, 0), 1)));
6466 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6467 XEXP (XEXP (x, 0), 0), temp);
d4d2b13f
RK		 6468 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6469 XEXP (XEXP (x, 0), 1));
e3d616e3 6470 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6471 }
6472
6473 binop:
dfbe1b2f 6474 /* For most binary operations, just propagate into the operation and
6139ff20
RK		 6475 change the mode if we have an operation of that mode. */
6476
e3d616e3
RK		 6477 op0 = gen_lowpart_for_combine (op_mode,
6478 force_to_mode (XEXP (x, 0), mode, mask,
6479 reg, next_select));
6480 op1 = gen_lowpart_for_combine (op_mode,
6481 force_to_mode (XEXP (x, 1), mode, mask,
6482 reg, next_select));
6139ff20 6483
2dd484ed
RK		 6484 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6485 MASK since OP1 might have been sign-extended but we never want
6486 to turn on extra bits, since combine might have previously relied
6487 on them being off. */
6488 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6489 && (INTVAL (op1) & mask) != 0)
6490 op1 = GEN_INT (INTVAL (op1) & mask);
6491
6139ff20
RK		 6492 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6493 x = gen_binary (code, op_mode, op0, op1);
d0ab8cd3 6494 break;
dfbe1b2f
RK		 6495
6496 case ASHIFT:
dfbe1b2f 6497 /* For left shifts, do the same, but just for the first operand.
f6785026
RK		 6498 However, we cannot do anything with shifts where we cannot
6499 guarantee that the counts are smaller than the size of the mode
6500 because such a count will have a different meaning in a
6139ff20 6501 wider mode. */
f6785026
RK		 6502
6503 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6139ff20 6504 && INTVAL (XEXP (x, 1)) >= 0
f6785026
RK		 6505 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6506 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6507 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
adb7a1cb 6508 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
f6785026
RK		 6509 break;
6510
6139ff20
RK		 6511 /* If the shift count is a constant and we can do arithmetic in
6512 the mode of the shift, refine which bits we need. Otherwise, use the
6513 conservative form of the mask. */
6514 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6515 && INTVAL (XEXP (x, 1)) >= 0
6516 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6517 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6518 mask >>= INTVAL (XEXP (x, 1));
6519 else
6520 mask = fuller_mask;
6521
6522 op0 = gen_lowpart_for_combine (op_mode,
6523 force_to_mode (XEXP (x, 0), op_mode,
e3d616e3 6524 mask, reg, next_select));
6139ff20
RK		 6525
6526 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6527 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
d0ab8cd3 6528 break;
dfbe1b2f
RK		 6529
6530 case LSHIFTRT:
1347292b
JW		 6531 /* Here we can only do something if the shift count is a constant,
6532 this shift constant is valid for the host, and we can do arithmetic
6533 in OP_MODE. */
dfbe1b2f
RK		 6534
6535 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1347292b 6536 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6139ff20 6537 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 6538 {
6139ff20
RK		 6539 rtx inner = XEXP (x, 0);
6540
6541 /* Select the mask of the bits we need for the shift operand. */
6542 mask <<= INTVAL (XEXP (x, 1));
d0ab8cd3 6543
6139ff20
RK		 6544 /* We can only change the mode of the shift if we can do arithmetic
6545 in the mode of the shift and MASK is no wider than the width of
6546 OP_MODE. */
6547 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6548 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
d0ab8cd3
RK		 6549 op_mode = GET_MODE (x);
6550
e3d616e3 6551 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6139ff20
RK		 6552
6553 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6554 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
d0ab8cd3 6555 }
6139ff20
RK		 6556
6557 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6558 shift and AND produces only copies of the sign bit (C2 is one less
6559 than a power of two), we can do this with just a shift. */
6560
6561 if (GET_CODE (x) == LSHIFTRT
6562 && GET_CODE (XEXP (x, 1)) == CONST_INT
6563 && ((INTVAL (XEXP (x, 1))
6564 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6565 >= GET_MODE_BITSIZE (GET_MODE (x)))
6566 && exact_log2 (mask + 1) >= 0
6567 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6568 >= exact_log2 (mask + 1)))
6569 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6570 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6571 - exact_log2 (mask + 1)));
d0ab8cd3
RK		 6572 break;
6573
6574 case ASHIFTRT:
6139ff20
RK		 6575 /* If we are just looking for the sign bit, we don't need this shift at
6576 all, even if it has a variable count. */
9bf22b75 6577 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
e51712db 6578 && (mask == ((unsigned HOST_WIDE_INT) 1
9bf22b75 6579 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
e3d616e3 6580 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20
RK		 6581
6582 /* If this is a shift by a constant, get a mask that contains those bits
6583 that are not copies of the sign bit. We then have two cases: If
6584 MASK only includes those bits, this can be a logical shift, which may
6585 allow simplifications. If MASK is a single-bit field not within
6586 those bits, we are requesting a copy of the sign bit and hence can
6587 shift the sign bit to the appropriate location. */
6588
6589 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6590 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6591 {
6592 int i = -1;
6593
b69960ac
RK		 6594 /* If the considered data is wider then HOST_WIDE_INT, we can't
6595 represent a mask for all its bits in a single scalar.
6596 But we only care about the lower bits, so calculate these. */
6597
6a11342f 6598 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
b69960ac 6599 {
0f41302f 6600 nonzero = ~ (HOST_WIDE_INT) 0;
b69960ac
RK		 6601
6602 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6603 is the number of bits a full-width mask would have set.
6604 We need only shift if these are fewer than nonzero can
6605 hold. If not, we must keep all bits set in nonzero. */
6606
6607 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6608 < HOST_BITS_PER_WIDE_INT)
6609 nonzero >>= INTVAL (XEXP (x, 1))
6610 + HOST_BITS_PER_WIDE_INT
6611 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6612 }
6613 else
6614 {
6615 nonzero = GET_MODE_MASK (GET_MODE (x));
6616 nonzero >>= INTVAL (XEXP (x, 1));
6617 }
6139ff20
RK		 6618
6619 if ((mask & ~ nonzero) == 0
6620 || (i = exact_log2 (mask)) >= 0)
6621 {
6622 x = simplify_shift_const
6623 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6624 i < 0 ? INTVAL (XEXP (x, 1))
6625 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6626
6627 if (GET_CODE (x) != ASHIFTRT)
e3d616e3 6628 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6629 }
6630 }
6631
6632 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6633 even if the shift count isn't a constant. */
6634 if (mask == 1)
6635 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6636
d0ab8cd3 6637 /* If this is a sign-extension operation that just affects bits
4c002f29
RK		 6638 we don't care about, remove it. Be sure the call above returned
6639 something that is still a shift. */
d0ab8cd3 6640
4c002f29
RK		 6641 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6642 && GET_CODE (XEXP (x, 1)) == CONST_INT
d0ab8cd3 6643 && INTVAL (XEXP (x, 1)) >= 0
6139ff20
RK		 6644 && (INTVAL (XEXP (x, 1))
6645 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
d0ab8cd3
RK		 6646 && GET_CODE (XEXP (x, 0)) == ASHIFT
6647 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6648 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
e3d616e3
RK		 6649 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6650 reg, next_select);
6139ff20 6651
dfbe1b2f
RK		 6652 break;
6653
6139ff20
RK		 6654 case ROTATE:
6655 case ROTATERT:
6656 /* If the shift count is constant and we can do computations
6657 in the mode of X, compute where the bits we care about are.
6658 Otherwise, we can't do anything. Don't change the mode of
6659 the shift or propagate MODE into the shift, though. */
6660 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6661 && INTVAL (XEXP (x, 1)) >= 0)
6662 {
6663 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6664 GET_MODE (x), GEN_INT (mask),
6665 XEXP (x, 1));
7d171a1e 6666 if (temp && GET_CODE(temp) == CONST_INT)
6139ff20
RK		 6667 SUBST (XEXP (x, 0),
6668 force_to_mode (XEXP (x, 0), GET_MODE (x),
e3d616e3 6669 INTVAL (temp), reg, next_select));
6139ff20
RK		 6670 }
6671 break;
6672
dfbe1b2f 6673 case NEG:
180b8e4b
RK		 6674 /* If we just want the low-order bit, the NEG isn't needed since it
6675 won't change the low-order bit. */
6676 if (mask == 1)
6677 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6678
6139ff20
RK		 6679 /* We need any bits less significant than the most significant bit in
6680 MASK since carries from those bits will affect the bits we are
6681 interested in. */
6682 mask = fuller_mask;
6683 goto unop;
6684
dfbe1b2f 6685 case NOT:
6139ff20
RK		 6686 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6687 same as the XOR case above. Ensure that the constant we form is not
6688 wider than the mode of X. */
6689
6690 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6691 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6692 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6693 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6694 < GET_MODE_BITSIZE (GET_MODE (x)))
6695 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6696 {
6697 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6698 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6699 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6700
e3d616e3 6701 return force_to_mode (x, mode, mask, reg, next_select);
6139ff20
RK		 6702 }
6703
f82da7d2
JW		 6704 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6705 use the full mask inside the NOT. */
6706 mask = fuller_mask;
6707
6139ff20 6708 unop:
e3d616e3
RK		 6709 op0 = gen_lowpart_for_combine (op_mode,
6710 force_to_mode (XEXP (x, 0), mode, mask,
6711 reg, next_select));
6139ff20 6712 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
0c1c8ea6 6713 x = gen_unary (code, op_mode, op_mode, op0);
6139ff20
RK		 6714 break;
6715
6716 case NE:
6717 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
3aceff0d 6718 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
1a6ec070 6719 which is equal to STORE_FLAG_VALUE. */
3aceff0d
RK		 6720 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6721 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
1a6ec070 6722 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
e3d616e3 6723 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6139ff20 6724
d0ab8cd3
RK		 6725 break;
6726
6727 case IF_THEN_ELSE:
6728 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6729 written in a narrower mode. We play it safe and do not do so. */
6730
6731 SUBST (XEXP (x, 1),
6732 gen_lowpart_for_combine (GET_MODE (x),
6733 force_to_mode (XEXP (x, 1), mode,
e3d616e3 6734 mask, reg, next_select)));
d0ab8cd3
RK		 6735 SUBST (XEXP (x, 2),
6736 gen_lowpart_for_combine (GET_MODE (x),
6737 force_to_mode (XEXP (x, 2), mode,
e3d616e3 6738 mask, reg,next_select)));
d0ab8cd3 6739 break;
e9a25f70
JL		 6740
6741 default:
6742 break;
dfbe1b2f
RK		 6743 }
6744
d0ab8cd3 6745 /* Ensure we return a value of the proper mode. */
dfbe1b2f
RK		 6746 return gen_lowpart_for_combine (mode, x);
6747}
6748\f
abe6e52f
RK		 6749/* Return nonzero if X is an expression that has one of two values depending on
6750 whether some other value is zero or nonzero. In that case, we return the
6751 value that is being tested, *PTRUE is set to the value if the rtx being
6752 returned has a nonzero value, and *PFALSE is set to the other alternative.
6753
6754 If we return zero, we set *PTRUE and *PFALSE to X. */
6755
6756static rtx
6757if_then_else_cond (x, ptrue, pfalse)
6758 rtx x;
6759 rtx *ptrue, *pfalse;
6760{
6761 enum machine_mode mode = GET_MODE (x);
6762 enum rtx_code code = GET_CODE (x);
6763 int size = GET_MODE_BITSIZE (mode);
6764 rtx cond0, cond1, true0, true1, false0, false1;
6765 unsigned HOST_WIDE_INT nz;
6766
6767 /* If this is a unary operation whose operand has one of two values, apply
6768 our opcode to compute those values. */
6769 if (GET_RTX_CLASS (code) == '1'
6770 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6771 {
0c1c8ea6
RK		 6772 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6773 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
abe6e52f
RK		 6774 return cond0;
6775 }
6776
3a19aabc 6777 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
ddd5a7c1 6778 make can't possibly match and would suppress other optimizations. */
3a19aabc
RK		 6779 else if (code == COMPARE)
6780 ;
6781
abe6e52f
RK		 6782 /* If this is a binary operation, see if either side has only one of two
6783 values. If either one does or if both do and they are conditional on
6784 the same value, compute the new true and false values. */
6785 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6786 || GET_RTX_CLASS (code) == '<')
6787 {
6788 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6789 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6790
6791 if ((cond0 != 0 || cond1 != 0)
6792 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6793 {
987e845a
JW		 6794 /* If if_then_else_cond returned zero, then true/false are the
6795 same rtl. We must copy one of them to prevent invalid rtl
6796 sharing. */
6797 if (cond0 == 0)
6798 true0 = copy_rtx (true0);
6799 else if (cond1 == 0)
6800 true1 = copy_rtx (true1);
6801
abe6e52f
RK		 6802 *ptrue = gen_binary (code, mode, true0, true1);
6803 *pfalse = gen_binary (code, mode, false0, false1);
6804 return cond0 ? cond0 : cond1;
6805 }
9210df58 6806
9210df58 6807 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
0802d516
RK		 6808 operands is zero when the other is non-zero, and vice-versa,
6809 and STORE_FLAG_VALUE is 1 or -1. */
9210df58 6810
0802d516
RK		 6811 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6812 && (code == PLUS || code == IOR || code == XOR || code == MINUS
9210df58
RK		 6813 || code == UMAX)
6814 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6815 {
6816 rtx op0 = XEXP (XEXP (x, 0), 1);
6817 rtx op1 = XEXP (XEXP (x, 1), 1);
6818
6819 cond0 = XEXP (XEXP (x, 0), 0);
6820 cond1 = XEXP (XEXP (x, 1), 0);
6821
6822 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6823 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6824 && reversible_comparison_p (cond1)
6825 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6826 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6827 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6828 || ((swap_condition (GET_CODE (cond0))
6829 == reverse_condition (GET_CODE (cond1)))
6830 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6831 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6832 && ! side_effects_p (x))
6833 {
6834 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6835 *pfalse = gen_binary (MULT, mode,
6836 (code == MINUS
0c1c8ea6 6837 ? gen_unary (NEG, mode, mode, op1) : op1),
9210df58
RK		 6838 const_true_rtx);
6839 return cond0;
6840 }
6841 }
6842
6843 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6844 is always zero. */
0802d516
RK		 6845 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6846 && (code == MULT || code == AND || code == UMIN)
9210df58
RK		 6847 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6848 {
6849 cond0 = XEXP (XEXP (x, 0), 0);
6850 cond1 = XEXP (XEXP (x, 1), 0);
6851
6852 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6853 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6854 && reversible_comparison_p (cond1)
6855 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6856 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6857 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6858 || ((swap_condition (GET_CODE (cond0))
6859 == reverse_condition (GET_CODE (cond1)))
6860 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6861 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6862 && ! side_effects_p (x))
6863 {
6864 *ptrue = *pfalse = const0_rtx;
6865 return cond0;
6866 }
6867 }
abe6e52f
RK		 6868 }
6869
6870 else if (code == IF_THEN_ELSE)
6871 {
6872 /* If we have IF_THEN_ELSE already, extract the condition and
6873 canonicalize it if it is NE or EQ. */
6874 cond0 = XEXP (x, 0);
6875 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6876 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6877 return XEXP (cond0, 0);
6878 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6879 {
6880 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6881 return XEXP (cond0, 0);
6882 }
6883 else
6884 return cond0;
6885 }
6886
6887 /* If X is a normal SUBREG with both inner and outer modes integral,
6888 we can narrow both the true and false values of the inner expression,
6889 if there is a condition. */
6890 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6891 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6892 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6893 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6894 &true0, &false0)))
6895 {
00244e6b
RK		 6896 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6897 *pfalse
6898 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
abe6e52f 6899
abe6e52f
RK		 6900 return cond0;
6901 }
6902
6903 /* If X is a constant, this isn't special and will cause confusions
6904 if we treat it as such. Likewise if it is equivalent to a constant. */
6905 else if (CONSTANT_P (x)
6906 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6907 ;
6908
6909 /* If X is known to be either 0 or -1, those are the true and
6910 false values when testing X. */
6911 else if (num_sign_bit_copies (x, mode) == size)
6912 {
6913 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6914 return x;
6915 }
6916
6917 /* Likewise for 0 or a single bit. */
6918 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6919 {
6920 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6921 return x;
6922 }
6923
6924 /* Otherwise fail; show no condition with true and false values the same. */
6925 *ptrue = *pfalse = x;
6926 return 0;
6927}
6928\f
1a26b032
RK		 6929/* Return the value of expression X given the fact that condition COND
6930 is known to be true when applied to REG as its first operand and VAL
6931 as its second. X is known to not be shared and so can be modified in
6932 place.
6933
6934 We only handle the simplest cases, and specifically those cases that
6935 arise with IF_THEN_ELSE expressions. */
6936
6937static rtx
6938known_cond (x, cond, reg, val)
6939 rtx x;
6940 enum rtx_code cond;
6941 rtx reg, val;
6942{
6943 enum rtx_code code = GET_CODE (x);
f24ad0e4 6944 rtx temp;
1a26b032
RK		 6945 char *fmt;
6946 int i, j;
6947
6948 if (side_effects_p (x))
6949 return x;
6950
6951 if (cond == EQ && rtx_equal_p (x, reg))
6952 return val;
6953
6954 /* If X is (abs REG) and we know something about REG's relationship
6955 with zero, we may be able to simplify this. */
6956
6957 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6958 switch (cond)
6959 {
6960 case GE: case GT: case EQ:
6961 return XEXP (x, 0);
6962 case LT: case LE:
0c1c8ea6
RK		 6963 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6964 XEXP (x, 0));
e9a25f70
JL		 6965 default:
6966 break;
1a26b032
RK		 6967 }
6968
6969 /* The only other cases we handle are MIN, MAX, and comparisons if the
6970 operands are the same as REG and VAL. */
6971
6972 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6973 {
6974 if (rtx_equal_p (XEXP (x, 0), val))
6975 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6976
6977 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6978 {
6979 if (GET_RTX_CLASS (code) == '<')
6980 return (comparison_dominates_p (cond, code) ? const_true_rtx
6981 : (comparison_dominates_p (cond,
6982 reverse_condition (code))
6983 ? const0_rtx : x));
6984
6985 else if (code == SMAX || code == SMIN
6986 || code == UMIN || code == UMAX)
6987 {
6988 int unsignedp = (code == UMIN || code == UMAX);
6989
6990 if (code == SMAX || code == UMAX)
6991 cond = reverse_condition (cond);
6992
6993 switch (cond)
6994 {
6995 case GE: case GT:
6996 return unsignedp ? x : XEXP (x, 1);
6997 case LE: case LT:
6998 return unsignedp ? x : XEXP (x, 0);
6999 case GEU: case GTU:
7000 return unsignedp ? XEXP (x, 1) : x;
7001 case LEU: case LTU:
7002 return unsignedp ? XEXP (x, 0) : x;
e9a25f70
JL		 7003 default:
7004 break;
1a26b032
RK		 7005 }
7006 }
7007 }
7008 }
7009
7010 fmt = GET_RTX_FORMAT (code);
7011 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7012 {
7013 if (fmt[i] == 'e')
7014 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7015 else if (fmt[i] == 'E')
7016 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7017 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7018 cond, reg, val));
7019 }
7020
7021 return x;
7022}
7023\f
e11fa86f
RK		 7024/* See if X and Y are equal for the purposes of seeing if we can rewrite an
7025 assignment as a field assignment. */
7026
7027static int
7028rtx_equal_for_field_assignment_p (x, y)
7029 rtx x;
7030 rtx y;
7031{
e11fa86f
RK		 7032 if (x == y || rtx_equal_p (x, y))
7033 return 1;
7034
7035 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7036 return 0;
7037
7038 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7039 Note that all SUBREGs of MEM are paradoxical; otherwise they
7040 would have been rewritten. */
7041 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7042 && GET_CODE (SUBREG_REG (y)) == MEM
7043 && rtx_equal_p (SUBREG_REG (y),
7044 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7045 return 1;
7046
7047 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7048 && GET_CODE (SUBREG_REG (x)) == MEM
7049 && rtx_equal_p (SUBREG_REG (x),
7050 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7051 return 1;
7052
9ec36da5
JL		 7053 /* We used to see if get_last_value of X and Y were the same but that's
7054 not correct. In one direction, we'll cause the assignment to have
7055 the wrong destination and in the case, we'll import a register into this
7056 insn that might have already have been dead. So fail if none of the
7057 above cases are true. */
7058 return 0;
e11fa86f
RK		 7059}
7060\f
230d793d
RS		 7061/* See if X, a SET operation, can be rewritten as a bit-field assignment.
7062 Return that assignment if so.
7063
7064 We only handle the most common cases. */
7065
7066static rtx
7067make_field_assignment (x)
7068 rtx x;
7069{
7070 rtx dest = SET_DEST (x);
7071 rtx src = SET_SRC (x);
dfbe1b2f 7072 rtx assign;
e11fa86f 7073 rtx rhs, lhs;
5f4f0e22
CH		 7074 HOST_WIDE_INT c1;
7075 int pos, len;
dfbe1b2f
RK		 7076 rtx other;
7077 enum machine_mode mode;
230d793d
RS		 7078
7079 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7080 a clear of a one-bit field. We will have changed it to
7081 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7082 for a SUBREG. */
7083
7084 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7085 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7086 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
e11fa86f 7087 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7088 {
8999a12e 7089 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7090 1, 1, 1, 0);
76184def 7091 if (assign != 0)
38a448ca 7092 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7093 return x;
230d793d
RS		 7094 }
7095
7096 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7097 && subreg_lowpart_p (XEXP (src, 0))
7098 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7099 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7100 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7101 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
e11fa86f 7102 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7103 {
8999a12e 7104 assign = make_extraction (VOIDmode, dest, 0,
230d793d
RS		 7105 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7106 1, 1, 1, 0);
76184def 7107 if (assign != 0)
38a448ca 7108 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
76184def 7109 return x;
230d793d
RS		 7110 }
7111
9dd11dcb 7112 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
230d793d
RS		 7113 one-bit field. */
7114 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7115 && XEXP (XEXP (src, 0), 0) == const1_rtx
e11fa86f 7116 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
230d793d 7117 {
8999a12e 7118 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
230d793d 7119 1, 1, 1, 0);
76184def 7120 if (assign != 0)
38a448ca 7121 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
76184def 7122 return x;
230d793d
RS		 7123 }
7124
dfbe1b2f 7125 /* The other case we handle is assignments into a constant-position
9dd11dcb 7126 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
dfbe1b2f
RK		 7127 a mask that has all one bits except for a group of zero bits and
7128 OTHER is known to have zeros where C1 has ones, this is such an
7129 assignment. Compute the position and length from C1. Shift OTHER
7130 to the appropriate position, force it to the required mode, and
7131 make the extraction. Check for the AND in both operands. */
7132
9dd11dcb 7133 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
e11fa86f
RK		 7134 return x;
7135
7136 rhs = expand_compound_operation (XEXP (src, 0));
7137 lhs = expand_compound_operation (XEXP (src, 1));
7138
7139 if (GET_CODE (rhs) == AND
7140 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7141 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7142 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7143 else if (GET_CODE (lhs) == AND
7144 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7145 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7146 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
dfbe1b2f
RK		 7147 else
7148 return x;
230d793d 7149
e11fa86f 7150 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
dfbe1b2f 7151 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
e5e809f4
JL		 7152 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7153 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
dfbe1b2f 7154 return x;
230d793d 7155
5f4f0e22 7156 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
76184def
DE		 7157 if (assign == 0)
7158 return x;
230d793d 7159
dfbe1b2f
RK		 7160 /* The mode to use for the source is the mode of the assignment, or of
7161 what is inside a possible STRICT_LOW_PART. */
7162 mode = (GET_CODE (assign) == STRICT_LOW_PART
7163 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
230d793d 7164
dfbe1b2f
RK		 7165 /* Shift OTHER right POS places and make it the source, restricting it
7166 to the proper length and mode. */
230d793d 7167
5f4f0e22
CH		 7168 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7169 GET_MODE (src), other, pos),
6139ff20
RK		 7170 mode,
7171 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7172 ? GET_MODE_MASK (mode)
7173 : ((HOST_WIDE_INT) 1 << len) - 1,
e3d616e3 7174 dest, 0);
230d793d 7175
dfbe1b2f 7176 return gen_rtx_combine (SET, VOIDmode, assign, src);
230d793d
RS		 7177}
7178\f
7179/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7180 if so. */
7181
7182static rtx
7183apply_distributive_law (x)
7184 rtx x;
7185{
7186 enum rtx_code code = GET_CODE (x);
7187 rtx lhs, rhs, other;
7188 rtx tem;
7189 enum rtx_code inner_code;
7190
d8a8a4da
RS		 7191 /* Distributivity is not true for floating point.
7192 It can change the value. So don't do it.
7193 -- rms and moshier@world.std.com. */
3ad2180a 7194 if (FLOAT_MODE_P (GET_MODE (x)))
d8a8a4da
RS		 7195 return x;
7196
230d793d
RS		 7197 /* The outer operation can only be one of the following: */
7198 if (code != IOR && code != AND && code != XOR
7199 && code != PLUS && code != MINUS)
7200 return x;
7201
7202 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7203
0f41302f
MS		 7204 /* If either operand is a primitive we can't do anything, so get out
7205 fast. */
230d793d 7206 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
dfbe1b2f 7207 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
230d793d
RS		 7208 return x;
7209
7210 lhs = expand_compound_operation (lhs);
7211 rhs = expand_compound_operation (rhs);
7212 inner_code = GET_CODE (lhs);
7213 if (inner_code != GET_CODE (rhs))
7214 return x;
7215
7216 /* See if the inner and outer operations distribute. */
7217 switch (inner_code)
7218 {
7219 case LSHIFTRT:
7220 case ASHIFTRT:
7221 case AND:
7222 case IOR:
7223 /* These all distribute except over PLUS. */
7224 if (code == PLUS || code == MINUS)
7225 return x;
7226 break;
7227
7228 case MULT:
7229 if (code != PLUS && code != MINUS)
7230 return x;
7231 break;
7232
7233 case ASHIFT:
45620ed4 7234 /* This is also a multiply, so it distributes over everything. */
230d793d
RS		 7235 break;
7236
7237 case SUBREG:
dfbe1b2f
RK		 7238 /* Non-paradoxical SUBREGs distributes over all operations, provided
7239 the inner modes and word numbers are the same, this is an extraction
2b4bd1bc
JW		 7240 of a low-order part, we don't convert an fp operation to int or
7241 vice versa, and we would not be converting a single-word
dfbe1b2f 7242 operation into a multi-word operation. The latter test is not
2b4bd1bc 7243 required, but it prevents generating unneeded multi-word operations.
dfbe1b2f
RK		 7244 Some of the previous tests are redundant given the latter test, but
7245 are retained because they are required for correctness.
7246
7247 We produce the result slightly differently in this case. */
7248
7249 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7250 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7251 || ! subreg_lowpart_p (lhs)
2b4bd1bc
JW		 7252 || (GET_MODE_CLASS (GET_MODE (lhs))
7253 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7254 || (GET_MODE_SIZE (GET_MODE (lhs))
8af24e26 7255 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
dfbe1b2f 7256 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
230d793d
RS		 7257 return x;
7258
7259 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7260 SUBREG_REG (lhs), SUBREG_REG (rhs));
7261 return gen_lowpart_for_combine (GET_MODE (x), tem);
7262
7263 default:
7264 return x;
7265 }
7266
7267 /* Set LHS and RHS to the inner operands (A and B in the example
7268 above) and set OTHER to the common operand (C in the example).
7269 These is only one way to do this unless the inner operation is
7270 commutative. */
7271 if (GET_RTX_CLASS (inner_code) == 'c'
7272 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7273 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7274 else if (GET_RTX_CLASS (inner_code) == 'c'
7275 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7276 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7277 else if (GET_RTX_CLASS (inner_code) == 'c'
7278 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7279 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7280 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7281 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7282 else
7283 return x;
7284
7285 /* Form the new inner operation, seeing if it simplifies first. */
7286 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7287
7288 /* There is one exception to the general way of distributing:
7289 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7290 if (code == XOR && inner_code == IOR)
7291 {
7292 inner_code = AND;
0c1c8ea6 7293 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
230d793d
RS		 7294 }
7295
7296 /* We may be able to continuing distributing the result, so call
7297 ourselves recursively on the inner operation before forming the
7298 outer operation, which we return. */
7299 return gen_binary (inner_code, GET_MODE (x),
7300 apply_distributive_law (tem), other);
7301}
7302\f
7303/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7304 in MODE.
7305
7306 Return an equivalent form, if different from X. Otherwise, return X. If
7307 X is zero, we are to always construct the equivalent form. */
7308
7309static rtx
7310simplify_and_const_int (x, mode, varop, constop)
7311 rtx x;
7312 enum machine_mode mode;
7313 rtx varop;
5f4f0e22 7314 unsigned HOST_WIDE_INT constop;
230d793d 7315{
951553af 7316 unsigned HOST_WIDE_INT nonzero;
9fa6d012 7317 int width = GET_MODE_BITSIZE (mode);
42301240 7318 int i;
230d793d 7319
6139ff20
RK		 7320 /* Simplify VAROP knowing that we will be only looking at some of the
7321 bits in it. */
e3d616e3 7322 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
230d793d 7323
6139ff20
RK		 7324 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7325 CONST_INT, we are done. */
7326 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7327 return varop;
230d793d 7328
fc06d7aa
RK		 7329 /* See what bits may be nonzero in VAROP. Unlike the general case of
7330 a call to nonzero_bits, here we don't care about bits outside
7331 MODE. */
7332
7333 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
230d793d 7334
9fa6d012
TG		 7335 /* If this would be an entire word for the target, but is not for
7336 the host, then sign-extend on the host so that the number will look
7337 the same way on the host that it would on the target.
7338
7339 For example, when building a 64 bit alpha hosted 32 bit sparc
7340 targeted compiler, then we want the 32 bit unsigned value -1 to be
7341 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7342 The later confuses the sparc backend. */
7343
7344 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7345 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7346 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7347
230d793d 7348 /* Turn off all bits in the constant that are known to already be zero.
951553af 7349 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
230d793d
RS		 7350 which is tested below. */
7351
951553af 7352 constop &= nonzero;
230d793d
RS		 7353
7354 /* If we don't have any bits left, return zero. */
7355 if (constop == 0)
7356 return const0_rtx;
7357
42301240
RK		 7358 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7359 a power of two, we can replace this with a ASHIFT. */
7360 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7361 && (i = exact_log2 (constop)) >= 0)
7362 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7363
6139ff20
RK		 7364 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7365 or XOR, then try to apply the distributive law. This may eliminate
7366 operations if either branch can be simplified because of the AND.
7367 It may also make some cases more complex, but those cases probably
7368 won't match a pattern either with or without this. */
7369
7370 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7371 return
7372 gen_lowpart_for_combine
7373 (mode,
7374 apply_distributive_law
7375 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7376 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7377 XEXP (varop, 0), constop),
7378 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7379 XEXP (varop, 1), constop))));
7380
230d793d
RS		 7381 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7382 if we already had one (just check for the simplest cases). */
7383 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7384 && GET_MODE (XEXP (x, 0)) == mode
7385 && SUBREG_REG (XEXP (x, 0)) == varop)
7386 varop = XEXP (x, 0);
7387 else
7388 varop = gen_lowpart_for_combine (mode, varop);
7389
0f41302f 7390 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 7391 if (GET_CODE (varop) == CLOBBER)
7392 return x ? x : varop;
7393
7394 /* If we are only masking insignificant bits, return VAROP. */
951553af 7395 if (constop == nonzero)
230d793d
RS		 7396 x = varop;
7397
7398 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7399 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6139ff20 7400 x = gen_binary (AND, mode, varop, GEN_INT (constop));
230d793d
RS		 7401
7402 else
7403 {
7404 if (GET_CODE (XEXP (x, 1)) != CONST_INT
e51712db 7405 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
5f4f0e22 7406 SUBST (XEXP (x, 1), GEN_INT (constop));
230d793d
RS		 7407
7408 SUBST (XEXP (x, 0), varop);
7409 }
7410
7411 return x;
7412}
7413\f
b3728b0e
JW		 7414/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7415 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7416 is less useful. We can't allow both, because that results in exponential
956d6950 7417 run time recursion. There is a nullstone testcase that triggered
b3728b0e
JW		 7418 this. This macro avoids accidental uses of num_sign_bit_copies. */
7419#define num_sign_bit_copies()
7420
230d793d
RS		 7421/* Given an expression, X, compute which bits in X can be non-zero.
7422 We don't care about bits outside of those defined in MODE.
7423
7424 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7425 a shift, AND, or zero_extract, we can do better. */
7426
5f4f0e22 7427static unsigned HOST_WIDE_INT
951553af 7428nonzero_bits (x, mode)
230d793d
RS		 7429 rtx x;
7430 enum machine_mode mode;
7431{
951553af
RK		 7432 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7433 unsigned HOST_WIDE_INT inner_nz;
230d793d
RS		 7434 enum rtx_code code;
7435 int mode_width = GET_MODE_BITSIZE (mode);
7436 rtx tem;
7437
1c75dfa4
RK		 7438 /* For floating-point values, assume all bits are needed. */
7439 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7440 return nonzero;
7441
230d793d
RS		 7442 /* If X is wider than MODE, use its mode instead. */
7443 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7444 {
7445 mode = GET_MODE (x);
951553af 7446 nonzero = GET_MODE_MASK (mode);
230d793d
RS		 7447 mode_width = GET_MODE_BITSIZE (mode);
7448 }
7449
5f4f0e22 7450 if (mode_width > HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7451 /* Our only callers in this case look for single bit values. So
7452 just return the mode mask. Those tests will then be false. */
951553af 7453 return nonzero;
230d793d 7454
8baf60bb 7455#ifndef WORD_REGISTER_OPERATIONS
c6965c0f 7456 /* If MODE is wider than X, but both are a single word for both the host
0840fd91
RK		 7457 and target machines, we can compute this from which bits of the
7458 object might be nonzero in its own mode, taking into account the fact
7459 that on many CISC machines, accessing an object in a wider mode
7460 causes the high-order bits to become undefined. So they are
7461 not known to be zero. */
7462
7463 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7464 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7465 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
c6965c0f 7466 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
0840fd91
RK		 7467 {
7468 nonzero &= nonzero_bits (x, GET_MODE (x));
7469 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7470 return nonzero;
7471 }
7472#endif
7473
230d793d
RS		 7474 code = GET_CODE (x);
7475 switch (code)
7476 {
7477 case REG:
320dd7a7
RK		 7478#ifdef POINTERS_EXTEND_UNSIGNED
7479 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7480 all the bits above ptr_mode are known to be zero. */
7481 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7482 && REGNO_POINTER_FLAG (REGNO (x)))
7483 nonzero &= GET_MODE_MASK (ptr_mode);
7484#endif
7485
b0d71df9
RK		 7486#ifdef STACK_BOUNDARY
7487 /* If this is the stack pointer, we may know something about its
7488 alignment. If PUSH_ROUNDING is defined, it is possible for the
230d793d
RS		 7489 stack to be momentarily aligned only to that amount, so we pick
7490 the least alignment. */
7491
ee49a9c7
JW		 7492 /* We can't check for arg_pointer_rtx here, because it is not
7493 guaranteed to have as much alignment as the stack pointer.
7494 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7495 alignment but the argument pointer has only 64 bit alignment. */
7496
0e9ff885
DM		 7497 if ((x == frame_pointer_rtx
7498 || x == stack_pointer_rtx
7499 || x == hard_frame_pointer_rtx
7500 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7501 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7502#ifdef STACK_BIAS
7503 && !STACK_BIAS
7504#endif
7505 )
230d793d 7506 {
b0d71df9 7507 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
230d793d
RS		 7508
7509#ifdef PUSH_ROUNDING
91102d5a 7510 if (REGNO (x) == STACK_POINTER_REGNUM)
b0d71df9 7511 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
230d793d
RS		 7512#endif
7513
320dd7a7
RK		 7514 /* We must return here, otherwise we may get a worse result from
7515 one of the choices below. There is nothing useful below as
7516 far as the stack pointer is concerned. */
b0d71df9 7517 return nonzero &= ~ (sp_alignment - 1);
230d793d 7518 }
b0d71df9 7519#endif
230d793d 7520
55310dad
RK		 7521 /* If X is a register whose nonzero bits value is current, use it.
7522 Otherwise, if X is a register whose value we can find, use that
7523 value. Otherwise, use the previously-computed global nonzero bits
7524 for this register. */
7525
7526 if (reg_last_set_value[REGNO (x)] != 0
7527 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7528 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7529 || reg_last_set_label[REGNO (x)] == label_tick)
7530 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7531 return reg_last_set_nonzero_bits[REGNO (x)];
230d793d
RS		 7532
7533 tem = get_last_value (x);
9afa3d54 7534
230d793d 7535 if (tem)
9afa3d54
RK		 7536 {
7537#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7538 /* If X is narrower than MODE and TEM is a non-negative
7539 constant that would appear negative in the mode of X,
7540 sign-extend it for use in reg_nonzero_bits because some
7541 machines (maybe most) will actually do the sign-extension
7542 and this is the conservative approach.
7543
7544 ??? For 2.5, try to tighten up the MD files in this regard
7545 instead of this kludge. */
7546
7547 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7548 && GET_CODE (tem) == CONST_INT
7549 && INTVAL (tem) > 0
7550 && 0 != (INTVAL (tem)
7551 & ((HOST_WIDE_INT) 1
9e69be8c 7552 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9afa3d54
RK		 7553 tem = GEN_INT (INTVAL (tem)
7554 | ((HOST_WIDE_INT) (-1)
7555 << GET_MODE_BITSIZE (GET_MODE (x))));
7556#endif
7557 return nonzero_bits (tem, mode);
7558 }
951553af
RK		 7559 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7560 return reg_nonzero_bits[REGNO (x)] & nonzero;
230d793d 7561 else
951553af 7562 return nonzero;
230d793d
RS		 7563
7564 case CONST_INT:
9afa3d54
RK		 7565#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7566 /* If X is negative in MODE, sign-extend the value. */
9e69be8c
RK		 7567 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7568 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7569 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
9afa3d54
RK		 7570#endif
7571
230d793d
RS		 7572 return INTVAL (x);
7573
230d793d 7574 case MEM:
8baf60bb 7575#ifdef LOAD_EXTEND_OP
230d793d
RS		 7576 /* In many, if not most, RISC machines, reading a byte from memory
7577 zeros the rest of the register. Noticing that fact saves a lot
7578 of extra zero-extends. */
8baf60bb
RK		 7579 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7580 nonzero &= GET_MODE_MASK (GET_MODE (x));
230d793d 7581#endif
8baf60bb 7582 break;
230d793d 7583
230d793d
RS		 7584 case EQ: case NE:
7585 case GT: case GTU:
7586 case LT: case LTU:
7587 case GE: case GEU:
7588 case LE: case LEU:
3f508eca 7589
c6965c0f
RK		 7590 /* If this produces an integer result, we know which bits are set.
7591 Code here used to clear bits outside the mode of X, but that is
7592 now done above. */
230d793d 7593
c6965c0f
RK		 7594 if (GET_MODE_CLASS (mode) == MODE_INT
7595 && mode_width <= HOST_BITS_PER_WIDE_INT)
7596 nonzero = STORE_FLAG_VALUE;
230d793d 7597 break;
230d793d 7598
230d793d 7599 case NEG:
b3728b0e
JW		 7600#if 0
7601 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7602 and num_sign_bit_copies. */
d0ab8cd3
RK		 7603 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7604 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7605 nonzero = 1;
b3728b0e 7606#endif
230d793d
RS		 7607
7608 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
951553af 7609 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
230d793d 7610 break;
d0ab8cd3
RK		 7611
7612 case ABS:
b3728b0e
JW		 7613#if 0
7614 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7615 and num_sign_bit_copies. */
d0ab8cd3
RK		 7616 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7617 == GET_MODE_BITSIZE (GET_MODE (x)))
951553af 7618 nonzero = 1;
b3728b0e 7619#endif
d0ab8cd3 7620 break;
230d793d
RS		 7621
7622 case TRUNCATE:
951553af 7623 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
230d793d
RS		 7624 break;
7625
7626 case ZERO_EXTEND:
951553af 7627 nonzero &= nonzero_bits (XEXP (x, 0), mode);
230d793d 7628 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
951553af 7629 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
230d793d
RS		 7630 break;
7631
7632 case SIGN_EXTEND:
7633 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7634 Otherwise, show all the bits in the outer mode but not the inner
7635 may be non-zero. */
951553af 7636 inner_nz = nonzero_bits (XEXP (x, 0), mode);
230d793d
RS		 7637 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7638 {
951553af 7639 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
e3da301d
MS		 7640 if (inner_nz
7641 & (((HOST_WIDE_INT) 1
7642 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
951553af 7643 inner_nz |= (GET_MODE_MASK (mode)
230d793d
RS		 7644 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7645 }
7646
951553af 7647 nonzero &= inner_nz;
230d793d
RS		 7648 break;
7649
7650 case AND:
951553af
RK		 7651 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7652 & nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7653 break;
7654
d0ab8cd3
RK		 7655 case XOR: case IOR:
7656 case UMIN: case UMAX: case SMIN: case SMAX:
951553af
RK		 7657 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7658 | nonzero_bits (XEXP (x, 1), mode));
230d793d
RS		 7659 break;
7660
7661 case PLUS: case MINUS:
7662 case MULT:
7663 case DIV: case UDIV:
7664 case MOD: case UMOD:
7665 /* We can apply the rules of arithmetic to compute the number of
7666 high- and low-order zero bits of these operations. We start by
7667 computing the width (position of the highest-order non-zero bit)
7668 and the number of low-order zero bits for each value. */
7669 {
951553af
RK		 7670 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7671 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7672 int width0 = floor_log2 (nz0) + 1;
7673 int width1 = floor_log2 (nz1) + 1;
7674 int low0 = floor_log2 (nz0 & -nz0);
7675 int low1 = floor_log2 (nz1 & -nz1);
318b149c
RK		 7676 HOST_WIDE_INT op0_maybe_minusp
7677 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7678 HOST_WIDE_INT op1_maybe_minusp
7679 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
230d793d
RS		 7680 int result_width = mode_width;
7681 int result_low = 0;
7682
7683 switch (code)
7684 {
7685 case PLUS:
0e9ff885
DM		 7686#ifdef STACK_BIAS
7687 if (STACK_BIAS
7688 && (XEXP (x, 0) == stack_pointer_rtx
7689 || XEXP (x, 0) == frame_pointer_rtx)
7690 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7691 {
7692 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7693
7694 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7695 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7696 width0 = floor_log2 (nz0) + 1;
7697 width1 = floor_log2 (nz1) + 1;
7698 low0 = floor_log2 (nz0 & -nz0);
7699 low1 = floor_log2 (nz1 & -nz1);
7700 }
7701#endif
230d793d
RS		 7702 result_width = MAX (width0, width1) + 1;
7703 result_low = MIN (low0, low1);
7704 break;
7705 case MINUS:
7706 result_low = MIN (low0, low1);
7707 break;
7708 case MULT:
7709 result_width = width0 + width1;
7710 result_low = low0 + low1;
7711 break;
7712 case DIV:
7713 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7714 result_width = width0;
7715 break;
7716 case UDIV:
7717 result_width = width0;
7718 break;
7719 case MOD:
7720 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7721 result_width = MIN (width0, width1);
7722 result_low = MIN (low0, low1);
7723 break;
7724 case UMOD:
7725 result_width = MIN (width0, width1);
7726 result_low = MIN (low0, low1);
7727 break;
e9a25f70
JL		 7728 default:
7729 abort ();
230d793d
RS		 7730 }
7731
7732 if (result_width < mode_width)
951553af 7733 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
230d793d
RS		 7734
7735 if (result_low > 0)
951553af 7736 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
230d793d
RS		 7737 }
7738 break;
7739
7740 case ZERO_EXTRACT:
7741 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5f4f0e22 7742 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
951553af 7743 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
230d793d
RS		 7744 break;
7745
7746 case SUBREG:
c3c2cb37
RK		 7747 /* If this is a SUBREG formed for a promoted variable that has
7748 been zero-extended, we know that at least the high-order bits
7749 are zero, though others might be too. */
7750
7751 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
951553af
RK		 7752 nonzero = (GET_MODE_MASK (GET_MODE (x))
7753 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
c3c2cb37 7754
230d793d
RS		 7755 /* If the inner mode is a single word for both the host and target
7756 machines, we can compute this from which bits of the inner
951553af 7757 object might be nonzero. */
230d793d 7758 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5f4f0e22
CH		 7759 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7760 <= HOST_BITS_PER_WIDE_INT))
230d793d 7761 {
951553af 7762 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8baf60bb 7763
b52ce03d
R		 7764#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7765 /* If this is a typical RISC machine, we only have to worry
7766 about the way loads are extended. */
7767 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7768 ? (nonzero
7769 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7770 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
230d793d 7771#endif
b52ce03d
R		 7772 {
7773 /* On many CISC machines, accessing an object in a wider mode
7774 causes the high-order bits to become undefined. So they are
7775 not known to be zero. */
7776 if (GET_MODE_SIZE (GET_MODE (x))
7777 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7778 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7779 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7780 }
230d793d
RS		 7781 }
7782 break;
7783
7784 case ASHIFTRT:
7785 case LSHIFTRT:
7786 case ASHIFT:
230d793d 7787 case ROTATE:
951553af 7788 /* The nonzero bits are in two classes: any bits within MODE
230d793d 7789 that aren't in GET_MODE (x) are always significant. The rest of the
951553af 7790 nonzero bits are those that are significant in the operand of
230d793d
RS		 7791 the shift when shifted the appropriate number of bits. This
7792 shows that high-order bits are cleared by the right shift and
7793 low-order bits by left shifts. */
7794 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7795 && INTVAL (XEXP (x, 1)) >= 0
5f4f0e22 7796 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 7797 {
7798 enum machine_mode inner_mode = GET_MODE (x);
7799 int width = GET_MODE_BITSIZE (inner_mode);
7800 int count = INTVAL (XEXP (x, 1));
5f4f0e22 7801 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
951553af
RK		 7802 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7803 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5f4f0e22 7804 unsigned HOST_WIDE_INT outer = 0;
230d793d
RS		 7805
7806 if (mode_width > width)
951553af 7807 outer = (op_nonzero & nonzero & ~ mode_mask);
230d793d
RS		 7808
7809 if (code == LSHIFTRT)
7810 inner >>= count;
7811 else if (code == ASHIFTRT)
7812 {
7813 inner >>= count;
7814
951553af 7815 /* If the sign bit may have been nonzero before the shift, we
230d793d 7816 need to mark all the places it could have been copied to
951553af 7817 by the shift as possibly nonzero. */
5f4f0e22
CH		 7818 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7819 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
230d793d 7820 }
45620ed4 7821 else if (code == ASHIFT)
230d793d
RS		 7822 inner <<= count;
7823 else
7824 inner = ((inner << (count % width)
7825 | (inner >> (width - (count % width)))) & mode_mask);
7826
951553af 7827 nonzero &= (outer | inner);
230d793d
RS		 7828 }
7829 break;
7830
7831 case FFS:
7832 /* This is at most the number of bits in the mode. */
951553af 7833 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
230d793d 7834 break;
d0ab8cd3
RK		 7835
7836 case IF_THEN_ELSE:
951553af
RK		 7837 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7838 | nonzero_bits (XEXP (x, 2), mode));
d0ab8cd3 7839 break;
e9a25f70
JL		 7840
7841 default:
7842 break;
230d793d
RS		 7843 }
7844
951553af 7845 return nonzero;
230d793d 7846}
b3728b0e
JW		 7847
7848/* See the macro definition above. */
7849#undef num_sign_bit_copies
230d793d 7850\f
d0ab8cd3 7851/* Return the number of bits at the high-order end of X that are known to
5109d49f
RK		 7852 be equal to the sign bit. X will be used in mode MODE; if MODE is
7853 VOIDmode, X will be used in its own mode. The returned value will always
7854 be between 1 and the number of bits in MODE. */
d0ab8cd3
RK		 7855
7856static int
7857num_sign_bit_copies (x, mode)
7858 rtx x;
7859 enum machine_mode mode;
7860{
7861 enum rtx_code code = GET_CODE (x);
7862 int bitwidth;
7863 int num0, num1, result;
951553af 7864 unsigned HOST_WIDE_INT nonzero;
d0ab8cd3
RK		 7865 rtx tem;
7866
7867 /* If we weren't given a mode, use the mode of X. If the mode is still
1c75dfa4
RK		 7868 VOIDmode, we don't know anything. Likewise if one of the modes is
7869 floating-point. */
d0ab8cd3
RK		 7870
7871 if (mode == VOIDmode)
7872 mode = GET_MODE (x);
7873
1c75dfa4 7874 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
6752e8d2 7875 return 1;
d0ab8cd3
RK		 7876
7877 bitwidth = GET_MODE_BITSIZE (mode);
7878
0f41302f 7879 /* For a smaller object, just ignore the high bits. */
312def2e
RK		 7880 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7881 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7882 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7883
e9a25f70
JL		 7884 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7885 {
0c314d1a
RK		 7886#ifndef WORD_REGISTER_OPERATIONS
7887 /* If this machine does not do all register operations on the entire
7888 register and MODE is wider than the mode of X, we can say nothing
7889 at all about the high-order bits. */
e9a25f70
JL		 7890 return 1;
7891#else
7892 /* Likewise on machines that do, if the mode of the object is smaller
7893 than a word and loads of that size don't sign extend, we can say
7894 nothing about the high order bits. */
7895 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7896#ifdef LOAD_EXTEND_OP
7897 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7898#endif
7899 )
7900 return 1;
0c314d1a 7901#endif
e9a25f70 7902 }
0c314d1a 7903
d0ab8cd3
RK		 7904 switch (code)
7905 {
7906 case REG:
55310dad 7907
ff0dbdd1
RK		 7908#ifdef POINTERS_EXTEND_UNSIGNED
7909 /* If pointers extend signed and this is a pointer in Pmode, say that
7910 all the bits above ptr_mode are known to be sign bit copies. */
7911 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7912 && REGNO_POINTER_FLAG (REGNO (x)))
7913 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7914#endif
7915
55310dad
RK		 7916 if (reg_last_set_value[REGNO (x)] != 0
7917 && reg_last_set_mode[REGNO (x)] == mode
b1f21e0a 7918 && (REG_N_SETS (REGNO (x)) == 1
55310dad
RK		 7919 || reg_last_set_label[REGNO (x)] == label_tick)
7920 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7921 return reg_last_set_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7922
7923 tem = get_last_value (x);
7924 if (tem != 0)
7925 return num_sign_bit_copies (tem, mode);
55310dad
RK		 7926
7927 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7928 return reg_sign_bit_copies[REGNO (x)];
d0ab8cd3
RK		 7929 break;
7930
457816e2 7931 case MEM:
8baf60bb 7932#ifdef LOAD_EXTEND_OP
457816e2 7933 /* Some RISC machines sign-extend all loads of smaller than a word. */
8baf60bb
RK		 7934 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7935 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
457816e2 7936#endif
8baf60bb 7937 break;
457816e2 7938
d0ab8cd3
RK		 7939 case CONST_INT:
7940 /* If the constant is negative, take its 1's complement and remask.
7941 Then see how many zero bits we have. */
951553af 7942 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
ac49a949 7943 if (bitwidth <= HOST_BITS_PER_WIDE_INT
951553af
RK		 7944 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7945 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
d0ab8cd3 7946
951553af 7947 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 7948
7949 case SUBREG:
c3c2cb37
RK		 7950 /* If this is a SUBREG for a promoted object that is sign-extended
7951 and we are looking at it in a wider mode, we know that at least the
7952 high-order bits are known to be sign bit copies. */
7953
7954 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
dc3e17ad
RK		 7955 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7956 num_sign_bit_copies (SUBREG_REG (x), mode));
c3c2cb37 7957
0f41302f 7958 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7959 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7960 {
7961 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7962 return MAX (1, (num0
7963 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7964 - bitwidth)));
7965 }
457816e2 7966
8baf60bb 7967#ifdef WORD_REGISTER_OPERATIONS
2aec5b7a 7968#ifdef LOAD_EXTEND_OP
8baf60bb
RK		 7969 /* For paradoxical SUBREGs on machines where all register operations
7970 affect the entire register, just look inside. Note that we are
7971 passing MODE to the recursive call, so the number of sign bit copies
7972 will remain relative to that mode, not the inner mode. */
457816e2 7973
2aec5b7a
JW		 7974 /* This works only if loads sign extend. Otherwise, if we get a
7975 reload for the inner part, it may be loaded from the stack, and
7976 then we lose all sign bit copies that existed before the store
7977 to the stack. */
7978
7979 if ((GET_MODE_SIZE (GET_MODE (x))
7980 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7981 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
457816e2 7982 return num_sign_bit_copies (SUBREG_REG (x), mode);
2aec5b7a 7983#endif
457816e2 7984#endif
d0ab8cd3
RK		 7985 break;
7986
7987 case SIGN_EXTRACT:
7988 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7989 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7990 break;
7991
7992 case SIGN_EXTEND:
7993 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7994 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7995
7996 case TRUNCATE:
0f41302f 7997 /* For a smaller object, just ignore the high bits. */
d0ab8cd3
RK		 7998 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7999 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8000 - bitwidth)));
8001
8002 case NOT:
8003 return num_sign_bit_copies (XEXP (x, 0), mode);
8004
8005 case ROTATE: case ROTATERT:
8006 /* If we are rotating left by a number of bits less than the number
8007 of sign bit copies, we can just subtract that amount from the
8008 number. */
8009 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8010 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8011 {
8012 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8013 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8014 : bitwidth - INTVAL (XEXP (x, 1))));
8015 }
8016 break;
8017
8018 case NEG:
8019 /* In general, this subtracts one sign bit copy. But if the value
8020 is known to be positive, the number of sign bit copies is the
951553af
RK		 8021 same as that of the input. Finally, if the input has just one bit
8022 that might be nonzero, all the bits are copies of the sign bit. */
8023 nonzero = nonzero_bits (XEXP (x, 0), mode);
8024 if (nonzero == 1)
d0ab8cd3
RK		 8025 return bitwidth;
8026
8027 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8028 if (num0 > 1
ac49a949 8029 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8030 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
d0ab8cd3
RK		 8031 num0--;
8032
8033 return num0;
8034
8035 case IOR: case AND: case XOR:
8036 case SMIN: case SMAX: case UMIN: case UMAX:
8037 /* Logical operations will preserve the number of sign-bit copies.
8038 MIN and MAX operations always return one of the operands. */
8039 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8040 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8041 return MIN (num0, num1);
8042
8043 case PLUS: case MINUS:
8044 /* For addition and subtraction, we can have a 1-bit carry. However,
8045 if we are subtracting 1 from a positive number, there will not
8046 be such a carry. Furthermore, if the positive number is known to
8047 be 0 or 1, we know the result is either -1 or 0. */
8048
3e3ea975 8049 if (code == PLUS && XEXP (x, 1) == constm1_rtx
9295e6af 8050 && bitwidth <= HOST_BITS_PER_WIDE_INT)
d0ab8cd3 8051 {
951553af
RK		 8052 nonzero = nonzero_bits (XEXP (x, 0), mode);
8053 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8054 return (nonzero == 1 || nonzero == 0 ? bitwidth
8055 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8056 }
8057
8058 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8059 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8060 return MAX (1, MIN (num0, num1) - 1);
8061
8062 case MULT:
8063 /* The number of bits of the product is the sum of the number of
8064 bits of both terms. However, unless one of the terms if known
8065 to be positive, we must allow for an additional bit since negating
8066 a negative number can remove one sign bit copy. */
8067
8068 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8069 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8070
8071 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8072 if (result > 0
9295e6af 8073 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8074 && ((nonzero_bits (XEXP (x, 0), mode)
d0ab8cd3 8075 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
01c82bbb
RK		 8076 && ((nonzero_bits (XEXP (x, 1), mode)
8077 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
d0ab8cd3
RK		 8078 result--;
8079
8080 return MAX (1, result);
8081
8082 case UDIV:
8083 /* The result must be <= the first operand. */
8084 return num_sign_bit_copies (XEXP (x, 0), mode);
8085
8086 case UMOD:
8087 /* The result must be <= the scond operand. */
8088 return num_sign_bit_copies (XEXP (x, 1), mode);
8089
8090 case DIV:
8091 /* Similar to unsigned division, except that we have to worry about
8092 the case where the divisor is negative, in which case we have
8093 to add 1. */
8094 result = num_sign_bit_copies (XEXP (x, 0), mode);
8095 if (result > 1
ac49a949 8096 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8097 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 8098 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8099 result --;
8100
8101 return result;
8102
8103 case MOD:
8104 result = num_sign_bit_copies (XEXP (x, 1), mode);
8105 if (result > 1
ac49a949 8106 && bitwidth <= HOST_BITS_PER_WIDE_INT
951553af 8107 && (nonzero_bits (XEXP (x, 1), mode)
d0ab8cd3
RK		 8108 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8109 result --;
8110
8111 return result;
8112
8113 case ASHIFTRT:
8114 /* Shifts by a constant add to the number of bits equal to the
8115 sign bit. */
8116 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8117 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8118 && INTVAL (XEXP (x, 1)) > 0)
8119 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8120
8121 return num0;
8122
8123 case ASHIFT:
d0ab8cd3
RK		 8124 /* Left shifts destroy copies. */
8125 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8126 || INTVAL (XEXP (x, 1)) < 0
8127 || INTVAL (XEXP (x, 1)) >= bitwidth)
8128 return 1;
8129
8130 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8131 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8132
8133 case IF_THEN_ELSE:
8134 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8135 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8136 return MIN (num0, num1);
8137
d0ab8cd3
RK		 8138 case EQ: case NE: case GE: case GT: case LE: case LT:
8139 case GEU: case GTU: case LEU: case LTU:
0802d516
RK		 8140 if (STORE_FLAG_VALUE == -1)
8141 return bitwidth;
e9a25f70
JL		 8142 break;
8143
8144 default:
8145 break;
d0ab8cd3
RK		 8146 }
8147
8148 /* If we haven't been able to figure it out by one of the above rules,
8149 see if some of the high-order bits are known to be zero. If so,
ac49a949
RS		 8150 count those bits and return one less than that amount. If we can't
8151 safely compute the mask for this mode, always return BITWIDTH. */
8152
8153 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6752e8d2 8154 return 1;
d0ab8cd3 8155
951553af 8156 nonzero = nonzero_bits (x, mode);
df6f4086 8157 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
951553af 8158 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
d0ab8cd3
RK		 8159}
8160\f
1a26b032
RK		 8161/* Return the number of "extended" bits there are in X, when interpreted
8162 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8163 unsigned quantities, this is the number of high-order zero bits.
8164 For signed quantities, this is the number of copies of the sign bit
8165 minus 1. In both case, this function returns the number of "spare"
8166 bits. For example, if two quantities for which this function returns
8167 at least 1 are added, the addition is known not to overflow.
8168
8169 This function will always return 0 unless called during combine, which
8170 implies that it must be called from a define_split. */
8171
8172int
8173extended_count (x, mode, unsignedp)
8174 rtx x;
8175 enum machine_mode mode;
8176 int unsignedp;
8177{
951553af 8178 if (nonzero_sign_valid == 0)
1a26b032
RK		 8179 return 0;
8180
8181 return (unsignedp
ac49a949
RS		 8182 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8183 && (GET_MODE_BITSIZE (mode) - 1
951553af 8184 - floor_log2 (nonzero_bits (x, mode))))
1a26b032
RK		 8185 : num_sign_bit_copies (x, mode) - 1);
8186}
8187\f
230d793d
RS		 8188/* This function is called from `simplify_shift_const' to merge two
8189 outer operations. Specifically, we have already found that we need
8190 to perform operation *POP0 with constant *PCONST0 at the outermost
8191 position. We would now like to also perform OP1 with constant CONST1
8192 (with *POP0 being done last).
8193
8194 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8195 the resulting operation. *PCOMP_P is set to 1 if we would need to
8196 complement the innermost operand, otherwise it is unchanged.
8197
8198 MODE is the mode in which the operation will be done. No bits outside
8199 the width of this mode matter. It is assumed that the width of this mode
5f4f0e22 8200 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
230d793d
RS		 8201
8202 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8203 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8204 result is simply *PCONST0.
8205
8206 If the resulting operation cannot be expressed as one operation, we
8207 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8208
8209static int
8210merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8211 enum rtx_code *pop0;
5f4f0e22 8212 HOST_WIDE_INT *pconst0;
230d793d 8213 enum rtx_code op1;
5f4f0e22 8214 HOST_WIDE_INT const1;
230d793d
RS		 8215 enum machine_mode mode;
8216 int *pcomp_p;
8217{
8218 enum rtx_code op0 = *pop0;
5f4f0e22 8219 HOST_WIDE_INT const0 = *pconst0;
9fa6d012 8220 int width = GET_MODE_BITSIZE (mode);
230d793d
RS		 8221
8222 const0 &= GET_MODE_MASK (mode);
8223 const1 &= GET_MODE_MASK (mode);
8224
8225 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8226 if (op0 == AND)
8227 const1 &= const0;
8228
8229 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8230 if OP0 is SET. */
8231
8232 if (op1 == NIL || op0 == SET)
8233 return 1;
8234
8235 else if (op0 == NIL)
8236 op0 = op1, const0 = const1;
8237
8238 else if (op0 == op1)
8239 {
8240 switch (op0)
8241 {
8242 case AND:
8243 const0 &= const1;
8244 break;
8245 case IOR:
8246 const0 |= const1;
8247 break;
8248 case XOR:
8249 const0 ^= const1;
8250 break;
8251 case PLUS:
8252 const0 += const1;
8253 break;
8254 case NEG:
8255 op0 = NIL;
8256 break;
e9a25f70
JL		 8257 default:
8258 break;
230d793d
RS		 8259 }
8260 }
8261
8262 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8263 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8264 return 0;
8265
8266 /* If the two constants aren't the same, we can't do anything. The
8267 remaining six cases can all be done. */
8268 else if (const0 != const1)
8269 return 0;
8270
8271 else
8272 switch (op0)
8273 {
8274 case IOR:
8275 if (op1 == AND)
8276 /* (a & b) | b == b */
8277 op0 = SET;
8278 else /* op1 == XOR */
8279 /* (a ^ b) | b == a | b */
b729186a 8280 {;}
230d793d
RS		 8281 break;
8282
8283 case XOR:
8284 if (op1 == AND)
8285 /* (a & b) ^ b == (~a) & b */
8286 op0 = AND, *pcomp_p = 1;
8287 else /* op1 == IOR */
8288 /* (a | b) ^ b == a & ~b */
8289 op0 = AND, *pconst0 = ~ const0;
8290 break;
8291
8292 case AND:
8293 if (op1 == IOR)
8294 /* (a | b) & b == b */
8295 op0 = SET;
8296 else /* op1 == XOR */
8297 /* (a ^ b) & b) == (~a) & b */
8298 *pcomp_p = 1;
8299 break;
e9a25f70
JL		 8300 default:
8301 break;
230d793d
RS		 8302 }
8303
8304 /* Check for NO-OP cases. */
8305 const0 &= GET_MODE_MASK (mode);
8306 if (const0 == 0
8307 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8308 op0 = NIL;
8309 else if (const0 == 0 && op0 == AND)
8310 op0 = SET;
e51712db
KG		 8311 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8312 && op0 == AND)
230d793d
RS		 8313 op0 = NIL;
8314
9fa6d012
TG		 8315 /* If this would be an entire word for the target, but is not for
8316 the host, then sign-extend on the host so that the number will look
8317 the same way on the host that it would on the target.
8318
8319 For example, when building a 64 bit alpha hosted 32 bit sparc
8320 targeted compiler, then we want the 32 bit unsigned value -1 to be
8321 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8322 The later confuses the sparc backend. */
8323
8324 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8325 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8326 const0 |= ((HOST_WIDE_INT) (-1) << width);
8327
230d793d
RS		 8328 *pop0 = op0;
8329 *pconst0 = const0;
8330
8331 return 1;
8332}
8333\f
8334/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8335 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8336 that we started with.
8337
8338 The shift is normally computed in the widest mode we find in VAROP, as
8339 long as it isn't a different number of words than RESULT_MODE. Exceptions
8340 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8341
8342static rtx
8343simplify_shift_const (x, code, result_mode, varop, count)
8344 rtx x;
8345 enum rtx_code code;
8346 enum machine_mode result_mode;
8347 rtx varop;
8348 int count;
8349{
8350 enum rtx_code orig_code = code;
8351 int orig_count = count;
8352 enum machine_mode mode = result_mode;
8353 enum machine_mode shift_mode, tmode;
8354 int mode_words
8355 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8356 /* We form (outer_op (code varop count) (outer_const)). */
8357 enum rtx_code outer_op = NIL;
c4e861e8 8358 HOST_WIDE_INT outer_const = 0;
230d793d
RS		 8359 rtx const_rtx;
8360 int complement_p = 0;
8361 rtx new;
8362
8363 /* If we were given an invalid count, don't do anything except exactly
8364 what was requested. */
8365
8366 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8367 {
8368 if (x)
8369 return x;
8370
38a448ca 8371 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
230d793d
RS		 8372 }
8373
8374 /* Unless one of the branches of the `if' in this loop does a `continue',
8375 we will `break' the loop after the `if'. */
8376
8377 while (count != 0)
8378 {
8379 /* If we have an operand of (clobber (const_int 0)), just return that
8380 value. */
8381 if (GET_CODE (varop) == CLOBBER)
8382 return varop;
8383
8384 /* If we discovered we had to complement VAROP, leave. Making a NOT
8385 here would cause an infinite loop. */
8386 if (complement_p)
8387 break;
8388
abc95ed3 8389 /* Convert ROTATERT to ROTATE. */
230d793d
RS		 8390 if (code == ROTATERT)
8391 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8392
230d793d 8393 /* We need to determine what mode we will do the shift in. If the
f6789c77
RK		 8394 shift is a right shift or a ROTATE, we must always do it in the mode
8395 it was originally done in. Otherwise, we can do it in MODE, the
0f41302f 8396 widest mode encountered. */
f6789c77
RK		 8397 shift_mode
8398 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8399 ? result_mode : mode);
230d793d
RS		 8400
8401 /* Handle cases where the count is greater than the size of the mode
8402 minus 1. For ASHIFT, use the size minus one as the count (this can
8403 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8404 take the count modulo the size. For other shifts, the result is
8405 zero.
8406
8407 Since these shifts are being produced by the compiler by combining
8408 multiple operations, each of which are defined, we know what the
8409 result is supposed to be. */
8410
8411 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8412 {
8413 if (code == ASHIFTRT)
8414 count = GET_MODE_BITSIZE (shift_mode) - 1;
8415 else if (code == ROTATE || code == ROTATERT)
8416 count %= GET_MODE_BITSIZE (shift_mode);
8417 else
8418 {
8419 /* We can't simply return zero because there may be an
8420 outer op. */
8421 varop = const0_rtx;
8422 count = 0;
8423 break;
8424 }
8425 }
8426
8427 /* Negative counts are invalid and should not have been made (a
8428 programmer-specified negative count should have been handled
0f41302f 8429 above). */
230d793d
RS		 8430 else if (count < 0)
8431 abort ();
8432
312def2e
RK		 8433 /* An arithmetic right shift of a quantity known to be -1 or 0
8434 is a no-op. */
8435 if (code == ASHIFTRT
8436 && (num_sign_bit_copies (varop, shift_mode)
8437 == GET_MODE_BITSIZE (shift_mode)))
d0ab8cd3 8438 {
312def2e
RK		 8439 count = 0;
8440 break;
8441 }
d0ab8cd3 8442
312def2e
RK		 8443 /* If we are doing an arithmetic right shift and discarding all but
8444 the sign bit copies, this is equivalent to doing a shift by the
8445 bitsize minus one. Convert it into that shift because it will often
8446 allow other simplifications. */
500c518b 8447
312def2e
RK		 8448 if (code == ASHIFTRT
8449 && (count + num_sign_bit_copies (varop, shift_mode)
8450 >= GET_MODE_BITSIZE (shift_mode)))
8451 count = GET_MODE_BITSIZE (shift_mode) - 1;
500c518b 8452
230d793d
RS		 8453 /* We simplify the tests below and elsewhere by converting
8454 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8455 `make_compound_operation' will convert it to a ASHIFTRT for
8456 those machines (such as Vax) that don't have a LSHIFTRT. */
5f4f0e22 8457 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8458 && code == ASHIFTRT
951553af 8459 && ((nonzero_bits (varop, shift_mode)
5f4f0e22
CH		 8460 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8461 == 0))
230d793d
RS		 8462 code = LSHIFTRT;
8463
8464 switch (GET_CODE (varop))
8465 {
8466 case SIGN_EXTEND:
8467 case ZERO_EXTEND:
8468 case SIGN_EXTRACT:
8469 case ZERO_EXTRACT:
8470 new = expand_compound_operation (varop);
8471 if (new != varop)
8472 {
8473 varop = new;
8474 continue;
8475 }
8476 break;
8477
8478 case MEM:
8479 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8480 minus the width of a smaller mode, we can do this with a
8481 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8482 if ((code == ASHIFTRT || code == LSHIFTRT)
8483 && ! mode_dependent_address_p (XEXP (varop, 0))
8484 && ! MEM_VOLATILE_P (varop)
8485 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8486 MODE_INT, 1)) != BLKmode)
8487 {
f76b9db2 8488 if (BYTES_BIG_ENDIAN)
38a448ca 8489 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
f76b9db2 8490 else
38a448ca
RH		 8491 new = gen_rtx_MEM (tmode,
8492 plus_constant (XEXP (varop, 0),
8493 count / BITS_PER_UNIT));
e24b00c8
ILT		 8494 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8495 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8496 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
230d793d
RS		 8497 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8498 : ZERO_EXTEND, mode, new);
8499 count = 0;
8500 continue;
8501 }
8502 break;
8503
8504 case USE:
8505 /* Similar to the case above, except that we can only do this if
8506 the resulting mode is the same as that of the underlying
8507 MEM and adjust the address depending on the *bits* endianness
8508 because of the way that bit-field extract insns are defined. */
8509 if ((code == ASHIFTRT || code == LSHIFTRT)
8510 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8511 MODE_INT, 1)) != BLKmode
8512 && tmode == GET_MODE (XEXP (varop, 0)))
8513 {
f76b9db2
ILT		 8514 if (BITS_BIG_ENDIAN)
8515 new = XEXP (varop, 0);
8516 else
8517 {
8518 new = copy_rtx (XEXP (varop, 0));
8519 SUBST (XEXP (new, 0),
8520 plus_constant (XEXP (new, 0),
8521 count / BITS_PER_UNIT));
8522 }
230d793d
RS		 8523
8524 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8525 : ZERO_EXTEND, mode, new);
8526 count = 0;
8527 continue;
8528 }
8529 break;
8530
8531 case SUBREG:
8532 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8533 the same number of words as what we've seen so far. Then store
8534 the widest mode in MODE. */
f9e67232
RS		 8535 if (subreg_lowpart_p (varop)
8536 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8537 > GET_MODE_SIZE (GET_MODE (varop)))
230d793d
RS		 8538 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8539 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8540 == mode_words))
8541 {
8542 varop = SUBREG_REG (varop);
8543 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8544 mode = GET_MODE (varop);
8545 continue;
8546 }
8547 break;
8548
8549 case MULT:
8550 /* Some machines use MULT instead of ASHIFT because MULT
8551 is cheaper. But it is still better on those machines to
8552 merge two shifts into one. */
8553 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8554 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8555 {
8556 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8557 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
230d793d
RS		 8558 continue;
8559 }
8560 break;
8561
8562 case UDIV:
8563 /* Similar, for when divides are cheaper. */
8564 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8565 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8566 {
8567 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5f4f0e22 8568 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
230d793d
RS		 8569 continue;
8570 }
8571 break;
8572
8573 case ASHIFTRT:
8574 /* If we are extracting just the sign bit of an arithmetic right
8575 shift, that shift is not needed. */
8576 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8577 {
8578 varop = XEXP (varop, 0);
8579 continue;
8580 }
8581
0f41302f 8582 /* ... fall through ... */
230d793d
RS		 8583
8584 case LSHIFTRT:
8585 case ASHIFT:
230d793d
RS		 8586 case ROTATE:
8587 /* Here we have two nested shifts. The result is usually the
8588 AND of a new shift with a mask. We compute the result below. */
8589 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8590 && INTVAL (XEXP (varop, 1)) >= 0
8591 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5f4f0e22
CH		 8592 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8593 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d
RS		 8594 {
8595 enum rtx_code first_code = GET_CODE (varop);
8596 int first_count = INTVAL (XEXP (varop, 1));
5f4f0e22 8597 unsigned HOST_WIDE_INT mask;
230d793d 8598 rtx mask_rtx;
230d793d 8599
230d793d
RS		 8600 /* We have one common special case. We can't do any merging if
8601 the inner code is an ASHIFTRT of a smaller mode. However, if
8602 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8603 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8604 we can convert it to
8605 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8606 This simplifies certain SIGN_EXTEND operations. */
8607 if (code == ASHIFT && first_code == ASHIFTRT
8608 && (GET_MODE_BITSIZE (result_mode)
8609 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8610 {
8611 /* C3 has the low-order C1 bits zero. */
8612
5f4f0e22
CH		 8613 mask = (GET_MODE_MASK (mode)
8614 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
230d793d 8615
5f4f0e22 8616 varop = simplify_and_const_int (NULL_RTX, result_mode,
230d793d 8617 XEXP (varop, 0), mask);
5f4f0e22 8618 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
230d793d
RS		 8619 varop, count);
8620 count = first_count;
8621 code = ASHIFTRT;
8622 continue;
8623 }
8624
d0ab8cd3
RK		 8625 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8626 than C1 high-order bits equal to the sign bit, we can convert
8627 this to either an ASHIFT or a ASHIFTRT depending on the
8628 two counts.
230d793d
RS		 8629
8630 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8631
8632 if (code == ASHIFTRT && first_code == ASHIFT
8633 && GET_MODE (varop) == shift_mode
d0ab8cd3
RK		 8634 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8635 > first_count))
230d793d 8636 {
d0ab8cd3
RK		 8637 count -= first_count;
8638 if (count < 0)
8639 count = - count, code = ASHIFT;
8640 varop = XEXP (varop, 0);
8641 continue;
230d793d
RS		 8642 }
8643
8644 /* There are some cases we can't do. If CODE is ASHIFTRT,
8645 we can only do this if FIRST_CODE is also ASHIFTRT.
8646
8647 We can't do the case when CODE is ROTATE and FIRST_CODE is
8648 ASHIFTRT.
8649
8650 If the mode of this shift is not the mode of the outer shift,
bdaae9a0 8651 we can't do this if either shift is a right shift or ROTATE.
230d793d
RS		 8652
8653 Finally, we can't do any of these if the mode is too wide
8654 unless the codes are the same.
8655
8656 Handle the case where the shift codes are the same
8657 first. */
8658
8659 if (code == first_code)
8660 {
8661 if (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8662 && (code == ASHIFTRT || code == LSHIFTRT
8663 || code == ROTATE))
230d793d
RS		 8664 break;
8665
8666 count += first_count;
8667 varop = XEXP (varop, 0);
8668 continue;
8669 }
8670
8671 if (code == ASHIFTRT
8672 || (code == ROTATE && first_code == ASHIFTRT)
5f4f0e22 8673 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
230d793d 8674 || (GET_MODE (varop) != result_mode
bdaae9a0
RK		 8675 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8676 || first_code == ROTATE
230d793d
RS		 8677 || code == ROTATE)))
8678 break;
8679
8680 /* To compute the mask to apply after the shift, shift the
951553af 8681 nonzero bits of the inner shift the same way the
230d793d
RS		 8682 outer shift will. */
8683
951553af 8684 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
230d793d
RS		 8685
8686 mask_rtx
8687 = simplify_binary_operation (code, result_mode, mask_rtx,
5f4f0e22 8688 GEN_INT (count));
230d793d
RS		 8689
8690 /* Give up if we can't compute an outer operation to use. */
8691 if (mask_rtx == 0
8692 || GET_CODE (mask_rtx) != CONST_INT
8693 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8694 INTVAL (mask_rtx),
8695 result_mode, &complement_p))
8696 break;
8697
8698 /* If the shifts are in the same direction, we add the
8699 counts. Otherwise, we subtract them. */
8700 if ((code == ASHIFTRT || code == LSHIFTRT)
8701 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8702 count += first_count;
8703 else
8704 count -= first_count;
8705
8706 /* If COUNT is positive, the new shift is usually CODE,
8707 except for the two exceptions below, in which case it is
8708 FIRST_CODE. If the count is negative, FIRST_CODE should
8709 always be used */
8710 if (count > 0
8711 && ((first_code == ROTATE && code == ASHIFT)
8712 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8713 code = first_code;
8714 else if (count < 0)
8715 code = first_code, count = - count;
8716
8717 varop = XEXP (varop, 0);
8718 continue;
8719 }
8720
8721 /* If we have (A << B << C) for any shift, we can convert this to
8722 (A << C << B). This wins if A is a constant. Only try this if
8723 B is not a constant. */
8724
8725 else if (GET_CODE (varop) == code
8726 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8727 && 0 != (new
8728 = simplify_binary_operation (code, mode,
8729 XEXP (varop, 0),
5f4f0e22 8730 GEN_INT (count))))
230d793d
RS		 8731 {
8732 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8733 count = 0;
8734 continue;
8735 }
8736 break;
8737
8738 case NOT:
8739 /* Make this fit the case below. */
8740 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5f4f0e22 8741 GEN_INT (GET_MODE_MASK (mode)));
230d793d
RS		 8742 continue;
8743
8744 case IOR:
8745 case AND:
8746 case XOR:
8747 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8748 with C the size of VAROP - 1 and the shift is logical if
8749 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8750 we have an (le X 0) operation. If we have an arithmetic shift
8751 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8752 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8753
8754 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8755 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8756 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8757 && (code == LSHIFTRT || code == ASHIFTRT)
8758 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8759 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8760 {
8761 count = 0;
8762 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8763 const0_rtx);
8764
8765 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8766 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8767
8768 continue;
8769 }
8770
8771 /* If we have (shift (logical)), move the logical to the outside
8772 to allow it to possibly combine with another logical and the
8773 shift to combine with another shift. This also canonicalizes to
8774 what a ZERO_EXTRACT looks like. Also, some machines have
8775 (and (shift)) insns. */
8776
8777 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8778 && (new = simplify_binary_operation (code, result_mode,
8779 XEXP (varop, 1),
5f4f0e22 8780 GEN_INT (count))) != 0
7d171a1e 8781 && GET_CODE(new) == CONST_INT
230d793d
RS		 8782 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8783 INTVAL (new), result_mode, &complement_p))
8784 {
8785 varop = XEXP (varop, 0);
8786 continue;
8787 }
8788
8789 /* If we can't do that, try to simplify the shift in each arm of the
8790 logical expression, make a new logical expression, and apply
8791 the inverse distributive law. */
8792 {
00d4ca1c 8793 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d 8794 XEXP (varop, 0), count);
00d4ca1c 8795 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
230d793d
RS		 8796 XEXP (varop, 1), count);
8797
21a64bf1 8798 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
230d793d
RS		 8799 varop = apply_distributive_law (varop);
8800
8801 count = 0;
8802 }
8803 break;
8804
8805 case EQ:
45620ed4 8806 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
230d793d 8807 says that the sign bit can be tested, FOO has mode MODE, C is
45620ed4
RK		 8808 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8809 that may be nonzero. */
8810 if (code == LSHIFTRT
230d793d
RS		 8811 && XEXP (varop, 1) == const0_rtx
8812 && GET_MODE (XEXP (varop, 0)) == result_mode
8813 && count == GET_MODE_BITSIZE (result_mode) - 1
5f4f0e22 8814 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
230d793d 8815 && ((STORE_FLAG_VALUE
5f4f0e22 8816 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
951553af 8817 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8818 && merge_outer_ops (&outer_op, &outer_const, XOR,
8819 (HOST_WIDE_INT) 1, result_mode,
8820 &complement_p))
230d793d
RS		 8821 {
8822 varop = XEXP (varop, 0);
8823 count = 0;
8824 continue;
8825 }
8826 break;
8827
8828 case NEG:
d0ab8cd3
RK		 8829 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8830 than the number of bits in the mode is equivalent to A. */
8831 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
951553af 8832 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
230d793d 8833 {
d0ab8cd3 8834 varop = XEXP (varop, 0);
230d793d
RS		 8835 count = 0;
8836 continue;
8837 }
8838
8839 /* NEG commutes with ASHIFT since it is multiplication. Move the
8840 NEG outside to allow shifts to combine. */
8841 if (code == ASHIFT
5f4f0e22
CH		 8842 && merge_outer_ops (&outer_op, &outer_const, NEG,
8843 (HOST_WIDE_INT) 0, result_mode,
8844 &complement_p))
230d793d
RS		 8845 {
8846 varop = XEXP (varop, 0);
8847 continue;
8848 }
8849 break;
8850
8851 case PLUS:
d0ab8cd3
RK		 8852 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8853 is one less than the number of bits in the mode is
8854 equivalent to (xor A 1). */
230d793d
RS		 8855 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8856 && XEXP (varop, 1) == constm1_rtx
951553af 8857 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
5f4f0e22
CH		 8858 && merge_outer_ops (&outer_op, &outer_const, XOR,
8859 (HOST_WIDE_INT) 1, result_mode,
8860 &complement_p))
230d793d
RS		 8861 {
8862 count = 0;
8863 varop = XEXP (varop, 0);
8864 continue;
8865 }
8866
3f508eca 8867 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
951553af 8868 that might be nonzero in BAR are those being shifted out and those
3f508eca
RK		 8869 bits are known zero in FOO, we can replace the PLUS with FOO.
8870 Similarly in the other operand order. This code occurs when
8871 we are computing the size of a variable-size array. */
8872
8873 if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8874 && count < HOST_BITS_PER_WIDE_INT
951553af
RK		 8875 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8876 && (nonzero_bits (XEXP (varop, 1), result_mode)
8877 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
3f508eca
RK		 8878 {
8879 varop = XEXP (varop, 0);
8880 continue;
8881 }
8882 else if ((code == ASHIFTRT || code == LSHIFTRT)
5f4f0e22 8883 && count < HOST_BITS_PER_WIDE_INT
ac49a949 8884 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
951553af 8885 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
3f508eca 8886 >> count)
951553af
RK		 8887 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8888 & nonzero_bits (XEXP (varop, 1),
3f508eca
RK		 8889 result_mode)))
8890 {
8891 varop = XEXP (varop, 1);
8892 continue;
8893 }
8894
230d793d
RS		 8895 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8896 if (code == ASHIFT
8897 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8898 && (new = simplify_binary_operation (ASHIFT, result_mode,
8899 XEXP (varop, 1),
5f4f0e22 8900 GEN_INT (count))) != 0
7d171a1e 8901 && GET_CODE(new) == CONST_INT
230d793d
RS		 8902 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8903 INTVAL (new), result_mode, &complement_p))
8904 {
8905 varop = XEXP (varop, 0);
8906 continue;
8907 }
8908 break;
8909
8910 case MINUS:
8911 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8912 with C the size of VAROP - 1 and the shift is logical if
8913 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8914 we have a (gt X 0) operation. If the shift is arithmetic with
8915 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8916 we have a (neg (gt X 0)) operation. */
8917
0802d516
RK		 8918 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8919 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
230d793d 8920 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
230d793d
RS		 8921 && (code == LSHIFTRT || code == ASHIFTRT)
8922 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8923 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8924 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8925 {
8926 count = 0;
8927 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8928 const0_rtx);
8929
8930 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8931 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8932
8933 continue;
8934 }
8935 break;
6e0ef100
JC		 8936
8937 case TRUNCATE:
8938 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8939 if the truncate does not affect the value. */
8940 if (code == LSHIFTRT
8941 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8942 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8943 && (INTVAL (XEXP (XEXP (varop, 0), 1))
b577a8ff
JL		 8944 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8945 - GET_MODE_BITSIZE (GET_MODE (varop)))))
6e0ef100
JC		 8946 {
8947 rtx varop_inner = XEXP (varop, 0);
8948
8949 varop_inner = gen_rtx_combine (LSHIFTRT,
8950 GET_MODE (varop_inner),
8951 XEXP (varop_inner, 0),
8952 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8953 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8954 varop_inner);
8955 count = 0;
8956 continue;
8957 }
8958 break;
e9a25f70
JL		 8959
8960 default:
8961 break;
230d793d
RS		 8962 }
8963
8964 break;
8965 }
8966
8967 /* We need to determine what mode to do the shift in. If the shift is
f6789c77
RK		 8968 a right shift or ROTATE, we must always do it in the mode it was
8969 originally done in. Otherwise, we can do it in MODE, the widest mode
8970 encountered. The code we care about is that of the shift that will
8971 actually be done, not the shift that was originally requested. */
8972 shift_mode
8973 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8974 ? result_mode : mode);
230d793d
RS		 8975
8976 /* We have now finished analyzing the shift. The result should be
8977 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8978 OUTER_OP is non-NIL, it is an operation that needs to be applied
8979 to the result of the shift. OUTER_CONST is the relevant constant,
8980 but we must turn off all bits turned off in the shift.
8981
8982 If we were passed a value for X, see if we can use any pieces of
8983 it. If not, make new rtx. */
8984
8985 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8986 && GET_CODE (XEXP (x, 1)) == CONST_INT
8987 && INTVAL (XEXP (x, 1)) == count)
8988 const_rtx = XEXP (x, 1);
8989 else
5f4f0e22 8990 const_rtx = GEN_INT (count);
230d793d
RS		 8991
8992 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8993 && GET_MODE (XEXP (x, 0)) == shift_mode
8994 && SUBREG_REG (XEXP (x, 0)) == varop)
8995 varop = XEXP (x, 0);
8996 else if (GET_MODE (varop) != shift_mode)
8997 varop = gen_lowpart_for_combine (shift_mode, varop);
8998
0f41302f 8999 /* If we can't make the SUBREG, try to return what we were given. */
230d793d
RS		 9000 if (GET_CODE (varop) == CLOBBER)
9001 return x ? x : varop;
9002
9003 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9004 if (new != 0)
9005 x = new;
9006 else
9007 {
9008 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9009 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9010
9011 SUBST (XEXP (x, 0), varop);
9012 SUBST (XEXP (x, 1), const_rtx);
9013 }
9014
224eeff2
RK		 9015 /* If we have an outer operation and we just made a shift, it is
9016 possible that we could have simplified the shift were it not
9017 for the outer operation. So try to do the simplification
9018 recursively. */
9019
9020 if (outer_op != NIL && GET_CODE (x) == code
9021 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9022 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9023 INTVAL (XEXP (x, 1)));
9024
230d793d
RS		 9025 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9026 turn off all the bits that the shift would have turned off. */
9027 if (orig_code == LSHIFTRT && result_mode != shift_mode)
5f4f0e22 9028 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
230d793d
RS		 9029 GET_MODE_MASK (result_mode) >> orig_count);
9030
9031 /* Do the remainder of the processing in RESULT_MODE. */
9032 x = gen_lowpart_for_combine (result_mode, x);
9033
9034 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9035 operation. */
9036 if (complement_p)
0c1c8ea6 9037 x = gen_unary (NOT, result_mode, result_mode, x);
230d793d
RS		 9038
9039 if (outer_op != NIL)
9040 {
5f4f0e22 9041 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9fa6d012
TG		 9042 {
9043 int width = GET_MODE_BITSIZE (result_mode);
9044
9045 outer_const &= GET_MODE_MASK (result_mode);
9046
9047 /* If this would be an entire word for the target, but is not for
9048 the host, then sign-extend on the host so that the number will
9049 look the same way on the host that it would on the target.
9050
9051 For example, when building a 64 bit alpha hosted 32 bit sparc
9052 targeted compiler, then we want the 32 bit unsigned value -1 to be
9053 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
9054 The later confuses the sparc backend. */
9055
9056 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
9057 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
9058 outer_const |= ((HOST_WIDE_INT) (-1) << width);
9059 }
230d793d
RS		 9060
9061 if (outer_op == AND)
5f4f0e22 9062 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
230d793d
RS		 9063 else if (outer_op == SET)
9064 /* This means that we have determined that the result is
9065 equivalent to a constant. This should be rare. */
5f4f0e22 9066 x = GEN_INT (outer_const);
230d793d 9067 else if (GET_RTX_CLASS (outer_op) == '1')
0c1c8ea6 9068 x = gen_unary (outer_op, result_mode, result_mode, x);
230d793d 9069 else
5f4f0e22 9070 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
230d793d
RS		 9071 }
9072
9073 return x;
9074}
9075\f
9076/* Like recog, but we receive the address of a pointer to a new pattern.
9077 We try to match the rtx that the pointer points to.
9078 If that fails, we may try to modify or replace the pattern,
9079 storing the replacement into the same pointer object.
9080
9081 Modifications include deletion or addition of CLOBBERs.
9082
9083 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9084 the CLOBBERs are placed.
9085
9086 The value is the final insn code from the pattern ultimately matched,
9087 or -1. */
9088
9089static int
8e2f6e35 9090recog_for_combine (pnewpat, insn, pnotes)
230d793d
RS		 9091 rtx *pnewpat;
9092 rtx insn;
9093 rtx *pnotes;
9094{
9095 register rtx pat = *pnewpat;
9096 int insn_code_number;
9097 int num_clobbers_to_add = 0;
9098 int i;
9099 rtx notes = 0;
9100
974f4146
RK		 9101 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9102 we use to indicate that something didn't match. If we find such a
9103 thing, force rejection. */
d96023cf 9104 if (GET_CODE (pat) == PARALLEL)
974f4146 9105 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
d96023cf
RK		 9106 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9107 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
974f4146
RK		 9108 return -1;
9109
230d793d
RS		 9110 /* Is the result of combination a valid instruction? */
9111 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9112
9113 /* If it isn't, there is the possibility that we previously had an insn
9114 that clobbered some register as a side effect, but the combined
9115 insn doesn't need to do that. So try once more without the clobbers
9116 unless this represents an ASM insn. */
9117
9118 if (insn_code_number < 0 && ! check_asm_operands (pat)
9119 && GET_CODE (pat) == PARALLEL)
9120 {
9121 int pos;
9122
9123 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9124 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9125 {
9126 if (i != pos)
9127 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9128 pos++;
9129 }
9130
9131 SUBST_INT (XVECLEN (pat, 0), pos);
9132
9133 if (pos == 1)
9134 pat = XVECEXP (pat, 0, 0);
9135
9136 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9137 }
9138
9139 /* If we had any clobbers to add, make a new pattern than contains
9140 them. Then check to make sure that all of them are dead. */
9141 if (num_clobbers_to_add)
9142 {
38a448ca
RH		 9143 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9144 gen_rtvec (GET_CODE (pat) == PARALLEL
9145 ? XVECLEN (pat, 0) + num_clobbers_to_add
9146 : num_clobbers_to_add + 1));
230d793d
RS		 9147
9148 if (GET_CODE (pat) == PARALLEL)
9149 for (i = 0; i < XVECLEN (pat, 0); i++)
9150 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9151 else
9152 XVECEXP (newpat, 0, 0) = pat;
9153
9154 add_clobbers (newpat, insn_code_number);
9155
9156 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9157 i < XVECLEN (newpat, 0); i++)
9158 {
9159 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9160 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9161 return -1;
38a448ca
RH		 9162 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9163 XEXP (XVECEXP (newpat, 0, i), 0), notes);
230d793d
RS		 9164 }
9165 pat = newpat;
9166 }
9167
9168 *pnewpat = pat;
9169 *pnotes = notes;
9170
9171 return insn_code_number;
9172}
9173\f
9174/* Like gen_lowpart but for use by combine. In combine it is not possible
9175 to create any new pseudoregs. However, it is safe to create
9176 invalid memory addresses, because combine will try to recognize
9177 them and all they will do is make the combine attempt fail.
9178
9179 If for some reason this cannot do its job, an rtx
9180 (clobber (const_int 0)) is returned.
9181 An insn containing that will not be recognized. */
9182
9183#undef gen_lowpart
9184
9185static rtx
9186gen_lowpart_for_combine (mode, x)
9187 enum machine_mode mode;
9188 register rtx x;
9189{
9190 rtx result;
9191
9192 if (GET_MODE (x) == mode)
9193 return x;
9194
eae957a8
RK		 9195 /* We can only support MODE being wider than a word if X is a
9196 constant integer or has a mode the same size. */
9197
9198 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9199 && ! ((GET_MODE (x) == VOIDmode
9200 && (GET_CODE (x) == CONST_INT
9201 || GET_CODE (x) == CONST_DOUBLE))
9202 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
38a448ca 9203 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9204
9205 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9206 won't know what to do. So we will strip off the SUBREG here and
9207 process normally. */
9208 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9209 {
9210 x = SUBREG_REG (x);
9211 if (GET_MODE (x) == mode)
9212 return x;
9213 }
9214
9215 result = gen_lowpart_common (mode, x);
64bf47a2
RK		 9216 if (result != 0
9217 && GET_CODE (result) == SUBREG
9218 && GET_CODE (SUBREG_REG (result)) == REG
9219 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9220 && (GET_MODE_SIZE (GET_MODE (result))
9221 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
b1f21e0a 9222 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
64bf47a2 9223
230d793d
RS		 9224 if (result)
9225 return result;
9226
9227 if (GET_CODE (x) == MEM)
9228 {
9229 register int offset = 0;
9230 rtx new;
9231
9232 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9233 address. */
9234 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
38a448ca 9235 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 9236
9237 /* If we want to refer to something bigger than the original memref,
9238 generate a perverse subreg instead. That will force a reload
9239 of the original memref X. */
9240 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
38a448ca 9241 return gen_rtx_SUBREG (mode, x, 0);
230d793d 9242
f76b9db2
ILT		 9243 if (WORDS_BIG_ENDIAN)
9244 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9245 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9246 if (BYTES_BIG_ENDIAN)
9247 {
9248 /* Adjust the address so that the address-after-the-data is
9249 unchanged. */
9250 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9251 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9252 }
38a448ca 9253 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
230d793d
RS		 9254 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9255 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
9256 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
9257 return new;
9258 }
9259
9260 /* If X is a comparison operator, rewrite it in a new mode. This
9261 probably won't match, but may allow further simplifications. */
9262 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9263 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9264
9265 /* If we couldn't simplify X any other way, just enclose it in a
9266 SUBREG. Normally, this SUBREG won't match, but some patterns may
a7c99304 9267 include an explicit SUBREG or we may simplify it further in combine. */
230d793d 9268 else
dfbe1b2f
RK		 9269 {
9270 int word = 0;
9271
9272 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9273 word = ((GET_MODE_SIZE (GET_MODE (x))
9274 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9275 / UNITS_PER_WORD);
38a448ca 9276 return gen_rtx_SUBREG (mode, x, word);
dfbe1b2f 9277 }
230d793d
RS		 9278}
9279\f
9280/* Make an rtx expression. This is a subset of gen_rtx and only supports
9281 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9282
9283 If the identical expression was previously in the insn (in the undobuf),
9284 it will be returned. Only if it is not found will a new expression
9285 be made. */
9286
9287/*VARARGS2*/
9288static rtx
4f90e4a0 9289gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
230d793d 9290{
4f90e4a0 9291#ifndef __STDC__
230d793d
RS		 9292 enum rtx_code code;
9293 enum machine_mode mode;
4f90e4a0
RK		 9294#endif
9295 va_list p;
230d793d
RS		 9296 int n_args;
9297 rtx args[3];
b729186a 9298 int j;
230d793d
RS		 9299 char *fmt;
9300 rtx rt;
241cea85 9301 struct undo *undo;
230d793d 9302
4f90e4a0
RK		 9303 VA_START (p, mode);
9304
9305#ifndef __STDC__
230d793d
RS		 9306 code = va_arg (p, enum rtx_code);
9307 mode = va_arg (p, enum machine_mode);
4f90e4a0
RK		 9308#endif
9309
230d793d
RS		 9310 n_args = GET_RTX_LENGTH (code);
9311 fmt = GET_RTX_FORMAT (code);
9312
9313 if (n_args == 0 || n_args > 3)
9314 abort ();
9315
9316 /* Get each arg and verify that it is supposed to be an expression. */
9317 for (j = 0; j < n_args; j++)
9318 {
9319 if (*fmt++ != 'e')
9320 abort ();
9321
9322 args[j] = va_arg (p, rtx);
9323 }
9324
9325 /* See if this is in undobuf. Be sure we don't use objects that came
9326 from another insn; this could produce circular rtl structures. */
9327
241cea85
RK		 9328 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9329 if (!undo->is_int
9330 && GET_CODE (undo->old_contents.r) == code
9331 && GET_MODE (undo->old_contents.r) == mode)
230d793d
RS		 9332 {
9333 for (j = 0; j < n_args; j++)
241cea85 9334 if (XEXP (undo->old_contents.r, j) != args[j])
230d793d
RS		 9335 break;
9336
9337 if (j == n_args)
241cea85 9338 return undo->old_contents.r;
230d793d
RS		 9339 }
9340
9341 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9342 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9343 rt = rtx_alloc (code);
9344 PUT_MODE (rt, mode);
9345 XEXP (rt, 0) = args[0];
9346 if (n_args > 1)
9347 {
9348 XEXP (rt, 1) = args[1];
9349 if (n_args > 2)
9350 XEXP (rt, 2) = args[2];
9351 }
9352 return rt;
9353}
9354
9355/* These routines make binary and unary operations by first seeing if they
9356 fold; if not, a new expression is allocated. */
9357
9358static rtx
9359gen_binary (code, mode, op0, op1)
9360 enum rtx_code code;
9361 enum machine_mode mode;
9362 rtx op0, op1;
9363{
9364 rtx result;
1a26b032
RK		 9365 rtx tem;
9366
9367 if (GET_RTX_CLASS (code) == 'c'
9368 && (GET_CODE (op0) == CONST_INT
9369 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9370 tem = op0, op0 = op1, op1 = tem;
230d793d
RS		 9371
9372 if (GET_RTX_CLASS (code) == '<')
9373 {
9374 enum machine_mode op_mode = GET_MODE (op0);
9210df58
RK		 9375
9376 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
0f41302f 9377 just (REL_OP X Y). */
9210df58
RK		 9378 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9379 {
9380 op1 = XEXP (op0, 1);
9381 op0 = XEXP (op0, 0);
9382 op_mode = GET_MODE (op0);
9383 }
9384
230d793d
RS		 9385 if (op_mode == VOIDmode)
9386 op_mode = GET_MODE (op1);
9387 result = simplify_relational_operation (code, op_mode, op0, op1);
9388 }
9389 else
9390 result = simplify_binary_operation (code, mode, op0, op1);
9391
9392 if (result)
9393 return result;
9394
9395 /* Put complex operands first and constants second. */
9396 if (GET_RTX_CLASS (code) == 'c'
9397 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9398 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9399 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9400 || (GET_CODE (op0) == SUBREG
9401 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9402 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9403 return gen_rtx_combine (code, mode, op1, op0);
9404
e5e809f4
JL		 9405 /* If we are turning off bits already known off in OP0, we need not do
9406 an AND. */
9407 else if (code == AND && GET_CODE (op1) == CONST_INT
9408 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9409 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9410 return op0;
9411
230d793d
RS		 9412 return gen_rtx_combine (code, mode, op0, op1);
9413}
9414
9415static rtx
0c1c8ea6 9416gen_unary (code, mode, op0_mode, op0)
230d793d 9417 enum rtx_code code;
0c1c8ea6 9418 enum machine_mode mode, op0_mode;
230d793d
RS		 9419 rtx op0;
9420{
0c1c8ea6 9421 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
230d793d
RS		 9422
9423 if (result)
9424 return result;
9425
9426 return gen_rtx_combine (code, mode, op0);
9427}
9428\f
9429/* Simplify a comparison between *POP0 and *POP1 where CODE is the
9430 comparison code that will be tested.
9431
9432 The result is a possibly different comparison code to use. *POP0 and
9433 *POP1 may be updated.
9434
9435 It is possible that we might detect that a comparison is either always
9436 true or always false. However, we do not perform general constant
5089e22e 9437 folding in combine, so this knowledge isn't useful. Such tautologies
230d793d
RS		 9438 should have been detected earlier. Hence we ignore all such cases. */
9439
9440static enum rtx_code
9441simplify_comparison (code, pop0, pop1)
9442 enum rtx_code code;
9443 rtx *pop0;
9444 rtx *pop1;
9445{
9446 rtx op0 = *pop0;
9447 rtx op1 = *pop1;
9448 rtx tem, tem1;
9449 int i;
9450 enum machine_mode mode, tmode;
9451
9452 /* Try a few ways of applying the same transformation to both operands. */
9453 while (1)
9454 {
3a19aabc
RK		 9455#ifndef WORD_REGISTER_OPERATIONS
9456 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9457 so check specially. */
9458 if (code != GTU && code != GEU && code != LTU && code != LEU
9459 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9460 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9461 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9462 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9463 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9464 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
ad25ba17 9465 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
3a19aabc
RK		 9466 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9467 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9468 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9469 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9470 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9471 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9472 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9473 && (INTVAL (XEXP (op0, 1))
9474 == (GET_MODE_BITSIZE (GET_MODE (op0))
9475 - (GET_MODE_BITSIZE
9476 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9477 {
9478 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9479 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9480 }
9481#endif
9482
230d793d
RS		 9483 /* If both operands are the same constant shift, see if we can ignore the
9484 shift. We can if the shift is a rotate or if the bits shifted out of
951553af 9485 this shift are known to be zero for both inputs and if the type of
230d793d 9486 comparison is compatible with the shift. */
67232b23
RK		 9487 if (GET_CODE (op0) == GET_CODE (op1)
9488 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9489 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
45620ed4 9490 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
67232b23
RK		 9491 && (code != GT && code != LT && code != GE && code != LE))
9492 || (GET_CODE (op0) == ASHIFTRT
9493 && (code != GTU && code != LTU
9494 && code != GEU && code != GEU)))
9495 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9496 && INTVAL (XEXP (op0, 1)) >= 0
9497 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9498 && XEXP (op0, 1) == XEXP (op1, 1))
230d793d
RS		 9499 {
9500 enum machine_mode mode = GET_MODE (op0);
5f4f0e22 9501 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9502 int shift_count = INTVAL (XEXP (op0, 1));
9503
9504 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9505 mask &= (mask >> shift_count) << shift_count;
45620ed4 9506 else if (GET_CODE (op0) == ASHIFT)
230d793d
RS		 9507 mask = (mask & (mask << shift_count)) >> shift_count;
9508
951553af
RK		 9509 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9510 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
230d793d
RS		 9511 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9512 else
9513 break;
9514 }
9515
9516 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9517 SUBREGs are of the same mode, and, in both cases, the AND would
9518 be redundant if the comparison was done in the narrower mode,
9519 do the comparison in the narrower mode (e.g., we are AND'ing with 1
951553af
RK		 9520 and the operand's possibly nonzero bits are 0xffffff01; in that case
9521 if we only care about QImode, we don't need the AND). This case
9522 occurs if the output mode of an scc insn is not SImode and
7e4dc511
RK		 9523 STORE_FLAG_VALUE == 1 (e.g., the 386).
9524
9525 Similarly, check for a case where the AND's are ZERO_EXTEND
9526 operations from some narrower mode even though a SUBREG is not
9527 present. */
230d793d
RS		 9528
9529 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9530 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7e4dc511 9531 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
230d793d 9532 {
7e4dc511
RK		 9533 rtx inner_op0 = XEXP (op0, 0);
9534 rtx inner_op1 = XEXP (op1, 0);
9535 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9536 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9537 int changed = 0;
9538
9539 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9540 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9541 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9542 && (GET_MODE (SUBREG_REG (inner_op0))
9543 == GET_MODE (SUBREG_REG (inner_op1)))
729a2bc6 9544 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
7e4dc511 9545 <= HOST_BITS_PER_WIDE_INT)
01c82bbb 9546 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
729a2bc6 9547 GET_MODE (SUBREG_REG (inner_op0)))))
01c82bbb
RK		 9548 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9549 GET_MODE (SUBREG_REG (inner_op1))))))
7e4dc511
RK		 9550 {
9551 op0 = SUBREG_REG (inner_op0);
9552 op1 = SUBREG_REG (inner_op1);
9553
9554 /* The resulting comparison is always unsigned since we masked
0f41302f 9555 off the original sign bit. */
7e4dc511
RK		 9556 code = unsigned_condition (code);
9557
9558 changed = 1;
9559 }
230d793d 9560
7e4dc511
RK		 9561 else if (c0 == c1)
9562 for (tmode = GET_CLASS_NARROWEST_MODE
9563 (GET_MODE_CLASS (GET_MODE (op0)));
9564 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
e51712db 9565 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
7e4dc511
RK		 9566 {
9567 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9568 op1 = gen_lowpart_for_combine (tmode, inner_op1);
66415c8b 9569 code = unsigned_condition (code);
7e4dc511
RK		 9570 changed = 1;
9571 break;
9572 }
9573
9574 if (! changed)
9575 break;
230d793d 9576 }
3a19aabc 9577
ad25ba17
RK		 9578 /* If both operands are NOT, we can strip off the outer operation
9579 and adjust the comparison code for swapped operands; similarly for
9580 NEG, except that this must be an equality comparison. */
9581 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9582 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9583 && (code == EQ || code == NE)))
9584 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
3a19aabc 9585
230d793d
RS		 9586 else
9587 break;
9588 }
9589
9590 /* If the first operand is a constant, swap the operands and adjust the
3aceff0d
RK		 9591 comparison code appropriately, but don't do this if the second operand
9592 is already a constant integer. */
9593 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
230d793d
RS		 9594 {
9595 tem = op0, op0 = op1, op1 = tem;
9596 code = swap_condition (code);
9597 }
9598
9599 /* We now enter a loop during which we will try to simplify the comparison.
9600 For the most part, we only are concerned with comparisons with zero,
9601 but some things may really be comparisons with zero but not start
9602 out looking that way. */
9603
9604 while (GET_CODE (op1) == CONST_INT)
9605 {
9606 enum machine_mode mode = GET_MODE (op0);
9607 int mode_width = GET_MODE_BITSIZE (mode);
5f4f0e22 9608 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
230d793d
RS		 9609 int equality_comparison_p;
9610 int sign_bit_comparison_p;
9611 int unsigned_comparison_p;
5f4f0e22 9612 HOST_WIDE_INT const_op;
230d793d
RS		 9613
9614 /* We only want to handle integral modes. This catches VOIDmode,
9615 CCmode, and the floating-point modes. An exception is that we
9616 can handle VOIDmode if OP0 is a COMPARE or a comparison
9617 operation. */
9618
9619 if (GET_MODE_CLASS (mode) != MODE_INT
9620 && ! (mode == VOIDmode
9621 && (GET_CODE (op0) == COMPARE
9622 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9623 break;
9624
9625 /* Get the constant we are comparing against and turn off all bits
9626 not on in our mode. */
9627 const_op = INTVAL (op1);
5f4f0e22 9628 if (mode_width <= HOST_BITS_PER_WIDE_INT)
4803a34a 9629 const_op &= mask;
230d793d
RS		 9630
9631 /* If we are comparing against a constant power of two and the value
951553af 9632 being compared can only have that single bit nonzero (e.g., it was
230d793d
RS		 9633 `and'ed with that bit), we can replace this with a comparison
9634 with zero. */
9635 if (const_op
9636 && (code == EQ || code == NE || code == GE || code == GEU
9637 || code == LT || code == LTU)
5f4f0e22 9638 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 9639 && exact_log2 (const_op) >= 0
e51712db 9640 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
230d793d
RS		 9641 {
9642 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9643 op1 = const0_rtx, const_op = 0;
9644 }
9645
d0ab8cd3
RK		 9646 /* Similarly, if we are comparing a value known to be either -1 or
9647 0 with -1, change it to the opposite comparison against zero. */
9648
9649 if (const_op == -1
9650 && (code == EQ || code == NE || code == GT || code == LE
9651 || code == GEU || code == LTU)
9652 && num_sign_bit_copies (op0, mode) == mode_width)
9653 {
9654 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9655 op1 = const0_rtx, const_op = 0;
9656 }
9657
230d793d 9658 /* Do some canonicalizations based on the comparison code. We prefer
4803a34a
RK		 9659 comparisons against zero and then prefer equality comparisons.
9660 If we can reduce the size of a constant, we will do that too. */
230d793d
RS		 9661
9662 switch (code)
9663 {
9664 case LT:
4803a34a
RK		 9665 /* < C is equivalent to <= (C - 1) */
9666 if (const_op > 0)
230d793d 9667 {
4803a34a 9668 const_op -= 1;
5f4f0e22 9669 op1 = GEN_INT (const_op);
230d793d
RS		 9670 code = LE;
9671 /* ... fall through to LE case below. */
9672 }
9673 else
9674 break;
9675
9676 case LE:
4803a34a
RK		 9677 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9678 if (const_op < 0)
9679 {
9680 const_op += 1;
5f4f0e22 9681 op1 = GEN_INT (const_op);
4803a34a
RK		 9682 code = LT;
9683 }
230d793d
RS		 9684
9685 /* If we are doing a <= 0 comparison on a value known to have
9686 a zero sign bit, we can replace this with == 0. */
9687 else if (const_op == 0
5f4f0e22 9688 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9689 && (nonzero_bits (op0, mode)
5f4f0e22 9690 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9691 code = EQ;
9692 break;
9693
9694 case GE:
0f41302f 9695 /* >= C is equivalent to > (C - 1). */
4803a34a 9696 if (const_op > 0)
230d793d 9697 {
4803a34a 9698 const_op -= 1;
5f4f0e22 9699 op1 = GEN_INT (const_op);
230d793d
RS		 9700 code = GT;
9701 /* ... fall through to GT below. */
9702 }
9703 else
9704 break;
9705
9706 case GT:
4803a34a
RK		 9707 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9708 if (const_op < 0)
9709 {
9710 const_op += 1;
5f4f0e22 9711 op1 = GEN_INT (const_op);
4803a34a
RK		 9712 code = GE;
9713 }
230d793d
RS		 9714
9715 /* If we are doing a > 0 comparison on a value known to have
9716 a zero sign bit, we can replace this with != 0. */
9717 else if (const_op == 0
5f4f0e22 9718 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9719 && (nonzero_bits (op0, mode)
5f4f0e22 9720 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
230d793d
RS		 9721 code = NE;
9722 break;
9723
230d793d 9724 case LTU:
4803a34a
RK		 9725 /* < C is equivalent to <= (C - 1). */
9726 if (const_op > 0)
9727 {
9728 const_op -= 1;
5f4f0e22 9729 op1 = GEN_INT (const_op);
4803a34a 9730 code = LEU;
0f41302f 9731 /* ... fall through ... */
4803a34a 9732 }
d0ab8cd3
RK		 9733
9734 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
f77aada2
JW		 9735 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9736 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9737 {
9738 const_op = 0, op1 = const0_rtx;
9739 code = GE;
9740 break;
9741 }
4803a34a
RK		 9742 else
9743 break;
230d793d
RS		 9744
9745 case LEU:
9746 /* unsigned <= 0 is equivalent to == 0 */
9747 if (const_op == 0)
9748 code = EQ;
d0ab8cd3 9749
0f41302f 9750 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
f77aada2
JW		 9751 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9752 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9753 {
9754 const_op = 0, op1 = const0_rtx;
9755 code = GE;
9756 }
230d793d
RS		 9757 break;
9758
4803a34a
RK		 9759 case GEU:
9760 /* >= C is equivalent to < (C - 1). */
9761 if (const_op > 1)
9762 {
9763 const_op -= 1;
5f4f0e22 9764 op1 = GEN_INT (const_op);
4803a34a 9765 code = GTU;
0f41302f 9766 /* ... fall through ... */
4803a34a 9767 }
d0ab8cd3
RK		 9768
9769 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
f77aada2
JW		 9770 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9771 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
d0ab8cd3
RK		 9772 {
9773 const_op = 0, op1 = const0_rtx;
9774 code = LT;
8b2e69e1 9775 break;
d0ab8cd3 9776 }
4803a34a
RK		 9777 else
9778 break;
9779
230d793d
RS		 9780 case GTU:
9781 /* unsigned > 0 is equivalent to != 0 */
9782 if (const_op == 0)
9783 code = NE;
d0ab8cd3
RK		 9784
9785 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
f77aada2
JW		 9786 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9787 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
d0ab8cd3
RK		 9788 {
9789 const_op = 0, op1 = const0_rtx;
9790 code = LT;
9791 }
230d793d 9792 break;
e9a25f70
JL		 9793
9794 default:
9795 break;
230d793d
RS		 9796 }
9797
9798 /* Compute some predicates to simplify code below. */
9799
9800 equality_comparison_p = (code == EQ || code == NE);
9801 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9802 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9803 || code == LEU);
9804
6139ff20
RK		 9805 /* If this is a sign bit comparison and we can do arithmetic in
9806 MODE, say that we will only be needing the sign bit of OP0. */
9807 if (sign_bit_comparison_p
9808 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9809 op0 = force_to_mode (op0, mode,
9810 ((HOST_WIDE_INT) 1
9811 << (GET_MODE_BITSIZE (mode) - 1)),
e3d616e3 9812 NULL_RTX, 0);
6139ff20 9813
230d793d
RS		 9814 /* Now try cases based on the opcode of OP0. If none of the cases
9815 does a "continue", we exit this loop immediately after the
9816 switch. */
9817
9818 switch (GET_CODE (op0))
9819 {
9820 case ZERO_EXTRACT:
9821 /* If we are extracting a single bit from a variable position in
9822 a constant that has only a single bit set and are comparing it
9823 with zero, we can convert this into an equality comparison
d7cd794f 9824 between the position and the location of the single bit. */
230d793d 9825
230d793d
RS		 9826 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9827 && XEXP (op0, 1) == const1_rtx
9828 && equality_comparison_p && const_op == 0
d7cd794f 9829 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
230d793d 9830 {
f76b9db2 9831 if (BITS_BIG_ENDIAN)
0d8e55d8 9832 {
d7cd794f 9833#ifdef HAVE_extzv
0d8e55d8
JL		 9834 mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
9835 if (mode == VOIDmode)
9836 mode = word_mode;
9837 i = (GET_MODE_BITSIZE (mode) - 1 - i);
d7cd794f 9838#else
0d8e55d8 9839 i = BITS_PER_WORD - 1 - i;
230d793d 9840#endif
0d8e55d8 9841 }
230d793d
RS		 9842
9843 op0 = XEXP (op0, 2);
5f4f0e22 9844 op1 = GEN_INT (i);
230d793d
RS		 9845 const_op = i;
9846
9847 /* Result is nonzero iff shift count is equal to I. */
9848 code = reverse_condition (code);
9849 continue;
9850 }
230d793d 9851
0f41302f 9852 /* ... fall through ... */
230d793d
RS		 9853
9854 case SIGN_EXTRACT:
9855 tem = expand_compound_operation (op0);
9856 if (tem != op0)
9857 {
9858 op0 = tem;
9859 continue;
9860 }
9861 break;
9862
9863 case NOT:
9864 /* If testing for equality, we can take the NOT of the constant. */
9865 if (equality_comparison_p
9866 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9867 {
9868 op0 = XEXP (op0, 0);
9869 op1 = tem;
9870 continue;
9871 }
9872
9873 /* If just looking at the sign bit, reverse the sense of the
9874 comparison. */
9875 if (sign_bit_comparison_p)
9876 {
9877 op0 = XEXP (op0, 0);
9878 code = (code == GE ? LT : GE);
9879 continue;
9880 }
9881 break;
9882
9883 case NEG:
9884 /* If testing for equality, we can take the NEG of the constant. */
9885 if (equality_comparison_p
9886 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9887 {
9888 op0 = XEXP (op0, 0);
9889 op1 = tem;
9890 continue;
9891 }
9892
9893 /* The remaining cases only apply to comparisons with zero. */
9894 if (const_op != 0)
9895 break;
9896
9897 /* When X is ABS or is known positive,
9898 (neg X) is < 0 if and only if X != 0. */
9899
9900 if (sign_bit_comparison_p
9901 && (GET_CODE (XEXP (op0, 0)) == ABS
5f4f0e22 9902 || (mode_width <= HOST_BITS_PER_WIDE_INT
951553af 9903 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 9904 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
230d793d
RS		 9905 {
9906 op0 = XEXP (op0, 0);
9907 code = (code == LT ? NE : EQ);
9908 continue;
9909 }
9910
3bed8141 9911 /* If we have NEG of something whose two high-order bits are the
0f41302f 9912 same, we know that "(-a) < 0" is equivalent to "a > 0". */
3bed8141 9913 if (num_sign_bit_copies (op0, mode) >= 2)
230d793d
RS		 9914 {
9915 op0 = XEXP (op0, 0);
9916 code = swap_condition (code);
9917 continue;
9918 }
9919 break;
9920
9921 case ROTATE:
9922 /* If we are testing equality and our count is a constant, we
9923 can perform the inverse operation on our RHS. */
9924 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9925 && (tem = simplify_binary_operation (ROTATERT, mode,
9926 op1, XEXP (op0, 1))) != 0)
9927 {
9928 op0 = XEXP (op0, 0);
9929 op1 = tem;
9930 continue;
9931 }
9932
9933 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9934 a particular bit. Convert it to an AND of a constant of that
9935 bit. This will be converted into a ZERO_EXTRACT. */
9936 if (const_op == 0 && sign_bit_comparison_p
9937 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 9938 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 9939 {
5f4f0e22
CH		 9940 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9941 ((HOST_WIDE_INT) 1
9942 << (mode_width - 1
9943 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 9944 code = (code == LT ? NE : EQ);
9945 continue;
9946 }
9947
0f41302f 9948 /* ... fall through ... */
230d793d
RS		 9949
9950 case ABS:
9951 /* ABS is ignorable inside an equality comparison with zero. */
9952 if (const_op == 0 && equality_comparison_p)
9953 {
9954 op0 = XEXP (op0, 0);
9955 continue;
9956 }
9957 break;
9958
9959
9960 case SIGN_EXTEND:
9961 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9962 to (compare FOO CONST) if CONST fits in FOO's mode and we
9963 are either testing inequality or have an unsigned comparison
9964 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9965 if (! unsigned_comparison_p
9966 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 9967 <= HOST_BITS_PER_WIDE_INT)
9968 && ((unsigned HOST_WIDE_INT) const_op
e51712db 9969 < (((unsigned HOST_WIDE_INT) 1
5f4f0e22 9970 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
230d793d
RS		 9971 {
9972 op0 = XEXP (op0, 0);
9973 continue;
9974 }
9975 break;
9976
9977 case SUBREG:
a687e897 9978 /* Check for the case where we are comparing A - C1 with C2,
abc95ed3 9979 both constants are smaller than 1/2 the maximum positive
a687e897
RK		 9980 value in MODE, and the comparison is equality or unsigned.
9981 In that case, if A is either zero-extended to MODE or has
9982 sufficient sign bits so that the high-order bit in MODE
9983 is a copy of the sign in the inner mode, we can prove that it is
9984 safe to do the operation in the wider mode. This simplifies
9985 many range checks. */
9986
9987 if (mode_width <= HOST_BITS_PER_WIDE_INT
9988 && subreg_lowpart_p (op0)
9989 && GET_CODE (SUBREG_REG (op0)) == PLUS
9990 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9991 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9992 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
e51712db 9993 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
adb7a1cb 9994 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
951553af
RK		 9995 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9996 GET_MODE (SUBREG_REG (op0)))
a687e897
RK		 9997 & ~ GET_MODE_MASK (mode))
9998 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9999 GET_MODE (SUBREG_REG (op0)))
10000 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10001 - GET_MODE_BITSIZE (mode)))))
10002 {
10003 op0 = SUBREG_REG (op0);
10004 continue;
10005 }
10006
fe0cf571
RK		 10007 /* If the inner mode is narrower and we are extracting the low part,
10008 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10009 if (subreg_lowpart_p (op0)
89f1c7f2
RS		 10010 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10011 /* Fall through */ ;
10012 else
230d793d
RS		 10013 break;
10014
0f41302f 10015 /* ... fall through ... */
230d793d
RS		 10016
10017 case ZERO_EXTEND:
10018 if ((unsigned_comparison_p || equality_comparison_p)
10019 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
5f4f0e22
CH		 10020 <= HOST_BITS_PER_WIDE_INT)
10021 && ((unsigned HOST_WIDE_INT) const_op
230d793d
RS		 10022 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10023 {
10024 op0 = XEXP (op0, 0);
10025 continue;
10026 }
10027 break;
10028
10029 case PLUS:
20fdd649 10030 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
5089e22e 10031 this for equality comparisons due to pathological cases involving
230d793d 10032 overflows. */
20fdd649
RK		 10033 if (equality_comparison_p
10034 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10035 op1, XEXP (op0, 1))))
230d793d
RS		 10036 {
10037 op0 = XEXP (op0, 0);
10038 op1 = tem;
10039 continue;
10040 }
10041
10042 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10043 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10044 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10045 {
10046 op0 = XEXP (XEXP (op0, 0), 0);
10047 code = (code == LT ? EQ : NE);
10048 continue;
10049 }
10050 break;
10051
10052 case MINUS:
20fdd649
RK		 10053 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10054 (eq B (minus A C)), whichever simplifies. We can only do
10055 this for equality comparisons due to pathological cases involving
10056 overflows. */
10057 if (equality_comparison_p
10058 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10059 XEXP (op0, 1), op1)))
10060 {
10061 op0 = XEXP (op0, 0);
10062 op1 = tem;
10063 continue;
10064 }
10065
10066 if (equality_comparison_p
10067 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10068 XEXP (op0, 0), op1)))
10069 {
10070 op0 = XEXP (op0, 1);
10071 op1 = tem;
10072 continue;
10073 }
10074
230d793d
RS		 10075 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10076 of bits in X minus 1, is one iff X > 0. */
10077 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10078 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10079 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10080 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10081 {
10082 op0 = XEXP (op0, 1);
10083 code = (code == GE ? LE : GT);
10084 continue;
10085 }
10086 break;
10087
10088 case XOR:
10089 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10090 if C is zero or B is a constant. */
10091 if (equality_comparison_p
10092 && 0 != (tem = simplify_binary_operation (XOR, mode,
10093 XEXP (op0, 1), op1)))
10094 {
10095 op0 = XEXP (op0, 0);
10096 op1 = tem;
10097 continue;
10098 }
10099 break;
10100
10101 case EQ: case NE:
10102 case LT: case LTU: case LE: case LEU:
10103 case GT: case GTU: case GE: case GEU:
10104 /* We can't do anything if OP0 is a condition code value, rather
10105 than an actual data value. */
10106 if (const_op != 0
10107#ifdef HAVE_cc0
10108 || XEXP (op0, 0) == cc0_rtx
10109#endif
10110 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10111 break;
10112
10113 /* Get the two operands being compared. */
10114 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10115 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10116 else
10117 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10118
10119 /* Check for the cases where we simply want the result of the
10120 earlier test or the opposite of that result. */
10121 if (code == NE
10122 || (code == EQ && reversible_comparison_p (op0))
5f4f0e22 10123 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
3f508eca 10124 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
230d793d 10125 && (STORE_FLAG_VALUE
5f4f0e22
CH		 10126 & (((HOST_WIDE_INT) 1
10127 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
230d793d
RS		 10128 && (code == LT
10129 || (code == GE && reversible_comparison_p (op0)))))
10130 {
10131 code = (code == LT || code == NE
10132 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10133 op0 = tem, op1 = tem1;
10134 continue;
10135 }
10136 break;
10137
10138 case IOR:
10139 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10140 iff X <= 0. */
10141 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10142 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10143 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10144 {
10145 op0 = XEXP (op0, 1);
10146 code = (code == GE ? GT : LE);
10147 continue;
10148 }
10149 break;
10150
10151 case AND:
10152 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10153 will be converted to a ZERO_EXTRACT later. */
10154 if (const_op == 0 && equality_comparison_p
45620ed4 10155 && GET_CODE (XEXP (op0, 0)) == ASHIFT
230d793d
RS		 10156 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10157 {
10158 op0 = simplify_and_const_int
10159 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10160 XEXP (op0, 1),
10161 XEXP (XEXP (op0, 0), 1)),
5f4f0e22 10162 (HOST_WIDE_INT) 1);
230d793d
RS		 10163 continue;
10164 }
10165
10166 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10167 zero and X is a comparison and C1 and C2 describe only bits set
10168 in STORE_FLAG_VALUE, we can compare with X. */
10169 if (const_op == 0 && equality_comparison_p
5f4f0e22 10170 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d
RS		 10171 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10172 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10173 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10174 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
5f4f0e22 10175 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
230d793d
RS		 10176 {
10177 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10178 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10179 if ((~ STORE_FLAG_VALUE & mask) == 0
10180 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10181 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10182 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10183 {
10184 op0 = XEXP (XEXP (op0, 0), 0);
10185 continue;
10186 }
10187 }
10188
10189 /* If we are doing an equality comparison of an AND of a bit equal
10190 to the sign bit, replace this with a LT or GE comparison of
10191 the underlying value. */
10192 if (equality_comparison_p
10193 && const_op == 0
10194 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10195 && mode_width <= HOST_BITS_PER_WIDE_INT
230d793d 10196 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
e51712db 10197 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
230d793d
RS		 10198 {
10199 op0 = XEXP (op0, 0);
10200 code = (code == EQ ? GE : LT);
10201 continue;
10202 }
10203
10204 /* If this AND operation is really a ZERO_EXTEND from a narrower
10205 mode, the constant fits within that mode, and this is either an
10206 equality or unsigned comparison, try to do this comparison in
10207 the narrower mode. */
10208 if ((equality_comparison_p || unsigned_comparison_p)
10209 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10210 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10211 & GET_MODE_MASK (mode))
10212 + 1)) >= 0
10213 && const_op >> i == 0
10214 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10215 {
10216 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10217 continue;
10218 }
e5e809f4
JL		 10219
10220 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10221 in both M1 and M2 and the SUBREG is either paradoxical or
10222 represents the low part, permute the SUBREG and the AND and
10223 try again. */
10224 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10225 && ((mode_width
10226 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
9ec36da5
JL		 10227#ifdef WORD_REGISTER_OPERATIONS
10228 || subreg_lowpart_p (XEXP (op0, 0))
10229#endif
10230 )
adc05e6c
JL		 10231#ifndef WORD_REGISTER_OPERATIONS
10232 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10233 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10234 As originally written the upper bits have a defined value
10235 due to the AND operation. However, if we commute the AND
10236 inside the SUBREG then they no longer have defined values
10237 and the meaning of the code has been changed. */
10238 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10239 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10240#endif
e5e809f4
JL		 10241 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10242 && mode_width <= HOST_BITS_PER_WIDE_INT
10243 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10244 <= HOST_BITS_PER_WIDE_INT)
10245 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10246 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
9ec36da5 10247 & INTVAL (XEXP (op0, 1)))
e51712db
KG		 10248 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10249 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
9ec36da5 10250 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
e5e809f4
JL		 10251
10252 {
10253 op0
10254 = gen_lowpart_for_combine
10255 (mode,
10256 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10257 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10258 continue;
10259 }
10260
230d793d
RS		 10261 break;
10262
10263 case ASHIFT:
45620ed4 10264 /* If we have (compare (ashift FOO N) (const_int C)) and
230d793d 10265 the high order N bits of FOO (N+1 if an inequality comparison)
951553af 10266 are known to be zero, we can do this by comparing FOO with C
230d793d
RS		 10267 shifted right N bits so long as the low-order N bits of C are
10268 zero. */
10269 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10270 && INTVAL (XEXP (op0, 1)) >= 0
10271 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
5f4f0e22
CH		 10272 < HOST_BITS_PER_WIDE_INT)
10273 && ((const_op
34785d05 10274 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
5f4f0e22 10275 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10276 && (nonzero_bits (XEXP (op0, 0), mode)
230d793d
RS		 10277 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10278 + ! equality_comparison_p))) == 0)
10279 {
10280 const_op >>= INTVAL (XEXP (op0, 1));
5f4f0e22 10281 op1 = GEN_INT (const_op);
230d793d
RS		 10282 op0 = XEXP (op0, 0);
10283 continue;
10284 }
10285
dfbe1b2f 10286 /* If we are doing a sign bit comparison, it means we are testing
230d793d 10287 a particular bit. Convert it to the appropriate AND. */
dfbe1b2f 10288 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
5f4f0e22 10289 && mode_width <= HOST_BITS_PER_WIDE_INT)
230d793d 10290 {
5f4f0e22
CH		 10291 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10292 ((HOST_WIDE_INT) 1
10293 << (mode_width - 1
10294 - INTVAL (XEXP (op0, 1)))));
230d793d
RS		 10295 code = (code == LT ? NE : EQ);
10296 continue;
10297 }
dfbe1b2f
RK		 10298
10299 /* If this an equality comparison with zero and we are shifting
10300 the low bit to the sign bit, we can convert this to an AND of the
10301 low-order bit. */
10302 if (const_op == 0 && equality_comparison_p
10303 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10304 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10305 {
5f4f0e22
CH		 10306 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10307 (HOST_WIDE_INT) 1);
dfbe1b2f
RK		 10308 continue;
10309 }
230d793d
RS		 10310 break;
10311
10312 case ASHIFTRT:
d0ab8cd3
RK		 10313 /* If this is an equality comparison with zero, we can do this
10314 as a logical shift, which might be much simpler. */
10315 if (equality_comparison_p && const_op == 0
10316 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10317 {
10318 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10319 XEXP (op0, 0),
10320 INTVAL (XEXP (op0, 1)));
10321 continue;
10322 }
10323
230d793d
RS		 10324 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10325 do the comparison in a narrower mode. */
10326 if (! unsigned_comparison_p
10327 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10328 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10329 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10330 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
22331794 10331 MODE_INT, 1)) != BLKmode
5f4f0e22
CH		 10332 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10333 || ((unsigned HOST_WIDE_INT) - const_op
10334 <= GET_MODE_MASK (tmode))))
230d793d
RS		 10335 {
10336 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10337 continue;
10338 }
10339
0f41302f 10340 /* ... fall through ... */
230d793d
RS		 10341 case LSHIFTRT:
10342 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
951553af 10343 the low order N bits of FOO are known to be zero, we can do this
230d793d
RS		 10344 by comparing FOO with C shifted left N bits so long as no
10345 overflow occurs. */
10346 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10347 && INTVAL (XEXP (op0, 1)) >= 0
5f4f0e22
CH		 10348 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10349 && mode_width <= HOST_BITS_PER_WIDE_INT
951553af 10350 && (nonzero_bits (XEXP (op0, 0), mode)
5f4f0e22 10351 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
230d793d
RS		 10352 && (const_op == 0
10353 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10354 < mode_width)))
10355 {
10356 const_op <<= INTVAL (XEXP (op0, 1));
5f4f0e22 10357 op1 = GEN_INT (const_op);
230d793d
RS		 10358 op0 = XEXP (op0, 0);
10359 continue;
10360 }
10361
10362 /* If we are using this shift to extract just the sign bit, we
10363 can replace this with an LT or GE comparison. */
10364 if (const_op == 0
10365 && (equality_comparison_p || sign_bit_comparison_p)
10366 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10367 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10368 {
10369 op0 = XEXP (op0, 0);
10370 code = (code == NE || code == GT ? LT : GE);
10371 continue;
10372 }
10373 break;
e9a25f70
JL		 10374
10375 default:
10376 break;
230d793d
RS		 10377 }
10378
10379 break;
10380 }
10381
10382 /* Now make any compound operations involved in this comparison. Then,
76d31c63 10383 check for an outmost SUBREG on OP0 that is not doing anything or is
230d793d
RS		 10384 paradoxical. The latter case can only occur when it is known that the
10385 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10386 We can never remove a SUBREG for a non-equality comparison because the
10387 sign bit is in a different place in the underlying object. */
10388
10389 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10390 op1 = make_compound_operation (op1, SET);
10391
10392 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10393 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10394 && (code == NE || code == EQ)
10395 && ((GET_MODE_SIZE (GET_MODE (op0))
10396 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10397 {
10398 op0 = SUBREG_REG (op0);
10399 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10400 }
10401
10402 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10403 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10404 && (code == NE || code == EQ)
ac49a949
RS		 10405 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10406 <= HOST_BITS_PER_WIDE_INT)
951553af 10407 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10408 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10409 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10410 op1),
951553af 10411 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
230d793d
RS		 10412 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10413 op0 = SUBREG_REG (op0), op1 = tem;
10414
10415 /* We now do the opposite procedure: Some machines don't have compare
10416 insns in all modes. If OP0's mode is an integer mode smaller than a
10417 word and we can't do a compare in that mode, see if there is a larger
a687e897
RK		 10418 mode for which we can do the compare. There are a number of cases in
10419 which we can use the wider mode. */
230d793d
RS		 10420
10421 mode = GET_MODE (op0);
10422 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10423 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10424 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10425 for (tmode = GET_MODE_WIDER_MODE (mode);
5f4f0e22
CH		 10426 (tmode != VOIDmode
10427 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
230d793d 10428 tmode = GET_MODE_WIDER_MODE (tmode))
a687e897 10429 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
230d793d 10430 {
951553af 10431 /* If the only nonzero bits in OP0 and OP1 are those in the
a687e897
RK		 10432 narrower mode and this is an equality or unsigned comparison,
10433 we can use the wider mode. Similarly for sign-extended
7e4dc511 10434 values, in which case it is true for all comparisons. */
a687e897
RK		 10435 if (((code == EQ || code == NE
10436 || code == GEU || code == GTU || code == LEU || code == LTU)
951553af
RK		 10437 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10438 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
7e4dc511
RK		 10439 || ((num_sign_bit_copies (op0, tmode)
10440 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
a687e897 10441 && (num_sign_bit_copies (op1, tmode)
58744483 10442 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
a687e897
RK		 10443 {
10444 op0 = gen_lowpart_for_combine (tmode, op0);
10445 op1 = gen_lowpart_for_combine (tmode, op1);
10446 break;
10447 }
230d793d 10448
a687e897
RK		 10449 /* If this is a test for negative, we can make an explicit
10450 test of the sign bit. */
10451
10452 if (op1 == const0_rtx && (code == LT || code == GE)
10453 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
230d793d 10454 {
a687e897
RK		 10455 op0 = gen_binary (AND, tmode,
10456 gen_lowpart_for_combine (tmode, op0),
5f4f0e22
CH		 10457 GEN_INT ((HOST_WIDE_INT) 1
10458 << (GET_MODE_BITSIZE (mode) - 1)));
230d793d 10459 code = (code == LT) ? NE : EQ;
a687e897 10460 break;
230d793d 10461 }
230d793d
RS		 10462 }
10463
b7a775b2
RK		 10464#ifdef CANONICALIZE_COMPARISON
10465 /* If this machine only supports a subset of valid comparisons, see if we
10466 can convert an unsupported one into a supported one. */
10467 CANONICALIZE_COMPARISON (code, op0, op1);
10468#endif
10469
230d793d
RS		 10470 *pop0 = op0;
10471 *pop1 = op1;
10472
10473 return code;
10474}
10475\f
10476/* Return 1 if we know that X, a comparison operation, is not operating
10477 on a floating-point value or is EQ or NE, meaning that we can safely
10478 reverse it. */
10479
10480static int
10481reversible_comparison_p (x)
10482 rtx x;
10483{
10484 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7e2a0d8e 10485 || flag_fast_math
230d793d
RS		 10486 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10487 return 1;
10488
10489 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10490 {
10491 case MODE_INT:
3ad2180a
RK		 10492 case MODE_PARTIAL_INT:
10493 case MODE_COMPLEX_INT:
230d793d
RS		 10494 return 1;
10495
10496 case MODE_CC:
9210df58
RK		 10497 /* If the mode of the condition codes tells us that this is safe,
10498 we need look no further. */
10499 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10500 return 1;
10501
10502 /* Otherwise try and find where the condition codes were last set and
10503 use that. */
230d793d
RS		 10504 x = get_last_value (XEXP (x, 0));
10505 return (x && GET_CODE (x) == COMPARE
3ad2180a 10506 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
e9a25f70
JL		 10507
10508 default:
10509 return 0;
230d793d 10510 }
230d793d
RS		 10511}
10512\f
10513/* Utility function for following routine. Called when X is part of a value
10514 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10515 for each register mentioned. Similar to mention_regs in cse.c */
10516
10517static void
10518update_table_tick (x)
10519 rtx x;
10520{
10521 register enum rtx_code code = GET_CODE (x);
10522 register char *fmt = GET_RTX_FORMAT (code);
10523 register int i;
10524
10525 if (code == REG)
10526 {
10527 int regno = REGNO (x);
10528 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10529 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10530
10531 for (i = regno; i < endregno; i++)
10532 reg_last_set_table_tick[i] = label_tick;
10533
10534 return;
10535 }
10536
10537 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10538 /* Note that we can't have an "E" in values stored; see
10539 get_last_value_validate. */
10540 if (fmt[i] == 'e')
10541 update_table_tick (XEXP (x, i));
10542}
10543
10544/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10545 are saying that the register is clobbered and we no longer know its
7988fd36
RK		 10546 value. If INSN is zero, don't update reg_last_set; this is only permitted
10547 with VALUE also zero and is used to invalidate the register. */
230d793d
RS		 10548
10549static void
10550record_value_for_reg (reg, insn, value)
10551 rtx reg;
10552 rtx insn;
10553 rtx value;
10554{
10555 int regno = REGNO (reg);
10556 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10557 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10558 int i;
10559
10560 /* If VALUE contains REG and we have a previous value for REG, substitute
10561 the previous value. */
10562 if (value && insn && reg_overlap_mentioned_p (reg, value))
10563 {
10564 rtx tem;
10565
10566 /* Set things up so get_last_value is allowed to see anything set up to
10567 our insn. */
10568 subst_low_cuid = INSN_CUID (insn);
10569 tem = get_last_value (reg);
10570
10571 if (tem)
10572 value = replace_rtx (copy_rtx (value), reg, tem);
10573 }
10574
10575 /* For each register modified, show we don't know its value, that
ef026f91
RS		 10576 we don't know about its bitwise content, that its value has been
10577 updated, and that we don't know the location of the death of the
10578 register. */
230d793d
RS		 10579 for (i = regno; i < endregno; i ++)
10580 {
10581 if (insn)
10582 reg_last_set[i] = insn;
10583 reg_last_set_value[i] = 0;
ef026f91
RS		 10584 reg_last_set_mode[i] = 0;
10585 reg_last_set_nonzero_bits[i] = 0;
10586 reg_last_set_sign_bit_copies[i] = 0;
230d793d
RS		 10587 reg_last_death[i] = 0;
10588 }
10589
10590 /* Mark registers that are being referenced in this value. */
10591 if (value)
10592 update_table_tick (value);
10593
10594 /* Now update the status of each register being set.
10595 If someone is using this register in this block, set this register
10596 to invalid since we will get confused between the two lives in this
10597 basic block. This makes using this register always invalid. In cse, we
10598 scan the table to invalidate all entries using this register, but this
10599 is too much work for us. */
10600
10601 for (i = regno; i < endregno; i++)
10602 {
10603 reg_last_set_label[i] = label_tick;
10604 if (value && reg_last_set_table_tick[i] == label_tick)
10605 reg_last_set_invalid[i] = 1;
10606 else
10607 reg_last_set_invalid[i] = 0;
10608 }
10609
10610 /* The value being assigned might refer to X (like in "x++;"). In that
10611 case, we must replace it with (clobber (const_int 0)) to prevent
10612 infinite loops. */
9a893315 10613 if (value && ! get_last_value_validate (&value, insn,
230d793d
RS		 10614 reg_last_set_label[regno], 0))
10615 {
10616 value = copy_rtx (value);
9a893315
JW		 10617 if (! get_last_value_validate (&value, insn,
10618 reg_last_set_label[regno], 1))
230d793d
RS		 10619 value = 0;
10620 }
10621
55310dad
RK		 10622 /* For the main register being modified, update the value, the mode, the
10623 nonzero bits, and the number of sign bit copies. */
10624
230d793d
RS		 10625 reg_last_set_value[regno] = value;
10626
55310dad
RK		 10627 if (value)
10628 {
2afabb48 10629 subst_low_cuid = INSN_CUID (insn);
55310dad
RK		 10630 reg_last_set_mode[regno] = GET_MODE (reg);
10631 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10632 reg_last_set_sign_bit_copies[regno]
10633 = num_sign_bit_copies (value, GET_MODE (reg));
10634 }
230d793d
RS		 10635}
10636
10637/* Used for communication between the following two routines. */
10638static rtx record_dead_insn;
10639
10640/* Called via note_stores from record_dead_and_set_regs to handle one
10641 SET or CLOBBER in an insn. */
10642
10643static void
10644record_dead_and_set_regs_1 (dest, setter)
10645 rtx dest, setter;
10646{
ca89d290
RK		 10647 if (GET_CODE (dest) == SUBREG)
10648 dest = SUBREG_REG (dest);
10649
230d793d
RS		 10650 if (GET_CODE (dest) == REG)
10651 {
10652 /* If we are setting the whole register, we know its value. Otherwise
10653 show that we don't know the value. We can handle SUBREG in
10654 some cases. */
10655 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10656 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10657 else if (GET_CODE (setter) == SET
10658 && GET_CODE (SET_DEST (setter)) == SUBREG
10659 && SUBREG_REG (SET_DEST (setter)) == dest
90bf8081 10660 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
230d793d 10661 && subreg_lowpart_p (SET_DEST (setter)))
d0ab8cd3
RK		 10662 record_value_for_reg (dest, record_dead_insn,
10663 gen_lowpart_for_combine (GET_MODE (dest),
10664 SET_SRC (setter)));
230d793d 10665 else
5f4f0e22 10666 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
230d793d
RS		 10667 }
10668 else if (GET_CODE (dest) == MEM
10669 /* Ignore pushes, they clobber nothing. */
10670 && ! push_operand (dest, GET_MODE (dest)))
10671 mem_last_set = INSN_CUID (record_dead_insn);
10672}
10673
10674/* Update the records of when each REG was most recently set or killed
10675 for the things done by INSN. This is the last thing done in processing
10676 INSN in the combiner loop.
10677
ef026f91
RS		 10678 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10679 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10680 and also the similar information mem_last_set (which insn most recently
10681 modified memory) and last_call_cuid (which insn was the most recent
10682 subroutine call). */
230d793d
RS		 10683
10684static void
10685record_dead_and_set_regs (insn)
10686 rtx insn;
10687{
10688 register rtx link;
55310dad
RK		 10689 int i;
10690
230d793d
RS		 10691 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10692 {
dbc131f3
RK		 10693 if (REG_NOTE_KIND (link) == REG_DEAD
10694 && GET_CODE (XEXP (link, 0)) == REG)
10695 {
10696 int regno = REGNO (XEXP (link, 0));
10697 int endregno
10698 = regno + (regno < FIRST_PSEUDO_REGISTER
10699 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10700 : 1);
dbc131f3
RK		 10701
10702 for (i = regno; i < endregno; i++)
10703 reg_last_death[i] = insn;
10704 }
230d793d 10705 else if (REG_NOTE_KIND (link) == REG_INC)
5f4f0e22 10706 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
230d793d
RS		 10707 }
10708
10709 if (GET_CODE (insn) == CALL_INSN)
55310dad
RK		 10710 {
10711 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10712 if (call_used_regs[i])
10713 {
10714 reg_last_set_value[i] = 0;
ef026f91
RS		 10715 reg_last_set_mode[i] = 0;
10716 reg_last_set_nonzero_bits[i] = 0;
10717 reg_last_set_sign_bit_copies[i] = 0;
55310dad
RK		 10718 reg_last_death[i] = 0;
10719 }
10720
10721 last_call_cuid = mem_last_set = INSN_CUID (insn);
10722 }
230d793d
RS		 10723
10724 record_dead_insn = insn;
10725 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10726}
10727\f
10728/* Utility routine for the following function. Verify that all the registers
10729 mentioned in *LOC are valid when *LOC was part of a value set when
10730 label_tick == TICK. Return 0 if some are not.
10731
10732 If REPLACE is non-zero, replace the invalid reference with
10733 (clobber (const_int 0)) and return 1. This replacement is useful because
10734 we often can get useful information about the form of a value (e.g., if
10735 it was produced by a shift that always produces -1 or 0) even though
10736 we don't know exactly what registers it was produced from. */
10737
10738static int
9a893315 10739get_last_value_validate (loc, insn, tick, replace)
230d793d 10740 rtx *loc;
9a893315 10741 rtx insn;
230d793d
RS		 10742 int tick;
10743 int replace;
10744{
10745 rtx x = *loc;
10746 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10747 int len = GET_RTX_LENGTH (GET_CODE (x));
10748 int i;
10749
10750 if (GET_CODE (x) == REG)
10751 {
10752 int regno = REGNO (x);
10753 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10754 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10755 int j;
10756
10757 for (j = regno; j < endregno; j++)
10758 if (reg_last_set_invalid[j]
10759 /* If this is a pseudo-register that was only set once, it is
10760 always valid. */
b1f21e0a 10761 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
230d793d
RS		 10762 && reg_last_set_label[j] > tick))
10763 {
10764 if (replace)
38a448ca 10765 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
230d793d
RS		 10766 return replace;
10767 }
10768
10769 return 1;
10770 }
9a893315
JW		 10771 /* If this is a memory reference, make sure that there were
10772 no stores after it that might have clobbered the value. We don't
10773 have alias info, so we assume any store invalidates it. */
10774 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10775 && INSN_CUID (insn) <= mem_last_set)
10776 {
10777 if (replace)
38a448ca 10778 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9a893315
JW		 10779 return replace;
10780 }
230d793d
RS		 10781
10782 for (i = 0; i < len; i++)
10783 if ((fmt[i] == 'e'
9a893315 10784 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
230d793d
RS		 10785 /* Don't bother with these. They shouldn't occur anyway. */
10786 || fmt[i] == 'E')
10787 return 0;
10788
10789 /* If we haven't found a reason for it to be invalid, it is valid. */
10790 return 1;
10791}
10792
10793/* Get the last value assigned to X, if known. Some registers
10794 in the value may be replaced with (clobber (const_int 0)) if their value
10795 is known longer known reliably. */
10796
10797static rtx
10798get_last_value (x)
10799 rtx x;
10800{
10801 int regno;
10802 rtx value;
10803
10804 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10805 then convert it to the desired mode. If this is a paradoxical SUBREG,
0f41302f 10806 we cannot predict what values the "extra" bits might have. */
230d793d
RS		 10807 if (GET_CODE (x) == SUBREG
10808 && subreg_lowpart_p (x)
10809 && (GET_MODE_SIZE (GET_MODE (x))
10810 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10811 && (value = get_last_value (SUBREG_REG (x))) != 0)
10812 return gen_lowpart_for_combine (GET_MODE (x), value);
10813
10814 if (GET_CODE (x) != REG)
10815 return 0;
10816
10817 regno = REGNO (x);
10818 value = reg_last_set_value[regno];
10819
0f41302f
MS		 10820 /* If we don't have a value or if it isn't for this basic block,
10821 return 0. */
230d793d
RS		 10822
10823 if (value == 0
b1f21e0a 10824 || (REG_N_SETS (regno) != 1
55310dad 10825 && reg_last_set_label[regno] != label_tick))
230d793d
RS		 10826 return 0;
10827
4255220d 10828 /* If the value was set in a later insn than the ones we are processing,
4090a6b3
RK		 10829 we can't use it even if the register was only set once, but make a quick
10830 check to see if the previous insn set it to something. This is commonly
0d9641d1
JW		 10831 the case when the same pseudo is used by repeated insns.
10832
10833 This does not work if there exists an instruction which is temporarily
10834 not on the insn chain. */
d0ab8cd3 10835
bcd49eb7 10836 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
d0ab8cd3
RK		 10837 {
10838 rtx insn, set;
10839
bcd49eb7
JW		 10840 /* We can not do anything useful in this case, because there is
10841 an instruction which is not on the insn chain. */
10842 if (subst_prev_insn)
10843 return 0;
10844
4255220d
JW		 10845 /* Skip over USE insns. They are not useful here, and they may have
10846 been made by combine, in which case they do not have a INSN_CUID
d6c80562 10847 value. We can't use prev_real_insn, because that would incorrectly
e340018d
JW		 10848 take us backwards across labels. Skip over BARRIERs also, since
10849 they could have been made by combine. If we see one, we must be
10850 optimizing dead code, so it doesn't matter what we do. */
d6c80562
JW		 10851 for (insn = prev_nonnote_insn (subst_insn);
10852 insn && ((GET_CODE (insn) == INSN
10853 && GET_CODE (PATTERN (insn)) == USE)
e340018d 10854 || GET_CODE (insn) == BARRIER
4255220d 10855 || INSN_CUID (insn) >= subst_low_cuid);
d6c80562 10856 insn = prev_nonnote_insn (insn))
3adde2a5 10857 ;
d0ab8cd3
RK		 10858
10859 if (insn
10860 && (set = single_set (insn)) != 0
10861 && rtx_equal_p (SET_DEST (set), x))
10862 {
10863 value = SET_SRC (set);
10864
10865 /* Make sure that VALUE doesn't reference X. Replace any
ddd5a7c1 10866 explicit references with a CLOBBER. If there are any remaining
d0ab8cd3
RK		 10867 references (rare), don't use the value. */
10868
10869 if (reg_mentioned_p (x, value))
10870 value = replace_rtx (copy_rtx (value), x,
38a448ca 10871 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
d0ab8cd3
RK		 10872
10873 if (reg_overlap_mentioned_p (x, value))
10874 return 0;
10875 }
10876 else
10877 return 0;
10878 }
10879
10880 /* If the value has all its registers valid, return it. */
9a893315
JW		 10881 if (get_last_value_validate (&value, reg_last_set[regno],
10882 reg_last_set_label[regno], 0))
230d793d
RS		 10883 return value;
10884
10885 /* Otherwise, make a copy and replace any invalid register with
10886 (clobber (const_int 0)). If that fails for some reason, return 0. */
10887
10888 value = copy_rtx (value);
9a893315
JW		 10889 if (get_last_value_validate (&value, reg_last_set[regno],
10890 reg_last_set_label[regno], 1))
230d793d
RS		 10891 return value;
10892
10893 return 0;
10894}
10895\f
10896/* Return nonzero if expression X refers to a REG or to memory
10897 that is set in an instruction more recent than FROM_CUID. */
10898
10899static int
10900use_crosses_set_p (x, from_cuid)
10901 register rtx x;
10902 int from_cuid;
10903{
10904 register char *fmt;
10905 register int i;
10906 register enum rtx_code code = GET_CODE (x);
10907
10908 if (code == REG)
10909 {
10910 register int regno = REGNO (x);
e28f5732
RK		 10911 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10912 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10913
230d793d
RS		 10914#ifdef PUSH_ROUNDING
10915 /* Don't allow uses of the stack pointer to be moved,
10916 because we don't know whether the move crosses a push insn. */
10917 if (regno == STACK_POINTER_REGNUM)
10918 return 1;
10919#endif
e28f5732
RK		 10920 for (;regno < endreg; regno++)
10921 if (reg_last_set[regno]
10922 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10923 return 1;
10924 return 0;
230d793d
RS		 10925 }
10926
10927 if (code == MEM && mem_last_set > from_cuid)
10928 return 1;
10929
10930 fmt = GET_RTX_FORMAT (code);
10931
10932 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10933 {
10934 if (fmt[i] == 'E')
10935 {
10936 register int j;
10937 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10938 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10939 return 1;
10940 }
10941 else if (fmt[i] == 'e'
10942 && use_crosses_set_p (XEXP (x, i), from_cuid))
10943 return 1;
10944 }
10945 return 0;
10946}
10947\f
10948/* Define three variables used for communication between the following
10949 routines. */
10950
10951static int reg_dead_regno, reg_dead_endregno;
10952static int reg_dead_flag;
10953
10954/* Function called via note_stores from reg_dead_at_p.
10955
ddd5a7c1 10956 If DEST is within [reg_dead_regno, reg_dead_endregno), set
230d793d
RS		 10957 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10958
10959static void
10960reg_dead_at_p_1 (dest, x)
10961 rtx dest;
10962 rtx x;
10963{
10964 int regno, endregno;
10965
10966 if (GET_CODE (dest) != REG)
10967 return;
10968
10969 regno = REGNO (dest);
10970 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10971 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10972
10973 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10974 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10975}
10976
10977/* Return non-zero if REG is known to be dead at INSN.
10978
10979 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10980 referencing REG, it is dead. If we hit a SET referencing REG, it is
10981 live. Otherwise, see if it is live or dead at the start of the basic
6e25d159
RK		 10982 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10983 must be assumed to be always live. */
230d793d
RS		 10984
10985static int
10986reg_dead_at_p (reg, insn)
10987 rtx reg;
10988 rtx insn;
10989{
10990 int block, i;
10991
10992 /* Set variables for reg_dead_at_p_1. */
10993 reg_dead_regno = REGNO (reg);
10994 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10995 ? HARD_REGNO_NREGS (reg_dead_regno,
10996 GET_MODE (reg))
10997 : 1);
10998
10999 reg_dead_flag = 0;
11000
6e25d159
RK		 11001 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11002 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11003 {
11004 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11005 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11006 return 0;
11007 }
11008
230d793d
RS		 11009 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11010 beginning of function. */
60715d0b 11011 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
230d793d
RS		 11012 insn = prev_nonnote_insn (insn))
11013 {
11014 note_stores (PATTERN (insn), reg_dead_at_p_1);
11015 if (reg_dead_flag)
11016 return reg_dead_flag == 1 ? 1 : 0;
11017
11018 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11019 return 1;
11020 }
11021
11022 /* Get the basic block number that we were in. */
11023 if (insn == 0)
11024 block = 0;
11025 else
11026 {
11027 for (block = 0; block < n_basic_blocks; block++)
11028 if (insn == basic_block_head[block])
11029 break;
11030
11031 if (block == n_basic_blocks)
11032 return 0;
11033 }
11034
11035 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8e08106d 11036 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
230d793d
RS		 11037 return 0;
11038
11039 return 1;
11040}
6e25d159
RK		 11041\f
11042/* Note hard registers in X that are used. This code is similar to
11043 that in flow.c, but much simpler since we don't care about pseudos. */
11044
11045static void
11046mark_used_regs_combine (x)
11047 rtx x;
11048{
11049 register RTX_CODE code = GET_CODE (x);
11050 register int regno;
11051 int i;
11052
11053 switch (code)
11054 {
11055 case LABEL_REF:
11056 case SYMBOL_REF:
11057 case CONST_INT:
11058 case CONST:
11059 case CONST_DOUBLE:
11060 case PC:
11061 case ADDR_VEC:
11062 case ADDR_DIFF_VEC:
11063 case ASM_INPUT:
11064#ifdef HAVE_cc0
11065 /* CC0 must die in the insn after it is set, so we don't need to take
11066 special note of it here. */
11067 case CC0:
11068#endif
11069 return;
11070
11071 case CLOBBER:
11072 /* If we are clobbering a MEM, mark any hard registers inside the
11073 address as used. */
11074 if (GET_CODE (XEXP (x, 0)) == MEM)
11075 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11076 return;
11077
11078 case REG:
11079 regno = REGNO (x);
11080 /* A hard reg in a wide mode may really be multiple registers.
11081 If so, mark all of them just like the first. */
11082 if (regno < FIRST_PSEUDO_REGISTER)
11083 {
11084 /* None of this applies to the stack, frame or arg pointers */
11085 if (regno == STACK_POINTER_REGNUM
11086#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11087 || regno == HARD_FRAME_POINTER_REGNUM
11088#endif
11089#if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11090 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11091#endif
11092 || regno == FRAME_POINTER_REGNUM)
11093 return;
11094
11095 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11096 while (i-- > 0)
11097 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11098 }
11099 return;
11100
11101 case SET:
11102 {
11103 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11104 the address. */
11105 register rtx testreg = SET_DEST (x);
11106
e048778f
RK		 11107 while (GET_CODE (testreg) == SUBREG
11108 || GET_CODE (testreg) == ZERO_EXTRACT
11109 || GET_CODE (testreg) == SIGN_EXTRACT
11110 || GET_CODE (testreg) == STRICT_LOW_PART)
6e25d159
RK		 11111 testreg = XEXP (testreg, 0);
11112
11113 if (GET_CODE (testreg) == MEM)
11114 mark_used_regs_combine (XEXP (testreg, 0));
11115
11116 mark_used_regs_combine (SET_SRC (x));
6e25d159 11117 }
e9a25f70
JL		 11118 return;
11119
11120 default:
11121 break;
6e25d159
RK		 11122 }
11123
11124 /* Recursively scan the operands of this expression. */
11125
11126 {
11127 register char *fmt = GET_RTX_FORMAT (code);
11128
11129 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11130 {
11131 if (fmt[i] == 'e')
11132 mark_used_regs_combine (XEXP (x, i));
11133 else if (fmt[i] == 'E')
11134 {
11135 register int j;
11136
11137 for (j = 0; j < XVECLEN (x, i); j++)
11138 mark_used_regs_combine (XVECEXP (x, i, j));
11139 }
11140 }
11141 }
11142}
11143
230d793d
RS		 11144\f
11145/* Remove register number REGNO from the dead registers list of INSN.
11146
11147 Return the note used to record the death, if there was one. */
11148
11149rtx
11150remove_death (regno, insn)
11151 int regno;
11152 rtx insn;
11153{
11154 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11155
11156 if (note)
1a26b032 11157 {
b1f21e0a 11158 REG_N_DEATHS (regno)--;
1a26b032
RK		 11159 remove_note (insn, note);
11160 }
230d793d
RS		 11161
11162 return note;
11163}
11164
11165/* For each register (hardware or pseudo) used within expression X, if its
11166 death is in an instruction with cuid between FROM_CUID (inclusive) and
11167 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11168 list headed by PNOTES.
11169
6eb12cef
RK		 11170 That said, don't move registers killed by maybe_kill_insn.
11171
230d793d
RS		 11172 This is done when X is being merged by combination into TO_INSN. These
11173 notes will then be distributed as needed. */
11174
11175static void
6eb12cef 11176move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
230d793d 11177 rtx x;
6eb12cef 11178 rtx maybe_kill_insn;
230d793d
RS		 11179 int from_cuid;
11180 rtx to_insn;
11181 rtx *pnotes;
11182{
11183 register char *fmt;
11184 register int len, i;
11185 register enum rtx_code code = GET_CODE (x);
11186
11187 if (code == REG)
11188 {
11189 register int regno = REGNO (x);
11190 register rtx where_dead = reg_last_death[regno];
e340018d
JW		 11191 register rtx before_dead, after_dead;
11192
6eb12cef
RK		 11193 /* Don't move the register if it gets killed in between from and to */
11194 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11195 && !reg_referenced_p (x, maybe_kill_insn))
11196 return;
11197
e340018d
JW		 11198 /* WHERE_DEAD could be a USE insn made by combine, so first we
11199 make sure that we have insns with valid INSN_CUID values. */
11200 before_dead = where_dead;
11201 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11202 before_dead = PREV_INSN (before_dead);
11203 after_dead = where_dead;
11204 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11205 after_dead = NEXT_INSN (after_dead);
11206
11207 if (before_dead && after_dead
11208 && INSN_CUID (before_dead) >= from_cuid
11209 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11210 || (where_dead != after_dead
11211 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
230d793d 11212 {
dbc131f3 11213 rtx note = remove_death (regno, where_dead);
230d793d
RS		 11214
11215 /* It is possible for the call above to return 0. This can occur
11216 when reg_last_death points to I2 or I1 that we combined with.
dbc131f3
RK		 11217 In that case make a new note.
11218
11219 We must also check for the case where X is a hard register
11220 and NOTE is a death note for a range of hard registers
11221 including X. In that case, we must put REG_DEAD notes for
11222 the remaining registers in place of NOTE. */
11223
11224 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11225 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
24e46fc4 11226 > GET_MODE_SIZE (GET_MODE (x))))
dbc131f3
RK		 11227 {
11228 int deadregno = REGNO (XEXP (note, 0));
11229 int deadend
11230 = (deadregno + HARD_REGNO_NREGS (deadregno,
11231 GET_MODE (XEXP (note, 0))));
11232 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11233 int i;
11234
11235 for (i = deadregno; i < deadend; i++)
11236 if (i < regno || i >= ourend)
11237 REG_NOTES (where_dead)
38a448ca
RH		 11238 = gen_rtx_EXPR_LIST (REG_DEAD,
11239 gen_rtx_REG (reg_raw_mode[i], i),
11240 REG_NOTES (where_dead));
dbc131f3 11241 }
24e46fc4
JW		 11242 /* If we didn't find any note, or if we found a REG_DEAD note that
11243 covers only part of the given reg, and we have a multi-reg hard
fabd69e8
RK		 11244 register, then to be safe we must check for REG_DEAD notes
11245 for each register other than the first. They could have
11246 their own REG_DEAD notes lying around. */
24e46fc4
JW		 11247 else if ((note == 0
11248 || (note != 0
11249 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11250 < GET_MODE_SIZE (GET_MODE (x)))))
11251 && regno < FIRST_PSEUDO_REGISTER
fabd69e8
RK		 11252 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11253 {
11254 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
24e46fc4 11255 int i, offset;
fabd69e8
RK		 11256 rtx oldnotes = 0;
11257
24e46fc4
JW		 11258 if (note)
11259 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11260 else
11261 offset = 1;
11262
11263 for (i = regno + offset; i < ourend; i++)
38a448ca 11264 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
6eb12cef 11265 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
fabd69e8 11266 }
230d793d 11267
dbc131f3 11268 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
230d793d
RS		 11269 {
11270 XEXP (note, 1) = *pnotes;
11271 *pnotes = note;
11272 }
11273 else
38a448ca 11274 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
1a26b032 11275
b1f21e0a 11276 REG_N_DEATHS (regno)++;
230d793d
RS		 11277 }
11278
11279 return;
11280 }
11281
11282 else if (GET_CODE (x) == SET)
11283 {
11284 rtx dest = SET_DEST (x);
11285
6eb12cef 11286 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d 11287
a7c99304
RK		 11288 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11289 that accesses one word of a multi-word item, some
11290 piece of everything register in the expression is used by
11291 this insn, so remove any old death. */
11292
11293 if (GET_CODE (dest) == ZERO_EXTRACT
11294 || GET_CODE (dest) == STRICT_LOW_PART
11295 || (GET_CODE (dest) == SUBREG
11296 && (((GET_MODE_SIZE (GET_MODE (dest))
11297 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11298 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11299 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
230d793d 11300 {
6eb12cef 11301 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
a7c99304 11302 return;
230d793d
RS		 11303 }
11304
a7c99304
RK		 11305 /* If this is some other SUBREG, we know it replaces the entire
11306 value, so use that as the destination. */
11307 if (GET_CODE (dest) == SUBREG)
11308 dest = SUBREG_REG (dest);
11309
11310 /* If this is a MEM, adjust deaths of anything used in the address.
11311 For a REG (the only other possibility), the entire value is
11312 being replaced so the old value is not used in this insn. */
230d793d
RS		 11313
11314 if (GET_CODE (dest) == MEM)
6eb12cef
RK		 11315 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11316 to_insn, pnotes);
230d793d
RS		 11317 return;
11318 }
11319
11320 else if (GET_CODE (x) == CLOBBER)
11321 return;
11322
11323 len = GET_RTX_LENGTH (code);
11324 fmt = GET_RTX_FORMAT (code);
11325
11326 for (i = 0; i < len; i++)
11327 {
11328 if (fmt[i] == 'E')
11329 {
11330 register int j;
11331 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6eb12cef
RK		 11332 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11333 to_insn, pnotes);
230d793d
RS		 11334 }
11335 else if (fmt[i] == 'e')
6eb12cef 11336 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
230d793d
RS		 11337 }
11338}
11339\f
a7c99304
RK		 11340/* Return 1 if X is the target of a bit-field assignment in BODY, the
11341 pattern of an insn. X must be a REG. */
230d793d
RS		 11342
11343static int
a7c99304
RK		 11344reg_bitfield_target_p (x, body)
11345 rtx x;
230d793d
RS		 11346 rtx body;
11347{
11348 int i;
11349
11350 if (GET_CODE (body) == SET)
a7c99304
RK		 11351 {
11352 rtx dest = SET_DEST (body);
11353 rtx target;
11354 int regno, tregno, endregno, endtregno;
11355
11356 if (GET_CODE (dest) == ZERO_EXTRACT)
11357 target = XEXP (dest, 0);
11358 else if (GET_CODE (dest) == STRICT_LOW_PART)
11359 target = SUBREG_REG (XEXP (dest, 0));
11360 else
11361 return 0;
11362
11363 if (GET_CODE (target) == SUBREG)
11364 target = SUBREG_REG (target);
11365
11366 if (GET_CODE (target) != REG)
11367 return 0;
11368
11369 tregno = REGNO (target), regno = REGNO (x);
11370 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11371 return target == x;
11372
11373 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11374 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11375
11376 return endregno > tregno && regno < endtregno;
11377 }
230d793d
RS		 11378
11379 else if (GET_CODE (body) == PARALLEL)
11380 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
a7c99304 11381 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
230d793d
RS		 11382 return 1;
11383
11384 return 0;
11385}
11386\f
11387/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11388 as appropriate. I3 and I2 are the insns resulting from the combination
11389 insns including FROM (I2 may be zero).
11390
11391 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11392 not need REG_DEAD notes because they are being substituted for. This
11393 saves searching in the most common cases.
11394
11395 Each note in the list is either ignored or placed on some insns, depending
11396 on the type of note. */
11397
11398static void
11399distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11400 rtx notes;
11401 rtx from_insn;
11402 rtx i3, i2;
11403 rtx elim_i2, elim_i1;
11404{
11405 rtx note, next_note;
11406 rtx tem;
11407
11408 for (note = notes; note; note = next_note)
11409 {
11410 rtx place = 0, place2 = 0;
11411
11412 /* If this NOTE references a pseudo register, ensure it references
11413 the latest copy of that register. */
11414 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11415 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11416 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11417
11418 next_note = XEXP (note, 1);
11419 switch (REG_NOTE_KIND (note))
11420 {
c9903b44
DE		 11421 case REG_BR_PROB:
11422 case REG_EXEC_COUNT:
11423 /* Doesn't matter much where we put this, as long as it's somewhere.
11424 It is preferable to keep these notes on branches, which is most
11425 likely to be i3. */
11426 place = i3;
11427 break;
11428
230d793d 11429 case REG_UNUSED:
07d0cbdd 11430 /* Any clobbers for i3 may still exist, and so we must process
176c9e6b
JW		 11431 REG_UNUSED notes from that insn.
11432
11433 Any clobbers from i2 or i1 can only exist if they were added by
11434 recog_for_combine. In that case, recog_for_combine created the
11435 necessary REG_UNUSED notes. Trying to keep any original
11436 REG_UNUSED notes from these insns can cause incorrect output
11437 if it is for the same register as the original i3 dest.
11438 In that case, we will notice that the register is set in i3,
11439 and then add a REG_UNUSED note for the destination of i3, which
07d0cbdd
JW		 11440 is wrong. However, it is possible to have REG_UNUSED notes from
11441 i2 or i1 for register which were both used and clobbered, so
11442 we keep notes from i2 or i1 if they will turn into REG_DEAD
11443 notes. */
176c9e6b 11444
230d793d
RS		 11445 /* If this register is set or clobbered in I3, put the note there
11446 unless there is one already. */
07d0cbdd 11447 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
230d793d 11448 {
07d0cbdd
JW		 11449 if (from_insn != i3)
11450 break;
11451
230d793d
RS		 11452 if (! (GET_CODE (XEXP (note, 0)) == REG
11453 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11454 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11455 place = i3;
11456 }
11457 /* Otherwise, if this register is used by I3, then this register
11458 now dies here, so we must put a REG_DEAD note here unless there
11459 is one already. */
11460 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11461 && ! (GET_CODE (XEXP (note, 0)) == REG
11462 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11463 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11464 {
11465 PUT_REG_NOTE_KIND (note, REG_DEAD);
11466 place = i3;
11467 }
11468 break;
11469
11470 case REG_EQUAL:
11471 case REG_EQUIV:
11472 case REG_NONNEG:
9ae8ffe7 11473 case REG_NOALIAS:
230d793d
RS		 11474 /* These notes say something about results of an insn. We can
11475 only support them if they used to be on I3 in which case they
a687e897
RK		 11476 remain on I3. Otherwise they are ignored.
11477
11478 If the note refers to an expression that is not a constant, we
11479 must also ignore the note since we cannot tell whether the
11480 equivalence is still true. It might be possible to do
11481 slightly better than this (we only have a problem if I2DEST
11482 or I1DEST is present in the expression), but it doesn't
11483 seem worth the trouble. */
11484
11485 if (from_insn == i3
11486 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
230d793d
RS		 11487 place = i3;
11488 break;
11489
11490 case REG_INC:
11491 case REG_NO_CONFLICT:
11492 case REG_LABEL:
11493 /* These notes say something about how a register is used. They must
11494 be present on any use of the register in I2 or I3. */
11495 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11496 place = i3;
11497
11498 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11499 {
11500 if (place)
11501 place2 = i2;
11502 else
11503 place = i2;
11504 }
11505 break;
11506
11507 case REG_WAS_0:
11508 /* It is too much trouble to try to see if this note is still
11509 correct in all situations. It is better to simply delete it. */
11510 break;
11511
11512 case REG_RETVAL:
11513 /* If the insn previously containing this note still exists,
11514 put it back where it was. Otherwise move it to the previous
11515 insn. Adjust the corresponding REG_LIBCALL note. */
11516 if (GET_CODE (from_insn) != NOTE)
11517 place = from_insn;
11518 else
11519 {
5f4f0e22 11520 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
230d793d
RS		 11521 place = prev_real_insn (from_insn);
11522 if (tem && place)
11523 XEXP (tem, 0) = place;
11524 }
11525 break;
11526
11527 case REG_LIBCALL:
11528 /* This is handled similarly to REG_RETVAL. */
11529 if (GET_CODE (from_insn) != NOTE)
11530 place = from_insn;
11531 else
11532 {
5f4f0e22 11533 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
230d793d
RS		 11534 place = next_real_insn (from_insn);
11535 if (tem && place)
11536 XEXP (tem, 0) = place;
11537 }
11538 break;
11539
11540 case REG_DEAD:
11541 /* If the register is used as an input in I3, it dies there.
11542 Similarly for I2, if it is non-zero and adjacent to I3.
11543
11544 If the register is not used as an input in either I3 or I2
11545 and it is not one of the registers we were supposed to eliminate,
11546 there are two possibilities. We might have a non-adjacent I2
11547 or we might have somehow eliminated an additional register
11548 from a computation. For example, we might have had A & B where
11549 we discover that B will always be zero. In this case we will
11550 eliminate the reference to A.
11551
11552 In both cases, we must search to see if we can find a previous
11553 use of A and put the death note there. */
11554
6e2d1486
RK		 11555 if (from_insn
11556 && GET_CODE (from_insn) == CALL_INSN
11557 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11558 place = from_insn;
11559 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
230d793d
RS		 11560 place = i3;
11561 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11562 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11563 place = i2;
11564
11565 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11566 break;
11567
510dd77e
RK		 11568 /* If the register is used in both I2 and I3 and it dies in I3,
11569 we might have added another reference to it. If reg_n_refs
11570 was 2, bump it to 3. This has to be correct since the
11571 register must have been set somewhere. The reason this is
11572 done is because local-alloc.c treats 2 references as a
11573 special case. */
11574
11575 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
b1f21e0a 11576 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
510dd77e 11577 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
b1f21e0a 11578 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
510dd77e 11579
230d793d 11580 if (place == 0)
38d8473f
RK		 11581 {
11582 for (tem = prev_nonnote_insn (i3);
11583 place == 0 && tem
11584 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11585 tem = prev_nonnote_insn (tem))
11586 {
11587 /* If the register is being set at TEM, see if that is all
11588 TEM is doing. If so, delete TEM. Otherwise, make this
11589 into a REG_UNUSED note instead. */
11590 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11591 {
11592 rtx set = single_set (tem);
e5e809f4 11593 rtx inner_dest = 0;
e51712db 11594#ifdef HAVE_cc0
f5c97640 11595 rtx cc0_setter = NULL_RTX;
e51712db 11596#endif
e5e809f4
JL		 11597
11598 if (set != 0)
11599 for (inner_dest = SET_DEST (set);
11600 GET_CODE (inner_dest) == STRICT_LOW_PART
11601 || GET_CODE (inner_dest) == SUBREG
11602 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11603 inner_dest = XEXP (inner_dest, 0))
11604 ;
38d8473f
RK		 11605
11606 /* Verify that it was the set, and not a clobber that
f5c97640
RH		 11607 modified the register.
11608
11609 CC0 targets must be careful to maintain setter/user
11610 pairs. If we cannot delete the setter due to side
11611 effects, mark the user with an UNUSED note instead
11612 of deleting it. */
38d8473f
RK		 11613
11614 if (set != 0 && ! side_effects_p (SET_SRC (set))
f5c97640
RH		 11615 && rtx_equal_p (XEXP (note, 0), inner_dest)
11616#ifdef HAVE_cc0
11617 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11618 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11619 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11620#endif
11621 )
38d8473f
RK		 11622 {
11623 /* Move the notes and links of TEM elsewhere.
11624 This might delete other dead insns recursively.
11625 First set the pattern to something that won't use
11626 any register. */
11627
11628 PATTERN (tem) = pc_rtx;
11629
11630 distribute_notes (REG_NOTES (tem), tem, tem,
11631 NULL_RTX, NULL_RTX, NULL_RTX);
11632 distribute_links (LOG_LINKS (tem));
11633
11634 PUT_CODE (tem, NOTE);
11635 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11636 NOTE_SOURCE_FILE (tem) = 0;
f5c97640
RH		 11637
11638#ifdef HAVE_cc0
11639 /* Delete the setter too. */
11640 if (cc0_setter)
11641 {
11642 PATTERN (cc0_setter) = pc_rtx;
11643
11644 distribute_notes (REG_NOTES (cc0_setter),
11645 cc0_setter, cc0_setter,
11646 NULL_RTX, NULL_RTX, NULL_RTX);
11647 distribute_links (LOG_LINKS (cc0_setter));
11648
11649 PUT_CODE (cc0_setter, NOTE);
11650 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED;
11651 NOTE_SOURCE_FILE (cc0_setter) = 0;
11652 }
11653#endif
38d8473f 11654 }
e5e809f4
JL		 11655 /* If the register is both set and used here, put the
11656 REG_DEAD note here, but place a REG_UNUSED note
11657 here too unless there already is one. */
11658 else if (reg_referenced_p (XEXP (note, 0),
11659 PATTERN (tem)))
11660 {
11661 place = tem;
11662
11663 if (! find_regno_note (tem, REG_UNUSED,
11664 REGNO (XEXP (note, 0))))
11665 REG_NOTES (tem)
9e6a5703
JC		 11666 = gen_rtx_EXPR_LIST (REG_UNUSED,
11667 XEXP (note, 0),
11668 REG_NOTES (tem));
e5e809f4 11669 }
38d8473f
RK		 11670 else
11671 {
11672 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11673
11674 /* If there isn't already a REG_UNUSED note, put one
11675 here. */
11676 if (! find_regno_note (tem, REG_UNUSED,
11677 REGNO (XEXP (note, 0))))
11678 place = tem;
11679 break;
230d793d
RS		 11680 }
11681 }
13018fad
RE		 11682 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11683 || (GET_CODE (tem) == CALL_INSN
11684 && find_reg_fusage (tem, USE, XEXP (note, 0))))
230d793d
RS		 11685 {
11686 place = tem;
932d1119
RK		 11687
11688 /* If we are doing a 3->2 combination, and we have a
11689 register which formerly died in i3 and was not used
11690 by i2, which now no longer dies in i3 and is used in
11691 i2 but does not die in i2, and place is between i2
11692 and i3, then we may need to move a link from place to
11693 i2. */
a8908849
RK		 11694 if (i2 && INSN_UID (place) <= max_uid_cuid
11695 && INSN_CUID (place) > INSN_CUID (i2)
932d1119
RK		 11696 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11697 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11698 {
11699 rtx links = LOG_LINKS (place);
11700 LOG_LINKS (place) = 0;
11701 distribute_links (links);
11702 }
230d793d
RS		 11703 break;
11704 }
38d8473f
RK		 11705 }
11706
11707 /* If we haven't found an insn for the death note and it
11708 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11709 insert a USE insn for the register at that label and
11710 put the death node there. This prevents problems with
11711 call-state tracking in caller-save.c. */
11712 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
e2cce0cf
RK		 11713 {
11714 place
38a448ca 11715 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
e2cce0cf
RK		 11716 tem);
11717
11718 /* If this insn was emitted between blocks, then update
11719 basic_block_head of the current block to include it. */
11720 if (basic_block_end[this_basic_block - 1] == tem)
11721 basic_block_head[this_basic_block] = place;
11722 }
38d8473f 11723 }
230d793d
RS		 11724
11725 /* If the register is set or already dead at PLACE, we needn't do
e5e809f4
JL		 11726 anything with this note if it is still a REG_DEAD note.
11727 We can here if it is set at all, not if is it totally replace,
11728 which is what `dead_or_set_p' checks, so also check for it being
11729 set partially. */
11730
230d793d 11731
230d793d
RS		 11732 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11733 {
11734 int regno = REGNO (XEXP (note, 0));
11735
11736 if (dead_or_set_p (place, XEXP (note, 0))
11737 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11738 {
11739 /* Unless the register previously died in PLACE, clear
11740 reg_last_death. [I no longer understand why this is
11741 being done.] */
11742 if (reg_last_death[regno] != place)
11743 reg_last_death[regno] = 0;
11744 place = 0;
11745 }
11746 else
11747 reg_last_death[regno] = place;
11748
11749 /* If this is a death note for a hard reg that is occupying
11750 multiple registers, ensure that we are still using all
11751 parts of the object. If we find a piece of the object
11752 that is unused, we must add a USE for that piece before
11753 PLACE and put the appropriate REG_DEAD note on it.
11754
11755 An alternative would be to put a REG_UNUSED for the pieces
11756 on the insn that set the register, but that can't be done if
11757 it is not in the same block. It is simpler, though less
11758 efficient, to add the USE insns. */
11759
11760 if (place && regno < FIRST_PSEUDO_REGISTER
11761 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11762 {
11763 int endregno
11764 = regno + HARD_REGNO_NREGS (regno,
11765 GET_MODE (XEXP (note, 0)));
11766 int all_used = 1;
11767 int i;
11768
11769 for (i = regno; i < endregno; i++)
9fd5bb62
JW		 11770 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11771 && ! find_regno_fusage (place, USE, i))
230d793d 11772 {
38a448ca 11773 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
28f6d3af
RK		 11774 rtx p;
11775
11776 /* See if we already placed a USE note for this
11777 register in front of PLACE. */
11778 for (p = place;
11779 GET_CODE (PREV_INSN (p)) == INSN
11780 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11781 p = PREV_INSN (p))
11782 if (rtx_equal_p (piece,
11783 XEXP (PATTERN (PREV_INSN (p)), 0)))
11784 {
11785 p = 0;
11786 break;
11787 }
11788
11789 if (p)
11790 {
11791 rtx use_insn
38a448ca
RH		 11792 = emit_insn_before (gen_rtx_USE (VOIDmode,
11793 piece),
28f6d3af
RK		 11794 p);
11795 REG_NOTES (use_insn)
38a448ca
RH		 11796 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11797 REG_NOTES (use_insn));
28f6d3af 11798 }
230d793d 11799
5089e22e 11800 all_used = 0;
230d793d
RS		 11801 }
11802
a394b17b
JW		 11803 /* Check for the case where the register dying partially
11804 overlaps the register set by this insn. */
11805 if (all_used)
11806 for (i = regno; i < endregno; i++)
11807 if (dead_or_set_regno_p (place, i))
11808 {
11809 all_used = 0;
11810 break;
11811 }
11812
230d793d
RS		 11813 if (! all_used)
11814 {
11815 /* Put only REG_DEAD notes for pieces that are
11816 still used and that are not already dead or set. */
11817
11818 for (i = regno; i < endregno; i++)
11819 {
38a448ca 11820 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
230d793d 11821
17cbf358
JW		 11822 if ((reg_referenced_p (piece, PATTERN (place))
11823 || (GET_CODE (place) == CALL_INSN
11824 && find_reg_fusage (place, USE, piece)))
230d793d
RS		 11825 && ! dead_or_set_p (place, piece)
11826 && ! reg_bitfield_target_p (piece,
11827 PATTERN (place)))
38a448ca
RH		 11828 REG_NOTES (place)
11829 = gen_rtx_EXPR_LIST (REG_DEAD,
11830 piece, REG_NOTES (place));
230d793d
RS		 11831 }
11832
11833 place = 0;
11834 }
11835 }
11836 }
11837 break;
11838
11839 default:
11840 /* Any other notes should not be present at this point in the
11841 compilation. */
11842 abort ();
11843 }
11844
11845 if (place)
11846 {
11847 XEXP (note, 1) = REG_NOTES (place);
11848 REG_NOTES (place) = note;
11849 }
1a26b032
RK		 11850 else if ((REG_NOTE_KIND (note) == REG_DEAD
11851 || REG_NOTE_KIND (note) == REG_UNUSED)
11852 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11853 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
230d793d
RS		 11854
11855 if (place2)
1a26b032
RK		 11856 {
11857 if ((REG_NOTE_KIND (note) == REG_DEAD
11858 || REG_NOTE_KIND (note) == REG_UNUSED)
11859 && GET_CODE (XEXP (note, 0)) == REG)
b1f21e0a 11860 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
1a26b032 11861
38a448ca
RH		 11862 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11863 REG_NOTE_KIND (note),
11864 XEXP (note, 0),
11865 REG_NOTES (place2));
1a26b032 11866 }
230d793d
RS		 11867 }
11868}
11869\f
11870/* Similarly to above, distribute the LOG_LINKS that used to be present on
5089e22e
RS		 11871 I3, I2, and I1 to new locations. This is also called in one case to
11872 add a link pointing at I3 when I3's destination is changed. */
230d793d
RS		 11873
11874static void
11875distribute_links (links)
11876 rtx links;
11877{
11878 rtx link, next_link;
11879
11880 for (link = links; link; link = next_link)
11881 {
11882 rtx place = 0;
11883 rtx insn;
11884 rtx set, reg;
11885
11886 next_link = XEXP (link, 1);
11887
11888 /* If the insn that this link points to is a NOTE or isn't a single
11889 set, ignore it. In the latter case, it isn't clear what we
11890 can do other than ignore the link, since we can't tell which
11891 register it was for. Such links wouldn't be used by combine
11892 anyway.
11893
11894 It is not possible for the destination of the target of the link to
11895 have been changed by combine. The only potential of this is if we
11896 replace I3, I2, and I1 by I3 and I2. But in that case the
11897 destination of I2 also remains unchanged. */
11898
11899 if (GET_CODE (XEXP (link, 0)) == NOTE
11900 || (set = single_set (XEXP (link, 0))) == 0)
11901 continue;
11902
11903 reg = SET_DEST (set);
11904 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11905 || GET_CODE (reg) == SIGN_EXTRACT
11906 || GET_CODE (reg) == STRICT_LOW_PART)
11907 reg = XEXP (reg, 0);
11908
11909 /* A LOG_LINK is defined as being placed on the first insn that uses
11910 a register and points to the insn that sets the register. Start
11911 searching at the next insn after the target of the link and stop
11912 when we reach a set of the register or the end of the basic block.
11913
11914 Note that this correctly handles the link that used to point from
5089e22e 11915 I3 to I2. Also note that not much searching is typically done here
230d793d
RS		 11916 since most links don't point very far away. */
11917
11918 for (insn = NEXT_INSN (XEXP (link, 0));
0d4d42c3
RK		 11919 (insn && (this_basic_block == n_basic_blocks - 1
11920 || basic_block_head[this_basic_block + 1] != insn));
230d793d
RS		 11921 insn = NEXT_INSN (insn))
11922 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11923 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11924 {
11925 if (reg_referenced_p (reg, PATTERN (insn)))
11926 place = insn;
11927 break;
11928 }
6e2d1486
RK		 11929 else if (GET_CODE (insn) == CALL_INSN
11930 && find_reg_fusage (insn, USE, reg))
11931 {
11932 place = insn;
11933 break;
11934 }
230d793d
RS		 11935
11936 /* If we found a place to put the link, place it there unless there
11937 is already a link to the same insn as LINK at that point. */
11938
11939 if (place)
11940 {
11941 rtx link2;
11942
11943 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11944 if (XEXP (link2, 0) == XEXP (link, 0))
11945 break;
11946
11947 if (link2 == 0)
11948 {
11949 XEXP (link, 1) = LOG_LINKS (place);
11950 LOG_LINKS (place) = link;
abe6e52f
RK		 11951
11952 /* Set added_links_insn to the earliest insn we added a
11953 link to. */
11954 if (added_links_insn == 0
11955 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11956 added_links_insn = place;
230d793d
RS		 11957 }
11958 }
11959 }
11960}
11961\f
1427d6d2
RK		 11962/* Compute INSN_CUID for INSN, which is an insn made by combine. */
11963
11964static int
11965insn_cuid (insn)
11966 rtx insn;
11967{
11968 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11969 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11970 insn = NEXT_INSN (insn);
11971
11972 if (INSN_UID (insn) > max_uid_cuid)
11973 abort ();
11974
11975 return INSN_CUID (insn);
11976}
11977\f
230d793d
RS		 11978void
11979dump_combine_stats (file)
11980 FILE *file;
11981{
11982 fprintf
11983 (file,
11984 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11985 combine_attempts, combine_merges, combine_extras, combine_successes);
11986}
11987
11988void
11989dump_combine_total_stats (file)
11990 FILE *file;
11991{
11992 fprintf
11993 (file,
11994 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11995 total_attempts, total_merges, total_extras, total_successes);
11996}
GNU Compiler Collection
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