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Commit | Line | Data |
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6b3a60e3 RM |
1 | 3. When find_reloads is used to count number of spills needed |
2 | it does not take into account the fact that a reload may | |
3 | turn out to be a dummy. | |
4 | ||
5 | I'm not sure this really happens any more. Doesn't it find | |
6 | all the dummies on both passes? | |
7 | ||
8 | 10. movl a3@,a0 | |
9 | movl a3@(16),a1 | |
10 | clrb a0@(a1:l) | |
11 | is generated and may be worse than | |
12 | movl a3@,a0 | |
13 | addl a3@(16),a0 | |
14 | clrb a0@ | |
15 | If ordering of operands is improved, many more | |
16 | such cases will be generated from typical array accesses. | |
17 | ||
18 | 38. Hack expand_mult so that if there is no same-modes multiply | |
19 | it will use a widening multiply and then truncate rather than | |
20 | calling the library. | |
21 | ||
22 | 39. Hack expanding of division to notice cases for | |
23 | long -> short division. | |
24 | ||
25 | 40. Represent divide insns as (DIV:SI ...) followed by | |
26 | a separate lowpart extract. Represent remainder insns as DIV:SI | |
27 | followed by a separate highpart extract. Then cse can work on | |
28 | the DIV:SI part. Problem is, this may not be desirable on machines | |
29 | where computing the quotient alone does not necessarily give | |
30 | a remainder--such as the 68020 for long operands. | |
31 | ||
32 | 52. Reloading can look at how reload_contents got set up. | |
33 | If it was copied from a register, just reload from that register. | |
34 | Otherwise, perhaps can change the previous insn to move the | |
35 | data via the reload reg, thus avoiding one memory ref. | |
36 | ||
37 | 63. Potential problem in cc_status.value2, if it ever activates itself | |
38 | after a two-address subtraction (which currently cannot happen). | |
39 | It is supposed to compare the current value of the destination | |
40 | but eliminating it would use the results of the subtraction, equivalent | |
41 | to comparing the previous value of the destination. | |
42 | ||
43 | 65. Should loops that neither start nor end with a break | |
44 | be rearranged to end with the last break? | |
45 | ||
46 | 69. Define the floating point converting arithmetic instructions | |
47 | for the 68881. | |
48 | ||
49 | 74. Combine loop opt with cse opt in one pass. Do cse on each loop, | |
50 | then loop opt on that loop, and go from innermost loops outward. | |
51 | Make loop invariants available for cse at end of loop. | |
52 | ||
53 | 85. pea can force a value to be reloaded into an areg | |
54 | which can make it worse than separate adding and pushing. | |
55 | This can only happen for adding something within addql range | |
56 | and it only loses if the qty becomes dead at that point | |
57 | so it can be added to with no copying. | |
58 | ||
59 | 93. If a pseudo doesn't get a hard reg everywhere, | |
60 | can it get one during a loop? | |
61 | ||
62 | 96. Can do SImode bitfield insns without reloading, but must | |
63 | alter the operands in special ways. | |
64 | ||
65 | 99. final could check loop-entry branches to see if they | |
66 | screw up deletion of a test instruction. If they do, | |
67 | can put another test instruction before the branch and | |
68 | make it conditional and redirect it. | |
69 | ||
70 | 106. Aliasing may be impossible if data types of refs differ | |
71 | and data type of containing objects also differ. | |
72 | (But check this wrt unions.) | |
73 | ||
74 | 108. Can speed up flow analysis by making a table saying which | |
75 | register is set and which registers are used by each instruction that | |
76 | only sets one register and only uses two. This way avoid the tree | |
77 | walk for such instructions (most instructions). | |
78 | ||
79 | 109. It is desirable to avoid converting INDEX to SImode if a | |
80 | narrower mode suffices, as HImode does on the 68000. | |
81 | How can this be done? | |
82 | ||
83 | 110. Possible special combination pattern: | |
84 | If the two operands to a comparison die there and both come from insns | |
85 | that are identical except for replacing one operand with the other, | |
86 | throw away those insns. Ok if insns being discarded are known 1 to 1. | |
87 | An andl #1 after a seq is 1 to 1, but how should compiler know that? | |
88 | ||
89 | 112. Can convert float to unsigned int by subtracting a constant, | |
90 | converting to signed int, and changing the sign bit. | |
91 | ||
92 | 117. Any number of slow zero-extensions in one loop, that have | |
93 | their clr insns moved out of the loop, can share one register | |
94 | if their original life spans are disjoint. | |
95 | But it may be hard to be sure of this since | |
96 | the life span data that regscan produces may be hard to interpret | |
97 | validly or may be incorrect after cse. | |
98 | ||
99 | 118. In cse, when a bfext insn refers to a register, if the field | |
100 | corresponds to a halfword or a byte and the register is equivalent | |
101 | to a memory location, it would be possible to detect this and | |
102 | replace it with a simple memory reference. | |
103 | ||
104 | 121. Insns that store two values cannot be moved out of loops. | |
105 | The code in scan_loop doesn't even try to deal with them. | |
106 | ||
107 | 122. When insn-output.c turns a bit-test into a sign-test, | |
108 | it should see whether the cc is already set up with that sign. | |
109 | ||
110 | 123. When a conditional expression is used as a function arg, it would | |
111 | be faster (and in some cases shorter) to push each alternative rather | |
112 | than compute in a register and push that. This would require | |
113 | being able to specify "push this" as a target for expand_expr. | |
114 | ||
115 | 124. On the 386, bad code results from foo (bar ()) when bar | |
116 | returns a double, because the pseudo used fails to get preferenced | |
117 | into an fp reg because of the distinction between regs 8 and 9. |