RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion

RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion

Adds a pattern to map the output of noce_try_store_flag_mask
if-conversion in the combiner onto vt.maskc<n>; the input patterns
supported are similar to the following:
  (set (reg/v/f:DI 75 [ <retval> ])
       (and:DI (neg:DI (ne:DI (reg:DI 82)
                       (const_int 0 [0])))
               (reg/v/f:DI 75 [ <retval> ])))

This reduces dynamic instruction counts for the perlbench-workload in
SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the
each of the 3 workloads in the 'ref'-workload).

To ensure that the combine-pass doesn't get confused about
profitability, we recognize the idiom as requiring a single
instruction when the XVentanaCondOps extension is present.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for
	  vt.maskc<n> as a single insn with TARGET_XVENTANACONDOPS.
	* config/riscv/riscv.md: Include xventanacondops.md.
	* config/riscv/xventanacondops.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xventanacondops-ne-03.c: New test.
	* gcc.target/riscv/xventanacondops-ne-04.c: New test.

Commit-changes: 2
- Ran whitespace-cleanup on xventanacondops-ne-03.c
- Ran whitespace-cleanup on xventanacondops-ne-04.c