[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
	(RISCV_CORE): Ditto.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
	option.
	* config/riscv/riscv.cc: New def.
	* config/riscv/riscv.md: New include.
	* config/riscv/xiangshan.md: New file.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.

	Co-Authored by: Lin Jiawei <jiawei.lin@epfl.ch>