RISC-V: Handle undef for vector mask patterns

RISC-V: Handle undef for vector mask patterns

Add new instruction pattern for setting vector mask to undefine value,
also merge undef and non-undef ternary operation pattern like MAC operations to
single pattern.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (legitimize_move): Allow undef value
	as legitimate value.
	* config/riscv/riscv-vector-builtins.cc
	(function_expander::use_ternop_insn): Fix bugs of ternary intrinsic.
	(function_expander::use_widen_ternop_insn): Ditto.
	* config/riscv/vector.md (@vundefined<mode>): New pattern.
	(pred_mul_<optab><mode>_undef_merge): Remove.
	(*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
	(*pred_mul_<optab><mode>_undef_merge_extended_scalar): Ditto.
	(pred_neg_mul_<optab><mode>_undef_merge): Ditto.
	(*pred_neg_mul_<optab><mode>_undef_merge_scalar): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: Adapt the test.
	* gcc.target/riscv/rvv/base/binop_vv_constraint-6.c: Ditto.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-127.c: Ditto.
	* g++.target/riscv/rvv/base/bug-1.C: New test.
	* gcc.target/riscv/rvv/base/bug-2.c: New test.

Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>