[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition...

[PATCH v3] [RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0

This patch recognizes Zicond patterns when the select pattern
with condition eq or neq to 0 (using eq as an example), namely:

1 rd = (rs2 == 0) ? non-imm : 0
2 rd = (rs2 == 0) ? non-imm : non-imm
3 rd = (rs2 == 0) ? reg : non-imm
4 rd = (rs2 == 0) ? reg : reg

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_conditional_move): Recognize
	more Zicond patterns.  Fix whitespace typo.
	(riscv_rtx_costs): Remove accidental code duplication.

	Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
(cherry picked from commit 4e87c953d16377457b31b65b6c3268d932e462ab)