aarch64: Improve RTL representation of ADDP instructions

aarch64: Improve RTL representation of ADDP instructions

Similar to the ADDLP instructions the non-widening ADDP ones can be
represented by adding the odd lanes with the even lanes of a vector.
These instructions take two vector inputs and the architecture spec
describes the operation as concatenating them together before going
through it with pairwise additions.
This patch chooses to represent ADDP on 64-bit and 128-bit input
vectors slightly differently, reasons explained in the comments
in aarhc64-simd.md.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_addp<mode><vczle><vczbe>):
	Reimplement as...
	(aarch64_addp<mode>_insn): ... This...
	(aarch64_addp<mode><vczle><vczbe>_insn): ... And this.
	(aarch64_addp<mode>): New define_expand.