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RISC-V: Add indexed loads/stores constraints testcases
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Sun, 29 Jan 2023 15:37:21 +0000 (23:37 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 30 Jan 2023 16:42:22 +0000 (00:42 +0800)
commit9da40aae23180fc9d240b762e4fea154df546570
tree52643c80841ca6f39e1e870aea9e330c6a055eadtree
parent6dfacebd2d6458b0774c76b7b2afbcc22bc43e4ccommit | diff
RISC-V: Add indexed loads/stores constraints testcases

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test.
gcc/testsuite/gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c [new file with mode: 0644] blob
GNU Compiler Collection
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