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(parent: e8089af) | patch
RISC-V: Add csrr vlenb instruction.
authorzhongjuzhe <juzhe.zhong@rivai.ai>
Tue, 30 Aug 2022 06:20:27 +0000 (14:20 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Thu, 1 Sep 2022 02:01:20 +0000 (10:01 +0800)
commit8fe75147a948ceab6fb9afbe0ee698517ce1dda0
tree52c5648f685b98ff46dc376c098ca642bc6055b8tree
parente8089aff3602447cd66ea723802d43cec4e7ec02commit | diff
RISC-V: Add csrr vlenb instruction.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int.
(riscv_output_move): Add csrr vlenb assembly.
* config/riscv/riscv.md (move_type): Add csrr vlenb type.
(ext): New attribute.
(ext_enabled): Ditto.
(enabled): Ditto.
gcc/config/riscv/riscv.cc diff | blob | blame | history
gcc/config/riscv/riscv.md diff | blob | blame | history
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