RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc'

RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc'

A subsequent change to enable the processing of conditional moves on a
floating-point condition by `riscv_expand_conditional_move' will cause
`riscv_expand_float_scc' to be called for word-mode target RTX with RV64
targets.  In that case an invalid insn such as:

(insn 25 24 0 (set (reg:DI 141)
        (subreg:SI (reg:DI 143) 0)) -1
     (nil))

would be produced, which would crash the compiler later on.  Since the
output operand of the SET operation to be produced already has the same
mode as the input operand does, just omit the use of SUBREG and assign
directly.

	gcc/
	* config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
	use of SUBREG if the conditional-set target is word-mode.