RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

RISC-V: Fix matches against subreg with a bytenum of 0 in riscv.md

These all intend the least significant subpart of the register.
Use the same endian-neutral "subreg_lowpart_operator" predicate that
ARM does instead.

gcc/
	* config/riscv/predicates.md (subreg_lowpart_operator): New predicate
	* config/riscv/riscv.md (*addsi3_extended2, *subsi3_extended2)
	(*negsi2_extended2, *mulsi3_extended2, *<optab>si3_mask)
	(*<optab>si3_mask_1, *<optab>di3_mask, *<optab>di3_mask_1)
	(*<optab>si3_extend_mask, *<optab>si3_extend_mask_1): Use
	new predicate "subreg_lowpart_operator"