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(parent: 6c9bcb6) | patch
RISC-V: Add VSETVL testcases for indexed loads/stores.
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Sun, 29 Jan 2023 15:34:57 +0000 (23:34 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 30 Jan 2023 16:42:18 +0000 (00:42 +0800)
commit6dfacebd2d6458b0774c76b7b2afbcc22bc43e4c
tree10de9f9e22dff3ca04fc5355b0ace0f1fbb076e4tree
parent6c9bcb6c7ec70aba260a388469fd88f31fe08d15commit | diff
RISC-V: Add VSETVL testcases for indexed loads/stores.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-72.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-76.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-77.c [new file with mode: 0644] blob
GNU Compiler Collection
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