RISC-V: Implement vectorizable early exit with vcond_mask_len

RISC-V: Implement vectorizable early exit with vcond_mask_len

After we support the loop lens for the vectorizable,  we would like to
implement the feature for the RISC-V target.  Given below example:

unsigned vect_a[1923];
unsigned vect_b[1923];

void test (unsigned limit, int n)
{
  for (int i = 0; i < n; i++)
    {
      vect_b[i] = limit + i;

      if (vect_a[i] > limit)
        {
          ret = vect_b[i];
          return ret;
        }

      vect_a[i] = limit;
    }
}

Before this patch:
  ...
.L8:
  sw    a3,0(a5)
  addiw a0,a0,1
  addi  a4,a4,4
  addi  a5,a5,4
  beq   a1,a0,.L2
.L4:
  sw    a0,0(a4)
  lw    a2,0(a5)
  bleu  a2,a3,.L8
  ret

After this patch:
  ...
.L5:
  vsetvli   a5,a3,e8,mf4,ta,ma
  vmv1r.v   v4,v2
  vsetvli   t4,zero,e32,m1,ta,ma
  vmv.v.x   v1,a5
  vadd.vv   v2,v2,v1
  vsetvli   zero,a5,e32,m1,ta,ma
  vadd.vv   v5,v4,v3
  slli      a6,a5,2
  vle32.v   v1,0(t1)
  vmsltu.vv v1,v3,v1
  vcpop.m   t4,v1
  beq       t4,zero,.L4
  vmv.x.s   a4,v4
.L3:
  ...

The below tests are passed for this patch:
1. The riscv fully regression tests.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md(*vcond_mask_len_popcount_<VB_VLS:mode><P:mode>):
	New pattern of vcond_mask_len_popcount for vector bool mode.
	* config/riscv/autovec.md (vcond_mask_len_<mode>): New pattern of
	vcond_mask_len for vector bool mode.
	(cbranch<mode>4): New pattern for vector bool mode.
	* config/riscv/vector-iterators.md: Add new unspec UNSPEC_SELECT_MASK.
	* config/riscv/vector.md (@pred_popcount<VB:mode><P:mode>): Add VLS mode
	to popcount pattern.
	(@pred_popcount<VB_VLS:mode><P:mode>): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/early-break-1.c: New test.
	* gcc.target/riscv/rvv/autovec/early-break-2.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>