[to-be-committed,RISC-V] Improve single inverted bit extraction - v3

[to-be-committed,RISC-V] Improve single inverted bit extraction - v3

So this patch fixes a minor code generation inefficiency that (IIRC) the
RAU team discovered a while ago in spec.

If we want the inverted value of a single bit we can use bext to extract
the bit, then seq to invert the value (if viewed as a 0/1 truth value).

The RTL is fairly convoluted, but it's basically a right shift to get
the bit into position, bitwise-not then masking off all but the low bit.
So it's a 3->2 combine, hidden by the fact that and-not is a
define_insn_and_split, so it actually looks like a 2->2 combine.

We've run this through Ventana's internal CI (which includes
zba_zbb_zbs) and I've run it in my own tester (rv64gc, rv32gcv).  I'll
wait for the upstream CI to finish with positive results before pushing.

gcc/
	* config/riscv/bitmanip.md (bextseqzdisi): New patterns.

gcc/testsuite/

	* gcc.target/riscv/zbs-bext-2.c: New test.
	* gcc.target/riscv/zbs-bext.c: Fix one of the possible expectes sequences.