gcc.gnu.org Git - gcc.git/commit

author	Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
	Sun, 29 Jan 2023 23:06:32 +0000 (07:06 +0800)
committer	Kito Cheng <kito.cheng@sifive.com>
	Mon, 30 Jan 2023 16:46:15 +0000 (00:46 +0800)
commit	0451ce4444dc5c9f84dd323b228e707323399487
tree	3fa6f2c6cb5bb12e535e89938de10e1ee0da4e6c	tree
parent	6e13f699f84437d00f304858b08831dfbcf947f6	commit \| diff

RISC-V: Add vluxei32 C API intrinsic testcases

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vluxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c: New test.

gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v-3.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_m-3.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c	[new file with mode: 0644]	blob