Bug 96231 - Can't generate ORR instruction
Summary: Can't generate ORR instruction
Status: RESOLVED MOVED
Alias: None
Product: gcc
Classification: Unclassified
Component: translation (show other bugs)
Version: 11.0
: P3 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2020-07-17 12:25 UTC by Alexei Fedorov
Modified: 2020-07-17 12:27 UTC (History)
0 users

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Description Alexei Fedorov 2020-07-17 12:25:25 UTC
Hello.
I have a problem with ORR instruction in GCC 11.0.0
orr w28,w28,#0x800080
is compiled with 0x3209839C encoding:

EL2N:0x0000000088013CA8 : ORR      w28,w28,#0x800080

orr x28,x28,#0x800080
generates
Error: immediate out of range at operand 3 -- `orr x28,x28,#0x800080'
If I modify encoding 0x3209839C for W28 in debugger
by setting 'sf' bit 31, according to ARM ARM:
"64-bit variant
Applies when sf == 1.
ORR <Xd|SP>, <Xn>, #<imm>"

Disassembly shows 
EL2N:0x0000000088013CA8 : ORR      x28,x28,#0x80008000800080
but when I execute it with initial X28 = 0, the result is
X28	0x0000000000800080

which is correct. Any ideas what might be wrong here?
Comment 1 Andrew Pinski 2020-07-17 12:27:46 UTC
This is an issue with the assembler and not GCC.  Please report it to binutils (https://sourceware.org/bugzilla) instead.