Bug 92846 - [ARC] floating point compares not generating Invalid Operand
Summary: [ARC] floating point compares not generating Invalid Operand
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 9.2.1
: P3 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2019-12-06 17:21 UTC by Vineet Gupta
Modified: 2021-04-30 19:28 UTC (History)
0 users

See Also:
Host:
Target: arc
Build:
Known to work:
Known to fail:
Last reconfirmed:


Attachments
proposed fix (2.04 KB, application/mbox)
2019-12-06 17:35 UTC, Vineet Gupta
Details

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Description Vineet Gupta 2019-12-06 17:21:29 UTC
This is similar to issues reported for other targets
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=52451
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77918

The FDCMP instructions generated raised Invalid operand only for sNaN. This causes glibc testsuite failures test-{double,float,...}-iseqsig which test both qNaN and sNaN and expect either to pass.
Comment 1 Vineet Gupta 2019-12-06 17:24:45 UTC
Test case:

int f(double x, double y)
{
        return x > y;                      // expected FDCMPF (qNaN, sNaN)
}

int f2(double x, double y)
{
        return __builtin_isgreater(x, y);  // expected FDCMP (only sNan)
}
Comment 2 Vineet Gupta 2019-12-06 17:35:04 UTC
Created attachment 47438 [details]
proposed fix

Ran full glibc tessuite with this: No regressions
gcc dejagnu test pr52451.c passes too
Comment 3 claziss 2019-12-12 08:42:54 UTC
Author: claziss
Date: Thu Dec 12 08:42:21 2019
New Revision: 279274

URL: https://gcc.gnu.org/viewcvs?rev=279274&root=gcc&view=rev
Log:
[ARC] generate signaling FDCMPF for hard float comparisons

PR 92846:
ARC gcc generates FDCMP instructions which raises Invalid operation for
signaling NaN only. This causes glibc iseqsig() primitives to fail (in
the current ongoing glibc port to ARC)

So break up the hard float compares into tw categories and for unordered
compares generate the FDCMPF instructions which raised exception for
either NaNs.

With this fix testsuite/gcc.dg/torture/pr52451.c passes for ARC.

Also no regressions for the glibc math testsuite, only 6 additional
passes for test*iseqsig

gcc/
xxxx-xx-xx  Vineet Gupta  <vgupta@synopsys.com>

	* config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE which
	helps codegen generate exceptions even for quiet NaN.
	* config/arc/arc.c (arc_init_reg_tables): Handle New CC_FPUE mode.
	(get_arc_condition_code): Likewise.
	(arc_select_cc_mode): LT, LE, GT, GE to use the New CC_FPUE mode.
	* config/arc/arc.h (REVERSE_CONDITION): Handle New CC_FPUE mode.
	* config/arc/predicates.md (proper_comparison_operator): Likewise.
	* config/arc/fpu.md (cmpsf_fpu_trap): New Pattern for CC_FPUE.
	(cmpdf_fpu_trap): Likewise.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arc/arc-modes.def
    trunk/gcc/config/arc/arc.c
    trunk/gcc/config/arc/arc.h
    trunk/gcc/config/arc/fpu.md
    trunk/gcc/config/arc/predicates.md
Comment 4 Vineet Gupta 2021-04-30 19:28:50 UTC
Resolved via

2019-12-12 fbf8314b0a8d [ARC] generate signaling FDCMPF for hard float comparisons