Two of the spec 2006 benchmarks (gamess and calculix) get errors when compiled by recent trunk compilers with -mcpu=power9: Error in gamess: Error: insn does not satisfy its constraints: (insn 8520 8519 8521 96 (parallel [ (set (reg:SI 4 4 [4221]) (vec_select:SI (reg:V4SI 43 11 [orig:586 vect__86.1681 ] [586]) (parallel [ (const_int 1 [0x1]) ]))) (clobber (reg:SI 29 29 [4222])) ]) "loccd.fppized.f":379 1184 {vsx_extract_v4si_p9} (expr_list:REG_UNUSED (reg:SI 29 29 [4222]) (nil))) loccd.fppized.f:564:0: internal compiler error: in extract_constrain_insn, at recog.c:2213 Error in calculix: SPOOLES/MSMD/src/MSMD_init.c: In function 'MSMD_init': SPOOLES/MSMD/src/MSMD_init.c:161:1: error: insn does not satisfy its constraints: return ; } ^~~~~~ (insn 2674 2673 2675 37 (parallel [ (set (reg:SI 0 0 [985]) (vec_select:SI (reg:V4SI 32 0 [orig:378 vect__50.42 ] [378]) (parallel [ (const_int 1 [0x1]) ]))) (clobber (reg:SI 31 31 [986])) ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1184 {vsx_extract_v4si_p9} (expr_list:REG_UNUSED (reg:SI 31 31 [986]) (nil)))
A quick glance at the code, shows that the V4SImode register is a traditional floating point register, but the splitter for vsx_extract_<mode>_p9 requires the register to be a traditional altivec register. I suspect vsx_extract_v4si_p9 is called from vsx_extract_si. The later has a constraint (wJ) that allows the operand to go in traditional floating registers in addition to Altivec registers (v).
Created attachment 40449 [details] Proposed patch to fix the problem
Author: meissner Date: Wed Jan 4 04:32:48 2017 New Revision: 244044 URL: https://gcc.gnu.org/viewcvs?rev=244044&root=gcc&view=rev Log: [gcc] 2016-12-30 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78900 * config/rs6000/rs6000.c (rs6000_split_signbit): Change some assertions. Add support for doing the signbit if the IEEE 128-bit floating point value is in a GPR. * config/rs6000/rs6000.md (Fsignbit): Delete. (signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa". Update the length attribute if the value is in a GPR. (signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate the sign or zero extension instruction, since the value is always 0/1. (signbit<mode>2_dm2): Delete using <Fsignbit>. 2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78953 * config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are extracting SImode to a GPR register so that we can generate a store, limit the vector to be in a traditional Altivec register for the vextuwrx instruction. [gcc/testsuite] 2017-01-03 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/78953 * gcc.target/powerpc/pr78953.c: New test. Added: trunk/gcc/testsuite/gcc.target/powerpc/pr78953.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/rs6000.c trunk/gcc/config/rs6000/rs6000.md trunk/gcc/config/rs6000/vsx.md trunk/gcc/testsuite/ChangeLog
Fixed in subversion id 244044.