Bug 78900 - ICE in gcc.target/powerpc/signbit-3.c
Summary: ICE in gcc.target/powerpc/signbit-3.c
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 6.3.1
: P3 normal
Target Milestone: ---
Assignee: Michael Meissner
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2016-12-22 12:54 UTC by acsawdey
Modified: 2017-01-19 15:33 UTC (History)
1 user (show)

See Also:
Host:
Target: powerpc64*-*-*
Build:
Known to work:
Known to fail:
Last reconfirmed: 2016-12-30 00:00:00


Attachments
Proposed patch to fix the problem (1.48 KB, patch)
2016-12-30 20:57 UTC, Michael Meissner
Details | Diff

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Description acsawdey 2016-12-22 12:54:35 UTC
Regtesting for -mcpu=power9 turned this up. Version tested is gcc-6-branch revision 243723.

/home/sawdey/src/gcc/gcc-6-branch/build/gcc/xgcc -B/home/sawdey/src/gcc/gcc-6-branch/build/gcc/ /home/sawdey/src/gcc/gcc-6-branch/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/signbit-3.c   -fno-diagnostics-show-caret -fdiagnostics-color=never   -mcpu=power7 -O2 -mfloat128 -lm -Wl,-rpath=/tmp/lib64  -lm   -mcpu=power9  -o ./signbit-3.exe

/home/sawdey/src/gcc/gcc-6-branch/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/signbit-3.c: In function 'test_signbit_gpr.isra.1':
/home/sawdey/src/gcc/gcc-6-branch/gcc-6-branch/gcc/testsuite/gcc.target/powerpc/signbit-3.c:111:1: internal compiler error: in rs6000_split_signbit, at config/rs6000/rs6000.c:23106
0x109de9f3 rs6000_split_signbit(rtx_def*, rtx_def*)
        ../../gcc-6-branch/gcc/config/rs6000/rs6000.c:23106
0x10b535cb gen_split_119(rtx_insn*, rtx_def**)
        ../../gcc-6-branch/gcc/config/rs6000/rs6000.md:4626
0x10c6ceb3 split_12
        ../../gcc-6-branch/gcc/config/rs6000/rs6000.md:4625
0x10c71287 split_15
        ../../gcc-6-branch/gcc/config/rs6000/rs6000.md:330
0x10c71287 split_insns(rtx_def*, rtx_insn*)
        ../../gcc-6-branch/gcc/config/rs6000/rs6000.md:411
0x10391e87 try_split(rtx_def*, rtx_insn*, int)
        ../../gcc-6-branch/gcc/emit-rtl.c:3658
0x10631cbb split_insn
        ../../gcc-6-branch/gcc/recog.c:2865
0x10637d37 split_all_insns()
        ../../gcc-6-branch/gcc/recog.c:2955
0x10637dbb rest_of_handle_split_after_reload
        ../../gcc-6-branch/gcc/recog.c:3891
0x10637dbb execute
        ../../gcc-6-branch/gcc/recog.c:3920
Please submit a full bug report,
with preprocessed source if appropriate.
Comment 1 Michael Meissner 2016-12-30 20:57:26 UTC
Created attachment 40432 [details]
Proposed patch to fix the problem
Comment 2 Michael Meissner 2017-01-04 04:33:20 UTC
Author: meissner
Date: Wed Jan  4 04:32:48 2017
New Revision: 244044

URL: https://gcc.gnu.org/viewcvs?rev=244044&root=gcc&view=rev
Log:
[gcc]
2016-12-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78900
	* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
	assertions.  Add support for doing the signbit if the IEEE 128-bit
	floating point value is in a GPR.
	* config/rs6000/rs6000.md (Fsignbit): Delete.
	(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
	Update the length attribute if the value is in a GPR.
	(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
	the sign or zero extension instruction, since the value is always
	0/1.
	(signbit<mode>2_dm2): Delete using <Fsignbit>.

2017-01-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78953
	* config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are
	extracting SImode to a GPR register so that we can generate a
	store, limit the vector to be in a traditional Altivec register
	for the vextuwrx instruction.

[gcc/testsuite]
2017-01-03  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78953
	* gcc.target/powerpc/pr78953.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/powerpc/pr78953.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/rs6000/rs6000.c
    trunk/gcc/config/rs6000/rs6000.md
    trunk/gcc/config/rs6000/vsx.md
    trunk/gcc/testsuite/ChangeLog
Comment 3 Michael Meissner 2017-01-04 20:04:08 UTC
Fixed in trunk in subversion id 244044.  I will hold the bug open until it is checked into the GCC 6 branch.
Comment 4 Michael Meissner 2017-01-10 20:03:32 UTC
Author: meissner
Date: Tue Jan 10 20:03:00 2017
New Revision: 244285

URL: https://gcc.gnu.org/viewcvs?rev=244285&root=gcc&view=rev
Log:
2017-01-10  Michael Meissner  <meissner@linux.vnet.ibm.com>

	Backport from mainline
	2016-12-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/78900
	* config/rs6000/rs6000.c (rs6000_split_signbit): Change some
	assertions.  Add support for doing the signbit if the IEEE 128-bit
	floating point value is in a GPR.
	* config/rs6000/rs6000.md (Fsignbit): Delete.
	(signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa".
	Update the length attribute if the value is in a GPR.
	(signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate
	the sign or zero extension instruction, since the value is always
	0/1.
	(signbit<mode>2_dm2): Delete using <Fsignbit>.


Modified:
    branches/gcc-6-branch/gcc/ChangeLog
    branches/gcc-6-branch/gcc/config/rs6000/rs6000.c
    branches/gcc-6-branch/gcc/config/rs6000/rs6000.md
Comment 5 Bill Schmidt 2017-01-19 15:33:45 UTC
Work is complete.