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Bug 7380 - ICE in extract_insn, at recog.c:2148
Summary: ICE in extract_insn, at recog.c:2148
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 3.1.1
: P3 normal
Target Milestone: ---
Assignee: Alan Modra
URL:
Keywords: ice-on-valid-code
Depends on:
Blocks:
 
Reported: 2002-07-22 19:26 UTC by Alan Modra
Modified: 2003-07-25 17:33 UTC (History)
2 users (show)

See Also:
Host:
Target:
Build:
Known to work:
Known to fail:
Last reconfirmed:


Attachments
workspace.i.gz (48.60 KB, application/x-gzip )
2003-05-21 15:17 UTC, Alan Modra
Details

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Description Alan Modra 2002-07-22 19:26:00 UTC
	rs6000.md splitters generate patterns that don't match insns

Release:
3.1.1 20020720 (prerelease)

Environment:
configured with: /src/gcc-3.1/configure --prefix=/usr/local --build=i686-linux --host=i686-linux --target=powerpc-linux --disable-nls --enable-languages=c,c++

How-To-Repeat:
	-O2 -S on attached .i
Comment 1 Alan Modra 2002-07-22 19:26:00 UTC
Fix:
This patch goes a little further than just fixing the immediate problem
in the (plus:SI (gt:SI ..)) splitter.  There were a number of similar
splitters with missing scratch regs, and after fixing a few I decided
that a better fix was to remove the need for the scratch reg in the
insn.

	* config/rs6000/rs6000.md: Remove scratch reg on insns using
	addze and similar (plus (comparison r1 r2) r3) insns.  Add
	missing scratch reg in one case.  Formatting fixes.

diff -urp gcc-3.1/gcc/config/rs6000/rs6000.md gcc-3.1-am/gcc/config/rs6000/rs6000.md
--- gcc-3.1/gcc/config/rs6000/rs6000.md	2002-07-15 14:44:53.000000000 +0930
+++ gcc-3.1-am/gcc/config/rs6000/rs6000.md	2002-07-23 07:51:45.000000000 +0930
@@ -11256,12 +11256,11 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
   "TARGET_POWER"
   "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
+   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
+   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -11292,46 +11291,43 @@
   "TARGET_POWER && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (le:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+		 (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
+	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER"
   "@
-   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
-   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
+   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
+   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,12,16,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -11481,37 +11477,34 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
+   {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,12")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -11529,10 +11522,9 @@
 	(and:SI (neg:SI
 		 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		(match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+		(match_operand:SI 3 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
+  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -11562,16 +11554,15 @@
    (clobber (match_scratch:SI 4 ""))]
   "! TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 4)
-	(and:SI (neg:SI (leu:SI (match_dup 1)
-			  (match_dup 2)))
-		 (match_dup 3)))
+	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
+		(match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (and:SI (neg:SI
 		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -11579,17 +11570,16 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
+   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (and:SI (neg:SI
 		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -11597,13 +11587,12 @@
 		 (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
-	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+  [(set (match_dup 0)
+	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
+		(match_dup 3)))
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -11651,10 +11640,9 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
   "TARGET_POWER"
-  "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
+  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -11683,44 +11671,41 @@
   "TARGET_POWER && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (lt:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+		 (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER"
   "@
-   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
+   doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -11815,46 +11800,43 @@
   "! TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (ltu:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+		 (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
+	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
+   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
+   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,12,16,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -11905,8 +11887,8 @@
    (clobber (match_scratch:SI 3 ""))]
   "TARGET_POWER && reload_completed"
   [(parallel [(set (match_dup 0)
-	(ge:SI (match_dup 1) (match_dup 2)))
-   (clobber (match_dup 3))])
+		   (ge:SI (match_dup 1) (match_dup 2)))
+	      (clobber (match_dup 3))])
    (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
@@ -11916,10 +11898,9 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
   "TARGET_POWER"
-  "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
+  "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -11948,44 +11929,41 @@
   "TARGET_POWER && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (ge:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+		 (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER"
   "@
-   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
+   doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -12130,39 +12108,36 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
+	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
-   {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
+   {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
+   {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,8,12,12")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -12182,12 +12157,11 @@
 	(and:SI (neg:SI
 		 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		(match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+		(match_operand:SI 3 "gpc_reg_operand" "r,r")))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
+   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
+   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12219,16 +12193,15 @@
    (clobber (match_scratch:SI 4 ""))]
   "! TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 4)
-	(and:SI (neg:SI (geu:SI (match_dup 1)
-			  (match_dup 2)))
-		 (match_dup 3)))
+	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
+		(match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (and:SI (neg:SI
 		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
@@ -12236,19 +12209,18 @@
 		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
+	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
-   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
+   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
+   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,12,16,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (and:SI (neg:SI
 		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -12256,13 +12228,11 @@
 		 (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -12397,10 +12367,9 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
 			(const_int 0))
-		 (match_operand:DI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:DI 3 "=&r"))]
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
   "TARGET_POWERPC64"
-  "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
+  "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12461,80 +12430,74 @@
   "TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 3)
 	(plus:DI (gt:DI (match_dup 1) (const_int 0))
-		  (match_dup 2)))
+		 (match_dup 2)))
    (set (match_dup 0)
 	(compare:CC (match_dup 3)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (const_int 0))
 		  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
+	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
   "! TARGET_POWERPC64"
   "@
-   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
+   {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (const_int 0))
 		  (match_operand:SI 2 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_scratch:SI 3 ""))]
+	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_dup 3))])
-   (set (match_dup 4)
+   (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			 (const_int 0))
 		  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_scratch:DI 3 "=&r,&r"))]
+	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
   "TARGET_POWERPC64"
   "@
-   addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
+   addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			 (const_int 0))
 		  (match_operand:DI 2 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_scratch:DI 3 ""))]
+	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
   "TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
-   (clobber (match_dup 3))])
-   (set (match_dup 4)
+   (set (match_dup 3)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -12543,10 +12506,9 @@
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "r"))
-		 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))]
   "TARGET_POWER"
-  "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
+  "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12574,45 +12536,41 @@
    (clobber (match_scratch:SI 4 ""))]
   "TARGET_POWER && reload_completed"
   [(set (match_dup 4)
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER"
   "@
-   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
+   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			 (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWER && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
@@ -12734,12 +12692,11 @@
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
 	(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
-		 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
-   (clobber (match_scratch:DI 4 "=&r,&r"))]
+		 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
   "TARGET_POWERPC64"
   "@
-   addic %4,%1,%k2\;addze %0,%3
-   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
+   addic %0,%1,%k2\;addze %0,%3
+   subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
   [(set_attr "length" "8,12")])
 
 (define_insn ""
@@ -12770,7 +12727,7 @@
   "! TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 4)
 	(plus:SI (gtu:SI (match_dup 1) (match_dup 2))
-		  (match_dup 3)))
+		 (match_dup 3)))
    (set (match_dup 0)
 	(compare:CC (match_dup 4)
 		    (const_int 0)))]
@@ -12811,77 +12768,71 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
 		  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
+	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64"
   "@
-   {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
+   {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
+   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,12,12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_operand:SI 2 "reg_or_short_operand" ""))
 		  (match_operand:SI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:SI 4 ""))]
+	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "! TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
 	(compare:CC
 	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
 		  (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
+	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWERPC64"
   "@
-   addic %4,%1,%k2\;addze. %0,%3
-   subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
+   addic %0,%1,%k2\;addze. %0,%3
+   subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
    #
    #"
   [(set_attr "type" "compare")
    (set_attr "length" "8,12,12,16")])
 
 (define_split
-  [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
+  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
 	(compare:CC
 	 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
 			  (match_operand:DI 2 "reg_or_short_operand" ""))
 		  (match_operand:DI 3 "gpc_reg_operand" ""))
 	 (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_scratch:DI 4 ""))]
+	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "TARGET_POWERPC64 && reload_completed"
-  [(parallel [(set (match_dup 0)
+  [(set (match_dup 0)
 	(plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
-   (clobber (match_dup 4))])
-   (set (match_dup 5)
+   (set (match_dup 4)
 	(compare:CC (match_dup 0)
 		    (const_int 0)))]
   "")
Comment 2 Alan Modra 2002-07-23 02:51:18 UTC
From: Alan Modra <amodra@bigpond.net.au>
To: gcc-gnats@gcc.gnu.org
Cc: gcc-bugs@gcc.gnu.org
Subject: Re: target/7380: ICE in extract_insn, at recog.c:2148
Date: 23 Jul 2002 02:51:18 -0000

 Responsible-Changed-From-To: unassigned->amodra
 State-Changed-From-To: open->analyzed
 State-Changed-By: amodra
 State-Changed-When: Tue Jul 23 12:19:07 2002
 State-Changed-Why:
     Patch in PR.

 State-Changed-From-To: analyzed->closed
 State-Changed-By: amodra
 State-Changed-When: Fri Sep 13 16:52:12 2002
 State-Changed-Why:
     Fixed mainline and 3.2 branch.