On the PowerPC/e6500 elemental synchronization operations should be used for acquire/release barriers. Currently a lwsync is used instead:
powerpc-rtems4.12-gcc -O2 -Wall -Wextra -pedantic -mcpu=e6500 -m32 -S fence.c
.type release, @function
.size release, .-release
.type acquire, @function
.size acquire, .-acquire
.ident "GCC: (GNU) 6.0.0 20160202 (experimental)
See also e6500 Core Reference Manual, 220.127.116.11.1 (Simplified memory barrier recommendations) and EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors (06/2014), 18.104.22.168 (Forcing Load and Store Ordering (Memory Barriers)).
For acquire semantic a "ESYNC 12" instruction should be used (Load-Load- and Load-Store-Barriere) and for release semantic a "ESYNC 5" instruction (Store-Store- and Load-Store-Barrier). See also Memory Model Rationales, section "Why ordering constraints are never limited to loads or stores" (www.open-std.org/jtc1/sc22/wg21/docs/papers/2007/n2176.html).
The e6500 core honours in contrast to the general PowerPC architecture a Load-Store-Ordering (EREF, 22.214.171.124 (Architecture Ordering Requirements), number 4), so maybe for acquire semantic "ESYNC 8" instruction (Load-Load-Barrier) and for release semantic a "ESYNC 1" instruction is sufficient (Store-Store-Barrier). See EREF, 126.96.36.199 (Architectural Memory Access Ordering), 188.8.131.52.1 (Acquire Lock and Import Shared Memory) and 184.108.40.206.1 (Export Shared Memory and Release Lock).