Bug 61983 - 64 bit floating point instructions created for 32 bit FPU on MIPS r5900
Summary: 64 bit floating point instructions created for 32 bit FPU on MIPS r5900
Status: UNCONFIRMED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 4.9.0
: P3 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2014-07-31 20:54 UTC by Jürgen Urban
Modified: 2015-08-20 11:40 UTC (History)
0 users

See Also:
Host:
Target:
Build:
Known to work:
Known to fail:
Last reconfirmed:


Attachments
Test code (109 bytes, text/x-csrc)
2014-07-31 20:54 UTC, Jürgen Urban
Details

Note You need to log in before you can comment on or make changes to this bug.
Description Jürgen Urban 2014-07-31 20:54:02 UTC
Created attachment 33221 [details]
Test code

When compiling the attached test code, the following errors occur:

mips64r5900el-linux-gnu-gcc -mhard-float -msingle-float -march=r5900 -mabi=n32 -c -o test.o float64test.c
/tmp/ccFuqKvD.s: Assembler messages:
/tmp/ccFuqKvD.s:28: Error: opcode not supported on this processor: r5900 (mips3) `dmtc1 $4,$f0'
/tmp/ccFuqKvD.s:29: Error: opcode not supported on this processor: r5900 (mips3) `dmtc1 $2,$f2'
/tmp/ccFuqKvD.s:66: Error: opcode not supported on this processor: r5900 (mips3) `dmfc1 $2,$f0'
/tmp/ccFuqKvD.s:67: Error: opcode not supported on this processor: r5900 (mips3) `dmfc1 $4,$f2'
/tmp/ccFuqKvD.s:72: Error: opcode not supported on this processor: r5900 (mips3) `dmtc1 $4,$f0'
/tmp/ccFuqKvD.s:73: Error: opcode not supported on this processor: r5900 (mips3) `dmtc1 $2,$f2'

The MIPS r5900 supports 64 bit instructions, but doesn't have a 64 bit FPU. It just has a 32 bit FPU. The compiler should not create dmtc1 or dmfc1.

The instructions as created in function mips_output_move() file gcc-4.9.0/gcc/config/mips/mips.c line 4583/4538:
return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";