Bug 57150 - GCC when targeting power7 spills long double using VSX instructions.
GCC when targeting power7 spills long double using VSX instructions.
Status: RESOLVED FIXED
Product: gcc
Classification: Unclassified
Component: target
4.9.0
: P3 normal
: ---
Assigned To: Michael Meissner
:
Depends on:
Blocks:
  Show dependency treegraph
 
Reported: 2013-05-02 19:36 UTC by Michael Meissner
Modified: 2013-05-07 16:26 UTC (History)
3 users (show)

See Also:
Host: powerp64-gnu-linux
Target: powerpc64-gnu-linux
Build: powerpc64-gnu-linux
Known to work:
Known to fail: 4.5.0
Last reconfirmed: 2013-05-02 00:00:00


Attachments
Cut down example to show the problem, using -mcpu=power7 -m64 (186 bytes, text/x-csrc)
2013-05-02 19:36 UTC, Michael Meissner
Details
Assembler file (986 bytes, text/plain)
2013-05-02 19:37 UTC, Michael Meissner
Details
Patch to use scalar modes for TF/TD caller saves. (2.64 KB, patch)
2013-05-03 19:18 UTC, Michael Meissner
Details | Diff

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Description Michael Meissner 2013-05-02 19:36:51 UTC
Created attachment 30008 [details]
Cut down example to show the problem, using -mcpu=power7 -m64

In the glibc file e_scalbl.c, the compiler is using VSX stxvd2x and lxvd2x instructions to spill long double, even though only 1/2 of the register is used.  The compiler should use scalar load/store instructions.
Comment 1 Michael Meissner 2013-05-02 19:37:21 UTC
Created attachment 30009 [details]
Assembler file
Comment 2 Michael Meissner 2013-05-02 19:42:51 UTC
This goes back to the original VSX submission for GCC 4.5.

While the code is slow, it does appear to be correct.
Comment 3 Michael Meissner 2013-05-02 21:03:08 UTC
It shows up due to -fcaller-saves, which creates a V2DF save area.
Comment 4 Michael Meissner 2013-05-03 19:18:21 UTC
Created attachment 30028 [details]
Patch to use scalar modes for TF/TD caller saves.
Comment 5 Michael Meissner 2013-05-07 16:26:02 UTC
Fixed in subversion id 198593.