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Bug 52294 - [4.7 Regression] [ARM Thumb] generated asm code produces "branch out of range" error in gas with -Os -mcpu=cortex-a9
Summary: [4.7 Regression] [ARM Thumb] generated asm code produces "branch out of range...
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 4.7.0
: P3 normal
Target Milestone: 4.5.4
Assignee: Richard Earnshaw
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2012-02-17 09:57 UTC by bero
Modified: 2012-06-08 08:57 UTC (History)
3 users (show)

See Also:
Host:
Target: arm
Build:
Known to work:
Known to fail:
Last reconfirmed: 2012-02-17 00:00:00


Attachments
Preprocessed source triggering this issue (4.09 KB, application/octet-stream)
2012-02-17 09:57 UTC, bero
Details

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Description bero 2012-02-17 09:57:34 UTC
Created attachment 26693 [details]
Preprocessed source triggering this issue

[bero@localhost ~]$ /opt/android-toolchain-4.7/bin/arm-linux-androideabi-g++ -mcpu=cortex-a9 -mthumb -Os -o agc2_amr_wb.o -c agc2_amr_wb.i 
/tmp/ccBg0Qr8.s: Assembler messages:
/tmp/ccBg0Qr8.s:110: Error: branch out of range

The problem disappears when taking out -mcpu=cortex-a9 or replacing -Os with any other optimization level.

Reproducable with arm-linux-androideabi, arm-eabi and arm-linux-gnueabi compilers.
Comment 1 Mikael Pettersson 2012-02-17 10:46:11 UTC
Fails with gcc 4.7 but works with 4.6, 4.5, and 4.4.
Comment 2 Richard Earnshaw 2012-02-17 23:22:41 UTC
Confirmed.
lsls Rd, Rn, Rm
is only 2 bytes in size if Rd == Rn

Although the testcase only fails on trunk, the miscalculation is certain to be present on all maintained branches.
Comment 3 Steven Bosscher 2012-02-18 12:27:50 UTC
Richard, I suppose you mean the problem is in this define_insn:

(define_insn "*thumb1_ashlsi3"
  [(set (match_operand:SI            0 "register_operand" "=l,l")
        (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
                   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
  "TARGET_THUMB1"
  "lsl\\t%0, %1, %2"
  [(set_attr "length" "2")
   (set_attr "conds" "set")])

which should set "length" depending on the operands?

(BTW when should ARM_LSL_NAME be used instead of "lsl"? Or is ARM_LSL_NAME not relevant for Thumb?)
Comment 4 Steven Bosscher 2012-02-18 12:36:29 UTC
(If the pattern of comment #3 is to blame, then this goes back all the way to the check-in of that pattern, see http://gcc.gnu.org/viewcvs?view=revision&revision=33028)
Comment 5 Steven Bosscher 2012-02-18 12:46:00 UTC
(In reply to comment #4)
> (If the pattern of comment #3 is to blame, then this ...

...probably fix it.

Index: arm.md
===================================================================
--- arm.md	(revision 184318)
+++ arm.md	(working copy)
@@ -3505,7 +3505,12 @@
 		   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
   "TARGET_THUMB1"
   "lsl\\t%0, %1, %2"
-  [(set_attr "length" "2")
+  [(set (attr "length")
+       (if_then_else
+	 (eq (symbol_ref ("which_alternative"))
+			 (const_int 0))
+	 (const_int 4)
+	 (const_int 2)))
    (set_attr "conds" "set")])
 
 (define_expand "ashrdi3"


And otherwise: sorry for all the noise :-)
Comment 6 Steven Bosscher 2012-02-18 12:47:20 UTC
Or better:
Index: arm.md
===================================================================
--- arm.md	(revision 184318)
+++ arm.md	(working copy)
@@ -3505,7 +3505,7 @@
 		   (match_operand:SI 2 "nonmemory_operand" "N,l")))]
   "TARGET_THUMB1"
   "lsl\\t%0, %1, %2"
-  [(set_attr "length" "2")
+  [(set_attr "length" "4,2")
    (set_attr "conds" "set")])
 
 (define_expand "ashrdi3"
Comment 7 Richard Earnshaw 2012-02-18 15:25:01 UTC
(In reply to comment #3)
> Richard, I suppose you mean the problem is in this define_insn:
> 
> (define_insn "*thumb1_ashlsi3"
>   [(set (match_operand:SI            0 "register_operand" "=l,l")
>         (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
>                    (match_operand:SI 2 "nonmemory_operand" "N,l")))]
>   "TARGET_THUMB1"
>   "lsl\\t%0, %1, %2"
>   [(set_attr "length" "2")
>    (set_attr "conds" "set")])

No, that pattern is only for Thumb1, it never applies to Thumb2.

I'm currently testing a fix
Comment 8 Richard Earnshaw 2012-02-21 15:38:40 UTC
Author: rearnsha
Date: Tue Feb 21 15:38:35 2012
New Revision: 184442

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184442
Log:
	PR target/52294
	* thumb2.md (thumb2_shiftsi3_short): Split register and 	
	immediate shifts.  For register shifts tie operands 0 and 1.
	(peephole2 for above): Check that register-controlled shifts
	have suitably tied operands.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arm/thumb2.md
Comment 9 Richard Earnshaw 2012-02-21 23:46:10 UTC
Author: rearnsha
Date: Tue Feb 21 23:46:05 2012
New Revision: 184452

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184452
Log:
	PR target/52294
	* thumb2.md (thumb2_shiftsi3_short): Split register and
	immediate shifts.  For register shifts tie operands 0 and 1.
	(peephole2 for above): Check that register-controlled shifts
	have suitably tied operands.

Modified:
    branches/gcc-4_6-branch/gcc/ChangeLog
    branches/gcc-4_6-branch/gcc/config/arm/thumb2.md
Comment 10 Richard Earnshaw 2012-02-21 23:51:21 UTC
Author: rearnsha
Date: Tue Feb 21 23:51:16 2012
New Revision: 184454

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=184454
Log:
	PR target/52294
	* thumb2.md (thumb2_shiftsi3_short): Split register and
	immediate shifts.  For register shifts tie operands 0 and 1.
	(peephole2 for above): Check that register-controlled shifts
	have suitably tied operands.

Modified:
    branches/gcc-4_5-branch/gcc/ChangeLog
    branches/gcc-4_5-branch/gcc/config/arm/thumb2.md
Comment 11 Richard Earnshaw 2012-02-22 00:11:27 UTC
Fixed in 4.5, 4.6 and trunk
Comment 12 jye2 2012-06-08 08:57:59 UTC
Author: jye2
Date: Fri Jun  8 08:57:53 2012
New Revision: 188332

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=188332
Log:
2012-06-08  Joey Ye  <joey.ye@arm.com>

	Backport r184442 from mainline
	2012-02-21  Richard Earnshaw  <rearnsha@arm.com>

	PR target/52294
	* thumb2.md (thumb2_shiftsi3_short): Split register and         
	immediate shifts.  For register shifts tie operands 0 and 1.
	(peephole2 for above): Check that register-controlled shifts
	have suitably tied operands.

	Backport r183756 from mainline
	2012-01-31  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

	* config/arm/thumb2.md (thumb2_mov_notscc): Use MVN for true
	condition.

	Backport r183349 from mainline
	2012-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/51915
	* config/arm/arm.c (arm_count_output_move_double_insns): Call
	output_move_double on a copy of operands array.

	Backport r183095 from mainline
	2012-01-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

	* config/arm/arm.md (mov_notscc): Use MVN for false condition.

	Backport r182628 from mainline
	2011-12-21  Richard Earnshaw  <rearnsha@arm.com>

	PR target/51643
	* arm.c (arm_function_ok_for_sibcall): Use DECL_WEAK in previous
	change.

	Backport r182621 from mainline
	2011-12-21  Richard Earnshaw  <rearnsha@arm.com>

	PR target/51643
	* arm.c (arm_function_ok_for_sibcall): Don't try to tailcall a
	weak function on bare-metal EABI targets.

Testsuite:
	Backport r183349 from mainline
	2012-01-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/51915
	* gcc.target/arm/pr51915.c: New test.

	Backport r183095 from mainline
	2012-01-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

	* gcc.c-torture/execute/20120110-1.c: New testcase.

	Backport r182621 from mainline
	2011-12-21  Richard Earnshaw  <rearnsha@arm.com>

	PR target/51643
	* gcc.target/arm/sibcall-2.c: New test.


Added:
    branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.c-torture/execute/20120111-1.c
    branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.target/arm/pr51915.c
    branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.target/arm/sibcall-2.c
Modified:
    branches/ARM/embedded-4_6-branch/gcc/ChangeLog.arm
    branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.c
    branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.md
    branches/ARM/embedded-4_6-branch/gcc/config/arm/thumb2.md
    branches/ARM/embedded-4_6-branch/gcc/testsuite/ChangeLog.arm