Created attachment 24689 [details] Sample code. The attached source code generates the following assembler code: 00000000 <_Watchdog_Handler_initialization>: 0: 2200 movs r2, #0 2: 4b06 ldr r3, [pc, #24] ; (1c <_Watchdog_Handler_initialization+0x1c>) 4: 601a str r2, [r3, #0] 6: 4b06 ldr r3, [pc, #24] ; (20 <_Watchdog_Handler_initialization+0x20>) 8: 601a str r2, [r3, #0] a: 4b06 ldr r3, [pc, #24] ; (24 <_Watchdog_Handler_initialization+0x24>) c: 601a str r2, [r3, #0] e: 4b06 ldr r3, [pc, #24] ; (28 <_Watchdog_Handler_initialization+0x28>) 10: 1d19 adds r1, r3, #4 12: c30e stmia r3!, {r1, r2, r3} 14: 4b05 ldr r3, [pc, #20] ; (2c <_Watchdog_Handler_initialization+0x2c>) 16: 1d19 adds r1, r3, #4 18: c30e stmia r3!, {r1, r2, r3} 1a: 4770 bx lr In particular it generates: stmia r3!, {r1, r2, r3} This instruction leads to UNPREDICTABLE behavior. According to "ARM Architecture Reference Manual, Issue I" we have in section "A7.1.57 STMIA", "Operand restrictions": "If <Rn> is specified in <registers>: o If <Rn> is the lowest-numbered register specified in <registers>, the original value of <Rn> is stored. o Otherwise, the stored value of <Rn> is UNPREDICTABLE." Since r3 is not the lowest-numbered register specified in {r1, r2, r3} the stored value of r3 is UNPREDICTABLE.
The command line is: arm-rtemseabi4.11-gcc -mcpu=arm7tdmi-s -mfpu=vfp -mfloat-abi=soft -mthumb -O2 -c watchdog.i We also get an assembler warning: watchdog.s: Assembler messages: watchdog.s:29: Warning: value stored for r3 is UNKNOWN watchdog.s:32: Warning: value stored for r3 is UNKNOWN Is the ARM7TDMI-S core still supported by GCC or is it too old?
This is the regression caused by the new ldm/stm optimizers that were added for 4.6
http://gcc.gnu.org/ml/gcc-patches/2011-07/msg01044.html http://gcc.gnu.org/ml/gcc-patches/2011-07/msg02174.html
The patch from Bernd Schmidt fixes the problem in my case. What is the status of this patch?
It would be nice if this can be fixed for 4.6.2 and 4.7.0.
GCC 4.6.2 is being released.
Author: rearnsha Date: Wed Nov 16 17:02:44 2011 New Revision: 181416 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=181416 Log: 2011-11-16 Richard Earnshaw <rearnsha@arm.com> Bernd Schmidt <bernds@coudesourcery.com> Sebastian Huber <sebastian.huber@embedded-brains.de> PR target/49641 * config/arm/arm.c (store_multiple_sequence): Avoid cases where the base reg is stored iff compiling for Thumb1. * gcc.target/arm/pr49641.c: New test. Added: trunk/gcc/testsuite/gcc.target/arm/pr49641.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.c trunk/gcc/testsuite/ChangeLog
Author: rearnsha Date: Wed Nov 16 17:53:28 2011 New Revision: 181418 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=181418 Log: 2011-11-16 Richard Earnshaw <rearnsha@arm.com> Bernd Schmidt <bernds@coudesourcery.com> Sebastian Huber <sebastian.huber@embedded-brains.de> PR target/49641 * config/arm/arm.c (store_multiple_sequence): Avoid cases where the base reg is stored iff compiling for Thumb1. * gcc.target/arm/pr49641.c: New test. Added: branches/gcc-4_6-branch/gcc/testsuite/gcc.target/arm/pr49641.c Modified: branches/gcc-4_6-branch/gcc/ChangeLog branches/gcc-4_6-branch/gcc/config/arm/arm.c branches/gcc-4_6-branch/gcc/testsuite/ChangeLog
Fixed.
Author: jye2 Date: Fri Jun 8 06:58:25 2012 New Revision: 188327 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=188327 Log: Backport mainline r179607, r179979, r179980, r181416, r182014 2012-06-08 Joey Ye <joey.ye@arm.com> Backport r182014 from mainline. 2011-12-05 Kazu Hirata <kazu@codesourcery.com> PR target/51408 * config/arm/arm.md (*minmax_arithsi): Always require the else clause in the MINUS case. Backport r181416 from mainline. 2011-11-16 Richard Earnshaw <rearnsha@arm.com> Bernd Schmidt <bernds@coudesourcery.com> Sebastian Huber <sebastian.huber@embedded-brains.de> PR target/49641 * config/arm/arm.c (store_multiple_sequence): Avoid cases where the base reg is stored iff compiling for Thumb1. Backport r179980 from mainline. 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> PR target/48126 * config/arm/arm.c (arm_output_sync_loop): Move label before barrier. Backport r179979 from mainline. 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org> * config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1. Backport r179607 from mainline. 2011-10-06 Bernd Schmidt <bernds@codesourcery.com> PR target/49049 * config/arm/arm.md (arm_subsi3_insn): Lose the last alternative. Testsuites: Backport r182014 from mainline 2011-12-05 Kazu Hirata <kazu@codesourcery.com> PR target/51408 * gcc.dg/pr51408.c: New. Backport r181416 from mainline 2011-11-16 Richard Earnshaw <rearnsha@arm.com> Bernd Schmidt <bernds@coudesourcery.com> Sebastian Huber <sebastian.huber@embedded-brains.de> PR target/49641 * gcc.target/arm/pr49641.c: New test. Backport r179607 from mainline 2011-10-06 Bernd Schmidt <bernds@codesourcery.com> PR target/49049 * gcc.c-torture/compile/pr49049.c: New test. Added: branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.c-torture/compile/pr49049.c branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.dg/pr51408.c branches/ARM/embedded-4_6-branch/gcc/testsuite/gcc.target/arm/pr49641.c Modified: branches/ARM/embedded-4_6-branch/gcc/ChangeLog.arm branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.c branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.h branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.md branches/ARM/embedded-4_6-branch/gcc/testsuite/ChangeLog.arm