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Bug 34932 - [avr] ICE in reload
Summary: [avr] ICE in reload
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 4.2.2
: P3 normal
Target Milestone: 4.3.2
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2008-01-23 02:11 UTC by Eric Weddington
Modified: 2008-08-22 01:19 UTC (History)
1 user (show)

See Also:
Host: mingw
Target: avr-*-*
Build:
Known to work:
Known to fail:
Last reconfirmed: 2008-04-04 22:31:36


Attachments
Reduced test case, (239 bytes, text/plain)
2008-01-23 02:13 UTC, Eric Weddington
Details
FIX for ICE (306 bytes, patch)
2008-03-21 22:52 UTC, Andy Hutchinson
Details | Diff

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Description Eric Weddington 2008-01-23 02:11:44 UTC
From WinAVR bug #1860717
http://sourceforge.net/tracker/index.php?func=detail&aid=1860717&group_id=68108&atid=520074

dimmer_profile.c: In function 'DIM_action':
dimmer_profile.c:26: error: could not find a spill register
(insn 30 29 31 3 (set (reg:HI 24 r24 [53])
        (plus:HI (zero_extend:HI (reg:QI 21 r21 [orig:41 D.1483 ] [41]))
            (zero_extend:HI (reg:QI 22 r22 [orig:42 D.1481 ] [42])))) 22 {*addhi3_zero_extend2} (insn_list:REG_DEP_TRUE 25 (insn_list:REG_DEP_TRUE 26 (nil)))
    (nil))
dimmer_profile.c:26: internal compiler error: in failed_reload, at reload1.c:5178
Comment 1 Eric Weddington 2008-01-23 02:13:14 UTC
Created attachment 14999 [details]
Reduced test case,
Comment 2 Eric Weddington 2008-01-23 02:19:27 UTC
Command line to test:

avr-gcc -c -mmcu=atmega32 -DF_CPU=14745600UL -O2 dimmer_profile.c -o dimmer_profile.o

Fails with -O[23]. Successful with -O[01s].
Comment 3 Andy Hutchinson 2008-01-23 02:50:14 UTC
The pattern requires operand 1 to be same register as operand 0

Operands 1 & 2 share 2 subregs of same Himode register R22

But should have been solvable without any problem, since HI24 is just right!

QI:21 -> QI:24

HI24 = Zex:QI24 + ZexQI22 voila!

QI22 could have been in top half of HI24. So this also works

HI:22 - > HI:22

HI:24 = Zex:QI24 + ZexQI24
Comment 4 Andy Hutchinson 2008-03-21 22:52:27 UTC
Created attachment 15357 [details]
FIX for ICE

This patches disables instruction pattern that causes ICE. This pattern is used for the case of addition where both operands are zero_extended. 

Since zero extension of this type must still  load a zero into one register anyway, there appears to be no benefit from this pattern over separate patterns for addhi3_zero_extend1 and zero_extend.

So rather than trying to get reload to figure it out, the problem instruction can be removed.
Comment 5 Andy Hutchinson 2008-05-26 17:19:57 UTC
Subject: Bug 34932

Author: hutchinsonandy
Date: Mon May 26 17:19:09 2008
New Revision: 135952

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=135952
Log:
PR target/34932
* config/avr/avr.md (*addhi3_zero_extend2): Remove.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/avr/avr.md

Comment 6 Eric Weddington 2008-06-02 19:02:23 UTC
Fixed in 4.4.0.
Comment 7 Andy Hutchinson 2008-06-07 15:49:07 UTC
Subject: Bug 34932

Author: hutchinsonandy
Date: Sat Jun  7 15:48:25 2008
New Revision: 136531

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=136531
Log:
Backports from 4.4
PR target/27386
* config/avr/avr.h: (PUSH_ROUNDING): Remove.
	
PR target/30243
* builtins.c (expand_builtin_signbit): Don't take lowpart when
register is already smaller or equal to required mode. 	

PR target/34932
* config/avr/avr.md (*addhi3_zero_extend2): Remove.
	
* config/avr/avr.h (MAX_OFILE_ALIGNMENT): Define.

Modified:
    branches/gcc-4_3-branch/gcc/ChangeLog
    branches/gcc-4_3-branch/gcc/builtins.c
    branches/gcc-4_3-branch/gcc/config/avr/avr.h
    branches/gcc-4_3-branch/gcc/config/avr/avr.md