Bug 33028 - Missed optimizations in peephole2 pass
Summary: Missed optimizations in peephole2 pass
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: rtl-optimization (show other bugs)
Version: 4.3.0
: P3 major
Target Milestone: 4.3.0
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2007-08-08 21:57 UTC by aesok
Modified: 2007-10-04 21:22 UTC (History)
3 users (show)

See Also:
Host:
Target: avr
Build:
Known to work:
Known to fail:
Last reconfirmed: 2007-08-28 23:30:12


Attachments
Patch. (301 bytes, patch)
2007-08-25 10:02 UTC, aesok
Details | Diff

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Description aesok 2007-08-08 21:57:50 UTC
Hi,

AVR backend have peephole2 for optimizing two register move instructions (mov) in one register pair move instruction (movw):

(define_peephole2 ; movw
  [(set (match_operand:QI 0 "even_register_operand" "")
        (match_operand:QI 1 "even_register_operand" ""))
   (set (match_operand:QI 2 "odd_register_operand" "")
        (match_operand:QI 3 "odd_register_operand" ""))]
  "(AVR_HAVE_MOVW
    && REGNO (operands[0]) == REGNO (operands[2]) - 1
    && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
  [(set (match_dup 4) (match_dup 5))]
  {
    operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
    operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
  })

Testcase:

unsigned char ADCH;
unsigned char ADCL;

unsigned int foo(void) {
  
  unsigned int temp = 0;  

  temp = ((ADCH<<8)|ADCL); 

  return temp;
}

# avr-gcc -Os  -mmcu=atmega16  -save-temps  -dP  -c -o demo.o demo.c

Compiled in:

.LM3:
 ; (insn 32 10 33 demo.c:34 (set (reg:QI 24 r24 [ <result> ])
 ;         (reg:QI 18 r18 [42])) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 18 r18 [42])
 ;         (nil)))
	mov r24,r18	 ;  32	*movqi/1	[length = 1]
 ; (insn 33 32 21 demo.c:34 (set (reg:QI 25 r25 [+1 ])
 ;         (reg:QI 19 r19 [+1 ])) 4 {*movqi} (expr_list:REG_DEAD (reg:QI 19 r19 [+1 ])
 ;         (nil)))
	mov r25,r19	 ;  33	*movqi/1	[length = 1]
/* epilogue start */
 ; (jump_insn/f 40 39 41 demo.c:34 (return) 128 {return} (nil))
	ret	 ;  40	return	[length = 1]

insns 32 ana 33 full match peephole, but do not optimize. If in avr.md file add new peephole2 with three insn patterns (now avr backend use peephole2 with max two insn patterns):


(define_peephole2 
  [(set (match_operand:QI 0 "register_operand" "")
        (match_dup 0))
   (set (match_dup 0)
        (match_dup 0))
   (set (match_dup 0)
        (match_dup 0))]
  ""
  [(set (match_dup 0) (match_dup 0))]
  {})

then two 'mov' instruction is optimized in 'movw':

.LM3:
 ; (insn 42 10 21 demo.c:34 (set (reg:HI 24 r24)
 ;         (reg:HI 18 r18)) 8 {*movhi} (nil))
	movw r24,r18	 ;  42	*movhi/1	[length = 1]
/* epilogue start */
 ; (jump_insn/f 40 39 41 demo.c:34 (return) 128 {return} (nil))
	ret	 ;  40	return	[length = 1]
.LFE2:


This behaviour is caused by the patch:
[patch RFA] Keep the correct peep2_current_count:
http://gcc.gnu.org/ml/gcc-patches/2005-10/msg01368.html


Anatoly.
Comment 1 aesok 2007-08-25 10:02:43 UTC
Created attachment 14112 [details]
Patch.
Comment 2 Eric Weddington 2007-08-28 23:30:12 UTC
Confirmed bug, and verified patch fixes bug.
Comment 3 Eric Weddington 2007-08-28 23:31:18 UTC
(In reply to comment #2)
> Confirmed bug, and verified patch fixes bug.
> 
... For the AVR port only.
Comment 4 aesok 2007-10-04 21:21:09 UTC
Patch <http://gcc.gnu.org/ml/gcc-patches/2007-10/msg00270.html> fix this bug.
Comment 5 aesok 2007-10-04 21:22:39 UTC
Fixed in trunk.