I found GCC can't optimize typedef unsigned long long u64; u64 mobility(u64 * a, u64 * b) { u64 mobility = 0; mobility += a[0]; mobility += a[1]; mobility += a[2]; mobility += a[3]; mobility -= b[0]; mobility -= b[1]; mobility -= b[2]; mobility -= b[3]; return mobility; } but llvm can https://godbolt.org/z/srWxxKhM9. The failure reason is "missed: not vectorized: no grouped stores in basic block." Any chance of gcc implementing vectorization like llvm?
Confirmed.
We are correctly detecting the reduction chain in vect_slp_check_for_roots but currently reject mixed operation chains there: if (chain[i].code != code) { invalid = true; break; } (gdb) p chain.length () $1 = 8 (gdb) p chain $2 = {<vec<chain_op_t, va_heap, vl_ptr>> = {m_vec = 0x4d957a0 = {{ code = PLUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff6e1c000 4>}, {code = PLUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff700df30 3>}, { code = PLUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff700de10 1>}, {code = PLUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff700dea0 2>}, { code = MINUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff6e1c1f8 8>}, {code = MINUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff6e1c168 7>}, { code = MINUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff6e1c0d8 6>}, {code = MINUS_EXPR, dt = vect_internal_def, op = <ssa_name 0x7ffff6e1c048 5>}}}, <No data fields>} mixed operation handling is missing in vectorize_slp_instance_root_stmt and it misses meta-data to indicate which lanes to negate.