Bug 100265 - [RISCV] Use proper fences for atomic load/store
Summary: [RISCV] Use proper fences for atomic load/store
Status: RESOLVED FIXED
Alias: None
Product: gcc
Classification: Unclassified
Component: target (show other bugs)
Version: 12.0
: P3 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords:
Depends on:
Blocks:
 
Reported: 2021-04-26 12:06 UTC by Christoph Müllner
Modified: 2023-10-24 08:37 UTC (History)
1 user (show)

See Also:
Host:
Target: riscv
Build:
Known to work:
Known to fail:
Last reconfirmed:


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Description Christoph Müllner 2021-04-26 12:06:41 UTC
On RISC-V we don't have load/store instructions with memory ordering bits.
To enforce memory ordering we need to use FENCE instructions.
The good thing is, we can have support for sub-word load/store.

The particular FENCE arguments (i.e. how to map the C ordering to RISC-V ordering is documented in the RISC-V unpriv spec in section "Code Porting and Mapping Guidelines").

Currenlty, GCC generates the following:

load_u32_n:
  lw a0,0(a0)
  sext.w a0,a0
  ret

load_u32_aq_n:
  lw a0,0(a0)
  fence iorw,iorw
  sext.w a0,a0
  ret

store_u32_n:
  amoswap.w zero,a1,0(a0)
  ret

store_u32_rl_n:
  fence iorw,ow
  amoswap.w zero,a1,0(a0)
  ret

The goal would be to generate this as follows:

load_u32_n:
  lw a0,0(a0)
  ret

load_u32_aq_n:
  lw a0,0(a0)
  fence r,rw
  ret

store_au32_n:
  sw a1,0(a0)
  ret

store_au32_rl_n:
  fence rw,w
  sw a1,0(a0)
  ret
Comment 1 Christoph Müllner 2021-04-26 12:47:03 UTC
A patchset to resolve this can be found here:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568684.html
Comment 2 Patrick O'Neill 2023-10-23 21:09:22 UTC
I believe this issue should be resolved now that the atomics fixes from a few months ago have landed/the atomics mappings are defined in the RISC-V PSABI doc.
https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/

Also backported for GCC 13.3
https://inbox.sourceware.org/gcc-patches/20230725180206.284777-1-patrick@rivosinc.com/

Thanks!
Comment 3 Christoph Müllner 2023-10-24 08:37:41 UTC
Yes, this got fixed.