Summary: | PPC vector fails to optimize shift (used bits) | ||
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Product: | gcc | Reporter: | Shawn Landden <shawn> |
Component: | target | Assignee: | Not yet assigned to anyone <unassigned> |
Status: | NEW --- | ||
Severity: | normal | CC: | segher |
Priority: | P3 | Keywords: | missed-optimization |
Version: | 8.0 | ||
Target Milestone: | --- | ||
Host: | Target: | powerpc | |
Build: | Known to work: | ||
Known to fail: | Last reconfirmed: | 2020-04-30 00:00:00 |
Description
Shawn Landden
2020-04-21 10:32:28 UTC
Confirmed. At combine time we start with insn_cost 4 for 25: r130:V1TI=%2:V1TI REG_DEAD %2:V1TI insn_cost 4 for 20: r129:V1TI=r130:V1TI REG_DEAD r130:V1TI insn_cost 4 for 21: r127:DI=r129:V1TI#0 insn_cost 4 for 22: r128:DI=r129:V1TI#8 REG_DEAD r129:V1TI insn_cost 4 for 24: r123:TI=0 insn_cost 4 for 7: r123:TI#8=r127:DI REG_DEAD r127:DI insn_cost 4 for 8: r123:TI#0=r128:DI REG_DEAD r128:DI insn_cost 4 for 9: r122:V1TI=r123:TI#0 REG_DEAD r123:TI insn_cost 4 for 14: %2:V1TI=r122:V1TI REG_DEAD r122:V1TI insn_cost 0 for 15: use %2:V1TI and those subregs at the lhs (insns 7 and 8) cannot combine with anything. 2-to-2 combine won't handle 20+21 (and then, 20+22) because 20 is a register move already. It would probably combine fine if that subreg lhs problem was fixed though. LLVM fixed this by lowering to vector shuffle: https://dev.gnupg.org/D501 |